1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
137 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
138 extern int mips_isa; /* architectural level */
139 extern int mips16; /* whether generating mips16 code */
140 extern int mips16_hard_float; /* mips16 without -msoft-float */
141 extern int mips_entry; /* generate entry/exit for mips16 */
142 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
143 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
144 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
145 extern const char *mips_entry_string; /* for -mentry */
146 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
147 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
148 extern int mips_split_addresses; /* perform high/lo_sum support */
149 extern int dslots_load_total; /* total # load related delay slots */
150 extern int dslots_load_filled; /* # filled load delay slots */
151 extern int dslots_jump_total; /* total # jump related delay slots */
152 extern int dslots_jump_filled; /* # filled jump delay slots */
153 extern int dslots_number_nops; /* # of nops needed by previous insn */
154 extern int num_refs[3]; /* # 1/2/3 word references */
155 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
156 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
157 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
158 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
159 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
160 extern int mips_string_length; /* length of strings for mips16 */
161 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
163 /* Functions to change what output section we are using. */
164 extern void rdata_section PARAMS ((void));
165 extern void sdata_section PARAMS ((void));
166 extern void sbss_section PARAMS ((void));
168 /* Stubs for half-pic support if not OSF/1 reference platform. */
171 #define HALF_PIC_P() 0
172 #define HALF_PIC_NUMBER_PTRS 0
173 #define HALF_PIC_NUMBER_REFS 0
174 #define HALF_PIC_ENCODE(DECL)
175 #define HALF_PIC_DECLARE(NAME)
176 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
177 #define HALF_PIC_ADDRESS_P(X) 0
178 #define HALF_PIC_PTR(X) X
179 #define HALF_PIC_FINISH(STREAM)
183 /* Run-time compilation parameters selecting different hardware subsets. */
185 /* Macros used in the machine description to test the flags. */
187 /* Bits for real switches */
188 #define MASK_INT64 0x00000001 /* ints are 64 bits */
189 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
190 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
191 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
192 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
193 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
194 #define MASK_STATS 0x00000040 /* print statistics to stderr */
195 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
196 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
197 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
198 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
199 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
200 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
201 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
202 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
203 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
204 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
205 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
206 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
207 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
208 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
209 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
210 #define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
211 #define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
212 #define MASK_UNINIT_CONST_IN_RODATA 0x10000000 /* Store uninitialized
215 /* Dummy switches used only in spec's*/
216 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
218 /* Debug switches, not documented */
219 #define MASK_DEBUG 0 /* Eliminate version # in .s file */
220 #define MASK_DEBUG_A 0x0 /* don't allow <label>($reg) addrs */
221 #define MASK_DEBUG_B 0x0 /* GO_IF_LEGITIMATE_ADDRESS debug */
222 #define MASK_DEBUG_C 0x0 /* don't expand seq, etc. */
223 #define MASK_DEBUG_D 0 /* don't do define_split's */
224 #define MASK_DEBUG_E 0 /* function_arg debug */
225 #define MASK_DEBUG_F 0
226 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
227 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
228 #define MASK_DEBUG_I 0 /* unused */
230 /* r4000 64 bit sizes */
231 #define TARGET_INT64 (target_flags & MASK_INT64)
232 #define TARGET_LONG64 (target_flags & MASK_LONG64)
233 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
234 #define TARGET_64BIT (target_flags & MASK_64BIT)
236 /* Mips vs. GNU linker */
237 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
239 /* generate mips 3900 insns */
240 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
242 /* Mips vs. GNU assembler */
243 #define TARGET_GAS (target_flags & MASK_GAS)
244 #define TARGET_UNIX_ASM (!TARGET_GAS)
245 #define TARGET_MIPS_AS TARGET_UNIX_ASM
248 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
249 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
250 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
251 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
252 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
253 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
254 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
255 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
256 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
257 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
259 /* Reg. Naming in .s ($21 vs. $a0) */
260 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
262 /* Optimize for Sdata/Sbss */
263 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
265 /* print program statistics */
266 #define TARGET_STATS (target_flags & MASK_STATS)
268 /* call memcpy instead of inline code */
269 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
271 /* .abicalls, etc from Pyramid V.4 */
272 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
274 /* OSF pic references to externs */
275 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
277 /* software floating point */
278 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
279 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
281 /* always call through a register */
282 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
284 /* generate embedded PIC code;
286 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
288 /* for embedded systems, optimize for
289 reduced RAM space instead of for
291 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
293 /* always store uninitialized const
294 variables in rodata, requires
295 TARGET_EMBEDDED_DATA. */
296 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
298 /* generate big endian code. */
299 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
301 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
302 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
304 #define TARGET_MAD (target_flags & MASK_MAD)
306 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
308 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
309 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
311 /* This is true if we must enable the assembly language file switching
314 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
316 /* We must disable the function end stabs when doing the file switching trick,
317 because the Lscope stabs end up in the wrong place, making it impossible
318 to debug the resulting code. */
319 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
321 /* Generate mips16 code */
322 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
324 /* Macro to define tables used to set the flags.
325 This is a list in braces of pairs in braces,
326 each pair being { "NAME", VALUE }
327 where VALUE is the bits to set or minus the bits to clear.
328 An empty string NAME is used to identify the default VALUE. */
330 #define TARGET_SWITCHES \
333 "No default crt0.o" }, \
334 {"int64", MASK_INT64 | MASK_LONG64, \
335 "Use 64-bit int type"}, \
336 {"long64", MASK_LONG64, \
337 "Use 64-bit long type"}, \
338 {"long32", -(MASK_LONG64 | MASK_INT64), \
339 "Use 32-bit long type"}, \
340 {"split-addresses", MASK_SPLIT_ADDR, \
341 "Optimize lui/addiu address loads"}, \
342 {"no-split-addresses", -MASK_SPLIT_ADDR, \
343 "Don't optimize lui/addiu address loads"}, \
344 {"mips-as", -MASK_GAS, \
348 {"rnames", MASK_NAME_REGS, \
349 "Use symbolic register names"}, \
350 {"no-rnames", -MASK_NAME_REGS, \
351 "Don't use symbolic register names"}, \
352 {"gpOPT", MASK_GPOPT, \
353 "Use GP relative sdata/sbss sections"}, \
354 {"gpopt", MASK_GPOPT, \
355 "Use GP relative sdata/sbss sections"}, \
356 {"no-gpOPT", -MASK_GPOPT, \
357 "Don't use GP relative sdata/sbss sections"}, \
358 {"no-gpopt", -MASK_GPOPT, \
359 "Don't use GP relative sdata/sbss sections"}, \
360 {"stats", MASK_STATS, \
361 "Output compiler statistics"}, \
362 {"no-stats", -MASK_STATS, \
363 "Don't output compiler statistics"}, \
364 {"memcpy", MASK_MEMCPY, \
365 "Don't optimize block moves"}, \
366 {"no-memcpy", -MASK_MEMCPY, \
367 "Optimize block moves"}, \
368 {"mips-tfile", MASK_MIPS_TFILE, \
369 "Use mips-tfile asm postpass"}, \
370 {"no-mips-tfile", -MASK_MIPS_TFILE, \
371 "Don't use mips-tfile asm postpass"}, \
372 {"soft-float", MASK_SOFT_FLOAT, \
373 "Use software floating point"}, \
374 {"hard-float", -MASK_SOFT_FLOAT, \
375 "Use hardware floating point"}, \
376 {"fp64", MASK_FLOAT64, \
377 "Use 64-bit FP registers"}, \
378 {"fp32", -MASK_FLOAT64, \
379 "Use 32-bit FP registers"}, \
380 {"gp64", MASK_64BIT, \
381 "Use 64-bit general registers"}, \
382 {"gp32", -MASK_64BIT, \
383 "Use 32-bit general registers"}, \
384 {"abicalls", MASK_ABICALLS, \
386 {"no-abicalls", -MASK_ABICALLS, \
387 "Don't use Irix PIC"}, \
388 {"half-pic", MASK_HALF_PIC, \
390 {"no-half-pic", -MASK_HALF_PIC, \
391 "Don't use OSF PIC"}, \
392 {"long-calls", MASK_LONG_CALLS, \
393 "Use indirect calls"}, \
394 {"no-long-calls", -MASK_LONG_CALLS, \
395 "Don't use indirect calls"}, \
396 {"embedded-pic", MASK_EMBEDDED_PIC, \
397 "Use embedded PIC"}, \
398 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
399 "Don't use embedded PIC"}, \
400 {"embedded-data", MASK_EMBEDDED_DATA, \
401 "Use ROM instead of RAM"}, \
402 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
403 "Don't use ROM instead of RAM"}, \
404 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
405 "Put uninitialized constants in ROM (needs -membedded-data)"}, \
406 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
407 "Don't put uninitialized constants in ROM"}, \
408 {"eb", MASK_BIG_ENDIAN, \
409 "Use big-endian byte order"}, \
410 {"el", -MASK_BIG_ENDIAN, \
411 "Use little-endian byte order"}, \
412 {"single-float", MASK_SINGLE_FLOAT, \
413 "Use single (32-bit) FP only"}, \
414 {"double-float", -MASK_SINGLE_FLOAT, \
415 "Don't use single (32-bit) FP only"}, \
417 "Use multiply accumulate"}, \
418 {"no-mad", -MASK_MAD, \
419 "Don't use multiply accumulate"}, \
420 {"fix4300", MASK_4300_MUL_FIX, \
421 "Work around early 4300 hardware bug"}, \
422 {"no-fix4300", -MASK_4300_MUL_FIX, \
423 "Don't work around early 4300 hardware bug"}, \
424 {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
425 "Optimize for 4650"}, \
426 {"3900", MASK_MIPS3900, \
427 "Optimize for 3900"}, \
428 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
429 "Trap on integer divide by zero"}, \
430 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
431 "Don't trap on integer divide by zero"}, \
432 {"check-range-division",MASK_CHECK_RANGE_DIV, \
433 "Trap on integer divide overflow"}, \
434 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
435 "Don't trap on integer divide overflow"}, \
436 {"debug", MASK_DEBUG, \
438 {"debuga", MASK_DEBUG_A, \
440 {"debugb", MASK_DEBUG_B, \
442 {"debugc", MASK_DEBUG_C, \
444 {"debugd", MASK_DEBUG_D, \
446 {"debuge", MASK_DEBUG_E, \
448 {"debugf", MASK_DEBUG_F, \
450 {"debugg", MASK_DEBUG_G, \
452 {"debugh", MASK_DEBUG_H, \
454 {"debugi", MASK_DEBUG_I, \
456 {"", (TARGET_DEFAULT \
457 | TARGET_CPU_DEFAULT \
458 | TARGET_ENDIAN_DEFAULT), \
462 /* Default target_flags if no switches are specified */
464 #ifndef TARGET_DEFAULT
465 #define TARGET_DEFAULT 0
468 #ifndef TARGET_CPU_DEFAULT
469 #define TARGET_CPU_DEFAULT 0
472 #ifndef TARGET_ENDIAN_DEFAULT
474 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
476 #define TARGET_ENDIAN_DEFAULT 0
480 #ifndef MIPS_ISA_DEFAULT
481 #define MIPS_ISA_DEFAULT 1
486 /* Make this compile time constant for libgcc2 */
488 #define TARGET_64BIT 1
490 #define TARGET_64BIT 0
492 #endif /* IN_LIBGCC2 */
494 #ifndef MULTILIB_ENDIAN_DEFAULT
495 #if TARGET_ENDIAN_DEFAULT == 0
496 #define MULTILIB_ENDIAN_DEFAULT "EL"
498 #define MULTILIB_ENDIAN_DEFAULT "EB"
502 #ifndef MULTILIB_ISA_DEFAULT
503 #if MIPS_ISA_DEFAULT == 1
504 #define MULTILIB_ISA_DEFAULT "mips1"
505 #elif MIPS_ISA_DEFAULT == 2
506 #define MULTILIB_ISA_DEFAULT "mips2"
507 #elif MIPS_ISA_DEFAULT == 3
508 #define MULTILIB_ISA_DEFAULT "mips3"
509 #elif MIPS_ISA_DEFAULT == 4
510 #define MULTILIB_ISA_DEFAULT "mips4"
512 #define MULTILIB_ISA_DEFAULT "mips1"
516 #ifndef MULTILIB_DEFAULTS
517 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
520 /* We must pass -EL to the linker by default for little endian embedded
521 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
522 linker will default to using big-endian output files. The OUTPUT_FORMAT
523 line must be in the linker script, otherwise -EB/-EL will not work. */
525 #ifndef LINKER_ENDIAN_SPEC
526 #if TARGET_ENDIAN_DEFAULT == 0
527 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
529 #define LINKER_ENDIAN_SPEC "%{!EL:%{!mel:-EB}}"
533 /* This macro is similar to `TARGET_SWITCHES' but defines names of
534 command options that have values. Its definition is an
535 initializer with a subgrouping for each command option.
537 Each subgrouping contains a string constant, that defines the
538 fixed part of the option name, and the address of a variable.
539 The variable, type `char *', is set to the variable part of the
540 given option if the fixed part matches. The actual option name
541 is made by appending `-m' to the specified name.
543 Here is an example which defines `-mshort-data-NUMBER'. If the
544 given option is `-mshort-data-512', the variable `m88k_short_data'
545 will be set to the string `"512"'.
547 extern char *m88k_short_data;
548 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
550 #define TARGET_OPTIONS \
552 SUBTARGET_TARGET_OPTIONS \
553 { "cpu=", &mips_cpu_string, \
554 "Specify CPU for scheduling purposes"}, \
555 { "ips", &mips_isa_string, \
556 "Specify MIPS ISA"}, \
557 { "entry", &mips_entry_string, \
558 "Use mips16 entry/exit psuedo ops"}, \
559 { "no-mips16", &mips_no_mips16_string, \
560 "Don't use MIPS16 instructions"}, \
561 { "explicit-type-size", &mips_explicit_type_size_string, \
565 /* This is meant to be redefined in the host dependent files. */
566 #define SUBTARGET_TARGET_OPTIONS
568 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
570 /* Generate three-operand multiply instructions for both SImode and DImode. */
571 #define GENERATE_MULT3 (TARGET_MIPS3900 \
574 /* Macros to decide whether certain features are available or not,
575 depending on the instruction set architecture level. */
577 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
578 #define HAVE_SQRT_P() (mips_isa != 1)
580 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
581 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
584 /* ISA has branch likely instructions (eg. mips2). */
585 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
587 /* ISA has the conditional move instructions introduced in mips4. */
588 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
591 /* ISA has just the integer condition move instructions (movn,movz) */
592 #define ISA_HAS_INT_CONDMOVE 0
596 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
597 branch on CC, and move (both FP and non-FP) on CC. */
598 #define ISA_HAS_8CC (mips_isa == 4 \
602 /* This is a catch all for the other new mips4 instructions: indexed load and
603 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
604 and the FP recip and recip sqrt instructions */
605 #define ISA_HAS_FP4 (mips_isa == 4 \
610 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
611 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
612 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
613 target_flags, and -mgp64 sets MASK_64BIT.
615 Setting MASK_64BIT in target_flags will cause gcc to assume that
616 registers are 64 bits wide. int, long and void * will be 32 bit;
617 this may be changed with -mint64 or -mlong64.
619 The gen* programs link code that refers to MASK_64BIT. They don't
620 actually use the information in target_flags; they just refer to
623 /* Switch Recognition by gcc.c. Add -G xx support */
625 #ifdef SWITCH_TAKES_ARG
626 #undef SWITCH_TAKES_ARG
629 #define SWITCH_TAKES_ARG(CHAR) \
630 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
632 /* Sometimes certain combinations of command options do not make sense
633 on a particular target machine. You can define a macro
634 `OVERRIDE_OPTIONS' to take account of this. This macro, if
635 defined, is executed once just after all the command options have
638 On the MIPS, it is used to handle -G. We also use it to set up all
639 of the tables referenced in the other macros. */
641 #define OVERRIDE_OPTIONS override_options ()
643 /* Zero or more C statements that may conditionally modify two
644 variables `fixed_regs' and `call_used_regs' (both of type `char
645 []') after they have been initialized from the two preceding
648 This is necessary in case the fixed or call-clobbered registers
649 depend on target flags.
651 You need not define this macro if it has no work to do.
653 If the usage of an entire class of registers depends on the target
654 flags, you may indicate this to GCC by using this macro to modify
655 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
656 the classes which should not be used by GCC. Also define the macro
657 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
658 letter for a class that shouldn't be used.
660 (However, if this class is not included in `GENERAL_REGS' and all
661 of the insn patterns whose constraints permit this class are
662 controlled by target switches, then GCC will automatically avoid
663 using these registers when the target switches are opposed to
666 #define CONDITIONAL_REGISTER_USAGE \
669 if (!TARGET_HARD_FLOAT) \
673 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
674 fixed_regs[regno] = call_used_regs[regno] = 1; \
675 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
676 fixed_regs[regno] = call_used_regs[regno] = 1; \
678 else if (! ISA_HAS_8CC) \
682 /* We only have a single condition code register. We \
683 implement this by hiding all the condition code registers, \
684 and generating RTL that refers directly to ST_REG_FIRST. */ \
685 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
686 fixed_regs[regno] = call_used_regs[regno] = 1; \
688 /* In mips16 mode, we permit the $t temporary registers to be used \
689 for reload. We prohibit the unused $s registers, since they \
690 are caller saved, and saving them via a mips16 register would \
691 probably waste more time than just reloading the value. */ \
694 fixed_regs[18] = call_used_regs[18] = 1; \
695 fixed_regs[19] = call_used_regs[19] = 1; \
696 fixed_regs[20] = call_used_regs[20] = 1; \
697 fixed_regs[21] = call_used_regs[21] = 1; \
698 fixed_regs[22] = call_used_regs[22] = 1; \
699 fixed_regs[23] = call_used_regs[23] = 1; \
700 fixed_regs[26] = call_used_regs[26] = 1; \
701 fixed_regs[27] = call_used_regs[27] = 1; \
702 fixed_regs[30] = call_used_regs[30] = 1; \
704 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
708 /* This is meant to be redefined in the host dependent files. */
709 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
711 /* Show we can debug even without a frame pointer. */
712 #define CAN_DEBUG_WITHOUT_FP
714 /* Complain about missing specs and predefines that should be defined in each
715 of the target tm files to override the defaults. This is mostly a place-
716 holder until I can get each of the files updated [mm]. */
718 #if defined(OSF_OS) \
719 || defined(DECSTATION) \
720 || defined(SGI_TARGET) \
721 || defined(MIPS_NEWS) \
722 || defined(MIPS_SYSV) \
723 || defined(MIPS_SVR4) \
724 || defined(MIPS_BSD43)
726 #ifndef CPP_PREDEFINES
727 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
731 #error "Define LIB_SPEC in the appropriate tm.h file"
734 #ifndef STARTFILE_SPEC
735 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
739 #error "Define MACHINE_TYPE in the appropriate tm.h file"
743 /* Tell collect what flags to pass to nm. */
745 #define NM_FLAGS "-Bn"
749 /* Names to predefine in the preprocessor for this target machine. */
751 #ifndef CPP_PREDEFINES
752 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
753 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
754 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
757 /* Assembler specs. */
759 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
762 #define MIPS_AS_ASM_SPEC "\
763 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
764 %{pipe: %e-pipe is not supported.} \
765 %{K} %(subtarget_mips_as_asm_spec)"
767 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
768 rather than gas. It may be overridden by subtargets. */
770 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
771 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
774 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
777 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
779 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
780 GAS_ASM_SPEC as the default, depending upon the value of
783 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
786 #define TARGET_ASM_SPEC "\
787 %{mmips-as: %(mips_as_asm_spec)} \
788 %{!mmips-as: %(gas_asm_spec)}"
792 #define TARGET_ASM_SPEC "\
793 %{!mgas: %(mips_as_asm_spec)} \
794 %{mgas: %(gas_asm_spec)}"
798 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
799 to the assembler. It may be overridden by subtargets. */
800 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
801 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
803 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
806 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
807 the assembler. It may be overridden by subtargets. */
808 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
809 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
810 %{g} %{g0} %{g1} %{g2} %{g3} \
811 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
812 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
813 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
814 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
817 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
818 overridden by subtargets. */
820 #ifndef SUBTARGET_ASM_SPEC
821 #define SUBTARGET_ASM_SPEC ""
824 /* ASM_SPEC is the set of arguments to pass to the assembler. */
827 %{!membedded-pic:%{G*}} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
828 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
829 %(subtarget_asm_optimizing_spec) \
830 %(subtarget_asm_debugging_spec) \
833 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
835 %(subtarget_asm_spec)"
837 /* Specify to run a post-processor, mips-tfile after the assembler
838 has run to stuff the mips debug information into the object file.
839 This is needed because the $#!%^ MIPS assembler provides no way
840 of specifying such information in the assembly file. If we are
841 cross compiling, disable mips-tfile unless the user specifies
844 #ifndef ASM_FINAL_SPEC
845 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
847 #define ASM_FINAL_SPEC "\
848 %{mmips-as: %{!mno-mips-tfile: \
849 \n mips-tfile %{v*: -v} \
851 %{!K: %{save-temps: -I %b.o~}} \
852 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
853 %{.s:%i} %{!.s:%g.s}}}"
857 #define ASM_FINAL_SPEC "\
858 %{!mgas: %{!mno-mips-tfile: \
859 \n mips-tfile %{v*: -v} \
861 %{!K: %{save-temps: -I %b.o~}} \
862 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
863 %{.s:%i} %{!.s:%g.s}}}"
866 #endif /* ASM_FINAL_SPEC */
868 /* Redefinition of libraries used. Mips doesn't support normal
869 UNIX style profiling via calling _mcount. It does offer
870 profiling that samples the PC, so do what we can... */
873 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
876 /* Extra switches sometimes passed to the linker. */
877 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
878 will interpret it as a -b option. */
882 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
883 %{bestGnum} %{shared} %{non_shared} \
884 %(linker_endian_spec)"
885 #endif /* LINK_SPEC defined */
887 /* Specs for the compiler proper */
889 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
890 overridden by subtargets. */
891 #ifndef SUBTARGET_CC1_SPEC
892 #define SUBTARGET_CC1_SPEC ""
895 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
899 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
900 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
901 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
902 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
903 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
904 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
905 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
906 %{m4650:-mcpu=r4650} \
907 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
908 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
909 %{pic-none: -mno-half-pic} \
910 %{pic-lib: -mhalf-pic} \
911 %{pic-extern: -mhalf-pic} \
912 %{pic-calls: -mhalf-pic} \
914 %(subtarget_cc1_spec) "
917 /* Preprocessor specs. */
919 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
920 be overridden by subtargets. */
922 #ifndef SUBTARGET_CPP_SIZE_SPEC
923 #define SUBTARGET_CPP_SIZE_SPEC "\
924 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
925 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
928 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
929 overridden by subtargets. */
930 #ifndef SUBTARGET_CPP_SPEC
931 #define SUBTARGET_CPP_SPEC ""
934 /* If we're using 64bit longs, then we have to define __LONG_MAX__
935 correctly. Similarly for 64bit ints and __INT_MAX__. */
936 #ifndef LONG_MAX_SPEC
937 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
938 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
940 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
944 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
948 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
949 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
950 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
951 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
952 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
953 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
954 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
955 %(subtarget_cpp_size_spec) \
956 %{mips3:-U__mips -D__mips=3 -D__mips64} \
957 %{mips4:-U__mips -D__mips=4 -D__mips64} \
958 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
959 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
960 %{m4650:%{!msoft-float:-D__mips_single_float}} \
961 %{msoft-float:-D__mips_soft_float} \
962 %{mabi=eabi:-D__mips_eabi} \
963 %{mips16:%{!mno-mips16:-D__mips16}} \
964 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
965 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
967 %(subtarget_cpp_spec) "
970 /* This macro defines names of additional specifications to put in the specs
971 that can be used in various specifications like CC1_SPEC. Its definition
972 is an initializer with a subgrouping for each command option.
974 Each subgrouping contains a string constant, that defines the
975 specification name, and a string constant that used by the GNU CC driver
978 Do not define this macro if it does not need to do anything. */
980 #define EXTRA_SPECS \
981 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
982 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
983 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
984 { "long_max_spec", LONG_MAX_SPEC }, \
985 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
986 { "gas_asm_spec", GAS_ASM_SPEC }, \
987 { "target_asm_spec", TARGET_ASM_SPEC }, \
988 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
989 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
990 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
991 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
992 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
993 SUBTARGET_EXTRA_SPECS
995 #ifndef SUBTARGET_EXTRA_SPECS
996 #define SUBTARGET_EXTRA_SPECS
999 /* If defined, this macro is an additional prefix to try after
1000 `STANDARD_EXEC_PREFIX'. */
1002 #ifndef MD_EXEC_PREFIX
1003 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1006 #ifndef MD_STARTFILE_PREFIX
1007 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1011 /* Print subsidiary information on the compiler version in use. */
1013 #define MIPS_VERSION "[AL 1.1, MM 40]"
1015 #ifndef MACHINE_TYPE
1016 #define MACHINE_TYPE "BSD Mips"
1019 #ifndef TARGET_VERSION_INTERNAL
1020 #define TARGET_VERSION_INTERNAL(STREAM) \
1021 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1024 #ifndef TARGET_VERSION
1025 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1029 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1030 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1031 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1033 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1034 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1037 /* By default, turn on GDB extensions. */
1038 #define DEFAULT_GDB_EXTENSIONS 1
1040 /* If we are passing smuggling stabs through the MIPS ECOFF object
1041 format, put a comment in front of the .stab<x> operation so
1042 that the MIPS assembler does not choke. The mips-tfile program
1043 will correctly put the stab into the object file. */
1045 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1046 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1047 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1049 /* Local compiler-generated symbols must have a prefix that the assembler
1050 understands. By default, this is $, although some targets (e.g.,
1051 NetBSD-ELF) need to override this. */
1053 #ifndef LOCAL_LABEL_PREFIX
1054 #define LOCAL_LABEL_PREFIX "$"
1057 /* By default on the mips, external symbols do not have an underscore
1058 prepended, but some targets (e.g., NetBSD) require this. */
1060 #ifndef USER_LABEL_PREFIX
1061 #define USER_LABEL_PREFIX ""
1064 /* Forward references to tags are allowed. */
1065 #define SDB_ALLOW_FORWARD_REFERENCES
1067 /* Unknown tags are also allowed. */
1068 #define SDB_ALLOW_UNKNOWN_REFERENCES
1070 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1071 since the length can run past this up to a continuation point. */
1072 #define DBX_CONTIN_LENGTH 1500
1074 /* How to renumber registers for dbx and gdb. */
1075 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1077 /* The mapping from gcc register number to DWARF 2 CFA column number.
1078 This mapping does not allow for tracking register 0, since SGI's broken
1079 dwarf reader thinks column 0 is used for the frame address, but since
1080 register 0 is fixed this is not a problem. */
1081 #define DWARF_FRAME_REGNUM(REG) \
1082 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1084 /* The DWARF 2 CFA column which tracks the return address. */
1085 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1087 /* Before the prologue, RA lives in r31. */
1088 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1090 /* Overrides for the COFF debug format. */
1091 #define PUT_SDB_SCL(a) \
1093 extern FILE *asm_out_text_file; \
1094 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1097 #define PUT_SDB_INT_VAL(a) \
1099 extern FILE *asm_out_text_file; \
1100 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1103 #define PUT_SDB_VAL(a) \
1105 extern FILE *asm_out_text_file; \
1106 fputs ("\t.val\t", asm_out_text_file); \
1107 output_addr_const (asm_out_text_file, (a)); \
1108 fputc (';', asm_out_text_file); \
1111 #define PUT_SDB_DEF(a) \
1113 extern FILE *asm_out_text_file; \
1114 fprintf (asm_out_text_file, "\t%s.def\t", \
1115 (TARGET_GAS) ? "" : "#"); \
1116 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1117 fputc (';', asm_out_text_file); \
1120 #define PUT_SDB_PLAIN_DEF(a) \
1122 extern FILE *asm_out_text_file; \
1123 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1124 (TARGET_GAS) ? "" : "#", (a)); \
1127 #define PUT_SDB_ENDEF \
1129 extern FILE *asm_out_text_file; \
1130 fprintf (asm_out_text_file, "\t.endef\n"); \
1133 #define PUT_SDB_TYPE(a) \
1135 extern FILE *asm_out_text_file; \
1136 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1139 #define PUT_SDB_SIZE(a) \
1141 extern FILE *asm_out_text_file; \
1142 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1145 #define PUT_SDB_DIM(a) \
1147 extern FILE *asm_out_text_file; \
1148 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1151 #ifndef PUT_SDB_START_DIM
1152 #define PUT_SDB_START_DIM \
1154 extern FILE *asm_out_text_file; \
1155 fprintf (asm_out_text_file, "\t.dim\t"); \
1159 #ifndef PUT_SDB_NEXT_DIM
1160 #define PUT_SDB_NEXT_DIM(a) \
1162 extern FILE *asm_out_text_file; \
1163 fprintf (asm_out_text_file, "%d,", a); \
1167 #ifndef PUT_SDB_LAST_DIM
1168 #define PUT_SDB_LAST_DIM(a) \
1170 extern FILE *asm_out_text_file; \
1171 fprintf (asm_out_text_file, "%d;", a); \
1175 #define PUT_SDB_TAG(a) \
1177 extern FILE *asm_out_text_file; \
1178 fprintf (asm_out_text_file, "\t.tag\t"); \
1179 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1180 fputc (';', asm_out_text_file); \
1183 /* For block start and end, we create labels, so that
1184 later we can figure out where the correct offset is.
1185 The normal .ent/.end serve well enough for functions,
1186 so those are just commented out. */
1188 #define PUT_SDB_BLOCK_START(LINE) \
1190 extern FILE *asm_out_text_file; \
1191 fprintf (asm_out_text_file, \
1192 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1193 LOCAL_LABEL_PREFIX, \
1195 (TARGET_GAS) ? "" : "#", \
1196 LOCAL_LABEL_PREFIX, \
1199 sdb_label_count++; \
1202 #define PUT_SDB_BLOCK_END(LINE) \
1204 extern FILE *asm_out_text_file; \
1205 fprintf (asm_out_text_file, \
1206 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1207 LOCAL_LABEL_PREFIX, \
1209 (TARGET_GAS) ? "" : "#", \
1210 LOCAL_LABEL_PREFIX, \
1213 sdb_label_count++; \
1216 #define PUT_SDB_FUNCTION_START(LINE)
1218 #define PUT_SDB_FUNCTION_END(LINE) \
1220 extern FILE *asm_out_text_file; \
1221 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1224 #define PUT_SDB_EPILOGUE_END(NAME)
1226 #define PUT_SDB_SRC_FILE(FILENAME) \
1228 extern FILE *asm_out_text_file; \
1229 output_file_directive (asm_out_text_file, (FILENAME)); \
1232 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1233 sprintf ((BUFFER), ".%dfake", (NUMBER));
1235 /* Correct the offset of automatic variables and arguments. Note that
1236 the MIPS debug format wants all automatic variables and arguments
1237 to be in terms of the virtual frame pointer (stack pointer before
1238 any adjustment in the function), while the MIPS 3.0 linker wants
1239 the frame pointer to be the stack pointer after the initial
1242 #define DEBUGGER_AUTO_OFFSET(X) \
1243 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1244 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1245 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1247 /* Tell collect that the object format is ECOFF */
1248 #ifndef OBJECT_FORMAT_ROSE
1249 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1250 #define EXTENDED_COFF /* ECOFF, not normal coff */
1253 #if 0 /* These definitions normally have no effect because
1254 MIPS systems define USE_COLLECT2, so
1255 assemble_constructor does nothing anyway. */
1257 /* Don't use the default definitions, because we don't have gld.
1258 Also, we don't want stabs when generating ECOFF output.
1259 Instead we depend on collect to handle these. */
1261 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1262 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1266 /* Target machine storage layout */
1268 /* Define in order to support both big and little endian float formats
1269 in the same gcc binary. */
1270 #define REAL_ARITHMETIC
1272 /* Define this if most significant bit is lowest numbered
1273 in instructions that operate on numbered bit-fields.
1275 #define BITS_BIG_ENDIAN 0
1277 /* Define this if most significant byte of a word is the lowest numbered. */
1278 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1280 /* Define this if most significant word of a multiword number is the lowest. */
1281 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1283 /* Define this to set the endianness to use in libgcc2.c, which can
1284 not depend on target_flags. */
1285 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1286 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1288 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1291 /* Number of bits in an addressable storage unit */
1292 #define BITS_PER_UNIT 8
1294 /* Width in bits of a "word", which is the contents of a machine register.
1295 Note that this is not necessarily the width of data type `int';
1296 if using 16-bit ints on a 68000, this would still be 32.
1297 But on a machine with 16-bit registers, this would be 16. */
1298 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1299 #define MAX_BITS_PER_WORD 64
1301 /* Width of a word, in units (bytes). */
1302 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1303 #define MIN_UNITS_PER_WORD 4
1305 /* For MIPS, width of a floating point register. */
1306 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1308 /* A C expression for the size in bits of the type `int' on the
1309 target machine. If you don't define this, the default is one
1311 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1312 #define MAX_INT_TYPE_SIZE 64
1314 /* Tell the preprocessor the maximum size of wchar_t. */
1315 #ifndef MAX_WCHAR_TYPE_SIZE
1316 #ifndef WCHAR_TYPE_SIZE
1317 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1321 /* A C expression for the size in bits of the type `short' on the
1322 target machine. If you don't define this, the default is half a
1323 word. (If this would be less than one storage unit, it is
1324 rounded up to one unit.) */
1325 #define SHORT_TYPE_SIZE 16
1327 /* A C expression for the size in bits of the type `long' on the
1328 target machine. If you don't define this, the default is one
1330 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1331 #define MAX_LONG_TYPE_SIZE 64
1333 /* A C expression for the size in bits of the type `long long' on the
1334 target machine. If you don't define this, the default is two
1336 #define LONG_LONG_TYPE_SIZE 64
1338 /* A C expression for the size in bits of the type `char' on the
1339 target machine. If you don't define this, the default is one
1340 quarter of a word. (If this would be less than one storage unit,
1341 it is rounded up to one unit.) */
1342 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1344 /* A C expression for the size in bits of the type `float' on the
1345 target machine. If you don't define this, the default is one
1347 #define FLOAT_TYPE_SIZE 32
1349 /* A C expression for the size in bits of the type `double' on the
1350 target machine. If you don't define this, the default is two
1352 #define DOUBLE_TYPE_SIZE 64
1354 /* A C expression for the size in bits of the type `long double' on
1355 the target machine. If you don't define this, the default is two
1357 #define LONG_DOUBLE_TYPE_SIZE 64
1359 /* Width in bits of a pointer.
1360 See also the macro `Pmode' defined below. */
1361 #ifndef POINTER_SIZE
1362 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1365 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1366 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1368 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1369 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1371 /* Allocation boundary (in *bits*) for the code of a function. */
1372 #define FUNCTION_BOUNDARY 32
1374 /* Alignment of field after `int : 0' in a structure. */
1375 #define EMPTY_FIELD_BOUNDARY 32
1377 /* Every structure's size must be a multiple of this. */
1378 /* 8 is observed right on a DECstation and on riscos 4.02. */
1379 #define STRUCTURE_SIZE_BOUNDARY 8
1381 /* There is no point aligning anything to a rounder boundary than this. */
1382 #define BIGGEST_ALIGNMENT 64
1384 /* Set this nonzero if move instructions will actually fail to work
1385 when given unaligned data. */
1386 #define STRICT_ALIGNMENT 1
1388 /* Define this if you wish to imitate the way many other C compilers
1389 handle alignment of bitfields and the structures that contain
1392 The behavior is that the type written for a bitfield (`int',
1393 `short', or other integer type) imposes an alignment for the
1394 entire structure, as if the structure really did contain an
1395 ordinary field of that type. In addition, the bitfield is placed
1396 within the structure so that it would fit within such a field,
1397 not crossing a boundary for it.
1399 Thus, on most machines, a bitfield whose type is written as `int'
1400 would not cross a four-byte boundary, and would force four-byte
1401 alignment for the whole structure. (The alignment used may not
1402 be four bytes; it is controlled by the other alignment
1405 If the macro is defined, its definition should be a C expression;
1406 a nonzero value for the expression enables this behavior. */
1408 #define PCC_BITFIELD_TYPE_MATTERS 1
1410 /* If defined, a C expression to compute the alignment given to a
1411 constant that is being placed in memory. CONSTANT is the constant
1412 and ALIGN is the alignment that the object would ordinarily have.
1413 The value of this macro is used instead of that alignment to align
1416 If this macro is not defined, then ALIGN is used.
1418 The typical use of this macro is to increase alignment for string
1419 constants to be word aligned so that `strcpy' calls that copy
1420 constants can be done inline. */
1422 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1423 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1424 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1426 /* If defined, a C expression to compute the alignment for a static
1427 variable. TYPE is the data type, and ALIGN is the alignment that
1428 the object would ordinarily have. The value of this macro is used
1429 instead of that alignment to align the object.
1431 If this macro is not defined, then ALIGN is used.
1433 One use of this macro is to increase alignment of medium-size
1434 data to make it all fit in fewer cache lines. Another is to
1435 cause character arrays to be word-aligned so that `strcpy' calls
1436 that copy constants to character arrays can be done inline. */
1438 #undef DATA_ALIGNMENT
1439 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1440 ((((ALIGN) < BITS_PER_WORD) \
1441 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1442 || TREE_CODE (TYPE) == UNION_TYPE \
1443 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1446 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1448 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1450 /* Define this macro if an argument declared as `char' or `short' in a
1451 prototype should actually be passed as an `int'. In addition to
1452 avoiding errors in certain cases of mismatch, it also makes for
1453 better code on certain machines. */
1455 #define PROMOTE_PROTOTYPES 1
1457 /* Define if operations between registers always perform the operation
1458 on the full register even if a narrower mode is specified. */
1459 #define WORD_REGISTER_OPERATIONS
1461 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1462 will either zero-extend or sign-extend. The value of this macro should
1463 be the code that says which one of the two operations is implicitly
1466 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1467 moves. All other referces are zero extended. */
1468 #define LOAD_EXTEND_OP(MODE) \
1469 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1470 ? SIGN_EXTEND : ZERO_EXTEND)
1472 /* Define this macro if it is advisable to hold scalars in registers
1473 in a wider mode than that declared by the program. In such cases,
1474 the value is constrained to be within the bounds of the declared
1475 type, but kept valid in the wider mode. The signedness of the
1476 extension may differ from that of the type.
1478 We promote any value smaller than SImode up to SImode. We don't
1479 want to promote to DImode when in 64 bit mode, because that would
1480 prevent us from using the faster SImode multiply and divide
1483 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1484 if (GET_MODE_CLASS (MODE) == MODE_INT \
1485 && GET_MODE_SIZE (MODE) < 4) \
1488 /* Define this if function arguments should also be promoted using the above
1491 #define PROMOTE_FUNCTION_ARGS
1493 /* Likewise, if the function return value is promoted. */
1495 #define PROMOTE_FUNCTION_RETURN
1497 /* Standard register usage. */
1499 /* Number of actual hardware registers.
1500 The hardware registers are assigned numbers for the compiler
1501 from 0 to just below FIRST_PSEUDO_REGISTER.
1502 All registers that the compiler knows about must be given numbers,
1503 even those that are not normally considered general registers.
1505 On the Mips, we have 32 integer registers, 32 floating point
1506 registers, 8 condition code registers, and the special registers
1507 hi, lo, hilo, and rap. The 8 condition code registers are only
1508 used if mips_isa >= 4. The hilo register is only used in 64 bit
1509 mode. It represents a 64 bit value stored as two 32 bit values in
1510 the hi and lo registers; this is the result of the mult
1511 instruction. rap is a pointer to the stack where the return
1512 address reg ($31) was stored. This is needed for C++ exception
1515 #define FIRST_PSEUDO_REGISTER 76
1517 /* 1 for registers that have pervasive standard uses
1518 and are not available for the register allocator.
1520 On the MIPS, see conventions, page D-2 */
1522 #define FIXED_REGISTERS \
1524 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1532 /* 1 for registers not available across function calls.
1533 These must include the FIXED_REGISTERS and also any
1534 registers that can be used without being saved.
1535 The latter must include the registers where values are returned
1536 and the register where structure-value addresses are passed.
1537 Aside from that, you can include as many other registers as you like. */
1539 #define CALL_USED_REGISTERS \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1549 /* Internal macros to classify a register number as to whether it's a
1550 general purpose register, a floating point register, a
1551 multiply/divide register, or a status register. */
1553 #define GP_REG_FIRST 0
1554 #define GP_REG_LAST 31
1555 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1556 #define GP_DBX_FIRST 0
1558 #define FP_REG_FIRST 32
1559 #define FP_REG_LAST 63
1560 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1561 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1563 #define MD_REG_FIRST 64
1564 #define MD_REG_LAST 66
1565 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1567 #define ST_REG_FIRST 67
1568 #define ST_REG_LAST 74
1569 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1571 #define RAP_REG_NUM 75
1573 #define AT_REGNUM (GP_REG_FIRST + 1)
1574 #define HI_REGNUM (MD_REG_FIRST + 0)
1575 #define LO_REGNUM (MD_REG_FIRST + 1)
1576 #define HILO_REGNUM (MD_REG_FIRST + 2)
1578 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1579 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1580 should be used instead. */
1581 #define FPSW_REGNUM ST_REG_FIRST
1583 #define GP_REG_P(REGNO) \
1584 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1585 #define M16_REG_P(REGNO) \
1586 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1587 #define FP_REG_P(REGNO) \
1588 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1589 #define MD_REG_P(REGNO) \
1590 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1591 #define ST_REG_P(REGNO) \
1592 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1594 /* Return number of consecutive hard regs needed starting at reg REGNO
1595 to hold something of mode MODE.
1596 This is ordinarily the length in words of a value of mode MODE
1597 but can be less for certain modes in special long registers.
1599 On the MIPS, all general registers are one word long. Except on
1600 the R4000 with the FR bit set, the floating point uses register
1601 pairs, with the second register not being allocable. */
1603 #define HARD_REGNO_NREGS(REGNO, MODE) \
1604 (! FP_REG_P (REGNO) \
1605 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1606 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1608 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1609 MODE. In 32 bit mode, require that DImode and DFmode be in even
1610 registers. For DImode, this makes some of the insns easier to
1611 write, since you don't have to worry about a DImode value in
1612 registers 3 & 4, producing a result in 4 & 5.
1614 To make the code simpler HARD_REGNO_MODE_OK now just references an
1615 array built in override_options. Because machmodes.h is not yet
1616 included before this file is processed, the MODE bound can't be
1619 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1621 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1622 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1624 /* Value is 1 if it is a good idea to tie two pseudo registers
1625 when one has mode MODE1 and one has mode MODE2.
1626 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1627 for any hard reg, then this must be 0 for correct output. */
1628 #define MODES_TIEABLE_P(MODE1, MODE2) \
1629 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1630 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1631 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1632 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1634 /* MIPS pc is not overloaded on a register. */
1635 /* #define PC_REGNUM xx */
1637 /* Register to use for pushing function arguments. */
1638 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1640 /* Offset from the stack pointer to the first available location. Use
1641 the default value zero. */
1642 /* #define STACK_POINTER_OFFSET 0 */
1644 /* Base register for access to local variables of the function. We
1645 pretend that the frame pointer is $1, and then eliminate it to
1646 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1647 a fixed register, and will not be used for anything else. */
1648 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1650 /* Temporary scratch register for use by the assembler. */
1651 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1653 /* $30 is not available on the mips16, so we use $17 as the frame
1655 #define HARD_FRAME_POINTER_REGNUM \
1656 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1658 /* Value should be nonzero if functions must have frame pointers.
1659 Zero means the frame pointer need not be set up (and parms
1660 may be accessed via the stack pointer) in functions that seem suitable.
1661 This is computed in `reload', in reload1.c. */
1662 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1664 /* Base register for access to arguments of the function. */
1665 #define ARG_POINTER_REGNUM GP_REG_FIRST
1667 /* Fake register that holds the address on the stack of the
1668 current function's return address. */
1669 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1671 /* Register in which static-chain is passed to a function. */
1672 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1674 /* If the structure value address is passed in a register, then
1675 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1676 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1678 /* If the structure value address is not passed in a register, define
1679 `STRUCT_VALUE' as an expression returning an RTX for the place
1680 where the address is passed. If it returns 0, the address is
1681 passed as an "invisible" first argument. */
1682 #define STRUCT_VALUE 0
1684 /* Mips registers used in prologue/epilogue code when the stack frame
1685 is larger than 32K bytes. These registers must come from the
1686 scratch register set, and not used for passing and returning
1687 arguments and any other information used in the calling sequence
1688 (such as pic). Must start at 12, since t0/t3 are parameter passing
1689 registers in the 64 bit ABI. */
1691 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1692 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1694 /* Define this macro if it is as good or better to call a constant
1695 function address than to call an address kept in a register. */
1696 #define NO_FUNCTION_CSE 1
1698 /* Define this macro if it is as good or better for a function to
1699 call itself with an explicit address than to call an address
1700 kept in a register. */
1701 #define NO_RECURSIVE_FUNCTION_CSE 1
1703 /* The register number of the register used to address a table of
1704 static data addresses in memory. In some cases this register is
1705 defined by a processor's "application binary interface" (ABI).
1706 When this macro is defined, RTL is generated for this register
1707 once, as with the stack pointer and frame pointer registers. If
1708 this macro is not defined, it is up to the machine-dependent
1709 files to allocate such a register (if necessary). */
1710 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1712 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1714 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1715 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1716 isn't always called for static inline functions. */
1717 #define INIT_EXPANDERS \
1719 embedded_pic_fnaddr_rtx = NULL; \
1720 mips16_gp_pseudo_rtx = NULL; \
1723 /* Define the classes of registers for register constraints in the
1724 machine description. Also define ranges of constants.
1726 One of the classes must always be named ALL_REGS and include all hard regs.
1727 If there is more than one class, another class must be named NO_REGS
1728 and contain no registers.
1730 The name GENERAL_REGS must be the name of a class (or an alias for
1731 another name such as ALL_REGS). This is the class of registers
1732 that is allowed by "g" or "r" in a register constraint.
1733 Also, registers outside this class are allocated only when
1734 instructions express preferences for them.
1736 The classes must be numbered in nondecreasing order; that is,
1737 a larger-numbered class must never be contained completely
1738 in a smaller-numbered class.
1740 For any two classes, it is very desirable that there be another
1741 class that represents their union. */
1745 NO_REGS, /* no registers in set */
1746 M16_NA_REGS, /* mips16 regs not used to pass args */
1747 M16_REGS, /* mips16 directly accessible registers */
1748 T_REG, /* mips16 T register ($24) */
1749 M16_T_REGS, /* mips16 registers plus T register */
1750 GR_REGS, /* integer registers */
1751 FP_REGS, /* floating point registers */
1752 HI_REG, /* hi register */
1753 LO_REG, /* lo register */
1754 HILO_REG, /* hilo register pair for 64 bit mode mult */
1755 MD_REGS, /* multiply/divide registers (hi/lo) */
1756 HI_AND_GR_REGS, /* union classes */
1759 ST_REGS, /* status registers (fp status) */
1760 ALL_REGS, /* all registers */
1761 LIM_REG_CLASSES /* max value + 1 */
1764 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1766 #define GENERAL_REGS GR_REGS
1768 /* An initializer containing the names of the register classes as C
1769 string constants. These names are used in writing some of the
1772 #define REG_CLASS_NAMES \
1787 "HILO_AND_GR_REGS", \
1792 /* An initializer containing the contents of the register classes,
1793 as integers which are bit masks. The Nth integer specifies the
1794 contents of class N. The way the integer MASK is interpreted is
1795 that register R is in the class if `MASK & (1 << R)' is 1.
1797 When the machine has more than 32 registers, an integer does not
1798 suffice. Then the integers are replaced by sub-initializers,
1799 braced groupings containing several integers. Each
1800 sub-initializer must be suitable as an initializer for the type
1801 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1803 #define REG_CLASS_CONTENTS \
1805 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1806 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1807 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1808 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1809 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1810 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1811 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1812 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1813 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1814 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1815 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1816 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1817 { 0xffffffff, 0x00000000, 0x00000002 }, \
1818 { 0xffffffff, 0x00000000, 0x00000004 }, \
1819 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1820 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1824 /* A C expression whose value is a register class containing hard
1825 register REGNO. In general there is more that one such class;
1826 choose a class which is "minimal", meaning that no smaller class
1827 also contains the register. */
1829 extern enum reg_class mips_regno_to_class[];
1831 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1833 /* A macro whose definition is the name of the class to which a
1834 valid base register must belong. A base register is one used in
1835 an address which is the register value plus a displacement. */
1837 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1839 /* A macro whose definition is the name of the class to which a
1840 valid index register must belong. An index register is one used
1841 in an address where its value is either multiplied by a scale
1842 factor or added to another register (as well as added to a
1845 #define INDEX_REG_CLASS NO_REGS
1847 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1848 registers explicitly used in the rtl to be used as spill registers
1849 but prevents the compiler from extending the lifetime of these
1852 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1854 /* This macro is used later on in the file. */
1855 #define GR_REG_CLASS_P(CLASS) \
1856 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1857 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1859 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1860 is the default value (allocate the registers in numeric order). We
1861 define it just so that we can override it for the mips16 target in
1862 ORDER_REGS_FOR_LOCAL_ALLOC. */
1864 #define REG_ALLOC_ORDER \
1865 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1866 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1867 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1868 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1869 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1872 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1873 to be rearranged based on a particular function. On the mips16, we
1874 want to allocate $24 (T_REG) before other registers for
1875 instructions for which it is possible. */
1877 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1879 /* REGISTER AND CONSTANT CLASSES */
1881 /* Get reg_class from a letter such as appears in the machine
1884 DEFINED REGISTER CLASSES:
1886 'd' General (aka integer) registers
1887 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1888 'y' General registers (in both mips16 and non mips16 mode)
1889 'e' mips16 non argument registers (M16_NA_REGS)
1890 't' mips16 temporary register ($24)
1891 'f' Floating point registers
1894 'x' Multiply/divide registers
1896 'z' FP Status register
1897 'b' All registers */
1899 extern enum reg_class mips_char_to_class[];
1901 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1903 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1904 string can be used to stand for particular ranges of immediate
1905 operands. This macro defines what the ranges are. C is the
1906 letter, and VALUE is a constant value. Return 1 if VALUE is
1907 in the range specified by C. */
1911 `I' is used for the range of constants an arithmetic insn can
1912 actually contain (16 bits signed integers).
1914 `J' is used for the range which is just zero (ie, $r0).
1916 `K' is used for the range of constants a logical insn can actually
1917 contain (16 bit zero-extended integers).
1919 `L' is used for the range of constants that be loaded with lui
1920 (ie, the bottom 16 bits are zero).
1922 `M' is used for the range of constants that take two words to load
1923 (ie, not matched by `I', `K', and `L').
1925 `N' is used for negative 16 bit constants other than -65536.
1927 `O' is a 15 bit signed integer.
1929 `P' is used for positive 16 bit constants. */
1931 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1932 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1934 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1935 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1936 : (C) == 'J' ? ((VALUE) == 0) \
1937 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1938 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1939 && (((VALUE) & ~2147483647) == 0 \
1940 || ((VALUE) & ~2147483647) == ~2147483647)) \
1941 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1942 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1943 && (((VALUE) & 0x0000ffff) != 0 \
1944 || (((VALUE) & ~2147483647) != 0 \
1945 && ((VALUE) & ~2147483647) != ~2147483647))) \
1946 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1947 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1948 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1951 /* Similar, but for floating constants, and defining letters G and H.
1952 Here VALUE is the CONST_DOUBLE rtx itself. */
1956 'G' : Floating point 0 */
1958 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1960 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1962 /* Letters in the range `Q' through `U' may be defined in a
1963 machine-dependent fashion to stand for arbitrary operand types.
1964 The machine description macro `EXTRA_CONSTRAINT' is passed the
1965 operand as its first argument and the constraint letter as its
1968 `Q' is for mips16 GP relative constants
1969 `R' is for memory references which take 1 word for the instruction.
1970 `S' is for references to extern items which are PIC for OSF/rose.
1971 `T' is for memory addresses that can be used to load two words. */
1973 #define EXTRA_CONSTRAINT(OP,CODE) \
1974 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1975 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1976 && mips16_gp_offset_p (OP)) \
1977 : (GET_CODE (OP) != MEM) ? FALSE \
1978 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1979 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1980 && HALF_PIC_ADDRESS_P (OP)) \
1983 /* Given an rtx X being reloaded into a reg required to be
1984 in class CLASS, return the class of reg to actually use.
1985 In general this is just CLASS; but on some machines
1986 in some cases it is preferable to use a more restrictive class. */
1988 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1989 ((CLASS) != ALL_REGS \
1990 ? (! TARGET_MIPS16 \
1992 : ((CLASS) != GR_REGS \
1995 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1996 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1997 ? (TARGET_SOFT_FLOAT \
1998 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2000 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2001 || GET_MODE (X) == VOIDmode) \
2002 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2005 /* Certain machines have the property that some registers cannot be
2006 copied to some other registers without using memory. Define this
2007 macro on those machines to be a C expression that is non-zero if
2008 objects of mode MODE in registers of CLASS1 can only be copied to
2009 registers of class CLASS2 by storing a register of CLASS1 into
2010 memory and loading that memory location into a register of CLASS2.
2012 Do not define this macro if its value would always be zero. */
2014 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2015 ((!TARGET_DEBUG_H_MODE \
2016 && GET_MODE_CLASS (MODE) == MODE_INT \
2017 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2018 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2019 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2020 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2021 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2023 /* The HI and LO registers can only be reloaded via the general
2024 registers. Condition code registers can only be loaded to the
2025 general registers, and from the floating point registers. */
2027 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2028 mips_secondary_reload_class (CLASS, MODE, X, 1)
2029 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2030 mips_secondary_reload_class (CLASS, MODE, X, 0)
2032 /* Return the maximum number of consecutive registers
2033 needed to represent mode MODE in a register of class CLASS. */
2035 #define CLASS_UNITS(mode, size) \
2036 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2038 #define CLASS_MAX_NREGS(CLASS, MODE) \
2039 ((CLASS) == FP_REGS \
2041 ? CLASS_UNITS (MODE, 8) \
2042 : 2 * CLASS_UNITS (MODE, 8)) \
2043 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2045 /* If defined, gives a class of registers that cannot be used as the
2046 operand of a SUBREG that changes the mode of the object illegally. */
2048 #define CLASS_CANNOT_CHANGE_MODE \
2049 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2051 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2053 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2054 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2056 /* Stack layout; function entry, exit and calling. */
2058 /* Define this if pushing a word on the stack
2059 makes the stack pointer a smaller address. */
2060 #define STACK_GROWS_DOWNWARD
2062 /* Define this if the nominal address of the stack frame
2063 is at the high-address end of the local variables;
2064 that is, each additional local variable allocated
2065 goes at a more negative offset in the frame. */
2066 /* #define FRAME_GROWS_DOWNWARD */
2068 /* Offset within stack frame to start allocating local variables at.
2069 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2070 first local allocated. Otherwise, it is the offset to the BEGINNING
2071 of the first local allocated. */
2072 #define STARTING_FRAME_OFFSET \
2073 (current_function_outgoing_args_size \
2074 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2076 /* Offset from the stack pointer register to an item dynamically
2077 allocated on the stack, e.g., by `alloca'.
2079 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2080 length of the outgoing arguments. The default is correct for most
2081 machines. See `function.c' for details.
2083 The MIPS ABI states that functions which dynamically allocate the
2084 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2085 we are trying to create a second frame pointer to the function, so
2086 allocate some stack space to make it happy.
2088 However, the linker currently complains about linking any code that
2089 dynamically allocates stack space, and there seems to be a bug in
2090 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2093 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2094 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2095 ? 4*UNITS_PER_WORD \
2096 : current_function_outgoing_args_size)
2099 /* The return address for the current frame is in r31 is this is a leaf
2100 function. Otherwise, it is on the stack. It is at a variable offset
2101 from sp/fp/ap, so we define a fake hard register rap which is a
2102 poiner to the return address on the stack. This always gets eliminated
2103 during reload to be either the frame pointer or the stack pointer plus
2106 /* ??? This definition fails for leaf functions. There is currently no
2107 general solution for this problem. */
2109 /* ??? There appears to be no way to get the return address of any previous
2110 frame except by disassembling instructions in the prologue/epilogue.
2111 So currently we support only the current frame. */
2113 #define RETURN_ADDR_RTX(count, frame) \
2115 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2118 /* Structure to be filled in by compute_frame_size with register
2119 save masks, and offsets for the current function. */
2121 struct mips_frame_info
2123 long total_size; /* # bytes that the entire frame takes up */
2124 long var_size; /* # bytes that variables take up */
2125 long args_size; /* # bytes that outgoing arguments take up */
2126 long extra_size; /* # bytes of extra gunk */
2127 int gp_reg_size; /* # bytes needed to store gp regs */
2128 int fp_reg_size; /* # bytes needed to store fp regs */
2129 long mask; /* mask of saved gp registers */
2130 long fmask; /* mask of saved fp registers */
2131 long gp_save_offset; /* offset from vfp to store gp registers */
2132 long fp_save_offset; /* offset from vfp to store fp registers */
2133 long gp_sp_offset; /* offset from new sp to store gp registers */
2134 long fp_sp_offset; /* offset from new sp to store fp registers */
2135 int initialized; /* != 0 if frame size already calculated */
2136 int num_gp; /* number of gp registers saved */
2137 int num_fp; /* number of fp registers saved */
2138 long insns_len; /* length of insns; mips16 only */
2141 extern struct mips_frame_info current_frame_info;
2143 /* If defined, this macro specifies a table of register pairs used to
2144 eliminate unneeded registers that point into the stack frame. If
2145 it is not defined, the only elimination attempted by the compiler
2146 is to replace references to the frame pointer with references to
2149 The definition of this macro is a list of structure
2150 initializations, each of which specifies an original and
2151 replacement register.
2153 On some machines, the position of the argument pointer is not
2154 known until the compilation is completed. In such a case, a
2155 separate hard register must be used for the argument pointer.
2156 This register can be eliminated by replacing it with either the
2157 frame pointer or the argument pointer, depending on whether or not
2158 the frame pointer has been eliminated.
2160 In this case, you might specify:
2161 #define ELIMINABLE_REGS \
2162 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2163 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2164 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2166 Note that the elimination of the argument pointer with the stack
2167 pointer is specified first since that is the preferred elimination.
2169 The eliminations to $17 are only used on the mips16. See the
2170 definition of HARD_FRAME_POINTER_REGNUM. */
2172 #define ELIMINABLE_REGS \
2173 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2174 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2175 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2176 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2177 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2178 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2179 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2180 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2181 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2182 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2184 /* A C expression that returns non-zero if the compiler is allowed to
2185 try to replace register number FROM-REG with register number
2186 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2187 defined, and will usually be the constant 1, since most of the
2188 cases preventing register elimination are things that the compiler
2189 already knows about.
2191 When not in mips16 and mips64, we can always eliminate to the
2192 frame pointer. We can eliminate to the stack pointer unless
2193 a frame pointer is needed. In mips16 mode, we need a frame
2194 pointer for a large frame; otherwise, reload may be unable
2195 to compute the address of a local variable, since there is
2196 no way to add a large constant to the stack pointer
2197 without using a temporary register.
2199 In mips16, for some instructions (eg lwu), we can't eliminate the
2200 frame pointer for the stack pointer. These instructions are
2201 only generated in TARGET_64BIT mode.
2204 #define CAN_ELIMINATE(FROM, TO) \
2205 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2206 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2207 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2208 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2209 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2210 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2211 && (! TARGET_MIPS16 \
2212 || compute_frame_size (get_frame_size ()) < 32768)))))
2214 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2215 specifies the initial difference between the specified pair of
2216 registers. This macro must be defined if `ELIMINABLE_REGS' is
2219 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2220 { compute_frame_size (get_frame_size ()); \
2221 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2222 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2223 (OFFSET) = - current_function_outgoing_args_size; \
2224 else if ((FROM) == FRAME_POINTER_REGNUM) \
2226 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2227 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2228 (OFFSET) = (current_frame_info.total_size \
2229 - current_function_outgoing_args_size \
2230 - ((mips_abi != ABI_32 \
2231 && mips_abi != ABI_O64 \
2232 && mips_abi != ABI_EABI) \
2233 ? current_function_pretend_args_size \
2235 else if ((FROM) == ARG_POINTER_REGNUM) \
2236 (OFFSET) = (current_frame_info.total_size \
2237 - ((mips_abi != ABI_32 \
2238 && mips_abi != ABI_O64 \
2239 && mips_abi != ABI_EABI) \
2240 ? current_function_pretend_args_size \
2242 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2243 so we must add 4 bytes to the offset to get the right value. */ \
2244 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2246 if (leaf_function_p ()) \
2248 else (OFFSET) = current_frame_info.gp_sp_offset \
2249 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2250 * (BYTES_BIG_ENDIAN != 0)); \
2254 /* If we generate an insn to push BYTES bytes,
2255 this says how many the stack pointer really advances by.
2256 On the vax, sp@- in a byte insn really pushes a word. */
2258 /* #define PUSH_ROUNDING(BYTES) 0 */
2260 /* If defined, the maximum amount of space required for outgoing
2261 arguments will be computed and placed into the variable
2262 `current_function_outgoing_args_size'. No space will be pushed
2263 onto the stack for each call; instead, the function prologue
2264 should increase the stack frame size by this amount.
2266 It is not proper to define both `PUSH_ROUNDING' and
2267 `ACCUMULATE_OUTGOING_ARGS'. */
2268 #define ACCUMULATE_OUTGOING_ARGS 1
2270 /* Offset from the argument pointer register to the first argument's
2271 address. On some machines it may depend on the data type of the
2274 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2275 the first argument's address.
2277 On the MIPS, we must skip the first argument position if we are
2278 returning a structure or a union, to account for its address being
2279 passed in $4. However, at the current time, this produces a compiler
2280 that can't bootstrap, so comment it out for now. */
2283 #define FIRST_PARM_OFFSET(FNDECL) \
2285 && TREE_TYPE (FNDECL) != 0 \
2286 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2287 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2288 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2292 #define FIRST_PARM_OFFSET(FNDECL) 0
2295 /* When a parameter is passed in a register, stack space is still
2296 allocated for it. For the MIPS, stack space must be allocated, cf
2297 Asm Lang Prog Guide page 7-8.
2299 BEWARE that some space is also allocated for non existing arguments
2300 in register. In case an argument list is of form GF used registers
2301 are a0 (a2,a3), but we should push over a1... */
2303 #define REG_PARM_STACK_SPACE(FNDECL) \
2304 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2306 /* Define this if it is the responsibility of the caller to
2307 allocate the area reserved for arguments passed in registers.
2308 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2309 of this macro is to determine whether the space is included in
2310 `current_function_outgoing_args_size'. */
2311 #define OUTGOING_REG_PARM_STACK_SPACE
2313 /* Align stack frames on 64 bits (Double Word ). */
2314 #ifndef STACK_BOUNDARY
2315 #define STACK_BOUNDARY 64
2318 /* Make sure 4 words are always allocated on the stack. */
2320 #ifndef STACK_ARGS_ADJUST
2321 #define STACK_ARGS_ADJUST(SIZE) \
2323 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2324 SIZE.constant = 4 * UNITS_PER_WORD; \
2329 /* A C expression that should indicate the number of bytes of its
2330 own arguments that a function pops on returning, or 0
2331 if the function pops no arguments and the caller must therefore
2332 pop them all after the function returns.
2334 FUNDECL is the declaration node of the function (as a tree).
2336 FUNTYPE is a C variable whose value is a tree node that
2337 describes the function in question. Normally it is a node of
2338 type `FUNCTION_TYPE' that describes the data type of the function.
2339 From this it is possible to obtain the data types of the value
2340 and arguments (if known).
2342 When a call to a library function is being considered, FUNTYPE
2343 will contain an identifier node for the library function. Thus,
2344 if you need to distinguish among various library functions, you
2345 can do so by their names. Note that "library function" in this
2346 context means a function used to perform arithmetic, whose name
2347 is known specially in the compiler and was not mentioned in the
2348 C code being compiled.
2350 STACK-SIZE is the number of bytes of arguments passed on the
2351 stack. If a variable number of bytes is passed, it is zero, and
2352 argument popping will always be the responsibility of the
2353 calling function. */
2355 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2358 /* Symbolic macros for the registers used to return integer and floating
2361 #define GP_RETURN (GP_REG_FIRST + 2)
2362 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2364 /* Symbolic macros for the first/last argument registers. */
2366 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2367 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2368 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2369 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2371 #define MAX_ARGS_IN_REGISTERS 4
2373 /* Define how to find the value returned by a library function
2374 assuming the value has mode MODE. Because we define
2375 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2376 PROMOTE_MODE does. */
2378 #define LIBCALL_VALUE(MODE) \
2380 ((GET_MODE_CLASS (MODE) != MODE_INT \
2381 || GET_MODE_SIZE (MODE) >= 4) \
2384 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2385 && (! TARGET_SINGLE_FLOAT \
2386 || GET_MODE_SIZE (MODE) <= 4)) \
2390 /* Define how to find the value returned by a function.
2391 VALTYPE is the data type of the value (as a tree).
2392 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2393 otherwise, FUNC is 0. */
2395 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2398 /* 1 if N is a possible register number for a function value.
2399 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2400 Currently, R2 and F0 are only implemented here (C has no complex type) */
2402 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2404 /* 1 if N is a possible register number for function argument passing.
2405 We have no FP argument registers when soft-float. When FP registers
2406 are 32 bits, we can't directly reference the odd numbered ones. */
2408 #define FUNCTION_ARG_REGNO_P(N) \
2409 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2410 || ((! TARGET_SOFT_FLOAT \
2411 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2412 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2413 && ! fixed_regs[N]))
2415 /* A C expression which can inhibit the returning of certain function
2416 values in registers, based on the type of value. A nonzero value says
2417 to return the function value in memory, just as large structures are
2418 always returned. Here TYPE will be a C expression of type
2419 `tree', representing the data type of the value.
2421 Note that values of mode `BLKmode' must be explicitly
2422 handled by this macro. Also, the option `-fpcc-struct-return'
2423 takes effect regardless of this macro. On most systems, it is
2424 possible to leave the macro undefined; this causes a default
2425 definition to be used, whose value is the constant 1 for BLKmode
2426 values, and 0 otherwise.
2428 GCC normally converts 1 byte structures into chars, 2 byte
2429 structs into shorts, and 4 byte structs into ints, and returns
2430 them this way. Defining the following macro overrides this,
2431 to give us MIPS cc compatibility. */
2433 #define RETURN_IN_MEMORY(TYPE) \
2434 (TYPE_MODE (TYPE) == BLKmode)
2436 /* A code distinguishing the floating point format of the target
2437 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2438 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2440 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2443 /* Define a data type for recording info about an argument list
2444 during the scan of that argument list. This data type should
2445 hold all necessary information about the function itself
2446 and about the args processed so far, enough to enable macros
2447 such as FUNCTION_ARG to determine where the next arg should go.
2449 On the mips16, we need to keep track of which floating point
2450 arguments were passed in general registers, but would have been
2451 passed in the FP regs if this were a 32 bit function, so that we
2452 can move them to the FP regs if we wind up calling a 32 bit
2453 function. We record this information in fp_code, encoded in base
2454 four. A zero digit means no floating point argument, a one digit
2455 means an SFmode argument, and a two digit means a DFmode argument,
2456 and a three digit is not used. The low order digit is the first
2457 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2458 an SFmode argument. ??? A more sophisticated approach will be
2459 needed if MIPS_ABI != ABI_32. */
2461 typedef struct mips_args {
2462 int gp_reg_found; /* whether a gp register was found yet */
2463 unsigned int arg_number; /* argument number */
2464 unsigned int arg_words; /* # total words the arguments take */
2465 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2466 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2467 int fp_code; /* Mode of FP arguments (mips16) */
2468 unsigned int num_adjusts; /* number of adjustments made */
2469 /* Adjustments made to args pass in regs. */
2470 /* ??? The size is doubled to work around a
2471 bug in the code that sets the adjustments
2473 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2476 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2477 for a call to a function whose data type is FNTYPE.
2478 For a library call, FNTYPE is 0.
2482 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2483 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2485 /* Update the data in CUM to advance over an argument
2486 of mode MODE and data type TYPE.
2487 (TYPE is null for libcalls where that information may not be available.) */
2489 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2490 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2492 /* Determine where to put an argument to a function.
2493 Value is zero to push the argument on the stack,
2494 or a hard register in which to store the argument.
2496 MODE is the argument's machine mode.
2497 TYPE is the data type of the argument (as a tree).
2498 This is null for libcalls where that information may
2500 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2501 the preceding args and about the function being called.
2502 NAMED is nonzero if this argument is a named parameter
2503 (otherwise it is an extra parameter matching an ellipsis). */
2505 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2506 function_arg( &CUM, MODE, TYPE, NAMED)
2508 /* For an arg passed partly in registers and partly in memory,
2509 this is the number of registers used.
2510 For args passed entirely in registers or entirely in memory, zero. */
2512 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2513 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2515 /* If defined, a C expression that gives the alignment boundary, in
2516 bits, of an argument with the specified mode and type. If it is
2517 not defined, `PARM_BOUNDARY' is used for all arguments. */
2519 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2521 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2523 : TYPE_ALIGN(TYPE)) \
2524 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2526 : GET_MODE_ALIGNMENT(MODE)))
2529 /* This macro generates the assembly code for function entry.
2530 FILE is a stdio stream to output the code to.
2531 SIZE is an int: how many units of temporary storage to allocate.
2532 Refer to the array `regs_ever_live' to determine which registers
2533 to save; `regs_ever_live[I]' is nonzero if register number I
2534 is ever used in the function. This macro is responsible for
2535 knowing which registers should not be saved even if used. */
2537 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2539 /* This macro generates the assembly code for function exit,
2540 on machines that need it. If FUNCTION_EPILOGUE is not defined
2541 then individual return instructions are generated for each
2542 return statement. Args are same as for FUNCTION_PROLOGUE. */
2544 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2546 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2548 #define MUST_SAVE_REGISTER(regno) \
2549 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2550 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2551 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2553 /* ALIGN FRAMES on double word boundaries */
2554 #ifndef MIPS_STACK_ALIGN
2555 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2559 /* Define the `__builtin_va_list' type for the ABI. */
2560 #define BUILD_VA_LIST_TYPE(VALIST) \
2561 (VALIST) = mips_build_va_list ()
2563 /* Implement `va_start' for varargs and stdarg. */
2564 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2565 mips_va_start (stdarg, valist, nextarg)
2567 /* Implement `va_arg'. */
2568 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2569 mips_va_arg (valist, type)
2571 /* Output assembler code to FILE to increment profiler label # LABELNO
2572 for profiling a function entry. */
2574 #define FUNCTION_PROFILER(FILE, LABELNO) \
2576 if (TARGET_MIPS16) \
2577 sorry ("mips16 function profiling"); \
2578 fprintf (FILE, "\t.set\tnoreorder\n"); \
2579 fprintf (FILE, "\t.set\tnoat\n"); \
2580 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2581 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2582 fprintf (FILE, "\tjal\t_mcount\n"); \
2584 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2585 TARGET_64BIT ? "dsubu" : "subu", \
2586 reg_names[STACK_POINTER_REGNUM], \
2587 reg_names[STACK_POINTER_REGNUM], \
2588 Pmode == DImode ? 16 : 8); \
2589 fprintf (FILE, "\t.set\treorder\n"); \
2590 fprintf (FILE, "\t.set\tat\n"); \
2593 /* Define this macro if the code for function profiling should come
2594 before the function prologue. Normally, the profiling code comes
2597 /* #define PROFILE_BEFORE_PROLOGUE */
2599 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2600 the stack pointer does not matter. The value is tested only in
2601 functions that have frame pointers.
2602 No definition is equivalent to always zero. */
2604 #define EXIT_IGNORE_STACK 1
2607 /* A C statement to output, on the stream FILE, assembler code for a
2608 block of data that contains the constant parts of a trampoline.
2609 This code should not include a label--the label is taken care of
2612 #define TRAMPOLINE_TEMPLATE(STREAM) \
2614 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2615 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2616 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2617 if (Pmode == DImode) \
2619 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2620 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2624 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2625 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2627 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2628 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2629 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2630 if (Pmode == DImode) \
2632 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2633 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2637 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2638 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2642 /* A C expression for the size in bytes of the trampoline, as an
2645 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2647 /* Alignment required for trampolines, in bits. */
2649 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2651 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2652 program and data caches. */
2654 #ifndef CACHE_FLUSH_FUNC
2655 #define CACHE_FLUSH_FUNC "_flush_cache"
2658 /* A C statement to initialize the variable parts of a trampoline.
2659 ADDR is an RTX for the address of the trampoline; FNADDR is an
2660 RTX for the address of the nested function; STATIC_CHAIN is an
2661 RTX for the static chain value that should be passed to the
2662 function when it is called. */
2664 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2667 if (Pmode == DImode) \
2669 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2670 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2674 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2675 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2678 /* Flush both caches. We need to flush the data cache in case \
2679 the system has a write-back cache. */ \
2680 /* ??? Should check the return value for errors. */ \
2681 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2682 0, VOIDmode, 3, addr, Pmode, \
2683 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2684 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2687 /* Addressing modes, and classification of registers for them. */
2689 /* #define HAVE_POST_INCREMENT 0 */
2690 /* #define HAVE_POST_DECREMENT 0 */
2692 /* #define HAVE_PRE_DECREMENT 0 */
2693 /* #define HAVE_PRE_INCREMENT 0 */
2695 /* These assume that REGNO is a hard or pseudo reg number.
2696 They give nonzero only if REGNO is a hard reg of the suitable class
2697 or a pseudo reg currently allocated to a suitable hard reg.
2698 These definitions are NOT overridden anywhere. */
2700 #define BASE_REG_P(regno, mode) \
2702 ? (M16_REG_P (regno) \
2703 || (regno) == FRAME_POINTER_REGNUM \
2704 || (regno) == ARG_POINTER_REGNUM \
2705 || ((regno) == STACK_POINTER_REGNUM \
2706 && (GET_MODE_SIZE (mode) == 4 \
2707 || GET_MODE_SIZE (mode) == 8))) \
2710 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2711 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2714 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2715 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2717 #define REGNO_OK_FOR_INDEX_P(regno) 0
2718 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2719 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2721 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2722 and check its validity for a certain class.
2723 We have two alternate definitions for each of them.
2724 The usual definition accepts all pseudo regs; the other rejects them all.
2725 The symbol REG_OK_STRICT causes the latter definition to be used.
2727 Most source files want to accept pseudo regs in the hope that
2728 they will get allocated to the class that the insn wants them to be in.
2729 Some source files that are used after register allocation
2730 need to be strict. */
2732 #ifndef REG_OK_STRICT
2733 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2734 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2736 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2737 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2740 #define REG_OK_FOR_INDEX_P(X) 0
2743 /* Maximum number of registers that can appear in a valid memory address. */
2745 #define MAX_REGS_PER_ADDRESS 1
2747 /* A C compound statement with a conditional `goto LABEL;' executed
2748 if X (an RTX) is a legitimate memory address on the target
2749 machine for a memory operand of mode MODE.
2751 It usually pays to define several simpler macros to serve as
2752 subroutines for this one. Otherwise it may be too complicated
2755 This macro must exist in two variants: a strict variant and a
2756 non-strict one. The strict variant is used in the reload pass.
2757 It must be defined so that any pseudo-register that has not been
2758 allocated a hard register is considered a memory reference. In
2759 contexts where some kind of register is required, a
2760 pseudo-register with no hard register must be rejected.
2762 The non-strict variant is used in other passes. It must be
2763 defined to accept all pseudo-registers in every context where
2764 some kind of register is required.
2766 Compiler source files that want to use the strict variant of
2767 this macro define the macro `REG_OK_STRICT'. You should use an
2768 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2769 in that case and the non-strict variant otherwise.
2771 Typically among the subroutines used to define
2772 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2773 acceptable registers for various purposes (one for base
2774 registers, one for index registers, and so on). Then only these
2775 subroutine macros need have two variants; the higher levels of
2776 macros may be the same whether strict or not.
2778 Normally, constant addresses which are the sum of a `symbol_ref'
2779 and an integer are stored inside a `const' RTX to mark them as
2780 constant. Therefore, there is no need to recognize such sums
2781 specifically as legitimate addresses. Normally you would simply
2782 recognize any `const' as legitimate.
2784 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2785 constant sums that are not marked with `const'. It assumes
2786 that a naked `plus' indicates indexing. If so, then you *must*
2787 reject such naked constant sums as illegitimate addresses, so
2788 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2790 On some machines, whether a symbolic address is legitimate
2791 depends on the section that the address refers to. On these
2792 machines, define the macro `ENCODE_SECTION_INFO' to store the
2793 information into the `symbol_ref', and then check for it here.
2794 When you see a `const', you will have to look inside it to find
2795 the `symbol_ref' in order to determine the section. */
2798 #define GO_PRINTF(x) fprintf(stderr, (x))
2799 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2800 #define GO_DEBUG_RTX(x) debug_rtx(x)
2803 #define GO_PRINTF(x)
2804 #define GO_PRINTF2(x,y)
2805 #define GO_DEBUG_RTX(x)
2808 #ifdef REG_OK_STRICT
2809 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2811 if (mips_legitimate_address_p (MODE, X, 1)) \
2815 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2817 if (mips_legitimate_address_p (MODE, X, 0)) \
2822 /* A C expression that is 1 if the RTX X is a constant which is a
2823 valid address. This is defined to be the same as `CONSTANT_P (X)',
2824 but rejecting CONST_DOUBLE. */
2825 /* When pic, we must reject addresses of the form symbol+large int.
2826 This is because an instruction `sw $4,s+70000' needs to be converted
2827 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2828 assembler would use $at as a temp to load in the large offset. In this
2829 case $at is already in use. We convert such problem addresses to
2830 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2831 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2832 #define CONSTANT_ADDRESS_P(X) \
2833 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2834 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2835 || (GET_CODE (X) == CONST \
2836 && ! (flag_pic && pic_address_needs_scratch (X)) \
2837 && (mips_abi == ABI_32 \
2838 || mips_abi == ABI_O64 \
2839 || mips_abi == ABI_EABI))) \
2840 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2842 /* Define this, so that when PIC, reload won't try to reload invalid
2843 addresses which require two reload registers. */
2845 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2847 /* Nonzero if the constant value X is a legitimate general operand.
2848 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2850 At present, GAS doesn't understand li.[sd], so don't allow it
2851 to be generated at present. Also, the MIPS assembler does not
2852 grok li.d Infinity. */
2854 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2855 Note that the Irix 6 assembler problem may already be fixed.
2856 Note also that the GET_CODE (X) == CONST test catches the mips16
2857 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2858 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2859 ABI_64 to work together, we'll need to fix this. */
2860 #define LEGITIMATE_CONSTANT_P(X) \
2861 ((GET_CODE (X) != CONST_DOUBLE \
2862 || mips_const_double_ok (X, GET_MODE (X))) \
2863 && ! (GET_CODE (X) == CONST \
2865 && (mips_abi == ABI_N32 \
2866 || mips_abi == ABI_64)) \
2867 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2869 /* A C compound statement that attempts to replace X with a valid
2870 memory address for an operand of mode MODE. WIN will be a C
2871 statement label elsewhere in the code; the macro definition may
2874 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2876 to avoid further processing if the address has become legitimate.
2878 X will always be the result of a call to `break_out_memory_refs',
2879 and OLDX will be the operand that was given to that function to
2882 The code generated by this macro should not alter the
2883 substructure of X. If it transforms X into a more legitimate
2884 form, it should assign X (which will always be a C variable) a
2887 It is not necessary for this macro to come up with a legitimate
2888 address. The compiler has standard ways of doing so in all
2889 cases. In fact, it is safe for this macro to do nothing. But
2890 often a machine-dependent strategy can generate better code.
2892 For the MIPS, transform:
2894 memory(X + <large int>)
2898 Y = <large int> & ~0x7fff;
2900 memory (Z + (<large int> & 0x7fff));
2902 This is for CSE to find several similar references, and only use one Z.
2904 When PIC, convert addresses of the form memory (symbol+large int) to
2905 memory (reg+large int). */
2908 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2910 register rtx xinsn = (X); \
2912 if (TARGET_DEBUG_B_MODE) \
2914 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2915 GO_DEBUG_RTX (xinsn); \
2918 if (mips_split_addresses && mips_check_split (X, MODE)) \
2920 /* ??? Is this ever executed? */ \
2921 X = gen_rtx_LO_SUM (Pmode, \
2922 copy_to_mode_reg (Pmode, \
2923 gen_rtx (HIGH, Pmode, X)), \
2928 if (GET_CODE (xinsn) == CONST \
2929 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2930 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2931 || (mips_abi != ABI_32 \
2932 && mips_abi != ABI_O64 \
2933 && mips_abi != ABI_EABI))) \
2935 rtx ptr_reg = gen_reg_rtx (Pmode); \
2936 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2938 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2940 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
2941 if (SMALL_INT (constant)) \
2943 /* Otherwise we fall through so the code below will fix the \
2948 if (GET_CODE (xinsn) == PLUS) \
2950 register rtx xplus0 = XEXP (xinsn, 0); \
2951 register rtx xplus1 = XEXP (xinsn, 1); \
2952 register enum rtx_code code0 = GET_CODE (xplus0); \
2953 register enum rtx_code code1 = GET_CODE (xplus1); \
2955 if (code0 != REG && code1 == REG) \
2957 xplus0 = XEXP (xinsn, 1); \
2958 xplus1 = XEXP (xinsn, 0); \
2959 code0 = GET_CODE (xplus0); \
2960 code1 = GET_CODE (xplus1); \
2963 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2964 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2966 rtx int_reg = gen_reg_rtx (Pmode); \
2967 rtx ptr_reg = gen_reg_rtx (Pmode); \
2969 emit_move_insn (int_reg, \
2970 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2972 emit_insn (gen_rtx_SET (VOIDmode, \
2974 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
2976 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
2981 if (TARGET_DEBUG_B_MODE) \
2982 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2986 /* A C statement or compound statement with a conditional `goto
2987 LABEL;' executed if memory address X (an RTX) can have different
2988 meanings depending on the machine mode of the memory reference it
2991 Autoincrement and autodecrement addresses typically have
2992 mode-dependent effects because the amount of the increment or
2993 decrement is the size of the operand being addressed. Some
2994 machines have other mode-dependent addresses. Many RISC machines
2995 have no mode-dependent addresses.
2997 You may assume that ADDR is a valid address for the machine. */
2999 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3002 /* Define this macro if references to a symbol must be treated
3003 differently depending on something about the variable or
3004 function named by the symbol (such as what section it is in).
3006 The macro definition, if any, is executed immediately after the
3007 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3008 The value of the rtl will be a `mem' whose address is a
3011 The usual thing for this macro to do is to a flag in the
3012 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3013 name string in the `symbol_ref' (if one bit is not enough
3016 The best way to modify the name string is by adding text to the
3017 beginning, with suitable punctuation to prevent any ambiguity.
3018 Allocate the new name in `saveable_obstack'. You will have to
3019 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3020 and output the name accordingly.
3022 You can also check the information stored in the `symbol_ref' in
3023 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3024 `PRINT_OPERAND_ADDRESS'.
3026 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3029 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3030 symbols which are not in the .text section.
3032 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3033 constants which are put in the .text section. We also record the
3034 total length of all such strings; this total is used to decide
3035 whether we need to split the constant table, and need not be
3038 When not mips16 code nor embedded PIC, if a symbol is in a
3039 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3040 splitting the reference so that gas can generate a gp relative
3043 When TARGET_EMBEDDED_DATA is set, we assume that all const
3044 variables will be stored in ROM, which is too far from %gp to use
3045 %gprel addressing. Note that (1) we include "extern const"
3046 variables in this, which mips_select_section doesn't, and (2) we
3047 can't always tell if they're really const (they might be const C++
3048 objects with non-const constructors), so we err on the side of
3049 caution and won't use %gprel anyway (otherwise we'd have to defer
3050 this decision to the linker/loader). The handling of extern consts
3051 is why the DECL_INITIAL macros differ from mips_select_section.
3053 If you are changing this macro, you should look at
3054 mips_select_section and see if it needs a similar change. */
3056 #ifndef UNIQUE_SECTION_P
3057 #define UNIQUE_SECTION_P(DECL) (0)
3060 #define ENCODE_SECTION_INFO(DECL) \
3063 if (TARGET_MIPS16) \
3065 if (TREE_CODE (DECL) == STRING_CST \
3066 && ! flag_writable_strings \
3067 /* If this string is from a function, and the function will \
3068 go in a gnu linkonce section, then we can't directly \
3069 access the string. This gets an assembler error \
3070 "unsupported PC relative reference to different section".\
3071 If we modify SELECT_SECTION to put it in function_section\
3072 instead of text_section, it still fails because \
3073 DECL_SECTION_NAME isn't set until assemble_start_function.\
3074 If we fix that, it still fails because strings are shared\
3075 among multiple functions, and we have cross section \
3076 references again. We force it to work by putting string \
3077 addresses in the constant pool and indirecting. */ \
3078 && (! current_function_decl \
3079 || ! UNIQUE_SECTION_P (current_function_decl))) \
3081 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3082 mips_string_length += TREE_STRING_LENGTH (DECL); \
3086 if (TARGET_EMBEDDED_DATA \
3087 && (TREE_CODE (DECL) == VAR_DECL \
3088 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3089 && (!DECL_INITIAL (DECL) \
3090 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3092 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3095 else if (TARGET_EMBEDDED_PIC) \
3097 if (TREE_CODE (DECL) == VAR_DECL) \
3098 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3099 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3100 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3101 else if (TREE_CODE (DECL) == STRING_CST \
3102 && ! flag_writable_strings) \
3103 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3105 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3108 else if (TREE_CODE (DECL) == VAR_DECL \
3109 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3110 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3112 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3115 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3118 /* We can not perform GP optimizations on variables which are in \
3119 specific sections, except for .sdata and .sbss which are \
3121 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3122 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3124 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3126 if (size > 0 && size <= mips_section_threshold) \
3127 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3130 else if (HALF_PIC_P ()) \
3132 HALF_PIC_ENCODE (DECL); \
3137 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3138 'the start of the function that this code is output in'. */
3140 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3141 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3142 asm_fprintf ((FILE), "%U%s", \
3143 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3145 asm_fprintf ((FILE), "%U%s", (NAME))
3147 /* The mips16 wants the constant pool to be after the function,
3148 because the PC relative load instructions use unsigned offsets. */
3150 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3152 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3153 mips_string_length = 0;
3156 /* In mips16 mode, put most string constants after the function. */
3157 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3158 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3161 /* Specify the machine mode that this machine uses
3162 for the index in the tablejump instruction.
3163 ??? Using HImode in mips16 mode can cause overflow. However, the
3164 overflow is no more likely than the overflow in a branch
3165 instruction. Large functions can currently break in both ways. */
3166 #define CASE_VECTOR_MODE \
3167 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3169 /* Define as C expression which evaluates to nonzero if the tablejump
3170 instruction expects the table to contain offsets from the address of the
3172 Do not define this if the table should contain absolute addresses. */
3173 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3175 /* Specify the tree operation to be used to convert reals to integers. */
3176 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3178 /* This is the kind of divide that is easiest to do in the general case. */
3179 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3181 /* Define this as 1 if `char' should by default be signed; else as 0. */
3182 #ifndef DEFAULT_SIGNED_CHAR
3183 #define DEFAULT_SIGNED_CHAR 1
3186 /* Max number of bytes we can move from memory to memory
3187 in one reasonably fast instruction. */
3188 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3189 #define MAX_MOVE_MAX 8
3191 /* Define this macro as a C expression which is nonzero if
3192 accessing less than a word of memory (i.e. a `char' or a
3193 `short') is no faster than accessing a word of memory, i.e., if
3194 such access require more than one instruction or if there is no
3195 difference in cost between byte and (aligned) word loads.
3197 On RISC machines, it tends to generate better code to define
3198 this as 1, since it avoids making a QI or HI mode register. */
3199 #define SLOW_BYTE_ACCESS 1
3201 /* We assume that the store-condition-codes instructions store 0 for false
3202 and some other value for true. This is the value stored for true. */
3204 #define STORE_FLAG_VALUE 1
3206 /* Define this if zero-extension is slow (more than one real instruction). */
3207 #define SLOW_ZERO_EXTEND
3209 /* Define this to be nonzero if shift instructions ignore all but the low-order
3211 #define SHIFT_COUNT_TRUNCATED 1
3213 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3214 is done just by pretending it is already truncated. */
3215 /* In 64 bit mode, 32 bit instructions require that register values be properly
3216 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3217 converts a value >32 bits to a value <32 bits. */
3218 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3219 Something needs to be done about this. Perhaps not use any 32 bit
3220 instructions? Perhaps use PROMOTE_MODE? */
3221 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3222 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3224 /* Specify the machine mode that pointers have.
3225 After generation of rtl, the compiler makes no further distinction
3226 between pointers and any other objects of this machine mode.
3228 For MIPS we make pointers are the smaller of longs and gp-registers. */
3231 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3234 /* A function address in a call instruction
3235 is a word address (for indexing purposes)
3236 so give the MEM rtx a words's mode. */
3238 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3240 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3241 memset, instead of the BSD functions bcopy and bzero. */
3243 #if defined(MIPS_SYSV) || defined(OSF_OS)
3244 #define TARGET_MEM_FUNCTIONS
3248 /* A part of a C `switch' statement that describes the relative
3249 costs of constant RTL expressions. It must contain `case'
3250 labels for expression codes `const_int', `const', `symbol_ref',
3251 `label_ref' and `const_double'. Each case must ultimately reach
3252 a `return' statement to return the relative cost of the use of
3253 that kind of constant value in an expression. The cost may
3254 depend on the precise value of the constant, which is available
3255 for examination in X.
3257 CODE is the expression code--redundant, since it can be obtained
3258 with `GET_CODE (X)'. */
3260 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3262 if (! TARGET_MIPS16) \
3264 /* Always return 0, since we don't have different sized \
3265 instructions, hence different costs according to Richard \
3269 if ((OUTER_CODE) == SET) \
3271 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3273 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3274 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3275 return COSTS_N_INSNS (1); \
3277 return COSTS_N_INSNS (2); \
3279 /* A PLUS could be an address. We don't want to force an address \
3280 to use a register, so accept any signed 16 bit value without \
3282 if ((OUTER_CODE) == PLUS \
3283 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3285 /* A number between 1 and 8 inclusive is efficient for a shift. \
3286 Otherwise, we will need an extended instruction. */ \
3287 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3288 || (OUTER_CODE) == LSHIFTRT) \
3290 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3292 return COSTS_N_INSNS (1); \
3294 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3295 if ((OUTER_CODE) == XOR \
3296 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3298 /* We may be able to use slt or sltu for a comparison with a \
3299 signed 16 bit value. (The boundary conditions aren't quite \
3300 right, but this is just a heuristic anyhow.) */ \
3301 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3302 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3303 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3304 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3305 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3307 /* Equality comparisons with 0 are cheap. */ \
3308 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3309 && INTVAL (X) == 0) \
3312 /* Otherwise, work out the cost to load the value into a \
3314 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3315 return COSTS_N_INSNS (1); \
3316 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3317 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3318 return COSTS_N_INSNS (2); \
3320 return COSTS_N_INSNS (3); \
3323 return COSTS_N_INSNS (2); \
3327 rtx offset = const0_rtx; \
3328 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3330 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3332 /* Treat this like a signed 16 bit CONST_INT. */ \
3333 if ((OUTER_CODE) == PLUS) \
3335 else if ((OUTER_CODE) == SET) \
3336 return COSTS_N_INSNS (1); \
3338 return COSTS_N_INSNS (2); \
3341 if (GET_CODE (symref) == LABEL_REF) \
3342 return COSTS_N_INSNS (2); \
3344 if (GET_CODE (symref) != SYMBOL_REF) \
3345 return COSTS_N_INSNS (4); \
3347 /* let's be paranoid.... */ \
3348 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3349 return COSTS_N_INSNS (2); \
3351 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3355 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3357 case CONST_DOUBLE: \
3360 if (TARGET_MIPS16) \
3361 return COSTS_N_INSNS (4); \
3362 split_double (X, &high, &low); \
3363 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3364 || low == CONST0_RTX (GET_MODE (low))) \
3368 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3369 This can be used, for example, to indicate how costly a multiply
3370 instruction is. In writing this macro, you can use the construct
3371 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3373 This macro is optional; do not define it if the default cost
3374 assumptions are adequate for the target machine.
3376 If -mdebugd is used, change the multiply cost to 2, so multiply by
3377 a constant isn't converted to a series of shifts. This helps
3378 strength reduction, and also makes it easier to identify what the
3379 compiler is doing. */
3381 /* ??? Fix this to be right for the R8000. */
3382 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3385 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3386 if (simple_memory_operand (X, GET_MODE (X))) \
3387 return COSTS_N_INSNS (num_words); \
3389 return COSTS_N_INSNS (2*num_words); \
3393 return COSTS_N_INSNS (6); \
3396 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3401 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3402 return COSTS_N_INSNS (2); \
3409 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3410 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3416 enum machine_mode xmode = GET_MODE (X); \
3417 if (xmode == SFmode || xmode == DFmode) \
3418 return COSTS_N_INSNS (1); \
3420 return COSTS_N_INSNS (4); \
3426 enum machine_mode xmode = GET_MODE (X); \
3427 if (xmode == SFmode || xmode == DFmode) \
3429 if (mips_cpu == PROCESSOR_R3000 \
3430 || mips_cpu == PROCESSOR_R3900) \
3431 return COSTS_N_INSNS (2); \
3432 else if (mips_cpu == PROCESSOR_R6000) \
3433 return COSTS_N_INSNS (3); \
3435 return COSTS_N_INSNS (6); \
3438 if (xmode == DImode && !TARGET_64BIT) \
3439 return COSTS_N_INSNS (4); \
3445 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3452 enum machine_mode xmode = GET_MODE (X); \
3453 if (xmode == SFmode) \
3455 if (mips_cpu == PROCESSOR_R3000 \
3456 || mips_cpu == PROCESSOR_R3900 \
3457 || mips_cpu == PROCESSOR_R5000) \
3458 return COSTS_N_INSNS (4); \
3459 else if (mips_cpu == PROCESSOR_R6000) \
3460 return COSTS_N_INSNS (5); \
3462 return COSTS_N_INSNS (7); \
3465 if (xmode == DFmode) \
3467 if (mips_cpu == PROCESSOR_R3000 \
3468 || mips_cpu == PROCESSOR_R3900 \
3469 || mips_cpu == PROCESSOR_R5000) \
3470 return COSTS_N_INSNS (5); \
3471 else if (mips_cpu == PROCESSOR_R6000) \
3472 return COSTS_N_INSNS (6); \
3474 return COSTS_N_INSNS (8); \
3477 if (mips_cpu == PROCESSOR_R3000) \
3478 return COSTS_N_INSNS (12); \
3479 else if (mips_cpu == PROCESSOR_R3900) \
3480 return COSTS_N_INSNS (2); \
3481 else if (mips_cpu == PROCESSOR_R6000) \
3482 return COSTS_N_INSNS (17); \
3483 else if (mips_cpu == PROCESSOR_R5000) \
3484 return COSTS_N_INSNS (5); \
3486 return COSTS_N_INSNS (10); \
3492 enum machine_mode xmode = GET_MODE (X); \
3493 if (xmode == SFmode) \
3495 if (mips_cpu == PROCESSOR_R3000 \
3496 || mips_cpu == PROCESSOR_R3900) \
3497 return COSTS_N_INSNS (12); \
3498 else if (mips_cpu == PROCESSOR_R6000) \
3499 return COSTS_N_INSNS (15); \
3501 return COSTS_N_INSNS (23); \
3504 if (xmode == DFmode) \
3506 if (mips_cpu == PROCESSOR_R3000 \
3507 || mips_cpu == PROCESSOR_R3900) \
3508 return COSTS_N_INSNS (19); \
3509 else if (mips_cpu == PROCESSOR_R6000) \
3510 return COSTS_N_INSNS (16); \
3512 return COSTS_N_INSNS (36); \
3515 /* fall through */ \
3519 if (mips_cpu == PROCESSOR_R3000 \
3520 || mips_cpu == PROCESSOR_R3900) \
3521 return COSTS_N_INSNS (35); \
3522 else if (mips_cpu == PROCESSOR_R6000) \
3523 return COSTS_N_INSNS (38); \
3524 else if (mips_cpu == PROCESSOR_R5000) \
3525 return COSTS_N_INSNS (36); \
3527 return COSTS_N_INSNS (69); \
3530 /* A sign extend from SImode to DImode in 64 bit mode is often \
3531 zero instructions, because the result can often be used \
3532 directly by another instruction; we'll call it one. */ \
3533 if (TARGET_64BIT && GET_MODE (X) == DImode \
3534 && GET_MODE (XEXP (X, 0)) == SImode) \
3535 return COSTS_N_INSNS (1); \
3537 return COSTS_N_INSNS (2); \
3540 if (TARGET_64BIT && GET_MODE (X) == DImode \
3541 && GET_MODE (XEXP (X, 0)) == SImode) \
3542 return COSTS_N_INSNS (2); \
3544 return COSTS_N_INSNS (1);
3546 /* An expression giving the cost of an addressing mode that
3547 contains ADDRESS. If not defined, the cost is computed from the
3548 form of the ADDRESS expression and the `CONST_COSTS' values.
3550 For most CISC machines, the default cost is a good approximation
3551 of the true cost of the addressing mode. However, on RISC
3552 machines, all instructions normally have the same length and
3553 execution time. Hence all addresses will have equal costs.
3555 In cases where more than one form of an address is known, the
3556 form with the lowest cost will be used. If multiple forms have
3557 the same, lowest, cost, the one that is the most complex will be
3560 For example, suppose an address that is equal to the sum of a
3561 register and a constant is used twice in the same basic block.
3562 When this macro is not defined, the address will be computed in
3563 a register and memory references will be indirect through that
3564 register. On machines where the cost of the addressing mode
3565 containing the sum is no higher than that of a simple indirect
3566 reference, this will produce an additional instruction and
3567 possibly require an additional register. Proper specification
3568 of this macro eliminates this overhead for such machines.
3570 Similar use of this macro is made in strength reduction of loops.
3572 ADDRESS need not be valid as an address. In such a case, the
3573 cost is not relevant and can be any value; invalid addresses
3574 need not be assigned a different cost.
3576 On machines where an address involving more than one register is
3577 as cheap as an address computation involving only one register,
3578 defining `ADDRESS_COST' to reflect this can cause two registers
3579 to be live over a region of code where only one would have been
3580 if `ADDRESS_COST' were not defined in that manner. This effect
3581 should be considered in the definition of this macro.
3582 Equivalent costs should probably only be given to addresses with
3583 different numbers of registers on machines with lots of registers.
3585 This macro will normally either not be defined or be defined as
3588 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3590 /* A C expression for the cost of moving data from a register in
3591 class FROM to one in class TO. The classes are expressed using
3592 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3593 the default; other values are interpreted relative to that.
3595 It is not required that the cost always equal 2 when FROM is the
3596 same as TO; on some machines it is expensive to move between
3597 registers if they are not general registers.
3599 If reload sees an insn consisting of a single `set' between two
3600 hard registers, and if `REGISTER_MOVE_COST' applied to their
3601 classes returns a value of 2, reload does not check to ensure
3602 that the constraints of the insn are met. Setting a cost of
3603 other than 2 will allow reload to verify that the constraints are
3604 met. You should do this if the `movM' pattern's constraints do
3605 not allow such copying.
3607 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3608 registers the same as for one of moving general registers to
3609 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3610 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3611 isn't clear if it is wise. And it might not work in all cases. We
3612 could solve the DImode LO reg problem by using a multiply, just like
3613 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3614 by using divide instructions. divu puts the remainder in the HI
3615 reg, so doing a divide by -1 will move the value in the HI reg for
3616 all values except -1. We could handle that case by using a signed
3617 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3618 compare/branch to test the input value to see which instruction we
3619 need to use. This gets pretty messy, but it is feasible. */
3621 #define REGISTER_MOVE_COST(FROM, TO) \
3622 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3623 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3624 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3625 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3626 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3627 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3628 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3629 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3630 : (((FROM) == HI_REG || (FROM) == LO_REG \
3631 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3632 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3633 : (((TO) == HI_REG || (TO) == LO_REG \
3634 || (TO) == MD_REGS || (TO) == HILO_REG) \
3635 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3636 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3637 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3640 /* ??? Fix this to be right for the R8000. */
3641 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3642 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3643 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3645 /* Define if copies to/from condition code registers should be avoided.
3647 This is needed for the MIPS because reload_outcc is not complete;
3648 it needs to handle cases where the source is a general or another
3649 condition code register. */
3650 #define AVOID_CCMODE_COPIES
3652 /* A C expression for the cost of a branch instruction. A value of
3653 1 is the default; other values are interpreted relative to that. */
3655 /* ??? Fix this to be right for the R8000. */
3656 #define BRANCH_COST \
3658 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3661 /* A C statement (sans semicolon) to update the integer variable COST
3662 based on the relationship between INSN that is dependent on
3663 DEP_INSN through the dependence LINK. The default is to make no
3664 adjustment to COST. On the MIPS, ignore the cost of anti- and
3665 output-dependencies. */
3667 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3668 if (REG_NOTE_KIND (LINK) != 0) \
3669 (COST) = 0; /* Anti or output dependence. */
3671 /* If defined, modifies the length assigned to instruction INSN as a
3672 function of the context in which it is used. LENGTH is an lvalue
3673 that contains the initially computed length of the insn and should
3674 be updated with the correct length of the insn. */
3675 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3676 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3679 /* Optionally define this if you have added predicates to
3680 `MACHINE.c'. This macro is called within an initializer of an
3681 array of structures. The first field in the structure is the
3682 name of a predicate and the second field is an array of rtl
3683 codes. For each predicate, list all rtl codes that can be in
3684 expressions matched by the predicate. The list should have a
3685 trailing comma. Here is an example of two entries in the list
3686 for a typical RISC machine:
3688 #define PREDICATE_CODES \
3689 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3690 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3692 Defining this macro does not affect the generated code (however,
3693 incorrect definitions that omit an rtl code that may be matched
3694 by the predicate can cause the compiler to malfunction).
3695 Instead, it allows the table built by `genrecog' to be more
3696 compact and efficient, thus speeding up the compiler. The most
3697 important predicates to include in the list specified by this
3698 macro are thoses used in the most insn patterns. */
3700 #define PREDICATE_CODES \
3701 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3702 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3703 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3704 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3705 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3706 {"small_int", { CONST_INT }}, \
3707 {"large_int", { CONST_INT }}, \
3708 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3709 {"const_float_1_operand", { CONST_DOUBLE }}, \
3710 {"simple_memory_operand", { MEM, SUBREG }}, \
3711 {"equality_op", { EQ, NE }}, \
3712 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3714 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3715 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3716 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3717 SYMBOL_REF, LABEL_REF, SUBREG, \
3719 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3720 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3721 MEM, SIGN_EXTEND }}, \
3722 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3723 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3725 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3727 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3729 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3730 SYMBOL_REF, LABEL_REF, SUBREG, \
3731 REG, SIGN_EXTEND }}, \
3732 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3733 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3734 CONST_DOUBLE, CONST }}, \
3735 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3736 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3738 /* A list of predicates that do special things with modes, and so
3739 should not elicit warnings for VOIDmode match_operand. */
3741 #define SPECIAL_MODE_PREDICATES \
3742 "pc_or_label_operand",
3745 /* If defined, a C statement to be executed just prior to the
3746 output of assembler code for INSN, to modify the extracted
3747 operands so they will be output differently.
3749 Here the argument OPVEC is the vector containing the operands
3750 extracted from INSN, and NOPERANDS is the number of elements of
3751 the vector which contain meaningful data for this insn. The
3752 contents of this vector are what will be used to convert the
3753 insn template into assembler code, so you can change the
3754 assembler output by changing the contents of the vector.
3756 We use it to check if the current insn needs a nop in front of it
3757 because of load delays, and also to update the delay slot
3760 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3761 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3764 /* Control the assembler format that we output. */
3766 /* Output at beginning of assembler file.
3767 If we are optimizing to use the global pointer, create a temporary
3768 file to hold all of the text stuff, and write it out to the end.
3769 This is needed because the MIPS assembler is evidently one pass,
3770 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3771 declaration when the code is processed, it generates a two
3772 instruction sequence. */
3774 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3776 /* Output to assembler file text saying following lines
3777 may contain character constants, extra white space, comments, etc. */
3779 #define ASM_APP_ON " #APP\n"
3781 /* Output to assembler file text saying following lines
3782 no longer contain unusual constructs. */
3784 #define ASM_APP_OFF " #NO_APP\n"
3786 /* How to refer to registers in assembler output.
3787 This sequence is indexed by compiler's hard-register-number (see above).
3789 In order to support the two different conventions for register names,
3790 we use the name of a table set up in mips.c, which is overwritten
3791 if -mrnames is used. */
3793 #define REGISTER_NAMES \
3795 &mips_reg_names[ 0][0], \
3796 &mips_reg_names[ 1][0], \
3797 &mips_reg_names[ 2][0], \
3798 &mips_reg_names[ 3][0], \
3799 &mips_reg_names[ 4][0], \
3800 &mips_reg_names[ 5][0], \
3801 &mips_reg_names[ 6][0], \
3802 &mips_reg_names[ 7][0], \
3803 &mips_reg_names[ 8][0], \
3804 &mips_reg_names[ 9][0], \
3805 &mips_reg_names[10][0], \
3806 &mips_reg_names[11][0], \
3807 &mips_reg_names[12][0], \
3808 &mips_reg_names[13][0], \
3809 &mips_reg_names[14][0], \
3810 &mips_reg_names[15][0], \
3811 &mips_reg_names[16][0], \
3812 &mips_reg_names[17][0], \
3813 &mips_reg_names[18][0], \
3814 &mips_reg_names[19][0], \
3815 &mips_reg_names[20][0], \
3816 &mips_reg_names[21][0], \
3817 &mips_reg_names[22][0], \
3818 &mips_reg_names[23][0], \
3819 &mips_reg_names[24][0], \
3820 &mips_reg_names[25][0], \
3821 &mips_reg_names[26][0], \
3822 &mips_reg_names[27][0], \
3823 &mips_reg_names[28][0], \
3824 &mips_reg_names[29][0], \
3825 &mips_reg_names[30][0], \
3826 &mips_reg_names[31][0], \
3827 &mips_reg_names[32][0], \
3828 &mips_reg_names[33][0], \
3829 &mips_reg_names[34][0], \
3830 &mips_reg_names[35][0], \
3831 &mips_reg_names[36][0], \
3832 &mips_reg_names[37][0], \
3833 &mips_reg_names[38][0], \
3834 &mips_reg_names[39][0], \
3835 &mips_reg_names[40][0], \
3836 &mips_reg_names[41][0], \
3837 &mips_reg_names[42][0], \
3838 &mips_reg_names[43][0], \
3839 &mips_reg_names[44][0], \
3840 &mips_reg_names[45][0], \
3841 &mips_reg_names[46][0], \
3842 &mips_reg_names[47][0], \
3843 &mips_reg_names[48][0], \
3844 &mips_reg_names[49][0], \
3845 &mips_reg_names[50][0], \
3846 &mips_reg_names[51][0], \
3847 &mips_reg_names[52][0], \
3848 &mips_reg_names[53][0], \
3849 &mips_reg_names[54][0], \
3850 &mips_reg_names[55][0], \
3851 &mips_reg_names[56][0], \
3852 &mips_reg_names[57][0], \
3853 &mips_reg_names[58][0], \
3854 &mips_reg_names[59][0], \
3855 &mips_reg_names[60][0], \
3856 &mips_reg_names[61][0], \
3857 &mips_reg_names[62][0], \
3858 &mips_reg_names[63][0], \
3859 &mips_reg_names[64][0], \
3860 &mips_reg_names[65][0], \
3861 &mips_reg_names[66][0], \
3862 &mips_reg_names[67][0], \
3863 &mips_reg_names[68][0], \
3864 &mips_reg_names[69][0], \
3865 &mips_reg_names[70][0], \
3866 &mips_reg_names[71][0], \
3867 &mips_reg_names[72][0], \
3868 &mips_reg_names[73][0], \
3869 &mips_reg_names[74][0], \
3870 &mips_reg_names[75][0], \
3873 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3874 So define this for it. */
3875 #define DEBUG_REGISTER_NAMES \
3877 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3878 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3879 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3880 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3881 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3882 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3883 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3884 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3885 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3886 "$fcc5","$fcc6","$fcc7","$rap" \
3889 /* If defined, a C initializer for an array of structures
3890 containing a name and a register number. This macro defines
3891 additional names for hard registers, thus allowing the `asm'
3892 option in declarations to refer to registers using alternate
3895 We define both names for the integer registers here. */
3897 #define ADDITIONAL_REGISTER_NAMES \
3899 { "$0", 0 + GP_REG_FIRST }, \
3900 { "$1", 1 + GP_REG_FIRST }, \
3901 { "$2", 2 + GP_REG_FIRST }, \
3902 { "$3", 3 + GP_REG_FIRST }, \
3903 { "$4", 4 + GP_REG_FIRST }, \
3904 { "$5", 5 + GP_REG_FIRST }, \
3905 { "$6", 6 + GP_REG_FIRST }, \
3906 { "$7", 7 + GP_REG_FIRST }, \
3907 { "$8", 8 + GP_REG_FIRST }, \
3908 { "$9", 9 + GP_REG_FIRST }, \
3909 { "$10", 10 + GP_REG_FIRST }, \
3910 { "$11", 11 + GP_REG_FIRST }, \
3911 { "$12", 12 + GP_REG_FIRST }, \
3912 { "$13", 13 + GP_REG_FIRST }, \
3913 { "$14", 14 + GP_REG_FIRST }, \
3914 { "$15", 15 + GP_REG_FIRST }, \
3915 { "$16", 16 + GP_REG_FIRST }, \
3916 { "$17", 17 + GP_REG_FIRST }, \
3917 { "$18", 18 + GP_REG_FIRST }, \
3918 { "$19", 19 + GP_REG_FIRST }, \
3919 { "$20", 20 + GP_REG_FIRST }, \
3920 { "$21", 21 + GP_REG_FIRST }, \
3921 { "$22", 22 + GP_REG_FIRST }, \
3922 { "$23", 23 + GP_REG_FIRST }, \
3923 { "$24", 24 + GP_REG_FIRST }, \
3924 { "$25", 25 + GP_REG_FIRST }, \
3925 { "$26", 26 + GP_REG_FIRST }, \
3926 { "$27", 27 + GP_REG_FIRST }, \
3927 { "$28", 28 + GP_REG_FIRST }, \
3928 { "$29", 29 + GP_REG_FIRST }, \
3929 { "$30", 30 + GP_REG_FIRST }, \
3930 { "$31", 31 + GP_REG_FIRST }, \
3931 { "$sp", 29 + GP_REG_FIRST }, \
3932 { "$fp", 30 + GP_REG_FIRST }, \
3933 { "at", 1 + GP_REG_FIRST }, \
3934 { "v0", 2 + GP_REG_FIRST }, \
3935 { "v1", 3 + GP_REG_FIRST }, \
3936 { "a0", 4 + GP_REG_FIRST }, \
3937 { "a1", 5 + GP_REG_FIRST }, \
3938 { "a2", 6 + GP_REG_FIRST }, \
3939 { "a3", 7 + GP_REG_FIRST }, \
3940 { "t0", 8 + GP_REG_FIRST }, \
3941 { "t1", 9 + GP_REG_FIRST }, \
3942 { "t2", 10 + GP_REG_FIRST }, \
3943 { "t3", 11 + GP_REG_FIRST }, \
3944 { "t4", 12 + GP_REG_FIRST }, \
3945 { "t5", 13 + GP_REG_FIRST }, \
3946 { "t6", 14 + GP_REG_FIRST }, \
3947 { "t7", 15 + GP_REG_FIRST }, \
3948 { "s0", 16 + GP_REG_FIRST }, \
3949 { "s1", 17 + GP_REG_FIRST }, \
3950 { "s2", 18 + GP_REG_FIRST }, \
3951 { "s3", 19 + GP_REG_FIRST }, \
3952 { "s4", 20 + GP_REG_FIRST }, \
3953 { "s5", 21 + GP_REG_FIRST }, \
3954 { "s6", 22 + GP_REG_FIRST }, \
3955 { "s7", 23 + GP_REG_FIRST }, \
3956 { "t8", 24 + GP_REG_FIRST }, \
3957 { "t9", 25 + GP_REG_FIRST }, \
3958 { "k0", 26 + GP_REG_FIRST }, \
3959 { "k1", 27 + GP_REG_FIRST }, \
3960 { "gp", 28 + GP_REG_FIRST }, \
3961 { "sp", 29 + GP_REG_FIRST }, \
3962 { "fp", 30 + GP_REG_FIRST }, \
3963 { "ra", 31 + GP_REG_FIRST }, \
3964 { "$sp", 29 + GP_REG_FIRST }, \
3965 { "$fp", 30 + GP_REG_FIRST } \
3968 /* Define results of standard character escape sequences. */
3969 #define TARGET_BELL 007
3970 #define TARGET_BS 010
3971 #define TARGET_TAB 011
3972 #define TARGET_NEWLINE 012
3973 #define TARGET_VT 013
3974 #define TARGET_FF 014
3975 #define TARGET_CR 015
3977 /* A C compound statement to output to stdio stream STREAM the
3978 assembler syntax for an instruction operand X. X is an RTL
3981 CODE is a value that can be used to specify one of several ways
3982 of printing the operand. It is used when identical operands
3983 must be printed differently depending on the context. CODE
3984 comes from the `%' specification that was used to request
3985 printing of the operand. If the specification was just `%DIGIT'
3986 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3987 is the ASCII code for LTR.
3989 If X is a register, this macro should print the register's name.
3990 The names can be found in an array `reg_names' whose type is
3991 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3993 When the machine description has a specification `%PUNCT' (a `%'
3994 followed by a punctuation character), this macro is called with
3995 a null pointer for X and the punctuation character for CODE.
3997 See mips.c for the MIPS specific codes. */
3999 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4001 /* A C expression which evaluates to true if CODE is a valid
4002 punctuation character for use in the `PRINT_OPERAND' macro. If
4003 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4004 punctuation characters (except for the standard one, `%') are
4005 used in this way. */
4007 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4009 /* A C compound statement to output to stdio stream STREAM the
4010 assembler syntax for an instruction operand that is a memory
4011 reference whose address is ADDR. ADDR is an RTL expression.
4013 On some machines, the syntax for a symbolic address depends on
4014 the section that the address refers to. On these machines,
4015 define the macro `ENCODE_SECTION_INFO' to store the information
4016 into the `symbol_ref', and then check for it here. */
4018 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4021 /* A C statement, to be executed after all slot-filler instructions
4022 have been output. If necessary, call `dbr_sequence_length' to
4023 determine the number of slots filled in a sequence (zero if not
4024 currently outputting a sequence), to decide how many no-ops to
4025 output, or whatever.
4027 Don't define this macro if it has nothing to do, but it is
4028 helpful in reading assembly output if the extent of the delay
4029 sequence is made explicit (e.g. with white space).
4031 Note that output routines for instructions with delay slots must
4032 be prepared to deal with not being output as part of a sequence
4033 (i.e. when the scheduling pass is not run, or when no slot
4034 fillers could be found.) The variable `final_sequence' is null
4035 when not processing a sequence, otherwise it contains the
4036 `sequence' rtx being output. */
4038 #define DBR_OUTPUT_SEQEND(STREAM) \
4041 if (set_nomacro > 0 && --set_nomacro == 0) \
4042 fputs ("\t.set\tmacro\n", STREAM); \
4044 if (set_noreorder > 0 && --set_noreorder == 0) \
4045 fputs ("\t.set\treorder\n", STREAM); \
4047 dslots_jump_filled++; \
4048 fputs ("\n", STREAM); \
4053 /* How to tell the debugger about changes of source files. Note, the
4054 mips ECOFF format cannot deal with changes of files inside of
4055 functions, which means the output of parser generators like bison
4056 is generally not debuggable without using the -l switch. Lose,
4057 lose, lose. Silicon graphics seems to want all .file's hardwired
4060 #ifndef SET_FILE_NUMBER
4061 #define SET_FILE_NUMBER() ++num_source_filenames
4064 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4065 mips_output_filename (STREAM, NAME)
4067 /* This is defined so that it can be overridden in iris6.h. */
4068 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4071 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4072 output_quoted_string (STREAM, NAME); \
4073 fputs ("\n", STREAM); \
4077 /* This is how to output a note the debugger telling it the line number
4078 to which the following sequence of instructions corresponds.
4079 Silicon graphics puts a label after each .loc. */
4081 #ifndef LABEL_AFTER_LOC
4082 #define LABEL_AFTER_LOC(STREAM)
4085 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4086 mips_output_lineno (STREAM, LINE)
4088 /* The MIPS implementation uses some labels for its own purpose. The
4089 following lists what labels are created, and are all formed by the
4090 pattern $L[a-z].*. The machine independent portion of GCC creates
4091 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4093 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4094 $Lb[0-9]+ Begin blocks for MIPS debug support
4095 $Lc[0-9]+ Label for use in s<xx> operation.
4096 $Le[0-9]+ End blocks for MIPS debug support
4097 $Lp\..+ Half-pic labels. */
4099 /* This is how to output the definition of a user-level label named NAME,
4100 such as the label on a static function or variable NAME.
4102 If we are optimizing the gp, remember that this label has been put
4103 out, so we know not to emit an .extern for it in mips_asm_file_end.
4104 We use one of the common bits in the IDENTIFIER tree node for this,
4105 since those bits seem to be unused, and we don't have any method
4106 of getting the decl nodes from the name. */
4108 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4110 assemble_name (STREAM, NAME); \
4111 fputs (":\n", STREAM); \
4115 /* A C statement (sans semicolon) to output to the stdio stream
4116 STREAM any text necessary for declaring the name NAME of an
4117 initialized variable which is being defined. This macro must
4118 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4119 The argument DECL is the `VAR_DECL' tree node representing the
4122 If this macro is not defined, then the variable name is defined
4123 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4125 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4128 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4129 HALF_PIC_DECLARE (NAME); \
4134 /* This is how to output a command to make the user-level label named NAME
4135 defined for reference from other files. */
4137 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4139 fputs ("\t.globl\t", STREAM); \
4140 assemble_name (STREAM, NAME); \
4141 fputs ("\n", STREAM); \
4144 /* This says how to define a global common symbol. */
4146 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4148 /* If the target wants uninitialized const declarations in \
4149 .rdata then don't put them in .comm */ \
4150 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4151 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4152 && (DECL_INITIAL (DECL) == 0 \
4153 || DECL_INITIAL (DECL) == error_mark_node)) \
4155 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4156 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4158 READONLY_DATA_SECTION (); \
4159 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4160 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4164 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4169 /* This says how to define a local common symbol (ie, not visible to
4172 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4173 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4176 /* This says how to output an external. It would be possible not to
4177 output anything and let undefined symbol become external. However
4178 the assembler uses length information on externals to allocate in
4179 data/sdata bss/sbss, thereby saving exec time. */
4181 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4182 mips_output_external(STREAM,DECL,NAME)
4184 /* This says what to print at the end of the assembly file */
4185 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4188 /* This is how to declare a function name. The actual work of
4189 emitting the label is moved to function_prologue, so that we can
4190 get the line number correctly emitted before the .ent directive,
4191 and after any .file directives.
4193 Also, switch files if we are optimizing the global pointer. */
4195 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4197 extern FILE *asm_out_text_file; \
4198 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4200 STREAM = asm_out_text_file; \
4201 /* ??? text_section gets called too soon. If the previous \
4202 function is in a special section and we're not, we have \
4203 to switch back to the text section. We can't call \
4204 text_section again as gcc thinks we're already there. */ \
4205 /* ??? See varasm.c. There are other things that get output \
4206 too early, like alignment (before we've switched STREAM). */ \
4207 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4208 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4211 HALF_PIC_DECLARE (NAME); \
4214 /* This is how to output an internal numbered label where
4215 PREFIX is the class of label and NUM is the number within the class. */
4217 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4218 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4220 /* This is how to store into the string LABEL
4221 the symbol_ref name of an internal numbered label where
4222 PREFIX is the class of label and NUM is the number within the class.
4223 This is suitable for output with `assemble_name'. */
4225 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4226 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4228 /* This is how to output an assembler line defining a `double' constant. */
4230 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4231 mips_output_double (STREAM, VALUE)
4234 /* This is how to output an assembler line defining a `float' constant. */
4236 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4237 mips_output_float (STREAM, VALUE)
4240 /* This is how to output an assembler line defining an `int' constant. */
4242 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4244 fprintf (STREAM, "\t.word\t"); \
4245 output_addr_const (STREAM, (VALUE)); \
4246 fprintf (STREAM, "\n"); \
4249 /* Likewise for 64 bit, `char' and `short' constants.
4251 FIXME: operand_subword can't handle some complex constant expressions
4252 that output_addr_const can (for example it does not call
4253 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4254 rely on that to avoid operand_subword for most of the cases where this
4255 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4256 or the same case with the type of 'i' changed to long long.
4260 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4262 if (TARGET_64BIT || TARGET_GAS) \
4264 fprintf (STREAM, "\t.dword\t"); \
4265 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4266 /* We can't use 'X' for negative numbers, because then we won't \
4267 get the right value for the upper 32 bits. */ \
4268 output_addr_const (STREAM, VALUE); \
4270 /* We must use 'X', because otherwise LONG_MIN will print as \
4271 a number that the Irix 6 assembler won't accept. */ \
4272 print_operand (STREAM, VALUE, 'X'); \
4273 fprintf (STREAM, "\n"); \
4277 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4278 UNITS_PER_WORD, 1); \
4279 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4280 UNITS_PER_WORD, 1); \
4284 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4286 fprintf (STREAM, "\t.half\t"); \
4287 output_addr_const (STREAM, (VALUE)); \
4288 fprintf (STREAM, "\n"); \
4291 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4293 fprintf (STREAM, "\t.byte\t"); \
4294 output_addr_const (STREAM, (VALUE)); \
4295 fprintf (STREAM, "\n"); \
4298 /* This is how to output an assembler line for a numeric constant byte. */
4300 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4301 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4303 /* This is how to output an element of a case-vector that is absolute. */
4305 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4306 fprintf (STREAM, "\t%s\t%sL%d\n", \
4307 Pmode == DImode ? ".dword" : ".word", \
4308 LOCAL_LABEL_PREFIX, \
4311 /* This is how to output an element of a case-vector that is relative.
4312 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4313 TARGET_EMBEDDED_PIC). */
4315 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4317 if (TARGET_MIPS16) \
4318 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4319 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4320 else if (TARGET_EMBEDDED_PIC) \
4321 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4322 Pmode == DImode ? ".dword" : ".word", \
4323 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4324 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4325 fprintf (STREAM, "\t%s\t%sL%d\n", \
4326 Pmode == DImode ? ".gpdword" : ".gpword", \
4327 LOCAL_LABEL_PREFIX, VALUE); \
4329 fprintf (STREAM, "\t%s\t%sL%d\n", \
4330 Pmode == DImode ? ".dword" : ".word", \
4331 LOCAL_LABEL_PREFIX, VALUE); \
4334 /* When generating embedded PIC or mips16 code we want to put the jump
4335 table in the .text section. In all other cases, we want to put the
4336 jump table in the .rdata section. Unfortunately, we can't use
4337 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4338 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4339 section if appropriate. */
4340 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4342 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4343 function_section (current_function_decl); \
4344 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4347 /* This is how to output an assembler line
4348 that says to advance the location counter
4349 to a multiple of 2**LOG bytes. */
4351 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4352 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4354 /* This is how to output an assembler line to advance the location
4355 counter by SIZE bytes. */
4357 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4358 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4360 /* This is how to output a string. */
4361 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4363 register int i, c, len = (LEN), cur_pos = 17; \
4364 register const unsigned char *string = \
4365 (const unsigned char *)(STRING); \
4366 fprintf ((STREAM), "\t.ascii\t\""); \
4367 for (i = 0; i < len; i++) \
4369 register int c = string[i]; \
4375 putc ('\\', (STREAM)); \
4376 putc (c, (STREAM)); \
4380 case TARGET_NEWLINE: \
4381 fputs ("\\n", (STREAM)); \
4383 && (((c = string[i+1]) >= '\040' && c <= '~') \
4384 || c == TARGET_TAB)) \
4385 cur_pos = 32767; /* break right here */ \
4391 fputs ("\\t", (STREAM)); \
4396 fputs ("\\f", (STREAM)); \
4401 fputs ("\\b", (STREAM)); \
4406 fputs ("\\r", (STREAM)); \
4411 if (c >= ' ' && c < 0177) \
4413 putc (c, (STREAM)); \
4418 fprintf ((STREAM), "\\%03o", c); \
4423 if (cur_pos > 72 && i+1 < len) \
4426 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4429 fprintf ((STREAM), "\"\n"); \
4432 /* Handle certain cpp directives used in header files on sysV. */
4433 #define SCCS_DIRECTIVE
4435 /* Output #ident as a in the read-only data section. */
4436 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4438 const char *p = STRING; \
4439 int size = strlen (p) + 1; \
4441 assemble_string (p, size); \
4444 /* Default to -G 8 */
4445 #ifndef MIPS_DEFAULT_GVALUE
4446 #define MIPS_DEFAULT_GVALUE 8
4449 /* Define the strings to put out for each section in the object file. */
4450 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4451 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4452 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4453 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4454 #define READONLY_DATA_SECTION rdata_section
4455 #define SMALL_DATA_SECTION sdata_section
4457 /* What other sections we support other than the normal .data/.text. */
4459 #define EXTRA_SECTIONS in_sdata, in_rdata
4461 /* Define the additional functions to select our additional sections. */
4463 /* on the MIPS it is not a good idea to put constants in the text
4464 section, since this defeats the sdata/data mechanism. This is
4465 especially true when -O is used. In this case an effort is made to
4466 address with faster (gp) register relative addressing, which can
4467 only get at sdata and sbss items (there is no stext !!) However,
4468 if the constant is too large for sdata, and it's readonly, it
4469 will go into the .rdata section. */
4471 #define EXTRA_SECTION_FUNCTIONS \
4475 if (in_section != in_sdata) \
4477 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4478 in_section = in_sdata; \
4485 if (in_section != in_rdata) \
4487 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4488 in_section = in_rdata; \
4492 /* Given a decl node or constant node, choose the section to output it in
4493 and select that section. */
4495 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4497 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4500 /* Store in OUTPUT a string (made with alloca) containing
4501 an assembler-name for a local static variable named NAME.
4502 LABELNO is an integer which is different for each call. */
4504 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4505 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4506 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4508 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4511 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4512 TARGET_64BIT ? "dsubu" : "subu", \
4513 reg_names[STACK_POINTER_REGNUM], \
4514 reg_names[STACK_POINTER_REGNUM], \
4515 TARGET_64BIT ? "sd" : "sw", \
4517 reg_names[STACK_POINTER_REGNUM]); \
4521 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4524 if (! set_noreorder) \
4525 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4527 dslots_load_total++; \
4528 dslots_load_filled++; \
4529 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4530 TARGET_64BIT ? "ld" : "lw", \
4532 reg_names[STACK_POINTER_REGNUM], \
4533 TARGET_64BIT ? "daddu" : "addu", \
4534 reg_names[STACK_POINTER_REGNUM], \
4535 reg_names[STACK_POINTER_REGNUM]); \
4537 if (! set_noreorder) \
4538 fprintf (STREAM, "\t.set\treorder\n"); \
4542 /* Define the parentheses used to group arithmetic operations
4543 in assembler code. */
4545 #define ASM_OPEN_PAREN "("
4546 #define ASM_CLOSE_PAREN ")"
4548 /* How to start an assembler comment.
4549 The leading space is important (the mips native assembler requires it). */
4550 #ifndef ASM_COMMENT_START
4551 #define ASM_COMMENT_START " #"
4555 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4556 and mips-tdump.c to print them out.
4558 These must match the corresponding definitions in gdb/mipsread.c.
4559 Unfortunately, gcc and gdb do not currently share any directories. */
4561 #define CODE_MASK 0x8F300
4562 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4563 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4564 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4567 /* Default definitions for size_t and ptrdiff_t. */
4570 #define NO_BUILTIN_SIZE_TYPE
4571 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4574 #ifndef PTRDIFF_TYPE
4575 #define NO_BUILTIN_PTRDIFF_TYPE
4576 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4579 /* See mips_expand_prologue's use of loadgp for when this should be
4582 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4583 && mips_abi != ABI_32 \
4584 && mips_abi != ABI_O64)
4586 /* In mips16 mode, we need to look through the function to check for
4587 PC relative loads that are out of range. */
4588 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4590 /* We need to use a special set of functions to handle hard floating
4591 point code in mips16 mode. */
4593 #ifndef INIT_SUBTARGET_OPTABS
4594 #define INIT_SUBTARGET_OPTABS
4597 #define INIT_TARGET_OPTABS \
4600 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4601 INIT_SUBTARGET_OPTABS; \
4604 add_optab->handlers[(int) SFmode].libfunc = \
4605 init_one_libfunc ("__mips16_addsf3"); \
4606 sub_optab->handlers[(int) SFmode].libfunc = \
4607 init_one_libfunc ("__mips16_subsf3"); \
4608 smul_optab->handlers[(int) SFmode].libfunc = \
4609 init_one_libfunc ("__mips16_mulsf3"); \
4610 flodiv_optab->handlers[(int) SFmode].libfunc = \
4611 init_one_libfunc ("__mips16_divsf3"); \
4613 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4614 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4615 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4616 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4617 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4618 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4620 floatsisf_libfunc = \
4621 init_one_libfunc ("__mips16_floatsisf"); \
4623 init_one_libfunc ("__mips16_fixsfsi"); \
4625 if (TARGET_DOUBLE_FLOAT) \
4627 add_optab->handlers[(int) DFmode].libfunc = \
4628 init_one_libfunc ("__mips16_adddf3"); \
4629 sub_optab->handlers[(int) DFmode].libfunc = \
4630 init_one_libfunc ("__mips16_subdf3"); \
4631 smul_optab->handlers[(int) DFmode].libfunc = \
4632 init_one_libfunc ("__mips16_muldf3"); \
4633 flodiv_optab->handlers[(int) DFmode].libfunc = \
4634 init_one_libfunc ("__mips16_divdf3"); \
4636 extendsfdf2_libfunc = \
4637 init_one_libfunc ("__mips16_extendsfdf2"); \
4638 truncdfsf2_libfunc = \
4639 init_one_libfunc ("__mips16_truncdfsf2"); \
4642 init_one_libfunc ("__mips16_eqdf2"); \
4644 init_one_libfunc ("__mips16_nedf2"); \
4646 init_one_libfunc ("__mips16_gtdf2"); \
4648 init_one_libfunc ("__mips16_gedf2"); \
4650 init_one_libfunc ("__mips16_ltdf2"); \
4652 init_one_libfunc ("__mips16_ledf2"); \
4654 floatsidf_libfunc = \
4655 init_one_libfunc ("__mips16_floatsidf"); \
4657 init_one_libfunc ("__mips16_fixdfsi"); \
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