1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
83 /* Recast the cpu class to be the cpu attribute. */
84 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
86 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
87 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
88 to work on a 64 bit machine. */
95 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
96 which is not the same as the above EABI (defined by Cygnus,
97 Greenhills, and Toshiba?). MEABI is not yet complete or published,
98 but at this point it looks like N32 as far as calling conventions go,
99 but allows for either 32 or 64 bit registers.
101 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
102 EABI the legacy EABI. In the end we may end up calling both ABI's
103 EABI but give them different version numbers, but for now I'm going
104 with different names. */
107 /* Whether to emit abicalls code sequences or not. */
109 enum mips_abicalls_type {
114 /* Recast the abicalls class to be the abicalls attribute. */
115 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
117 /* Which type of block move to do (whether or not the last store is
118 split out so it can fill a branch delay slot). */
120 enum block_move_type {
121 BLOCK_MOVE_NORMAL, /* generate complete block move */
122 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
123 BLOCK_MOVE_LAST /* generate just the last store */
126 /* Information about one recognized processor. Defined here for the
127 benefit of TARGET_CPU_CPP_BUILTINS. */
128 struct mips_cpu_info {
129 /* The 'canonical' name of the processor as far as GCC is concerned.
130 It's typically a manufacturer's prefix followed by a numerical
131 designation. It should be lower case. */
134 /* The internal processor number that most closely matches this
135 entry. Several processors can have the same value, if there's no
136 difference between them from GCC's point of view. */
137 enum processor_type cpu;
139 /* The ISA level that the processor implements. */
143 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
144 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
145 extern const char *current_function_file; /* filename current function is in */
146 extern int num_source_filenames; /* current .file # */
147 extern int inside_function; /* != 0 if inside of a function */
148 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
149 extern int file_in_function_warning; /* warning given about .file in func */
150 extern int sdb_label_count; /* block start/end next label # */
151 extern int sdb_begin_function_line; /* Starting Line of current function */
152 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
153 extern int g_switch_value; /* value of the -G xx switch */
154 extern int g_switch_set; /* whether -G xx was passed. */
155 extern int sym_lineno; /* sgi next label # for each stmt */
156 extern int set_noreorder; /* # of nested .set noreorder's */
157 extern int set_nomacro; /* # of nested .set nomacro's */
158 extern int set_noat; /* # of nested .set noat's */
159 extern int set_volatile; /* # of nested .set volatile's */
160 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
161 extern int mips_dbx_regno[]; /* Map register # to debug register # */
162 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
163 extern enum cmp_type branch_type; /* what type of branch to use */
164 extern enum processor_type mips_arch; /* which cpu to codegen for */
165 extern enum processor_type mips_tune; /* which cpu to schedule for */
166 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
167 extern int mips_isa; /* architectural level */
168 extern int mips16; /* whether generating mips16 code */
169 extern int mips16_hard_float; /* mips16 without -msoft-float */
170 extern int mips_entry; /* generate entry/exit for mips16 */
171 extern const char *mips_arch_string; /* for -march=<xxx> */
172 extern const char *mips_tune_string; /* for -mtune=<xxx> */
173 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
174 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
175 extern const char *mips_entry_string; /* for -mentry */
176 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
177 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
178 extern int mips_split_addresses; /* perform high/lo_sum support */
179 extern int dslots_load_total; /* total # load related delay slots */
180 extern int dslots_load_filled; /* # filled load delay slots */
181 extern int dslots_jump_total; /* total # jump related delay slots */
182 extern int dslots_jump_filled; /* # filled jump delay slots */
183 extern int dslots_number_nops; /* # of nops needed by previous insn */
184 extern int num_refs[3]; /* # 1/2/3 word references */
185 extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
186 extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
187 extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
188 extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
189 extern int mips_string_length; /* length of strings for mips16 */
190 extern const struct mips_cpu_info mips_cpu_info_table[];
191 extern const struct mips_cpu_info *mips_arch_info;
192 extern const struct mips_cpu_info *mips_tune_info;
194 /* Functions to change what output section we are using. */
195 extern void sdata_section PARAMS ((void));
196 extern void sbss_section PARAMS ((void));
198 /* Macros to silence warnings about numbers being signed in traditional
199 C and unsigned in ISO C when compiled on 32-bit hosts. */
201 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
202 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
203 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
206 /* Run-time compilation parameters selecting different hardware subsets. */
208 /* Macros used in the machine description to test the flags. */
210 /* Bits for real switches */
211 #define MASK_INT64 0x00000001 /* ints are 64 bits */
212 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
213 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
214 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
215 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
216 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
217 #define MASK_STATS 0x00000040 /* print statistics to stderr */
218 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
219 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
220 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
221 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
222 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
223 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
224 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
225 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
226 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
227 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
228 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
229 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
230 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
231 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
232 #define MASK_NO_CHECK_ZERO_DIV \
233 0x00200000 /* divide by zero checking */
234 #define MASK_CHECK_RANGE_DIV \
235 0x00400000 /* divide result range checking */
236 #define MASK_UNINIT_CONST_IN_RODATA \
237 0x00800000 /* Store uninitialized
239 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
240 multiply-add operations. */
241 #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
244 /* Debug switches, not documented */
245 #define MASK_DEBUG 0 /* unused */
246 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
247 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
248 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
249 #define MASK_DEBUG_D 0 /* don't do define_split's */
250 #define MASK_DEBUG_E 0 /* function_arg debug */
251 #define MASK_DEBUG_F 0 /* ??? */
252 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
253 #define MASK_DEBUG_I 0 /* unused */
255 /* Dummy switches used only in specs */
256 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
258 /* r4000 64 bit sizes */
259 #define TARGET_INT64 (target_flags & MASK_INT64)
260 #define TARGET_LONG64 (target_flags & MASK_LONG64)
261 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
262 #define TARGET_64BIT (target_flags & MASK_64BIT)
264 /* Mips vs. GNU linker */
265 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
267 /* Mips vs. GNU assembler */
268 #define TARGET_GAS (target_flags & MASK_GAS)
269 #define TARGET_MIPS_AS (!TARGET_GAS)
272 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
273 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
274 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
275 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
276 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
277 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
278 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
279 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
280 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
282 /* Reg. Naming in .s ($21 vs. $a0) */
283 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
285 /* Optimize for Sdata/Sbss */
286 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
288 /* print program statistics */
289 #define TARGET_STATS (target_flags & MASK_STATS)
291 /* call memcpy instead of inline code */
292 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
294 /* .abicalls, etc from Pyramid V.4 */
295 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
297 /* software floating point */
298 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
299 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
301 /* always call through a register */
302 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
304 /* generate embedded PIC code;
306 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
308 /* for embedded systems, optimize for
309 reduced RAM space instead of for
311 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
313 /* always store uninitialized const
314 variables in rodata, requires
315 TARGET_EMBEDDED_DATA. */
316 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
318 /* generate big endian code. */
319 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
321 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
322 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
324 #define TARGET_MAD (target_flags & MASK_MAD)
326 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
328 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
330 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
331 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
333 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
335 /* This is true if we must enable the assembly language file switching
338 #define TARGET_FILE_SWITCHING \
339 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
341 /* We must disable the function end stabs when doing the file switching trick,
342 because the Lscope stabs end up in the wrong place, making it impossible
343 to debug the resulting code. */
344 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
346 /* Generate mips16 code */
347 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
349 /* Generic ISA defines. */
350 #define ISA_MIPS1 (mips_isa == 1)
351 #define ISA_MIPS2 (mips_isa == 2)
352 #define ISA_MIPS3 (mips_isa == 3)
353 #define ISA_MIPS4 (mips_isa == 4)
354 #define ISA_MIPS32 (mips_isa == 32)
355 #define ISA_MIPS32R2 (mips_isa == 33)
356 #define ISA_MIPS64 (mips_isa == 64)
358 /* Architecture target defines. */
359 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
360 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
361 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
362 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
363 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
364 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
365 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
366 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
367 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
368 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
369 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
371 /* Scheduling target defines. */
372 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
373 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
374 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
375 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
376 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
377 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
378 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
379 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
380 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
382 /* Define preprocessor macros for the -march and -mtune options.
383 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
384 processor. If INFO's canonical name is "foo", define PREFIX to
385 be "foo", and define an additional macro PREFIX_FOO. */
386 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
391 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
392 for (p = macro; *p != 0; p++) \
395 builtin_define (macro); \
396 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
401 /* Target CPU builtins. */
402 #define TARGET_CPU_CPP_BUILTINS() \
405 builtin_assert ("cpu=mips"); \
406 builtin_define ("__mips__"); \
407 builtin_define ("_mips"); \
409 /* We do this here because __mips is defined below \
410 and so we can't use builtin_define_std. */ \
412 builtin_define ("mips"); \
414 /* Treat _R3000 and _R4000 like register-size defines, \
415 which is how they've historically been used. */ \
418 builtin_define ("__mips64"); \
419 builtin_define_std ("R4000"); \
420 builtin_define ("_R4000"); \
424 builtin_define_std ("R3000"); \
425 builtin_define ("_R3000"); \
427 if (TARGET_FLOAT64) \
428 builtin_define ("__mips_fpr=64"); \
430 builtin_define ("__mips_fpr=32"); \
433 builtin_define ("__mips16"); \
435 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
436 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
440 builtin_define ("__mips=1"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
443 else if (ISA_MIPS2) \
445 builtin_define ("__mips=2"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
448 else if (ISA_MIPS3) \
450 builtin_define ("__mips=3"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
453 else if (ISA_MIPS4) \
455 builtin_define ("__mips=4"); \
456 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
458 else if (ISA_MIPS32) \
460 builtin_define ("__mips=32"); \
461 builtin_define ("__mips_isa_rev=1"); \
462 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
464 else if (ISA_MIPS32R2) \
466 builtin_define ("__mips=32"); \
467 builtin_define ("__mips_isa_rev=2"); \
468 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
470 else if (ISA_MIPS64) \
472 builtin_define ("__mips=64"); \
473 builtin_define ("__mips_isa_rev=1"); \
474 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
477 if (TARGET_HARD_FLOAT) \
478 builtin_define ("__mips_hard_float"); \
479 else if (TARGET_SOFT_FLOAT) \
480 builtin_define ("__mips_soft_float"); \
482 if (TARGET_SINGLE_FLOAT) \
483 builtin_define ("__mips_single_float"); \
485 if (TARGET_BIG_ENDIAN) \
487 builtin_define_std ("MIPSEB"); \
488 builtin_define ("_MIPSEB"); \
492 builtin_define_std ("MIPSEL"); \
493 builtin_define ("_MIPSEL"); \
496 /* Macros dependent on the C dialect. */ \
497 if (preprocessing_asm_p ()) \
499 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
500 builtin_define ("_LANGUAGE_ASSEMBLY"); \
502 else if (c_language == clk_c) \
504 builtin_define_std ("LANGUAGE_C"); \
505 builtin_define ("_LANGUAGE_C"); \
507 else if (c_language == clk_cplusplus) \
509 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
510 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
511 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
515 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
516 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
517 /* Bizzare, but needed at least for Irix. */ \
518 builtin_define_std ("LANGUAGE_C"); \
519 builtin_define ("_LANGUAGE_C"); \
522 if (mips_abi == ABI_EABI) \
523 builtin_define ("__mips_eabi"); \
529 /* Macro to define tables used to set the flags.
530 This is a list in braces of pairs in braces,
531 each pair being { "NAME", VALUE }
532 where VALUE is the bits to set or minus the bits to clear.
533 An empty string NAME is used to identify the default VALUE. */
535 #define TARGET_SWITCHES \
538 N_("No default crt0.o") }, \
539 {"int64", MASK_INT64 | MASK_LONG64, \
540 N_("Use 64-bit int type")}, \
541 {"long64", MASK_LONG64, \
542 N_("Use 64-bit long type")}, \
543 {"long32", -(MASK_LONG64 | MASK_INT64), \
544 N_("Use 32-bit long type")}, \
545 {"split-addresses", MASK_SPLIT_ADDR, \
546 N_("Optimize lui/addiu address loads")}, \
547 {"no-split-addresses", -MASK_SPLIT_ADDR, \
548 N_("Don't optimize lui/addiu address loads")}, \
549 {"mips-as", -MASK_GAS, \
550 N_("Use MIPS as")}, \
553 {"rnames", MASK_NAME_REGS, \
554 N_("Use symbolic register names")}, \
555 {"no-rnames", -MASK_NAME_REGS, \
556 N_("Don't use symbolic register names")}, \
557 {"gpOPT", MASK_GPOPT, \
558 N_("Use GP relative sdata/sbss sections")}, \
559 {"gpopt", MASK_GPOPT, \
560 N_("Use GP relative sdata/sbss sections")}, \
561 {"no-gpOPT", -MASK_GPOPT, \
562 N_("Don't use GP relative sdata/sbss sections")}, \
563 {"no-gpopt", -MASK_GPOPT, \
564 N_("Don't use GP relative sdata/sbss sections")}, \
565 {"stats", MASK_STATS, \
566 N_("Output compiler statistics")}, \
567 {"no-stats", -MASK_STATS, \
568 N_("Don't output compiler statistics")}, \
569 {"memcpy", MASK_MEMCPY, \
570 N_("Don't optimize block moves")}, \
571 {"no-memcpy", -MASK_MEMCPY, \
572 N_("Optimize block moves")}, \
573 {"mips-tfile", MASK_MIPS_TFILE, \
574 N_("Use mips-tfile asm postpass")}, \
575 {"no-mips-tfile", -MASK_MIPS_TFILE, \
576 N_("Don't use mips-tfile asm postpass")}, \
577 {"soft-float", MASK_SOFT_FLOAT, \
578 N_("Use software floating point")}, \
579 {"hard-float", -MASK_SOFT_FLOAT, \
580 N_("Use hardware floating point")}, \
581 {"fp64", MASK_FLOAT64, \
582 N_("Use 64-bit FP registers")}, \
583 {"fp32", -MASK_FLOAT64, \
584 N_("Use 32-bit FP registers")}, \
585 {"gp64", MASK_64BIT, \
586 N_("Use 64-bit general registers")}, \
587 {"gp32", -MASK_64BIT, \
588 N_("Use 32-bit general registers")}, \
589 {"abicalls", MASK_ABICALLS, \
590 N_("Use Irix PIC")}, \
591 {"no-abicalls", -MASK_ABICALLS, \
592 N_("Don't use Irix PIC")}, \
593 {"long-calls", MASK_LONG_CALLS, \
594 N_("Use indirect calls")}, \
595 {"no-long-calls", -MASK_LONG_CALLS, \
596 N_("Don't use indirect calls")}, \
597 {"embedded-pic", MASK_EMBEDDED_PIC, \
598 N_("Use embedded PIC")}, \
599 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
600 N_("Don't use embedded PIC")}, \
601 {"embedded-data", MASK_EMBEDDED_DATA, \
602 N_("Use ROM instead of RAM")}, \
603 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
604 N_("Don't use ROM instead of RAM")}, \
605 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
606 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
607 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
608 N_("Don't put uninitialized constants in ROM")}, \
609 {"eb", MASK_BIG_ENDIAN, \
610 N_("Use big-endian byte order")}, \
611 {"el", -MASK_BIG_ENDIAN, \
612 N_("Use little-endian byte order")}, \
613 {"single-float", MASK_SINGLE_FLOAT, \
614 N_("Use single (32-bit) FP only")}, \
615 {"double-float", -MASK_SINGLE_FLOAT, \
616 N_("Don't use single (32-bit) FP only")}, \
618 N_("Use multiply accumulate")}, \
619 {"no-mad", -MASK_MAD, \
620 N_("Don't use multiply accumulate")}, \
621 {"no-fused-madd", MASK_NO_FUSED_MADD, \
622 N_("Don't generate fused multiply/add instructions")}, \
623 {"fused-madd", -MASK_NO_FUSED_MADD, \
624 N_("Generate fused multiply/add instructions")}, \
625 {"fix4300", MASK_4300_MUL_FIX, \
626 N_("Work around early 4300 hardware bug")}, \
627 {"no-fix4300", -MASK_4300_MUL_FIX, \
628 N_("Don't work around early 4300 hardware bug")}, \
629 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
630 N_("Trap on integer divide by zero")}, \
631 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
632 N_("Don't trap on integer divide by zero")}, \
633 {"check-range-division",MASK_CHECK_RANGE_DIV, \
634 N_("Trap on integer divide overflow")}, \
635 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
636 N_("Don't trap on integer divide overflow")}, \
637 { "branch-likely", MASK_BRANCHLIKELY, \
638 N_("Use Branch Likely instructions, overriding default for arch")}, \
639 { "no-branch-likely", -MASK_BRANCHLIKELY, \
640 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
641 {"debug", MASK_DEBUG, \
643 {"debuga", MASK_DEBUG_A, \
645 {"debugb", MASK_DEBUG_B, \
647 {"debugc", MASK_DEBUG_C, \
649 {"debugd", MASK_DEBUG_D, \
651 {"debuge", MASK_DEBUG_E, \
653 {"debugf", MASK_DEBUG_F, \
655 {"debugg", MASK_DEBUG_G, \
657 {"debugi", MASK_DEBUG_I, \
659 {"", (TARGET_DEFAULT \
660 | TARGET_CPU_DEFAULT \
661 | TARGET_ENDIAN_DEFAULT), \
665 /* Default target_flags if no switches are specified */
667 #ifndef TARGET_DEFAULT
668 #define TARGET_DEFAULT 0
671 #ifndef TARGET_CPU_DEFAULT
672 #define TARGET_CPU_DEFAULT 0
675 #ifndef TARGET_ENDIAN_DEFAULT
676 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
679 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
680 #ifndef MIPS_ISA_DEFAULT
681 #ifndef MIPS_CPU_STRING_DEFAULT
682 #define MIPS_CPU_STRING_DEFAULT "from-abi"
688 /* Make this compile time constant for libgcc2 */
690 #define TARGET_64BIT 1
692 #define TARGET_64BIT 0
694 #endif /* IN_LIBGCC2 */
696 #ifndef MULTILIB_ENDIAN_DEFAULT
697 #if TARGET_ENDIAN_DEFAULT == 0
698 #define MULTILIB_ENDIAN_DEFAULT "EL"
700 #define MULTILIB_ENDIAN_DEFAULT "EB"
704 #ifndef MULTILIB_ISA_DEFAULT
705 # if MIPS_ISA_DEFAULT == 1
706 # define MULTILIB_ISA_DEFAULT "mips1"
708 # if MIPS_ISA_DEFAULT == 2
709 # define MULTILIB_ISA_DEFAULT "mips2"
711 # if MIPS_ISA_DEFAULT == 3
712 # define MULTILIB_ISA_DEFAULT "mips3"
714 # if MIPS_ISA_DEFAULT == 4
715 # define MULTILIB_ISA_DEFAULT "mips4"
717 # if MIPS_ISA_DEFAULT == 32
718 # define MULTILIB_ISA_DEFAULT "mips32"
720 # if MIPS_ISA_DEFAULT == 33
721 # define MULTILIB_ISA_DEFAULT "mips32r2"
723 # if MIPS_ISA_DEFAULT == 64
724 # define MULTILIB_ISA_DEFAULT "mips64"
726 # define MULTILIB_ISA_DEFAULT "mips1"
736 #ifndef MULTILIB_DEFAULTS
737 #define MULTILIB_DEFAULTS \
738 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
741 /* We must pass -EL to the linker by default for little endian embedded
742 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
743 linker will default to using big-endian output files. The OUTPUT_FORMAT
744 line must be in the linker script, otherwise -EB/-EL will not work. */
747 #if TARGET_ENDIAN_DEFAULT == 0
748 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
750 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
754 #define TARGET_OPTIONS \
756 SUBTARGET_TARGET_OPTIONS \
757 { "tune=", &mips_tune_string, \
758 N_("Specify CPU for scheduling purposes")}, \
759 { "arch=", &mips_arch_string, \
760 N_("Specify CPU for code generation purposes")}, \
761 { "abi=", &mips_abi_string, \
762 N_("Specify an ABI")}, \
763 { "ips", &mips_isa_string, \
764 N_("Specify a Standard MIPS ISA")}, \
765 { "entry", &mips_entry_string, \
766 N_("Use mips16 entry/exit psuedo ops")}, \
767 { "no-mips16", &mips_no_mips16_string, \
768 N_("Don't use MIPS16 instructions")}, \
769 { "no-flush-func", &mips_cache_flush_func, \
770 N_("Don't call any cache flush functions")}, \
771 { "flush-func=", &mips_cache_flush_func, \
772 N_("Specify cache flush function")}, \
775 /* This is meant to be redefined in the host dependent files. */
776 #define SUBTARGET_TARGET_OPTIONS
778 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
782 /* Generate three-operand multiply instructions for SImode. */
783 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
791 /* Generate three-operand multiply instructions for DImode. */
792 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
795 /* Macros to decide whether certain features are available or not,
796 depending on the instruction set architecture level. */
798 #define HAVE_SQRT_P() (!ISA_MIPS1)
800 /* True if the ABI can only work with 64-bit integer registers. We
801 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
802 otherwise floating-point registers must also be 64-bit. */
803 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
804 || mips_abi == ABI_O64 \
805 || mips_abi == ABI_N32)
807 /* Likewise for 32-bit regs. */
808 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
810 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
811 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
815 /* ISA has branch likely instructions (eg. mips2). */
816 /* Disable branchlikely for tx39 until compare rewrite. They haven't
817 been generated up to this point. */
818 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
821 /* ISA has the conditional move instructions introduced in mips4. */
822 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
826 && !TARGET_MIPS5500 \
829 /* ISA has just the integer condition move instructions (movn,movz) */
830 #define ISA_HAS_INT_CONDMOVE 0
832 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
833 branch on CC, and move (both FP and non-FP) on CC. */
834 #define ISA_HAS_8CC (ISA_MIPS4 \
839 /* This is a catch all for the other new mips4 instructions: indexed load and
840 indexed prefetch instructions, the FP madd and msub instructions,
841 and the FP recip and recip sqrt instructions */
842 #define ISA_HAS_FP4 ((ISA_MIPS4 \
846 /* ISA has conditional trap instructions. */
847 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
850 /* ISA has integer multiply-accumulate instructions, madd and msub. */
851 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
856 /* ISA has floating-point nmadd and nmsub instructions. */
857 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
859 && (!TARGET_MIPS5400 || TARGET_MAD) \
862 /* ISA has count leading zeroes/ones instruction (not implemented). */
863 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
868 /* ISA has double-word count leading zeroes/ones instruction (not
870 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
873 /* ISA has three operand multiply instructions that put
874 the high part in an accumulator: mulhi or mulhiu. */
875 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
880 /* ISA has three operand multiply instructions that
881 negates the result and puts the result in an accumulator. */
882 #define ISA_HAS_MULS (TARGET_MIPS5400 \
887 /* ISA has three operand multiply instructions that subtracts the
888 result from a 4th operand and puts the result in an accumulator. */
889 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
893 /* ISA has three operand multiply instructions that the result
894 from a 4th operand and puts the result in an accumulator. */
895 #define ISA_HAS_MACC (TARGET_MIPS5400 \
900 /* ISA has 32-bit rotate right instruction. */
901 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
908 /* ISA has 64-bit rotate right instruction. */
909 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
911 && (TARGET_MIPS5400 \
916 /* ISA has data prefetch instruction. */
917 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
923 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
924 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
925 also requires TARGET_DOUBLE_FLOAT. */
926 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
928 /* ISA includes the MIPS32r2 seb and seh instructions. */
929 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
933 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
934 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
935 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
936 target_flags, and -mgp64 sets MASK_64BIT.
938 Setting MASK_64BIT in target_flags will cause gcc to assume that
939 registers are 64 bits wide. int, long and void * will be 32 bit;
940 this may be changed with -mint64 or -mlong64.
942 The gen* programs link code that refers to MASK_64BIT. They don't
943 actually use the information in target_flags; they just refer to
946 /* Switch Recognition by gcc.c. Add -G xx support */
948 #undef SWITCH_TAKES_ARG
949 #define SWITCH_TAKES_ARG(CHAR) \
950 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
952 /* Sometimes certain combinations of command options do not make sense
953 on a particular target machine. You can define a macro
954 `OVERRIDE_OPTIONS' to take account of this. This macro, if
955 defined, is executed once just after all the command options have
958 On the MIPS, it is used to handle -G. We also use it to set up all
959 of the tables referenced in the other macros. */
961 #define OVERRIDE_OPTIONS override_options ()
963 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
965 /* Show we can debug even without a frame pointer. */
966 #define CAN_DEBUG_WITHOUT_FP
968 /* Tell collect what flags to pass to nm. */
970 #define NM_FLAGS "-Bn"
974 /* Assembler specs. */
976 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
979 #define MIPS_AS_ASM_SPEC "\
980 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
981 %{pipe: %e-pipe is not supported} \
982 %{K} %(subtarget_mips_as_asm_spec)"
984 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
985 rather than gas. It may be overridden by subtargets. */
987 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
988 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
991 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
994 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
999 #ifndef MIPS_ABI_DEFAULT
1000 #define MIPS_ABI_DEFAULT ABI_32
1003 /* Use the most portable ABI flag for the ASM specs. */
1005 #if MIPS_ABI_DEFAULT == ABI_32
1006 #define MULTILIB_ABI_DEFAULT "mabi=32"
1007 #define ASM_ABI_DEFAULT_SPEC "-32"
1010 #if MIPS_ABI_DEFAULT == ABI_O64
1011 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1012 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1015 #if MIPS_ABI_DEFAULT == ABI_N32
1016 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1017 #define ASM_ABI_DEFAULT_SPEC "-n32"
1020 #if MIPS_ABI_DEFAULT == ABI_64
1021 #define MULTILIB_ABI_DEFAULT "mabi=64"
1022 #define ASM_ABI_DEFAULT_SPEC "-64"
1025 #if MIPS_ABI_DEFAULT == ABI_EABI
1026 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1027 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1030 #if MIPS_ABI_DEFAULT == ABI_MEABI
1031 /* Most GAS don't know about MEABI. */
1032 #define MULTILIB_ABI_DEFAULT "mabi=meabi"
1033 #define ASM_ABI_DEFAULT_SPEC ""
1036 /* Only ELF targets can switch the ABI. */
1037 #ifndef OBJECT_FORMAT_ELF
1038 #undef ASM_ABI_DEFAULT_SPEC
1039 #define ASM_ABI_DEFAULT_SPEC ""
1042 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1043 GAS_ASM_SPEC as the default, depending upon the value of
1046 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1049 #define TARGET_ASM_SPEC "\
1050 %{mmips-as: %(mips_as_asm_spec)} \
1051 %{!mmips-as: %(gas_asm_spec)}"
1055 #define TARGET_ASM_SPEC "\
1056 %{!mgas: %(mips_as_asm_spec)} \
1057 %{mgas: %(gas_asm_spec)}"
1059 #endif /* not GAS */
1061 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1062 to the assembler. It may be overridden by subtargets. */
1063 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1064 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1066 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1069 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1070 the assembler. It may be overridden by subtargets. */
1071 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1072 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1073 %{g} %{g0} %{g1} %{g2} %{g3} \
1074 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1075 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1076 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1077 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1078 %{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1081 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1082 overridden by subtargets. */
1084 #ifndef SUBTARGET_ASM_SPEC
1085 #define SUBTARGET_ASM_SPEC ""
1088 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1089 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1090 whether we're using GAS. These options can only be used properly
1091 with GAS, and it is better to get an error from a non-GAS assembler
1092 than to silently generate bad code. */
1096 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1097 %{mips32} %{mips32r2} %{mips64} \
1098 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1099 %(subtarget_asm_optimizing_spec) \
1100 %(subtarget_asm_debugging_spec) \
1102 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1103 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1104 %{mgp32} %{mgp64} %{march=*} \
1105 %(target_asm_spec) \
1106 %(subtarget_asm_spec)"
1108 /* Specify to run a post-processor, mips-tfile after the assembler
1109 has run to stuff the mips debug information into the object file.
1110 This is needed because the $#!%^ MIPS assembler provides no way
1111 of specifying such information in the assembly file. If we are
1112 cross compiling, disable mips-tfile unless the user specifies
1115 #ifndef ASM_FINAL_SPEC
1116 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1118 #define ASM_FINAL_SPEC "\
1119 %{mmips-as: %{!mno-mips-tfile: \
1120 \n mips-tfile %{v*: -v} \
1122 %{!K: %{save-temps: -I %b.o~}} \
1123 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1124 %{.s:%i} %{!.s:%g.s}}}"
1128 #define ASM_FINAL_SPEC "\
1129 %{!mgas: %{!mno-mips-tfile: \
1130 \n mips-tfile %{v*: -v} \
1132 %{!K: %{save-temps: -I %b.o~}} \
1133 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1134 %{.s:%i} %{!.s:%g.s}}}"
1137 #endif /* ASM_FINAL_SPEC */
1139 /* Redefinition of libraries used. Mips doesn't support normal
1140 UNIX style profiling via calling _mcount. It does offer
1141 profiling that samples the PC, so do what we can... */
1144 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1147 /* Extra switches sometimes passed to the linker. */
1148 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1149 will interpret it as a -b option. */
1152 #define LINK_SPEC "\
1154 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1155 %{bestGnum} %{shared} %{non_shared}"
1156 #endif /* LINK_SPEC defined */
1159 /* Specs for the compiler proper */
1161 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1162 overridden by subtargets. */
1163 #ifndef SUBTARGET_CC1_SPEC
1164 #define SUBTARGET_CC1_SPEC ""
1167 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1168 /* Note, we will need to adjust the following if we ever find a MIPS variant
1169 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1170 that show up in this case. */
1174 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1175 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1177 %(subtarget_cc1_spec)"
1180 /* Preprocessor specs. */
1182 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1183 overridden by subtargets. */
1184 #ifndef SUBTARGET_CPP_SPEC
1185 #define SUBTARGET_CPP_SPEC ""
1188 #define CPP_SPEC "%(subtarget_cpp_spec)"
1190 /* This macro defines names of additional specifications to put in the specs
1191 that can be used in various specifications like CC1_SPEC. Its definition
1192 is an initializer with a subgrouping for each command option.
1194 Each subgrouping contains a string constant, that defines the
1195 specification name, and a string constant that used by the GNU CC driver
1198 Do not define this macro if it does not need to do anything. */
1200 #define EXTRA_SPECS \
1201 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1202 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1203 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1204 { "gas_asm_spec", GAS_ASM_SPEC }, \
1205 { "target_asm_spec", TARGET_ASM_SPEC }, \
1206 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1207 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1208 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1209 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1210 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1211 { "endian_spec", ENDIAN_SPEC }, \
1212 SUBTARGET_EXTRA_SPECS
1214 #ifndef SUBTARGET_EXTRA_SPECS
1215 #define SUBTARGET_EXTRA_SPECS
1218 /* If defined, this macro is an additional prefix to try after
1219 `STANDARD_EXEC_PREFIX'. */
1221 #ifndef MD_EXEC_PREFIX
1222 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1225 #ifndef MD_STARTFILE_PREFIX
1226 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1230 /* Print subsidiary information on the compiler version in use. */
1232 #define MIPS_VERSION "[AL 1.1, MM 40]"
1234 #ifndef MACHINE_TYPE
1235 #define MACHINE_TYPE "BSD Mips"
1238 #ifndef TARGET_VERSION_INTERNAL
1239 #define TARGET_VERSION_INTERNAL(STREAM) \
1240 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1243 #ifndef TARGET_VERSION
1244 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1248 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1249 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1250 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1252 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1253 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1256 /* By default, turn on GDB extensions. */
1257 #define DEFAULT_GDB_EXTENSIONS 1
1259 /* If we are passing smuggling stabs through the MIPS ECOFF object
1260 format, put a comment in front of the .stab<x> operation so
1261 that the MIPS assembler does not choke. The mips-tfile program
1262 will correctly put the stab into the object file. */
1264 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1265 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1266 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1268 /* Local compiler-generated symbols must have a prefix that the assembler
1269 understands. By default, this is $, although some targets (e.g.,
1270 NetBSD-ELF) need to override this. */
1272 #ifndef LOCAL_LABEL_PREFIX
1273 #define LOCAL_LABEL_PREFIX "$"
1276 /* By default on the mips, external symbols do not have an underscore
1277 prepended, but some targets (e.g., NetBSD) require this. */
1279 #ifndef USER_LABEL_PREFIX
1280 #define USER_LABEL_PREFIX ""
1283 /* Forward references to tags are allowed. */
1284 #define SDB_ALLOW_FORWARD_REFERENCES
1286 /* Unknown tags are also allowed. */
1287 #define SDB_ALLOW_UNKNOWN_REFERENCES
1289 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1290 since the length can run past this up to a continuation point. */
1291 #undef DBX_CONTIN_LENGTH
1292 #define DBX_CONTIN_LENGTH 1500
1294 /* How to renumber registers for dbx and gdb. */
1295 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1297 /* The mapping from gcc register number to DWARF 2 CFA column number.
1298 This mapping does not allow for tracking register 0, since SGI's broken
1299 dwarf reader thinks column 0 is used for the frame address, but since
1300 register 0 is fixed this is not a problem. */
1301 #define DWARF_FRAME_REGNUM(REG) \
1302 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1304 /* The DWARF 2 CFA column which tracks the return address. */
1305 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1307 /* Before the prologue, RA lives in r31. */
1308 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1310 /* Describe how we implement __builtin_eh_return. */
1311 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1312 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1314 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1315 The default for this in 64-bit mode is 8, which causes problems with
1316 SFmode register saves. */
1317 #define DWARF_CIE_DATA_ALIGNMENT 4
1319 /* Overrides for the COFF debug format. */
1320 #define PUT_SDB_SCL(a) \
1322 extern FILE *asm_out_text_file; \
1323 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1326 #define PUT_SDB_INT_VAL(a) \
1328 extern FILE *asm_out_text_file; \
1329 fprintf (asm_out_text_file, "\t.val\t"); \
1330 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1331 fprintf (asm_out_text_file, ";"); \
1334 #define PUT_SDB_VAL(a) \
1336 extern FILE *asm_out_text_file; \
1337 fputs ("\t.val\t", asm_out_text_file); \
1338 output_addr_const (asm_out_text_file, (a)); \
1339 fputc (';', asm_out_text_file); \
1342 #define PUT_SDB_DEF(a) \
1344 extern FILE *asm_out_text_file; \
1345 fprintf (asm_out_text_file, "\t%s.def\t", \
1346 (TARGET_GAS) ? "" : "#"); \
1347 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1348 fputc (';', asm_out_text_file); \
1351 #define PUT_SDB_PLAIN_DEF(a) \
1353 extern FILE *asm_out_text_file; \
1354 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1355 (TARGET_GAS) ? "" : "#", (a)); \
1358 #define PUT_SDB_ENDEF \
1360 extern FILE *asm_out_text_file; \
1361 fprintf (asm_out_text_file, "\t.endef\n"); \
1364 #define PUT_SDB_TYPE(a) \
1366 extern FILE *asm_out_text_file; \
1367 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1370 #define PUT_SDB_SIZE(a) \
1372 extern FILE *asm_out_text_file; \
1373 fprintf (asm_out_text_file, "\t.size\t"); \
1374 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1375 fprintf (asm_out_text_file, ";"); \
1378 #define PUT_SDB_DIM(a) \
1380 extern FILE *asm_out_text_file; \
1381 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1384 #ifndef PUT_SDB_START_DIM
1385 #define PUT_SDB_START_DIM \
1387 extern FILE *asm_out_text_file; \
1388 fprintf (asm_out_text_file, "\t.dim\t"); \
1392 #ifndef PUT_SDB_NEXT_DIM
1393 #define PUT_SDB_NEXT_DIM(a) \
1395 extern FILE *asm_out_text_file; \
1396 fprintf (asm_out_text_file, "%d,", a); \
1400 #ifndef PUT_SDB_LAST_DIM
1401 #define PUT_SDB_LAST_DIM(a) \
1403 extern FILE *asm_out_text_file; \
1404 fprintf (asm_out_text_file, "%d;", a); \
1408 #define PUT_SDB_TAG(a) \
1410 extern FILE *asm_out_text_file; \
1411 fprintf (asm_out_text_file, "\t.tag\t"); \
1412 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1413 fputc (';', asm_out_text_file); \
1416 /* For block start and end, we create labels, so that
1417 later we can figure out where the correct offset is.
1418 The normal .ent/.end serve well enough for functions,
1419 so those are just commented out. */
1421 #define PUT_SDB_BLOCK_START(LINE) \
1423 extern FILE *asm_out_text_file; \
1424 fprintf (asm_out_text_file, \
1425 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1426 LOCAL_LABEL_PREFIX, \
1428 (TARGET_GAS) ? "" : "#", \
1429 LOCAL_LABEL_PREFIX, \
1432 sdb_label_count++; \
1435 #define PUT_SDB_BLOCK_END(LINE) \
1437 extern FILE *asm_out_text_file; \
1438 fprintf (asm_out_text_file, \
1439 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1440 LOCAL_LABEL_PREFIX, \
1442 (TARGET_GAS) ? "" : "#", \
1443 LOCAL_LABEL_PREFIX, \
1446 sdb_label_count++; \
1449 #define PUT_SDB_FUNCTION_START(LINE)
1451 #define PUT_SDB_FUNCTION_END(LINE) \
1453 extern FILE *asm_out_text_file; \
1454 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1457 #define PUT_SDB_EPILOGUE_END(NAME)
1459 #define PUT_SDB_SRC_FILE(FILENAME) \
1461 extern FILE *asm_out_text_file; \
1462 output_file_directive (asm_out_text_file, (FILENAME));\
1465 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1466 sprintf ((BUFFER), ".%dfake", (NUMBER));
1468 /* Correct the offset of automatic variables and arguments. Note that
1469 the MIPS debug format wants all automatic variables and arguments
1470 to be in terms of the virtual frame pointer (stack pointer before
1471 any adjustment in the function), while the MIPS 3.0 linker wants
1472 the frame pointer to be the stack pointer after the initial
1475 #define DEBUGGER_AUTO_OFFSET(X) \
1476 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1477 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1478 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1480 /* Tell collect that the object format is ECOFF */
1481 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1482 #define EXTENDED_COFF /* ECOFF, not normal coff */
1484 /* Target machine storage layout */
1486 /* Define this if most significant bit is lowest numbered
1487 in instructions that operate on numbered bit-fields.
1489 #define BITS_BIG_ENDIAN 0
1491 /* Define this if most significant byte of a word is the lowest numbered. */
1492 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1494 /* Define this if most significant word of a multiword number is the lowest. */
1495 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1497 /* Define this to set the endianness to use in libgcc2.c, which can
1498 not depend on target_flags. */
1499 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1500 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1502 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1505 #define MAX_BITS_PER_WORD 64
1507 /* Width of a word, in units (bytes). */
1508 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1509 #define MIN_UNITS_PER_WORD 4
1511 /* For MIPS, width of a floating point register. */
1512 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1514 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1515 the next available register. */
1516 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1518 /* The largest size of value that can be held in floating-point registers. */
1519 #define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1521 /* The number of bytes in a double. */
1522 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1524 /* A C expression for the size in bits of the type `int' on the
1525 target machine. If you don't define this, the default is one
1527 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1529 /* Tell the preprocessor the maximum size of wchar_t. */
1530 #ifndef MAX_WCHAR_TYPE_SIZE
1531 #ifndef WCHAR_TYPE_SIZE
1532 #define MAX_WCHAR_TYPE_SIZE 64
1536 /* A C expression for the size in bits of the type `short' on the
1537 target machine. If you don't define this, the default is half a
1538 word. (If this would be less than one storage unit, it is
1539 rounded up to one unit.) */
1540 #define SHORT_TYPE_SIZE 16
1542 /* A C expression for the size in bits of the type `long' on the
1543 target machine. If you don't define this, the default is one
1545 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1546 #define MAX_LONG_TYPE_SIZE 64
1548 /* A C expression for the size in bits of the type `long long' on the
1549 target machine. If you don't define this, the default is two
1551 #define LONG_LONG_TYPE_SIZE 64
1553 /* A C expression for the size in bits of the type `float' on the
1554 target machine. If you don't define this, the default is one
1556 #define FLOAT_TYPE_SIZE 32
1558 /* A C expression for the size in bits of the type `double' on the
1559 target machine. If you don't define this, the default is two
1561 #define DOUBLE_TYPE_SIZE 64
1563 /* A C expression for the size in bits of the type `long double' on
1564 the target machine. If you don't define this, the default is two
1566 #define LONG_DOUBLE_TYPE_SIZE 64
1568 /* Width in bits of a pointer.
1569 See also the macro `Pmode' defined below. */
1570 #ifndef POINTER_SIZE
1571 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1574 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1575 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1577 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1578 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1579 || mips_abi == ABI_64 \
1580 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1582 /* Allocation boundary (in *bits*) for the code of a function. */
1583 #define FUNCTION_BOUNDARY 32
1585 /* Alignment of field after `int : 0' in a structure. */
1586 #define EMPTY_FIELD_BOUNDARY 32
1588 /* Every structure's size must be a multiple of this. */
1589 /* 8 is observed right on a DECstation and on riscos 4.02. */
1590 #define STRUCTURE_SIZE_BOUNDARY 8
1592 /* There is no point aligning anything to a rounder boundary than this. */
1593 #define BIGGEST_ALIGNMENT 64
1595 /* Set this nonzero if move instructions will actually fail to work
1596 when given unaligned data. */
1597 #define STRICT_ALIGNMENT 1
1599 /* Define this if you wish to imitate the way many other C compilers
1600 handle alignment of bitfields and the structures that contain
1603 The behavior is that the type written for a bit-field (`int',
1604 `short', or other integer type) imposes an alignment for the
1605 entire structure, as if the structure really did contain an
1606 ordinary field of that type. In addition, the bit-field is placed
1607 within the structure so that it would fit within such a field,
1608 not crossing a boundary for it.
1610 Thus, on most machines, a bit-field whose type is written as `int'
1611 would not cross a four-byte boundary, and would force four-byte
1612 alignment for the whole structure. (The alignment used may not
1613 be four bytes; it is controlled by the other alignment
1616 If the macro is defined, its definition should be a C expression;
1617 a nonzero value for the expression enables this behavior. */
1619 #define PCC_BITFIELD_TYPE_MATTERS 1
1621 /* If defined, a C expression to compute the alignment given to a
1622 constant that is being placed in memory. CONSTANT is the constant
1623 and ALIGN is the alignment that the object would ordinarily have.
1624 The value of this macro is used instead of that alignment to align
1627 If this macro is not defined, then ALIGN is used.
1629 The typical use of this macro is to increase alignment for string
1630 constants to be word aligned so that `strcpy' calls that copy
1631 constants can be done inline. */
1633 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1634 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1635 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1637 /* If defined, a C expression to compute the alignment for a static
1638 variable. TYPE is the data type, and ALIGN is the alignment that
1639 the object would ordinarily have. The value of this macro is used
1640 instead of that alignment to align the object.
1642 If this macro is not defined, then ALIGN is used.
1644 One use of this macro is to increase alignment of medium-size
1645 data to make it all fit in fewer cache lines. Another is to
1646 cause character arrays to be word-aligned so that `strcpy' calls
1647 that copy constants to character arrays can be done inline. */
1649 #undef DATA_ALIGNMENT
1650 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1651 ((((ALIGN) < BITS_PER_WORD) \
1652 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1653 || TREE_CODE (TYPE) == UNION_TYPE \
1654 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1657 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1659 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1660 || mips_abi == ABI_MEABI \
1661 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1663 /* Define this macro if an argument declared as `char' or `short' in a
1664 prototype should actually be passed as an `int'. In addition to
1665 avoiding errors in certain cases of mismatch, it also makes for
1666 better code on certain machines. */
1668 #define PROMOTE_PROTOTYPES 1
1670 /* Define if operations between registers always perform the operation
1671 on the full register even if a narrower mode is specified. */
1672 #define WORD_REGISTER_OPERATIONS
1674 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1675 will either zero-extend or sign-extend. The value of this macro should
1676 be the code that says which one of the two operations is implicitly
1679 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1680 moves. All other referces are zero extended. */
1681 #define LOAD_EXTEND_OP(MODE) \
1682 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1683 ? SIGN_EXTEND : ZERO_EXTEND)
1685 /* Define this macro if it is advisable to hold scalars in registers
1686 in a wider mode than that declared by the program. In such cases,
1687 the value is constrained to be within the bounds of the declared
1688 type, but kept valid in the wider mode. The signedness of the
1689 extension may differ from that of the type.
1691 We promote any value smaller than SImode up to SImode. We don't
1692 want to promote to DImode when in 64 bit mode, because that would
1693 prevent us from using the faster SImode multiply and divide
1696 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1697 if (GET_MODE_CLASS (MODE) == MODE_INT \
1698 && GET_MODE_SIZE (MODE) < 4) \
1701 /* Define this if function arguments should also be promoted using the above
1704 #define PROMOTE_FUNCTION_ARGS
1706 /* Likewise, if the function return value is promoted. */
1708 #define PROMOTE_FUNCTION_RETURN
1710 /* Standard register usage. */
1712 /* Number of actual hardware registers.
1713 The hardware registers are assigned numbers for the compiler
1714 from 0 to just below FIRST_PSEUDO_REGISTER.
1715 All registers that the compiler knows about must be given numbers,
1716 even those that are not normally considered general registers.
1718 On the Mips, we have 32 integer registers, 32 floating point
1719 registers, 8 condition code registers, and the special registers
1720 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1721 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1722 processor.) The 8 condition code registers are only used if
1723 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1724 represents a 64 bit value stored as two 32 bit values in the hi and
1725 lo registers; this is the result of the mult instruction. rap is a
1726 pointer to the stack where the return address reg ($31) was stored.
1727 This is needed for C++ exception handling. */
1729 #define FIRST_PSEUDO_REGISTER 176
1731 /* 1 for registers that have pervasive standard uses
1732 and are not available for the register allocator.
1734 On the MIPS, see conventions, page D-2 */
1736 /* Regarding coprocessor registers: without evidence to the contrary,
1737 it's best to assume that each coprocessor register has a unique
1738 use. This can be overridden, in, e.g., override_options() or
1739 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1740 for a particular target. */
1742 #define FIXED_REGISTERS \
1744 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1745 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1746 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1747 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1748 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
1749 /* COP0 registers */ \
1750 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1751 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1752 /* COP2 registers */ \
1753 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1754 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1755 /* COP3 registers */ \
1756 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1757 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1761 /* 1 for registers not available across function calls.
1762 These must include the FIXED_REGISTERS and also any
1763 registers that can be used without being saved.
1764 The latter must include the registers where values are returned
1765 and the register where structure-value addresses are passed.
1766 Aside from that, you can include as many other registers as you like. */
1768 #define CALL_USED_REGISTERS \
1770 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1771 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1772 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1773 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1774 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1775 /* COP0 registers */ \
1776 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1777 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1778 /* COP2 registers */ \
1779 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1780 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1781 /* COP3 registers */ \
1782 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1783 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1786 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1787 problem which makes CALL_USED_REGISTERS *always* include
1788 all the FIXED_REGISTERS. Until this problem has been
1789 resolved this macro can be used to overcome this situation.
1790 In particular, block_propagate() requires this list
1791 be acurate, or we can remove registers which should be live.
1792 This macro is used in regs_invalidated_by_call. */
1795 #define CALL_REALLY_USED_REGISTERS \
1796 { /* General registers. */ \
1797 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1798 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1799 /* Floating-point registers. */ \
1800 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1801 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1803 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1804 /* COP0 registers */ \
1805 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1806 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1807 /* COP2 registers */ \
1808 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1809 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1810 /* COP3 registers */ \
1811 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1815 /* Internal macros to classify a register number as to whether it's a
1816 general purpose register, a floating point register, a
1817 multiply/divide register, or a status register. */
1819 #define GP_REG_FIRST 0
1820 #define GP_REG_LAST 31
1821 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1822 #define GP_DBX_FIRST 0
1824 #define FP_REG_FIRST 32
1825 #define FP_REG_LAST 63
1826 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1827 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1829 #define MD_REG_FIRST 64
1830 #define MD_REG_LAST 66
1831 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1833 #define ST_REG_FIRST 67
1834 #define ST_REG_LAST 74
1835 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1837 #define RAP_REG_NUM 75
1839 #define COP0_REG_FIRST 80
1840 #define COP0_REG_LAST 111
1841 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1843 #define COP2_REG_FIRST 112
1844 #define COP2_REG_LAST 143
1845 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1847 #define COP3_REG_FIRST 144
1848 #define COP3_REG_LAST 175
1849 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1850 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1851 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1853 #define AT_REGNUM (GP_REG_FIRST + 1)
1854 #define HI_REGNUM (MD_REG_FIRST + 0)
1855 #define LO_REGNUM (MD_REG_FIRST + 1)
1856 #define HILO_REGNUM (MD_REG_FIRST + 2)
1858 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1859 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1860 should be used instead. */
1861 #define FPSW_REGNUM ST_REG_FIRST
1863 #define GP_REG_P(REGNO) \
1864 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1865 #define M16_REG_P(REGNO) \
1866 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1867 #define FP_REG_P(REGNO) \
1868 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1869 #define MD_REG_P(REGNO) \
1870 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1871 #define ST_REG_P(REGNO) \
1872 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1873 #define COP0_REG_P(REGNO) \
1874 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1875 #define COP2_REG_P(REGNO) \
1876 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1877 #define COP3_REG_P(REGNO) \
1878 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1879 #define ALL_COP_REG_P(REGNO) \
1880 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1882 /* Return coprocessor number from register number. */
1884 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1885 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1886 : COP3_REG_P (REGNO) ? '3' : '?')
1888 /* Return number of consecutive hard regs needed starting at reg REGNO
1889 to hold something of mode MODE.
1890 This is ordinarily the length in words of a value of mode MODE
1891 but can be less for certain modes in special long registers.
1893 On the MIPS, all general registers are one word long. Except on
1894 the R4000 with the FR bit set, the floating point uses register
1895 pairs, with the second register not being allocable. */
1897 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1899 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1900 MODE. In 32 bit mode, require that DImode and DFmode be in even
1901 registers. For DImode, this makes some of the insns easier to
1902 write, since you don't have to worry about a DImode value in
1903 registers 3 & 4, producing a result in 4 & 5.
1905 To make the code simpler HARD_REGNO_MODE_OK now just references an
1906 array built in override_options. Because machmodes.h is not yet
1907 included before this file is processed, the MODE bound can't be
1910 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1912 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1913 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1915 /* Value is 1 if it is a good idea to tie two pseudo registers
1916 when one has mode MODE1 and one has mode MODE2.
1917 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1918 for any hard reg, then this must be 0 for correct output. */
1919 #define MODES_TIEABLE_P(MODE1, MODE2) \
1920 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1921 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1922 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1923 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1925 /* MIPS pc is not overloaded on a register. */
1926 /* #define PC_REGNUM xx */
1928 /* Register to use for pushing function arguments. */
1929 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1931 /* Offset from the stack pointer to the first available location. Use
1932 the default value zero. */
1933 /* #define STACK_POINTER_OFFSET 0 */
1935 /* Base register for access to local variables of the function. We
1936 pretend that the frame pointer is $1, and then eliminate it to
1937 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1938 a fixed register, and will not be used for anything else. */
1939 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1941 /* Temporary scratch register for use by the assembler. */
1942 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1944 /* $30 is not available on the mips16, so we use $17 as the frame
1946 #define HARD_FRAME_POINTER_REGNUM \
1947 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1949 /* Value should be nonzero if functions must have frame pointers.
1950 Zero means the frame pointer need not be set up (and parms
1951 may be accessed via the stack pointer) in functions that seem suitable.
1952 This is computed in `reload', in reload1.c. */
1953 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1955 /* Base register for access to arguments of the function. */
1956 #define ARG_POINTER_REGNUM GP_REG_FIRST
1958 /* Fake register that holds the address on the stack of the
1959 current function's return address. */
1960 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1962 /* Register in which static-chain is passed to a function. */
1963 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1965 /* If the structure value address is passed in a register, then
1966 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1967 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1969 /* If the structure value address is not passed in a register, define
1970 `STRUCT_VALUE' as an expression returning an RTX for the place
1971 where the address is passed. If it returns 0, the address is
1972 passed as an "invisible" first argument. */
1973 #define STRUCT_VALUE 0
1975 /* Mips registers used in prologue/epilogue code when the stack frame
1976 is larger than 32K bytes. These registers must come from the
1977 scratch register set, and not used for passing and returning
1978 arguments and any other information used in the calling sequence
1979 (such as pic). Must start at 12, since t0/t3 are parameter passing
1980 registers in the 64 bit ABI. */
1982 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1983 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1985 /* Define this macro if it is as good or better to call a constant
1986 function address than to call an address kept in a register. */
1987 #define NO_FUNCTION_CSE 1
1989 /* Define this macro if it is as good or better for a function to
1990 call itself with an explicit address than to call an address
1991 kept in a register. */
1992 #define NO_RECURSIVE_FUNCTION_CSE 1
1994 /* The register number of the register used to address a table of
1995 static data addresses in memory. In some cases this register is
1996 defined by a processor's "application binary interface" (ABI).
1997 When this macro is defined, RTL is generated for this register
1998 once, as with the stack pointer and frame pointer registers. If
1999 this macro is not defined, it is up to the machine-dependent
2000 files to allocate such a register (if necessary). */
2001 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
2003 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
2005 /* Define the classes of registers for register constraints in the
2006 machine description. Also define ranges of constants.
2008 One of the classes must always be named ALL_REGS and include all hard regs.
2009 If there is more than one class, another class must be named NO_REGS
2010 and contain no registers.
2012 The name GENERAL_REGS must be the name of a class (or an alias for
2013 another name such as ALL_REGS). This is the class of registers
2014 that is allowed by "g" or "r" in a register constraint.
2015 Also, registers outside this class are allocated only when
2016 instructions express preferences for them.
2018 The classes must be numbered in nondecreasing order; that is,
2019 a larger-numbered class must never be contained completely
2020 in a smaller-numbered class.
2022 For any two classes, it is very desirable that there be another
2023 class that represents their union. */
2027 NO_REGS, /* no registers in set */
2028 M16_NA_REGS, /* mips16 regs not used to pass args */
2029 M16_REGS, /* mips16 directly accessible registers */
2030 T_REG, /* mips16 T register ($24) */
2031 M16_T_REGS, /* mips16 registers plus T register */
2032 GR_REGS, /* integer registers */
2033 FP_REGS, /* floating point registers */
2034 HI_REG, /* hi register */
2035 LO_REG, /* lo register */
2036 HILO_REG, /* hilo register pair for 64 bit mode mult */
2037 MD_REGS, /* multiply/divide registers (hi/lo) */
2038 COP0_REGS, /* generic coprocessor classes */
2041 HI_AND_GR_REGS, /* union classes */
2049 ALL_COP_AND_GR_REGS,
2050 ST_REGS, /* status registers (fp status) */
2051 ALL_REGS, /* all registers */
2052 LIM_REG_CLASSES /* max value + 1 */
2055 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2057 #define GENERAL_REGS GR_REGS
2059 /* An initializer containing the names of the register classes as C
2060 string constants. These names are used in writing some of the
2063 #define REG_CLASS_NAMES \
2076 /* coprocessor registers */ \
2082 "HILO_AND_GR_REGS", \
2084 "COP0_AND_GR_REGS", \
2085 "COP2_AND_GR_REGS", \
2086 "COP3_AND_GR_REGS", \
2088 "ALL_COP_AND_GR_REGS", \
2093 /* An initializer containing the contents of the register classes,
2094 as integers which are bit masks. The Nth integer specifies the
2095 contents of class N. The way the integer MASK is interpreted is
2096 that register R is in the class if `MASK & (1 << R)' is 1.
2098 When the machine has more than 32 registers, an integer does not
2099 suffice. Then the integers are replaced by sub-initializers,
2100 braced groupings containing several integers. Each
2101 sub-initializer must be suitable as an initializer for the type
2102 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2104 #define REG_CLASS_CONTENTS \
2106 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2107 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2108 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2109 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2110 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2111 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2112 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2113 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2114 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2115 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2116 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2117 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2118 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2119 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2120 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2121 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2122 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2123 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2124 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2125 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2126 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2127 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2128 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2129 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2130 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2134 /* A C expression whose value is a register class containing hard
2135 register REGNO. In general there is more that one such class;
2136 choose a class which is "minimal", meaning that no smaller class
2137 also contains the register. */
2139 extern const enum reg_class mips_regno_to_class[];
2141 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2143 /* A macro whose definition is the name of the class to which a
2144 valid base register must belong. A base register is one used in
2145 an address which is the register value plus a displacement. */
2147 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2149 /* A macro whose definition is the name of the class to which a
2150 valid index register must belong. An index register is one used
2151 in an address where its value is either multiplied by a scale
2152 factor or added to another register (as well as added to a
2155 #define INDEX_REG_CLASS NO_REGS
2157 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2158 registers explicitly used in the rtl to be used as spill registers
2159 but prevents the compiler from extending the lifetime of these
2162 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2164 /* This macro is used later on in the file. */
2165 #define GR_REG_CLASS_P(CLASS) \
2166 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2167 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2169 /* This macro is also used later on in the file. */
2170 #define COP_REG_CLASS_P(CLASS) \
2171 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2173 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2174 is the default value (allocate the registers in numeric order). We
2175 define it just so that we can override it for the mips16 target in
2176 ORDER_REGS_FOR_LOCAL_ALLOC. */
2178 #define REG_ALLOC_ORDER \
2179 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2180 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2181 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2182 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2183 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2184 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2185 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2186 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2187 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2188 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2189 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2192 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2193 to be rearranged based on a particular function. On the mips16, we
2194 want to allocate $24 (T_REG) before other registers for
2195 instructions for which it is possible. */
2197 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2199 /* REGISTER AND CONSTANT CLASSES */
2201 /* Get reg_class from a letter such as appears in the machine
2204 DEFINED REGISTER CLASSES:
2206 'd' General (aka integer) registers
2207 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2208 'y' General registers (in both mips16 and non mips16 mode)
2209 'e' mips16 non argument registers (M16_NA_REGS)
2210 't' mips16 temporary register ($24)
2211 'f' Floating point registers
2214 'x' Multiply/divide registers
2216 'z' FP Status register
2220 'b' All registers */
2222 extern enum reg_class mips_char_to_class[256];
2224 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2226 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2227 string can be used to stand for particular ranges of immediate
2228 operands. This macro defines what the ranges are. C is the
2229 letter, and VALUE is a constant value. Return 1 if VALUE is
2230 in the range specified by C. */
2234 `I' is used for the range of constants an arithmetic insn can
2235 actually contain (16 bits signed integers).
2237 `J' is used for the range which is just zero (ie, $r0).
2239 `K' is used for the range of constants a logical insn can actually
2240 contain (16 bit zero-extended integers).
2242 `L' is used for the range of constants that be loaded with lui
2243 (ie, the bottom 16 bits are zero).
2245 `M' is used for the range of constants that take two words to load
2246 (ie, not matched by `I', `K', and `L').
2248 `N' is used for negative 16 bit constants other than -65536.
2250 `O' is a 15 bit signed integer.
2252 `P' is used for positive 16 bit constants. */
2254 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2255 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2257 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2258 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2259 : (C) == 'J' ? ((VALUE) == 0) \
2260 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2261 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2262 && (((VALUE) & ~2147483647) == 0 \
2263 || ((VALUE) & ~2147483647) == ~2147483647)) \
2264 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2265 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2266 && (((VALUE) & 0x0000ffff) != 0 \
2267 || (((VALUE) & ~2147483647) != 0 \
2268 && ((VALUE) & ~2147483647) != ~2147483647))) \
2269 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2270 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2271 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2274 /* Similar, but for floating constants, and defining letters G and H.
2275 Here VALUE is the CONST_DOUBLE rtx itself. */
2279 'G' : Floating point 0 */
2281 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2283 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2285 /* Letters in the range `Q' through `U' may be defined in a
2286 machine-dependent fashion to stand for arbitrary operand types.
2287 The machine description macro `EXTRA_CONSTRAINT' is passed the
2288 operand as its first argument and the constraint letter as its
2291 `Q' is for mips16 GP relative constants
2292 `R' is for memory references which take 1 word for the instruction.
2293 `T' is for memory addresses that can be used to load two words. */
2295 #define EXTRA_CONSTRAINT(OP,CODE) \
2296 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2297 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2298 && mips16_gp_offset_p (OP)) \
2299 : (GET_CODE (OP) != MEM) ? FALSE \
2300 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2303 /* Given an rtx X being reloaded into a reg required to be
2304 in class CLASS, return the class of reg to actually use.
2305 In general this is just CLASS; but on some machines
2306 in some cases it is preferable to use a more restrictive class. */
2308 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2309 ((CLASS) != ALL_REGS \
2310 ? (! TARGET_MIPS16 \
2312 : ((CLASS) != GR_REGS \
2315 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2316 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2317 ? (TARGET_SOFT_FLOAT \
2318 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2320 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2321 || GET_MODE (X) == VOIDmode) \
2322 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2325 /* Certain machines have the property that some registers cannot be
2326 copied to some other registers without using memory. Define this
2327 macro on those machines to be a C expression that is nonzero if
2328 objects of mode MODE in registers of CLASS1 can only be copied to
2329 registers of class CLASS2 by storing a register of CLASS1 into
2330 memory and loading that memory location into a register of CLASS2.
2332 Do not define this macro if its value would always be zero. */
2334 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2335 ((!TARGET_DEBUG_H_MODE \
2336 && GET_MODE_CLASS (MODE) == MODE_INT \
2337 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2338 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2339 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2340 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2341 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2343 /* The HI and LO registers can only be reloaded via the general
2344 registers. Condition code registers can only be loaded to the
2345 general registers, and from the floating point registers. */
2347 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2348 mips_secondary_reload_class (CLASS, MODE, X, 1)
2349 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2350 mips_secondary_reload_class (CLASS, MODE, X, 0)
2352 /* Return the maximum number of consecutive registers
2353 needed to represent mode MODE in a register of class CLASS. */
2355 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2357 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \
2358 mips_cannot_change_mode_class (FROM, TO)
2360 /* Stack layout; function entry, exit and calling. */
2362 /* Define this if pushing a word on the stack
2363 makes the stack pointer a smaller address. */
2364 #define STACK_GROWS_DOWNWARD
2366 /* Define this if the nominal address of the stack frame
2367 is at the high-address end of the local variables;
2368 that is, each additional local variable allocated
2369 goes at a more negative offset in the frame. */
2370 /* #define FRAME_GROWS_DOWNWARD */
2372 /* Offset within stack frame to start allocating local variables at.
2373 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2374 first local allocated. Otherwise, it is the offset to the BEGINNING
2375 of the first local allocated. */
2376 #define STARTING_FRAME_OFFSET \
2377 (current_function_outgoing_args_size \
2378 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2380 /* Offset from the stack pointer register to an item dynamically
2381 allocated on the stack, e.g., by `alloca'.
2383 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2384 length of the outgoing arguments. The default is correct for most
2385 machines. See `function.c' for details.
2387 The MIPS ABI states that functions which dynamically allocate the
2388 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2389 we are trying to create a second frame pointer to the function, so
2390 allocate some stack space to make it happy.
2392 However, the linker currently complains about linking any code that
2393 dynamically allocates stack space, and there seems to be a bug in
2394 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2397 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2398 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2399 ? 4*UNITS_PER_WORD \
2400 : current_function_outgoing_args_size)
2403 /* The return address for the current frame is in r31 if this is a leaf
2404 function. Otherwise, it is on the stack. It is at a variable offset
2405 from sp/fp/ap, so we define a fake hard register rap which is a
2406 poiner to the return address on the stack. This always gets eliminated
2407 during reload to be either the frame pointer or the stack pointer plus
2410 /* ??? This definition fails for leaf functions. There is currently no
2411 general solution for this problem. */
2413 /* ??? There appears to be no way to get the return address of any previous
2414 frame except by disassembling instructions in the prologue/epilogue.
2415 So currently we support only the current frame. */
2417 #define RETURN_ADDR_RTX(count, frame) \
2419 ? (leaf_function_p () \
2420 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
2421 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
2422 RETURN_ADDRESS_POINTER_REGNUM))) \
2425 /* Since the mips16 ISA mode is encoded in the least-significant bit
2426 of the address, mask it off return addresses for purposes of
2427 finding exception handling regions. */
2429 #define MASK_RETURN_ADDR GEN_INT (-2)
2431 /* Similarly, don't use the least-significant bit to tell pointers to
2432 code from vtable index. */
2434 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2436 /* If defined, this macro specifies a table of register pairs used to
2437 eliminate unneeded registers that point into the stack frame. If
2438 it is not defined, the only elimination attempted by the compiler
2439 is to replace references to the frame pointer with references to
2442 The definition of this macro is a list of structure
2443 initializations, each of which specifies an original and
2444 replacement register.
2446 On some machines, the position of the argument pointer is not
2447 known until the compilation is completed. In such a case, a
2448 separate hard register must be used for the argument pointer.
2449 This register can be eliminated by replacing it with either the
2450 frame pointer or the argument pointer, depending on whether or not
2451 the frame pointer has been eliminated.
2453 In this case, you might specify:
2454 #define ELIMINABLE_REGS \
2455 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2456 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2457 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2459 Note that the elimination of the argument pointer with the stack
2460 pointer is specified first since that is the preferred elimination.
2462 The eliminations to $17 are only used on the mips16. See the
2463 definition of HARD_FRAME_POINTER_REGNUM. */
2465 #define ELIMINABLE_REGS \
2466 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2467 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2468 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2469 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2470 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2471 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2472 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2473 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2474 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2476 /* A C expression that returns nonzero if the compiler is allowed to
2477 try to replace register number FROM-REG with register number
2478 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2479 defined, and will usually be the constant 1, since most of the
2480 cases preventing register elimination are things that the compiler
2481 already knows about.
2483 When not in mips16 and mips64, we can always eliminate to the
2484 frame pointer. We can eliminate to the stack pointer unless
2485 a frame pointer is needed. In mips16 mode, we need a frame
2486 pointer for a large frame; otherwise, reload may be unable
2487 to compute the address of a local variable, since there is
2488 no way to add a large constant to the stack pointer
2489 without using a temporary register.
2491 In mips16, for some instructions (eg lwu), we can't eliminate the
2492 frame pointer for the stack pointer. These instructions are
2493 only generated in TARGET_64BIT mode.
2496 #define CAN_ELIMINATE(FROM, TO) \
2497 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
2498 && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
2499 || (TO) == HARD_FRAME_POINTER_REGNUM)) \
2500 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2501 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2502 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2503 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2504 && (! TARGET_MIPS16 \
2505 || compute_frame_size (get_frame_size ()) < 32768)))))
2507 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2508 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2510 /* If we generate an insn to push BYTES bytes,
2511 this says how many the stack pointer really advances by.
2512 On the VAX, sp@- in a byte insn really pushes a word. */
2514 /* #define PUSH_ROUNDING(BYTES) 0 */
2516 /* If defined, the maximum amount of space required for outgoing
2517 arguments will be computed and placed into the variable
2518 `current_function_outgoing_args_size'. No space will be pushed
2519 onto the stack for each call; instead, the function prologue
2520 should increase the stack frame size by this amount.
2522 It is not proper to define both `PUSH_ROUNDING' and
2523 `ACCUMULATE_OUTGOING_ARGS'. */
2524 #define ACCUMULATE_OUTGOING_ARGS 1
2526 /* Offset from the argument pointer register to the first argument's
2527 address. On some machines it may depend on the data type of the
2530 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2531 the first argument's address.
2533 On the MIPS, we must skip the first argument position if we are
2534 returning a structure or a union, to account for its address being
2535 passed in $4. However, at the current time, this produces a compiler
2536 that can't bootstrap, so comment it out for now. */
2539 #define FIRST_PARM_OFFSET(FNDECL) \
2541 && TREE_TYPE (FNDECL) != 0 \
2542 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2543 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2544 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2548 #define FIRST_PARM_OFFSET(FNDECL) 0
2551 /* When a parameter is passed in a register, stack space is still
2552 allocated for it. For the MIPS, stack space must be allocated, cf
2553 Asm Lang Prog Guide page 7-8.
2555 BEWARE that some space is also allocated for non existing arguments
2556 in register. In case an argument list is of form GF used registers
2557 are a0 (a2,a3), but we should push over a1... */
2559 #define REG_PARM_STACK_SPACE(FNDECL) \
2560 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2561 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2564 /* Define this if it is the responsibility of the caller to
2565 allocate the area reserved for arguments passed in registers.
2566 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2567 of this macro is to determine whether the space is included in
2568 `current_function_outgoing_args_size'. */
2569 #define OUTGOING_REG_PARM_STACK_SPACE
2571 #define STACK_BOUNDARY \
2572 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2575 /* Make sure 4 words are always allocated on the stack. */
2577 #ifndef STACK_ARGS_ADJUST
2578 #define STACK_ARGS_ADJUST(SIZE) \
2580 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2581 SIZE.constant = 4 * UNITS_PER_WORD; \
2586 /* A C expression that should indicate the number of bytes of its
2587 own arguments that a function pops on returning, or 0
2588 if the function pops no arguments and the caller must therefore
2589 pop them all after the function returns.
2591 FUNDECL is the declaration node of the function (as a tree).
2593 FUNTYPE is a C variable whose value is a tree node that
2594 describes the function in question. Normally it is a node of
2595 type `FUNCTION_TYPE' that describes the data type of the function.
2596 From this it is possible to obtain the data types of the value
2597 and arguments (if known).
2599 When a call to a library function is being considered, FUNTYPE
2600 will contain an identifier node for the library function. Thus,
2601 if you need to distinguish among various library functions, you
2602 can do so by their names. Note that "library function" in this
2603 context means a function used to perform arithmetic, whose name
2604 is known specially in the compiler and was not mentioned in the
2605 C code being compiled.
2607 STACK-SIZE is the number of bytes of arguments passed on the
2608 stack. If a variable number of bytes is passed, it is zero, and
2609 argument popping will always be the responsibility of the
2610 calling function. */
2612 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2615 /* Symbolic macros for the registers used to return integer and floating
2618 #define GP_RETURN (GP_REG_FIRST + 2)
2619 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2621 #define MAX_ARGS_IN_REGISTERS \
2622 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2624 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2626 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2628 /* Symbolic macros for the first/last argument registers. */
2630 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2631 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2632 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2633 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2635 /* Define how to find the value returned by a library function
2636 assuming the value has mode MODE. Because we define
2637 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2638 PROMOTE_MODE does. */
2640 #define LIBCALL_VALUE(MODE) \
2641 mips_function_value (NULL_TREE, NULL, (MODE))
2643 /* Define how to find the value returned by a function.
2644 VALTYPE is the data type of the value (as a tree).
2645 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2646 otherwise, FUNC is 0. */
2648 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2649 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2651 /* 1 if N is a possible register number for a function value.
2652 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2653 Currently, R2 and F0 are only implemented here (C has no complex type) */
2655 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2657 /* 1 if N is a possible register number for function argument passing.
2658 We have no FP argument registers when soft-float. When FP registers
2659 are 32 bits, we can't directly reference the odd numbered ones. */
2661 #define FUNCTION_ARG_REGNO_P(N) \
2662 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2663 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2664 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2667 /* A C expression which can inhibit the returning of certain function
2668 values in registers, based on the type of value. A nonzero value says
2669 to return the function value in memory, just as large structures are
2670 always returned. Here TYPE will be a C expression of type
2671 `tree', representing the data type of the value.
2673 Note that values of mode `BLKmode' must be explicitly
2674 handled by this macro. Also, the option `-fpcc-struct-return'
2675 takes effect regardless of this macro. On most systems, it is
2676 possible to leave the macro undefined; this causes a default
2677 definition to be used, whose value is the constant 1 for BLKmode
2678 values, and 0 otherwise.
2680 GCC normally converts 1 byte structures into chars, 2 byte
2681 structs into shorts, and 4 byte structs into ints, and returns
2682 them this way. Defining the following macro overrides this,
2683 to give us MIPS cc compatibility. */
2685 #define RETURN_IN_MEMORY(TYPE) \
2686 mips_return_in_memory (TYPE)
2688 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2689 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2692 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2694 /* Define a data type for recording info about an argument list
2695 during the scan of that argument list. This data type should
2696 hold all necessary information about the function itself
2697 and about the args processed so far, enough to enable macros
2698 such as FUNCTION_ARG to determine where the next arg should go.
2700 This structure has to cope with two different argument allocation
2701 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2702 first N words go in registers and the rest go on the stack. If I < N,
2703 the Ith word might go in Ith integer argument register or the
2704 Ith floating-point one. In some cases, it has to go in both (see
2705 function_arg). For these ABIs, we only need to remember the number
2706 of words passed so far.
2708 The EABI instead allocates the integer and floating-point arguments
2709 separately. The first N words of FP arguments go in FP registers,
2710 the rest go on the stack. Likewise, the first N words of the other
2711 arguments go in integer registers, and the rest go on the stack. We
2712 need to maintain three counts: the number of integer registers used,
2713 the number of floating-point registers used, and the number of words
2714 passed on the stack.
2716 We could keep separate information for the two ABIs (a word count for
2717 the standard ABIs, and three separate counts for the EABI). But it
2718 seems simpler to view the standard ABIs as forms of EABI that do not
2719 allocate floating-point registers.
2721 So for the standard ABIs, the first N words are allocated to integer
2722 registers, and function_arg decides on an argument-by-argument basis
2723 whether that argument should really go in an integer register, or in
2724 a floating-point one. */
2726 typedef struct mips_args {
2727 /* Always true for varargs functions. Otherwise true if at least
2728 one argument has been passed in an integer register. */
2731 /* The number of arguments seen so far. */
2732 unsigned int arg_number;
2734 /* For EABI, the number of integer registers used so far. For other
2735 ABIs, the number of words passed in registers (whether integer
2736 or floating-point). */
2737 unsigned int num_gprs;
2739 /* For EABI, the number of floating-point registers used so far. */
2740 unsigned int num_fprs;
2742 /* The number of words passed on the stack. */
2743 unsigned int stack_words;
2745 /* On the mips16, we need to keep track of which floating point
2746 arguments were passed in general registers, but would have been
2747 passed in the FP regs if this were a 32 bit function, so that we
2748 can move them to the FP regs if we wind up calling a 32 bit
2749 function. We record this information in fp_code, encoded in base
2750 four. A zero digit means no floating point argument, a one digit
2751 means an SFmode argument, and a two digit means a DFmode argument,
2752 and a three digit is not used. The low order digit is the first
2753 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2754 an SFmode argument. ??? A more sophisticated approach will be
2755 needed if MIPS_ABI != ABI_32. */
2758 /* True if the function has a prototype. */
2761 /* When a structure does not take up a full register, the argument
2762 should sometimes be shifted left so that it occupies the high part
2763 of the register. These two fields describe an array of ashl
2764 patterns for doing this. See function_arg_advance, which creates
2765 the shift patterns, and function_arg, which returns them when given
2766 a VOIDmode argument. */
2767 unsigned int num_adjusts;
2768 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2771 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2772 for a call to a function whose data type is FNTYPE.
2773 For a library call, FNTYPE is 0.
2777 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2778 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2780 /* Update the data in CUM to advance over an argument
2781 of mode MODE and data type TYPE.
2782 (TYPE is null for libcalls where that information may not be available.) */
2784 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2785 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2787 /* Determine where to put an argument to a function.
2788 Value is zero to push the argument on the stack,
2789 or a hard register in which to store the argument.
2791 MODE is the argument's machine mode.
2792 TYPE is the data type of the argument (as a tree).
2793 This is null for libcalls where that information may
2795 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2796 the preceding args and about the function being called.
2797 NAMED is nonzero if this argument is a named parameter
2798 (otherwise it is an extra parameter matching an ellipsis). */
2800 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2801 function_arg( &CUM, MODE, TYPE, NAMED)
2803 /* For an arg passed partly in registers and partly in memory,
2804 this is the number of registers used.
2805 For args passed entirely in registers or entirely in memory, zero. */
2807 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2808 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2810 /* If defined, a C expression that gives the alignment boundary, in
2811 bits, of an argument with the specified mode and type. If it is
2812 not defined, `PARM_BOUNDARY' is used for all arguments. */
2814 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2816 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2818 : TYPE_ALIGN(TYPE)) \
2819 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2821 : GET_MODE_ALIGNMENT(MODE)))
2823 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2824 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2826 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2827 (! BYTES_BIG_ENDIAN \
2829 : (((MODE) == BLKmode \
2830 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2831 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2832 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2833 && (mips_abi == ABI_32 \
2834 || mips_abi == ABI_O64 \
2835 || mips_abi == ABI_EABI \
2836 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2837 ? downward : upward))
2839 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2840 (mips_abi == ABI_EABI && (NAMED) \
2841 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2843 /* Modified version of the macro in expr.h. */
2844 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2846 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2847 || TREE_ADDRESSABLE (TYPE) \
2848 || ((MODE) == BLKmode \
2849 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2850 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2851 && 0 == (int_size_in_bytes (TYPE) \
2852 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2853 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2854 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2856 /* True if using EABI and varargs can be passed in floating-point
2857 registers. Under these conditions, we need a more complex form
2858 of va_list, which tracks GPR, FPR and stack arguments separately. */
2859 #define EABI_FLOAT_VARARGS_P \
2860 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2863 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2865 #define MUST_SAVE_REGISTER(regno) \
2866 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2867 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2868 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2870 /* Treat LOC as a byte offset from the stack pointer and round it up
2871 to the next fully-aligned offset. */
2872 #define MIPS_STACK_ALIGN(LOC) \
2873 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2874 ? ((LOC) + 7) & ~7 \
2875 : ((LOC) + 15) & ~15)
2878 /* Define the `__builtin_va_list' type for the ABI. */
2879 #define BUILD_VA_LIST_TYPE(VALIST) \
2880 (VALIST) = mips_build_va_list ()
2882 /* Implement `va_start' for varargs and stdarg. */
2883 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2884 mips_va_start (valist, nextarg)
2886 /* Implement `va_arg'. */
2887 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2888 mips_va_arg (valist, type)
2890 /* Output assembler code to FILE to increment profiler label # LABELNO
2891 for profiling a function entry. */
2893 #define FUNCTION_PROFILER(FILE, LABELNO) \
2895 if (TARGET_MIPS16) \
2896 sorry ("mips16 function profiling"); \
2897 fprintf (FILE, "\t.set\tnoat\n"); \
2898 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2899 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2901 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2902 TARGET_64BIT ? "dsubu" : "subu", \
2903 reg_names[STACK_POINTER_REGNUM], \
2904 reg_names[STACK_POINTER_REGNUM], \
2905 Pmode == DImode ? 16 : 8); \
2906 fprintf (FILE, "\tjal\t_mcount\n"); \
2907 fprintf (FILE, "\t.set\tat\n"); \
2910 /* Define this macro if the code for function profiling should come
2911 before the function prologue. Normally, the profiling code comes
2914 /* #define PROFILE_BEFORE_PROLOGUE */
2916 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2917 the stack pointer does not matter. The value is tested only in
2918 functions that have frame pointers.
2919 No definition is equivalent to always zero. */
2921 #define EXIT_IGNORE_STACK 1
2924 /* A C statement to output, on the stream FILE, assembler code for a
2925 block of data that contains the constant parts of a trampoline.
2926 This code should not include a label--the label is taken care of
2929 #define TRAMPOLINE_TEMPLATE(STREAM) \
2931 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2932 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2933 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2934 if (Pmode == DImode) \
2936 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2937 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2941 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2942 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2944 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2945 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2946 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2947 if (Pmode == DImode) \
2949 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2950 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2954 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2955 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2959 /* A C expression for the size in bytes of the trampoline, as an
2962 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2964 /* Alignment required for trampolines, in bits. */
2966 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2968 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2969 program and data caches. */
2971 #ifndef CACHE_FLUSH_FUNC
2972 #define CACHE_FLUSH_FUNC "_flush_cache"
2975 /* A C statement to initialize the variable parts of a trampoline.
2976 ADDR is an RTX for the address of the trampoline; FNADDR is an
2977 RTX for the address of the nested function; STATIC_CHAIN is an
2978 RTX for the static chain value that should be passed to the
2979 function when it is called. */
2981 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2984 if (Pmode == DImode) \
2986 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2987 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2991 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2992 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2995 /* Flush both caches. We need to flush the data cache in case \
2996 the system has a write-back cache. */ \
2997 /* ??? Should check the return value for errors. */ \
2998 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2999 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
3000 0, VOIDmode, 3, addr, Pmode, \
3001 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
3002 GEN_INT (3), TYPE_MODE (integer_type_node)); \
3005 /* Addressing modes, and classification of registers for them. */
3007 /* These assume that REGNO is a hard or pseudo reg number.
3008 They give nonzero only if REGNO is a hard reg of the suitable class
3009 or a pseudo reg currently allocated to a suitable hard reg.
3010 These definitions are NOT overridden anywhere. */
3012 #define BASE_REG_P(regno, mode) \
3014 ? (M16_REG_P (regno) \
3015 || (regno) == FRAME_POINTER_REGNUM \
3016 || (regno) == ARG_POINTER_REGNUM \
3017 || ((regno) == STACK_POINTER_REGNUM \
3018 && (GET_MODE_SIZE (mode) == 4 \
3019 || GET_MODE_SIZE (mode) == 8))) \
3022 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
3023 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3026 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3027 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3029 #define REGNO_OK_FOR_INDEX_P(regno) 0
3030 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3031 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3033 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3034 and check its validity for a certain class.
3035 We have two alternate definitions for each of them.
3036 The usual definition accepts all pseudo regs; the other rejects them all.
3037 The symbol REG_OK_STRICT causes the latter definition to be used.
3039 Most source files want to accept pseudo regs in the hope that
3040 they will get allocated to the class that the insn wants them to be in.
3041 Some source files that are used after register allocation
3042 need to be strict. */
3044 #ifndef REG_OK_STRICT
3045 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3046 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3048 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3049 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3052 #define REG_OK_FOR_INDEX_P(X) 0
3055 /* Maximum number of registers that can appear in a valid memory address. */
3057 #define MAX_REGS_PER_ADDRESS 1
3059 /* A C compound statement with a conditional `goto LABEL;' executed
3060 if X (an RTX) is a legitimate memory address on the target
3061 machine for a memory operand of mode MODE. */
3064 #define GO_PRINTF(x) fprintf(stderr, (x))
3065 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3066 #define GO_DEBUG_RTX(x) debug_rtx(x)
3069 #define GO_PRINTF(x)
3070 #define GO_PRINTF2(x,y)
3071 #define GO_DEBUG_RTX(x)
3074 #ifdef REG_OK_STRICT
3075 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3077 if (mips_legitimate_address_p (MODE, X, 1)) \
3081 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3083 if (mips_legitimate_address_p (MODE, X, 0)) \
3088 /* A C expression that is 1 if the RTX X is a constant which is a
3089 valid address. This is defined to be the same as `CONSTANT_P (X)',
3090 but rejecting CONST_DOUBLE. */
3091 /* When pic, we must reject addresses of the form symbol+large int.
3092 This is because an instruction `sw $4,s+70000' needs to be converted
3093 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3094 assembler would use $at as a temp to load in the large offset. In this
3095 case $at is already in use. We convert such problem addresses to
3096 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3097 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them
3098 when !TARGET_GAS. */
3099 /* We should be rejecting everything but const addresses. */
3100 #define CONSTANT_ADDRESS_P(X) \
3101 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3102 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3103 || (GET_CODE (X) == CONST \
3104 && ! (flag_pic && pic_address_needs_scratch (X)) \
3106 && (mips_abi != ABI_N32 \
3107 && mips_abi != ABI_64)))
3110 /* Define this, so that when PIC, reload won't try to reload invalid
3111 addresses which require two reload registers. */
3113 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3115 /* Nonzero if the constant value X is a legitimate general operand.
3116 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3118 At present, GAS doesn't understand li.[sd], so don't allow it
3119 to be generated at present. Also, the MIPS assembler does not
3120 grok li.d Infinity. */
3122 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3123 Note that the Irix 6 assembler problem may already be fixed.
3124 Note also that the GET_CODE (X) == CONST test catches the mips16
3125 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3126 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3127 ABI_64 to work together, we'll need to fix this. */
3128 #define LEGITIMATE_CONSTANT_P(X) \
3129 ((GET_CODE (X) != CONST_DOUBLE \
3130 || mips_const_double_ok (X, GET_MODE (X))) \
3131 && ! (GET_CODE (X) == CONST \
3133 && (mips_abi == ABI_N32 \
3134 || mips_abi == ABI_64)) \
3135 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3137 /* A C compound statement that attempts to replace X with a valid
3138 memory address for an operand of mode MODE. WIN will be a C
3139 statement label elsewhere in the code; the macro definition may
3142 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3144 to avoid further processing if the address has become legitimate.
3146 X will always be the result of a call to `break_out_memory_refs',
3147 and OLDX will be the operand that was given to that function to
3150 The code generated by this macro should not alter the
3151 substructure of X. If it transforms X into a more legitimate
3152 form, it should assign X (which will always be a C variable) a
3155 It is not necessary for this macro to come up with a legitimate
3156 address. The compiler has standard ways of doing so in all
3157 cases. In fact, it is safe for this macro to do nothing. But
3158 often a machine-dependent strategy can generate better code.
3160 For the MIPS, transform:
3162 memory(X + <large int>)
3166 Y = <large int> & ~0x7fff;
3168 memory (Z + (<large int> & 0x7fff));
3170 This is for CSE to find several similar references, and only use one Z.
3172 When PIC, convert addresses of the form memory (symbol+large int) to
3173 memory (reg+large int). */
3176 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3178 register rtx xinsn = (X); \
3180 if (TARGET_DEBUG_B_MODE) \
3182 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3183 GO_DEBUG_RTX (xinsn); \
3186 if (mips_split_addresses && mips_check_split (X, MODE)) \
3188 /* ??? Is this ever executed? */ \
3189 X = gen_rtx_LO_SUM (Pmode, \
3190 copy_to_mode_reg (Pmode, \
3191 gen_rtx (HIGH, Pmode, X)), \
3196 if (GET_CODE (xinsn) == CONST \
3197 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3198 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3200 && (mips_abi == ABI_N32 \
3201 || mips_abi == ABI_64)))) \
3203 rtx ptr_reg = gen_reg_rtx (Pmode); \
3204 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3206 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3208 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3209 if (SMALL_INT (constant)) \
3211 /* Otherwise we fall through so the code below will fix the \
3216 if (GET_CODE (xinsn) == PLUS) \
3218 register rtx xplus0 = XEXP (xinsn, 0); \
3219 register rtx xplus1 = XEXP (xinsn, 1); \
3220 register enum rtx_code code0 = GET_CODE (xplus0); \
3221 register enum rtx_code code1 = GET_CODE (xplus1); \
3223 if (code0 != REG && code1 == REG) \
3225 xplus0 = XEXP (xinsn, 1); \
3226 xplus1 = XEXP (xinsn, 0); \
3227 code0 = GET_CODE (xplus0); \
3228 code1 = GET_CODE (xplus1); \
3231 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3232 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3234 rtx int_reg = gen_reg_rtx (Pmode); \
3235 rtx ptr_reg = gen_reg_rtx (Pmode); \
3237 emit_move_insn (int_reg, \
3238 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3240 emit_insn (gen_rtx_SET (VOIDmode, \
3242 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3244 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3249 if (TARGET_DEBUG_B_MODE) \
3250 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3254 /* A C statement or compound statement with a conditional `goto
3255 LABEL;' executed if memory address X (an RTX) can have different
3256 meanings depending on the machine mode of the memory reference it
3259 Autoincrement and autodecrement addresses typically have
3260 mode-dependent effects because the amount of the increment or
3261 decrement is the size of the operand being addressed. Some
3262 machines have other mode-dependent addresses. Many RISC machines
3263 have no mode-dependent addresses.
3265 You may assume that ADDR is a valid address for the machine. */
3267 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3269 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3270 'the start of the function that this code is output in'. */
3272 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3273 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3274 asm_fprintf ((FILE), "%U%s", \
3275 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3277 asm_fprintf ((FILE), "%U%s", (NAME))
3279 /* The mips16 wants the constant pool to be after the function,
3280 because the PC relative load instructions use unsigned offsets. */
3282 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3284 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3285 mips_string_length = 0;
3288 /* In mips16 mode, put most string constants after the function. */
3289 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3290 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3293 /* Specify the machine mode that this machine uses
3294 for the index in the tablejump instruction.
3295 ??? Using HImode in mips16 mode can cause overflow. However, the
3296 overflow is no more likely than the overflow in a branch
3297 instruction. Large functions can currently break in both ways. */
3298 #define CASE_VECTOR_MODE \
3299 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3301 /* Define as C expression which evaluates to nonzero if the tablejump
3302 instruction expects the table to contain offsets from the address of the
3304 Do not define this if the table should contain absolute addresses. */
3305 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3307 /* Define this as 1 if `char' should by default be signed; else as 0. */
3308 #ifndef DEFAULT_SIGNED_CHAR
3309 #define DEFAULT_SIGNED_CHAR 1
3312 /* Max number of bytes we can move from memory to memory
3313 in one reasonably fast instruction. */
3314 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3315 #define MAX_MOVE_MAX 8
3317 /* Define this macro as a C expression which is nonzero if
3318 accessing less than a word of memory (i.e. a `char' or a
3319 `short') is no faster than accessing a word of memory, i.e., if
3320 such access require more than one instruction or if there is no
3321 difference in cost between byte and (aligned) word loads.
3323 On RISC machines, it tends to generate better code to define
3324 this as 1, since it avoids making a QI or HI mode register. */
3325 #define SLOW_BYTE_ACCESS 1
3327 /* We assume that the store-condition-codes instructions store 0 for false
3328 and some other value for true. This is the value stored for true. */
3330 #define STORE_FLAG_VALUE 1
3332 /* Define this to be nonzero if shift instructions ignore all but the low-order
3334 #define SHIFT_COUNT_TRUNCATED 1
3336 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3337 is done just by pretending it is already truncated. */
3338 /* In 64 bit mode, 32 bit instructions require that register values be properly
3339 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3340 converts a value >32 bits to a value <32 bits. */
3341 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3342 Something needs to be done about this. Perhaps not use any 32 bit
3343 instructions? Perhaps use PROMOTE_MODE? */
3344 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3345 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3347 /* Specify the machine mode that pointers have.
3348 After generation of rtl, the compiler makes no further distinction
3349 between pointers and any other objects of this machine mode.
3351 For MIPS we make pointers are the smaller of longs and gp-registers. */
3354 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3357 /* A function address in a call instruction
3358 is a word address (for indexing purposes)
3359 so give the MEM rtx a words's mode. */
3361 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3364 /* A part of a C `switch' statement that describes the relative
3365 costs of constant RTL expressions. It must contain `case'
3366 labels for expression codes `const_int', `const', `symbol_ref',
3367 `label_ref' and `const_double'. Each case must ultimately reach
3368 a `return' statement to return the relative cost of the use of
3369 that kind of constant value in an expression. The cost may
3370 depend on the precise value of the constant, which is available
3371 for examination in X.
3373 CODE is the expression code--redundant, since it can be obtained
3374 with `GET_CODE (X)'. */
3376 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3378 if (! TARGET_MIPS16) \
3380 /* Always return 0, since we don't have different sized \
3381 instructions, hence different costs according to Richard \
3385 if ((OUTER_CODE) == SET) \
3387 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3389 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3390 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3391 return COSTS_N_INSNS (1); \
3393 return COSTS_N_INSNS (2); \
3395 /* A PLUS could be an address. We don't want to force an address \
3396 to use a register, so accept any signed 16 bit value without \
3398 if ((OUTER_CODE) == PLUS \
3399 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3401 /* A number between 1 and 8 inclusive is efficient for a shift. \
3402 Otherwise, we will need an extended instruction. */ \
3403 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3404 || (OUTER_CODE) == LSHIFTRT) \
3406 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3408 return COSTS_N_INSNS (1); \
3410 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3411 if ((OUTER_CODE) == XOR \
3412 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3414 /* We may be able to use slt or sltu for a comparison with a \
3415 signed 16 bit value. (The boundary conditions aren't quite \
3416 right, but this is just a heuristic anyhow.) */ \
3417 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3418 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3419 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3420 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3421 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3423 /* Equality comparisons with 0 are cheap. */ \
3424 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3425 && INTVAL (X) == 0) \
3428 /* Otherwise, work out the cost to load the value into a \
3430 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3431 return COSTS_N_INSNS (1); \
3432 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3433 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3434 return COSTS_N_INSNS (2); \
3436 return COSTS_N_INSNS (3); \
3439 return COSTS_N_INSNS (2); \
3443 rtx offset = const0_rtx; \
3444 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3446 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3448 /* Treat this like a signed 16 bit CONST_INT. */ \
3449 if ((OUTER_CODE) == PLUS) \
3451 else if ((OUTER_CODE) == SET) \
3452 return COSTS_N_INSNS (1); \
3454 return COSTS_N_INSNS (2); \
3457 if (GET_CODE (symref) == LABEL_REF) \
3458 return COSTS_N_INSNS (2); \
3460 if (GET_CODE (symref) != SYMBOL_REF) \
3461 return COSTS_N_INSNS (4); \
3463 /* let's be paranoid.... */ \
3464 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3465 return COSTS_N_INSNS (2); \
3467 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3471 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3473 case CONST_DOUBLE: \
3476 if (TARGET_MIPS16) \
3477 return COSTS_N_INSNS (4); \
3478 split_double (X, &high, &low); \
3479 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3480 || low == CONST0_RTX (GET_MODE (low))) \
3484 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3485 This can be used, for example, to indicate how costly a multiply
3486 instruction is. In writing this macro, you can use the construct
3487 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3489 This macro is optional; do not define it if the default cost
3490 assumptions are adequate for the target machine.
3492 If -mdebugd is used, change the multiply cost to 2, so multiply by
3493 a constant isn't converted to a series of shifts. This helps
3494 strength reduction, and also makes it easier to identify what the
3495 compiler is doing. */
3497 /* ??? Fix this to be right for the R8000. */
3498 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3501 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3502 if (simple_memory_operand (X, GET_MODE (X))) \
3503 return COSTS_N_INSNS (num_words); \
3505 return COSTS_N_INSNS (2*num_words); \
3509 return COSTS_N_INSNS (6); \
3512 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3517 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3518 return COSTS_N_INSNS (2); \
3525 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3526 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3532 enum machine_mode xmode = GET_MODE (X); \
3533 if (xmode == SFmode || xmode == DFmode) \
3534 return COSTS_N_INSNS (1); \
3536 return COSTS_N_INSNS (4); \
3542 enum machine_mode xmode = GET_MODE (X); \
3543 if (xmode == SFmode || xmode == DFmode) \
3547 return COSTS_N_INSNS (2); \
3548 else if (TUNE_MIPS6000) \
3549 return COSTS_N_INSNS (3); \
3551 return COSTS_N_INSNS (6); \
3554 if (xmode == DImode && !TARGET_64BIT) \
3555 return COSTS_N_INSNS (4); \
3561 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3568 enum machine_mode xmode = GET_MODE (X); \
3569 if (xmode == SFmode) \
3574 return COSTS_N_INSNS (4); \
3575 else if (TUNE_MIPS6000 \
3578 return COSTS_N_INSNS (5); \
3580 return COSTS_N_INSNS (7); \
3583 if (xmode == DFmode) \
3588 return COSTS_N_INSNS (5); \
3589 else if (TUNE_MIPS6000 \
3592 return COSTS_N_INSNS (6); \
3594 return COSTS_N_INSNS (8); \
3597 if (TUNE_MIPS3000) \
3598 return COSTS_N_INSNS (12); \
3599 else if (TUNE_MIPS3900) \
3600 return COSTS_N_INSNS (2); \
3601 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3602 return COSTS_N_INSNS ((xmode == DImode) ? 4 : 3); \
3603 else if (TUNE_MIPS6000) \
3604 return COSTS_N_INSNS (17); \
3605 else if (TUNE_MIPS5000) \
3606 return COSTS_N_INSNS (5); \
3608 return COSTS_N_INSNS (10); \
3614 enum machine_mode xmode = GET_MODE (X); \
3615 if (xmode == SFmode) \
3619 return COSTS_N_INSNS (12); \
3620 else if (TUNE_MIPS6000) \
3621 return COSTS_N_INSNS (15); \
3622 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3623 return COSTS_N_INSNS (30); \
3625 return COSTS_N_INSNS (23); \
3628 if (xmode == DFmode) \
3632 return COSTS_N_INSNS (19); \
3633 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3634 return COSTS_N_INSNS (59); \
3635 else if (TUNE_MIPS6000) \
3636 return COSTS_N_INSNS (16); \
3638 return COSTS_N_INSNS (36); \
3641 /* fall through */ \
3647 return COSTS_N_INSNS (35); \
3648 else if (TUNE_MIPS6000) \
3649 return COSTS_N_INSNS (38); \
3650 else if (TUNE_MIPS5000) \
3651 return COSTS_N_INSNS (36); \
3652 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3653 return COSTS_N_INSNS ((GET_MODE (X) == SImode) ? 42 : 74); \
3655 return COSTS_N_INSNS (69); \
3658 /* A sign extend from SImode to DImode in 64 bit mode is often \
3659 zero instructions, because the result can often be used \
3660 directly by another instruction; we'll call it one. */ \
3661 if (TARGET_64BIT && GET_MODE (X) == DImode \
3662 && GET_MODE (XEXP (X, 0)) == SImode) \
3663 return COSTS_N_INSNS (1); \
3665 return COSTS_N_INSNS (2); \
3668 if (TARGET_64BIT && GET_MODE (X) == DImode \
3669 && GET_MODE (XEXP (X, 0)) == SImode) \
3670 return COSTS_N_INSNS (2); \
3672 return COSTS_N_INSNS (1);
3674 /* An expression giving the cost of an addressing mode that
3675 contains ADDRESS. If not defined, the cost is computed from the
3676 form of the ADDRESS expression and the `CONST_COSTS' values.
3678 For most CISC machines, the default cost is a good approximation
3679 of the true cost of the addressing mode. However, on RISC
3680 machines, all instructions normally have the same length and
3681 execution time. Hence all addresses will have equal costs.
3683 In cases where more than one form of an address is known, the
3684 form with the lowest cost will be used. If multiple forms have
3685 the same, lowest, cost, the one that is the most complex will be
3688 For example, suppose an address that is equal to the sum of a
3689 register and a constant is used twice in the same basic block.
3690 When this macro is not defined, the address will be computed in
3691 a register and memory references will be indirect through that
3692 register. On machines where the cost of the addressing mode
3693 containing the sum is no higher than that of a simple indirect
3694 reference, this will produce an additional instruction and
3695 possibly require an additional register. Proper specification
3696 of this macro eliminates this overhead for such machines.
3698 Similar use of this macro is made in strength reduction of loops.
3700 ADDRESS need not be valid as an address. In such a case, the
3701 cost is not relevant and can be any value; invalid addresses
3702 need not be assigned a different cost.
3704 On machines where an address involving more than one register is
3705 as cheap as an address computation involving only one register,
3706 defining `ADDRESS_COST' to reflect this can cause two registers
3707 to be live over a region of code where only one would have been
3708 if `ADDRESS_COST' were not defined in that manner. This effect
3709 should be considered in the definition of this macro.
3710 Equivalent costs should probably only be given to addresses with
3711 different numbers of registers on machines with lots of registers.
3713 This macro will normally either not be defined or be defined as
3716 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3718 /* A C expression for the cost of moving data from a register in
3719 class FROM to one in class TO. The classes are expressed using
3720 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3721 the default; other values are interpreted relative to that.
3723 It is not required that the cost always equal 2 when FROM is the
3724 same as TO; on some machines it is expensive to move between
3725 registers if they are not general registers.
3727 If reload sees an insn consisting of a single `set' between two
3728 hard registers, and if `REGISTER_MOVE_COST' applied to their
3729 classes returns a value of 2, reload does not check to ensure
3730 that the constraints of the insn are met. Setting a cost of
3731 other than 2 will allow reload to verify that the constraints are
3732 met. You should do this if the `movM' pattern's constraints do
3733 not allow such copying. */
3735 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3736 mips_register_move_cost (MODE, FROM, TO)
3738 /* ??? Fix this to be right for the R8000. */
3739 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3740 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3741 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3743 /* Define if copies to/from condition code registers should be avoided.
3745 This is needed for the MIPS because reload_outcc is not complete;
3746 it needs to handle cases where the source is a general or another
3747 condition code register. */
3748 #define AVOID_CCMODE_COPIES
3750 /* A C expression for the cost of a branch instruction. A value of
3751 1 is the default; other values are interpreted relative to that. */
3753 /* ??? Fix this to be right for the R8000. */
3754 #define BRANCH_COST \
3756 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3759 /* If defined, modifies the length assigned to instruction INSN as a
3760 function of the context in which it is used. LENGTH is an lvalue
3761 that contains the initially computed length of the insn and should
3762 be updated with the correct length of the insn. */
3763 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3764 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3767 /* Optionally define this if you have added predicates to
3768 `MACHINE.c'. This macro is called within an initializer of an
3769 array of structures. The first field in the structure is the
3770 name of a predicate and the second field is an array of rtl
3771 codes. For each predicate, list all rtl codes that can be in
3772 expressions matched by the predicate. The list should have a
3773 trailing comma. Here is an example of two entries in the list
3774 for a typical RISC machine:
3776 #define PREDICATE_CODES \
3777 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3778 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3780 Defining this macro does not affect the generated code (however,
3781 incorrect definitions that omit an rtl code that may be matched
3782 by the predicate can cause the compiler to malfunction).
3783 Instead, it allows the table built by `genrecog' to be more
3784 compact and efficient, thus speeding up the compiler. The most
3785 important predicates to include in the list specified by this
3786 macro are thoses used in the most insn patterns. */
3788 #define PREDICATE_CODES \
3789 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3790 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3791 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3792 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3793 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3794 {"small_int", { CONST_INT }}, \
3795 {"large_int", { CONST_INT }}, \
3796 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3797 {"const_float_1_operand", { CONST_DOUBLE }}, \
3798 {"simple_memory_operand", { MEM, SUBREG }}, \
3799 {"equality_op", { EQ, NE }}, \
3800 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3802 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3803 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3804 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3805 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3806 SYMBOL_REF, LABEL_REF, SUBREG, \
3808 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3809 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3810 MEM, SIGN_EXTEND }}, \
3811 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3812 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3814 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3816 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3818 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3819 SYMBOL_REF, LABEL_REF, SUBREG, \
3820 REG, SIGN_EXTEND }}, \
3821 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3822 CONST_DOUBLE, CONST }}, \
3823 {"fcc_register_operand", { REG, SUBREG }}, \
3824 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3825 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3827 /* A list of predicates that do special things with modes, and so
3828 should not elicit warnings for VOIDmode match_operand. */
3830 #define SPECIAL_MODE_PREDICATES \
3831 "pc_or_label_operand",
3834 /* If defined, a C statement to be executed just prior to the
3835 output of assembler code for INSN, to modify the extracted
3836 operands so they will be output differently.
3838 Here the argument OPVEC is the vector containing the operands
3839 extracted from INSN, and NOPERANDS is the number of elements of
3840 the vector which contain meaningful data for this insn. The
3841 contents of this vector are what will be used to convert the
3842 insn template into assembler code, so you can change the
3843 assembler output by changing the contents of the vector.
3845 We use it to check if the current insn needs a nop in front of it
3846 because of load delays, and also to update the delay slot
3849 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3850 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3853 /* Control the assembler format that we output. */
3855 /* Output at beginning of assembler file.
3856 If we are optimizing to use the global pointer, create a temporary
3857 file to hold all of the text stuff, and write it out to the end.
3858 This is needed because the MIPS assembler is evidently one pass,
3859 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3860 declaration when the code is processed, it generates a two
3861 instruction sequence. */
3863 #undef ASM_FILE_START
3864 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3866 /* Output to assembler file text saying following lines
3867 may contain character constants, extra white space, comments, etc. */
3870 #define ASM_APP_ON " #APP\n"
3873 /* Output to assembler file text saying following lines
3874 no longer contain unusual constructs. */
3877 #define ASM_APP_OFF " #NO_APP\n"
3880 /* How to refer to registers in assembler output.
3881 This sequence is indexed by compiler's hard-register-number (see above).
3883 In order to support the two different conventions for register names,
3884 we use the name of a table set up in mips.c, which is overwritten
3885 if -mrnames is used. */
3887 #define REGISTER_NAMES \
3889 &mips_reg_names[ 0][0], \
3890 &mips_reg_names[ 1][0], \
3891 &mips_reg_names[ 2][0], \
3892 &mips_reg_names[ 3][0], \
3893 &mips_reg_names[ 4][0], \
3894 &mips_reg_names[ 5][0], \
3895 &mips_reg_names[ 6][0], \
3896 &mips_reg_names[ 7][0], \
3897 &mips_reg_names[ 8][0], \
3898 &mips_reg_names[ 9][0], \
3899 &mips_reg_names[10][0], \
3900 &mips_reg_names[11][0], \
3901 &mips_reg_names[12][0], \
3902 &mips_reg_names[13][0], \
3903 &mips_reg_names[14][0], \
3904 &mips_reg_names[15][0], \
3905 &mips_reg_names[16][0], \
3906 &mips_reg_names[17][0], \
3907 &mips_reg_names[18][0], \
3908 &mips_reg_names[19][0], \
3909 &mips_reg_names[20][0], \
3910 &mips_reg_names[21][0], \
3911 &mips_reg_names[22][0], \
3912 &mips_reg_names[23][0], \
3913 &mips_reg_names[24][0], \
3914 &mips_reg_names[25][0], \
3915 &mips_reg_names[26][0], \
3916 &mips_reg_names[27][0], \
3917 &mips_reg_names[28][0], \
3918 &mips_reg_names[29][0], \
3919 &mips_reg_names[30][0], \
3920 &mips_reg_names[31][0], \
3921 &mips_reg_names[32][0], \
3922 &mips_reg_names[33][0], \
3923 &mips_reg_names[34][0], \
3924 &mips_reg_names[35][0], \
3925 &mips_reg_names[36][0], \
3926 &mips_reg_names[37][0], \
3927 &mips_reg_names[38][0], \
3928 &mips_reg_names[39][0], \
3929 &mips_reg_names[40][0], \
3930 &mips_reg_names[41][0], \
3931 &mips_reg_names[42][0], \
3932 &mips_reg_names[43][0], \
3933 &mips_reg_names[44][0], \
3934 &mips_reg_names[45][0], \
3935 &mips_reg_names[46][0], \
3936 &mips_reg_names[47][0], \
3937 &mips_reg_names[48][0], \
3938 &mips_reg_names[49][0], \
3939 &mips_reg_names[50][0], \
3940 &mips_reg_names[51][0], \
3941 &mips_reg_names[52][0], \
3942 &mips_reg_names[53][0], \
3943 &mips_reg_names[54][0], \
3944 &mips_reg_names[55][0], \
3945 &mips_reg_names[56][0], \
3946 &mips_reg_names[57][0], \
3947 &mips_reg_names[58][0], \
3948 &mips_reg_names[59][0], \
3949 &mips_reg_names[60][0], \
3950 &mips_reg_names[61][0], \
3951 &mips_reg_names[62][0], \
3952 &mips_reg_names[63][0], \
3953 &mips_reg_names[64][0], \
3954 &mips_reg_names[65][0], \
3955 &mips_reg_names[66][0], \
3956 &mips_reg_names[67][0], \
3957 &mips_reg_names[68][0], \
3958 &mips_reg_names[69][0], \
3959 &mips_reg_names[70][0], \
3960 &mips_reg_names[71][0], \
3961 &mips_reg_names[72][0], \
3962 &mips_reg_names[73][0], \
3963 &mips_reg_names[74][0], \
3964 &mips_reg_names[75][0], \
3965 &mips_reg_names[76][0], \
3966 &mips_reg_names[77][0], \
3967 &mips_reg_names[78][0], \
3968 &mips_reg_names[79][0], \
3969 &mips_reg_names[80][0], \
3970 &mips_reg_names[81][0], \
3971 &mips_reg_names[82][0], \
3972 &mips_reg_names[83][0], \
3973 &mips_reg_names[84][0], \
3974 &mips_reg_names[85][0], \
3975 &mips_reg_names[86][0], \
3976 &mips_reg_names[87][0], \
3977 &mips_reg_names[88][0], \
3978 &mips_reg_names[89][0], \
3979 &mips_reg_names[90][0], \
3980 &mips_reg_names[91][0], \
3981 &mips_reg_names[92][0], \
3982 &mips_reg_names[93][0], \
3983 &mips_reg_names[94][0], \
3984 &mips_reg_names[95][0], \
3985 &mips_reg_names[96][0], \
3986 &mips_reg_names[97][0], \
3987 &mips_reg_names[98][0], \
3988 &mips_reg_names[99][0], \
3989 &mips_reg_names[100][0], \
3990 &mips_reg_names[101][0], \
3991 &mips_reg_names[102][0], \
3992 &mips_reg_names[103][0], \
3993 &mips_reg_names[104][0], \
3994 &mips_reg_names[105][0], \
3995 &mips_reg_names[106][0], \
3996 &mips_reg_names[107][0], \
3997 &mips_reg_names[108][0], \
3998 &mips_reg_names[109][0], \
3999 &mips_reg_names[110][0], \
4000 &mips_reg_names[111][0], \
4001 &mips_reg_names[112][0], \
4002 &mips_reg_names[113][0], \
4003 &mips_reg_names[114][0], \
4004 &mips_reg_names[115][0], \
4005 &mips_reg_names[116][0], \
4006 &mips_reg_names[117][0], \
4007 &mips_reg_names[118][0], \
4008 &mips_reg_names[119][0], \
4009 &mips_reg_names[120][0], \
4010 &mips_reg_names[121][0], \
4011 &mips_reg_names[122][0], \
4012 &mips_reg_names[123][0], \
4013 &mips_reg_names[124][0], \
4014 &mips_reg_names[125][0], \
4015 &mips_reg_names[126][0], \
4016 &mips_reg_names[127][0], \
4017 &mips_reg_names[128][0], \
4018 &mips_reg_names[129][0], \
4019 &mips_reg_names[130][0], \
4020 &mips_reg_names[131][0], \
4021 &mips_reg_names[132][0], \
4022 &mips_reg_names[133][0], \
4023 &mips_reg_names[134][0], \
4024 &mips_reg_names[135][0], \
4025 &mips_reg_names[136][0], \
4026 &mips_reg_names[137][0], \
4027 &mips_reg_names[138][0], \
4028 &mips_reg_names[139][0], \
4029 &mips_reg_names[140][0], \
4030 &mips_reg_names[141][0], \
4031 &mips_reg_names[142][0], \
4032 &mips_reg_names[143][0], \
4033 &mips_reg_names[144][0], \
4034 &mips_reg_names[145][0], \
4035 &mips_reg_names[146][0], \
4036 &mips_reg_names[147][0], \
4037 &mips_reg_names[148][0], \
4038 &mips_reg_names[149][0], \
4039 &mips_reg_names[150][0], \
4040 &mips_reg_names[151][0], \
4041 &mips_reg_names[152][0], \
4042 &mips_reg_names[153][0], \
4043 &mips_reg_names[154][0], \
4044 &mips_reg_names[155][0], \
4045 &mips_reg_names[156][0], \
4046 &mips_reg_names[157][0], \
4047 &mips_reg_names[158][0], \
4048 &mips_reg_names[159][0], \
4049 &mips_reg_names[160][0], \
4050 &mips_reg_names[161][0], \
4051 &mips_reg_names[162][0], \
4052 &mips_reg_names[163][0], \
4053 &mips_reg_names[164][0], \
4054 &mips_reg_names[165][0], \
4055 &mips_reg_names[166][0], \
4056 &mips_reg_names[167][0], \
4057 &mips_reg_names[168][0], \
4058 &mips_reg_names[169][0], \
4059 &mips_reg_names[170][0], \
4060 &mips_reg_names[171][0], \
4061 &mips_reg_names[172][0], \
4062 &mips_reg_names[173][0], \
4063 &mips_reg_names[174][0], \
4064 &mips_reg_names[175][0] \
4067 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4068 So define this for it. */
4069 #define DEBUG_REGISTER_NAMES \
4071 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4072 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4073 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4074 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4075 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4076 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4077 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4078 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4079 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4080 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
4081 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
4082 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
4083 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
4084 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
4085 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
4086 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
4087 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
4088 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
4089 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
4090 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
4091 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
4092 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
4095 /* If defined, a C initializer for an array of structures
4096 containing a name and a register number. This macro defines
4097 additional names for hard registers, thus allowing the `asm'
4098 option in declarations to refer to registers using alternate
4101 We define both names for the integer registers here. */
4103 #define ADDITIONAL_REGISTER_NAMES \
4105 { "$0", 0 + GP_REG_FIRST }, \
4106 { "$1", 1 + GP_REG_FIRST }, \
4107 { "$2", 2 + GP_REG_FIRST }, \
4108 { "$3", 3 + GP_REG_FIRST }, \
4109 { "$4", 4 + GP_REG_FIRST }, \
4110 { "$5", 5 + GP_REG_FIRST }, \
4111 { "$6", 6 + GP_REG_FIRST }, \
4112 { "$7", 7 + GP_REG_FIRST }, \
4113 { "$8", 8 + GP_REG_FIRST }, \
4114 { "$9", 9 + GP_REG_FIRST }, \
4115 { "$10", 10 + GP_REG_FIRST }, \
4116 { "$11", 11 + GP_REG_FIRST }, \
4117 { "$12", 12 + GP_REG_FIRST }, \
4118 { "$13", 13 + GP_REG_FIRST }, \
4119 { "$14", 14 + GP_REG_FIRST }, \
4120 { "$15", 15 + GP_REG_FIRST }, \
4121 { "$16", 16 + GP_REG_FIRST }, \
4122 { "$17", 17 + GP_REG_FIRST }, \
4123 { "$18", 18 + GP_REG_FIRST }, \
4124 { "$19", 19 + GP_REG_FIRST }, \
4125 { "$20", 20 + GP_REG_FIRST }, \
4126 { "$21", 21 + GP_REG_FIRST }, \
4127 { "$22", 22 + GP_REG_FIRST }, \
4128 { "$23", 23 + GP_REG_FIRST }, \
4129 { "$24", 24 + GP_REG_FIRST }, \
4130 { "$25", 25 + GP_REG_FIRST }, \
4131 { "$26", 26 + GP_REG_FIRST }, \
4132 { "$27", 27 + GP_REG_FIRST }, \
4133 { "$28", 28 + GP_REG_FIRST }, \
4134 { "$29", 29 + GP_REG_FIRST }, \
4135 { "$30", 30 + GP_REG_FIRST }, \
4136 { "$31", 31 + GP_REG_FIRST }, \
4137 { "$sp", 29 + GP_REG_FIRST }, \
4138 { "$fp", 30 + GP_REG_FIRST }, \
4139 { "at", 1 + GP_REG_FIRST }, \
4140 { "v0", 2 + GP_REG_FIRST }, \
4141 { "v1", 3 + GP_REG_FIRST }, \
4142 { "a0", 4 + GP_REG_FIRST }, \
4143 { "a1", 5 + GP_REG_FIRST }, \
4144 { "a2", 6 + GP_REG_FIRST }, \
4145 { "a3", 7 + GP_REG_FIRST }, \
4146 { "t0", 8 + GP_REG_FIRST }, \
4147 { "t1", 9 + GP_REG_FIRST }, \
4148 { "t2", 10 + GP_REG_FIRST }, \
4149 { "t3", 11 + GP_REG_FIRST }, \
4150 { "t4", 12 + GP_REG_FIRST }, \
4151 { "t5", 13 + GP_REG_FIRST }, \
4152 { "t6", 14 + GP_REG_FIRST }, \
4153 { "t7", 15 + GP_REG_FIRST }, \
4154 { "s0", 16 + GP_REG_FIRST }, \
4155 { "s1", 17 + GP_REG_FIRST }, \
4156 { "s2", 18 + GP_REG_FIRST }, \
4157 { "s3", 19 + GP_REG_FIRST }, \
4158 { "s4", 20 + GP_REG_FIRST }, \
4159 { "s5", 21 + GP_REG_FIRST }, \
4160 { "s6", 22 + GP_REG_FIRST }, \
4161 { "s7", 23 + GP_REG_FIRST }, \
4162 { "t8", 24 + GP_REG_FIRST }, \
4163 { "t9", 25 + GP_REG_FIRST }, \
4164 { "k0", 26 + GP_REG_FIRST }, \
4165 { "k1", 27 + GP_REG_FIRST }, \
4166 { "gp", 28 + GP_REG_FIRST }, \
4167 { "sp", 29 + GP_REG_FIRST }, \
4168 { "fp", 30 + GP_REG_FIRST }, \
4169 { "ra", 31 + GP_REG_FIRST }, \
4170 { "$sp", 29 + GP_REG_FIRST }, \
4171 { "$fp", 30 + GP_REG_FIRST } \
4172 ALL_COP_ADDITIONAL_REGISTER_NAMES \
4175 /* This is meant to be redefined in the host dependent files. It is a
4176 set of alternative names and regnums for mips coprocessors. */
4178 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
4180 /* A C compound statement to output to stdio stream STREAM the
4181 assembler syntax for an instruction operand X. X is an RTL
4184 CODE is a value that can be used to specify one of several ways
4185 of printing the operand. It is used when identical operands
4186 must be printed differently depending on the context. CODE
4187 comes from the `%' specification that was used to request
4188 printing of the operand. If the specification was just `%DIGIT'
4189 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4190 is the ASCII code for LTR.
4192 If X is a register, this macro should print the register's name.
4193 The names can be found in an array `reg_names' whose type is
4194 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4196 When the machine description has a specification `%PUNCT' (a `%'
4197 followed by a punctuation character), this macro is called with
4198 a null pointer for X and the punctuation character for CODE.
4200 See mips.c for the MIPS specific codes. */
4202 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4204 /* A C expression which evaluates to true if CODE is a valid
4205 punctuation character for use in the `PRINT_OPERAND' macro. If
4206 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4207 punctuation characters (except for the standard one, `%') are
4208 used in this way. */
4210 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4212 /* A C compound statement to output to stdio stream STREAM the
4213 assembler syntax for an instruction operand that is a memory
4214 reference whose address is ADDR. ADDR is an RTL expression. */
4216 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4219 /* A C statement, to be executed after all slot-filler instructions
4220 have been output. If necessary, call `dbr_sequence_length' to
4221 determine the number of slots filled in a sequence (zero if not
4222 currently outputting a sequence), to decide how many no-ops to
4223 output, or whatever.
4225 Don't define this macro if it has nothing to do, but it is
4226 helpful in reading assembly output if the extent of the delay
4227 sequence is made explicit (e.g. with white space).
4229 Note that output routines for instructions with delay slots must
4230 be prepared to deal with not being output as part of a sequence
4231 (i.e. when the scheduling pass is not run, or when no slot
4232 fillers could be found.) The variable `final_sequence' is null
4233 when not processing a sequence, otherwise it contains the
4234 `sequence' rtx being output. */
4236 #define DBR_OUTPUT_SEQEND(STREAM) \
4239 if (set_nomacro > 0 && --set_nomacro == 0) \
4240 fputs ("\t.set\tmacro\n", STREAM); \
4242 if (set_noreorder > 0 && --set_noreorder == 0) \
4243 fputs ("\t.set\treorder\n", STREAM); \
4245 dslots_jump_filled++; \
4246 fputs ("\n", STREAM); \
4251 /* How to tell the debugger about changes of source files. Note, the
4252 mips ECOFF format cannot deal with changes of files inside of
4253 functions, which means the output of parser generators like bison
4254 is generally not debuggable without using the -l switch. Lose,
4255 lose, lose. Silicon graphics seems to want all .file's hardwired
4258 #ifndef SET_FILE_NUMBER
4259 #define SET_FILE_NUMBER() ++num_source_filenames
4262 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4263 mips_output_filename (STREAM, NAME)
4265 /* This is defined so that it can be overridden in iris6.h. */
4266 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4269 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4270 output_quoted_string (STREAM, NAME); \
4271 fputs ("\n", STREAM); \
4275 /* This is how to output a note the debugger telling it the line number
4276 to which the following sequence of instructions corresponds.
4277 Silicon graphics puts a label after each .loc. */
4279 #ifndef LABEL_AFTER_LOC
4280 #define LABEL_AFTER_LOC(STREAM)
4283 #ifndef ASM_OUTPUT_SOURCE_LINE
4284 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4285 mips_output_lineno (STREAM, LINE)
4288 /* The MIPS implementation uses some labels for its own purpose. The
4289 following lists what labels are created, and are all formed by the
4290 pattern $L[a-z].*. The machine independent portion of GCC creates
4291 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4293 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4294 $Lb[0-9]+ Begin blocks for MIPS debug support
4295 $Lc[0-9]+ Label for use in s<xx> operation.
4296 $Le[0-9]+ End blocks for MIPS debug support */
4298 /* A C statement (sans semicolon) to output to the stdio stream
4299 STREAM any text necessary for declaring the name NAME of an
4300 initialized variable which is being defined. This macro must
4301 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4302 The argument DECL is the `VAR_DECL' tree node representing the
4305 If this macro is not defined, then the variable name is defined
4306 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4308 #undef ASM_DECLARE_OBJECT_NAME
4309 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4312 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4316 /* Globalizing directive for a label. */
4317 #define GLOBAL_ASM_OP "\t.globl\t"
4319 /* This says how to define a global common symbol. */
4321 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4323 /* If the target wants uninitialized const declarations in \
4324 .rdata then don't put them in .comm */ \
4325 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4326 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4327 && (DECL_INITIAL (DECL) == 0 \
4328 || DECL_INITIAL (DECL) == error_mark_node)) \
4330 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4331 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
4333 readonly_data_section (); \
4334 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4335 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4339 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4344 /* This says how to define a local common symbol (ie, not visible to
4347 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4348 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4351 /* This says how to output an external. It would be possible not to
4352 output anything and let undefined symbol become external. However
4353 the assembler uses length information on externals to allocate in
4354 data/sdata bss/sbss, thereby saving exec time. */
4356 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4357 mips_output_external(STREAM,DECL,NAME)
4359 /* This says what to print at the end of the assembly file */
4361 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4364 /* Play switch file games if we're optimizing the global pointer. */
4367 #define TEXT_SECTION() \
4369 extern FILE *asm_out_text_file; \
4370 if (TARGET_FILE_SWITCHING) \
4371 asm_out_file = asm_out_text_file; \
4372 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4373 fputc ('\n', asm_out_file); \
4377 /* This is how to declare a function name. The actual work of
4378 emitting the label is moved to function_prologue, so that we can
4379 get the line number correctly emitted before the .ent directive,
4380 and after any .file directives. Define as empty so that the function
4381 is not declared before the .ent directive elsewhere. */
4383 #undef ASM_DECLARE_FUNCTION_NAME
4384 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4386 /* This is how to store into the string LABEL
4387 the symbol_ref name of an internal numbered label where
4388 PREFIX is the class of label and NUM is the number within the class.
4389 This is suitable for output with `assemble_name'. */
4391 #undef ASM_GENERATE_INTERNAL_LABEL
4392 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4393 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4395 /* This is how to output an element of a case-vector that is absolute. */
4397 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4398 fprintf (STREAM, "\t%s\t%sL%d\n", \
4399 Pmode == DImode ? ".dword" : ".word", \
4400 LOCAL_LABEL_PREFIX, \
4403 /* This is how to output an element of a case-vector that is relative.
4404 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4405 TARGET_EMBEDDED_PIC). */
4407 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4409 if (TARGET_MIPS16) \
4410 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4411 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4412 else if (TARGET_EMBEDDED_PIC) \
4413 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4414 Pmode == DImode ? ".dword" : ".word", \
4415 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4416 else if (mips_abi == ABI_32 || mips_abi == ABI_O64 \
4417 || (TARGET_GAS && mips_abi == ABI_N32) \
4418 || (TARGET_GAS && mips_abi == ABI_64)) \
4419 fprintf (STREAM, "\t%s\t%sL%d\n", \
4420 Pmode == DImode ? ".gpdword" : ".gpword", \
4421 LOCAL_LABEL_PREFIX, VALUE); \
4423 fprintf (STREAM, "\t%s\t%sL%d\n", \
4424 Pmode == DImode ? ".dword" : ".word", \
4425 LOCAL_LABEL_PREFIX, VALUE); \
4428 /* When generating embedded PIC or mips16 code we want to put the jump
4429 table in the .text section. In all other cases, we want to put the
4430 jump table in the .rdata section. Unfortunately, we can't use
4431 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4432 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4433 section if appropriate. */
4434 #undef ASM_OUTPUT_CASE_LABEL
4435 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4437 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4438 function_section (current_function_decl); \
4439 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
4442 /* This is how to output an assembler line
4443 that says to advance the location counter
4444 to a multiple of 2**LOG bytes. */
4446 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4447 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4449 /* This is how to output an assembler line to advance the location
4450 counter by SIZE bytes. */
4452 #undef ASM_OUTPUT_SKIP
4453 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4454 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4456 /* This is how to output a string. */
4457 #undef ASM_OUTPUT_ASCII
4458 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4459 mips_output_ascii (STREAM, STRING, LEN)
4461 /* Output #ident as a in the read-only data section. */
4462 #undef ASM_OUTPUT_IDENT
4463 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4465 const char *p = STRING; \
4466 int size = strlen (p) + 1; \
4467 readonly_data_section (); \
4468 assemble_string (p, size); \
4471 /* Default to -G 8 */
4472 #ifndef MIPS_DEFAULT_GVALUE
4473 #define MIPS_DEFAULT_GVALUE 8
4476 /* Define the strings to put out for each section in the object file. */
4477 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4478 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4479 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4481 #undef READONLY_DATA_SECTION_ASM_OP
4482 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4484 #define SMALL_DATA_SECTION sdata_section
4486 /* What other sections we support other than the normal .data/.text. */
4488 #undef EXTRA_SECTIONS
4489 #define EXTRA_SECTIONS in_sdata
4491 /* Define the additional functions to select our additional sections. */
4493 /* on the MIPS it is not a good idea to put constants in the text
4494 section, since this defeats the sdata/data mechanism. This is
4495 especially true when -O is used. In this case an effort is made to
4496 address with faster (gp) register relative addressing, which can
4497 only get at sdata and sbss items (there is no stext !!) However,
4498 if the constant is too large for sdata, and it's readonly, it
4499 will go into the .rdata section. */
4501 #undef EXTRA_SECTION_FUNCTIONS
4502 #define EXTRA_SECTION_FUNCTIONS \
4506 if (in_section != in_sdata) \
4508 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4509 in_section = in_sdata; \
4513 /* Given a decl node or constant node, choose the section to output it in
4514 and select that section. */
4516 #undef TARGET_ASM_SELECT_SECTION
4517 #define TARGET_ASM_SELECT_SECTION mips_select_section
4519 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4522 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4523 TARGET_64BIT ? "dsubu" : "subu", \
4524 reg_names[STACK_POINTER_REGNUM], \
4525 reg_names[STACK_POINTER_REGNUM], \
4526 TARGET_64BIT ? "sd" : "sw", \
4528 reg_names[STACK_POINTER_REGNUM]); \
4532 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4535 if (! set_noreorder) \
4536 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4538 dslots_load_total++; \
4539 dslots_load_filled++; \
4540 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4541 TARGET_64BIT ? "ld" : "lw", \
4543 reg_names[STACK_POINTER_REGNUM], \
4544 TARGET_64BIT ? "daddu" : "addu", \
4545 reg_names[STACK_POINTER_REGNUM], \
4546 reg_names[STACK_POINTER_REGNUM]); \
4548 if (! set_noreorder) \
4549 fprintf (STREAM, "\t.set\treorder\n"); \
4553 /* How to start an assembler comment.
4554 The leading space is important (the mips native assembler requires it). */
4555 #ifndef ASM_COMMENT_START
4556 #define ASM_COMMENT_START " #"
4560 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4561 and mips-tdump.c to print them out.
4563 These must match the corresponding definitions in gdb/mipsread.c.
4564 Unfortunately, gcc and gdb do not currently share any directories. */
4566 #define CODE_MASK 0x8F300
4567 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4568 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4569 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4572 /* Default definitions for size_t and ptrdiff_t. We must override the
4573 definitions from ../svr4.h on mips-*-linux-gnu. */
4576 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4579 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4581 /* See mips_expand_prologue's use of loadgp for when this should be
4584 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4585 && mips_abi != ABI_32 \
4586 && mips_abi != ABI_O64)
4588 /* In mips16 mode, we need to look through the function to check for
4589 PC relative loads that are out of range. */
4590 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4592 /* We need to use a special set of functions to handle hard floating
4593 point code in mips16 mode. */
4595 #ifndef INIT_SUBTARGET_OPTABS
4596 #define INIT_SUBTARGET_OPTABS
4599 #define INIT_TARGET_OPTABS \
4602 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4603 INIT_SUBTARGET_OPTABS; \
4606 add_optab->handlers[(int) SFmode].libfunc = \
4607 init_one_libfunc ("__mips16_addsf3"); \
4608 sub_optab->handlers[(int) SFmode].libfunc = \
4609 init_one_libfunc ("__mips16_subsf3"); \
4610 smul_optab->handlers[(int) SFmode].libfunc = \
4611 init_one_libfunc ("__mips16_mulsf3"); \
4612 sdiv_optab->handlers[(int) SFmode].libfunc = \
4613 init_one_libfunc ("__mips16_divsf3"); \
4615 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4616 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4617 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4618 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4619 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4620 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4622 floatsisf_libfunc = \
4623 init_one_libfunc ("__mips16_floatsisf"); \
4625 init_one_libfunc ("__mips16_fixsfsi"); \
4627 if (TARGET_DOUBLE_FLOAT) \
4629 add_optab->handlers[(int) DFmode].libfunc = \
4630 init_one_libfunc ("__mips16_adddf3"); \
4631 sub_optab->handlers[(int) DFmode].libfunc = \
4632 init_one_libfunc ("__mips16_subdf3"); \
4633 smul_optab->handlers[(int) DFmode].libfunc = \
4634 init_one_libfunc ("__mips16_muldf3"); \
4635 sdiv_optab->handlers[(int) DFmode].libfunc = \
4636 init_one_libfunc ("__mips16_divdf3"); \
4638 extendsfdf2_libfunc = \
4639 init_one_libfunc ("__mips16_extendsfdf2"); \
4640 truncdfsf2_libfunc = \
4641 init_one_libfunc ("__mips16_truncdfsf2"); \
4644 init_one_libfunc ("__mips16_eqdf2"); \
4646 init_one_libfunc ("__mips16_nedf2"); \
4648 init_one_libfunc ("__mips16_gtdf2"); \
4650 init_one_libfunc ("__mips16_gedf2"); \
4652 init_one_libfunc ("__mips16_ltdf2"); \
4654 init_one_libfunc ("__mips16_ledf2"); \
4656 floatsidf_libfunc = \
4657 init_one_libfunc ("__mips16_floatsidf"); \
4659 init_one_libfunc ("__mips16_fixdfsi"); \
4665 #define DFMODE_NAN \
4666 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4667 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4668 #define SFMODE_NAN \
4669 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4670 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4672 /* Generate calls to memcpy, etc., not bcopy, etc. */
4673 #define TARGET_MEM_FUNCTIONS