1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern int target_flags;
31 /* MIPS external variables defined in mips.c. */
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
73 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
74 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
75 to work on a 64 bit machine. */
83 /* Information about one recognized processor. Defined here for the
84 benefit of TARGET_CPU_CPP_BUILTINS. */
85 struct mips_cpu_info {
86 /* The 'canonical' name of the processor as far as GCC is concerned.
87 It's typically a manufacturer's prefix followed by a numerical
88 designation. It should be lower case. */
91 /* The internal processor number that most closely matches this
92 entry. Several processors can have the same value, if there's no
93 difference between them from GCC's point of view. */
94 enum processor_type cpu;
96 /* The ISA level that the processor implements. */
100 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern int mips_entry; /* generate entry/exit for mips16 */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_entry_string; /* for -mentry */
125 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
126 extern int mips_string_length; /* length of strings for mips16 */
127 extern const struct mips_cpu_info mips_cpu_info_table[];
128 extern const struct mips_cpu_info *mips_arch_info;
129 extern const struct mips_cpu_info *mips_tune_info;
131 /* Macros to silence warnings about numbers being signed in traditional
132 C and unsigned in ISO C when compiled on 32-bit hosts. */
134 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
135 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
136 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
139 /* Run-time compilation parameters selecting different hardware subsets. */
141 /* Macros used in the machine description to test the flags. */
143 /* Bits for real switches */
144 #define MASK_INT64 0x00000001 /* ints are 64 bits */
145 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
146 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
147 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
148 multiply-add operations. */
149 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
150 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
151 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
152 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
153 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
154 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
155 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
156 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
157 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
158 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
159 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
160 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
161 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
162 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
163 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
164 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
165 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
166 #define MASK_NO_CHECK_ZERO_DIV \
167 0x00200000 /* divide by zero checking */
168 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
170 #define MASK_UNINIT_CONST_IN_RODATA \
171 0x00800000 /* Store uninitialized
174 /* Debug switches, not documented */
175 #define MASK_DEBUG 0 /* unused */
176 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
177 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
178 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
179 #define MASK_DEBUG_D 0 /* don't do define_split's */
180 #define MASK_DEBUG_E 0 /* function_arg debug */
181 #define MASK_DEBUG_F 0 /* ??? */
182 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
183 #define MASK_DEBUG_I 0 /* unused */
185 /* Dummy switches used only in specs */
186 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
188 /* r4000 64 bit sizes */
189 #define TARGET_INT64 (target_flags & MASK_INT64)
190 #define TARGET_LONG64 (target_flags & MASK_LONG64)
191 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
192 #define TARGET_64BIT (target_flags & MASK_64BIT)
194 /* Mips vs. GNU linker */
195 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
197 /* Mips vs. GNU assembler */
198 #define TARGET_GAS (target_flags & MASK_GAS)
199 #define TARGET_MIPS_AS (!TARGET_GAS)
202 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
203 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
204 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
205 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
206 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
207 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
208 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
209 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
210 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
212 /* Reg. Naming in .s ($21 vs. $a0) */
213 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
215 /* call memcpy instead of inline code */
216 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
218 /* .abicalls, etc from Pyramid V.4 */
219 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
221 /* software floating point */
222 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
223 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
225 /* always call through a register */
226 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
228 /* generate embedded PIC code;
230 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
232 /* for embedded systems, optimize for
233 reduced RAM space instead of for
235 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
237 /* always store uninitialized const
238 variables in rodata, requires
239 TARGET_EMBEDDED_DATA. */
240 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
242 /* generate big endian code. */
243 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
245 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
246 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
248 #define TARGET_MAD (target_flags & MASK_MAD)
250 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
252 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
254 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
256 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
259 /* True if we should use NewABI-style relocation operators for
260 symbolic addresses. This is never true for mips16 code,
261 which has its own conventions. */
263 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
266 /* True if the call patterns should be split into a jalr followed by
267 an instruction to restore $gp. This is only ever true for SVR4 PIC,
268 in which $gp is call-clobbered. It is only safe to split the load
269 from the call when every use of $gp is explicit. */
271 #define TARGET_SPLIT_CALLS \
272 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
274 /* True if we can optimize sibling calls. For simplicity, we only
275 handle cases in which call_insn_operand will reject invalid
276 sibcall addresses. There are two cases in which this isn't true:
278 - TARGET_MIPS16. call_insn_operand accepts constant addresses
279 but there is no direct jump instruction. It isn't worth
280 using sibling calls in this case anyway; they would usually
281 be longer than normal calls.
283 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
284 accepts global constants, but "jr $25" is the only allowed
287 #define TARGET_SIBCALLS \
288 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
290 /* True if .gpword or .gpdword should be used for switch tables.
291 Not all SGI assemblers support this. */
293 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
295 /* Generate mips16 code */
296 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
298 /* Generic ISA defines. */
299 #define ISA_MIPS1 (mips_isa == 1)
300 #define ISA_MIPS2 (mips_isa == 2)
301 #define ISA_MIPS3 (mips_isa == 3)
302 #define ISA_MIPS4 (mips_isa == 4)
303 #define ISA_MIPS32 (mips_isa == 32)
304 #define ISA_MIPS32R2 (mips_isa == 33)
305 #define ISA_MIPS64 (mips_isa == 64)
307 /* Architecture target defines. */
308 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
309 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
310 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
311 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
312 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
313 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
314 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
315 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
316 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
317 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
318 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
319 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
320 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
322 /* Scheduling target defines. */
323 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
324 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
325 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
326 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
327 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
328 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
329 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
330 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
331 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
332 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
333 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
335 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
337 /* Define preprocessor macros for the -march and -mtune options.
338 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
339 processor. If INFO's canonical name is "foo", define PREFIX to
340 be "foo", and define an additional macro PREFIX_FOO. */
341 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
346 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
347 for (p = macro; *p != 0; p++) \
350 builtin_define (macro); \
351 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
356 /* Target CPU builtins. */
357 #define TARGET_CPU_CPP_BUILTINS() \
360 builtin_assert ("cpu=mips"); \
361 builtin_define ("__mips__"); \
362 builtin_define ("_mips"); \
364 /* We do this here because __mips is defined below \
365 and so we can't use builtin_define_std. */ \
367 builtin_define ("mips"); \
369 /* Treat _R3000 and _R4000 like register-size defines, \
370 which is how they've historically been used. */ \
373 builtin_define ("__mips64"); \
374 builtin_define_std ("R4000"); \
375 builtin_define ("_R4000"); \
379 builtin_define_std ("R3000"); \
380 builtin_define ("_R3000"); \
382 if (TARGET_FLOAT64) \
383 builtin_define ("__mips_fpr=64"); \
385 builtin_define ("__mips_fpr=32"); \
388 builtin_define ("__mips16"); \
390 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
391 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
395 builtin_define ("__mips=1"); \
396 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
398 else if (ISA_MIPS2) \
400 builtin_define ("__mips=2"); \
401 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
403 else if (ISA_MIPS3) \
405 builtin_define ("__mips=3"); \
406 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
408 else if (ISA_MIPS4) \
410 builtin_define ("__mips=4"); \
411 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
413 else if (ISA_MIPS32) \
415 builtin_define ("__mips=32"); \
416 builtin_define ("__mips_isa_rev=1"); \
417 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
419 else if (ISA_MIPS32R2) \
421 builtin_define ("__mips=32"); \
422 builtin_define ("__mips_isa_rev=2"); \
423 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
425 else if (ISA_MIPS64) \
427 builtin_define ("__mips=64"); \
428 builtin_define ("__mips_isa_rev=1"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
432 if (TARGET_HARD_FLOAT) \
433 builtin_define ("__mips_hard_float"); \
434 else if (TARGET_SOFT_FLOAT) \
435 builtin_define ("__mips_soft_float"); \
437 if (TARGET_SINGLE_FLOAT) \
438 builtin_define ("__mips_single_float"); \
440 if (TARGET_BIG_ENDIAN) \
442 builtin_define_std ("MIPSEB"); \
443 builtin_define ("_MIPSEB"); \
447 builtin_define_std ("MIPSEL"); \
448 builtin_define ("_MIPSEL"); \
451 /* Macros dependent on the C dialect. */ \
452 if (preprocessing_asm_p ()) \
454 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
455 builtin_define ("_LANGUAGE_ASSEMBLY"); \
457 else if (c_dialect_cxx ()) \
459 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
460 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
461 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
465 builtin_define_std ("LANGUAGE_C"); \
466 builtin_define ("_LANGUAGE_C"); \
468 if (c_dialect_objc ()) \
470 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
471 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
472 /* Bizzare, but needed at least for Irix. */ \
473 builtin_define_std ("LANGUAGE_C"); \
474 builtin_define ("_LANGUAGE_C"); \
477 if (mips_abi == ABI_EABI) \
478 builtin_define ("__mips_eabi"); \
484 /* Macro to define tables used to set the flags.
485 This is a list in braces of pairs in braces,
486 each pair being { "NAME", VALUE }
487 where VALUE is the bits to set or minus the bits to clear.
488 An empty string NAME is used to identify the default VALUE. */
490 #define TARGET_SWITCHES \
492 SUBTARGET_TARGET_SWITCHES \
493 {"int64", MASK_INT64 | MASK_LONG64, \
494 N_("Use 64-bit int type")}, \
495 {"long64", MASK_LONG64, \
496 N_("Use 64-bit long type")}, \
497 {"long32", -(MASK_LONG64 | MASK_INT64), \
498 N_("Use 32-bit long type")}, \
499 {"split-addresses", MASK_SPLIT_ADDR, \
500 N_("Optimize lui/addiu address loads")}, \
501 {"no-split-addresses", -MASK_SPLIT_ADDR, \
502 N_("Don't optimize lui/addiu address loads")}, \
503 {"mips-as", -MASK_GAS, \
504 N_("Use MIPS as")}, \
507 {"rnames", MASK_NAME_REGS, \
508 N_("Use symbolic register names")}, \
509 {"no-rnames", -MASK_NAME_REGS, \
510 N_("Don't use symbolic register names")}, \
512 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
514 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
516 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
518 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
520 N_("Output compiler statistics (now ignored)")}, \
522 N_("Don't output compiler statistics")}, \
523 {"memcpy", MASK_MEMCPY, \
524 N_("Don't optimize block moves")}, \
525 {"no-memcpy", -MASK_MEMCPY, \
526 N_("Optimize block moves")}, \
527 {"mips-tfile", MASK_MIPS_TFILE, \
528 N_("Use mips-tfile asm postpass")}, \
529 {"no-mips-tfile", -MASK_MIPS_TFILE, \
530 N_("Don't use mips-tfile asm postpass")}, \
531 {"soft-float", MASK_SOFT_FLOAT, \
532 N_("Use software floating point")}, \
533 {"hard-float", -MASK_SOFT_FLOAT, \
534 N_("Use hardware floating point")}, \
535 {"fp64", MASK_FLOAT64, \
536 N_("Use 64-bit FP registers")}, \
537 {"fp32", -MASK_FLOAT64, \
538 N_("Use 32-bit FP registers")}, \
539 {"gp64", MASK_64BIT, \
540 N_("Use 64-bit general registers")}, \
541 {"gp32", -MASK_64BIT, \
542 N_("Use 32-bit general registers")}, \
543 {"abicalls", MASK_ABICALLS, \
544 N_("Use Irix PIC")}, \
545 {"no-abicalls", -MASK_ABICALLS, \
546 N_("Don't use Irix PIC")}, \
547 {"long-calls", MASK_LONG_CALLS, \
548 N_("Use indirect calls")}, \
549 {"no-long-calls", -MASK_LONG_CALLS, \
550 N_("Don't use indirect calls")}, \
551 {"embedded-pic", MASK_EMBEDDED_PIC, \
552 N_("Use embedded PIC")}, \
553 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
554 N_("Don't use embedded PIC")}, \
555 {"embedded-data", MASK_EMBEDDED_DATA, \
556 N_("Use ROM instead of RAM")}, \
557 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
558 N_("Don't use ROM instead of RAM")}, \
559 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
560 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
561 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
562 N_("Don't put uninitialized constants in ROM")}, \
563 {"eb", MASK_BIG_ENDIAN, \
564 N_("Use big-endian byte order")}, \
565 {"el", -MASK_BIG_ENDIAN, \
566 N_("Use little-endian byte order")}, \
567 {"single-float", MASK_SINGLE_FLOAT, \
568 N_("Use single (32-bit) FP only")}, \
569 {"double-float", -MASK_SINGLE_FLOAT, \
570 N_("Don't use single (32-bit) FP only")}, \
572 N_("Use multiply accumulate")}, \
573 {"no-mad", -MASK_MAD, \
574 N_("Don't use multiply accumulate")}, \
575 {"no-fused-madd", MASK_NO_FUSED_MADD, \
576 N_("Don't generate fused multiply/add instructions")}, \
577 {"fused-madd", -MASK_NO_FUSED_MADD, \
578 N_("Generate fused multiply/add instructions")}, \
579 {"fix4300", MASK_4300_MUL_FIX, \
580 N_("Work around early 4300 hardware bug")}, \
581 {"no-fix4300", -MASK_4300_MUL_FIX, \
582 N_("Don't work around early 4300 hardware bug")}, \
583 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
584 N_("Trap on integer divide by zero")}, \
585 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
586 N_("Don't trap on integer divide by zero")}, \
587 { "branch-likely", MASK_BRANCHLIKELY, \
588 N_("Use Branch Likely instructions, overriding default for arch")}, \
589 { "no-branch-likely", -MASK_BRANCHLIKELY, \
590 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
591 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
592 N_("Use NewABI-style %reloc() assembly operators")}, \
593 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
594 N_("Use assembler macros instead of relocation operators")}, \
595 {"ips16", MASK_MIPS16, \
596 N_("Generate mips16 code") }, \
597 {"no-mips16", -MASK_MIPS16, \
598 N_("Generate normal-mode code") }, \
599 {"debug", MASK_DEBUG, \
601 {"debuga", MASK_DEBUG_A, \
603 {"debugb", MASK_DEBUG_B, \
605 {"debugc", MASK_DEBUG_C, \
607 {"debugd", MASK_DEBUG_D, \
609 {"debuge", MASK_DEBUG_E, \
611 {"debugf", MASK_DEBUG_F, \
613 {"debugg", MASK_DEBUG_G, \
615 {"debugi", MASK_DEBUG_I, \
617 {"", (TARGET_DEFAULT \
618 | TARGET_CPU_DEFAULT \
619 | TARGET_ENDIAN_DEFAULT), \
623 /* Default target_flags if no switches are specified */
625 #ifndef TARGET_DEFAULT
626 #define TARGET_DEFAULT 0
629 #ifndef TARGET_CPU_DEFAULT
630 #define TARGET_CPU_DEFAULT 0
633 #ifndef TARGET_ENDIAN_DEFAULT
634 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
637 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
638 #ifndef MIPS_ISA_DEFAULT
639 #ifndef MIPS_CPU_STRING_DEFAULT
640 #define MIPS_CPU_STRING_DEFAULT "from-abi"
646 /* Make this compile time constant for libgcc2 */
648 #define TARGET_64BIT 1
650 #define TARGET_64BIT 0
652 #endif /* IN_LIBGCC2 */
654 #ifndef MULTILIB_ENDIAN_DEFAULT
655 #if TARGET_ENDIAN_DEFAULT == 0
656 #define MULTILIB_ENDIAN_DEFAULT "EL"
658 #define MULTILIB_ENDIAN_DEFAULT "EB"
662 #ifndef MULTILIB_ISA_DEFAULT
663 # if MIPS_ISA_DEFAULT == 1
664 # define MULTILIB_ISA_DEFAULT "mips1"
666 # if MIPS_ISA_DEFAULT == 2
667 # define MULTILIB_ISA_DEFAULT "mips2"
669 # if MIPS_ISA_DEFAULT == 3
670 # define MULTILIB_ISA_DEFAULT "mips3"
672 # if MIPS_ISA_DEFAULT == 4
673 # define MULTILIB_ISA_DEFAULT "mips4"
675 # if MIPS_ISA_DEFAULT == 32
676 # define MULTILIB_ISA_DEFAULT "mips32"
678 # if MIPS_ISA_DEFAULT == 33
679 # define MULTILIB_ISA_DEFAULT "mips32r2"
681 # if MIPS_ISA_DEFAULT == 64
682 # define MULTILIB_ISA_DEFAULT "mips64"
684 # define MULTILIB_ISA_DEFAULT "mips1"
694 #ifndef MULTILIB_DEFAULTS
695 #define MULTILIB_DEFAULTS \
696 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
699 /* We must pass -EL to the linker by default for little endian embedded
700 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
701 linker will default to using big-endian output files. The OUTPUT_FORMAT
702 line must be in the linker script, otherwise -EB/-EL will not work. */
705 #if TARGET_ENDIAN_DEFAULT == 0
706 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
708 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
712 #define TARGET_OPTIONS \
714 SUBTARGET_TARGET_OPTIONS \
715 { "tune=", &mips_tune_string, \
716 N_("Specify CPU for scheduling purposes"), 0}, \
717 { "arch=", &mips_arch_string, \
718 N_("Specify CPU for code generation purposes"), 0}, \
719 { "abi=", &mips_abi_string, \
720 N_("Specify an ABI"), 0}, \
721 { "ips", &mips_isa_string, \
722 N_("Specify a Standard MIPS ISA"), 0}, \
723 { "entry", &mips_entry_string, \
724 N_("Use mips16 entry/exit psuedo ops"), 0}, \
725 { "no-flush-func", &mips_cache_flush_func, \
726 N_("Don't call any cache flush functions"), 0}, \
727 { "flush-func=", &mips_cache_flush_func, \
728 N_("Specify cache flush function"), 0}, \
731 /* This is meant to be redefined in the host dependent files. */
732 #define SUBTARGET_TARGET_OPTIONS
734 /* Support for a compile-time default CPU, et cetera. The rules are:
735 --with-arch is ignored if -march is specified or a -mips is specified
736 (other than -mips16).
737 --with-tune is ignored if -mtune is specified.
738 --with-abi is ignored if -mabi is specified.
739 --with-float is ignored if -mhard-float or -msoft-float are
741 #define OPTION_DEFAULT_SPECS \
742 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
743 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
744 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
745 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
748 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
752 /* Generate three-operand multiply instructions for SImode. */
753 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
763 /* Generate three-operand multiply instructions for DImode. */
764 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
767 /* Macros to decide whether certain features are available or not,
768 depending on the instruction set architecture level. */
770 #define HAVE_SQRT_P() (!ISA_MIPS1)
772 /* True if the ABI can only work with 64-bit integer registers. We
773 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
774 otherwise floating-point registers must also be 64-bit. */
775 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
776 || mips_abi == ABI_O64 \
777 || mips_abi == ABI_N32)
779 /* Likewise for 32-bit regs. */
780 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
782 /* True if symbols are 64 bits wide. At present, n64 is the only
783 ABI for which this is true. */
784 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
786 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
787 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
791 /* ISA has branch likely instructions (eg. mips2). */
792 /* Disable branchlikely for tx39 until compare rewrite. They haven't
793 been generated up to this point. */
794 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
797 /* ISA has the conditional move instructions introduced in mips4. */
798 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
802 && !TARGET_MIPS5500 \
805 /* ISA has just the integer condition move instructions (movn,movz) */
806 #define ISA_HAS_INT_CONDMOVE 0
808 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
809 branch on CC, and move (both FP and non-FP) on CC. */
810 #define ISA_HAS_8CC (ISA_MIPS4 \
815 /* This is a catch all for the other new mips4 instructions: indexed load and
816 indexed prefetch instructions, the FP madd and msub instructions,
817 and the FP recip and recip sqrt instructions */
818 #define ISA_HAS_FP4 ((ISA_MIPS4 \
822 /* ISA has conditional trap instructions. */
823 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
826 /* ISA has integer multiply-accumulate instructions, madd and msub. */
827 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
832 /* ISA has floating-point nmadd and nmsub instructions. */
833 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
835 && (!TARGET_MIPS5400 || TARGET_MAD) \
838 /* ISA has count leading zeroes/ones instruction (not implemented). */
839 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
844 /* ISA has double-word count leading zeroes/ones instruction (not
846 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
849 /* ISA has three operand multiply instructions that put
850 the high part in an accumulator: mulhi or mulhiu. */
851 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
856 /* ISA has three operand multiply instructions that
857 negates the result and puts the result in an accumulator. */
858 #define ISA_HAS_MULS (TARGET_MIPS5400 \
863 /* ISA has three operand multiply instructions that subtracts the
864 result from a 4th operand and puts the result in an accumulator. */
865 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
869 /* ISA has three operand multiply instructions that the result
870 from a 4th operand and puts the result in an accumulator. */
871 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
877 /* ISA has 32-bit rotate right instruction. */
878 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
885 /* ISA has 64-bit rotate right instruction. */
886 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
888 && (TARGET_MIPS5400 \
893 /* ISA has data prefetch instruction. */
894 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
900 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
901 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
902 also requires TARGET_DOUBLE_FLOAT. */
903 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
905 /* ISA includes the MIPS32r2 seb and seh instructions. */
906 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
910 /* True if the result of a load is not available to the next instruction.
911 A nop will then be needed between instructions like "lw $4,..."
912 and "addiu $4,$4,1". */
913 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
914 && !TARGET_MIPS3900 \
917 /* Likewise mtc1 and mfc1. */
918 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
920 /* Likewise floating-point comparisons. */
921 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
923 /* True if mflo and mfhi can be immediately followed by instructions
924 which write to the HI and LO registers. Most targets require a
925 two-instruction gap. */
926 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
928 /* Switch Recognition by gcc.c. Add -G xx support */
930 #undef SWITCH_TAKES_ARG
931 #define SWITCH_TAKES_ARG(CHAR) \
932 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
934 /* Sometimes certain combinations of command options do not make sense
935 on a particular target machine. You can define a macro
936 `OVERRIDE_OPTIONS' to take account of this. This macro, if
937 defined, is executed once just after all the command options have
940 On the MIPS, it is used to handle -G. We also use it to set up all
941 of the tables referenced in the other macros. */
943 #define OVERRIDE_OPTIONS override_options ()
945 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
947 /* Show we can debug even without a frame pointer. */
948 #define CAN_DEBUG_WITHOUT_FP
950 /* Tell collect what flags to pass to nm. */
952 #define NM_FLAGS "-Bn"
956 /* Assembler specs. */
958 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
961 #define MIPS_AS_ASM_SPEC "\
962 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
963 %{pipe: %e-pipe is not supported} \
964 %{K} %(subtarget_mips_as_asm_spec)"
966 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
967 rather than gas. It may be overridden by subtargets. */
969 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
970 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
973 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
976 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
978 #define SUBTARGET_TARGET_SWITCHES
980 #ifndef MIPS_ABI_DEFAULT
981 #define MIPS_ABI_DEFAULT ABI_32
984 /* Use the most portable ABI flag for the ASM specs. */
986 #if MIPS_ABI_DEFAULT == ABI_32
987 #define MULTILIB_ABI_DEFAULT "mabi=32"
988 #define ASM_ABI_DEFAULT_SPEC "-32"
991 #if MIPS_ABI_DEFAULT == ABI_O64
992 #define MULTILIB_ABI_DEFAULT "mabi=o64"
993 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
996 #if MIPS_ABI_DEFAULT == ABI_N32
997 #define MULTILIB_ABI_DEFAULT "mabi=n32"
998 #define ASM_ABI_DEFAULT_SPEC "-n32"
1001 #if MIPS_ABI_DEFAULT == ABI_64
1002 #define MULTILIB_ABI_DEFAULT "mabi=64"
1003 #define ASM_ABI_DEFAULT_SPEC "-64"
1006 #if MIPS_ABI_DEFAULT == ABI_EABI
1007 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1008 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1011 /* Only ELF targets can switch the ABI. */
1012 #ifndef OBJECT_FORMAT_ELF
1013 #undef ASM_ABI_DEFAULT_SPEC
1014 #define ASM_ABI_DEFAULT_SPEC ""
1017 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1018 GAS_ASM_SPEC as the default, depending upon the value of
1021 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1024 #define TARGET_ASM_SPEC "\
1025 %{mmips-as: %(mips_as_asm_spec)} \
1026 %{!mmips-as: %(gas_asm_spec)}"
1030 #define TARGET_ASM_SPEC "\
1031 %{!mgas: %(mips_as_asm_spec)} \
1032 %{mgas: %(gas_asm_spec)}"
1034 #endif /* not GAS */
1036 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1037 to the assembler. It may be overridden by subtargets. */
1038 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1039 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1041 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1044 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1045 the assembler. It may be overridden by subtargets. */
1046 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1047 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1048 %{g} %{g0} %{g1} %{g2} %{g3} \
1049 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1050 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1051 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1052 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1056 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1057 and stabs debugging info. */
1058 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1060 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1062 #define MDEBUG_ASM_SPEC ""
1063 #endif /* not GAS */
1065 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1066 overridden by subtargets. */
1068 #ifndef SUBTARGET_ASM_SPEC
1069 #define SUBTARGET_ASM_SPEC ""
1072 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1073 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1074 whether we're using GAS. These options can only be used properly
1075 with GAS, and it is better to get an error from a non-GAS assembler
1076 than to silently generate bad code. */
1080 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1081 %{mips32} %{mips32r2} %{mips64} \
1082 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1083 %(subtarget_asm_optimizing_spec) \
1084 %(subtarget_asm_debugging_spec) \
1086 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1087 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1088 %{mgp32} %{mgp64} %{march=*} \
1089 %(target_asm_spec) \
1090 %(subtarget_asm_spec)"
1092 /* Extra switches sometimes passed to the linker. */
1093 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1094 will interpret it as a -b option. */
1097 #define LINK_SPEC "\
1099 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1100 %{bestGnum} %{shared} %{non_shared}"
1101 #endif /* LINK_SPEC defined */
1104 /* Specs for the compiler proper */
1106 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1107 overridden by subtargets. */
1108 #ifndef SUBTARGET_CC1_SPEC
1109 #define SUBTARGET_CC1_SPEC ""
1112 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1116 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1117 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1119 %(subtarget_cc1_spec)"
1122 /* Preprocessor specs. */
1124 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1125 overridden by subtargets. */
1126 #ifndef SUBTARGET_CPP_SPEC
1127 #define SUBTARGET_CPP_SPEC ""
1130 #define CPP_SPEC "%(subtarget_cpp_spec)"
1132 /* This macro defines names of additional specifications to put in the specs
1133 that can be used in various specifications like CC1_SPEC. Its definition
1134 is an initializer with a subgrouping for each command option.
1136 Each subgrouping contains a string constant, that defines the
1137 specification name, and a string constant that used by the GNU CC driver
1140 Do not define this macro if it does not need to do anything. */
1142 #define EXTRA_SPECS \
1143 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1144 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1145 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1146 { "gas_asm_spec", GAS_ASM_SPEC }, \
1147 { "target_asm_spec", TARGET_ASM_SPEC }, \
1148 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1149 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1150 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1151 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1152 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1153 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1154 { "endian_spec", ENDIAN_SPEC }, \
1155 SUBTARGET_EXTRA_SPECS
1157 #ifndef SUBTARGET_EXTRA_SPECS
1158 #define SUBTARGET_EXTRA_SPECS
1161 /* If defined, this macro is an additional prefix to try after
1162 `STANDARD_EXEC_PREFIX'. */
1164 #ifndef MD_EXEC_PREFIX
1165 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1168 #ifndef MD_STARTFILE_PREFIX
1169 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1173 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1174 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1176 /* By default, turn on GDB extensions. */
1177 #define DEFAULT_GDB_EXTENSIONS 1
1179 /* If we are passing smuggling stabs through the MIPS ECOFF object
1180 format, put a comment in front of the .stab<x> operation so
1181 that the MIPS assembler does not choke. The mips-tfile program
1182 will correctly put the stab into the object file. */
1184 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1185 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1186 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1188 /* Local compiler-generated symbols must have a prefix that the assembler
1189 understands. By default, this is $, although some targets (e.g.,
1190 NetBSD-ELF) need to override this. */
1192 #ifndef LOCAL_LABEL_PREFIX
1193 #define LOCAL_LABEL_PREFIX "$"
1196 /* By default on the mips, external symbols do not have an underscore
1197 prepended, but some targets (e.g., NetBSD) require this. */
1199 #ifndef USER_LABEL_PREFIX
1200 #define USER_LABEL_PREFIX ""
1203 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1204 since the length can run past this up to a continuation point. */
1205 #undef DBX_CONTIN_LENGTH
1206 #define DBX_CONTIN_LENGTH 1500
1208 /* How to renumber registers for dbx and gdb. */
1209 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1211 /* The mapping from gcc register number to DWARF 2 CFA column number.
1212 This mapping does not allow for tracking register 0, since SGI's broken
1213 dwarf reader thinks column 0 is used for the frame address, but since
1214 register 0 is fixed this is not a problem. */
1215 #define DWARF_FRAME_REGNUM(REG) \
1216 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1218 /* The DWARF 2 CFA column which tracks the return address. */
1219 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1221 /* Before the prologue, RA lives in r31. */
1222 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1224 /* Describe how we implement __builtin_eh_return. */
1225 #define EH_RETURN_DATA_REGNO(N) \
1226 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1228 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1230 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1231 The default for this in 64-bit mode is 8, which causes problems with
1232 SFmode register saves. */
1233 #define DWARF_CIE_DATA_ALIGNMENT 4
1235 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1237 /* Correct the offset of automatic variables and arguments. Note that
1238 the MIPS debug format wants all automatic variables and arguments
1239 to be in terms of the virtual frame pointer (stack pointer before
1240 any adjustment in the function), while the MIPS 3.0 linker wants
1241 the frame pointer to be the stack pointer after the initial
1244 #define DEBUGGER_AUTO_OFFSET(X) \
1245 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1246 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1247 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1249 /* Target machine storage layout */
1251 /* Define this if most significant bit is lowest numbered
1252 in instructions that operate on numbered bit-fields.
1254 #define BITS_BIG_ENDIAN 0
1256 /* Define this if most significant byte of a word is the lowest numbered. */
1257 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1259 /* Define this if most significant word of a multiword number is the lowest. */
1260 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1262 /* Define this to set the endianness to use in libgcc2.c, which can
1263 not depend on target_flags. */
1264 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1265 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1267 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1270 #define MAX_BITS_PER_WORD 64
1272 /* Width of a word, in units (bytes). */
1273 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1274 #define MIN_UNITS_PER_WORD 4
1276 /* For MIPS, width of a floating point register. */
1277 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1279 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1280 the next available register. */
1281 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1283 /* The largest size of value that can be held in floating-point
1284 registers and moved with a single instruction. */
1285 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1287 /* The largest size of value that can be held in floating-point
1289 #define UNITS_PER_FPVALUE \
1290 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1292 /* The number of bytes in a double. */
1293 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1295 /* A C expression for the size in bits of the type `int' on the
1296 target machine. If you don't define this, the default is one
1298 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1300 /* Tell the preprocessor the maximum size of wchar_t. */
1301 #ifndef MAX_WCHAR_TYPE_SIZE
1302 #ifndef WCHAR_TYPE_SIZE
1303 #define MAX_WCHAR_TYPE_SIZE 64
1307 /* A C expression for the size in bits of the type `short' on the
1308 target machine. If you don't define this, the default is half a
1309 word. (If this would be less than one storage unit, it is
1310 rounded up to one unit.) */
1311 #define SHORT_TYPE_SIZE 16
1313 /* A C expression for the size in bits of the type `long' on the
1314 target machine. If you don't define this, the default is one
1316 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1317 #define MAX_LONG_TYPE_SIZE 64
1319 /* A C expression for the size in bits of the type `long long' on the
1320 target machine. If you don't define this, the default is two
1322 #define LONG_LONG_TYPE_SIZE 64
1324 /* A C expression for the size in bits of the type `float' on the
1325 target machine. If you don't define this, the default is one
1327 #define FLOAT_TYPE_SIZE 32
1329 /* A C expression for the size in bits of the type `double' on the
1330 target machine. If you don't define this, the default is two
1332 #define DOUBLE_TYPE_SIZE 64
1334 /* A C expression for the size in bits of the type `long double' on
1335 the target machine. If you don't define this, the default is two
1337 #define LONG_DOUBLE_TYPE_SIZE \
1338 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1340 /* long double is not a fixed mode, but the idea is that, if we
1341 support long double, we also want a 128-bit integer type. */
1342 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1345 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1346 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1347 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1349 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1353 /* Width in bits of a pointer. */
1354 #ifndef POINTER_SIZE
1355 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1358 #define POINTERS_EXTEND_UNSIGNED 0
1360 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1361 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1362 || mips_abi == ABI_64 \
1363 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1366 /* Allocation boundary (in *bits*) for the code of a function. */
1367 #define FUNCTION_BOUNDARY 32
1369 /* Alignment of field after `int : 0' in a structure. */
1370 #define EMPTY_FIELD_BOUNDARY 32
1372 /* Every structure's size must be a multiple of this. */
1373 /* 8 is observed right on a DECstation and on riscos 4.02. */
1374 #define STRUCTURE_SIZE_BOUNDARY 8
1376 /* There is no point aligning anything to a rounder boundary than this. */
1377 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1379 /* Set this nonzero if move instructions will actually fail to work
1380 when given unaligned data. */
1381 #define STRICT_ALIGNMENT 1
1383 /* Define this if you wish to imitate the way many other C compilers
1384 handle alignment of bitfields and the structures that contain
1387 The behavior is that the type written for a bit-field (`int',
1388 `short', or other integer type) imposes an alignment for the
1389 entire structure, as if the structure really did contain an
1390 ordinary field of that type. In addition, the bit-field is placed
1391 within the structure so that it would fit within such a field,
1392 not crossing a boundary for it.
1394 Thus, on most machines, a bit-field whose type is written as `int'
1395 would not cross a four-byte boundary, and would force four-byte
1396 alignment for the whole structure. (The alignment used may not
1397 be four bytes; it is controlled by the other alignment
1400 If the macro is defined, its definition should be a C expression;
1401 a nonzero value for the expression enables this behavior. */
1403 #define PCC_BITFIELD_TYPE_MATTERS 1
1405 /* If defined, a C expression to compute the alignment given to a
1406 constant that is being placed in memory. CONSTANT is the constant
1407 and ALIGN is the alignment that the object would ordinarily have.
1408 The value of this macro is used instead of that alignment to align
1411 If this macro is not defined, then ALIGN is used.
1413 The typical use of this macro is to increase alignment for string
1414 constants to be word aligned so that `strcpy' calls that copy
1415 constants can be done inline. */
1417 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1418 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1419 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1421 /* If defined, a C expression to compute the alignment for a static
1422 variable. TYPE is the data type, and ALIGN is the alignment that
1423 the object would ordinarily have. The value of this macro is used
1424 instead of that alignment to align the object.
1426 If this macro is not defined, then ALIGN is used.
1428 One use of this macro is to increase alignment of medium-size
1429 data to make it all fit in fewer cache lines. Another is to
1430 cause character arrays to be word-aligned so that `strcpy' calls
1431 that copy constants to character arrays can be done inline. */
1433 #undef DATA_ALIGNMENT
1434 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1435 ((((ALIGN) < BITS_PER_WORD) \
1436 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1437 || TREE_CODE (TYPE) == UNION_TYPE \
1438 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1441 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1443 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1445 /* Define this macro if an argument declared as `char' or `short' in a
1446 prototype should actually be passed as an `int'. In addition to
1447 avoiding errors in certain cases of mismatch, it also makes for
1448 better code on certain machines. */
1450 #define PROMOTE_PROTOTYPES 1
1452 /* Define if operations between registers always perform the operation
1453 on the full register even if a narrower mode is specified. */
1454 #define WORD_REGISTER_OPERATIONS
1456 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1457 will either zero-extend or sign-extend. The value of this macro should
1458 be the code that says which one of the two operations is implicitly
1461 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1462 moves. All other references are zero extended. */
1463 #define LOAD_EXTEND_OP(MODE) \
1464 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1465 ? SIGN_EXTEND : ZERO_EXTEND)
1467 /* Define this macro if it is advisable to hold scalars in registers
1468 in a wider mode than that declared by the program. In such cases,
1469 the value is constrained to be within the bounds of the declared
1470 type, but kept valid in the wider mode. The signedness of the
1471 extension may differ from that of the type. */
1473 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1474 if (GET_MODE_CLASS (MODE) == MODE_INT \
1475 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1477 if ((MODE) == SImode) \
1482 /* Define if loading short immediate values into registers sign extends. */
1483 #define SHORT_IMMEDIATES_SIGN_EXTEND
1486 /* Define this if function arguments should also be promoted using the above
1488 #define PROMOTE_FUNCTION_ARGS
1490 /* Likewise, if the function return value is promoted. */
1491 #define PROMOTE_FUNCTION_RETURN
1494 /* Standard register usage. */
1496 /* Number of actual hardware registers.
1497 The hardware registers are assigned numbers for the compiler
1498 from 0 to just below FIRST_PSEUDO_REGISTER.
1499 All registers that the compiler knows about must be given numbers,
1500 even those that are not normally considered general registers.
1502 On the Mips, we have 32 integer registers, 32 floating point
1503 registers, 8 condition code registers, and the special registers
1504 hi and lo. After that we have 32 COP0 registers, 32 COP2 registers,
1505 and 32 COP3 registers. (COP1 is the floating-point processor.)
1506 The 8 condition code registers are only used if mips_isa >= 4. */
1508 #define FIRST_PSEUDO_REGISTER 176
1510 /* 1 for registers that have pervasive standard uses
1511 and are not available for the register allocator.
1513 On the MIPS, see conventions, page D-2 */
1515 /* Regarding coprocessor registers: without evidence to the contrary,
1516 it's best to assume that each coprocessor register has a unique
1517 use. This can be overridden, in, e.g., override_options() or
1518 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1519 for a particular target. */
1521 #define FIXED_REGISTERS \
1523 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1527 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1528 /* COP0 registers */ \
1529 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 /* COP2 registers */ \
1532 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 /* COP3 registers */ \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1540 /* Don't mark $31 as a call-clobbered register. The idea is that
1541 it's really the call instructions themselves which clobber $31.
1542 We don't care what the called function does with it afterwards.
1544 This approach makes it easier to implement sibcalls. Unlike normal
1545 calls, sibcalls don't clobber $31, so the register reaches the
1546 called function in tact. EPILOGUE_USES says that $31 is useful
1547 to the called function. */
1549 #define CALL_USED_REGISTERS \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 /* COP0 registers */ \
1557 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 /* COP2 registers */ \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1562 /* COP3 registers */ \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1567 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1568 problem which makes CALL_USED_REGISTERS *always* include
1569 all the FIXED_REGISTERS. Until this problem has been
1570 resolved this macro can be used to overcome this situation.
1571 In particular, block_propagate() requires this list
1572 be accurate, or we can remove registers which should be live.
1573 This macro is used in regs_invalidated_by_call. */
1576 #define CALL_REALLY_USED_REGISTERS \
1577 { /* General registers. */ \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1579 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1580 /* Floating-point registers. */ \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1585 /* COP0 registers */ \
1586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 /* COP2 registers */ \
1589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1591 /* COP3 registers */ \
1592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1596 /* Internal macros to classify a register number as to whether it's a
1597 general purpose register, a floating point register, a
1598 multiply/divide register, or a status register. */
1600 #define GP_REG_FIRST 0
1601 #define GP_REG_LAST 31
1602 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1603 #define GP_DBX_FIRST 0
1605 #define FP_REG_FIRST 32
1606 #define FP_REG_LAST 63
1607 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1608 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1610 #define MD_REG_FIRST 64
1611 #define MD_REG_LAST 65
1612 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1613 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1615 #define ST_REG_FIRST 67
1616 #define ST_REG_LAST 74
1617 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1620 /* FIXME: renumber. */
1621 #define COP0_REG_FIRST 80
1622 #define COP0_REG_LAST 111
1623 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1625 #define COP2_REG_FIRST 112
1626 #define COP2_REG_LAST 143
1627 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1629 #define COP3_REG_FIRST 144
1630 #define COP3_REG_LAST 175
1631 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1632 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1633 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1635 #define AT_REGNUM (GP_REG_FIRST + 1)
1636 #define HI_REGNUM (MD_REG_FIRST + 0)
1637 #define LO_REGNUM (MD_REG_FIRST + 1)
1639 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1640 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1641 should be used instead. */
1642 #define FPSW_REGNUM ST_REG_FIRST
1644 #define GP_REG_P(REGNO) \
1645 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1646 #define M16_REG_P(REGNO) \
1647 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1648 #define FP_REG_P(REGNO) \
1649 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1650 #define MD_REG_P(REGNO) \
1651 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1652 #define ST_REG_P(REGNO) \
1653 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1654 #define COP0_REG_P(REGNO) \
1655 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1656 #define COP2_REG_P(REGNO) \
1657 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1658 #define COP3_REG_P(REGNO) \
1659 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1660 #define ALL_COP_REG_P(REGNO) \
1661 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1663 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1665 /* Return coprocessor number from register number. */
1667 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1668 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1669 : COP3_REG_P (REGNO) ? '3' : '?')
1671 /* Return number of consecutive hard regs needed starting at reg REGNO
1672 to hold something of mode MODE.
1673 This is ordinarily the length in words of a value of mode MODE
1674 but can be less for certain modes in special long registers.
1676 On the MIPS, all general registers are one word long. Except on
1677 the R4000 with the FR bit set, the floating point uses register
1678 pairs, with the second register not being allocable. */
1680 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1682 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1683 MODE. In 32 bit mode, require that DImode and DFmode be in even
1684 registers. For DImode, this makes some of the insns easier to
1685 write, since you don't have to worry about a DImode value in
1686 registers 3 & 4, producing a result in 4 & 5.
1688 To make the code simpler HARD_REGNO_MODE_OK now just references an
1689 array built in override_options. Because machmodes.h is not yet
1690 included before this file is processed, the MODE bound can't be
1693 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1695 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1696 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1698 /* Value is 1 if it is a good idea to tie two pseudo registers
1699 when one has mode MODE1 and one has mode MODE2.
1700 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1701 for any hard reg, then this must be 0 for correct output. */
1702 #define MODES_TIEABLE_P(MODE1, MODE2) \
1703 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1704 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1705 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1706 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1708 /* Register to use for pushing function arguments. */
1709 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1711 /* Base register for access to local variables of the function. We
1712 pretend that the frame pointer is $1, and then eliminate it to
1713 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1714 a fixed register, and will not be used for anything else. */
1715 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1717 /* $30 is not available on the mips16, so we use $17 as the frame
1719 #define HARD_FRAME_POINTER_REGNUM \
1720 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1722 /* Value should be nonzero if functions must have frame pointers.
1723 Zero means the frame pointer need not be set up (and parms
1724 may be accessed via the stack pointer) in functions that seem suitable.
1725 This is computed in `reload', in reload1.c. */
1726 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1728 /* Base register for access to arguments of the function. */
1729 #define ARG_POINTER_REGNUM GP_REG_FIRST
1731 /* Register in which static-chain is passed to a function. */
1732 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1734 /* If the structure value address is not passed in a register, define
1735 `STRUCT_VALUE' as an expression returning an RTX for the place
1736 where the address is passed. If it returns 0, the address is
1737 passed as an "invisible" first argument. */
1738 #define STRUCT_VALUE 0
1740 /* Mips registers used in prologue/epilogue code when the stack frame
1741 is larger than 32K bytes. These registers must come from the
1742 scratch register set, and not used for passing and returning
1743 arguments and any other information used in the calling sequence
1744 (such as pic). Must start at 12, since t0/t3 are parameter passing
1745 registers in the 64 bit ABI. */
1747 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1748 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1750 /* Define this macro if it is as good or better to call a constant
1751 function address than to call an address kept in a register. */
1752 #define NO_FUNCTION_CSE 1
1754 /* Define this macro if it is as good or better for a function to
1755 call itself with an explicit address than to call an address
1756 kept in a register. */
1757 #define NO_RECURSIVE_FUNCTION_CSE 1
1759 /* The ABI-defined global pointer. Sometimes we use a different
1760 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1761 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1763 /* We normally use $28 as the global pointer. However, when generating
1764 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1765 register instead. They can then avoid saving and restoring $28
1766 and perhaps avoid using a frame at all.
1768 When a leaf function uses something other than $28, mips_expand_prologue
1769 will modify pic_offset_table_rtx in place. Take the register number
1770 from there after reload. */
1771 #define PIC_OFFSET_TABLE_REGNUM \
1772 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1774 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1776 /* Define the classes of registers for register constraints in the
1777 machine description. Also define ranges of constants.
1779 One of the classes must always be named ALL_REGS and include all hard regs.
1780 If there is more than one class, another class must be named NO_REGS
1781 and contain no registers.
1783 The name GENERAL_REGS must be the name of a class (or an alias for
1784 another name such as ALL_REGS). This is the class of registers
1785 that is allowed by "g" or "r" in a register constraint.
1786 Also, registers outside this class are allocated only when
1787 instructions express preferences for them.
1789 The classes must be numbered in nondecreasing order; that is,
1790 a larger-numbered class must never be contained completely
1791 in a smaller-numbered class.
1793 For any two classes, it is very desirable that there be another
1794 class that represents their union. */
1798 NO_REGS, /* no registers in set */
1799 M16_NA_REGS, /* mips16 regs not used to pass args */
1800 M16_REGS, /* mips16 directly accessible registers */
1801 T_REG, /* mips16 T register ($24) */
1802 M16_T_REGS, /* mips16 registers plus T register */
1803 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1804 LEA_REGS, /* Every GPR except $25 */
1805 GR_REGS, /* integer registers */
1806 FP_REGS, /* floating point registers */
1807 HI_REG, /* hi register */
1808 LO_REG, /* lo register */
1809 MD_REGS, /* multiply/divide registers (hi/lo) */
1810 COP0_REGS, /* generic coprocessor classes */
1813 HI_AND_GR_REGS, /* union classes */
1820 ALL_COP_AND_GR_REGS,
1821 ST_REGS, /* status registers (fp status) */
1822 ALL_REGS, /* all registers */
1823 LIM_REG_CLASSES /* max value + 1 */
1826 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1828 #define GENERAL_REGS GR_REGS
1830 /* An initializer containing the names of the register classes as C
1831 string constants. These names are used in writing some of the
1834 #define REG_CLASS_NAMES \
1841 "PIC_FN_ADDR_REG", \
1848 /* coprocessor registers */ \
1855 "COP0_AND_GR_REGS", \
1856 "COP2_AND_GR_REGS", \
1857 "COP3_AND_GR_REGS", \
1859 "ALL_COP_AND_GR_REGS", \
1864 /* An initializer containing the contents of the register classes,
1865 as integers which are bit masks. The Nth integer specifies the
1866 contents of class N. The way the integer MASK is interpreted is
1867 that register R is in the class if `MASK & (1 << R)' is 1.
1869 When the machine has more than 32 registers, an integer does not
1870 suffice. Then the integers are replaced by sub-initializers,
1871 braced groupings containing several integers. Each
1872 sub-initializer must be suitable as an initializer for the type
1873 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1875 #define REG_CLASS_CONTENTS \
1877 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1878 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1879 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1880 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1881 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1882 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1883 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1884 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1885 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1886 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1887 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1888 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1889 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1890 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1891 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1892 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1893 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1894 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1895 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1896 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1897 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1898 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1899 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1900 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1901 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1905 /* A C expression whose value is a register class containing hard
1906 register REGNO. In general there is more that one such class;
1907 choose a class which is "minimal", meaning that no smaller class
1908 also contains the register. */
1910 extern const enum reg_class mips_regno_to_class[];
1912 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1914 /* A macro whose definition is the name of the class to which a
1915 valid base register must belong. A base register is one used in
1916 an address which is the register value plus a displacement. */
1918 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1920 /* A macro whose definition is the name of the class to which a
1921 valid index register must belong. An index register is one used
1922 in an address where its value is either multiplied by a scale
1923 factor or added to another register (as well as added to a
1926 #define INDEX_REG_CLASS NO_REGS
1928 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1929 registers explicitly used in the rtl to be used as spill registers
1930 but prevents the compiler from extending the lifetime of these
1933 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1935 /* This macro is used later on in the file. */
1936 #define GR_REG_CLASS_P(CLASS) \
1937 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1938 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1939 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1941 /* This macro is also used later on in the file. */
1942 #define COP_REG_CLASS_P(CLASS) \
1943 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1945 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1946 is the default value (allocate the registers in numeric order). We
1947 define it just so that we can override it for the mips16 target in
1948 ORDER_REGS_FOR_LOCAL_ALLOC. */
1950 #define REG_ALLOC_ORDER \
1951 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1952 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1953 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1954 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1955 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1956 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1957 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1958 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1959 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1960 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1961 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1964 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1965 to be rearranged based on a particular function. On the mips16, we
1966 want to allocate $24 (T_REG) before other registers for
1967 instructions for which it is possible. */
1969 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1971 /* REGISTER AND CONSTANT CLASSES */
1973 /* Get reg_class from a letter such as appears in the machine
1976 DEFINED REGISTER CLASSES:
1978 'd' General (aka integer) registers
1979 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1980 'y' General registers (in both mips16 and non mips16 mode)
1981 'e' mips16 non argument registers (M16_NA_REGS)
1982 't' mips16 temporary register ($24)
1983 'f' Floating point registers
1986 'x' Multiply/divide registers
1987 'z' FP Status register
1991 'b' All registers */
1993 extern enum reg_class mips_char_to_class[256];
1995 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1997 /* True if VALUE is a signed 16-bit number. */
1999 #define SMALL_OPERAND(VALUE) \
2000 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2002 /* True if VALUE is an unsigned 16-bit number. */
2004 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2005 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2007 /* True if VALUE can be loaded into a register using LUI. */
2009 #define LUI_OPERAND(VALUE) \
2010 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2011 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2013 /* Return a value X with the low 16 bits clear, and such that
2014 VALUE - X is a signed 16-bit value. */
2016 #define CONST_HIGH_PART(VALUE) \
2017 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2019 #define CONST_LOW_PART(VALUE) \
2020 ((VALUE) - CONST_HIGH_PART (VALUE))
2022 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2023 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2024 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2026 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2027 string can be used to stand for particular ranges of immediate
2028 operands. This macro defines what the ranges are. C is the
2029 letter, and VALUE is a constant value. Return 1 if VALUE is
2030 in the range specified by C. */
2034 `I' is used for the range of constants an arithmetic insn can
2035 actually contain (16 bits signed integers).
2037 `J' is used for the range which is just zero (ie, $r0).
2039 `K' is used for the range of constants a logical insn can actually
2040 contain (16 bit zero-extended integers).
2042 `L' is used for the range of constants that be loaded with lui
2043 (ie, the bottom 16 bits are zero).
2045 `M' is used for the range of constants that take two words to load
2046 (ie, not matched by `I', `K', and `L').
2048 `N' is used for negative 16 bit constants other than -65536.
2050 `O' is a 15 bit signed integer.
2052 `P' is used for positive 16 bit constants. */
2054 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2055 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2056 : (C) == 'J' ? ((VALUE) == 0) \
2057 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2058 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2059 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2060 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2061 && !LUI_OPERAND (VALUE)) \
2062 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2063 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2064 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2067 /* Similar, but for floating constants, and defining letters G and H.
2068 Here VALUE is the CONST_DOUBLE rtx itself. */
2072 'G' : Floating point 0 */
2074 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2076 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2078 /* True if OP is a constant that should not be moved into $25.
2079 We need this because many versions of gas treat 'la $25,foo' as
2080 part of a call sequence and allow a global 'foo' to be lazily bound. */
2082 #define DANGEROUS_FOR_LA25_P(OP) \
2084 && !TARGET_EXPLICIT_RELOCS \
2085 && mips_global_pic_constant_p (OP))
2087 /* Letters in the range `Q' through `U' may be defined in a
2088 machine-dependent fashion to stand for arbitrary operand types.
2089 The machine description macro `EXTRA_CONSTRAINT' is passed the
2090 operand as its first argument and the constraint letter as its
2093 `Q' is for signed 16-bit constants.
2094 `R' is for single-instruction memory references. Note that this
2095 constraint has often been used in linux and glibc code.
2096 `S' is for legitimate constant call addresses.
2097 `T' is for constant move_operands that cannot be safely loaded into $25.
2098 `U' is for constant move_operands that can be safely loaded into $25. */
2100 #define EXTRA_CONSTRAINT(OP,CODE) \
2101 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2102 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2103 && mips_fetch_insns (OP) == 1) \
2104 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2105 && call_insn_operand (OP, VOIDmode)) \
2106 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2107 && move_operand (OP, VOIDmode) \
2108 && DANGEROUS_FOR_LA25_P (OP)) \
2109 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2110 && move_operand (OP, VOIDmode) \
2111 && !DANGEROUS_FOR_LA25_P (OP)) \
2114 /* Given an rtx X being reloaded into a reg required to be
2115 in class CLASS, return the class of reg to actually use.
2116 In general this is just CLASS; but on some machines
2117 in some cases it is preferable to use a more restrictive class. */
2119 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2120 ((CLASS) != ALL_REGS \
2121 ? (! TARGET_MIPS16 \
2123 : ((CLASS) != GR_REGS \
2126 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2127 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2128 ? (TARGET_SOFT_FLOAT \
2129 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2131 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2132 || GET_MODE (X) == VOIDmode) \
2133 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2136 /* Certain machines have the property that some registers cannot be
2137 copied to some other registers without using memory. Define this
2138 macro on those machines to be a C expression that is nonzero if
2139 objects of mode MODE in registers of CLASS1 can only be copied to
2140 registers of class CLASS2 by storing a register of CLASS1 into
2141 memory and loading that memory location into a register of CLASS2.
2143 Do not define this macro if its value would always be zero. */
2145 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2146 ((!TARGET_DEBUG_H_MODE \
2147 && GET_MODE_CLASS (MODE) == MODE_INT \
2148 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2149 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2150 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2151 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2152 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2154 /* The HI and LO registers can only be reloaded via the general
2155 registers. Condition code registers can only be loaded to the
2156 general registers, and from the floating point registers. */
2158 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2159 mips_secondary_reload_class (CLASS, MODE, X, 1)
2160 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2161 mips_secondary_reload_class (CLASS, MODE, X, 0)
2163 /* Return the maximum number of consecutive registers
2164 needed to represent mode MODE in a register of class CLASS. */
2166 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2168 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2169 mips_cannot_change_mode_class (FROM, TO, CLASS)
2171 /* Stack layout; function entry, exit and calling. */
2173 #define STACK_GROWS_DOWNWARD
2175 /* The offset of the first local variable from the beginning of the frame.
2176 See compute_frame_size for details about the frame layout. */
2177 #define STARTING_FRAME_OFFSET \
2178 (current_function_outgoing_args_size \
2179 + (TARGET_ABICALLS && !TARGET_NEWABI \
2180 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2182 /* The return address for the current frame is in r31 if this is a leaf
2183 function. Otherwise, it is on the stack. It is at a variable offset
2184 from sp/fp/ap, so we define a fake hard register rap which is a
2185 pointer to the return address on the stack. This always gets eliminated
2186 during reload to be either the frame pointer or the stack pointer plus
2189 #define RETURN_ADDR_RTX mips_return_addr
2191 /* Since the mips16 ISA mode is encoded in the least-significant bit
2192 of the address, mask it off return addresses for purposes of
2193 finding exception handling regions. */
2195 #define MASK_RETURN_ADDR GEN_INT (-2)
2198 /* Similarly, don't use the least-significant bit to tell pointers to
2199 code from vtable index. */
2201 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2203 /* If defined, this macro specifies a table of register pairs used to
2204 eliminate unneeded registers that point into the stack frame. If
2205 it is not defined, the only elimination attempted by the compiler
2206 is to replace references to the frame pointer with references to
2209 The definition of this macro is a list of structure
2210 initializations, each of which specifies an original and
2211 replacement register.
2213 On some machines, the position of the argument pointer is not
2214 known until the compilation is completed. In such a case, a
2215 separate hard register must be used for the argument pointer.
2216 This register can be eliminated by replacing it with either the
2217 frame pointer or the argument pointer, depending on whether or not
2218 the frame pointer has been eliminated.
2220 In this case, you might specify:
2221 #define ELIMINABLE_REGS \
2222 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2223 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2224 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2226 Note that the elimination of the argument pointer with the stack
2227 pointer is specified first since that is the preferred elimination.
2229 The eliminations to $17 are only used on the mips16. See the
2230 definition of HARD_FRAME_POINTER_REGNUM. */
2232 #define ELIMINABLE_REGS \
2233 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2234 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2235 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2236 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2237 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2238 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2240 /* A C expression that returns nonzero if the compiler is allowed to
2241 try to replace register number FROM-REG with register number
2242 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2243 defined, and will usually be the constant 1, since most of the
2244 cases preventing register elimination are things that the compiler
2245 already knows about.
2247 When not in mips16 and mips64, we can always eliminate to the
2248 frame pointer. We can eliminate to the stack pointer unless
2249 a frame pointer is needed. In mips16 mode, we need a frame
2250 pointer for a large frame; otherwise, reload may be unable
2251 to compute the address of a local variable, since there is
2252 no way to add a large constant to the stack pointer
2253 without using a temporary register.
2255 In mips16, for some instructions (eg lwu), we can't eliminate the
2256 frame pointer for the stack pointer. These instructions are
2257 only generated in TARGET_64BIT mode.
2260 #define CAN_ELIMINATE(FROM, TO) \
2261 (((TO) == HARD_FRAME_POINTER_REGNUM \
2262 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2263 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2264 && (! TARGET_MIPS16 \
2265 || compute_frame_size (get_frame_size ()) < 32768))))
2267 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2268 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2270 /* If defined, the maximum amount of space required for outgoing
2271 arguments will be computed and placed into the variable
2272 `current_function_outgoing_args_size'. No space will be pushed
2273 onto the stack for each call; instead, the function prologue
2274 should increase the stack frame size by this amount.
2276 It is not proper to define both `PUSH_ROUNDING' and
2277 `ACCUMULATE_OUTGOING_ARGS'. */
2278 #define ACCUMULATE_OUTGOING_ARGS 1
2280 /* Offset from the argument pointer register to the first argument's
2281 address. On some machines it may depend on the data type of the
2284 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2285 the first argument's address.
2287 On the MIPS, we must skip the first argument position if we are
2288 returning a structure or a union, to account for its address being
2289 passed in $4. However, at the current time, this produces a compiler
2290 that can't bootstrap, so comment it out for now. */
2293 #define FIRST_PARM_OFFSET(FNDECL) \
2295 && TREE_TYPE (FNDECL) != 0 \
2296 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2297 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2298 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2302 #define FIRST_PARM_OFFSET(FNDECL) 0
2305 /* When a parameter is passed in a register, stack space is still
2306 allocated for it. For the MIPS, stack space must be allocated, cf
2307 Asm Lang Prog Guide page 7-8.
2309 BEWARE that some space is also allocated for non existing arguments
2310 in register. In case an argument list is of form GF used registers
2311 are a0 (a2,a3), but we should push over a1... */
2313 #define REG_PARM_STACK_SPACE(FNDECL) \
2314 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2315 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2318 /* Define this if it is the responsibility of the caller to
2319 allocate the area reserved for arguments passed in registers.
2320 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2321 of this macro is to determine whether the space is included in
2322 `current_function_outgoing_args_size'. */
2323 #define OUTGOING_REG_PARM_STACK_SPACE
2325 #define STACK_BOUNDARY \
2326 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2330 /* A C expression that should indicate the number of bytes of its
2331 own arguments that a function pops on returning, or 0
2332 if the function pops no arguments and the caller must therefore
2333 pop them all after the function returns.
2335 FUNDECL is the declaration node of the function (as a tree).
2337 FUNTYPE is a C variable whose value is a tree node that
2338 describes the function in question. Normally it is a node of
2339 type `FUNCTION_TYPE' that describes the data type of the function.
2340 From this it is possible to obtain the data types of the value
2341 and arguments (if known).
2343 When a call to a library function is being considered, FUNTYPE
2344 will contain an identifier node for the library function. Thus,
2345 if you need to distinguish among various library functions, you
2346 can do so by their names. Note that "library function" in this
2347 context means a function used to perform arithmetic, whose name
2348 is known specially in the compiler and was not mentioned in the
2349 C code being compiled.
2351 STACK-SIZE is the number of bytes of arguments passed on the
2352 stack. If a variable number of bytes is passed, it is zero, and
2353 argument popping will always be the responsibility of the
2354 calling function. */
2356 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2359 /* Symbolic macros for the registers used to return integer and floating
2362 #define GP_RETURN (GP_REG_FIRST + 2)
2363 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2365 #define MAX_ARGS_IN_REGISTERS \
2366 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2368 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2370 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2372 /* Symbolic macros for the first/last argument registers. */
2374 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2375 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2376 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2377 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2379 /* Define how to find the value returned by a library function
2380 assuming the value has mode MODE. Because we define
2381 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2382 PROMOTE_MODE does. */
2384 #define LIBCALL_VALUE(MODE) \
2385 mips_function_value (NULL_TREE, NULL, (MODE))
2387 /* Define how to find the value returned by a function.
2388 VALTYPE is the data type of the value (as a tree).
2389 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2390 otherwise, FUNC is 0. */
2392 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2393 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2395 /* 1 if N is a possible register number for a function value.
2396 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2397 Currently, R2 and F0 are only implemented here (C has no complex type) */
2399 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2400 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2401 && (N) == FP_RETURN + 2))
2403 /* 1 if N is a possible register number for function argument passing.
2404 We have no FP argument registers when soft-float. When FP registers
2405 are 32 bits, we can't directly reference the odd numbered ones. */
2407 #define FUNCTION_ARG_REGNO_P(N) \
2408 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2409 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2410 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2413 /* A C expression which can inhibit the returning of certain function
2414 values in registers, based on the type of value. A nonzero value says
2415 to return the function value in memory, just as large structures are
2416 always returned. Here TYPE will be a C expression of type
2417 `tree', representing the data type of the value.
2419 Note that values of mode `BLKmode' must be explicitly
2420 handled by this macro. Also, the option `-fpcc-struct-return'
2421 takes effect regardless of this macro. On most systems, it is
2422 possible to leave the macro undefined; this causes a default
2423 definition to be used, whose value is the constant 1 for BLKmode
2424 values, and 0 otherwise.
2426 GCC normally converts 1 byte structures into chars, 2 byte
2427 structs into shorts, and 4 byte structs into ints, and returns
2428 them this way. Defining the following macro overrides this,
2429 to give us MIPS cc compatibility. */
2431 #define RETURN_IN_MEMORY(TYPE) \
2432 mips_return_in_memory (TYPE)
2434 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2435 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2438 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2440 /* Define a data type for recording info about an argument list
2441 during the scan of that argument list. This data type should
2442 hold all necessary information about the function itself
2443 and about the args processed so far, enough to enable macros
2444 such as FUNCTION_ARG to determine where the next arg should go.
2446 This structure has to cope with two different argument allocation
2447 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2448 first N words go in registers and the rest go on the stack. If I < N,
2449 the Ith word might go in Ith integer argument register or the
2450 Ith floating-point one. In some cases, it has to go in both (see
2451 function_arg). For these ABIs, we only need to remember the number
2452 of words passed so far.
2454 The EABI instead allocates the integer and floating-point arguments
2455 separately. The first N words of FP arguments go in FP registers,
2456 the rest go on the stack. Likewise, the first N words of the other
2457 arguments go in integer registers, and the rest go on the stack. We
2458 need to maintain three counts: the number of integer registers used,
2459 the number of floating-point registers used, and the number of words
2460 passed on the stack.
2462 We could keep separate information for the two ABIs (a word count for
2463 the standard ABIs, and three separate counts for the EABI). But it
2464 seems simpler to view the standard ABIs as forms of EABI that do not
2465 allocate floating-point registers.
2467 So for the standard ABIs, the first N words are allocated to integer
2468 registers, and function_arg decides on an argument-by-argument basis
2469 whether that argument should really go in an integer register, or in
2470 a floating-point one. */
2472 typedef struct mips_args {
2473 /* Always true for varargs functions. Otherwise true if at least
2474 one argument has been passed in an integer register. */
2477 /* The number of arguments seen so far. */
2478 unsigned int arg_number;
2480 /* For EABI, the number of integer registers used so far. For other
2481 ABIs, the number of words passed in registers (whether integer
2482 or floating-point). */
2483 unsigned int num_gprs;
2485 /* For EABI, the number of floating-point registers used so far. */
2486 unsigned int num_fprs;
2488 /* The number of words passed on the stack. */
2489 unsigned int stack_words;
2491 /* On the mips16, we need to keep track of which floating point
2492 arguments were passed in general registers, but would have been
2493 passed in the FP regs if this were a 32 bit function, so that we
2494 can move them to the FP regs if we wind up calling a 32 bit
2495 function. We record this information in fp_code, encoded in base
2496 four. A zero digit means no floating point argument, a one digit
2497 means an SFmode argument, and a two digit means a DFmode argument,
2498 and a three digit is not used. The low order digit is the first
2499 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2500 an SFmode argument. ??? A more sophisticated approach will be
2501 needed if MIPS_ABI != ABI_32. */
2504 /* True if the function has a prototype. */
2507 /* When a structure does not take up a full register, the argument
2508 should sometimes be shifted left so that it occupies the high part
2509 of the register. These two fields describe an array of ashl
2510 patterns for doing this. See function_arg_advance, which creates
2511 the shift patterns, and function_arg, which returns them when given
2512 a VOIDmode argument. */
2513 unsigned int num_adjusts;
2514 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2517 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2518 for a call to a function whose data type is FNTYPE.
2519 For a library call, FNTYPE is 0.
2523 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2524 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2526 /* Update the data in CUM to advance over an argument
2527 of mode MODE and data type TYPE.
2528 (TYPE is null for libcalls where that information may not be available.) */
2530 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2531 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2533 /* Determine where to put an argument to a function.
2534 Value is zero to push the argument on the stack,
2535 or a hard register in which to store the argument.
2537 MODE is the argument's machine mode.
2538 TYPE is the data type of the argument (as a tree).
2539 This is null for libcalls where that information may
2541 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2542 the preceding args and about the function being called.
2543 NAMED is nonzero if this argument is a named parameter
2544 (otherwise it is an extra parameter matching an ellipsis). */
2546 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2547 function_arg( &CUM, MODE, TYPE, NAMED)
2549 /* For an arg passed partly in registers and partly in memory,
2550 this is the number of registers used.
2551 For args passed entirely in registers or entirely in memory, zero. */
2553 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2554 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2556 /* If defined, a C expression that gives the alignment boundary, in
2557 bits, of an argument with the specified mode and type. If it is
2558 not defined, `PARM_BOUNDARY' is used for all arguments. */
2560 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2562 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2564 : TYPE_ALIGN(TYPE)) \
2565 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2567 : GET_MODE_ALIGNMENT(MODE)))
2569 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2570 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2572 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2573 (! BYTES_BIG_ENDIAN \
2575 : (((MODE) == BLKmode \
2576 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2577 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2578 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2579 && (mips_abi == ABI_32 \
2580 || mips_abi == ABI_O64 \
2581 || mips_abi == ABI_EABI \
2582 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2583 ? downward : upward))
2585 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2586 (mips_abi == ABI_EABI && (NAMED) \
2587 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2589 /* Modified version of the macro in expr.h. */
2590 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2592 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2593 || TREE_ADDRESSABLE (TYPE) \
2594 || ((MODE) == BLKmode \
2595 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2596 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2597 && 0 == (int_size_in_bytes (TYPE) \
2598 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2599 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2600 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2602 /* True if using EABI and varargs can be passed in floating-point
2603 registers. Under these conditions, we need a more complex form
2604 of va_list, which tracks GPR, FPR and stack arguments separately. */
2605 #define EABI_FLOAT_VARARGS_P \
2606 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2609 /* Say that the epilogue uses the return address register. Note that
2610 in the case of sibcalls, the values "used by the epilogue" are
2611 considered live at the start of the called function. */
2612 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2614 /* Treat LOC as a byte offset from the stack pointer and round it up
2615 to the next fully-aligned offset. */
2616 #define MIPS_STACK_ALIGN(LOC) \
2617 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2618 ? ((LOC) + 7) & ~7 \
2619 : ((LOC) + 15) & ~15)
2622 /* Define the `__builtin_va_list' type for the ABI. */
2623 #define BUILD_VA_LIST_TYPE(VALIST) \
2624 (VALIST) = mips_build_va_list ()
2626 /* Implement `va_start' for varargs and stdarg. */
2627 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2628 mips_va_start (valist, nextarg)
2630 /* Implement `va_arg'. */
2631 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2632 mips_va_arg (valist, type)
2634 /* Output assembler code to FILE to increment profiler label # LABELNO
2635 for profiling a function entry. */
2637 #define FUNCTION_PROFILER(FILE, LABELNO) \
2639 if (TARGET_MIPS16) \
2640 sorry ("mips16 function profiling"); \
2641 fprintf (FILE, "\t.set\tnoat\n"); \
2642 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2643 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2644 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2647 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2648 TARGET_64BIT ? "dsubu" : "subu", \
2649 reg_names[STACK_POINTER_REGNUM], \
2650 reg_names[STACK_POINTER_REGNUM], \
2651 Pmode == DImode ? 16 : 8); \
2653 fprintf (FILE, "\tjal\t_mcount\n"); \
2654 fprintf (FILE, "\t.set\tat\n"); \
2657 /* Define this macro if the code for function profiling should come
2658 before the function prologue. Normally, the profiling code comes
2661 /* #define PROFILE_BEFORE_PROLOGUE */
2663 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2664 the stack pointer does not matter. The value is tested only in
2665 functions that have frame pointers.
2666 No definition is equivalent to always zero. */
2668 #define EXIT_IGNORE_STACK 1
2671 /* A C statement to output, on the stream FILE, assembler code for a
2672 block of data that contains the constant parts of a trampoline.
2673 This code should not include a label--the label is taken care of
2676 #define TRAMPOLINE_TEMPLATE(STREAM) \
2678 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2679 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2680 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2681 if (ptr_mode == DImode) \
2683 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2684 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2688 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2689 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2691 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2692 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2693 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2694 if (ptr_mode == DImode) \
2696 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2697 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2701 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2702 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2706 /* A C expression for the size in bytes of the trampoline, as an
2709 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2711 /* Alignment required for trampolines, in bits. */
2713 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2715 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2716 program and data caches. */
2718 #ifndef CACHE_FLUSH_FUNC
2719 #define CACHE_FLUSH_FUNC "_flush_cache"
2722 /* A C statement to initialize the variable parts of a trampoline.
2723 ADDR is an RTX for the address of the trampoline; FNADDR is an
2724 RTX for the address of the nested function; STATIC_CHAIN is an
2725 RTX for the static chain value that should be passed to the
2726 function when it is called. */
2728 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2730 rtx func_addr, chain_addr; \
2732 func_addr = plus_constant (ADDR, 32); \
2733 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2734 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2735 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2736 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2737 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
2739 /* Flush both caches. We need to flush the data cache in case \
2740 the system has a write-back cache. */ \
2741 /* ??? Should check the return value for errors. */ \
2742 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2743 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2744 0, VOIDmode, 3, ADDR, Pmode, \
2745 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2746 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2749 /* Addressing modes, and classification of registers for them. */
2751 /* These assume that REGNO is a hard or pseudo reg number.
2752 They give nonzero only if REGNO is a hard reg of the suitable class
2753 or a pseudo reg currently allocated to a suitable hard reg.
2754 These definitions are NOT overridden anywhere. */
2756 #define BASE_REG_P(regno, mode) \
2758 ? (M16_REG_P (regno) \
2759 || (regno) == FRAME_POINTER_REGNUM \
2760 || (regno) == ARG_POINTER_REGNUM \
2761 || ((regno) == STACK_POINTER_REGNUM \
2762 && (GET_MODE_SIZE (mode) == 4 \
2763 || GET_MODE_SIZE (mode) == 8))) \
2766 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2767 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2770 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2771 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2773 #define REGNO_OK_FOR_INDEX_P(regno) 0
2774 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2775 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2777 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2778 and check its validity for a certain class.
2779 We have two alternate definitions for each of them.
2780 The usual definition accepts all pseudo regs; the other rejects them all.
2781 The symbol REG_OK_STRICT causes the latter definition to be used.
2783 Most source files want to accept pseudo regs in the hope that
2784 they will get allocated to the class that the insn wants them to be in.
2785 Some source files that are used after register allocation
2786 need to be strict. */
2788 #ifndef REG_OK_STRICT
2789 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2790 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2792 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2793 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2796 #define REG_OK_FOR_INDEX_P(X) 0
2799 /* Maximum number of registers that can appear in a valid memory address. */
2801 #define MAX_REGS_PER_ADDRESS 1
2803 /* A C compound statement with a conditional `goto LABEL;' executed
2804 if X (an RTX) is a legitimate memory address on the target
2805 machine for a memory operand of mode MODE. */
2808 #define GO_PRINTF(x) fprintf(stderr, (x))
2809 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2810 #define GO_DEBUG_RTX(x) debug_rtx(x)
2813 #define GO_PRINTF(x)
2814 #define GO_PRINTF2(x,y)
2815 #define GO_DEBUG_RTX(x)
2818 #ifdef REG_OK_STRICT
2819 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2821 if (mips_legitimate_address_p (MODE, X, 1)) \
2825 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2827 if (mips_legitimate_address_p (MODE, X, 0)) \
2832 /* Check for constness inline but use mips_legitimate_address_p
2833 to check whether a constant really is an address. */
2835 #define CONSTANT_ADDRESS_P(X) \
2836 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2839 /* Nonzero if the constant value X is a legitimate general operand.
2840 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2842 At present, GAS doesn't understand li.[sd], so don't allow it
2843 to be generated at present. Also, the MIPS assembler does not
2844 grok li.d Infinity. */
2846 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2847 Note that the Irix 6 assembler problem may already be fixed.
2848 Note also that the GET_CODE (X) == CONST test catches the mips16
2849 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2850 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2851 ABI_64 to work together, we'll need to fix this. */
2852 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2854 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2856 if (mips_legitimize_address (&(X), MODE)) \
2861 /* A C statement or compound statement with a conditional `goto
2862 LABEL;' executed if memory address X (an RTX) can have different
2863 meanings depending on the machine mode of the memory reference it
2866 Autoincrement and autodecrement addresses typically have
2867 mode-dependent effects because the amount of the increment or
2868 decrement is the size of the operand being addressed. Some
2869 machines have other mode-dependent addresses. Many RISC machines
2870 have no mode-dependent addresses.
2872 You may assume that ADDR is a valid address for the machine. */
2874 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2876 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2877 'the start of the function that this code is output in'. */
2879 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2880 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2881 asm_fprintf ((FILE), "%U%s", \
2882 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2884 asm_fprintf ((FILE), "%U%s", (NAME))
2886 /* The mips16 wants the constant pool to be after the function,
2887 because the PC relative load instructions use unsigned offsets. */
2889 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
2891 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
2892 mips_string_length = 0;
2894 /* Specify the machine mode that this machine uses
2895 for the index in the tablejump instruction.
2896 ??? Using HImode in mips16 mode can cause overflow. However, the
2897 overflow is no more likely than the overflow in a branch
2898 instruction. Large functions can currently break in both ways. */
2899 #define CASE_VECTOR_MODE \
2900 (TARGET_MIPS16 ? HImode : ptr_mode)
2902 /* Define as C expression which evaluates to nonzero if the tablejump
2903 instruction expects the table to contain offsets from the address of the
2905 Do not define this if the table should contain absolute addresses. */
2906 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2908 /* Define this as 1 if `char' should by default be signed; else as 0. */
2909 #ifndef DEFAULT_SIGNED_CHAR
2910 #define DEFAULT_SIGNED_CHAR 1
2913 /* Max number of bytes we can move from memory to memory
2914 in one reasonably fast instruction. */
2915 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2916 #define MAX_MOVE_MAX 8
2918 /* Define this macro as a C expression which is nonzero if
2919 accessing less than a word of memory (i.e. a `char' or a
2920 `short') is no faster than accessing a word of memory, i.e., if
2921 such access require more than one instruction or if there is no
2922 difference in cost between byte and (aligned) word loads.
2924 On RISC machines, it tends to generate better code to define
2925 this as 1, since it avoids making a QI or HI mode register. */
2926 #define SLOW_BYTE_ACCESS 1
2928 /* Define this to be nonzero if shift instructions ignore all but the low-order
2930 #define SHIFT_COUNT_TRUNCATED 1
2932 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2933 is done just by pretending it is already truncated. */
2934 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2935 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2938 /* Specify the machine mode that pointers have.
2939 After generation of rtl, the compiler makes no further distinction
2940 between pointers and any other objects of this machine mode. */
2943 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2946 /* Give call MEMs SImode since it is the "most permissive" mode
2947 for both 32-bit and 64-bit targets. */
2949 #define FUNCTION_MODE SImode
2952 /* The cost of loading values from the constant pool. It should be
2953 larger than the cost of any constant we want to synthesize in-line. */
2955 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2957 /* A C expression for the cost of moving data from a register in
2958 class FROM to one in class TO. The classes are expressed using
2959 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2960 the default; other values are interpreted relative to that.
2962 It is not required that the cost always equal 2 when FROM is the
2963 same as TO; on some machines it is expensive to move between
2964 registers if they are not general registers.
2966 If reload sees an insn consisting of a single `set' between two
2967 hard registers, and if `REGISTER_MOVE_COST' applied to their
2968 classes returns a value of 2, reload does not check to ensure
2969 that the constraints of the insn are met. Setting a cost of
2970 other than 2 will allow reload to verify that the constraints are
2971 met. You should do this if the `movM' pattern's constraints do
2972 not allow such copying. */
2974 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2975 mips_register_move_cost (MODE, FROM, TO)
2977 /* ??? Fix this to be right for the R8000. */
2978 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2979 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2980 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2982 /* Define if copies to/from condition code registers should be avoided.
2984 This is needed for the MIPS because reload_outcc is not complete;
2985 it needs to handle cases where the source is a general or another
2986 condition code register. */
2987 #define AVOID_CCMODE_COPIES
2989 /* A C expression for the cost of a branch instruction. A value of
2990 1 is the default; other values are interpreted relative to that. */
2992 /* ??? Fix this to be right for the R8000. */
2993 #define BRANCH_COST \
2995 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2998 /* If defined, modifies the length assigned to instruction INSN as a
2999 function of the context in which it is used. LENGTH is an lvalue
3000 that contains the initially computed length of the insn and should
3001 be updated with the correct length of the insn. */
3002 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3003 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3006 /* Optionally define this if you have added predicates to
3007 `MACHINE.c'. This macro is called within an initializer of an
3008 array of structures. The first field in the structure is the
3009 name of a predicate and the second field is an array of rtl
3010 codes. For each predicate, list all rtl codes that can be in
3011 expressions matched by the predicate. The list should have a
3012 trailing comma. Here is an example of two entries in the list
3013 for a typical RISC machine:
3015 #define PREDICATE_CODES \
3016 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3017 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3019 Defining this macro does not affect the generated code (however,
3020 incorrect definitions that omit an rtl code that may be matched
3021 by the predicate can cause the compiler to malfunction).
3022 Instead, it allows the table built by `genrecog' to be more
3023 compact and efficient, thus speeding up the compiler. The most
3024 important predicates to include in the list specified by this
3025 macro are thoses used in the most insn patterns. */
3027 #define PREDICATE_CODES \
3028 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3029 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3030 {"const_arith_operand", { CONST, CONST_INT }}, \
3031 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3032 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3033 {"small_int", { CONST_INT }}, \
3034 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3035 {"const_float_1_operand", { CONST_DOUBLE }}, \
3036 {"simple_memory_operand", { MEM, SUBREG }}, \
3037 {"equality_op", { EQ, NE }}, \
3038 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3040 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3041 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3042 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
3043 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3044 SYMBOL_REF, LABEL_REF, SUBREG, \
3046 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3047 CONST_DOUBLE, CONST }}, \
3048 {"fcc_register_operand", { REG, SUBREG }}, \
3049 {"hilo_operand", { REG }}, \
3050 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
3052 /* A list of predicates that do special things with modes, and so
3053 should not elicit warnings for VOIDmode match_operand. */
3055 #define SPECIAL_MODE_PREDICATES \
3056 "pc_or_label_operand",
3058 /* Control the assembler format that we output. */
3060 /* Output to assembler file text saying following lines
3061 may contain character constants, extra white space, comments, etc. */
3064 #define ASM_APP_ON " #APP\n"
3067 /* Output to assembler file text saying following lines
3068 no longer contain unusual constructs. */
3071 #define ASM_APP_OFF " #NO_APP\n"
3074 /* How to refer to registers in assembler output.
3075 This sequence is indexed by compiler's hard-register-number (see above).
3077 In order to support the two different conventions for register names,
3078 we use the name of a table set up in mips.c, which is overwritten
3079 if -mrnames is used. */
3081 #define REGISTER_NAMES \
3083 &mips_reg_names[ 0][0], \
3084 &mips_reg_names[ 1][0], \
3085 &mips_reg_names[ 2][0], \
3086 &mips_reg_names[ 3][0], \
3087 &mips_reg_names[ 4][0], \
3088 &mips_reg_names[ 5][0], \
3089 &mips_reg_names[ 6][0], \
3090 &mips_reg_names[ 7][0], \
3091 &mips_reg_names[ 8][0], \
3092 &mips_reg_names[ 9][0], \
3093 &mips_reg_names[10][0], \
3094 &mips_reg_names[11][0], \
3095 &mips_reg_names[12][0], \
3096 &mips_reg_names[13][0], \
3097 &mips_reg_names[14][0], \
3098 &mips_reg_names[15][0], \
3099 &mips_reg_names[16][0], \
3100 &mips_reg_names[17][0], \
3101 &mips_reg_names[18][0], \
3102 &mips_reg_names[19][0], \
3103 &mips_reg_names[20][0], \
3104 &mips_reg_names[21][0], \
3105 &mips_reg_names[22][0], \
3106 &mips_reg_names[23][0], \
3107 &mips_reg_names[24][0], \
3108 &mips_reg_names[25][0], \
3109 &mips_reg_names[26][0], \
3110 &mips_reg_names[27][0], \
3111 &mips_reg_names[28][0], \
3112 &mips_reg_names[29][0], \
3113 &mips_reg_names[30][0], \
3114 &mips_reg_names[31][0], \
3115 &mips_reg_names[32][0], \
3116 &mips_reg_names[33][0], \
3117 &mips_reg_names[34][0], \
3118 &mips_reg_names[35][0], \
3119 &mips_reg_names[36][0], \
3120 &mips_reg_names[37][0], \
3121 &mips_reg_names[38][0], \
3122 &mips_reg_names[39][0], \
3123 &mips_reg_names[40][0], \
3124 &mips_reg_names[41][0], \
3125 &mips_reg_names[42][0], \
3126 &mips_reg_names[43][0], \
3127 &mips_reg_names[44][0], \
3128 &mips_reg_names[45][0], \
3129 &mips_reg_names[46][0], \
3130 &mips_reg_names[47][0], \
3131 &mips_reg_names[48][0], \
3132 &mips_reg_names[49][0], \
3133 &mips_reg_names[50][0], \
3134 &mips_reg_names[51][0], \
3135 &mips_reg_names[52][0], \
3136 &mips_reg_names[53][0], \
3137 &mips_reg_names[54][0], \
3138 &mips_reg_names[55][0], \
3139 &mips_reg_names[56][0], \
3140 &mips_reg_names[57][0], \
3141 &mips_reg_names[58][0], \
3142 &mips_reg_names[59][0], \
3143 &mips_reg_names[60][0], \
3144 &mips_reg_names[61][0], \
3145 &mips_reg_names[62][0], \
3146 &mips_reg_names[63][0], \
3147 &mips_reg_names[64][0], \
3148 &mips_reg_names[65][0], \
3149 &mips_reg_names[66][0], \
3150 &mips_reg_names[67][0], \
3151 &mips_reg_names[68][0], \
3152 &mips_reg_names[69][0], \
3153 &mips_reg_names[70][0], \
3154 &mips_reg_names[71][0], \
3155 &mips_reg_names[72][0], \
3156 &mips_reg_names[73][0], \
3157 &mips_reg_names[74][0], \
3158 &mips_reg_names[75][0], \
3159 &mips_reg_names[76][0], \
3160 &mips_reg_names[77][0], \
3161 &mips_reg_names[78][0], \
3162 &mips_reg_names[79][0], \
3163 &mips_reg_names[80][0], \
3164 &mips_reg_names[81][0], \
3165 &mips_reg_names[82][0], \
3166 &mips_reg_names[83][0], \
3167 &mips_reg_names[84][0], \
3168 &mips_reg_names[85][0], \
3169 &mips_reg_names[86][0], \
3170 &mips_reg_names[87][0], \
3171 &mips_reg_names[88][0], \
3172 &mips_reg_names[89][0], \
3173 &mips_reg_names[90][0], \
3174 &mips_reg_names[91][0], \
3175 &mips_reg_names[92][0], \
3176 &mips_reg_names[93][0], \
3177 &mips_reg_names[94][0], \
3178 &mips_reg_names[95][0], \
3179 &mips_reg_names[96][0], \
3180 &mips_reg_names[97][0], \
3181 &mips_reg_names[98][0], \
3182 &mips_reg_names[99][0], \
3183 &mips_reg_names[100][0], \
3184 &mips_reg_names[101][0], \
3185 &mips_reg_names[102][0], \
3186 &mips_reg_names[103][0], \
3187 &mips_reg_names[104][0], \
3188 &mips_reg_names[105][0], \
3189 &mips_reg_names[106][0], \
3190 &mips_reg_names[107][0], \
3191 &mips_reg_names[108][0], \
3192 &mips_reg_names[109][0], \
3193 &mips_reg_names[110][0], \
3194 &mips_reg_names[111][0], \
3195 &mips_reg_names[112][0], \
3196 &mips_reg_names[113][0], \
3197 &mips_reg_names[114][0], \
3198 &mips_reg_names[115][0], \
3199 &mips_reg_names[116][0], \
3200 &mips_reg_names[117][0], \
3201 &mips_reg_names[118][0], \
3202 &mips_reg_names[119][0], \
3203 &mips_reg_names[120][0], \
3204 &mips_reg_names[121][0], \
3205 &mips_reg_names[122][0], \
3206 &mips_reg_names[123][0], \
3207 &mips_reg_names[124][0], \
3208 &mips_reg_names[125][0], \
3209 &mips_reg_names[126][0], \
3210 &mips_reg_names[127][0], \
3211 &mips_reg_names[128][0], \
3212 &mips_reg_names[129][0], \
3213 &mips_reg_names[130][0], \
3214 &mips_reg_names[131][0], \
3215 &mips_reg_names[132][0], \
3216 &mips_reg_names[133][0], \
3217 &mips_reg_names[134][0], \
3218 &mips_reg_names[135][0], \
3219 &mips_reg_names[136][0], \
3220 &mips_reg_names[137][0], \
3221 &mips_reg_names[138][0], \
3222 &mips_reg_names[139][0], \
3223 &mips_reg_names[140][0], \
3224 &mips_reg_names[141][0], \
3225 &mips_reg_names[142][0], \
3226 &mips_reg_names[143][0], \
3227 &mips_reg_names[144][0], \
3228 &mips_reg_names[145][0], \
3229 &mips_reg_names[146][0], \
3230 &mips_reg_names[147][0], \
3231 &mips_reg_names[148][0], \
3232 &mips_reg_names[149][0], \
3233 &mips_reg_names[150][0], \
3234 &mips_reg_names[151][0], \
3235 &mips_reg_names[152][0], \
3236 &mips_reg_names[153][0], \
3237 &mips_reg_names[154][0], \
3238 &mips_reg_names[155][0], \
3239 &mips_reg_names[156][0], \
3240 &mips_reg_names[157][0], \
3241 &mips_reg_names[158][0], \
3242 &mips_reg_names[159][0], \
3243 &mips_reg_names[160][0], \
3244 &mips_reg_names[161][0], \
3245 &mips_reg_names[162][0], \
3246 &mips_reg_names[163][0], \
3247 &mips_reg_names[164][0], \
3248 &mips_reg_names[165][0], \
3249 &mips_reg_names[166][0], \
3250 &mips_reg_names[167][0], \
3251 &mips_reg_names[168][0], \
3252 &mips_reg_names[169][0], \
3253 &mips_reg_names[170][0], \
3254 &mips_reg_names[171][0], \
3255 &mips_reg_names[172][0], \
3256 &mips_reg_names[173][0], \
3257 &mips_reg_names[174][0], \
3258 &mips_reg_names[175][0] \
3261 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3262 So define this for it. */
3263 #define DEBUG_REGISTER_NAMES \
3265 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3266 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3267 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3268 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3269 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3270 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3271 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3272 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3273 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3274 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3275 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3276 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3277 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3278 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3279 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3280 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3281 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3282 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3283 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3284 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3285 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3286 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3289 /* If defined, a C initializer for an array of structures
3290 containing a name and a register number. This macro defines
3291 additional names for hard registers, thus allowing the `asm'
3292 option in declarations to refer to registers using alternate
3295 We define both names for the integer registers here. */
3297 #define ADDITIONAL_REGISTER_NAMES \
3299 { "$0", 0 + GP_REG_FIRST }, \
3300 { "$1", 1 + GP_REG_FIRST }, \
3301 { "$2", 2 + GP_REG_FIRST }, \
3302 { "$3", 3 + GP_REG_FIRST }, \
3303 { "$4", 4 + GP_REG_FIRST }, \
3304 { "$5", 5 + GP_REG_FIRST }, \
3305 { "$6", 6 + GP_REG_FIRST }, \
3306 { "$7", 7 + GP_REG_FIRST }, \
3307 { "$8", 8 + GP_REG_FIRST }, \
3308 { "$9", 9 + GP_REG_FIRST }, \
3309 { "$10", 10 + GP_REG_FIRST }, \
3310 { "$11", 11 + GP_REG_FIRST }, \
3311 { "$12", 12 + GP_REG_FIRST }, \
3312 { "$13", 13 + GP_REG_FIRST }, \
3313 { "$14", 14 + GP_REG_FIRST }, \
3314 { "$15", 15 + GP_REG_FIRST }, \
3315 { "$16", 16 + GP_REG_FIRST }, \
3316 { "$17", 17 + GP_REG_FIRST }, \
3317 { "$18", 18 + GP_REG_FIRST }, \
3318 { "$19", 19 + GP_REG_FIRST }, \
3319 { "$20", 20 + GP_REG_FIRST }, \
3320 { "$21", 21 + GP_REG_FIRST }, \
3321 { "$22", 22 + GP_REG_FIRST }, \
3322 { "$23", 23 + GP_REG_FIRST }, \
3323 { "$24", 24 + GP_REG_FIRST }, \
3324 { "$25", 25 + GP_REG_FIRST }, \
3325 { "$26", 26 + GP_REG_FIRST }, \
3326 { "$27", 27 + GP_REG_FIRST }, \
3327 { "$28", 28 + GP_REG_FIRST }, \
3328 { "$29", 29 + GP_REG_FIRST }, \
3329 { "$30", 30 + GP_REG_FIRST }, \
3330 { "$31", 31 + GP_REG_FIRST }, \
3331 { "$sp", 29 + GP_REG_FIRST }, \
3332 { "$fp", 30 + GP_REG_FIRST }, \
3333 { "at", 1 + GP_REG_FIRST }, \
3334 { "v0", 2 + GP_REG_FIRST }, \
3335 { "v1", 3 + GP_REG_FIRST }, \
3336 { "a0", 4 + GP_REG_FIRST }, \
3337 { "a1", 5 + GP_REG_FIRST }, \
3338 { "a2", 6 + GP_REG_FIRST }, \
3339 { "a3", 7 + GP_REG_FIRST }, \
3340 { "t0", 8 + GP_REG_FIRST }, \
3341 { "t1", 9 + GP_REG_FIRST }, \
3342 { "t2", 10 + GP_REG_FIRST }, \
3343 { "t3", 11 + GP_REG_FIRST }, \
3344 { "t4", 12 + GP_REG_FIRST }, \
3345 { "t5", 13 + GP_REG_FIRST }, \
3346 { "t6", 14 + GP_REG_FIRST }, \
3347 { "t7", 15 + GP_REG_FIRST }, \
3348 { "s0", 16 + GP_REG_FIRST }, \
3349 { "s1", 17 + GP_REG_FIRST }, \
3350 { "s2", 18 + GP_REG_FIRST }, \
3351 { "s3", 19 + GP_REG_FIRST }, \
3352 { "s4", 20 + GP_REG_FIRST }, \
3353 { "s5", 21 + GP_REG_FIRST }, \
3354 { "s6", 22 + GP_REG_FIRST }, \
3355 { "s7", 23 + GP_REG_FIRST }, \
3356 { "t8", 24 + GP_REG_FIRST }, \
3357 { "t9", 25 + GP_REG_FIRST }, \
3358 { "k0", 26 + GP_REG_FIRST }, \
3359 { "k1", 27 + GP_REG_FIRST }, \
3360 { "gp", 28 + GP_REG_FIRST }, \
3361 { "sp", 29 + GP_REG_FIRST }, \
3362 { "fp", 30 + GP_REG_FIRST }, \
3363 { "ra", 31 + GP_REG_FIRST }, \
3364 { "$sp", 29 + GP_REG_FIRST }, \
3365 { "$fp", 30 + GP_REG_FIRST } \
3366 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3369 /* This is meant to be redefined in the host dependent files. It is a
3370 set of alternative names and regnums for mips coprocessors. */
3372 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3374 /* A C compound statement to output to stdio stream STREAM the
3375 assembler syntax for an instruction operand X. X is an RTL
3378 CODE is a value that can be used to specify one of several ways
3379 of printing the operand. It is used when identical operands
3380 must be printed differently depending on the context. CODE
3381 comes from the `%' specification that was used to request
3382 printing of the operand. If the specification was just `%DIGIT'
3383 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3384 is the ASCII code for LTR.
3386 If X is a register, this macro should print the register's name.
3387 The names can be found in an array `reg_names' whose type is
3388 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3390 When the machine description has a specification `%PUNCT' (a `%'
3391 followed by a punctuation character), this macro is called with
3392 a null pointer for X and the punctuation character for CODE.
3394 See mips.c for the MIPS specific codes. */
3396 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3398 /* A C expression which evaluates to true if CODE is a valid
3399 punctuation character for use in the `PRINT_OPERAND' macro. If
3400 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3401 punctuation characters (except for the standard one, `%') are
3402 used in this way. */
3404 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3406 /* A C compound statement to output to stdio stream STREAM the
3407 assembler syntax for an instruction operand that is a memory
3408 reference whose address is ADDR. ADDR is an RTL expression. */
3410 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3413 /* A C statement, to be executed after all slot-filler instructions
3414 have been output. If necessary, call `dbr_sequence_length' to
3415 determine the number of slots filled in a sequence (zero if not
3416 currently outputting a sequence), to decide how many no-ops to
3417 output, or whatever.
3419 Don't define this macro if it has nothing to do, but it is
3420 helpful in reading assembly output if the extent of the delay
3421 sequence is made explicit (e.g. with white space).
3423 Note that output routines for instructions with delay slots must
3424 be prepared to deal with not being output as part of a sequence
3425 (i.e. when the scheduling pass is not run, or when no slot
3426 fillers could be found.) The variable `final_sequence' is null
3427 when not processing a sequence, otherwise it contains the
3428 `sequence' rtx being output. */
3430 #define DBR_OUTPUT_SEQEND(STREAM) \
3433 if (set_nomacro > 0 && --set_nomacro == 0) \
3434 fputs ("\t.set\tmacro\n", STREAM); \
3436 if (set_noreorder > 0 && --set_noreorder == 0) \
3437 fputs ("\t.set\treorder\n", STREAM); \
3439 fputs ("\n", STREAM); \
3444 /* How to tell the debugger about changes of source files. */
3446 #ifndef SET_FILE_NUMBER
3447 #define SET_FILE_NUMBER() ++num_source_filenames
3450 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3451 mips_output_filename (STREAM, NAME)
3453 /* This is defined so that it can be overridden in iris6.h. */
3454 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3457 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3458 output_quoted_string (STREAM, NAME); \
3459 fputs ("\n", STREAM); \
3463 /* This is how to output a note the debugger telling it the line number
3464 to which the following sequence of instructions corresponds.
3465 Silicon graphics puts a label after each .loc. */
3467 #ifndef LABEL_AFTER_LOC
3468 #define LABEL_AFTER_LOC(STREAM)
3471 #ifndef ASM_OUTPUT_SOURCE_LINE
3472 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3473 mips_output_lineno (STREAM, LINE)
3476 /* The MIPS implementation uses some labels for its own purpose. The
3477 following lists what labels are created, and are all formed by the
3478 pattern $L[a-z].*. The machine independent portion of GCC creates
3479 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3481 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3482 $Lb[0-9]+ Begin blocks for MIPS debug support
3483 $Lc[0-9]+ Label for use in s<xx> operation.
3484 $Le[0-9]+ End blocks for MIPS debug support */
3486 #undef ASM_DECLARE_OBJECT_NAME
3487 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3488 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3490 /* Globalizing directive for a label. */
3491 #define GLOBAL_ASM_OP "\t.globl\t"
3493 /* This says how to define a global common symbol. */
3495 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3497 /* If the target wants uninitialized const declarations in \
3498 .rdata then don't put them in .comm */ \
3499 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3500 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3501 && (DECL_INITIAL (DECL) == 0 \
3502 || DECL_INITIAL (DECL) == error_mark_node)) \
3504 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3505 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3507 readonly_data_section (); \
3508 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3509 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3513 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3518 /* This says how to define a local common symbol (ie, not visible to
3521 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3522 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3525 /* This says how to output an external. It would be possible not to
3526 output anything and let undefined symbol become external. However
3527 the assembler uses length information on externals to allocate in
3528 data/sdata bss/sbss, thereby saving exec time. */
3530 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3531 mips_output_external(STREAM,DECL,NAME)
3534 /* This is how to declare a function name. The actual work of
3535 emitting the label is moved to function_prologue, so that we can
3536 get the line number correctly emitted before the .ent directive,
3537 and after any .file directives. Define as empty so that the function
3538 is not declared before the .ent directive elsewhere. */
3540 #undef ASM_DECLARE_FUNCTION_NAME
3541 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3543 /* This is how to store into the string LABEL
3544 the symbol_ref name of an internal numbered label where
3545 PREFIX is the class of label and NUM is the number within the class.
3546 This is suitable for output with `assemble_name'. */
3548 #undef ASM_GENERATE_INTERNAL_LABEL
3549 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3550 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3552 /* This is how to output an element of a case-vector that is absolute. */
3554 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3555 fprintf (STREAM, "\t%s\t%sL%d\n", \
3556 ptr_mode == DImode ? ".dword" : ".word", \
3557 LOCAL_LABEL_PREFIX, \
3560 /* This is how to output an element of a case-vector that is relative.
3561 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3562 TARGET_EMBEDDED_PIC). */
3564 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3566 if (TARGET_MIPS16) \
3567 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3568 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3569 else if (TARGET_EMBEDDED_PIC) \
3570 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3571 ptr_mode == DImode ? ".dword" : ".word", \
3572 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3573 else if (TARGET_GPWORD) \
3574 fprintf (STREAM, "\t%s\t%sL%d\n", \
3575 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3576 LOCAL_LABEL_PREFIX, VALUE); \
3578 fprintf (STREAM, "\t%s\t%sL%d\n", \
3579 ptr_mode == DImode ? ".dword" : ".word", \
3580 LOCAL_LABEL_PREFIX, VALUE); \
3583 /* When generating embedded PIC or mips16 code we want to put the jump
3584 table in the .text section. In all other cases, we want to put the
3585 jump table in the .rdata section. Unfortunately, we can't use
3586 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3587 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3588 section if appropriate. */
3589 #undef ASM_OUTPUT_CASE_LABEL
3590 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3592 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3593 function_section (current_function_decl); \
3594 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3597 /* This is how to output an assembler line
3598 that says to advance the location counter
3599 to a multiple of 2**LOG bytes. */
3601 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3602 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3604 /* This is how to output an assembler line to advance the location
3605 counter by SIZE bytes. */
3607 #undef ASM_OUTPUT_SKIP
3608 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3609 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3611 /* This is how to output a string. */
3612 #undef ASM_OUTPUT_ASCII
3613 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3614 mips_output_ascii (STREAM, STRING, LEN)
3616 /* Output #ident as a in the read-only data section. */
3617 #undef ASM_OUTPUT_IDENT
3618 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3620 const char *p = STRING; \
3621 int size = strlen (p) + 1; \
3622 readonly_data_section (); \
3623 assemble_string (p, size); \
3626 /* Default to -G 8 */
3627 #ifndef MIPS_DEFAULT_GVALUE
3628 #define MIPS_DEFAULT_GVALUE 8
3631 /* Define the strings to put out for each section in the object file. */
3632 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3633 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3634 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3636 #undef READONLY_DATA_SECTION_ASM_OP
3637 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3639 /* Given a decl node or constant node, choose the section to output it in
3640 and select that section. */
3642 #undef TARGET_ASM_SELECT_SECTION
3643 #define TARGET_ASM_SELECT_SECTION mips_select_section
3645 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3648 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3649 TARGET_64BIT ? "dsubu" : "subu", \
3650 reg_names[STACK_POINTER_REGNUM], \
3651 reg_names[STACK_POINTER_REGNUM], \
3652 TARGET_64BIT ? "sd" : "sw", \
3654 reg_names[STACK_POINTER_REGNUM]); \
3658 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3661 if (! set_noreorder) \
3662 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3664 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3665 TARGET_64BIT ? "ld" : "lw", \
3667 reg_names[STACK_POINTER_REGNUM], \
3668 TARGET_64BIT ? "daddu" : "addu", \
3669 reg_names[STACK_POINTER_REGNUM], \
3670 reg_names[STACK_POINTER_REGNUM]); \
3672 if (! set_noreorder) \
3673 fprintf (STREAM, "\t.set\treorder\n"); \
3677 /* How to start an assembler comment.
3678 The leading space is important (the mips native assembler requires it). */
3679 #ifndef ASM_COMMENT_START
3680 #define ASM_COMMENT_START " #"
3683 /* Default definitions for size_t and ptrdiff_t. We must override the
3684 definitions from ../svr4.h on mips-*-linux-gnu. */
3687 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3690 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3692 /* See mips_expand_prologue's use of loadgp for when this should be
3695 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3696 && mips_abi != ABI_32 \
3697 && mips_abi != ABI_O64)
3699 /* We need to use a special set of functions to handle hard floating
3700 point code in mips16 mode. */
3702 #ifndef INIT_SUBTARGET_OPTABS
3703 #define INIT_SUBTARGET_OPTABS
3706 #define INIT_TARGET_OPTABS \
3709 if (! TARGET_MIPS16 || ! mips16_hard_float) \
3710 INIT_SUBTARGET_OPTABS; \
3713 add_optab->handlers[(int) SFmode].libfunc = \
3714 init_one_libfunc ("__mips16_addsf3"); \
3715 sub_optab->handlers[(int) SFmode].libfunc = \
3716 init_one_libfunc ("__mips16_subsf3"); \
3717 smul_optab->handlers[(int) SFmode].libfunc = \
3718 init_one_libfunc ("__mips16_mulsf3"); \
3719 sdiv_optab->handlers[(int) SFmode].libfunc = \
3720 init_one_libfunc ("__mips16_divsf3"); \
3722 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
3723 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
3724 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
3725 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
3726 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
3727 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
3729 floatsisf_libfunc = \
3730 init_one_libfunc ("__mips16_floatsisf"); \
3732 init_one_libfunc ("__mips16_fixsfsi"); \
3734 if (TARGET_DOUBLE_FLOAT) \
3736 add_optab->handlers[(int) DFmode].libfunc = \
3737 init_one_libfunc ("__mips16_adddf3"); \
3738 sub_optab->handlers[(int) DFmode].libfunc = \
3739 init_one_libfunc ("__mips16_subdf3"); \
3740 smul_optab->handlers[(int) DFmode].libfunc = \
3741 init_one_libfunc ("__mips16_muldf3"); \
3742 sdiv_optab->handlers[(int) DFmode].libfunc = \
3743 init_one_libfunc ("__mips16_divdf3"); \
3745 extendsfdf2_libfunc = \
3746 init_one_libfunc ("__mips16_extendsfdf2"); \
3747 truncdfsf2_libfunc = \
3748 init_one_libfunc ("__mips16_truncdfsf2"); \
3751 init_one_libfunc ("__mips16_eqdf2"); \
3753 init_one_libfunc ("__mips16_nedf2"); \
3755 init_one_libfunc ("__mips16_gtdf2"); \
3757 init_one_libfunc ("__mips16_gedf2"); \
3759 init_one_libfunc ("__mips16_ltdf2"); \
3761 init_one_libfunc ("__mips16_ledf2"); \
3763 floatsidf_libfunc = \
3764 init_one_libfunc ("__mips16_floatsidf"); \
3766 init_one_libfunc ("__mips16_fixdfsi"); \
3772 #define DFMODE_NAN \
3773 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
3774 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
3775 #define SFMODE_NAN \
3776 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
3777 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
3779 /* Generate calls to memcpy, etc., not bcopy, etc. */
3780 #define TARGET_MEM_FUNCTIONS
3783 /* Since the bits of the _init and _fini function is spread across
3784 many object files, each potentially with its own GP, we must assume
3785 we need to load our GP. We don't preserve $gp or $ra, since each
3786 init/fini chunk is supposed to initialize $gp, and crti/crtn
3787 already take care of preserving $ra and, when appropriate, $gp. */
3788 #if _MIPS_SIM == _MIPS_SIM_ABI32
3789 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3790 asm (SECTION_OP "\n\
3796 jal " USER_LABEL_PREFIX #FUNC "\n\
3797 " TEXT_SECTION_ASM_OP);
3798 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3799 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3800 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3801 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3802 asm (SECTION_OP "\n\
3807 .cpsetup $31, $2, 1b\n\
3808 jal " USER_LABEL_PREFIX #FUNC "\n\
3809 " TEXT_SECTION_ASM_OP);
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