1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int may_call_alloca;
31 extern char **save_argv;
32 extern int target_flags;
33 extern char *version_string;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
137 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
138 extern int mips_isa; /* architectural level */
139 extern int mips16; /* whether generating mips16 code */
140 extern int mips16_hard_float; /* mips16 without -msoft-float */
141 extern int mips_entry; /* generate entry/exit for mips16 */
142 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
143 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
144 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
145 extern const char *mips_entry_string; /* for -mentry */
146 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
147 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
148 extern int mips_split_addresses; /* perform high/lo_sum support */
149 extern int dslots_load_total; /* total # load related delay slots */
150 extern int dslots_load_filled; /* # filled load delay slots */
151 extern int dslots_jump_total; /* total # jump related delay slots */
152 extern int dslots_jump_filled; /* # filled jump delay slots */
153 extern int dslots_number_nops; /* # of nops needed by previous insn */
154 extern int num_refs[3]; /* # 1/2/3 word references */
155 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
156 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
157 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
158 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
159 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
160 extern int mips_string_length; /* length of strings for mips16 */
161 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
163 /* Functions to change what output section we are using. */
164 extern void rdata_section PARAMS ((void));
165 extern void sdata_section PARAMS ((void));
167 /* Stubs for half-pic support if not OSF/1 reference platform. */
170 #define HALF_PIC_P() 0
171 #define HALF_PIC_NUMBER_PTRS 0
172 #define HALF_PIC_NUMBER_REFS 0
173 #define HALF_PIC_ENCODE(DECL)
174 #define HALF_PIC_DECLARE(NAME)
175 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
176 #define HALF_PIC_ADDRESS_P(X) 0
177 #define HALF_PIC_PTR(X) X
178 #define HALF_PIC_FINISH(STREAM)
182 /* Run-time compilation parameters selecting different hardware subsets. */
184 /* Macros used in the machine description to test the flags. */
186 /* Bits for real switches */
187 #define MASK_INT64 0x00000001 /* ints are 64 bits */
188 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
189 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
190 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
191 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
192 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
193 #define MASK_STATS 0x00000040 /* print statistics to stderr */
194 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
195 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
196 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
197 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
198 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
199 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
200 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
201 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
202 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
203 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
204 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
205 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
206 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
207 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
208 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
209 #define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
210 #define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
212 /* Dummy switches used only in spec's*/
213 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
215 /* Debug switches, not documented */
216 #define MASK_DEBUG 0 /* Eliminate version # in .s file */
217 #define MASK_DEBUG_A 0x40000000 /* don't allow <label>($reg) addrs */
218 #define MASK_DEBUG_B 0x20000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
219 #define MASK_DEBUG_C 0x10000000 /* don't expand seq, etc. */
220 #define MASK_DEBUG_D 0 /* don't do define_split's */
221 #define MASK_DEBUG_E 0 /* function_arg debug */
222 #define MASK_DEBUG_F 0
223 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
224 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
225 #define MASK_DEBUG_I 0 /* unused */
227 /* r4000 64 bit sizes */
228 #define TARGET_INT64 (target_flags & MASK_INT64)
229 #define TARGET_LONG64 (target_flags & MASK_LONG64)
230 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
231 #define TARGET_64BIT (target_flags & MASK_64BIT)
233 /* Mips vs. GNU linker */
234 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
236 /* generate mips 3900 insns */
237 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
239 /* Mips vs. GNU assembler */
240 #define TARGET_GAS (target_flags & MASK_GAS)
241 #define TARGET_UNIX_ASM (!TARGET_GAS)
242 #define TARGET_MIPS_AS TARGET_UNIX_ASM
245 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
246 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
247 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
248 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
249 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
250 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
251 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
252 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
253 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
254 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
256 /* Reg. Naming in .s ($21 vs. $a0) */
257 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
259 /* Optimize for Sdata/Sbss */
260 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
262 /* print program statistics */
263 #define TARGET_STATS (target_flags & MASK_STATS)
265 /* call memcpy instead of inline code */
266 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
268 /* .abicalls, etc from Pyramid V.4 */
269 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
271 /* OSF pic references to externs */
272 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
274 /* software floating point */
275 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
276 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
278 /* always call through a register */
279 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
281 /* generate embedded PIC code;
283 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
285 /* for embedded systems, optimize for
286 reduced RAM space instead of for
288 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
290 /* generate big endian code. */
291 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
293 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
294 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
296 #define TARGET_MAD (target_flags & MASK_MAD)
298 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
300 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
301 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
303 /* This is true if we must enable the assembly language file switching
306 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
308 /* We must disable the function end stabs when doing the file switching trick,
309 because the Lscope stabs end up in the wrong place, making it impossible
310 to debug the resulting code. */
311 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
313 /* Generate mips16 code */
314 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
316 /* Macro to define tables used to set the flags.
317 This is a list in braces of pairs in braces,
318 each pair being { "NAME", VALUE }
319 where VALUE is the bits to set or minus the bits to clear.
320 An empty string NAME is used to identify the default VALUE. */
322 #define TARGET_SWITCHES \
324 {"int64", MASK_INT64 | MASK_LONG64, \
325 "Use 64-bit int type"}, \
326 {"long64", MASK_LONG64, \
327 "Use 64-bit long type"}, \
328 {"long32", -(MASK_LONG64 | MASK_INT64), \
329 "Use 32-bit long type"}, \
330 {"split-addresses", MASK_SPLIT_ADDR, \
331 "Optimize lui/addiu address loads"}, \
332 {"no-split-addresses", -MASK_SPLIT_ADDR, \
333 "Don't optimize lui/addiu address loads"}, \
334 {"mips-as", -MASK_GAS, \
338 {"rnames", MASK_NAME_REGS, \
339 "Use symbolic register names"}, \
340 {"no-rnames", -MASK_NAME_REGS, \
341 "Don't use symbolic register names"}, \
342 {"gpOPT", MASK_GPOPT, \
343 "Use GP relative sdata/sbss sections"}, \
344 {"gpopt", MASK_GPOPT, \
345 "Use GP relative sdata/sbss sections"}, \
346 {"no-gpOPT", -MASK_GPOPT, \
347 "Don't use GP relative sdata/sbss sections"}, \
348 {"no-gpopt", -MASK_GPOPT, \
349 "Don't use GP relative sdata/sbss sections"}, \
350 {"stats", MASK_STATS, \
351 "Output compiler statistics"}, \
352 {"no-stats", -MASK_STATS, \
353 "Don't output compiler statistics"}, \
354 {"memcpy", MASK_MEMCPY, \
355 "Don't optimize block moves"}, \
356 {"no-memcpy", -MASK_MEMCPY, \
357 "Optimize block moves"}, \
358 {"mips-tfile", MASK_MIPS_TFILE, \
359 "Use mips-tfile asm postpass"}, \
360 {"no-mips-tfile", -MASK_MIPS_TFILE, \
361 "Don't use mips-tfile asm postpass"}, \
362 {"soft-float", MASK_SOFT_FLOAT, \
363 "Use software floating point"}, \
364 {"hard-float", -MASK_SOFT_FLOAT, \
365 "Use hardware floating point"}, \
366 {"fp64", MASK_FLOAT64, \
367 "Use 64-bit FP registers"}, \
368 {"fp32", -MASK_FLOAT64, \
369 "Use 32-bit FP registers"}, \
370 {"gp64", MASK_64BIT, \
371 "Use 64-bit general registers"}, \
372 {"gp32", -MASK_64BIT, \
373 "Use 32-bit general registers"}, \
374 {"abicalls", MASK_ABICALLS, \
376 {"no-abicalls", -MASK_ABICALLS, \
377 "Don't use Irix PIC"}, \
378 {"half-pic", MASK_HALF_PIC, \
380 {"no-half-pic", -MASK_HALF_PIC, \
381 "Don't use OSF PIC"}, \
382 {"long-calls", MASK_LONG_CALLS, \
383 "Use indirect calls"}, \
384 {"no-long-calls", -MASK_LONG_CALLS, \
385 "Don't use indirect calls"}, \
386 {"embedded-pic", MASK_EMBEDDED_PIC, \
387 "Use embedded PIC"}, \
388 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
389 "Don't use embedded PIC"}, \
390 {"embedded-data", MASK_EMBEDDED_DATA, \
391 "Use ROM instead of RAM"}, \
392 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
393 "Don't use ROM instead of RAM"}, \
394 {"eb", MASK_BIG_ENDIAN, \
395 "Use big-endian byte order"}, \
396 {"el", -MASK_BIG_ENDIAN, \
397 "Use little-endian byte order"}, \
398 {"single-float", MASK_SINGLE_FLOAT, \
399 "Use single (32-bit) FP only"}, \
400 {"double-float", -MASK_SINGLE_FLOAT, \
401 "Don't use single (32-bit) FP only"}, \
403 "Use multiply accumulate"}, \
404 {"no-mad", -MASK_MAD, \
405 "Don't use multiply accumulate"}, \
406 {"fix4300", MASK_4300_MUL_FIX, \
407 "Work around early 4300 hardware bug"}, \
408 {"no-fix4300", -MASK_4300_MUL_FIX, \
409 "Don't work around early 4300 hardware bug"}, \
410 {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
411 "Optimize for 4650"}, \
412 {"3900", MASK_MIPS3900, \
413 "Optimize for 3900"}, \
414 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
415 "Trap on integer divide by zero"}, \
416 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
417 "Don't trap on integer divide by zero"}, \
418 {"check-range-division",MASK_CHECK_RANGE_DIV, \
419 "Trap on integer divide overflow"}, \
420 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
421 "Don't trap on integer divide overflow"}, \
422 {"debug", MASK_DEBUG, \
424 {"debuga", MASK_DEBUG_A, \
426 {"debugb", MASK_DEBUG_B, \
428 {"debugc", MASK_DEBUG_C, \
430 {"debugd", MASK_DEBUG_D, \
432 {"debuge", MASK_DEBUG_E, \
434 {"debugf", MASK_DEBUG_F, \
436 {"debugg", MASK_DEBUG_G, \
438 {"debugh", MASK_DEBUG_H, \
440 {"debugi", MASK_DEBUG_I, \
442 {"", (TARGET_DEFAULT \
443 | TARGET_CPU_DEFAULT \
444 | TARGET_ENDIAN_DEFAULT), \
448 /* Default target_flags if no switches are specified */
450 #ifndef TARGET_DEFAULT
451 #define TARGET_DEFAULT 0
454 #ifndef TARGET_CPU_DEFAULT
455 #define TARGET_CPU_DEFAULT 0
458 #ifndef TARGET_ENDIAN_DEFAULT
460 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
462 #define TARGET_ENDIAN_DEFAULT 0
466 #ifndef MULTILIB_ENDIAN_DEFAULT
467 #if TARGET_ENDIAN_DEFAULT == 0
468 #define MULTILIB_ENDIAN_DEFAULT "EL"
470 #define MULTILIB_ENDIAN_DEFAULT "EB"
474 #ifndef MULTILIB_DEFAULTS
475 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, "mips1" }
478 /* We must pass -EL to the linker by default for little endian embedded
479 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
480 linker will default to using big-endian output files. The OUTPUT_FORMAT
481 line must be in the linker script, otherwise -EB/-EL will not work. */
483 #ifndef LINKER_ENDIAN_SPEC
484 #if TARGET_ENDIAN_DEFAULT == 0
485 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
487 #define LINKER_ENDIAN_SPEC ""
491 /* This macro is similar to `TARGET_SWITCHES' but defines names of
492 command options that have values. Its definition is an
493 initializer with a subgrouping for each command option.
495 Each subgrouping contains a string constant, that defines the
496 fixed part of the option name, and the address of a variable.
497 The variable, type `char *', is set to the variable part of the
498 given option if the fixed part matches. The actual option name
499 is made by appending `-m' to the specified name.
501 Here is an example which defines `-mshort-data-NUMBER'. If the
502 given option is `-mshort-data-512', the variable `m88k_short_data'
503 will be set to the string `"512"'.
505 extern char *m88k_short_data;
506 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
508 #define TARGET_OPTIONS \
510 SUBTARGET_TARGET_OPTIONS \
511 { "cpu=", &mips_cpu_string, \
512 "Specify CPU for scheduling purposes"}, \
513 { "ips", &mips_isa_string, \
514 "Specify MIPS ISA"}, \
515 { "entry", &mips_entry_string, \
516 "Use mips16 entry/exit psuedo ops"}, \
517 { "no-mips16", &mips_no_mips16_string, \
518 "Don't use MIPS16 instructions"}, \
519 { "explicit-type-size", &mips_explicit_type_size_string, \
523 /* This is meant to be redefined in the host dependent files. */
524 #define SUBTARGET_TARGET_OPTIONS
526 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
528 /* Generate three-operand multiply instructions for both SImode and DImode. */
529 #define GENERATE_MULT3 (TARGET_MIPS3900 \
532 /* Macros to decide whether certain features are available or not,
533 depending on the instruction set architecture level. */
535 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
536 #define HAVE_SQRT_P() (mips_isa >= 2)
538 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
539 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
540 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
541 target_flags, and -mgp64 sets MASK_64BIT.
543 Setting MASK_64BIT in target_flags will cause gcc to assume that
544 registers are 64 bits wide. int, long and void * will be 32 bit;
545 this may be changed with -mint64 or -mlong64.
547 The gen* programs link code that refers to MASK_64BIT. They don't
548 actually use the information in target_flags; they just refer to
551 /* Switch Recognition by gcc.c. Add -G xx support */
553 #ifdef SWITCH_TAKES_ARG
554 #undef SWITCH_TAKES_ARG
557 #define SWITCH_TAKES_ARG(CHAR) \
558 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
560 /* Sometimes certain combinations of command options do not make sense
561 on a particular target machine. You can define a macro
562 `OVERRIDE_OPTIONS' to take account of this. This macro, if
563 defined, is executed once just after all the command options have
566 On the MIPS, it is used to handle -G. We also use it to set up all
567 of the tables referenced in the other macros. */
569 #define OVERRIDE_OPTIONS override_options ()
571 /* Zero or more C statements that may conditionally modify two
572 variables `fixed_regs' and `call_used_regs' (both of type `char
573 []') after they have been initialized from the two preceding
576 This is necessary in case the fixed or call-clobbered registers
577 depend on target flags.
579 You need not define this macro if it has no work to do.
581 If the usage of an entire class of registers depends on the target
582 flags, you may indicate this to GCC by using this macro to modify
583 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
584 the classes which should not be used by GCC. Also define the macro
585 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
586 letter for a class that shouldn't be used.
588 (However, if this class is not included in `GENERAL_REGS' and all
589 of the insn patterns whose constraints permit this class are
590 controlled by target switches, then GCC will automatically avoid
591 using these registers when the target switches are opposed to
594 #define CONDITIONAL_REGISTER_USAGE \
597 if (!TARGET_HARD_FLOAT) \
601 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
602 fixed_regs[regno] = call_used_regs[regno] = 1; \
603 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
604 fixed_regs[regno] = call_used_regs[regno] = 1; \
606 else if (mips_isa < 4) \
610 /* We only have a single condition code register. We \
611 implement this by hiding all the condition code registers, \
612 and generating RTL that refers directly to ST_REG_FIRST. */ \
613 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
614 fixed_regs[regno] = call_used_regs[regno] = 1; \
616 /* In mips16 mode, we permit the $t temporary registers to be used \
617 for reload. We prohibit the unused $s registers, since they \
618 are caller saved, and saving them via a mips16 register would \
619 probably waste more time than just reloading the value. */ \
622 fixed_regs[18] = call_used_regs[18] = 1; \
623 fixed_regs[19] = call_used_regs[19] = 1; \
624 fixed_regs[20] = call_used_regs[20] = 1; \
625 fixed_regs[21] = call_used_regs[21] = 1; \
626 fixed_regs[22] = call_used_regs[22] = 1; \
627 fixed_regs[23] = call_used_regs[23] = 1; \
628 fixed_regs[26] = call_used_regs[26] = 1; \
629 fixed_regs[27] = call_used_regs[27] = 1; \
630 fixed_regs[30] = call_used_regs[30] = 1; \
632 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
636 /* This is meant to be redefined in the host dependent files. */
637 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
639 /* Show we can debug even without a frame pointer. */
640 #define CAN_DEBUG_WITHOUT_FP
642 /* Complain about missing specs and predefines that should be defined in each
643 of the target tm files to override the defaults. This is mostly a place-
644 holder until I can get each of the files updated [mm]. */
646 #if defined(OSF_OS) \
647 || defined(DECSTATION) \
648 || defined(SGI_TARGET) \
649 || defined(MIPS_NEWS) \
650 || defined(MIPS_SYSV) \
651 || defined(MIPS_SVR4) \
652 || defined(MIPS_BSD43)
654 #ifndef CPP_PREDEFINES
655 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
659 #error "Define LIB_SPEC in the appropriate tm.h file"
662 #ifndef STARTFILE_SPEC
663 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
667 #error "Define MACHINE_TYPE in the appropriate tm.h file"
671 /* Tell collect what flags to pass to nm. */
673 #define NM_FLAGS "-Bn"
677 /* Names to predefine in the preprocessor for this target machine. */
679 #ifndef CPP_PREDEFINES
680 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
681 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
682 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
685 /* Assembler specs. */
687 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
690 #define MIPS_AS_ASM_SPEC "\
691 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
692 %{pipe: %e-pipe is not supported.} \
693 %{K} %(subtarget_mips_as_asm_spec)"
695 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
696 rather than gas. It may be overridden by subtargets. */
698 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
699 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
702 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
705 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
707 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
708 GAS_ASM_SPEC as the default, depending upon the value of
711 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
714 #define TARGET_ASM_SPEC "\
715 %{mmips-as: %(mips_as_asm_spec)} \
716 %{!mmips-as: %(gas_asm_spec)}"
720 #define TARGET_ASM_SPEC "\
721 %{!mgas: %(mips_as_asm_spec)} \
722 %{mgas: %(gas_asm_spec)}"
726 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
727 to the assembler. It may be overridden by subtargets. */
728 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
729 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
731 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
734 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
735 the assembler. It may be overridden by subtargets. */
736 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
737 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
738 %{g} %{g0} %{g1} %{g2} %{g3} \
739 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
740 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
741 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
742 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
745 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
746 overridden by subtargets. */
748 #ifndef SUBTARGET_ASM_SPEC
749 #define SUBTARGET_ASM_SPEC ""
752 /* ASM_SPEC is the set of arguments to pass to the assembler. */
755 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
756 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
757 %(subtarget_asm_optimizing_spec) \
758 %(subtarget_asm_debugging_spec) \
760 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
762 %(subtarget_asm_spec)"
764 /* Specify to run a post-processor, mips-tfile after the assembler
765 has run to stuff the mips debug information into the object file.
766 This is needed because the $#!%^ MIPS assembler provides no way
767 of specifying such information in the assembly file. If we are
768 cross compiling, disable mips-tfile unless the user specifies
771 #ifndef ASM_FINAL_SPEC
772 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
774 #define ASM_FINAL_SPEC "\
775 %{mmips-as: %{!mno-mips-tfile: \
776 \n mips-tfile %{v*: -v} \
778 %{!K: %{save-temps: -I %b.o~}} \
779 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
780 %{.s:%i} %{!.s:%g.s}}}"
784 #define ASM_FINAL_SPEC "\
785 %{!mgas: %{!mno-mips-tfile: \
786 \n mips-tfile %{v*: -v} \
788 %{!K: %{save-temps: -I %b.o~}} \
789 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
790 %{.s:%i} %{!.s:%g.s}}}"
793 #endif /* ASM_FINAL_SPEC */
795 /* Redefinition of libraries used. Mips doesn't support normal
796 UNIX style profiling via calling _mcount. It does offer
797 profiling that samples the PC, so do what we can... */
800 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
803 /* Extra switches sometimes passed to the linker. */
804 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
805 will interpret it as a -b option. */
809 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
810 %{bestGnum} %{shared} %{non_shared} \
811 %(linker_endian_spec)"
812 #endif /* LINK_SPEC defined */
814 /* Specs for the compiler proper */
816 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
817 overridden by subtargets. */
818 #ifndef SUBTARGET_CC1_SPEC
819 #define SUBTARGET_CC1_SPEC ""
822 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
826 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
827 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
828 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
829 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
830 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
831 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
832 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
833 %{m4650:-mcpu=r4650} \
834 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
835 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
836 %{pic-none: -mno-half-pic} \
837 %{pic-lib: -mhalf-pic} \
838 %{pic-extern: -mhalf-pic} \
839 %{pic-calls: -mhalf-pic} \
841 %(subtarget_cc1_spec) "
844 /* Preprocessor specs. */
846 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
847 be overridden by subtargets. */
849 #ifndef SUBTARGET_CPP_SIZE_SPEC
850 #define SUBTARGET_CPP_SIZE_SPEC "\
851 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
852 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
855 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
856 overridden by subtargets. */
857 #ifndef SUBTARGET_CPP_SPEC
858 #define SUBTARGET_CPP_SPEC ""
861 /* If we're using 64bit longs, then we have to define __LONG_MAX__
862 correctly. Similarly for 64bit ints and __INT_MAX__. */
863 #ifndef LONG_MAX_SPEC
864 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
865 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
867 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
871 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
875 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
876 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
877 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
878 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
879 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
880 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
881 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
882 %(subtarget_cpp_size_spec) \
883 %{mips3:-U__mips -D__mips=3 -D__mips64} \
884 %{mips4:-U__mips -D__mips=4 -D__mips64} \
885 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
886 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
887 %{m4650:%{!msoft-float:-D__mips_single_float}} \
888 %{msoft-float:-D__mips_soft_float} \
889 %{mabi=eabi:-D__mips_eabi} \
890 %{mips16:%{!mno-mips16:-D__mips16}} \
891 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
892 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
894 %(subtarget_cpp_spec) "
897 /* This macro defines names of additional specifications to put in the specs
898 that can be used in various specifications like CC1_SPEC. Its definition
899 is an initializer with a subgrouping for each command option.
901 Each subgrouping contains a string constant, that defines the
902 specification name, and a string constant that used by the GNU CC driver
905 Do not define this macro if it does not need to do anything. */
907 #define EXTRA_SPECS \
908 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
909 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
910 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
911 { "long_max_spec", LONG_MAX_SPEC }, \
912 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
913 { "gas_asm_spec", GAS_ASM_SPEC }, \
914 { "target_asm_spec", TARGET_ASM_SPEC }, \
915 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
916 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
917 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
918 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
919 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
920 SUBTARGET_EXTRA_SPECS
922 #ifndef SUBTARGET_EXTRA_SPECS
923 #define SUBTARGET_EXTRA_SPECS
926 /* If defined, this macro is an additional prefix to try after
927 `STANDARD_EXEC_PREFIX'. */
929 #ifndef MD_EXEC_PREFIX
930 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
933 #ifndef MD_STARTFILE_PREFIX
934 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
938 /* Print subsidiary information on the compiler version in use. */
940 #define MIPS_VERSION "[AL 1.1, MM 40]"
943 #define MACHINE_TYPE "BSD Mips"
946 #ifndef TARGET_VERSION_INTERNAL
947 #define TARGET_VERSION_INTERNAL(STREAM) \
948 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
951 #ifndef TARGET_VERSION
952 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
956 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
957 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
958 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
960 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
961 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
964 /* By default, turn on GDB extensions. */
965 #define DEFAULT_GDB_EXTENSIONS 1
967 /* If we are passing smuggling stabs through the MIPS ECOFF object
968 format, put a comment in front of the .stab<x> operation so
969 that the MIPS assembler does not choke. The mips-tfile program
970 will correctly put the stab into the object file. */
972 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
973 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
974 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
976 /* Local compiler-generated symbols must have a prefix that the assembler
977 understands. By default, this is $, although some targets (e.g.,
978 NetBSD-ELF) need to override this. */
980 #ifndef LOCAL_LABEL_PREFIX
981 #define LOCAL_LABEL_PREFIX "$"
984 /* By default on the mips, external symbols do not have an underscore
985 prepended, but some targets (e.g., NetBSD) require this. */
987 #ifndef USER_LABEL_PREFIX
988 #define USER_LABEL_PREFIX ""
991 /* Forward references to tags are allowed. */
992 #define SDB_ALLOW_FORWARD_REFERENCES
994 /* Unknown tags are also allowed. */
995 #define SDB_ALLOW_UNKNOWN_REFERENCES
997 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
998 since the length can run past this up to a continuation point. */
999 #define DBX_CONTIN_LENGTH 1500
1001 /* How to renumber registers for dbx and gdb. */
1002 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1004 /* The mapping from gcc register number to DWARF 2 CFA column number.
1005 This mapping does not allow for tracking register 0, since SGI's broken
1006 dwarf reader thinks column 0 is used for the frame address, but since
1007 register 0 is fixed this is not a problem. */
1008 #define DWARF_FRAME_REGNUM(REG) \
1009 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1011 /* The DWARF 2 CFA column which tracks the return address. */
1012 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1014 /* Before the prologue, RA lives in r31. */
1015 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1017 /* Overrides for the COFF debug format. */
1018 #define PUT_SDB_SCL(a) \
1020 extern FILE *asm_out_text_file; \
1021 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1024 #define PUT_SDB_INT_VAL(a) \
1026 extern FILE *asm_out_text_file; \
1027 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1030 #define PUT_SDB_VAL(a) \
1032 extern FILE *asm_out_text_file; \
1033 fputs ("\t.val\t", asm_out_text_file); \
1034 output_addr_const (asm_out_text_file, (a)); \
1035 fputc (';', asm_out_text_file); \
1038 #define PUT_SDB_DEF(a) \
1040 extern FILE *asm_out_text_file; \
1041 fprintf (asm_out_text_file, "\t%s.def\t", \
1042 (TARGET_GAS) ? "" : "#"); \
1043 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1044 fputc (';', asm_out_text_file); \
1047 #define PUT_SDB_PLAIN_DEF(a) \
1049 extern FILE *asm_out_text_file; \
1050 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1051 (TARGET_GAS) ? "" : "#", (a)); \
1054 #define PUT_SDB_ENDEF \
1056 extern FILE *asm_out_text_file; \
1057 fprintf (asm_out_text_file, "\t.endef\n"); \
1060 #define PUT_SDB_TYPE(a) \
1062 extern FILE *asm_out_text_file; \
1063 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1066 #define PUT_SDB_SIZE(a) \
1068 extern FILE *asm_out_text_file; \
1069 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1072 #define PUT_SDB_DIM(a) \
1074 extern FILE *asm_out_text_file; \
1075 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1078 #ifndef PUT_SDB_START_DIM
1079 #define PUT_SDB_START_DIM \
1081 extern FILE *asm_out_text_file; \
1082 fprintf (asm_out_text_file, "\t.dim\t"); \
1086 #ifndef PUT_SDB_NEXT_DIM
1087 #define PUT_SDB_NEXT_DIM(a) \
1089 extern FILE *asm_out_text_file; \
1090 fprintf (asm_out_text_file, "%d,", a); \
1094 #ifndef PUT_SDB_LAST_DIM
1095 #define PUT_SDB_LAST_DIM(a) \
1097 extern FILE *asm_out_text_file; \
1098 fprintf (asm_out_text_file, "%d;", a); \
1102 #define PUT_SDB_TAG(a) \
1104 extern FILE *asm_out_text_file; \
1105 fprintf (asm_out_text_file, "\t.tag\t"); \
1106 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1107 fputc (';', asm_out_text_file); \
1110 /* For block start and end, we create labels, so that
1111 later we can figure out where the correct offset is.
1112 The normal .ent/.end serve well enough for functions,
1113 so those are just commented out. */
1115 #define PUT_SDB_BLOCK_START(LINE) \
1117 extern FILE *asm_out_text_file; \
1118 fprintf (asm_out_text_file, \
1119 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1120 LOCAL_LABEL_PREFIX, \
1122 (TARGET_GAS) ? "" : "#", \
1123 LOCAL_LABEL_PREFIX, \
1126 sdb_label_count++; \
1129 #define PUT_SDB_BLOCK_END(LINE) \
1131 extern FILE *asm_out_text_file; \
1132 fprintf (asm_out_text_file, \
1133 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1134 LOCAL_LABEL_PREFIX, \
1136 (TARGET_GAS) ? "" : "#", \
1137 LOCAL_LABEL_PREFIX, \
1140 sdb_label_count++; \
1143 #define PUT_SDB_FUNCTION_START(LINE)
1145 #define PUT_SDB_FUNCTION_END(LINE) \
1147 extern FILE *asm_out_text_file; \
1148 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1151 #define PUT_SDB_EPILOGUE_END(NAME)
1153 #define PUT_SDB_SRC_FILE(FILENAME) \
1155 extern FILE *asm_out_text_file; \
1156 output_file_directive (asm_out_text_file, (FILENAME)); \
1159 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1160 sprintf ((BUFFER), ".%dfake", (NUMBER));
1162 /* Correct the offset of automatic variables and arguments. Note that
1163 the MIPS debug format wants all automatic variables and arguments
1164 to be in terms of the virtual frame pointer (stack pointer before
1165 any adjustment in the function), while the MIPS 3.0 linker wants
1166 the frame pointer to be the stack pointer after the initial
1169 #define DEBUGGER_AUTO_OFFSET(X) \
1170 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1171 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1172 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1174 /* Tell collect that the object format is ECOFF */
1175 #ifndef OBJECT_FORMAT_ROSE
1176 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1177 #define EXTENDED_COFF /* ECOFF, not normal coff */
1180 #if 0 /* These definitions normally have no effect because
1181 MIPS systems define USE_COLLECT2, so
1182 assemble_constructor does nothing anyway. */
1184 /* Don't use the default definitions, because we don't have gld.
1185 Also, we don't want stabs when generating ECOFF output.
1186 Instead we depend on collect to handle these. */
1188 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1189 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1193 /* Target machine storage layout */
1195 /* Define in order to support both big and little endian float formats
1196 in the same gcc binary. */
1197 #define REAL_ARITHMETIC
1199 /* Define this if most significant bit is lowest numbered
1200 in instructions that operate on numbered bit-fields.
1202 #define BITS_BIG_ENDIAN 0
1204 /* Define this if most significant byte of a word is the lowest numbered. */
1205 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1207 /* Define this if most significant word of a multiword number is the lowest. */
1208 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1210 /* Define this to set the endianness to use in libgcc2.c, which can
1211 not depend on target_flags. */
1212 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1213 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1215 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1218 /* Number of bits in an addressable storage unit */
1219 #define BITS_PER_UNIT 8
1221 /* Width in bits of a "word", which is the contents of a machine register.
1222 Note that this is not necessarily the width of data type `int';
1223 if using 16-bit ints on a 68000, this would still be 32.
1224 But on a machine with 16-bit registers, this would be 16. */
1225 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1226 #define MAX_BITS_PER_WORD 64
1228 /* Width of a word, in units (bytes). */
1229 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1230 #define MIN_UNITS_PER_WORD 4
1232 /* For MIPS, width of a floating point register. */
1233 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1235 /* A C expression for the size in bits of the type `int' on the
1236 target machine. If you don't define this, the default is one
1238 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1239 #define MAX_INT_TYPE_SIZE 64
1241 /* Tell the preprocessor the maximum size of wchar_t. */
1242 #ifndef MAX_WCHAR_TYPE_SIZE
1243 #ifndef WCHAR_TYPE_SIZE
1244 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1248 /* A C expression for the size in bits of the type `short' on the
1249 target machine. If you don't define this, the default is half a
1250 word. (If this would be less than one storage unit, it is
1251 rounded up to one unit.) */
1252 #define SHORT_TYPE_SIZE 16
1254 /* A C expression for the size in bits of the type `long' on the
1255 target machine. If you don't define this, the default is one
1257 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1258 #define MAX_LONG_TYPE_SIZE 64
1260 /* A C expression for the size in bits of the type `long long' on the
1261 target machine. If you don't define this, the default is two
1263 #define LONG_LONG_TYPE_SIZE 64
1265 /* A C expression for the size in bits of the type `char' on the
1266 target machine. If you don't define this, the default is one
1267 quarter of a word. (If this would be less than one storage unit,
1268 it is rounded up to one unit.) */
1269 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1271 /* A C expression for the size in bits of the type `float' on the
1272 target machine. If you don't define this, the default is one
1274 #define FLOAT_TYPE_SIZE 32
1276 /* A C expression for the size in bits of the type `double' on the
1277 target machine. If you don't define this, the default is two
1279 #define DOUBLE_TYPE_SIZE 64
1281 /* A C expression for the size in bits of the type `long double' on
1282 the target machine. If you don't define this, the default is two
1284 #define LONG_DOUBLE_TYPE_SIZE 64
1286 /* Width in bits of a pointer.
1287 See also the macro `Pmode' defined below. */
1288 #ifndef POINTER_SIZE
1289 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1292 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1293 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1295 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1296 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1298 /* Allocation boundary (in *bits*) for the code of a function. */
1299 #define FUNCTION_BOUNDARY 32
1301 /* Alignment of field after `int : 0' in a structure. */
1302 #define EMPTY_FIELD_BOUNDARY 32
1304 /* Every structure's size must be a multiple of this. */
1305 /* 8 is observed right on a DECstation and on riscos 4.02. */
1306 #define STRUCTURE_SIZE_BOUNDARY 8
1308 /* There is no point aligning anything to a rounder boundary than this. */
1309 #define BIGGEST_ALIGNMENT 64
1311 /* Set this nonzero if move instructions will actually fail to work
1312 when given unaligned data. */
1313 #define STRICT_ALIGNMENT 1
1315 /* Define this if you wish to imitate the way many other C compilers
1316 handle alignment of bitfields and the structures that contain
1319 The behavior is that the type written for a bitfield (`int',
1320 `short', or other integer type) imposes an alignment for the
1321 entire structure, as if the structure really did contain an
1322 ordinary field of that type. In addition, the bitfield is placed
1323 within the structure so that it would fit within such a field,
1324 not crossing a boundary for it.
1326 Thus, on most machines, a bitfield whose type is written as `int'
1327 would not cross a four-byte boundary, and would force four-byte
1328 alignment for the whole structure. (The alignment used may not
1329 be four bytes; it is controlled by the other alignment
1332 If the macro is defined, its definition should be a C expression;
1333 a nonzero value for the expression enables this behavior. */
1335 #define PCC_BITFIELD_TYPE_MATTERS 1
1337 /* If defined, a C expression to compute the alignment given to a
1338 constant that is being placed in memory. CONSTANT is the constant
1339 and ALIGN is the alignment that the object would ordinarily have.
1340 The value of this macro is used instead of that alignment to align
1343 If this macro is not defined, then ALIGN is used.
1345 The typical use of this macro is to increase alignment for string
1346 constants to be word aligned so that `strcpy' calls that copy
1347 constants can be done inline. */
1349 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1350 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1351 && (ALIGN) < BITS_PER_WORD \
1355 /* If defined, a C expression to compute the alignment for a static
1356 variable. TYPE is the data type, and ALIGN is the alignment that
1357 the object would ordinarily have. The value of this macro is used
1358 instead of that alignment to align the object.
1360 If this macro is not defined, then ALIGN is used.
1362 One use of this macro is to increase alignment of medium-size
1363 data to make it all fit in fewer cache lines. Another is to
1364 cause character arrays to be word-aligned so that `strcpy' calls
1365 that copy constants to character arrays can be done inline. */
1367 #undef DATA_ALIGNMENT
1368 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1369 ((((ALIGN) < BITS_PER_WORD) \
1370 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1371 || TREE_CODE (TYPE) == UNION_TYPE \
1372 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1374 /* Define this macro if an argument declared as `char' or `short' in a
1375 prototype should actually be passed as an `int'. In addition to
1376 avoiding errors in certain cases of mismatch, it also makes for
1377 better code on certain machines. */
1379 #define PROMOTE_PROTOTYPES 1
1381 /* Define if operations between registers always perform the operation
1382 on the full register even if a narrower mode is specified. */
1383 #define WORD_REGISTER_OPERATIONS
1385 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1386 will either zero-extend or sign-extend. The value of this macro should
1387 be the code that says which one of the two operations is implicitly
1390 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1391 moves. All other referces are zero extended. */
1392 #define LOAD_EXTEND_OP(MODE) \
1393 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1394 ? SIGN_EXTEND : ZERO_EXTEND)
1396 /* Define this macro if it is advisable to hold scalars in registers
1397 in a wider mode than that declared by the program. In such cases,
1398 the value is constrained to be within the bounds of the declared
1399 type, but kept valid in the wider mode. The signedness of the
1400 extension may differ from that of the type.
1402 We promote any value smaller than SImode up to SImode. We don't
1403 want to promote to DImode when in 64 bit mode, because that would
1404 prevent us from using the faster SImode multiply and divide
1407 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1408 if (GET_MODE_CLASS (MODE) == MODE_INT \
1409 && GET_MODE_SIZE (MODE) < 4) \
1412 /* Define this if function arguments should also be promoted using the above
1415 #define PROMOTE_FUNCTION_ARGS
1417 /* Likewise, if the function return value is promoted. */
1419 #define PROMOTE_FUNCTION_RETURN
1421 /* Standard register usage. */
1423 /* Number of actual hardware registers.
1424 The hardware registers are assigned numbers for the compiler
1425 from 0 to just below FIRST_PSEUDO_REGISTER.
1426 All registers that the compiler knows about must be given numbers,
1427 even those that are not normally considered general registers.
1429 On the Mips, we have 32 integer registers, 32 floating point
1430 registers, 8 condition code registers, and the special registers
1431 hi, lo, hilo, and rap. The 8 condition code registers are only
1432 used if mips_isa >= 4. The hilo register is only used in 64 bit
1433 mode. It represents a 64 bit value stored as two 32 bit values in
1434 the hi and lo registers; this is the result of the mult
1435 instruction. rap is a pointer to the stack where the return
1436 address reg ($31) was stored. This is needed for C++ exception
1439 #define FIRST_PSEUDO_REGISTER 76
1441 /* 1 for registers that have pervasive standard uses
1442 and are not available for the register allocator.
1444 On the MIPS, see conventions, page D-2 */
1446 #define FIXED_REGISTERS \
1448 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1450 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1456 /* 1 for registers not available across function calls.
1457 These must include the FIXED_REGISTERS and also any
1458 registers that can be used without being saved.
1459 The latter must include the registers where values are returned
1460 and the register where structure-value addresses are passed.
1461 Aside from that, you can include as many other registers as you like. */
1463 #define CALL_USED_REGISTERS \
1465 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1466 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1467 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1468 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1469 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1473 /* Internal macros to classify a register number as to whether it's a
1474 general purpose register, a floating point register, a
1475 multiply/divide register, or a status register. */
1477 #define GP_REG_FIRST 0
1478 #define GP_REG_LAST 31
1479 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1480 #define GP_DBX_FIRST 0
1482 #define FP_REG_FIRST 32
1483 #define FP_REG_LAST 63
1484 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1485 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1487 #define MD_REG_FIRST 64
1488 #define MD_REG_LAST 66
1489 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1491 #define ST_REG_FIRST 67
1492 #define ST_REG_LAST 74
1493 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1495 #define RAP_REG_NUM 75
1497 #define AT_REGNUM (GP_REG_FIRST + 1)
1498 #define HI_REGNUM (MD_REG_FIRST + 0)
1499 #define LO_REGNUM (MD_REG_FIRST + 1)
1500 #define HILO_REGNUM (MD_REG_FIRST + 2)
1502 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1503 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1504 should be used instead. */
1505 #define FPSW_REGNUM ST_REG_FIRST
1507 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1508 #define M16_REG_P(REGNO) \
1509 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1510 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1511 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1512 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1514 /* Return number of consecutive hard regs needed starting at reg REGNO
1515 to hold something of mode MODE.
1516 This is ordinarily the length in words of a value of mode MODE
1517 but can be less for certain modes in special long registers.
1519 On the MIPS, all general registers are one word long. Except on
1520 the R4000 with the FR bit set, the floating point uses register
1521 pairs, with the second register not being allocable. */
1523 #define HARD_REGNO_NREGS(REGNO, MODE) \
1524 (! FP_REG_P (REGNO) \
1525 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1526 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1528 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1529 MODE. In 32 bit mode, require that DImode and DFmode be in even
1530 registers. For DImode, this makes some of the insns easier to
1531 write, since you don't have to worry about a DImode value in
1532 registers 3 & 4, producing a result in 4 & 5.
1534 To make the code simpler HARD_REGNO_MODE_OK now just references an
1535 array built in override_options. Because machmodes.h is not yet
1536 included before this file is processed, the MODE bound can't be
1539 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1541 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1542 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1544 /* Value is 1 if it is a good idea to tie two pseudo registers
1545 when one has mode MODE1 and one has mode MODE2.
1546 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1547 for any hard reg, then this must be 0 for correct output. */
1548 #define MODES_TIEABLE_P(MODE1, MODE2) \
1549 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1550 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1551 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1552 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1554 /* MIPS pc is not overloaded on a register. */
1555 /* #define PC_REGNUM xx */
1557 /* Register to use for pushing function arguments. */
1558 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1560 /* Offset from the stack pointer to the first available location. Use
1561 the default value zero. */
1562 /* #define STACK_POINTER_OFFSET 0 */
1564 /* Base register for access to local variables of the function. We
1565 pretend that the frame pointer is $1, and then eliminate it to
1566 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1567 a fixed register, and will not be used for anything else. */
1568 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1570 /* Temporary scratch register for use by the assembler. */
1571 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1573 /* $30 is not available on the mips16, so we use $17 as the frame
1575 #define HARD_FRAME_POINTER_REGNUM \
1576 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1578 /* Value should be nonzero if functions must have frame pointers.
1579 Zero means the frame pointer need not be set up (and parms
1580 may be accessed via the stack pointer) in functions that seem suitable.
1581 This is computed in `reload', in reload1.c. */
1582 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1584 /* Base register for access to arguments of the function. */
1585 #define ARG_POINTER_REGNUM GP_REG_FIRST
1587 /* Fake register that holds the address on the stack of the
1588 current function's return address. */
1589 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1591 /* Register in which static-chain is passed to a function. */
1592 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1594 /* If the structure value address is passed in a register, then
1595 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1596 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1598 /* If the structure value address is not passed in a register, define
1599 `STRUCT_VALUE' as an expression returning an RTX for the place
1600 where the address is passed. If it returns 0, the address is
1601 passed as an "invisible" first argument. */
1602 #define STRUCT_VALUE 0
1604 /* Mips registers used in prologue/epilogue code when the stack frame
1605 is larger than 32K bytes. These registers must come from the
1606 scratch register set, and not used for passing and returning
1607 arguments and any other information used in the calling sequence
1608 (such as pic). Must start at 12, since t0/t3 are parameter passing
1609 registers in the 64 bit ABI. */
1611 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1612 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1614 /* Define this macro if it is as good or better to call a constant
1615 function address than to call an address kept in a register. */
1616 #define NO_FUNCTION_CSE 1
1618 /* Define this macro if it is as good or better for a function to
1619 call itself with an explicit address than to call an address
1620 kept in a register. */
1621 #define NO_RECURSIVE_FUNCTION_CSE 1
1623 /* The register number of the register used to address a table of
1624 static data addresses in memory. In some cases this register is
1625 defined by a processor's "application binary interface" (ABI).
1626 When this macro is defined, RTL is generated for this register
1627 once, as with the stack pointer and frame pointer registers. If
1628 this macro is not defined, it is up to the machine-dependent
1629 files to allocate such a register (if necessary). */
1630 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1632 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1634 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1635 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1636 isn't always called for static inline functions. */
1637 #define INIT_EXPANDERS \
1639 embedded_pic_fnaddr_rtx = NULL; \
1640 mips16_gp_pseudo_rtx = NULL; \
1643 /* Define the classes of registers for register constraints in the
1644 machine description. Also define ranges of constants.
1646 One of the classes must always be named ALL_REGS and include all hard regs.
1647 If there is more than one class, another class must be named NO_REGS
1648 and contain no registers.
1650 The name GENERAL_REGS must be the name of a class (or an alias for
1651 another name such as ALL_REGS). This is the class of registers
1652 that is allowed by "g" or "r" in a register constraint.
1653 Also, registers outside this class are allocated only when
1654 instructions express preferences for them.
1656 The classes must be numbered in nondecreasing order; that is,
1657 a larger-numbered class must never be contained completely
1658 in a smaller-numbered class.
1660 For any two classes, it is very desirable that there be another
1661 class that represents their union. */
1665 NO_REGS, /* no registers in set */
1666 M16_NA_REGS, /* mips16 regs not used to pass args */
1667 M16_REGS, /* mips16 directly accessible registers */
1668 T_REG, /* mips16 T register ($24) */
1669 M16_T_REGS, /* mips16 registers plus T register */
1670 GR_REGS, /* integer registers */
1671 FP_REGS, /* floating point registers */
1672 HI_REG, /* hi register */
1673 LO_REG, /* lo register */
1674 HILO_REG, /* hilo register pair for 64 bit mode mult */
1675 MD_REGS, /* multiply/divide registers (hi/lo) */
1676 HI_AND_GR_REGS, /* union classes */
1679 ST_REGS, /* status registers (fp status) */
1680 ALL_REGS, /* all registers */
1681 LIM_REG_CLASSES /* max value + 1 */
1684 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1686 #define GENERAL_REGS GR_REGS
1688 /* An initializer containing the names of the register classes as C
1689 string constants. These names are used in writing some of the
1692 #define REG_CLASS_NAMES \
1707 "HILO_AND_GR_REGS", \
1712 /* An initializer containing the contents of the register classes,
1713 as integers which are bit masks. The Nth integer specifies the
1714 contents of class N. The way the integer MASK is interpreted is
1715 that register R is in the class if `MASK & (1 << R)' is 1.
1717 When the machine has more than 32 registers, an integer does not
1718 suffice. Then the integers are replaced by sub-initializers,
1719 braced groupings containing several integers. Each
1720 sub-initializer must be suitable as an initializer for the type
1721 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1723 #define REG_CLASS_CONTENTS \
1725 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1726 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1727 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1728 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1729 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1730 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1731 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1732 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1733 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1734 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1735 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1736 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1737 { 0xffffffff, 0x00000000, 0x00000002 }, \
1738 { 0xffffffff, 0x00000000, 0x00000004 }, \
1739 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1740 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1744 /* A C expression whose value is a register class containing hard
1745 register REGNO. In general there is more that one such class;
1746 choose a class which is "minimal", meaning that no smaller class
1747 also contains the register. */
1749 extern enum reg_class mips_regno_to_class[];
1751 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1753 /* A macro whose definition is the name of the class to which a
1754 valid base register must belong. A base register is one used in
1755 an address which is the register value plus a displacement. */
1757 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1759 /* A macro whose definition is the name of the class to which a
1760 valid index register must belong. An index register is one used
1761 in an address where its value is either multiplied by a scale
1762 factor or added to another register (as well as added to a
1765 #define INDEX_REG_CLASS NO_REGS
1767 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1768 registers explicitly used in the rtl to be used as spill registers
1769 but prevents the compiler from extending the lifetime of these
1772 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1774 /* This macro is used later on in the file. */
1775 #define GR_REG_CLASS_P(CLASS) \
1776 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1777 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1779 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1780 is the default value (allocate the registers in numeric order). We
1781 define it just so that we can override it for the mips16 target in
1782 ORDER_REGS_FOR_LOCAL_ALLOC. */
1784 #define REG_ALLOC_ORDER \
1785 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1786 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1787 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1788 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1789 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1792 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1793 to be rearranged based on a particular function. On the mips16, we
1794 want to allocate $24 (T_REG) before other registers for
1795 instructions for which it is possible. */
1797 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1799 /* REGISTER AND CONSTANT CLASSES */
1801 /* Get reg_class from a letter such as appears in the machine
1804 DEFINED REGISTER CLASSES:
1806 'd' General (aka integer) registers
1807 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1808 'y' General registers (in both mips16 and non mips16 mode)
1809 'e' mips16 non argument registers (M16_NA_REGS)
1810 't' mips16 temporary register ($24)
1811 'f' Floating point registers
1814 'x' Multiply/divide registers
1816 'z' FP Status register
1817 'b' All registers */
1819 extern enum reg_class mips_char_to_class[];
1821 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1823 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1824 string can be used to stand for particular ranges of immediate
1825 operands. This macro defines what the ranges are. C is the
1826 letter, and VALUE is a constant value. Return 1 if VALUE is
1827 in the range specified by C. */
1831 `I' is used for the range of constants an arithmetic insn can
1832 actually contain (16 bits signed integers).
1834 `J' is used for the range which is just zero (ie, $r0).
1836 `K' is used for the range of constants a logical insn can actually
1837 contain (16 bit zero-extended integers).
1839 `L' is used for the range of constants that be loaded with lui
1840 (ie, the bottom 16 bits are zero).
1842 `M' is used for the range of constants that take two words to load
1843 (ie, not matched by `I', `K', and `L').
1845 `N' is used for negative 16 bit constants other than -65536.
1847 `O' is a 15 bit signed integer.
1849 `P' is used for positive 16 bit constants. */
1851 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1852 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1854 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1855 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1856 : (C) == 'J' ? ((VALUE) == 0) \
1857 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1858 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1859 && (((VALUE) & ~2147483647) == 0 \
1860 || ((VALUE) & ~2147483647) == ~2147483647)) \
1861 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1862 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1863 && (((VALUE) & 0x0000ffff) != 0 \
1864 || (((VALUE) & ~2147483647) != 0 \
1865 && ((VALUE) & ~2147483647) != ~2147483647))) \
1866 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1867 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1868 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1871 /* Similar, but for floating constants, and defining letters G and H.
1872 Here VALUE is the CONST_DOUBLE rtx itself. */
1876 'G' : Floating point 0 */
1878 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1880 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1882 /* Letters in the range `Q' through `U' may be defined in a
1883 machine-dependent fashion to stand for arbitrary operand types.
1884 The machine description macro `EXTRA_CONSTRAINT' is passed the
1885 operand as its first argument and the constraint letter as its
1888 `Q' is for mips16 GP relative constants
1889 `R' is for memory references which take 1 word for the instruction.
1890 `S' is for references to extern items which are PIC for OSF/rose.
1891 `T' is for memory addresses that can be used to load two words. */
1893 #define EXTRA_CONSTRAINT(OP,CODE) \
1894 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1895 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1896 && mips16_gp_offset_p (OP)) \
1897 : (GET_CODE (OP) != MEM) ? FALSE \
1898 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1899 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1900 && HALF_PIC_ADDRESS_P (OP)) \
1903 /* Given an rtx X being reloaded into a reg required to be
1904 in class CLASS, return the class of reg to actually use.
1905 In general this is just CLASS; but on some machines
1906 in some cases it is preferable to use a more restrictive class. */
1908 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1909 ((CLASS) != ALL_REGS \
1910 ? (! TARGET_MIPS16 \
1912 : ((CLASS) != GR_REGS \
1915 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1916 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1917 ? (TARGET_SOFT_FLOAT \
1918 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1920 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1921 || GET_MODE (X) == VOIDmode) \
1922 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1925 /* Certain machines have the property that some registers cannot be
1926 copied to some other registers without using memory. Define this
1927 macro on those machines to be a C expression that is non-zero if
1928 objects of mode MODE in registers of CLASS1 can only be copied to
1929 registers of class CLASS2 by storing a register of CLASS1 into
1930 memory and loading that memory location into a register of CLASS2.
1932 Do not define this macro if its value would always be zero. */
1934 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1935 ((!TARGET_DEBUG_H_MODE \
1936 && GET_MODE_CLASS (MODE) == MODE_INT \
1937 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1938 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1939 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1940 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1941 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1943 /* The HI and LO registers can only be reloaded via the general
1944 registers. Condition code registers can only be loaded to the
1945 general registers, and from the floating point registers. */
1947 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1948 mips_secondary_reload_class (CLASS, MODE, X, 1)
1949 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1950 mips_secondary_reload_class (CLASS, MODE, X, 0)
1952 /* Return the maximum number of consecutive registers
1953 needed to represent mode MODE in a register of class CLASS. */
1955 #define CLASS_UNITS(mode, size) \
1956 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1958 #define CLASS_MAX_NREGS(CLASS, MODE) \
1959 ((CLASS) == FP_REGS \
1961 ? CLASS_UNITS (MODE, 8) \
1962 : 2 * CLASS_UNITS (MODE, 8)) \
1963 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1965 /* If defined, gives a class of registers that cannot be used as the
1966 operand of a SUBREG that changes the size of the object. */
1968 #define CLASS_CANNOT_CHANGE_SIZE \
1969 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
1971 /* If defined, this is a C expression whose value should be
1972 nonzero if the insn INSN has the effect of mysteriously
1973 clobbering the contents of hard register number REGNO. By
1974 "mysterious" we mean that the insn's RTL expression doesn't
1975 describe such an effect.
1977 If this macro is not defined, it means that no insn clobbers
1978 registers mysteriously. This is the usual situation; all else
1979 being equal, it is best for the RTL expression to show all the
1982 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1985 /* Stack layout; function entry, exit and calling. */
1987 /* Define this if pushing a word on the stack
1988 makes the stack pointer a smaller address. */
1989 #define STACK_GROWS_DOWNWARD
1991 /* Define this if the nominal address of the stack frame
1992 is at the high-address end of the local variables;
1993 that is, each additional local variable allocated
1994 goes at a more negative offset in the frame. */
1995 /* #define FRAME_GROWS_DOWNWARD */
1997 /* Offset within stack frame to start allocating local variables at.
1998 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1999 first local allocated. Otherwise, it is the offset to the BEGINNING
2000 of the first local allocated. */
2001 #define STARTING_FRAME_OFFSET \
2002 (current_function_outgoing_args_size \
2003 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2005 /* Offset from the stack pointer register to an item dynamically
2006 allocated on the stack, e.g., by `alloca'.
2008 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2009 length of the outgoing arguments. The default is correct for most
2010 machines. See `function.c' for details.
2012 The MIPS ABI states that functions which dynamically allocate the
2013 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2014 we are trying to create a second frame pointer to the function, so
2015 allocate some stack space to make it happy.
2017 However, the linker currently complains about linking any code that
2018 dynamically allocates stack space, and there seems to be a bug in
2019 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2022 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2023 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2024 ? 4*UNITS_PER_WORD \
2025 : current_function_outgoing_args_size)
2028 /* The return address for the current frame is in r31 is this is a leaf
2029 function. Otherwise, it is on the stack. It is at a variable offset
2030 from sp/fp/ap, so we define a fake hard register rap which is a
2031 poiner to the return address on the stack. This always gets eliminated
2032 during reload to be either the frame pointer or the stack pointer plus
2035 /* ??? This definition fails for leaf functions. There is currently no
2036 general solution for this problem. */
2038 /* ??? There appears to be no way to get the return address of any previous
2039 frame except by disassembling instructions in the prologue/epilogue.
2040 So currently we support only the current frame. */
2042 #define RETURN_ADDR_RTX(count, frame) \
2044 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2047 /* Structure to be filled in by compute_frame_size with register
2048 save masks, and offsets for the current function. */
2050 struct mips_frame_info
2052 long total_size; /* # bytes that the entire frame takes up */
2053 long var_size; /* # bytes that variables take up */
2054 long args_size; /* # bytes that outgoing arguments take up */
2055 long extra_size; /* # bytes of extra gunk */
2056 int gp_reg_size; /* # bytes needed to store gp regs */
2057 int fp_reg_size; /* # bytes needed to store fp regs */
2058 long mask; /* mask of saved gp registers */
2059 long fmask; /* mask of saved fp registers */
2060 long gp_save_offset; /* offset from vfp to store gp registers */
2061 long fp_save_offset; /* offset from vfp to store fp registers */
2062 long gp_sp_offset; /* offset from new sp to store gp registers */
2063 long fp_sp_offset; /* offset from new sp to store fp registers */
2064 int initialized; /* != 0 if frame size already calculated */
2065 int num_gp; /* number of gp registers saved */
2066 int num_fp; /* number of fp registers saved */
2067 long insns_len; /* length of insns; mips16 only */
2070 extern struct mips_frame_info current_frame_info;
2072 /* If defined, this macro specifies a table of register pairs used to
2073 eliminate unneeded registers that point into the stack frame. If
2074 it is not defined, the only elimination attempted by the compiler
2075 is to replace references to the frame pointer with references to
2078 The definition of this macro is a list of structure
2079 initializations, each of which specifies an original and
2080 replacement register.
2082 On some machines, the position of the argument pointer is not
2083 known until the compilation is completed. In such a case, a
2084 separate hard register must be used for the argument pointer.
2085 This register can be eliminated by replacing it with either the
2086 frame pointer or the argument pointer, depending on whether or not
2087 the frame pointer has been eliminated.
2089 In this case, you might specify:
2090 #define ELIMINABLE_REGS \
2091 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2092 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2093 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2095 Note that the elimination of the argument pointer with the stack
2096 pointer is specified first since that is the preferred elimination.
2098 The eliminations to $17 are only used on the mips16. See the
2099 definition of HARD_FRAME_POINTER_REGNUM. */
2101 #define ELIMINABLE_REGS \
2102 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2103 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2104 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2105 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2106 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2107 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2108 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2109 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2110 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2111 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2113 /* A C expression that returns non-zero if the compiler is allowed to
2114 try to replace register number FROM-REG with register number
2115 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2116 defined, and will usually be the constant 1, since most of the
2117 cases preventing register elimination are things that the compiler
2118 already knows about.
2120 When not in mips16 and mips64, we can always eliminate to the
2121 frame pointer. We can eliminate to the stack pointer unless
2122 a frame pointer is needed. In mips16 mode, we need a frame
2123 pointer for a large frame; otherwise, reload may be unable
2124 to compute the address of a local variable, since there is
2125 no way to add a large constant to the stack pointer
2126 without using a temporary register.
2128 In mips16, for some instructions (eg lwu), we can't eliminate the
2129 frame pointer for the stack pointer. These instructions are
2130 only generated in TARGET_64BIT mode.
2133 #define CAN_ELIMINATE(FROM, TO) \
2134 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2135 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2136 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2137 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2138 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2139 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2140 && (! TARGET_MIPS16 \
2141 || compute_frame_size (get_frame_size ()) < 32768)))))
2143 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2144 specifies the initial difference between the specified pair of
2145 registers. This macro must be defined if `ELIMINABLE_REGS' is
2148 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2149 { compute_frame_size (get_frame_size ()); \
2150 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2151 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2152 (OFFSET) = - current_function_outgoing_args_size; \
2153 else if ((FROM) == FRAME_POINTER_REGNUM) \
2155 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2156 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2157 (OFFSET) = (current_frame_info.total_size \
2158 - current_function_outgoing_args_size \
2159 - ((mips_abi != ABI_32 \
2160 && mips_abi != ABI_O64 \
2161 && mips_abi != ABI_EABI) \
2162 ? current_function_pretend_args_size \
2164 else if ((FROM) == ARG_POINTER_REGNUM) \
2165 (OFFSET) = (current_frame_info.total_size \
2166 - ((mips_abi != ABI_32 \
2167 && mips_abi != ABI_O64 \
2168 && mips_abi != ABI_EABI) \
2169 ? current_function_pretend_args_size \
2171 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2172 so we must add 4 bytes to the offset to get the right value. */ \
2173 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2175 if (leaf_function_p ()) \
2177 else (OFFSET) = current_frame_info.gp_sp_offset \
2178 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2179 * (BYTES_BIG_ENDIAN != 0)); \
2183 /* If we generate an insn to push BYTES bytes,
2184 this says how many the stack pointer really advances by.
2185 On the vax, sp@- in a byte insn really pushes a word. */
2187 /* #define PUSH_ROUNDING(BYTES) 0 */
2189 /* If defined, the maximum amount of space required for outgoing
2190 arguments will be computed and placed into the variable
2191 `current_function_outgoing_args_size'. No space will be pushed
2192 onto the stack for each call; instead, the function prologue
2193 should increase the stack frame size by this amount.
2195 It is not proper to define both `PUSH_ROUNDING' and
2196 `ACCUMULATE_OUTGOING_ARGS'. */
2197 #define ACCUMULATE_OUTGOING_ARGS
2199 /* Offset from the argument pointer register to the first argument's
2200 address. On some machines it may depend on the data type of the
2203 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2204 the first argument's address.
2206 On the MIPS, we must skip the first argument position if we are
2207 returning a structure or a union, to account for its address being
2208 passed in $4. However, at the current time, this produces a compiler
2209 that can't bootstrap, so comment it out for now. */
2212 #define FIRST_PARM_OFFSET(FNDECL) \
2214 && TREE_TYPE (FNDECL) != 0 \
2215 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2216 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2217 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2221 #define FIRST_PARM_OFFSET(FNDECL) 0
2224 /* When a parameter is passed in a register, stack space is still
2225 allocated for it. For the MIPS, stack space must be allocated, cf
2226 Asm Lang Prog Guide page 7-8.
2228 BEWARE that some space is also allocated for non existing arguments
2229 in register. In case an argument list is of form GF used registers
2230 are a0 (a2,a3), but we should push over a1... */
2232 #define REG_PARM_STACK_SPACE(FNDECL) \
2233 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2235 /* Define this if it is the responsibility of the caller to
2236 allocate the area reserved for arguments passed in registers.
2237 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2238 of this macro is to determine whether the space is included in
2239 `current_function_outgoing_args_size'. */
2240 #define OUTGOING_REG_PARM_STACK_SPACE
2242 /* Align stack frames on 64 bits (Double Word ). */
2243 #ifndef STACK_BOUNDARY
2244 #define STACK_BOUNDARY 64
2247 /* Make sure 4 words are always allocated on the stack. */
2249 #ifndef STACK_ARGS_ADJUST
2250 #define STACK_ARGS_ADJUST(SIZE) \
2252 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2253 SIZE.constant = 4 * UNITS_PER_WORD; \
2258 /* A C expression that should indicate the number of bytes of its
2259 own arguments that a function pops on returning, or 0
2260 if the function pops no arguments and the caller must therefore
2261 pop them all after the function returns.
2263 FUNDECL is the declaration node of the function (as a tree).
2265 FUNTYPE is a C variable whose value is a tree node that
2266 describes the function in question. Normally it is a node of
2267 type `FUNCTION_TYPE' that describes the data type of the function.
2268 From this it is possible to obtain the data types of the value
2269 and arguments (if known).
2271 When a call to a library function is being considered, FUNTYPE
2272 will contain an identifier node for the library function. Thus,
2273 if you need to distinguish among various library functions, you
2274 can do so by their names. Note that "library function" in this
2275 context means a function used to perform arithmetic, whose name
2276 is known specially in the compiler and was not mentioned in the
2277 C code being compiled.
2279 STACK-SIZE is the number of bytes of arguments passed on the
2280 stack. If a variable number of bytes is passed, it is zero, and
2281 argument popping will always be the responsibility of the
2282 calling function. */
2284 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2287 /* Symbolic macros for the registers used to return integer and floating
2290 #define GP_RETURN (GP_REG_FIRST + 2)
2291 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2293 /* Symbolic macros for the first/last argument registers. */
2295 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2296 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2297 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2298 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2300 #define MAX_ARGS_IN_REGISTERS 4
2302 /* Define how to find the value returned by a library function
2303 assuming the value has mode MODE. Because we define
2304 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2305 PROMOTE_MODE does. */
2307 #define LIBCALL_VALUE(MODE) \
2309 ((GET_MODE_CLASS (MODE) != MODE_INT \
2310 || GET_MODE_SIZE (MODE) >= 4) \
2313 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2314 && (! TARGET_SINGLE_FLOAT \
2315 || GET_MODE_SIZE (MODE) <= 4)) \
2319 /* Define how to find the value returned by a function.
2320 VALTYPE is the data type of the value (as a tree).
2321 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2322 otherwise, FUNC is 0. */
2324 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2327 /* 1 if N is a possible register number for a function value.
2328 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2329 Currently, R2 and F0 are only implemented here (C has no complex type) */
2331 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2333 /* 1 if N is a possible register number for function argument passing.
2334 We have no FP argument registers when soft-float. When FP registers
2335 are 32 bits, we can't directly reference the odd numbered ones. */
2337 #define FUNCTION_ARG_REGNO_P(N) \
2338 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2339 || ((! TARGET_SOFT_FLOAT \
2340 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2341 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2342 && ! fixed_regs[N]))
2344 /* A C expression which can inhibit the returning of certain function
2345 values in registers, based on the type of value. A nonzero value says
2346 to return the function value in memory, just as large structures are
2347 always returned. Here TYPE will be a C expression of type
2348 `tree', representing the data type of the value.
2350 Note that values of mode `BLKmode' must be explicitly
2351 handled by this macro. Also, the option `-fpcc-struct-return'
2352 takes effect regardless of this macro. On most systems, it is
2353 possible to leave the macro undefined; this causes a default
2354 definition to be used, whose value is the constant 1 for BLKmode
2355 values, and 0 otherwise.
2357 GCC normally converts 1 byte structures into chars, 2 byte
2358 structs into shorts, and 4 byte structs into ints, and returns
2359 them this way. Defining the following macro overrides this,
2360 to give us MIPS cc compatibility. */
2362 #define RETURN_IN_MEMORY(TYPE) \
2363 (TYPE_MODE (TYPE) == BLKmode)
2365 /* A code distinguishing the floating point format of the target
2366 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2367 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2369 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2372 /* Define a data type for recording info about an argument list
2373 during the scan of that argument list. This data type should
2374 hold all necessary information about the function itself
2375 and about the args processed so far, enough to enable macros
2376 such as FUNCTION_ARG to determine where the next arg should go.
2378 On the mips16, we need to keep track of which floating point
2379 arguments were passed in general registers, but would have been
2380 passed in the FP regs if this were a 32 bit function, so that we
2381 can move them to the FP regs if we wind up calling a 32 bit
2382 function. We record this information in fp_code, encoded in base
2383 four. A zero digit means no floating point argument, a one digit
2384 means an SFmode argument, and a two digit means a DFmode argument,
2385 and a three digit is not used. The low order digit is the first
2386 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2387 an SFmode argument. ??? A more sophisticated approach will be
2388 needed if MIPS_ABI != ABI_32. */
2390 typedef struct mips_args {
2391 int gp_reg_found; /* whether a gp register was found yet */
2392 int arg_number; /* argument number */
2393 int arg_words; /* # total words the arguments take */
2394 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2395 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2396 int fp_code; /* Mode of FP arguments (mips16) */
2397 int num_adjusts; /* number of adjustments made */
2398 /* Adjustments made to args pass in regs. */
2399 /* ??? The size is doubled to work around a
2400 bug in the code that sets the adjustments
2402 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2405 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2406 for a call to a function whose data type is FNTYPE.
2407 For a library call, FNTYPE is 0.
2411 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2412 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2414 /* Update the data in CUM to advance over an argument
2415 of mode MODE and data type TYPE.
2416 (TYPE is null for libcalls where that information may not be available.) */
2418 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2419 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2421 /* Determine where to put an argument to a function.
2422 Value is zero to push the argument on the stack,
2423 or a hard register in which to store the argument.
2425 MODE is the argument's machine mode.
2426 TYPE is the data type of the argument (as a tree).
2427 This is null for libcalls where that information may
2429 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2430 the preceding args and about the function being called.
2431 NAMED is nonzero if this argument is a named parameter
2432 (otherwise it is an extra parameter matching an ellipsis). */
2434 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2435 function_arg( &CUM, MODE, TYPE, NAMED)
2437 /* For an arg passed partly in registers and partly in memory,
2438 this is the number of registers used.
2439 For args passed entirely in registers or entirely in memory, zero. */
2441 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2442 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2444 /* If defined, a C expression that gives the alignment boundary, in
2445 bits, of an argument with the specified mode and type. If it is
2446 not defined, `PARM_BOUNDARY' is used for all arguments. */
2448 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2450 ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \
2452 : TYPE_ALIGN(TYPE)) \
2453 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2455 : GET_MODE_ALIGNMENT(MODE)))
2458 /* This macro generates the assembly code for function entry.
2459 FILE is a stdio stream to output the code to.
2460 SIZE is an int: how many units of temporary storage to allocate.
2461 Refer to the array `regs_ever_live' to determine which registers
2462 to save; `regs_ever_live[I]' is nonzero if register number I
2463 is ever used in the function. This macro is responsible for
2464 knowing which registers should not be saved even if used. */
2466 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2468 /* This macro generates the assembly code for function exit,
2469 on machines that need it. If FUNCTION_EPILOGUE is not defined
2470 then individual return instructions are generated for each
2471 return statement. Args are same as for FUNCTION_PROLOGUE. */
2473 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2475 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2477 #define MUST_SAVE_REGISTER(regno) \
2478 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2479 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2480 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2482 /* ALIGN FRAMES on double word boundaries */
2483 #ifndef MIPS_STACK_ALIGN
2484 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2488 /* Define the `__builtin_va_list' type for the ABI. */
2489 #define BUILD_VA_LIST_TYPE(VALIST) \
2490 (VALIST) = mips_build_va_list ()
2492 /* Implement `va_start' for varargs and stdarg. */
2493 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2494 mips_va_start (stdarg, valist, nextarg)
2496 /* Implement `va_arg'. */
2497 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2498 mips_va_arg (valist, type)
2500 /* Output assembler code to FILE to increment profiler label # LABELNO
2501 for profiling a function entry. */
2503 #define FUNCTION_PROFILER(FILE, LABELNO) \
2505 if (TARGET_MIPS16) \
2506 sorry ("mips16 function profiling"); \
2507 fprintf (FILE, "\t.set\tnoreorder\n"); \
2508 fprintf (FILE, "\t.set\tnoat\n"); \
2509 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2510 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2511 fprintf (FILE, "\tjal\t_mcount\n"); \
2513 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2514 TARGET_64BIT ? "dsubu" : "subu", \
2515 reg_names[STACK_POINTER_REGNUM], \
2516 reg_names[STACK_POINTER_REGNUM], \
2517 Pmode == DImode ? 16 : 8); \
2518 fprintf (FILE, "\t.set\treorder\n"); \
2519 fprintf (FILE, "\t.set\tat\n"); \
2522 /* Define this macro if the code for function profiling should come
2523 before the function prologue. Normally, the profiling code comes
2526 /* #define PROFILE_BEFORE_PROLOGUE */
2528 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2529 the stack pointer does not matter. The value is tested only in
2530 functions that have frame pointers.
2531 No definition is equivalent to always zero. */
2533 #define EXIT_IGNORE_STACK 1
2536 /* A C statement to output, on the stream FILE, assembler code for a
2537 block of data that contains the constant parts of a trampoline.
2538 This code should not include a label--the label is taken care of
2541 #define TRAMPOLINE_TEMPLATE(STREAM) \
2543 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2544 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2545 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2546 if (Pmode == DImode) \
2548 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2549 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2553 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2554 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2556 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2557 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2558 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2559 if (Pmode == DImode) \
2561 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2562 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2566 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2567 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2571 /* A C expression for the size in bytes of the trampoline, as an
2574 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2576 /* Alignment required for trampolines, in bits. */
2578 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2580 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2581 program and data caches. */
2583 #ifndef CACHE_FLUSH_FUNC
2584 #define CACHE_FLUSH_FUNC "_flush_cache"
2587 /* A C statement to initialize the variable parts of a trampoline.
2588 ADDR is an RTX for the address of the trampoline; FNADDR is an
2589 RTX for the address of the nested function; STATIC_CHAIN is an
2590 RTX for the static chain value that should be passed to the
2591 function when it is called. */
2593 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2596 if (Pmode == DImode) \
2598 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2599 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2603 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2604 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2607 /* Flush both caches. We need to flush the data cache in case \
2608 the system has a write-back cache. */ \
2609 /* ??? Should check the return value for errors. */ \
2610 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2611 0, VOIDmode, 3, addr, Pmode, \
2612 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2613 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2616 /* Addressing modes, and classification of registers for them. */
2618 /* #define HAVE_POST_INCREMENT 0 */
2619 /* #define HAVE_POST_DECREMENT 0 */
2621 /* #define HAVE_PRE_DECREMENT 0 */
2622 /* #define HAVE_PRE_INCREMENT 0 */
2624 /* These assume that REGNO is a hard or pseudo reg number.
2625 They give nonzero only if REGNO is a hard reg of the suitable class
2626 or a pseudo reg currently allocated to a suitable hard reg.
2627 These definitions are NOT overridden anywhere. */
2629 #define BASE_REG_P(regno, mode) \
2631 ? (M16_REG_P (regno) \
2632 || (regno) == FRAME_POINTER_REGNUM \
2633 || (regno) == ARG_POINTER_REGNUM \
2634 || ((regno) == STACK_POINTER_REGNUM \
2635 && (GET_MODE_SIZE (mode) == 4 \
2636 || GET_MODE_SIZE (mode) == 8))) \
2639 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2640 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2643 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2644 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2646 #define REGNO_OK_FOR_INDEX_P(regno) 0
2647 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2648 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2650 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2651 and check its validity for a certain class.
2652 We have two alternate definitions for each of them.
2653 The usual definition accepts all pseudo regs; the other rejects them all.
2654 The symbol REG_OK_STRICT causes the latter definition to be used.
2656 Most source files want to accept pseudo regs in the hope that
2657 they will get allocated to the class that the insn wants them to be in.
2658 Some source files that are used after register allocation
2659 need to be strict. */
2661 #ifndef REG_OK_STRICT
2663 #define REG_OK_STRICT_P 0
2664 #define REG_OK_FOR_INDEX_P(X) 0
2665 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2666 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2670 #define REG_OK_STRICT_P 1
2671 #define REG_OK_FOR_INDEX_P(X) 0
2672 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2673 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2678 /* Maximum number of registers that can appear in a valid memory address. */
2680 #define MAX_REGS_PER_ADDRESS 1
2682 /* A C compound statement with a conditional `goto LABEL;' executed
2683 if X (an RTX) is a legitimate memory address on the target
2684 machine for a memory operand of mode MODE.
2686 It usually pays to define several simpler macros to serve as
2687 subroutines for this one. Otherwise it may be too complicated
2690 This macro must exist in two variants: a strict variant and a
2691 non-strict one. The strict variant is used in the reload pass.
2692 It must be defined so that any pseudo-register that has not been
2693 allocated a hard register is considered a memory reference. In
2694 contexts where some kind of register is required, a
2695 pseudo-register with no hard register must be rejected.
2697 The non-strict variant is used in other passes. It must be
2698 defined to accept all pseudo-registers in every context where
2699 some kind of register is required.
2701 Compiler source files that want to use the strict variant of
2702 this macro define the macro `REG_OK_STRICT'. You should use an
2703 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2704 in that case and the non-strict variant otherwise.
2706 Typically among the subroutines used to define
2707 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2708 acceptable registers for various purposes (one for base
2709 registers, one for index registers, and so on). Then only these
2710 subroutine macros need have two variants; the higher levels of
2711 macros may be the same whether strict or not.
2713 Normally, constant addresses which are the sum of a `symbol_ref'
2714 and an integer are stored inside a `const' RTX to mark them as
2715 constant. Therefore, there is no need to recognize such sums
2716 specifically as legitimate addresses. Normally you would simply
2717 recognize any `const' as legitimate.
2719 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2720 constant sums that are not marked with `const'. It assumes
2721 that a naked `plus' indicates indexing. If so, then you *must*
2722 reject such naked constant sums as illegitimate addresses, so
2723 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2725 On some machines, whether a symbolic address is legitimate
2726 depends on the section that the address refers to. On these
2727 machines, define the macro `ENCODE_SECTION_INFO' to store the
2728 information into the `symbol_ref', and then check for it here.
2729 When you see a `const', you will have to look inside it to find
2730 the `symbol_ref' in order to determine the section. */
2733 #define GO_PRINTF(x) fprintf(stderr, (x))
2734 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2735 #define GO_DEBUG_RTX(x) debug_rtx(x)
2738 #define GO_PRINTF(x)
2739 #define GO_PRINTF2(x,y)
2740 #define GO_DEBUG_RTX(x)
2743 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2745 register rtx xinsn = (X); \
2747 if (TARGET_DEBUG_B_MODE) \
2749 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2750 (REG_OK_STRICT_P) ? "" : "not "); \
2751 GO_DEBUG_RTX (xinsn); \
2754 while (GET_CODE (xinsn) == SUBREG) \
2755 xinsn = SUBREG_REG (xinsn); \
2757 /* The mips16 can only use the stack pointer as a base register when \
2758 loading SImode or DImode values. */ \
2759 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2762 if (CONSTANT_ADDRESS_P (xinsn) \
2763 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2764 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2767 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2769 register rtx xlow0 = XEXP (xinsn, 0); \
2770 register rtx xlow1 = XEXP (xinsn, 1); \
2772 while (GET_CODE (xlow0) == SUBREG) \
2773 xlow0 = SUBREG_REG (xlow0); \
2774 if (GET_CODE (xlow0) == REG \
2775 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2776 && mips_check_split (xlow1, MODE)) \
2780 if (GET_CODE (xinsn) == PLUS) \
2782 register rtx xplus0 = XEXP (xinsn, 0); \
2783 register rtx xplus1 = XEXP (xinsn, 1); \
2784 register enum rtx_code code0; \
2785 register enum rtx_code code1; \
2787 while (GET_CODE (xplus0) == SUBREG) \
2788 xplus0 = SUBREG_REG (xplus0); \
2789 code0 = GET_CODE (xplus0); \
2791 while (GET_CODE (xplus1) == SUBREG) \
2792 xplus1 = SUBREG_REG (xplus1); \
2793 code1 = GET_CODE (xplus1); \
2795 /* The mips16 can only use the stack pointer as a base register \
2796 when loading SImode or DImode values. */ \
2797 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2799 if (code1 == CONST_INT \
2800 && INTVAL (xplus1) >= -32768 \
2801 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2804 /* On the mips16, we represent GP relative offsets in RTL. \
2805 These are 16 bit signed values, and can serve as register \
2808 && mips16_gp_offset_p (xplus1)) \
2811 /* For some code sequences, you actually get better code by \
2812 pretending that the MIPS supports an address mode of a \
2813 constant address + a register, even though the real \
2814 machine doesn't support it. This is because the \
2815 assembler can use $r1 to load just the high 16 bits, add \
2816 in the register, and fold the low 16 bits into the memory \
2817 reference, whereas the compiler generates a 4 instruction \
2818 sequence. On the other hand, CSE is not as effective. \
2819 It would be a win to generate the lui directly, but the \
2820 MIPS assembler does not have syntax to generate the \
2821 appropriate relocation. */ \
2823 /* Also accept CONST_INT addresses here, so no else. */ \
2824 /* Reject combining an embedded PIC text segment reference \
2825 with a register. That requires an additional \
2827 /* ??? Reject combining an address with a register for the MIPS \
2828 64 bit ABI, because the SGI assembler can not handle this. */ \
2829 if (!TARGET_DEBUG_A_MODE \
2830 && (mips_abi == ABI_32 \
2831 || mips_abi == ABI_O64 \
2832 || mips_abi == ABI_EABI) \
2833 && CONSTANT_ADDRESS_P (xplus1) \
2834 && ! mips_split_addresses \
2835 && (!TARGET_EMBEDDED_PIC \
2837 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2838 && ! (code1 == CONST_INT && ! SMALL_INT (xplus1)) \
2839 && !TARGET_MIPS16) \
2844 if (TARGET_DEBUG_B_MODE) \
2845 GO_PRINTF ("Not a legitimate address\n"); \
2849 /* A C expression that is 1 if the RTX X is a constant which is a
2850 valid address. This is defined to be the same as `CONSTANT_P (X)',
2851 but rejecting CONST_DOUBLE. */
2852 /* When pic, we must reject addresses of the form symbol+large int.
2853 This is because an instruction `sw $4,s+70000' needs to be converted
2854 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2855 assembler would use $at as a temp to load in the large offset. In this
2856 case $at is already in use. We convert such problem addresses to
2857 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2858 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2859 #define CONSTANT_ADDRESS_P(X) \
2860 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2861 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2862 || (GET_CODE (X) == CONST \
2863 && ! (flag_pic && pic_address_needs_scratch (X)) \
2864 && (mips_abi == ABI_32 \
2865 || mips_abi == ABI_O64 \
2866 || mips_abi == ABI_EABI))) \
2867 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2869 /* Define this, so that when PIC, reload won't try to reload invalid
2870 addresses which require two reload registers. */
2872 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2874 /* Nonzero if the constant value X is a legitimate general operand.
2875 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2877 At present, GAS doesn't understand li.[sd], so don't allow it
2878 to be generated at present. Also, the MIPS assembler does not
2879 grok li.d Infinity. */
2881 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2882 #define LEGITIMATE_CONSTANT_P(X) \
2883 ((GET_CODE (X) != CONST_DOUBLE \
2884 || mips_const_double_ok (X, GET_MODE (X))) \
2885 && ! (GET_CODE (X) == CONST \
2886 && mips_abi != ABI_32 \
2887 && mips_abi != ABI_O64 \
2888 && mips_abi != ABI_EABI) \
2889 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2891 /* A C compound statement that attempts to replace X with a valid
2892 memory address for an operand of mode MODE. WIN will be a C
2893 statement label elsewhere in the code; the macro definition may
2896 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2898 to avoid further processing if the address has become legitimate.
2900 X will always be the result of a call to `break_out_memory_refs',
2901 and OLDX will be the operand that was given to that function to
2904 The code generated by this macro should not alter the
2905 substructure of X. If it transforms X into a more legitimate
2906 form, it should assign X (which will always be a C variable) a
2909 It is not necessary for this macro to come up with a legitimate
2910 address. The compiler has standard ways of doing so in all
2911 cases. In fact, it is safe for this macro to do nothing. But
2912 often a machine-dependent strategy can generate better code.
2914 For the MIPS, transform:
2916 memory(X + <large int>)
2920 Y = <large int> & ~0x7fff;
2922 memory (Z + (<large int> & 0x7fff));
2924 This is for CSE to find several similar references, and only use one Z.
2926 When PIC, convert addresses of the form memory (symbol+large int) to
2927 memory (reg+large int). */
2930 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2932 register rtx xinsn = (X); \
2934 if (TARGET_DEBUG_B_MODE) \
2936 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2937 GO_DEBUG_RTX (xinsn); \
2940 if (mips_split_addresses && mips_check_split (X, MODE)) \
2942 /* ??? Is this ever executed? */ \
2943 X = gen_rtx_LO_SUM (Pmode, \
2944 copy_to_mode_reg (Pmode, \
2945 gen_rtx (HIGH, Pmode, X)), \
2950 if (GET_CODE (xinsn) == CONST \
2951 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2952 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2953 || (mips_abi != ABI_32 \
2954 && mips_abi != ABI_O64 \
2955 && mips_abi != ABI_EABI))) \
2957 rtx ptr_reg = gen_reg_rtx (Pmode); \
2958 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2960 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2962 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
2963 if (SMALL_INT (constant)) \
2965 /* Otherwise we fall through so the code below will fix the \
2970 if (GET_CODE (xinsn) == PLUS) \
2972 register rtx xplus0 = XEXP (xinsn, 0); \
2973 register rtx xplus1 = XEXP (xinsn, 1); \
2974 register enum rtx_code code0 = GET_CODE (xplus0); \
2975 register enum rtx_code code1 = GET_CODE (xplus1); \
2977 if (code0 != REG && code1 == REG) \
2979 xplus0 = XEXP (xinsn, 1); \
2980 xplus1 = XEXP (xinsn, 0); \
2981 code0 = GET_CODE (xplus0); \
2982 code1 = GET_CODE (xplus1); \
2985 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2986 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2988 rtx int_reg = gen_reg_rtx (Pmode); \
2989 rtx ptr_reg = gen_reg_rtx (Pmode); \
2991 emit_move_insn (int_reg, \
2992 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2994 emit_insn (gen_rtx_SET (VOIDmode, \
2996 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
2998 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3003 if (TARGET_DEBUG_B_MODE) \
3004 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3008 /* A C statement or compound statement with a conditional `goto
3009 LABEL;' executed if memory address X (an RTX) can have different
3010 meanings depending on the machine mode of the memory reference it
3013 Autoincrement and autodecrement addresses typically have
3014 mode-dependent effects because the amount of the increment or
3015 decrement is the size of the operand being addressed. Some
3016 machines have other mode-dependent addresses. Many RISC machines
3017 have no mode-dependent addresses.
3019 You may assume that ADDR is a valid address for the machine. */
3021 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3024 /* Define this macro if references to a symbol must be treated
3025 differently depending on something about the variable or
3026 function named by the symbol (such as what section it is in).
3028 The macro definition, if any, is executed immediately after the
3029 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3030 The value of the rtl will be a `mem' whose address is a
3033 The usual thing for this macro to do is to a flag in the
3034 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3035 name string in the `symbol_ref' (if one bit is not enough
3038 The best way to modify the name string is by adding text to the
3039 beginning, with suitable punctuation to prevent any ambiguity.
3040 Allocate the new name in `saveable_obstack'. You will have to
3041 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3042 and output the name accordingly.
3044 You can also check the information stored in the `symbol_ref' in
3045 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3046 `PRINT_OPERAND_ADDRESS'.
3048 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3051 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3052 symbols which are not in the .text section.
3054 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3055 constants which are put in the .text section. We also record the
3056 total length of all such strings; this total is used to decide
3057 whether we need to split the constant table, and need not be
3060 When not mips16 code nor embedded PIC, if a symbol is in a
3061 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3062 splitting the reference so that gas can generate a gp relative
3065 When TARGET_EMBEDDED_DATA is set, we assume that all const
3066 variables will be stored in ROM, which is too far from %gp to use
3067 %gprel addressing. Note that (1) we include "extern const"
3068 variables in this, which mips_select_section doesn't, and (2) we
3069 can't always tell if they're really const (they might be const C++
3070 objects with non-const constructors), so we err on the side of
3071 caution and won't use %gprel anyway (otherwise we'd have to defer
3072 this decision to the linker/loader). The handling of extern consts
3073 is why the DECL_INITIAL macros differ from mips_select_section.
3075 If you are changing this macro, you should look at
3076 mips_select_section and see if it needs a similar change. */
3078 #ifndef UNIQUE_SECTION_P
3079 #define UNIQUE_SECTION_P(DECL) (0)
3082 #define ENCODE_SECTION_INFO(DECL) \
3085 if (TARGET_MIPS16) \
3087 if (TREE_CODE (DECL) == STRING_CST \
3088 && ! flag_writable_strings \
3089 /* If this string is from a function, and the function will \
3090 go in a gnu linkonce section, then we can't directly \
3091 access the string. This gets an assembler error \
3092 "unsupported PC relative reference to different section".\
3093 If we modify SELECT_SECTION to put it in function_section\
3094 instead of text_section, it still fails because \
3095 DECL_SECTION_NAME isn't set until assemble_start_function.\
3096 If we fix that, it still fails because strings are shared\
3097 among multiple functions, and we have cross section \
3098 references again. We force it to work by putting string \
3099 addresses in the constant pool and indirecting. */ \
3100 && (! current_function_decl \
3101 || ! UNIQUE_SECTION_P (current_function_decl))) \
3103 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3104 mips_string_length += TREE_STRING_LENGTH (DECL); \
3108 if (TARGET_EMBEDDED_DATA \
3109 && (TREE_CODE (DECL) == VAR_DECL \
3110 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3111 && (!DECL_INITIAL (DECL) \
3112 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3114 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3117 else if (TARGET_EMBEDDED_PIC) \
3119 if (TREE_CODE (DECL) == VAR_DECL) \
3120 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3121 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3122 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3123 else if (TREE_CODE (DECL) == STRING_CST \
3124 && ! flag_writable_strings) \
3125 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3127 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3130 else if (TREE_CODE (DECL) == VAR_DECL \
3131 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3132 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3134 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3137 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3140 /* We can not perform GP optimizations on variables which are in \
3141 specific sections, except for .sdata and .sbss which are \
3143 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3144 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3146 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3148 if (size > 0 && size <= mips_section_threshold) \
3149 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3152 else if (HALF_PIC_P ()) \
3154 HALF_PIC_ENCODE (DECL); \
3159 /* The mips16 wants the constant pool to be after the function,
3160 because the PC relative load instructions use unsigned offsets. */
3162 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3164 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3165 mips_string_length = 0;
3168 /* In mips16 mode, put most string constants after the function. */
3169 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3170 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3173 /* Specify the machine mode that this machine uses
3174 for the index in the tablejump instruction.
3175 ??? Using HImode in mips16 mode can cause overflow. However, the
3176 overflow is no more likely than the overflow in a branch
3177 instruction. Large functions can currently break in both ways. */
3178 #define CASE_VECTOR_MODE \
3179 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3181 /* Define as C expression which evaluates to nonzero if the tablejump
3182 instruction expects the table to contain offsets from the address of the
3184 Do not define this if the table should contain absolute addresses. */
3185 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3187 /* Specify the tree operation to be used to convert reals to integers. */
3188 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3190 /* This is the kind of divide that is easiest to do in the general case. */
3191 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3193 /* Define this as 1 if `char' should by default be signed; else as 0. */
3194 #ifndef DEFAULT_SIGNED_CHAR
3195 #define DEFAULT_SIGNED_CHAR 1
3198 /* Max number of bytes we can move from memory to memory
3199 in one reasonably fast instruction. */
3200 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3201 #define MAX_MOVE_MAX 8
3203 /* Define this macro as a C expression which is nonzero if
3204 accessing less than a word of memory (i.e. a `char' or a
3205 `short') is no faster than accessing a word of memory, i.e., if
3206 such access require more than one instruction or if there is no
3207 difference in cost between byte and (aligned) word loads.
3209 On RISC machines, it tends to generate better code to define
3210 this as 1, since it avoids making a QI or HI mode register. */
3211 #define SLOW_BYTE_ACCESS 1
3213 /* We assume that the store-condition-codes instructions store 0 for false
3214 and some other value for true. This is the value stored for true. */
3216 #define STORE_FLAG_VALUE 1
3218 /* Define this if zero-extension is slow (more than one real instruction). */
3219 #define SLOW_ZERO_EXTEND
3221 /* Define this to be nonzero if shift instructions ignore all but the low-order
3223 #define SHIFT_COUNT_TRUNCATED 1
3225 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3226 is done just by pretending it is already truncated. */
3227 /* In 64 bit mode, 32 bit instructions require that register values be properly
3228 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3229 converts a value >32 bits to a value <32 bits. */
3230 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3231 Something needs to be done about this. Perhaps not use any 32 bit
3232 instructions? Perhaps use PROMOTE_MODE? */
3233 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3234 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3236 /* Specify the machine mode that pointers have.
3237 After generation of rtl, the compiler makes no further distinction
3238 between pointers and any other objects of this machine mode.
3240 For MIPS we make pointers are the smaller of longs and gp-registers. */
3243 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3246 /* A function address in a call instruction
3247 is a word address (for indexing purposes)
3248 so give the MEM rtx a words's mode. */
3250 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3252 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3253 memset, instead of the BSD functions bcopy and bzero. */
3255 #if defined(MIPS_SYSV) || defined(OSF_OS)
3256 #define TARGET_MEM_FUNCTIONS
3260 /* A part of a C `switch' statement that describes the relative
3261 costs of constant RTL expressions. It must contain `case'
3262 labels for expression codes `const_int', `const', `symbol_ref',
3263 `label_ref' and `const_double'. Each case must ultimately reach
3264 a `return' statement to return the relative cost of the use of
3265 that kind of constant value in an expression. The cost may
3266 depend on the precise value of the constant, which is available
3267 for examination in X.
3269 CODE is the expression code--redundant, since it can be obtained
3270 with `GET_CODE (X)'. */
3272 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3274 if (! TARGET_MIPS16) \
3276 /* Always return 0, since we don't have different sized \
3277 instructions, hence different costs according to Richard \
3281 if ((OUTER_CODE) == SET) \
3283 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3285 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3286 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3287 return COSTS_N_INSNS (1); \
3289 return COSTS_N_INSNS (2); \
3291 /* A PLUS could be an address. We don't want to force an address \
3292 to use a register, so accept any signed 16 bit value without \
3294 if ((OUTER_CODE) == PLUS \
3295 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3297 /* A number between 1 and 8 inclusive is efficient for a shift. \
3298 Otherwise, we will need an extended instruction. */ \
3299 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3300 || (OUTER_CODE) == LSHIFTRT) \
3302 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3304 return COSTS_N_INSNS (1); \
3306 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3307 if ((OUTER_CODE) == XOR \
3308 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3310 /* We may be able to use slt or sltu for a comparison with a \
3311 signed 16 bit value. (The boundary conditions aren't quite \
3312 right, but this is just a heuristic anyhow.) */ \
3313 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3314 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3315 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3316 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3317 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3319 /* Equality comparisons with 0 are cheap. */ \
3320 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3321 && INTVAL (X) == 0) \
3324 /* Otherwise, work out the cost to load the value into a \
3326 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3327 return COSTS_N_INSNS (1); \
3328 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3329 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3330 return COSTS_N_INSNS (2); \
3332 return COSTS_N_INSNS (3); \
3335 return COSTS_N_INSNS (2); \
3339 rtx offset = const0_rtx; \
3340 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3342 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3344 /* Treat this like a signed 16 bit CONST_INT. */ \
3345 if ((OUTER_CODE) == PLUS) \
3347 else if ((OUTER_CODE) == SET) \
3348 return COSTS_N_INSNS (1); \
3350 return COSTS_N_INSNS (2); \
3353 if (GET_CODE (symref) == LABEL_REF) \
3354 return COSTS_N_INSNS (2); \
3356 if (GET_CODE (symref) != SYMBOL_REF) \
3357 return COSTS_N_INSNS (4); \
3359 /* let's be paranoid.... */ \
3360 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3361 return COSTS_N_INSNS (2); \
3363 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3367 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3369 case CONST_DOUBLE: \
3372 if (TARGET_MIPS16) \
3373 return COSTS_N_INSNS (4); \
3374 split_double (X, &high, &low); \
3375 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3376 || low == CONST0_RTX (GET_MODE (low))) \
3380 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3381 This can be used, for example, to indicate how costly a multiply
3382 instruction is. In writing this macro, you can use the construct
3383 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3385 This macro is optional; do not define it if the default cost
3386 assumptions are adequate for the target machine.
3388 If -mdebugd is used, change the multiply cost to 2, so multiply by
3389 a constant isn't converted to a series of shifts. This helps
3390 strength reduction, and also makes it easier to identify what the
3391 compiler is doing. */
3393 /* ??? Fix this to be right for the R8000. */
3394 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3397 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3398 if (simple_memory_operand (X, GET_MODE (X))) \
3399 return COSTS_N_INSNS (num_words); \
3401 return COSTS_N_INSNS (2*num_words); \
3405 return COSTS_N_INSNS (6); \
3408 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3413 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3414 return COSTS_N_INSNS (2); \
3421 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3422 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3428 enum machine_mode xmode = GET_MODE (X); \
3429 if (xmode == SFmode || xmode == DFmode) \
3430 return COSTS_N_INSNS (1); \
3432 return COSTS_N_INSNS (4); \
3438 enum machine_mode xmode = GET_MODE (X); \
3439 if (xmode == SFmode || xmode == DFmode) \
3441 if (mips_cpu == PROCESSOR_R3000 \
3442 || mips_cpu == PROCESSOR_R3900) \
3443 return COSTS_N_INSNS (2); \
3444 else if (mips_cpu == PROCESSOR_R6000) \
3445 return COSTS_N_INSNS (3); \
3447 return COSTS_N_INSNS (6); \
3450 if (xmode == DImode && !TARGET_64BIT) \
3451 return COSTS_N_INSNS (4); \
3457 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3464 enum machine_mode xmode = GET_MODE (X); \
3465 if (xmode == SFmode) \
3467 if (mips_cpu == PROCESSOR_R3000 \
3468 || mips_cpu == PROCESSOR_R3900 \
3469 || mips_cpu == PROCESSOR_R5000) \
3470 return COSTS_N_INSNS (4); \
3471 else if (mips_cpu == PROCESSOR_R6000) \
3472 return COSTS_N_INSNS (5); \
3474 return COSTS_N_INSNS (7); \
3477 if (xmode == DFmode) \
3479 if (mips_cpu == PROCESSOR_R3000 \
3480 || mips_cpu == PROCESSOR_R3900 \
3481 || mips_cpu == PROCESSOR_R5000) \
3482 return COSTS_N_INSNS (5); \
3483 else if (mips_cpu == PROCESSOR_R6000) \
3484 return COSTS_N_INSNS (6); \
3486 return COSTS_N_INSNS (8); \
3489 if (mips_cpu == PROCESSOR_R3000) \
3490 return COSTS_N_INSNS (12); \
3491 else if (mips_cpu == PROCESSOR_R3900) \
3492 return COSTS_N_INSNS (2); \
3493 else if (mips_cpu == PROCESSOR_R6000) \
3494 return COSTS_N_INSNS (17); \
3495 else if (mips_cpu == PROCESSOR_R5000) \
3496 return COSTS_N_INSNS (5); \
3498 return COSTS_N_INSNS (10); \
3504 enum machine_mode xmode = GET_MODE (X); \
3505 if (xmode == SFmode) \
3507 if (mips_cpu == PROCESSOR_R3000 \
3508 || mips_cpu == PROCESSOR_R3900) \
3509 return COSTS_N_INSNS (12); \
3510 else if (mips_cpu == PROCESSOR_R6000) \
3511 return COSTS_N_INSNS (15); \
3513 return COSTS_N_INSNS (23); \
3516 if (xmode == DFmode) \
3518 if (mips_cpu == PROCESSOR_R3000 \
3519 || mips_cpu == PROCESSOR_R3900) \
3520 return COSTS_N_INSNS (19); \
3521 else if (mips_cpu == PROCESSOR_R6000) \
3522 return COSTS_N_INSNS (16); \
3524 return COSTS_N_INSNS (36); \
3527 /* fall through */ \
3531 if (mips_cpu == PROCESSOR_R3000 \
3532 || mips_cpu == PROCESSOR_R3900) \
3533 return COSTS_N_INSNS (35); \
3534 else if (mips_cpu == PROCESSOR_R6000) \
3535 return COSTS_N_INSNS (38); \
3536 else if (mips_cpu == PROCESSOR_R5000) \
3537 return COSTS_N_INSNS (36); \
3539 return COSTS_N_INSNS (69); \
3542 /* A sign extend from SImode to DImode in 64 bit mode is often \
3543 zero instructions, because the result can often be used \
3544 directly by another instruction; we'll call it one. */ \
3545 if (TARGET_64BIT && GET_MODE (X) == DImode \
3546 && GET_MODE (XEXP (X, 0)) == SImode) \
3547 return COSTS_N_INSNS (1); \
3549 return COSTS_N_INSNS (2); \
3552 if (TARGET_64BIT && GET_MODE (X) == DImode \
3553 && GET_MODE (XEXP (X, 0)) == SImode) \
3554 return COSTS_N_INSNS (2); \
3556 return COSTS_N_INSNS (1);
3558 /* An expression giving the cost of an addressing mode that
3559 contains ADDRESS. If not defined, the cost is computed from the
3560 form of the ADDRESS expression and the `CONST_COSTS' values.
3562 For most CISC machines, the default cost is a good approximation
3563 of the true cost of the addressing mode. However, on RISC
3564 machines, all instructions normally have the same length and
3565 execution time. Hence all addresses will have equal costs.
3567 In cases where more than one form of an address is known, the
3568 form with the lowest cost will be used. If multiple forms have
3569 the same, lowest, cost, the one that is the most complex will be
3572 For example, suppose an address that is equal to the sum of a
3573 register and a constant is used twice in the same basic block.
3574 When this macro is not defined, the address will be computed in
3575 a register and memory references will be indirect through that
3576 register. On machines where the cost of the addressing mode
3577 containing the sum is no higher than that of a simple indirect
3578 reference, this will produce an additional instruction and
3579 possibly require an additional register. Proper specification
3580 of this macro eliminates this overhead for such machines.
3582 Similar use of this macro is made in strength reduction of loops.
3584 ADDRESS need not be valid as an address. In such a case, the
3585 cost is not relevant and can be any value; invalid addresses
3586 need not be assigned a different cost.
3588 On machines where an address involving more than one register is
3589 as cheap as an address computation involving only one register,
3590 defining `ADDRESS_COST' to reflect this can cause two registers
3591 to be live over a region of code where only one would have been
3592 if `ADDRESS_COST' were not defined in that manner. This effect
3593 should be considered in the definition of this macro.
3594 Equivalent costs should probably only be given to addresses with
3595 different numbers of registers on machines with lots of registers.
3597 This macro will normally either not be defined or be defined as
3600 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3602 /* A C expression for the cost of moving data from a register in
3603 class FROM to one in class TO. The classes are expressed using
3604 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3605 the default; other values are interpreted relative to that.
3607 It is not required that the cost always equal 2 when FROM is the
3608 same as TO; on some machines it is expensive to move between
3609 registers if they are not general registers.
3611 If reload sees an insn consisting of a single `set' between two
3612 hard registers, and if `REGISTER_MOVE_COST' applied to their
3613 classes returns a value of 2, reload does not check to ensure
3614 that the constraints of the insn are met. Setting a cost of
3615 other than 2 will allow reload to verify that the constraints are
3616 met. You should do this if the `movM' pattern's constraints do
3617 not allow such copying.
3619 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3620 registers the same as for one of moving general registers to
3621 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3622 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3623 isn't clear if it is wise. And it might not work in all cases. We
3624 could solve the DImode LO reg problem by using a multiply, just like
3625 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3626 by using divide instructions. divu puts the remainder in the HI
3627 reg, so doing a divide by -1 will move the value in the HI reg for
3628 all values except -1. We could handle that case by using a signed
3629 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3630 compare/branch to test the input value to see which instruction we
3631 need to use. This gets pretty messy, but it is feasible. */
3633 #define REGISTER_MOVE_COST(FROM, TO) \
3634 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3635 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3636 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3637 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3638 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3639 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3640 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3641 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3642 : (((FROM) == HI_REG || (FROM) == LO_REG \
3643 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3644 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3645 : (((FROM) == HI_REG || (FROM) == LO_REG \
3646 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3647 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3648 : (((TO) == HI_REG || (TO) == LO_REG \
3649 || (TO) == MD_REGS || (TO) == HILO_REG) \
3650 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3651 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3652 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3655 /* ??? Fix this to be right for the R8000. */
3656 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3657 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3658 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3660 /* Define if copies to/from condition code registers should be avoided.
3662 This is needed for the MIPS because reload_outcc is not complete;
3663 it needs to handle cases where the source is a general or another
3664 condition code register. */
3665 #define AVOID_CCMODE_COPIES
3667 /* A C expression for the cost of a branch instruction. A value of
3668 1 is the default; other values are interpreted relative to that. */
3670 /* ??? Fix this to be right for the R8000. */
3671 #define BRANCH_COST \
3673 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3676 /* A C statement (sans semicolon) to update the integer variable COST
3677 based on the relationship between INSN that is dependent on
3678 DEP_INSN through the dependence LINK. The default is to make no
3679 adjustment to COST. On the MIPS, ignore the cost of anti- and
3680 output-dependencies. */
3682 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3683 if (REG_NOTE_KIND (LINK) != 0) \
3684 (COST) = 0; /* Anti or output dependence. */
3686 /* If defined, modifies the length assigned to instruction INSN as a
3687 function of the context in which it is used. LENGTH is an lvalue
3688 that contains the initially computed length of the insn and should
3689 be updated with the correct length of the insn. */
3690 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3691 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3694 /* Optionally define this if you have added predicates to
3695 `MACHINE.c'. This macro is called within an initializer of an
3696 array of structures. The first field in the structure is the
3697 name of a predicate and the second field is an array of rtl
3698 codes. For each predicate, list all rtl codes that can be in
3699 expressions matched by the predicate. The list should have a
3700 trailing comma. Here is an example of two entries in the list
3701 for a typical RISC machine:
3703 #define PREDICATE_CODES \
3704 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3705 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3707 Defining this macro does not affect the generated code (however,
3708 incorrect definitions that omit an rtl code that may be matched
3709 by the predicate can cause the compiler to malfunction).
3710 Instead, it allows the table built by `genrecog' to be more
3711 compact and efficient, thus speeding up the compiler. The most
3712 important predicates to include in the list specified by this
3713 macro are thoses used in the most insn patterns. */
3715 #define PREDICATE_CODES \
3716 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3717 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3718 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3719 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3720 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3721 {"small_int", { CONST_INT }}, \
3722 {"large_int", { CONST_INT }}, \
3723 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3724 {"const_float_1_operand", { CONST_DOUBLE }}, \
3725 {"simple_memory_operand", { MEM, SUBREG }}, \
3726 {"equality_op", { EQ, NE }}, \
3727 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3729 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3730 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3731 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3732 SYMBOL_REF, LABEL_REF, SUBREG, \
3734 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3735 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3736 MEM, SIGN_EXTEND }}, \
3737 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3738 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3740 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3742 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3744 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3745 SYMBOL_REF, LABEL_REF, SUBREG, \
3746 REG, SIGN_EXTEND }}, \
3747 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3748 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3749 CONST_DOUBLE, CONST }}, \
3750 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3751 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3755 /* If defined, a C statement to be executed just prior to the
3756 output of assembler code for INSN, to modify the extracted
3757 operands so they will be output differently.
3759 Here the argument OPVEC is the vector containing the operands
3760 extracted from INSN, and NOPERANDS is the number of elements of
3761 the vector which contain meaningful data for this insn. The
3762 contents of this vector are what will be used to convert the
3763 insn template into assembler code, so you can change the
3764 assembler output by changing the contents of the vector.
3766 We use it to check if the current insn needs a nop in front of it
3767 because of load delays, and also to update the delay slot
3770 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3771 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3774 /* Control the assembler format that we output. */
3776 /* Output at beginning of assembler file.
3777 If we are optimizing to use the global pointer, create a temporary
3778 file to hold all of the text stuff, and write it out to the end.
3779 This is needed because the MIPS assembler is evidently one pass,
3780 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3781 declaration when the code is processed, it generates a two
3782 instruction sequence. */
3784 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3786 /* Output to assembler file text saying following lines
3787 may contain character constants, extra white space, comments, etc. */
3789 #define ASM_APP_ON " #APP\n"
3791 /* Output to assembler file text saying following lines
3792 no longer contain unusual constructs. */
3794 #define ASM_APP_OFF " #NO_APP\n"
3796 /* How to refer to registers in assembler output.
3797 This sequence is indexed by compiler's hard-register-number (see above).
3799 In order to support the two different conventions for register names,
3800 we use the name of a table set up in mips.c, which is overwritten
3801 if -mrnames is used. */
3803 #define REGISTER_NAMES \
3805 &mips_reg_names[ 0][0], \
3806 &mips_reg_names[ 1][0], \
3807 &mips_reg_names[ 2][0], \
3808 &mips_reg_names[ 3][0], \
3809 &mips_reg_names[ 4][0], \
3810 &mips_reg_names[ 5][0], \
3811 &mips_reg_names[ 6][0], \
3812 &mips_reg_names[ 7][0], \
3813 &mips_reg_names[ 8][0], \
3814 &mips_reg_names[ 9][0], \
3815 &mips_reg_names[10][0], \
3816 &mips_reg_names[11][0], \
3817 &mips_reg_names[12][0], \
3818 &mips_reg_names[13][0], \
3819 &mips_reg_names[14][0], \
3820 &mips_reg_names[15][0], \
3821 &mips_reg_names[16][0], \
3822 &mips_reg_names[17][0], \
3823 &mips_reg_names[18][0], \
3824 &mips_reg_names[19][0], \
3825 &mips_reg_names[20][0], \
3826 &mips_reg_names[21][0], \
3827 &mips_reg_names[22][0], \
3828 &mips_reg_names[23][0], \
3829 &mips_reg_names[24][0], \
3830 &mips_reg_names[25][0], \
3831 &mips_reg_names[26][0], \
3832 &mips_reg_names[27][0], \
3833 &mips_reg_names[28][0], \
3834 &mips_reg_names[29][0], \
3835 &mips_reg_names[30][0], \
3836 &mips_reg_names[31][0], \
3837 &mips_reg_names[32][0], \
3838 &mips_reg_names[33][0], \
3839 &mips_reg_names[34][0], \
3840 &mips_reg_names[35][0], \
3841 &mips_reg_names[36][0], \
3842 &mips_reg_names[37][0], \
3843 &mips_reg_names[38][0], \
3844 &mips_reg_names[39][0], \
3845 &mips_reg_names[40][0], \
3846 &mips_reg_names[41][0], \
3847 &mips_reg_names[42][0], \
3848 &mips_reg_names[43][0], \
3849 &mips_reg_names[44][0], \
3850 &mips_reg_names[45][0], \
3851 &mips_reg_names[46][0], \
3852 &mips_reg_names[47][0], \
3853 &mips_reg_names[48][0], \
3854 &mips_reg_names[49][0], \
3855 &mips_reg_names[50][0], \
3856 &mips_reg_names[51][0], \
3857 &mips_reg_names[52][0], \
3858 &mips_reg_names[53][0], \
3859 &mips_reg_names[54][0], \
3860 &mips_reg_names[55][0], \
3861 &mips_reg_names[56][0], \
3862 &mips_reg_names[57][0], \
3863 &mips_reg_names[58][0], \
3864 &mips_reg_names[59][0], \
3865 &mips_reg_names[60][0], \
3866 &mips_reg_names[61][0], \
3867 &mips_reg_names[62][0], \
3868 &mips_reg_names[63][0], \
3869 &mips_reg_names[64][0], \
3870 &mips_reg_names[65][0], \
3871 &mips_reg_names[66][0], \
3872 &mips_reg_names[67][0], \
3873 &mips_reg_names[68][0], \
3874 &mips_reg_names[69][0], \
3875 &mips_reg_names[70][0], \
3876 &mips_reg_names[71][0], \
3877 &mips_reg_names[72][0], \
3878 &mips_reg_names[73][0], \
3879 &mips_reg_names[74][0], \
3880 &mips_reg_names[75][0], \
3883 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3884 So define this for it. */
3885 #define DEBUG_REGISTER_NAMES \
3887 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3888 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3889 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3890 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3891 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3892 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3893 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3894 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3895 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3896 "$fcc5","$fcc6","$fcc7","$rap" \
3899 /* If defined, a C initializer for an array of structures
3900 containing a name and a register number. This macro defines
3901 additional names for hard registers, thus allowing the `asm'
3902 option in declarations to refer to registers using alternate
3905 We define both names for the integer registers here. */
3907 #define ADDITIONAL_REGISTER_NAMES \
3909 { "$0", 0 + GP_REG_FIRST }, \
3910 { "$1", 1 + GP_REG_FIRST }, \
3911 { "$2", 2 + GP_REG_FIRST }, \
3912 { "$3", 3 + GP_REG_FIRST }, \
3913 { "$4", 4 + GP_REG_FIRST }, \
3914 { "$5", 5 + GP_REG_FIRST }, \
3915 { "$6", 6 + GP_REG_FIRST }, \
3916 { "$7", 7 + GP_REG_FIRST }, \
3917 { "$8", 8 + GP_REG_FIRST }, \
3918 { "$9", 9 + GP_REG_FIRST }, \
3919 { "$10", 10 + GP_REG_FIRST }, \
3920 { "$11", 11 + GP_REG_FIRST }, \
3921 { "$12", 12 + GP_REG_FIRST }, \
3922 { "$13", 13 + GP_REG_FIRST }, \
3923 { "$14", 14 + GP_REG_FIRST }, \
3924 { "$15", 15 + GP_REG_FIRST }, \
3925 { "$16", 16 + GP_REG_FIRST }, \
3926 { "$17", 17 + GP_REG_FIRST }, \
3927 { "$18", 18 + GP_REG_FIRST }, \
3928 { "$19", 19 + GP_REG_FIRST }, \
3929 { "$20", 20 + GP_REG_FIRST }, \
3930 { "$21", 21 + GP_REG_FIRST }, \
3931 { "$22", 22 + GP_REG_FIRST }, \
3932 { "$23", 23 + GP_REG_FIRST }, \
3933 { "$24", 24 + GP_REG_FIRST }, \
3934 { "$25", 25 + GP_REG_FIRST }, \
3935 { "$26", 26 + GP_REG_FIRST }, \
3936 { "$27", 27 + GP_REG_FIRST }, \
3937 { "$28", 28 + GP_REG_FIRST }, \
3938 { "$29", 29 + GP_REG_FIRST }, \
3939 { "$30", 30 + GP_REG_FIRST }, \
3940 { "$31", 31 + GP_REG_FIRST }, \
3941 { "$sp", 29 + GP_REG_FIRST }, \
3942 { "$fp", 30 + GP_REG_FIRST }, \
3943 { "at", 1 + GP_REG_FIRST }, \
3944 { "v0", 2 + GP_REG_FIRST }, \
3945 { "v1", 3 + GP_REG_FIRST }, \
3946 { "a0", 4 + GP_REG_FIRST }, \
3947 { "a1", 5 + GP_REG_FIRST }, \
3948 { "a2", 6 + GP_REG_FIRST }, \
3949 { "a3", 7 + GP_REG_FIRST }, \
3950 { "t0", 8 + GP_REG_FIRST }, \
3951 { "t1", 9 + GP_REG_FIRST }, \
3952 { "t2", 10 + GP_REG_FIRST }, \
3953 { "t3", 11 + GP_REG_FIRST }, \
3954 { "t4", 12 + GP_REG_FIRST }, \
3955 { "t5", 13 + GP_REG_FIRST }, \
3956 { "t6", 14 + GP_REG_FIRST }, \
3957 { "t7", 15 + GP_REG_FIRST }, \
3958 { "s0", 16 + GP_REG_FIRST }, \
3959 { "s1", 17 + GP_REG_FIRST }, \
3960 { "s2", 18 + GP_REG_FIRST }, \
3961 { "s3", 19 + GP_REG_FIRST }, \
3962 { "s4", 20 + GP_REG_FIRST }, \
3963 { "s5", 21 + GP_REG_FIRST }, \
3964 { "s6", 22 + GP_REG_FIRST }, \
3965 { "s7", 23 + GP_REG_FIRST }, \
3966 { "t8", 24 + GP_REG_FIRST }, \
3967 { "t9", 25 + GP_REG_FIRST }, \
3968 { "k0", 26 + GP_REG_FIRST }, \
3969 { "k1", 27 + GP_REG_FIRST }, \
3970 { "gp", 28 + GP_REG_FIRST }, \
3971 { "sp", 29 + GP_REG_FIRST }, \
3972 { "fp", 30 + GP_REG_FIRST }, \
3973 { "ra", 31 + GP_REG_FIRST }, \
3974 { "$sp", 29 + GP_REG_FIRST }, \
3975 { "$fp", 30 + GP_REG_FIRST } \
3978 /* Define results of standard character escape sequences. */
3979 #define TARGET_BELL 007
3980 #define TARGET_BS 010
3981 #define TARGET_TAB 011
3982 #define TARGET_NEWLINE 012
3983 #define TARGET_VT 013
3984 #define TARGET_FF 014
3985 #define TARGET_CR 015
3987 /* A C compound statement to output to stdio stream STREAM the
3988 assembler syntax for an instruction operand X. X is an RTL
3991 CODE is a value that can be used to specify one of several ways
3992 of printing the operand. It is used when identical operands
3993 must be printed differently depending on the context. CODE
3994 comes from the `%' specification that was used to request
3995 printing of the operand. If the specification was just `%DIGIT'
3996 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3997 is the ASCII code for LTR.
3999 If X is a register, this macro should print the register's name.
4000 The names can be found in an array `reg_names' whose type is
4001 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4003 When the machine description has a specification `%PUNCT' (a `%'
4004 followed by a punctuation character), this macro is called with
4005 a null pointer for X and the punctuation character for CODE.
4007 See mips.c for the MIPS specific codes. */
4009 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4011 /* A C expression which evaluates to true if CODE is a valid
4012 punctuation character for use in the `PRINT_OPERAND' macro. If
4013 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4014 punctuation characters (except for the standard one, `%') are
4015 used in this way. */
4017 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4019 /* A C compound statement to output to stdio stream STREAM the
4020 assembler syntax for an instruction operand that is a memory
4021 reference whose address is ADDR. ADDR is an RTL expression.
4023 On some machines, the syntax for a symbolic address depends on
4024 the section that the address refers to. On these machines,
4025 define the macro `ENCODE_SECTION_INFO' to store the information
4026 into the `symbol_ref', and then check for it here. */
4028 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4031 /* A C statement, to be executed after all slot-filler instructions
4032 have been output. If necessary, call `dbr_sequence_length' to
4033 determine the number of slots filled in a sequence (zero if not
4034 currently outputting a sequence), to decide how many no-ops to
4035 output, or whatever.
4037 Don't define this macro if it has nothing to do, but it is
4038 helpful in reading assembly output if the extent of the delay
4039 sequence is made explicit (e.g. with white space).
4041 Note that output routines for instructions with delay slots must
4042 be prepared to deal with not being output as part of a sequence
4043 (i.e. when the scheduling pass is not run, or when no slot
4044 fillers could be found.) The variable `final_sequence' is null
4045 when not processing a sequence, otherwise it contains the
4046 `sequence' rtx being output. */
4048 #define DBR_OUTPUT_SEQEND(STREAM) \
4051 if (set_nomacro > 0 && --set_nomacro == 0) \
4052 fputs ("\t.set\tmacro\n", STREAM); \
4054 if (set_noreorder > 0 && --set_noreorder == 0) \
4055 fputs ("\t.set\treorder\n", STREAM); \
4057 dslots_jump_filled++; \
4058 fputs ("\n", STREAM); \
4063 /* How to tell the debugger about changes of source files. Note, the
4064 mips ECOFF format cannot deal with changes of files inside of
4065 functions, which means the output of parser generators like bison
4066 is generally not debuggable without using the -l switch. Lose,
4067 lose, lose. Silicon graphics seems to want all .file's hardwired
4070 #ifndef SET_FILE_NUMBER
4071 #define SET_FILE_NUMBER() ++num_source_filenames
4074 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4075 mips_output_filename (STREAM, NAME)
4077 /* This is defined so that it can be overridden in iris6.h. */
4078 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4081 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4082 output_quoted_string (STREAM, NAME); \
4083 fputs ("\n", STREAM); \
4087 /* This is how to output a note the debugger telling it the line number
4088 to which the following sequence of instructions corresponds.
4089 Silicon graphics puts a label after each .loc. */
4091 #ifndef LABEL_AFTER_LOC
4092 #define LABEL_AFTER_LOC(STREAM)
4095 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4096 mips_output_lineno (STREAM, LINE)
4098 /* The MIPS implementation uses some labels for its own purpose. The
4099 following lists what labels are created, and are all formed by the
4100 pattern $L[a-z].*. The machine independent portion of GCC creates
4101 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4103 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4104 $Lb[0-9]+ Begin blocks for MIPS debug support
4105 $Lc[0-9]+ Label for use in s<xx> operation.
4106 $Le[0-9]+ End blocks for MIPS debug support
4107 $Lp\..+ Half-pic labels. */
4109 /* This is how to output the definition of a user-level label named NAME,
4110 such as the label on a static function or variable NAME.
4112 If we are optimizing the gp, remember that this label has been put
4113 out, so we know not to emit an .extern for it in mips_asm_file_end.
4114 We use one of the common bits in the IDENTIFIER tree node for this,
4115 since those bits seem to be unused, and we don't have any method
4116 of getting the decl nodes from the name. */
4118 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4120 assemble_name (STREAM, NAME); \
4121 fputs (":\n", STREAM); \
4125 /* A C statement (sans semicolon) to output to the stdio stream
4126 STREAM any text necessary for declaring the name NAME of an
4127 initialized variable which is being defined. This macro must
4128 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4129 The argument DECL is the `VAR_DECL' tree node representing the
4132 If this macro is not defined, then the variable name is defined
4133 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4135 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4138 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4139 HALF_PIC_DECLARE (NAME); \
4144 /* This is how to output a command to make the user-level label named NAME
4145 defined for reference from other files. */
4147 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4149 fputs ("\t.globl\t", STREAM); \
4150 assemble_name (STREAM, NAME); \
4151 fputs ("\n", STREAM); \
4154 /* This says how to define a global common symbol. */
4156 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
4157 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
4159 /* This says how to define a local common symbol (ie, not visible to
4162 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4163 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4166 /* This says how to output an external. It would be possible not to
4167 output anything and let undefined symbol become external. However
4168 the assembler uses length information on externals to allocate in
4169 data/sdata bss/sbss, thereby saving exec time. */
4171 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4172 mips_output_external(STREAM,DECL,NAME)
4174 /* This says what to print at the end of the assembly file */
4175 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4178 /* This is how to declare a function name. The actual work of
4179 emitting the label is moved to function_prologue, so that we can
4180 get the line number correctly emitted before the .ent directive,
4181 and after any .file directives.
4183 Also, switch files if we are optimizing the global pointer. */
4185 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4187 extern FILE *asm_out_text_file; \
4188 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4190 STREAM = asm_out_text_file; \
4191 /* ??? text_section gets called too soon. If the previous \
4192 function is in a special section and we're not, we have \
4193 to switch back to the text section. We can't call \
4194 text_section again as gcc thinks we're already there. */ \
4195 /* ??? See varasm.c. There are other things that get output \
4196 too early, like alignment (before we've switched STREAM). */ \
4197 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4198 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4201 HALF_PIC_DECLARE (NAME); \
4204 /* This is how to output an internal numbered label where
4205 PREFIX is the class of label and NUM is the number within the class. */
4207 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4208 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4210 /* This is how to store into the string LABEL
4211 the symbol_ref name of an internal numbered label where
4212 PREFIX is the class of label and NUM is the number within the class.
4213 This is suitable for output with `assemble_name'. */
4215 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4216 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4218 /* This is how to output an assembler line defining a `double' constant. */
4220 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4221 mips_output_double (STREAM, VALUE)
4224 /* This is how to output an assembler line defining a `float' constant. */
4226 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4227 mips_output_float (STREAM, VALUE)
4230 /* This is how to output an assembler line defining an `int' constant. */
4232 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4234 fprintf (STREAM, "\t.word\t"); \
4235 output_addr_const (STREAM, (VALUE)); \
4236 fprintf (STREAM, "\n"); \
4239 /* Likewise for 64 bit, `char' and `short' constants.
4241 FIXME: operand_subword can't handle some complex constant expressions
4242 that output_addr_const can (for example it does not call
4243 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4244 rely on that to avoid operand_subword for most of the cases where this
4245 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4246 or the same case with the type of 'i' changed to long long.
4250 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4252 if (TARGET_64BIT || TARGET_GAS) \
4254 fprintf (STREAM, "\t.dword\t"); \
4255 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4256 /* We can't use 'X' for negative numbers, because then we won't \
4257 get the right value for the upper 32 bits. */ \
4258 output_addr_const (STREAM, VALUE); \
4260 /* We must use 'X', because otherwise LONG_MIN will print as \
4261 a number that the Irix 6 assembler won't accept. */ \
4262 print_operand (STREAM, VALUE, 'X'); \
4263 fprintf (STREAM, "\n"); \
4267 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4268 UNITS_PER_WORD, 1); \
4269 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4270 UNITS_PER_WORD, 1); \
4274 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4276 fprintf (STREAM, "\t.half\t"); \
4277 output_addr_const (STREAM, (VALUE)); \
4278 fprintf (STREAM, "\n"); \
4281 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4283 fprintf (STREAM, "\t.byte\t"); \
4284 output_addr_const (STREAM, (VALUE)); \
4285 fprintf (STREAM, "\n"); \
4288 /* This is how to output an assembler line for a numeric constant byte. */
4290 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4291 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4293 /* This is how to output an element of a case-vector that is absolute. */
4295 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4296 fprintf (STREAM, "\t%s\t%sL%d\n", \
4297 Pmode == DImode ? ".dword" : ".word", \
4298 LOCAL_LABEL_PREFIX, \
4301 /* This is how to output an element of a case-vector that is relative.
4302 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4303 TARGET_EMBEDDED_PIC). */
4305 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4307 if (TARGET_MIPS16) \
4308 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4309 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4310 else if (TARGET_EMBEDDED_PIC) \
4311 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4312 Pmode == DImode ? ".dword" : ".word", \
4313 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4314 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4315 fprintf (STREAM, "\t%s\t%sL%d\n", \
4316 Pmode == DImode ? ".gpdword" : ".gpword", \
4317 LOCAL_LABEL_PREFIX, VALUE); \
4319 fprintf (STREAM, "\t%s\t%sL%d\n", \
4320 Pmode == DImode ? ".dword" : ".word", \
4321 LOCAL_LABEL_PREFIX, VALUE); \
4324 /* When generating embedded PIC or mips16 code we want to put the jump
4325 table in the .text section. In all other cases, we want to put the
4326 jump table in the .rdata section. Unfortunately, we can't use
4327 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4328 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4329 section if appropriate. */
4330 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4332 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4333 function_section (current_function_decl); \
4334 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4337 /* This is how to output an assembler line
4338 that says to advance the location counter
4339 to a multiple of 2**LOG bytes. */
4341 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4342 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4344 /* This is how to output an assembler line to advance the location
4345 counter by SIZE bytes. */
4347 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4348 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4350 /* This is how to output a string. */
4351 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4353 register int i, c, len = (LEN), cur_pos = 17; \
4354 register unsigned char *string = (unsigned char *)(STRING); \
4355 fprintf ((STREAM), "\t.ascii\t\""); \
4356 for (i = 0; i < len; i++) \
4358 register int c = string[i]; \
4364 putc ('\\', (STREAM)); \
4365 putc (c, (STREAM)); \
4369 case TARGET_NEWLINE: \
4370 fputs ("\\n", (STREAM)); \
4372 && (((c = string[i+1]) >= '\040' && c <= '~') \
4373 || c == TARGET_TAB)) \
4374 cur_pos = 32767; /* break right here */ \
4380 fputs ("\\t", (STREAM)); \
4385 fputs ("\\f", (STREAM)); \
4390 fputs ("\\b", (STREAM)); \
4395 fputs ("\\r", (STREAM)); \
4400 if (c >= ' ' && c < 0177) \
4402 putc (c, (STREAM)); \
4407 fprintf ((STREAM), "\\%03o", c); \
4412 if (cur_pos > 72 && i+1 < len) \
4415 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4418 fprintf ((STREAM), "\"\n"); \
4421 /* Handle certain cpp directives used in header files on sysV. */
4422 #define SCCS_DIRECTIVE
4424 /* Output #ident as a in the read-only data section. */
4425 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4428 int size = strlen (p) + 1; \
4430 assemble_string (p, size); \
4433 /* Default to -G 8 */
4434 #ifndef MIPS_DEFAULT_GVALUE
4435 #define MIPS_DEFAULT_GVALUE 8
4438 /* Define the strings to put out for each section in the object file. */
4439 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4440 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4441 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4442 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4443 #define READONLY_DATA_SECTION rdata_section
4444 #define SMALL_DATA_SECTION sdata_section
4446 /* What other sections we support other than the normal .data/.text. */
4448 #define EXTRA_SECTIONS in_sdata, in_rdata
4450 /* Define the additional functions to select our additional sections. */
4452 /* on the MIPS it is not a good idea to put constants in the text
4453 section, since this defeats the sdata/data mechanism. This is
4454 especially true when -O is used. In this case an effort is made to
4455 address with faster (gp) register relative addressing, which can
4456 only get at sdata and sbss items (there is no stext !!) However,
4457 if the constant is too large for sdata, and it's readonly, it
4458 will go into the .rdata section. */
4460 #define EXTRA_SECTION_FUNCTIONS \
4464 if (in_section != in_sdata) \
4466 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4467 in_section = in_sdata; \
4474 if (in_section != in_rdata) \
4476 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4477 in_section = in_rdata; \
4481 /* Given a decl node or constant node, choose the section to output it in
4482 and select that section. */
4484 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4486 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4489 /* Store in OUTPUT a string (made with alloca) containing
4490 an assembler-name for a local static variable named NAME.
4491 LABELNO is an integer which is different for each call. */
4493 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4494 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4495 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4497 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4500 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4501 TARGET_64BIT ? "dsubu" : "subu", \
4502 reg_names[STACK_POINTER_REGNUM], \
4503 reg_names[STACK_POINTER_REGNUM], \
4504 TARGET_64BIT ? "sd" : "sw", \
4506 reg_names[STACK_POINTER_REGNUM]); \
4510 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4513 if (! set_noreorder) \
4514 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4516 dslots_load_total++; \
4517 dslots_load_filled++; \
4518 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4519 TARGET_64BIT ? "ld" : "lw", \
4521 reg_names[STACK_POINTER_REGNUM], \
4522 TARGET_64BIT ? "daddu" : "addu", \
4523 reg_names[STACK_POINTER_REGNUM], \
4524 reg_names[STACK_POINTER_REGNUM]); \
4526 if (! set_noreorder) \
4527 fprintf (STREAM, "\t.set\treorder\n"); \
4531 /* Define the parentheses used to group arithmetic operations
4532 in assembler code. */
4534 #define ASM_OPEN_PAREN "("
4535 #define ASM_CLOSE_PAREN ")"
4537 /* How to start an assembler comment.
4538 The leading space is important (the mips native assembler requires it). */
4539 #ifndef ASM_COMMENT_START
4540 #define ASM_COMMENT_START " #"
4544 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4545 and mips-tdump.c to print them out.
4547 These must match the corresponding definitions in gdb/mipsread.c.
4548 Unfortunately, gcc and gdb do not currently share any directories. */
4550 #define CODE_MASK 0x8F300
4551 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4552 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4553 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4556 /* Default definitions for size_t and ptrdiff_t. */
4559 #define NO_BUILTIN_SIZE_TYPE
4560 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4563 #ifndef PTRDIFF_TYPE
4564 #define NO_BUILTIN_PTRDIFF_TYPE
4565 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4568 /* See mips_expand_prologue's use of loadgp for when this should be
4571 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4572 && mips_abi != ABI_32 \
4573 && mips_abi != ABI_O64)
4575 /* In mips16 mode, we need to look through the function to check for
4576 PC relative loads that are out of range. */
4577 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4579 /* We need to use a special set of functions to handle hard floating
4580 point code in mips16 mode. */
4582 #ifndef INIT_SUBTARGET_OPTABS
4583 #define INIT_SUBTARGET_OPTABS
4586 #define INIT_TARGET_OPTABS \
4589 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4590 INIT_SUBTARGET_OPTABS; \
4593 add_optab->handlers[(int) SFmode].libfunc = \
4594 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4595 sub_optab->handlers[(int) SFmode].libfunc = \
4596 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4597 smul_optab->handlers[(int) SFmode].libfunc = \
4598 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4599 flodiv_optab->handlers[(int) SFmode].libfunc = \
4600 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4602 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4603 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4604 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4605 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4606 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4607 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4609 floatsisf_libfunc = \
4610 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4612 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4614 if (TARGET_DOUBLE_FLOAT) \
4616 add_optab->handlers[(int) DFmode].libfunc = \
4617 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4618 sub_optab->handlers[(int) DFmode].libfunc = \
4619 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4620 smul_optab->handlers[(int) DFmode].libfunc = \
4621 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4622 flodiv_optab->handlers[(int) DFmode].libfunc = \
4623 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4625 extendsfdf2_libfunc = \
4626 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4627 truncdfsf2_libfunc = \
4628 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4631 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4633 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4635 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4637 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4639 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4641 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4643 floatsidf_libfunc = \
4644 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4646 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \
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