1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int may_call_alloca;
31 extern char **save_argv;
32 extern int target_flags;
33 extern char *version_string;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
137 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
138 extern int mips_isa; /* architectural level */
139 extern int mips16; /* whether generating mips16 code */
140 extern int mips16_hard_float; /* mips16 without -msoft-float */
141 extern int mips_entry; /* generate entry/exit for mips16 */
142 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
143 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
144 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
145 extern const char *mips_entry_string; /* for -mentry */
146 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
147 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
148 extern int mips_split_addresses; /* perform high/lo_sum support */
149 extern int dslots_load_total; /* total # load related delay slots */
150 extern int dslots_load_filled; /* # filled load delay slots */
151 extern int dslots_jump_total; /* total # jump related delay slots */
152 extern int dslots_jump_filled; /* # filled jump delay slots */
153 extern int dslots_number_nops; /* # of nops needed by previous insn */
154 extern int num_refs[3]; /* # 1/2/3 word references */
155 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
156 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
157 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
158 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
159 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
160 extern int mips_string_length; /* length of strings for mips16 */
161 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
163 /* Functions to change what output section we are using. */
164 extern void rdata_section PARAMS ((void));
165 extern void sdata_section PARAMS ((void));
166 extern void sbss_section PARAMS ((void));
168 /* Stubs for half-pic support if not OSF/1 reference platform. */
171 #define HALF_PIC_P() 0
172 #define HALF_PIC_NUMBER_PTRS 0
173 #define HALF_PIC_NUMBER_REFS 0
174 #define HALF_PIC_ENCODE(DECL)
175 #define HALF_PIC_DECLARE(NAME)
176 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
177 #define HALF_PIC_ADDRESS_P(X) 0
178 #define HALF_PIC_PTR(X) X
179 #define HALF_PIC_FINISH(STREAM)
183 /* Run-time compilation parameters selecting different hardware subsets. */
185 /* Macros used in the machine description to test the flags. */
187 /* Bits for real switches */
188 #define MASK_INT64 0x00000001 /* ints are 64 bits */
189 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
190 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
191 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
192 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
193 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
194 #define MASK_STATS 0x00000040 /* print statistics to stderr */
195 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
196 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
197 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
198 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
199 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
200 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
201 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
202 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
203 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
204 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
205 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
206 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
207 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
208 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
209 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
210 #define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
211 #define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
212 #define MASK_UNINIT_CONST_IN_RODATA 0x10000000 /* Store uninitialized
215 /* Dummy switches used only in spec's*/
216 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
218 /* Debug switches, not documented */
219 #define MASK_DEBUG 0 /* Eliminate version # in .s file */
220 #define MASK_DEBUG_A 0x40000000 /* don't allow <label>($reg) addrs */
221 #define MASK_DEBUG_B 0x20000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
222 #define MASK_DEBUG_C 0x10000000 /* don't expand seq, etc. */
223 #define MASK_DEBUG_D 0 /* don't do define_split's */
224 #define MASK_DEBUG_E 0 /* function_arg debug */
225 #define MASK_DEBUG_F 0
226 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
227 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
228 #define MASK_DEBUG_I 0 /* unused */
230 /* r4000 64 bit sizes */
231 #define TARGET_INT64 (target_flags & MASK_INT64)
232 #define TARGET_LONG64 (target_flags & MASK_LONG64)
233 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
234 #define TARGET_64BIT (target_flags & MASK_64BIT)
236 /* Mips vs. GNU linker */
237 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
239 /* generate mips 3900 insns */
240 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
242 /* Mips vs. GNU assembler */
243 #define TARGET_GAS (target_flags & MASK_GAS)
244 #define TARGET_UNIX_ASM (!TARGET_GAS)
245 #define TARGET_MIPS_AS TARGET_UNIX_ASM
248 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
249 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
250 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
251 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
252 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
253 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
254 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
255 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
256 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
257 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
259 /* Reg. Naming in .s ($21 vs. $a0) */
260 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
262 /* Optimize for Sdata/Sbss */
263 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
265 /* print program statistics */
266 #define TARGET_STATS (target_flags & MASK_STATS)
268 /* call memcpy instead of inline code */
269 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
271 /* .abicalls, etc from Pyramid V.4 */
272 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
274 /* OSF pic references to externs */
275 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
277 /* software floating point */
278 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
279 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
281 /* always call through a register */
282 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
284 /* generate embedded PIC code;
286 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
288 /* for embedded systems, optimize for
289 reduced RAM space instead of for
291 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
293 /* always store uninitialized const
294 variables in rodata, requires
295 TARGET_EMBEDDED_DATA. */
296 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
298 /* generate big endian code. */
299 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
301 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
302 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
304 #define TARGET_MAD (target_flags & MASK_MAD)
306 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
308 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
309 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
311 /* This is true if we must enable the assembly language file switching
314 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
316 /* We must disable the function end stabs when doing the file switching trick,
317 because the Lscope stabs end up in the wrong place, making it impossible
318 to debug the resulting code. */
319 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
321 /* Generate mips16 code */
322 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
324 /* Macro to define tables used to set the flags.
325 This is a list in braces of pairs in braces,
326 each pair being { "NAME", VALUE }
327 where VALUE is the bits to set or minus the bits to clear.
328 An empty string NAME is used to identify the default VALUE. */
330 #define TARGET_SWITCHES \
333 "No default crt0.o" }, \
334 {"int64", MASK_INT64 | MASK_LONG64, \
335 "Use 64-bit int type"}, \
336 {"long64", MASK_LONG64, \
337 "Use 64-bit long type"}, \
338 {"long32", -(MASK_LONG64 | MASK_INT64), \
339 "Use 32-bit long type"}, \
340 {"split-addresses", MASK_SPLIT_ADDR, \
341 "Optimize lui/addiu address loads"}, \
342 {"no-split-addresses", -MASK_SPLIT_ADDR, \
343 "Don't optimize lui/addiu address loads"}, \
344 {"mips-as", -MASK_GAS, \
348 {"rnames", MASK_NAME_REGS, \
349 "Use symbolic register names"}, \
350 {"no-rnames", -MASK_NAME_REGS, \
351 "Don't use symbolic register names"}, \
352 {"gpOPT", MASK_GPOPT, \
353 "Use GP relative sdata/sbss sections"}, \
354 {"gpopt", MASK_GPOPT, \
355 "Use GP relative sdata/sbss sections"}, \
356 {"no-gpOPT", -MASK_GPOPT, \
357 "Don't use GP relative sdata/sbss sections"}, \
358 {"no-gpopt", -MASK_GPOPT, \
359 "Don't use GP relative sdata/sbss sections"}, \
360 {"stats", MASK_STATS, \
361 "Output compiler statistics"}, \
362 {"no-stats", -MASK_STATS, \
363 "Don't output compiler statistics"}, \
364 {"memcpy", MASK_MEMCPY, \
365 "Don't optimize block moves"}, \
366 {"no-memcpy", -MASK_MEMCPY, \
367 "Optimize block moves"}, \
368 {"mips-tfile", MASK_MIPS_TFILE, \
369 "Use mips-tfile asm postpass"}, \
370 {"no-mips-tfile", -MASK_MIPS_TFILE, \
371 "Don't use mips-tfile asm postpass"}, \
372 {"soft-float", MASK_SOFT_FLOAT, \
373 "Use software floating point"}, \
374 {"hard-float", -MASK_SOFT_FLOAT, \
375 "Use hardware floating point"}, \
376 {"fp64", MASK_FLOAT64, \
377 "Use 64-bit FP registers"}, \
378 {"fp32", -MASK_FLOAT64, \
379 "Use 32-bit FP registers"}, \
380 {"gp64", MASK_64BIT, \
381 "Use 64-bit general registers"}, \
382 {"gp32", -MASK_64BIT, \
383 "Use 32-bit general registers"}, \
384 {"abicalls", MASK_ABICALLS, \
386 {"no-abicalls", -MASK_ABICALLS, \
387 "Don't use Irix PIC"}, \
388 {"half-pic", MASK_HALF_PIC, \
390 {"no-half-pic", -MASK_HALF_PIC, \
391 "Don't use OSF PIC"}, \
392 {"long-calls", MASK_LONG_CALLS, \
393 "Use indirect calls"}, \
394 {"no-long-calls", -MASK_LONG_CALLS, \
395 "Don't use indirect calls"}, \
396 {"embedded-pic", MASK_EMBEDDED_PIC, \
397 "Use embedded PIC"}, \
398 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
399 "Don't use embedded PIC"}, \
400 {"embedded-data", MASK_EMBEDDED_DATA, \
401 "Use ROM instead of RAM"}, \
402 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
403 "Don't use ROM instead of RAM"}, \
404 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
405 "Put uninitialized constants in ROM (needs -membedded-data)"}, \
406 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
407 "Don't put uninitialized constants in ROM"}, \
408 {"eb", MASK_BIG_ENDIAN, \
409 "Use big-endian byte order"}, \
410 {"el", -MASK_BIG_ENDIAN, \
411 "Use little-endian byte order"}, \
412 {"single-float", MASK_SINGLE_FLOAT, \
413 "Use single (32-bit) FP only"}, \
414 {"double-float", -MASK_SINGLE_FLOAT, \
415 "Don't use single (32-bit) FP only"}, \
417 "Use multiply accumulate"}, \
418 {"no-mad", -MASK_MAD, \
419 "Don't use multiply accumulate"}, \
420 {"fix4300", MASK_4300_MUL_FIX, \
421 "Work around early 4300 hardware bug"}, \
422 {"no-fix4300", -MASK_4300_MUL_FIX, \
423 "Don't work around early 4300 hardware bug"}, \
424 {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
425 "Optimize for 4650"}, \
426 {"3900", MASK_MIPS3900, \
427 "Optimize for 3900"}, \
428 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
429 "Trap on integer divide by zero"}, \
430 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
431 "Don't trap on integer divide by zero"}, \
432 {"check-range-division",MASK_CHECK_RANGE_DIV, \
433 "Trap on integer divide overflow"}, \
434 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
435 "Don't trap on integer divide overflow"}, \
436 {"debug", MASK_DEBUG, \
438 {"debuga", MASK_DEBUG_A, \
440 {"debugb", MASK_DEBUG_B, \
442 {"debugc", MASK_DEBUG_C, \
444 {"debugd", MASK_DEBUG_D, \
446 {"debuge", MASK_DEBUG_E, \
448 {"debugf", MASK_DEBUG_F, \
450 {"debugg", MASK_DEBUG_G, \
452 {"debugh", MASK_DEBUG_H, \
454 {"debugi", MASK_DEBUG_I, \
456 {"", (TARGET_DEFAULT \
457 | TARGET_CPU_DEFAULT \
458 | TARGET_ENDIAN_DEFAULT), \
462 /* Default target_flags if no switches are specified */
464 #ifndef TARGET_DEFAULT
465 #define TARGET_DEFAULT 0
468 #ifndef TARGET_CPU_DEFAULT
469 #define TARGET_CPU_DEFAULT 0
472 #ifndef TARGET_ENDIAN_DEFAULT
474 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
476 #define TARGET_ENDIAN_DEFAULT 0
480 #ifndef MIPS_ISA_DEFAULT
481 #define MIPS_ISA_DEFAULT 1
486 /* Make this compile time constant for libgcc2 */
488 #define TARGET_64BIT 1
490 #define TARGET_64BIT 0
492 #endif /* IN_LIBGCC2 */
494 #ifndef MULTILIB_ENDIAN_DEFAULT
495 #if TARGET_ENDIAN_DEFAULT == 0
496 #define MULTILIB_ENDIAN_DEFAULT "EL"
498 #define MULTILIB_ENDIAN_DEFAULT "EB"
502 #ifndef MULTILIB_ISA_DEFAULT
503 #if MIPS_ISA_DEFAULT == 1
504 #define MULTILIB_ISA_DEFAULT "mips1"
505 #elif MIPS_ISA_DEFAULT == 2
506 #define MULTILIB_ISA_DEFAULT "mips2"
507 #elif MIPS_ISA_DEFAULT == 3
508 #define MULTILIB_ISA_DEFAULT "mips3"
509 #elif MIPS_ISA_DEFAULT == 4
510 #define MULTILIB_ISA_DEFAULT "mips4"
512 #define MULTILIB_ISA_DEFAULT "mips1"
516 #ifndef MULTILIB_DEFAULTS
517 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
520 /* We must pass -EL to the linker by default for little endian embedded
521 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
522 linker will default to using big-endian output files. The OUTPUT_FORMAT
523 line must be in the linker script, otherwise -EB/-EL will not work. */
525 #ifndef LINKER_ENDIAN_SPEC
526 #if TARGET_ENDIAN_DEFAULT == 0
527 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
529 #define LINKER_ENDIAN_SPEC ""
533 /* This macro is similar to `TARGET_SWITCHES' but defines names of
534 command options that have values. Its definition is an
535 initializer with a subgrouping for each command option.
537 Each subgrouping contains a string constant, that defines the
538 fixed part of the option name, and the address of a variable.
539 The variable, type `char *', is set to the variable part of the
540 given option if the fixed part matches. The actual option name
541 is made by appending `-m' to the specified name.
543 Here is an example which defines `-mshort-data-NUMBER'. If the
544 given option is `-mshort-data-512', the variable `m88k_short_data'
545 will be set to the string `"512"'.
547 extern char *m88k_short_data;
548 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
550 #define TARGET_OPTIONS \
552 SUBTARGET_TARGET_OPTIONS \
553 { "cpu=", &mips_cpu_string, \
554 "Specify CPU for scheduling purposes"}, \
555 { "ips", &mips_isa_string, \
556 "Specify MIPS ISA"}, \
557 { "entry", &mips_entry_string, \
558 "Use mips16 entry/exit psuedo ops"}, \
559 { "no-mips16", &mips_no_mips16_string, \
560 "Don't use MIPS16 instructions"}, \
561 { "explicit-type-size", &mips_explicit_type_size_string, \
565 /* This is meant to be redefined in the host dependent files. */
566 #define SUBTARGET_TARGET_OPTIONS
568 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
570 /* Generate three-operand multiply instructions for both SImode and DImode. */
571 #define GENERATE_MULT3 (TARGET_MIPS3900 \
574 /* Macros to decide whether certain features are available or not,
575 depending on the instruction set architecture level. */
577 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
578 #define HAVE_SQRT_P() (mips_isa != 1)
580 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
581 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
584 /* ISA has branch likely instructions (eg. mips2). */
585 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
587 /* ISA has the conditional move instructions introduced in mips4. */
588 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
591 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
592 branch on CC, and move (both FP and non-FP) on CC. */
593 #define ISA_HAS_8CC (mips_isa == 4 \
597 /* This is a catch all for the other new mips4 instructions: indexed load and
598 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
599 and the FP recip and recip sqrt instructions */
600 #define ISA_HAS_FP4 (mips_isa == 4 \
605 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
606 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
607 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
608 target_flags, and -mgp64 sets MASK_64BIT.
610 Setting MASK_64BIT in target_flags will cause gcc to assume that
611 registers are 64 bits wide. int, long and void * will be 32 bit;
612 this may be changed with -mint64 or -mlong64.
614 The gen* programs link code that refers to MASK_64BIT. They don't
615 actually use the information in target_flags; they just refer to
618 /* Switch Recognition by gcc.c. Add -G xx support */
620 #ifdef SWITCH_TAKES_ARG
621 #undef SWITCH_TAKES_ARG
624 #define SWITCH_TAKES_ARG(CHAR) \
625 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
627 /* Sometimes certain combinations of command options do not make sense
628 on a particular target machine. You can define a macro
629 `OVERRIDE_OPTIONS' to take account of this. This macro, if
630 defined, is executed once just after all the command options have
633 On the MIPS, it is used to handle -G. We also use it to set up all
634 of the tables referenced in the other macros. */
636 #define OVERRIDE_OPTIONS override_options ()
638 /* Zero or more C statements that may conditionally modify two
639 variables `fixed_regs' and `call_used_regs' (both of type `char
640 []') after they have been initialized from the two preceding
643 This is necessary in case the fixed or call-clobbered registers
644 depend on target flags.
646 You need not define this macro if it has no work to do.
648 If the usage of an entire class of registers depends on the target
649 flags, you may indicate this to GCC by using this macro to modify
650 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
651 the classes which should not be used by GCC. Also define the macro
652 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
653 letter for a class that shouldn't be used.
655 (However, if this class is not included in `GENERAL_REGS' and all
656 of the insn patterns whose constraints permit this class are
657 controlled by target switches, then GCC will automatically avoid
658 using these registers when the target switches are opposed to
661 #define CONDITIONAL_REGISTER_USAGE \
664 if (!TARGET_HARD_FLOAT) \
668 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
669 fixed_regs[regno] = call_used_regs[regno] = 1; \
670 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
671 fixed_regs[regno] = call_used_regs[regno] = 1; \
673 else if (! ISA_HAS_8CC) \
677 /* We only have a single condition code register. We \
678 implement this by hiding all the condition code registers, \
679 and generating RTL that refers directly to ST_REG_FIRST. */ \
680 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
681 fixed_regs[regno] = call_used_regs[regno] = 1; \
683 /* In mips16 mode, we permit the $t temporary registers to be used \
684 for reload. We prohibit the unused $s registers, since they \
685 are caller saved, and saving them via a mips16 register would \
686 probably waste more time than just reloading the value. */ \
689 fixed_regs[18] = call_used_regs[18] = 1; \
690 fixed_regs[19] = call_used_regs[19] = 1; \
691 fixed_regs[20] = call_used_regs[20] = 1; \
692 fixed_regs[21] = call_used_regs[21] = 1; \
693 fixed_regs[22] = call_used_regs[22] = 1; \
694 fixed_regs[23] = call_used_regs[23] = 1; \
695 fixed_regs[26] = call_used_regs[26] = 1; \
696 fixed_regs[27] = call_used_regs[27] = 1; \
697 fixed_regs[30] = call_used_regs[30] = 1; \
699 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
703 /* This is meant to be redefined in the host dependent files. */
704 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
706 /* Show we can debug even without a frame pointer. */
707 #define CAN_DEBUG_WITHOUT_FP
709 /* Complain about missing specs and predefines that should be defined in each
710 of the target tm files to override the defaults. This is mostly a place-
711 holder until I can get each of the files updated [mm]. */
713 #if defined(OSF_OS) \
714 || defined(DECSTATION) \
715 || defined(SGI_TARGET) \
716 || defined(MIPS_NEWS) \
717 || defined(MIPS_SYSV) \
718 || defined(MIPS_SVR4) \
719 || defined(MIPS_BSD43)
721 #ifndef CPP_PREDEFINES
722 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
726 #error "Define LIB_SPEC in the appropriate tm.h file"
729 #ifndef STARTFILE_SPEC
730 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
734 #error "Define MACHINE_TYPE in the appropriate tm.h file"
738 /* Tell collect what flags to pass to nm. */
740 #define NM_FLAGS "-Bn"
744 /* Names to predefine in the preprocessor for this target machine. */
746 #ifndef CPP_PREDEFINES
747 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
748 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
749 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
752 /* Assembler specs. */
754 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
757 #define MIPS_AS_ASM_SPEC "\
758 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
759 %{pipe: %e-pipe is not supported.} \
760 %{K} %(subtarget_mips_as_asm_spec)"
762 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
763 rather than gas. It may be overridden by subtargets. */
765 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
766 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
769 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
772 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
774 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
775 GAS_ASM_SPEC as the default, depending upon the value of
778 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
781 #define TARGET_ASM_SPEC "\
782 %{mmips-as: %(mips_as_asm_spec)} \
783 %{!mmips-as: %(gas_asm_spec)}"
787 #define TARGET_ASM_SPEC "\
788 %{!mgas: %(mips_as_asm_spec)} \
789 %{mgas: %(gas_asm_spec)}"
793 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
794 to the assembler. It may be overridden by subtargets. */
795 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
796 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
798 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
801 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
802 the assembler. It may be overridden by subtargets. */
803 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
804 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
805 %{g} %{g0} %{g1} %{g2} %{g3} \
806 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
807 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
808 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
809 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
812 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
813 overridden by subtargets. */
815 #ifndef SUBTARGET_ASM_SPEC
816 #define SUBTARGET_ASM_SPEC ""
819 /* ASM_SPEC is the set of arguments to pass to the assembler. */
822 %{!membedded-pic:%{G*}} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
823 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
824 %(subtarget_asm_optimizing_spec) \
825 %(subtarget_asm_debugging_spec) \
827 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
829 %(subtarget_asm_spec)"
831 /* Specify to run a post-processor, mips-tfile after the assembler
832 has run to stuff the mips debug information into the object file.
833 This is needed because the $#!%^ MIPS assembler provides no way
834 of specifying such information in the assembly file. If we are
835 cross compiling, disable mips-tfile unless the user specifies
838 #ifndef ASM_FINAL_SPEC
839 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
841 #define ASM_FINAL_SPEC "\
842 %{mmips-as: %{!mno-mips-tfile: \
843 \n mips-tfile %{v*: -v} \
845 %{!K: %{save-temps: -I %b.o~}} \
846 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
847 %{.s:%i} %{!.s:%g.s}}}"
851 #define ASM_FINAL_SPEC "\
852 %{!mgas: %{!mno-mips-tfile: \
853 \n mips-tfile %{v*: -v} \
855 %{!K: %{save-temps: -I %b.o~}} \
856 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
857 %{.s:%i} %{!.s:%g.s}}}"
860 #endif /* ASM_FINAL_SPEC */
862 /* Redefinition of libraries used. Mips doesn't support normal
863 UNIX style profiling via calling _mcount. It does offer
864 profiling that samples the PC, so do what we can... */
867 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
870 /* Extra switches sometimes passed to the linker. */
871 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
872 will interpret it as a -b option. */
876 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
877 %{bestGnum} %{shared} %{non_shared} \
878 %(linker_endian_spec)"
879 #endif /* LINK_SPEC defined */
881 /* Specs for the compiler proper */
883 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
884 overridden by subtargets. */
885 #ifndef SUBTARGET_CC1_SPEC
886 #define SUBTARGET_CC1_SPEC ""
889 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
893 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
894 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
895 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
896 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
897 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
898 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
899 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
900 %{m4650:-mcpu=r4650} \
901 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
902 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
903 %{pic-none: -mno-half-pic} \
904 %{pic-lib: -mhalf-pic} \
905 %{pic-extern: -mhalf-pic} \
906 %{pic-calls: -mhalf-pic} \
908 %(subtarget_cc1_spec) "
911 /* Preprocessor specs. */
913 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
914 be overridden by subtargets. */
916 #ifndef SUBTARGET_CPP_SIZE_SPEC
917 #define SUBTARGET_CPP_SIZE_SPEC "\
918 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
919 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
922 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
923 overridden by subtargets. */
924 #ifndef SUBTARGET_CPP_SPEC
925 #define SUBTARGET_CPP_SPEC ""
928 /* If we're using 64bit longs, then we have to define __LONG_MAX__
929 correctly. Similarly for 64bit ints and __INT_MAX__. */
930 #ifndef LONG_MAX_SPEC
931 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
932 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
934 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
938 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
942 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
943 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
944 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
945 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
946 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
947 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
948 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
949 %(subtarget_cpp_size_spec) \
950 %{mips3:-U__mips -D__mips=3 -D__mips64} \
951 %{mips4:-U__mips -D__mips=4 -D__mips64} \
952 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
953 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
954 %{m4650:%{!msoft-float:-D__mips_single_float}} \
955 %{msoft-float:-D__mips_soft_float} \
956 %{mabi=eabi:-D__mips_eabi} \
957 %{mips16:%{!mno-mips16:-D__mips16}} \
958 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
959 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
961 %(subtarget_cpp_spec) "
964 /* This macro defines names of additional specifications to put in the specs
965 that can be used in various specifications like CC1_SPEC. Its definition
966 is an initializer with a subgrouping for each command option.
968 Each subgrouping contains a string constant, that defines the
969 specification name, and a string constant that used by the GNU CC driver
972 Do not define this macro if it does not need to do anything. */
974 #define EXTRA_SPECS \
975 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
976 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
977 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
978 { "long_max_spec", LONG_MAX_SPEC }, \
979 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
980 { "gas_asm_spec", GAS_ASM_SPEC }, \
981 { "target_asm_spec", TARGET_ASM_SPEC }, \
982 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
983 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
984 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
985 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
986 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
987 SUBTARGET_EXTRA_SPECS
989 #ifndef SUBTARGET_EXTRA_SPECS
990 #define SUBTARGET_EXTRA_SPECS
993 /* If defined, this macro is an additional prefix to try after
994 `STANDARD_EXEC_PREFIX'. */
996 #ifndef MD_EXEC_PREFIX
997 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1000 #ifndef MD_STARTFILE_PREFIX
1001 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1005 /* Print subsidiary information on the compiler version in use. */
1007 #define MIPS_VERSION "[AL 1.1, MM 40]"
1009 #ifndef MACHINE_TYPE
1010 #define MACHINE_TYPE "BSD Mips"
1013 #ifndef TARGET_VERSION_INTERNAL
1014 #define TARGET_VERSION_INTERNAL(STREAM) \
1015 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1018 #ifndef TARGET_VERSION
1019 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1023 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1024 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1025 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1027 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1028 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1031 /* By default, turn on GDB extensions. */
1032 #define DEFAULT_GDB_EXTENSIONS 1
1034 /* If we are passing smuggling stabs through the MIPS ECOFF object
1035 format, put a comment in front of the .stab<x> operation so
1036 that the MIPS assembler does not choke. The mips-tfile program
1037 will correctly put the stab into the object file. */
1039 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1040 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1041 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1043 /* Local compiler-generated symbols must have a prefix that the assembler
1044 understands. By default, this is $, although some targets (e.g.,
1045 NetBSD-ELF) need to override this. */
1047 #ifndef LOCAL_LABEL_PREFIX
1048 #define LOCAL_LABEL_PREFIX "$"
1051 /* By default on the mips, external symbols do not have an underscore
1052 prepended, but some targets (e.g., NetBSD) require this. */
1054 #ifndef USER_LABEL_PREFIX
1055 #define USER_LABEL_PREFIX ""
1058 /* Forward references to tags are allowed. */
1059 #define SDB_ALLOW_FORWARD_REFERENCES
1061 /* Unknown tags are also allowed. */
1062 #define SDB_ALLOW_UNKNOWN_REFERENCES
1064 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1065 since the length can run past this up to a continuation point. */
1066 #define DBX_CONTIN_LENGTH 1500
1068 /* How to renumber registers for dbx and gdb. */
1069 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1071 /* The mapping from gcc register number to DWARF 2 CFA column number.
1072 This mapping does not allow for tracking register 0, since SGI's broken
1073 dwarf reader thinks column 0 is used for the frame address, but since
1074 register 0 is fixed this is not a problem. */
1075 #define DWARF_FRAME_REGNUM(REG) \
1076 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1078 /* The DWARF 2 CFA column which tracks the return address. */
1079 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1081 /* Before the prologue, RA lives in r31. */
1082 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1084 /* Overrides for the COFF debug format. */
1085 #define PUT_SDB_SCL(a) \
1087 extern FILE *asm_out_text_file; \
1088 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1091 #define PUT_SDB_INT_VAL(a) \
1093 extern FILE *asm_out_text_file; \
1094 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1097 #define PUT_SDB_VAL(a) \
1099 extern FILE *asm_out_text_file; \
1100 fputs ("\t.val\t", asm_out_text_file); \
1101 output_addr_const (asm_out_text_file, (a)); \
1102 fputc (';', asm_out_text_file); \
1105 #define PUT_SDB_DEF(a) \
1107 extern FILE *asm_out_text_file; \
1108 fprintf (asm_out_text_file, "\t%s.def\t", \
1109 (TARGET_GAS) ? "" : "#"); \
1110 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1111 fputc (';', asm_out_text_file); \
1114 #define PUT_SDB_PLAIN_DEF(a) \
1116 extern FILE *asm_out_text_file; \
1117 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1118 (TARGET_GAS) ? "" : "#", (a)); \
1121 #define PUT_SDB_ENDEF \
1123 extern FILE *asm_out_text_file; \
1124 fprintf (asm_out_text_file, "\t.endef\n"); \
1127 #define PUT_SDB_TYPE(a) \
1129 extern FILE *asm_out_text_file; \
1130 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1133 #define PUT_SDB_SIZE(a) \
1135 extern FILE *asm_out_text_file; \
1136 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1139 #define PUT_SDB_DIM(a) \
1141 extern FILE *asm_out_text_file; \
1142 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1145 #ifndef PUT_SDB_START_DIM
1146 #define PUT_SDB_START_DIM \
1148 extern FILE *asm_out_text_file; \
1149 fprintf (asm_out_text_file, "\t.dim\t"); \
1153 #ifndef PUT_SDB_NEXT_DIM
1154 #define PUT_SDB_NEXT_DIM(a) \
1156 extern FILE *asm_out_text_file; \
1157 fprintf (asm_out_text_file, "%d,", a); \
1161 #ifndef PUT_SDB_LAST_DIM
1162 #define PUT_SDB_LAST_DIM(a) \
1164 extern FILE *asm_out_text_file; \
1165 fprintf (asm_out_text_file, "%d;", a); \
1169 #define PUT_SDB_TAG(a) \
1171 extern FILE *asm_out_text_file; \
1172 fprintf (asm_out_text_file, "\t.tag\t"); \
1173 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1174 fputc (';', asm_out_text_file); \
1177 /* For block start and end, we create labels, so that
1178 later we can figure out where the correct offset is.
1179 The normal .ent/.end serve well enough for functions,
1180 so those are just commented out. */
1182 #define PUT_SDB_BLOCK_START(LINE) \
1184 extern FILE *asm_out_text_file; \
1185 fprintf (asm_out_text_file, \
1186 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1187 LOCAL_LABEL_PREFIX, \
1189 (TARGET_GAS) ? "" : "#", \
1190 LOCAL_LABEL_PREFIX, \
1193 sdb_label_count++; \
1196 #define PUT_SDB_BLOCK_END(LINE) \
1198 extern FILE *asm_out_text_file; \
1199 fprintf (asm_out_text_file, \
1200 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1201 LOCAL_LABEL_PREFIX, \
1203 (TARGET_GAS) ? "" : "#", \
1204 LOCAL_LABEL_PREFIX, \
1207 sdb_label_count++; \
1210 #define PUT_SDB_FUNCTION_START(LINE)
1212 #define PUT_SDB_FUNCTION_END(LINE) \
1214 extern FILE *asm_out_text_file; \
1215 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1218 #define PUT_SDB_EPILOGUE_END(NAME)
1220 #define PUT_SDB_SRC_FILE(FILENAME) \
1222 extern FILE *asm_out_text_file; \
1223 output_file_directive (asm_out_text_file, (FILENAME)); \
1226 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1227 sprintf ((BUFFER), ".%dfake", (NUMBER));
1229 /* Correct the offset of automatic variables and arguments. Note that
1230 the MIPS debug format wants all automatic variables and arguments
1231 to be in terms of the virtual frame pointer (stack pointer before
1232 any adjustment in the function), while the MIPS 3.0 linker wants
1233 the frame pointer to be the stack pointer after the initial
1236 #define DEBUGGER_AUTO_OFFSET(X) \
1237 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1238 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1239 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1241 /* Tell collect that the object format is ECOFF */
1242 #ifndef OBJECT_FORMAT_ROSE
1243 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1244 #define EXTENDED_COFF /* ECOFF, not normal coff */
1247 #if 0 /* These definitions normally have no effect because
1248 MIPS systems define USE_COLLECT2, so
1249 assemble_constructor does nothing anyway. */
1251 /* Don't use the default definitions, because we don't have gld.
1252 Also, we don't want stabs when generating ECOFF output.
1253 Instead we depend on collect to handle these. */
1255 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1256 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1260 /* Target machine storage layout */
1262 /* Define in order to support both big and little endian float formats
1263 in the same gcc binary. */
1264 #define REAL_ARITHMETIC
1266 /* Define this if most significant bit is lowest numbered
1267 in instructions that operate on numbered bit-fields.
1269 #define BITS_BIG_ENDIAN 0
1271 /* Define this if most significant byte of a word is the lowest numbered. */
1272 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1274 /* Define this if most significant word of a multiword number is the lowest. */
1275 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1277 /* Define this to set the endianness to use in libgcc2.c, which can
1278 not depend on target_flags. */
1279 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1280 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1282 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1285 /* Number of bits in an addressable storage unit */
1286 #define BITS_PER_UNIT 8
1288 /* Width in bits of a "word", which is the contents of a machine register.
1289 Note that this is not necessarily the width of data type `int';
1290 if using 16-bit ints on a 68000, this would still be 32.
1291 But on a machine with 16-bit registers, this would be 16. */
1292 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1293 #define MAX_BITS_PER_WORD 64
1295 /* Width of a word, in units (bytes). */
1296 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1297 #define MIN_UNITS_PER_WORD 4
1299 /* For MIPS, width of a floating point register. */
1300 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1302 /* A C expression for the size in bits of the type `int' on the
1303 target machine. If you don't define this, the default is one
1305 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1306 #define MAX_INT_TYPE_SIZE 64
1308 /* Tell the preprocessor the maximum size of wchar_t. */
1309 #ifndef MAX_WCHAR_TYPE_SIZE
1310 #ifndef WCHAR_TYPE_SIZE
1311 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1315 /* A C expression for the size in bits of the type `short' on the
1316 target machine. If you don't define this, the default is half a
1317 word. (If this would be less than one storage unit, it is
1318 rounded up to one unit.) */
1319 #define SHORT_TYPE_SIZE 16
1321 /* A C expression for the size in bits of the type `long' on the
1322 target machine. If you don't define this, the default is one
1324 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1325 #define MAX_LONG_TYPE_SIZE 64
1327 /* A C expression for the size in bits of the type `long long' on the
1328 target machine. If you don't define this, the default is two
1330 #define LONG_LONG_TYPE_SIZE 64
1332 /* A C expression for the size in bits of the type `char' on the
1333 target machine. If you don't define this, the default is one
1334 quarter of a word. (If this would be less than one storage unit,
1335 it is rounded up to one unit.) */
1336 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1338 /* A C expression for the size in bits of the type `float' on the
1339 target machine. If you don't define this, the default is one
1341 #define FLOAT_TYPE_SIZE 32
1343 /* A C expression for the size in bits of the type `double' on the
1344 target machine. If you don't define this, the default is two
1346 #define DOUBLE_TYPE_SIZE 64
1348 /* A C expression for the size in bits of the type `long double' on
1349 the target machine. If you don't define this, the default is two
1351 #define LONG_DOUBLE_TYPE_SIZE 64
1353 /* Width in bits of a pointer.
1354 See also the macro `Pmode' defined below. */
1355 #ifndef POINTER_SIZE
1356 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1359 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1360 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1362 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1363 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1365 /* Allocation boundary (in *bits*) for the code of a function. */
1366 #define FUNCTION_BOUNDARY 32
1368 /* Alignment of field after `int : 0' in a structure. */
1369 #define EMPTY_FIELD_BOUNDARY 32
1371 /* Every structure's size must be a multiple of this. */
1372 /* 8 is observed right on a DECstation and on riscos 4.02. */
1373 #define STRUCTURE_SIZE_BOUNDARY 8
1375 /* There is no point aligning anything to a rounder boundary than this. */
1376 #define BIGGEST_ALIGNMENT 64
1378 /* Set this nonzero if move instructions will actually fail to work
1379 when given unaligned data. */
1380 #define STRICT_ALIGNMENT 1
1382 /* Define this if you wish to imitate the way many other C compilers
1383 handle alignment of bitfields and the structures that contain
1386 The behavior is that the type written for a bitfield (`int',
1387 `short', or other integer type) imposes an alignment for the
1388 entire structure, as if the structure really did contain an
1389 ordinary field of that type. In addition, the bitfield is placed
1390 within the structure so that it would fit within such a field,
1391 not crossing a boundary for it.
1393 Thus, on most machines, a bitfield whose type is written as `int'
1394 would not cross a four-byte boundary, and would force four-byte
1395 alignment for the whole structure. (The alignment used may not
1396 be four bytes; it is controlled by the other alignment
1399 If the macro is defined, its definition should be a C expression;
1400 a nonzero value for the expression enables this behavior. */
1402 #define PCC_BITFIELD_TYPE_MATTERS 1
1404 /* If defined, a C expression to compute the alignment given to a
1405 constant that is being placed in memory. CONSTANT is the constant
1406 and ALIGN is the alignment that the object would ordinarily have.
1407 The value of this macro is used instead of that alignment to align
1410 If this macro is not defined, then ALIGN is used.
1412 The typical use of this macro is to increase alignment for string
1413 constants to be word aligned so that `strcpy' calls that copy
1414 constants can be done inline. */
1416 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1417 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1418 && (ALIGN) < BITS_PER_WORD \
1422 /* If defined, a C expression to compute the alignment for a static
1423 variable. TYPE is the data type, and ALIGN is the alignment that
1424 the object would ordinarily have. The value of this macro is used
1425 instead of that alignment to align the object.
1427 If this macro is not defined, then ALIGN is used.
1429 One use of this macro is to increase alignment of medium-size
1430 data to make it all fit in fewer cache lines. Another is to
1431 cause character arrays to be word-aligned so that `strcpy' calls
1432 that copy constants to character arrays can be done inline. */
1434 #undef DATA_ALIGNMENT
1435 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1436 ((((ALIGN) < BITS_PER_WORD) \
1437 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1438 || TREE_CODE (TYPE) == UNION_TYPE \
1439 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1441 /* Define this macro if an argument declared as `char' or `short' in a
1442 prototype should actually be passed as an `int'. In addition to
1443 avoiding errors in certain cases of mismatch, it also makes for
1444 better code on certain machines. */
1446 #define PROMOTE_PROTOTYPES 1
1448 /* Define if operations between registers always perform the operation
1449 on the full register even if a narrower mode is specified. */
1450 #define WORD_REGISTER_OPERATIONS
1452 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1453 will either zero-extend or sign-extend. The value of this macro should
1454 be the code that says which one of the two operations is implicitly
1457 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1458 moves. All other referces are zero extended. */
1459 #define LOAD_EXTEND_OP(MODE) \
1460 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1461 ? SIGN_EXTEND : ZERO_EXTEND)
1463 /* Define this macro if it is advisable to hold scalars in registers
1464 in a wider mode than that declared by the program. In such cases,
1465 the value is constrained to be within the bounds of the declared
1466 type, but kept valid in the wider mode. The signedness of the
1467 extension may differ from that of the type.
1469 We promote any value smaller than SImode up to SImode. We don't
1470 want to promote to DImode when in 64 bit mode, because that would
1471 prevent us from using the faster SImode multiply and divide
1474 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1475 if (GET_MODE_CLASS (MODE) == MODE_INT \
1476 && GET_MODE_SIZE (MODE) < 4) \
1479 /* Define this if function arguments should also be promoted using the above
1482 #define PROMOTE_FUNCTION_ARGS
1484 /* Likewise, if the function return value is promoted. */
1486 #define PROMOTE_FUNCTION_RETURN
1488 /* Standard register usage. */
1490 /* Number of actual hardware registers.
1491 The hardware registers are assigned numbers for the compiler
1492 from 0 to just below FIRST_PSEUDO_REGISTER.
1493 All registers that the compiler knows about must be given numbers,
1494 even those that are not normally considered general registers.
1496 On the Mips, we have 32 integer registers, 32 floating point
1497 registers, 8 condition code registers, and the special registers
1498 hi, lo, hilo, and rap. The 8 condition code registers are only
1499 used if mips_isa >= 4. The hilo register is only used in 64 bit
1500 mode. It represents a 64 bit value stored as two 32 bit values in
1501 the hi and lo registers; this is the result of the mult
1502 instruction. rap is a pointer to the stack where the return
1503 address reg ($31) was stored. This is needed for C++ exception
1506 #define FIRST_PSEUDO_REGISTER 76
1508 /* 1 for registers that have pervasive standard uses
1509 and are not available for the register allocator.
1511 On the MIPS, see conventions, page D-2 */
1513 #define FIXED_REGISTERS \
1515 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1523 /* 1 for registers not available across function calls.
1524 These must include the FIXED_REGISTERS and also any
1525 registers that can be used without being saved.
1526 The latter must include the registers where values are returned
1527 and the register where structure-value addresses are passed.
1528 Aside from that, you can include as many other registers as you like. */
1530 #define CALL_USED_REGISTERS \
1532 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1533 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1535 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1540 /* Internal macros to classify a register number as to whether it's a
1541 general purpose register, a floating point register, a
1542 multiply/divide register, or a status register. */
1544 #define GP_REG_FIRST 0
1545 #define GP_REG_LAST 31
1546 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1547 #define GP_DBX_FIRST 0
1549 #define FP_REG_FIRST 32
1550 #define FP_REG_LAST 63
1551 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1552 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1554 #define MD_REG_FIRST 64
1555 #define MD_REG_LAST 66
1556 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1558 #define ST_REG_FIRST 67
1559 #define ST_REG_LAST 74
1560 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1562 #define RAP_REG_NUM 75
1564 #define AT_REGNUM (GP_REG_FIRST + 1)
1565 #define HI_REGNUM (MD_REG_FIRST + 0)
1566 #define LO_REGNUM (MD_REG_FIRST + 1)
1567 #define HILO_REGNUM (MD_REG_FIRST + 2)
1569 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1570 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1571 should be used instead. */
1572 #define FPSW_REGNUM ST_REG_FIRST
1574 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1575 #define M16_REG_P(REGNO) \
1576 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1577 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1578 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1579 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1581 /* Return number of consecutive hard regs needed starting at reg REGNO
1582 to hold something of mode MODE.
1583 This is ordinarily the length in words of a value of mode MODE
1584 but can be less for certain modes in special long registers.
1586 On the MIPS, all general registers are one word long. Except on
1587 the R4000 with the FR bit set, the floating point uses register
1588 pairs, with the second register not being allocable. */
1590 #define HARD_REGNO_NREGS(REGNO, MODE) \
1591 (! FP_REG_P (REGNO) \
1592 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1593 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1595 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1596 MODE. In 32 bit mode, require that DImode and DFmode be in even
1597 registers. For DImode, this makes some of the insns easier to
1598 write, since you don't have to worry about a DImode value in
1599 registers 3 & 4, producing a result in 4 & 5.
1601 To make the code simpler HARD_REGNO_MODE_OK now just references an
1602 array built in override_options. Because machmodes.h is not yet
1603 included before this file is processed, the MODE bound can't be
1606 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1608 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1609 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1611 /* Value is 1 if it is a good idea to tie two pseudo registers
1612 when one has mode MODE1 and one has mode MODE2.
1613 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1614 for any hard reg, then this must be 0 for correct output. */
1615 #define MODES_TIEABLE_P(MODE1, MODE2) \
1616 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1617 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1618 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1619 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1621 /* MIPS pc is not overloaded on a register. */
1622 /* #define PC_REGNUM xx */
1624 /* Register to use for pushing function arguments. */
1625 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1627 /* Offset from the stack pointer to the first available location. Use
1628 the default value zero. */
1629 /* #define STACK_POINTER_OFFSET 0 */
1631 /* Base register for access to local variables of the function. We
1632 pretend that the frame pointer is $1, and then eliminate it to
1633 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1634 a fixed register, and will not be used for anything else. */
1635 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1637 /* Temporary scratch register for use by the assembler. */
1638 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1640 /* $30 is not available on the mips16, so we use $17 as the frame
1642 #define HARD_FRAME_POINTER_REGNUM \
1643 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1645 /* Value should be nonzero if functions must have frame pointers.
1646 Zero means the frame pointer need not be set up (and parms
1647 may be accessed via the stack pointer) in functions that seem suitable.
1648 This is computed in `reload', in reload1.c. */
1649 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1651 /* Base register for access to arguments of the function. */
1652 #define ARG_POINTER_REGNUM GP_REG_FIRST
1654 /* Fake register that holds the address on the stack of the
1655 current function's return address. */
1656 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1658 /* Register in which static-chain is passed to a function. */
1659 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1661 /* If the structure value address is passed in a register, then
1662 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1663 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1665 /* If the structure value address is not passed in a register, define
1666 `STRUCT_VALUE' as an expression returning an RTX for the place
1667 where the address is passed. If it returns 0, the address is
1668 passed as an "invisible" first argument. */
1669 #define STRUCT_VALUE 0
1671 /* Mips registers used in prologue/epilogue code when the stack frame
1672 is larger than 32K bytes. These registers must come from the
1673 scratch register set, and not used for passing and returning
1674 arguments and any other information used in the calling sequence
1675 (such as pic). Must start at 12, since t0/t3 are parameter passing
1676 registers in the 64 bit ABI. */
1678 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1679 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1681 /* Define this macro if it is as good or better to call a constant
1682 function address than to call an address kept in a register. */
1683 #define NO_FUNCTION_CSE 1
1685 /* Define this macro if it is as good or better for a function to
1686 call itself with an explicit address than to call an address
1687 kept in a register. */
1688 #define NO_RECURSIVE_FUNCTION_CSE 1
1690 /* The register number of the register used to address a table of
1691 static data addresses in memory. In some cases this register is
1692 defined by a processor's "application binary interface" (ABI).
1693 When this macro is defined, RTL is generated for this register
1694 once, as with the stack pointer and frame pointer registers. If
1695 this macro is not defined, it is up to the machine-dependent
1696 files to allocate such a register (if necessary). */
1697 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1699 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1701 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1702 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1703 isn't always called for static inline functions. */
1704 #define INIT_EXPANDERS \
1706 embedded_pic_fnaddr_rtx = NULL; \
1707 mips16_gp_pseudo_rtx = NULL; \
1710 /* Define the classes of registers for register constraints in the
1711 machine description. Also define ranges of constants.
1713 One of the classes must always be named ALL_REGS and include all hard regs.
1714 If there is more than one class, another class must be named NO_REGS
1715 and contain no registers.
1717 The name GENERAL_REGS must be the name of a class (or an alias for
1718 another name such as ALL_REGS). This is the class of registers
1719 that is allowed by "g" or "r" in a register constraint.
1720 Also, registers outside this class are allocated only when
1721 instructions express preferences for them.
1723 The classes must be numbered in nondecreasing order; that is,
1724 a larger-numbered class must never be contained completely
1725 in a smaller-numbered class.
1727 For any two classes, it is very desirable that there be another
1728 class that represents their union. */
1732 NO_REGS, /* no registers in set */
1733 M16_NA_REGS, /* mips16 regs not used to pass args */
1734 M16_REGS, /* mips16 directly accessible registers */
1735 T_REG, /* mips16 T register ($24) */
1736 M16_T_REGS, /* mips16 registers plus T register */
1737 GR_REGS, /* integer registers */
1738 FP_REGS, /* floating point registers */
1739 HI_REG, /* hi register */
1740 LO_REG, /* lo register */
1741 HILO_REG, /* hilo register pair for 64 bit mode mult */
1742 MD_REGS, /* multiply/divide registers (hi/lo) */
1743 HI_AND_GR_REGS, /* union classes */
1746 ST_REGS, /* status registers (fp status) */
1747 ALL_REGS, /* all registers */
1748 LIM_REG_CLASSES /* max value + 1 */
1751 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1753 #define GENERAL_REGS GR_REGS
1755 /* An initializer containing the names of the register classes as C
1756 string constants. These names are used in writing some of the
1759 #define REG_CLASS_NAMES \
1774 "HILO_AND_GR_REGS", \
1779 /* An initializer containing the contents of the register classes,
1780 as integers which are bit masks. The Nth integer specifies the
1781 contents of class N. The way the integer MASK is interpreted is
1782 that register R is in the class if `MASK & (1 << R)' is 1.
1784 When the machine has more than 32 registers, an integer does not
1785 suffice. Then the integers are replaced by sub-initializers,
1786 braced groupings containing several integers. Each
1787 sub-initializer must be suitable as an initializer for the type
1788 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1790 #define REG_CLASS_CONTENTS \
1792 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1793 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1794 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1795 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1796 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1797 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1798 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1799 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1800 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1801 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1802 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1803 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1804 { 0xffffffff, 0x00000000, 0x00000002 }, \
1805 { 0xffffffff, 0x00000000, 0x00000004 }, \
1806 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1807 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1811 /* A C expression whose value is a register class containing hard
1812 register REGNO. In general there is more that one such class;
1813 choose a class which is "minimal", meaning that no smaller class
1814 also contains the register. */
1816 extern enum reg_class mips_regno_to_class[];
1818 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1820 /* A macro whose definition is the name of the class to which a
1821 valid base register must belong. A base register is one used in
1822 an address which is the register value plus a displacement. */
1824 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1826 /* A macro whose definition is the name of the class to which a
1827 valid index register must belong. An index register is one used
1828 in an address where its value is either multiplied by a scale
1829 factor or added to another register (as well as added to a
1832 #define INDEX_REG_CLASS NO_REGS
1834 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1835 registers explicitly used in the rtl to be used as spill registers
1836 but prevents the compiler from extending the lifetime of these
1839 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1841 /* This macro is used later on in the file. */
1842 #define GR_REG_CLASS_P(CLASS) \
1843 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1844 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1846 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1847 is the default value (allocate the registers in numeric order). We
1848 define it just so that we can override it for the mips16 target in
1849 ORDER_REGS_FOR_LOCAL_ALLOC. */
1851 #define REG_ALLOC_ORDER \
1852 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1853 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1854 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1855 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1856 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1859 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1860 to be rearranged based on a particular function. On the mips16, we
1861 want to allocate $24 (T_REG) before other registers for
1862 instructions for which it is possible. */
1864 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1866 /* REGISTER AND CONSTANT CLASSES */
1868 /* Get reg_class from a letter such as appears in the machine
1871 DEFINED REGISTER CLASSES:
1873 'd' General (aka integer) registers
1874 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1875 'y' General registers (in both mips16 and non mips16 mode)
1876 'e' mips16 non argument registers (M16_NA_REGS)
1877 't' mips16 temporary register ($24)
1878 'f' Floating point registers
1881 'x' Multiply/divide registers
1883 'z' FP Status register
1884 'b' All registers */
1886 extern enum reg_class mips_char_to_class[];
1888 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1890 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1891 string can be used to stand for particular ranges of immediate
1892 operands. This macro defines what the ranges are. C is the
1893 letter, and VALUE is a constant value. Return 1 if VALUE is
1894 in the range specified by C. */
1898 `I' is used for the range of constants an arithmetic insn can
1899 actually contain (16 bits signed integers).
1901 `J' is used for the range which is just zero (ie, $r0).
1903 `K' is used for the range of constants a logical insn can actually
1904 contain (16 bit zero-extended integers).
1906 `L' is used for the range of constants that be loaded with lui
1907 (ie, the bottom 16 bits are zero).
1909 `M' is used for the range of constants that take two words to load
1910 (ie, not matched by `I', `K', and `L').
1912 `N' is used for negative 16 bit constants other than -65536.
1914 `O' is a 15 bit signed integer.
1916 `P' is used for positive 16 bit constants. */
1918 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1919 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1921 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1922 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1923 : (C) == 'J' ? ((VALUE) == 0) \
1924 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1925 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1926 && (((VALUE) & ~2147483647) == 0 \
1927 || ((VALUE) & ~2147483647) == ~2147483647)) \
1928 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1929 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1930 && (((VALUE) & 0x0000ffff) != 0 \
1931 || (((VALUE) & ~2147483647) != 0 \
1932 && ((VALUE) & ~2147483647) != ~2147483647))) \
1933 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1934 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1935 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1938 /* Similar, but for floating constants, and defining letters G and H.
1939 Here VALUE is the CONST_DOUBLE rtx itself. */
1943 'G' : Floating point 0 */
1945 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1947 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1949 /* Letters in the range `Q' through `U' may be defined in a
1950 machine-dependent fashion to stand for arbitrary operand types.
1951 The machine description macro `EXTRA_CONSTRAINT' is passed the
1952 operand as its first argument and the constraint letter as its
1955 `Q' is for mips16 GP relative constants
1956 `R' is for memory references which take 1 word for the instruction.
1957 `S' is for references to extern items which are PIC for OSF/rose.
1958 `T' is for memory addresses that can be used to load two words. */
1960 #define EXTRA_CONSTRAINT(OP,CODE) \
1961 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1962 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1963 && mips16_gp_offset_p (OP)) \
1964 : (GET_CODE (OP) != MEM) ? FALSE \
1965 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1966 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1967 && HALF_PIC_ADDRESS_P (OP)) \
1970 /* Given an rtx X being reloaded into a reg required to be
1971 in class CLASS, return the class of reg to actually use.
1972 In general this is just CLASS; but on some machines
1973 in some cases it is preferable to use a more restrictive class. */
1975 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1976 ((CLASS) != ALL_REGS \
1977 ? (! TARGET_MIPS16 \
1979 : ((CLASS) != GR_REGS \
1982 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1983 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1984 ? (TARGET_SOFT_FLOAT \
1985 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1987 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1988 || GET_MODE (X) == VOIDmode) \
1989 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1992 /* Certain machines have the property that some registers cannot be
1993 copied to some other registers without using memory. Define this
1994 macro on those machines to be a C expression that is non-zero if
1995 objects of mode MODE in registers of CLASS1 can only be copied to
1996 registers of class CLASS2 by storing a register of CLASS1 into
1997 memory and loading that memory location into a register of CLASS2.
1999 Do not define this macro if its value would always be zero. */
2001 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2002 ((!TARGET_DEBUG_H_MODE \
2003 && GET_MODE_CLASS (MODE) == MODE_INT \
2004 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2005 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2006 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2007 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2008 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2010 /* The HI and LO registers can only be reloaded via the general
2011 registers. Condition code registers can only be loaded to the
2012 general registers, and from the floating point registers. */
2014 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2015 mips_secondary_reload_class (CLASS, MODE, X, 1)
2016 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2017 mips_secondary_reload_class (CLASS, MODE, X, 0)
2019 /* Return the maximum number of consecutive registers
2020 needed to represent mode MODE in a register of class CLASS. */
2022 #define CLASS_UNITS(mode, size) \
2023 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2025 #define CLASS_MAX_NREGS(CLASS, MODE) \
2026 ((CLASS) == FP_REGS \
2028 ? CLASS_UNITS (MODE, 8) \
2029 : 2 * CLASS_UNITS (MODE, 8)) \
2030 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2032 /* If defined, gives a class of registers that cannot be used as the
2033 operand of a SUBREG that changes the size of the object. */
2035 #define CLASS_CANNOT_CHANGE_SIZE \
2036 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2038 /* Stack layout; function entry, exit and calling. */
2040 /* Define this if pushing a word on the stack
2041 makes the stack pointer a smaller address. */
2042 #define STACK_GROWS_DOWNWARD
2044 /* Define this if the nominal address of the stack frame
2045 is at the high-address end of the local variables;
2046 that is, each additional local variable allocated
2047 goes at a more negative offset in the frame. */
2048 /* #define FRAME_GROWS_DOWNWARD */
2050 /* Offset within stack frame to start allocating local variables at.
2051 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2052 first local allocated. Otherwise, it is the offset to the BEGINNING
2053 of the first local allocated. */
2054 #define STARTING_FRAME_OFFSET \
2055 (current_function_outgoing_args_size \
2056 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2058 /* Offset from the stack pointer register to an item dynamically
2059 allocated on the stack, e.g., by `alloca'.
2061 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2062 length of the outgoing arguments. The default is correct for most
2063 machines. See `function.c' for details.
2065 The MIPS ABI states that functions which dynamically allocate the
2066 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2067 we are trying to create a second frame pointer to the function, so
2068 allocate some stack space to make it happy.
2070 However, the linker currently complains about linking any code that
2071 dynamically allocates stack space, and there seems to be a bug in
2072 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2075 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2076 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2077 ? 4*UNITS_PER_WORD \
2078 : current_function_outgoing_args_size)
2081 /* The return address for the current frame is in r31 is this is a leaf
2082 function. Otherwise, it is on the stack. It is at a variable offset
2083 from sp/fp/ap, so we define a fake hard register rap which is a
2084 poiner to the return address on the stack. This always gets eliminated
2085 during reload to be either the frame pointer or the stack pointer plus
2088 /* ??? This definition fails for leaf functions. There is currently no
2089 general solution for this problem. */
2091 /* ??? There appears to be no way to get the return address of any previous
2092 frame except by disassembling instructions in the prologue/epilogue.
2093 So currently we support only the current frame. */
2095 #define RETURN_ADDR_RTX(count, frame) \
2097 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2100 /* Structure to be filled in by compute_frame_size with register
2101 save masks, and offsets for the current function. */
2103 struct mips_frame_info
2105 long total_size; /* # bytes that the entire frame takes up */
2106 long var_size; /* # bytes that variables take up */
2107 long args_size; /* # bytes that outgoing arguments take up */
2108 long extra_size; /* # bytes of extra gunk */
2109 int gp_reg_size; /* # bytes needed to store gp regs */
2110 int fp_reg_size; /* # bytes needed to store fp regs */
2111 long mask; /* mask of saved gp registers */
2112 long fmask; /* mask of saved fp registers */
2113 long gp_save_offset; /* offset from vfp to store gp registers */
2114 long fp_save_offset; /* offset from vfp to store fp registers */
2115 long gp_sp_offset; /* offset from new sp to store gp registers */
2116 long fp_sp_offset; /* offset from new sp to store fp registers */
2117 int initialized; /* != 0 if frame size already calculated */
2118 int num_gp; /* number of gp registers saved */
2119 int num_fp; /* number of fp registers saved */
2120 long insns_len; /* length of insns; mips16 only */
2123 extern struct mips_frame_info current_frame_info;
2125 /* If defined, this macro specifies a table of register pairs used to
2126 eliminate unneeded registers that point into the stack frame. If
2127 it is not defined, the only elimination attempted by the compiler
2128 is to replace references to the frame pointer with references to
2131 The definition of this macro is a list of structure
2132 initializations, each of which specifies an original and
2133 replacement register.
2135 On some machines, the position of the argument pointer is not
2136 known until the compilation is completed. In such a case, a
2137 separate hard register must be used for the argument pointer.
2138 This register can be eliminated by replacing it with either the
2139 frame pointer or the argument pointer, depending on whether or not
2140 the frame pointer has been eliminated.
2142 In this case, you might specify:
2143 #define ELIMINABLE_REGS \
2144 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2145 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2146 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2148 Note that the elimination of the argument pointer with the stack
2149 pointer is specified first since that is the preferred elimination.
2151 The eliminations to $17 are only used on the mips16. See the
2152 definition of HARD_FRAME_POINTER_REGNUM. */
2154 #define ELIMINABLE_REGS \
2155 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2156 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2157 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2158 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2159 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2160 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2161 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2162 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2163 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2164 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2166 /* A C expression that returns non-zero if the compiler is allowed to
2167 try to replace register number FROM-REG with register number
2168 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2169 defined, and will usually be the constant 1, since most of the
2170 cases preventing register elimination are things that the compiler
2171 already knows about.
2173 When not in mips16 and mips64, we can always eliminate to the
2174 frame pointer. We can eliminate to the stack pointer unless
2175 a frame pointer is needed. In mips16 mode, we need a frame
2176 pointer for a large frame; otherwise, reload may be unable
2177 to compute the address of a local variable, since there is
2178 no way to add a large constant to the stack pointer
2179 without using a temporary register.
2181 In mips16, for some instructions (eg lwu), we can't eliminate the
2182 frame pointer for the stack pointer. These instructions are
2183 only generated in TARGET_64BIT mode.
2186 #define CAN_ELIMINATE(FROM, TO) \
2187 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2188 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2189 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2190 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2191 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2192 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2193 && (! TARGET_MIPS16 \
2194 || compute_frame_size (get_frame_size ()) < 32768)))))
2196 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2197 specifies the initial difference between the specified pair of
2198 registers. This macro must be defined if `ELIMINABLE_REGS' is
2201 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2202 { compute_frame_size (get_frame_size ()); \
2203 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2204 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2205 (OFFSET) = - current_function_outgoing_args_size; \
2206 else if ((FROM) == FRAME_POINTER_REGNUM) \
2208 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2209 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2210 (OFFSET) = (current_frame_info.total_size \
2211 - current_function_outgoing_args_size \
2212 - ((mips_abi != ABI_32 \
2213 && mips_abi != ABI_O64 \
2214 && mips_abi != ABI_EABI) \
2215 ? current_function_pretend_args_size \
2217 else if ((FROM) == ARG_POINTER_REGNUM) \
2218 (OFFSET) = (current_frame_info.total_size \
2219 - ((mips_abi != ABI_32 \
2220 && mips_abi != ABI_O64 \
2221 && mips_abi != ABI_EABI) \
2222 ? current_function_pretend_args_size \
2224 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2225 so we must add 4 bytes to the offset to get the right value. */ \
2226 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2228 if (leaf_function_p ()) \
2230 else (OFFSET) = current_frame_info.gp_sp_offset \
2231 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2232 * (BYTES_BIG_ENDIAN != 0)); \
2236 /* If we generate an insn to push BYTES bytes,
2237 this says how many the stack pointer really advances by.
2238 On the vax, sp@- in a byte insn really pushes a word. */
2240 /* #define PUSH_ROUNDING(BYTES) 0 */
2242 /* If defined, the maximum amount of space required for outgoing
2243 arguments will be computed and placed into the variable
2244 `current_function_outgoing_args_size'. No space will be pushed
2245 onto the stack for each call; instead, the function prologue
2246 should increase the stack frame size by this amount.
2248 It is not proper to define both `PUSH_ROUNDING' and
2249 `ACCUMULATE_OUTGOING_ARGS'. */
2250 #define ACCUMULATE_OUTGOING_ARGS
2252 /* Offset from the argument pointer register to the first argument's
2253 address. On some machines it may depend on the data type of the
2256 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2257 the first argument's address.
2259 On the MIPS, we must skip the first argument position if we are
2260 returning a structure or a union, to account for its address being
2261 passed in $4. However, at the current time, this produces a compiler
2262 that can't bootstrap, so comment it out for now. */
2265 #define FIRST_PARM_OFFSET(FNDECL) \
2267 && TREE_TYPE (FNDECL) != 0 \
2268 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2269 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2270 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2274 #define FIRST_PARM_OFFSET(FNDECL) 0
2277 /* When a parameter is passed in a register, stack space is still
2278 allocated for it. For the MIPS, stack space must be allocated, cf
2279 Asm Lang Prog Guide page 7-8.
2281 BEWARE that some space is also allocated for non existing arguments
2282 in register. In case an argument list is of form GF used registers
2283 are a0 (a2,a3), but we should push over a1... */
2285 #define REG_PARM_STACK_SPACE(FNDECL) \
2286 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2288 /* Define this if it is the responsibility of the caller to
2289 allocate the area reserved for arguments passed in registers.
2290 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2291 of this macro is to determine whether the space is included in
2292 `current_function_outgoing_args_size'. */
2293 #define OUTGOING_REG_PARM_STACK_SPACE
2295 /* Align stack frames on 64 bits (Double Word ). */
2296 #ifndef STACK_BOUNDARY
2297 #define STACK_BOUNDARY 64
2300 /* Make sure 4 words are always allocated on the stack. */
2302 #ifndef STACK_ARGS_ADJUST
2303 #define STACK_ARGS_ADJUST(SIZE) \
2305 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2306 SIZE.constant = 4 * UNITS_PER_WORD; \
2311 /* A C expression that should indicate the number of bytes of its
2312 own arguments that a function pops on returning, or 0
2313 if the function pops no arguments and the caller must therefore
2314 pop them all after the function returns.
2316 FUNDECL is the declaration node of the function (as a tree).
2318 FUNTYPE is a C variable whose value is a tree node that
2319 describes the function in question. Normally it is a node of
2320 type `FUNCTION_TYPE' that describes the data type of the function.
2321 From this it is possible to obtain the data types of the value
2322 and arguments (if known).
2324 When a call to a library function is being considered, FUNTYPE
2325 will contain an identifier node for the library function. Thus,
2326 if you need to distinguish among various library functions, you
2327 can do so by their names. Note that "library function" in this
2328 context means a function used to perform arithmetic, whose name
2329 is known specially in the compiler and was not mentioned in the
2330 C code being compiled.
2332 STACK-SIZE is the number of bytes of arguments passed on the
2333 stack. If a variable number of bytes is passed, it is zero, and
2334 argument popping will always be the responsibility of the
2335 calling function. */
2337 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2340 /* Symbolic macros for the registers used to return integer and floating
2343 #define GP_RETURN (GP_REG_FIRST + 2)
2344 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2346 /* Symbolic macros for the first/last argument registers. */
2348 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2349 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2350 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2351 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2353 #define MAX_ARGS_IN_REGISTERS 4
2355 /* Define how to find the value returned by a library function
2356 assuming the value has mode MODE. Because we define
2357 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2358 PROMOTE_MODE does. */
2360 #define LIBCALL_VALUE(MODE) \
2362 ((GET_MODE_CLASS (MODE) != MODE_INT \
2363 || GET_MODE_SIZE (MODE) >= 4) \
2366 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2367 && (! TARGET_SINGLE_FLOAT \
2368 || GET_MODE_SIZE (MODE) <= 4)) \
2372 /* Define how to find the value returned by a function.
2373 VALTYPE is the data type of the value (as a tree).
2374 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2375 otherwise, FUNC is 0. */
2377 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2380 /* 1 if N is a possible register number for a function value.
2381 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2382 Currently, R2 and F0 are only implemented here (C has no complex type) */
2384 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2386 /* 1 if N is a possible register number for function argument passing.
2387 We have no FP argument registers when soft-float. When FP registers
2388 are 32 bits, we can't directly reference the odd numbered ones. */
2390 #define FUNCTION_ARG_REGNO_P(N) \
2391 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2392 || ((! TARGET_SOFT_FLOAT \
2393 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2394 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2395 && ! fixed_regs[N]))
2397 /* A C expression which can inhibit the returning of certain function
2398 values in registers, based on the type of value. A nonzero value says
2399 to return the function value in memory, just as large structures are
2400 always returned. Here TYPE will be a C expression of type
2401 `tree', representing the data type of the value.
2403 Note that values of mode `BLKmode' must be explicitly
2404 handled by this macro. Also, the option `-fpcc-struct-return'
2405 takes effect regardless of this macro. On most systems, it is
2406 possible to leave the macro undefined; this causes a default
2407 definition to be used, whose value is the constant 1 for BLKmode
2408 values, and 0 otherwise.
2410 GCC normally converts 1 byte structures into chars, 2 byte
2411 structs into shorts, and 4 byte structs into ints, and returns
2412 them this way. Defining the following macro overrides this,
2413 to give us MIPS cc compatibility. */
2415 #define RETURN_IN_MEMORY(TYPE) \
2416 (TYPE_MODE (TYPE) == BLKmode)
2418 /* A code distinguishing the floating point format of the target
2419 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2420 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2422 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2425 /* Define a data type for recording info about an argument list
2426 during the scan of that argument list. This data type should
2427 hold all necessary information about the function itself
2428 and about the args processed so far, enough to enable macros
2429 such as FUNCTION_ARG to determine where the next arg should go.
2431 On the mips16, we need to keep track of which floating point
2432 arguments were passed in general registers, but would have been
2433 passed in the FP regs if this were a 32 bit function, so that we
2434 can move them to the FP regs if we wind up calling a 32 bit
2435 function. We record this information in fp_code, encoded in base
2436 four. A zero digit means no floating point argument, a one digit
2437 means an SFmode argument, and a two digit means a DFmode argument,
2438 and a three digit is not used. The low order digit is the first
2439 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2440 an SFmode argument. ??? A more sophisticated approach will be
2441 needed if MIPS_ABI != ABI_32. */
2443 typedef struct mips_args {
2444 int gp_reg_found; /* whether a gp register was found yet */
2445 int arg_number; /* argument number */
2446 int arg_words; /* # total words the arguments take */
2447 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2448 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2449 int fp_code; /* Mode of FP arguments (mips16) */
2450 int num_adjusts; /* number of adjustments made */
2451 /* Adjustments made to args pass in regs. */
2452 /* ??? The size is doubled to work around a
2453 bug in the code that sets the adjustments
2455 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2458 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2459 for a call to a function whose data type is FNTYPE.
2460 For a library call, FNTYPE is 0.
2464 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2465 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2467 /* Update the data in CUM to advance over an argument
2468 of mode MODE and data type TYPE.
2469 (TYPE is null for libcalls where that information may not be available.) */
2471 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2472 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2474 /* Determine where to put an argument to a function.
2475 Value is zero to push the argument on the stack,
2476 or a hard register in which to store the argument.
2478 MODE is the argument's machine mode.
2479 TYPE is the data type of the argument (as a tree).
2480 This is null for libcalls where that information may
2482 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2483 the preceding args and about the function being called.
2484 NAMED is nonzero if this argument is a named parameter
2485 (otherwise it is an extra parameter matching an ellipsis). */
2487 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2488 function_arg( &CUM, MODE, TYPE, NAMED)
2490 /* For an arg passed partly in registers and partly in memory,
2491 this is the number of registers used.
2492 For args passed entirely in registers or entirely in memory, zero. */
2494 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2495 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2497 /* If defined, a C expression that gives the alignment boundary, in
2498 bits, of an argument with the specified mode and type. If it is
2499 not defined, `PARM_BOUNDARY' is used for all arguments. */
2501 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2503 ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \
2505 : TYPE_ALIGN(TYPE)) \
2506 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2508 : GET_MODE_ALIGNMENT(MODE)))
2511 /* This macro generates the assembly code for function entry.
2512 FILE is a stdio stream to output the code to.
2513 SIZE is an int: how many units of temporary storage to allocate.
2514 Refer to the array `regs_ever_live' to determine which registers
2515 to save; `regs_ever_live[I]' is nonzero if register number I
2516 is ever used in the function. This macro is responsible for
2517 knowing which registers should not be saved even if used. */
2519 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2521 /* This macro generates the assembly code for function exit,
2522 on machines that need it. If FUNCTION_EPILOGUE is not defined
2523 then individual return instructions are generated for each
2524 return statement. Args are same as for FUNCTION_PROLOGUE. */
2526 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2528 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2530 #define MUST_SAVE_REGISTER(regno) \
2531 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2532 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2533 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2535 /* ALIGN FRAMES on double word boundaries */
2536 #ifndef MIPS_STACK_ALIGN
2537 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2541 /* Define the `__builtin_va_list' type for the ABI. */
2542 #define BUILD_VA_LIST_TYPE(VALIST) \
2543 (VALIST) = mips_build_va_list ()
2545 /* Implement `va_start' for varargs and stdarg. */
2546 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2547 mips_va_start (stdarg, valist, nextarg)
2549 /* Implement `va_arg'. */
2550 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2551 mips_va_arg (valist, type)
2553 /* Output assembler code to FILE to increment profiler label # LABELNO
2554 for profiling a function entry. */
2556 #define FUNCTION_PROFILER(FILE, LABELNO) \
2558 if (TARGET_MIPS16) \
2559 sorry ("mips16 function profiling"); \
2560 fprintf (FILE, "\t.set\tnoreorder\n"); \
2561 fprintf (FILE, "\t.set\tnoat\n"); \
2562 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2563 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2564 fprintf (FILE, "\tjal\t_mcount\n"); \
2566 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2567 TARGET_64BIT ? "dsubu" : "subu", \
2568 reg_names[STACK_POINTER_REGNUM], \
2569 reg_names[STACK_POINTER_REGNUM], \
2570 Pmode == DImode ? 16 : 8); \
2571 fprintf (FILE, "\t.set\treorder\n"); \
2572 fprintf (FILE, "\t.set\tat\n"); \
2575 /* Define this macro if the code for function profiling should come
2576 before the function prologue. Normally, the profiling code comes
2579 /* #define PROFILE_BEFORE_PROLOGUE */
2581 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2582 the stack pointer does not matter. The value is tested only in
2583 functions that have frame pointers.
2584 No definition is equivalent to always zero. */
2586 #define EXIT_IGNORE_STACK 1
2589 /* A C statement to output, on the stream FILE, assembler code for a
2590 block of data that contains the constant parts of a trampoline.
2591 This code should not include a label--the label is taken care of
2594 #define TRAMPOLINE_TEMPLATE(STREAM) \
2596 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2597 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2598 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2599 if (Pmode == DImode) \
2601 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2602 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2606 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2607 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2609 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2610 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2611 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2612 if (Pmode == DImode) \
2614 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2615 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2619 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2620 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2624 /* A C expression for the size in bytes of the trampoline, as an
2627 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2629 /* Alignment required for trampolines, in bits. */
2631 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2633 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2634 program and data caches. */
2636 #ifndef CACHE_FLUSH_FUNC
2637 #define CACHE_FLUSH_FUNC "_flush_cache"
2640 /* A C statement to initialize the variable parts of a trampoline.
2641 ADDR is an RTX for the address of the trampoline; FNADDR is an
2642 RTX for the address of the nested function; STATIC_CHAIN is an
2643 RTX for the static chain value that should be passed to the
2644 function when it is called. */
2646 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2649 if (Pmode == DImode) \
2651 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2652 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2656 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2657 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2660 /* Flush both caches. We need to flush the data cache in case \
2661 the system has a write-back cache. */ \
2662 /* ??? Should check the return value for errors. */ \
2663 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2664 0, VOIDmode, 3, addr, Pmode, \
2665 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2666 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2669 /* Addressing modes, and classification of registers for them. */
2671 /* #define HAVE_POST_INCREMENT 0 */
2672 /* #define HAVE_POST_DECREMENT 0 */
2674 /* #define HAVE_PRE_DECREMENT 0 */
2675 /* #define HAVE_PRE_INCREMENT 0 */
2677 /* These assume that REGNO is a hard or pseudo reg number.
2678 They give nonzero only if REGNO is a hard reg of the suitable class
2679 or a pseudo reg currently allocated to a suitable hard reg.
2680 These definitions are NOT overridden anywhere. */
2682 #define BASE_REG_P(regno, mode) \
2684 ? (M16_REG_P (regno) \
2685 || (regno) == FRAME_POINTER_REGNUM \
2686 || (regno) == ARG_POINTER_REGNUM \
2687 || ((regno) == STACK_POINTER_REGNUM \
2688 && (GET_MODE_SIZE (mode) == 4 \
2689 || GET_MODE_SIZE (mode) == 8))) \
2692 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2693 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2696 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2697 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2699 #define REGNO_OK_FOR_INDEX_P(regno) 0
2700 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2701 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2703 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2704 and check its validity for a certain class.
2705 We have two alternate definitions for each of them.
2706 The usual definition accepts all pseudo regs; the other rejects them all.
2707 The symbol REG_OK_STRICT causes the latter definition to be used.
2709 Most source files want to accept pseudo regs in the hope that
2710 they will get allocated to the class that the insn wants them to be in.
2711 Some source files that are used after register allocation
2712 need to be strict. */
2714 #ifndef REG_OK_STRICT
2716 #define REG_OK_STRICT_P 0
2717 #define REG_OK_FOR_INDEX_P(X) 0
2718 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2719 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2723 #define REG_OK_STRICT_P 1
2724 #define REG_OK_FOR_INDEX_P(X) 0
2725 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2726 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2731 /* Maximum number of registers that can appear in a valid memory address. */
2733 #define MAX_REGS_PER_ADDRESS 1
2735 /* A C compound statement with a conditional `goto LABEL;' executed
2736 if X (an RTX) is a legitimate memory address on the target
2737 machine for a memory operand of mode MODE.
2739 It usually pays to define several simpler macros to serve as
2740 subroutines for this one. Otherwise it may be too complicated
2743 This macro must exist in two variants: a strict variant and a
2744 non-strict one. The strict variant is used in the reload pass.
2745 It must be defined so that any pseudo-register that has not been
2746 allocated a hard register is considered a memory reference. In
2747 contexts where some kind of register is required, a
2748 pseudo-register with no hard register must be rejected.
2750 The non-strict variant is used in other passes. It must be
2751 defined to accept all pseudo-registers in every context where
2752 some kind of register is required.
2754 Compiler source files that want to use the strict variant of
2755 this macro define the macro `REG_OK_STRICT'. You should use an
2756 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2757 in that case and the non-strict variant otherwise.
2759 Typically among the subroutines used to define
2760 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2761 acceptable registers for various purposes (one for base
2762 registers, one for index registers, and so on). Then only these
2763 subroutine macros need have two variants; the higher levels of
2764 macros may be the same whether strict or not.
2766 Normally, constant addresses which are the sum of a `symbol_ref'
2767 and an integer are stored inside a `const' RTX to mark them as
2768 constant. Therefore, there is no need to recognize such sums
2769 specifically as legitimate addresses. Normally you would simply
2770 recognize any `const' as legitimate.
2772 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2773 constant sums that are not marked with `const'. It assumes
2774 that a naked `plus' indicates indexing. If so, then you *must*
2775 reject such naked constant sums as illegitimate addresses, so
2776 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2778 On some machines, whether a symbolic address is legitimate
2779 depends on the section that the address refers to. On these
2780 machines, define the macro `ENCODE_SECTION_INFO' to store the
2781 information into the `symbol_ref', and then check for it here.
2782 When you see a `const', you will have to look inside it to find
2783 the `symbol_ref' in order to determine the section. */
2786 #define GO_PRINTF(x) fprintf(stderr, (x))
2787 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2788 #define GO_DEBUG_RTX(x) debug_rtx(x)
2791 #define GO_PRINTF(x)
2792 #define GO_PRINTF2(x,y)
2793 #define GO_DEBUG_RTX(x)
2796 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2798 register rtx xinsn = (X); \
2800 if (TARGET_DEBUG_B_MODE) \
2802 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2803 (REG_OK_STRICT_P) ? "" : "not "); \
2804 GO_DEBUG_RTX (xinsn); \
2807 /* Check for constant before stripping off SUBREG, so that we don't \
2808 accept (subreg (const_int)) which will fail to reload. */ \
2809 if (CONSTANT_ADDRESS_P (xinsn) \
2810 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2811 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2814 while (GET_CODE (xinsn) == SUBREG) \
2815 xinsn = SUBREG_REG (xinsn); \
2817 /* The mips16 can only use the stack pointer as a base register when \
2818 loading SImode or DImode values. */ \
2819 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2822 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2824 register rtx xlow0 = XEXP (xinsn, 0); \
2825 register rtx xlow1 = XEXP (xinsn, 1); \
2827 while (GET_CODE (xlow0) == SUBREG) \
2828 xlow0 = SUBREG_REG (xlow0); \
2829 if (GET_CODE (xlow0) == REG \
2830 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2831 && mips_check_split (xlow1, MODE)) \
2835 if (GET_CODE (xinsn) == PLUS) \
2837 register rtx xplus0 = XEXP (xinsn, 0); \
2838 register rtx xplus1 = XEXP (xinsn, 1); \
2839 register enum rtx_code code0; \
2840 register enum rtx_code code1; \
2842 while (GET_CODE (xplus0) == SUBREG) \
2843 xplus0 = SUBREG_REG (xplus0); \
2844 code0 = GET_CODE (xplus0); \
2846 while (GET_CODE (xplus1) == SUBREG) \
2847 xplus1 = SUBREG_REG (xplus1); \
2848 code1 = GET_CODE (xplus1); \
2850 /* The mips16 can only use the stack pointer as a base register \
2851 when loading SImode or DImode values. */ \
2852 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2854 if (code1 == CONST_INT \
2855 && INTVAL (xplus1) >= -32768 \
2856 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2859 /* On the mips16, we represent GP relative offsets in RTL. \
2860 These are 16 bit signed values, and can serve as register \
2863 && mips16_gp_offset_p (xplus1)) \
2866 /* For some code sequences, you actually get better code by \
2867 pretending that the MIPS supports an address mode of a \
2868 constant address + a register, even though the real \
2869 machine doesn't support it. This is because the \
2870 assembler can use $r1 to load just the high 16 bits, add \
2871 in the register, and fold the low 16 bits into the memory \
2872 reference, whereas the compiler generates a 4 instruction \
2873 sequence. On the other hand, CSE is not as effective. \
2874 It would be a win to generate the lui directly, but the \
2875 MIPS assembler does not have syntax to generate the \
2876 appropriate relocation. */ \
2878 /* Also accept CONST_INT addresses here, so no else. */ \
2879 /* Reject combining an embedded PIC text segment reference \
2880 with a register. That requires an additional \
2882 /* ??? Reject combining an address with a register for the MIPS \
2883 64 bit ABI, because the SGI assembler can not handle this. */ \
2884 if (!TARGET_DEBUG_A_MODE \
2885 && (mips_abi == ABI_32 \
2886 || mips_abi == ABI_O64 \
2887 || mips_abi == ABI_EABI) \
2888 && CONSTANT_ADDRESS_P (xplus1) \
2889 && ! mips_split_addresses \
2890 && (!TARGET_EMBEDDED_PIC \
2892 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2893 && !TARGET_MIPS16) \
2898 if (TARGET_DEBUG_B_MODE) \
2899 GO_PRINTF ("Not a legitimate address\n"); \
2903 /* A C expression that is 1 if the RTX X is a constant which is a
2904 valid address. This is defined to be the same as `CONSTANT_P (X)',
2905 but rejecting CONST_DOUBLE. */
2906 /* When pic, we must reject addresses of the form symbol+large int.
2907 This is because an instruction `sw $4,s+70000' needs to be converted
2908 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2909 assembler would use $at as a temp to load in the large offset. In this
2910 case $at is already in use. We convert such problem addresses to
2911 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2912 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2913 #define CONSTANT_ADDRESS_P(X) \
2914 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2915 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2916 || (GET_CODE (X) == CONST \
2917 && ! (flag_pic && pic_address_needs_scratch (X)) \
2918 && (mips_abi == ABI_32 \
2919 || mips_abi == ABI_O64 \
2920 || mips_abi == ABI_EABI))) \
2921 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2923 /* Define this, so that when PIC, reload won't try to reload invalid
2924 addresses which require two reload registers. */
2926 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2928 /* Nonzero if the constant value X is a legitimate general operand.
2929 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2931 At present, GAS doesn't understand li.[sd], so don't allow it
2932 to be generated at present. Also, the MIPS assembler does not
2933 grok li.d Infinity. */
2935 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2936 #define LEGITIMATE_CONSTANT_P(X) \
2937 ((GET_CODE (X) != CONST_DOUBLE \
2938 || mips_const_double_ok (X, GET_MODE (X))) \
2939 && ! (GET_CODE (X) == CONST \
2940 && mips_abi != ABI_32 \
2941 && mips_abi != ABI_O64 \
2942 && mips_abi != ABI_EABI) \
2943 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2945 /* A C compound statement that attempts to replace X with a valid
2946 memory address for an operand of mode MODE. WIN will be a C
2947 statement label elsewhere in the code; the macro definition may
2950 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2952 to avoid further processing if the address has become legitimate.
2954 X will always be the result of a call to `break_out_memory_refs',
2955 and OLDX will be the operand that was given to that function to
2958 The code generated by this macro should not alter the
2959 substructure of X. If it transforms X into a more legitimate
2960 form, it should assign X (which will always be a C variable) a
2963 It is not necessary for this macro to come up with a legitimate
2964 address. The compiler has standard ways of doing so in all
2965 cases. In fact, it is safe for this macro to do nothing. But
2966 often a machine-dependent strategy can generate better code.
2968 For the MIPS, transform:
2970 memory(X + <large int>)
2974 Y = <large int> & ~0x7fff;
2976 memory (Z + (<large int> & 0x7fff));
2978 This is for CSE to find several similar references, and only use one Z.
2980 When PIC, convert addresses of the form memory (symbol+large int) to
2981 memory (reg+large int). */
2984 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2986 register rtx xinsn = (X); \
2988 if (TARGET_DEBUG_B_MODE) \
2990 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2991 GO_DEBUG_RTX (xinsn); \
2994 if (mips_split_addresses && mips_check_split (X, MODE)) \
2996 /* ??? Is this ever executed? */ \
2997 X = gen_rtx_LO_SUM (Pmode, \
2998 copy_to_mode_reg (Pmode, \
2999 gen_rtx (HIGH, Pmode, X)), \
3004 if (GET_CODE (xinsn) == CONST \
3005 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3006 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3007 || (mips_abi != ABI_32 \
3008 && mips_abi != ABI_O64 \
3009 && mips_abi != ABI_EABI))) \
3011 rtx ptr_reg = gen_reg_rtx (Pmode); \
3012 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3014 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3016 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3017 if (SMALL_INT (constant)) \
3019 /* Otherwise we fall through so the code below will fix the \
3024 if (GET_CODE (xinsn) == PLUS) \
3026 register rtx xplus0 = XEXP (xinsn, 0); \
3027 register rtx xplus1 = XEXP (xinsn, 1); \
3028 register enum rtx_code code0 = GET_CODE (xplus0); \
3029 register enum rtx_code code1 = GET_CODE (xplus1); \
3031 if (code0 != REG && code1 == REG) \
3033 xplus0 = XEXP (xinsn, 1); \
3034 xplus1 = XEXP (xinsn, 0); \
3035 code0 = GET_CODE (xplus0); \
3036 code1 = GET_CODE (xplus1); \
3039 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3040 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3042 rtx int_reg = gen_reg_rtx (Pmode); \
3043 rtx ptr_reg = gen_reg_rtx (Pmode); \
3045 emit_move_insn (int_reg, \
3046 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3048 emit_insn (gen_rtx_SET (VOIDmode, \
3050 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3052 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3057 if (TARGET_DEBUG_B_MODE) \
3058 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3062 /* A C statement or compound statement with a conditional `goto
3063 LABEL;' executed if memory address X (an RTX) can have different
3064 meanings depending on the machine mode of the memory reference it
3067 Autoincrement and autodecrement addresses typically have
3068 mode-dependent effects because the amount of the increment or
3069 decrement is the size of the operand being addressed. Some
3070 machines have other mode-dependent addresses. Many RISC machines
3071 have no mode-dependent addresses.
3073 You may assume that ADDR is a valid address for the machine. */
3075 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3078 /* Define this macro if references to a symbol must be treated
3079 differently depending on something about the variable or
3080 function named by the symbol (such as what section it is in).
3082 The macro definition, if any, is executed immediately after the
3083 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3084 The value of the rtl will be a `mem' whose address is a
3087 The usual thing for this macro to do is to a flag in the
3088 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3089 name string in the `symbol_ref' (if one bit is not enough
3092 The best way to modify the name string is by adding text to the
3093 beginning, with suitable punctuation to prevent any ambiguity.
3094 Allocate the new name in `saveable_obstack'. You will have to
3095 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3096 and output the name accordingly.
3098 You can also check the information stored in the `symbol_ref' in
3099 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3100 `PRINT_OPERAND_ADDRESS'.
3102 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3105 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3106 symbols which are not in the .text section.
3108 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3109 constants which are put in the .text section. We also record the
3110 total length of all such strings; this total is used to decide
3111 whether we need to split the constant table, and need not be
3114 When not mips16 code nor embedded PIC, if a symbol is in a
3115 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3116 splitting the reference so that gas can generate a gp relative
3119 When TARGET_EMBEDDED_DATA is set, we assume that all const
3120 variables will be stored in ROM, which is too far from %gp to use
3121 %gprel addressing. Note that (1) we include "extern const"
3122 variables in this, which mips_select_section doesn't, and (2) we
3123 can't always tell if they're really const (they might be const C++
3124 objects with non-const constructors), so we err on the side of
3125 caution and won't use %gprel anyway (otherwise we'd have to defer
3126 this decision to the linker/loader). The handling of extern consts
3127 is why the DECL_INITIAL macros differ from mips_select_section.
3129 If you are changing this macro, you should look at
3130 mips_select_section and see if it needs a similar change. */
3132 #ifndef UNIQUE_SECTION_P
3133 #define UNIQUE_SECTION_P(DECL) (0)
3136 #define ENCODE_SECTION_INFO(DECL) \
3139 if (TARGET_MIPS16) \
3141 if (TREE_CODE (DECL) == STRING_CST \
3142 && ! flag_writable_strings \
3143 /* If this string is from a function, and the function will \
3144 go in a gnu linkonce section, then we can't directly \
3145 access the string. This gets an assembler error \
3146 "unsupported PC relative reference to different section".\
3147 If we modify SELECT_SECTION to put it in function_section\
3148 instead of text_section, it still fails because \
3149 DECL_SECTION_NAME isn't set until assemble_start_function.\
3150 If we fix that, it still fails because strings are shared\
3151 among multiple functions, and we have cross section \
3152 references again. We force it to work by putting string \
3153 addresses in the constant pool and indirecting. */ \
3154 && (! current_function_decl \
3155 || ! UNIQUE_SECTION_P (current_function_decl))) \
3157 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3158 mips_string_length += TREE_STRING_LENGTH (DECL); \
3162 if (TARGET_EMBEDDED_DATA \
3163 && (TREE_CODE (DECL) == VAR_DECL \
3164 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3165 && (!DECL_INITIAL (DECL) \
3166 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3168 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3171 else if (TARGET_EMBEDDED_PIC) \
3173 if (TREE_CODE (DECL) == VAR_DECL) \
3174 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3175 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3176 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3177 else if (TREE_CODE (DECL) == STRING_CST \
3178 && ! flag_writable_strings) \
3179 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3181 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3184 else if (TREE_CODE (DECL) == VAR_DECL \
3185 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3186 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3188 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3191 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3194 /* We can not perform GP optimizations on variables which are in \
3195 specific sections, except for .sdata and .sbss which are \
3197 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3198 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3200 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3202 if (size > 0 && size <= mips_section_threshold) \
3203 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3206 else if (HALF_PIC_P ()) \
3208 HALF_PIC_ENCODE (DECL); \
3213 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3214 'the start of the function that this code is output in'. */
3216 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3217 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3218 asm_fprintf ((FILE), "%U%s", \
3219 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3221 asm_fprintf ((FILE), "%U%s", (NAME))
3223 /* The mips16 wants the constant pool to be after the function,
3224 because the PC relative load instructions use unsigned offsets. */
3226 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3228 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3229 mips_string_length = 0;
3232 /* In mips16 mode, put most string constants after the function. */
3233 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3234 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3237 /* Specify the machine mode that this machine uses
3238 for the index in the tablejump instruction.
3239 ??? Using HImode in mips16 mode can cause overflow. However, the
3240 overflow is no more likely than the overflow in a branch
3241 instruction. Large functions can currently break in both ways. */
3242 #define CASE_VECTOR_MODE \
3243 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3245 /* Define as C expression which evaluates to nonzero if the tablejump
3246 instruction expects the table to contain offsets from the address of the
3248 Do not define this if the table should contain absolute addresses. */
3249 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3251 /* Specify the tree operation to be used to convert reals to integers. */
3252 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3254 /* This is the kind of divide that is easiest to do in the general case. */
3255 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3257 /* Define this as 1 if `char' should by default be signed; else as 0. */
3258 #ifndef DEFAULT_SIGNED_CHAR
3259 #define DEFAULT_SIGNED_CHAR 1
3262 /* Max number of bytes we can move from memory to memory
3263 in one reasonably fast instruction. */
3264 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3265 #define MAX_MOVE_MAX 8
3267 /* Define this macro as a C expression which is nonzero if
3268 accessing less than a word of memory (i.e. a `char' or a
3269 `short') is no faster than accessing a word of memory, i.e., if
3270 such access require more than one instruction or if there is no
3271 difference in cost between byte and (aligned) word loads.
3273 On RISC machines, it tends to generate better code to define
3274 this as 1, since it avoids making a QI or HI mode register. */
3275 #define SLOW_BYTE_ACCESS 1
3277 /* We assume that the store-condition-codes instructions store 0 for false
3278 and some other value for true. This is the value stored for true. */
3280 #define STORE_FLAG_VALUE 1
3282 /* Define this if zero-extension is slow (more than one real instruction). */
3283 #define SLOW_ZERO_EXTEND
3285 /* Define this to be nonzero if shift instructions ignore all but the low-order
3287 #define SHIFT_COUNT_TRUNCATED 1
3289 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3290 is done just by pretending it is already truncated. */
3291 /* In 64 bit mode, 32 bit instructions require that register values be properly
3292 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3293 converts a value >32 bits to a value <32 bits. */
3294 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3295 Something needs to be done about this. Perhaps not use any 32 bit
3296 instructions? Perhaps use PROMOTE_MODE? */
3297 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3298 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3300 /* Specify the machine mode that pointers have.
3301 After generation of rtl, the compiler makes no further distinction
3302 between pointers and any other objects of this machine mode.
3304 For MIPS we make pointers are the smaller of longs and gp-registers. */
3307 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3310 /* A function address in a call instruction
3311 is a word address (for indexing purposes)
3312 so give the MEM rtx a words's mode. */
3314 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3316 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3317 memset, instead of the BSD functions bcopy and bzero. */
3319 #if defined(MIPS_SYSV) || defined(OSF_OS)
3320 #define TARGET_MEM_FUNCTIONS
3324 /* A part of a C `switch' statement that describes the relative
3325 costs of constant RTL expressions. It must contain `case'
3326 labels for expression codes `const_int', `const', `symbol_ref',
3327 `label_ref' and `const_double'. Each case must ultimately reach
3328 a `return' statement to return the relative cost of the use of
3329 that kind of constant value in an expression. The cost may
3330 depend on the precise value of the constant, which is available
3331 for examination in X.
3333 CODE is the expression code--redundant, since it can be obtained
3334 with `GET_CODE (X)'. */
3336 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3338 if (! TARGET_MIPS16) \
3340 /* Always return 0, since we don't have different sized \
3341 instructions, hence different costs according to Richard \
3345 if ((OUTER_CODE) == SET) \
3347 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3349 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3350 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3351 return COSTS_N_INSNS (1); \
3353 return COSTS_N_INSNS (2); \
3355 /* A PLUS could be an address. We don't want to force an address \
3356 to use a register, so accept any signed 16 bit value without \
3358 if ((OUTER_CODE) == PLUS \
3359 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3361 /* A number between 1 and 8 inclusive is efficient for a shift. \
3362 Otherwise, we will need an extended instruction. */ \
3363 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3364 || (OUTER_CODE) == LSHIFTRT) \
3366 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3368 return COSTS_N_INSNS (1); \
3370 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3371 if ((OUTER_CODE) == XOR \
3372 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3374 /* We may be able to use slt or sltu for a comparison with a \
3375 signed 16 bit value. (The boundary conditions aren't quite \
3376 right, but this is just a heuristic anyhow.) */ \
3377 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3378 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3379 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3380 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3381 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3383 /* Equality comparisons with 0 are cheap. */ \
3384 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3385 && INTVAL (X) == 0) \
3388 /* Otherwise, work out the cost to load the value into a \
3390 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3391 return COSTS_N_INSNS (1); \
3392 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3393 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3394 return COSTS_N_INSNS (2); \
3396 return COSTS_N_INSNS (3); \
3399 return COSTS_N_INSNS (2); \
3403 rtx offset = const0_rtx; \
3404 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3406 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3408 /* Treat this like a signed 16 bit CONST_INT. */ \
3409 if ((OUTER_CODE) == PLUS) \
3411 else if ((OUTER_CODE) == SET) \
3412 return COSTS_N_INSNS (1); \
3414 return COSTS_N_INSNS (2); \
3417 if (GET_CODE (symref) == LABEL_REF) \
3418 return COSTS_N_INSNS (2); \
3420 if (GET_CODE (symref) != SYMBOL_REF) \
3421 return COSTS_N_INSNS (4); \
3423 /* let's be paranoid.... */ \
3424 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3425 return COSTS_N_INSNS (2); \
3427 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3431 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3433 case CONST_DOUBLE: \
3436 if (TARGET_MIPS16) \
3437 return COSTS_N_INSNS (4); \
3438 split_double (X, &high, &low); \
3439 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3440 || low == CONST0_RTX (GET_MODE (low))) \
3444 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3445 This can be used, for example, to indicate how costly a multiply
3446 instruction is. In writing this macro, you can use the construct
3447 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3449 This macro is optional; do not define it if the default cost
3450 assumptions are adequate for the target machine.
3452 If -mdebugd is used, change the multiply cost to 2, so multiply by
3453 a constant isn't converted to a series of shifts. This helps
3454 strength reduction, and also makes it easier to identify what the
3455 compiler is doing. */
3457 /* ??? Fix this to be right for the R8000. */
3458 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3461 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3462 if (simple_memory_operand (X, GET_MODE (X))) \
3463 return COSTS_N_INSNS (num_words); \
3465 return COSTS_N_INSNS (2*num_words); \
3469 return COSTS_N_INSNS (6); \
3472 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3477 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3478 return COSTS_N_INSNS (2); \
3485 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3486 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3492 enum machine_mode xmode = GET_MODE (X); \
3493 if (xmode == SFmode || xmode == DFmode) \
3494 return COSTS_N_INSNS (1); \
3496 return COSTS_N_INSNS (4); \
3502 enum machine_mode xmode = GET_MODE (X); \
3503 if (xmode == SFmode || xmode == DFmode) \
3505 if (mips_cpu == PROCESSOR_R3000 \
3506 || mips_cpu == PROCESSOR_R3900) \
3507 return COSTS_N_INSNS (2); \
3508 else if (mips_cpu == PROCESSOR_R6000) \
3509 return COSTS_N_INSNS (3); \
3511 return COSTS_N_INSNS (6); \
3514 if (xmode == DImode && !TARGET_64BIT) \
3515 return COSTS_N_INSNS (4); \
3521 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3528 enum machine_mode xmode = GET_MODE (X); \
3529 if (xmode == SFmode) \
3531 if (mips_cpu == PROCESSOR_R3000 \
3532 || mips_cpu == PROCESSOR_R3900 \
3533 || mips_cpu == PROCESSOR_R5000) \
3534 return COSTS_N_INSNS (4); \
3535 else if (mips_cpu == PROCESSOR_R6000) \
3536 return COSTS_N_INSNS (5); \
3538 return COSTS_N_INSNS (7); \
3541 if (xmode == DFmode) \
3543 if (mips_cpu == PROCESSOR_R3000 \
3544 || mips_cpu == PROCESSOR_R3900 \
3545 || mips_cpu == PROCESSOR_R5000) \
3546 return COSTS_N_INSNS (5); \
3547 else if (mips_cpu == PROCESSOR_R6000) \
3548 return COSTS_N_INSNS (6); \
3550 return COSTS_N_INSNS (8); \
3553 if (mips_cpu == PROCESSOR_R3000) \
3554 return COSTS_N_INSNS (12); \
3555 else if (mips_cpu == PROCESSOR_R3900) \
3556 return COSTS_N_INSNS (2); \
3557 else if (mips_cpu == PROCESSOR_R6000) \
3558 return COSTS_N_INSNS (17); \
3559 else if (mips_cpu == PROCESSOR_R5000) \
3560 return COSTS_N_INSNS (5); \
3562 return COSTS_N_INSNS (10); \
3568 enum machine_mode xmode = GET_MODE (X); \
3569 if (xmode == SFmode) \
3571 if (mips_cpu == PROCESSOR_R3000 \
3572 || mips_cpu == PROCESSOR_R3900) \
3573 return COSTS_N_INSNS (12); \
3574 else if (mips_cpu == PROCESSOR_R6000) \
3575 return COSTS_N_INSNS (15); \
3577 return COSTS_N_INSNS (23); \
3580 if (xmode == DFmode) \
3582 if (mips_cpu == PROCESSOR_R3000 \
3583 || mips_cpu == PROCESSOR_R3900) \
3584 return COSTS_N_INSNS (19); \
3585 else if (mips_cpu == PROCESSOR_R6000) \
3586 return COSTS_N_INSNS (16); \
3588 return COSTS_N_INSNS (36); \
3591 /* fall through */ \
3595 if (mips_cpu == PROCESSOR_R3000 \
3596 || mips_cpu == PROCESSOR_R3900) \
3597 return COSTS_N_INSNS (35); \
3598 else if (mips_cpu == PROCESSOR_R6000) \
3599 return COSTS_N_INSNS (38); \
3600 else if (mips_cpu == PROCESSOR_R5000) \
3601 return COSTS_N_INSNS (36); \
3603 return COSTS_N_INSNS (69); \
3606 /* A sign extend from SImode to DImode in 64 bit mode is often \
3607 zero instructions, because the result can often be used \
3608 directly by another instruction; we'll call it one. */ \
3609 if (TARGET_64BIT && GET_MODE (X) == DImode \
3610 && GET_MODE (XEXP (X, 0)) == SImode) \
3611 return COSTS_N_INSNS (1); \
3613 return COSTS_N_INSNS (2); \
3616 if (TARGET_64BIT && GET_MODE (X) == DImode \
3617 && GET_MODE (XEXP (X, 0)) == SImode) \
3618 return COSTS_N_INSNS (2); \
3620 return COSTS_N_INSNS (1);
3622 /* An expression giving the cost of an addressing mode that
3623 contains ADDRESS. If not defined, the cost is computed from the
3624 form of the ADDRESS expression and the `CONST_COSTS' values.
3626 For most CISC machines, the default cost is a good approximation
3627 of the true cost of the addressing mode. However, on RISC
3628 machines, all instructions normally have the same length and
3629 execution time. Hence all addresses will have equal costs.
3631 In cases where more than one form of an address is known, the
3632 form with the lowest cost will be used. If multiple forms have
3633 the same, lowest, cost, the one that is the most complex will be
3636 For example, suppose an address that is equal to the sum of a
3637 register and a constant is used twice in the same basic block.
3638 When this macro is not defined, the address will be computed in
3639 a register and memory references will be indirect through that
3640 register. On machines where the cost of the addressing mode
3641 containing the sum is no higher than that of a simple indirect
3642 reference, this will produce an additional instruction and
3643 possibly require an additional register. Proper specification
3644 of this macro eliminates this overhead for such machines.
3646 Similar use of this macro is made in strength reduction of loops.
3648 ADDRESS need not be valid as an address. In such a case, the
3649 cost is not relevant and can be any value; invalid addresses
3650 need not be assigned a different cost.
3652 On machines where an address involving more than one register is
3653 as cheap as an address computation involving only one register,
3654 defining `ADDRESS_COST' to reflect this can cause two registers
3655 to be live over a region of code where only one would have been
3656 if `ADDRESS_COST' were not defined in that manner. This effect
3657 should be considered in the definition of this macro.
3658 Equivalent costs should probably only be given to addresses with
3659 different numbers of registers on machines with lots of registers.
3661 This macro will normally either not be defined or be defined as
3664 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3666 /* A C expression for the cost of moving data from a register in
3667 class FROM to one in class TO. The classes are expressed using
3668 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3669 the default; other values are interpreted relative to that.
3671 It is not required that the cost always equal 2 when FROM is the
3672 same as TO; on some machines it is expensive to move between
3673 registers if they are not general registers.
3675 If reload sees an insn consisting of a single `set' between two
3676 hard registers, and if `REGISTER_MOVE_COST' applied to their
3677 classes returns a value of 2, reload does not check to ensure
3678 that the constraints of the insn are met. Setting a cost of
3679 other than 2 will allow reload to verify that the constraints are
3680 met. You should do this if the `movM' pattern's constraints do
3681 not allow such copying.
3683 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3684 registers the same as for one of moving general registers to
3685 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3686 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3687 isn't clear if it is wise. And it might not work in all cases. We
3688 could solve the DImode LO reg problem by using a multiply, just like
3689 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3690 by using divide instructions. divu puts the remainder in the HI
3691 reg, so doing a divide by -1 will move the value in the HI reg for
3692 all values except -1. We could handle that case by using a signed
3693 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3694 compare/branch to test the input value to see which instruction we
3695 need to use. This gets pretty messy, but it is feasible. */
3697 #define REGISTER_MOVE_COST(FROM, TO) \
3698 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3699 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3700 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3701 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3702 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3703 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3704 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3705 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3706 : (((FROM) == HI_REG || (FROM) == LO_REG \
3707 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3708 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3709 : (((FROM) == HI_REG || (FROM) == LO_REG \
3710 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3711 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3712 : (((TO) == HI_REG || (TO) == LO_REG \
3713 || (TO) == MD_REGS || (TO) == HILO_REG) \
3714 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3715 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3716 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3719 /* ??? Fix this to be right for the R8000. */
3720 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3721 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3722 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3724 /* Define if copies to/from condition code registers should be avoided.
3726 This is needed for the MIPS because reload_outcc is not complete;
3727 it needs to handle cases where the source is a general or another
3728 condition code register. */
3729 #define AVOID_CCMODE_COPIES
3731 /* A C expression for the cost of a branch instruction. A value of
3732 1 is the default; other values are interpreted relative to that. */
3734 /* ??? Fix this to be right for the R8000. */
3735 #define BRANCH_COST \
3737 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3740 /* A C statement (sans semicolon) to update the integer variable COST
3741 based on the relationship between INSN that is dependent on
3742 DEP_INSN through the dependence LINK. The default is to make no
3743 adjustment to COST. On the MIPS, ignore the cost of anti- and
3744 output-dependencies. */
3746 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3747 if (REG_NOTE_KIND (LINK) != 0) \
3748 (COST) = 0; /* Anti or output dependence. */
3750 /* If defined, modifies the length assigned to instruction INSN as a
3751 function of the context in which it is used. LENGTH is an lvalue
3752 that contains the initially computed length of the insn and should
3753 be updated with the correct length of the insn. */
3754 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3755 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3758 /* Optionally define this if you have added predicates to
3759 `MACHINE.c'. This macro is called within an initializer of an
3760 array of structures. The first field in the structure is the
3761 name of a predicate and the second field is an array of rtl
3762 codes. For each predicate, list all rtl codes that can be in
3763 expressions matched by the predicate. The list should have a
3764 trailing comma. Here is an example of two entries in the list
3765 for a typical RISC machine:
3767 #define PREDICATE_CODES \
3768 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3769 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3771 Defining this macro does not affect the generated code (however,
3772 incorrect definitions that omit an rtl code that may be matched
3773 by the predicate can cause the compiler to malfunction).
3774 Instead, it allows the table built by `genrecog' to be more
3775 compact and efficient, thus speeding up the compiler. The most
3776 important predicates to include in the list specified by this
3777 macro are thoses used in the most insn patterns. */
3779 #define PREDICATE_CODES \
3780 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3781 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3782 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3783 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3784 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3785 {"small_int", { CONST_INT }}, \
3786 {"large_int", { CONST_INT }}, \
3787 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3788 {"const_float_1_operand", { CONST_DOUBLE }}, \
3789 {"simple_memory_operand", { MEM, SUBREG }}, \
3790 {"equality_op", { EQ, NE }}, \
3791 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3793 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3794 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3795 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3796 SYMBOL_REF, LABEL_REF, SUBREG, \
3798 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3799 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3800 MEM, SIGN_EXTEND }}, \
3801 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3802 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3804 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3806 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3808 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3809 SYMBOL_REF, LABEL_REF, SUBREG, \
3810 REG, SIGN_EXTEND }}, \
3811 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3812 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3813 CONST_DOUBLE, CONST }}, \
3814 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3815 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3817 /* A list of predicates that do special things with modes, and so
3818 should not elicit warnings for VOIDmode match_operand. */
3820 #define SPECIAL_MODE_PREDICATES \
3821 "pc_or_label_operand",
3824 /* If defined, a C statement to be executed just prior to the
3825 output of assembler code for INSN, to modify the extracted
3826 operands so they will be output differently.
3828 Here the argument OPVEC is the vector containing the operands
3829 extracted from INSN, and NOPERANDS is the number of elements of
3830 the vector which contain meaningful data for this insn. The
3831 contents of this vector are what will be used to convert the
3832 insn template into assembler code, so you can change the
3833 assembler output by changing the contents of the vector.
3835 We use it to check if the current insn needs a nop in front of it
3836 because of load delays, and also to update the delay slot
3839 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3840 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3843 /* Control the assembler format that we output. */
3845 /* Output at beginning of assembler file.
3846 If we are optimizing to use the global pointer, create a temporary
3847 file to hold all of the text stuff, and write it out to the end.
3848 This is needed because the MIPS assembler is evidently one pass,
3849 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3850 declaration when the code is processed, it generates a two
3851 instruction sequence. */
3853 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3855 /* Output to assembler file text saying following lines
3856 may contain character constants, extra white space, comments, etc. */
3858 #define ASM_APP_ON " #APP\n"
3860 /* Output to assembler file text saying following lines
3861 no longer contain unusual constructs. */
3863 #define ASM_APP_OFF " #NO_APP\n"
3865 /* How to refer to registers in assembler output.
3866 This sequence is indexed by compiler's hard-register-number (see above).
3868 In order to support the two different conventions for register names,
3869 we use the name of a table set up in mips.c, which is overwritten
3870 if -mrnames is used. */
3872 #define REGISTER_NAMES \
3874 &mips_reg_names[ 0][0], \
3875 &mips_reg_names[ 1][0], \
3876 &mips_reg_names[ 2][0], \
3877 &mips_reg_names[ 3][0], \
3878 &mips_reg_names[ 4][0], \
3879 &mips_reg_names[ 5][0], \
3880 &mips_reg_names[ 6][0], \
3881 &mips_reg_names[ 7][0], \
3882 &mips_reg_names[ 8][0], \
3883 &mips_reg_names[ 9][0], \
3884 &mips_reg_names[10][0], \
3885 &mips_reg_names[11][0], \
3886 &mips_reg_names[12][0], \
3887 &mips_reg_names[13][0], \
3888 &mips_reg_names[14][0], \
3889 &mips_reg_names[15][0], \
3890 &mips_reg_names[16][0], \
3891 &mips_reg_names[17][0], \
3892 &mips_reg_names[18][0], \
3893 &mips_reg_names[19][0], \
3894 &mips_reg_names[20][0], \
3895 &mips_reg_names[21][0], \
3896 &mips_reg_names[22][0], \
3897 &mips_reg_names[23][0], \
3898 &mips_reg_names[24][0], \
3899 &mips_reg_names[25][0], \
3900 &mips_reg_names[26][0], \
3901 &mips_reg_names[27][0], \
3902 &mips_reg_names[28][0], \
3903 &mips_reg_names[29][0], \
3904 &mips_reg_names[30][0], \
3905 &mips_reg_names[31][0], \
3906 &mips_reg_names[32][0], \
3907 &mips_reg_names[33][0], \
3908 &mips_reg_names[34][0], \
3909 &mips_reg_names[35][0], \
3910 &mips_reg_names[36][0], \
3911 &mips_reg_names[37][0], \
3912 &mips_reg_names[38][0], \
3913 &mips_reg_names[39][0], \
3914 &mips_reg_names[40][0], \
3915 &mips_reg_names[41][0], \
3916 &mips_reg_names[42][0], \
3917 &mips_reg_names[43][0], \
3918 &mips_reg_names[44][0], \
3919 &mips_reg_names[45][0], \
3920 &mips_reg_names[46][0], \
3921 &mips_reg_names[47][0], \
3922 &mips_reg_names[48][0], \
3923 &mips_reg_names[49][0], \
3924 &mips_reg_names[50][0], \
3925 &mips_reg_names[51][0], \
3926 &mips_reg_names[52][0], \
3927 &mips_reg_names[53][0], \
3928 &mips_reg_names[54][0], \
3929 &mips_reg_names[55][0], \
3930 &mips_reg_names[56][0], \
3931 &mips_reg_names[57][0], \
3932 &mips_reg_names[58][0], \
3933 &mips_reg_names[59][0], \
3934 &mips_reg_names[60][0], \
3935 &mips_reg_names[61][0], \
3936 &mips_reg_names[62][0], \
3937 &mips_reg_names[63][0], \
3938 &mips_reg_names[64][0], \
3939 &mips_reg_names[65][0], \
3940 &mips_reg_names[66][0], \
3941 &mips_reg_names[67][0], \
3942 &mips_reg_names[68][0], \
3943 &mips_reg_names[69][0], \
3944 &mips_reg_names[70][0], \
3945 &mips_reg_names[71][0], \
3946 &mips_reg_names[72][0], \
3947 &mips_reg_names[73][0], \
3948 &mips_reg_names[74][0], \
3949 &mips_reg_names[75][0], \
3952 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3953 So define this for it. */
3954 #define DEBUG_REGISTER_NAMES \
3956 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3957 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3958 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3959 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3960 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3961 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3962 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3963 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3964 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3965 "$fcc5","$fcc6","$fcc7","$rap" \
3968 /* If defined, a C initializer for an array of structures
3969 containing a name and a register number. This macro defines
3970 additional names for hard registers, thus allowing the `asm'
3971 option in declarations to refer to registers using alternate
3974 We define both names for the integer registers here. */
3976 #define ADDITIONAL_REGISTER_NAMES \
3978 { "$0", 0 + GP_REG_FIRST }, \
3979 { "$1", 1 + GP_REG_FIRST }, \
3980 { "$2", 2 + GP_REG_FIRST }, \
3981 { "$3", 3 + GP_REG_FIRST }, \
3982 { "$4", 4 + GP_REG_FIRST }, \
3983 { "$5", 5 + GP_REG_FIRST }, \
3984 { "$6", 6 + GP_REG_FIRST }, \
3985 { "$7", 7 + GP_REG_FIRST }, \
3986 { "$8", 8 + GP_REG_FIRST }, \
3987 { "$9", 9 + GP_REG_FIRST }, \
3988 { "$10", 10 + GP_REG_FIRST }, \
3989 { "$11", 11 + GP_REG_FIRST }, \
3990 { "$12", 12 + GP_REG_FIRST }, \
3991 { "$13", 13 + GP_REG_FIRST }, \
3992 { "$14", 14 + GP_REG_FIRST }, \
3993 { "$15", 15 + GP_REG_FIRST }, \
3994 { "$16", 16 + GP_REG_FIRST }, \
3995 { "$17", 17 + GP_REG_FIRST }, \
3996 { "$18", 18 + GP_REG_FIRST }, \
3997 { "$19", 19 + GP_REG_FIRST }, \
3998 { "$20", 20 + GP_REG_FIRST }, \
3999 { "$21", 21 + GP_REG_FIRST }, \
4000 { "$22", 22 + GP_REG_FIRST }, \
4001 { "$23", 23 + GP_REG_FIRST }, \
4002 { "$24", 24 + GP_REG_FIRST }, \
4003 { "$25", 25 + GP_REG_FIRST }, \
4004 { "$26", 26 + GP_REG_FIRST }, \
4005 { "$27", 27 + GP_REG_FIRST }, \
4006 { "$28", 28 + GP_REG_FIRST }, \
4007 { "$29", 29 + GP_REG_FIRST }, \
4008 { "$30", 30 + GP_REG_FIRST }, \
4009 { "$31", 31 + GP_REG_FIRST }, \
4010 { "$sp", 29 + GP_REG_FIRST }, \
4011 { "$fp", 30 + GP_REG_FIRST }, \
4012 { "at", 1 + GP_REG_FIRST }, \
4013 { "v0", 2 + GP_REG_FIRST }, \
4014 { "v1", 3 + GP_REG_FIRST }, \
4015 { "a0", 4 + GP_REG_FIRST }, \
4016 { "a1", 5 + GP_REG_FIRST }, \
4017 { "a2", 6 + GP_REG_FIRST }, \
4018 { "a3", 7 + GP_REG_FIRST }, \
4019 { "t0", 8 + GP_REG_FIRST }, \
4020 { "t1", 9 + GP_REG_FIRST }, \
4021 { "t2", 10 + GP_REG_FIRST }, \
4022 { "t3", 11 + GP_REG_FIRST }, \
4023 { "t4", 12 + GP_REG_FIRST }, \
4024 { "t5", 13 + GP_REG_FIRST }, \
4025 { "t6", 14 + GP_REG_FIRST }, \
4026 { "t7", 15 + GP_REG_FIRST }, \
4027 { "s0", 16 + GP_REG_FIRST }, \
4028 { "s1", 17 + GP_REG_FIRST }, \
4029 { "s2", 18 + GP_REG_FIRST }, \
4030 { "s3", 19 + GP_REG_FIRST }, \
4031 { "s4", 20 + GP_REG_FIRST }, \
4032 { "s5", 21 + GP_REG_FIRST }, \
4033 { "s6", 22 + GP_REG_FIRST }, \
4034 { "s7", 23 + GP_REG_FIRST }, \
4035 { "t8", 24 + GP_REG_FIRST }, \
4036 { "t9", 25 + GP_REG_FIRST }, \
4037 { "k0", 26 + GP_REG_FIRST }, \
4038 { "k1", 27 + GP_REG_FIRST }, \
4039 { "gp", 28 + GP_REG_FIRST }, \
4040 { "sp", 29 + GP_REG_FIRST }, \
4041 { "fp", 30 + GP_REG_FIRST }, \
4042 { "ra", 31 + GP_REG_FIRST }, \
4043 { "$sp", 29 + GP_REG_FIRST }, \
4044 { "$fp", 30 + GP_REG_FIRST } \
4047 /* Define results of standard character escape sequences. */
4048 #define TARGET_BELL 007
4049 #define TARGET_BS 010
4050 #define TARGET_TAB 011
4051 #define TARGET_NEWLINE 012
4052 #define TARGET_VT 013
4053 #define TARGET_FF 014
4054 #define TARGET_CR 015
4056 /* A C compound statement to output to stdio stream STREAM the
4057 assembler syntax for an instruction operand X. X is an RTL
4060 CODE is a value that can be used to specify one of several ways
4061 of printing the operand. It is used when identical operands
4062 must be printed differently depending on the context. CODE
4063 comes from the `%' specification that was used to request
4064 printing of the operand. If the specification was just `%DIGIT'
4065 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4066 is the ASCII code for LTR.
4068 If X is a register, this macro should print the register's name.
4069 The names can be found in an array `reg_names' whose type is
4070 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4072 When the machine description has a specification `%PUNCT' (a `%'
4073 followed by a punctuation character), this macro is called with
4074 a null pointer for X and the punctuation character for CODE.
4076 See mips.c for the MIPS specific codes. */
4078 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4080 /* A C expression which evaluates to true if CODE is a valid
4081 punctuation character for use in the `PRINT_OPERAND' macro. If
4082 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4083 punctuation characters (except for the standard one, `%') are
4084 used in this way. */
4086 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4088 /* A C compound statement to output to stdio stream STREAM the
4089 assembler syntax for an instruction operand that is a memory
4090 reference whose address is ADDR. ADDR is an RTL expression.
4092 On some machines, the syntax for a symbolic address depends on
4093 the section that the address refers to. On these machines,
4094 define the macro `ENCODE_SECTION_INFO' to store the information
4095 into the `symbol_ref', and then check for it here. */
4097 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4100 /* A C statement, to be executed after all slot-filler instructions
4101 have been output. If necessary, call `dbr_sequence_length' to
4102 determine the number of slots filled in a sequence (zero if not
4103 currently outputting a sequence), to decide how many no-ops to
4104 output, or whatever.
4106 Don't define this macro if it has nothing to do, but it is
4107 helpful in reading assembly output if the extent of the delay
4108 sequence is made explicit (e.g. with white space).
4110 Note that output routines for instructions with delay slots must
4111 be prepared to deal with not being output as part of a sequence
4112 (i.e. when the scheduling pass is not run, or when no slot
4113 fillers could be found.) The variable `final_sequence' is null
4114 when not processing a sequence, otherwise it contains the
4115 `sequence' rtx being output. */
4117 #define DBR_OUTPUT_SEQEND(STREAM) \
4120 if (set_nomacro > 0 && --set_nomacro == 0) \
4121 fputs ("\t.set\tmacro\n", STREAM); \
4123 if (set_noreorder > 0 && --set_noreorder == 0) \
4124 fputs ("\t.set\treorder\n", STREAM); \
4126 dslots_jump_filled++; \
4127 fputs ("\n", STREAM); \
4132 /* How to tell the debugger about changes of source files. Note, the
4133 mips ECOFF format cannot deal with changes of files inside of
4134 functions, which means the output of parser generators like bison
4135 is generally not debuggable without using the -l switch. Lose,
4136 lose, lose. Silicon graphics seems to want all .file's hardwired
4139 #ifndef SET_FILE_NUMBER
4140 #define SET_FILE_NUMBER() ++num_source_filenames
4143 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4144 mips_output_filename (STREAM, NAME)
4146 /* This is defined so that it can be overridden in iris6.h. */
4147 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4150 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4151 output_quoted_string (STREAM, NAME); \
4152 fputs ("\n", STREAM); \
4156 /* This is how to output a note the debugger telling it the line number
4157 to which the following sequence of instructions corresponds.
4158 Silicon graphics puts a label after each .loc. */
4160 #ifndef LABEL_AFTER_LOC
4161 #define LABEL_AFTER_LOC(STREAM)
4164 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4165 mips_output_lineno (STREAM, LINE)
4167 /* The MIPS implementation uses some labels for its own purpose. The
4168 following lists what labels are created, and are all formed by the
4169 pattern $L[a-z].*. The machine independent portion of GCC creates
4170 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4172 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4173 $Lb[0-9]+ Begin blocks for MIPS debug support
4174 $Lc[0-9]+ Label for use in s<xx> operation.
4175 $Le[0-9]+ End blocks for MIPS debug support
4176 $Lp\..+ Half-pic labels. */
4178 /* This is how to output the definition of a user-level label named NAME,
4179 such as the label on a static function or variable NAME.
4181 If we are optimizing the gp, remember that this label has been put
4182 out, so we know not to emit an .extern for it in mips_asm_file_end.
4183 We use one of the common bits in the IDENTIFIER tree node for this,
4184 since those bits seem to be unused, and we don't have any method
4185 of getting the decl nodes from the name. */
4187 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4189 assemble_name (STREAM, NAME); \
4190 fputs (":\n", STREAM); \
4194 /* A C statement (sans semicolon) to output to the stdio stream
4195 STREAM any text necessary for declaring the name NAME of an
4196 initialized variable which is being defined. This macro must
4197 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4198 The argument DECL is the `VAR_DECL' tree node representing the
4201 If this macro is not defined, then the variable name is defined
4202 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4204 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4207 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4208 HALF_PIC_DECLARE (NAME); \
4213 /* This is how to output a command to make the user-level label named NAME
4214 defined for reference from other files. */
4216 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4218 fputs ("\t.globl\t", STREAM); \
4219 assemble_name (STREAM, NAME); \
4220 fputs ("\n", STREAM); \
4223 /* This says how to define a global common symbol. */
4225 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4227 /* If the target wants uninitialized const declarations in \
4228 .rdata then don't put them in .comm */ \
4229 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4230 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4231 && (DECL_INITIAL (DECL) == 0 \
4232 || DECL_INITIAL (DECL) == error_mark_node)) \
4234 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4235 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4237 READONLY_DATA_SECTION (); \
4238 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4239 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4243 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4248 /* This says how to define a local common symbol (ie, not visible to
4251 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4252 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4255 /* This says how to output an external. It would be possible not to
4256 output anything and let undefined symbol become external. However
4257 the assembler uses length information on externals to allocate in
4258 data/sdata bss/sbss, thereby saving exec time. */
4260 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4261 mips_output_external(STREAM,DECL,NAME)
4263 /* This says what to print at the end of the assembly file */
4264 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4267 /* This is how to declare a function name. The actual work of
4268 emitting the label is moved to function_prologue, so that we can
4269 get the line number correctly emitted before the .ent directive,
4270 and after any .file directives.
4272 Also, switch files if we are optimizing the global pointer. */
4274 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4276 extern FILE *asm_out_text_file; \
4277 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4279 STREAM = asm_out_text_file; \
4280 /* ??? text_section gets called too soon. If the previous \
4281 function is in a special section and we're not, we have \
4282 to switch back to the text section. We can't call \
4283 text_section again as gcc thinks we're already there. */ \
4284 /* ??? See varasm.c. There are other things that get output \
4285 too early, like alignment (before we've switched STREAM). */ \
4286 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4287 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4290 HALF_PIC_DECLARE (NAME); \
4293 /* This is how to output an internal numbered label where
4294 PREFIX is the class of label and NUM is the number within the class. */
4296 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4297 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4299 /* This is how to store into the string LABEL
4300 the symbol_ref name of an internal numbered label where
4301 PREFIX is the class of label and NUM is the number within the class.
4302 This is suitable for output with `assemble_name'. */
4304 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4305 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4307 /* This is how to output an assembler line defining a `double' constant. */
4309 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4310 mips_output_double (STREAM, VALUE)
4313 /* This is how to output an assembler line defining a `float' constant. */
4315 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4316 mips_output_float (STREAM, VALUE)
4319 /* This is how to output an assembler line defining an `int' constant. */
4321 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4323 fprintf (STREAM, "\t.word\t"); \
4324 output_addr_const (STREAM, (VALUE)); \
4325 fprintf (STREAM, "\n"); \
4328 /* Likewise for 64 bit, `char' and `short' constants.
4330 FIXME: operand_subword can't handle some complex constant expressions
4331 that output_addr_const can (for example it does not call
4332 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4333 rely on that to avoid operand_subword for most of the cases where this
4334 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4335 or the same case with the type of 'i' changed to long long.
4339 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4341 if (TARGET_64BIT || TARGET_GAS) \
4343 fprintf (STREAM, "\t.dword\t"); \
4344 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4345 /* We can't use 'X' for negative numbers, because then we won't \
4346 get the right value for the upper 32 bits. */ \
4347 output_addr_const (STREAM, VALUE); \
4349 /* We must use 'X', because otherwise LONG_MIN will print as \
4350 a number that the Irix 6 assembler won't accept. */ \
4351 print_operand (STREAM, VALUE, 'X'); \
4352 fprintf (STREAM, "\n"); \
4356 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4357 UNITS_PER_WORD, 1); \
4358 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4359 UNITS_PER_WORD, 1); \
4363 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4365 fprintf (STREAM, "\t.half\t"); \
4366 output_addr_const (STREAM, (VALUE)); \
4367 fprintf (STREAM, "\n"); \
4370 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4372 fprintf (STREAM, "\t.byte\t"); \
4373 output_addr_const (STREAM, (VALUE)); \
4374 fprintf (STREAM, "\n"); \
4377 /* This is how to output an assembler line for a numeric constant byte. */
4379 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4380 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4382 /* This is how to output an element of a case-vector that is absolute. */
4384 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4385 fprintf (STREAM, "\t%s\t%sL%d\n", \
4386 Pmode == DImode ? ".dword" : ".word", \
4387 LOCAL_LABEL_PREFIX, \
4390 /* This is how to output an element of a case-vector that is relative.
4391 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4392 TARGET_EMBEDDED_PIC). */
4394 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4396 if (TARGET_MIPS16) \
4397 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4398 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4399 else if (TARGET_EMBEDDED_PIC) \
4400 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4401 Pmode == DImode ? ".dword" : ".word", \
4402 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4403 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4404 fprintf (STREAM, "\t%s\t%sL%d\n", \
4405 Pmode == DImode ? ".gpdword" : ".gpword", \
4406 LOCAL_LABEL_PREFIX, VALUE); \
4408 fprintf (STREAM, "\t%s\t%sL%d\n", \
4409 Pmode == DImode ? ".dword" : ".word", \
4410 LOCAL_LABEL_PREFIX, VALUE); \
4413 /* When generating embedded PIC or mips16 code we want to put the jump
4414 table in the .text section. In all other cases, we want to put the
4415 jump table in the .rdata section. Unfortunately, we can't use
4416 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4417 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4418 section if appropriate. */
4419 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4421 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4422 function_section (current_function_decl); \
4423 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4426 /* This is how to output an assembler line
4427 that says to advance the location counter
4428 to a multiple of 2**LOG bytes. */
4430 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4431 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4433 /* This is how to output an assembler line to advance the location
4434 counter by SIZE bytes. */
4436 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4437 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4439 /* This is how to output a string. */
4440 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4442 register int i, c, len = (LEN), cur_pos = 17; \
4443 register const unsigned char *string = \
4444 (const unsigned char *)(STRING); \
4445 fprintf ((STREAM), "\t.ascii\t\""); \
4446 for (i = 0; i < len; i++) \
4448 register int c = string[i]; \
4454 putc ('\\', (STREAM)); \
4455 putc (c, (STREAM)); \
4459 case TARGET_NEWLINE: \
4460 fputs ("\\n", (STREAM)); \
4462 && (((c = string[i+1]) >= '\040' && c <= '~') \
4463 || c == TARGET_TAB)) \
4464 cur_pos = 32767; /* break right here */ \
4470 fputs ("\\t", (STREAM)); \
4475 fputs ("\\f", (STREAM)); \
4480 fputs ("\\b", (STREAM)); \
4485 fputs ("\\r", (STREAM)); \
4490 if (c >= ' ' && c < 0177) \
4492 putc (c, (STREAM)); \
4497 fprintf ((STREAM), "\\%03o", c); \
4502 if (cur_pos > 72 && i+1 < len) \
4505 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4508 fprintf ((STREAM), "\"\n"); \
4511 /* Handle certain cpp directives used in header files on sysV. */
4512 #define SCCS_DIRECTIVE
4514 /* Output #ident as a in the read-only data section. */
4515 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4518 int size = strlen (p) + 1; \
4520 assemble_string (p, size); \
4523 /* Default to -G 8 */
4524 #ifndef MIPS_DEFAULT_GVALUE
4525 #define MIPS_DEFAULT_GVALUE 8
4528 /* Define the strings to put out for each section in the object file. */
4529 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4530 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4531 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4532 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4533 #define READONLY_DATA_SECTION rdata_section
4534 #define SMALL_DATA_SECTION sdata_section
4536 /* What other sections we support other than the normal .data/.text. */
4538 #define EXTRA_SECTIONS in_sdata, in_rdata
4540 /* Define the additional functions to select our additional sections. */
4542 /* on the MIPS it is not a good idea to put constants in the text
4543 section, since this defeats the sdata/data mechanism. This is
4544 especially true when -O is used. In this case an effort is made to
4545 address with faster (gp) register relative addressing, which can
4546 only get at sdata and sbss items (there is no stext !!) However,
4547 if the constant is too large for sdata, and it's readonly, it
4548 will go into the .rdata section. */
4550 #define EXTRA_SECTION_FUNCTIONS \
4554 if (in_section != in_sdata) \
4556 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4557 in_section = in_sdata; \
4564 if (in_section != in_rdata) \
4566 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4567 in_section = in_rdata; \
4571 /* Given a decl node or constant node, choose the section to output it in
4572 and select that section. */
4574 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4576 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4579 /* Store in OUTPUT a string (made with alloca) containing
4580 an assembler-name for a local static variable named NAME.
4581 LABELNO is an integer which is different for each call. */
4583 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4584 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4585 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4587 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4590 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4591 TARGET_64BIT ? "dsubu" : "subu", \
4592 reg_names[STACK_POINTER_REGNUM], \
4593 reg_names[STACK_POINTER_REGNUM], \
4594 TARGET_64BIT ? "sd" : "sw", \
4596 reg_names[STACK_POINTER_REGNUM]); \
4600 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4603 if (! set_noreorder) \
4604 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4606 dslots_load_total++; \
4607 dslots_load_filled++; \
4608 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4609 TARGET_64BIT ? "ld" : "lw", \
4611 reg_names[STACK_POINTER_REGNUM], \
4612 TARGET_64BIT ? "daddu" : "addu", \
4613 reg_names[STACK_POINTER_REGNUM], \
4614 reg_names[STACK_POINTER_REGNUM]); \
4616 if (! set_noreorder) \
4617 fprintf (STREAM, "\t.set\treorder\n"); \
4621 /* Define the parentheses used to group arithmetic operations
4622 in assembler code. */
4624 #define ASM_OPEN_PAREN "("
4625 #define ASM_CLOSE_PAREN ")"
4627 /* How to start an assembler comment.
4628 The leading space is important (the mips native assembler requires it). */
4629 #ifndef ASM_COMMENT_START
4630 #define ASM_COMMENT_START " #"
4634 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4635 and mips-tdump.c to print them out.
4637 These must match the corresponding definitions in gdb/mipsread.c.
4638 Unfortunately, gcc and gdb do not currently share any directories. */
4640 #define CODE_MASK 0x8F300
4641 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4642 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4643 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4646 /* Default definitions for size_t and ptrdiff_t. */
4649 #define NO_BUILTIN_SIZE_TYPE
4650 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4653 #ifndef PTRDIFF_TYPE
4654 #define NO_BUILTIN_PTRDIFF_TYPE
4655 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4658 /* See mips_expand_prologue's use of loadgp for when this should be
4661 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4662 && mips_abi != ABI_32 \
4663 && mips_abi != ABI_O64)
4665 /* In mips16 mode, we need to look through the function to check for
4666 PC relative loads that are out of range. */
4667 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4669 /* We need to use a special set of functions to handle hard floating
4670 point code in mips16 mode. */
4672 #ifndef INIT_SUBTARGET_OPTABS
4673 #define INIT_SUBTARGET_OPTABS
4676 #define INIT_TARGET_OPTABS \
4679 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4680 INIT_SUBTARGET_OPTABS; \
4683 add_optab->handlers[(int) SFmode].libfunc = \
4684 init_one_libfunc ("__mips16_addsf3"); \
4685 sub_optab->handlers[(int) SFmode].libfunc = \
4686 init_one_libfunc ("__mips16_subsf3"); \
4687 smul_optab->handlers[(int) SFmode].libfunc = \
4688 init_one_libfunc ("__mips16_mulsf3"); \
4689 flodiv_optab->handlers[(int) SFmode].libfunc = \
4690 init_one_libfunc ("__mips16_divsf3"); \
4692 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4693 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4694 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4695 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4696 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4697 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4699 floatsisf_libfunc = \
4700 init_one_libfunc ("__mips16_floatsisf"); \
4702 init_one_libfunc ("__mips16_fixsfsi"); \
4704 if (TARGET_DOUBLE_FLOAT) \
4706 add_optab->handlers[(int) DFmode].libfunc = \
4707 init_one_libfunc ("__mips16_adddf3"); \
4708 sub_optab->handlers[(int) DFmode].libfunc = \
4709 init_one_libfunc ("__mips16_subdf3"); \
4710 smul_optab->handlers[(int) DFmode].libfunc = \
4711 init_one_libfunc ("__mips16_muldf3"); \
4712 flodiv_optab->handlers[(int) DFmode].libfunc = \
4713 init_one_libfunc ("__mips16_divdf3"); \
4715 extendsfdf2_libfunc = \
4716 init_one_libfunc ("__mips16_extendsfdf2"); \
4717 truncdfsf2_libfunc = \
4718 init_one_libfunc ("__mips16_truncdfsf2"); \
4721 init_one_libfunc ("__mips16_eqdf2"); \
4723 init_one_libfunc ("__mips16_nedf2"); \
4725 init_one_libfunc ("__mips16_gtdf2"); \
4727 init_one_libfunc ("__mips16_gedf2"); \
4729 init_one_libfunc ("__mips16_ltdf2"); \
4731 init_one_libfunc ("__mips16_ledf2"); \
4733 floatsidf_libfunc = \
4734 init_one_libfunc ("__mips16_floatsidf"); \
4736 init_one_libfunc ("__mips16_fixdfsi"); \
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