1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int may_call_alloca;
31 extern char **save_argv;
32 extern int target_flags;
34 /* MIPS external variables defined in mips.c. */
38 CMP_SI, /* compare four byte integers */
39 CMP_DI, /* compare eight byte integers */
40 CMP_SF, /* compare single precision floats */
41 CMP_DF, /* compare double precision floats */
42 CMP_MAX /* max comparison type */
45 /* types of delay slot */
47 DELAY_NONE, /* no delay slot */
48 DELAY_LOAD, /* load from memory delay */
49 DELAY_HILO, /* move from/to hi/lo registers */
50 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
53 /* Which processor to schedule for. Since there is no difference between
54 a R2000 and R3000 in terms of the scheduler, we collapse them into
55 just an R3000. The elements of the enumeration must match exactly
56 the cpu attribute in the mips.md machine description. */
72 /* Recast the cpu class to be the cpu attribute. */
73 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
75 /* Which ABI to use. These are constants because abi64.h must check their
76 value at preprocessing time.
78 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
79 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
87 #ifndef MIPS_ABI_DEFAULT
88 /* We define this away so that there is no extra runtime cost if the target
89 doesn't support multiple ABIs. */
90 #define mips_abi ABI_32
95 /* Whether to emit abicalls code sequences or not. */
97 enum mips_abicalls_type {
102 /* Recast the abicalls class to be the abicalls attribute. */
103 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
105 /* Which type of block move to do (whether or not the last store is
106 split out so it can fill a branch delay slot). */
108 enum block_move_type {
109 BLOCK_MOVE_NORMAL, /* generate complete block move */
110 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
111 BLOCK_MOVE_LAST /* generate just the last store */
114 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
115 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
116 extern const char *current_function_file; /* filename current function is in */
117 extern int num_source_filenames; /* current .file # */
118 extern int inside_function; /* != 0 if inside of a function */
119 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
120 extern int file_in_function_warning; /* warning given about .file in func */
121 extern int sdb_label_count; /* block start/end next label # */
122 extern int sdb_begin_function_line; /* Starting Line of current function */
123 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
124 extern int g_switch_value; /* value of the -G xx switch */
125 extern int g_switch_set; /* whether -G xx was passed. */
126 extern int sym_lineno; /* sgi next label # for each stmt */
127 extern int set_noreorder; /* # of nested .set noreorder's */
128 extern int set_nomacro; /* # of nested .set nomacro's */
129 extern int set_noat; /* # of nested .set noat's */
130 extern int set_volatile; /* # of nested .set volatile's */
131 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
132 extern int mips_dbx_regno[]; /* Map register # to debug register # */
133 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
134 extern enum cmp_type branch_type; /* what type of branch to use */
135 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
136 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
137 extern int mips_isa; /* architectural level */
138 extern int mips16; /* whether generating mips16 code */
139 extern int mips16_hard_float; /* mips16 without -msoft-float */
140 extern int mips_entry; /* generate entry/exit for mips16 */
141 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
142 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
143 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
144 extern const char *mips_entry_string; /* for -mentry */
145 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
146 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
147 extern int mips_split_addresses; /* perform high/lo_sum support */
148 extern int dslots_load_total; /* total # load related delay slots */
149 extern int dslots_load_filled; /* # filled load delay slots */
150 extern int dslots_jump_total; /* total # jump related delay slots */
151 extern int dslots_jump_filled; /* # filled jump delay slots */
152 extern int dslots_number_nops; /* # of nops needed by previous insn */
153 extern int num_refs[3]; /* # 1/2/3 word references */
154 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
155 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
156 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
157 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
158 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
159 extern int mips_string_length; /* length of strings for mips16 */
160 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
162 /* Functions to change what output section we are using. */
163 extern void rdata_section PARAMS ((void));
164 extern void sdata_section PARAMS ((void));
165 extern void sbss_section PARAMS ((void));
167 /* Stubs for half-pic support if not OSF/1 reference platform. */
170 #define HALF_PIC_P() 0
171 #define HALF_PIC_NUMBER_PTRS 0
172 #define HALF_PIC_NUMBER_REFS 0
173 #define HALF_PIC_ENCODE(DECL)
174 #define HALF_PIC_DECLARE(NAME)
175 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
176 #define HALF_PIC_ADDRESS_P(X) 0
177 #define HALF_PIC_PTR(X) X
178 #define HALF_PIC_FINISH(STREAM)
182 /* Run-time compilation parameters selecting different hardware subsets. */
184 /* Macros used in the machine description to test the flags. */
186 /* Bits for real switches */
187 #define MASK_INT64 0x00000001 /* ints are 64 bits */
188 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
189 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
190 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
191 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
192 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
193 #define MASK_STATS 0x00000040 /* print statistics to stderr */
194 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
195 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
196 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
197 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
198 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
199 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
200 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
201 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
202 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
203 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
204 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
205 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
206 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
207 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
208 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
209 #define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
210 #define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
211 #define MASK_UNINIT_CONST_IN_RODATA 0x10000000 /* Store uninitialized
214 /* Dummy switches used only in spec's*/
215 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
217 /* Debug switches, not documented */
218 #define MASK_DEBUG 0 /* Eliminate version # in .s file */
219 #define MASK_DEBUG_A 0x40000000 /* don't allow <label>($reg) addrs */
220 #define MASK_DEBUG_B 0x20000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
221 #define MASK_DEBUG_C 0x10000000 /* don't expand seq, etc. */
222 #define MASK_DEBUG_D 0 /* don't do define_split's */
223 #define MASK_DEBUG_E 0 /* function_arg debug */
224 #define MASK_DEBUG_F 0
225 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
226 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
227 #define MASK_DEBUG_I 0 /* unused */
229 /* r4000 64 bit sizes */
230 #define TARGET_INT64 (target_flags & MASK_INT64)
231 #define TARGET_LONG64 (target_flags & MASK_LONG64)
232 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
233 #define TARGET_64BIT (target_flags & MASK_64BIT)
235 /* Mips vs. GNU linker */
236 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
238 /* generate mips 3900 insns */
239 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
241 /* Mips vs. GNU assembler */
242 #define TARGET_GAS (target_flags & MASK_GAS)
243 #define TARGET_UNIX_ASM (!TARGET_GAS)
244 #define TARGET_MIPS_AS TARGET_UNIX_ASM
247 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
248 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
249 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
250 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
251 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
252 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
253 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
254 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
255 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
256 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
258 /* Reg. Naming in .s ($21 vs. $a0) */
259 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
261 /* Optimize for Sdata/Sbss */
262 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
264 /* print program statistics */
265 #define TARGET_STATS (target_flags & MASK_STATS)
267 /* call memcpy instead of inline code */
268 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
270 /* .abicalls, etc from Pyramid V.4 */
271 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
273 /* OSF pic references to externs */
274 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
276 /* software floating point */
277 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
278 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
280 /* always call through a register */
281 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
283 /* generate embedded PIC code;
285 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
287 /* for embedded systems, optimize for
288 reduced RAM space instead of for
290 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
292 /* always store uninitialized const
293 variables in rodata, requires
294 TARGET_EMBEDDED_DATA. */
295 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
297 /* generate big endian code. */
298 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
300 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
301 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
303 #define TARGET_MAD (target_flags & MASK_MAD)
305 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
307 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
308 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
310 /* This is true if we must enable the assembly language file switching
313 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
315 /* We must disable the function end stabs when doing the file switching trick,
316 because the Lscope stabs end up in the wrong place, making it impossible
317 to debug the resulting code. */
318 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
320 /* Generate mips16 code */
321 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
323 /* Macro to define tables used to set the flags.
324 This is a list in braces of pairs in braces,
325 each pair being { "NAME", VALUE }
326 where VALUE is the bits to set or minus the bits to clear.
327 An empty string NAME is used to identify the default VALUE. */
329 #define TARGET_SWITCHES \
332 "No default crt0.o" }, \
333 {"int64", MASK_INT64 | MASK_LONG64, \
334 "Use 64-bit int type"}, \
335 {"long64", MASK_LONG64, \
336 "Use 64-bit long type"}, \
337 {"long32", -(MASK_LONG64 | MASK_INT64), \
338 "Use 32-bit long type"}, \
339 {"split-addresses", MASK_SPLIT_ADDR, \
340 "Optimize lui/addiu address loads"}, \
341 {"no-split-addresses", -MASK_SPLIT_ADDR, \
342 "Don't optimize lui/addiu address loads"}, \
343 {"mips-as", -MASK_GAS, \
347 {"rnames", MASK_NAME_REGS, \
348 "Use symbolic register names"}, \
349 {"no-rnames", -MASK_NAME_REGS, \
350 "Don't use symbolic register names"}, \
351 {"gpOPT", MASK_GPOPT, \
352 "Use GP relative sdata/sbss sections"}, \
353 {"gpopt", MASK_GPOPT, \
354 "Use GP relative sdata/sbss sections"}, \
355 {"no-gpOPT", -MASK_GPOPT, \
356 "Don't use GP relative sdata/sbss sections"}, \
357 {"no-gpopt", -MASK_GPOPT, \
358 "Don't use GP relative sdata/sbss sections"}, \
359 {"stats", MASK_STATS, \
360 "Output compiler statistics"}, \
361 {"no-stats", -MASK_STATS, \
362 "Don't output compiler statistics"}, \
363 {"memcpy", MASK_MEMCPY, \
364 "Don't optimize block moves"}, \
365 {"no-memcpy", -MASK_MEMCPY, \
366 "Optimize block moves"}, \
367 {"mips-tfile", MASK_MIPS_TFILE, \
368 "Use mips-tfile asm postpass"}, \
369 {"no-mips-tfile", -MASK_MIPS_TFILE, \
370 "Don't use mips-tfile asm postpass"}, \
371 {"soft-float", MASK_SOFT_FLOAT, \
372 "Use software floating point"}, \
373 {"hard-float", -MASK_SOFT_FLOAT, \
374 "Use hardware floating point"}, \
375 {"fp64", MASK_FLOAT64, \
376 "Use 64-bit FP registers"}, \
377 {"fp32", -MASK_FLOAT64, \
378 "Use 32-bit FP registers"}, \
379 {"gp64", MASK_64BIT, \
380 "Use 64-bit general registers"}, \
381 {"gp32", -MASK_64BIT, \
382 "Use 32-bit general registers"}, \
383 {"abicalls", MASK_ABICALLS, \
385 {"no-abicalls", -MASK_ABICALLS, \
386 "Don't use Irix PIC"}, \
387 {"half-pic", MASK_HALF_PIC, \
389 {"no-half-pic", -MASK_HALF_PIC, \
390 "Don't use OSF PIC"}, \
391 {"long-calls", MASK_LONG_CALLS, \
392 "Use indirect calls"}, \
393 {"no-long-calls", -MASK_LONG_CALLS, \
394 "Don't use indirect calls"}, \
395 {"embedded-pic", MASK_EMBEDDED_PIC, \
396 "Use embedded PIC"}, \
397 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
398 "Don't use embedded PIC"}, \
399 {"embedded-data", MASK_EMBEDDED_DATA, \
400 "Use ROM instead of RAM"}, \
401 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
402 "Don't use ROM instead of RAM"}, \
403 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
404 "Put uninitialized constants in ROM (needs -membedded-data)"}, \
405 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
406 "Don't put uninitialized constants in ROM"}, \
407 {"eb", MASK_BIG_ENDIAN, \
408 "Use big-endian byte order"}, \
409 {"el", -MASK_BIG_ENDIAN, \
410 "Use little-endian byte order"}, \
411 {"single-float", MASK_SINGLE_FLOAT, \
412 "Use single (32-bit) FP only"}, \
413 {"double-float", -MASK_SINGLE_FLOAT, \
414 "Don't use single (32-bit) FP only"}, \
416 "Use multiply accumulate"}, \
417 {"no-mad", -MASK_MAD, \
418 "Don't use multiply accumulate"}, \
419 {"fix4300", MASK_4300_MUL_FIX, \
420 "Work around early 4300 hardware bug"}, \
421 {"no-fix4300", -MASK_4300_MUL_FIX, \
422 "Don't work around early 4300 hardware bug"}, \
423 {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
424 "Optimize for 4650"}, \
425 {"3900", MASK_MIPS3900, \
426 "Optimize for 3900"}, \
427 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
428 "Trap on integer divide by zero"}, \
429 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
430 "Don't trap on integer divide by zero"}, \
431 {"check-range-division",MASK_CHECK_RANGE_DIV, \
432 "Trap on integer divide overflow"}, \
433 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
434 "Don't trap on integer divide overflow"}, \
435 {"debug", MASK_DEBUG, \
437 {"debuga", MASK_DEBUG_A, \
439 {"debugb", MASK_DEBUG_B, \
441 {"debugc", MASK_DEBUG_C, \
443 {"debugd", MASK_DEBUG_D, \
445 {"debuge", MASK_DEBUG_E, \
447 {"debugf", MASK_DEBUG_F, \
449 {"debugg", MASK_DEBUG_G, \
451 {"debugh", MASK_DEBUG_H, \
453 {"debugi", MASK_DEBUG_I, \
455 {"", (TARGET_DEFAULT \
456 | TARGET_CPU_DEFAULT \
457 | TARGET_ENDIAN_DEFAULT), \
461 /* Default target_flags if no switches are specified */
463 #ifndef TARGET_DEFAULT
464 #define TARGET_DEFAULT 0
467 #ifndef TARGET_CPU_DEFAULT
468 #define TARGET_CPU_DEFAULT 0
471 #ifndef TARGET_ENDIAN_DEFAULT
473 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
475 #define TARGET_ENDIAN_DEFAULT 0
479 #ifndef MIPS_ISA_DEFAULT
480 #define MIPS_ISA_DEFAULT 1
485 /* Make this compile time constant for libgcc2 */
487 #define TARGET_64BIT 1
489 #define TARGET_64BIT 0
491 #endif /* IN_LIBGCC2 */
493 #ifndef MULTILIB_ENDIAN_DEFAULT
494 #if TARGET_ENDIAN_DEFAULT == 0
495 #define MULTILIB_ENDIAN_DEFAULT "EL"
497 #define MULTILIB_ENDIAN_DEFAULT "EB"
501 #ifndef MULTILIB_ISA_DEFAULT
502 #if MIPS_ISA_DEFAULT == 1
503 #define MULTILIB_ISA_DEFAULT "mips1"
504 #elif MIPS_ISA_DEFAULT == 2
505 #define MULTILIB_ISA_DEFAULT "mips2"
506 #elif MIPS_ISA_DEFAULT == 3
507 #define MULTILIB_ISA_DEFAULT "mips3"
508 #elif MIPS_ISA_DEFAULT == 4
509 #define MULTILIB_ISA_DEFAULT "mips4"
511 #define MULTILIB_ISA_DEFAULT "mips1"
515 #ifndef MULTILIB_DEFAULTS
516 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
519 /* We must pass -EL to the linker by default for little endian embedded
520 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
521 linker will default to using big-endian output files. The OUTPUT_FORMAT
522 line must be in the linker script, otherwise -EB/-EL will not work. */
524 #ifndef LINKER_ENDIAN_SPEC
525 #if TARGET_ENDIAN_DEFAULT == 0
526 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
528 #define LINKER_ENDIAN_SPEC ""
532 /* This macro is similar to `TARGET_SWITCHES' but defines names of
533 command options that have values. Its definition is an
534 initializer with a subgrouping for each command option.
536 Each subgrouping contains a string constant, that defines the
537 fixed part of the option name, and the address of a variable.
538 The variable, type `char *', is set to the variable part of the
539 given option if the fixed part matches. The actual option name
540 is made by appending `-m' to the specified name.
542 Here is an example which defines `-mshort-data-NUMBER'. If the
543 given option is `-mshort-data-512', the variable `m88k_short_data'
544 will be set to the string `"512"'.
546 extern char *m88k_short_data;
547 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
549 #define TARGET_OPTIONS \
551 SUBTARGET_TARGET_OPTIONS \
552 { "cpu=", &mips_cpu_string, \
553 "Specify CPU for scheduling purposes"}, \
554 { "ips", &mips_isa_string, \
555 "Specify MIPS ISA"}, \
556 { "entry", &mips_entry_string, \
557 "Use mips16 entry/exit psuedo ops"}, \
558 { "no-mips16", &mips_no_mips16_string, \
559 "Don't use MIPS16 instructions"}, \
560 { "explicit-type-size", &mips_explicit_type_size_string, \
564 /* This is meant to be redefined in the host dependent files. */
565 #define SUBTARGET_TARGET_OPTIONS
567 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
569 /* Generate three-operand multiply instructions for both SImode and DImode. */
570 #define GENERATE_MULT3 (TARGET_MIPS3900 \
573 /* Macros to decide whether certain features are available or not,
574 depending on the instruction set architecture level. */
576 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
577 #define HAVE_SQRT_P() (mips_isa != 1)
579 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
580 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
583 /* ISA has branch likely instructions (eg. mips2). */
584 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
586 /* ISA has the conditional move instructions introduced in mips4. */
587 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
590 /* ISA has just the integer condition move instructions (movn,movz) */
591 #define ISA_HAS_INT_CONDMOVE 0
595 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
596 branch on CC, and move (both FP and non-FP) on CC. */
597 #define ISA_HAS_8CC (mips_isa == 4 \
601 /* This is a catch all for the other new mips4 instructions: indexed load and
602 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
603 and the FP recip and recip sqrt instructions */
604 #define ISA_HAS_FP4 (mips_isa == 4 \
609 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
610 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
611 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
612 target_flags, and -mgp64 sets MASK_64BIT.
614 Setting MASK_64BIT in target_flags will cause gcc to assume that
615 registers are 64 bits wide. int, long and void * will be 32 bit;
616 this may be changed with -mint64 or -mlong64.
618 The gen* programs link code that refers to MASK_64BIT. They don't
619 actually use the information in target_flags; they just refer to
622 /* Switch Recognition by gcc.c. Add -G xx support */
624 #ifdef SWITCH_TAKES_ARG
625 #undef SWITCH_TAKES_ARG
628 #define SWITCH_TAKES_ARG(CHAR) \
629 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
631 /* Sometimes certain combinations of command options do not make sense
632 on a particular target machine. You can define a macro
633 `OVERRIDE_OPTIONS' to take account of this. This macro, if
634 defined, is executed once just after all the command options have
637 On the MIPS, it is used to handle -G. We also use it to set up all
638 of the tables referenced in the other macros. */
640 #define OVERRIDE_OPTIONS override_options ()
642 /* Zero or more C statements that may conditionally modify two
643 variables `fixed_regs' and `call_used_regs' (both of type `char
644 []') after they have been initialized from the two preceding
647 This is necessary in case the fixed or call-clobbered registers
648 depend on target flags.
650 You need not define this macro if it has no work to do.
652 If the usage of an entire class of registers depends on the target
653 flags, you may indicate this to GCC by using this macro to modify
654 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
655 the classes which should not be used by GCC. Also define the macro
656 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
657 letter for a class that shouldn't be used.
659 (However, if this class is not included in `GENERAL_REGS' and all
660 of the insn patterns whose constraints permit this class are
661 controlled by target switches, then GCC will automatically avoid
662 using these registers when the target switches are opposed to
665 #define CONDITIONAL_REGISTER_USAGE \
668 if (!TARGET_HARD_FLOAT) \
672 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
673 fixed_regs[regno] = call_used_regs[regno] = 1; \
674 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
675 fixed_regs[regno] = call_used_regs[regno] = 1; \
677 else if (! ISA_HAS_8CC) \
681 /* We only have a single condition code register. We \
682 implement this by hiding all the condition code registers, \
683 and generating RTL that refers directly to ST_REG_FIRST. */ \
684 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
685 fixed_regs[regno] = call_used_regs[regno] = 1; \
687 /* In mips16 mode, we permit the $t temporary registers to be used \
688 for reload. We prohibit the unused $s registers, since they \
689 are caller saved, and saving them via a mips16 register would \
690 probably waste more time than just reloading the value. */ \
693 fixed_regs[18] = call_used_regs[18] = 1; \
694 fixed_regs[19] = call_used_regs[19] = 1; \
695 fixed_regs[20] = call_used_regs[20] = 1; \
696 fixed_regs[21] = call_used_regs[21] = 1; \
697 fixed_regs[22] = call_used_regs[22] = 1; \
698 fixed_regs[23] = call_used_regs[23] = 1; \
699 fixed_regs[26] = call_used_regs[26] = 1; \
700 fixed_regs[27] = call_used_regs[27] = 1; \
701 fixed_regs[30] = call_used_regs[30] = 1; \
703 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
707 /* This is meant to be redefined in the host dependent files. */
708 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
710 /* Show we can debug even without a frame pointer. */
711 #define CAN_DEBUG_WITHOUT_FP
713 /* Complain about missing specs and predefines that should be defined in each
714 of the target tm files to override the defaults. This is mostly a place-
715 holder until I can get each of the files updated [mm]. */
717 #if defined(OSF_OS) \
718 || defined(DECSTATION) \
719 || defined(SGI_TARGET) \
720 || defined(MIPS_NEWS) \
721 || defined(MIPS_SYSV) \
722 || defined(MIPS_SVR4) \
723 || defined(MIPS_BSD43)
725 #ifndef CPP_PREDEFINES
726 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
730 #error "Define LIB_SPEC in the appropriate tm.h file"
733 #ifndef STARTFILE_SPEC
734 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
738 #error "Define MACHINE_TYPE in the appropriate tm.h file"
742 /* Tell collect what flags to pass to nm. */
744 #define NM_FLAGS "-Bn"
748 /* Names to predefine in the preprocessor for this target machine. */
750 #ifndef CPP_PREDEFINES
751 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
752 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
753 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
756 /* Assembler specs. */
758 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
761 #define MIPS_AS_ASM_SPEC "\
762 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
763 %{pipe: %e-pipe is not supported.} \
764 %{K} %(subtarget_mips_as_asm_spec)"
766 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
767 rather than gas. It may be overridden by subtargets. */
769 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
770 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
773 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
776 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
778 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
779 GAS_ASM_SPEC as the default, depending upon the value of
782 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
785 #define TARGET_ASM_SPEC "\
786 %{mmips-as: %(mips_as_asm_spec)} \
787 %{!mmips-as: %(gas_asm_spec)}"
791 #define TARGET_ASM_SPEC "\
792 %{!mgas: %(mips_as_asm_spec)} \
793 %{mgas: %(gas_asm_spec)}"
797 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
798 to the assembler. It may be overridden by subtargets. */
799 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
800 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
802 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
805 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
806 the assembler. It may be overridden by subtargets. */
807 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
808 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
809 %{g} %{g0} %{g1} %{g2} %{g3} \
810 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
811 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
812 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
813 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
816 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
817 overridden by subtargets. */
819 #ifndef SUBTARGET_ASM_SPEC
820 #define SUBTARGET_ASM_SPEC ""
823 /* ASM_SPEC is the set of arguments to pass to the assembler. */
826 %{!membedded-pic:%{G*}} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
827 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
828 %(subtarget_asm_optimizing_spec) \
829 %(subtarget_asm_debugging_spec) \
831 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
833 %(subtarget_asm_spec)"
835 /* Specify to run a post-processor, mips-tfile after the assembler
836 has run to stuff the mips debug information into the object file.
837 This is needed because the $#!%^ MIPS assembler provides no way
838 of specifying such information in the assembly file. If we are
839 cross compiling, disable mips-tfile unless the user specifies
842 #ifndef ASM_FINAL_SPEC
843 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
845 #define ASM_FINAL_SPEC "\
846 %{mmips-as: %{!mno-mips-tfile: \
847 \n mips-tfile %{v*: -v} \
849 %{!K: %{save-temps: -I %b.o~}} \
850 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
851 %{.s:%i} %{!.s:%g.s}}}"
855 #define ASM_FINAL_SPEC "\
856 %{!mgas: %{!mno-mips-tfile: \
857 \n mips-tfile %{v*: -v} \
859 %{!K: %{save-temps: -I %b.o~}} \
860 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
861 %{.s:%i} %{!.s:%g.s}}}"
864 #endif /* ASM_FINAL_SPEC */
866 /* Redefinition of libraries used. Mips doesn't support normal
867 UNIX style profiling via calling _mcount. It does offer
868 profiling that samples the PC, so do what we can... */
871 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
874 /* Extra switches sometimes passed to the linker. */
875 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
876 will interpret it as a -b option. */
880 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
881 %{bestGnum} %{shared} %{non_shared} \
882 %(linker_endian_spec)"
883 #endif /* LINK_SPEC defined */
885 /* Specs for the compiler proper */
887 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
888 overridden by subtargets. */
889 #ifndef SUBTARGET_CC1_SPEC
890 #define SUBTARGET_CC1_SPEC ""
893 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
897 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
898 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
899 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
900 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
901 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
902 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
903 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
904 %{m4650:-mcpu=r4650} \
905 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
906 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
907 %{pic-none: -mno-half-pic} \
908 %{pic-lib: -mhalf-pic} \
909 %{pic-extern: -mhalf-pic} \
910 %{pic-calls: -mhalf-pic} \
912 %(subtarget_cc1_spec) "
915 /* Preprocessor specs. */
917 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
918 be overridden by subtargets. */
920 #ifndef SUBTARGET_CPP_SIZE_SPEC
921 #define SUBTARGET_CPP_SIZE_SPEC "\
922 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
923 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
926 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
927 overridden by subtargets. */
928 #ifndef SUBTARGET_CPP_SPEC
929 #define SUBTARGET_CPP_SPEC ""
932 /* If we're using 64bit longs, then we have to define __LONG_MAX__
933 correctly. Similarly for 64bit ints and __INT_MAX__. */
934 #ifndef LONG_MAX_SPEC
935 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
936 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
938 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
942 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
946 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
947 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
948 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
949 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
950 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
951 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
952 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
953 %(subtarget_cpp_size_spec) \
954 %{mips3:-U__mips -D__mips=3 -D__mips64} \
955 %{mips4:-U__mips -D__mips=4 -D__mips64} \
956 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
957 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
958 %{m4650:%{!msoft-float:-D__mips_single_float}} \
959 %{msoft-float:-D__mips_soft_float} \
960 %{mabi=eabi:-D__mips_eabi} \
961 %{mips16:%{!mno-mips16:-D__mips16}} \
962 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
963 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
965 %(subtarget_cpp_spec) "
968 /* This macro defines names of additional specifications to put in the specs
969 that can be used in various specifications like CC1_SPEC. Its definition
970 is an initializer with a subgrouping for each command option.
972 Each subgrouping contains a string constant, that defines the
973 specification name, and a string constant that used by the GNU CC driver
976 Do not define this macro if it does not need to do anything. */
978 #define EXTRA_SPECS \
979 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
980 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
981 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
982 { "long_max_spec", LONG_MAX_SPEC }, \
983 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
984 { "gas_asm_spec", GAS_ASM_SPEC }, \
985 { "target_asm_spec", TARGET_ASM_SPEC }, \
986 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
987 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
988 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
989 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
990 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
991 SUBTARGET_EXTRA_SPECS
993 #ifndef SUBTARGET_EXTRA_SPECS
994 #define SUBTARGET_EXTRA_SPECS
997 /* If defined, this macro is an additional prefix to try after
998 `STANDARD_EXEC_PREFIX'. */
1000 #ifndef MD_EXEC_PREFIX
1001 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1004 #ifndef MD_STARTFILE_PREFIX
1005 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1009 /* Print subsidiary information on the compiler version in use. */
1011 #define MIPS_VERSION "[AL 1.1, MM 40]"
1013 #ifndef MACHINE_TYPE
1014 #define MACHINE_TYPE "BSD Mips"
1017 #ifndef TARGET_VERSION_INTERNAL
1018 #define TARGET_VERSION_INTERNAL(STREAM) \
1019 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1022 #ifndef TARGET_VERSION
1023 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1027 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1028 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1029 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1031 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1032 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1035 /* By default, turn on GDB extensions. */
1036 #define DEFAULT_GDB_EXTENSIONS 1
1038 /* If we are passing smuggling stabs through the MIPS ECOFF object
1039 format, put a comment in front of the .stab<x> operation so
1040 that the MIPS assembler does not choke. The mips-tfile program
1041 will correctly put the stab into the object file. */
1043 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1044 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1045 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1047 /* Local compiler-generated symbols must have a prefix that the assembler
1048 understands. By default, this is $, although some targets (e.g.,
1049 NetBSD-ELF) need to override this. */
1051 #ifndef LOCAL_LABEL_PREFIX
1052 #define LOCAL_LABEL_PREFIX "$"
1055 /* By default on the mips, external symbols do not have an underscore
1056 prepended, but some targets (e.g., NetBSD) require this. */
1058 #ifndef USER_LABEL_PREFIX
1059 #define USER_LABEL_PREFIX ""
1062 /* Forward references to tags are allowed. */
1063 #define SDB_ALLOW_FORWARD_REFERENCES
1065 /* Unknown tags are also allowed. */
1066 #define SDB_ALLOW_UNKNOWN_REFERENCES
1068 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1069 since the length can run past this up to a continuation point. */
1070 #define DBX_CONTIN_LENGTH 1500
1072 /* How to renumber registers for dbx and gdb. */
1073 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1075 /* The mapping from gcc register number to DWARF 2 CFA column number.
1076 This mapping does not allow for tracking register 0, since SGI's broken
1077 dwarf reader thinks column 0 is used for the frame address, but since
1078 register 0 is fixed this is not a problem. */
1079 #define DWARF_FRAME_REGNUM(REG) \
1080 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1082 /* The DWARF 2 CFA column which tracks the return address. */
1083 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1085 /* Before the prologue, RA lives in r31. */
1086 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1088 /* Overrides for the COFF debug format. */
1089 #define PUT_SDB_SCL(a) \
1091 extern FILE *asm_out_text_file; \
1092 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1095 #define PUT_SDB_INT_VAL(a) \
1097 extern FILE *asm_out_text_file; \
1098 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1101 #define PUT_SDB_VAL(a) \
1103 extern FILE *asm_out_text_file; \
1104 fputs ("\t.val\t", asm_out_text_file); \
1105 output_addr_const (asm_out_text_file, (a)); \
1106 fputc (';', asm_out_text_file); \
1109 #define PUT_SDB_DEF(a) \
1111 extern FILE *asm_out_text_file; \
1112 fprintf (asm_out_text_file, "\t%s.def\t", \
1113 (TARGET_GAS) ? "" : "#"); \
1114 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1115 fputc (';', asm_out_text_file); \
1118 #define PUT_SDB_PLAIN_DEF(a) \
1120 extern FILE *asm_out_text_file; \
1121 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1122 (TARGET_GAS) ? "" : "#", (a)); \
1125 #define PUT_SDB_ENDEF \
1127 extern FILE *asm_out_text_file; \
1128 fprintf (asm_out_text_file, "\t.endef\n"); \
1131 #define PUT_SDB_TYPE(a) \
1133 extern FILE *asm_out_text_file; \
1134 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1137 #define PUT_SDB_SIZE(a) \
1139 extern FILE *asm_out_text_file; \
1140 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1143 #define PUT_SDB_DIM(a) \
1145 extern FILE *asm_out_text_file; \
1146 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1149 #ifndef PUT_SDB_START_DIM
1150 #define PUT_SDB_START_DIM \
1152 extern FILE *asm_out_text_file; \
1153 fprintf (asm_out_text_file, "\t.dim\t"); \
1157 #ifndef PUT_SDB_NEXT_DIM
1158 #define PUT_SDB_NEXT_DIM(a) \
1160 extern FILE *asm_out_text_file; \
1161 fprintf (asm_out_text_file, "%d,", a); \
1165 #ifndef PUT_SDB_LAST_DIM
1166 #define PUT_SDB_LAST_DIM(a) \
1168 extern FILE *asm_out_text_file; \
1169 fprintf (asm_out_text_file, "%d;", a); \
1173 #define PUT_SDB_TAG(a) \
1175 extern FILE *asm_out_text_file; \
1176 fprintf (asm_out_text_file, "\t.tag\t"); \
1177 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1178 fputc (';', asm_out_text_file); \
1181 /* For block start and end, we create labels, so that
1182 later we can figure out where the correct offset is.
1183 The normal .ent/.end serve well enough for functions,
1184 so those are just commented out. */
1186 #define PUT_SDB_BLOCK_START(LINE) \
1188 extern FILE *asm_out_text_file; \
1189 fprintf (asm_out_text_file, \
1190 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1191 LOCAL_LABEL_PREFIX, \
1193 (TARGET_GAS) ? "" : "#", \
1194 LOCAL_LABEL_PREFIX, \
1197 sdb_label_count++; \
1200 #define PUT_SDB_BLOCK_END(LINE) \
1202 extern FILE *asm_out_text_file; \
1203 fprintf (asm_out_text_file, \
1204 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1205 LOCAL_LABEL_PREFIX, \
1207 (TARGET_GAS) ? "" : "#", \
1208 LOCAL_LABEL_PREFIX, \
1211 sdb_label_count++; \
1214 #define PUT_SDB_FUNCTION_START(LINE)
1216 #define PUT_SDB_FUNCTION_END(LINE) \
1218 extern FILE *asm_out_text_file; \
1219 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1222 #define PUT_SDB_EPILOGUE_END(NAME)
1224 #define PUT_SDB_SRC_FILE(FILENAME) \
1226 extern FILE *asm_out_text_file; \
1227 output_file_directive (asm_out_text_file, (FILENAME)); \
1230 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1231 sprintf ((BUFFER), ".%dfake", (NUMBER));
1233 /* Correct the offset of automatic variables and arguments. Note that
1234 the MIPS debug format wants all automatic variables and arguments
1235 to be in terms of the virtual frame pointer (stack pointer before
1236 any adjustment in the function), while the MIPS 3.0 linker wants
1237 the frame pointer to be the stack pointer after the initial
1240 #define DEBUGGER_AUTO_OFFSET(X) \
1241 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1242 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1243 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1245 /* Tell collect that the object format is ECOFF */
1246 #ifndef OBJECT_FORMAT_ROSE
1247 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1248 #define EXTENDED_COFF /* ECOFF, not normal coff */
1251 #if 0 /* These definitions normally have no effect because
1252 MIPS systems define USE_COLLECT2, so
1253 assemble_constructor does nothing anyway. */
1255 /* Don't use the default definitions, because we don't have gld.
1256 Also, we don't want stabs when generating ECOFF output.
1257 Instead we depend on collect to handle these. */
1259 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1260 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1264 /* Target machine storage layout */
1266 /* Define in order to support both big and little endian float formats
1267 in the same gcc binary. */
1268 #define REAL_ARITHMETIC
1270 /* Define this if most significant bit is lowest numbered
1271 in instructions that operate on numbered bit-fields.
1273 #define BITS_BIG_ENDIAN 0
1275 /* Define this if most significant byte of a word is the lowest numbered. */
1276 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1278 /* Define this if most significant word of a multiword number is the lowest. */
1279 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1281 /* Define this to set the endianness to use in libgcc2.c, which can
1282 not depend on target_flags. */
1283 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1284 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1286 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1289 /* Number of bits in an addressable storage unit */
1290 #define BITS_PER_UNIT 8
1292 /* Width in bits of a "word", which is the contents of a machine register.
1293 Note that this is not necessarily the width of data type `int';
1294 if using 16-bit ints on a 68000, this would still be 32.
1295 But on a machine with 16-bit registers, this would be 16. */
1296 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1297 #define MAX_BITS_PER_WORD 64
1299 /* Width of a word, in units (bytes). */
1300 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1301 #define MIN_UNITS_PER_WORD 4
1303 /* For MIPS, width of a floating point register. */
1304 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1306 /* A C expression for the size in bits of the type `int' on the
1307 target machine. If you don't define this, the default is one
1309 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1310 #define MAX_INT_TYPE_SIZE 64
1312 /* Tell the preprocessor the maximum size of wchar_t. */
1313 #ifndef MAX_WCHAR_TYPE_SIZE
1314 #ifndef WCHAR_TYPE_SIZE
1315 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1319 /* A C expression for the size in bits of the type `short' on the
1320 target machine. If you don't define this, the default is half a
1321 word. (If this would be less than one storage unit, it is
1322 rounded up to one unit.) */
1323 #define SHORT_TYPE_SIZE 16
1325 /* A C expression for the size in bits of the type `long' on the
1326 target machine. If you don't define this, the default is one
1328 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1329 #define MAX_LONG_TYPE_SIZE 64
1331 /* A C expression for the size in bits of the type `long long' on the
1332 target machine. If you don't define this, the default is two
1334 #define LONG_LONG_TYPE_SIZE 64
1336 /* A C expression for the size in bits of the type `char' on the
1337 target machine. If you don't define this, the default is one
1338 quarter of a word. (If this would be less than one storage unit,
1339 it is rounded up to one unit.) */
1340 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1342 /* A C expression for the size in bits of the type `float' on the
1343 target machine. If you don't define this, the default is one
1345 #define FLOAT_TYPE_SIZE 32
1347 /* A C expression for the size in bits of the type `double' on the
1348 target machine. If you don't define this, the default is two
1350 #define DOUBLE_TYPE_SIZE 64
1352 /* A C expression for the size in bits of the type `long double' on
1353 the target machine. If you don't define this, the default is two
1355 #define LONG_DOUBLE_TYPE_SIZE 64
1357 /* Width in bits of a pointer.
1358 See also the macro `Pmode' defined below. */
1359 #ifndef POINTER_SIZE
1360 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1363 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1364 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1366 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1367 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1369 /* Allocation boundary (in *bits*) for the code of a function. */
1370 #define FUNCTION_BOUNDARY 32
1372 /* Alignment of field after `int : 0' in a structure. */
1373 #define EMPTY_FIELD_BOUNDARY 32
1375 /* Every structure's size must be a multiple of this. */
1376 /* 8 is observed right on a DECstation and on riscos 4.02. */
1377 #define STRUCTURE_SIZE_BOUNDARY 8
1379 /* There is no point aligning anything to a rounder boundary than this. */
1380 #define BIGGEST_ALIGNMENT 64
1382 /* Set this nonzero if move instructions will actually fail to work
1383 when given unaligned data. */
1384 #define STRICT_ALIGNMENT 1
1386 /* Define this if you wish to imitate the way many other C compilers
1387 handle alignment of bitfields and the structures that contain
1390 The behavior is that the type written for a bitfield (`int',
1391 `short', or other integer type) imposes an alignment for the
1392 entire structure, as if the structure really did contain an
1393 ordinary field of that type. In addition, the bitfield is placed
1394 within the structure so that it would fit within such a field,
1395 not crossing a boundary for it.
1397 Thus, on most machines, a bitfield whose type is written as `int'
1398 would not cross a four-byte boundary, and would force four-byte
1399 alignment for the whole structure. (The alignment used may not
1400 be four bytes; it is controlled by the other alignment
1403 If the macro is defined, its definition should be a C expression;
1404 a nonzero value for the expression enables this behavior. */
1406 #define PCC_BITFIELD_TYPE_MATTERS 1
1408 /* If defined, a C expression to compute the alignment given to a
1409 constant that is being placed in memory. CONSTANT is the constant
1410 and ALIGN is the alignment that the object would ordinarily have.
1411 The value of this macro is used instead of that alignment to align
1414 If this macro is not defined, then ALIGN is used.
1416 The typical use of this macro is to increase alignment for string
1417 constants to be word aligned so that `strcpy' calls that copy
1418 constants can be done inline. */
1420 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1421 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1422 && (ALIGN) < BITS_PER_WORD \
1426 /* If defined, a C expression to compute the alignment for a static
1427 variable. TYPE is the data type, and ALIGN is the alignment that
1428 the object would ordinarily have. The value of this macro is used
1429 instead of that alignment to align the object.
1431 If this macro is not defined, then ALIGN is used.
1433 One use of this macro is to increase alignment of medium-size
1434 data to make it all fit in fewer cache lines. Another is to
1435 cause character arrays to be word-aligned so that `strcpy' calls
1436 that copy constants to character arrays can be done inline. */
1438 #undef DATA_ALIGNMENT
1439 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1440 ((((ALIGN) < BITS_PER_WORD) \
1441 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1442 || TREE_CODE (TYPE) == UNION_TYPE \
1443 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1446 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1448 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1450 /* Define this macro if an argument declared as `char' or `short' in a
1451 prototype should actually be passed as an `int'. In addition to
1452 avoiding errors in certain cases of mismatch, it also makes for
1453 better code on certain machines. */
1455 #define PROMOTE_PROTOTYPES 1
1457 /* Define if operations between registers always perform the operation
1458 on the full register even if a narrower mode is specified. */
1459 #define WORD_REGISTER_OPERATIONS
1461 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1462 will either zero-extend or sign-extend. The value of this macro should
1463 be the code that says which one of the two operations is implicitly
1466 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1467 moves. All other referces are zero extended. */
1468 #define LOAD_EXTEND_OP(MODE) \
1469 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1470 ? SIGN_EXTEND : ZERO_EXTEND)
1472 /* Define this macro if it is advisable to hold scalars in registers
1473 in a wider mode than that declared by the program. In such cases,
1474 the value is constrained to be within the bounds of the declared
1475 type, but kept valid in the wider mode. The signedness of the
1476 extension may differ from that of the type.
1478 We promote any value smaller than SImode up to SImode. We don't
1479 want to promote to DImode when in 64 bit mode, because that would
1480 prevent us from using the faster SImode multiply and divide
1483 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1484 if (GET_MODE_CLASS (MODE) == MODE_INT \
1485 && GET_MODE_SIZE (MODE) < 4) \
1488 /* Define this if function arguments should also be promoted using the above
1491 #define PROMOTE_FUNCTION_ARGS
1493 /* Likewise, if the function return value is promoted. */
1495 #define PROMOTE_FUNCTION_RETURN
1497 /* Standard register usage. */
1499 /* Number of actual hardware registers.
1500 The hardware registers are assigned numbers for the compiler
1501 from 0 to just below FIRST_PSEUDO_REGISTER.
1502 All registers that the compiler knows about must be given numbers,
1503 even those that are not normally considered general registers.
1505 On the Mips, we have 32 integer registers, 32 floating point
1506 registers, 8 condition code registers, and the special registers
1507 hi, lo, hilo, and rap. The 8 condition code registers are only
1508 used if mips_isa >= 4. The hilo register is only used in 64 bit
1509 mode. It represents a 64 bit value stored as two 32 bit values in
1510 the hi and lo registers; this is the result of the mult
1511 instruction. rap is a pointer to the stack where the return
1512 address reg ($31) was stored. This is needed for C++ exception
1515 #define FIRST_PSEUDO_REGISTER 76
1517 /* 1 for registers that have pervasive standard uses
1518 and are not available for the register allocator.
1520 On the MIPS, see conventions, page D-2 */
1522 #define FIXED_REGISTERS \
1524 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1532 /* 1 for registers not available across function calls.
1533 These must include the FIXED_REGISTERS and also any
1534 registers that can be used without being saved.
1535 The latter must include the registers where values are returned
1536 and the register where structure-value addresses are passed.
1537 Aside from that, you can include as many other registers as you like. */
1539 #define CALL_USED_REGISTERS \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1549 /* Internal macros to classify a register number as to whether it's a
1550 general purpose register, a floating point register, a
1551 multiply/divide register, or a status register. */
1553 #define GP_REG_FIRST 0
1554 #define GP_REG_LAST 31
1555 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1556 #define GP_DBX_FIRST 0
1558 #define FP_REG_FIRST 32
1559 #define FP_REG_LAST 63
1560 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1561 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1563 #define MD_REG_FIRST 64
1564 #define MD_REG_LAST 66
1565 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1567 #define ST_REG_FIRST 67
1568 #define ST_REG_LAST 74
1569 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1571 #define RAP_REG_NUM 75
1573 #define AT_REGNUM (GP_REG_FIRST + 1)
1574 #define HI_REGNUM (MD_REG_FIRST + 0)
1575 #define LO_REGNUM (MD_REG_FIRST + 1)
1576 #define HILO_REGNUM (MD_REG_FIRST + 2)
1578 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1579 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1580 should be used instead. */
1581 #define FPSW_REGNUM ST_REG_FIRST
1583 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1584 #define M16_REG_P(REGNO) \
1585 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1586 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1587 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1588 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1590 /* Return number of consecutive hard regs needed starting at reg REGNO
1591 to hold something of mode MODE.
1592 This is ordinarily the length in words of a value of mode MODE
1593 but can be less for certain modes in special long registers.
1595 On the MIPS, all general registers are one word long. Except on
1596 the R4000 with the FR bit set, the floating point uses register
1597 pairs, with the second register not being allocable. */
1599 #define HARD_REGNO_NREGS(REGNO, MODE) \
1600 (! FP_REG_P (REGNO) \
1601 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1602 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1604 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1605 MODE. In 32 bit mode, require that DImode and DFmode be in even
1606 registers. For DImode, this makes some of the insns easier to
1607 write, since you don't have to worry about a DImode value in
1608 registers 3 & 4, producing a result in 4 & 5.
1610 To make the code simpler HARD_REGNO_MODE_OK now just references an
1611 array built in override_options. Because machmodes.h is not yet
1612 included before this file is processed, the MODE bound can't be
1615 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1617 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1618 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1620 /* Value is 1 if it is a good idea to tie two pseudo registers
1621 when one has mode MODE1 and one has mode MODE2.
1622 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1623 for any hard reg, then this must be 0 for correct output. */
1624 #define MODES_TIEABLE_P(MODE1, MODE2) \
1625 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1626 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1627 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1628 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1630 /* MIPS pc is not overloaded on a register. */
1631 /* #define PC_REGNUM xx */
1633 /* Register to use for pushing function arguments. */
1634 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1636 /* Offset from the stack pointer to the first available location. Use
1637 the default value zero. */
1638 /* #define STACK_POINTER_OFFSET 0 */
1640 /* Base register for access to local variables of the function. We
1641 pretend that the frame pointer is $1, and then eliminate it to
1642 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1643 a fixed register, and will not be used for anything else. */
1644 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1646 /* Temporary scratch register for use by the assembler. */
1647 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1649 /* $30 is not available on the mips16, so we use $17 as the frame
1651 #define HARD_FRAME_POINTER_REGNUM \
1652 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1654 /* Value should be nonzero if functions must have frame pointers.
1655 Zero means the frame pointer need not be set up (and parms
1656 may be accessed via the stack pointer) in functions that seem suitable.
1657 This is computed in `reload', in reload1.c. */
1658 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1660 /* Base register for access to arguments of the function. */
1661 #define ARG_POINTER_REGNUM GP_REG_FIRST
1663 /* Fake register that holds the address on the stack of the
1664 current function's return address. */
1665 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1667 /* Register in which static-chain is passed to a function. */
1668 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1670 /* If the structure value address is passed in a register, then
1671 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1672 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1674 /* If the structure value address is not passed in a register, define
1675 `STRUCT_VALUE' as an expression returning an RTX for the place
1676 where the address is passed. If it returns 0, the address is
1677 passed as an "invisible" first argument. */
1678 #define STRUCT_VALUE 0
1680 /* Mips registers used in prologue/epilogue code when the stack frame
1681 is larger than 32K bytes. These registers must come from the
1682 scratch register set, and not used for passing and returning
1683 arguments and any other information used in the calling sequence
1684 (such as pic). Must start at 12, since t0/t3 are parameter passing
1685 registers in the 64 bit ABI. */
1687 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1688 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1690 /* Define this macro if it is as good or better to call a constant
1691 function address than to call an address kept in a register. */
1692 #define NO_FUNCTION_CSE 1
1694 /* Define this macro if it is as good or better for a function to
1695 call itself with an explicit address than to call an address
1696 kept in a register. */
1697 #define NO_RECURSIVE_FUNCTION_CSE 1
1699 /* The register number of the register used to address a table of
1700 static data addresses in memory. In some cases this register is
1701 defined by a processor's "application binary interface" (ABI).
1702 When this macro is defined, RTL is generated for this register
1703 once, as with the stack pointer and frame pointer registers. If
1704 this macro is not defined, it is up to the machine-dependent
1705 files to allocate such a register (if necessary). */
1706 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1708 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1710 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1711 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1712 isn't always called for static inline functions. */
1713 #define INIT_EXPANDERS \
1715 embedded_pic_fnaddr_rtx = NULL; \
1716 mips16_gp_pseudo_rtx = NULL; \
1719 /* Define the classes of registers for register constraints in the
1720 machine description. Also define ranges of constants.
1722 One of the classes must always be named ALL_REGS and include all hard regs.
1723 If there is more than one class, another class must be named NO_REGS
1724 and contain no registers.
1726 The name GENERAL_REGS must be the name of a class (or an alias for
1727 another name such as ALL_REGS). This is the class of registers
1728 that is allowed by "g" or "r" in a register constraint.
1729 Also, registers outside this class are allocated only when
1730 instructions express preferences for them.
1732 The classes must be numbered in nondecreasing order; that is,
1733 a larger-numbered class must never be contained completely
1734 in a smaller-numbered class.
1736 For any two classes, it is very desirable that there be another
1737 class that represents their union. */
1741 NO_REGS, /* no registers in set */
1742 M16_NA_REGS, /* mips16 regs not used to pass args */
1743 M16_REGS, /* mips16 directly accessible registers */
1744 T_REG, /* mips16 T register ($24) */
1745 M16_T_REGS, /* mips16 registers plus T register */
1746 GR_REGS, /* integer registers */
1747 FP_REGS, /* floating point registers */
1748 HI_REG, /* hi register */
1749 LO_REG, /* lo register */
1750 HILO_REG, /* hilo register pair for 64 bit mode mult */
1751 MD_REGS, /* multiply/divide registers (hi/lo) */
1752 HI_AND_GR_REGS, /* union classes */
1755 ST_REGS, /* status registers (fp status) */
1756 ALL_REGS, /* all registers */
1757 LIM_REG_CLASSES /* max value + 1 */
1760 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1762 #define GENERAL_REGS GR_REGS
1764 /* An initializer containing the names of the register classes as C
1765 string constants. These names are used in writing some of the
1768 #define REG_CLASS_NAMES \
1783 "HILO_AND_GR_REGS", \
1788 /* An initializer containing the contents of the register classes,
1789 as integers which are bit masks. The Nth integer specifies the
1790 contents of class N. The way the integer MASK is interpreted is
1791 that register R is in the class if `MASK & (1 << R)' is 1.
1793 When the machine has more than 32 registers, an integer does not
1794 suffice. Then the integers are replaced by sub-initializers,
1795 braced groupings containing several integers. Each
1796 sub-initializer must be suitable as an initializer for the type
1797 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1799 #define REG_CLASS_CONTENTS \
1801 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1802 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1803 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1804 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1805 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1806 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1807 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1808 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1809 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1810 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1811 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1812 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1813 { 0xffffffff, 0x00000000, 0x00000002 }, \
1814 { 0xffffffff, 0x00000000, 0x00000004 }, \
1815 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1816 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1820 /* A C expression whose value is a register class containing hard
1821 register REGNO. In general there is more that one such class;
1822 choose a class which is "minimal", meaning that no smaller class
1823 also contains the register. */
1825 extern enum reg_class mips_regno_to_class[];
1827 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1829 /* A macro whose definition is the name of the class to which a
1830 valid base register must belong. A base register is one used in
1831 an address which is the register value plus a displacement. */
1833 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1835 /* A macro whose definition is the name of the class to which a
1836 valid index register must belong. An index register is one used
1837 in an address where its value is either multiplied by a scale
1838 factor or added to another register (as well as added to a
1841 #define INDEX_REG_CLASS NO_REGS
1843 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1844 registers explicitly used in the rtl to be used as spill registers
1845 but prevents the compiler from extending the lifetime of these
1848 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1850 /* This macro is used later on in the file. */
1851 #define GR_REG_CLASS_P(CLASS) \
1852 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1853 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1855 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1856 is the default value (allocate the registers in numeric order). We
1857 define it just so that we can override it for the mips16 target in
1858 ORDER_REGS_FOR_LOCAL_ALLOC. */
1860 #define REG_ALLOC_ORDER \
1861 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1862 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1863 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1864 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1865 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1868 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1869 to be rearranged based on a particular function. On the mips16, we
1870 want to allocate $24 (T_REG) before other registers for
1871 instructions for which it is possible. */
1873 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1875 /* REGISTER AND CONSTANT CLASSES */
1877 /* Get reg_class from a letter such as appears in the machine
1880 DEFINED REGISTER CLASSES:
1882 'd' General (aka integer) registers
1883 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1884 'y' General registers (in both mips16 and non mips16 mode)
1885 'e' mips16 non argument registers (M16_NA_REGS)
1886 't' mips16 temporary register ($24)
1887 'f' Floating point registers
1890 'x' Multiply/divide registers
1892 'z' FP Status register
1893 'b' All registers */
1895 extern enum reg_class mips_char_to_class[];
1897 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1899 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1900 string can be used to stand for particular ranges of immediate
1901 operands. This macro defines what the ranges are. C is the
1902 letter, and VALUE is a constant value. Return 1 if VALUE is
1903 in the range specified by C. */
1907 `I' is used for the range of constants an arithmetic insn can
1908 actually contain (16 bits signed integers).
1910 `J' is used for the range which is just zero (ie, $r0).
1912 `K' is used for the range of constants a logical insn can actually
1913 contain (16 bit zero-extended integers).
1915 `L' is used for the range of constants that be loaded with lui
1916 (ie, the bottom 16 bits are zero).
1918 `M' is used for the range of constants that take two words to load
1919 (ie, not matched by `I', `K', and `L').
1921 `N' is used for negative 16 bit constants other than -65536.
1923 `O' is a 15 bit signed integer.
1925 `P' is used for positive 16 bit constants. */
1927 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1928 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1930 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1931 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1932 : (C) == 'J' ? ((VALUE) == 0) \
1933 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1934 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1935 && (((VALUE) & ~2147483647) == 0 \
1936 || ((VALUE) & ~2147483647) == ~2147483647)) \
1937 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1938 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1939 && (((VALUE) & 0x0000ffff) != 0 \
1940 || (((VALUE) & ~2147483647) != 0 \
1941 && ((VALUE) & ~2147483647) != ~2147483647))) \
1942 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1943 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1944 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1947 /* Similar, but for floating constants, and defining letters G and H.
1948 Here VALUE is the CONST_DOUBLE rtx itself. */
1952 'G' : Floating point 0 */
1954 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1956 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1958 /* Letters in the range `Q' through `U' may be defined in a
1959 machine-dependent fashion to stand for arbitrary operand types.
1960 The machine description macro `EXTRA_CONSTRAINT' is passed the
1961 operand as its first argument and the constraint letter as its
1964 `Q' is for mips16 GP relative constants
1965 `R' is for memory references which take 1 word for the instruction.
1966 `S' is for references to extern items which are PIC for OSF/rose.
1967 `T' is for memory addresses that can be used to load two words. */
1969 #define EXTRA_CONSTRAINT(OP,CODE) \
1970 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1971 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1972 && mips16_gp_offset_p (OP)) \
1973 : (GET_CODE (OP) != MEM) ? FALSE \
1974 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1975 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1976 && HALF_PIC_ADDRESS_P (OP)) \
1979 /* Given an rtx X being reloaded into a reg required to be
1980 in class CLASS, return the class of reg to actually use.
1981 In general this is just CLASS; but on some machines
1982 in some cases it is preferable to use a more restrictive class. */
1984 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1985 ((CLASS) != ALL_REGS \
1986 ? (! TARGET_MIPS16 \
1988 : ((CLASS) != GR_REGS \
1991 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1992 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1993 ? (TARGET_SOFT_FLOAT \
1994 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1996 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1997 || GET_MODE (X) == VOIDmode) \
1998 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2001 /* Certain machines have the property that some registers cannot be
2002 copied to some other registers without using memory. Define this
2003 macro on those machines to be a C expression that is non-zero if
2004 objects of mode MODE in registers of CLASS1 can only be copied to
2005 registers of class CLASS2 by storing a register of CLASS1 into
2006 memory and loading that memory location into a register of CLASS2.
2008 Do not define this macro if its value would always be zero. */
2010 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2011 ((!TARGET_DEBUG_H_MODE \
2012 && GET_MODE_CLASS (MODE) == MODE_INT \
2013 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2014 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2015 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2016 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2017 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2019 /* The HI and LO registers can only be reloaded via the general
2020 registers. Condition code registers can only be loaded to the
2021 general registers, and from the floating point registers. */
2023 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2024 mips_secondary_reload_class (CLASS, MODE, X, 1)
2025 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2026 mips_secondary_reload_class (CLASS, MODE, X, 0)
2028 /* Return the maximum number of consecutive registers
2029 needed to represent mode MODE in a register of class CLASS. */
2031 #define CLASS_UNITS(mode, size) \
2032 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2034 #define CLASS_MAX_NREGS(CLASS, MODE) \
2035 ((CLASS) == FP_REGS \
2037 ? CLASS_UNITS (MODE, 8) \
2038 : 2 * CLASS_UNITS (MODE, 8)) \
2039 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2041 /* If defined, gives a class of registers that cannot be used as the
2042 operand of a SUBREG that changes the size of the object. */
2044 #define CLASS_CANNOT_CHANGE_SIZE \
2045 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2047 /* Stack layout; function entry, exit and calling. */
2049 /* Define this if pushing a word on the stack
2050 makes the stack pointer a smaller address. */
2051 #define STACK_GROWS_DOWNWARD
2053 /* Define this if the nominal address of the stack frame
2054 is at the high-address end of the local variables;
2055 that is, each additional local variable allocated
2056 goes at a more negative offset in the frame. */
2057 /* #define FRAME_GROWS_DOWNWARD */
2059 /* Offset within stack frame to start allocating local variables at.
2060 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2061 first local allocated. Otherwise, it is the offset to the BEGINNING
2062 of the first local allocated. */
2063 #define STARTING_FRAME_OFFSET \
2064 (current_function_outgoing_args_size \
2065 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2067 /* Offset from the stack pointer register to an item dynamically
2068 allocated on the stack, e.g., by `alloca'.
2070 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2071 length of the outgoing arguments. The default is correct for most
2072 machines. See `function.c' for details.
2074 The MIPS ABI states that functions which dynamically allocate the
2075 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2076 we are trying to create a second frame pointer to the function, so
2077 allocate some stack space to make it happy.
2079 However, the linker currently complains about linking any code that
2080 dynamically allocates stack space, and there seems to be a bug in
2081 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2084 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2085 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2086 ? 4*UNITS_PER_WORD \
2087 : current_function_outgoing_args_size)
2090 /* The return address for the current frame is in r31 is this is a leaf
2091 function. Otherwise, it is on the stack. It is at a variable offset
2092 from sp/fp/ap, so we define a fake hard register rap which is a
2093 poiner to the return address on the stack. This always gets eliminated
2094 during reload to be either the frame pointer or the stack pointer plus
2097 /* ??? This definition fails for leaf functions. There is currently no
2098 general solution for this problem. */
2100 /* ??? There appears to be no way to get the return address of any previous
2101 frame except by disassembling instructions in the prologue/epilogue.
2102 So currently we support only the current frame. */
2104 #define RETURN_ADDR_RTX(count, frame) \
2106 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2109 /* Structure to be filled in by compute_frame_size with register
2110 save masks, and offsets for the current function. */
2112 struct mips_frame_info
2114 long total_size; /* # bytes that the entire frame takes up */
2115 long var_size; /* # bytes that variables take up */
2116 long args_size; /* # bytes that outgoing arguments take up */
2117 long extra_size; /* # bytes of extra gunk */
2118 int gp_reg_size; /* # bytes needed to store gp regs */
2119 int fp_reg_size; /* # bytes needed to store fp regs */
2120 long mask; /* mask of saved gp registers */
2121 long fmask; /* mask of saved fp registers */
2122 long gp_save_offset; /* offset from vfp to store gp registers */
2123 long fp_save_offset; /* offset from vfp to store fp registers */
2124 long gp_sp_offset; /* offset from new sp to store gp registers */
2125 long fp_sp_offset; /* offset from new sp to store fp registers */
2126 int initialized; /* != 0 if frame size already calculated */
2127 int num_gp; /* number of gp registers saved */
2128 int num_fp; /* number of fp registers saved */
2129 long insns_len; /* length of insns; mips16 only */
2132 extern struct mips_frame_info current_frame_info;
2134 /* If defined, this macro specifies a table of register pairs used to
2135 eliminate unneeded registers that point into the stack frame. If
2136 it is not defined, the only elimination attempted by the compiler
2137 is to replace references to the frame pointer with references to
2140 The definition of this macro is a list of structure
2141 initializations, each of which specifies an original and
2142 replacement register.
2144 On some machines, the position of the argument pointer is not
2145 known until the compilation is completed. In such a case, a
2146 separate hard register must be used for the argument pointer.
2147 This register can be eliminated by replacing it with either the
2148 frame pointer or the argument pointer, depending on whether or not
2149 the frame pointer has been eliminated.
2151 In this case, you might specify:
2152 #define ELIMINABLE_REGS \
2153 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2154 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2155 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2157 Note that the elimination of the argument pointer with the stack
2158 pointer is specified first since that is the preferred elimination.
2160 The eliminations to $17 are only used on the mips16. See the
2161 definition of HARD_FRAME_POINTER_REGNUM. */
2163 #define ELIMINABLE_REGS \
2164 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2165 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2166 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2167 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2168 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2169 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2170 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2171 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2172 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2173 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2175 /* A C expression that returns non-zero if the compiler is allowed to
2176 try to replace register number FROM-REG with register number
2177 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2178 defined, and will usually be the constant 1, since most of the
2179 cases preventing register elimination are things that the compiler
2180 already knows about.
2182 When not in mips16 and mips64, we can always eliminate to the
2183 frame pointer. We can eliminate to the stack pointer unless
2184 a frame pointer is needed. In mips16 mode, we need a frame
2185 pointer for a large frame; otherwise, reload may be unable
2186 to compute the address of a local variable, since there is
2187 no way to add a large constant to the stack pointer
2188 without using a temporary register.
2190 In mips16, for some instructions (eg lwu), we can't eliminate the
2191 frame pointer for the stack pointer. These instructions are
2192 only generated in TARGET_64BIT mode.
2195 #define CAN_ELIMINATE(FROM, TO) \
2196 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2197 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2198 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2199 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2200 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2201 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2202 && (! TARGET_MIPS16 \
2203 || compute_frame_size (get_frame_size ()) < 32768)))))
2205 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2206 specifies the initial difference between the specified pair of
2207 registers. This macro must be defined if `ELIMINABLE_REGS' is
2210 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2211 { compute_frame_size (get_frame_size ()); \
2212 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2213 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2214 (OFFSET) = - current_function_outgoing_args_size; \
2215 else if ((FROM) == FRAME_POINTER_REGNUM) \
2217 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2218 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2219 (OFFSET) = (current_frame_info.total_size \
2220 - current_function_outgoing_args_size \
2221 - ((mips_abi != ABI_32 \
2222 && mips_abi != ABI_O64 \
2223 && mips_abi != ABI_EABI) \
2224 ? current_function_pretend_args_size \
2226 else if ((FROM) == ARG_POINTER_REGNUM) \
2227 (OFFSET) = (current_frame_info.total_size \
2228 - ((mips_abi != ABI_32 \
2229 && mips_abi != ABI_O64 \
2230 && mips_abi != ABI_EABI) \
2231 ? current_function_pretend_args_size \
2233 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2234 so we must add 4 bytes to the offset to get the right value. */ \
2235 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2237 if (leaf_function_p ()) \
2239 else (OFFSET) = current_frame_info.gp_sp_offset \
2240 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2241 * (BYTES_BIG_ENDIAN != 0)); \
2245 /* If we generate an insn to push BYTES bytes,
2246 this says how many the stack pointer really advances by.
2247 On the vax, sp@- in a byte insn really pushes a word. */
2249 /* #define PUSH_ROUNDING(BYTES) 0 */
2251 /* If defined, the maximum amount of space required for outgoing
2252 arguments will be computed and placed into the variable
2253 `current_function_outgoing_args_size'. No space will be pushed
2254 onto the stack for each call; instead, the function prologue
2255 should increase the stack frame size by this amount.
2257 It is not proper to define both `PUSH_ROUNDING' and
2258 `ACCUMULATE_OUTGOING_ARGS'. */
2259 #define ACCUMULATE_OUTGOING_ARGS
2261 /* Offset from the argument pointer register to the first argument's
2262 address. On some machines it may depend on the data type of the
2265 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2266 the first argument's address.
2268 On the MIPS, we must skip the first argument position if we are
2269 returning a structure or a union, to account for its address being
2270 passed in $4. However, at the current time, this produces a compiler
2271 that can't bootstrap, so comment it out for now. */
2274 #define FIRST_PARM_OFFSET(FNDECL) \
2276 && TREE_TYPE (FNDECL) != 0 \
2277 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2278 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2279 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2283 #define FIRST_PARM_OFFSET(FNDECL) 0
2286 /* When a parameter is passed in a register, stack space is still
2287 allocated for it. For the MIPS, stack space must be allocated, cf
2288 Asm Lang Prog Guide page 7-8.
2290 BEWARE that some space is also allocated for non existing arguments
2291 in register. In case an argument list is of form GF used registers
2292 are a0 (a2,a3), but we should push over a1... */
2294 #define REG_PARM_STACK_SPACE(FNDECL) \
2295 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2297 /* Define this if it is the responsibility of the caller to
2298 allocate the area reserved for arguments passed in registers.
2299 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2300 of this macro is to determine whether the space is included in
2301 `current_function_outgoing_args_size'. */
2302 #define OUTGOING_REG_PARM_STACK_SPACE
2304 /* Align stack frames on 64 bits (Double Word ). */
2305 #ifndef STACK_BOUNDARY
2306 #define STACK_BOUNDARY 64
2309 /* Make sure 4 words are always allocated on the stack. */
2311 #ifndef STACK_ARGS_ADJUST
2312 #define STACK_ARGS_ADJUST(SIZE) \
2314 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2315 SIZE.constant = 4 * UNITS_PER_WORD; \
2320 /* A C expression that should indicate the number of bytes of its
2321 own arguments that a function pops on returning, or 0
2322 if the function pops no arguments and the caller must therefore
2323 pop them all after the function returns.
2325 FUNDECL is the declaration node of the function (as a tree).
2327 FUNTYPE is a C variable whose value is a tree node that
2328 describes the function in question. Normally it is a node of
2329 type `FUNCTION_TYPE' that describes the data type of the function.
2330 From this it is possible to obtain the data types of the value
2331 and arguments (if known).
2333 When a call to a library function is being considered, FUNTYPE
2334 will contain an identifier node for the library function. Thus,
2335 if you need to distinguish among various library functions, you
2336 can do so by their names. Note that "library function" in this
2337 context means a function used to perform arithmetic, whose name
2338 is known specially in the compiler and was not mentioned in the
2339 C code being compiled.
2341 STACK-SIZE is the number of bytes of arguments passed on the
2342 stack. If a variable number of bytes is passed, it is zero, and
2343 argument popping will always be the responsibility of the
2344 calling function. */
2346 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2349 /* Symbolic macros for the registers used to return integer and floating
2352 #define GP_RETURN (GP_REG_FIRST + 2)
2353 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2355 /* Symbolic macros for the first/last argument registers. */
2357 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2358 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2359 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2360 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2362 #define MAX_ARGS_IN_REGISTERS 4
2364 /* Define how to find the value returned by a library function
2365 assuming the value has mode MODE. Because we define
2366 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2367 PROMOTE_MODE does. */
2369 #define LIBCALL_VALUE(MODE) \
2371 ((GET_MODE_CLASS (MODE) != MODE_INT \
2372 || GET_MODE_SIZE (MODE) >= 4) \
2375 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2376 && (! TARGET_SINGLE_FLOAT \
2377 || GET_MODE_SIZE (MODE) <= 4)) \
2381 /* Define how to find the value returned by a function.
2382 VALTYPE is the data type of the value (as a tree).
2383 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2384 otherwise, FUNC is 0. */
2386 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2389 /* 1 if N is a possible register number for a function value.
2390 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2391 Currently, R2 and F0 are only implemented here (C has no complex type) */
2393 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2395 /* 1 if N is a possible register number for function argument passing.
2396 We have no FP argument registers when soft-float. When FP registers
2397 are 32 bits, we can't directly reference the odd numbered ones. */
2399 #define FUNCTION_ARG_REGNO_P(N) \
2400 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2401 || ((! TARGET_SOFT_FLOAT \
2402 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2403 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2404 && ! fixed_regs[N]))
2406 /* A C expression which can inhibit the returning of certain function
2407 values in registers, based on the type of value. A nonzero value says
2408 to return the function value in memory, just as large structures are
2409 always returned. Here TYPE will be a C expression of type
2410 `tree', representing the data type of the value.
2412 Note that values of mode `BLKmode' must be explicitly
2413 handled by this macro. Also, the option `-fpcc-struct-return'
2414 takes effect regardless of this macro. On most systems, it is
2415 possible to leave the macro undefined; this causes a default
2416 definition to be used, whose value is the constant 1 for BLKmode
2417 values, and 0 otherwise.
2419 GCC normally converts 1 byte structures into chars, 2 byte
2420 structs into shorts, and 4 byte structs into ints, and returns
2421 them this way. Defining the following macro overrides this,
2422 to give us MIPS cc compatibility. */
2424 #define RETURN_IN_MEMORY(TYPE) \
2425 (TYPE_MODE (TYPE) == BLKmode)
2427 /* A code distinguishing the floating point format of the target
2428 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2429 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2431 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2434 /* Define a data type for recording info about an argument list
2435 during the scan of that argument list. This data type should
2436 hold all necessary information about the function itself
2437 and about the args processed so far, enough to enable macros
2438 such as FUNCTION_ARG to determine where the next arg should go.
2440 On the mips16, we need to keep track of which floating point
2441 arguments were passed in general registers, but would have been
2442 passed in the FP regs if this were a 32 bit function, so that we
2443 can move them to the FP regs if we wind up calling a 32 bit
2444 function. We record this information in fp_code, encoded in base
2445 four. A zero digit means no floating point argument, a one digit
2446 means an SFmode argument, and a two digit means a DFmode argument,
2447 and a three digit is not used. The low order digit is the first
2448 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2449 an SFmode argument. ??? A more sophisticated approach will be
2450 needed if MIPS_ABI != ABI_32. */
2452 typedef struct mips_args {
2453 int gp_reg_found; /* whether a gp register was found yet */
2454 int arg_number; /* argument number */
2455 int arg_words; /* # total words the arguments take */
2456 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2457 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2458 int fp_code; /* Mode of FP arguments (mips16) */
2459 int num_adjusts; /* number of adjustments made */
2460 /* Adjustments made to args pass in regs. */
2461 /* ??? The size is doubled to work around a
2462 bug in the code that sets the adjustments
2464 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2467 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2468 for a call to a function whose data type is FNTYPE.
2469 For a library call, FNTYPE is 0.
2473 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2474 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2476 /* Update the data in CUM to advance over an argument
2477 of mode MODE and data type TYPE.
2478 (TYPE is null for libcalls where that information may not be available.) */
2480 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2481 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2483 /* Determine where to put an argument to a function.
2484 Value is zero to push the argument on the stack,
2485 or a hard register in which to store the argument.
2487 MODE is the argument's machine mode.
2488 TYPE is the data type of the argument (as a tree).
2489 This is null for libcalls where that information may
2491 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2492 the preceding args and about the function being called.
2493 NAMED is nonzero if this argument is a named parameter
2494 (otherwise it is an extra parameter matching an ellipsis). */
2496 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2497 function_arg( &CUM, MODE, TYPE, NAMED)
2499 /* For an arg passed partly in registers and partly in memory,
2500 this is the number of registers used.
2501 For args passed entirely in registers or entirely in memory, zero. */
2503 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2504 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2506 /* If defined, a C expression that gives the alignment boundary, in
2507 bits, of an argument with the specified mode and type. If it is
2508 not defined, `PARM_BOUNDARY' is used for all arguments. */
2510 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2512 ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \
2514 : TYPE_ALIGN(TYPE)) \
2515 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2517 : GET_MODE_ALIGNMENT(MODE)))
2520 /* This macro generates the assembly code for function entry.
2521 FILE is a stdio stream to output the code to.
2522 SIZE is an int: how many units of temporary storage to allocate.
2523 Refer to the array `regs_ever_live' to determine which registers
2524 to save; `regs_ever_live[I]' is nonzero if register number I
2525 is ever used in the function. This macro is responsible for
2526 knowing which registers should not be saved even if used. */
2528 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2530 /* This macro generates the assembly code for function exit,
2531 on machines that need it. If FUNCTION_EPILOGUE is not defined
2532 then individual return instructions are generated for each
2533 return statement. Args are same as for FUNCTION_PROLOGUE. */
2535 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2537 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2539 #define MUST_SAVE_REGISTER(regno) \
2540 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2541 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2542 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2544 /* ALIGN FRAMES on double word boundaries */
2545 #ifndef MIPS_STACK_ALIGN
2546 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2550 /* Define the `__builtin_va_list' type for the ABI. */
2551 #define BUILD_VA_LIST_TYPE(VALIST) \
2552 (VALIST) = mips_build_va_list ()
2554 /* Implement `va_start' for varargs and stdarg. */
2555 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2556 mips_va_start (stdarg, valist, nextarg)
2558 /* Implement `va_arg'. */
2559 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2560 mips_va_arg (valist, type)
2562 /* Output assembler code to FILE to increment profiler label # LABELNO
2563 for profiling a function entry. */
2565 #define FUNCTION_PROFILER(FILE, LABELNO) \
2567 if (TARGET_MIPS16) \
2568 sorry ("mips16 function profiling"); \
2569 fprintf (FILE, "\t.set\tnoreorder\n"); \
2570 fprintf (FILE, "\t.set\tnoat\n"); \
2571 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2572 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2573 fprintf (FILE, "\tjal\t_mcount\n"); \
2575 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2576 TARGET_64BIT ? "dsubu" : "subu", \
2577 reg_names[STACK_POINTER_REGNUM], \
2578 reg_names[STACK_POINTER_REGNUM], \
2579 Pmode == DImode ? 16 : 8); \
2580 fprintf (FILE, "\t.set\treorder\n"); \
2581 fprintf (FILE, "\t.set\tat\n"); \
2584 /* Define this macro if the code for function profiling should come
2585 before the function prologue. Normally, the profiling code comes
2588 /* #define PROFILE_BEFORE_PROLOGUE */
2590 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2591 the stack pointer does not matter. The value is tested only in
2592 functions that have frame pointers.
2593 No definition is equivalent to always zero. */
2595 #define EXIT_IGNORE_STACK 1
2598 /* A C statement to output, on the stream FILE, assembler code for a
2599 block of data that contains the constant parts of a trampoline.
2600 This code should not include a label--the label is taken care of
2603 #define TRAMPOLINE_TEMPLATE(STREAM) \
2605 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2606 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2607 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2608 if (Pmode == DImode) \
2610 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2611 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2615 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2616 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2618 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2619 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2620 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2621 if (Pmode == DImode) \
2623 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2624 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2628 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2629 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2633 /* A C expression for the size in bytes of the trampoline, as an
2636 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2638 /* Alignment required for trampolines, in bits. */
2640 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2642 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2643 program and data caches. */
2645 #ifndef CACHE_FLUSH_FUNC
2646 #define CACHE_FLUSH_FUNC "_flush_cache"
2649 /* A C statement to initialize the variable parts of a trampoline.
2650 ADDR is an RTX for the address of the trampoline; FNADDR is an
2651 RTX for the address of the nested function; STATIC_CHAIN is an
2652 RTX for the static chain value that should be passed to the
2653 function when it is called. */
2655 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2658 if (Pmode == DImode) \
2660 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2661 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2665 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2666 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2669 /* Flush both caches. We need to flush the data cache in case \
2670 the system has a write-back cache. */ \
2671 /* ??? Should check the return value for errors. */ \
2672 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2673 0, VOIDmode, 3, addr, Pmode, \
2674 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2675 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2678 /* Addressing modes, and classification of registers for them. */
2680 /* #define HAVE_POST_INCREMENT 0 */
2681 /* #define HAVE_POST_DECREMENT 0 */
2683 /* #define HAVE_PRE_DECREMENT 0 */
2684 /* #define HAVE_PRE_INCREMENT 0 */
2686 /* These assume that REGNO is a hard or pseudo reg number.
2687 They give nonzero only if REGNO is a hard reg of the suitable class
2688 or a pseudo reg currently allocated to a suitable hard reg.
2689 These definitions are NOT overridden anywhere. */
2691 #define BASE_REG_P(regno, mode) \
2693 ? (M16_REG_P (regno) \
2694 || (regno) == FRAME_POINTER_REGNUM \
2695 || (regno) == ARG_POINTER_REGNUM \
2696 || ((regno) == STACK_POINTER_REGNUM \
2697 && (GET_MODE_SIZE (mode) == 4 \
2698 || GET_MODE_SIZE (mode) == 8))) \
2701 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2702 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2705 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2706 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2708 #define REGNO_OK_FOR_INDEX_P(regno) 0
2709 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2710 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2712 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2713 and check its validity for a certain class.
2714 We have two alternate definitions for each of them.
2715 The usual definition accepts all pseudo regs; the other rejects them all.
2716 The symbol REG_OK_STRICT causes the latter definition to be used.
2718 Most source files want to accept pseudo regs in the hope that
2719 they will get allocated to the class that the insn wants them to be in.
2720 Some source files that are used after register allocation
2721 need to be strict. */
2723 #ifndef REG_OK_STRICT
2725 #define REG_OK_STRICT_P 0
2726 #define REG_OK_FOR_INDEX_P(X) 0
2727 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2728 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2732 #define REG_OK_STRICT_P 1
2733 #define REG_OK_FOR_INDEX_P(X) 0
2734 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2735 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2740 /* Maximum number of registers that can appear in a valid memory address. */
2742 #define MAX_REGS_PER_ADDRESS 1
2744 /* A C compound statement with a conditional `goto LABEL;' executed
2745 if X (an RTX) is a legitimate memory address on the target
2746 machine for a memory operand of mode MODE.
2748 It usually pays to define several simpler macros to serve as
2749 subroutines for this one. Otherwise it may be too complicated
2752 This macro must exist in two variants: a strict variant and a
2753 non-strict one. The strict variant is used in the reload pass.
2754 It must be defined so that any pseudo-register that has not been
2755 allocated a hard register is considered a memory reference. In
2756 contexts where some kind of register is required, a
2757 pseudo-register with no hard register must be rejected.
2759 The non-strict variant is used in other passes. It must be
2760 defined to accept all pseudo-registers in every context where
2761 some kind of register is required.
2763 Compiler source files that want to use the strict variant of
2764 this macro define the macro `REG_OK_STRICT'. You should use an
2765 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2766 in that case and the non-strict variant otherwise.
2768 Typically among the subroutines used to define
2769 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2770 acceptable registers for various purposes (one for base
2771 registers, one for index registers, and so on). Then only these
2772 subroutine macros need have two variants; the higher levels of
2773 macros may be the same whether strict or not.
2775 Normally, constant addresses which are the sum of a `symbol_ref'
2776 and an integer are stored inside a `const' RTX to mark them as
2777 constant. Therefore, there is no need to recognize such sums
2778 specifically as legitimate addresses. Normally you would simply
2779 recognize any `const' as legitimate.
2781 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2782 constant sums that are not marked with `const'. It assumes
2783 that a naked `plus' indicates indexing. If so, then you *must*
2784 reject such naked constant sums as illegitimate addresses, so
2785 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2787 On some machines, whether a symbolic address is legitimate
2788 depends on the section that the address refers to. On these
2789 machines, define the macro `ENCODE_SECTION_INFO' to store the
2790 information into the `symbol_ref', and then check for it here.
2791 When you see a `const', you will have to look inside it to find
2792 the `symbol_ref' in order to determine the section. */
2795 #define GO_PRINTF(x) fprintf(stderr, (x))
2796 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2797 #define GO_DEBUG_RTX(x) debug_rtx(x)
2800 #define GO_PRINTF(x)
2801 #define GO_PRINTF2(x,y)
2802 #define GO_DEBUG_RTX(x)
2805 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2807 register rtx xinsn = (X); \
2809 if (TARGET_DEBUG_B_MODE) \
2811 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2812 (REG_OK_STRICT_P) ? "" : "not "); \
2813 GO_DEBUG_RTX (xinsn); \
2816 /* Check for constant before stripping off SUBREG, so that we don't \
2817 accept (subreg (const_int)) which will fail to reload. */ \
2818 if (CONSTANT_ADDRESS_P (xinsn) \
2819 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2820 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2823 while (GET_CODE (xinsn) == SUBREG) \
2824 xinsn = SUBREG_REG (xinsn); \
2826 /* The mips16 can only use the stack pointer as a base register when \
2827 loading SImode or DImode values. */ \
2828 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2831 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2833 register rtx xlow0 = XEXP (xinsn, 0); \
2834 register rtx xlow1 = XEXP (xinsn, 1); \
2836 while (GET_CODE (xlow0) == SUBREG) \
2837 xlow0 = SUBREG_REG (xlow0); \
2838 if (GET_CODE (xlow0) == REG \
2839 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2840 && mips_check_split (xlow1, MODE)) \
2844 if (GET_CODE (xinsn) == PLUS) \
2846 register rtx xplus0 = XEXP (xinsn, 0); \
2847 register rtx xplus1 = XEXP (xinsn, 1); \
2848 register enum rtx_code code0; \
2849 register enum rtx_code code1; \
2851 while (GET_CODE (xplus0) == SUBREG) \
2852 xplus0 = SUBREG_REG (xplus0); \
2853 code0 = GET_CODE (xplus0); \
2855 while (GET_CODE (xplus1) == SUBREG) \
2856 xplus1 = SUBREG_REG (xplus1); \
2857 code1 = GET_CODE (xplus1); \
2859 /* The mips16 can only use the stack pointer as a base register \
2860 when loading SImode or DImode values. */ \
2861 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2863 if (code1 == CONST_INT \
2864 && INTVAL (xplus1) >= -32768 \
2865 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2868 /* On the mips16, we represent GP relative offsets in RTL. \
2869 These are 16 bit signed values, and can serve as register \
2872 && mips16_gp_offset_p (xplus1)) \
2875 /* For some code sequences, you actually get better code by \
2876 pretending that the MIPS supports an address mode of a \
2877 constant address + a register, even though the real \
2878 machine doesn't support it. This is because the \
2879 assembler can use $r1 to load just the high 16 bits, add \
2880 in the register, and fold the low 16 bits into the memory \
2881 reference, whereas the compiler generates a 4 instruction \
2882 sequence. On the other hand, CSE is not as effective. \
2883 It would be a win to generate the lui directly, but the \
2884 MIPS assembler does not have syntax to generate the \
2885 appropriate relocation. */ \
2887 /* Also accept CONST_INT addresses here, so no else. */ \
2888 /* Reject combining an embedded PIC text segment reference \
2889 with a register. That requires an additional \
2891 /* ??? Reject combining an address with a register for the MIPS \
2892 64 bit ABI, because the SGI assembler can not handle this. */ \
2893 if (!TARGET_DEBUG_A_MODE \
2894 && (mips_abi == ABI_32 \
2895 || mips_abi == ABI_O64 \
2896 || mips_abi == ABI_EABI) \
2897 && CONSTANT_ADDRESS_P (xplus1) \
2898 && ! mips_split_addresses \
2899 && (!TARGET_EMBEDDED_PIC \
2901 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2902 && !TARGET_MIPS16) \
2907 if (TARGET_DEBUG_B_MODE) \
2908 GO_PRINTF ("Not a legitimate address\n"); \
2912 /* A C expression that is 1 if the RTX X is a constant which is a
2913 valid address. This is defined to be the same as `CONSTANT_P (X)',
2914 but rejecting CONST_DOUBLE. */
2915 /* When pic, we must reject addresses of the form symbol+large int.
2916 This is because an instruction `sw $4,s+70000' needs to be converted
2917 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2918 assembler would use $at as a temp to load in the large offset. In this
2919 case $at is already in use. We convert such problem addresses to
2920 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2921 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2922 #define CONSTANT_ADDRESS_P(X) \
2923 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2924 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2925 || (GET_CODE (X) == CONST \
2926 && ! (flag_pic && pic_address_needs_scratch (X)) \
2927 && (mips_abi == ABI_32 \
2928 || mips_abi == ABI_O64 \
2929 || mips_abi == ABI_EABI))) \
2930 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2932 /* Define this, so that when PIC, reload won't try to reload invalid
2933 addresses which require two reload registers. */
2935 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2937 /* Nonzero if the constant value X is a legitimate general operand.
2938 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2940 At present, GAS doesn't understand li.[sd], so don't allow it
2941 to be generated at present. Also, the MIPS assembler does not
2942 grok li.d Infinity. */
2944 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2945 Note that the Irix 6 assembler problem may already be fixed.
2946 Note also that the GET_CODE (X) == CONST test catches the mips16
2947 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2948 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2949 ABI_64 to work together, we'll need to fix this. */
2950 #define LEGITIMATE_CONSTANT_P(X) \
2951 ((GET_CODE (X) != CONST_DOUBLE \
2952 || mips_const_double_ok (X, GET_MODE (X))) \
2953 && ! (GET_CODE (X) == CONST \
2955 && (mips_abi == ABI_N32 \
2956 || mips_abi == ABI_64)) \
2957 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2959 /* A C compound statement that attempts to replace X with a valid
2960 memory address for an operand of mode MODE. WIN will be a C
2961 statement label elsewhere in the code; the macro definition may
2964 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2966 to avoid further processing if the address has become legitimate.
2968 X will always be the result of a call to `break_out_memory_refs',
2969 and OLDX will be the operand that was given to that function to
2972 The code generated by this macro should not alter the
2973 substructure of X. If it transforms X into a more legitimate
2974 form, it should assign X (which will always be a C variable) a
2977 It is not necessary for this macro to come up with a legitimate
2978 address. The compiler has standard ways of doing so in all
2979 cases. In fact, it is safe for this macro to do nothing. But
2980 often a machine-dependent strategy can generate better code.
2982 For the MIPS, transform:
2984 memory(X + <large int>)
2988 Y = <large int> & ~0x7fff;
2990 memory (Z + (<large int> & 0x7fff));
2992 This is for CSE to find several similar references, and only use one Z.
2994 When PIC, convert addresses of the form memory (symbol+large int) to
2995 memory (reg+large int). */
2998 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3000 register rtx xinsn = (X); \
3002 if (TARGET_DEBUG_B_MODE) \
3004 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3005 GO_DEBUG_RTX (xinsn); \
3008 if (mips_split_addresses && mips_check_split (X, MODE)) \
3010 /* ??? Is this ever executed? */ \
3011 X = gen_rtx_LO_SUM (Pmode, \
3012 copy_to_mode_reg (Pmode, \
3013 gen_rtx (HIGH, Pmode, X)), \
3018 if (GET_CODE (xinsn) == CONST \
3019 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3020 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3021 || (mips_abi != ABI_32 \
3022 && mips_abi != ABI_O64 \
3023 && mips_abi != ABI_EABI))) \
3025 rtx ptr_reg = gen_reg_rtx (Pmode); \
3026 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3028 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3030 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3031 if (SMALL_INT (constant)) \
3033 /* Otherwise we fall through so the code below will fix the \
3038 if (GET_CODE (xinsn) == PLUS) \
3040 register rtx xplus0 = XEXP (xinsn, 0); \
3041 register rtx xplus1 = XEXP (xinsn, 1); \
3042 register enum rtx_code code0 = GET_CODE (xplus0); \
3043 register enum rtx_code code1 = GET_CODE (xplus1); \
3045 if (code0 != REG && code1 == REG) \
3047 xplus0 = XEXP (xinsn, 1); \
3048 xplus1 = XEXP (xinsn, 0); \
3049 code0 = GET_CODE (xplus0); \
3050 code1 = GET_CODE (xplus1); \
3053 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3054 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3056 rtx int_reg = gen_reg_rtx (Pmode); \
3057 rtx ptr_reg = gen_reg_rtx (Pmode); \
3059 emit_move_insn (int_reg, \
3060 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3062 emit_insn (gen_rtx_SET (VOIDmode, \
3064 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3066 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3071 if (TARGET_DEBUG_B_MODE) \
3072 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3076 /* A C statement or compound statement with a conditional `goto
3077 LABEL;' executed if memory address X (an RTX) can have different
3078 meanings depending on the machine mode of the memory reference it
3081 Autoincrement and autodecrement addresses typically have
3082 mode-dependent effects because the amount of the increment or
3083 decrement is the size of the operand being addressed. Some
3084 machines have other mode-dependent addresses. Many RISC machines
3085 have no mode-dependent addresses.
3087 You may assume that ADDR is a valid address for the machine. */
3089 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3092 /* Define this macro if references to a symbol must be treated
3093 differently depending on something about the variable or
3094 function named by the symbol (such as what section it is in).
3096 The macro definition, if any, is executed immediately after the
3097 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3098 The value of the rtl will be a `mem' whose address is a
3101 The usual thing for this macro to do is to a flag in the
3102 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3103 name string in the `symbol_ref' (if one bit is not enough
3106 The best way to modify the name string is by adding text to the
3107 beginning, with suitable punctuation to prevent any ambiguity.
3108 Allocate the new name in `saveable_obstack'. You will have to
3109 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3110 and output the name accordingly.
3112 You can also check the information stored in the `symbol_ref' in
3113 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3114 `PRINT_OPERAND_ADDRESS'.
3116 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3119 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3120 symbols which are not in the .text section.
3122 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3123 constants which are put in the .text section. We also record the
3124 total length of all such strings; this total is used to decide
3125 whether we need to split the constant table, and need not be
3128 When not mips16 code nor embedded PIC, if a symbol is in a
3129 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3130 splitting the reference so that gas can generate a gp relative
3133 When TARGET_EMBEDDED_DATA is set, we assume that all const
3134 variables will be stored in ROM, which is too far from %gp to use
3135 %gprel addressing. Note that (1) we include "extern const"
3136 variables in this, which mips_select_section doesn't, and (2) we
3137 can't always tell if they're really const (they might be const C++
3138 objects with non-const constructors), so we err on the side of
3139 caution and won't use %gprel anyway (otherwise we'd have to defer
3140 this decision to the linker/loader). The handling of extern consts
3141 is why the DECL_INITIAL macros differ from mips_select_section.
3143 If you are changing this macro, you should look at
3144 mips_select_section and see if it needs a similar change. */
3146 #ifndef UNIQUE_SECTION_P
3147 #define UNIQUE_SECTION_P(DECL) (0)
3150 #define ENCODE_SECTION_INFO(DECL) \
3153 if (TARGET_MIPS16) \
3155 if (TREE_CODE (DECL) == STRING_CST \
3156 && ! flag_writable_strings \
3157 /* If this string is from a function, and the function will \
3158 go in a gnu linkonce section, then we can't directly \
3159 access the string. This gets an assembler error \
3160 "unsupported PC relative reference to different section".\
3161 If we modify SELECT_SECTION to put it in function_section\
3162 instead of text_section, it still fails because \
3163 DECL_SECTION_NAME isn't set until assemble_start_function.\
3164 If we fix that, it still fails because strings are shared\
3165 among multiple functions, and we have cross section \
3166 references again. We force it to work by putting string \
3167 addresses in the constant pool and indirecting. */ \
3168 && (! current_function_decl \
3169 || ! UNIQUE_SECTION_P (current_function_decl))) \
3171 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3172 mips_string_length += TREE_STRING_LENGTH (DECL); \
3176 if (TARGET_EMBEDDED_DATA \
3177 && (TREE_CODE (DECL) == VAR_DECL \
3178 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3179 && (!DECL_INITIAL (DECL) \
3180 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3182 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3185 else if (TARGET_EMBEDDED_PIC) \
3187 if (TREE_CODE (DECL) == VAR_DECL) \
3188 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3189 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3190 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3191 else if (TREE_CODE (DECL) == STRING_CST \
3192 && ! flag_writable_strings) \
3193 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3195 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3198 else if (TREE_CODE (DECL) == VAR_DECL \
3199 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3200 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3202 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3205 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3208 /* We can not perform GP optimizations on variables which are in \
3209 specific sections, except for .sdata and .sbss which are \
3211 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3212 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3214 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3216 if (size > 0 && size <= mips_section_threshold) \
3217 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3220 else if (HALF_PIC_P ()) \
3222 HALF_PIC_ENCODE (DECL); \
3227 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3228 'the start of the function that this code is output in'. */
3230 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3231 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3232 asm_fprintf ((FILE), "%U%s", \
3233 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3235 asm_fprintf ((FILE), "%U%s", (NAME))
3237 /* The mips16 wants the constant pool to be after the function,
3238 because the PC relative load instructions use unsigned offsets. */
3240 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3242 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3243 mips_string_length = 0;
3246 /* In mips16 mode, put most string constants after the function. */
3247 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3248 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3251 /* Specify the machine mode that this machine uses
3252 for the index in the tablejump instruction.
3253 ??? Using HImode in mips16 mode can cause overflow. However, the
3254 overflow is no more likely than the overflow in a branch
3255 instruction. Large functions can currently break in both ways. */
3256 #define CASE_VECTOR_MODE \
3257 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3259 /* Define as C expression which evaluates to nonzero if the tablejump
3260 instruction expects the table to contain offsets from the address of the
3262 Do not define this if the table should contain absolute addresses. */
3263 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3265 /* Specify the tree operation to be used to convert reals to integers. */
3266 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3268 /* This is the kind of divide that is easiest to do in the general case. */
3269 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3271 /* Define this as 1 if `char' should by default be signed; else as 0. */
3272 #ifndef DEFAULT_SIGNED_CHAR
3273 #define DEFAULT_SIGNED_CHAR 1
3276 /* Max number of bytes we can move from memory to memory
3277 in one reasonably fast instruction. */
3278 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3279 #define MAX_MOVE_MAX 8
3281 /* Define this macro as a C expression which is nonzero if
3282 accessing less than a word of memory (i.e. a `char' or a
3283 `short') is no faster than accessing a word of memory, i.e., if
3284 such access require more than one instruction or if there is no
3285 difference in cost between byte and (aligned) word loads.
3287 On RISC machines, it tends to generate better code to define
3288 this as 1, since it avoids making a QI or HI mode register. */
3289 #define SLOW_BYTE_ACCESS 1
3291 /* We assume that the store-condition-codes instructions store 0 for false
3292 and some other value for true. This is the value stored for true. */
3294 #define STORE_FLAG_VALUE 1
3296 /* Define this if zero-extension is slow (more than one real instruction). */
3297 #define SLOW_ZERO_EXTEND
3299 /* Define this to be nonzero if shift instructions ignore all but the low-order
3301 #define SHIFT_COUNT_TRUNCATED 1
3303 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3304 is done just by pretending it is already truncated. */
3305 /* In 64 bit mode, 32 bit instructions require that register values be properly
3306 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3307 converts a value >32 bits to a value <32 bits. */
3308 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3309 Something needs to be done about this. Perhaps not use any 32 bit
3310 instructions? Perhaps use PROMOTE_MODE? */
3311 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3312 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3314 /* Specify the machine mode that pointers have.
3315 After generation of rtl, the compiler makes no further distinction
3316 between pointers and any other objects of this machine mode.
3318 For MIPS we make pointers are the smaller of longs and gp-registers. */
3321 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3324 /* A function address in a call instruction
3325 is a word address (for indexing purposes)
3326 so give the MEM rtx a words's mode. */
3328 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3330 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3331 memset, instead of the BSD functions bcopy and bzero. */
3333 #if defined(MIPS_SYSV) || defined(OSF_OS)
3334 #define TARGET_MEM_FUNCTIONS
3338 /* A part of a C `switch' statement that describes the relative
3339 costs of constant RTL expressions. It must contain `case'
3340 labels for expression codes `const_int', `const', `symbol_ref',
3341 `label_ref' and `const_double'. Each case must ultimately reach
3342 a `return' statement to return the relative cost of the use of
3343 that kind of constant value in an expression. The cost may
3344 depend on the precise value of the constant, which is available
3345 for examination in X.
3347 CODE is the expression code--redundant, since it can be obtained
3348 with `GET_CODE (X)'. */
3350 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3352 if (! TARGET_MIPS16) \
3354 /* Always return 0, since we don't have different sized \
3355 instructions, hence different costs according to Richard \
3359 if ((OUTER_CODE) == SET) \
3361 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3363 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3364 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3365 return COSTS_N_INSNS (1); \
3367 return COSTS_N_INSNS (2); \
3369 /* A PLUS could be an address. We don't want to force an address \
3370 to use a register, so accept any signed 16 bit value without \
3372 if ((OUTER_CODE) == PLUS \
3373 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3375 /* A number between 1 and 8 inclusive is efficient for a shift. \
3376 Otherwise, we will need an extended instruction. */ \
3377 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3378 || (OUTER_CODE) == LSHIFTRT) \
3380 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3382 return COSTS_N_INSNS (1); \
3384 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3385 if ((OUTER_CODE) == XOR \
3386 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3388 /* We may be able to use slt or sltu for a comparison with a \
3389 signed 16 bit value. (The boundary conditions aren't quite \
3390 right, but this is just a heuristic anyhow.) */ \
3391 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3392 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3393 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3394 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3395 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3397 /* Equality comparisons with 0 are cheap. */ \
3398 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3399 && INTVAL (X) == 0) \
3402 /* Otherwise, work out the cost to load the value into a \
3404 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3405 return COSTS_N_INSNS (1); \
3406 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3407 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3408 return COSTS_N_INSNS (2); \
3410 return COSTS_N_INSNS (3); \
3413 return COSTS_N_INSNS (2); \
3417 rtx offset = const0_rtx; \
3418 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3420 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3422 /* Treat this like a signed 16 bit CONST_INT. */ \
3423 if ((OUTER_CODE) == PLUS) \
3425 else if ((OUTER_CODE) == SET) \
3426 return COSTS_N_INSNS (1); \
3428 return COSTS_N_INSNS (2); \
3431 if (GET_CODE (symref) == LABEL_REF) \
3432 return COSTS_N_INSNS (2); \
3434 if (GET_CODE (symref) != SYMBOL_REF) \
3435 return COSTS_N_INSNS (4); \
3437 /* let's be paranoid.... */ \
3438 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3439 return COSTS_N_INSNS (2); \
3441 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3445 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3447 case CONST_DOUBLE: \
3450 if (TARGET_MIPS16) \
3451 return COSTS_N_INSNS (4); \
3452 split_double (X, &high, &low); \
3453 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3454 || low == CONST0_RTX (GET_MODE (low))) \
3458 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3459 This can be used, for example, to indicate how costly a multiply
3460 instruction is. In writing this macro, you can use the construct
3461 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3463 This macro is optional; do not define it if the default cost
3464 assumptions are adequate for the target machine.
3466 If -mdebugd is used, change the multiply cost to 2, so multiply by
3467 a constant isn't converted to a series of shifts. This helps
3468 strength reduction, and also makes it easier to identify what the
3469 compiler is doing. */
3471 /* ??? Fix this to be right for the R8000. */
3472 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3475 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3476 if (simple_memory_operand (X, GET_MODE (X))) \
3477 return COSTS_N_INSNS (num_words); \
3479 return COSTS_N_INSNS (2*num_words); \
3483 return COSTS_N_INSNS (6); \
3486 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3491 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3492 return COSTS_N_INSNS (2); \
3499 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3500 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3506 enum machine_mode xmode = GET_MODE (X); \
3507 if (xmode == SFmode || xmode == DFmode) \
3508 return COSTS_N_INSNS (1); \
3510 return COSTS_N_INSNS (4); \
3516 enum machine_mode xmode = GET_MODE (X); \
3517 if (xmode == SFmode || xmode == DFmode) \
3519 if (mips_cpu == PROCESSOR_R3000 \
3520 || mips_cpu == PROCESSOR_R3900) \
3521 return COSTS_N_INSNS (2); \
3522 else if (mips_cpu == PROCESSOR_R6000) \
3523 return COSTS_N_INSNS (3); \
3525 return COSTS_N_INSNS (6); \
3528 if (xmode == DImode && !TARGET_64BIT) \
3529 return COSTS_N_INSNS (4); \
3535 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3542 enum machine_mode xmode = GET_MODE (X); \
3543 if (xmode == SFmode) \
3545 if (mips_cpu == PROCESSOR_R3000 \
3546 || mips_cpu == PROCESSOR_R3900 \
3547 || mips_cpu == PROCESSOR_R5000) \
3548 return COSTS_N_INSNS (4); \
3549 else if (mips_cpu == PROCESSOR_R6000) \
3550 return COSTS_N_INSNS (5); \
3552 return COSTS_N_INSNS (7); \
3555 if (xmode == DFmode) \
3557 if (mips_cpu == PROCESSOR_R3000 \
3558 || mips_cpu == PROCESSOR_R3900 \
3559 || mips_cpu == PROCESSOR_R5000) \
3560 return COSTS_N_INSNS (5); \
3561 else if (mips_cpu == PROCESSOR_R6000) \
3562 return COSTS_N_INSNS (6); \
3564 return COSTS_N_INSNS (8); \
3567 if (mips_cpu == PROCESSOR_R3000) \
3568 return COSTS_N_INSNS (12); \
3569 else if (mips_cpu == PROCESSOR_R3900) \
3570 return COSTS_N_INSNS (2); \
3571 else if (mips_cpu == PROCESSOR_R6000) \
3572 return COSTS_N_INSNS (17); \
3573 else if (mips_cpu == PROCESSOR_R5000) \
3574 return COSTS_N_INSNS (5); \
3576 return COSTS_N_INSNS (10); \
3582 enum machine_mode xmode = GET_MODE (X); \
3583 if (xmode == SFmode) \
3585 if (mips_cpu == PROCESSOR_R3000 \
3586 || mips_cpu == PROCESSOR_R3900) \
3587 return COSTS_N_INSNS (12); \
3588 else if (mips_cpu == PROCESSOR_R6000) \
3589 return COSTS_N_INSNS (15); \
3591 return COSTS_N_INSNS (23); \
3594 if (xmode == DFmode) \
3596 if (mips_cpu == PROCESSOR_R3000 \
3597 || mips_cpu == PROCESSOR_R3900) \
3598 return COSTS_N_INSNS (19); \
3599 else if (mips_cpu == PROCESSOR_R6000) \
3600 return COSTS_N_INSNS (16); \
3602 return COSTS_N_INSNS (36); \
3605 /* fall through */ \
3609 if (mips_cpu == PROCESSOR_R3000 \
3610 || mips_cpu == PROCESSOR_R3900) \
3611 return COSTS_N_INSNS (35); \
3612 else if (mips_cpu == PROCESSOR_R6000) \
3613 return COSTS_N_INSNS (38); \
3614 else if (mips_cpu == PROCESSOR_R5000) \
3615 return COSTS_N_INSNS (36); \
3617 return COSTS_N_INSNS (69); \
3620 /* A sign extend from SImode to DImode in 64 bit mode is often \
3621 zero instructions, because the result can often be used \
3622 directly by another instruction; we'll call it one. */ \
3623 if (TARGET_64BIT && GET_MODE (X) == DImode \
3624 && GET_MODE (XEXP (X, 0)) == SImode) \
3625 return COSTS_N_INSNS (1); \
3627 return COSTS_N_INSNS (2); \
3630 if (TARGET_64BIT && GET_MODE (X) == DImode \
3631 && GET_MODE (XEXP (X, 0)) == SImode) \
3632 return COSTS_N_INSNS (2); \
3634 return COSTS_N_INSNS (1);
3636 /* An expression giving the cost of an addressing mode that
3637 contains ADDRESS. If not defined, the cost is computed from the
3638 form of the ADDRESS expression and the `CONST_COSTS' values.
3640 For most CISC machines, the default cost is a good approximation
3641 of the true cost of the addressing mode. However, on RISC
3642 machines, all instructions normally have the same length and
3643 execution time. Hence all addresses will have equal costs.
3645 In cases where more than one form of an address is known, the
3646 form with the lowest cost will be used. If multiple forms have
3647 the same, lowest, cost, the one that is the most complex will be
3650 For example, suppose an address that is equal to the sum of a
3651 register and a constant is used twice in the same basic block.
3652 When this macro is not defined, the address will be computed in
3653 a register and memory references will be indirect through that
3654 register. On machines where the cost of the addressing mode
3655 containing the sum is no higher than that of a simple indirect
3656 reference, this will produce an additional instruction and
3657 possibly require an additional register. Proper specification
3658 of this macro eliminates this overhead for such machines.
3660 Similar use of this macro is made in strength reduction of loops.
3662 ADDRESS need not be valid as an address. In such a case, the
3663 cost is not relevant and can be any value; invalid addresses
3664 need not be assigned a different cost.
3666 On machines where an address involving more than one register is
3667 as cheap as an address computation involving only one register,
3668 defining `ADDRESS_COST' to reflect this can cause two registers
3669 to be live over a region of code where only one would have been
3670 if `ADDRESS_COST' were not defined in that manner. This effect
3671 should be considered in the definition of this macro.
3672 Equivalent costs should probably only be given to addresses with
3673 different numbers of registers on machines with lots of registers.
3675 This macro will normally either not be defined or be defined as
3678 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3680 /* A C expression for the cost of moving data from a register in
3681 class FROM to one in class TO. The classes are expressed using
3682 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3683 the default; other values are interpreted relative to that.
3685 It is not required that the cost always equal 2 when FROM is the
3686 same as TO; on some machines it is expensive to move between
3687 registers if they are not general registers.
3689 If reload sees an insn consisting of a single `set' between two
3690 hard registers, and if `REGISTER_MOVE_COST' applied to their
3691 classes returns a value of 2, reload does not check to ensure
3692 that the constraints of the insn are met. Setting a cost of
3693 other than 2 will allow reload to verify that the constraints are
3694 met. You should do this if the `movM' pattern's constraints do
3695 not allow such copying.
3697 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3698 registers the same as for one of moving general registers to
3699 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3700 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3701 isn't clear if it is wise. And it might not work in all cases. We
3702 could solve the DImode LO reg problem by using a multiply, just like
3703 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3704 by using divide instructions. divu puts the remainder in the HI
3705 reg, so doing a divide by -1 will move the value in the HI reg for
3706 all values except -1. We could handle that case by using a signed
3707 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3708 compare/branch to test the input value to see which instruction we
3709 need to use. This gets pretty messy, but it is feasible. */
3711 #define REGISTER_MOVE_COST(FROM, TO) \
3712 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3713 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3714 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3715 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3716 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3717 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3718 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3719 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3720 : (((FROM) == HI_REG || (FROM) == LO_REG \
3721 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3722 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3723 : (((TO) == HI_REG || (TO) == LO_REG \
3724 || (TO) == MD_REGS || (TO) == HILO_REG) \
3725 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3726 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3727 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3730 /* ??? Fix this to be right for the R8000. */
3731 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3732 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3733 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3735 /* Define if copies to/from condition code registers should be avoided.
3737 This is needed for the MIPS because reload_outcc is not complete;
3738 it needs to handle cases where the source is a general or another
3739 condition code register. */
3740 #define AVOID_CCMODE_COPIES
3742 /* A C expression for the cost of a branch instruction. A value of
3743 1 is the default; other values are interpreted relative to that. */
3745 /* ??? Fix this to be right for the R8000. */
3746 #define BRANCH_COST \
3748 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3751 /* A C statement (sans semicolon) to update the integer variable COST
3752 based on the relationship between INSN that is dependent on
3753 DEP_INSN through the dependence LINK. The default is to make no
3754 adjustment to COST. On the MIPS, ignore the cost of anti- and
3755 output-dependencies. */
3757 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3758 if (REG_NOTE_KIND (LINK) != 0) \
3759 (COST) = 0; /* Anti or output dependence. */
3761 /* If defined, modifies the length assigned to instruction INSN as a
3762 function of the context in which it is used. LENGTH is an lvalue
3763 that contains the initially computed length of the insn and should
3764 be updated with the correct length of the insn. */
3765 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3766 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3769 /* Optionally define this if you have added predicates to
3770 `MACHINE.c'. This macro is called within an initializer of an
3771 array of structures. The first field in the structure is the
3772 name of a predicate and the second field is an array of rtl
3773 codes. For each predicate, list all rtl codes that can be in
3774 expressions matched by the predicate. The list should have a
3775 trailing comma. Here is an example of two entries in the list
3776 for a typical RISC machine:
3778 #define PREDICATE_CODES \
3779 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3780 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3782 Defining this macro does not affect the generated code (however,
3783 incorrect definitions that omit an rtl code that may be matched
3784 by the predicate can cause the compiler to malfunction).
3785 Instead, it allows the table built by `genrecog' to be more
3786 compact and efficient, thus speeding up the compiler. The most
3787 important predicates to include in the list specified by this
3788 macro are thoses used in the most insn patterns. */
3790 #define PREDICATE_CODES \
3791 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3792 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3793 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3794 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3795 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3796 {"small_int", { CONST_INT }}, \
3797 {"large_int", { CONST_INT }}, \
3798 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3799 {"const_float_1_operand", { CONST_DOUBLE }}, \
3800 {"simple_memory_operand", { MEM, SUBREG }}, \
3801 {"equality_op", { EQ, NE }}, \
3802 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3804 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3805 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3806 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3807 SYMBOL_REF, LABEL_REF, SUBREG, \
3809 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3810 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3811 MEM, SIGN_EXTEND }}, \
3812 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3813 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3815 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3817 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3819 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3820 SYMBOL_REF, LABEL_REF, SUBREG, \
3821 REG, SIGN_EXTEND }}, \
3822 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3823 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3824 CONST_DOUBLE, CONST }}, \
3825 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3826 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3828 /* A list of predicates that do special things with modes, and so
3829 should not elicit warnings for VOIDmode match_operand. */
3831 #define SPECIAL_MODE_PREDICATES \
3832 "pc_or_label_operand",
3835 /* If defined, a C statement to be executed just prior to the
3836 output of assembler code for INSN, to modify the extracted
3837 operands so they will be output differently.
3839 Here the argument OPVEC is the vector containing the operands
3840 extracted from INSN, and NOPERANDS is the number of elements of
3841 the vector which contain meaningful data for this insn. The
3842 contents of this vector are what will be used to convert the
3843 insn template into assembler code, so you can change the
3844 assembler output by changing the contents of the vector.
3846 We use it to check if the current insn needs a nop in front of it
3847 because of load delays, and also to update the delay slot
3850 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3851 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3854 /* Control the assembler format that we output. */
3856 /* Output at beginning of assembler file.
3857 If we are optimizing to use the global pointer, create a temporary
3858 file to hold all of the text stuff, and write it out to the end.
3859 This is needed because the MIPS assembler is evidently one pass,
3860 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3861 declaration when the code is processed, it generates a two
3862 instruction sequence. */
3864 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3866 /* Output to assembler file text saying following lines
3867 may contain character constants, extra white space, comments, etc. */
3869 #define ASM_APP_ON " #APP\n"
3871 /* Output to assembler file text saying following lines
3872 no longer contain unusual constructs. */
3874 #define ASM_APP_OFF " #NO_APP\n"
3876 /* How to refer to registers in assembler output.
3877 This sequence is indexed by compiler's hard-register-number (see above).
3879 In order to support the two different conventions for register names,
3880 we use the name of a table set up in mips.c, which is overwritten
3881 if -mrnames is used. */
3883 #define REGISTER_NAMES \
3885 &mips_reg_names[ 0][0], \
3886 &mips_reg_names[ 1][0], \
3887 &mips_reg_names[ 2][0], \
3888 &mips_reg_names[ 3][0], \
3889 &mips_reg_names[ 4][0], \
3890 &mips_reg_names[ 5][0], \
3891 &mips_reg_names[ 6][0], \
3892 &mips_reg_names[ 7][0], \
3893 &mips_reg_names[ 8][0], \
3894 &mips_reg_names[ 9][0], \
3895 &mips_reg_names[10][0], \
3896 &mips_reg_names[11][0], \
3897 &mips_reg_names[12][0], \
3898 &mips_reg_names[13][0], \
3899 &mips_reg_names[14][0], \
3900 &mips_reg_names[15][0], \
3901 &mips_reg_names[16][0], \
3902 &mips_reg_names[17][0], \
3903 &mips_reg_names[18][0], \
3904 &mips_reg_names[19][0], \
3905 &mips_reg_names[20][0], \
3906 &mips_reg_names[21][0], \
3907 &mips_reg_names[22][0], \
3908 &mips_reg_names[23][0], \
3909 &mips_reg_names[24][0], \
3910 &mips_reg_names[25][0], \
3911 &mips_reg_names[26][0], \
3912 &mips_reg_names[27][0], \
3913 &mips_reg_names[28][0], \
3914 &mips_reg_names[29][0], \
3915 &mips_reg_names[30][0], \
3916 &mips_reg_names[31][0], \
3917 &mips_reg_names[32][0], \
3918 &mips_reg_names[33][0], \
3919 &mips_reg_names[34][0], \
3920 &mips_reg_names[35][0], \
3921 &mips_reg_names[36][0], \
3922 &mips_reg_names[37][0], \
3923 &mips_reg_names[38][0], \
3924 &mips_reg_names[39][0], \
3925 &mips_reg_names[40][0], \
3926 &mips_reg_names[41][0], \
3927 &mips_reg_names[42][0], \
3928 &mips_reg_names[43][0], \
3929 &mips_reg_names[44][0], \
3930 &mips_reg_names[45][0], \
3931 &mips_reg_names[46][0], \
3932 &mips_reg_names[47][0], \
3933 &mips_reg_names[48][0], \
3934 &mips_reg_names[49][0], \
3935 &mips_reg_names[50][0], \
3936 &mips_reg_names[51][0], \
3937 &mips_reg_names[52][0], \
3938 &mips_reg_names[53][0], \
3939 &mips_reg_names[54][0], \
3940 &mips_reg_names[55][0], \
3941 &mips_reg_names[56][0], \
3942 &mips_reg_names[57][0], \
3943 &mips_reg_names[58][0], \
3944 &mips_reg_names[59][0], \
3945 &mips_reg_names[60][0], \
3946 &mips_reg_names[61][0], \
3947 &mips_reg_names[62][0], \
3948 &mips_reg_names[63][0], \
3949 &mips_reg_names[64][0], \
3950 &mips_reg_names[65][0], \
3951 &mips_reg_names[66][0], \
3952 &mips_reg_names[67][0], \
3953 &mips_reg_names[68][0], \
3954 &mips_reg_names[69][0], \
3955 &mips_reg_names[70][0], \
3956 &mips_reg_names[71][0], \
3957 &mips_reg_names[72][0], \
3958 &mips_reg_names[73][0], \
3959 &mips_reg_names[74][0], \
3960 &mips_reg_names[75][0], \
3963 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3964 So define this for it. */
3965 #define DEBUG_REGISTER_NAMES \
3967 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3968 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3969 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3970 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3971 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3972 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3973 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3974 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3975 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3976 "$fcc5","$fcc6","$fcc7","$rap" \
3979 /* If defined, a C initializer for an array of structures
3980 containing a name and a register number. This macro defines
3981 additional names for hard registers, thus allowing the `asm'
3982 option in declarations to refer to registers using alternate
3985 We define both names for the integer registers here. */
3987 #define ADDITIONAL_REGISTER_NAMES \
3989 { "$0", 0 + GP_REG_FIRST }, \
3990 { "$1", 1 + GP_REG_FIRST }, \
3991 { "$2", 2 + GP_REG_FIRST }, \
3992 { "$3", 3 + GP_REG_FIRST }, \
3993 { "$4", 4 + GP_REG_FIRST }, \
3994 { "$5", 5 + GP_REG_FIRST }, \
3995 { "$6", 6 + GP_REG_FIRST }, \
3996 { "$7", 7 + GP_REG_FIRST }, \
3997 { "$8", 8 + GP_REG_FIRST }, \
3998 { "$9", 9 + GP_REG_FIRST }, \
3999 { "$10", 10 + GP_REG_FIRST }, \
4000 { "$11", 11 + GP_REG_FIRST }, \
4001 { "$12", 12 + GP_REG_FIRST }, \
4002 { "$13", 13 + GP_REG_FIRST }, \
4003 { "$14", 14 + GP_REG_FIRST }, \
4004 { "$15", 15 + GP_REG_FIRST }, \
4005 { "$16", 16 + GP_REG_FIRST }, \
4006 { "$17", 17 + GP_REG_FIRST }, \
4007 { "$18", 18 + GP_REG_FIRST }, \
4008 { "$19", 19 + GP_REG_FIRST }, \
4009 { "$20", 20 + GP_REG_FIRST }, \
4010 { "$21", 21 + GP_REG_FIRST }, \
4011 { "$22", 22 + GP_REG_FIRST }, \
4012 { "$23", 23 + GP_REG_FIRST }, \
4013 { "$24", 24 + GP_REG_FIRST }, \
4014 { "$25", 25 + GP_REG_FIRST }, \
4015 { "$26", 26 + GP_REG_FIRST }, \
4016 { "$27", 27 + GP_REG_FIRST }, \
4017 { "$28", 28 + GP_REG_FIRST }, \
4018 { "$29", 29 + GP_REG_FIRST }, \
4019 { "$30", 30 + GP_REG_FIRST }, \
4020 { "$31", 31 + GP_REG_FIRST }, \
4021 { "$sp", 29 + GP_REG_FIRST }, \
4022 { "$fp", 30 + GP_REG_FIRST }, \
4023 { "at", 1 + GP_REG_FIRST }, \
4024 { "v0", 2 + GP_REG_FIRST }, \
4025 { "v1", 3 + GP_REG_FIRST }, \
4026 { "a0", 4 + GP_REG_FIRST }, \
4027 { "a1", 5 + GP_REG_FIRST }, \
4028 { "a2", 6 + GP_REG_FIRST }, \
4029 { "a3", 7 + GP_REG_FIRST }, \
4030 { "t0", 8 + GP_REG_FIRST }, \
4031 { "t1", 9 + GP_REG_FIRST }, \
4032 { "t2", 10 + GP_REG_FIRST }, \
4033 { "t3", 11 + GP_REG_FIRST }, \
4034 { "t4", 12 + GP_REG_FIRST }, \
4035 { "t5", 13 + GP_REG_FIRST }, \
4036 { "t6", 14 + GP_REG_FIRST }, \
4037 { "t7", 15 + GP_REG_FIRST }, \
4038 { "s0", 16 + GP_REG_FIRST }, \
4039 { "s1", 17 + GP_REG_FIRST }, \
4040 { "s2", 18 + GP_REG_FIRST }, \
4041 { "s3", 19 + GP_REG_FIRST }, \
4042 { "s4", 20 + GP_REG_FIRST }, \
4043 { "s5", 21 + GP_REG_FIRST }, \
4044 { "s6", 22 + GP_REG_FIRST }, \
4045 { "s7", 23 + GP_REG_FIRST }, \
4046 { "t8", 24 + GP_REG_FIRST }, \
4047 { "t9", 25 + GP_REG_FIRST }, \
4048 { "k0", 26 + GP_REG_FIRST }, \
4049 { "k1", 27 + GP_REG_FIRST }, \
4050 { "gp", 28 + GP_REG_FIRST }, \
4051 { "sp", 29 + GP_REG_FIRST }, \
4052 { "fp", 30 + GP_REG_FIRST }, \
4053 { "ra", 31 + GP_REG_FIRST }, \
4054 { "$sp", 29 + GP_REG_FIRST }, \
4055 { "$fp", 30 + GP_REG_FIRST } \
4058 /* Define results of standard character escape sequences. */
4059 #define TARGET_BELL 007
4060 #define TARGET_BS 010
4061 #define TARGET_TAB 011
4062 #define TARGET_NEWLINE 012
4063 #define TARGET_VT 013
4064 #define TARGET_FF 014
4065 #define TARGET_CR 015
4067 /* A C compound statement to output to stdio stream STREAM the
4068 assembler syntax for an instruction operand X. X is an RTL
4071 CODE is a value that can be used to specify one of several ways
4072 of printing the operand. It is used when identical operands
4073 must be printed differently depending on the context. CODE
4074 comes from the `%' specification that was used to request
4075 printing of the operand. If the specification was just `%DIGIT'
4076 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4077 is the ASCII code for LTR.
4079 If X is a register, this macro should print the register's name.
4080 The names can be found in an array `reg_names' whose type is
4081 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4083 When the machine description has a specification `%PUNCT' (a `%'
4084 followed by a punctuation character), this macro is called with
4085 a null pointer for X and the punctuation character for CODE.
4087 See mips.c for the MIPS specific codes. */
4089 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4091 /* A C expression which evaluates to true if CODE is a valid
4092 punctuation character for use in the `PRINT_OPERAND' macro. If
4093 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4094 punctuation characters (except for the standard one, `%') are
4095 used in this way. */
4097 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4099 /* A C compound statement to output to stdio stream STREAM the
4100 assembler syntax for an instruction operand that is a memory
4101 reference whose address is ADDR. ADDR is an RTL expression.
4103 On some machines, the syntax for a symbolic address depends on
4104 the section that the address refers to. On these machines,
4105 define the macro `ENCODE_SECTION_INFO' to store the information
4106 into the `symbol_ref', and then check for it here. */
4108 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4111 /* A C statement, to be executed after all slot-filler instructions
4112 have been output. If necessary, call `dbr_sequence_length' to
4113 determine the number of slots filled in a sequence (zero if not
4114 currently outputting a sequence), to decide how many no-ops to
4115 output, or whatever.
4117 Don't define this macro if it has nothing to do, but it is
4118 helpful in reading assembly output if the extent of the delay
4119 sequence is made explicit (e.g. with white space).
4121 Note that output routines for instructions with delay slots must
4122 be prepared to deal with not being output as part of a sequence
4123 (i.e. when the scheduling pass is not run, or when no slot
4124 fillers could be found.) The variable `final_sequence' is null
4125 when not processing a sequence, otherwise it contains the
4126 `sequence' rtx being output. */
4128 #define DBR_OUTPUT_SEQEND(STREAM) \
4131 if (set_nomacro > 0 && --set_nomacro == 0) \
4132 fputs ("\t.set\tmacro\n", STREAM); \
4134 if (set_noreorder > 0 && --set_noreorder == 0) \
4135 fputs ("\t.set\treorder\n", STREAM); \
4137 dslots_jump_filled++; \
4138 fputs ("\n", STREAM); \
4143 /* How to tell the debugger about changes of source files. Note, the
4144 mips ECOFF format cannot deal with changes of files inside of
4145 functions, which means the output of parser generators like bison
4146 is generally not debuggable without using the -l switch. Lose,
4147 lose, lose. Silicon graphics seems to want all .file's hardwired
4150 #ifndef SET_FILE_NUMBER
4151 #define SET_FILE_NUMBER() ++num_source_filenames
4154 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4155 mips_output_filename (STREAM, NAME)
4157 /* This is defined so that it can be overridden in iris6.h. */
4158 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4161 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4162 output_quoted_string (STREAM, NAME); \
4163 fputs ("\n", STREAM); \
4167 /* This is how to output a note the debugger telling it the line number
4168 to which the following sequence of instructions corresponds.
4169 Silicon graphics puts a label after each .loc. */
4171 #ifndef LABEL_AFTER_LOC
4172 #define LABEL_AFTER_LOC(STREAM)
4175 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4176 mips_output_lineno (STREAM, LINE)
4178 /* The MIPS implementation uses some labels for its own purpose. The
4179 following lists what labels are created, and are all formed by the
4180 pattern $L[a-z].*. The machine independent portion of GCC creates
4181 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4183 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4184 $Lb[0-9]+ Begin blocks for MIPS debug support
4185 $Lc[0-9]+ Label for use in s<xx> operation.
4186 $Le[0-9]+ End blocks for MIPS debug support
4187 $Lp\..+ Half-pic labels. */
4189 /* This is how to output the definition of a user-level label named NAME,
4190 such as the label on a static function or variable NAME.
4192 If we are optimizing the gp, remember that this label has been put
4193 out, so we know not to emit an .extern for it in mips_asm_file_end.
4194 We use one of the common bits in the IDENTIFIER tree node for this,
4195 since those bits seem to be unused, and we don't have any method
4196 of getting the decl nodes from the name. */
4198 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4200 assemble_name (STREAM, NAME); \
4201 fputs (":\n", STREAM); \
4205 /* A C statement (sans semicolon) to output to the stdio stream
4206 STREAM any text necessary for declaring the name NAME of an
4207 initialized variable which is being defined. This macro must
4208 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4209 The argument DECL is the `VAR_DECL' tree node representing the
4212 If this macro is not defined, then the variable name is defined
4213 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4215 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4218 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4219 HALF_PIC_DECLARE (NAME); \
4224 /* This is how to output a command to make the user-level label named NAME
4225 defined for reference from other files. */
4227 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4229 fputs ("\t.globl\t", STREAM); \
4230 assemble_name (STREAM, NAME); \
4231 fputs ("\n", STREAM); \
4234 /* This says how to define a global common symbol. */
4236 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4238 /* If the target wants uninitialized const declarations in \
4239 .rdata then don't put them in .comm */ \
4240 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4241 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4242 && (DECL_INITIAL (DECL) == 0 \
4243 || DECL_INITIAL (DECL) == error_mark_node)) \
4245 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4246 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4248 READONLY_DATA_SECTION (); \
4249 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4250 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4254 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4259 /* This says how to define a local common symbol (ie, not visible to
4262 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4263 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4266 /* This says how to output an external. It would be possible not to
4267 output anything and let undefined symbol become external. However
4268 the assembler uses length information on externals to allocate in
4269 data/sdata bss/sbss, thereby saving exec time. */
4271 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4272 mips_output_external(STREAM,DECL,NAME)
4274 /* This says what to print at the end of the assembly file */
4275 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4278 /* This is how to declare a function name. The actual work of
4279 emitting the label is moved to function_prologue, so that we can
4280 get the line number correctly emitted before the .ent directive,
4281 and after any .file directives.
4283 Also, switch files if we are optimizing the global pointer. */
4285 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4287 extern FILE *asm_out_text_file; \
4288 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4290 STREAM = asm_out_text_file; \
4291 /* ??? text_section gets called too soon. If the previous \
4292 function is in a special section and we're not, we have \
4293 to switch back to the text section. We can't call \
4294 text_section again as gcc thinks we're already there. */ \
4295 /* ??? See varasm.c. There are other things that get output \
4296 too early, like alignment (before we've switched STREAM). */ \
4297 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4298 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4301 HALF_PIC_DECLARE (NAME); \
4304 /* This is how to output an internal numbered label where
4305 PREFIX is the class of label and NUM is the number within the class. */
4307 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4308 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4310 /* This is how to store into the string LABEL
4311 the symbol_ref name of an internal numbered label where
4312 PREFIX is the class of label and NUM is the number within the class.
4313 This is suitable for output with `assemble_name'. */
4315 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4316 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4318 /* This is how to output an assembler line defining a `double' constant. */
4320 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4321 mips_output_double (STREAM, VALUE)
4324 /* This is how to output an assembler line defining a `float' constant. */
4326 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4327 mips_output_float (STREAM, VALUE)
4330 /* This is how to output an assembler line defining an `int' constant. */
4332 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4334 fprintf (STREAM, "\t.word\t"); \
4335 output_addr_const (STREAM, (VALUE)); \
4336 fprintf (STREAM, "\n"); \
4339 /* Likewise for 64 bit, `char' and `short' constants.
4341 FIXME: operand_subword can't handle some complex constant expressions
4342 that output_addr_const can (for example it does not call
4343 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4344 rely on that to avoid operand_subword for most of the cases where this
4345 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4346 or the same case with the type of 'i' changed to long long.
4350 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4352 if (TARGET_64BIT || TARGET_GAS) \
4354 fprintf (STREAM, "\t.dword\t"); \
4355 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4356 /* We can't use 'X' for negative numbers, because then we won't \
4357 get the right value for the upper 32 bits. */ \
4358 output_addr_const (STREAM, VALUE); \
4360 /* We must use 'X', because otherwise LONG_MIN will print as \
4361 a number that the Irix 6 assembler won't accept. */ \
4362 print_operand (STREAM, VALUE, 'X'); \
4363 fprintf (STREAM, "\n"); \
4367 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4368 UNITS_PER_WORD, 1); \
4369 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4370 UNITS_PER_WORD, 1); \
4374 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4376 fprintf (STREAM, "\t.half\t"); \
4377 output_addr_const (STREAM, (VALUE)); \
4378 fprintf (STREAM, "\n"); \
4381 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4383 fprintf (STREAM, "\t.byte\t"); \
4384 output_addr_const (STREAM, (VALUE)); \
4385 fprintf (STREAM, "\n"); \
4388 /* This is how to output an assembler line for a numeric constant byte. */
4390 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4391 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4393 /* This is how to output an element of a case-vector that is absolute. */
4395 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4396 fprintf (STREAM, "\t%s\t%sL%d\n", \
4397 Pmode == DImode ? ".dword" : ".word", \
4398 LOCAL_LABEL_PREFIX, \
4401 /* This is how to output an element of a case-vector that is relative.
4402 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4403 TARGET_EMBEDDED_PIC). */
4405 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4407 if (TARGET_MIPS16) \
4408 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4409 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4410 else if (TARGET_EMBEDDED_PIC) \
4411 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4412 Pmode == DImode ? ".dword" : ".word", \
4413 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4414 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4415 fprintf (STREAM, "\t%s\t%sL%d\n", \
4416 Pmode == DImode ? ".gpdword" : ".gpword", \
4417 LOCAL_LABEL_PREFIX, VALUE); \
4419 fprintf (STREAM, "\t%s\t%sL%d\n", \
4420 Pmode == DImode ? ".dword" : ".word", \
4421 LOCAL_LABEL_PREFIX, VALUE); \
4424 /* When generating embedded PIC or mips16 code we want to put the jump
4425 table in the .text section. In all other cases, we want to put the
4426 jump table in the .rdata section. Unfortunately, we can't use
4427 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4428 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4429 section if appropriate. */
4430 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4432 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4433 function_section (current_function_decl); \
4434 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4437 /* This is how to output an assembler line
4438 that says to advance the location counter
4439 to a multiple of 2**LOG bytes. */
4441 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4442 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4444 /* This is how to output an assembler line to advance the location
4445 counter by SIZE bytes. */
4447 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4448 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4450 /* This is how to output a string. */
4451 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4453 register int i, c, len = (LEN), cur_pos = 17; \
4454 register const unsigned char *string = \
4455 (const unsigned char *)(STRING); \
4456 fprintf ((STREAM), "\t.ascii\t\""); \
4457 for (i = 0; i < len; i++) \
4459 register int c = string[i]; \
4465 putc ('\\', (STREAM)); \
4466 putc (c, (STREAM)); \
4470 case TARGET_NEWLINE: \
4471 fputs ("\\n", (STREAM)); \
4473 && (((c = string[i+1]) >= '\040' && c <= '~') \
4474 || c == TARGET_TAB)) \
4475 cur_pos = 32767; /* break right here */ \
4481 fputs ("\\t", (STREAM)); \
4486 fputs ("\\f", (STREAM)); \
4491 fputs ("\\b", (STREAM)); \
4496 fputs ("\\r", (STREAM)); \
4501 if (c >= ' ' && c < 0177) \
4503 putc (c, (STREAM)); \
4508 fprintf ((STREAM), "\\%03o", c); \
4513 if (cur_pos > 72 && i+1 < len) \
4516 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4519 fprintf ((STREAM), "\"\n"); \
4522 /* Handle certain cpp directives used in header files on sysV. */
4523 #define SCCS_DIRECTIVE
4525 /* Output #ident as a in the read-only data section. */
4526 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4529 int size = strlen (p) + 1; \
4531 assemble_string (p, size); \
4534 /* Default to -G 8 */
4535 #ifndef MIPS_DEFAULT_GVALUE
4536 #define MIPS_DEFAULT_GVALUE 8
4539 /* Define the strings to put out for each section in the object file. */
4540 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4541 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4542 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4543 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4544 #define READONLY_DATA_SECTION rdata_section
4545 #define SMALL_DATA_SECTION sdata_section
4547 /* What other sections we support other than the normal .data/.text. */
4549 #define EXTRA_SECTIONS in_sdata, in_rdata
4551 /* Define the additional functions to select our additional sections. */
4553 /* on the MIPS it is not a good idea to put constants in the text
4554 section, since this defeats the sdata/data mechanism. This is
4555 especially true when -O is used. In this case an effort is made to
4556 address with faster (gp) register relative addressing, which can
4557 only get at sdata and sbss items (there is no stext !!) However,
4558 if the constant is too large for sdata, and it's readonly, it
4559 will go into the .rdata section. */
4561 #define EXTRA_SECTION_FUNCTIONS \
4565 if (in_section != in_sdata) \
4567 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4568 in_section = in_sdata; \
4575 if (in_section != in_rdata) \
4577 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4578 in_section = in_rdata; \
4582 /* Given a decl node or constant node, choose the section to output it in
4583 and select that section. */
4585 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4587 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4590 /* Store in OUTPUT a string (made with alloca) containing
4591 an assembler-name for a local static variable named NAME.
4592 LABELNO is an integer which is different for each call. */
4594 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4595 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4596 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4598 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4601 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4602 TARGET_64BIT ? "dsubu" : "subu", \
4603 reg_names[STACK_POINTER_REGNUM], \
4604 reg_names[STACK_POINTER_REGNUM], \
4605 TARGET_64BIT ? "sd" : "sw", \
4607 reg_names[STACK_POINTER_REGNUM]); \
4611 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4614 if (! set_noreorder) \
4615 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4617 dslots_load_total++; \
4618 dslots_load_filled++; \
4619 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4620 TARGET_64BIT ? "ld" : "lw", \
4622 reg_names[STACK_POINTER_REGNUM], \
4623 TARGET_64BIT ? "daddu" : "addu", \
4624 reg_names[STACK_POINTER_REGNUM], \
4625 reg_names[STACK_POINTER_REGNUM]); \
4627 if (! set_noreorder) \
4628 fprintf (STREAM, "\t.set\treorder\n"); \
4632 /* Define the parentheses used to group arithmetic operations
4633 in assembler code. */
4635 #define ASM_OPEN_PAREN "("
4636 #define ASM_CLOSE_PAREN ")"
4638 /* How to start an assembler comment.
4639 The leading space is important (the mips native assembler requires it). */
4640 #ifndef ASM_COMMENT_START
4641 #define ASM_COMMENT_START " #"
4645 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4646 and mips-tdump.c to print them out.
4648 These must match the corresponding definitions in gdb/mipsread.c.
4649 Unfortunately, gcc and gdb do not currently share any directories. */
4651 #define CODE_MASK 0x8F300
4652 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4653 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4654 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4657 /* Default definitions for size_t and ptrdiff_t. */
4660 #define NO_BUILTIN_SIZE_TYPE
4661 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4664 #ifndef PTRDIFF_TYPE
4665 #define NO_BUILTIN_PTRDIFF_TYPE
4666 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4669 /* See mips_expand_prologue's use of loadgp for when this should be
4672 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4673 && mips_abi != ABI_32 \
4674 && mips_abi != ABI_O64)
4676 /* In mips16 mode, we need to look through the function to check for
4677 PC relative loads that are out of range. */
4678 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4680 /* We need to use a special set of functions to handle hard floating
4681 point code in mips16 mode. */
4683 #ifndef INIT_SUBTARGET_OPTABS
4684 #define INIT_SUBTARGET_OPTABS
4687 #define INIT_TARGET_OPTABS \
4690 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4691 INIT_SUBTARGET_OPTABS; \
4694 add_optab->handlers[(int) SFmode].libfunc = \
4695 init_one_libfunc ("__mips16_addsf3"); \
4696 sub_optab->handlers[(int) SFmode].libfunc = \
4697 init_one_libfunc ("__mips16_subsf3"); \
4698 smul_optab->handlers[(int) SFmode].libfunc = \
4699 init_one_libfunc ("__mips16_mulsf3"); \
4700 flodiv_optab->handlers[(int) SFmode].libfunc = \
4701 init_one_libfunc ("__mips16_divsf3"); \
4703 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4704 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4705 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4706 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4707 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4708 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4710 floatsisf_libfunc = \
4711 init_one_libfunc ("__mips16_floatsisf"); \
4713 init_one_libfunc ("__mips16_fixsfsi"); \
4715 if (TARGET_DOUBLE_FLOAT) \
4717 add_optab->handlers[(int) DFmode].libfunc = \
4718 init_one_libfunc ("__mips16_adddf3"); \
4719 sub_optab->handlers[(int) DFmode].libfunc = \
4720 init_one_libfunc ("__mips16_subdf3"); \
4721 smul_optab->handlers[(int) DFmode].libfunc = \
4722 init_one_libfunc ("__mips16_muldf3"); \
4723 flodiv_optab->handlers[(int) DFmode].libfunc = \
4724 init_one_libfunc ("__mips16_divdf3"); \
4726 extendsfdf2_libfunc = \
4727 init_one_libfunc ("__mips16_extendsfdf2"); \
4728 truncdfsf2_libfunc = \
4729 init_one_libfunc ("__mips16_truncdfsf2"); \
4732 init_one_libfunc ("__mips16_eqdf2"); \
4734 init_one_libfunc ("__mips16_nedf2"); \
4736 init_one_libfunc ("__mips16_gtdf2"); \
4738 init_one_libfunc ("__mips16_gedf2"); \
4740 init_one_libfunc ("__mips16_ltdf2"); \
4742 init_one_libfunc ("__mips16_ledf2"); \
4744 floatsidf_libfunc = \
4745 init_one_libfunc ("__mips16_floatsidf"); \
4747 init_one_libfunc ("__mips16_fixdfsi"); \
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