1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern int target_flags;
31 /* MIPS external variables defined in mips.c. */
33 /* Which processor to schedule for. Since there is no difference between
34 a R2000 and R3000 in terms of the scheduler, we collapse them into
35 just an R3000. The elements of the enumeration must match exactly
36 the cpu attribute in the mips.md machine description. */
65 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
66 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
67 to work on a 64 bit machine. */
75 /* Information about one recognized processor. Defined here for the
76 benefit of TARGET_CPU_CPP_BUILTINS. */
77 struct mips_cpu_info {
78 /* The 'canonical' name of the processor as far as GCC is concerned.
79 It's typically a manufacturer's prefix followed by a numerical
80 designation. It should be lower case. */
83 /* The internal processor number that most closely matches this
84 entry. Several processors can have the same value, if there's no
85 difference between them from GCC's point of view. */
86 enum processor_type cpu;
88 /* The ISA level that the processor implements. */
92 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
93 extern const char *current_function_file; /* filename current function is in */
94 extern int num_source_filenames; /* current .file # */
95 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
96 extern int sym_lineno; /* sgi next label # for each stmt */
97 extern int set_noreorder; /* # of nested .set noreorder's */
98 extern int set_nomacro; /* # of nested .set nomacro's */
99 extern int set_noat; /* # of nested .set noat's */
100 extern int set_volatile; /* # of nested .set volatile's */
101 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
102 extern int mips_dbx_regno[]; /* Map register # to debug register # */
103 extern GTY(()) rtx cmp_operands[2];
104 extern enum processor_type mips_arch; /* which cpu to codegen for */
105 extern enum processor_type mips_tune; /* which cpu to schedule for */
106 extern int mips_isa; /* architectural level */
107 extern int mips_abi; /* which ABI to use */
108 extern int mips16_hard_float; /* mips16 without -msoft-float */
109 extern const char *mips_arch_string; /* for -march=<xxx> */
110 extern const char *mips_tune_string; /* for -mtune=<xxx> */
111 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
112 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
113 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
114 extern const struct mips_cpu_info mips_cpu_info_table[];
115 extern const struct mips_cpu_info *mips_arch_info;
116 extern const struct mips_cpu_info *mips_tune_info;
118 /* Macros to silence warnings about numbers being signed in traditional
119 C and unsigned in ISO C when compiled on 32-bit hosts. */
121 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
122 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
123 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
126 /* Run-time compilation parameters selecting different hardware subsets. */
128 /* Macros used in the machine description to test the flags. */
130 /* Bits for real switches */
131 #define MASK_INT64 0x00000001 /* ints are 64 bits */
132 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
133 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
134 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
135 multiply-add operations. */
136 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
137 #define MASK_EXPLICIT_RELOCS 0x00000020 /* Use relocation operators. */
138 #define MASK_MEMCPY 0x00000040 /* call memcpy instead of inline code*/
139 #define MASK_SOFT_FLOAT 0x00000080 /* software floating point */
140 #define MASK_FLOAT64 0x00000100 /* fp registers are 64 bits */
141 #define MASK_ABICALLS 0x00000200 /* emit .abicalls/.cprestore/.cpload */
142 #define MASK_XGOT 0x00000400 /* emit big-got PIC */
143 #define MASK_LONG_CALLS 0x00000800 /* Always call through a register */
144 #define MASK_64BIT 0x00001000 /* Use 64 bit GP registers and insns */
145 #define MASK_EMBEDDED_DATA 0x00002000 /* Reduce RAM usage, not fast code */
146 #define MASK_BIG_ENDIAN 0x00004000 /* Generate big endian code */
147 #define MASK_SINGLE_FLOAT 0x00008000 /* Only single precision FPU. */
148 #define MASK_MAD 0x00010000 /* Generate mad/madu as on 4650. */
149 #define MASK_4300_MUL_FIX 0x00020000 /* Work-around early Vr4300 CPU bug */
150 #define MASK_MIPS16 0x00040000 /* Generate mips16 code */
151 #define MASK_NO_CHECK_ZERO_DIV \
152 0x00080000 /* divide by zero checking */
153 #define MASK_BRANCHLIKELY 0x00100000 /* Generate Branch Likely
155 #define MASK_UNINIT_CONST_IN_RODATA \
156 0x00200000 /* Store uninitialized
158 #define MASK_FIX_R4000 0x00400000 /* Work around R4000 errata. */
159 #define MASK_FIX_R4400 0x00800000 /* Work around R4400 errata. */
160 #define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
161 #define MASK_FIX_VR4120 0x02000000 /* Work around VR4120 errata. */
162 #define MASK_VR4130_ALIGN 0x04000000 /* Perform VR4130 alignment opts. */
163 #define MASK_FP_EXCEPTIONS 0x08000000 /* FP exceptions are enabled. */
165 /* Debug switches, not documented */
166 #define MASK_DEBUG 0 /* unused */
167 #define MASK_DEBUG_D 0 /* don't do define_split's */
169 /* Dummy switches used only in specs */
170 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
172 /* r4000 64 bit sizes */
173 #define TARGET_INT64 ((target_flags & MASK_INT64) != 0)
174 #define TARGET_LONG64 ((target_flags & MASK_LONG64) != 0)
175 #define TARGET_FLOAT64 ((target_flags & MASK_FLOAT64) != 0)
176 #define TARGET_64BIT ((target_flags & MASK_64BIT) != 0)
178 /* Mips vs. GNU linker */
179 #define TARGET_SPLIT_ADDRESSES ((target_flags & MASK_SPLIT_ADDR) != 0)
181 /* Mips vs. GNU assembler */
182 #define TARGET_GAS ((target_flags & MASK_GAS) != 0)
183 #define TARGET_MIPS_AS (!TARGET_GAS)
186 #define TARGET_DEBUG_MODE ((target_flags & MASK_DEBUG) != 0)
187 #define TARGET_DEBUG_D_MODE ((target_flags & MASK_DEBUG_D) != 0)
189 /* call memcpy instead of inline code */
190 #define TARGET_MEMCPY ((target_flags & MASK_MEMCPY) != 0)
192 /* .abicalls, etc from Pyramid V.4 */
193 #define TARGET_ABICALLS ((target_flags & MASK_ABICALLS) != 0)
194 #define TARGET_XGOT ((target_flags & MASK_XGOT) != 0)
196 /* software floating point */
197 #define TARGET_SOFT_FLOAT ((target_flags & MASK_SOFT_FLOAT) != 0)
198 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
200 /* always call through a register */
201 #define TARGET_LONG_CALLS ((target_flags & MASK_LONG_CALLS) != 0)
203 /* for embedded systems, optimize for
204 reduced RAM space instead of for
206 #define TARGET_EMBEDDED_DATA ((target_flags & MASK_EMBEDDED_DATA) != 0)
208 /* always store uninitialized const
209 variables in rodata, requires
210 TARGET_EMBEDDED_DATA. */
211 #define TARGET_UNINIT_CONST_IN_RODATA \
212 ((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)
214 /* generate big endian code. */
215 #define TARGET_BIG_ENDIAN ((target_flags & MASK_BIG_ENDIAN) != 0)
217 #define TARGET_SINGLE_FLOAT ((target_flags & MASK_SINGLE_FLOAT) != 0)
218 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
220 #define TARGET_MAD ((target_flags & MASK_MAD) != 0)
222 #define TARGET_FUSED_MADD ((target_flags & MASK_NO_FUSED_MADD) == 0)
224 #define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
226 #define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
228 #define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
230 #define TARGET_FIX_SB1 ((target_flags & MASK_FIX_SB1) != 0)
232 /* Work around R4000 errata. */
233 #define TARGET_FIX_R4000 ((target_flags & MASK_FIX_R4000) != 0)
235 /* Work around R4400 errata. */
236 #define TARGET_FIX_R4400 ((target_flags & MASK_FIX_R4400) != 0)
237 #define TARGET_FIX_VR4120 ((target_flags & MASK_FIX_VR4120) != 0)
238 #define TARGET_VR4130_ALIGN ((target_flags & MASK_VR4130_ALIGN) != 0)
240 #define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
242 /* True if we should use NewABI-style relocation operators for
243 symbolic addresses. This is never true for mips16 code,
244 which has its own conventions. */
246 #define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
249 /* True if the call patterns should be split into a jalr followed by
250 an instruction to restore $gp. This is only ever true for SVR4 PIC,
251 in which $gp is call-clobbered. It is only safe to split the load
252 from the call when every use of $gp is explicit. */
254 #define TARGET_SPLIT_CALLS \
255 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
257 /* True if we can optimize sibling calls. For simplicity, we only
258 handle cases in which call_insn_operand will reject invalid
259 sibcall addresses. There are two cases in which this isn't true:
261 - TARGET_MIPS16. call_insn_operand accepts constant addresses
262 but there is no direct jump instruction. It isn't worth
263 using sibling calls in this case anyway; they would usually
264 be longer than normal calls.
266 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
267 accepts global constants, but "jr $25" is the only allowed
270 #define TARGET_SIBCALLS \
271 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
273 /* True if .gpword or .gpdword should be used for switch tables.
274 There are some problems with using these directives with the
277 - It has been reported that some versions of the native n32
278 assembler mishandle .gpword, complaining that symbols are
279 global when they are in fact local.
281 - The native assemblers don't understand .gpdword.
283 - Although GAS does understand .gpdword, the native linker
284 mishandles the relocations GAS generates (R_MIPS_GPREL32
285 followed by R_MIPS_64).
287 We therefore disable GP-relative switch tables for n32 and n64
289 #define TARGET_GPWORD (TARGET_ABICALLS && !(TARGET_NEWABI && TARGET_IRIX))
291 /* Generate mips16 code */
292 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
294 /* Generic ISA defines. */
295 #define ISA_MIPS1 (mips_isa == 1)
296 #define ISA_MIPS2 (mips_isa == 2)
297 #define ISA_MIPS3 (mips_isa == 3)
298 #define ISA_MIPS4 (mips_isa == 4)
299 #define ISA_MIPS32 (mips_isa == 32)
300 #define ISA_MIPS32R2 (mips_isa == 33)
301 #define ISA_MIPS64 (mips_isa == 64)
303 /* Architecture target defines. */
304 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
305 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
306 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
307 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
308 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
309 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
310 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
311 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
312 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
314 /* Scheduling target defines. */
315 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
316 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
317 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
318 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
319 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
320 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
321 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
322 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
323 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
324 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
325 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
326 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
328 /* True if the pre-reload scheduler should try to create chains of
329 multiply-add or multiply-subtract instructions. For example,
337 t1 will have a higher priority than t2 and t3 will have a higher
338 priority than t4. However, before reload, there is no dependence
339 between t1 and t3, and they can often have similar priorities.
340 The scheduler will then tend to prefer:
347 which stops us from making full use of macc/madd-style instructions.
348 This sort of situation occurs frequently in Fourier transforms and
351 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
352 queue so that chained multiply-add and multiply-subtract instructions
353 appear ahead of any other instruction that is likely to clobber lo.
354 In the example above, if t2 and t3 become ready at the same time,
355 the code ensures that t2 is scheduled first.
357 Multiply-accumulate instructions are a bigger win for some targets
358 than others, so this macro is defined on an opt-in basis. */
359 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
363 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
364 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
366 /* IRIX specific stuff. */
367 #define TARGET_IRIX 0
368 #define TARGET_IRIX5 0
369 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
371 /* Define preprocessor macros for the -march and -mtune options.
372 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
373 processor. If INFO's canonical name is "foo", define PREFIX to
374 be "foo", and define an additional macro PREFIX_FOO. */
375 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
380 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
381 for (p = macro; *p != 0; p++) \
384 builtin_define (macro); \
385 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
390 /* Target CPU builtins. */
391 #define TARGET_CPU_CPP_BUILTINS() \
394 builtin_assert ("cpu=mips"); \
395 builtin_define ("__mips__"); \
396 builtin_define ("_mips"); \
398 /* We do this here because __mips is defined below \
399 and so we can't use builtin_define_std. */ \
401 builtin_define ("mips"); \
403 /* Treat _R3000 and _R4000 like register-size defines, \
404 which is how they've historically been used. */ \
407 builtin_define ("__mips64"); \
408 builtin_define_std ("R4000"); \
409 builtin_define ("_R4000"); \
413 builtin_define_std ("R3000"); \
414 builtin_define ("_R3000"); \
416 if (TARGET_FLOAT64) \
417 builtin_define ("__mips_fpr=64"); \
419 builtin_define ("__mips_fpr=32"); \
422 builtin_define ("__mips16"); \
424 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
425 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
429 builtin_define ("__mips=1"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
432 else if (ISA_MIPS2) \
434 builtin_define ("__mips=2"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
437 else if (ISA_MIPS3) \
439 builtin_define ("__mips=3"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
442 else if (ISA_MIPS4) \
444 builtin_define ("__mips=4"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
447 else if (ISA_MIPS32) \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=1"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
453 else if (ISA_MIPS32R2) \
455 builtin_define ("__mips=32"); \
456 builtin_define ("__mips_isa_rev=2"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
459 else if (ISA_MIPS64) \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=1"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
466 if (TARGET_HARD_FLOAT) \
467 builtin_define ("__mips_hard_float"); \
468 else if (TARGET_SOFT_FLOAT) \
469 builtin_define ("__mips_soft_float"); \
471 if (TARGET_SINGLE_FLOAT) \
472 builtin_define ("__mips_single_float"); \
474 if (TARGET_BIG_ENDIAN) \
476 builtin_define_std ("MIPSEB"); \
477 builtin_define ("_MIPSEB"); \
481 builtin_define_std ("MIPSEL"); \
482 builtin_define ("_MIPSEL"); \
485 /* Macros dependent on the C dialect. */ \
486 if (preprocessing_asm_p ()) \
488 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
489 builtin_define ("_LANGUAGE_ASSEMBLY"); \
491 else if (c_dialect_cxx ()) \
493 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
494 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
495 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
499 builtin_define_std ("LANGUAGE_C"); \
500 builtin_define ("_LANGUAGE_C"); \
502 if (c_dialect_objc ()) \
504 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
505 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
506 /* Bizarre, but needed at least for Irix. */ \
507 builtin_define_std ("LANGUAGE_C"); \
508 builtin_define ("_LANGUAGE_C"); \
511 if (mips_abi == ABI_EABI) \
512 builtin_define ("__mips_eabi"); \
518 /* Macro to define tables used to set the flags.
519 This is a list in braces of pairs in braces,
520 each pair being { "NAME", VALUE }
521 where VALUE is the bits to set or minus the bits to clear.
522 An empty string NAME is used to identify the default VALUE. */
524 #define TARGET_SWITCHES \
526 SUBTARGET_TARGET_SWITCHES \
527 {"int64", MASK_INT64 | MASK_LONG64, \
528 N_("Use 64-bit int type")}, \
529 {"long64", MASK_LONG64, \
530 N_("Use 64-bit long type")}, \
531 {"long32", -(MASK_LONG64 | MASK_INT64), \
532 N_("Use 32-bit long type")}, \
533 {"split-addresses", MASK_SPLIT_ADDR, \
534 N_("Optimize lui/addiu address loads")}, \
535 {"no-split-addresses", -MASK_SPLIT_ADDR, \
536 N_("Don't optimize lui/addiu address loads")}, \
537 {"mips-as", -MASK_GAS, \
538 N_("Use MIPS as")}, \
542 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
544 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
546 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
548 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
550 N_("Output compiler statistics (now ignored)")}, \
552 N_("Don't output compiler statistics")}, \
553 {"memcpy", MASK_MEMCPY, \
554 N_("Don't optimize block moves")}, \
555 {"no-memcpy", -MASK_MEMCPY, \
556 N_("Optimize block moves")}, \
557 {"mips-tfile", MASK_MIPS_TFILE, \
558 N_("Use mips-tfile asm postpass")}, \
559 {"no-mips-tfile", -MASK_MIPS_TFILE, \
560 N_("Don't use mips-tfile asm postpass")}, \
561 {"soft-float", MASK_SOFT_FLOAT, \
562 N_("Use software floating point")}, \
563 {"hard-float", -MASK_SOFT_FLOAT, \
564 N_("Use hardware floating point")}, \
565 {"fp64", MASK_FLOAT64, \
566 N_("Use 64-bit FP registers")}, \
567 {"fp32", -MASK_FLOAT64, \
568 N_("Use 32-bit FP registers")}, \
569 {"gp64", MASK_64BIT, \
570 N_("Use 64-bit general registers")}, \
571 {"gp32", -MASK_64BIT, \
572 N_("Use 32-bit general registers")}, \
573 {"abicalls", MASK_ABICALLS, \
574 N_("Use Irix PIC")}, \
575 {"no-abicalls", -MASK_ABICALLS, \
576 N_("Don't use Irix PIC")}, \
577 {"long-calls", MASK_LONG_CALLS, \
578 N_("Use indirect calls")}, \
579 {"no-long-calls", -MASK_LONG_CALLS, \
580 N_("Don't use indirect calls")}, \
581 {"embedded-data", MASK_EMBEDDED_DATA, \
582 N_("Use ROM instead of RAM")}, \
583 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
584 N_("Don't use ROM instead of RAM")}, \
585 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
586 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
587 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
588 N_("Don't put uninitialized constants in ROM")}, \
589 {"eb", MASK_BIG_ENDIAN, \
590 N_("Use big-endian byte order")}, \
591 {"el", -MASK_BIG_ENDIAN, \
592 N_("Use little-endian byte order")}, \
593 {"single-float", MASK_SINGLE_FLOAT, \
594 N_("Use single (32-bit) FP only")}, \
595 {"double-float", -MASK_SINGLE_FLOAT, \
596 N_("Don't use single (32-bit) FP only")}, \
598 N_("Use multiply accumulate")}, \
599 {"no-mad", -MASK_MAD, \
600 N_("Don't use multiply accumulate")}, \
601 {"no-fused-madd", MASK_NO_FUSED_MADD, \
602 N_("Don't generate fused multiply/add instructions")}, \
603 {"fused-madd", -MASK_NO_FUSED_MADD, \
604 N_("Generate fused multiply/add instructions")}, \
605 {"vr4130-align", MASK_VR4130_ALIGN, \
606 N_("Perform VR4130-specific alignment optimizations")}, \
607 {"no-vr4130-align", -MASK_VR4130_ALIGN, \
608 N_("Don't perform VR4130-specific alignment optimizations")}, \
609 {"fix4300", MASK_4300_MUL_FIX, \
610 N_("Work around early 4300 hardware bug")}, \
611 {"no-fix4300", -MASK_4300_MUL_FIX, \
612 N_("Don't work around early 4300 hardware bug")}, \
613 {"fix-sb1", MASK_FIX_SB1, \
614 N_("Work around errata for early SB-1 revision 2 cores")}, \
615 {"no-fix-sb1", -MASK_FIX_SB1, \
616 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
617 {"fix-r4000", MASK_FIX_R4000, \
618 N_("Work around R4000 errata")}, \
619 {"no-fix-r4000", -MASK_FIX_R4000, \
620 N_("Don't work around R4000 errata")}, \
621 {"fix-r4400", MASK_FIX_R4400, \
622 N_("Work around R4400 errata")}, \
623 {"no-fix-r4400", -MASK_FIX_R4400, \
624 N_("Don't work around R4400 errata")}, \
625 {"fix-vr4120", MASK_FIX_VR4120, \
626 N_("Work around certain VR4120 errata")}, \
627 {"no-fix-vr4120", -MASK_FIX_VR4120, \
628 N_("Don't work around certain VR4120 errata")}, \
629 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
630 N_("Trap on integer divide by zero")}, \
631 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
632 N_("Don't trap on integer divide by zero")}, \
633 { "branch-likely", MASK_BRANCHLIKELY, \
634 N_("Use Branch Likely instructions, overriding default for arch")}, \
635 { "no-branch-likely", -MASK_BRANCHLIKELY, \
636 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
637 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
638 N_("Use NewABI-style %reloc() assembly operators")}, \
639 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
640 N_("Use assembler macros instead of relocation operators")}, \
641 {"ips16", MASK_MIPS16, \
642 N_("Generate mips16 code") }, \
643 {"no-mips16", -MASK_MIPS16, \
644 N_("Generate normal-mode code") }, \
645 {"xgot", MASK_XGOT, \
646 N_("Lift restrictions on GOT size") }, \
647 {"no-xgot", -MASK_XGOT, \
648 N_("Do not lift restrictions on GOT size") }, \
649 {"fp-exceptions", MASK_FP_EXCEPTIONS, \
650 N_("FP exceptions are enabled") }, \
651 {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
652 N_("FP exceptions are not enabled") }, \
653 {"debug", MASK_DEBUG, \
655 {"debugd", MASK_DEBUG_D, \
657 {"", (TARGET_DEFAULT \
658 | TARGET_CPU_DEFAULT \
659 | TARGET_ENDIAN_DEFAULT \
660 | TARGET_FP_EXCEPTIONS_DEFAULT), \
664 /* Default target_flags if no switches are specified */
666 #ifndef TARGET_DEFAULT
667 #define TARGET_DEFAULT 0
670 #ifndef TARGET_CPU_DEFAULT
671 #define TARGET_CPU_DEFAULT 0
674 #ifndef TARGET_ENDIAN_DEFAULT
675 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
678 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
679 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
682 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
683 #ifndef MIPS_ISA_DEFAULT
684 #ifndef MIPS_CPU_STRING_DEFAULT
685 #define MIPS_CPU_STRING_DEFAULT "from-abi"
691 /* Make this compile time constant for libgcc2 */
693 #define TARGET_64BIT 1
695 #define TARGET_64BIT 0
697 #endif /* IN_LIBGCC2 */
699 #ifndef MULTILIB_ENDIAN_DEFAULT
700 #if TARGET_ENDIAN_DEFAULT == 0
701 #define MULTILIB_ENDIAN_DEFAULT "EL"
703 #define MULTILIB_ENDIAN_DEFAULT "EB"
707 #ifndef MULTILIB_ISA_DEFAULT
708 # if MIPS_ISA_DEFAULT == 1
709 # define MULTILIB_ISA_DEFAULT "mips1"
711 # if MIPS_ISA_DEFAULT == 2
712 # define MULTILIB_ISA_DEFAULT "mips2"
714 # if MIPS_ISA_DEFAULT == 3
715 # define MULTILIB_ISA_DEFAULT "mips3"
717 # if MIPS_ISA_DEFAULT == 4
718 # define MULTILIB_ISA_DEFAULT "mips4"
720 # if MIPS_ISA_DEFAULT == 32
721 # define MULTILIB_ISA_DEFAULT "mips32"
723 # if MIPS_ISA_DEFAULT == 33
724 # define MULTILIB_ISA_DEFAULT "mips32r2"
726 # if MIPS_ISA_DEFAULT == 64
727 # define MULTILIB_ISA_DEFAULT "mips64"
729 # define MULTILIB_ISA_DEFAULT "mips1"
739 #ifndef MULTILIB_DEFAULTS
740 #define MULTILIB_DEFAULTS \
741 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
744 /* We must pass -EL to the linker by default for little endian embedded
745 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
746 linker will default to using big-endian output files. The OUTPUT_FORMAT
747 line must be in the linker script, otherwise -EB/-EL will not work. */
750 #if TARGET_ENDIAN_DEFAULT == 0
751 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
753 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
757 #define TARGET_OPTIONS \
759 SUBTARGET_TARGET_OPTIONS \
760 { "tune=", &mips_tune_string, \
761 N_("Specify CPU for scheduling purposes"), 0}, \
762 { "arch=", &mips_arch_string, \
763 N_("Specify CPU for code generation purposes"), 0}, \
764 { "abi=", &mips_abi_string, \
765 N_("Specify an ABI"), 0}, \
766 { "ips", &mips_isa_string, \
767 N_("Specify a Standard MIPS ISA"), 0}, \
768 { "no-flush-func", &mips_cache_flush_func, \
769 N_("Don't call any cache flush functions"), 0}, \
770 { "flush-func=", &mips_cache_flush_func, \
771 N_("Specify cache flush function"), 0}, \
774 /* This is meant to be redefined in the host dependent files. */
775 #define SUBTARGET_TARGET_OPTIONS
777 /* Support for a compile-time default CPU, et cetera. The rules are:
778 --with-arch is ignored if -march is specified or a -mips is specified
779 (other than -mips16).
780 --with-tune is ignored if -mtune is specified.
781 --with-abi is ignored if -mabi is specified.
782 --with-float is ignored if -mhard-float or -msoft-float are
784 #define OPTION_DEFAULT_SPECS \
785 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
786 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
787 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
788 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
791 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
795 /* Generate three-operand multiply instructions for SImode. */
796 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
806 /* Generate three-operand multiply instructions for DImode. */
807 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
810 /* Macros to decide whether certain features are available or not,
811 depending on the instruction set architecture level. */
813 #define HAVE_SQRT_P() (!ISA_MIPS1)
815 /* True if the ABI can only work with 64-bit integer registers. We
816 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
817 otherwise floating-point registers must also be 64-bit. */
818 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
820 /* Likewise for 32-bit regs. */
821 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
823 /* True if symbols are 64 bits wide. At present, n64 is the only
824 ABI for which this is true. */
825 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
827 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
828 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
832 /* ISA has branch likely instructions (eg. mips2). */
833 /* Disable branchlikely for tx39 until compare rewrite. They haven't
834 been generated up to this point. */
835 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
837 /* ISA has the conditional move instructions introduced in mips4. */
838 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
842 && !TARGET_MIPS5500 \
845 /* ISA has just the integer condition move instructions (movn,movz) */
846 #define ISA_HAS_INT_CONDMOVE 0
848 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
849 branch on CC, and move (both FP and non-FP) on CC. */
850 #define ISA_HAS_8CC (ISA_MIPS4 \
855 /* This is a catch all for other mips4 instructions: indexed load, the
856 FP madd and msub instructions, and the FP recip and recip sqrt
858 #define ISA_HAS_FP4 ((ISA_MIPS4 \
862 /* ISA has conditional trap instructions. */
863 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
866 /* ISA has integer multiply-accumulate instructions, madd and msub. */
867 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
872 /* ISA has floating-point nmadd and nmsub instructions. */
873 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
875 && (!TARGET_MIPS5400 || TARGET_MAD) \
878 /* ISA has count leading zeroes/ones instruction (not implemented). */
879 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
884 /* ISA has double-word count leading zeroes/ones instruction (not
886 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
889 /* ISA has three operand multiply instructions that put
890 the high part in an accumulator: mulhi or mulhiu. */
891 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
896 /* ISA has three operand multiply instructions that
897 negates the result and puts the result in an accumulator. */
898 #define ISA_HAS_MULS (TARGET_MIPS5400 \
903 /* ISA has three operand multiply instructions that subtracts the
904 result from a 4th operand and puts the result in an accumulator. */
905 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
909 /* ISA has three operand multiply instructions that the result
910 from a 4th operand and puts the result in an accumulator. */
911 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
912 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
918 /* ISA has 32-bit rotate right instruction. */
919 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
926 /* ISA has 64-bit rotate right instruction. */
927 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
929 && (TARGET_MIPS5400 \
934 /* ISA has data prefetch instructions. This controls use of 'pref'. */
935 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
941 /* ISA has data indexed prefetch instructions. This controls use of
942 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
943 (prefx is a cop1x instruction, so can only be used if FP is
945 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
949 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
950 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
951 also requires TARGET_DOUBLE_FLOAT. */
952 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
954 /* ISA includes the MIPS32r2 seb and seh instructions. */
955 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
959 /* True if the result of a load is not available to the next instruction.
960 A nop will then be needed between instructions like "lw $4,..."
961 and "addiu $4,$4,1". */
962 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
963 && !TARGET_MIPS3900 \
966 /* Likewise mtc1 and mfc1. */
967 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
969 /* Likewise floating-point comparisons. */
970 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
972 /* True if mflo and mfhi can be immediately followed by instructions
973 which write to the HI and LO registers.
975 According to MIPS specifications, MIPS ISAs I, II, and III need
976 (at least) two instructions between the reads of HI/LO and
977 instructions which write them, and later ISAs do not. Contradicting
978 the MIPS specifications, some MIPS IV processor user manuals (e.g.
979 the UM for the NEC Vr5000) document needing the instructions between
980 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
981 MIPS64 and later ISAs to have the interlocks, plus any specific
982 earlier-ISA CPUs for which CPU documentation declares that the
983 instructions are really interlocked. */
984 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
989 /* Add -G xx support. */
991 #undef SWITCH_TAKES_ARG
992 #define SWITCH_TAKES_ARG(CHAR) \
993 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
995 #define OVERRIDE_OPTIONS override_options ()
997 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
999 /* Show we can debug even without a frame pointer. */
1000 #define CAN_DEBUG_WITHOUT_FP
1002 /* Tell collect what flags to pass to nm. */
1004 #define NM_FLAGS "-Bn"
1008 /* Assembler specs. */
1010 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1013 #define MIPS_AS_ASM_SPEC "\
1014 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1015 %{pipe: %e-pipe is not supported} \
1016 %{K} %(subtarget_mips_as_asm_spec)"
1018 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1019 rather than gas. It may be overridden by subtargets. */
1021 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1022 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1025 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1028 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1030 #define SUBTARGET_TARGET_SWITCHES
1032 #ifndef MIPS_ABI_DEFAULT
1033 #define MIPS_ABI_DEFAULT ABI_32
1036 /* Use the most portable ABI flag for the ASM specs. */
1038 #if MIPS_ABI_DEFAULT == ABI_32
1039 #define MULTILIB_ABI_DEFAULT "mabi=32"
1040 #define ASM_ABI_DEFAULT_SPEC "-32"
1043 #if MIPS_ABI_DEFAULT == ABI_O64
1044 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1045 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1048 #if MIPS_ABI_DEFAULT == ABI_N32
1049 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1050 #define ASM_ABI_DEFAULT_SPEC "-n32"
1053 #if MIPS_ABI_DEFAULT == ABI_64
1054 #define MULTILIB_ABI_DEFAULT "mabi=64"
1055 #define ASM_ABI_DEFAULT_SPEC "-64"
1058 #if MIPS_ABI_DEFAULT == ABI_EABI
1059 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1060 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1063 /* Only ELF targets can switch the ABI. */
1064 #ifndef OBJECT_FORMAT_ELF
1065 #undef ASM_ABI_DEFAULT_SPEC
1066 #define ASM_ABI_DEFAULT_SPEC ""
1069 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1070 GAS_ASM_SPEC as the default, depending upon the value of
1073 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1076 #define TARGET_ASM_SPEC "\
1077 %{mmips-as: %(mips_as_asm_spec)} \
1078 %{!mmips-as: %(gas_asm_spec)}"
1082 #define TARGET_ASM_SPEC "\
1083 %{!mgas: %(mips_as_asm_spec)} \
1084 %{mgas: %(gas_asm_spec)}"
1086 #endif /* not GAS */
1088 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1089 to the assembler. It may be overridden by subtargets. */
1090 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1091 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1093 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1096 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1097 the assembler. It may be overridden by subtargets. */
1098 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1099 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1100 %{g} %{g0} %{g1} %{g2} %{g3} \
1101 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1102 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1103 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1104 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1108 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1110 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1112 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1113 %{!gcoff*:-no-mdebug}"
1115 #define MDEBUG_ASM_SPEC ""
1116 #endif /* not GAS */
1118 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1119 overridden by subtargets. */
1121 #ifndef SUBTARGET_ASM_SPEC
1122 #define SUBTARGET_ASM_SPEC ""
1125 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1126 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1127 whether we're using GAS. These options can only be used properly
1128 with GAS, and it is better to get an error from a non-GAS assembler
1129 than to silently generate bad code. */
1133 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1134 %{mips32} %{mips32r2} %{mips64} \
1135 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1137 %(subtarget_asm_optimizing_spec) \
1138 %(subtarget_asm_debugging_spec) \
1139 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1140 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1141 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1142 %(target_asm_spec) \
1143 %(subtarget_asm_spec)"
1145 /* Extra switches sometimes passed to the linker. */
1146 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1147 will interpret it as a -b option. */
1150 #define LINK_SPEC "\
1152 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1153 %{bestGnum} %{shared} %{non_shared}"
1154 #endif /* LINK_SPEC defined */
1157 /* Specs for the compiler proper */
1159 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1160 overridden by subtargets. */
1161 #ifndef SUBTARGET_CC1_SPEC
1162 #define SUBTARGET_CC1_SPEC ""
1165 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1169 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1170 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1172 %(subtarget_cc1_spec)"
1175 /* Preprocessor specs. */
1177 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1178 overridden by subtargets. */
1179 #ifndef SUBTARGET_CPP_SPEC
1180 #define SUBTARGET_CPP_SPEC ""
1183 #define CPP_SPEC "%(subtarget_cpp_spec)"
1185 /* This macro defines names of additional specifications to put in the specs
1186 that can be used in various specifications like CC1_SPEC. Its definition
1187 is an initializer with a subgrouping for each command option.
1189 Each subgrouping contains a string constant, that defines the
1190 specification name, and a string constant that used by the GCC driver
1193 Do not define this macro if it does not need to do anything. */
1195 #define EXTRA_SPECS \
1196 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1197 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1198 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1199 { "gas_asm_spec", GAS_ASM_SPEC }, \
1200 { "target_asm_spec", TARGET_ASM_SPEC }, \
1201 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1202 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1203 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1204 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1205 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1206 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1207 { "endian_spec", ENDIAN_SPEC }, \
1208 SUBTARGET_EXTRA_SPECS
1210 #ifndef SUBTARGET_EXTRA_SPECS
1211 #define SUBTARGET_EXTRA_SPECS
1214 /* If defined, this macro is an additional prefix to try after
1215 `STANDARD_EXEC_PREFIX'. */
1217 #ifndef MD_EXEC_PREFIX
1218 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1221 #ifndef MD_STARTFILE_PREFIX
1222 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1226 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1227 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1228 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1230 #ifndef PREFERRED_DEBUGGING_TYPE
1231 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1234 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1236 /* By default, turn on GDB extensions. */
1237 #define DEFAULT_GDB_EXTENSIONS 1
1239 /* If we are passing smuggling stabs through the MIPS ECOFF object
1240 format, put a comment in front of the .stab<x> operation so
1241 that the MIPS assembler does not choke. The mips-tfile program
1242 will correctly put the stab into the object file. */
1244 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1245 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1246 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1248 /* Local compiler-generated symbols must have a prefix that the assembler
1249 understands. By default, this is $, although some targets (e.g.,
1250 NetBSD-ELF) need to override this. */
1252 #ifndef LOCAL_LABEL_PREFIX
1253 #define LOCAL_LABEL_PREFIX "$"
1256 /* By default on the mips, external symbols do not have an underscore
1257 prepended, but some targets (e.g., NetBSD) require this. */
1259 #ifndef USER_LABEL_PREFIX
1260 #define USER_LABEL_PREFIX ""
1263 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1264 since the length can run past this up to a continuation point. */
1265 #undef DBX_CONTIN_LENGTH
1266 #define DBX_CONTIN_LENGTH 1500
1268 /* How to renumber registers for dbx and gdb. */
1269 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1271 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1272 #define DWARF_FRAME_REGNUM(REG) (REG)
1274 /* The DWARF 2 CFA column which tracks the return address. */
1275 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1277 /* The DWARF 2 CFA column which tracks the return address from a
1278 signal handler context. */
1279 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1281 /* Before the prologue, RA lives in r31. */
1282 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1284 /* Describe how we implement __builtin_eh_return. */
1285 #define EH_RETURN_DATA_REGNO(N) \
1286 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1288 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1290 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1291 The default for this in 64-bit mode is 8, which causes problems with
1292 SFmode register saves. */
1293 #define DWARF_CIE_DATA_ALIGNMENT 4
1295 /* Correct the offset of automatic variables and arguments. Note that
1296 the MIPS debug format wants all automatic variables and arguments
1297 to be in terms of the virtual frame pointer (stack pointer before
1298 any adjustment in the function), while the MIPS 3.0 linker wants
1299 the frame pointer to be the stack pointer after the initial
1302 #define DEBUGGER_AUTO_OFFSET(X) \
1303 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1304 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1305 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1307 /* Target machine storage layout */
1309 #define BITS_BIG_ENDIAN 0
1310 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1311 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1313 /* Define this to set the endianness to use in libgcc2.c, which can
1314 not depend on target_flags. */
1315 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1316 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1318 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1321 #define MAX_BITS_PER_WORD 64
1323 /* Width of a word, in units (bytes). */
1324 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1325 #define MIN_UNITS_PER_WORD 4
1327 /* For MIPS, width of a floating point register. */
1328 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1330 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1331 the next available register. */
1332 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1334 /* The largest size of value that can be held in floating-point
1335 registers and moved with a single instruction. */
1336 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1338 /* The largest size of value that can be held in floating-point
1340 #define UNITS_PER_FPVALUE \
1341 (TARGET_SOFT_FLOAT ? 0 \
1342 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1343 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1345 /* The number of bytes in a double. */
1346 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1348 /* Set the sizes of the core types. */
1349 #define SHORT_TYPE_SIZE 16
1350 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1351 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1352 #define LONG_LONG_TYPE_SIZE 64
1354 #define FLOAT_TYPE_SIZE 32
1355 #define DOUBLE_TYPE_SIZE 64
1356 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1358 /* long double is not a fixed mode, but the idea is that, if we
1359 support long double, we also want a 128-bit integer type. */
1360 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1363 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1364 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1365 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1367 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1371 /* Width in bits of a pointer. */
1372 #ifndef POINTER_SIZE
1373 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1376 #define POINTERS_EXTEND_UNSIGNED 0
1378 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1379 #define PARM_BOUNDARY ((mips_abi == ABI_O64 \
1381 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1384 /* Allocation boundary (in *bits*) for the code of a function. */
1385 #define FUNCTION_BOUNDARY 32
1387 /* Alignment of field after `int : 0' in a structure. */
1388 #define EMPTY_FIELD_BOUNDARY 32
1390 /* Every structure's size must be a multiple of this. */
1391 /* 8 is observed right on a DECstation and on riscos 4.02. */
1392 #define STRUCTURE_SIZE_BOUNDARY 8
1394 /* There is no point aligning anything to a rounder boundary than this. */
1395 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1397 /* All accesses must be aligned. */
1398 #define STRICT_ALIGNMENT 1
1400 /* Define this if you wish to imitate the way many other C compilers
1401 handle alignment of bitfields and the structures that contain
1404 The behavior is that the type written for a bit-field (`int',
1405 `short', or other integer type) imposes an alignment for the
1406 entire structure, as if the structure really did contain an
1407 ordinary field of that type. In addition, the bit-field is placed
1408 within the structure so that it would fit within such a field,
1409 not crossing a boundary for it.
1411 Thus, on most machines, a bit-field whose type is written as `int'
1412 would not cross a four-byte boundary, and would force four-byte
1413 alignment for the whole structure. (The alignment used may not
1414 be four bytes; it is controlled by the other alignment
1417 If the macro is defined, its definition should be a C expression;
1418 a nonzero value for the expression enables this behavior. */
1420 #define PCC_BITFIELD_TYPE_MATTERS 1
1422 /* If defined, a C expression to compute the alignment given to a
1423 constant that is being placed in memory. CONSTANT is the constant
1424 and ALIGN is the alignment that the object would ordinarily have.
1425 The value of this macro is used instead of that alignment to align
1428 If this macro is not defined, then ALIGN is used.
1430 The typical use of this macro is to increase alignment for string
1431 constants to be word aligned so that `strcpy' calls that copy
1432 constants can be done inline. */
1434 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1435 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1436 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1438 /* If defined, a C expression to compute the alignment for a static
1439 variable. TYPE is the data type, and ALIGN is the alignment that
1440 the object would ordinarily have. The value of this macro is used
1441 instead of that alignment to align the object.
1443 If this macro is not defined, then ALIGN is used.
1445 One use of this macro is to increase alignment of medium-size
1446 data to make it all fit in fewer cache lines. Another is to
1447 cause character arrays to be word-aligned so that `strcpy' calls
1448 that copy constants to character arrays can be done inline. */
1450 #undef DATA_ALIGNMENT
1451 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1452 ((((ALIGN) < BITS_PER_WORD) \
1453 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1454 || TREE_CODE (TYPE) == UNION_TYPE \
1455 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1458 #define PAD_VARARGS_DOWN \
1459 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1461 /* Define if operations between registers always perform the operation
1462 on the full register even if a narrower mode is specified. */
1463 #define WORD_REGISTER_OPERATIONS
1465 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1466 moves. All other references are zero extended. */
1467 #define LOAD_EXTEND_OP(MODE) \
1468 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1469 ? SIGN_EXTEND : ZERO_EXTEND)
1471 /* Define this macro if it is advisable to hold scalars in registers
1472 in a wider mode than that declared by the program. In such cases,
1473 the value is constrained to be within the bounds of the declared
1474 type, but kept valid in the wider mode. The signedness of the
1475 extension may differ from that of the type. */
1477 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1478 if (GET_MODE_CLASS (MODE) == MODE_INT \
1479 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1481 if ((MODE) == SImode) \
1486 /* Define if loading short immediate values into registers sign extends. */
1487 #define SHORT_IMMEDIATES_SIGN_EXTEND
1489 /* Standard register usage. */
1491 /* Number of hardware registers. We have:
1493 - 32 integer registers
1494 - 32 floating point registers
1495 - 8 condition code registers
1496 - 2 accumulator registers (hi and lo)
1497 - 32 registers each for coprocessors 0, 2 and 3
1499 - ARG_POINTER_REGNUM
1500 - FRAME_POINTER_REGNUM
1501 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1502 - 3 dummy entries that were used at various times in the past. */
1504 #define FIRST_PSEUDO_REGISTER 176
1506 /* By default, fix the kernel registers ($26 and $27), the global
1507 pointer ($28) and the stack pointer ($29). This can change
1508 depending on the command-line options.
1510 Regarding coprocessor registers: without evidence to the contrary,
1511 it's best to assume that each coprocessor register has a unique
1512 use. This can be overridden, in, e.g., override_options() or
1513 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1514 for a particular target. */
1516 #define FIXED_REGISTERS \
1518 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1522 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1523 /* COP0 registers */ \
1524 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1525 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1526 /* COP2 registers */ \
1527 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1529 /* COP3 registers */ \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1535 /* Set up this array for o32 by default.
1537 Note that we don't mark $31 as a call-clobbered register. The idea is
1538 that it's really the call instructions themselves which clobber $31.
1539 We don't care what the called function does with it afterwards.
1541 This approach makes it easier to implement sibcalls. Unlike normal
1542 calls, sibcalls don't clobber $31, so the register reaches the
1543 called function in tact. EPILOGUE_USES says that $31 is useful
1544 to the called function. */
1546 #define CALL_USED_REGISTERS \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 /* COP0 registers */ \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 /* COP2 registers */ \
1557 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 /* COP3 registers */ \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1565 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1567 #define CALL_REALLY_USED_REGISTERS \
1568 { /* General registers. */ \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1570 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1571 /* Floating-point registers. */ \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 /* COP0 registers */ \
1577 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1578 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1579 /* COP2 registers */ \
1580 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1581 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1582 /* COP3 registers */ \
1583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1587 /* Internal macros to classify a register number as to whether it's a
1588 general purpose register, a floating point register, a
1589 multiply/divide register, or a status register. */
1591 #define GP_REG_FIRST 0
1592 #define GP_REG_LAST 31
1593 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1594 #define GP_DBX_FIRST 0
1596 #define FP_REG_FIRST 32
1597 #define FP_REG_LAST 63
1598 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1599 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1601 #define MD_REG_FIRST 64
1602 #define MD_REG_LAST 65
1603 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1604 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1606 #define ST_REG_FIRST 67
1607 #define ST_REG_LAST 74
1608 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1611 /* FIXME: renumber. */
1612 #define COP0_REG_FIRST 80
1613 #define COP0_REG_LAST 111
1614 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1616 #define COP2_REG_FIRST 112
1617 #define COP2_REG_LAST 143
1618 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1620 #define COP3_REG_FIRST 144
1621 #define COP3_REG_LAST 175
1622 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1623 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1624 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1626 #define AT_REGNUM (GP_REG_FIRST + 1)
1627 #define HI_REGNUM (MD_REG_FIRST + 0)
1628 #define LO_REGNUM (MD_REG_FIRST + 1)
1630 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1631 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1632 should be used instead. */
1633 #define FPSW_REGNUM ST_REG_FIRST
1635 #define GP_REG_P(REGNO) \
1636 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1637 #define M16_REG_P(REGNO) \
1638 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1639 #define FP_REG_P(REGNO) \
1640 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1641 #define MD_REG_P(REGNO) \
1642 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1643 #define ST_REG_P(REGNO) \
1644 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1645 #define COP0_REG_P(REGNO) \
1646 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1647 #define COP2_REG_P(REGNO) \
1648 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1649 #define COP3_REG_P(REGNO) \
1650 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1651 #define ALL_COP_REG_P(REGNO) \
1652 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1654 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1656 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1657 to initialize the mips16 gp pseudo register. */
1658 #define CONST_GP_P(X) \
1659 (GET_CODE (X) == CONST \
1660 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1661 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1663 /* Return coprocessor number from register number. */
1665 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1666 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1667 : COP3_REG_P (REGNO) ? '3' : '?')
1670 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1672 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1673 array built in override_options. Because machmodes.h is not yet
1674 included before this file is processed, the MODE bound can't be
1677 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1679 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1680 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1682 /* Value is 1 if it is a good idea to tie two pseudo registers
1683 when one has mode MODE1 and one has mode MODE2.
1684 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1685 for any hard reg, then this must be 0 for correct output. */
1686 #define MODES_TIEABLE_P(MODE1, MODE2) \
1687 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1688 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1689 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1690 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1692 /* Register to use for pushing function arguments. */
1693 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1695 /* These two registers don't really exist: they get eliminated to either
1696 the stack or hard frame pointer. */
1697 #define ARG_POINTER_REGNUM 77
1698 #define FRAME_POINTER_REGNUM 78
1700 /* $30 is not available on the mips16, so we use $17 as the frame
1702 #define HARD_FRAME_POINTER_REGNUM \
1703 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1705 /* Value should be nonzero if functions must have frame pointers.
1706 Zero means the frame pointer need not be set up (and parms
1707 may be accessed via the stack pointer) in functions that seem suitable.
1708 This is computed in `reload', in reload1.c. */
1709 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1711 /* Register in which static-chain is passed to a function. */
1712 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1714 /* Registers used as temporaries in prologue/epilogue code. If we're
1715 generating mips16 code, these registers must come from the core set
1716 of 8. The prologue register mustn't conflict with any incoming
1717 arguments, the static chain pointer, or the frame pointer. The
1718 epilogue temporary mustn't conflict with the return registers, the
1719 frame pointer, the EH stack adjustment, or the EH data registers. */
1721 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1722 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1724 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1725 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1727 /* Define this macro if it is as good or better to call a constant
1728 function address than to call an address kept in a register. */
1729 #define NO_FUNCTION_CSE 1
1731 /* The ABI-defined global pointer. Sometimes we use a different
1732 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1733 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1735 /* We normally use $28 as the global pointer. However, when generating
1736 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1737 register instead. They can then avoid saving and restoring $28
1738 and perhaps avoid using a frame at all.
1740 When a leaf function uses something other than $28, mips_expand_prologue
1741 will modify pic_offset_table_rtx in place. Take the register number
1742 from there after reload. */
1743 #define PIC_OFFSET_TABLE_REGNUM \
1744 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1746 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1748 /* Define the classes of registers for register constraints in the
1749 machine description. Also define ranges of constants.
1751 One of the classes must always be named ALL_REGS and include all hard regs.
1752 If there is more than one class, another class must be named NO_REGS
1753 and contain no registers.
1755 The name GENERAL_REGS must be the name of a class (or an alias for
1756 another name such as ALL_REGS). This is the class of registers
1757 that is allowed by "g" or "r" in a register constraint.
1758 Also, registers outside this class are allocated only when
1759 instructions express preferences for them.
1761 The classes must be numbered in nondecreasing order; that is,
1762 a larger-numbered class must never be contained completely
1763 in a smaller-numbered class.
1765 For any two classes, it is very desirable that there be another
1766 class that represents their union. */
1770 NO_REGS, /* no registers in set */
1771 M16_NA_REGS, /* mips16 regs not used to pass args */
1772 M16_REGS, /* mips16 directly accessible registers */
1773 T_REG, /* mips16 T register ($24) */
1774 M16_T_REGS, /* mips16 registers plus T register */
1775 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1776 LEA_REGS, /* Every GPR except $25 */
1777 GR_REGS, /* integer registers */
1778 FP_REGS, /* floating point registers */
1779 HI_REG, /* hi register */
1780 LO_REG, /* lo register */
1781 MD_REGS, /* multiply/divide registers (hi/lo) */
1782 COP0_REGS, /* generic coprocessor classes */
1785 HI_AND_GR_REGS, /* union classes */
1792 ALL_COP_AND_GR_REGS,
1793 ST_REGS, /* status registers (fp status) */
1794 ALL_REGS, /* all registers */
1795 LIM_REG_CLASSES /* max value + 1 */
1798 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1800 #define GENERAL_REGS GR_REGS
1802 /* An initializer containing the names of the register classes as C
1803 string constants. These names are used in writing some of the
1806 #define REG_CLASS_NAMES \
1813 "PIC_FN_ADDR_REG", \
1820 /* coprocessor registers */ \
1827 "COP0_AND_GR_REGS", \
1828 "COP2_AND_GR_REGS", \
1829 "COP3_AND_GR_REGS", \
1831 "ALL_COP_AND_GR_REGS", \
1836 /* An initializer containing the contents of the register classes,
1837 as integers which are bit masks. The Nth integer specifies the
1838 contents of class N. The way the integer MASK is interpreted is
1839 that register R is in the class if `MASK & (1 << R)' is 1.
1841 When the machine has more than 32 registers, an integer does not
1842 suffice. Then the integers are replaced by sub-initializers,
1843 braced groupings containing several integers. Each
1844 sub-initializer must be suitable as an initializer for the type
1845 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1847 #define REG_CLASS_CONTENTS \
1849 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1850 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1851 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1852 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1853 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1854 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1855 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1856 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1857 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1858 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1859 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1860 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1861 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1862 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1863 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1864 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1865 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1866 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1867 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1868 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1869 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1870 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1871 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1872 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1873 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1877 /* A C expression whose value is a register class containing hard
1878 register REGNO. In general there is more that one such class;
1879 choose a class which is "minimal", meaning that no smaller class
1880 also contains the register. */
1882 extern const enum reg_class mips_regno_to_class[];
1884 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1886 /* A macro whose definition is the name of the class to which a
1887 valid base register must belong. A base register is one used in
1888 an address which is the register value plus a displacement. */
1890 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1892 /* A macro whose definition is the name of the class to which a
1893 valid index register must belong. An index register is one used
1894 in an address where its value is either multiplied by a scale
1895 factor or added to another register (as well as added to a
1898 #define INDEX_REG_CLASS NO_REGS
1900 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1901 registers explicitly used in the rtl to be used as spill registers
1902 but prevents the compiler from extending the lifetime of these
1905 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1907 /* This macro is used later on in the file. */
1908 #define GR_REG_CLASS_P(CLASS) \
1909 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1910 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1911 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1913 /* This macro is also used later on in the file. */
1914 #define COP_REG_CLASS_P(CLASS) \
1915 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1917 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1918 is the default value (allocate the registers in numeric order). We
1919 define it just so that we can override it for the mips16 target in
1920 ORDER_REGS_FOR_LOCAL_ALLOC. */
1922 #define REG_ALLOC_ORDER \
1923 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1924 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1925 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1926 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1927 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1928 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1929 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1930 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1931 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1932 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1933 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1936 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1937 to be rearranged based on a particular function. On the mips16, we
1938 want to allocate $24 (T_REG) before other registers for
1939 instructions for which it is possible. */
1941 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1943 /* REGISTER AND CONSTANT CLASSES */
1945 /* Get reg_class from a letter such as appears in the machine
1948 DEFINED REGISTER CLASSES:
1950 'd' General (aka integer) registers
1951 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1952 'y' General registers (in both mips16 and non mips16 mode)
1953 'e' Effective address registers (general registers except $25)
1954 't' mips16 temporary register ($24)
1955 'f' Floating point registers
1958 'x' Multiply/divide registers
1959 'z' FP Status register
1963 'b' All registers */
1965 extern enum reg_class mips_char_to_class[256];
1967 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1969 /* True if VALUE is a signed 16-bit number. */
1971 #define SMALL_OPERAND(VALUE) \
1972 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1974 /* True if VALUE is an unsigned 16-bit number. */
1976 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1977 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1979 /* True if VALUE can be loaded into a register using LUI. */
1981 #define LUI_OPERAND(VALUE) \
1982 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1983 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1985 /* Return a value X with the low 16 bits clear, and such that
1986 VALUE - X is a signed 16-bit value. */
1988 #define CONST_HIGH_PART(VALUE) \
1989 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1991 #define CONST_LOW_PART(VALUE) \
1992 ((VALUE) - CONST_HIGH_PART (VALUE))
1994 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1995 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1996 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1998 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1999 string can be used to stand for particular ranges of immediate
2000 operands. This macro defines what the ranges are. C is the
2001 letter, and VALUE is a constant value. Return 1 if VALUE is
2002 in the range specified by C. */
2006 `I' is used for the range of constants an arithmetic insn can
2007 actually contain (16 bits signed integers).
2009 `J' is used for the range which is just zero (ie, $r0).
2011 `K' is used for the range of constants a logical insn can actually
2012 contain (16 bit zero-extended integers).
2014 `L' is used for the range of constants that be loaded with lui
2015 (ie, the bottom 16 bits are zero).
2017 `M' is used for the range of constants that take two words to load
2018 (ie, not matched by `I', `K', and `L').
2020 `N' is used for negative 16 bit constants other than -65536.
2022 `O' is a 15 bit signed integer.
2024 `P' is used for positive 16 bit constants. */
2026 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2027 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2028 : (C) == 'J' ? ((VALUE) == 0) \
2029 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2030 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2031 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2032 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2033 && !LUI_OPERAND (VALUE)) \
2034 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2035 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2036 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2039 /* Similar, but for floating constants, and defining letters G and H.
2040 Here VALUE is the CONST_DOUBLE rtx itself. */
2044 'G' : Floating point 0 */
2046 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2048 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2050 /* Letters in the range `Q' through `U' may be defined in a
2051 machine-dependent fashion to stand for arbitrary operand types.
2052 The machine description macro `EXTRA_CONSTRAINT' is passed the
2053 operand as its first argument and the constraint letter as its
2056 `Q' is for signed 16-bit constants.
2057 `R' is for single-instruction memory references. Note that this
2058 constraint has often been used in linux and glibc code.
2059 `S' is for legitimate constant call addresses.
2060 `T' is for constant move_operands that cannot be safely loaded into $25.
2061 `U' is for constant move_operands that can be safely loaded into $25.
2062 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2063 This is true for all non-mips16 references (although it can sometimes
2064 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2065 stack and constant-pool references. */
2067 #define EXTRA_CONSTRAINT(OP,CODE) \
2068 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2069 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2070 && mips_fetch_insns (OP) == 1) \
2071 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2072 && call_insn_operand (OP, VOIDmode)) \
2073 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2074 && move_operand (OP, VOIDmode) \
2075 && mips_dangerous_for_la25_p (OP)) \
2076 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2077 && move_operand (OP, VOIDmode) \
2078 && !mips_dangerous_for_la25_p (OP)) \
2079 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2080 && memory_operand (OP, VOIDmode) \
2081 && (!TARGET_MIPS16 \
2082 || (!stack_operand (OP, VOIDmode) \
2083 && !CONSTANT_P (XEXP (OP, 0))))) \
2086 /* Say which of the above are memory constraints. */
2087 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2089 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2090 mips_preferred_reload_class (X, CLASS)
2092 /* Certain machines have the property that some registers cannot be
2093 copied to some other registers without using memory. Define this
2094 macro on those machines to be a C expression that is nonzero if
2095 objects of mode MODE in registers of CLASS1 can only be copied to
2096 registers of class CLASS2 by storing a register of CLASS1 into
2097 memory and loading that memory location into a register of CLASS2.
2099 Do not define this macro if its value would always be zero. */
2101 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2102 ((!TARGET_DEBUG_H_MODE \
2103 && GET_MODE_CLASS (MODE) == MODE_INT \
2104 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2105 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2106 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2107 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2108 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2110 /* The HI and LO registers can only be reloaded via the general
2111 registers. Condition code registers can only be loaded to the
2112 general registers, and from the floating point registers. */
2114 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2115 mips_secondary_reload_class (CLASS, MODE, X, 1)
2116 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2117 mips_secondary_reload_class (CLASS, MODE, X, 0)
2119 /* Return the maximum number of consecutive registers
2120 needed to represent mode MODE in a register of class CLASS. */
2122 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2124 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2125 mips_cannot_change_mode_class (FROM, TO, CLASS)
2127 /* Stack layout; function entry, exit and calling. */
2129 #define STACK_GROWS_DOWNWARD
2131 /* The offset of the first local variable from the beginning of the frame.
2132 See compute_frame_size for details about the frame layout.
2134 ??? If flag_profile_values is true, and we are generating 32-bit code, then
2135 we assume that we will need 16 bytes of argument space. This is because
2136 the value profiling code may emit calls to cmpdi2 in leaf functions.
2137 Without this hack, the local variables will start at sp+8 and the gp save
2138 area will be at sp+16, and thus they will overlap. compute_frame_size is
2139 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
2140 will end up as 24 instead of 8. This won't be needed if profiling code is
2141 inserted before virtual register instantiation. */
2143 #define STARTING_FRAME_OFFSET \
2144 ((flag_profile_values && ! TARGET_64BIT \
2145 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
2146 : current_function_outgoing_args_size) \
2147 + (TARGET_ABICALLS && !TARGET_NEWABI \
2148 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2150 #define RETURN_ADDR_RTX mips_return_addr
2152 /* Since the mips16 ISA mode is encoded in the least-significant bit
2153 of the address, mask it off return addresses for purposes of
2154 finding exception handling regions. */
2156 #define MASK_RETURN_ADDR GEN_INT (-2)
2159 /* Similarly, don't use the least-significant bit to tell pointers to
2160 code from vtable index. */
2162 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2164 /* The eliminations to $17 are only used for mips16 code. See the
2165 definition of HARD_FRAME_POINTER_REGNUM. */
2167 #define ELIMINABLE_REGS \
2168 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2169 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2170 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2171 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2172 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2173 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2175 /* We can always eliminate to the hard frame pointer. We can eliminate
2176 to the stack pointer unless a frame pointer is needed.
2178 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2179 reload may be unable to compute the address of a local variable,
2180 since there is no way to add a large constant to the stack pointer
2181 without using a temporary register. */
2182 #define CAN_ELIMINATE(FROM, TO) \
2183 ((TO) == HARD_FRAME_POINTER_REGNUM \
2184 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2185 && (!TARGET_MIPS16 \
2186 || compute_frame_size (get_frame_size ()) < 32768)))
2188 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2189 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2191 /* Allocate stack space for arguments at the beginning of each function. */
2192 #define ACCUMULATE_OUTGOING_ARGS 1
2194 /* The argument pointer always points to the first argument. */
2195 #define FIRST_PARM_OFFSET(FNDECL) 0
2197 /* o32 and o64 reserve stack space for all argument registers. */
2198 #define REG_PARM_STACK_SPACE(FNDECL) \
2200 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2203 /* Define this if it is the responsibility of the caller to
2204 allocate the area reserved for arguments passed in registers.
2205 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2206 of this macro is to determine whether the space is included in
2207 `current_function_outgoing_args_size'. */
2208 #define OUTGOING_REG_PARM_STACK_SPACE
2210 #define STACK_BOUNDARY ((TARGET_OLDABI || mips_abi == ABI_EABI) ? 64 : 128)
2212 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2214 /* Symbolic macros for the registers used to return integer and floating
2217 #define GP_RETURN (GP_REG_FIRST + 2)
2218 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2220 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2222 /* Symbolic macros for the first/last argument registers. */
2224 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2225 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2226 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2227 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2229 #define LIBCALL_VALUE(MODE) \
2230 mips_function_value (NULL_TREE, NULL, (MODE))
2232 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2233 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2235 /* 1 if N is a possible register number for a function value.
2236 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2237 Currently, R2 and F0 are only implemented here (C has no complex type) */
2239 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2240 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2241 && (N) == FP_RETURN + 2))
2243 /* 1 if N is a possible register number for function argument passing.
2244 We have no FP argument registers when soft-float. When FP registers
2245 are 32 bits, we can't directly reference the odd numbered ones. */
2247 #define FUNCTION_ARG_REGNO_P(N) \
2248 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2249 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2252 /* This structure has to cope with two different argument allocation
2253 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2254 first N words go in registers and the rest go on the stack. If I < N,
2255 the Ith word might go in Ith integer argument register or the
2256 Ith floating-point one. For these ABIs, we only need to remember
2257 the number of words passed so far.
2259 The EABI instead allocates the integer and floating-point arguments
2260 separately. The first N words of FP arguments go in FP registers,
2261 the rest go on the stack. Likewise, the first N words of the other
2262 arguments go in integer registers, and the rest go on the stack. We
2263 need to maintain three counts: the number of integer registers used,
2264 the number of floating-point registers used, and the number of words
2265 passed on the stack.
2267 We could keep separate information for the two ABIs (a word count for
2268 the standard ABIs, and three separate counts for the EABI). But it
2269 seems simpler to view the standard ABIs as forms of EABI that do not
2270 allocate floating-point registers.
2272 So for the standard ABIs, the first N words are allocated to integer
2273 registers, and function_arg decides on an argument-by-argument basis
2274 whether that argument should really go in an integer register, or in
2275 a floating-point one. */
2277 typedef struct mips_args {
2278 /* Always true for varargs functions. Otherwise true if at least
2279 one argument has been passed in an integer register. */
2282 /* The number of arguments seen so far. */
2283 unsigned int arg_number;
2285 /* For EABI, the number of integer registers used so far. For other
2286 ABIs, the number of words passed in registers (whether integer
2287 or floating-point). */
2288 unsigned int num_gprs;
2290 /* For EABI, the number of floating-point registers used so far. */
2291 unsigned int num_fprs;
2293 /* The number of words passed on the stack. */
2294 unsigned int stack_words;
2296 /* On the mips16, we need to keep track of which floating point
2297 arguments were passed in general registers, but would have been
2298 passed in the FP regs if this were a 32 bit function, so that we
2299 can move them to the FP regs if we wind up calling a 32 bit
2300 function. We record this information in fp_code, encoded in base
2301 four. A zero digit means no floating point argument, a one digit
2302 means an SFmode argument, and a two digit means a DFmode argument,
2303 and a three digit is not used. The low order digit is the first
2304 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2305 an SFmode argument. ??? A more sophisticated approach will be
2306 needed if MIPS_ABI != ABI_32. */
2309 /* True if the function has a prototype. */
2313 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2314 for a call to a function whose data type is FNTYPE.
2315 For a library call, FNTYPE is 0. */
2317 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2318 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2320 /* Update the data in CUM to advance over an argument
2321 of mode MODE and data type TYPE.
2322 (TYPE is null for libcalls where that information may not be available.) */
2324 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2325 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2327 /* Determine where to put an argument to a function.
2328 Value is zero to push the argument on the stack,
2329 or a hard register in which to store the argument.
2331 MODE is the argument's machine mode.
2332 TYPE is the data type of the argument (as a tree).
2333 This is null for libcalls where that information may
2335 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2336 the preceding args and about the function being called.
2337 NAMED is nonzero if this argument is a named parameter
2338 (otherwise it is an extra parameter matching an ellipsis). */
2340 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2341 function_arg( &CUM, MODE, TYPE, NAMED)
2343 /* For an arg passed partly in registers and partly in memory,
2344 this is the number of registers used.
2345 For args passed entirely in registers or entirely in memory, zero. */
2347 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2348 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2350 /* If defined, a C expression that gives the alignment boundary, in
2351 bits, of an argument with the specified mode and type. If it is
2352 not defined, `PARM_BOUNDARY' is used for all arguments. */
2354 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2356 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2358 : TYPE_ALIGN(TYPE)) \
2359 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2361 : GET_MODE_ALIGNMENT(MODE)))
2363 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2364 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2366 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2367 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2369 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2370 (mips_abi == ABI_EABI && (NAMED))
2372 /* True if using EABI and varargs can be passed in floating-point
2373 registers. Under these conditions, we need a more complex form
2374 of va_list, which tracks GPR, FPR and stack arguments separately. */
2375 #define EABI_FLOAT_VARARGS_P \
2376 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2379 /* Say that the epilogue uses the return address register. Note that
2380 in the case of sibcalls, the values "used by the epilogue" are
2381 considered live at the start of the called function. */
2382 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2384 /* Treat LOC as a byte offset from the stack pointer and round it up
2385 to the next fully-aligned offset. */
2386 #define MIPS_STACK_ALIGN(LOC) \
2387 ((TARGET_OLDABI || mips_abi == ABI_EABI) \
2388 ? ((LOC) + 7) & ~7 \
2389 : ((LOC) + 15) & ~15)
2392 /* Implement `va_start' for varargs and stdarg. */
2393 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2394 mips_va_start (valist, nextarg)
2396 /* Output assembler code to FILE to increment profiler label # LABELNO
2397 for profiling a function entry. */
2399 #define FUNCTION_PROFILER(FILE, LABELNO) \
2401 if (TARGET_MIPS16) \
2402 sorry ("mips16 function profiling"); \
2403 fprintf (FILE, "\t.set\tnoat\n"); \
2404 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2405 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2406 if (!TARGET_NEWABI) \
2409 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2410 TARGET_64BIT ? "dsubu" : "subu", \
2411 reg_names[STACK_POINTER_REGNUM], \
2412 reg_names[STACK_POINTER_REGNUM], \
2413 Pmode == DImode ? 16 : 8); \
2415 fprintf (FILE, "\tjal\t_mcount\n"); \
2416 fprintf (FILE, "\t.set\tat\n"); \
2419 /* Define this macro if the code for function profiling should come
2420 before the function prologue. Normally, the profiling code comes
2423 /* #define PROFILE_BEFORE_PROLOGUE */
2425 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2426 the stack pointer does not matter. The value is tested only in
2427 functions that have frame pointers.
2428 No definition is equivalent to always zero. */
2430 #define EXIT_IGNORE_STACK 1
2433 /* A C statement to output, on the stream FILE, assembler code for a
2434 block of data that contains the constant parts of a trampoline.
2435 This code should not include a label--the label is taken care of
2438 #define TRAMPOLINE_TEMPLATE(STREAM) \
2440 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2441 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2442 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2443 if (ptr_mode == DImode) \
2445 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2446 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2450 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2451 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2453 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2454 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2455 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2456 if (ptr_mode == DImode) \
2458 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2459 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2463 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2464 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2468 /* A C expression for the size in bytes of the trampoline, as an
2471 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2473 /* Alignment required for trampolines, in bits. */
2475 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2477 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2478 program and data caches. */
2480 #ifndef CACHE_FLUSH_FUNC
2481 #define CACHE_FLUSH_FUNC "_flush_cache"
2484 /* A C statement to initialize the variable parts of a trampoline.
2485 ADDR is an RTX for the address of the trampoline; FNADDR is an
2486 RTX for the address of the nested function; STATIC_CHAIN is an
2487 RTX for the static chain value that should be passed to the
2488 function when it is called. */
2490 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2492 rtx func_addr, chain_addr; \
2494 func_addr = plus_constant (ADDR, 32); \
2495 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2496 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2497 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2499 /* Flush both caches. We need to flush the data cache in case \
2500 the system has a write-back cache. */ \
2501 /* ??? Should check the return value for errors. */ \
2502 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2503 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2504 0, VOIDmode, 3, ADDR, Pmode, \
2505 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2506 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2509 /* Addressing modes, and classification of registers for them. */
2511 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2512 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2513 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2515 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2516 and check its validity for a certain class.
2517 We have two alternate definitions for each of them.
2518 The usual definition accepts all pseudo regs; the other rejects them all.
2519 The symbol REG_OK_STRICT causes the latter definition to be used.
2521 Most source files want to accept pseudo regs in the hope that
2522 they will get allocated to the class that the insn wants them to be in.
2523 Some source files that are used after register allocation
2524 need to be strict. */
2526 #ifndef REG_OK_STRICT
2527 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2528 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2530 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2531 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2534 #define REG_OK_FOR_INDEX_P(X) 0
2537 /* Maximum number of registers that can appear in a valid memory address. */
2539 #define MAX_REGS_PER_ADDRESS 1
2541 #ifdef REG_OK_STRICT
2542 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2544 if (mips_legitimate_address_p (MODE, X, 1)) \
2548 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2550 if (mips_legitimate_address_p (MODE, X, 0)) \
2555 /* Check for constness inline but use mips_legitimate_address_p
2556 to check whether a constant really is an address. */
2558 #define CONSTANT_ADDRESS_P(X) \
2559 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2561 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2563 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2565 if (mips_legitimize_address (&(X), MODE)) \
2570 /* A C statement or compound statement with a conditional `goto
2571 LABEL;' executed if memory address X (an RTX) can have different
2572 meanings depending on the machine mode of the memory reference it
2575 Autoincrement and autodecrement addresses typically have
2576 mode-dependent effects because the amount of the increment or
2577 decrement is the size of the operand being addressed. Some
2578 machines have other mode-dependent addresses. Many RISC machines
2579 have no mode-dependent addresses.
2581 You may assume that ADDR is a valid address for the machine. */
2583 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2585 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2586 'the start of the function that this code is output in'. */
2588 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2589 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2590 asm_fprintf ((FILE), "%U%s", \
2591 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2593 asm_fprintf ((FILE), "%U%s", (NAME))
2595 /* Specify the machine mode that this machine uses
2596 for the index in the tablejump instruction.
2597 ??? Using HImode in mips16 mode can cause overflow. */
2598 #define CASE_VECTOR_MODE \
2599 (TARGET_MIPS16 ? HImode : ptr_mode)
2601 /* Define as C expression which evaluates to nonzero if the tablejump
2602 instruction expects the table to contain offsets from the address of the
2604 Do not define this if the table should contain absolute addresses. */
2605 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2607 /* Define this as 1 if `char' should by default be signed; else as 0. */
2608 #ifndef DEFAULT_SIGNED_CHAR
2609 #define DEFAULT_SIGNED_CHAR 1
2612 /* Max number of bytes we can move from memory to memory
2613 in one reasonably fast instruction. */
2614 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2615 #define MAX_MOVE_MAX 8
2617 /* Define this macro as a C expression which is nonzero if
2618 accessing less than a word of memory (i.e. a `char' or a
2619 `short') is no faster than accessing a word of memory, i.e., if
2620 such access require more than one instruction or if there is no
2621 difference in cost between byte and (aligned) word loads.
2623 On RISC machines, it tends to generate better code to define
2624 this as 1, since it avoids making a QI or HI mode register. */
2625 #define SLOW_BYTE_ACCESS 1
2627 /* Define this to be nonzero if shift instructions ignore all but the low-order
2629 #define SHIFT_COUNT_TRUNCATED 1
2631 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2632 is done just by pretending it is already truncated. */
2633 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2634 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2637 /* Specify the machine mode that pointers have.
2638 After generation of rtl, the compiler makes no further distinction
2639 between pointers and any other objects of this machine mode. */
2642 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2645 /* Give call MEMs SImode since it is the "most permissive" mode
2646 for both 32-bit and 64-bit targets. */
2648 #define FUNCTION_MODE SImode
2651 /* The cost of loading values from the constant pool. It should be
2652 larger than the cost of any constant we want to synthesize in-line. */
2654 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2656 /* A C expression for the cost of moving data from a register in
2657 class FROM to one in class TO. The classes are expressed using
2658 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2659 the default; other values are interpreted relative to that.
2661 It is not required that the cost always equal 2 when FROM is the
2662 same as TO; on some machines it is expensive to move between
2663 registers if they are not general registers.
2665 If reload sees an insn consisting of a single `set' between two
2666 hard registers, and if `REGISTER_MOVE_COST' applied to their
2667 classes returns a value of 2, reload does not check to ensure
2668 that the constraints of the insn are met. Setting a cost of
2669 other than 2 will allow reload to verify that the constraints are
2670 met. You should do this if the `movM' pattern's constraints do
2671 not allow such copying. */
2673 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2674 mips_register_move_cost (MODE, FROM, TO)
2676 /* ??? Fix this to be right for the R8000. */
2677 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2678 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2679 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2681 /* Define if copies to/from condition code registers should be avoided.
2683 This is needed for the MIPS because reload_outcc is not complete;
2684 it needs to handle cases where the source is a general or another
2685 condition code register. */
2686 #define AVOID_CCMODE_COPIES
2688 /* A C expression for the cost of a branch instruction. A value of
2689 1 is the default; other values are interpreted relative to that. */
2691 /* ??? Fix this to be right for the R8000. */
2692 #define BRANCH_COST \
2694 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2697 /* If defined, modifies the length assigned to instruction INSN as a
2698 function of the context in which it is used. LENGTH is an lvalue
2699 that contains the initially computed length of the insn and should
2700 be updated with the correct length of the insn. */
2701 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2702 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2704 /* Control the assembler format that we output. */
2706 /* Output to assembler file text saying following lines
2707 may contain character constants, extra white space, comments, etc. */
2710 #define ASM_APP_ON " #APP\n"
2713 /* Output to assembler file text saying following lines
2714 no longer contain unusual constructs. */
2717 #define ASM_APP_OFF " #NO_APP\n"
2720 #define REGISTER_NAMES \
2721 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2722 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2723 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2724 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2725 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2726 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2727 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2728 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2729 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2730 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2731 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2732 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2733 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2734 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2735 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2736 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2737 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2738 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2739 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2740 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2741 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2742 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
2744 /* List the "software" names for each register. Also list the numerical
2745 names for $fp and $sp. */
2747 #define ADDITIONAL_REGISTER_NAMES \
2749 { "$29", 29 + GP_REG_FIRST }, \
2750 { "$30", 30 + GP_REG_FIRST }, \
2751 { "at", 1 + GP_REG_FIRST }, \
2752 { "v0", 2 + GP_REG_FIRST }, \
2753 { "v1", 3 + GP_REG_FIRST }, \
2754 { "a0", 4 + GP_REG_FIRST }, \
2755 { "a1", 5 + GP_REG_FIRST }, \
2756 { "a2", 6 + GP_REG_FIRST }, \
2757 { "a3", 7 + GP_REG_FIRST }, \
2758 { "t0", 8 + GP_REG_FIRST }, \
2759 { "t1", 9 + GP_REG_FIRST }, \
2760 { "t2", 10 + GP_REG_FIRST }, \
2761 { "t3", 11 + GP_REG_FIRST }, \
2762 { "t4", 12 + GP_REG_FIRST }, \
2763 { "t5", 13 + GP_REG_FIRST }, \
2764 { "t6", 14 + GP_REG_FIRST }, \
2765 { "t7", 15 + GP_REG_FIRST }, \
2766 { "s0", 16 + GP_REG_FIRST }, \
2767 { "s1", 17 + GP_REG_FIRST }, \
2768 { "s2", 18 + GP_REG_FIRST }, \
2769 { "s3", 19 + GP_REG_FIRST }, \
2770 { "s4", 20 + GP_REG_FIRST }, \
2771 { "s5", 21 + GP_REG_FIRST }, \
2772 { "s6", 22 + GP_REG_FIRST }, \
2773 { "s7", 23 + GP_REG_FIRST }, \
2774 { "t8", 24 + GP_REG_FIRST }, \
2775 { "t9", 25 + GP_REG_FIRST }, \
2776 { "k0", 26 + GP_REG_FIRST }, \
2777 { "k1", 27 + GP_REG_FIRST }, \
2778 { "gp", 28 + GP_REG_FIRST }, \
2779 { "sp", 29 + GP_REG_FIRST }, \
2780 { "fp", 30 + GP_REG_FIRST }, \
2781 { "ra", 31 + GP_REG_FIRST }, \
2782 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2785 /* This is meant to be redefined in the host dependent files. It is a
2786 set of alternative names and regnums for mips coprocessors. */
2788 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2790 /* A C compound statement to output to stdio stream STREAM the
2791 assembler syntax for an instruction operand X. X is an RTL
2794 CODE is a value that can be used to specify one of several ways
2795 of printing the operand. It is used when identical operands
2796 must be printed differently depending on the context. CODE
2797 comes from the `%' specification that was used to request
2798 printing of the operand. If the specification was just `%DIGIT'
2799 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2800 is the ASCII code for LTR.
2802 If X is a register, this macro should print the register's name.
2803 The names can be found in an array `reg_names' whose type is
2804 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2806 When the machine description has a specification `%PUNCT' (a `%'
2807 followed by a punctuation character), this macro is called with
2808 a null pointer for X and the punctuation character for CODE.
2810 See mips.c for the MIPS specific codes. */
2812 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2814 /* A C expression which evaluates to true if CODE is a valid
2815 punctuation character for use in the `PRINT_OPERAND' macro. If
2816 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2817 punctuation characters (except for the standard one, `%') are
2818 used in this way. */
2820 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2822 /* A C compound statement to output to stdio stream STREAM the
2823 assembler syntax for an instruction operand that is a memory
2824 reference whose address is ADDR. ADDR is an RTL expression. */
2826 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2829 /* A C statement, to be executed after all slot-filler instructions
2830 have been output. If necessary, call `dbr_sequence_length' to
2831 determine the number of slots filled in a sequence (zero if not
2832 currently outputting a sequence), to decide how many no-ops to
2833 output, or whatever.
2835 Don't define this macro if it has nothing to do, but it is
2836 helpful in reading assembly output if the extent of the delay
2837 sequence is made explicit (e.g. with white space).
2839 Note that output routines for instructions with delay slots must
2840 be prepared to deal with not being output as part of a sequence
2841 (i.e. when the scheduling pass is not run, or when no slot
2842 fillers could be found.) The variable `final_sequence' is null
2843 when not processing a sequence, otherwise it contains the
2844 `sequence' rtx being output. */
2846 #define DBR_OUTPUT_SEQEND(STREAM) \
2849 if (set_nomacro > 0 && --set_nomacro == 0) \
2850 fputs ("\t.set\tmacro\n", STREAM); \
2852 if (set_noreorder > 0 && --set_noreorder == 0) \
2853 fputs ("\t.set\treorder\n", STREAM); \
2855 fputs ("\n", STREAM); \
2860 /* How to tell the debugger about changes of source files. */
2862 #ifndef SET_FILE_NUMBER
2863 #define SET_FILE_NUMBER() ++num_source_filenames
2866 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2867 mips_output_filename (STREAM, NAME)
2869 /* This is defined so that it can be overridden in iris6.h. */
2870 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
2873 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
2874 output_quoted_string (STREAM, NAME); \
2875 fputs ("\n", STREAM); \
2879 /* This is how to output a note the debugger telling it the line number
2880 to which the following sequence of instructions corresponds.
2881 Silicon graphics puts a label after each .loc. */
2883 #ifndef LABEL_AFTER_LOC
2884 #define LABEL_AFTER_LOC(STREAM)
2887 #ifndef ASM_OUTPUT_SOURCE_LINE
2888 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
2889 mips_output_lineno (STREAM, LINE)
2892 /* The MIPS implementation uses some labels for its own purpose. The
2893 following lists what labels are created, and are all formed by the
2894 pattern $L[a-z].*. The machine independent portion of GCC creates
2895 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2897 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2898 $Lb[0-9]+ Begin blocks for MIPS debug support
2899 $Lc[0-9]+ Label for use in s<xx> operation.
2900 $Le[0-9]+ End blocks for MIPS debug support */
2902 #undef ASM_DECLARE_OBJECT_NAME
2903 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2904 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2906 /* Globalizing directive for a label. */
2907 #define GLOBAL_ASM_OP "\t.globl\t"
2909 /* This says how to define a global common symbol. */
2911 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2913 /* This says how to define a local common symbol (ie, not visible to
2916 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2917 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2918 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2921 /* This says how to output an external. It would be possible not to
2922 output anything and let undefined symbol become external. However
2923 the assembler uses length information on externals to allocate in
2924 data/sdata bss/sbss, thereby saving exec time. */
2926 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2927 mips_output_external(STREAM,DECL,NAME)
2929 /* This is how to declare a function name. The actual work of
2930 emitting the label is moved to function_prologue, so that we can
2931 get the line number correctly emitted before the .ent directive,
2932 and after any .file directives. Define as empty so that the function
2933 is not declared before the .ent directive elsewhere. */
2935 #undef ASM_DECLARE_FUNCTION_NAME
2936 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2938 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2939 #define FUNCTION_NAME_ALREADY_DECLARED 0
2942 /* This is how to store into the string LABEL
2943 the symbol_ref name of an internal numbered label where
2944 PREFIX is the class of label and NUM is the number within the class.
2945 This is suitable for output with `assemble_name'. */
2947 #undef ASM_GENERATE_INTERNAL_LABEL
2948 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2949 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2951 /* This is how to output an element of a case-vector that is absolute. */
2953 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2954 fprintf (STREAM, "\t%s\t%sL%d\n", \
2955 ptr_mode == DImode ? ".dword" : ".word", \
2956 LOCAL_LABEL_PREFIX, \
2959 /* This is how to output an element of a case-vector. We can make the
2960 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2963 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2965 if (TARGET_MIPS16) \
2966 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2967 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2968 else if (TARGET_GPWORD) \
2969 fprintf (STREAM, "\t%s\t%sL%d\n", \
2970 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2971 LOCAL_LABEL_PREFIX, VALUE); \
2973 fprintf (STREAM, "\t%s\t%sL%d\n", \
2974 ptr_mode == DImode ? ".dword" : ".word", \
2975 LOCAL_LABEL_PREFIX, VALUE); \
2978 /* When generating mips16 code we want to put the jump table in the .text
2979 section. In all other cases, we want to put the jump table in the .rdata
2980 section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
2981 it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
2982 to the .text section if appropriate. */
2983 #undef ASM_OUTPUT_CASE_LABEL
2984 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
2986 if (TARGET_MIPS16) \
2987 function_section (current_function_decl); \
2988 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2991 /* This is how to output an assembler line
2992 that says to advance the location counter
2993 to a multiple of 2**LOG bytes. */
2995 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2996 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2998 /* This is how to output an assembler line to advance the location
2999 counter by SIZE bytes. */
3001 #undef ASM_OUTPUT_SKIP
3002 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3003 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3005 /* This is how to output a string. */
3006 #undef ASM_OUTPUT_ASCII
3007 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3008 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3010 /* Output #ident as a in the read-only data section. */
3011 #undef ASM_OUTPUT_IDENT
3012 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3014 const char *p = STRING; \
3015 int size = strlen (p) + 1; \
3016 readonly_data_section (); \
3017 assemble_string (p, size); \
3020 /* Default to -G 8 */
3021 #ifndef MIPS_DEFAULT_GVALUE
3022 #define MIPS_DEFAULT_GVALUE 8
3025 /* Define the strings to put out for each section in the object file. */
3026 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3027 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3028 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3030 #undef READONLY_DATA_SECTION_ASM_OP
3031 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3033 /* Given a decl node or constant node, choose the section to output it in
3034 and select that section. */
3036 #undef TARGET_ASM_SELECT_SECTION
3037 #define TARGET_ASM_SELECT_SECTION mips_select_section
3039 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3042 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3043 TARGET_64BIT ? "dsubu" : "subu", \
3044 reg_names[STACK_POINTER_REGNUM], \
3045 reg_names[STACK_POINTER_REGNUM], \
3046 TARGET_64BIT ? "sd" : "sw", \
3048 reg_names[STACK_POINTER_REGNUM]); \
3052 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3055 if (! set_noreorder) \
3056 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3058 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3059 TARGET_64BIT ? "ld" : "lw", \
3061 reg_names[STACK_POINTER_REGNUM], \
3062 TARGET_64BIT ? "daddu" : "addu", \
3063 reg_names[STACK_POINTER_REGNUM], \
3064 reg_names[STACK_POINTER_REGNUM]); \
3066 if (! set_noreorder) \
3067 fprintf (STREAM, "\t.set\treorder\n"); \
3071 /* How to start an assembler comment.
3072 The leading space is important (the mips native assembler requires it). */
3073 #ifndef ASM_COMMENT_START
3074 #define ASM_COMMENT_START " #"
3077 /* Default definitions for size_t and ptrdiff_t. We must override the
3078 definitions from ../svr4.h on mips-*-linux-gnu. */
3081 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3084 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3086 /* See mips_expand_prologue's use of loadgp for when this should be
3089 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
3092 /* Since the bits of the _init and _fini function is spread across
3093 many object files, each potentially with its own GP, we must assume
3094 we need to load our GP. We don't preserve $gp or $ra, since each
3095 init/fini chunk is supposed to initialize $gp, and crti/crtn
3096 already take care of preserving $ra and, when appropriate, $gp. */
3097 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3098 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3099 asm (SECTION_OP "\n\
3105 jal " USER_LABEL_PREFIX #FUNC "\n\
3106 " TEXT_SECTION_ASM_OP);
3107 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3108 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3109 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3110 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3111 asm (SECTION_OP "\n\
3116 .cpsetup $31, $2, 1b\n\
3117 jal " USER_LABEL_PREFIX #FUNC "\n\
3118 " TEXT_SECTION_ASM_OP);