1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern char *language_string;
32 extern int may_call_alloca;
33 extern char **save_argv;
34 extern int target_flags;
35 extern char *version_string;
37 /* MIPS external variables defined in mips.c. */
41 CMP_SI, /* compare four byte integers */
42 CMP_DI, /* compare eight byte integers */
43 CMP_SF, /* compare single precision floats */
44 CMP_DF, /* compare double precision floats */
45 CMP_MAX /* max comparison type */
48 /* types of delay slot */
50 DELAY_NONE, /* no delay slot */
51 DELAY_LOAD, /* load from memory delay */
52 DELAY_HILO, /* move from/to hi/lo registers */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. These are constants because abi64.h must check their
79 value at preprocessing time.
81 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
82 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
90 #ifndef MIPS_ABI_DEFAULT
91 /* We define this away so that there is no extra runtime cost if the target
92 doesn't support multiple ABIs. */
93 #define mips_abi ABI_32
98 /* Whether to emit abicalls code sequences or not. */
100 enum mips_abicalls_type {
105 /* Recast the abicalls class to be the abicalls attribute. */
106 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
108 /* Which type of block move to do (whether or not the last store is
109 split out so it can fill a branch delay slot). */
111 enum block_move_type {
112 BLOCK_MOVE_NORMAL, /* generate complete block move */
113 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
114 BLOCK_MOVE_LAST /* generate just the last store */
117 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
118 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
119 extern const char *current_function_file; /* filename current function is in */
120 extern int num_source_filenames; /* current .file # */
121 extern int inside_function; /* != 0 if inside of a function */
122 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
123 extern int file_in_function_warning; /* warning given about .file in func */
124 extern int sdb_label_count; /* block start/end next label # */
125 extern int sdb_begin_function_line; /* Starting Line of current function */
126 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
127 extern int g_switch_value; /* value of the -G xx switch */
128 extern int g_switch_set; /* whether -G xx was passed. */
129 extern int sym_lineno; /* sgi next label # for each stmt */
130 extern int set_noreorder; /* # of nested .set noreorder's */
131 extern int set_nomacro; /* # of nested .set nomacro's */
132 extern int set_noat; /* # of nested .set noat's */
133 extern int set_volatile; /* # of nested .set volatile's */
134 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
135 extern int mips_dbx_regno[]; /* Map register # to debug register # */
136 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
137 extern enum cmp_type branch_type; /* what type of branch to use */
138 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
139 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
140 extern int mips_isa; /* architectural level */
141 extern int mips16; /* whether generating mips16 code */
142 extern int mips16_hard_float; /* mips16 without -msoft-float */
143 extern int mips_entry; /* generate entry/exit for mips16 */
144 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
145 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
146 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
147 extern const char *mips_entry_string; /* for -mentry */
148 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
149 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
150 extern int mips_split_addresses; /* perform high/lo_sum support */
151 extern int dslots_load_total; /* total # load related delay slots */
152 extern int dslots_load_filled; /* # filled load delay slots */
153 extern int dslots_jump_total; /* total # jump related delay slots */
154 extern int dslots_jump_filled; /* # filled jump delay slots */
155 extern int dslots_number_nops; /* # of nops needed by previous insn */
156 extern int num_refs[3]; /* # 1/2/3 word references */
157 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
158 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
159 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
160 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
161 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
162 extern int mips_string_length; /* length of strings for mips16 */
163 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
165 /* Functions within mips.c that we reference. Some of these return
166 type HOST_WIDE_INT, so define that here. */
170 extern int arith32_operand ();
171 extern int arith_operand ();
172 extern int cmp_op ();
174 extern HOST_WIDE_INT compute_frame_size ();
176 extern int const_float_1_operand ();
177 extern void expand_block_move ();
178 extern int equality_op ();
179 extern void final_prescan_insn ();
180 extern struct rtx_def * function_arg ();
181 extern void function_arg_advance ();
182 extern int function_arg_partial_nregs ();
183 extern int function_arg_pass_by_reference ();
184 extern void function_epilogue ();
185 extern void function_prologue ();
186 extern void gen_conditional_branch ();
187 extern void gen_conditional_move ();
188 extern struct rtx_def * gen_int_relational ();
189 extern void init_cumulative_args ();
190 extern int large_int ();
191 extern void machine_dependent_reorg ();
192 extern int mips_address_cost ();
193 extern void mips_asm_file_end ();
194 extern void mips_asm_file_start ();
195 extern int mips_can_use_return_insn ();
196 extern int mips_const_double_ok ();
197 extern void mips_count_memory_refs ();
199 extern HOST_WIDE_INT mips_debugger_offset ();
201 extern void mips_declare_object ();
202 extern int mips_epilogue_delay_slots ();
203 extern void mips_expand_epilogue ();
204 extern void mips_expand_prologue ();
205 extern int mips_check_split ();
206 extern char *mips_fill_delay_slot ();
207 extern const char *mips_move_1word ();
208 extern const char *mips_move_2words ();
209 extern void mips_output_double ();
210 extern int mips_output_external ();
211 extern void mips_output_float ();
212 extern void mips_output_filename ();
213 extern void mips_output_lineno ();
214 extern const char *output_block_move ();
215 extern void override_options ();
216 extern int pc_or_label_operand ();
217 extern void print_operand_address ();
218 extern void print_operand ();
219 extern void print_options ();
220 extern int reg_or_0_operand ();
221 extern int true_reg_or_0_operand ();
222 extern int simple_epilogue_p ();
223 extern int simple_memory_operand ();
224 extern int double_memory_operand ();
225 extern int small_int ();
226 extern void trace ();
227 extern int uns_arith_operand ();
228 extern struct rtx_def * embedded_pic_offset ();
229 extern void mips_order_regs_for_local_alloc ();
230 extern struct rtx_def * mips16_gp_pseudo_reg ();
231 extern struct rtx_def * mips16_gp_offset ();
232 extern int mips16_gp_offset_p ();
233 extern int mips16_constant ();
234 extern int mips16_constant_after_function_p ();
235 extern int build_mips16_call_stub ();
236 extern char *mips_output_conditional_branch ();
237 extern int mips_adjust_insn_length ();
239 /* Recognition functions that return if a condition is true. */
240 extern int address_operand ();
241 extern int call_insn_operand ();
242 extern int const_double_operand ();
243 extern int const_int_operand ();
244 extern int consttable_operand ();
245 extern int general_operand ();
246 extern int immediate_operand ();
247 extern int memory_address_p ();
248 extern int memory_operand ();
249 extern int nonimmediate_operand ();
250 extern int nonmemory_operand ();
251 extern int pic_address_needs_scratch ();
252 extern int register_operand ();
253 extern int scratch_operand ();
254 extern int move_operand ();
255 extern int movdi_operand ();
256 extern int se_register_operand ();
257 extern int se_reg_or_0_operand ();
258 extern int se_uns_arith_operand ();
259 extern int se_arith_operand ();
260 extern int se_nonmemory_operand ();
261 extern int se_nonimmediate_operand ();
262 extern int extend_operator ();
263 extern int highpart_shift_operator ();
264 extern int m16_uimm3_b ();
265 extern int m16_simm4_1 ();
266 extern int m16_nsimm4_1 ();
267 extern int m16_simm5_1 ();
268 extern int m16_nsimm5_1 ();
269 extern int m16_uimm5_4 ();
270 extern int m16_nuimm5_4 ();
271 extern int m16_simm8_1 ();
272 extern int m16_nsimm8_1 ();
273 extern int m16_uimm8_1 ();
274 extern int m16_nuimm8_1 ();
275 extern int m16_uimm8_m1_1 ();
276 extern int m16_uimm8_4 ();
277 extern int m16_nuimm8_4 ();
278 extern int m16_simm8_8 ();
279 extern int m16_nsimm8_8 ();
280 extern int m16_usym8_4 ();
281 extern int m16_usym5_4 ();
283 /* Functions to change what output section we are using. */
284 extern void data_section ();
285 extern void rdata_section ();
286 extern void readonly_data_section ();
287 extern void sdata_section ();
288 extern void text_section ();
289 extern void mips_select_rtx_section ();
290 extern void mips_select_section ();
292 /* Stubs for half-pic support if not OSF/1 reference platform. */
295 #define HALF_PIC_P() 0
296 #define HALF_PIC_NUMBER_PTRS 0
297 #define HALF_PIC_NUMBER_REFS 0
298 #define HALF_PIC_ENCODE(DECL)
299 #define HALF_PIC_DECLARE(NAME)
300 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
301 #define HALF_PIC_ADDRESS_P(X) 0
302 #define HALF_PIC_PTR(X) X
303 #define HALF_PIC_FINISH(STREAM)
307 /* Run-time compilation parameters selecting different hardware subsets. */
309 /* Macros used in the machine description to test the flags. */
311 /* Bits for real switches */
312 #define MASK_INT64 0x00000001 /* ints are 64 bits */
313 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
314 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
315 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
316 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
317 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
318 #define MASK_STATS 0x00000040 /* print statistics to stderr */
319 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
320 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
321 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
322 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
323 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
324 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
325 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
326 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
327 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
328 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
329 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
330 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
331 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
332 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
333 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
334 #define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
335 #define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
337 /* Dummy switches used only in spec's*/
338 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
340 /* Debug switches, not documented */
341 #define MASK_DEBUG 0 /* Eliminate version # in .s file */
342 #define MASK_DEBUG_A 0x40000000 /* don't allow <label>($reg) addrs */
343 #define MASK_DEBUG_B 0x20000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
344 #define MASK_DEBUG_C 0x10000000 /* don't expand seq, etc. */
345 #define MASK_DEBUG_D 0 /* don't do define_split's */
346 #define MASK_DEBUG_E 0 /* function_arg debug */
347 #define MASK_DEBUG_F 0
348 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
349 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
350 #define MASK_DEBUG_I 0 /* unused */
352 /* r4000 64 bit sizes */
353 #define TARGET_INT64 (target_flags & MASK_INT64)
354 #define TARGET_LONG64 (target_flags & MASK_LONG64)
355 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
356 #define TARGET_64BIT (target_flags & MASK_64BIT)
358 /* Mips vs. GNU linker */
359 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
361 /* generate mips 3900 insns */
362 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
364 /* Mips vs. GNU assembler */
365 #define TARGET_GAS (target_flags & MASK_GAS)
366 #define TARGET_UNIX_ASM (!TARGET_GAS)
367 #define TARGET_MIPS_AS TARGET_UNIX_ASM
370 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
371 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
372 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
373 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
374 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
375 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
376 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
377 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
378 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
379 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
381 /* Reg. Naming in .s ($21 vs. $a0) */
382 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
384 /* Optimize for Sdata/Sbss */
385 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
387 /* print program statistics */
388 #define TARGET_STATS (target_flags & MASK_STATS)
390 /* call memcpy instead of inline code */
391 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
393 /* .abicalls, etc from Pyramid V.4 */
394 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
396 /* OSF pic references to externs */
397 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
399 /* software floating point */
400 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
401 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
403 /* always call through a register */
404 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
406 /* generate embedded PIC code;
408 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
410 /* for embedded systems, optimize for
411 reduced RAM space instead of for
413 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
415 /* generate big endian code. */
416 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
418 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
419 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
421 #define TARGET_MAD (target_flags & MASK_MAD)
423 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
425 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
426 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
428 /* This is true if we must enable the assembly language file switching
431 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
433 /* We must disable the function end stabs when doing the file switching trick,
434 because the Lscope stabs end up in the wrong place, making it impossible
435 to debug the resulting code. */
436 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
438 /* Generate mips16 code */
439 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
441 /* Macro to define tables used to set the flags.
442 This is a list in braces of pairs in braces,
443 each pair being { "NAME", VALUE }
444 where VALUE is the bits to set or minus the bits to clear.
445 An empty string NAME is used to identify the default VALUE. */
447 #define TARGET_SWITCHES \
449 {"int64", MASK_INT64 | MASK_LONG64, \
450 "Use 64-bit int type"}, \
451 {"long64", MASK_LONG64, \
452 "Use 64-bit long type"}, \
453 {"long32", -(MASK_LONG64 | MASK_INT64), \
454 "Use 32-bit long type"}, \
455 {"split-addresses", MASK_SPLIT_ADDR, \
456 "Optimize lui/addiu address loads"}, \
457 {"no-split-addresses", -MASK_SPLIT_ADDR, \
458 "Don't optimize lui/addiu address loads"}, \
459 {"mips-as", -MASK_GAS, \
463 {"rnames", MASK_NAME_REGS, \
464 "Use symbolic register names"}, \
465 {"no-rnames", -MASK_NAME_REGS, \
466 "Don't use symbolic register names"}, \
467 {"gpOPT", MASK_GPOPT, \
468 "Use GP relative sdata/sbss sections"}, \
469 {"gpopt", MASK_GPOPT, \
470 "Use GP relative sdata/sbss sections"}, \
471 {"no-gpOPT", -MASK_GPOPT, \
472 "Don't use GP relative sdata/sbss sections"}, \
473 {"no-gpopt", -MASK_GPOPT, \
474 "Don't use GP relative sdata/sbss sections"}, \
475 {"stats", MASK_STATS, \
476 "Output compiler statistics"}, \
477 {"no-stats", -MASK_STATS, \
478 "Don't output compiler statistics"}, \
479 {"memcpy", MASK_MEMCPY, \
480 "Don't optimize block moves"}, \
481 {"no-memcpy", -MASK_MEMCPY, \
482 "Optimize block moves"}, \
483 {"mips-tfile", MASK_MIPS_TFILE, \
484 "Use mips-tfile asm postpass"}, \
485 {"no-mips-tfile", -MASK_MIPS_TFILE, \
486 "Don't use mips-tfile asm postpass"}, \
487 {"soft-float", MASK_SOFT_FLOAT, \
488 "Use software floating point"}, \
489 {"hard-float", -MASK_SOFT_FLOAT, \
490 "Use hardware floating point"}, \
491 {"fp64", MASK_FLOAT64, \
492 "Use 64-bit FP registers"}, \
493 {"fp32", -MASK_FLOAT64, \
494 "Use 32-bit FP registers"}, \
495 {"gp64", MASK_64BIT, \
496 "Use 64-bit general registers"}, \
497 {"gp32", -MASK_64BIT, \
498 "Use 32-bit general registers"}, \
499 {"abicalls", MASK_ABICALLS, \
501 {"no-abicalls", -MASK_ABICALLS, \
502 "Don't use Irix PIC"}, \
503 {"half-pic", MASK_HALF_PIC, \
505 {"no-half-pic", -MASK_HALF_PIC, \
506 "Don't use OSF PIC"}, \
507 {"long-calls", MASK_LONG_CALLS, \
508 "Use indirect calls"}, \
509 {"no-long-calls", -MASK_LONG_CALLS, \
510 "Don't use indirect calls"}, \
511 {"embedded-pic", MASK_EMBEDDED_PIC, \
512 "Use embedded PIC"}, \
513 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
514 "Don't use embedded PIC"}, \
515 {"embedded-data", MASK_EMBEDDED_DATA, \
516 "Use ROM instead of RAM"}, \
517 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
518 "Don't use ROM instead of RAM"}, \
519 {"eb", MASK_BIG_ENDIAN, \
520 "Use big-endian byte order"}, \
521 {"el", -MASK_BIG_ENDIAN, \
522 "Use little-endian byte order"}, \
523 {"single-float", MASK_SINGLE_FLOAT, \
524 "Use single (32-bit) FP only"}, \
525 {"double-float", -MASK_SINGLE_FLOAT, \
526 "Don't use single (32-bit) FP only"}, \
528 "Use multiply accumulate"}, \
529 {"no-mad", -MASK_MAD, \
530 "Don't use multiply accumulate"}, \
531 {"fix4300", MASK_4300_MUL_FIX, \
532 "Work around early 4300 hardware bug"}, \
533 {"no-fix4300", -MASK_4300_MUL_FIX, \
534 "Don't work around early 4300 hardware bug"}, \
535 {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
536 "Optimize for 4650"}, \
537 {"3900", MASK_MIPS3900, \
538 "Optimize for 3900"}, \
539 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
540 "Trap on integer divide by zero"}, \
541 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
542 "Don't trap on integer divide by zero"}, \
543 {"check-range-division",MASK_CHECK_RANGE_DIV, \
544 "Trap on integer divide overflow"}, \
545 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
546 "Don't trap on integer divide overflow"}, \
547 {"debug", MASK_DEBUG, \
549 {"debuga", MASK_DEBUG_A, \
551 {"debugb", MASK_DEBUG_B, \
553 {"debugc", MASK_DEBUG_C, \
555 {"debugd", MASK_DEBUG_D, \
557 {"debuge", MASK_DEBUG_E, \
559 {"debugf", MASK_DEBUG_F, \
561 {"debugg", MASK_DEBUG_G, \
563 {"debugh", MASK_DEBUG_H, \
565 {"debugi", MASK_DEBUG_I, \
567 {"", (TARGET_DEFAULT \
568 | TARGET_CPU_DEFAULT \
569 | TARGET_ENDIAN_DEFAULT), \
573 /* Default target_flags if no switches are specified */
575 #ifndef TARGET_DEFAULT
576 #define TARGET_DEFAULT 0
579 #ifndef TARGET_CPU_DEFAULT
580 #define TARGET_CPU_DEFAULT 0
583 #ifndef TARGET_ENDIAN_DEFAULT
585 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
587 #define TARGET_ENDIAN_DEFAULT 0
591 #ifndef MULTILIB_DEFAULTS
592 #if TARGET_ENDIAN_DEFAULT == 0
593 #define MULTILIB_DEFAULTS { "EL", "mips1" }
595 #define MULTILIB_DEFAULTS { "EB", "mips1" }
599 /* We must pass -EL to the linker by default for little endian embedded
600 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
601 linker will default to using big-endian output files. The OUTPUT_FORMAT
602 line must be in the linker script, otherwise -EB/-EL will not work. */
604 #ifndef LINKER_ENDIAN_SPEC
605 #if TARGET_ENDIAN_DEFAULT == 0
606 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
608 #define LINKER_ENDIAN_SPEC ""
612 /* This macro is similar to `TARGET_SWITCHES' but defines names of
613 command options that have values. Its definition is an
614 initializer with a subgrouping for each command option.
616 Each subgrouping contains a string constant, that defines the
617 fixed part of the option name, and the address of a variable.
618 The variable, type `char *', is set to the variable part of the
619 given option if the fixed part matches. The actual option name
620 is made by appending `-m' to the specified name.
622 Here is an example which defines `-mshort-data-NUMBER'. If the
623 given option is `-mshort-data-512', the variable `m88k_short_data'
624 will be set to the string `"512"'.
626 extern char *m88k_short_data;
627 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
629 #define TARGET_OPTIONS \
631 SUBTARGET_TARGET_OPTIONS \
632 { "cpu=", &mips_cpu_string, \
633 "Specify CPU for scheduling purposes"}, \
634 { "ips", &mips_isa_string, \
635 "Specify MIPS ISA"}, \
636 { "entry", &mips_entry_string, \
637 "Use mips16 entry/exit psuedo ops"}, \
638 { "no-mips16", &mips_no_mips16_string, \
639 "Don't use MIPS16 instructions"}, \
640 { "explicit-type-size", &mips_explicit_type_size_string, \
644 /* This is meant to be redefined in the host dependent files. */
645 #define SUBTARGET_TARGET_OPTIONS
647 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
649 /* Generate three-operand multiply instructions for both SImode and DImode. */
650 #define GENERATE_MULT3 (TARGET_MIPS3900 \
653 /* Macros to decide whether certain features are available or not,
654 depending on the instruction set architecture level. */
656 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
657 #define HAVE_SQRT_P() (mips_isa >= 2)
659 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
660 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
661 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
662 target_flags, and -mgp64 sets MASK_64BIT.
664 Setting MASK_64BIT in target_flags will cause gcc to assume that
665 registers are 64 bits wide. int, long and void * will be 32 bit;
666 this may be changed with -mint64 or -mlong64.
668 The gen* programs link code that refers to MASK_64BIT. They don't
669 actually use the information in target_flags; they just refer to
672 /* Switch Recognition by gcc.c. Add -G xx support */
674 #ifdef SWITCH_TAKES_ARG
675 #undef SWITCH_TAKES_ARG
678 #define SWITCH_TAKES_ARG(CHAR) \
679 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
681 /* Sometimes certain combinations of command options do not make sense
682 on a particular target machine. You can define a macro
683 `OVERRIDE_OPTIONS' to take account of this. This macro, if
684 defined, is executed once just after all the command options have
687 On the MIPS, it is used to handle -G. We also use it to set up all
688 of the tables referenced in the other macros. */
690 #define OVERRIDE_OPTIONS override_options ()
692 /* Zero or more C statements that may conditionally modify two
693 variables `fixed_regs' and `call_used_regs' (both of type `char
694 []') after they have been initialized from the two preceding
697 This is necessary in case the fixed or call-clobbered registers
698 depend on target flags.
700 You need not define this macro if it has no work to do.
702 If the usage of an entire class of registers depends on the target
703 flags, you may indicate this to GCC by using this macro to modify
704 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
705 the classes which should not be used by GCC. Also define the macro
706 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
707 letter for a class that shouldn't be used.
709 (However, if this class is not included in `GENERAL_REGS' and all
710 of the insn patterns whose constraints permit this class are
711 controlled by target switches, then GCC will automatically avoid
712 using these registers when the target switches are opposed to
715 #define CONDITIONAL_REGISTER_USAGE \
718 if (!TARGET_HARD_FLOAT) \
722 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
723 fixed_regs[regno] = call_used_regs[regno] = 1; \
724 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
725 fixed_regs[regno] = call_used_regs[regno] = 1; \
727 else if (mips_isa < 4) \
731 /* We only have a single condition code register. We \
732 implement this by hiding all the condition code registers, \
733 and generating RTL that refers directly to ST_REG_FIRST. */ \
734 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
735 fixed_regs[regno] = call_used_regs[regno] = 1; \
737 /* In mips16 mode, we permit the $t temporary registers to be used \
738 for reload. We prohibit the unused $s registers, since they \
739 are caller saved, and saving them via a mips16 register would \
740 probably waste more time than just reloading the value. */ \
743 fixed_regs[18] = call_used_regs[18] = 1; \
744 fixed_regs[19] = call_used_regs[19] = 1; \
745 fixed_regs[20] = call_used_regs[20] = 1; \
746 fixed_regs[21] = call_used_regs[21] = 1; \
747 fixed_regs[22] = call_used_regs[22] = 1; \
748 fixed_regs[23] = call_used_regs[23] = 1; \
749 fixed_regs[26] = call_used_regs[26] = 1; \
750 fixed_regs[27] = call_used_regs[27] = 1; \
751 fixed_regs[30] = call_used_regs[30] = 1; \
753 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
757 /* This is meant to be redefined in the host dependent files. */
758 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
760 /* Show we can debug even without a frame pointer. */
761 #define CAN_DEBUG_WITHOUT_FP
763 /* Complain about missing specs and predefines that should be defined in each
764 of the target tm files to override the defaults. This is mostly a place-
765 holder until I can get each of the files updated [mm]. */
767 #if defined(OSF_OS) \
768 || defined(DECSTATION) \
769 || defined(SGI_TARGET) \
770 || defined(MIPS_NEWS) \
771 || defined(MIPS_SYSV) \
772 || defined(MIPS_SVR4) \
773 || defined(MIPS_BSD43)
775 #ifndef CPP_PREDEFINES
776 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
780 #error "Define LIB_SPEC in the appropriate tm.h file"
783 #ifndef STARTFILE_SPEC
784 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
788 #error "Define MACHINE_TYPE in the appropriate tm.h file"
792 /* Tell collect what flags to pass to nm. */
794 #define NM_FLAGS "-Bn"
798 /* Names to predefine in the preprocessor for this target machine. */
800 #ifndef CPP_PREDEFINES
801 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
802 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
803 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
806 /* Assembler specs. */
808 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
811 #define MIPS_AS_ASM_SPEC "\
812 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
813 %{pipe: %e-pipe is not supported.} \
814 %{K} %(subtarget_mips_as_asm_spec)"
816 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
817 rather than gas. It may be overridden by subtargets. */
819 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
820 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
823 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
826 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
828 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
829 GAS_ASM_SPEC as the default, depending upon the value of
832 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
835 #define TARGET_ASM_SPEC "\
836 %{mmips-as: %(mips_as_asm_spec)} \
837 %{!mmips-as: %(gas_asm_spec)}"
841 #define TARGET_ASM_SPEC "\
842 %{!mgas: %(mips_as_asm_spec)} \
843 %{mgas: %(gas_asm_spec)}"
847 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
848 to the assembler. It may be overridden by subtargets. */
849 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
850 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
852 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
855 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
856 the assembler. It may be overridden by subtargets. */
857 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
858 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
859 %{g} %{g0} %{g1} %{g2} %{g3} \
860 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
861 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
862 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
863 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
866 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
867 overridden by subtargets. */
869 #ifndef SUBTARGET_ASM_SPEC
870 #define SUBTARGET_ASM_SPEC ""
873 /* ASM_SPEC is the set of arguments to pass to the assembler. */
876 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
877 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
878 %(subtarget_asm_optimizing_spec) \
879 %(subtarget_asm_debugging_spec) \
881 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
883 %(subtarget_asm_spec)"
885 /* Specify to run a post-processor, mips-tfile after the assembler
886 has run to stuff the mips debug information into the object file.
887 This is needed because the $#!%^ MIPS assembler provides no way
888 of specifying such information in the assembly file. If we are
889 cross compiling, disable mips-tfile unless the user specifies
892 #ifndef ASM_FINAL_SPEC
893 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
895 #define ASM_FINAL_SPEC "\
896 %{mmips-as: %{!mno-mips-tfile: \
897 \n mips-tfile %{v*: -v} \
899 %{!K: %{save-temps: -I %b.o~}} \
900 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
901 %{.s:%i} %{!.s:%g.s}}}"
905 #define ASM_FINAL_SPEC "\
906 %{!mgas: %{!mno-mips-tfile: \
907 \n mips-tfile %{v*: -v} \
909 %{!K: %{save-temps: -I %b.o~}} \
910 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
911 %{.s:%i} %{!.s:%g.s}}}"
914 #endif /* ASM_FINAL_SPEC */
916 /* Redefinition of libraries used. Mips doesn't support normal
917 UNIX style profiling via calling _mcount. It does offer
918 profiling that samples the PC, so do what we can... */
921 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
924 /* Extra switches sometimes passed to the linker. */
925 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
926 will interpret it as a -b option. */
930 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
931 %{bestGnum} %{shared} %{non_shared} \
932 %(linker_endian_spec)"
933 #endif /* LINK_SPEC defined */
935 /* Specs for the compiler proper */
937 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
938 overridden by subtargets. */
939 #ifndef SUBTARGET_CC1_SPEC
940 #define SUBTARGET_CC1_SPEC ""
943 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
947 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
948 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
949 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
950 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
951 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
952 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
953 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
954 %{m4650:-mcpu=r4650} \
955 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
956 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
957 %{pic-none: -mno-half-pic} \
958 %{pic-lib: -mhalf-pic} \
959 %{pic-extern: -mhalf-pic} \
960 %{pic-calls: -mhalf-pic} \
962 %(subtarget_cc1_spec) "
965 /* Preprocessor specs. */
967 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
968 be overridden by subtargets. */
970 #ifndef SUBTARGET_CPP_SIZE_SPEC
971 #define SUBTARGET_CPP_SIZE_SPEC "\
972 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
973 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
976 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
977 overridden by subtargets. */
978 #ifndef SUBTARGET_CPP_SPEC
979 #define SUBTARGET_CPP_SPEC ""
982 /* If we're using 64bit longs, then we have to define __LONG_MAX__
983 correctly. Similarly for 64bit ints and __INT_MAX__. */
984 #ifndef LONG_MAX_SPEC
985 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
986 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
988 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
992 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
996 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
997 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
998 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
999 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1000 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1001 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1002 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
1003 %(subtarget_cpp_size_spec) \
1004 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1005 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1006 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1007 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1008 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1009 %{msoft-float:-D__mips_soft_float} \
1010 %{mabi=eabi:-D__mips_eabi} \
1011 %{mips16:%{!mno-mips16:-D__mips16}} \
1012 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1013 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1015 %(subtarget_cpp_spec) "
1018 /* This macro defines names of additional specifications to put in the specs
1019 that can be used in various specifications like CC1_SPEC. Its definition
1020 is an initializer with a subgrouping for each command option.
1022 Each subgrouping contains a string constant, that defines the
1023 specification name, and a string constant that used by the GNU CC driver
1026 Do not define this macro if it does not need to do anything. */
1028 #define EXTRA_SPECS \
1029 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1030 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1031 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1032 { "long_max_spec", LONG_MAX_SPEC }, \
1033 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1034 { "gas_asm_spec", GAS_ASM_SPEC }, \
1035 { "target_asm_spec", TARGET_ASM_SPEC }, \
1036 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1037 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1038 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1039 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1040 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
1041 SUBTARGET_EXTRA_SPECS
1043 #ifndef SUBTARGET_EXTRA_SPECS
1044 #define SUBTARGET_EXTRA_SPECS
1047 /* If defined, this macro is an additional prefix to try after
1048 `STANDARD_EXEC_PREFIX'. */
1050 #ifndef MD_EXEC_PREFIX
1051 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1054 #ifndef MD_STARTFILE_PREFIX
1055 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1059 /* Print subsidiary information on the compiler version in use. */
1061 #define MIPS_VERSION "[AL 1.1, MM 40]"
1063 #ifndef MACHINE_TYPE
1064 #define MACHINE_TYPE "BSD Mips"
1067 #ifndef TARGET_VERSION_INTERNAL
1068 #define TARGET_VERSION_INTERNAL(STREAM) \
1069 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1072 #ifndef TARGET_VERSION
1073 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1077 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1078 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1079 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1081 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1082 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1085 /* By default, turn on GDB extensions. */
1086 #define DEFAULT_GDB_EXTENSIONS 1
1088 /* If we are passing smuggling stabs through the MIPS ECOFF object
1089 format, put a comment in front of the .stab<x> operation so
1090 that the MIPS assembler does not choke. The mips-tfile program
1091 will correctly put the stab into the object file. */
1093 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1094 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1095 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1097 /* Local compiler-generated symbols must have a prefix that the assembler
1098 understands. By default, this is $, although some targets (e.g.,
1099 NetBSD-ELF) need to override this. */
1101 #ifndef LOCAL_LABEL_PREFIX
1102 #define LOCAL_LABEL_PREFIX "$"
1105 /* By default on the mips, external symbols do not have an underscore
1106 prepended, but some targets (e.g., NetBSD) require this. */
1108 #ifndef USER_LABEL_PREFIX
1109 #define USER_LABEL_PREFIX ""
1112 /* Forward references to tags are allowed. */
1113 #define SDB_ALLOW_FORWARD_REFERENCES
1115 /* Unknown tags are also allowed. */
1116 #define SDB_ALLOW_UNKNOWN_REFERENCES
1118 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1119 since the length can run past this up to a continuation point. */
1120 #define DBX_CONTIN_LENGTH 1500
1122 /* How to renumber registers for dbx and gdb. */
1123 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1125 /* The mapping from gcc register number to DWARF 2 CFA column number.
1126 This mapping does not allow for tracking register 0, since SGI's broken
1127 dwarf reader thinks column 0 is used for the frame address, but since
1128 register 0 is fixed this is not a problem. */
1129 #define DWARF_FRAME_REGNUM(REG) \
1130 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1132 /* The DWARF 2 CFA column which tracks the return address. */
1133 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1135 /* Before the prologue, RA lives in r31. */
1136 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
1138 /* Overrides for the COFF debug format. */
1139 #define PUT_SDB_SCL(a) \
1141 extern FILE *asm_out_text_file; \
1142 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1145 #define PUT_SDB_INT_VAL(a) \
1147 extern FILE *asm_out_text_file; \
1148 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1151 #define PUT_SDB_VAL(a) \
1153 extern FILE *asm_out_text_file; \
1154 fputs ("\t.val\t", asm_out_text_file); \
1155 output_addr_const (asm_out_text_file, (a)); \
1156 fputc (';', asm_out_text_file); \
1159 #define PUT_SDB_DEF(a) \
1161 extern FILE *asm_out_text_file; \
1162 fprintf (asm_out_text_file, "\t%s.def\t", \
1163 (TARGET_GAS) ? "" : "#"); \
1164 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1165 fputc (';', asm_out_text_file); \
1168 #define PUT_SDB_PLAIN_DEF(a) \
1170 extern FILE *asm_out_text_file; \
1171 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1172 (TARGET_GAS) ? "" : "#", (a)); \
1175 #define PUT_SDB_ENDEF \
1177 extern FILE *asm_out_text_file; \
1178 fprintf (asm_out_text_file, "\t.endef\n"); \
1181 #define PUT_SDB_TYPE(a) \
1183 extern FILE *asm_out_text_file; \
1184 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1187 #define PUT_SDB_SIZE(a) \
1189 extern FILE *asm_out_text_file; \
1190 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1193 #define PUT_SDB_DIM(a) \
1195 extern FILE *asm_out_text_file; \
1196 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1199 #ifndef PUT_SDB_START_DIM
1200 #define PUT_SDB_START_DIM \
1202 extern FILE *asm_out_text_file; \
1203 fprintf (asm_out_text_file, "\t.dim\t"); \
1207 #ifndef PUT_SDB_NEXT_DIM
1208 #define PUT_SDB_NEXT_DIM(a) \
1210 extern FILE *asm_out_text_file; \
1211 fprintf (asm_out_text_file, "%d,", a); \
1215 #ifndef PUT_SDB_LAST_DIM
1216 #define PUT_SDB_LAST_DIM(a) \
1218 extern FILE *asm_out_text_file; \
1219 fprintf (asm_out_text_file, "%d;", a); \
1223 #define PUT_SDB_TAG(a) \
1225 extern FILE *asm_out_text_file; \
1226 fprintf (asm_out_text_file, "\t.tag\t"); \
1227 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1228 fputc (';', asm_out_text_file); \
1231 /* For block start and end, we create labels, so that
1232 later we can figure out where the correct offset is.
1233 The normal .ent/.end serve well enough for functions,
1234 so those are just commented out. */
1236 #define PUT_SDB_BLOCK_START(LINE) \
1238 extern FILE *asm_out_text_file; \
1239 fprintf (asm_out_text_file, \
1240 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1241 LOCAL_LABEL_PREFIX, \
1243 (TARGET_GAS) ? "" : "#", \
1244 LOCAL_LABEL_PREFIX, \
1247 sdb_label_count++; \
1250 #define PUT_SDB_BLOCK_END(LINE) \
1252 extern FILE *asm_out_text_file; \
1253 fprintf (asm_out_text_file, \
1254 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1255 LOCAL_LABEL_PREFIX, \
1257 (TARGET_GAS) ? "" : "#", \
1258 LOCAL_LABEL_PREFIX, \
1261 sdb_label_count++; \
1264 #define PUT_SDB_FUNCTION_START(LINE)
1266 #define PUT_SDB_FUNCTION_END(LINE) \
1268 extern FILE *asm_out_text_file; \
1269 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1272 #define PUT_SDB_EPILOGUE_END(NAME)
1274 #define PUT_SDB_SRC_FILE(FILENAME) \
1276 extern FILE *asm_out_text_file; \
1277 output_file_directive (asm_out_text_file, (FILENAME)); \
1280 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1281 sprintf ((BUFFER), ".%dfake", (NUMBER));
1283 /* Correct the offset of automatic variables and arguments. Note that
1284 the MIPS debug format wants all automatic variables and arguments
1285 to be in terms of the virtual frame pointer (stack pointer before
1286 any adjustment in the function), while the MIPS 3.0 linker wants
1287 the frame pointer to be the stack pointer after the initial
1290 #define DEBUGGER_AUTO_OFFSET(X) \
1291 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1292 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1293 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1295 /* Tell collect that the object format is ECOFF */
1296 #ifndef OBJECT_FORMAT_ROSE
1297 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1298 #define EXTENDED_COFF /* ECOFF, not normal coff */
1301 #if 0 /* These definitions normally have no effect because
1302 MIPS systems define USE_COLLECT2, so
1303 assemble_constructor does nothing anyway. */
1305 /* Don't use the default definitions, because we don't have gld.
1306 Also, we don't want stabs when generating ECOFF output.
1307 Instead we depend on collect to handle these. */
1309 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1310 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1314 /* Target machine storage layout */
1316 /* Define in order to support both big and little endian float formats
1317 in the same gcc binary. */
1318 #define REAL_ARITHMETIC
1320 /* Define this if most significant bit is lowest numbered
1321 in instructions that operate on numbered bit-fields.
1323 #define BITS_BIG_ENDIAN 0
1325 /* Define this if most significant byte of a word is the lowest numbered. */
1326 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1328 /* Define this if most significant word of a multiword number is the lowest. */
1329 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1331 /* Define this to set the endianness to use in libgcc2.c, which can
1332 not depend on target_flags. */
1333 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1334 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1336 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1339 /* Number of bits in an addressable storage unit */
1340 #define BITS_PER_UNIT 8
1342 /* Width in bits of a "word", which is the contents of a machine register.
1343 Note that this is not necessarily the width of data type `int';
1344 if using 16-bit ints on a 68000, this would still be 32.
1345 But on a machine with 16-bit registers, this would be 16. */
1346 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1347 #define MAX_BITS_PER_WORD 64
1349 /* Width of a word, in units (bytes). */
1350 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1351 #define MIN_UNITS_PER_WORD 4
1353 /* For MIPS, width of a floating point register. */
1354 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1356 /* A C expression for the size in bits of the type `int' on the
1357 target machine. If you don't define this, the default is one
1359 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1360 #define MAX_INT_TYPE_SIZE 64
1362 /* Tell the preprocessor the maximum size of wchar_t. */
1363 #ifndef MAX_WCHAR_TYPE_SIZE
1364 #ifndef WCHAR_TYPE_SIZE
1365 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1369 /* A C expression for the size in bits of the type `short' on the
1370 target machine. If you don't define this, the default is half a
1371 word. (If this would be less than one storage unit, it is
1372 rounded up to one unit.) */
1373 #define SHORT_TYPE_SIZE 16
1375 /* A C expression for the size in bits of the type `long' on the
1376 target machine. If you don't define this, the default is one
1378 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1379 #define MAX_LONG_TYPE_SIZE 64
1381 /* A C expression for the size in bits of the type `long long' on the
1382 target machine. If you don't define this, the default is two
1384 #define LONG_LONG_TYPE_SIZE 64
1386 /* A C expression for the size in bits of the type `char' on the
1387 target machine. If you don't define this, the default is one
1388 quarter of a word. (If this would be less than one storage unit,
1389 it is rounded up to one unit.) */
1390 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1392 /* A C expression for the size in bits of the type `float' on the
1393 target machine. If you don't define this, the default is one
1395 #define FLOAT_TYPE_SIZE 32
1397 /* A C expression for the size in bits of the type `double' on the
1398 target machine. If you don't define this, the default is two
1400 #define DOUBLE_TYPE_SIZE 64
1402 /* A C expression for the size in bits of the type `long double' on
1403 the target machine. If you don't define this, the default is two
1405 #define LONG_DOUBLE_TYPE_SIZE 64
1407 /* Width in bits of a pointer.
1408 See also the macro `Pmode' defined below. */
1409 #ifndef POINTER_SIZE
1410 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1413 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1414 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1416 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1417 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1419 /* Allocation boundary (in *bits*) for the code of a function. */
1420 #define FUNCTION_BOUNDARY 32
1422 /* Alignment of field after `int : 0' in a structure. */
1423 #define EMPTY_FIELD_BOUNDARY 32
1425 /* Every structure's size must be a multiple of this. */
1426 /* 8 is observed right on a DECstation and on riscos 4.02. */
1427 #define STRUCTURE_SIZE_BOUNDARY 8
1429 /* There is no point aligning anything to a rounder boundary than this. */
1430 #define BIGGEST_ALIGNMENT 64
1432 /* Set this nonzero if move instructions will actually fail to work
1433 when given unaligned data. */
1434 #define STRICT_ALIGNMENT 1
1436 /* Define this if you wish to imitate the way many other C compilers
1437 handle alignment of bitfields and the structures that contain
1440 The behavior is that the type written for a bitfield (`int',
1441 `short', or other integer type) imposes an alignment for the
1442 entire structure, as if the structure really did contain an
1443 ordinary field of that type. In addition, the bitfield is placed
1444 within the structure so that it would fit within such a field,
1445 not crossing a boundary for it.
1447 Thus, on most machines, a bitfield whose type is written as `int'
1448 would not cross a four-byte boundary, and would force four-byte
1449 alignment for the whole structure. (The alignment used may not
1450 be four bytes; it is controlled by the other alignment
1453 If the macro is defined, its definition should be a C expression;
1454 a nonzero value for the expression enables this behavior. */
1456 #define PCC_BITFIELD_TYPE_MATTERS 1
1458 /* If defined, a C expression to compute the alignment given to a
1459 constant that is being placed in memory. CONSTANT is the constant
1460 and ALIGN is the alignment that the object would ordinarily have.
1461 The value of this macro is used instead of that alignment to align
1464 If this macro is not defined, then ALIGN is used.
1466 The typical use of this macro is to increase alignment for string
1467 constants to be word aligned so that `strcpy' calls that copy
1468 constants can be done inline. */
1470 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1471 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1472 && (ALIGN) < BITS_PER_WORD \
1476 /* If defined, a C expression to compute the alignment for a static
1477 variable. TYPE is the data type, and ALIGN is the alignment that
1478 the object would ordinarily have. The value of this macro is used
1479 instead of that alignment to align the object.
1481 If this macro is not defined, then ALIGN is used.
1483 One use of this macro is to increase alignment of medium-size
1484 data to make it all fit in fewer cache lines. Another is to
1485 cause character arrays to be word-aligned so that `strcpy' calls
1486 that copy constants to character arrays can be done inline. */
1488 #undef DATA_ALIGNMENT
1489 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1490 ((((ALIGN) < BITS_PER_WORD) \
1491 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1492 || TREE_CODE (TYPE) == UNION_TYPE \
1493 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1495 /* Define this macro if an argument declared as `char' or `short' in a
1496 prototype should actually be passed as an `int'. In addition to
1497 avoiding errors in certain cases of mismatch, it also makes for
1498 better code on certain machines. */
1500 #define PROMOTE_PROTOTYPES
1502 /* Define if operations between registers always perform the operation
1503 on the full register even if a narrower mode is specified. */
1504 #define WORD_REGISTER_OPERATIONS
1506 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1507 will either zero-extend or sign-extend. The value of this macro should
1508 be the code that says which one of the two operations is implicitly
1511 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1512 moves. All other referces are zero extended. */
1513 #define LOAD_EXTEND_OP(MODE) \
1514 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1515 ? SIGN_EXTEND : ZERO_EXTEND)
1517 /* Define this macro if it is advisable to hold scalars in registers
1518 in a wider mode than that declared by the program. In such cases,
1519 the value is constrained to be within the bounds of the declared
1520 type, but kept valid in the wider mode. The signedness of the
1521 extension may differ from that of the type.
1523 We promote any value smaller than SImode up to SImode. We don't
1524 want to promote to DImode when in 64 bit mode, because that would
1525 prevent us from using the faster SImode multiply and divide
1528 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1529 if (GET_MODE_CLASS (MODE) == MODE_INT \
1530 && GET_MODE_SIZE (MODE) < 4) \
1533 /* Define this if function arguments should also be promoted using the above
1536 #define PROMOTE_FUNCTION_ARGS
1538 /* Likewise, if the function return value is promoted. */
1540 #define PROMOTE_FUNCTION_RETURN
1542 /* Standard register usage. */
1544 /* Number of actual hardware registers.
1545 The hardware registers are assigned numbers for the compiler
1546 from 0 to just below FIRST_PSEUDO_REGISTER.
1547 All registers that the compiler knows about must be given numbers,
1548 even those that are not normally considered general registers.
1550 On the Mips, we have 32 integer registers, 32 floating point
1551 registers, 8 condition code registers, and the special registers
1552 hi, lo, hilo, and rap. The 8 condition code registers are only
1553 used if mips_isa >= 4. The hilo register is only used in 64 bit
1554 mode. It represents a 64 bit value stored as two 32 bit values in
1555 the hi and lo registers; this is the result of the mult
1556 instruction. rap is a pointer to the stack where the return
1557 address reg ($31) was stored. This is needed for C++ exception
1560 #define FIRST_PSEUDO_REGISTER 76
1562 /* 1 for registers that have pervasive standard uses
1563 and are not available for the register allocator.
1565 On the MIPS, see conventions, page D-2 */
1567 #define FIXED_REGISTERS \
1569 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1570 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1577 /* 1 for registers not available across function calls.
1578 These must include the FIXED_REGISTERS and also any
1579 registers that can be used without being saved.
1580 The latter must include the registers where values are returned
1581 and the register where structure-value addresses are passed.
1582 Aside from that, you can include as many other registers as you like. */
1584 #define CALL_USED_REGISTERS \
1586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1587 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1589 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1590 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1594 /* Internal macros to classify a register number as to whether it's a
1595 general purpose register, a floating point register, a
1596 multiply/divide register, or a status register. */
1598 #define GP_REG_FIRST 0
1599 #define GP_REG_LAST 31
1600 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1601 #define GP_DBX_FIRST 0
1603 #define FP_REG_FIRST 32
1604 #define FP_REG_LAST 63
1605 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1606 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1608 #define MD_REG_FIRST 64
1609 #define MD_REG_LAST 66
1610 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1612 #define ST_REG_FIRST 67
1613 #define ST_REG_LAST 74
1614 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1616 #define RAP_REG_NUM 75
1618 #define AT_REGNUM (GP_REG_FIRST + 1)
1619 #define HI_REGNUM (MD_REG_FIRST + 0)
1620 #define LO_REGNUM (MD_REG_FIRST + 1)
1621 #define HILO_REGNUM (MD_REG_FIRST + 2)
1623 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1624 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1625 should be used instead. */
1626 #define FPSW_REGNUM ST_REG_FIRST
1628 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1629 #define M16_REG_P(REGNO) \
1630 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1631 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1632 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1633 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1635 /* Return number of consecutive hard regs needed starting at reg REGNO
1636 to hold something of mode MODE.
1637 This is ordinarily the length in words of a value of mode MODE
1638 but can be less for certain modes in special long registers.
1640 On the MIPS, all general registers are one word long. Except on
1641 the R4000 with the FR bit set, the floating point uses register
1642 pairs, with the second register not being allocable. */
1644 #define HARD_REGNO_NREGS(REGNO, MODE) \
1645 (! FP_REG_P (REGNO) \
1646 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1647 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1649 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1650 MODE. In 32 bit mode, require that DImode and DFmode be in even
1651 registers. For DImode, this makes some of the insns easier to
1652 write, since you don't have to worry about a DImode value in
1653 registers 3 & 4, producing a result in 4 & 5.
1655 To make the code simpler HARD_REGNO_MODE_OK now just references an
1656 array built in override_options. Because machmodes.h is not yet
1657 included before this file is processed, the MODE bound can't be
1660 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1662 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1663 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1665 /* Value is 1 if it is a good idea to tie two pseudo registers
1666 when one has mode MODE1 and one has mode MODE2.
1667 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1668 for any hard reg, then this must be 0 for correct output. */
1669 #define MODES_TIEABLE_P(MODE1, MODE2) \
1670 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1671 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1672 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1673 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1675 /* MIPS pc is not overloaded on a register. */
1676 /* #define PC_REGNUM xx */
1678 /* Register to use for pushing function arguments. */
1679 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1681 /* Offset from the stack pointer to the first available location. Use
1682 the default value zero. */
1683 /* #define STACK_POINTER_OFFSET 0 */
1685 /* Base register for access to local variables of the function. We
1686 pretend that the frame pointer is $1, and then eliminate it to
1687 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1688 a fixed register, and will not be used for anything else. */
1689 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1691 /* Temporary scratch register for use by the assembler. */
1692 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1694 /* $30 is not available on the mips16, so we use $17 as the frame
1696 #define HARD_FRAME_POINTER_REGNUM \
1697 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1699 /* Value should be nonzero if functions must have frame pointers.
1700 Zero means the frame pointer need not be set up (and parms
1701 may be accessed via the stack pointer) in functions that seem suitable.
1702 This is computed in `reload', in reload1.c. */
1703 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1705 /* Base register for access to arguments of the function. */
1706 #define ARG_POINTER_REGNUM GP_REG_FIRST
1708 /* Fake register that holds the address on the stack of the
1709 current function's return address. */
1710 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1712 /* Register in which static-chain is passed to a function. */
1713 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1715 /* If the structure value address is passed in a register, then
1716 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1717 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1719 /* If the structure value address is not passed in a register, define
1720 `STRUCT_VALUE' as an expression returning an RTX for the place
1721 where the address is passed. If it returns 0, the address is
1722 passed as an "invisible" first argument. */
1723 #define STRUCT_VALUE 0
1725 /* Mips registers used in prologue/epilogue code when the stack frame
1726 is larger than 32K bytes. These registers must come from the
1727 scratch register set, and not used for passing and returning
1728 arguments and any other information used in the calling sequence
1729 (such as pic). Must start at 12, since t0/t3 are parameter passing
1730 registers in the 64 bit ABI. */
1732 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1733 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1735 /* Define this macro if it is as good or better to call a constant
1736 function address than to call an address kept in a register. */
1737 #define NO_FUNCTION_CSE 1
1739 /* Define this macro if it is as good or better for a function to
1740 call itself with an explicit address than to call an address
1741 kept in a register. */
1742 #define NO_RECURSIVE_FUNCTION_CSE 1
1744 /* The register number of the register used to address a table of
1745 static data addresses in memory. In some cases this register is
1746 defined by a processor's "application binary interface" (ABI).
1747 When this macro is defined, RTL is generated for this register
1748 once, as with the stack pointer and frame pointer registers. If
1749 this macro is not defined, it is up to the machine-dependent
1750 files to allocate such a register (if necessary). */
1751 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1753 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1755 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1756 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1757 isn't always called for static inline functions. */
1758 #define INIT_EXPANDERS \
1760 embedded_pic_fnaddr_rtx = NULL; \
1761 mips16_gp_pseudo_rtx = NULL; \
1764 /* Define the classes of registers for register constraints in the
1765 machine description. Also define ranges of constants.
1767 One of the classes must always be named ALL_REGS and include all hard regs.
1768 If there is more than one class, another class must be named NO_REGS
1769 and contain no registers.
1771 The name GENERAL_REGS must be the name of a class (or an alias for
1772 another name such as ALL_REGS). This is the class of registers
1773 that is allowed by "g" or "r" in a register constraint.
1774 Also, registers outside this class are allocated only when
1775 instructions express preferences for them.
1777 The classes must be numbered in nondecreasing order; that is,
1778 a larger-numbered class must never be contained completely
1779 in a smaller-numbered class.
1781 For any two classes, it is very desirable that there be another
1782 class that represents their union. */
1786 NO_REGS, /* no registers in set */
1787 M16_NA_REGS, /* mips16 regs not used to pass args */
1788 M16_REGS, /* mips16 directly accessible registers */
1789 T_REG, /* mips16 T register ($24) */
1790 M16_T_REGS, /* mips16 registers plus T register */
1791 GR_REGS, /* integer registers */
1792 FP_REGS, /* floating point registers */
1793 HI_REG, /* hi register */
1794 LO_REG, /* lo register */
1795 HILO_REG, /* hilo register pair for 64 bit mode mult */
1796 MD_REGS, /* multiply/divide registers (hi/lo) */
1797 HI_AND_GR_REGS, /* union classes */
1800 ST_REGS, /* status registers (fp status) */
1801 ALL_REGS, /* all registers */
1802 LIM_REG_CLASSES /* max value + 1 */
1805 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1807 #define GENERAL_REGS GR_REGS
1809 /* An initializer containing the names of the register classes as C
1810 string constants. These names are used in writing some of the
1813 #define REG_CLASS_NAMES \
1828 "HILO_AND_GR_REGS", \
1833 /* An initializer containing the contents of the register classes,
1834 as integers which are bit masks. The Nth integer specifies the
1835 contents of class N. The way the integer MASK is interpreted is
1836 that register R is in the class if `MASK & (1 << R)' is 1.
1838 When the machine has more than 32 registers, an integer does not
1839 suffice. Then the integers are replaced by sub-initializers,
1840 braced groupings containing several integers. Each
1841 sub-initializer must be suitable as an initializer for the type
1842 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1844 #define REG_CLASS_CONTENTS \
1846 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1847 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1848 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1849 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1850 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1851 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1852 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1853 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1854 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1855 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1856 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1857 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1858 { 0xffffffff, 0x00000000, 0x00000002 }, \
1859 { 0xffffffff, 0x00000000, 0x00000004 }, \
1860 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1861 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1865 /* A C expression whose value is a register class containing hard
1866 register REGNO. In general there is more that one such class;
1867 choose a class which is "minimal", meaning that no smaller class
1868 also contains the register. */
1870 extern enum reg_class mips_regno_to_class[];
1872 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1874 /* A macro whose definition is the name of the class to which a
1875 valid base register must belong. A base register is one used in
1876 an address which is the register value plus a displacement. */
1878 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1880 /* A macro whose definition is the name of the class to which a
1881 valid index register must belong. An index register is one used
1882 in an address where its value is either multiplied by a scale
1883 factor or added to another register (as well as added to a
1886 #define INDEX_REG_CLASS NO_REGS
1888 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1889 registers explicitly used in the rtl to be used as spill registers
1890 but prevents the compiler from extending the lifetime of these
1893 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1895 /* This macro is used later on in the file. */
1896 #define GR_REG_CLASS_P(CLASS) \
1897 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1898 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1900 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1901 is the default value (allocate the registers in numeric order). We
1902 define it just so that we can override it for the mips16 target in
1903 ORDER_REGS_FOR_LOCAL_ALLOC. */
1905 #define REG_ALLOC_ORDER \
1906 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1907 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1908 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1909 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1910 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1913 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1914 to be rearranged based on a particular function. On the mips16, we
1915 want to allocate $24 (T_REG) before other registers for
1916 instructions for which it is possible. */
1918 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1920 /* REGISTER AND CONSTANT CLASSES */
1922 /* Get reg_class from a letter such as appears in the machine
1925 DEFINED REGISTER CLASSES:
1927 'd' General (aka integer) registers
1928 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1929 'y' General registers (in both mips16 and non mips16 mode)
1930 'e' mips16 non argument registers (M16_NA_REGS)
1931 't' mips16 temporary register ($24)
1932 'f' Floating point registers
1935 'x' Multiply/divide registers
1937 'z' FP Status register
1938 'b' All registers */
1940 extern enum reg_class mips_char_to_class[];
1942 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1944 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1945 string can be used to stand for particular ranges of immediate
1946 operands. This macro defines what the ranges are. C is the
1947 letter, and VALUE is a constant value. Return 1 if VALUE is
1948 in the range specified by C. */
1952 `I' is used for the range of constants an arithmetic insn can
1953 actually contain (16 bits signed integers).
1955 `J' is used for the range which is just zero (ie, $r0).
1957 `K' is used for the range of constants a logical insn can actually
1958 contain (16 bit zero-extended integers).
1960 `L' is used for the range of constants that be loaded with lui
1961 (ie, the bottom 16 bits are zero).
1963 `M' is used for the range of constants that take two words to load
1964 (ie, not matched by `I', `K', and `L').
1966 `N' is used for negative 16 bit constants other than -65536.
1968 `O' is a 15 bit signed integer.
1970 `P' is used for positive 16 bit constants. */
1972 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1973 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1975 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1976 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1977 : (C) == 'J' ? ((VALUE) == 0) \
1978 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1979 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1980 && (((VALUE) & ~2147483647) == 0 \
1981 || ((VALUE) & ~2147483647) == ~2147483647)) \
1982 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1983 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1984 && (((VALUE) & 0x0000ffff) != 0 \
1985 || (((VALUE) & ~2147483647) != 0 \
1986 && ((VALUE) & ~2147483647) != ~2147483647))) \
1987 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1988 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1989 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1992 /* Similar, but for floating constants, and defining letters G and H.
1993 Here VALUE is the CONST_DOUBLE rtx itself. */
1997 'G' : Floating point 0 */
1999 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2001 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2003 /* Letters in the range `Q' through `U' may be defined in a
2004 machine-dependent fashion to stand for arbitrary operand types.
2005 The machine description macro `EXTRA_CONSTRAINT' is passed the
2006 operand as its first argument and the constraint letter as its
2009 `Q' is for mips16 GP relative constants
2010 `R' is for memory references which take 1 word for the instruction.
2011 `S' is for references to extern items which are PIC for OSF/rose.
2012 `T' is for memory addresses that can be used to load two words. */
2014 #define EXTRA_CONSTRAINT(OP,CODE) \
2015 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2016 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2017 && mips16_gp_offset_p (OP)) \
2018 : (GET_CODE (OP) != MEM) ? FALSE \
2019 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2020 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2021 && HALF_PIC_ADDRESS_P (OP)) \
2024 /* Given an rtx X being reloaded into a reg required to be
2025 in class CLASS, return the class of reg to actually use.
2026 In general this is just CLASS; but on some machines
2027 in some cases it is preferable to use a more restrictive class. */
2029 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2030 ((CLASS) != ALL_REGS \
2031 ? (! TARGET_MIPS16 \
2033 : ((CLASS) != GR_REGS \
2036 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2037 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2038 ? (TARGET_SOFT_FLOAT \
2039 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2041 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2042 || GET_MODE (X) == VOIDmode) \
2043 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2046 /* Certain machines have the property that some registers cannot be
2047 copied to some other registers without using memory. Define this
2048 macro on those machines to be a C expression that is non-zero if
2049 objects of mode MODE in registers of CLASS1 can only be copied to
2050 registers of class CLASS2 by storing a register of CLASS1 into
2051 memory and loading that memory location into a register of CLASS2.
2053 Do not define this macro if its value would always be zero. */
2055 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2056 ((!TARGET_DEBUG_H_MODE \
2057 && GET_MODE_CLASS (MODE) == MODE_INT \
2058 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2059 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2060 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2061 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2062 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2064 /* The HI and LO registers can only be reloaded via the general
2065 registers. Condition code registers can only be loaded to the
2066 general registers, and from the floating point registers. */
2068 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2069 mips_secondary_reload_class (CLASS, MODE, X, 1)
2070 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2071 mips_secondary_reload_class (CLASS, MODE, X, 0)
2073 /* Not declared above, with the other functions, because enum
2074 reg_class is not declared yet. */
2075 extern enum reg_class mips_secondary_reload_class ();
2077 /* Return the maximum number of consecutive registers
2078 needed to represent mode MODE in a register of class CLASS. */
2080 #define CLASS_UNITS(mode, size) \
2081 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2083 #define CLASS_MAX_NREGS(CLASS, MODE) \
2084 ((CLASS) == FP_REGS \
2086 ? CLASS_UNITS (MODE, 8) \
2087 : 2 * CLASS_UNITS (MODE, 8)) \
2088 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2090 /* If defined, this is a C expression whose value should be
2091 nonzero if the insn INSN has the effect of mysteriously
2092 clobbering the contents of hard register number REGNO. By
2093 "mysterious" we mean that the insn's RTL expression doesn't
2094 describe such an effect.
2096 If this macro is not defined, it means that no insn clobbers
2097 registers mysteriously. This is the usual situation; all else
2098 being equal, it is best for the RTL expression to show all the
2101 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
2104 /* Stack layout; function entry, exit and calling. */
2106 /* Define this if pushing a word on the stack
2107 makes the stack pointer a smaller address. */
2108 #define STACK_GROWS_DOWNWARD
2110 /* Define this if the nominal address of the stack frame
2111 is at the high-address end of the local variables;
2112 that is, each additional local variable allocated
2113 goes at a more negative offset in the frame. */
2114 /* #define FRAME_GROWS_DOWNWARD */
2116 /* Offset within stack frame to start allocating local variables at.
2117 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2118 first local allocated. Otherwise, it is the offset to the BEGINNING
2119 of the first local allocated. */
2120 #define STARTING_FRAME_OFFSET \
2121 (current_function_outgoing_args_size \
2122 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2124 /* Offset from the stack pointer register to an item dynamically
2125 allocated on the stack, e.g., by `alloca'.
2127 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2128 length of the outgoing arguments. The default is correct for most
2129 machines. See `function.c' for details.
2131 The MIPS ABI states that functions which dynamically allocate the
2132 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2133 we are trying to create a second frame pointer to the function, so
2134 allocate some stack space to make it happy.
2136 However, the linker currently complains about linking any code that
2137 dynamically allocates stack space, and there seems to be a bug in
2138 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2141 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2142 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2143 ? 4*UNITS_PER_WORD \
2144 : current_function_outgoing_args_size)
2147 /* The return address for the current frame is in r31 is this is a leaf
2148 function. Otherwise, it is on the stack. It is at a variable offset
2149 from sp/fp/ap, so we define a fake hard register rap which is a
2150 poiner to the return address on the stack. This always gets eliminated
2151 during reload to be either the frame pointer or the stack pointer plus
2154 /* ??? This definition fails for leaf functions. There is currently no
2155 general solution for this problem. */
2157 /* ??? There appears to be no way to get the return address of any previous
2158 frame except by disassembling instructions in the prologue/epilogue.
2159 So currently we support only the current frame. */
2161 #define RETURN_ADDR_RTX(count, frame) \
2163 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2166 /* Structure to be filled in by compute_frame_size with register
2167 save masks, and offsets for the current function. */
2169 struct mips_frame_info
2171 long total_size; /* # bytes that the entire frame takes up */
2172 long var_size; /* # bytes that variables take up */
2173 long args_size; /* # bytes that outgoing arguments take up */
2174 long extra_size; /* # bytes of extra gunk */
2175 int gp_reg_size; /* # bytes needed to store gp regs */
2176 int fp_reg_size; /* # bytes needed to store fp regs */
2177 long mask; /* mask of saved gp registers */
2178 long fmask; /* mask of saved fp registers */
2179 long gp_save_offset; /* offset from vfp to store gp registers */
2180 long fp_save_offset; /* offset from vfp to store fp registers */
2181 long gp_sp_offset; /* offset from new sp to store gp registers */
2182 long fp_sp_offset; /* offset from new sp to store fp registers */
2183 int initialized; /* != 0 if frame size already calculated */
2184 int num_gp; /* number of gp registers saved */
2185 int num_fp; /* number of fp registers saved */
2186 long insns_len; /* length of insns; mips16 only */
2189 extern struct mips_frame_info current_frame_info;
2191 /* If defined, this macro specifies a table of register pairs used to
2192 eliminate unneeded registers that point into the stack frame. If
2193 it is not defined, the only elimination attempted by the compiler
2194 is to replace references to the frame pointer with references to
2197 The definition of this macro is a list of structure
2198 initializations, each of which specifies an original and
2199 replacement register.
2201 On some machines, the position of the argument pointer is not
2202 known until the compilation is completed. In such a case, a
2203 separate hard register must be used for the argument pointer.
2204 This register can be eliminated by replacing it with either the
2205 frame pointer or the argument pointer, depending on whether or not
2206 the frame pointer has been eliminated.
2208 In this case, you might specify:
2209 #define ELIMINABLE_REGS \
2210 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2211 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2212 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2214 Note that the elimination of the argument pointer with the stack
2215 pointer is specified first since that is the preferred elimination.
2217 The eliminations to $17 are only used on the mips16. See the
2218 definition of HARD_FRAME_POINTER_REGNUM. */
2220 #define ELIMINABLE_REGS \
2221 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2222 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2223 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2224 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2225 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2226 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2227 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2228 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2229 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2230 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2232 /* A C expression that returns non-zero if the compiler is allowed to
2233 try to replace register number FROM-REG with register number
2234 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2235 defined, and will usually be the constant 1, since most of the
2236 cases preventing register elimination are things that the compiler
2237 already knows about.
2239 When not in mips16 and mips64, we can always eliminate to the
2240 frame pointer. We can eliminate to the stack pointer unless
2241 a frame pointer is needed. In mips16 mode, we need a frame
2242 pointer for a large frame; otherwise, reload may be unable
2243 to compute the address of a local variable, since there is
2244 no way to add a large constant to the stack pointer
2245 without using a temporary register.
2247 In mips16, for some instructions (eg lwu), we can't eliminate the
2248 frame pointer for the stack pointer. These instructions are
2249 only generated in TARGET_64BIT mode.
2252 #define CAN_ELIMINATE(FROM, TO) \
2253 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2254 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2255 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2256 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2257 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2258 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2259 && (! TARGET_MIPS16 \
2260 || compute_frame_size (get_frame_size ()) < 32768)))))
2262 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2263 specifies the initial difference between the specified pair of
2264 registers. This macro must be defined if `ELIMINABLE_REGS' is
2267 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2268 { compute_frame_size (get_frame_size ()); \
2269 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2270 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2271 (OFFSET) = - current_function_outgoing_args_size; \
2272 else if ((FROM) == FRAME_POINTER_REGNUM) \
2274 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2275 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2276 (OFFSET) = (current_frame_info.total_size \
2277 - current_function_outgoing_args_size \
2278 - ((mips_abi != ABI_32 \
2279 && mips_abi != ABI_O64 \
2280 && mips_abi != ABI_EABI) \
2281 ? current_function_pretend_args_size \
2283 else if ((FROM) == ARG_POINTER_REGNUM) \
2284 (OFFSET) = (current_frame_info.total_size \
2285 - ((mips_abi != ABI_32 \
2286 && mips_abi != ABI_O64 \
2287 && mips_abi != ABI_EABI) \
2288 ? current_function_pretend_args_size \
2290 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2291 so we must add 4 bytes to the offset to get the right value. */ \
2292 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2294 if (leaf_function_p ()) \
2296 else (OFFSET) = current_frame_info.gp_sp_offset \
2297 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2298 * (BYTES_BIG_ENDIAN != 0)); \
2302 /* If we generate an insn to push BYTES bytes,
2303 this says how many the stack pointer really advances by.
2304 On the vax, sp@- in a byte insn really pushes a word. */
2306 /* #define PUSH_ROUNDING(BYTES) 0 */
2308 /* If defined, the maximum amount of space required for outgoing
2309 arguments will be computed and placed into the variable
2310 `current_function_outgoing_args_size'. No space will be pushed
2311 onto the stack for each call; instead, the function prologue
2312 should increase the stack frame size by this amount.
2314 It is not proper to define both `PUSH_ROUNDING' and
2315 `ACCUMULATE_OUTGOING_ARGS'. */
2316 #define ACCUMULATE_OUTGOING_ARGS
2318 /* Offset from the argument pointer register to the first argument's
2319 address. On some machines it may depend on the data type of the
2322 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2323 the first argument's address.
2325 On the MIPS, we must skip the first argument position if we are
2326 returning a structure or a union, to account for its address being
2327 passed in $4. However, at the current time, this produces a compiler
2328 that can't bootstrap, so comment it out for now. */
2331 #define FIRST_PARM_OFFSET(FNDECL) \
2333 && TREE_TYPE (FNDECL) != 0 \
2334 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2335 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2336 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2340 #define FIRST_PARM_OFFSET(FNDECL) 0
2343 /* When a parameter is passed in a register, stack space is still
2344 allocated for it. For the MIPS, stack space must be allocated, cf
2345 Asm Lang Prog Guide page 7-8.
2347 BEWARE that some space is also allocated for non existing arguments
2348 in register. In case an argument list is of form GF used registers
2349 are a0 (a2,a3), but we should push over a1... */
2351 #define REG_PARM_STACK_SPACE(FNDECL) \
2352 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2354 /* Define this if it is the responsibility of the caller to
2355 allocate the area reserved for arguments passed in registers.
2356 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2357 of this macro is to determine whether the space is included in
2358 `current_function_outgoing_args_size'. */
2359 #define OUTGOING_REG_PARM_STACK_SPACE
2361 /* Align stack frames on 64 bits (Double Word ). */
2362 #ifndef STACK_BOUNDARY
2363 #define STACK_BOUNDARY 64
2366 /* Make sure 4 words are always allocated on the stack. */
2368 #ifndef STACK_ARGS_ADJUST
2369 #define STACK_ARGS_ADJUST(SIZE) \
2371 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2372 SIZE.constant = 4 * UNITS_PER_WORD; \
2377 /* A C expression that should indicate the number of bytes of its
2378 own arguments that a function pops on returning, or 0
2379 if the function pops no arguments and the caller must therefore
2380 pop them all after the function returns.
2382 FUNDECL is the declaration node of the function (as a tree).
2384 FUNTYPE is a C variable whose value is a tree node that
2385 describes the function in question. Normally it is a node of
2386 type `FUNCTION_TYPE' that describes the data type of the function.
2387 From this it is possible to obtain the data types of the value
2388 and arguments (if known).
2390 When a call to a library function is being considered, FUNTYPE
2391 will contain an identifier node for the library function. Thus,
2392 if you need to distinguish among various library functions, you
2393 can do so by their names. Note that "library function" in this
2394 context means a function used to perform arithmetic, whose name
2395 is known specially in the compiler and was not mentioned in the
2396 C code being compiled.
2398 STACK-SIZE is the number of bytes of arguments passed on the
2399 stack. If a variable number of bytes is passed, it is zero, and
2400 argument popping will always be the responsibility of the
2401 calling function. */
2403 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2406 /* Symbolic macros for the registers used to return integer and floating
2409 #define GP_RETURN (GP_REG_FIRST + 2)
2410 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2412 /* Symbolic macros for the first/last argument registers. */
2414 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2415 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2416 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2417 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2419 #define MAX_ARGS_IN_REGISTERS 4
2421 /* Define how to find the value returned by a library function
2422 assuming the value has mode MODE. Because we define
2423 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2424 PROMOTE_MODE does. */
2426 #define LIBCALL_VALUE(MODE) \
2428 ((GET_MODE_CLASS (MODE) != MODE_INT \
2429 || GET_MODE_SIZE (MODE) >= 4) \
2432 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2433 && (! TARGET_SINGLE_FLOAT \
2434 || GET_MODE_SIZE (MODE) <= 4)) \
2438 /* Define how to find the value returned by a function.
2439 VALTYPE is the data type of the value (as a tree).
2440 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2441 otherwise, FUNC is 0. */
2443 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2446 /* 1 if N is a possible register number for a function value.
2447 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2448 Currently, R2 and F0 are only implemented here (C has no complex type) */
2450 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2452 /* 1 if N is a possible register number for function argument passing.
2453 We have no FP argument registers when soft-float. When FP registers
2454 are 32 bits, we can't directly reference the odd numbered ones. */
2456 #define FUNCTION_ARG_REGNO_P(N) \
2457 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2458 || ((! TARGET_SOFT_FLOAT \
2459 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2460 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2461 && ! fixed_regs[N]))
2463 /* A C expression which can inhibit the returning of certain function
2464 values in registers, based on the type of value. A nonzero value says
2465 to return the function value in memory, just as large structures are
2466 always returned. Here TYPE will be a C expression of type
2467 `tree', representing the data type of the value.
2469 Note that values of mode `BLKmode' must be explicitly
2470 handled by this macro. Also, the option `-fpcc-struct-return'
2471 takes effect regardless of this macro. On most systems, it is
2472 possible to leave the macro undefined; this causes a default
2473 definition to be used, whose value is the constant 1 for BLKmode
2474 values, and 0 otherwise.
2476 GCC normally converts 1 byte structures into chars, 2 byte
2477 structs into shorts, and 4 byte structs into ints, and returns
2478 them this way. Defining the following macro overrides this,
2479 to give us MIPS cc compatibility. */
2481 #define RETURN_IN_MEMORY(TYPE) \
2482 (TYPE_MODE (TYPE) == BLKmode)
2484 /* A code distinguishing the floating point format of the target
2485 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2486 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2488 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2491 /* Define a data type for recording info about an argument list
2492 during the scan of that argument list. This data type should
2493 hold all necessary information about the function itself
2494 and about the args processed so far, enough to enable macros
2495 such as FUNCTION_ARG to determine where the next arg should go.
2497 On the mips16, we need to keep track of which floating point
2498 arguments were passed in general registers, but would have been
2499 passed in the FP regs if this were a 32 bit function, so that we
2500 can move them to the FP regs if we wind up calling a 32 bit
2501 function. We record this information in fp_code, encoded in base
2502 four. A zero digit means no floating point argument, a one digit
2503 means an SFmode argument, and a two digit means a DFmode argument,
2504 and a three digit is not used. The low order digit is the first
2505 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2506 an SFmode argument. ??? A more sophisticated approach will be
2507 needed if MIPS_ABI != ABI_32. */
2509 typedef struct mips_args {
2510 int gp_reg_found; /* whether a gp register was found yet */
2511 int arg_number; /* argument number */
2512 int arg_words; /* # total words the arguments take */
2513 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2514 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2515 int fp_code; /* Mode of FP arguments (mips16) */
2516 int num_adjusts; /* number of adjustments made */
2517 /* Adjustments made to args pass in regs. */
2518 /* ??? The size is doubled to work around a
2519 bug in the code that sets the adjustments
2521 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2524 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2525 for a call to a function whose data type is FNTYPE.
2526 For a library call, FNTYPE is 0.
2530 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2531 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2533 /* Update the data in CUM to advance over an argument
2534 of mode MODE and data type TYPE.
2535 (TYPE is null for libcalls where that information may not be available.) */
2537 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2538 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2540 /* Determine where to put an argument to a function.
2541 Value is zero to push the argument on the stack,
2542 or a hard register in which to store the argument.
2544 MODE is the argument's machine mode.
2545 TYPE is the data type of the argument (as a tree).
2546 This is null for libcalls where that information may
2548 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2549 the preceding args and about the function being called.
2550 NAMED is nonzero if this argument is a named parameter
2551 (otherwise it is an extra parameter matching an ellipsis). */
2553 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2554 function_arg( &CUM, MODE, TYPE, NAMED)
2556 /* For an arg passed partly in registers and partly in memory,
2557 this is the number of registers used.
2558 For args passed entirely in registers or entirely in memory, zero. */
2560 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2561 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2563 /* If defined, a C expression that gives the alignment boundary, in
2564 bits, of an argument with the specified mode and type. If it is
2565 not defined, `PARM_BOUNDARY' is used for all arguments. */
2567 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2569 ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \
2571 : TYPE_ALIGN(TYPE)) \
2572 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2574 : GET_MODE_ALIGNMENT(MODE)))
2577 /* This macro generates the assembly code for function entry.
2578 FILE is a stdio stream to output the code to.
2579 SIZE is an int: how many units of temporary storage to allocate.
2580 Refer to the array `regs_ever_live' to determine which registers
2581 to save; `regs_ever_live[I]' is nonzero if register number I
2582 is ever used in the function. This macro is responsible for
2583 knowing which registers should not be saved even if used. */
2585 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2587 /* This macro generates the assembly code for function exit,
2588 on machines that need it. If FUNCTION_EPILOGUE is not defined
2589 then individual return instructions are generated for each
2590 return statement. Args are same as for FUNCTION_PROLOGUE. */
2592 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2594 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2596 #define MUST_SAVE_REGISTER(regno) \
2597 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2598 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2599 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2601 /* ALIGN FRAMES on double word boundaries */
2602 #ifndef MIPS_STACK_ALIGN
2603 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2607 /* Output assembler code to FILE to increment profiler label # LABELNO
2608 for profiling a function entry. */
2610 #define FUNCTION_PROFILER(FILE, LABELNO) \
2612 if (TARGET_MIPS16) \
2613 sorry ("mips16 function profiling"); \
2614 fprintf (FILE, "\t.set\tnoreorder\n"); \
2615 fprintf (FILE, "\t.set\tnoat\n"); \
2616 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2617 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2618 fprintf (FILE, "\tjal\t_mcount\n"); \
2620 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2621 TARGET_64BIT ? "dsubu" : "subu", \
2622 reg_names[STACK_POINTER_REGNUM], \
2623 reg_names[STACK_POINTER_REGNUM], \
2624 Pmode == DImode ? 16 : 8); \
2625 fprintf (FILE, "\t.set\treorder\n"); \
2626 fprintf (FILE, "\t.set\tat\n"); \
2629 /* Define this macro if the code for function profiling should come
2630 before the function prologue. Normally, the profiling code comes
2633 /* #define PROFILE_BEFORE_PROLOGUE */
2635 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2636 the stack pointer does not matter. The value is tested only in
2637 functions that have frame pointers.
2638 No definition is equivalent to always zero. */
2640 #define EXIT_IGNORE_STACK 1
2643 /* A C statement to output, on the stream FILE, assembler code for a
2644 block of data that contains the constant parts of a trampoline.
2645 This code should not include a label--the label is taken care of
2648 #define TRAMPOLINE_TEMPLATE(STREAM) \
2650 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2651 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2652 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2653 if (Pmode == DImode) \
2655 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2656 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2660 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2661 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2663 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2664 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2665 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2666 if (Pmode == DImode) \
2668 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2669 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2673 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2674 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2678 /* A C expression for the size in bytes of the trampoline, as an
2681 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2683 /* Alignment required for trampolines, in bits. */
2685 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2687 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2688 program and data caches. */
2690 #ifndef CACHE_FLUSH_FUNC
2691 #define CACHE_FLUSH_FUNC "_flush_cache"
2694 /* A C statement to initialize the variable parts of a trampoline.
2695 ADDR is an RTX for the address of the trampoline; FNADDR is an
2696 RTX for the address of the nested function; STATIC_CHAIN is an
2697 RTX for the static chain value that should be passed to the
2698 function when it is called. */
2700 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2703 if (Pmode == DImode) \
2705 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2706 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2710 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2711 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2714 /* Flush both caches. We need to flush the data cache in case \
2715 the system has a write-back cache. */ \
2716 /* ??? Should check the return value for errors. */ \
2717 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \
2718 0, VOIDmode, 3, addr, Pmode, \
2719 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2720 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2723 /* Addressing modes, and classification of registers for them. */
2725 /* #define HAVE_POST_INCREMENT 0 */
2726 /* #define HAVE_POST_DECREMENT 0 */
2728 /* #define HAVE_PRE_DECREMENT 0 */
2729 /* #define HAVE_PRE_INCREMENT 0 */
2731 /* These assume that REGNO is a hard or pseudo reg number.
2732 They give nonzero only if REGNO is a hard reg of the suitable class
2733 or a pseudo reg currently allocated to a suitable hard reg.
2734 These definitions are NOT overridden anywhere. */
2736 #define BASE_REG_P(regno, mode) \
2738 ? (M16_REG_P (regno) \
2739 || (regno) == FRAME_POINTER_REGNUM \
2740 || (regno) == ARG_POINTER_REGNUM \
2741 || ((regno) == STACK_POINTER_REGNUM \
2742 && (GET_MODE_SIZE (mode) == 4 \
2743 || GET_MODE_SIZE (mode) == 8))) \
2746 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2747 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2750 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2751 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2753 #define REGNO_OK_FOR_INDEX_P(regno) 0
2754 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2755 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2757 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2758 and check its validity for a certain class.
2759 We have two alternate definitions for each of them.
2760 The usual definition accepts all pseudo regs; the other rejects them all.
2761 The symbol REG_OK_STRICT causes the latter definition to be used.
2763 Most source files want to accept pseudo regs in the hope that
2764 they will get allocated to the class that the insn wants them to be in.
2765 Some source files that are used after register allocation
2766 need to be strict. */
2768 #ifndef REG_OK_STRICT
2770 #define REG_OK_STRICT_P 0
2771 #define REG_OK_FOR_INDEX_P(X) 0
2772 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2773 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2777 #define REG_OK_STRICT_P 1
2778 #define REG_OK_FOR_INDEX_P(X) 0
2779 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2780 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2785 /* Maximum number of registers that can appear in a valid memory address. */
2787 #define MAX_REGS_PER_ADDRESS 1
2789 /* A C compound statement with a conditional `goto LABEL;' executed
2790 if X (an RTX) is a legitimate memory address on the target
2791 machine for a memory operand of mode MODE.
2793 It usually pays to define several simpler macros to serve as
2794 subroutines for this one. Otherwise it may be too complicated
2797 This macro must exist in two variants: a strict variant and a
2798 non-strict one. The strict variant is used in the reload pass.
2799 It must be defined so that any pseudo-register that has not been
2800 allocated a hard register is considered a memory reference. In
2801 contexts where some kind of register is required, a
2802 pseudo-register with no hard register must be rejected.
2804 The non-strict variant is used in other passes. It must be
2805 defined to accept all pseudo-registers in every context where
2806 some kind of register is required.
2808 Compiler source files that want to use the strict variant of
2809 this macro define the macro `REG_OK_STRICT'. You should use an
2810 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2811 in that case and the non-strict variant otherwise.
2813 Typically among the subroutines used to define
2814 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2815 acceptable registers for various purposes (one for base
2816 registers, one for index registers, and so on). Then only these
2817 subroutine macros need have two variants; the higher levels of
2818 macros may be the same whether strict or not.
2820 Normally, constant addresses which are the sum of a `symbol_ref'
2821 and an integer are stored inside a `const' RTX to mark them as
2822 constant. Therefore, there is no need to recognize such sums
2823 specifically as legitimate addresses. Normally you would simply
2824 recognize any `const' as legitimate.
2826 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2827 constant sums that are not marked with `const'. It assumes
2828 that a naked `plus' indicates indexing. If so, then you *must*
2829 reject such naked constant sums as illegitimate addresses, so
2830 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2832 On some machines, whether a symbolic address is legitimate
2833 depends on the section that the address refers to. On these
2834 machines, define the macro `ENCODE_SECTION_INFO' to store the
2835 information into the `symbol_ref', and then check for it here.
2836 When you see a `const', you will have to look inside it to find
2837 the `symbol_ref' in order to determine the section. */
2840 #define GO_PRINTF(x) trace(x)
2841 #define GO_PRINTF2(x,y) trace(x,y)
2842 #define GO_DEBUG_RTX(x) debug_rtx(x)
2845 #define GO_PRINTF(x)
2846 #define GO_PRINTF2(x,y)
2847 #define GO_DEBUG_RTX(x)
2850 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2852 register rtx xinsn = (X); \
2854 if (TARGET_DEBUG_B_MODE) \
2856 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2857 (REG_OK_STRICT_P) ? "" : "not "); \
2858 GO_DEBUG_RTX (xinsn); \
2861 /* The mips16 can only use the stack pointer as a base register when \
2862 loading SImode or DImode values. */ \
2863 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2866 if (CONSTANT_ADDRESS_P (xinsn) \
2867 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2868 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2871 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2873 register rtx xlow0 = XEXP (xinsn, 0); \
2874 register rtx xlow1 = XEXP (xinsn, 1); \
2876 if (GET_CODE (xlow0) == REG \
2877 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2878 && mips_check_split (xlow1, MODE)) \
2882 if (GET_CODE (xinsn) == PLUS) \
2884 register rtx xplus0 = XEXP (xinsn, 0); \
2885 register rtx xplus1 = XEXP (xinsn, 1); \
2886 register enum rtx_code code0 = GET_CODE (xplus0); \
2887 register enum rtx_code code1 = GET_CODE (xplus1); \
2889 /* The mips16 can only use the stack pointer as a base register \
2890 when loading SImode or DImode values. */ \
2891 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2893 if (code1 == CONST_INT \
2894 && INTVAL (xplus1) >= -32768 \
2895 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2898 /* On the mips16, we represent GP relative offsets in RTL. \
2899 These are 16 bit signed values, and can serve as register \
2902 && mips16_gp_offset_p (xplus1)) \
2905 /* For some code sequences, you actually get better code by \
2906 pretending that the MIPS supports an address mode of a \
2907 constant address + a register, even though the real \
2908 machine doesn't support it. This is because the \
2909 assembler can use $r1 to load just the high 16 bits, add \
2910 in the register, and fold the low 16 bits into the memory \
2911 reference, whereas the compiler generates a 4 instruction \
2912 sequence. On the other hand, CSE is not as effective. \
2913 It would be a win to generate the lui directly, but the \
2914 MIPS assembler does not have syntax to generate the \
2915 appropriate relocation. */ \
2917 /* Also accept CONST_INT addresses here, so no else. */ \
2918 /* Reject combining an embedded PIC text segment reference \
2919 with a register. That requires an additional \
2921 /* ??? Reject combining an address with a register for the MIPS \
2922 64 bit ABI, because the SGI assembler can not handle this. */ \
2923 if (!TARGET_DEBUG_A_MODE \
2924 && (mips_abi == ABI_32 \
2925 || mips_abi == ABI_O64 \
2926 || mips_abi == ABI_EABI) \
2927 && CONSTANT_ADDRESS_P (xplus1) \
2928 && ! mips_split_addresses \
2929 && (!TARGET_EMBEDDED_PIC \
2931 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2932 && !TARGET_MIPS16) \
2937 if (TARGET_DEBUG_B_MODE) \
2938 GO_PRINTF ("Not a legitimate address\n"); \
2942 /* A C expression that is 1 if the RTX X is a constant which is a
2943 valid address. This is defined to be the same as `CONSTANT_P (X)',
2944 but rejecting CONST_DOUBLE. */
2945 /* When pic, we must reject addresses of the form symbol+large int.
2946 This is because an instruction `sw $4,s+70000' needs to be converted
2947 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2948 assembler would use $at as a temp to load in the large offset. In this
2949 case $at is already in use. We convert such problem addresses to
2950 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2951 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2952 #define CONSTANT_ADDRESS_P(X) \
2953 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2954 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2955 || (GET_CODE (X) == CONST \
2956 && ! (flag_pic && pic_address_needs_scratch (X)) \
2957 && (mips_abi == ABI_32 \
2958 || mips_abi == ABI_O64 \
2959 || mips_abi == ABI_EABI))) \
2960 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2962 /* Define this, so that when PIC, reload won't try to reload invalid
2963 addresses which require two reload registers. */
2965 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2967 /* Nonzero if the constant value X is a legitimate general operand.
2968 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2970 At present, GAS doesn't understand li.[sd], so don't allow it
2971 to be generated at present. Also, the MIPS assembler does not
2972 grok li.d Infinity. */
2974 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2975 #define LEGITIMATE_CONSTANT_P(X) \
2976 ((GET_CODE (X) != CONST_DOUBLE \
2977 || mips_const_double_ok (X, GET_MODE (X))) \
2978 && ! (GET_CODE (X) == CONST \
2979 && mips_abi != ABI_32 \
2980 && mips_abi != ABI_O64 \
2981 && mips_abi != ABI_EABI) \
2982 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2984 /* A C compound statement that attempts to replace X with a valid
2985 memory address for an operand of mode MODE. WIN will be a C
2986 statement label elsewhere in the code; the macro definition may
2989 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2991 to avoid further processing if the address has become legitimate.
2993 X will always be the result of a call to `break_out_memory_refs',
2994 and OLDX will be the operand that was given to that function to
2997 The code generated by this macro should not alter the
2998 substructure of X. If it transforms X into a more legitimate
2999 form, it should assign X (which will always be a C variable) a
3002 It is not necessary for this macro to come up with a legitimate
3003 address. The compiler has standard ways of doing so in all
3004 cases. In fact, it is safe for this macro to do nothing. But
3005 often a machine-dependent strategy can generate better code.
3007 For the MIPS, transform:
3009 memory(X + <large int>)
3013 Y = <large int> & ~0x7fff;
3015 memory (Z + (<large int> & 0x7fff));
3017 This is for CSE to find several similar references, and only use one Z.
3019 When PIC, convert addresses of the form memory (symbol+large int) to
3020 memory (reg+large int). */
3023 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3025 register rtx xinsn = (X); \
3027 if (TARGET_DEBUG_B_MODE) \
3029 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3030 GO_DEBUG_RTX (xinsn); \
3033 if (mips_split_addresses && mips_check_split (X, MODE)) \
3035 /* ??? Is this ever executed? */ \
3036 X = gen_rtx (LO_SUM, Pmode, \
3037 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
3041 if (GET_CODE (xinsn) == CONST \
3042 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3043 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3044 || (mips_abi != ABI_32 \
3045 && mips_abi != ABI_O64 \
3046 && mips_abi != ABI_EABI))) \
3048 rtx ptr_reg = gen_reg_rtx (Pmode); \
3049 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3051 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3053 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
3054 if (SMALL_INT (constant)) \
3056 /* Otherwise we fall through so the code below will fix the \
3061 if (GET_CODE (xinsn) == PLUS) \
3063 register rtx xplus0 = XEXP (xinsn, 0); \
3064 register rtx xplus1 = XEXP (xinsn, 1); \
3065 register enum rtx_code code0 = GET_CODE (xplus0); \
3066 register enum rtx_code code1 = GET_CODE (xplus1); \
3068 if (code0 != REG && code1 == REG) \
3070 xplus0 = XEXP (xinsn, 1); \
3071 xplus1 = XEXP (xinsn, 0); \
3072 code0 = GET_CODE (xplus0); \
3073 code1 = GET_CODE (xplus1); \
3076 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3077 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3079 rtx int_reg = gen_reg_rtx (Pmode); \
3080 rtx ptr_reg = gen_reg_rtx (Pmode); \
3082 emit_move_insn (int_reg, \
3083 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3085 emit_insn (gen_rtx (SET, VOIDmode, \
3087 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
3089 X = gen_rtx (PLUS, Pmode, ptr_reg, \
3090 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
3095 if (TARGET_DEBUG_B_MODE) \
3096 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3100 /* A C statement or compound statement with a conditional `goto
3101 LABEL;' executed if memory address X (an RTX) can have different
3102 meanings depending on the machine mode of the memory reference it
3105 Autoincrement and autodecrement addresses typically have
3106 mode-dependent effects because the amount of the increment or
3107 decrement is the size of the operand being addressed. Some
3108 machines have other mode-dependent addresses. Many RISC machines
3109 have no mode-dependent addresses.
3111 You may assume that ADDR is a valid address for the machine. */
3113 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3116 /* Define this macro if references to a symbol must be treated
3117 differently depending on something about the variable or
3118 function named by the symbol (such as what section it is in).
3120 The macro definition, if any, is executed immediately after the
3121 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3122 The value of the rtl will be a `mem' whose address is a
3125 The usual thing for this macro to do is to a flag in the
3126 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3127 name string in the `symbol_ref' (if one bit is not enough
3130 The best way to modify the name string is by adding text to the
3131 beginning, with suitable punctuation to prevent any ambiguity.
3132 Allocate the new name in `saveable_obstack'. You will have to
3133 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3134 and output the name accordingly.
3136 You can also check the information stored in the `symbol_ref' in
3137 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3138 `PRINT_OPERAND_ADDRESS'.
3140 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3143 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3144 symbols which are not in the .text section.
3146 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3147 constants which are put in the .text section. We also record the
3148 total length of all such strings; this total is used to decide
3149 whether we need to split the constant table, and need not be
3152 When not mips16 code nor embedded PIC, if a symbol is in a
3153 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3154 splitting the reference so that gas can generate a gp relative
3157 When TARGET_EMBEDDED_DATA is set, we assume that all const
3158 variables will be stored in ROM, which is too far from %gp to use
3159 %gprel addressing. Note that (1) we include "extern const"
3160 variables in this, which mips_select_section doesn't, and (2) we
3161 can't always tell if they're really const (they might be const C++
3162 objects with non-const constructors), so we err on the side of
3163 caution and won't use %gprel anyway (otherwise we'd have to defer
3164 this decision to the linker/loader). The handling of extern consts
3165 is why the DECL_INITIAL macros differ from mips_select_section.
3167 If you are changing this macro, you should look at
3168 mips_select_section and see if it needs a similar change. */
3170 #ifndef UNIQUE_SECTION_P
3171 #define UNIQUE_SECTION_P(DECL) (0)
3174 #define ENCODE_SECTION_INFO(DECL) \
3177 if (TARGET_MIPS16) \
3179 if (TREE_CODE (DECL) == STRING_CST \
3180 && ! flag_writable_strings \
3181 /* If this string is from a function, and the function will \
3182 go in a gnu linkonce section, then we can't directly \
3183 access the string. This gets an assembler error \
3184 "unsupported PC relative reference to different section".\
3185 If we modify SELECT_SECTION to put it in function_section\
3186 instead of text_section, it still fails because \
3187 DECL_SECTION_NAME isn't set until assemble_start_function.\
3188 If we fix that, it still fails because strings are shared\
3189 among multiple functions, and we have cross section \
3190 references again. We force it to work by putting string \
3191 addresses in the constant pool and indirecting. */ \
3192 && (! current_function_decl \
3193 || ! UNIQUE_SECTION_P (current_function_decl))) \
3195 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3196 mips_string_length += TREE_STRING_LENGTH (DECL); \
3200 if (TARGET_EMBEDDED_DATA \
3201 && (TREE_CODE (DECL) == VAR_DECL \
3202 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3203 && (!DECL_INITIAL (DECL) \
3204 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3206 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3209 else if (TARGET_EMBEDDED_PIC) \
3211 if (TREE_CODE (DECL) == VAR_DECL) \
3212 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3213 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3214 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3215 else if (TREE_CODE (DECL) == STRING_CST \
3216 && ! flag_writable_strings) \
3217 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3219 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3222 else if (TREE_CODE (DECL) == VAR_DECL \
3223 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3224 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3226 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3229 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3232 /* We can not perform GP optimizations on variables which are in \
3233 specific sections, except for .sdata and .sbss which are \
3235 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3236 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3238 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3240 if (size > 0 && size <= mips_section_threshold) \
3241 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3244 else if (HALF_PIC_P ()) \
3246 HALF_PIC_ENCODE (DECL); \
3251 /* The mips16 wants the constant pool to be after the function,
3252 because the PC relative load instructions use unsigned offsets. */
3254 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3256 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3257 mips_string_length = 0;
3260 /* In mips16 mode, put most string constants after the function. */
3261 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3262 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3265 /* Specify the machine mode that this machine uses
3266 for the index in the tablejump instruction.
3267 ??? Using HImode in mips16 mode can cause overflow. However, the
3268 overflow is no more likely than the overflow in a branch
3269 instruction. Large functions can currently break in both ways. */
3270 #define CASE_VECTOR_MODE \
3271 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3273 /* Define as C expression which evaluates to nonzero if the tablejump
3274 instruction expects the table to contain offsets from the address of the
3276 Do not define this if the table should contain absolute addresses. */
3277 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3279 /* Specify the tree operation to be used to convert reals to integers. */
3280 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3282 /* This is the kind of divide that is easiest to do in the general case. */
3283 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3285 /* Define this as 1 if `char' should by default be signed; else as 0. */
3286 #ifndef DEFAULT_SIGNED_CHAR
3287 #define DEFAULT_SIGNED_CHAR 1
3290 /* Max number of bytes we can move from memory to memory
3291 in one reasonably fast instruction. */
3292 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3293 #define MAX_MOVE_MAX 8
3295 /* Define this macro as a C expression which is nonzero if
3296 accessing less than a word of memory (i.e. a `char' or a
3297 `short') is no faster than accessing a word of memory, i.e., if
3298 such access require more than one instruction or if there is no
3299 difference in cost between byte and (aligned) word loads.
3301 On RISC machines, it tends to generate better code to define
3302 this as 1, since it avoids making a QI or HI mode register. */
3303 #define SLOW_BYTE_ACCESS 1
3305 /* We assume that the store-condition-codes instructions store 0 for false
3306 and some other value for true. This is the value stored for true. */
3308 #define STORE_FLAG_VALUE 1
3310 /* Define this if zero-extension is slow (more than one real instruction). */
3311 #define SLOW_ZERO_EXTEND
3313 /* Define this to be nonzero if shift instructions ignore all but the low-order
3315 #define SHIFT_COUNT_TRUNCATED 1
3317 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3318 is done just by pretending it is already truncated. */
3319 /* In 64 bit mode, 32 bit instructions require that register values be properly
3320 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3321 converts a value >32 bits to a value <32 bits. */
3322 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3323 Something needs to be done about this. Perhaps not use any 32 bit
3324 instructions? Perhaps use PROMOTE_MODE? */
3325 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3326 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3328 /* Specify the machine mode that pointers have.
3329 After generation of rtl, the compiler makes no further distinction
3330 between pointers and any other objects of this machine mode.
3332 For MIPS we make pointers are the smaller of longs and gp-registers. */
3335 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3338 /* A function address in a call instruction
3339 is a word address (for indexing purposes)
3340 so give the MEM rtx a words's mode. */
3342 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3344 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3345 memset, instead of the BSD functions bcopy and bzero. */
3347 #if defined(MIPS_SYSV) || defined(OSF_OS)
3348 #define TARGET_MEM_FUNCTIONS
3352 /* A part of a C `switch' statement that describes the relative
3353 costs of constant RTL expressions. It must contain `case'
3354 labels for expression codes `const_int', `const', `symbol_ref',
3355 `label_ref' and `const_double'. Each case must ultimately reach
3356 a `return' statement to return the relative cost of the use of
3357 that kind of constant value in an expression. The cost may
3358 depend on the precise value of the constant, which is available
3359 for examination in X.
3361 CODE is the expression code--redundant, since it can be obtained
3362 with `GET_CODE (X)'. */
3364 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3366 if (! TARGET_MIPS16) \
3368 /* Always return 0, since we don't have different sized \
3369 instructions, hence different costs according to Richard \
3373 if ((OUTER_CODE) == SET) \
3375 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3377 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3378 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3379 return COSTS_N_INSNS (1); \
3381 return COSTS_N_INSNS (2); \
3383 /* A PLUS could be an address. We don't want to force an address \
3384 to use a register, so accept any signed 16 bit value without \
3386 if ((OUTER_CODE) == PLUS \
3387 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3389 /* A number between 1 and 8 inclusive is efficient for a shift. \
3390 Otherwise, we will need an extended instruction. */ \
3391 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3392 || (OUTER_CODE) == LSHIFTRT) \
3394 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3396 return COSTS_N_INSNS (1); \
3398 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3399 if ((OUTER_CODE) == XOR \
3400 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3402 /* We may be able to use slt or sltu for a comparison with a \
3403 signed 16 bit value. (The boundary conditions aren't quite \
3404 right, but this is just a heuristic anyhow.) */ \
3405 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3406 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3407 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3408 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3409 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3411 /* Equality comparisons with 0 are cheap. */ \
3412 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3413 && INTVAL (X) == 0) \
3416 /* Otherwise, work out the cost to load the value into a \
3418 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3419 return COSTS_N_INSNS (1); \
3420 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3421 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3422 return COSTS_N_INSNS (2); \
3424 return COSTS_N_INSNS (3); \
3427 return COSTS_N_INSNS (2); \
3431 rtx offset = const0_rtx; \
3432 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3434 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3436 /* Treat this like a signed 16 bit CONST_INT. */ \
3437 if ((OUTER_CODE) == PLUS) \
3439 else if ((OUTER_CODE) == SET) \
3440 return COSTS_N_INSNS (1); \
3442 return COSTS_N_INSNS (2); \
3445 if (GET_CODE (symref) == LABEL_REF) \
3446 return COSTS_N_INSNS (2); \
3448 if (GET_CODE (symref) != SYMBOL_REF) \
3449 return COSTS_N_INSNS (4); \
3451 /* let's be paranoid.... */ \
3452 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3453 return COSTS_N_INSNS (2); \
3455 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3459 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3461 case CONST_DOUBLE: \
3464 if (TARGET_MIPS16) \
3465 return COSTS_N_INSNS (4); \
3466 split_double (X, &high, &low); \
3467 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3468 || low == CONST0_RTX (GET_MODE (low))) \
3472 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3473 This can be used, for example, to indicate how costly a multiply
3474 instruction is. In writing this macro, you can use the construct
3475 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3477 This macro is optional; do not define it if the default cost
3478 assumptions are adequate for the target machine.
3480 If -mdebugd is used, change the multiply cost to 2, so multiply by
3481 a constant isn't converted to a series of shifts. This helps
3482 strength reduction, and also makes it easier to identify what the
3483 compiler is doing. */
3485 /* ??? Fix this to be right for the R8000. */
3486 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3489 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3490 if (simple_memory_operand (X, GET_MODE (X))) \
3491 return COSTS_N_INSNS (num_words); \
3493 return COSTS_N_INSNS (2*num_words); \
3497 return COSTS_N_INSNS (6); \
3500 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3505 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3506 return COSTS_N_INSNS (2); \
3513 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3514 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3520 enum machine_mode xmode = GET_MODE (X); \
3521 if (xmode == SFmode || xmode == DFmode) \
3522 return COSTS_N_INSNS (1); \
3524 return COSTS_N_INSNS (4); \
3530 enum machine_mode xmode = GET_MODE (X); \
3531 if (xmode == SFmode || xmode == DFmode) \
3533 if (mips_cpu == PROCESSOR_R3000 \
3534 || mips_cpu == PROCESSOR_R3900) \
3535 return COSTS_N_INSNS (2); \
3536 else if (mips_cpu == PROCESSOR_R6000) \
3537 return COSTS_N_INSNS (3); \
3539 return COSTS_N_INSNS (6); \
3542 if (xmode == DImode && !TARGET_64BIT) \
3543 return COSTS_N_INSNS (4); \
3549 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3556 enum machine_mode xmode = GET_MODE (X); \
3557 if (xmode == SFmode) \
3559 if (mips_cpu == PROCESSOR_R3000 \
3560 || mips_cpu == PROCESSOR_R3900 \
3561 || mips_cpu == PROCESSOR_R5000) \
3562 return COSTS_N_INSNS (4); \
3563 else if (mips_cpu == PROCESSOR_R6000) \
3564 return COSTS_N_INSNS (5); \
3566 return COSTS_N_INSNS (7); \
3569 if (xmode == DFmode) \
3571 if (mips_cpu == PROCESSOR_R3000 \
3572 || mips_cpu == PROCESSOR_R3900 \
3573 || mips_cpu == PROCESSOR_R5000) \
3574 return COSTS_N_INSNS (5); \
3575 else if (mips_cpu == PROCESSOR_R6000) \
3576 return COSTS_N_INSNS (6); \
3578 return COSTS_N_INSNS (8); \
3581 if (mips_cpu == PROCESSOR_R3000) \
3582 return COSTS_N_INSNS (12); \
3583 else if (mips_cpu == PROCESSOR_R3900) \
3584 return COSTS_N_INSNS (2); \
3585 else if (mips_cpu == PROCESSOR_R6000) \
3586 return COSTS_N_INSNS (17); \
3587 else if (mips_cpu == PROCESSOR_R5000) \
3588 return COSTS_N_INSNS (5); \
3590 return COSTS_N_INSNS (10); \
3596 enum machine_mode xmode = GET_MODE (X); \
3597 if (xmode == SFmode) \
3599 if (mips_cpu == PROCESSOR_R3000 \
3600 || mips_cpu == PROCESSOR_R3900) \
3601 return COSTS_N_INSNS (12); \
3602 else if (mips_cpu == PROCESSOR_R6000) \
3603 return COSTS_N_INSNS (15); \
3605 return COSTS_N_INSNS (23); \
3608 if (xmode == DFmode) \
3610 if (mips_cpu == PROCESSOR_R3000 \
3611 || mips_cpu == PROCESSOR_R3900) \
3612 return COSTS_N_INSNS (19); \
3613 else if (mips_cpu == PROCESSOR_R6000) \
3614 return COSTS_N_INSNS (16); \
3616 return COSTS_N_INSNS (36); \
3619 /* fall through */ \
3623 if (mips_cpu == PROCESSOR_R3000 \
3624 || mips_cpu == PROCESSOR_R3900) \
3625 return COSTS_N_INSNS (35); \
3626 else if (mips_cpu == PROCESSOR_R6000) \
3627 return COSTS_N_INSNS (38); \
3628 else if (mips_cpu == PROCESSOR_R5000) \
3629 return COSTS_N_INSNS (36); \
3631 return COSTS_N_INSNS (69); \
3634 /* A sign extend from SImode to DImode in 64 bit mode is often \
3635 zero instructions, because the result can often be used \
3636 directly by another instruction; we'll call it one. */ \
3637 if (TARGET_64BIT && GET_MODE (X) == DImode \
3638 && GET_MODE (XEXP (X, 0)) == SImode) \
3639 return COSTS_N_INSNS (1); \
3641 return COSTS_N_INSNS (2); \
3644 if (TARGET_64BIT && GET_MODE (X) == DImode \
3645 && GET_MODE (XEXP (X, 0)) == SImode) \
3646 return COSTS_N_INSNS (2); \
3648 return COSTS_N_INSNS (1);
3650 /* An expression giving the cost of an addressing mode that
3651 contains ADDRESS. If not defined, the cost is computed from the
3652 form of the ADDRESS expression and the `CONST_COSTS' values.
3654 For most CISC machines, the default cost is a good approximation
3655 of the true cost of the addressing mode. However, on RISC
3656 machines, all instructions normally have the same length and
3657 execution time. Hence all addresses will have equal costs.
3659 In cases where more than one form of an address is known, the
3660 form with the lowest cost will be used. If multiple forms have
3661 the same, lowest, cost, the one that is the most complex will be
3664 For example, suppose an address that is equal to the sum of a
3665 register and a constant is used twice in the same basic block.
3666 When this macro is not defined, the address will be computed in
3667 a register and memory references will be indirect through that
3668 register. On machines where the cost of the addressing mode
3669 containing the sum is no higher than that of a simple indirect
3670 reference, this will produce an additional instruction and
3671 possibly require an additional register. Proper specification
3672 of this macro eliminates this overhead for such machines.
3674 Similar use of this macro is made in strength reduction of loops.
3676 ADDRESS need not be valid as an address. In such a case, the
3677 cost is not relevant and can be any value; invalid addresses
3678 need not be assigned a different cost.
3680 On machines where an address involving more than one register is
3681 as cheap as an address computation involving only one register,
3682 defining `ADDRESS_COST' to reflect this can cause two registers
3683 to be live over a region of code where only one would have been
3684 if `ADDRESS_COST' were not defined in that manner. This effect
3685 should be considered in the definition of this macro.
3686 Equivalent costs should probably only be given to addresses with
3687 different numbers of registers on machines with lots of registers.
3689 This macro will normally either not be defined or be defined as
3692 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3694 /* A C expression for the cost of moving data from a register in
3695 class FROM to one in class TO. The classes are expressed using
3696 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3697 the default; other values are interpreted relative to that.
3699 It is not required that the cost always equal 2 when FROM is the
3700 same as TO; on some machines it is expensive to move between
3701 registers if they are not general registers.
3703 If reload sees an insn consisting of a single `set' between two
3704 hard registers, and if `REGISTER_MOVE_COST' applied to their
3705 classes returns a value of 2, reload does not check to ensure
3706 that the constraints of the insn are met. Setting a cost of
3707 other than 2 will allow reload to verify that the constraints are
3708 met. You should do this if the `movM' pattern's constraints do
3709 not allow such copying.
3711 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3712 registers the same as for one of moving general registers to
3713 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3714 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3715 isn't clear if it is wise. And it might not work in all cases. We
3716 could solve the DImode LO reg problem by using a multiply, just like
3717 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3718 by using divide instructions. divu puts the remainder in the HI
3719 reg, so doing a divide by -1 will move the value in the HI reg for
3720 all values except -1. We could handle that case by using a signed
3721 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3722 compare/branch to test the input value to see which instruction we
3723 need to use. This gets pretty messy, but it is feasible. */
3725 #define REGISTER_MOVE_COST(FROM, TO) \
3726 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3727 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3728 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3729 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3730 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3731 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3732 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3733 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3734 : (((FROM) == HI_REG || (FROM) == LO_REG \
3735 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3736 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3737 : (((FROM) == HI_REG || (FROM) == LO_REG \
3738 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3739 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3740 : (((TO) == HI_REG || (TO) == LO_REG \
3741 || (TO) == MD_REGS || (TO) == HILO_REG) \
3742 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3743 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3744 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3747 /* ??? Fix this to be right for the R8000. */
3748 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3749 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3750 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3752 /* Define if copies to/from condition code registers should be avoided.
3754 This is needed for the MIPS because reload_outcc is not complete;
3755 it needs to handle cases where the source is a general or another
3756 condition code register. */
3757 #define AVOID_CCMODE_COPIES
3759 /* A C expression for the cost of a branch instruction. A value of
3760 1 is the default; other values are interpreted relative to that. */
3762 /* ??? Fix this to be right for the R8000. */
3763 #define BRANCH_COST \
3765 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3768 /* A C statement (sans semicolon) to update the integer variable COST
3769 based on the relationship between INSN that is dependent on
3770 DEP_INSN through the dependence LINK. The default is to make no
3771 adjustment to COST. On the MIPS, ignore the cost of anti- and
3772 output-dependencies. */
3774 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3775 if (REG_NOTE_KIND (LINK) != 0) \
3776 (COST) = 0; /* Anti or output dependence. */
3778 /* If defined, modifies the length assigned to instruction INSN as a
3779 function of the context in which it is used. LENGTH is an lvalue
3780 that contains the initially computed length of the insn and should
3781 be updated with the correct length of the insn. */
3782 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3783 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3786 /* Optionally define this if you have added predicates to
3787 `MACHINE.c'. This macro is called within an initializer of an
3788 array of structures. The first field in the structure is the
3789 name of a predicate and the second field is an array of rtl
3790 codes. For each predicate, list all rtl codes that can be in
3791 expressions matched by the predicate. The list should have a
3792 trailing comma. Here is an example of two entries in the list
3793 for a typical RISC machine:
3795 #define PREDICATE_CODES \
3796 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3797 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3799 Defining this macro does not affect the generated code (however,
3800 incorrect definitions that omit an rtl code that may be matched
3801 by the predicate can cause the compiler to malfunction).
3802 Instead, it allows the table built by `genrecog' to be more
3803 compact and efficient, thus speeding up the compiler. The most
3804 important predicates to include in the list specified by this
3805 macro are thoses used in the most insn patterns. */
3807 #define PREDICATE_CODES \
3808 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3809 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3810 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3811 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3812 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3813 {"small_int", { CONST_INT }}, \
3814 {"large_int", { CONST_INT }}, \
3815 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3816 {"const_float_1_operand", { CONST_DOUBLE }}, \
3817 {"simple_memory_operand", { MEM, SUBREG }}, \
3818 {"equality_op", { EQ, NE }}, \
3819 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3821 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3822 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3823 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3824 SYMBOL_REF, LABEL_REF, SUBREG, \
3826 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3827 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3828 MEM, SIGN_EXTEND }}, \
3829 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3830 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3832 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3834 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3836 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3837 SYMBOL_REF, LABEL_REF, SUBREG, \
3838 REG, SIGN_EXTEND }}, \
3839 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3840 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3841 CONST_DOUBLE, CONST }}, \
3842 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3843 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3847 /* If defined, a C statement to be executed just prior to the
3848 output of assembler code for INSN, to modify the extracted
3849 operands so they will be output differently.
3851 Here the argument OPVEC is the vector containing the operands
3852 extracted from INSN, and NOPERANDS is the number of elements of
3853 the vector which contain meaningful data for this insn. The
3854 contents of this vector are what will be used to convert the
3855 insn template into assembler code, so you can change the
3856 assembler output by changing the contents of the vector.
3858 We use it to check if the current insn needs a nop in front of it
3859 because of load delays, and also to update the delay slot
3862 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3863 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3866 /* Control the assembler format that we output. */
3868 /* Output at beginning of assembler file.
3869 If we are optimizing to use the global pointer, create a temporary
3870 file to hold all of the text stuff, and write it out to the end.
3871 This is needed because the MIPS assembler is evidently one pass,
3872 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3873 declaration when the code is processed, it generates a two
3874 instruction sequence. */
3876 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3878 /* Output to assembler file text saying following lines
3879 may contain character constants, extra white space, comments, etc. */
3881 #define ASM_APP_ON " #APP\n"
3883 /* Output to assembler file text saying following lines
3884 no longer contain unusual constructs. */
3886 #define ASM_APP_OFF " #NO_APP\n"
3888 /* How to refer to registers in assembler output.
3889 This sequence is indexed by compiler's hard-register-number (see above).
3891 In order to support the two different conventions for register names,
3892 we use the name of a table set up in mips.c, which is overwritten
3893 if -mrnames is used. */
3895 #define REGISTER_NAMES \
3897 &mips_reg_names[ 0][0], \
3898 &mips_reg_names[ 1][0], \
3899 &mips_reg_names[ 2][0], \
3900 &mips_reg_names[ 3][0], \
3901 &mips_reg_names[ 4][0], \
3902 &mips_reg_names[ 5][0], \
3903 &mips_reg_names[ 6][0], \
3904 &mips_reg_names[ 7][0], \
3905 &mips_reg_names[ 8][0], \
3906 &mips_reg_names[ 9][0], \
3907 &mips_reg_names[10][0], \
3908 &mips_reg_names[11][0], \
3909 &mips_reg_names[12][0], \
3910 &mips_reg_names[13][0], \
3911 &mips_reg_names[14][0], \
3912 &mips_reg_names[15][0], \
3913 &mips_reg_names[16][0], \
3914 &mips_reg_names[17][0], \
3915 &mips_reg_names[18][0], \
3916 &mips_reg_names[19][0], \
3917 &mips_reg_names[20][0], \
3918 &mips_reg_names[21][0], \
3919 &mips_reg_names[22][0], \
3920 &mips_reg_names[23][0], \
3921 &mips_reg_names[24][0], \
3922 &mips_reg_names[25][0], \
3923 &mips_reg_names[26][0], \
3924 &mips_reg_names[27][0], \
3925 &mips_reg_names[28][0], \
3926 &mips_reg_names[29][0], \
3927 &mips_reg_names[30][0], \
3928 &mips_reg_names[31][0], \
3929 &mips_reg_names[32][0], \
3930 &mips_reg_names[33][0], \
3931 &mips_reg_names[34][0], \
3932 &mips_reg_names[35][0], \
3933 &mips_reg_names[36][0], \
3934 &mips_reg_names[37][0], \
3935 &mips_reg_names[38][0], \
3936 &mips_reg_names[39][0], \
3937 &mips_reg_names[40][0], \
3938 &mips_reg_names[41][0], \
3939 &mips_reg_names[42][0], \
3940 &mips_reg_names[43][0], \
3941 &mips_reg_names[44][0], \
3942 &mips_reg_names[45][0], \
3943 &mips_reg_names[46][0], \
3944 &mips_reg_names[47][0], \
3945 &mips_reg_names[48][0], \
3946 &mips_reg_names[49][0], \
3947 &mips_reg_names[50][0], \
3948 &mips_reg_names[51][0], \
3949 &mips_reg_names[52][0], \
3950 &mips_reg_names[53][0], \
3951 &mips_reg_names[54][0], \
3952 &mips_reg_names[55][0], \
3953 &mips_reg_names[56][0], \
3954 &mips_reg_names[57][0], \
3955 &mips_reg_names[58][0], \
3956 &mips_reg_names[59][0], \
3957 &mips_reg_names[60][0], \
3958 &mips_reg_names[61][0], \
3959 &mips_reg_names[62][0], \
3960 &mips_reg_names[63][0], \
3961 &mips_reg_names[64][0], \
3962 &mips_reg_names[65][0], \
3963 &mips_reg_names[66][0], \
3964 &mips_reg_names[67][0], \
3965 &mips_reg_names[68][0], \
3966 &mips_reg_names[69][0], \
3967 &mips_reg_names[70][0], \
3968 &mips_reg_names[71][0], \
3969 &mips_reg_names[72][0], \
3970 &mips_reg_names[73][0], \
3971 &mips_reg_names[74][0], \
3972 &mips_reg_names[75][0], \
3975 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3976 So define this for it. */
3977 #define DEBUG_REGISTER_NAMES \
3979 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3980 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3981 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3982 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3983 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3984 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3985 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3986 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3987 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3988 "$fcc5","$fcc6","$fcc7","$rap" \
3991 /* If defined, a C initializer for an array of structures
3992 containing a name and a register number. This macro defines
3993 additional names for hard registers, thus allowing the `asm'
3994 option in declarations to refer to registers using alternate
3997 We define both names for the integer registers here. */
3999 #define ADDITIONAL_REGISTER_NAMES \
4001 { "$0", 0 + GP_REG_FIRST }, \
4002 { "$1", 1 + GP_REG_FIRST }, \
4003 { "$2", 2 + GP_REG_FIRST }, \
4004 { "$3", 3 + GP_REG_FIRST }, \
4005 { "$4", 4 + GP_REG_FIRST }, \
4006 { "$5", 5 + GP_REG_FIRST }, \
4007 { "$6", 6 + GP_REG_FIRST }, \
4008 { "$7", 7 + GP_REG_FIRST }, \
4009 { "$8", 8 + GP_REG_FIRST }, \
4010 { "$9", 9 + GP_REG_FIRST }, \
4011 { "$10", 10 + GP_REG_FIRST }, \
4012 { "$11", 11 + GP_REG_FIRST }, \
4013 { "$12", 12 + GP_REG_FIRST }, \
4014 { "$13", 13 + GP_REG_FIRST }, \
4015 { "$14", 14 + GP_REG_FIRST }, \
4016 { "$15", 15 + GP_REG_FIRST }, \
4017 { "$16", 16 + GP_REG_FIRST }, \
4018 { "$17", 17 + GP_REG_FIRST }, \
4019 { "$18", 18 + GP_REG_FIRST }, \
4020 { "$19", 19 + GP_REG_FIRST }, \
4021 { "$20", 20 + GP_REG_FIRST }, \
4022 { "$21", 21 + GP_REG_FIRST }, \
4023 { "$22", 22 + GP_REG_FIRST }, \
4024 { "$23", 23 + GP_REG_FIRST }, \
4025 { "$24", 24 + GP_REG_FIRST }, \
4026 { "$25", 25 + GP_REG_FIRST }, \
4027 { "$26", 26 + GP_REG_FIRST }, \
4028 { "$27", 27 + GP_REG_FIRST }, \
4029 { "$28", 28 + GP_REG_FIRST }, \
4030 { "$29", 29 + GP_REG_FIRST }, \
4031 { "$30", 30 + GP_REG_FIRST }, \
4032 { "$31", 31 + GP_REG_FIRST }, \
4033 { "$sp", 29 + GP_REG_FIRST }, \
4034 { "$fp", 30 + GP_REG_FIRST }, \
4035 { "at", 1 + GP_REG_FIRST }, \
4036 { "v0", 2 + GP_REG_FIRST }, \
4037 { "v1", 3 + GP_REG_FIRST }, \
4038 { "a0", 4 + GP_REG_FIRST }, \
4039 { "a1", 5 + GP_REG_FIRST }, \
4040 { "a2", 6 + GP_REG_FIRST }, \
4041 { "a3", 7 + GP_REG_FIRST }, \
4042 { "t0", 8 + GP_REG_FIRST }, \
4043 { "t1", 9 + GP_REG_FIRST }, \
4044 { "t2", 10 + GP_REG_FIRST }, \
4045 { "t3", 11 + GP_REG_FIRST }, \
4046 { "t4", 12 + GP_REG_FIRST }, \
4047 { "t5", 13 + GP_REG_FIRST }, \
4048 { "t6", 14 + GP_REG_FIRST }, \
4049 { "t7", 15 + GP_REG_FIRST }, \
4050 { "s0", 16 + GP_REG_FIRST }, \
4051 { "s1", 17 + GP_REG_FIRST }, \
4052 { "s2", 18 + GP_REG_FIRST }, \
4053 { "s3", 19 + GP_REG_FIRST }, \
4054 { "s4", 20 + GP_REG_FIRST }, \
4055 { "s5", 21 + GP_REG_FIRST }, \
4056 { "s6", 22 + GP_REG_FIRST }, \
4057 { "s7", 23 + GP_REG_FIRST }, \
4058 { "t8", 24 + GP_REG_FIRST }, \
4059 { "t9", 25 + GP_REG_FIRST }, \
4060 { "k0", 26 + GP_REG_FIRST }, \
4061 { "k1", 27 + GP_REG_FIRST }, \
4062 { "gp", 28 + GP_REG_FIRST }, \
4063 { "sp", 29 + GP_REG_FIRST }, \
4064 { "fp", 30 + GP_REG_FIRST }, \
4065 { "ra", 31 + GP_REG_FIRST }, \
4066 { "$sp", 29 + GP_REG_FIRST }, \
4067 { "$fp", 30 + GP_REG_FIRST } \
4070 /* Define results of standard character escape sequences. */
4071 #define TARGET_BELL 007
4072 #define TARGET_BS 010
4073 #define TARGET_TAB 011
4074 #define TARGET_NEWLINE 012
4075 #define TARGET_VT 013
4076 #define TARGET_FF 014
4077 #define TARGET_CR 015
4079 /* A C compound statement to output to stdio stream STREAM the
4080 assembler syntax for an instruction operand X. X is an RTL
4083 CODE is a value that can be used to specify one of several ways
4084 of printing the operand. It is used when identical operands
4085 must be printed differently depending on the context. CODE
4086 comes from the `%' specification that was used to request
4087 printing of the operand. If the specification was just `%DIGIT'
4088 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4089 is the ASCII code for LTR.
4091 If X is a register, this macro should print the register's name.
4092 The names can be found in an array `reg_names' whose type is
4093 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4095 When the machine description has a specification `%PUNCT' (a `%'
4096 followed by a punctuation character), this macro is called with
4097 a null pointer for X and the punctuation character for CODE.
4099 See mips.c for the MIPS specific codes. */
4101 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4103 /* A C expression which evaluates to true if CODE is a valid
4104 punctuation character for use in the `PRINT_OPERAND' macro. If
4105 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4106 punctuation characters (except for the standard one, `%') are
4107 used in this way. */
4109 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4111 /* A C compound statement to output to stdio stream STREAM the
4112 assembler syntax for an instruction operand that is a memory
4113 reference whose address is ADDR. ADDR is an RTL expression.
4115 On some machines, the syntax for a symbolic address depends on
4116 the section that the address refers to. On these machines,
4117 define the macro `ENCODE_SECTION_INFO' to store the information
4118 into the `symbol_ref', and then check for it here. */
4120 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4123 /* A C statement, to be executed after all slot-filler instructions
4124 have been output. If necessary, call `dbr_sequence_length' to
4125 determine the number of slots filled in a sequence (zero if not
4126 currently outputting a sequence), to decide how many no-ops to
4127 output, or whatever.
4129 Don't define this macro if it has nothing to do, but it is
4130 helpful in reading assembly output if the extent of the delay
4131 sequence is made explicit (e.g. with white space).
4133 Note that output routines for instructions with delay slots must
4134 be prepared to deal with not being output as part of a sequence
4135 (i.e. when the scheduling pass is not run, or when no slot
4136 fillers could be found.) The variable `final_sequence' is null
4137 when not processing a sequence, otherwise it contains the
4138 `sequence' rtx being output. */
4140 #define DBR_OUTPUT_SEQEND(STREAM) \
4143 if (set_nomacro > 0 && --set_nomacro == 0) \
4144 fputs ("\t.set\tmacro\n", STREAM); \
4146 if (set_noreorder > 0 && --set_noreorder == 0) \
4147 fputs ("\t.set\treorder\n", STREAM); \
4149 dslots_jump_filled++; \
4150 fputs ("\n", STREAM); \
4155 /* How to tell the debugger about changes of source files. Note, the
4156 mips ECOFF format cannot deal with changes of files inside of
4157 functions, which means the output of parser generators like bison
4158 is generally not debuggable without using the -l switch. Lose,
4159 lose, lose. Silicon graphics seems to want all .file's hardwired
4162 #ifndef SET_FILE_NUMBER
4163 #define SET_FILE_NUMBER() ++num_source_filenames
4166 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4167 mips_output_filename (STREAM, NAME)
4169 /* This is defined so that it can be overridden in iris6.h. */
4170 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4173 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4174 output_quoted_string (STREAM, NAME); \
4175 fputs ("\n", STREAM); \
4179 /* This is how to output a note the debugger telling it the line number
4180 to which the following sequence of instructions corresponds.
4181 Silicon graphics puts a label after each .loc. */
4183 #ifndef LABEL_AFTER_LOC
4184 #define LABEL_AFTER_LOC(STREAM)
4187 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4188 mips_output_lineno (STREAM, LINE)
4190 /* The MIPS implementation uses some labels for its own purpose. The
4191 following lists what labels are created, and are all formed by the
4192 pattern $L[a-z].*. The machine independent portion of GCC creates
4193 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4195 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4196 $Lb[0-9]+ Begin blocks for MIPS debug support
4197 $Lc[0-9]+ Label for use in s<xx> operation.
4198 $Le[0-9]+ End blocks for MIPS debug support
4199 $Lp\..+ Half-pic labels. */
4201 /* This is how to output the definition of a user-level label named NAME,
4202 such as the label on a static function or variable NAME.
4204 If we are optimizing the gp, remember that this label has been put
4205 out, so we know not to emit an .extern for it in mips_asm_file_end.
4206 We use one of the common bits in the IDENTIFIER tree node for this,
4207 since those bits seem to be unused, and we don't have any method
4208 of getting the decl nodes from the name. */
4210 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4212 assemble_name (STREAM, NAME); \
4213 fputs (":\n", STREAM); \
4217 /* A C statement (sans semicolon) to output to the stdio stream
4218 STREAM any text necessary for declaring the name NAME of an
4219 initialized variable which is being defined. This macro must
4220 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4221 The argument DECL is the `VAR_DECL' tree node representing the
4224 If this macro is not defined, then the variable name is defined
4225 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4227 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4230 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4231 HALF_PIC_DECLARE (NAME); \
4236 /* This is how to output a command to make the user-level label named NAME
4237 defined for reference from other files. */
4239 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4241 fputs ("\t.globl\t", STREAM); \
4242 assemble_name (STREAM, NAME); \
4243 fputs ("\n", STREAM); \
4246 /* This says how to define a global common symbol. */
4248 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
4249 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
4251 /* This says how to define a local common symbol (ie, not visible to
4254 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4255 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4258 /* This says how to output an external. It would be possible not to
4259 output anything and let undefined symbol become external. However
4260 the assembler uses length information on externals to allocate in
4261 data/sdata bss/sbss, thereby saving exec time. */
4263 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4264 mips_output_external(STREAM,DECL,NAME)
4266 /* This says what to print at the end of the assembly file */
4267 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4270 /* This is how to declare a function name. The actual work of
4271 emitting the label is moved to function_prologue, so that we can
4272 get the line number correctly emitted before the .ent directive,
4273 and after any .file directives.
4275 Also, switch files if we are optimizing the global pointer. */
4277 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4279 extern FILE *asm_out_text_file; \
4280 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4282 STREAM = asm_out_text_file; \
4283 /* ??? text_section gets called too soon. If the previous \
4284 function is in a special section and we're not, we have \
4285 to switch back to the text section. We can't call \
4286 text_section again as gcc thinks we're already there. */ \
4287 /* ??? See varasm.c. There are other things that get output \
4288 too early, like alignment (before we've switched STREAM). */ \
4289 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4290 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4293 HALF_PIC_DECLARE (NAME); \
4296 /* This is how to output an internal numbered label where
4297 PREFIX is the class of label and NUM is the number within the class. */
4299 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4300 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4302 /* This is how to store into the string LABEL
4303 the symbol_ref name of an internal numbered label where
4304 PREFIX is the class of label and NUM is the number within the class.
4305 This is suitable for output with `assemble_name'. */
4307 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4308 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4310 /* This is how to output an assembler line defining a `double' constant. */
4312 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4313 mips_output_double (STREAM, VALUE)
4316 /* This is how to output an assembler line defining a `float' constant. */
4318 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4319 mips_output_float (STREAM, VALUE)
4322 /* This is how to output an assembler line defining an `int' constant. */
4324 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4326 fprintf (STREAM, "\t.word\t"); \
4327 output_addr_const (STREAM, (VALUE)); \
4328 fprintf (STREAM, "\n"); \
4331 /* Likewise for 64 bit, `char' and `short' constants.
4333 FIXME: operand_subword can't handle some complex constant expressions
4334 that output_addr_const can (for example it does not call
4335 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4336 rely on that to avoid operand_subword for most of the cases where this
4337 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4338 or the same case with the type of 'i' changed to long long.
4342 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4344 if (TARGET_64BIT || TARGET_GAS) \
4346 fprintf (STREAM, "\t.dword\t"); \
4347 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4348 /* We can't use 'X' for negative numbers, because then we won't \
4349 get the right value for the upper 32 bits. */ \
4350 output_addr_const (STREAM, VALUE); \
4352 /* We must use 'X', because otherwise LONG_MIN will print as \
4353 a number that the Irix 6 assembler won't accept. */ \
4354 print_operand (STREAM, VALUE, 'X'); \
4355 fprintf (STREAM, "\n"); \
4359 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4360 UNITS_PER_WORD, 1); \
4361 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4362 UNITS_PER_WORD, 1); \
4366 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4368 fprintf (STREAM, "\t.half\t"); \
4369 output_addr_const (STREAM, (VALUE)); \
4370 fprintf (STREAM, "\n"); \
4373 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4375 fprintf (STREAM, "\t.byte\t"); \
4376 output_addr_const (STREAM, (VALUE)); \
4377 fprintf (STREAM, "\n"); \
4380 /* This is how to output an assembler line for a numeric constant byte. */
4382 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4383 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4385 /* This is how to output an element of a case-vector that is absolute. */
4387 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4388 fprintf (STREAM, "\t%s\t%sL%d\n", \
4389 Pmode == DImode ? ".dword" : ".word", \
4390 LOCAL_LABEL_PREFIX, \
4393 /* This is how to output an element of a case-vector that is relative.
4394 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4395 TARGET_EMBEDDED_PIC). */
4397 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4399 if (TARGET_MIPS16) \
4400 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4401 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4402 else if (TARGET_EMBEDDED_PIC) \
4403 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4404 Pmode == DImode ? ".dword" : ".word", \
4405 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4406 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4407 fprintf (STREAM, "\t%s\t%sL%d\n", \
4408 Pmode == DImode ? ".gpdword" : ".gpword", \
4409 LOCAL_LABEL_PREFIX, VALUE); \
4411 fprintf (STREAM, "\t%s\t%sL%d\n", \
4412 Pmode == DImode ? ".dword" : ".word", \
4413 LOCAL_LABEL_PREFIX, VALUE); \
4416 /* When generating embedded PIC or mips16 code we want to put the jump
4417 table in the .text section. In all other cases, we want to put the
4418 jump table in the .rdata section. Unfortunately, we can't use
4419 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4420 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4421 section if appropriate. */
4422 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4424 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4425 function_section (current_function_decl); \
4426 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4429 /* This is how to output an assembler line
4430 that says to advance the location counter
4431 to a multiple of 2**LOG bytes. */
4433 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4434 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4436 /* This is how to output an assembler line to advance the location
4437 counter by SIZE bytes. */
4439 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4440 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4442 /* This is how to output a string. */
4443 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4445 register int i, c, len = (LEN), cur_pos = 17; \
4446 register unsigned char *string = (unsigned char *)(STRING); \
4447 fprintf ((STREAM), "\t.ascii\t\""); \
4448 for (i = 0; i < len; i++) \
4450 register int c = string[i]; \
4456 putc ('\\', (STREAM)); \
4457 putc (c, (STREAM)); \
4461 case TARGET_NEWLINE: \
4462 fputs ("\\n", (STREAM)); \
4464 && (((c = string[i+1]) >= '\040' && c <= '~') \
4465 || c == TARGET_TAB)) \
4466 cur_pos = 32767; /* break right here */ \
4472 fputs ("\\t", (STREAM)); \
4477 fputs ("\\f", (STREAM)); \
4482 fputs ("\\b", (STREAM)); \
4487 fputs ("\\r", (STREAM)); \
4492 if (c >= ' ' && c < 0177) \
4494 putc (c, (STREAM)); \
4499 fprintf ((STREAM), "\\%03o", c); \
4504 if (cur_pos > 72 && i+1 < len) \
4507 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4510 fprintf ((STREAM), "\"\n"); \
4513 /* Handle certain cpp directives used in header files on sysV. */
4514 #define SCCS_DIRECTIVE
4516 /* Output #ident as a in the read-only data section. */
4517 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4520 int size = strlen (p) + 1; \
4522 assemble_string (p, size); \
4525 /* Default to -G 8 */
4526 #ifndef MIPS_DEFAULT_GVALUE
4527 #define MIPS_DEFAULT_GVALUE 8
4530 /* Define the strings to put out for each section in the object file. */
4531 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4532 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4533 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4534 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4535 #define READONLY_DATA_SECTION rdata_section
4536 #define SMALL_DATA_SECTION sdata_section
4538 /* What other sections we support other than the normal .data/.text. */
4540 #define EXTRA_SECTIONS in_sdata, in_rdata
4542 /* Define the additional functions to select our additional sections. */
4544 /* on the MIPS it is not a good idea to put constants in the text
4545 section, since this defeats the sdata/data mechanism. This is
4546 especially true when -O is used. In this case an effort is made to
4547 address with faster (gp) register relative addressing, which can
4548 only get at sdata and sbss items (there is no stext !!) However,
4549 if the constant is too large for sdata, and it's readonly, it
4550 will go into the .rdata section. */
4552 #define EXTRA_SECTION_FUNCTIONS \
4556 if (in_section != in_sdata) \
4558 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4559 in_section = in_sdata; \
4566 if (in_section != in_rdata) \
4568 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4569 in_section = in_rdata; \
4573 /* Given a decl node or constant node, choose the section to output it in
4574 and select that section. */
4576 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4578 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4581 /* Store in OUTPUT a string (made with alloca) containing
4582 an assembler-name for a local static variable named NAME.
4583 LABELNO is an integer which is different for each call. */
4585 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4586 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4587 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4589 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4592 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4593 TARGET_64BIT ? "dsubu" : "subu", \
4594 reg_names[STACK_POINTER_REGNUM], \
4595 reg_names[STACK_POINTER_REGNUM], \
4596 TARGET_64BIT ? "sd" : "sw", \
4598 reg_names[STACK_POINTER_REGNUM]); \
4602 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4605 if (! set_noreorder) \
4606 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4608 dslots_load_total++; \
4609 dslots_load_filled++; \
4610 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4611 TARGET_64BIT ? "ld" : "lw", \
4613 reg_names[STACK_POINTER_REGNUM], \
4614 TARGET_64BIT ? "daddu" : "addu", \
4615 reg_names[STACK_POINTER_REGNUM], \
4616 reg_names[STACK_POINTER_REGNUM]); \
4618 if (! set_noreorder) \
4619 fprintf (STREAM, "\t.set\treorder\n"); \
4623 /* Define the parentheses used to group arithmetic operations
4624 in assembler code. */
4626 #define ASM_OPEN_PAREN "("
4627 #define ASM_CLOSE_PAREN ")"
4629 /* How to start an assembler comment.
4630 The leading space is important (the mips native assembler requires it). */
4631 #ifndef ASM_COMMENT_START
4632 #define ASM_COMMENT_START " #"
4636 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4637 and mips-tdump.c to print them out.
4639 These must match the corresponding definitions in gdb/mipsread.c.
4640 Unfortunately, gcc and gdb do not currently share any directories. */
4642 #define CODE_MASK 0x8F300
4643 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4644 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4645 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4648 /* Default definitions for size_t and ptrdiff_t. */
4651 #define NO_BUILTIN_SIZE_TYPE
4652 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4655 #ifndef PTRDIFF_TYPE
4656 #define NO_BUILTIN_PTRDIFF_TYPE
4657 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4660 /* See mips_expand_prologue's use of loadgp for when this should be
4663 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4664 && mips_abi != ABI_32 \
4665 && mips_abi != ABI_O64)
4667 /* In mips16 mode, we need to look through the function to check for
4668 PC relative loads that are out of range. */
4669 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4671 /* We need to use a special set of functions to handle hard floating
4672 point code in mips16 mode. */
4674 #ifndef INIT_SUBTARGET_OPTABS
4675 #define INIT_SUBTARGET_OPTABS
4678 #define INIT_TARGET_OPTABS \
4681 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4682 INIT_SUBTARGET_OPTABS; \
4685 add_optab->handlers[(int) SFmode].libfunc = \
4686 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4687 sub_optab->handlers[(int) SFmode].libfunc = \
4688 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4689 smul_optab->handlers[(int) SFmode].libfunc = \
4690 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4691 flodiv_optab->handlers[(int) SFmode].libfunc = \
4692 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4694 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4695 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4696 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4697 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4698 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4699 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4701 floatsisf_libfunc = \
4702 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4704 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4706 if (TARGET_DOUBLE_FLOAT) \
4708 add_optab->handlers[(int) DFmode].libfunc = \
4709 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4710 sub_optab->handlers[(int) DFmode].libfunc = \
4711 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4712 smul_optab->handlers[(int) DFmode].libfunc = \
4713 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4714 flodiv_optab->handlers[(int) DFmode].libfunc = \
4715 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4717 extendsfdf2_libfunc = \
4718 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4719 truncdfsf2_libfunc = \
4720 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4723 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4725 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4727 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4729 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4731 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4733 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4735 floatsidf_libfunc = \
4736 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4738 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \
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