1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 /* MIPS external variables defined in mips.c. */
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
78 /* Costs of various operations on the different architectures. */
80 struct mips_rtx_cost_data
82 unsigned short fp_add;
83 unsigned short fp_mult_sf;
84 unsigned short fp_mult_df;
85 unsigned short fp_div_sf;
86 unsigned short fp_div_df;
87 unsigned short int_mult_si;
88 unsigned short int_mult_di;
89 unsigned short int_div_si;
90 unsigned short int_div_di;
91 unsigned short branch_cost;
92 unsigned short memory_latency;
95 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
96 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
97 to work on a 64-bit machine. */
105 /* Masks that affect tuning.
107 PTF_AVOID_BRANCHLIKELY
108 Set if it is usually not profitable to use branch-likely instructions
109 for this target, typically because the branches are always predicted
110 taken and so incur a large overhead when not taken. */
111 #define PTF_AVOID_BRANCHLIKELY 0x1
113 /* Information about one recognized processor. Defined here for the
114 benefit of TARGET_CPU_CPP_BUILTINS. */
115 struct mips_cpu_info {
116 /* The 'canonical' name of the processor as far as GCC is concerned.
117 It's typically a manufacturer's prefix followed by a numerical
118 designation. It should be lowercase. */
121 /* The internal processor number that most closely matches this
122 entry. Several processors can have the same value, if there's no
123 difference between them from GCC's point of view. */
124 enum processor_type cpu;
126 /* The ISA level that the processor implements. */
129 /* A mask of PTF_* values. */
130 unsigned int tune_flags;
133 /* Enumerates the setting of the -mcode-readable option. */
134 enum mips_code_readable_setting {
140 /* Macros to silence warnings about numbers being signed in traditional
141 C and unsigned in ISO C when compiled on 32-bit hosts. */
143 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
144 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
145 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
148 /* Run-time compilation parameters selecting different hardware subsets. */
150 /* True if we are generating position-independent VxWorks RTP code. */
151 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
153 /* True if the output file is marked as ".abicalls; .option pic0"
155 #define TARGET_ABICALLS_PIC0 \
156 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
158 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
159 #define TARGET_ABICALLS_PIC2 \
160 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
162 /* True if the call patterns should be split into a jalr followed by
163 an instruction to restore $gp. It is only safe to split the load
164 from the call when every use of $gp is explicit. */
166 #define TARGET_SPLIT_CALLS \
167 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
169 /* True if we're generating a form of -mabicalls in which we can use
170 operators like %hi and %lo to refer to locally-binding symbols.
171 We can only do this for -mno-shared, and only then if we can use
172 relocation operations instead of assembly macros. It isn't really
173 worth using absolute sequences for 64-bit symbols because GOT
174 accesses are so much shorter. */
176 #define TARGET_ABSOLUTE_ABICALLS \
179 && TARGET_EXPLICIT_RELOCS \
180 && !ABI_HAS_64BIT_SYMBOLS)
182 /* True if we can optimize sibling calls. For simplicity, we only
183 handle cases in which call_insn_operand will reject invalid
184 sibcall addresses. There are two cases in which this isn't true:
186 - TARGET_MIPS16. call_insn_operand accepts constant addresses
187 but there is no direct jump instruction. It isn't worth
188 using sibling calls in this case anyway; they would usually
189 be longer than normal calls.
191 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
192 accepts global constants, but all sibcalls must be indirect. */
193 #define TARGET_SIBCALLS \
194 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
196 /* True if we need to use a global offset table to access some symbols. */
197 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
199 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
200 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
202 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
203 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
205 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
206 This is true for both the PIC and non-PIC VxWorks RTP modes. */
207 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
209 /* True if .gpword or .gpdword should be used for switch tables.
211 Although GAS does understand .gpdword, the SGI linker mishandles
212 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
213 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
214 #define TARGET_GPWORD \
216 && !TARGET_ABSOLUTE_ABICALLS \
217 && !(mips_abi == ABI_64 && TARGET_IRIX))
219 /* Generate mips16 code */
220 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
221 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
222 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
223 /* Generate mips16e register save/restore sequences. */
224 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
226 /* True if we're generating a form of MIPS16 code in which general
227 text loads are allowed. */
228 #define TARGET_MIPS16_TEXT_LOADS \
229 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
231 /* True if we're generating a form of MIPS16 code in which PC-relative
232 loads are allowed. */
233 #define TARGET_MIPS16_PCREL_LOADS \
234 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
236 /* Generic ISA defines. */
237 #define ISA_MIPS1 (mips_isa == 1)
238 #define ISA_MIPS2 (mips_isa == 2)
239 #define ISA_MIPS3 (mips_isa == 3)
240 #define ISA_MIPS4 (mips_isa == 4)
241 #define ISA_MIPS32 (mips_isa == 32)
242 #define ISA_MIPS32R2 (mips_isa == 33)
243 #define ISA_MIPS64 (mips_isa == 64)
244 #define ISA_MIPS64R2 (mips_isa == 65)
246 /* Architecture target defines. */
247 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
248 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
249 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
250 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
251 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
252 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
253 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
254 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
255 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
256 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
257 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
258 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
259 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
260 || mips_arch == PROCESSOR_SB1A)
261 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
263 /* Scheduling target defines. */
264 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
265 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
266 || mips_tune == PROCESSOR_24KF2_1 \
267 || mips_tune == PROCESSOR_24KF1_1)
268 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
269 || mips_tune == PROCESSOR_74KF2_1 \
270 || mips_tune == PROCESSOR_74KF1_1 \
271 || mips_tune == PROCESSOR_74KF3_2)
272 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
273 || mips_tune == PROCESSOR_LOONGSON_2F)
274 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
275 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
276 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
277 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
278 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
279 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
280 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
281 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
282 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
283 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
284 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
285 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
286 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
287 || mips_tune == PROCESSOR_SB1A)
289 /* Whether vector modes and intrinsics for ST Microelectronics
290 Loongson-2E/2F processors should be enabled. In o32 pairs of
291 floating-point registers provide 64-bit values. */
292 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
293 && TARGET_LOONGSON_2EF)
295 /* True if the pre-reload scheduler should try to create chains of
296 multiply-add or multiply-subtract instructions. For example,
304 t1 will have a higher priority than t2 and t3 will have a higher
305 priority than t4. However, before reload, there is no dependence
306 between t1 and t3, and they can often have similar priorities.
307 The scheduler will then tend to prefer:
314 which stops us from making full use of macc/madd-style instructions.
315 This sort of situation occurs frequently in Fourier transforms and
318 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
319 queue so that chained multiply-add and multiply-subtract instructions
320 appear ahead of any other instruction that is likely to clobber lo.
321 In the example above, if t2 and t3 become ready at the same time,
322 the code ensures that t2 is scheduled first.
324 Multiply-accumulate instructions are a bigger win for some targets
325 than others, so this macro is defined on an opt-in basis. */
326 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
331 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
332 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
334 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
335 directly accessible, while the command-line options select
336 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
338 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
339 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
341 /* False if SC acts as a memory barrier with respect to itself,
342 otherwise a SYNC will be emitted after SC for atomic operations
343 that require ordering between the SC and following loads and
344 stores. It does not tell anything about ordering of loads and
345 stores prior to and following the SC, only about the SC itself and
346 those loads and stores follow it. */
347 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
349 /* IRIX specific stuff. */
350 #define TARGET_IRIX 0
351 #define TARGET_IRIX6 0
353 /* Define preprocessor macros for the -march and -mtune options.
354 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
355 processor. If INFO's canonical name is "foo", define PREFIX to
356 be "foo", and define an additional macro PREFIX_FOO. */
357 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
362 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
363 for (p = macro; *p != 0; p++) \
366 builtin_define (macro); \
367 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
372 /* Target CPU builtins. */
373 #define TARGET_CPU_CPP_BUILTINS() \
376 /* Everyone but IRIX defines this to mips. */ \
378 builtin_assert ("machine=mips"); \
380 builtin_assert ("cpu=mips"); \
381 builtin_define ("__mips__"); \
382 builtin_define ("_mips"); \
384 /* We do this here because __mips is defined below and so we \
385 can't use builtin_define_std. We don't ever want to define \
386 "mips" for VxWorks because some of the VxWorks headers \
387 construct include filenames from a root directory macro, \
388 an architecture macro and a filename, where the architecture \
389 macro expands to 'mips'. If we define 'mips' to 1, the \
390 architecture macro expands to 1 as well. */ \
391 if (!flag_iso && !TARGET_VXWORKS) \
392 builtin_define ("mips"); \
395 builtin_define ("__mips64"); \
399 /* Treat _R3000 and _R4000 like register-size \
400 defines, which is how they've historically \
404 builtin_define_std ("R4000"); \
405 builtin_define ("_R4000"); \
409 builtin_define_std ("R3000"); \
410 builtin_define ("_R3000"); \
413 if (TARGET_FLOAT64) \
414 builtin_define ("__mips_fpr=64"); \
416 builtin_define ("__mips_fpr=32"); \
418 if (mips_base_mips16) \
419 builtin_define ("__mips16"); \
422 builtin_define ("__mips3d"); \
424 if (TARGET_SMARTMIPS) \
425 builtin_define ("__mips_smartmips"); \
429 builtin_define ("__mips_dsp"); \
432 builtin_define ("__mips_dspr2"); \
433 builtin_define ("__mips_dsp_rev=2"); \
436 builtin_define ("__mips_dsp_rev=1"); \
439 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
440 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
444 builtin_define ("__mips=1"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
447 else if (ISA_MIPS2) \
449 builtin_define ("__mips=2"); \
450 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
452 else if (ISA_MIPS3) \
454 builtin_define ("__mips=3"); \
455 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
457 else if (ISA_MIPS4) \
459 builtin_define ("__mips=4"); \
460 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
462 else if (ISA_MIPS32) \
464 builtin_define ("__mips=32"); \
465 builtin_define ("__mips_isa_rev=1"); \
466 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
468 else if (ISA_MIPS32R2) \
470 builtin_define ("__mips=32"); \
471 builtin_define ("__mips_isa_rev=2"); \
472 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
474 else if (ISA_MIPS64) \
476 builtin_define ("__mips=64"); \
477 builtin_define ("__mips_isa_rev=1"); \
478 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
480 else if (ISA_MIPS64R2) \
482 builtin_define ("__mips=64"); \
483 builtin_define ("__mips_isa_rev=2"); \
484 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
490 builtin_define ("_ABIO32=1"); \
491 builtin_define ("_MIPS_SIM=_ABIO32"); \
495 builtin_define ("_ABIN32=2"); \
496 builtin_define ("_MIPS_SIM=_ABIN32"); \
500 builtin_define ("_ABI64=3"); \
501 builtin_define ("_MIPS_SIM=_ABI64"); \
505 builtin_define ("_ABIO64=4"); \
506 builtin_define ("_MIPS_SIM=_ABIO64"); \
510 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
511 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
512 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
513 builtin_define_with_int_value ("_MIPS_FPSET", \
514 32 / MAX_FPRS_PER_FMT); \
516 /* These defines reflect the ABI in use, not whether the \
517 FPU is directly accessible. */ \
518 if (TARGET_HARD_FLOAT_ABI) \
519 builtin_define ("__mips_hard_float"); \
521 builtin_define ("__mips_soft_float"); \
523 if (TARGET_SINGLE_FLOAT) \
524 builtin_define ("__mips_single_float"); \
526 if (TARGET_PAIRED_SINGLE_FLOAT) \
527 builtin_define ("__mips_paired_single_float"); \
529 if (TARGET_BIG_ENDIAN) \
531 builtin_define_std ("MIPSEB"); \
532 builtin_define ("_MIPSEB"); \
536 builtin_define_std ("MIPSEL"); \
537 builtin_define ("_MIPSEL"); \
540 /* Whether calls should go through $25. The separate __PIC__ \
541 macro indicates whether abicalls code might use a GOT. */ \
542 if (TARGET_ABICALLS) \
543 builtin_define ("__mips_abicalls"); \
545 /* Whether Loongson vector modes are enabled. */ \
546 if (TARGET_LOONGSON_VECTORS) \
547 builtin_define ("__mips_loongson_vector_rev"); \
549 /* Historical Octeon macro. */ \
551 builtin_define ("__OCTEON__"); \
553 /* Macros dependent on the C dialect. */ \
554 if (preprocessing_asm_p ()) \
556 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
557 builtin_define ("_LANGUAGE_ASSEMBLY"); \
559 else if (c_dialect_cxx ()) \
561 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
562 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
563 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
567 builtin_define_std ("LANGUAGE_C"); \
568 builtin_define ("_LANGUAGE_C"); \
570 if (c_dialect_objc ()) \
572 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
573 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
574 /* Bizarre, but needed at least for Irix. */ \
575 builtin_define_std ("LANGUAGE_C"); \
576 builtin_define ("_LANGUAGE_C"); \
579 if (mips_abi == ABI_EABI) \
580 builtin_define ("__mips_eabi"); \
582 if (TARGET_CACHE_BUILTIN) \
583 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
587 /* Default target_flags if no switches are specified */
589 #ifndef TARGET_DEFAULT
590 #define TARGET_DEFAULT 0
593 #ifndef TARGET_CPU_DEFAULT
594 #define TARGET_CPU_DEFAULT 0
597 #ifndef TARGET_ENDIAN_DEFAULT
598 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
601 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
602 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
605 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
606 #ifndef MIPS_ISA_DEFAULT
607 #ifndef MIPS_CPU_STRING_DEFAULT
608 #define MIPS_CPU_STRING_DEFAULT "from-abi"
614 /* Make this compile time constant for libgcc2 */
616 #define TARGET_64BIT 1
618 #define TARGET_64BIT 0
620 #endif /* IN_LIBGCC2 */
622 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
623 when compiled with hardware floating point. This is because MIPS16
624 code cannot save and restore the floating-point registers, which is
625 important if in a mixed MIPS16/non-MIPS16 environment. */
628 #if __mips_hard_float
629 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
631 #endif /* IN_LIBGCC2 */
633 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
635 #ifndef MULTILIB_ENDIAN_DEFAULT
636 #if TARGET_ENDIAN_DEFAULT == 0
637 #define MULTILIB_ENDIAN_DEFAULT "EL"
639 #define MULTILIB_ENDIAN_DEFAULT "EB"
643 #ifndef MULTILIB_ISA_DEFAULT
644 # if MIPS_ISA_DEFAULT == 1
645 # define MULTILIB_ISA_DEFAULT "mips1"
647 # if MIPS_ISA_DEFAULT == 2
648 # define MULTILIB_ISA_DEFAULT "mips2"
650 # if MIPS_ISA_DEFAULT == 3
651 # define MULTILIB_ISA_DEFAULT "mips3"
653 # if MIPS_ISA_DEFAULT == 4
654 # define MULTILIB_ISA_DEFAULT "mips4"
656 # if MIPS_ISA_DEFAULT == 32
657 # define MULTILIB_ISA_DEFAULT "mips32"
659 # if MIPS_ISA_DEFAULT == 33
660 # define MULTILIB_ISA_DEFAULT "mips32r2"
662 # if MIPS_ISA_DEFAULT == 64
663 # define MULTILIB_ISA_DEFAULT "mips64"
665 # if MIPS_ISA_DEFAULT == 65
666 # define MULTILIB_ISA_DEFAULT "mips64r2"
668 # define MULTILIB_ISA_DEFAULT "mips1"
679 #ifndef MIPS_ABI_DEFAULT
680 #define MIPS_ABI_DEFAULT ABI_32
683 /* Use the most portable ABI flag for the ASM specs. */
685 #if MIPS_ABI_DEFAULT == ABI_32
686 #define MULTILIB_ABI_DEFAULT "mabi=32"
689 #if MIPS_ABI_DEFAULT == ABI_O64
690 #define MULTILIB_ABI_DEFAULT "mabi=o64"
693 #if MIPS_ABI_DEFAULT == ABI_N32
694 #define MULTILIB_ABI_DEFAULT "mabi=n32"
697 #if MIPS_ABI_DEFAULT == ABI_64
698 #define MULTILIB_ABI_DEFAULT "mabi=64"
701 #if MIPS_ABI_DEFAULT == ABI_EABI
702 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
705 #ifndef MULTILIB_DEFAULTS
706 #define MULTILIB_DEFAULTS \
707 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
710 /* We must pass -EL to the linker by default for little endian embedded
711 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
712 linker will default to using big-endian output files. The OUTPUT_FORMAT
713 line must be in the linker script, otherwise -EB/-EL will not work. */
716 #if TARGET_ENDIAN_DEFAULT == 0
717 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
719 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
723 /* A spec condition that matches all non-mips16 -mips arguments. */
725 #define MIPS_ISA_LEVEL_OPTION_SPEC \
726 "mips1|mips2|mips3|mips4|mips32*|mips64*"
728 /* A spec condition that matches all non-mips16 architecture arguments. */
730 #define MIPS_ARCH_OPTION_SPEC \
731 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
733 /* A spec that infers a -mips argument from an -march argument,
734 or injects the default if no architecture is specified. */
736 #define MIPS_ISA_LEVEL_SPEC \
737 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
738 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
739 %{march=mips2|march=r6000:-mips2} \
740 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
741 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
742 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
743 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
744 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
745 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
746 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
747 |march=xlr: -mips64} \
748 %{march=mips64r2|march=octeon: -mips64r2} \
749 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
751 /* A spec that infers a -mhard-float or -msoft-float setting from an
752 -march argument. Note that soft-float and hard-float code are not
755 #define MIPS_ARCH_FLOAT_SPEC \
756 "%{mhard-float|msoft-float|march=mips*:; \
757 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
758 |march=34kc|march=74kc|march=1004kc|march=5kc \
759 |march=octeon|march=xlr: -msoft-float; \
760 march=*: -mhard-float}"
762 /* A spec condition that matches 32-bit options. It only works if
763 MIPS_ISA_LEVEL_SPEC has been applied. */
765 #define MIPS_32BIT_OPTION_SPEC \
766 "mips1|mips2|mips32*|mgp32"
768 #if MIPS_ABI_DEFAULT == ABI_O64 \
769 || MIPS_ABI_DEFAULT == ABI_N32 \
770 || MIPS_ABI_DEFAULT == ABI_64
771 #define OPT_ARCH64 "mabi=32|mgp32:;"
772 #define OPT_ARCH32 "mabi=32|mgp32"
774 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
775 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
778 /* Support for a compile-time default CPU, et cetera. The rules are:
779 --with-arch is ignored if -march is specified or a -mips is specified
780 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
781 --with-tune is ignored if -mtune is specified; likewise
782 --with-tune-32 and --with-tune-64.
783 --with-abi is ignored if -mabi is specified.
784 --with-float is ignored if -mhard-float or -msoft-float are
786 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
788 #define OPTION_DEFAULT_SPECS \
789 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
790 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
791 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
792 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
793 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
794 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
795 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
796 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
797 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
798 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
799 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
800 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
803 /* A spec that infers the -mdsp setting from an -march argument. */
804 #define BASE_DRIVER_SELF_SPECS \
805 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*|march=1004k*: -mdsp}}"
807 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
809 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
810 && ISA_HAS_COND_TRAP)
812 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
814 /* True if the ABI can only work with 64-bit integer registers. We
815 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
816 otherwise floating-point registers must also be 64-bit. */
817 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
819 /* Likewise for 32-bit regs. */
820 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
822 /* True if the file format uses 64-bit symbols. At present, this is
823 only true for n64, which uses 64-bit ELF. */
824 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
826 /* True if symbols are 64 bits wide. This is usually determined by
827 the ABI's file format, but it can be overridden by -msym32. Note that
828 overriding the size with -msym32 changes the ABI of relocatable objects,
829 although it doesn't change the ABI of a fully-linked object. */
830 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
832 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
833 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
838 /* ISA has branch likely instructions (e.g. mips2). */
839 /* Disable branchlikely for tx39 until compare rewrite. They haven't
840 been generated up to this point. */
841 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
843 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
844 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
856 /* ISA has a three-operand multiplication instruction. */
857 #define ISA_HAS_DMUL3 (TARGET_64BIT \
861 /* ISA has the floating-point conditional move instructions introduced
863 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
868 && !TARGET_MIPS5500 \
871 /* ISA has the integer conditional move instructions introduced in mips4 and
872 ST Loongson 2E/2F. */
873 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
875 /* ISA has LDC1 and SDC1. */
876 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
878 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
879 branch on CC, and move (both FP and non-FP) on CC. */
880 #define ISA_HAS_8CC (ISA_MIPS4 \
886 /* This is a catch all for other mips4 instructions: indexed load, the
887 FP madd and msub instructions, and the FP recip and recip sqrt
889 #define ISA_HAS_FP4 ((ISA_MIPS4 \
890 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
895 /* ISA has paired-single instructions. */
896 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
898 /* ISA has conditional trap instructions. */
899 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
902 /* ISA has integer multiply-accumulate instructions, madd and msub. */
903 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
909 /* Integer multiply-accumulate instructions should be generated. */
910 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
912 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
913 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
915 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
916 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
918 /* ISA has floating-point nmadd and nmsub instructions
919 'd = -((a * b) [+-] c)'. */
920 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
922 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
925 && (!TARGET_MIPS5400 || TARGET_MAD) \
928 /* ISA has floating-point nmadd and nmsub instructions
929 'c = -((a * b) [+-] c)'. */
930 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
933 /* ISA has count leading zeroes/ones instruction (not implemented). */
934 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
940 /* ISA has three operand multiply instructions that put
941 the high part in an accumulator: mulhi or mulhiu. */
942 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
947 /* ISA has three operand multiply instructions that
948 negates the result and puts the result in an accumulator. */
949 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
954 /* ISA has three operand multiply instructions that subtracts the
955 result from a 4th operand and puts the result in an accumulator. */
956 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
961 /* ISA has three operand multiply instructions that the result
962 from a 4th operand and puts the result in an accumulator. */
963 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
970 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
971 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
972 || TARGET_MIPS4130) \
975 /* ISA has the "ror" (rotate right) instructions. */
976 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
981 || TARGET_SMARTMIPS) \
984 /* ISA has data prefetch instructions. This controls use of 'pref'. */
985 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
986 || TARGET_LOONGSON_2EF \
993 /* ISA has data indexed prefetch instructions. This controls use of
994 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
995 (prefx is a cop1x instruction, so can only be used if FP is
997 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
1003 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1004 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1005 also requires TARGET_DOUBLE_FLOAT. */
1006 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1008 /* ISA includes the MIPS32r2 seb and seh instructions. */
1009 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
1013 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1014 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
1018 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1019 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1023 /* ISA has lwxs instruction (load w/scaled index address. */
1024 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
1026 /* The DSP ASE is available. */
1027 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1029 /* Revision 2 of the DSP ASE is available. */
1030 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1032 /* True if the result of a load is not available to the next instruction.
1033 A nop will then be needed between instructions like "lw $4,..."
1034 and "addiu $4,$4,1". */
1035 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1036 && !TARGET_MIPS3900 \
1039 /* Likewise mtc1 and mfc1. */
1040 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1041 && !TARGET_LOONGSON_2EF)
1043 /* Likewise floating-point comparisons. */
1044 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1045 && !TARGET_LOONGSON_2EF)
1047 /* True if mflo and mfhi can be immediately followed by instructions
1048 which write to the HI and LO registers.
1050 According to MIPS specifications, MIPS ISAs I, II, and III need
1051 (at least) two instructions between the reads of HI/LO and
1052 instructions which write them, and later ISAs do not. Contradicting
1053 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1054 the UM for the NEC Vr5000) document needing the instructions between
1055 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1056 MIPS64 and later ISAs to have the interlocks, plus any specific
1057 earlier-ISA CPUs for which CPU documentation declares that the
1058 instructions are really interlocked. */
1059 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1063 || TARGET_MIPS5500 \
1064 || TARGET_LOONGSON_2EF)
1066 /* ISA includes synci, jr.hb and jalr.hb. */
1067 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1071 /* ISA includes sync. */
1072 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1073 #define GENERATE_SYNC \
1074 (target_flags_explicit & MASK_LLSC \
1075 ? TARGET_LLSC && !TARGET_MIPS16 \
1078 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1079 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1081 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1082 #define GENERATE_LL_SC \
1083 (target_flags_explicit & MASK_LLSC \
1084 ? TARGET_LLSC && !TARGET_MIPS16 \
1087 /* ISA includes the baddu instruction. */
1088 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1090 /* ISA includes the bbit* instructions. */
1091 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1093 /* ISA includes the cins instruction. */
1094 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1096 /* ISA includes the exts instruction. */
1097 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1099 /* ISA includes the seq and sne instructions. */
1100 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1102 /* ISA includes the pop instruction. */
1103 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1105 /* The CACHE instruction is available in non-MIPS16 code. */
1106 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1108 /* The CACHE instruction is available. */
1109 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1111 /* Add -G xx support. */
1113 #undef SWITCH_TAKES_ARG
1114 #define SWITCH_TAKES_ARG(CHAR) \
1115 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1117 #define OVERRIDE_OPTIONS mips_override_options ()
1119 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1121 /* Show we can debug even without a frame pointer. */
1122 #define CAN_DEBUG_WITHOUT_FP
1124 /* Tell collect what flags to pass to nm. */
1126 #define NM_FLAGS "-Bn"
1130 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1131 to the assembler. It may be overridden by subtargets. */
1132 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1133 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1135 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1138 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1139 the assembler. It may be overridden by subtargets.
1141 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1142 COFF debugging info. */
1144 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1145 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1146 %{g} %{g0} %{g1} %{g2} %{g3} \
1147 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1148 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1149 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1150 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1151 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1154 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1155 overridden by subtargets. */
1157 #ifndef SUBTARGET_ASM_SPEC
1158 #define SUBTARGET_ASM_SPEC ""
1163 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1164 %{mips32*} %{mips64*} \
1165 %{mips16} %{mno-mips16:-no-mips16} \
1166 %{mips3d} %{mno-mips3d:-no-mips3d} \
1167 %{mdmx} %{mno-mdmx:-no-mdmx} \
1168 %{mdsp} %{mno-dsp} \
1169 %{mdspr2} %{mno-dspr2} \
1170 %{msmartmips} %{mno-smartmips} \
1172 %{mfix-vr4120} %{mfix-vr4130} \
1173 %(subtarget_asm_optimizing_spec) \
1174 %(subtarget_asm_debugging_spec) \
1175 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1176 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1178 %{mshared} %{mno-shared} \
1179 %{msym32} %{mno-sym32} \
1181 %(subtarget_asm_spec)"
1183 /* Extra switches sometimes passed to the linker. */
1184 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1185 will interpret it as a -b option. */
1188 #define LINK_SPEC "\
1190 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1191 %{bestGnum} %{shared} %{non_shared}"
1192 #endif /* LINK_SPEC defined */
1195 /* Specs for the compiler proper */
1197 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1198 overridden by subtargets. */
1199 #ifndef SUBTARGET_CC1_SPEC
1200 #define SUBTARGET_CC1_SPEC ""
1203 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1207 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1208 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1210 %(subtarget_cc1_spec)"
1212 /* Preprocessor specs. */
1214 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1215 overridden by subtargets. */
1216 #ifndef SUBTARGET_CPP_SPEC
1217 #define SUBTARGET_CPP_SPEC ""
1220 #define CPP_SPEC "%(subtarget_cpp_spec)"
1222 /* This macro defines names of additional specifications to put in the specs
1223 that can be used in various specifications like CC1_SPEC. Its definition
1224 is an initializer with a subgrouping for each command option.
1226 Each subgrouping contains a string constant, that defines the
1227 specification name, and a string constant that used by the GCC driver
1230 Do not define this macro if it does not need to do anything. */
1232 #define EXTRA_SPECS \
1233 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1234 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1235 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1236 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1237 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1238 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1239 { "endian_spec", ENDIAN_SPEC }, \
1240 SUBTARGET_EXTRA_SPECS
1242 #ifndef SUBTARGET_EXTRA_SPECS
1243 #define SUBTARGET_EXTRA_SPECS
1246 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1247 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1249 #ifndef PREFERRED_DEBUGGING_TYPE
1250 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1253 /* The size of DWARF addresses should be the same as the size of symbols
1254 in the target file format. They shouldn't depend on things like -msym32,
1255 because many DWARF consumers do not allow the mixture of address sizes
1256 that one would then get from linking -msym32 code with -msym64 code.
1258 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1259 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1260 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1262 /* By default, turn on GDB extensions. */
1263 #define DEFAULT_GDB_EXTENSIONS 1
1265 /* Local compiler-generated symbols must have a prefix that the assembler
1266 understands. By default, this is $, although some targets (e.g.,
1267 NetBSD-ELF) need to override this. */
1269 #ifndef LOCAL_LABEL_PREFIX
1270 #define LOCAL_LABEL_PREFIX "$"
1273 /* By default on the mips, external symbols do not have an underscore
1274 prepended, but some targets (e.g., NetBSD) require this. */
1276 #ifndef USER_LABEL_PREFIX
1277 #define USER_LABEL_PREFIX ""
1280 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1281 since the length can run past this up to a continuation point. */
1282 #undef DBX_CONTIN_LENGTH
1283 #define DBX_CONTIN_LENGTH 1500
1285 /* How to renumber registers for dbx and gdb. */
1286 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1288 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1289 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1291 /* The DWARF 2 CFA column which tracks the return address. */
1292 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1294 /* Before the prologue, RA lives in r31. */
1295 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1297 /* Describe how we implement __builtin_eh_return. */
1298 #define EH_RETURN_DATA_REGNO(N) \
1299 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1301 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1303 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1304 The default for this in 64-bit mode is 8, which causes problems with
1305 SFmode register saves. */
1306 #define DWARF_CIE_DATA_ALIGNMENT -4
1308 /* Correct the offset of automatic variables and arguments. Note that
1309 the MIPS debug format wants all automatic variables and arguments
1310 to be in terms of the virtual frame pointer (stack pointer before
1311 any adjustment in the function), while the MIPS 3.0 linker wants
1312 the frame pointer to be the stack pointer after the initial
1315 #define DEBUGGER_AUTO_OFFSET(X) \
1316 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1317 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1318 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1320 /* Target machine storage layout */
1322 #define BITS_BIG_ENDIAN 0
1323 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1324 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1326 /* Define this to set the endianness to use in libgcc2.c, which can
1327 not depend on target_flags. */
1328 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1329 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1331 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1334 #define MAX_BITS_PER_WORD 64
1336 /* Width of a word, in units (bytes). */
1337 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1339 #define MIN_UNITS_PER_WORD 4
1342 /* For MIPS, width of a floating point register. */
1343 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1345 /* The number of consecutive floating-point registers needed to store the
1346 largest format supported by the FPU. */
1347 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1349 /* The number of consecutive floating-point registers needed to store the
1350 smallest format supported by the FPU. */
1351 #define MIN_FPRS_PER_FMT \
1352 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1353 ? 1 : MAX_FPRS_PER_FMT)
1355 /* The largest size of value that can be held in floating-point
1356 registers and moved with a single instruction. */
1357 #define UNITS_PER_HWFPVALUE \
1358 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1360 /* The largest size of value that can be held in floating-point
1362 #define UNITS_PER_FPVALUE \
1363 (TARGET_SOFT_FLOAT_ABI ? 0 \
1364 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1365 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1367 /* The number of bytes in a double. */
1368 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1370 #define UNITS_PER_SIMD_WORD(MODE) \
1371 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1373 /* Set the sizes of the core types. */
1374 #define SHORT_TYPE_SIZE 16
1375 #define INT_TYPE_SIZE 32
1376 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1377 #define LONG_LONG_TYPE_SIZE 64
1379 #define FLOAT_TYPE_SIZE 32
1380 #define DOUBLE_TYPE_SIZE 64
1381 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1383 /* Define the sizes of fixed-point types. */
1384 #define SHORT_FRACT_TYPE_SIZE 8
1385 #define FRACT_TYPE_SIZE 16
1386 #define LONG_FRACT_TYPE_SIZE 32
1387 #define LONG_LONG_FRACT_TYPE_SIZE 64
1389 #define SHORT_ACCUM_TYPE_SIZE 16
1390 #define ACCUM_TYPE_SIZE 32
1391 #define LONG_ACCUM_TYPE_SIZE 64
1392 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1393 doesn't support 128-bit integers for MIPS32 currently. */
1394 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1396 /* long double is not a fixed mode, but the idea is that, if we
1397 support long double, we also want a 128-bit integer type. */
1398 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1401 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1402 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1403 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1405 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1409 /* Width in bits of a pointer. */
1410 #ifndef POINTER_SIZE
1411 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1414 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1415 #define PARM_BOUNDARY BITS_PER_WORD
1417 /* Allocation boundary (in *bits*) for the code of a function. */
1418 #define FUNCTION_BOUNDARY 32
1420 /* Alignment of field after `int : 0' in a structure. */
1421 #define EMPTY_FIELD_BOUNDARY 32
1423 /* Every structure's size must be a multiple of this. */
1424 /* 8 is observed right on a DECstation and on riscos 4.02. */
1425 #define STRUCTURE_SIZE_BOUNDARY 8
1427 /* There is no point aligning anything to a rounder boundary than this. */
1428 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1430 /* All accesses must be aligned. */
1431 #define STRICT_ALIGNMENT 1
1433 /* Define this if you wish to imitate the way many other C compilers
1434 handle alignment of bitfields and the structures that contain
1437 The behavior is that the type written for a bit-field (`int',
1438 `short', or other integer type) imposes an alignment for the
1439 entire structure, as if the structure really did contain an
1440 ordinary field of that type. In addition, the bit-field is placed
1441 within the structure so that it would fit within such a field,
1442 not crossing a boundary for it.
1444 Thus, on most machines, a bit-field whose type is written as `int'
1445 would not cross a four-byte boundary, and would force four-byte
1446 alignment for the whole structure. (The alignment used may not
1447 be four bytes; it is controlled by the other alignment
1450 If the macro is defined, its definition should be a C expression;
1451 a nonzero value for the expression enables this behavior. */
1453 #define PCC_BITFIELD_TYPE_MATTERS 1
1455 /* If defined, a C expression to compute the alignment given to a
1456 constant that is being placed in memory. CONSTANT is the constant
1457 and ALIGN is the alignment that the object would ordinarily have.
1458 The value of this macro is used instead of that alignment to align
1461 If this macro is not defined, then ALIGN is used.
1463 The typical use of this macro is to increase alignment for string
1464 constants to be word aligned so that `strcpy' calls that copy
1465 constants can be done inline. */
1467 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1468 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1469 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1471 /* If defined, a C expression to compute the alignment for a static
1472 variable. TYPE is the data type, and ALIGN is the alignment that
1473 the object would ordinarily have. The value of this macro is used
1474 instead of that alignment to align the object.
1476 If this macro is not defined, then ALIGN is used.
1478 One use of this macro is to increase alignment of medium-size
1479 data to make it all fit in fewer cache lines. Another is to
1480 cause character arrays to be word-aligned so that `strcpy' calls
1481 that copy constants to character arrays can be done inline. */
1483 #undef DATA_ALIGNMENT
1484 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1485 ((((ALIGN) < BITS_PER_WORD) \
1486 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1487 || TREE_CODE (TYPE) == UNION_TYPE \
1488 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1490 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1491 character arrays to be word-aligned so that `strcpy' calls that copy
1492 constants to character arrays can be done inline, and 'strcmp' can be
1493 optimised to use word loads. */
1494 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1495 DATA_ALIGNMENT (TYPE, ALIGN)
1497 #define PAD_VARARGS_DOWN \
1498 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1500 /* Define if operations between registers always perform the operation
1501 on the full register even if a narrower mode is specified. */
1502 #define WORD_REGISTER_OPERATIONS
1504 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1505 moves. All other references are zero extended. */
1506 #define LOAD_EXTEND_OP(MODE) \
1507 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1508 ? SIGN_EXTEND : ZERO_EXTEND)
1510 /* Define this macro if it is advisable to hold scalars in registers
1511 in a wider mode than that declared by the program. In such cases,
1512 the value is constrained to be within the bounds of the declared
1513 type, but kept valid in the wider mode. The signedness of the
1514 extension may differ from that of the type. */
1516 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1517 if (GET_MODE_CLASS (MODE) == MODE_INT \
1518 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1520 if ((MODE) == SImode) \
1525 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1526 Extensions of pointers to word_mode must be signed. */
1527 #define POINTERS_EXTEND_UNSIGNED false
1529 /* Define if loading short immediate values into registers sign extends. */
1530 #define SHORT_IMMEDIATES_SIGN_EXTEND
1532 /* The [d]clz instructions have the natural values at 0. */
1534 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1535 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1537 /* Standard register usage. */
1539 /* Number of hardware registers. We have:
1541 - 32 integer registers
1542 - 32 floating point registers
1543 - 8 condition code registers
1544 - 2 accumulator registers (hi and lo)
1545 - 32 registers each for coprocessors 0, 2 and 3
1547 - ARG_POINTER_REGNUM
1548 - FRAME_POINTER_REGNUM
1549 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1550 - 3 dummy entries that were used at various times in the past.
1551 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1552 - 6 DSP control registers */
1554 #define FIRST_PSEUDO_REGISTER 188
1556 /* By default, fix the kernel registers ($26 and $27), the global
1557 pointer ($28) and the stack pointer ($29). This can change
1558 depending on the command-line options.
1560 Regarding coprocessor registers: without evidence to the contrary,
1561 it's best to assume that each coprocessor register has a unique
1562 use. This can be overridden, in, e.g., mips_override_options or
1563 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1564 for a particular target. */
1566 #define FIXED_REGISTERS \
1568 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1570 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1572 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1573 /* COP0 registers */ \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 /* COP2 registers */ \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1579 /* COP3 registers */ \
1580 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 /* 6 DSP accumulator registers & 6 control registers */ \
1583 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1587 /* Set up this array for o32 by default.
1589 Note that we don't mark $31 as a call-clobbered register. The idea is
1590 that it's really the call instructions themselves which clobber $31.
1591 We don't care what the called function does with it afterwards.
1593 This approach makes it easier to implement sibcalls. Unlike normal
1594 calls, sibcalls don't clobber $31, so the register reaches the
1595 called function in tact. EPILOGUE_USES says that $31 is useful
1596 to the called function. */
1598 #define CALL_USED_REGISTERS \
1600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1601 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1603 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1605 /* COP0 registers */ \
1606 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1608 /* COP2 registers */ \
1609 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1610 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1611 /* COP3 registers */ \
1612 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1613 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1614 /* 6 DSP accumulator registers & 6 control registers */ \
1615 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1619 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1621 #define CALL_REALLY_USED_REGISTERS \
1622 { /* General registers. */ \
1623 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1624 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1625 /* Floating-point registers. */ \
1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1627 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1629 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1630 /* COP0 registers */ \
1631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1632 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1633 /* COP2 registers */ \
1634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1636 /* COP3 registers */ \
1637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1639 /* 6 DSP accumulator registers & 6 control registers */ \
1640 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1643 /* Internal macros to classify a register number as to whether it's a
1644 general purpose register, a floating point register, a
1645 multiply/divide register, or a status register. */
1647 #define GP_REG_FIRST 0
1648 #define GP_REG_LAST 31
1649 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1650 #define GP_DBX_FIRST 0
1651 #define K0_REG_NUM (GP_REG_FIRST + 26)
1652 #define K1_REG_NUM (GP_REG_FIRST + 27)
1653 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1655 #define FP_REG_FIRST 32
1656 #define FP_REG_LAST 63
1657 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1658 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1660 #define MD_REG_FIRST 64
1661 #define MD_REG_LAST 65
1662 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1663 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1665 /* The DWARF 2 CFA column which tracks the return address from a
1666 signal handler context. This means that to maintain backwards
1667 compatibility, no hard register can be assigned this column if it
1668 would need to be handled by the DWARF unwinder. */
1669 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1671 #define ST_REG_FIRST 67
1672 #define ST_REG_LAST 74
1673 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1676 /* FIXME: renumber. */
1677 #define COP0_REG_FIRST 80
1678 #define COP0_REG_LAST 111
1679 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1681 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1682 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1683 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1685 #define COP2_REG_FIRST 112
1686 #define COP2_REG_LAST 143
1687 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1689 #define COP3_REG_FIRST 144
1690 #define COP3_REG_LAST 175
1691 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1692 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1693 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1695 #define DSP_ACC_REG_FIRST 176
1696 #define DSP_ACC_REG_LAST 181
1697 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1699 #define AT_REGNUM (GP_REG_FIRST + 1)
1700 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1701 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1703 /* A few bitfield locations for the coprocessor registers. */
1704 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1705 the cause register for the EIC interrupt mode. */
1706 #define CAUSE_IPL 10
1707 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1709 /* Exception Level is at bit 1 of the status register. */
1711 /* Interrupt Enable is at bit 0 of the status register. */
1714 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1715 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1716 should be used instead. */
1717 #define FPSW_REGNUM ST_REG_FIRST
1719 #define GP_REG_P(REGNO) \
1720 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1721 #define M16_REG_P(REGNO) \
1722 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1723 #define FP_REG_P(REGNO) \
1724 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1725 #define MD_REG_P(REGNO) \
1726 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1727 #define ST_REG_P(REGNO) \
1728 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1729 #define COP0_REG_P(REGNO) \
1730 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1731 #define COP2_REG_P(REGNO) \
1732 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1733 #define COP3_REG_P(REGNO) \
1734 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1735 #define ALL_COP_REG_P(REGNO) \
1736 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1737 /* Test if REGNO is one of the 6 new DSP accumulators. */
1738 #define DSP_ACC_REG_P(REGNO) \
1739 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1740 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1741 #define ACC_REG_P(REGNO) \
1742 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1744 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1746 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1747 to initialize the mips16 gp pseudo register. */
1748 #define CONST_GP_P(X) \
1749 (GET_CODE (X) == CONST \
1750 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1751 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1753 /* Return coprocessor number from register number. */
1755 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1756 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1757 : COP3_REG_P (REGNO) ? '3' : '?')
1760 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1762 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1763 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1765 #define MODES_TIEABLE_P mips_modes_tieable_p
1767 /* Register to use for pushing function arguments. */
1768 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1770 /* These two registers don't really exist: they get eliminated to either
1771 the stack or hard frame pointer. */
1772 #define ARG_POINTER_REGNUM 77
1773 #define FRAME_POINTER_REGNUM 78
1775 /* $30 is not available on the mips16, so we use $17 as the frame
1777 #define HARD_FRAME_POINTER_REGNUM \
1778 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1780 /* Register in which static-chain is passed to a function. */
1781 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1783 /* Registers used as temporaries in prologue/epilogue code:
1785 - If a MIPS16 PIC function needs access to _gp, it first loads
1786 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1788 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1789 register. The register must not conflict with MIPS16_PIC_TEMP.
1791 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1794 If we're generating MIPS16 code, these registers must come from the
1795 core set of 8. The prologue registers mustn't conflict with any
1796 incoming arguments, the static chain pointer, or the frame pointer.
1797 The epilogue temporary mustn't conflict with the return registers,
1798 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1799 or the EH data registers.
1801 If we're generating interrupt handlers, we use K0 as a temporary register
1802 in prologue/epilogue code. */
1804 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1805 #define MIPS_PROLOGUE_TEMP_REGNUM \
1806 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1807 #define MIPS_EPILOGUE_TEMP_REGNUM \
1808 (cfun->machine->interrupt_handler_p \
1810 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1812 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1813 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1814 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1816 /* Define this macro if it is as good or better to call a constant
1817 function address than to call an address kept in a register. */
1818 #define NO_FUNCTION_CSE 1
1820 /* The ABI-defined global pointer. Sometimes we use a different
1821 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1822 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1824 /* We normally use $28 as the global pointer. However, when generating
1825 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1826 register instead. They can then avoid saving and restoring $28
1827 and perhaps avoid using a frame at all.
1829 When a leaf function uses something other than $28, mips_expand_prologue
1830 will modify pic_offset_table_rtx in place. Take the register number
1831 from there after reload. */
1832 #define PIC_OFFSET_TABLE_REGNUM \
1833 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1835 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1837 /* Define the classes of registers for register constraints in the
1838 machine description. Also define ranges of constants.
1840 One of the classes must always be named ALL_REGS and include all hard regs.
1841 If there is more than one class, another class must be named NO_REGS
1842 and contain no registers.
1844 The name GENERAL_REGS must be the name of a class (or an alias for
1845 another name such as ALL_REGS). This is the class of registers
1846 that is allowed by "g" or "r" in a register constraint.
1847 Also, registers outside this class are allocated only when
1848 instructions express preferences for them.
1850 The classes must be numbered in nondecreasing order; that is,
1851 a larger-numbered class must never be contained completely
1852 in a smaller-numbered class.
1854 For any two classes, it is very desirable that there be another
1855 class that represents their union. */
1859 NO_REGS, /* no registers in set */
1860 M16_REGS, /* mips16 directly accessible registers */
1861 T_REG, /* mips16 T register ($24) */
1862 M16_T_REGS, /* mips16 registers plus T register */
1863 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1864 V1_REG, /* Register $v1 ($3) used for TLS access. */
1865 LEA_REGS, /* Every GPR except $25 */
1866 GR_REGS, /* integer registers */
1867 FP_REGS, /* floating point registers */
1868 MD0_REG, /* first multiply/divide register */
1869 MD1_REG, /* second multiply/divide register */
1870 MD_REGS, /* multiply/divide registers (hi/lo) */
1871 COP0_REGS, /* generic coprocessor classes */
1874 ST_REGS, /* status registers (fp status) */
1875 DSP_ACC_REGS, /* DSP accumulator registers */
1876 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1877 FRAME_REGS, /* $arg and $frame */
1878 GR_AND_MD0_REGS, /* union classes */
1882 ALL_REGS, /* all registers */
1883 LIM_REG_CLASSES /* max value + 1 */
1886 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1888 #define GENERAL_REGS GR_REGS
1890 /* An initializer containing the names of the register classes as C
1891 string constants. These names are used in writing some of the
1894 #define REG_CLASS_NAMES \
1900 "PIC_FN_ADDR_REG", \
1908 /* coprocessor registers */ \
1916 "GR_AND_MD0_REGS", \
1917 "GR_AND_MD1_REGS", \
1919 "GR_AND_ACC_REGS", \
1923 /* An initializer containing the contents of the register classes,
1924 as integers which are bit masks. The Nth integer specifies the
1925 contents of class N. The way the integer MASK is interpreted is
1926 that register R is in the class if `MASK & (1 << R)' is 1.
1928 When the machine has more than 32 registers, an integer does not
1929 suffice. Then the integers are replaced by sub-initializers,
1930 braced groupings containing several integers. Each
1931 sub-initializer must be suitable as an initializer for the type
1932 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1934 #define REG_CLASS_CONTENTS \
1936 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1937 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1938 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1939 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1940 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1941 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1942 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1943 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1944 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1945 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1946 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1947 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1948 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1949 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1950 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1951 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1952 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1953 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1954 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1955 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1956 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1957 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1958 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1959 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1963 /* A C expression whose value is a register class containing hard
1964 register REGNO. In general there is more that one such class;
1965 choose a class which is "minimal", meaning that no smaller class
1966 also contains the register. */
1968 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1970 /* A macro whose definition is the name of the class to which a
1971 valid base register must belong. A base register is one used in
1972 an address which is the register value plus a displacement. */
1974 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1976 /* A macro whose definition is the name of the class to which a
1977 valid index register must belong. An index register is one used
1978 in an address where its value is either multiplied by a scale
1979 factor or added to another register (as well as added to a
1982 #define INDEX_REG_CLASS NO_REGS
1984 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1985 registers explicitly used in the rtl to be used as spill registers
1986 but prevents the compiler from extending the lifetime of these
1989 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1991 /* We generally want to put call-clobbered registers ahead of
1992 call-saved ones. (IRA expects this.) */
1994 #define REG_ALLOC_ORDER \
1995 { /* Accumulator registers. When GPRs and accumulators have equal \
1996 cost, we generally prefer to use accumulators. For example, \
1997 a division of multiplication result is better allocated to LO, \
1998 so that we put the MFLO at the point of use instead of at the \
1999 point of definition. It's also needed if we're to take advantage \
2000 of the extra accumulators available with -mdspr2. In some cases, \
2001 it can also help to reduce register pressure. */ \
2002 64, 65,176,177,178,179,180,181, \
2003 /* Call-clobbered GPRs. */ \
2004 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2006 /* The global pointer. This is call-clobbered for o32 and o64 \
2007 abicalls, call-saved for n32 and n64 abicalls, and a program \
2008 invariant otherwise. Putting it between the call-clobbered \
2009 and call-saved registers should cope with all eventualities. */ \
2011 /* Call-saved GPRs. */ \
2012 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2013 /* GPRs that can never be exposed to the register allocator. */ \
2015 /* Call-clobbered FPRs. */ \
2016 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2018 /* FPRs that are usually call-saved. The odd ones are actually \
2019 call-clobbered for n32, but listing them ahead of the even \
2020 registers might encourage the register allocator to fragment \
2021 the available FPR pairs. We need paired FPRs to store long \
2022 doubles, so it isn't clear that using a different order \
2023 for n32 would be a win. */ \
2024 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2025 /* None of the remaining classes have defined call-saved \
2027 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2028 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2029 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2030 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2031 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2032 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2033 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2034 182,183,184,185,186,187 \
2037 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2038 to be rearranged based on a particular function. On the mips16, we
2039 want to allocate $24 (T_REG) before other registers for
2040 instructions for which it is possible. */
2042 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2044 /* True if VALUE is an unsigned 6-bit number. */
2046 #define UIMM6_OPERAND(VALUE) \
2047 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2049 /* True if VALUE is a signed 10-bit number. */
2051 #define IMM10_OPERAND(VALUE) \
2052 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2054 /* True if VALUE is a signed 16-bit number. */
2056 #define SMALL_OPERAND(VALUE) \
2057 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2059 /* True if VALUE is an unsigned 16-bit number. */
2061 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2062 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2064 /* True if VALUE can be loaded into a register using LUI. */
2066 #define LUI_OPERAND(VALUE) \
2067 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2068 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2070 /* Return a value X with the low 16 bits clear, and such that
2071 VALUE - X is a signed 16-bit value. */
2073 #define CONST_HIGH_PART(VALUE) \
2074 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2076 #define CONST_LOW_PART(VALUE) \
2077 ((VALUE) - CONST_HIGH_PART (VALUE))
2079 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2080 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2081 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2083 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2084 mips_preferred_reload_class (X, CLASS)
2086 /* The HI and LO registers can only be reloaded via the general
2087 registers. Condition code registers can only be loaded to the
2088 general registers, and from the floating point registers. */
2090 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2091 mips_secondary_reload_class (CLASS, MODE, X, true)
2092 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2093 mips_secondary_reload_class (CLASS, MODE, X, false)
2095 /* Return the maximum number of consecutive registers
2096 needed to represent mode MODE in a register of class CLASS. */
2098 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2100 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2101 mips_cannot_change_mode_class (FROM, TO, CLASS)
2103 /* Stack layout; function entry, exit and calling. */
2105 #define STACK_GROWS_DOWNWARD
2107 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2109 /* Size of the area allocated in the frame to save the GP. */
2111 #define MIPS_GP_SAVE_AREA_SIZE \
2112 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2114 /* The offset of the first local variable from the frame pointer. See
2115 mips_compute_frame_info for details about the frame layout. */
2117 #define STARTING_FRAME_OFFSET \
2118 (FRAME_GROWS_DOWNWARD \
2120 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2122 #define RETURN_ADDR_RTX mips_return_addr
2124 /* Mask off the MIPS16 ISA bit in unwind addresses.
2126 The reason for this is a little subtle. When unwinding a call,
2127 we are given the call's return address, which on most targets
2128 is the address of the following instruction. However, what we
2129 actually want to find is the EH region for the call itself.
2130 The target-independent unwind code therefore searches for "RA - 1".
2132 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2133 RA - 1 is therefore the real (even-valued) start of the return
2134 instruction. EH region labels are usually odd-valued MIPS16 symbols
2135 too, so a search for an even address within a MIPS16 region would
2138 However, there is an exception. If the end of an EH region is also
2139 the end of a function, the end label is allowed to be even. This is
2140 necessary because a following non-MIPS16 function may also need EH
2141 information for its first instruction.
2143 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2144 non-ISA-encoded address. This probably isn't ideal, but it is
2145 the traditional (legacy) behavior. It is therefore only safe
2146 to search MIPS EH regions for an _odd-valued_ address.
2148 Masking off the ISA bit means that the target-independent code
2149 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2150 #define MASK_RETURN_ADDR GEN_INT (-2)
2153 /* Similarly, don't use the least-significant bit to tell pointers to
2154 code from vtable index. */
2156 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2158 /* The eliminations to $17 are only used for mips16 code. See the
2159 definition of HARD_FRAME_POINTER_REGNUM. */
2161 #define ELIMINABLE_REGS \
2162 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2163 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2164 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2165 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2166 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2167 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2169 /* Make sure that we're not trying to eliminate to the wrong hard frame
2171 #define CAN_ELIMINATE(FROM, TO) \
2172 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
2174 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2175 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2177 /* Allocate stack space for arguments at the beginning of each function. */
2178 #define ACCUMULATE_OUTGOING_ARGS 1
2180 /* The argument pointer always points to the first argument. */
2181 #define FIRST_PARM_OFFSET(FNDECL) 0
2183 /* o32 and o64 reserve stack space for all argument registers. */
2184 #define REG_PARM_STACK_SPACE(FNDECL) \
2186 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2189 /* Define this if it is the responsibility of the caller to
2190 allocate the area reserved for arguments passed in registers.
2191 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2192 of this macro is to determine whether the space is included in
2193 `crtl->outgoing_args_size'. */
2194 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2196 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2198 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2200 /* Symbolic macros for the registers used to return integer and floating
2203 #define GP_RETURN (GP_REG_FIRST + 2)
2204 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2206 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2208 /* Symbolic macros for the first/last argument registers. */
2210 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2211 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2212 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2213 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2215 #define LIBCALL_VALUE(MODE) \
2216 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2218 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2219 mips_function_value (VALTYPE, FUNC, VOIDmode)
2221 /* 1 if N is a possible register number for a function value.
2222 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2223 Currently, R2 and F0 are only implemented here (C has no complex type) */
2225 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2226 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2227 && (N) == FP_RETURN + 2))
2229 /* 1 if N is a possible register number for function argument passing.
2230 We have no FP argument registers when soft-float. When FP registers
2231 are 32 bits, we can't directly reference the odd numbered ones. */
2233 #define FUNCTION_ARG_REGNO_P(N) \
2234 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2235 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2238 /* This structure has to cope with two different argument allocation
2239 schemes. Most MIPS ABIs view the arguments as a structure, of which
2240 the first N words go in registers and the rest go on the stack. If I
2241 < N, the Ith word might go in Ith integer argument register or in a
2242 floating-point register. For these ABIs, we only need to remember
2243 the offset of the current argument into the structure.
2245 The EABI instead allocates the integer and floating-point arguments
2246 separately. The first N words of FP arguments go in FP registers,
2247 the rest go on the stack. Likewise, the first N words of the other
2248 arguments go in integer registers, and the rest go on the stack. We
2249 need to maintain three counts: the number of integer registers used,
2250 the number of floating-point registers used, and the number of words
2251 passed on the stack.
2253 We could keep separate information for the two ABIs (a word count for
2254 the standard ABIs, and three separate counts for the EABI). But it
2255 seems simpler to view the standard ABIs as forms of EABI that do not
2256 allocate floating-point registers.
2258 So for the standard ABIs, the first N words are allocated to integer
2259 registers, and mips_function_arg decides on an argument-by-argument
2260 basis whether that argument should really go in an integer register,
2261 or in a floating-point one. */
2263 typedef struct mips_args {
2264 /* Always true for varargs functions. Otherwise true if at least
2265 one argument has been passed in an integer register. */
2268 /* The number of arguments seen so far. */
2269 unsigned int arg_number;
2271 /* The number of integer registers used so far. For all ABIs except
2272 EABI, this is the number of words that have been added to the
2273 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2274 unsigned int num_gprs;
2276 /* For EABI, the number of floating-point registers used so far. */
2277 unsigned int num_fprs;
2279 /* The number of words passed on the stack. */
2280 unsigned int stack_words;
2282 /* On the mips16, we need to keep track of which floating point
2283 arguments were passed in general registers, but would have been
2284 passed in the FP regs if this were a 32-bit function, so that we
2285 can move them to the FP regs if we wind up calling a 32-bit
2286 function. We record this information in fp_code, encoded in base
2287 four. A zero digit means no floating point argument, a one digit
2288 means an SFmode argument, and a two digit means a DFmode argument,
2289 and a three digit is not used. The low order digit is the first
2290 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2291 an SFmode argument. ??? A more sophisticated approach will be
2292 needed if MIPS_ABI != ABI_32. */
2295 /* True if the function has a prototype. */
2299 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2300 for a call to a function whose data type is FNTYPE.
2301 For a library call, FNTYPE is 0. */
2303 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2304 mips_init_cumulative_args (&CUM, FNTYPE)
2306 /* Update the data in CUM to advance over an argument
2307 of mode MODE and data type TYPE.
2308 (TYPE is null for libcalls where that information may not be available.) */
2310 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2311 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2313 /* Determine where to put an argument to a function.
2314 Value is zero to push the argument on the stack,
2315 or a hard register in which to store the argument.
2317 MODE is the argument's machine mode.
2318 TYPE is the data type of the argument (as a tree).
2319 This is null for libcalls where that information may
2321 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2322 the preceding args and about the function being called.
2323 NAMED is nonzero if this argument is a named parameter
2324 (otherwise it is an extra parameter matching an ellipsis). */
2326 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2327 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2329 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2331 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2332 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2334 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2335 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2337 /* True if using EABI and varargs can be passed in floating-point
2338 registers. Under these conditions, we need a more complex form
2339 of va_list, which tracks GPR, FPR and stack arguments separately. */
2340 #define EABI_FLOAT_VARARGS_P \
2341 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2344 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2346 /* Treat LOC as a byte offset from the stack pointer and round it up
2347 to the next fully-aligned offset. */
2348 #define MIPS_STACK_ALIGN(LOC) \
2349 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2352 /* Output assembler code to FILE to increment profiler label # LABELNO
2353 for profiling a function entry. */
2355 #define FUNCTION_PROFILER(FILE, LABELNO) \
2357 if (TARGET_MIPS16) \
2358 sorry ("mips16 function profiling"); \
2359 if (TARGET_LONG_CALLS) \
2361 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ \
2362 if (Pmode == DImode) \
2363 fprintf (FILE, "\tdla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2365 fprintf (FILE, "\tla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2367 mips_push_asm_switch (&mips_noat); \
2368 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2369 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2370 /* _mcount treats $2 as the static chain register. */ \
2371 if (cfun->static_chain_decl != NULL) \
2372 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[2], \
2373 reg_names[STATIC_CHAIN_REGNUM]); \
2374 if (!TARGET_NEWABI) \
2377 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2378 TARGET_64BIT ? "dsubu" : "subu", \
2379 reg_names[STACK_POINTER_REGNUM], \
2380 reg_names[STACK_POINTER_REGNUM], \
2381 Pmode == DImode ? 16 : 8); \
2383 if (TARGET_LONG_CALLS) \
2384 fprintf (FILE, "\tjalr\t%s\n", reg_names[GP_REG_FIRST + 3]); \
2386 fprintf (FILE, "\tjal\t_mcount\n"); \
2387 mips_pop_asm_switch (&mips_noat); \
2388 /* _mcount treats $2 as the static chain register. */ \
2389 if (cfun->static_chain_decl != NULL) \
2390 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], \
2394 /* The profiler preserves all interesting registers, including $31. */
2395 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2397 /* No mips port has ever used the profiler counter word, so don't emit it
2398 or the label for it. */
2400 #define NO_PROFILE_COUNTERS 1
2402 /* Define this macro if the code for function profiling should come
2403 before the function prologue. Normally, the profiling code comes
2406 /* #define PROFILE_BEFORE_PROLOGUE */
2408 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2409 the stack pointer does not matter. The value is tested only in
2410 functions that have frame pointers.
2411 No definition is equivalent to always zero. */
2413 #define EXIT_IGNORE_STACK 1
2416 /* A C statement to output, on the stream FILE, assembler code for a
2417 block of data that contains the constant parts of a trampoline.
2418 This code should not include a label--the label is taken care of
2421 #define TRAMPOLINE_TEMPLATE(STREAM) \
2423 if (ptr_mode == DImode) \
2424 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2426 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2427 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2428 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2429 if (ptr_mode == DImode) \
2431 fprintf (STREAM, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n"); \
2432 fprintf (STREAM, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n"); \
2436 fprintf (STREAM, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n"); \
2437 fprintf (STREAM, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n"); \
2439 fprintf (STREAM, "\t.word\t0x03200008\t\t# jr $25\n"); \
2440 if (ptr_mode == DImode) \
2442 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2443 fprintf (STREAM, "\t.word\t0x00000000\t\t# <padding>\n"); \
2444 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2445 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2449 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2450 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2451 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2455 /* A C expression for the size in bytes of the trampoline, as an
2458 #define TRAMPOLINE_SIZE (ptr_mode == DImode ? 48 : 36)
2460 /* Alignment required for trampolines, in bits. */
2462 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2464 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2465 program and data caches. */
2467 #ifndef CACHE_FLUSH_FUNC
2468 #define CACHE_FLUSH_FUNC "_flush_cache"
2471 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2472 /* Flush both caches. We need to flush the data cache in case \
2473 the system has a write-back cache. */ \
2474 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2475 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2476 GEN_INT (3), TYPE_MODE (integer_type_node))
2478 /* A C statement to initialize the variable parts of a trampoline.
2479 ADDR is an RTX for the address of the trampoline; FNADDR is an
2480 RTX for the address of the nested function; STATIC_CHAIN is an
2481 RTX for the static chain value that should be passed to the
2482 function when it is called. */
2484 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2486 rtx func_addr, chain_addr, end_addr; \
2488 func_addr = plus_constant (ADDR, ptr_mode == DImode ? 32 : 28); \
2489 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2490 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2491 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2492 end_addr = gen_reg_rtx (Pmode); \
2493 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2494 GEN_INT (TRAMPOLINE_SIZE))); \
2495 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2498 /* Addressing modes, and classification of registers for them. */
2500 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2501 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2502 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2504 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2505 and check its validity for a certain class.
2506 We have two alternate definitions for each of them.
2507 The usual definition accepts all pseudo regs; the other rejects them all.
2508 The symbol REG_OK_STRICT causes the latter definition to be used.
2510 Most source files want to accept pseudo regs in the hope that
2511 they will get allocated to the class that the insn wants them to be in.
2512 Some source files that are used after register allocation
2513 need to be strict. */
2515 #ifndef REG_OK_STRICT
2516 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2517 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2519 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2520 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2523 #define REG_OK_FOR_INDEX_P(X) 0
2526 /* Maximum number of registers that can appear in a valid memory address. */
2528 #define MAX_REGS_PER_ADDRESS 1
2530 /* Check for constness inline but use mips_legitimate_address_p
2531 to check whether a constant really is an address. */
2533 #define CONSTANT_ADDRESS_P(X) \
2534 (CONSTANT_P (X) && memory_address_p (SImode, X))
2536 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2538 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2539 'the start of the function that this code is output in'. */
2541 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2542 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2543 asm_fprintf ((FILE), "%U%s", \
2544 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2546 asm_fprintf ((FILE), "%U%s", (NAME))
2548 /* Flag to mark a function decl symbol that requires a long call. */
2549 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2550 #define SYMBOL_REF_LONG_CALL_P(X) \
2551 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2553 /* This flag marks functions that cannot be lazily bound. */
2554 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2555 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2556 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2558 /* True if we're generating a form of MIPS16 code in which jump tables
2559 are stored in the text section and encoded as 16-bit PC-relative
2560 offsets. This is only possible when general text loads are allowed,
2561 since the table access itself will be an "lh" instruction. */
2562 /* ??? 16-bit offsets can overflow in large functions. */
2563 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2565 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2567 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2569 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2571 /* Define this as 1 if `char' should by default be signed; else as 0. */
2572 #ifndef DEFAULT_SIGNED_CHAR
2573 #define DEFAULT_SIGNED_CHAR 1
2576 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2577 we generally don't want to use them for copying arbitrary data.
2578 A single N-word move is usually the same cost as N single-word moves. */
2579 #define MOVE_MAX UNITS_PER_WORD
2580 #define MAX_MOVE_MAX 8
2582 /* Define this macro as a C expression which is nonzero if
2583 accessing less than a word of memory (i.e. a `char' or a
2584 `short') is no faster than accessing a word of memory, i.e., if
2585 such access require more than one instruction or if there is no
2586 difference in cost between byte and (aligned) word loads.
2588 On RISC machines, it tends to generate better code to define
2589 this as 1, since it avoids making a QI or HI mode register.
2591 But, generating word accesses for -mips16 is generally bad as shifts
2592 (often extended) would be needed for byte accesses. */
2593 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2595 /* Define this to be nonzero if shift instructions ignore all but the low-order
2597 #define SHIFT_COUNT_TRUNCATED 1
2599 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2600 is done just by pretending it is already truncated. */
2601 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2602 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2605 /* Specify the machine mode that pointers have.
2606 After generation of rtl, the compiler makes no further distinction
2607 between pointers and any other objects of this machine mode. */
2610 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2613 /* Give call MEMs SImode since it is the "most permissive" mode
2614 for both 32-bit and 64-bit targets. */
2616 #define FUNCTION_MODE SImode
2619 /* A C expression for the cost of moving data from a register in
2620 class FROM to one in class TO. The classes are expressed using
2621 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2622 the default; other values are interpreted relative to that.
2624 It is not required that the cost always equal 2 when FROM is the
2625 same as TO; on some machines it is expensive to move between
2626 registers if they are not general registers.
2628 If reload sees an insn consisting of a single `set' between two
2629 hard registers, and if `REGISTER_MOVE_COST' applied to their
2630 classes returns a value of 2, reload does not check to ensure
2631 that the constraints of the insn are met. Setting a cost of
2632 other than 2 will allow reload to verify that the constraints are
2633 met. You should do this if the `movM' pattern's constraints do
2634 not allow such copying. */
2636 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2637 mips_register_move_cost (MODE, FROM, TO)
2639 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2640 (mips_cost->memory_latency \
2641 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2643 /* Define if copies to/from condition code registers should be avoided.
2645 This is needed for the MIPS because reload_outcc is not complete;
2646 it needs to handle cases where the source is a general or another
2647 condition code register. */
2648 #define AVOID_CCMODE_COPIES
2650 /* A C expression for the cost of a branch instruction. A value of
2651 1 is the default; other values are interpreted relative to that. */
2653 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2654 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2656 /* If defined, modifies the length assigned to instruction INSN as a
2657 function of the context in which it is used. LENGTH is an lvalue
2658 that contains the initially computed length of the insn and should
2659 be updated with the correct length of the insn. */
2660 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2661 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2663 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2664 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2666 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2667 "%*" OPCODE "%?\t" OPERANDS "%/"
2669 /* Return the asm template for a call. INSN is the instruction's mnemonic
2670 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2673 When generating GOT code without explicit relocation operators,
2674 all calls should use assembly macros. Otherwise, all indirect
2675 calls should use "jr" or "jalr"; we will arrange to restore $gp
2676 afterwards if necessary. Finally, we can only generate direct
2677 calls for -mabicalls by temporarily switching to non-PIC mode. */
2678 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2679 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2680 ? "%*" INSN "\t%" #OPNO "%/" \
2681 : REG_P (OPERANDS[OPNO]) \
2682 ? "%*" INSN "r\t%" #OPNO "%/" \
2683 : TARGET_ABICALLS_PIC2 \
2684 ? (".option\tpic0\n\t" \
2685 "%*" INSN "\t%" #OPNO "%/\n\t" \
2687 : "%*" INSN "\t%" #OPNO "%/")
2689 /* Control the assembler format that we output. */
2691 /* Output to assembler file text saying following lines
2692 may contain character constants, extra white space, comments, etc. */
2695 #define ASM_APP_ON " #APP\n"
2698 /* Output to assembler file text saying following lines
2699 no longer contain unusual constructs. */
2702 #define ASM_APP_OFF " #NO_APP\n"
2705 #define REGISTER_NAMES \
2706 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2707 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2708 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2709 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2710 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2711 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2712 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2713 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2714 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2715 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2716 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2717 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2718 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2719 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2720 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2721 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2722 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2723 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2724 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2725 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2726 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2727 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2728 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2729 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2731 /* List the "software" names for each register. Also list the numerical
2732 names for $fp and $sp. */
2734 #define ADDITIONAL_REGISTER_NAMES \
2736 { "$29", 29 + GP_REG_FIRST }, \
2737 { "$30", 30 + GP_REG_FIRST }, \
2738 { "at", 1 + GP_REG_FIRST }, \
2739 { "v0", 2 + GP_REG_FIRST }, \
2740 { "v1", 3 + GP_REG_FIRST }, \
2741 { "a0", 4 + GP_REG_FIRST }, \
2742 { "a1", 5 + GP_REG_FIRST }, \
2743 { "a2", 6 + GP_REG_FIRST }, \
2744 { "a3", 7 + GP_REG_FIRST }, \
2745 { "t0", 8 + GP_REG_FIRST }, \
2746 { "t1", 9 + GP_REG_FIRST }, \
2747 { "t2", 10 + GP_REG_FIRST }, \
2748 { "t3", 11 + GP_REG_FIRST }, \
2749 { "t4", 12 + GP_REG_FIRST }, \
2750 { "t5", 13 + GP_REG_FIRST }, \
2751 { "t6", 14 + GP_REG_FIRST }, \
2752 { "t7", 15 + GP_REG_FIRST }, \
2753 { "s0", 16 + GP_REG_FIRST }, \
2754 { "s1", 17 + GP_REG_FIRST }, \
2755 { "s2", 18 + GP_REG_FIRST }, \
2756 { "s3", 19 + GP_REG_FIRST }, \
2757 { "s4", 20 + GP_REG_FIRST }, \
2758 { "s5", 21 + GP_REG_FIRST }, \
2759 { "s6", 22 + GP_REG_FIRST }, \
2760 { "s7", 23 + GP_REG_FIRST }, \
2761 { "t8", 24 + GP_REG_FIRST }, \
2762 { "t9", 25 + GP_REG_FIRST }, \
2763 { "k0", 26 + GP_REG_FIRST }, \
2764 { "k1", 27 + GP_REG_FIRST }, \
2765 { "gp", 28 + GP_REG_FIRST }, \
2766 { "sp", 29 + GP_REG_FIRST }, \
2767 { "fp", 30 + GP_REG_FIRST }, \
2768 { "ra", 31 + GP_REG_FIRST }, \
2769 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2772 /* This is meant to be redefined in the host dependent files. It is a
2773 set of alternative names and regnums for mips coprocessors. */
2775 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2777 #define PRINT_OPERAND mips_print_operand
2778 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2779 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2781 #define DBR_OUTPUT_SEQEND(STREAM) \
2784 /* Undo the effect of '%*'. */ \
2785 mips_pop_asm_switch (&mips_nomacro); \
2786 mips_pop_asm_switch (&mips_noreorder); \
2787 /* Emit a blank line after the delay slot for emphasis. */ \
2788 fputs ("\n", STREAM); \
2792 /* How to tell the debugger about changes of source files. */
2793 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2795 /* mips-tfile does not understand .stabd directives. */
2796 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2797 dbxout_begin_stabn_sline (LINE); \
2798 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2801 /* Use .loc directives for SDB line numbers. */
2802 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2803 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2805 /* The MIPS implementation uses some labels for its own purpose. The
2806 following lists what labels are created, and are all formed by the
2807 pattern $L[a-z].*. The machine independent portion of GCC creates
2808 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2810 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2811 $Lb[0-9]+ Begin blocks for MIPS debug support
2812 $Lc[0-9]+ Label for use in s<xx> operation.
2813 $Le[0-9]+ End blocks for MIPS debug support */
2815 #undef ASM_DECLARE_OBJECT_NAME
2816 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2817 mips_declare_object (STREAM, NAME, "", ":\n")
2819 /* Globalizing directive for a label. */
2820 #define GLOBAL_ASM_OP "\t.globl\t"
2822 /* This says how to define a global common symbol. */
2824 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2826 /* This says how to define a local common symbol (i.e., not visible to
2829 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2830 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2831 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2834 /* This says how to output an external. It would be possible not to
2835 output anything and let undefined symbol become external. However
2836 the assembler uses length information on externals to allocate in
2837 data/sdata bss/sbss, thereby saving exec time. */
2839 #undef ASM_OUTPUT_EXTERNAL
2840 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2841 mips_output_external(STREAM,DECL,NAME)
2843 /* This is how to declare a function name. The actual work of
2844 emitting the label is moved to function_prologue, so that we can
2845 get the line number correctly emitted before the .ent directive,
2846 and after any .file directives. Define as empty so that the function
2847 is not declared before the .ent directive elsewhere. */
2849 #undef ASM_DECLARE_FUNCTION_NAME
2850 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2852 /* This is how to store into the string LABEL
2853 the symbol_ref name of an internal numbered label where
2854 PREFIX is the class of label and NUM is the number within the class.
2855 This is suitable for output with `assemble_name'. */
2857 #undef ASM_GENERATE_INTERNAL_LABEL
2858 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2859 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2861 /* Print debug labels as "foo = ." rather than "foo:" because they should
2862 represent a byte pointer rather than an ISA-encoded address. This is
2863 particularly important for code like:
2868 .section .gcc_except_table,...
2870 .uleb128 foo-$LFBxxx
2872 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2873 likewise a byte pointer rather than an ISA-encoded address.
2875 At the time of writing, this hook is not used for the function end
2881 But this doesn't matter, because GAS doesn't treat a pre-.end label
2882 as a MIPS16 one anyway. */
2884 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2885 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2887 /* This is how to output an element of a case-vector that is absolute. */
2889 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2890 fprintf (STREAM, "\t%s\t%sL%d\n", \
2891 ptr_mode == DImode ? ".dword" : ".word", \
2892 LOCAL_LABEL_PREFIX, \
2895 /* This is how to output an element of a case-vector. We can make the
2896 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2899 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2901 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2902 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2903 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2904 else if (TARGET_GPWORD) \
2905 fprintf (STREAM, "\t%s\t%sL%d\n", \
2906 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2907 LOCAL_LABEL_PREFIX, VALUE); \
2908 else if (TARGET_RTP_PIC) \
2910 /* Make the entry relative to the start of the function. */ \
2911 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2912 fprintf (STREAM, "\t%s\t%sL%d-", \
2913 Pmode == DImode ? ".dword" : ".word", \
2914 LOCAL_LABEL_PREFIX, VALUE); \
2915 assemble_name (STREAM, XSTR (fnsym, 0)); \
2916 fprintf (STREAM, "\n"); \
2919 fprintf (STREAM, "\t%s\t%sL%d\n", \
2920 ptr_mode == DImode ? ".dword" : ".word", \
2921 LOCAL_LABEL_PREFIX, VALUE); \
2924 /* This is how to output an assembler line
2925 that says to advance the location counter
2926 to a multiple of 2**LOG bytes. */
2928 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2929 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2931 /* This is how to output an assembler line to advance the location
2932 counter by SIZE bytes. */
2934 #undef ASM_OUTPUT_SKIP
2935 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2936 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2938 /* This is how to output a string. */
2939 #undef ASM_OUTPUT_ASCII
2940 #define ASM_OUTPUT_ASCII mips_output_ascii
2942 /* Output #ident as a in the read-only data section. */
2943 #undef ASM_OUTPUT_IDENT
2944 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2946 const char *p = STRING; \
2947 int size = strlen (p) + 1; \
2948 switch_to_section (readonly_data_section); \
2949 assemble_string (p, size); \
2952 /* Default to -G 8 */
2953 #ifndef MIPS_DEFAULT_GVALUE
2954 #define MIPS_DEFAULT_GVALUE 8
2957 /* Define the strings to put out for each section in the object file. */
2958 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2959 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2961 #undef READONLY_DATA_SECTION_ASM_OP
2962 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2964 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2967 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2968 TARGET_64BIT ? "daddiu" : "addiu", \
2969 reg_names[STACK_POINTER_REGNUM], \
2970 reg_names[STACK_POINTER_REGNUM], \
2971 TARGET_64BIT ? "sd" : "sw", \
2973 reg_names[STACK_POINTER_REGNUM]); \
2977 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2980 mips_push_asm_switch (&mips_noreorder); \
2981 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2982 TARGET_64BIT ? "ld" : "lw", \
2984 reg_names[STACK_POINTER_REGNUM], \
2985 TARGET_64BIT ? "daddu" : "addu", \
2986 reg_names[STACK_POINTER_REGNUM], \
2987 reg_names[STACK_POINTER_REGNUM]); \
2988 mips_pop_asm_switch (&mips_noreorder); \
2992 /* How to start an assembler comment.
2993 The leading space is important (the mips native assembler requires it). */
2994 #ifndef ASM_COMMENT_START
2995 #define ASM_COMMENT_START " #"
2998 /* Default definitions for size_t and ptrdiff_t. We must override the
2999 definitions from ../svr4.h on mips-*-linux-gnu. */
3002 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3005 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3007 /* The maximum number of bytes that can be copied by one iteration of
3008 a movmemsi loop; see mips_block_move_loop. */
3009 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3010 (UNITS_PER_WORD * 4)
3012 /* The maximum number of bytes that can be copied by a straight-line
3013 implementation of movmemsi; see mips_block_move_straight. We want
3014 to make sure that any loop-based implementation will iterate at
3016 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3017 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3019 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3020 values were determined experimentally by benchmarking with CSiBE.
3021 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3022 for o32 where we have to restore $gp afterwards as well as make an
3023 indirect call), but in practice, bumping this up higher for
3024 TARGET_ABICALLS doesn't make much difference to code size. */
3026 #define MIPS_CALL_RATIO 8
3028 /* Any loop-based implementation of movmemsi will have at least
3029 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3030 moves, so allow individual copies of fewer elements.
3032 When movmemsi is not available, use a value approximating
3033 the length of a memcpy call sequence, so that move_by_pieces
3034 will generate inline code if it is shorter than a function call.
3035 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3036 we'll have to generate a load/store pair for each, halve the
3037 value of MIPS_CALL_RATIO to take that into account. */
3039 #define MOVE_RATIO(speed) \
3041 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3042 : MIPS_CALL_RATIO / 2)
3044 /* movmemsi is meant to generate code that is at least as good as
3045 move_by_pieces. However, movmemsi effectively uses a by-pieces
3046 implementation both for moves smaller than a word and for word-aligned
3047 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
3048 allow the tree-level optimisers to do such moves by pieces, as it
3049 often exposes other optimization opportunities. We might as well
3050 continue to use movmemsi at the rtl level though, as it produces
3051 better code when scheduling is disabled (such as at -O). */
3053 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
3055 ? (!currently_expanding_to_rtl \
3056 && ((ALIGN) < BITS_PER_WORD \
3057 ? (SIZE) < UNITS_PER_WORD \
3058 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
3059 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
3060 < (unsigned int) MOVE_RATIO (false)))
3062 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3063 of the length of a memset call, but use the default otherwise. */
3065 #define CLEAR_RATIO(speed)\
3066 ((speed) ? 15 : MIPS_CALL_RATIO)
3068 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3069 optimizing for size adjust the ratio to account for the overhead of
3070 loading the constant and replicating it across the word. */
3072 #define SET_RATIO(speed) \
3073 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3075 /* STORE_BY_PIECES_P can be used when copying a constant string, but
3076 in that case each word takes 3 insns (lui, ori, sw), or more in
3077 64-bit mode, instead of 2 (lw, sw). For now we always fail this
3078 and let the move_by_pieces code copy the string from read-only
3079 memory. In the future, this could be tuned further for multi-issue
3080 CPUs that can issue stores down one pipe and arithmetic instructions
3081 down another; in that case, the lui/ori/sw combination would be a
3082 win for long enough strings. */
3084 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
3087 /* Since the bits of the _init and _fini function is spread across
3088 many object files, each potentially with its own GP, we must assume
3089 we need to load our GP. We don't preserve $gp or $ra, since each
3090 init/fini chunk is supposed to initialize $gp, and crti/crtn
3091 already take care of preserving $ra and, when appropriate, $gp. */
3092 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3093 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3094 asm (SECTION_OP "\n\
3100 jal " USER_LABEL_PREFIX #FUNC "\n\
3101 " TEXT_SECTION_ASM_OP);
3102 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3103 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3104 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3105 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3106 asm (SECTION_OP "\n\
3111 .cpsetup $31, $2, 1b\n\
3112 jal " USER_LABEL_PREFIX #FUNC "\n\
3113 " TEXT_SECTION_ASM_OP);
3118 #define HAVE_AS_TLS 0
3121 /* Return an asm string that atomically:
3123 - Compares memory reference %1 to register %2 and, if they are
3124 equal, changes %1 to %3.
3126 - Sets register %0 to the old value of memory reference %1.
3128 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
3129 and OP is the instruction that should be used to load %3 into a
3131 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
3132 "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
3133 "\tbne\t%0,%z2,2f\n" \
3134 "\t" OP "\t%@,%3\n" \
3135 "\tsc" SUFFIX "\t%@,%1\n" \
3136 "\tbeq%?\t%@,%.,1b\n" \
3140 /* Return an asm string that atomically:
3142 - Given that %2 contains a bit mask and %3 the inverted mask and
3143 that %4 and %5 have already been ANDed with %2.
3145 - Compares the bits in memory reference %1 selected by mask %2 to
3146 register %4 and, if they are equal, changes the selected bits
3149 - Sets register %0 to the old value of memory reference %1.
3151 OPS are the instructions needed to OR %5 with %@. */
3152 #define MIPS_COMPARE_AND_SWAP_12(OPS) \
3153 "%(%<%[%|1:\tll\t%0,%1\n" \
3154 "\tand\t%@,%0,%2\n" \
3155 "\tbne\t%@,%z4,2f\n" \
3156 "\tand\t%@,%0,%3\n" \
3159 "\tbeq%?\t%@,%.,1b\n" \
3163 #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
3164 #define MIPS_COMPARE_AND_SWAP_12_NONZERO_OP "\tor\t%@,%@,%5\n"
3167 /* Return an asm string that atomically:
3169 - Sets memory reference %0 to %0 INSN %1.
3171 SUFFIX is the suffix that should be added to "ll" and "sc"
3173 #define MIPS_SYNC_OP(SUFFIX, INSN) \
3174 "%(%<%[%|1:\tll" SUFFIX "\t%@,%0\n" \
3175 "\t" INSN "\t%@,%@,%1\n" \
3176 "\tsc" SUFFIX "\t%@,%0\n" \
3177 "\tbeq%?\t%@,%.,1b\n" \
3180 /* Return an asm string that atomically:
3182 - Given that %1 contains a bit mask and %2 the inverted mask and
3183 that %3 has already been ANDed with %1.
3185 - Sets the selected bits of memory reference %0 to %0 INSN %3.
3187 - Uses scratch register %4.
3189 AND_OP is an instruction done after INSN to mask INSN's result
3190 with the mask. For most operations, this is an AND with the
3191 inclusive mask (%1). For nand operations -- where the result of
3192 INSN is already correctly masked -- it instead performs a bitwise
3194 #define MIPS_SYNC_OP_12(INSN, AND_OP) \
3195 "%(%<%[%|1:\tll\t%4,%0\n" \
3196 "\tand\t%@,%4,%2\n" \
3197 "\t" INSN "\t%4,%4,%z3\n" \
3199 "\tor\t%@,%@,%4\n" \
3201 "\tbeq%?\t%@,%.,1b\n" \
3204 #define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n"
3205 #define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n"
3207 /* Return an asm string that atomically:
3209 - Given that %2 contains a bit mask and %3 the inverted mask and
3210 that %4 has already been ANDed with %2.
3212 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3214 - Sets %0 to the original value of %1.
3216 - Uses scratch register %5.
3218 AND_OP is an instruction done after INSN to mask INSN's result
3219 with the mask. For most operations, this is an AND with the
3220 inclusive mask (%1). For nand operations -- where the result of
3221 INSN is already correctly masked -- it instead performs a bitwise
3223 #define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \
3224 "%(%<%[%|1:\tll\t%0,%1\n" \
3225 "\tand\t%@,%0,%3\n" \
3226 "\t" INSN "\t%5,%0,%z4\n" \
3228 "\tor\t%@,%@,%5\n" \
3230 "\tbeq%?\t%@,%.,1b\n" \
3233 #define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n"
3234 #define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n"
3236 /* Return an asm string that atomically:
3238 - Given that %2 contains a bit mask and %3 the inverted mask and
3239 that %4 has already been ANDed with %2.
3241 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3243 - Sets %0 to the new value of %1.
3245 AND_OP is an instruction done after INSN to mask INSN's result
3246 with the mask. For most operations, this is an AND with the
3247 inclusive mask (%1). For nand operations -- where the result of
3248 INSN is already correctly masked -- it instead performs a bitwise
3250 #define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \
3251 "%(%<%[%|1:\tll\t%0,%1\n" \
3252 "\tand\t%@,%0,%3\n" \
3253 "\t" INSN "\t%0,%0,%z4\n" \
3255 "\tor\t%@,%@,%0\n" \
3257 "\tbeq%?\t%@,%.,1b\n" \
3260 #define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n"
3261 #define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n"
3263 /* Return an asm string that atomically:
3265 - Sets memory reference %1 to %1 INSN %2.
3267 - Sets register %0 to the old value of memory reference %1.
3269 SUFFIX is the suffix that should be added to "ll" and "sc"
3271 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
3272 "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
3273 "\t" INSN "\t%@,%0,%2\n" \
3274 "\tsc" SUFFIX "\t%@,%1\n" \
3275 "\tbeq%?\t%@,%.,1b\n" \
3278 /* Return an asm string that atomically:
3280 - Sets memory reference %1 to %1 INSN %2.
3282 - Sets register %0 to the new value of memory reference %1.
3284 SUFFIX is the suffix that should be added to "ll" and "sc"
3286 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3287 "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
3288 "\t" INSN "\t%@,%0,%2\n" \
3289 "\tsc" SUFFIX "\t%@,%1\n" \
3290 "\tbeq%?\t%@,%.,1b%~\n" \
3291 "\t" INSN "\t%0,%0,%2%-%]%>%)"
3293 /* Return an asm string that atomically:
3295 - Sets memory reference %0 to ~(%0 AND %1).
3297 SUFFIX is the suffix that should be added to "ll" and "sc"
3298 instructions. INSN is the and instruction needed to and a register
3300 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3301 "%(%<%[%|1:\tll" SUFFIX "\t%@,%0\n" \
3302 "\t" INSN "\t%@,%@,%1\n" \
3303 "\tnor\t%@,%@,%.\n" \
3304 "\tsc" SUFFIX "\t%@,%0\n" \
3305 "\tbeq%?\t%@,%.,1b\n" \
3308 /* Return an asm string that atomically:
3310 - Sets memory reference %1 to ~(%1 AND %2).
3312 - Sets register %0 to the old value of memory reference %1.
3314 SUFFIX is the suffix that should be added to "ll" and "sc"
3315 instructions. INSN is the and instruction needed to and a register
3317 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3318 "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
3319 "\t" INSN "\t%@,%0,%2\n" \
3320 "\tnor\t%@,%@,%.\n" \
3321 "\tsc" SUFFIX "\t%@,%1\n" \
3322 "\tbeq%?\t%@,%.,1b\n" \
3325 /* Return an asm string that atomically:
3327 - Sets memory reference %1 to ~(%1 AND %2).
3329 - Sets register %0 to the new value of memory reference %1.
3331 SUFFIX is the suffix that should be added to "ll" and "sc"
3332 instructions. INSN is the and instruction needed to and a register
3334 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3335 "%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
3336 "\t" INSN "\t%0,%0,%2\n" \
3337 "\tnor\t%@,%0,%.\n" \
3338 "\tsc" SUFFIX "\t%@,%1\n" \
3339 "\tbeq%?\t%@,%.,1b%~\n" \
3340 "\tnor\t%0,%0,%.%-%]%>%)"
3342 /* Return an asm string that atomically:
3344 - Sets memory reference %1 to %2.
3346 - Sets register %0 to the old value of memory reference %1.
3348 SUFFIX is the suffix that should be added to "ll" and "sc"
3349 instructions. OP is the and instruction that should be used to
3350 load %2 into a register. */
3351 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3353 "1:\tll" SUFFIX "\t%0,%1\n" \
3354 "\t" OP "\t%@,%2\n" \
3355 "\tsc" SUFFIX "\t%@,%1\n" \
3356 "\tbeq%?\t%@,%.,1b\n" \
3359 /* Return an asm string that atomically:
3361 - Given that %2 contains an inclusive mask, %3 and exclusive mask
3362 and %4 has already been ANDed with the inclusive mask.
3364 - Sets bits selected by the inclusive mask of memory reference %1
3367 - Sets register %0 to the old value of memory reference %1.
3369 OPS are the instructions needed to OR %4 with %@.
3371 Operand %2 is unused, but needed as to give the test_and_set_12
3372 insn the five operands expected by the expander. */
3373 #define MIPS_SYNC_EXCHANGE_12(OPS) \
3376 "\tand\t%@,%0,%3\n" \
3379 "\tbeq%?\t%@,%.,1b\n" \
3382 #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
3383 #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
3385 #ifndef USED_FOR_TARGET
3386 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3387 struct mips_asm_switch {
3388 /* The FOO in the description above. */
3391 /* The current block nesting level, or 0 if we aren't in a block. */
3395 extern const enum reg_class mips_regno_to_class[];
3396 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3397 extern bool mips_print_operand_punct[256];
3398 extern const char *current_function_file; /* filename current function is in */
3399 extern int num_source_filenames; /* current .file # */
3400 extern struct mips_asm_switch mips_noreorder;
3401 extern struct mips_asm_switch mips_nomacro;
3402 extern struct mips_asm_switch mips_noat;
3403 extern int mips_dbx_regno[];
3404 extern int mips_dwarf_regno[];
3405 extern bool mips_split_p[];
3406 extern bool mips_split_hi_p[];
3407 extern enum processor_type mips_arch; /* which cpu to codegen for */
3408 extern enum processor_type mips_tune; /* which cpu to schedule for */
3409 extern int mips_isa; /* architectural level */
3410 extern int mips_abi; /* which ABI to use */
3411 extern const struct mips_cpu_info *mips_arch_info;
3412 extern const struct mips_cpu_info *mips_tune_info;
3413 extern const struct mips_rtx_cost_data *mips_cost;
3414 extern bool mips_base_mips16;
3415 extern enum mips_code_readable_setting mips_code_readable;
3418 /* Enable querying of DFA units. */
3419 #define CPU_UNITS_QUERY 1
3421 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3422 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3424 /* This is necessary to avoid a warning about comparing different enum
3426 #define mips_tune_attr ((enum attr_cpu) mips_tune)
OSDN Git Service
