1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern int target_flags;
31 /* MIPS external variables defined in mips.c. */
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
74 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
75 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
76 to work on a 64 bit machine. */
84 /* Information about one recognized processor. Defined here for the
85 benefit of TARGET_CPU_CPP_BUILTINS. */
86 struct mips_cpu_info {
87 /* The 'canonical' name of the processor as far as GCC is concerned.
88 It's typically a manufacturer's prefix followed by a numerical
89 designation. It should be lower case. */
92 /* The internal processor number that most closely matches this
93 entry. Several processors can have the same value, if there's no
94 difference between them from GCC's point of view. */
95 enum processor_type cpu;
97 /* The ISA level that the processor implements. */
101 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
102 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
103 extern const char *current_function_file; /* filename current function is in */
104 extern int num_source_filenames; /* current .file # */
105 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
106 extern int sym_lineno; /* sgi next label # for each stmt */
107 extern int set_noreorder; /* # of nested .set noreorder's */
108 extern int set_nomacro; /* # of nested .set nomacro's */
109 extern int set_noat; /* # of nested .set noat's */
110 extern int set_volatile; /* # of nested .set volatile's */
111 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
112 extern int mips_dbx_regno[]; /* Map register # to debug register # */
113 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
114 extern enum cmp_type branch_type; /* what type of branch to use */
115 extern enum processor_type mips_arch; /* which cpu to codegen for */
116 extern enum processor_type mips_tune; /* which cpu to schedule for */
117 extern int mips_isa; /* architectural level */
118 extern int mips_abi; /* which ABI to use */
119 extern int mips16_hard_float; /* mips16 without -msoft-float */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern const struct mips_cpu_info mips_cpu_info_table[];
126 extern const struct mips_cpu_info *mips_arch_info;
127 extern const struct mips_cpu_info *mips_tune_info;
129 /* Macros to silence warnings about numbers being signed in traditional
130 C and unsigned in ISO C when compiled on 32-bit hosts. */
132 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
133 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
134 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
137 /* Run-time compilation parameters selecting different hardware subsets. */
139 /* Macros used in the machine description to test the flags. */
141 /* Bits for real switches */
142 #define MASK_INT64 0x00000001 /* ints are 64 bits */
143 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
144 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
145 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
146 multiply-add operations. */
147 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
148 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
149 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
150 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
151 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
152 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
153 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
154 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
155 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
156 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
157 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
158 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
159 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
160 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
161 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
162 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
163 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
164 #define MASK_NO_CHECK_ZERO_DIV \
165 0x00200000 /* divide by zero checking */
166 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
168 #define MASK_UNINIT_CONST_IN_RODATA \
169 0x00800000 /* Store uninitialized
171 #define MASK_FIX_R4000 0x01000000 /* Work around R4000 errata. */
172 #define MASK_FIX_R4400 0x02000000 /* Work around R4400 errata. */
173 #define MASK_FIX_SB1 0x04000000 /* Work around SB-1 errata. */
174 #define MASK_FIX_VR4120 0x08000000 /* Work around VR4120 errata. */
176 /* Debug switches, not documented */
177 #define MASK_DEBUG 0 /* unused */
178 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
179 #define MASK_DEBUG_D 0 /* don't do define_split's */
180 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
182 /* Dummy switches used only in specs */
183 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
185 /* r4000 64 bit sizes */
186 #define TARGET_INT64 (target_flags & MASK_INT64)
187 #define TARGET_LONG64 (target_flags & MASK_LONG64)
188 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
189 #define TARGET_64BIT (target_flags & MASK_64BIT)
191 /* Mips vs. GNU linker */
192 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
194 /* Mips vs. GNU assembler */
195 #define TARGET_GAS (target_flags & MASK_GAS)
196 #define TARGET_MIPS_AS (!TARGET_GAS)
199 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
200 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
201 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
202 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
204 /* Reg. Naming in .s ($21 vs. $a0) */
205 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
207 /* call memcpy instead of inline code */
208 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
210 /* .abicalls, etc from Pyramid V.4 */
211 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
212 #define TARGET_XGOT (target_flags & MASK_XGOT)
214 /* software floating point */
215 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
216 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
218 /* always call through a register */
219 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
221 /* generate embedded PIC code;
223 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
225 /* for embedded systems, optimize for
226 reduced RAM space instead of for
228 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
230 /* always store uninitialized const
231 variables in rodata, requires
232 TARGET_EMBEDDED_DATA. */
233 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
235 /* generate big endian code. */
236 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
238 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
239 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
241 #define TARGET_MAD (target_flags & MASK_MAD)
243 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
245 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
247 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
249 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
251 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
253 /* Work around R4000 errata. */
254 #define TARGET_FIX_R4000 (target_flags & MASK_FIX_R4000)
256 /* Work around R4400 errata. */
257 #define TARGET_FIX_R4400 (target_flags & MASK_FIX_R4400)
258 #define TARGET_FIX_VR4120 (target_flags & MASK_FIX_VR4120)
260 /* True if we should use NewABI-style relocation operators for
261 symbolic addresses. This is never true for mips16 code,
262 which has its own conventions. */
264 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
267 /* True if the call patterns should be split into a jalr followed by
268 an instruction to restore $gp. This is only ever true for SVR4 PIC,
269 in which $gp is call-clobbered. It is only safe to split the load
270 from the call when every use of $gp is explicit. */
272 #define TARGET_SPLIT_CALLS \
273 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
275 /* True if we can optimize sibling calls. For simplicity, we only
276 handle cases in which call_insn_operand will reject invalid
277 sibcall addresses. There are two cases in which this isn't true:
279 - TARGET_MIPS16. call_insn_operand accepts constant addresses
280 but there is no direct jump instruction. It isn't worth
281 using sibling calls in this case anyway; they would usually
282 be longer than normal calls.
284 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
285 accepts global constants, but "jr $25" is the only allowed
288 #define TARGET_SIBCALLS \
289 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
291 /* True if .gpword or .gpdword should be used for switch tables.
292 There are some problems with using these directives with the
295 - It has been reported that some versions of the native n32
296 assembler mishandle .gpword, complaining that symbols are
297 global when they are in fact local.
299 - The native assemblers don't understand .gpdword.
301 - Although GAS does understand .gpdword, the native linker
302 mishandles the relocations GAS generates (R_MIPS_GPREL32
303 followed by R_MIPS_64).
305 We therefore disable GP-relative switch tables for n32 and n64
307 #define TARGET_GPWORD (TARGET_ABICALLS && !(TARGET_NEWABI && TARGET_IRIX))
309 /* Generate mips16 code */
310 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
312 /* Generic ISA defines. */
313 #define ISA_MIPS1 (mips_isa == 1)
314 #define ISA_MIPS2 (mips_isa == 2)
315 #define ISA_MIPS3 (mips_isa == 3)
316 #define ISA_MIPS4 (mips_isa == 4)
317 #define ISA_MIPS32 (mips_isa == 32)
318 #define ISA_MIPS32R2 (mips_isa == 33)
319 #define ISA_MIPS64 (mips_isa == 64)
321 /* Architecture target defines. */
322 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
323 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
324 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
325 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
326 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
327 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
328 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
329 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
330 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
332 /* Scheduling target defines. */
333 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
334 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
335 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
336 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
337 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
338 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
339 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
340 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
341 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
343 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
344 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
346 /* IRIX specific stuff. */
347 #define TARGET_IRIX 0
348 #define TARGET_IRIX5 0
349 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
351 /* Define preprocessor macros for the -march and -mtune options.
352 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
353 processor. If INFO's canonical name is "foo", define PREFIX to
354 be "foo", and define an additional macro PREFIX_FOO. */
355 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
360 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
361 for (p = macro; *p != 0; p++) \
364 builtin_define (macro); \
365 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
370 /* Target CPU builtins. */
371 #define TARGET_CPU_CPP_BUILTINS() \
374 builtin_assert ("cpu=mips"); \
375 builtin_define ("__mips__"); \
376 builtin_define ("_mips"); \
378 /* We do this here because __mips is defined below \
379 and so we can't use builtin_define_std. */ \
381 builtin_define ("mips"); \
383 /* Treat _R3000 and _R4000 like register-size defines, \
384 which is how they've historically been used. */ \
387 builtin_define ("__mips64"); \
388 builtin_define_std ("R4000"); \
389 builtin_define ("_R4000"); \
393 builtin_define_std ("R3000"); \
394 builtin_define ("_R3000"); \
396 if (TARGET_FLOAT64) \
397 builtin_define ("__mips_fpr=64"); \
399 builtin_define ("__mips_fpr=32"); \
402 builtin_define ("__mips16"); \
404 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
405 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
409 builtin_define ("__mips=1"); \
410 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
412 else if (ISA_MIPS2) \
414 builtin_define ("__mips=2"); \
415 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
417 else if (ISA_MIPS3) \
419 builtin_define ("__mips=3"); \
420 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
422 else if (ISA_MIPS4) \
424 builtin_define ("__mips=4"); \
425 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
427 else if (ISA_MIPS32) \
429 builtin_define ("__mips=32"); \
430 builtin_define ("__mips_isa_rev=1"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
433 else if (ISA_MIPS32R2) \
435 builtin_define ("__mips=32"); \
436 builtin_define ("__mips_isa_rev=2"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
439 else if (ISA_MIPS64) \
441 builtin_define ("__mips=64"); \
442 builtin_define ("__mips_isa_rev=1"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
446 if (TARGET_HARD_FLOAT) \
447 builtin_define ("__mips_hard_float"); \
448 else if (TARGET_SOFT_FLOAT) \
449 builtin_define ("__mips_soft_float"); \
451 if (TARGET_SINGLE_FLOAT) \
452 builtin_define ("__mips_single_float"); \
454 if (TARGET_BIG_ENDIAN) \
456 builtin_define_std ("MIPSEB"); \
457 builtin_define ("_MIPSEB"); \
461 builtin_define_std ("MIPSEL"); \
462 builtin_define ("_MIPSEL"); \
465 /* Macros dependent on the C dialect. */ \
466 if (preprocessing_asm_p ()) \
468 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
469 builtin_define ("_LANGUAGE_ASSEMBLY"); \
471 else if (c_dialect_cxx ()) \
473 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
474 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
475 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
479 builtin_define_std ("LANGUAGE_C"); \
480 builtin_define ("_LANGUAGE_C"); \
482 if (c_dialect_objc ()) \
484 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
485 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
486 /* Bizarre, but needed at least for Irix. */ \
487 builtin_define_std ("LANGUAGE_C"); \
488 builtin_define ("_LANGUAGE_C"); \
491 if (mips_abi == ABI_EABI) \
492 builtin_define ("__mips_eabi"); \
498 /* Macro to define tables used to set the flags.
499 This is a list in braces of pairs in braces,
500 each pair being { "NAME", VALUE }
501 where VALUE is the bits to set or minus the bits to clear.
502 An empty string NAME is used to identify the default VALUE. */
504 #define TARGET_SWITCHES \
506 SUBTARGET_TARGET_SWITCHES \
507 {"int64", MASK_INT64 | MASK_LONG64, \
508 N_("Use 64-bit int type")}, \
509 {"long64", MASK_LONG64, \
510 N_("Use 64-bit long type")}, \
511 {"long32", -(MASK_LONG64 | MASK_INT64), \
512 N_("Use 32-bit long type")}, \
513 {"split-addresses", MASK_SPLIT_ADDR, \
514 N_("Optimize lui/addiu address loads")}, \
515 {"no-split-addresses", -MASK_SPLIT_ADDR, \
516 N_("Don't optimize lui/addiu address loads")}, \
517 {"mips-as", -MASK_GAS, \
518 N_("Use MIPS as")}, \
521 {"rnames", MASK_NAME_REGS, \
522 N_("Use symbolic register names")}, \
523 {"no-rnames", -MASK_NAME_REGS, \
524 N_("Don't use symbolic register names")}, \
526 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
528 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
530 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
532 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
534 N_("Output compiler statistics (now ignored)")}, \
536 N_("Don't output compiler statistics")}, \
537 {"memcpy", MASK_MEMCPY, \
538 N_("Don't optimize block moves")}, \
539 {"no-memcpy", -MASK_MEMCPY, \
540 N_("Optimize block moves")}, \
541 {"mips-tfile", MASK_MIPS_TFILE, \
542 N_("Use mips-tfile asm postpass")}, \
543 {"no-mips-tfile", -MASK_MIPS_TFILE, \
544 N_("Don't use mips-tfile asm postpass")}, \
545 {"soft-float", MASK_SOFT_FLOAT, \
546 N_("Use software floating point")}, \
547 {"hard-float", -MASK_SOFT_FLOAT, \
548 N_("Use hardware floating point")}, \
549 {"fp64", MASK_FLOAT64, \
550 N_("Use 64-bit FP registers")}, \
551 {"fp32", -MASK_FLOAT64, \
552 N_("Use 32-bit FP registers")}, \
553 {"gp64", MASK_64BIT, \
554 N_("Use 64-bit general registers")}, \
555 {"gp32", -MASK_64BIT, \
556 N_("Use 32-bit general registers")}, \
557 {"abicalls", MASK_ABICALLS, \
558 N_("Use Irix PIC")}, \
559 {"no-abicalls", -MASK_ABICALLS, \
560 N_("Don't use Irix PIC")}, \
561 {"long-calls", MASK_LONG_CALLS, \
562 N_("Use indirect calls")}, \
563 {"no-long-calls", -MASK_LONG_CALLS, \
564 N_("Don't use indirect calls")}, \
565 {"embedded-pic", MASK_EMBEDDED_PIC, \
566 N_("Use embedded PIC")}, \
567 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
568 N_("Don't use embedded PIC")}, \
569 {"embedded-data", MASK_EMBEDDED_DATA, \
570 N_("Use ROM instead of RAM")}, \
571 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
572 N_("Don't use ROM instead of RAM")}, \
573 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
574 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
575 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
576 N_("Don't put uninitialized constants in ROM")}, \
577 {"eb", MASK_BIG_ENDIAN, \
578 N_("Use big-endian byte order")}, \
579 {"el", -MASK_BIG_ENDIAN, \
580 N_("Use little-endian byte order")}, \
581 {"single-float", MASK_SINGLE_FLOAT, \
582 N_("Use single (32-bit) FP only")}, \
583 {"double-float", -MASK_SINGLE_FLOAT, \
584 N_("Don't use single (32-bit) FP only")}, \
586 N_("Use multiply accumulate")}, \
587 {"no-mad", -MASK_MAD, \
588 N_("Don't use multiply accumulate")}, \
589 {"no-fused-madd", MASK_NO_FUSED_MADD, \
590 N_("Don't generate fused multiply/add instructions")}, \
591 {"fused-madd", -MASK_NO_FUSED_MADD, \
592 N_("Generate fused multiply/add instructions")}, \
593 {"fix4300", MASK_4300_MUL_FIX, \
594 N_("Work around early 4300 hardware bug")}, \
595 {"no-fix4300", -MASK_4300_MUL_FIX, \
596 N_("Don't work around early 4300 hardware bug")}, \
597 {"fix-sb1", MASK_FIX_SB1, \
598 N_("Work around errata for early SB-1 revision 2 cores")}, \
599 {"no-fix-sb1", -MASK_FIX_SB1, \
600 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
601 {"fix-r4000", MASK_FIX_R4000, \
602 N_("Work around R4000 errata")}, \
603 {"no-fix-r4000", -MASK_FIX_R4000, \
604 N_("Don't work around R4000 errata")}, \
605 {"fix-r4400", MASK_FIX_R4400, \
606 N_("Work around R4400 errata")}, \
607 {"no-fix-r4400", -MASK_FIX_R4400, \
608 N_("Don't work around R4400 errata")}, \
609 {"fix-vr4120", MASK_FIX_VR4120, \
610 N_("Work around certain VR4120 errata")}, \
611 {"no-fix-vr4120", -MASK_FIX_VR4120, \
612 N_("Don't work around certain VR4120 errata")}, \
613 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
614 N_("Trap on integer divide by zero")}, \
615 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
616 N_("Don't trap on integer divide by zero")}, \
617 { "branch-likely", MASK_BRANCHLIKELY, \
618 N_("Use Branch Likely instructions, overriding default for arch")}, \
619 { "no-branch-likely", -MASK_BRANCHLIKELY, \
620 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
621 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
622 N_("Use NewABI-style %reloc() assembly operators")}, \
623 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
624 N_("Use assembler macros instead of relocation operators")}, \
625 {"ips16", MASK_MIPS16, \
626 N_("Generate mips16 code") }, \
627 {"no-mips16", -MASK_MIPS16, \
628 N_("Generate normal-mode code") }, \
629 {"xgot", MASK_XGOT, \
630 N_("Lift restrictions on GOT size") }, \
631 {"no-xgot", -MASK_XGOT, \
632 N_("Do not lift restrictions on GOT size") }, \
633 {"debug", MASK_DEBUG, \
635 {"debugc", MASK_DEBUG_C, \
637 {"debugd", MASK_DEBUG_D, \
639 {"debugg", MASK_DEBUG_G, \
641 {"", (TARGET_DEFAULT \
642 | TARGET_CPU_DEFAULT \
643 | TARGET_ENDIAN_DEFAULT), \
647 /* Default target_flags if no switches are specified */
649 #ifndef TARGET_DEFAULT
650 #define TARGET_DEFAULT 0
653 #ifndef TARGET_CPU_DEFAULT
654 #define TARGET_CPU_DEFAULT 0
657 #ifndef TARGET_ENDIAN_DEFAULT
658 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
661 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
662 #ifndef MIPS_ISA_DEFAULT
663 #ifndef MIPS_CPU_STRING_DEFAULT
664 #define MIPS_CPU_STRING_DEFAULT "from-abi"
670 /* Make this compile time constant for libgcc2 */
672 #define TARGET_64BIT 1
674 #define TARGET_64BIT 0
676 #endif /* IN_LIBGCC2 */
678 #ifndef MULTILIB_ENDIAN_DEFAULT
679 #if TARGET_ENDIAN_DEFAULT == 0
680 #define MULTILIB_ENDIAN_DEFAULT "EL"
682 #define MULTILIB_ENDIAN_DEFAULT "EB"
686 #ifndef MULTILIB_ISA_DEFAULT
687 # if MIPS_ISA_DEFAULT == 1
688 # define MULTILIB_ISA_DEFAULT "mips1"
690 # if MIPS_ISA_DEFAULT == 2
691 # define MULTILIB_ISA_DEFAULT "mips2"
693 # if MIPS_ISA_DEFAULT == 3
694 # define MULTILIB_ISA_DEFAULT "mips3"
696 # if MIPS_ISA_DEFAULT == 4
697 # define MULTILIB_ISA_DEFAULT "mips4"
699 # if MIPS_ISA_DEFAULT == 32
700 # define MULTILIB_ISA_DEFAULT "mips32"
702 # if MIPS_ISA_DEFAULT == 33
703 # define MULTILIB_ISA_DEFAULT "mips32r2"
705 # if MIPS_ISA_DEFAULT == 64
706 # define MULTILIB_ISA_DEFAULT "mips64"
708 # define MULTILIB_ISA_DEFAULT "mips1"
718 #ifndef MULTILIB_DEFAULTS
719 #define MULTILIB_DEFAULTS \
720 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
723 /* We must pass -EL to the linker by default for little endian embedded
724 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
725 linker will default to using big-endian output files. The OUTPUT_FORMAT
726 line must be in the linker script, otherwise -EB/-EL will not work. */
729 #if TARGET_ENDIAN_DEFAULT == 0
730 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
732 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
736 #define TARGET_OPTIONS \
738 SUBTARGET_TARGET_OPTIONS \
739 { "tune=", &mips_tune_string, \
740 N_("Specify CPU for scheduling purposes"), 0}, \
741 { "arch=", &mips_arch_string, \
742 N_("Specify CPU for code generation purposes"), 0}, \
743 { "abi=", &mips_abi_string, \
744 N_("Specify an ABI"), 0}, \
745 { "ips", &mips_isa_string, \
746 N_("Specify a Standard MIPS ISA"), 0}, \
747 { "no-flush-func", &mips_cache_flush_func, \
748 N_("Don't call any cache flush functions"), 0}, \
749 { "flush-func=", &mips_cache_flush_func, \
750 N_("Specify cache flush function"), 0}, \
753 /* This is meant to be redefined in the host dependent files. */
754 #define SUBTARGET_TARGET_OPTIONS
756 /* Support for a compile-time default CPU, et cetera. The rules are:
757 --with-arch is ignored if -march is specified or a -mips is specified
758 (other than -mips16).
759 --with-tune is ignored if -mtune is specified.
760 --with-abi is ignored if -mabi is specified.
761 --with-float is ignored if -mhard-float or -msoft-float are
763 #define OPTION_DEFAULT_SPECS \
764 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
765 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
766 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
767 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
770 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
774 /* Generate three-operand multiply instructions for SImode. */
775 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
785 /* Generate three-operand multiply instructions for DImode. */
786 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
789 /* Macros to decide whether certain features are available or not,
790 depending on the instruction set architecture level. */
792 #define HAVE_SQRT_P() (!ISA_MIPS1)
794 /* True if the ABI can only work with 64-bit integer registers. We
795 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
796 otherwise floating-point registers must also be 64-bit. */
797 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
799 /* Likewise for 32-bit regs. */
800 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
802 /* True if symbols are 64 bits wide. At present, n64 is the only
803 ABI for which this is true. */
804 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
806 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
807 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
811 /* ISA has branch likely instructions (eg. mips2). */
812 /* Disable branchlikely for tx39 until compare rewrite. They haven't
813 been generated up to this point. */
814 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
817 /* ISA has the conditional move instructions introduced in mips4. */
818 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
822 && !TARGET_MIPS5500 \
825 /* ISA has just the integer condition move instructions (movn,movz) */
826 #define ISA_HAS_INT_CONDMOVE 0
828 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
829 branch on CC, and move (both FP and non-FP) on CC. */
830 #define ISA_HAS_8CC (ISA_MIPS4 \
835 /* This is a catch all for other mips4 instructions: indexed load, the
836 FP madd and msub instructions, and the FP recip and recip sqrt
838 #define ISA_HAS_FP4 ((ISA_MIPS4 \
842 /* ISA has conditional trap instructions. */
843 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
846 /* ISA has integer multiply-accumulate instructions, madd and msub. */
847 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
852 /* ISA has floating-point nmadd and nmsub instructions. */
853 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
855 && (!TARGET_MIPS5400 || TARGET_MAD) \
858 /* ISA has count leading zeroes/ones instruction (not implemented). */
859 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
864 /* ISA has double-word count leading zeroes/ones instruction (not
866 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
869 /* ISA has three operand multiply instructions that put
870 the high part in an accumulator: mulhi or mulhiu. */
871 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
876 /* ISA has three operand multiply instructions that
877 negates the result and puts the result in an accumulator. */
878 #define ISA_HAS_MULS (TARGET_MIPS5400 \
883 /* ISA has three operand multiply instructions that subtracts the
884 result from a 4th operand and puts the result in an accumulator. */
885 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
889 /* ISA has three operand multiply instructions that the result
890 from a 4th operand and puts the result in an accumulator. */
891 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
892 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
898 /* ISA has 32-bit rotate right instruction. */
899 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
906 /* ISA has 64-bit rotate right instruction. */
907 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
909 && (TARGET_MIPS5400 \
914 /* ISA has data prefetch instructions. This controls use of 'pref'. */
915 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
921 /* ISA has data indexed prefetch instructions. This controls use of
922 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
923 (prefx is a cop1x instruction, so can only be used if FP is
925 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
929 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
930 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
931 also requires TARGET_DOUBLE_FLOAT. */
932 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
934 /* ISA includes the MIPS32r2 seb and seh instructions. */
935 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
939 /* True if the result of a load is not available to the next instruction.
940 A nop will then be needed between instructions like "lw $4,..."
941 and "addiu $4,$4,1". */
942 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
943 && !TARGET_MIPS3900 \
946 /* Likewise mtc1 and mfc1. */
947 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
949 /* Likewise floating-point comparisons. */
950 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
952 /* True if mflo and mfhi can be immediately followed by instructions
953 which write to the HI and LO registers.
955 According to MIPS specifications, MIPS ISAs I, II, and III need
956 (at least) two instructions between the reads of HI/LO and
957 instructions which write them, and later ISAs do not. Contradicting
958 the MIPS specifications, some MIPS IV processor user manuals (e.g.
959 the UM for the NEC Vr5000) document needing the instructions between
960 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
961 MIPS64 and later ISAs to have the interlocks, plus any specific
962 earlier-ISA CPUs for which CPU documentation declares that the
963 instructions are really interlocked. */
964 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
969 /* Add -G xx support. */
971 #undef SWITCH_TAKES_ARG
972 #define SWITCH_TAKES_ARG(CHAR) \
973 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
975 #define OVERRIDE_OPTIONS override_options ()
977 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
979 /* Show we can debug even without a frame pointer. */
980 #define CAN_DEBUG_WITHOUT_FP
982 /* Tell collect what flags to pass to nm. */
984 #define NM_FLAGS "-Bn"
988 /* Assembler specs. */
990 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
993 #define MIPS_AS_ASM_SPEC "\
994 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
995 %{pipe: %e-pipe is not supported} \
996 %{K} %(subtarget_mips_as_asm_spec)"
998 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
999 rather than gas. It may be overridden by subtargets. */
1001 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1002 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1005 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1008 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1010 #define SUBTARGET_TARGET_SWITCHES
1012 #ifndef MIPS_ABI_DEFAULT
1013 #define MIPS_ABI_DEFAULT ABI_32
1016 /* Use the most portable ABI flag for the ASM specs. */
1018 #if MIPS_ABI_DEFAULT == ABI_32
1019 #define MULTILIB_ABI_DEFAULT "mabi=32"
1020 #define ASM_ABI_DEFAULT_SPEC "-32"
1023 #if MIPS_ABI_DEFAULT == ABI_O64
1024 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1025 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1028 #if MIPS_ABI_DEFAULT == ABI_N32
1029 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1030 #define ASM_ABI_DEFAULT_SPEC "-n32"
1033 #if MIPS_ABI_DEFAULT == ABI_64
1034 #define MULTILIB_ABI_DEFAULT "mabi=64"
1035 #define ASM_ABI_DEFAULT_SPEC "-64"
1038 #if MIPS_ABI_DEFAULT == ABI_EABI
1039 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1040 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1043 /* Only ELF targets can switch the ABI. */
1044 #ifndef OBJECT_FORMAT_ELF
1045 #undef ASM_ABI_DEFAULT_SPEC
1046 #define ASM_ABI_DEFAULT_SPEC ""
1049 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1050 GAS_ASM_SPEC as the default, depending upon the value of
1053 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1056 #define TARGET_ASM_SPEC "\
1057 %{mmips-as: %(mips_as_asm_spec)} \
1058 %{!mmips-as: %(gas_asm_spec)}"
1062 #define TARGET_ASM_SPEC "\
1063 %{!mgas: %(mips_as_asm_spec)} \
1064 %{mgas: %(gas_asm_spec)}"
1066 #endif /* not GAS */
1068 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1069 to the assembler. It may be overridden by subtargets. */
1070 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1071 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1073 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1076 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1077 the assembler. It may be overridden by subtargets. */
1078 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1079 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1080 %{g} %{g0} %{g1} %{g2} %{g3} \
1081 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1082 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1083 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1084 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1088 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1090 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1092 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1093 %{!gcoff*:-no-mdebug}"
1095 #define MDEBUG_ASM_SPEC ""
1096 #endif /* not GAS */
1098 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1099 overridden by subtargets. */
1101 #ifndef SUBTARGET_ASM_SPEC
1102 #define SUBTARGET_ASM_SPEC ""
1105 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1106 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1107 whether we're using GAS. These options can only be used properly
1108 with GAS, and it is better to get an error from a non-GAS assembler
1109 than to silently generate bad code. */
1113 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1114 %{mips32} %{mips32r2} %{mips64} \
1115 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1117 %(subtarget_asm_optimizing_spec) \
1118 %(subtarget_asm_debugging_spec) \
1120 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1121 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1122 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1123 %(target_asm_spec) \
1124 %(subtarget_asm_spec)"
1126 /* Extra switches sometimes passed to the linker. */
1127 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1128 will interpret it as a -b option. */
1131 #define LINK_SPEC "\
1133 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1134 %{bestGnum} %{shared} %{non_shared}"
1135 #endif /* LINK_SPEC defined */
1138 /* Specs for the compiler proper */
1140 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1141 overridden by subtargets. */
1142 #ifndef SUBTARGET_CC1_SPEC
1143 #define SUBTARGET_CC1_SPEC ""
1146 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1150 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1151 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1153 %(subtarget_cc1_spec)"
1156 /* Preprocessor specs. */
1158 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1159 overridden by subtargets. */
1160 #ifndef SUBTARGET_CPP_SPEC
1161 #define SUBTARGET_CPP_SPEC ""
1164 #define CPP_SPEC "%(subtarget_cpp_spec)"
1166 /* This macro defines names of additional specifications to put in the specs
1167 that can be used in various specifications like CC1_SPEC. Its definition
1168 is an initializer with a subgrouping for each command option.
1170 Each subgrouping contains a string constant, that defines the
1171 specification name, and a string constant that used by the GCC driver
1174 Do not define this macro if it does not need to do anything. */
1176 #define EXTRA_SPECS \
1177 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1178 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1179 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1180 { "gas_asm_spec", GAS_ASM_SPEC }, \
1181 { "target_asm_spec", TARGET_ASM_SPEC }, \
1182 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1183 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1184 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1185 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1186 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1187 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1188 { "endian_spec", ENDIAN_SPEC }, \
1189 SUBTARGET_EXTRA_SPECS
1191 #ifndef SUBTARGET_EXTRA_SPECS
1192 #define SUBTARGET_EXTRA_SPECS
1195 /* If defined, this macro is an additional prefix to try after
1196 `STANDARD_EXEC_PREFIX'. */
1198 #ifndef MD_EXEC_PREFIX
1199 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1202 #ifndef MD_STARTFILE_PREFIX
1203 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1207 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1208 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1209 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1211 #ifndef PREFERRED_DEBUGGING_TYPE
1212 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1215 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1217 /* By default, turn on GDB extensions. */
1218 #define DEFAULT_GDB_EXTENSIONS 1
1220 /* If we are passing smuggling stabs through the MIPS ECOFF object
1221 format, put a comment in front of the .stab<x> operation so
1222 that the MIPS assembler does not choke. The mips-tfile program
1223 will correctly put the stab into the object file. */
1225 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1226 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1227 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1229 /* Local compiler-generated symbols must have a prefix that the assembler
1230 understands. By default, this is $, although some targets (e.g.,
1231 NetBSD-ELF) need to override this. */
1233 #ifndef LOCAL_LABEL_PREFIX
1234 #define LOCAL_LABEL_PREFIX "$"
1237 /* By default on the mips, external symbols do not have an underscore
1238 prepended, but some targets (e.g., NetBSD) require this. */
1240 #ifndef USER_LABEL_PREFIX
1241 #define USER_LABEL_PREFIX ""
1244 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1245 since the length can run past this up to a continuation point. */
1246 #undef DBX_CONTIN_LENGTH
1247 #define DBX_CONTIN_LENGTH 1500
1249 /* How to renumber registers for dbx and gdb. */
1250 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1252 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1253 #define DWARF_FRAME_REGNUM(REG) (REG)
1255 /* The DWARF 2 CFA column which tracks the return address. */
1256 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1258 /* The DWARF 2 CFA column which tracks the return address from a
1259 signal handler context. */
1260 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1262 /* Before the prologue, RA lives in r31. */
1263 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1265 /* Describe how we implement __builtin_eh_return. */
1266 #define EH_RETURN_DATA_REGNO(N) \
1267 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1269 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1271 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1272 The default for this in 64-bit mode is 8, which causes problems with
1273 SFmode register saves. */
1274 #define DWARF_CIE_DATA_ALIGNMENT 4
1276 /* Correct the offset of automatic variables and arguments. Note that
1277 the MIPS debug format wants all automatic variables and arguments
1278 to be in terms of the virtual frame pointer (stack pointer before
1279 any adjustment in the function), while the MIPS 3.0 linker wants
1280 the frame pointer to be the stack pointer after the initial
1283 #define DEBUGGER_AUTO_OFFSET(X) \
1284 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1285 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1286 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1288 /* Target machine storage layout */
1290 #define BITS_BIG_ENDIAN 0
1291 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1292 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1294 /* Define this to set the endianness to use in libgcc2.c, which can
1295 not depend on target_flags. */
1296 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1297 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1299 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1302 #define MAX_BITS_PER_WORD 64
1304 /* Width of a word, in units (bytes). */
1305 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1306 #define MIN_UNITS_PER_WORD 4
1308 /* For MIPS, width of a floating point register. */
1309 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1311 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1312 the next available register. */
1313 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1315 /* The largest size of value that can be held in floating-point
1316 registers and moved with a single instruction. */
1317 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1319 /* The largest size of value that can be held in floating-point
1321 #define UNITS_PER_FPVALUE \
1322 (TARGET_SOFT_FLOAT ? 0 \
1323 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1324 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1326 /* The number of bytes in a double. */
1327 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1329 /* Set the sizes of the core types. */
1330 #define SHORT_TYPE_SIZE 16
1331 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1332 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1333 #define LONG_LONG_TYPE_SIZE 64
1335 #define FLOAT_TYPE_SIZE 32
1336 #define DOUBLE_TYPE_SIZE 64
1337 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1339 /* long double is not a fixed mode, but the idea is that, if we
1340 support long double, we also want a 128-bit integer type. */
1341 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1344 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1345 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1346 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1348 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1352 /* Width in bits of a pointer. */
1353 #ifndef POINTER_SIZE
1354 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1357 #define POINTERS_EXTEND_UNSIGNED 0
1359 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1360 #define PARM_BOUNDARY ((mips_abi == ABI_O64 \
1362 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1365 /* Allocation boundary (in *bits*) for the code of a function. */
1366 #define FUNCTION_BOUNDARY 32
1368 /* Alignment of field after `int : 0' in a structure. */
1369 #define EMPTY_FIELD_BOUNDARY 32
1371 /* Every structure's size must be a multiple of this. */
1372 /* 8 is observed right on a DECstation and on riscos 4.02. */
1373 #define STRUCTURE_SIZE_BOUNDARY 8
1375 /* There is no point aligning anything to a rounder boundary than this. */
1376 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1378 /* All accesses must be aligned. */
1379 #define STRICT_ALIGNMENT 1
1381 /* Define this if you wish to imitate the way many other C compilers
1382 handle alignment of bitfields and the structures that contain
1385 The behavior is that the type written for a bit-field (`int',
1386 `short', or other integer type) imposes an alignment for the
1387 entire structure, as if the structure really did contain an
1388 ordinary field of that type. In addition, the bit-field is placed
1389 within the structure so that it would fit within such a field,
1390 not crossing a boundary for it.
1392 Thus, on most machines, a bit-field whose type is written as `int'
1393 would not cross a four-byte boundary, and would force four-byte
1394 alignment for the whole structure. (The alignment used may not
1395 be four bytes; it is controlled by the other alignment
1398 If the macro is defined, its definition should be a C expression;
1399 a nonzero value for the expression enables this behavior. */
1401 #define PCC_BITFIELD_TYPE_MATTERS 1
1403 /* If defined, a C expression to compute the alignment given to a
1404 constant that is being placed in memory. CONSTANT is the constant
1405 and ALIGN is the alignment that the object would ordinarily have.
1406 The value of this macro is used instead of that alignment to align
1409 If this macro is not defined, then ALIGN is used.
1411 The typical use of this macro is to increase alignment for string
1412 constants to be word aligned so that `strcpy' calls that copy
1413 constants can be done inline. */
1415 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1416 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1417 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1419 /* If defined, a C expression to compute the alignment for a static
1420 variable. TYPE is the data type, and ALIGN is the alignment that
1421 the object would ordinarily have. The value of this macro is used
1422 instead of that alignment to align the object.
1424 If this macro is not defined, then ALIGN is used.
1426 One use of this macro is to increase alignment of medium-size
1427 data to make it all fit in fewer cache lines. Another is to
1428 cause character arrays to be word-aligned so that `strcpy' calls
1429 that copy constants to character arrays can be done inline. */
1431 #undef DATA_ALIGNMENT
1432 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1433 ((((ALIGN) < BITS_PER_WORD) \
1434 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1435 || TREE_CODE (TYPE) == UNION_TYPE \
1436 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1439 #define PAD_VARARGS_DOWN \
1440 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1442 /* Define if operations between registers always perform the operation
1443 on the full register even if a narrower mode is specified. */
1444 #define WORD_REGISTER_OPERATIONS
1446 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1447 moves. All other references are zero extended. */
1448 #define LOAD_EXTEND_OP(MODE) \
1449 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1450 ? SIGN_EXTEND : ZERO_EXTEND)
1452 /* Define this macro if it is advisable to hold scalars in registers
1453 in a wider mode than that declared by the program. In such cases,
1454 the value is constrained to be within the bounds of the declared
1455 type, but kept valid in the wider mode. The signedness of the
1456 extension may differ from that of the type. */
1458 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1459 if (GET_MODE_CLASS (MODE) == MODE_INT \
1460 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1462 if ((MODE) == SImode) \
1467 /* Define if loading short immediate values into registers sign extends. */
1468 #define SHORT_IMMEDIATES_SIGN_EXTEND
1470 /* Standard register usage. */
1472 /* Number of hardware registers. We have:
1474 - 32 integer registers
1475 - 32 floating point registers
1476 - 8 condition code registers
1477 - 2 accumulator registers (hi and lo)
1478 - 32 registers each for coprocessors 0, 2 and 3
1480 - ARG_POINTER_REGNUM
1481 - FRAME_POINTER_REGNUM
1482 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1483 - 3 dummy entries that were used at various times in the past. */
1485 #define FIRST_PSEUDO_REGISTER 176
1487 /* By default, fix the kernel registers ($26 and $27), the global
1488 pointer ($28) and the stack pointer ($29). This can change
1489 depending on the command-line options.
1491 Regarding coprocessor registers: without evidence to the contrary,
1492 it's best to assume that each coprocessor register has a unique
1493 use. This can be overridden, in, e.g., override_options() or
1494 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1495 for a particular target. */
1497 #define FIXED_REGISTERS \
1499 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1500 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1503 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1504 /* COP0 registers */ \
1505 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1506 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1507 /* COP2 registers */ \
1508 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1509 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1510 /* COP3 registers */ \
1511 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1512 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1516 /* Set up this array for o32 by default.
1518 Note that we don't mark $31 as a call-clobbered register. The idea is
1519 that it's really the call instructions themselves which clobber $31.
1520 We don't care what the called function does with it afterwards.
1522 This approach makes it easier to implement sibcalls. Unlike normal
1523 calls, sibcalls don't clobber $31, so the register reaches the
1524 called function in tact. EPILOGUE_USES says that $31 is useful
1525 to the called function. */
1527 #define CALL_USED_REGISTERS \
1529 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1530 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1531 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1532 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 /* COP0 registers */ \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 /* COP2 registers */ \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 /* COP3 registers */ \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1546 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1548 #define CALL_REALLY_USED_REGISTERS \
1549 { /* General registers. */ \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1552 /* Floating-point registers. */ \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1557 /* COP0 registers */ \
1558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1560 /* COP2 registers */ \
1561 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1562 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1563 /* COP3 registers */ \
1564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1568 /* Internal macros to classify a register number as to whether it's a
1569 general purpose register, a floating point register, a
1570 multiply/divide register, or a status register. */
1572 #define GP_REG_FIRST 0
1573 #define GP_REG_LAST 31
1574 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1575 #define GP_DBX_FIRST 0
1577 #define FP_REG_FIRST 32
1578 #define FP_REG_LAST 63
1579 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1580 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1582 #define MD_REG_FIRST 64
1583 #define MD_REG_LAST 65
1584 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1585 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1587 #define ST_REG_FIRST 67
1588 #define ST_REG_LAST 74
1589 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1592 /* FIXME: renumber. */
1593 #define COP0_REG_FIRST 80
1594 #define COP0_REG_LAST 111
1595 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1597 #define COP2_REG_FIRST 112
1598 #define COP2_REG_LAST 143
1599 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1601 #define COP3_REG_FIRST 144
1602 #define COP3_REG_LAST 175
1603 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1604 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1605 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1607 #define AT_REGNUM (GP_REG_FIRST + 1)
1608 #define HI_REGNUM (MD_REG_FIRST + 0)
1609 #define LO_REGNUM (MD_REG_FIRST + 1)
1611 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1612 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1613 should be used instead. */
1614 #define FPSW_REGNUM ST_REG_FIRST
1616 #define GP_REG_P(REGNO) \
1617 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1618 #define M16_REG_P(REGNO) \
1619 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1620 #define FP_REG_P(REGNO) \
1621 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1622 #define MD_REG_P(REGNO) \
1623 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1624 #define ST_REG_P(REGNO) \
1625 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1626 #define COP0_REG_P(REGNO) \
1627 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1628 #define COP2_REG_P(REGNO) \
1629 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1630 #define COP3_REG_P(REGNO) \
1631 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1632 #define ALL_COP_REG_P(REGNO) \
1633 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1635 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1637 /* Return coprocessor number from register number. */
1639 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1640 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1641 : COP3_REG_P (REGNO) ? '3' : '?')
1644 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1646 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1647 array built in override_options. Because machmodes.h is not yet
1648 included before this file is processed, the MODE bound can't be
1651 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1653 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1654 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1656 /* Value is 1 if it is a good idea to tie two pseudo registers
1657 when one has mode MODE1 and one has mode MODE2.
1658 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1659 for any hard reg, then this must be 0 for correct output. */
1660 #define MODES_TIEABLE_P(MODE1, MODE2) \
1661 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1662 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1663 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1664 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1666 /* Register to use for pushing function arguments. */
1667 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1669 /* These two registers don't really exist: they get eliminated to either
1670 the stack or hard frame pointer. */
1671 #define ARG_POINTER_REGNUM 77
1672 #define FRAME_POINTER_REGNUM 78
1674 /* $30 is not available on the mips16, so we use $17 as the frame
1676 #define HARD_FRAME_POINTER_REGNUM \
1677 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1679 /* Value should be nonzero if functions must have frame pointers.
1680 Zero means the frame pointer need not be set up (and parms
1681 may be accessed via the stack pointer) in functions that seem suitable.
1682 This is computed in `reload', in reload1.c. */
1683 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1685 /* Register in which static-chain is passed to a function. */
1686 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1688 /* Registers used as temporaries in prologue/epilogue code. If we're
1689 generating mips16 code, these registers must come from the core set
1690 of 8. The prologue register mustn't conflict with any incoming
1691 arguments, the static chain pointer, or the frame pointer. The
1692 epilogue temporary mustn't conflict with the return registers, the
1693 frame pointer, the EH stack adjustment, or the EH data registers. */
1695 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1696 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1698 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1699 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1701 /* Define this macro if it is as good or better to call a constant
1702 function address than to call an address kept in a register. */
1703 #define NO_FUNCTION_CSE 1
1705 /* Define this macro if it is as good or better for a function to
1706 call itself with an explicit address than to call an address
1707 kept in a register. */
1708 #define NO_RECURSIVE_FUNCTION_CSE 1
1710 /* The ABI-defined global pointer. Sometimes we use a different
1711 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1712 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1714 /* We normally use $28 as the global pointer. However, when generating
1715 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1716 register instead. They can then avoid saving and restoring $28
1717 and perhaps avoid using a frame at all.
1719 When a leaf function uses something other than $28, mips_expand_prologue
1720 will modify pic_offset_table_rtx in place. Take the register number
1721 from there after reload. */
1722 #define PIC_OFFSET_TABLE_REGNUM \
1723 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1725 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1727 /* Define the classes of registers for register constraints in the
1728 machine description. Also define ranges of constants.
1730 One of the classes must always be named ALL_REGS and include all hard regs.
1731 If there is more than one class, another class must be named NO_REGS
1732 and contain no registers.
1734 The name GENERAL_REGS must be the name of a class (or an alias for
1735 another name such as ALL_REGS). This is the class of registers
1736 that is allowed by "g" or "r" in a register constraint.
1737 Also, registers outside this class are allocated only when
1738 instructions express preferences for them.
1740 The classes must be numbered in nondecreasing order; that is,
1741 a larger-numbered class must never be contained completely
1742 in a smaller-numbered class.
1744 For any two classes, it is very desirable that there be another
1745 class that represents their union. */
1749 NO_REGS, /* no registers in set */
1750 M16_NA_REGS, /* mips16 regs not used to pass args */
1751 M16_REGS, /* mips16 directly accessible registers */
1752 T_REG, /* mips16 T register ($24) */
1753 M16_T_REGS, /* mips16 registers plus T register */
1754 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1755 LEA_REGS, /* Every GPR except $25 */
1756 GR_REGS, /* integer registers */
1757 FP_REGS, /* floating point registers */
1758 HI_REG, /* hi register */
1759 LO_REG, /* lo register */
1760 MD_REGS, /* multiply/divide registers (hi/lo) */
1761 COP0_REGS, /* generic coprocessor classes */
1764 HI_AND_GR_REGS, /* union classes */
1771 ALL_COP_AND_GR_REGS,
1772 ST_REGS, /* status registers (fp status) */
1773 ALL_REGS, /* all registers */
1774 LIM_REG_CLASSES /* max value + 1 */
1777 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1779 #define GENERAL_REGS GR_REGS
1781 /* An initializer containing the names of the register classes as C
1782 string constants. These names are used in writing some of the
1785 #define REG_CLASS_NAMES \
1792 "PIC_FN_ADDR_REG", \
1799 /* coprocessor registers */ \
1806 "COP0_AND_GR_REGS", \
1807 "COP2_AND_GR_REGS", \
1808 "COP3_AND_GR_REGS", \
1810 "ALL_COP_AND_GR_REGS", \
1815 /* An initializer containing the contents of the register classes,
1816 as integers which are bit masks. The Nth integer specifies the
1817 contents of class N. The way the integer MASK is interpreted is
1818 that register R is in the class if `MASK & (1 << R)' is 1.
1820 When the machine has more than 32 registers, an integer does not
1821 suffice. Then the integers are replaced by sub-initializers,
1822 braced groupings containing several integers. Each
1823 sub-initializer must be suitable as an initializer for the type
1824 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1826 #define REG_CLASS_CONTENTS \
1828 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1829 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1830 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1831 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1832 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1833 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1834 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1835 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1836 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1837 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1838 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1839 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1840 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1841 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1842 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1843 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1844 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1845 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1846 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1847 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1848 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1849 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1850 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1851 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1852 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1856 /* A C expression whose value is a register class containing hard
1857 register REGNO. In general there is more that one such class;
1858 choose a class which is "minimal", meaning that no smaller class
1859 also contains the register. */
1861 extern const enum reg_class mips_regno_to_class[];
1863 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1865 /* A macro whose definition is the name of the class to which a
1866 valid base register must belong. A base register is one used in
1867 an address which is the register value plus a displacement. */
1869 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1871 /* A macro whose definition is the name of the class to which a
1872 valid index register must belong. An index register is one used
1873 in an address where its value is either multiplied by a scale
1874 factor or added to another register (as well as added to a
1877 #define INDEX_REG_CLASS NO_REGS
1879 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1880 registers explicitly used in the rtl to be used as spill registers
1881 but prevents the compiler from extending the lifetime of these
1884 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1886 /* This macro is used later on in the file. */
1887 #define GR_REG_CLASS_P(CLASS) \
1888 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1889 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1890 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1892 /* This macro is also used later on in the file. */
1893 #define COP_REG_CLASS_P(CLASS) \
1894 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1896 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1897 is the default value (allocate the registers in numeric order). We
1898 define it just so that we can override it for the mips16 target in
1899 ORDER_REGS_FOR_LOCAL_ALLOC. */
1901 #define REG_ALLOC_ORDER \
1902 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1903 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1904 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1905 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1906 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1907 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1908 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1909 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1910 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1911 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1912 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1915 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1916 to be rearranged based on a particular function. On the mips16, we
1917 want to allocate $24 (T_REG) before other registers for
1918 instructions for which it is possible. */
1920 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1922 /* REGISTER AND CONSTANT CLASSES */
1924 /* Get reg_class from a letter such as appears in the machine
1927 DEFINED REGISTER CLASSES:
1929 'd' General (aka integer) registers
1930 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1931 'y' General registers (in both mips16 and non mips16 mode)
1932 'e' Effective address registers (general registers except $25)
1933 't' mips16 temporary register ($24)
1934 'f' Floating point registers
1937 'x' Multiply/divide registers
1938 'z' FP Status register
1942 'b' All registers */
1944 extern enum reg_class mips_char_to_class[256];
1946 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1948 /* True if VALUE is a signed 16-bit number. */
1950 #define SMALL_OPERAND(VALUE) \
1951 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1953 /* True if VALUE is an unsigned 16-bit number. */
1955 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1956 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1958 /* True if VALUE can be loaded into a register using LUI. */
1960 #define LUI_OPERAND(VALUE) \
1961 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1962 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1964 /* Return a value X with the low 16 bits clear, and such that
1965 VALUE - X is a signed 16-bit value. */
1967 #define CONST_HIGH_PART(VALUE) \
1968 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1970 #define CONST_LOW_PART(VALUE) \
1971 ((VALUE) - CONST_HIGH_PART (VALUE))
1973 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1974 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1975 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1977 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1978 string can be used to stand for particular ranges of immediate
1979 operands. This macro defines what the ranges are. C is the
1980 letter, and VALUE is a constant value. Return 1 if VALUE is
1981 in the range specified by C. */
1985 `I' is used for the range of constants an arithmetic insn can
1986 actually contain (16 bits signed integers).
1988 `J' is used for the range which is just zero (ie, $r0).
1990 `K' is used for the range of constants a logical insn can actually
1991 contain (16 bit zero-extended integers).
1993 `L' is used for the range of constants that be loaded with lui
1994 (ie, the bottom 16 bits are zero).
1996 `M' is used for the range of constants that take two words to load
1997 (ie, not matched by `I', `K', and `L').
1999 `N' is used for negative 16 bit constants other than -65536.
2001 `O' is a 15 bit signed integer.
2003 `P' is used for positive 16 bit constants. */
2005 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2006 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2007 : (C) == 'J' ? ((VALUE) == 0) \
2008 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2009 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2010 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2011 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2012 && !LUI_OPERAND (VALUE)) \
2013 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2014 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2015 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2018 /* Similar, but for floating constants, and defining letters G and H.
2019 Here VALUE is the CONST_DOUBLE rtx itself. */
2023 'G' : Floating point 0 */
2025 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2027 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2029 /* Letters in the range `Q' through `U' may be defined in a
2030 machine-dependent fashion to stand for arbitrary operand types.
2031 The machine description macro `EXTRA_CONSTRAINT' is passed the
2032 operand as its first argument and the constraint letter as its
2035 `Q' is for signed 16-bit constants.
2036 `R' is for single-instruction memory references. Note that this
2037 constraint has often been used in linux and glibc code.
2038 `S' is for legitimate constant call addresses.
2039 `T' is for constant move_operands that cannot be safely loaded into $25.
2040 `U' is for constant move_operands that can be safely loaded into $25.
2041 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2042 This is true for all non-mips16 references (although it can somtimes
2043 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2044 stack and constant-pool references. */
2046 #define EXTRA_CONSTRAINT(OP,CODE) \
2047 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2048 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2049 && mips_fetch_insns (OP) == 1) \
2050 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2051 && call_insn_operand (OP, VOIDmode)) \
2052 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2053 && move_operand (OP, VOIDmode) \
2054 && mips_dangerous_for_la25_p (OP)) \
2055 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2056 && move_operand (OP, VOIDmode) \
2057 && !mips_dangerous_for_la25_p (OP)) \
2058 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2059 && memory_operand (OP, VOIDmode) \
2060 && (!TARGET_MIPS16 \
2061 || (!stack_operand (OP, VOIDmode) \
2062 && !CONSTANT_P (XEXP (OP, 0))))) \
2065 /* Say which of the above are memory constraints. */
2066 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2068 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2069 mips_preferred_reload_class (X, CLASS)
2071 /* Certain machines have the property that some registers cannot be
2072 copied to some other registers without using memory. Define this
2073 macro on those machines to be a C expression that is nonzero if
2074 objects of mode MODE in registers of CLASS1 can only be copied to
2075 registers of class CLASS2 by storing a register of CLASS1 into
2076 memory and loading that memory location into a register of CLASS2.
2078 Do not define this macro if its value would always be zero. */
2080 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2081 ((!TARGET_DEBUG_H_MODE \
2082 && GET_MODE_CLASS (MODE) == MODE_INT \
2083 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2084 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2085 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2086 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2087 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2089 /* The HI and LO registers can only be reloaded via the general
2090 registers. Condition code registers can only be loaded to the
2091 general registers, and from the floating point registers. */
2093 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2094 mips_secondary_reload_class (CLASS, MODE, X, 1)
2095 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2096 mips_secondary_reload_class (CLASS, MODE, X, 0)
2098 /* Return the maximum number of consecutive registers
2099 needed to represent mode MODE in a register of class CLASS. */
2101 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2103 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2104 mips_cannot_change_mode_class (FROM, TO, CLASS)
2106 /* Stack layout; function entry, exit and calling. */
2108 #define STACK_GROWS_DOWNWARD
2110 /* The offset of the first local variable from the beginning of the frame.
2111 See compute_frame_size for details about the frame layout. */
2112 #define STARTING_FRAME_OFFSET \
2113 (current_function_outgoing_args_size \
2114 + (TARGET_ABICALLS && !TARGET_NEWABI \
2115 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2117 #define RETURN_ADDR_RTX mips_return_addr
2119 /* Since the mips16 ISA mode is encoded in the least-significant bit
2120 of the address, mask it off return addresses for purposes of
2121 finding exception handling regions. */
2123 #define MASK_RETURN_ADDR GEN_INT (-2)
2126 /* Similarly, don't use the least-significant bit to tell pointers to
2127 code from vtable index. */
2129 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2131 /* The eliminations to $17 are only used for mips16 code. See the
2132 definition of HARD_FRAME_POINTER_REGNUM. */
2134 #define ELIMINABLE_REGS \
2135 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2136 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2137 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2138 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2139 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2140 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2142 /* We can always eliminate to the hard frame pointer. We can eliminate
2143 to the stack pointer unless a frame pointer is needed.
2145 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2146 reload may be unable to compute the address of a local variable,
2147 since there is no way to add a large constant to the stack pointer
2148 without using a temporary register. */
2149 #define CAN_ELIMINATE(FROM, TO) \
2150 ((TO) == HARD_FRAME_POINTER_REGNUM \
2151 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2152 && (!TARGET_MIPS16 \
2153 || compute_frame_size (get_frame_size ()) < 32768)))
2155 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2156 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2158 /* Allocate stack space for arguments at the beginning of each function. */
2159 #define ACCUMULATE_OUTGOING_ARGS 1
2161 /* The argument pointer always points to the first argument. */
2162 #define FIRST_PARM_OFFSET(FNDECL) 0
2164 /* o32 and o64 reserve stack space for all argument registers. */
2165 #define REG_PARM_STACK_SPACE(FNDECL) \
2167 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2170 /* Define this if it is the responsibility of the caller to
2171 allocate the area reserved for arguments passed in registers.
2172 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2173 of this macro is to determine whether the space is included in
2174 `current_function_outgoing_args_size'. */
2175 #define OUTGOING_REG_PARM_STACK_SPACE
2177 #define STACK_BOUNDARY ((TARGET_OLDABI || mips_abi == ABI_EABI) ? 64 : 128)
2179 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2181 /* Symbolic macros for the registers used to return integer and floating
2184 #define GP_RETURN (GP_REG_FIRST + 2)
2185 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2187 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2189 /* Symbolic macros for the first/last argument registers. */
2191 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2192 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2193 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2194 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2196 #define LIBCALL_VALUE(MODE) \
2197 mips_function_value (NULL_TREE, NULL, (MODE))
2199 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2200 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2202 /* 1 if N is a possible register number for a function value.
2203 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2204 Currently, R2 and F0 are only implemented here (C has no complex type) */
2206 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2207 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2208 && (N) == FP_RETURN + 2))
2210 /* 1 if N is a possible register number for function argument passing.
2211 We have no FP argument registers when soft-float. When FP registers
2212 are 32 bits, we can't directly reference the odd numbered ones. */
2214 #define FUNCTION_ARG_REGNO_P(N) \
2215 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2216 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2219 /* This structure has to cope with two different argument allocation
2220 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2221 first N words go in registers and the rest go on the stack. If I < N,
2222 the Ith word might go in Ith integer argument register or the
2223 Ith floating-point one. For these ABIs, we only need to remember
2224 the number of words passed so far.
2226 The EABI instead allocates the integer and floating-point arguments
2227 separately. The first N words of FP arguments go in FP registers,
2228 the rest go on the stack. Likewise, the first N words of the other
2229 arguments go in integer registers, and the rest go on the stack. We
2230 need to maintain three counts: the number of integer registers used,
2231 the number of floating-point registers used, and the number of words
2232 passed on the stack.
2234 We could keep separate information for the two ABIs (a word count for
2235 the standard ABIs, and three separate counts for the EABI). But it
2236 seems simpler to view the standard ABIs as forms of EABI that do not
2237 allocate floating-point registers.
2239 So for the standard ABIs, the first N words are allocated to integer
2240 registers, and function_arg decides on an argument-by-argument basis
2241 whether that argument should really go in an integer register, or in
2242 a floating-point one. */
2244 typedef struct mips_args {
2245 /* Always true for varargs functions. Otherwise true if at least
2246 one argument has been passed in an integer register. */
2249 /* The number of arguments seen so far. */
2250 unsigned int arg_number;
2252 /* For EABI, the number of integer registers used so far. For other
2253 ABIs, the number of words passed in registers (whether integer
2254 or floating-point). */
2255 unsigned int num_gprs;
2257 /* For EABI, the number of floating-point registers used so far. */
2258 unsigned int num_fprs;
2260 /* The number of words passed on the stack. */
2261 unsigned int stack_words;
2263 /* On the mips16, we need to keep track of which floating point
2264 arguments were passed in general registers, but would have been
2265 passed in the FP regs if this were a 32 bit function, so that we
2266 can move them to the FP regs if we wind up calling a 32 bit
2267 function. We record this information in fp_code, encoded in base
2268 four. A zero digit means no floating point argument, a one digit
2269 means an SFmode argument, and a two digit means a DFmode argument,
2270 and a three digit is not used. The low order digit is the first
2271 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2272 an SFmode argument. ??? A more sophisticated approach will be
2273 needed if MIPS_ABI != ABI_32. */
2276 /* True if the function has a prototype. */
2280 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2281 for a call to a function whose data type is FNTYPE.
2282 For a library call, FNTYPE is 0. */
2284 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2285 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2287 /* Update the data in CUM to advance over an argument
2288 of mode MODE and data type TYPE.
2289 (TYPE is null for libcalls where that information may not be available.) */
2291 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2292 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2294 /* Determine where to put an argument to a function.
2295 Value is zero to push the argument on the stack,
2296 or a hard register in which to store the argument.
2298 MODE is the argument's machine mode.
2299 TYPE is the data type of the argument (as a tree).
2300 This is null for libcalls where that information may
2302 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2303 the preceding args and about the function being called.
2304 NAMED is nonzero if this argument is a named parameter
2305 (otherwise it is an extra parameter matching an ellipsis). */
2307 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2308 function_arg( &CUM, MODE, TYPE, NAMED)
2310 /* For an arg passed partly in registers and partly in memory,
2311 this is the number of registers used.
2312 For args passed entirely in registers or entirely in memory, zero. */
2314 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2315 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2317 /* If defined, a C expression that gives the alignment boundary, in
2318 bits, of an argument with the specified mode and type. If it is
2319 not defined, `PARM_BOUNDARY' is used for all arguments. */
2321 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2323 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2325 : TYPE_ALIGN(TYPE)) \
2326 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2328 : GET_MODE_ALIGNMENT(MODE)))
2330 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2331 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2333 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2334 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2336 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2337 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2339 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2340 (mips_abi == ABI_EABI && (NAMED) \
2341 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2343 /* Modified version of the macro in expr.h. Only return true if
2344 the type has a variable size or if the front end requires it
2345 to be passed by reference. */
2346 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2348 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2349 || TREE_ADDRESSABLE (TYPE)))
2351 /* True if using EABI and varargs can be passed in floating-point
2352 registers. Under these conditions, we need a more complex form
2353 of va_list, which tracks GPR, FPR and stack arguments separately. */
2354 #define EABI_FLOAT_VARARGS_P \
2355 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2358 /* Say that the epilogue uses the return address register. Note that
2359 in the case of sibcalls, the values "used by the epilogue" are
2360 considered live at the start of the called function. */
2361 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2363 /* Treat LOC as a byte offset from the stack pointer and round it up
2364 to the next fully-aligned offset. */
2365 #define MIPS_STACK_ALIGN(LOC) \
2366 ((TARGET_OLDABI || mips_abi == ABI_EABI) \
2367 ? ((LOC) + 7) & ~7 \
2368 : ((LOC) + 15) & ~15)
2371 /* Implement `va_start' for varargs and stdarg. */
2372 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2373 mips_va_start (valist, nextarg)
2375 /* Implement `va_arg'. */
2376 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2377 mips_va_arg (valist, type)
2379 /* Output assembler code to FILE to increment profiler label # LABELNO
2380 for profiling a function entry. */
2382 #define FUNCTION_PROFILER(FILE, LABELNO) \
2384 if (TARGET_MIPS16) \
2385 sorry ("mips16 function profiling"); \
2386 fprintf (FILE, "\t.set\tnoat\n"); \
2387 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2388 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2389 if (!TARGET_NEWABI) \
2392 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2393 TARGET_64BIT ? "dsubu" : "subu", \
2394 reg_names[STACK_POINTER_REGNUM], \
2395 reg_names[STACK_POINTER_REGNUM], \
2396 Pmode == DImode ? 16 : 8); \
2398 fprintf (FILE, "\tjal\t_mcount\n"); \
2399 fprintf (FILE, "\t.set\tat\n"); \
2402 /* Define this macro if the code for function profiling should come
2403 before the function prologue. Normally, the profiling code comes
2406 /* #define PROFILE_BEFORE_PROLOGUE */
2408 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2409 the stack pointer does not matter. The value is tested only in
2410 functions that have frame pointers.
2411 No definition is equivalent to always zero. */
2413 #define EXIT_IGNORE_STACK 1
2416 /* A C statement to output, on the stream FILE, assembler code for a
2417 block of data that contains the constant parts of a trampoline.
2418 This code should not include a label--the label is taken care of
2421 #define TRAMPOLINE_TEMPLATE(STREAM) \
2423 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2424 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2425 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2426 if (ptr_mode == DImode) \
2428 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2429 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2433 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2434 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2436 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2437 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2438 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2439 if (ptr_mode == DImode) \
2441 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2442 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2446 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2447 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2451 /* A C expression for the size in bytes of the trampoline, as an
2454 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2456 /* Alignment required for trampolines, in bits. */
2458 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2460 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2461 program and data caches. */
2463 #ifndef CACHE_FLUSH_FUNC
2464 #define CACHE_FLUSH_FUNC "_flush_cache"
2467 /* A C statement to initialize the variable parts of a trampoline.
2468 ADDR is an RTX for the address of the trampoline; FNADDR is an
2469 RTX for the address of the nested function; STATIC_CHAIN is an
2470 RTX for the static chain value that should be passed to the
2471 function when it is called. */
2473 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2475 rtx func_addr, chain_addr; \
2477 func_addr = plus_constant (ADDR, 32); \
2478 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2479 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2480 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2482 /* Flush both caches. We need to flush the data cache in case \
2483 the system has a write-back cache. */ \
2484 /* ??? Should check the return value for errors. */ \
2485 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2486 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2487 0, VOIDmode, 3, ADDR, Pmode, \
2488 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2489 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2492 /* Addressing modes, and classification of registers for them. */
2494 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2495 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2496 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2498 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2499 and check its validity for a certain class.
2500 We have two alternate definitions for each of them.
2501 The usual definition accepts all pseudo regs; the other rejects them all.
2502 The symbol REG_OK_STRICT causes the latter definition to be used.
2504 Most source files want to accept pseudo regs in the hope that
2505 they will get allocated to the class that the insn wants them to be in.
2506 Some source files that are used after register allocation
2507 need to be strict. */
2509 #ifndef REG_OK_STRICT
2510 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2511 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2513 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2514 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2517 #define REG_OK_FOR_INDEX_P(X) 0
2520 /* Maximum number of registers that can appear in a valid memory address. */
2522 #define MAX_REGS_PER_ADDRESS 1
2524 #ifdef REG_OK_STRICT
2525 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2527 if (mips_legitimate_address_p (MODE, X, 1)) \
2531 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2533 if (mips_legitimate_address_p (MODE, X, 0)) \
2538 /* Check for constness inline but use mips_legitimate_address_p
2539 to check whether a constant really is an address. */
2541 #define CONSTANT_ADDRESS_P(X) \
2542 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2544 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2546 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2548 if (mips_legitimize_address (&(X), MODE)) \
2553 /* A C statement or compound statement with a conditional `goto
2554 LABEL;' executed if memory address X (an RTX) can have different
2555 meanings depending on the machine mode of the memory reference it
2558 Autoincrement and autodecrement addresses typically have
2559 mode-dependent effects because the amount of the increment or
2560 decrement is the size of the operand being addressed. Some
2561 machines have other mode-dependent addresses. Many RISC machines
2562 have no mode-dependent addresses.
2564 You may assume that ADDR is a valid address for the machine. */
2566 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2568 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2569 'the start of the function that this code is output in'. */
2571 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2572 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2573 asm_fprintf ((FILE), "%U%s", \
2574 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2576 asm_fprintf ((FILE), "%U%s", (NAME))
2578 /* Specify the machine mode that this machine uses
2579 for the index in the tablejump instruction.
2580 ??? Using HImode in mips16 mode can cause overflow. */
2581 #define CASE_VECTOR_MODE \
2582 (TARGET_MIPS16 ? HImode : ptr_mode)
2584 /* Define as C expression which evaluates to nonzero if the tablejump
2585 instruction expects the table to contain offsets from the address of the
2587 Do not define this if the table should contain absolute addresses. */
2588 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2590 /* Define this as 1 if `char' should by default be signed; else as 0. */
2591 #ifndef DEFAULT_SIGNED_CHAR
2592 #define DEFAULT_SIGNED_CHAR 1
2595 /* Max number of bytes we can move from memory to memory
2596 in one reasonably fast instruction. */
2597 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2598 #define MAX_MOVE_MAX 8
2600 /* Define this macro as a C expression which is nonzero if
2601 accessing less than a word of memory (i.e. a `char' or a
2602 `short') is no faster than accessing a word of memory, i.e., if
2603 such access require more than one instruction or if there is no
2604 difference in cost between byte and (aligned) word loads.
2606 On RISC machines, it tends to generate better code to define
2607 this as 1, since it avoids making a QI or HI mode register. */
2608 #define SLOW_BYTE_ACCESS 1
2610 /* Define this to be nonzero if shift instructions ignore all but the low-order
2612 #define SHIFT_COUNT_TRUNCATED 1
2614 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2615 is done just by pretending it is already truncated. */
2616 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2617 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2620 /* Specify the machine mode that pointers have.
2621 After generation of rtl, the compiler makes no further distinction
2622 between pointers and any other objects of this machine mode. */
2625 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2628 /* Give call MEMs SImode since it is the "most permissive" mode
2629 for both 32-bit and 64-bit targets. */
2631 #define FUNCTION_MODE SImode
2634 /* The cost of loading values from the constant pool. It should be
2635 larger than the cost of any constant we want to synthesize in-line. */
2637 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2639 /* A C expression for the cost of moving data from a register in
2640 class FROM to one in class TO. The classes are expressed using
2641 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2642 the default; other values are interpreted relative to that.
2644 It is not required that the cost always equal 2 when FROM is the
2645 same as TO; on some machines it is expensive to move between
2646 registers if they are not general registers.
2648 If reload sees an insn consisting of a single `set' between two
2649 hard registers, and if `REGISTER_MOVE_COST' applied to their
2650 classes returns a value of 2, reload does not check to ensure
2651 that the constraints of the insn are met. Setting a cost of
2652 other than 2 will allow reload to verify that the constraints are
2653 met. You should do this if the `movM' pattern's constraints do
2654 not allow such copying. */
2656 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2657 mips_register_move_cost (MODE, FROM, TO)
2659 /* ??? Fix this to be right for the R8000. */
2660 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2661 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2662 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2664 /* Define if copies to/from condition code registers should be avoided.
2666 This is needed for the MIPS because reload_outcc is not complete;
2667 it needs to handle cases where the source is a general or another
2668 condition code register. */
2669 #define AVOID_CCMODE_COPIES
2671 /* A C expression for the cost of a branch instruction. A value of
2672 1 is the default; other values are interpreted relative to that. */
2674 /* ??? Fix this to be right for the R8000. */
2675 #define BRANCH_COST \
2677 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2680 /* If defined, modifies the length assigned to instruction INSN as a
2681 function of the context in which it is used. LENGTH is an lvalue
2682 that contains the initially computed length of the insn and should
2683 be updated with the correct length of the insn. */
2684 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2685 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2688 /* Optionally define this if you have added predicates to
2689 `MACHINE.c'. This macro is called within an initializer of an
2690 array of structures. The first field in the structure is the
2691 name of a predicate and the second field is an array of rtl
2692 codes. For each predicate, list all rtl codes that can be in
2693 expressions matched by the predicate. The list should have a
2694 trailing comma. Here is an example of two entries in the list
2695 for a typical RISC machine:
2697 #define PREDICATE_CODES \
2698 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2699 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2701 Defining this macro does not affect the generated code (however,
2702 incorrect definitions that omit an rtl code that may be matched
2703 by the predicate can cause the compiler to malfunction).
2704 Instead, it allows the table built by `genrecog' to be more
2705 compact and efficient, thus speeding up the compiler. The most
2706 important predicates to include in the list specified by this
2707 macro are thoses used in the most insn patterns. */
2709 #define PREDICATE_CODES \
2710 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2711 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2712 {"general_symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2713 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2714 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2715 {"const_arith_operand", { CONST_INT }}, \
2716 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2717 UNSPEC_VOLATILE }}, \
2718 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2719 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2720 {"small_int", { CONST_INT }}, \
2721 {"const_float_1_operand", { CONST_DOUBLE }}, \
2722 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2723 {"equality_op", { EQ, NE }}, \
2724 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2726 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2727 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2728 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2729 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2730 SYMBOL_REF, LABEL_REF, SUBREG, \
2732 {"stack_operand", { MEM }}, \
2733 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2734 CONST_DOUBLE, CONST }}, \
2735 {"fcc_register_operand", { REG, SUBREG }}, \
2736 {"hilo_operand", { REG }}, \
2737 {"macc_msac_operand", { PLUS, MINUS }}, \
2738 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2740 /* A list of predicates that do special things with modes, and so
2741 should not elicit warnings for VOIDmode match_operand. */
2743 #define SPECIAL_MODE_PREDICATES \
2744 "pc_or_label_operand",
2746 /* Control the assembler format that we output. */
2748 /* Output to assembler file text saying following lines
2749 may contain character constants, extra white space, comments, etc. */
2752 #define ASM_APP_ON " #APP\n"
2755 /* Output to assembler file text saying following lines
2756 no longer contain unusual constructs. */
2759 #define ASM_APP_OFF " #NO_APP\n"
2762 /* How to refer to registers in assembler output.
2763 This sequence is indexed by compiler's hard-register-number (see above).
2765 In order to support the two different conventions for register names,
2766 we use the name of a table set up in mips.c, which is overwritten
2767 if -mrnames is used. */
2769 #define REGISTER_NAMES \
2771 &mips_reg_names[ 0][0], \
2772 &mips_reg_names[ 1][0], \
2773 &mips_reg_names[ 2][0], \
2774 &mips_reg_names[ 3][0], \
2775 &mips_reg_names[ 4][0], \
2776 &mips_reg_names[ 5][0], \
2777 &mips_reg_names[ 6][0], \
2778 &mips_reg_names[ 7][0], \
2779 &mips_reg_names[ 8][0], \
2780 &mips_reg_names[ 9][0], \
2781 &mips_reg_names[10][0], \
2782 &mips_reg_names[11][0], \
2783 &mips_reg_names[12][0], \
2784 &mips_reg_names[13][0], \
2785 &mips_reg_names[14][0], \
2786 &mips_reg_names[15][0], \
2787 &mips_reg_names[16][0], \
2788 &mips_reg_names[17][0], \
2789 &mips_reg_names[18][0], \
2790 &mips_reg_names[19][0], \
2791 &mips_reg_names[20][0], \
2792 &mips_reg_names[21][0], \
2793 &mips_reg_names[22][0], \
2794 &mips_reg_names[23][0], \
2795 &mips_reg_names[24][0], \
2796 &mips_reg_names[25][0], \
2797 &mips_reg_names[26][0], \
2798 &mips_reg_names[27][0], \
2799 &mips_reg_names[28][0], \
2800 &mips_reg_names[29][0], \
2801 &mips_reg_names[30][0], \
2802 &mips_reg_names[31][0], \
2803 &mips_reg_names[32][0], \
2804 &mips_reg_names[33][0], \
2805 &mips_reg_names[34][0], \
2806 &mips_reg_names[35][0], \
2807 &mips_reg_names[36][0], \
2808 &mips_reg_names[37][0], \
2809 &mips_reg_names[38][0], \
2810 &mips_reg_names[39][0], \
2811 &mips_reg_names[40][0], \
2812 &mips_reg_names[41][0], \
2813 &mips_reg_names[42][0], \
2814 &mips_reg_names[43][0], \
2815 &mips_reg_names[44][0], \
2816 &mips_reg_names[45][0], \
2817 &mips_reg_names[46][0], \
2818 &mips_reg_names[47][0], \
2819 &mips_reg_names[48][0], \
2820 &mips_reg_names[49][0], \
2821 &mips_reg_names[50][0], \
2822 &mips_reg_names[51][0], \
2823 &mips_reg_names[52][0], \
2824 &mips_reg_names[53][0], \
2825 &mips_reg_names[54][0], \
2826 &mips_reg_names[55][0], \
2827 &mips_reg_names[56][0], \
2828 &mips_reg_names[57][0], \
2829 &mips_reg_names[58][0], \
2830 &mips_reg_names[59][0], \
2831 &mips_reg_names[60][0], \
2832 &mips_reg_names[61][0], \
2833 &mips_reg_names[62][0], \
2834 &mips_reg_names[63][0], \
2835 &mips_reg_names[64][0], \
2836 &mips_reg_names[65][0], \
2837 &mips_reg_names[66][0], \
2838 &mips_reg_names[67][0], \
2839 &mips_reg_names[68][0], \
2840 &mips_reg_names[69][0], \
2841 &mips_reg_names[70][0], \
2842 &mips_reg_names[71][0], \
2843 &mips_reg_names[72][0], \
2844 &mips_reg_names[73][0], \
2845 &mips_reg_names[74][0], \
2846 &mips_reg_names[75][0], \
2847 &mips_reg_names[76][0], \
2848 &mips_reg_names[77][0], \
2849 &mips_reg_names[78][0], \
2850 &mips_reg_names[79][0], \
2851 &mips_reg_names[80][0], \
2852 &mips_reg_names[81][0], \
2853 &mips_reg_names[82][0], \
2854 &mips_reg_names[83][0], \
2855 &mips_reg_names[84][0], \
2856 &mips_reg_names[85][0], \
2857 &mips_reg_names[86][0], \
2858 &mips_reg_names[87][0], \
2859 &mips_reg_names[88][0], \
2860 &mips_reg_names[89][0], \
2861 &mips_reg_names[90][0], \
2862 &mips_reg_names[91][0], \
2863 &mips_reg_names[92][0], \
2864 &mips_reg_names[93][0], \
2865 &mips_reg_names[94][0], \
2866 &mips_reg_names[95][0], \
2867 &mips_reg_names[96][0], \
2868 &mips_reg_names[97][0], \
2869 &mips_reg_names[98][0], \
2870 &mips_reg_names[99][0], \
2871 &mips_reg_names[100][0], \
2872 &mips_reg_names[101][0], \
2873 &mips_reg_names[102][0], \
2874 &mips_reg_names[103][0], \
2875 &mips_reg_names[104][0], \
2876 &mips_reg_names[105][0], \
2877 &mips_reg_names[106][0], \
2878 &mips_reg_names[107][0], \
2879 &mips_reg_names[108][0], \
2880 &mips_reg_names[109][0], \
2881 &mips_reg_names[110][0], \
2882 &mips_reg_names[111][0], \
2883 &mips_reg_names[112][0], \
2884 &mips_reg_names[113][0], \
2885 &mips_reg_names[114][0], \
2886 &mips_reg_names[115][0], \
2887 &mips_reg_names[116][0], \
2888 &mips_reg_names[117][0], \
2889 &mips_reg_names[118][0], \
2890 &mips_reg_names[119][0], \
2891 &mips_reg_names[120][0], \
2892 &mips_reg_names[121][0], \
2893 &mips_reg_names[122][0], \
2894 &mips_reg_names[123][0], \
2895 &mips_reg_names[124][0], \
2896 &mips_reg_names[125][0], \
2897 &mips_reg_names[126][0], \
2898 &mips_reg_names[127][0], \
2899 &mips_reg_names[128][0], \
2900 &mips_reg_names[129][0], \
2901 &mips_reg_names[130][0], \
2902 &mips_reg_names[131][0], \
2903 &mips_reg_names[132][0], \
2904 &mips_reg_names[133][0], \
2905 &mips_reg_names[134][0], \
2906 &mips_reg_names[135][0], \
2907 &mips_reg_names[136][0], \
2908 &mips_reg_names[137][0], \
2909 &mips_reg_names[138][0], \
2910 &mips_reg_names[139][0], \
2911 &mips_reg_names[140][0], \
2912 &mips_reg_names[141][0], \
2913 &mips_reg_names[142][0], \
2914 &mips_reg_names[143][0], \
2915 &mips_reg_names[144][0], \
2916 &mips_reg_names[145][0], \
2917 &mips_reg_names[146][0], \
2918 &mips_reg_names[147][0], \
2919 &mips_reg_names[148][0], \
2920 &mips_reg_names[149][0], \
2921 &mips_reg_names[150][0], \
2922 &mips_reg_names[151][0], \
2923 &mips_reg_names[152][0], \
2924 &mips_reg_names[153][0], \
2925 &mips_reg_names[154][0], \
2926 &mips_reg_names[155][0], \
2927 &mips_reg_names[156][0], \
2928 &mips_reg_names[157][0], \
2929 &mips_reg_names[158][0], \
2930 &mips_reg_names[159][0], \
2931 &mips_reg_names[160][0], \
2932 &mips_reg_names[161][0], \
2933 &mips_reg_names[162][0], \
2934 &mips_reg_names[163][0], \
2935 &mips_reg_names[164][0], \
2936 &mips_reg_names[165][0], \
2937 &mips_reg_names[166][0], \
2938 &mips_reg_names[167][0], \
2939 &mips_reg_names[168][0], \
2940 &mips_reg_names[169][0], \
2941 &mips_reg_names[170][0], \
2942 &mips_reg_names[171][0], \
2943 &mips_reg_names[172][0], \
2944 &mips_reg_names[173][0], \
2945 &mips_reg_names[174][0], \
2946 &mips_reg_names[175][0] \
2949 /* If defined, a C initializer for an array of structures
2950 containing a name and a register number. This macro defines
2951 additional names for hard registers, thus allowing the `asm'
2952 option in declarations to refer to registers using alternate
2955 We define both names for the integer registers here. */
2957 #define ADDITIONAL_REGISTER_NAMES \
2959 { "$0", 0 + GP_REG_FIRST }, \
2960 { "$1", 1 + GP_REG_FIRST }, \
2961 { "$2", 2 + GP_REG_FIRST }, \
2962 { "$3", 3 + GP_REG_FIRST }, \
2963 { "$4", 4 + GP_REG_FIRST }, \
2964 { "$5", 5 + GP_REG_FIRST }, \
2965 { "$6", 6 + GP_REG_FIRST }, \
2966 { "$7", 7 + GP_REG_FIRST }, \
2967 { "$8", 8 + GP_REG_FIRST }, \
2968 { "$9", 9 + GP_REG_FIRST }, \
2969 { "$10", 10 + GP_REG_FIRST }, \
2970 { "$11", 11 + GP_REG_FIRST }, \
2971 { "$12", 12 + GP_REG_FIRST }, \
2972 { "$13", 13 + GP_REG_FIRST }, \
2973 { "$14", 14 + GP_REG_FIRST }, \
2974 { "$15", 15 + GP_REG_FIRST }, \
2975 { "$16", 16 + GP_REG_FIRST }, \
2976 { "$17", 17 + GP_REG_FIRST }, \
2977 { "$18", 18 + GP_REG_FIRST }, \
2978 { "$19", 19 + GP_REG_FIRST }, \
2979 { "$20", 20 + GP_REG_FIRST }, \
2980 { "$21", 21 + GP_REG_FIRST }, \
2981 { "$22", 22 + GP_REG_FIRST }, \
2982 { "$23", 23 + GP_REG_FIRST }, \
2983 { "$24", 24 + GP_REG_FIRST }, \
2984 { "$25", 25 + GP_REG_FIRST }, \
2985 { "$26", 26 + GP_REG_FIRST }, \
2986 { "$27", 27 + GP_REG_FIRST }, \
2987 { "$28", 28 + GP_REG_FIRST }, \
2988 { "$29", 29 + GP_REG_FIRST }, \
2989 { "$30", 30 + GP_REG_FIRST }, \
2990 { "$31", 31 + GP_REG_FIRST }, \
2991 { "$sp", 29 + GP_REG_FIRST }, \
2992 { "$fp", 30 + GP_REG_FIRST }, \
2993 { "at", 1 + GP_REG_FIRST }, \
2994 { "v0", 2 + GP_REG_FIRST }, \
2995 { "v1", 3 + GP_REG_FIRST }, \
2996 { "a0", 4 + GP_REG_FIRST }, \
2997 { "a1", 5 + GP_REG_FIRST }, \
2998 { "a2", 6 + GP_REG_FIRST }, \
2999 { "a3", 7 + GP_REG_FIRST }, \
3000 { "t0", 8 + GP_REG_FIRST }, \
3001 { "t1", 9 + GP_REG_FIRST }, \
3002 { "t2", 10 + GP_REG_FIRST }, \
3003 { "t3", 11 + GP_REG_FIRST }, \
3004 { "t4", 12 + GP_REG_FIRST }, \
3005 { "t5", 13 + GP_REG_FIRST }, \
3006 { "t6", 14 + GP_REG_FIRST }, \
3007 { "t7", 15 + GP_REG_FIRST }, \
3008 { "s0", 16 + GP_REG_FIRST }, \
3009 { "s1", 17 + GP_REG_FIRST }, \
3010 { "s2", 18 + GP_REG_FIRST }, \
3011 { "s3", 19 + GP_REG_FIRST }, \
3012 { "s4", 20 + GP_REG_FIRST }, \
3013 { "s5", 21 + GP_REG_FIRST }, \
3014 { "s6", 22 + GP_REG_FIRST }, \
3015 { "s7", 23 + GP_REG_FIRST }, \
3016 { "t8", 24 + GP_REG_FIRST }, \
3017 { "t9", 25 + GP_REG_FIRST }, \
3018 { "k0", 26 + GP_REG_FIRST }, \
3019 { "k1", 27 + GP_REG_FIRST }, \
3020 { "gp", 28 + GP_REG_FIRST }, \
3021 { "sp", 29 + GP_REG_FIRST }, \
3022 { "fp", 30 + GP_REG_FIRST }, \
3023 { "ra", 31 + GP_REG_FIRST }, \
3024 { "$sp", 29 + GP_REG_FIRST }, \
3025 { "$fp", 30 + GP_REG_FIRST } \
3026 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3029 /* This is meant to be redefined in the host dependent files. It is a
3030 set of alternative names and regnums for mips coprocessors. */
3032 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3034 /* A C compound statement to output to stdio stream STREAM the
3035 assembler syntax for an instruction operand X. X is an RTL
3038 CODE is a value that can be used to specify one of several ways
3039 of printing the operand. It is used when identical operands
3040 must be printed differently depending on the context. CODE
3041 comes from the `%' specification that was used to request
3042 printing of the operand. If the specification was just `%DIGIT'
3043 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3044 is the ASCII code for LTR.
3046 If X is a register, this macro should print the register's name.
3047 The names can be found in an array `reg_names' whose type is
3048 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3050 When the machine description has a specification `%PUNCT' (a `%'
3051 followed by a punctuation character), this macro is called with
3052 a null pointer for X and the punctuation character for CODE.
3054 See mips.c for the MIPS specific codes. */
3056 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3058 /* A C expression which evaluates to true if CODE is a valid
3059 punctuation character for use in the `PRINT_OPERAND' macro. If
3060 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3061 punctuation characters (except for the standard one, `%') are
3062 used in this way. */
3064 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3066 /* A C compound statement to output to stdio stream STREAM the
3067 assembler syntax for an instruction operand that is a memory
3068 reference whose address is ADDR. ADDR is an RTL expression. */
3070 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3073 /* A C statement, to be executed after all slot-filler instructions
3074 have been output. If necessary, call `dbr_sequence_length' to
3075 determine the number of slots filled in a sequence (zero if not
3076 currently outputting a sequence), to decide how many no-ops to
3077 output, or whatever.
3079 Don't define this macro if it has nothing to do, but it is
3080 helpful in reading assembly output if the extent of the delay
3081 sequence is made explicit (e.g. with white space).
3083 Note that output routines for instructions with delay slots must
3084 be prepared to deal with not being output as part of a sequence
3085 (i.e. when the scheduling pass is not run, or when no slot
3086 fillers could be found.) The variable `final_sequence' is null
3087 when not processing a sequence, otherwise it contains the
3088 `sequence' rtx being output. */
3090 #define DBR_OUTPUT_SEQEND(STREAM) \
3093 if (set_nomacro > 0 && --set_nomacro == 0) \
3094 fputs ("\t.set\tmacro\n", STREAM); \
3096 if (set_noreorder > 0 && --set_noreorder == 0) \
3097 fputs ("\t.set\treorder\n", STREAM); \
3099 fputs ("\n", STREAM); \
3104 /* How to tell the debugger about changes of source files. */
3106 #ifndef SET_FILE_NUMBER
3107 #define SET_FILE_NUMBER() ++num_source_filenames
3110 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3111 mips_output_filename (STREAM, NAME)
3113 /* This is defined so that it can be overridden in iris6.h. */
3114 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3117 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3118 output_quoted_string (STREAM, NAME); \
3119 fputs ("\n", STREAM); \
3123 /* This is how to output a note the debugger telling it the line number
3124 to which the following sequence of instructions corresponds.
3125 Silicon graphics puts a label after each .loc. */
3127 #ifndef LABEL_AFTER_LOC
3128 #define LABEL_AFTER_LOC(STREAM)
3131 #ifndef ASM_OUTPUT_SOURCE_LINE
3132 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3133 mips_output_lineno (STREAM, LINE)
3136 /* The MIPS implementation uses some labels for its own purpose. The
3137 following lists what labels are created, and are all formed by the
3138 pattern $L[a-z].*. The machine independent portion of GCC creates
3139 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3141 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3142 $Lb[0-9]+ Begin blocks for MIPS debug support
3143 $Lc[0-9]+ Label for use in s<xx> operation.
3144 $Le[0-9]+ End blocks for MIPS debug support */
3146 #undef ASM_DECLARE_OBJECT_NAME
3147 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3148 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3150 /* Globalizing directive for a label. */
3151 #define GLOBAL_ASM_OP "\t.globl\t"
3153 /* This says how to define a global common symbol. */
3155 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
3157 /* This says how to define a local common symbol (ie, not visible to
3160 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3161 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3164 /* This says how to output an external. It would be possible not to
3165 output anything and let undefined symbol become external. However
3166 the assembler uses length information on externals to allocate in
3167 data/sdata bss/sbss, thereby saving exec time. */
3169 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3170 mips_output_external(STREAM,DECL,NAME)
3172 /* This is how to declare a function name. The actual work of
3173 emitting the label is moved to function_prologue, so that we can
3174 get the line number correctly emitted before the .ent directive,
3175 and after any .file directives. Define as empty so that the function
3176 is not declared before the .ent directive elsewhere. */
3178 #undef ASM_DECLARE_FUNCTION_NAME
3179 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3181 #ifndef FUNCTION_NAME_ALREADY_DECLARED
3182 #define FUNCTION_NAME_ALREADY_DECLARED 0
3185 /* This is how to store into the string LABEL
3186 the symbol_ref name of an internal numbered label where
3187 PREFIX is the class of label and NUM is the number within the class.
3188 This is suitable for output with `assemble_name'. */
3190 #undef ASM_GENERATE_INTERNAL_LABEL
3191 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3192 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3194 /* This is how to output an element of a case-vector that is absolute. */
3196 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3197 fprintf (STREAM, "\t%s\t%sL%d\n", \
3198 ptr_mode == DImode ? ".dword" : ".word", \
3199 LOCAL_LABEL_PREFIX, \
3202 /* This is how to output an element of a case-vector that is relative.
3203 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3204 TARGET_EMBEDDED_PIC). */
3206 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3208 if (TARGET_MIPS16) \
3209 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3210 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3211 else if (TARGET_EMBEDDED_PIC) \
3212 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3213 ptr_mode == DImode ? ".dword" : ".word", \
3214 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3215 else if (TARGET_GPWORD) \
3216 fprintf (STREAM, "\t%s\t%sL%d\n", \
3217 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3218 LOCAL_LABEL_PREFIX, VALUE); \
3220 fprintf (STREAM, "\t%s\t%sL%d\n", \
3221 ptr_mode == DImode ? ".dword" : ".word", \
3222 LOCAL_LABEL_PREFIX, VALUE); \
3225 /* When generating embedded PIC or mips16 code we want to put the jump
3226 table in the .text section. In all other cases, we want to put the
3227 jump table in the .rdata section. Unfortunately, we can't use
3228 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3229 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3230 section if appropriate. */
3231 #undef ASM_OUTPUT_CASE_LABEL
3232 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3234 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3235 function_section (current_function_decl); \
3236 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3239 /* This is how to output an assembler line
3240 that says to advance the location counter
3241 to a multiple of 2**LOG bytes. */
3243 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3244 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3246 /* This is how to output an assembler line to advance the location
3247 counter by SIZE bytes. */
3249 #undef ASM_OUTPUT_SKIP
3250 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3251 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3253 /* This is how to output a string. */
3254 #undef ASM_OUTPUT_ASCII
3255 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3256 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3258 /* Output #ident as a in the read-only data section. */
3259 #undef ASM_OUTPUT_IDENT
3260 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3262 const char *p = STRING; \
3263 int size = strlen (p) + 1; \
3264 readonly_data_section (); \
3265 assemble_string (p, size); \
3268 /* Default to -G 8 */
3269 #ifndef MIPS_DEFAULT_GVALUE
3270 #define MIPS_DEFAULT_GVALUE 8
3273 /* Define the strings to put out for each section in the object file. */
3274 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3275 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3276 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3278 #undef READONLY_DATA_SECTION_ASM_OP
3279 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3281 /* Given a decl node or constant node, choose the section to output it in
3282 and select that section. */
3284 #undef TARGET_ASM_SELECT_SECTION
3285 #define TARGET_ASM_SELECT_SECTION mips_select_section
3287 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3290 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3291 TARGET_64BIT ? "dsubu" : "subu", \
3292 reg_names[STACK_POINTER_REGNUM], \
3293 reg_names[STACK_POINTER_REGNUM], \
3294 TARGET_64BIT ? "sd" : "sw", \
3296 reg_names[STACK_POINTER_REGNUM]); \
3300 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3303 if (! set_noreorder) \
3304 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3306 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3307 TARGET_64BIT ? "ld" : "lw", \
3309 reg_names[STACK_POINTER_REGNUM], \
3310 TARGET_64BIT ? "daddu" : "addu", \
3311 reg_names[STACK_POINTER_REGNUM], \
3312 reg_names[STACK_POINTER_REGNUM]); \
3314 if (! set_noreorder) \
3315 fprintf (STREAM, "\t.set\treorder\n"); \
3319 /* How to start an assembler comment.
3320 The leading space is important (the mips native assembler requires it). */
3321 #ifndef ASM_COMMENT_START
3322 #define ASM_COMMENT_START " #"
3325 /* Default definitions for size_t and ptrdiff_t. We must override the
3326 definitions from ../svr4.h on mips-*-linux-gnu. */
3329 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3332 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3334 /* See mips_expand_prologue's use of loadgp for when this should be
3337 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
3339 /* Generate calls to memcpy, etc., not bcopy, etc. */
3340 #define TARGET_MEM_FUNCTIONS
3343 /* Since the bits of the _init and _fini function is spread across
3344 many object files, each potentially with its own GP, we must assume
3345 we need to load our GP. We don't preserve $gp or $ra, since each
3346 init/fini chunk is supposed to initialize $gp, and crti/crtn
3347 already take care of preserving $ra and, when appropriate, $gp. */
3348 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3349 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3350 asm (SECTION_OP "\n\
3356 jal " USER_LABEL_PREFIX #FUNC "\n\
3357 " TEXT_SECTION_ASM_OP);
3358 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3359 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3360 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3361 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3362 asm (SECTION_OP "\n\
3367 .cpsetup $31, $2, 1b\n\
3368 jal " USER_LABEL_PREFIX #FUNC "\n\
3369 " TEXT_SECTION_ASM_OP);
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