1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
27 /* MIPS external variables defined in mips.c. */
29 /* Which processor to schedule for. Since there is no difference between
30 a R2000 and R3000 in terms of the scheduler, we collapse them into
31 just an R3000. The elements of the enumeration must match exactly
32 the cpu attribute in the mips.md machine description. */
67 /* Costs of various operations on the different architectures. */
69 struct mips_rtx_cost_data
71 unsigned short fp_add;
72 unsigned short fp_mult_sf;
73 unsigned short fp_mult_df;
74 unsigned short fp_div_sf;
75 unsigned short fp_div_df;
76 unsigned short int_mult_si;
77 unsigned short int_mult_di;
78 unsigned short int_div_si;
79 unsigned short int_div_di;
80 unsigned short branch_cost;
81 unsigned short memory_latency;
84 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
85 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
86 to work on a 64-bit machine. */
94 /* Information about one recognized processor. Defined here for the
95 benefit of TARGET_CPU_CPP_BUILTINS. */
96 struct mips_cpu_info {
97 /* The 'canonical' name of the processor as far as GCC is concerned.
98 It's typically a manufacturer's prefix followed by a numerical
99 designation. It should be lowercase. */
102 /* The internal processor number that most closely matches this
103 entry. Several processors can have the same value, if there's no
104 difference between them from GCC's point of view. */
105 enum processor_type cpu;
107 /* The ISA level that the processor implements. */
111 #ifndef USED_FOR_TARGET
112 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
113 extern const char *current_function_file; /* filename current function is in */
114 extern int num_source_filenames; /* current .file # */
115 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
116 extern int sym_lineno; /* sgi next label # for each stmt */
117 extern int set_noreorder; /* # of nested .set noreorder's */
118 extern int set_nomacro; /* # of nested .set nomacro's */
119 extern int set_noat; /* # of nested .set noat's */
120 extern int set_volatile; /* # of nested .set volatile's */
121 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
122 extern int mips_dbx_regno[]; /* Map register # to debug register # */
123 extern bool mips_split_p[];
124 extern GTY(()) rtx cmp_operands[2];
125 extern enum processor_type mips_arch; /* which cpu to codegen for */
126 extern enum processor_type mips_tune; /* which cpu to schedule for */
127 extern int mips_isa; /* architectural level */
128 extern int mips_abi; /* which ABI to use */
129 extern int mips16_hard_float; /* mips16 without -msoft-float */
130 extern const struct mips_cpu_info mips_cpu_info_table[];
131 extern const struct mips_cpu_info *mips_arch_info;
132 extern const struct mips_cpu_info *mips_tune_info;
133 extern const struct mips_rtx_cost_data *mips_cost;
136 /* Macros to silence warnings about numbers being signed in traditional
137 C and unsigned in ISO C when compiled on 32-bit hosts. */
139 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
140 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
141 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
144 /* Run-time compilation parameters selecting different hardware subsets. */
146 /* True if the call patterns should be split into a jalr followed by
147 an instruction to restore $gp. This is only ever true for SVR4 PIC,
148 in which $gp is call-clobbered. It is only safe to split the load
149 from the call when every use of $gp is explicit. */
151 #define TARGET_SPLIT_CALLS \
152 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
154 /* True if we're generating a form of -mabicalls in which we can use
155 operators like %hi and %lo to refer to locally-binding symbols.
156 We can only do this for -mno-shared, and only then if we can use
157 relocation operations instead of assembly macros. It isn't really
158 worth using absolute sequences for 64-bit symbols because GOT
159 accesses are so much shorter. */
161 #define TARGET_ABSOLUTE_ABICALLS \
164 && TARGET_EXPLICIT_RELOCS \
165 && !ABI_HAS_64BIT_SYMBOLS)
167 /* True if we can optimize sibling calls. For simplicity, we only
168 handle cases in which call_insn_operand will reject invalid
169 sibcall addresses. There are two cases in which this isn't true:
171 - TARGET_MIPS16. call_insn_operand accepts constant addresses
172 but there is no direct jump instruction. It isn't worth
173 using sibling calls in this case anyway; they would usually
174 be longer than normal calls.
176 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
177 accepts global constants, but "jr $25" is the only allowed
180 #define TARGET_SIBCALLS \
181 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
183 /* True if .gpword or .gpdword should be used for switch tables.
185 Although GAS does understand .gpdword, the SGI linker mishandles
186 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
187 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
188 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
190 /* Generate mips16 code */
191 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
192 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
193 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
195 /* Generic ISA defines. */
196 #define ISA_MIPS1 (mips_isa == 1)
197 #define ISA_MIPS2 (mips_isa == 2)
198 #define ISA_MIPS3 (mips_isa == 3)
199 #define ISA_MIPS4 (mips_isa == 4)
200 #define ISA_MIPS32 (mips_isa == 32)
201 #define ISA_MIPS32R2 (mips_isa == 33)
202 #define ISA_MIPS64 (mips_isa == 64)
204 /* Architecture target defines. */
205 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
206 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
207 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
208 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
209 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
210 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
211 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
212 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
213 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
214 || mips_arch == PROCESSOR_SB1A)
215 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
217 /* Scheduling target defines. */
218 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
219 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
220 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
221 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
222 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
223 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
224 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
225 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
226 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
227 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
228 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
229 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
230 || mips_tune == PROCESSOR_SB1A)
232 /* True if the pre-reload scheduler should try to create chains of
233 multiply-add or multiply-subtract instructions. For example,
241 t1 will have a higher priority than t2 and t3 will have a higher
242 priority than t4. However, before reload, there is no dependence
243 between t1 and t3, and they can often have similar priorities.
244 The scheduler will then tend to prefer:
251 which stops us from making full use of macc/madd-style instructions.
252 This sort of situation occurs frequently in Fourier transforms and
255 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
256 queue so that chained multiply-add and multiply-subtract instructions
257 appear ahead of any other instruction that is likely to clobber lo.
258 In the example above, if t2 and t3 become ready at the same time,
259 the code ensures that t2 is scheduled first.
261 Multiply-accumulate instructions are a bigger win for some targets
262 than others, so this macro is defined on an opt-in basis. */
263 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
267 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
268 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
270 /* IRIX specific stuff. */
271 #define TARGET_IRIX 0
272 #define TARGET_IRIX6 0
274 /* Define preprocessor macros for the -march and -mtune options.
275 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
276 processor. If INFO's canonical name is "foo", define PREFIX to
277 be "foo", and define an additional macro PREFIX_FOO. */
278 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
283 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
284 for (p = macro; *p != 0; p++) \
287 builtin_define (macro); \
288 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
293 /* Target CPU builtins. */
294 #define TARGET_CPU_CPP_BUILTINS() \
297 /* Everyone but IRIX defines this to mips. */ \
299 builtin_assert ("machine=mips"); \
301 builtin_assert ("cpu=mips"); \
302 builtin_define ("__mips__"); \
303 builtin_define ("_mips"); \
305 /* We do this here because __mips is defined below \
306 and so we can't use builtin_define_std. */ \
308 builtin_define ("mips"); \
311 builtin_define ("__mips64"); \
315 /* Treat _R3000 and _R4000 like register-size \
316 defines, which is how they've historically \
320 builtin_define_std ("R4000"); \
321 builtin_define ("_R4000"); \
325 builtin_define_std ("R3000"); \
326 builtin_define ("_R3000"); \
329 if (TARGET_FLOAT64) \
330 builtin_define ("__mips_fpr=64"); \
332 builtin_define ("__mips_fpr=32"); \
335 builtin_define ("__mips16"); \
338 builtin_define ("__mips3d"); \
341 builtin_define ("__mips_dsp"); \
344 builtin_define ("__mips_dspr2"); \
346 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
347 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
351 builtin_define ("__mips=1"); \
352 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
354 else if (ISA_MIPS2) \
356 builtin_define ("__mips=2"); \
357 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
359 else if (ISA_MIPS3) \
361 builtin_define ("__mips=3"); \
362 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
364 else if (ISA_MIPS4) \
366 builtin_define ("__mips=4"); \
367 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
369 else if (ISA_MIPS32) \
371 builtin_define ("__mips=32"); \
372 builtin_define ("__mips_isa_rev=1"); \
373 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
375 else if (ISA_MIPS32R2) \
377 builtin_define ("__mips=32"); \
378 builtin_define ("__mips_isa_rev=2"); \
379 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
381 else if (ISA_MIPS64) \
383 builtin_define ("__mips=64"); \
384 builtin_define ("__mips_isa_rev=1"); \
385 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
388 if (TARGET_HARD_FLOAT) \
389 builtin_define ("__mips_hard_float"); \
390 else if (TARGET_SOFT_FLOAT) \
391 builtin_define ("__mips_soft_float"); \
393 if (TARGET_SINGLE_FLOAT) \
394 builtin_define ("__mips_single_float"); \
396 if (TARGET_PAIRED_SINGLE_FLOAT) \
397 builtin_define ("__mips_paired_single_float"); \
399 if (TARGET_BIG_ENDIAN) \
401 builtin_define_std ("MIPSEB"); \
402 builtin_define ("_MIPSEB"); \
406 builtin_define_std ("MIPSEL"); \
407 builtin_define ("_MIPSEL"); \
410 /* Macros dependent on the C dialect. */ \
411 if (preprocessing_asm_p ()) \
413 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
414 builtin_define ("_LANGUAGE_ASSEMBLY"); \
416 else if (c_dialect_cxx ()) \
418 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
419 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
420 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
424 builtin_define_std ("LANGUAGE_C"); \
425 builtin_define ("_LANGUAGE_C"); \
427 if (c_dialect_objc ()) \
429 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
430 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
431 /* Bizarre, but needed at least for Irix. */ \
432 builtin_define_std ("LANGUAGE_C"); \
433 builtin_define ("_LANGUAGE_C"); \
436 if (mips_abi == ABI_EABI) \
437 builtin_define ("__mips_eabi"); \
441 /* Default target_flags if no switches are specified */
443 #ifndef TARGET_DEFAULT
444 #define TARGET_DEFAULT 0
447 #ifndef TARGET_CPU_DEFAULT
448 #define TARGET_CPU_DEFAULT 0
451 #ifndef TARGET_ENDIAN_DEFAULT
452 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
455 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
456 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
459 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
460 #ifndef MIPS_ISA_DEFAULT
461 #ifndef MIPS_CPU_STRING_DEFAULT
462 #define MIPS_CPU_STRING_DEFAULT "from-abi"
468 /* Make this compile time constant for libgcc2 */
470 #define TARGET_64BIT 1
472 #define TARGET_64BIT 0
474 #endif /* IN_LIBGCC2 */
476 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
478 #ifndef MULTILIB_ENDIAN_DEFAULT
479 #if TARGET_ENDIAN_DEFAULT == 0
480 #define MULTILIB_ENDIAN_DEFAULT "EL"
482 #define MULTILIB_ENDIAN_DEFAULT "EB"
486 #ifndef MULTILIB_ISA_DEFAULT
487 # if MIPS_ISA_DEFAULT == 1
488 # define MULTILIB_ISA_DEFAULT "mips1"
490 # if MIPS_ISA_DEFAULT == 2
491 # define MULTILIB_ISA_DEFAULT "mips2"
493 # if MIPS_ISA_DEFAULT == 3
494 # define MULTILIB_ISA_DEFAULT "mips3"
496 # if MIPS_ISA_DEFAULT == 4
497 # define MULTILIB_ISA_DEFAULT "mips4"
499 # if MIPS_ISA_DEFAULT == 32
500 # define MULTILIB_ISA_DEFAULT "mips32"
502 # if MIPS_ISA_DEFAULT == 33
503 # define MULTILIB_ISA_DEFAULT "mips32r2"
505 # if MIPS_ISA_DEFAULT == 64
506 # define MULTILIB_ISA_DEFAULT "mips64"
508 # define MULTILIB_ISA_DEFAULT "mips1"
518 #ifndef MULTILIB_DEFAULTS
519 #define MULTILIB_DEFAULTS \
520 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
523 /* We must pass -EL to the linker by default for little endian embedded
524 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
525 linker will default to using big-endian output files. The OUTPUT_FORMAT
526 line must be in the linker script, otherwise -EB/-EL will not work. */
529 #if TARGET_ENDIAN_DEFAULT == 0
530 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
532 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
536 /* Support for a compile-time default CPU, et cetera. The rules are:
537 --with-arch is ignored if -march is specified or a -mips is specified
538 (other than -mips16).
539 --with-tune is ignored if -mtune is specified.
540 --with-abi is ignored if -mabi is specified.
541 --with-float is ignored if -mhard-float or -msoft-float are
543 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
545 #define OPTION_DEFAULT_SPECS \
546 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
547 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
548 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
549 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
550 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
553 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
554 && ISA_HAS_COND_TRAP)
556 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
560 /* True if the ABI can only work with 64-bit integer registers. We
561 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
562 otherwise floating-point registers must also be 64-bit. */
563 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
565 /* Likewise for 32-bit regs. */
566 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
568 /* True if symbols are 64 bits wide. At present, n64 is the only
569 ABI for which this is true. */
570 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
572 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
573 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
577 /* ISA has branch likely instructions (e.g. mips2). */
578 /* Disable branchlikely for tx39 until compare rewrite. They haven't
579 been generated up to this point. */
580 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
582 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
583 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
594 /* ISA has the conditional move instructions introduced in mips4. */
595 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
599 && !TARGET_MIPS5500 \
602 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
603 branch on CC, and move (both FP and non-FP) on CC. */
604 #define ISA_HAS_8CC (ISA_MIPS4 \
609 /* This is a catch all for other mips4 instructions: indexed load, the
610 FP madd and msub instructions, and the FP recip and recip sqrt
612 #define ISA_HAS_FP4 ((ISA_MIPS4 \
613 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
617 /* ISA has conditional trap instructions. */
618 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
621 /* ISA has integer multiply-accumulate instructions, madd and msub. */
622 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
627 /* ISA has floating-point nmadd and nmsub instructions. */
628 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
630 && (!TARGET_MIPS5400 || TARGET_MAD) \
633 /* ISA has count leading zeroes/ones instruction (not implemented). */
634 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
639 /* ISA has three operand multiply instructions that put
640 the high part in an accumulator: mulhi or mulhiu. */
641 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
646 /* ISA has three operand multiply instructions that
647 negates the result and puts the result in an accumulator. */
648 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
653 /* ISA has three operand multiply instructions that subtracts the
654 result from a 4th operand and puts the result in an accumulator. */
655 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
660 /* ISA has three operand multiply instructions that the result
661 from a 4th operand and puts the result in an accumulator. */
662 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
669 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
670 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
671 || TARGET_MIPS4130) \
674 /* ISA has the "ror" (rotate right) instructions. */
675 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
681 /* ISA has data prefetch instructions. This controls use of 'pref'. */
682 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
688 /* ISA has data indexed prefetch instructions. This controls use of
689 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
690 (prefx is a cop1x instruction, so can only be used if FP is
692 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
697 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
698 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
699 also requires TARGET_DOUBLE_FLOAT. */
700 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
702 /* ISA includes the MIPS32r2 seb and seh instructions. */
703 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
706 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
707 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
710 /* ISA has instructions for accessing top part of 64-bit fp regs. */
711 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
713 /* True if the result of a load is not available to the next instruction.
714 A nop will then be needed between instructions like "lw $4,..."
715 and "addiu $4,$4,1". */
716 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
717 && !TARGET_MIPS3900 \
720 /* Likewise mtc1 and mfc1. */
721 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
723 /* Likewise floating-point comparisons. */
724 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
726 /* True if mflo and mfhi can be immediately followed by instructions
727 which write to the HI and LO registers.
729 According to MIPS specifications, MIPS ISAs I, II, and III need
730 (at least) two instructions between the reads of HI/LO and
731 instructions which write them, and later ISAs do not. Contradicting
732 the MIPS specifications, some MIPS IV processor user manuals (e.g.
733 the UM for the NEC Vr5000) document needing the instructions between
734 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
735 MIPS64 and later ISAs to have the interlocks, plus any specific
736 earlier-ISA CPUs for which CPU documentation declares that the
737 instructions are really interlocked. */
738 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
743 /* Add -G xx support. */
745 #undef SWITCH_TAKES_ARG
746 #define SWITCH_TAKES_ARG(CHAR) \
747 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
749 #define OVERRIDE_OPTIONS override_options ()
751 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
753 /* Show we can debug even without a frame pointer. */
754 #define CAN_DEBUG_WITHOUT_FP
756 /* Tell collect what flags to pass to nm. */
758 #define NM_FLAGS "-Bn"
762 #ifndef MIPS_ABI_DEFAULT
763 #define MIPS_ABI_DEFAULT ABI_32
766 /* Use the most portable ABI flag for the ASM specs. */
768 #if MIPS_ABI_DEFAULT == ABI_32
769 #define MULTILIB_ABI_DEFAULT "mabi=32"
772 #if MIPS_ABI_DEFAULT == ABI_O64
773 #define MULTILIB_ABI_DEFAULT "mabi=o64"
776 #if MIPS_ABI_DEFAULT == ABI_N32
777 #define MULTILIB_ABI_DEFAULT "mabi=n32"
780 #if MIPS_ABI_DEFAULT == ABI_64
781 #define MULTILIB_ABI_DEFAULT "mabi=64"
784 #if MIPS_ABI_DEFAULT == ABI_EABI
785 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
788 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
789 to the assembler. It may be overridden by subtargets. */
790 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
791 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
793 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
796 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
797 the assembler. It may be overridden by subtargets.
799 Beginning with gas 2.13, -mdebug must be passed to correctly handle
800 COFF debugging info. */
802 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
803 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
804 %{g} %{g0} %{g1} %{g2} %{g3} \
805 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
806 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
807 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
808 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
809 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
812 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
813 overridden by subtargets. */
815 #ifndef SUBTARGET_ASM_SPEC
816 #define SUBTARGET_ASM_SPEC ""
821 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
822 %{mips32} %{mips32r2} %{mips64} \
823 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
827 %{mfix-vr4120} %{mfix-vr4130} \
828 %(subtarget_asm_optimizing_spec) \
829 %(subtarget_asm_debugging_spec) \
830 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
831 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
833 %{mshared} %{mno-shared} \
834 %{msym32} %{mno-sym32} \
836 %(subtarget_asm_spec)"
838 /* Extra switches sometimes passed to the linker. */
839 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
840 will interpret it as a -b option. */
845 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
846 %{bestGnum} %{shared} %{non_shared}"
847 #endif /* LINK_SPEC defined */
850 /* Specs for the compiler proper */
852 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
853 overridden by subtargets. */
854 #ifndef SUBTARGET_CC1_SPEC
855 #define SUBTARGET_CC1_SPEC ""
858 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
862 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
863 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
865 %(subtarget_cc1_spec)"
867 /* Preprocessor specs. */
869 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
870 overridden by subtargets. */
871 #ifndef SUBTARGET_CPP_SPEC
872 #define SUBTARGET_CPP_SPEC ""
875 #define CPP_SPEC "%(subtarget_cpp_spec)"
877 /* This macro defines names of additional specifications to put in the specs
878 that can be used in various specifications like CC1_SPEC. Its definition
879 is an initializer with a subgrouping for each command option.
881 Each subgrouping contains a string constant, that defines the
882 specification name, and a string constant that used by the GCC driver
885 Do not define this macro if it does not need to do anything. */
887 #define EXTRA_SPECS \
888 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
889 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
890 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
891 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
892 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
893 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
894 { "endian_spec", ENDIAN_SPEC }, \
895 SUBTARGET_EXTRA_SPECS
897 #ifndef SUBTARGET_EXTRA_SPECS
898 #define SUBTARGET_EXTRA_SPECS
901 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
902 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
903 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
905 #ifndef PREFERRED_DEBUGGING_TYPE
906 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
909 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
911 /* By default, turn on GDB extensions. */
912 #define DEFAULT_GDB_EXTENSIONS 1
914 /* Local compiler-generated symbols must have a prefix that the assembler
915 understands. By default, this is $, although some targets (e.g.,
916 NetBSD-ELF) need to override this. */
918 #ifndef LOCAL_LABEL_PREFIX
919 #define LOCAL_LABEL_PREFIX "$"
922 /* By default on the mips, external symbols do not have an underscore
923 prepended, but some targets (e.g., NetBSD) require this. */
925 #ifndef USER_LABEL_PREFIX
926 #define USER_LABEL_PREFIX ""
929 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
930 since the length can run past this up to a continuation point. */
931 #undef DBX_CONTIN_LENGTH
932 #define DBX_CONTIN_LENGTH 1500
934 /* How to renumber registers for dbx and gdb. */
935 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
937 /* The mapping from gcc register number to DWARF 2 CFA column number. */
938 #define DWARF_FRAME_REGNUM(REG) (REG)
940 /* The DWARF 2 CFA column which tracks the return address. */
941 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
943 /* The DWARF 2 CFA column which tracks the return address from a
944 signal handler context. */
945 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
947 /* Before the prologue, RA lives in r31. */
948 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
950 /* Describe how we implement __builtin_eh_return. */
951 #define EH_RETURN_DATA_REGNO(N) \
952 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
954 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
956 /* Offsets recorded in opcodes are a multiple of this alignment factor.
957 The default for this in 64-bit mode is 8, which causes problems with
958 SFmode register saves. */
959 #define DWARF_CIE_DATA_ALIGNMENT -4
961 /* Correct the offset of automatic variables and arguments. Note that
962 the MIPS debug format wants all automatic variables and arguments
963 to be in terms of the virtual frame pointer (stack pointer before
964 any adjustment in the function), while the MIPS 3.0 linker wants
965 the frame pointer to be the stack pointer after the initial
968 #define DEBUGGER_AUTO_OFFSET(X) \
969 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
970 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
971 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
973 /* Target machine storage layout */
975 #define BITS_BIG_ENDIAN 0
976 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
977 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
979 /* Define this to set the endianness to use in libgcc2.c, which can
980 not depend on target_flags. */
981 #if !defined(MIPSEL) && !defined(__MIPSEL__)
982 #define LIBGCC2_WORDS_BIG_ENDIAN 1
984 #define LIBGCC2_WORDS_BIG_ENDIAN 0
987 #define MAX_BITS_PER_WORD 64
989 /* Width of a word, in units (bytes). */
990 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
992 #define MIN_UNITS_PER_WORD 4
995 /* For MIPS, width of a floating point register. */
996 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
998 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
999 the next available register. */
1000 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1002 /* The largest size of value that can be held in floating-point
1003 registers and moved with a single instruction. */
1004 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1006 /* The largest size of value that can be held in floating-point
1008 #define UNITS_PER_FPVALUE \
1009 (TARGET_SOFT_FLOAT ? 0 \
1010 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1011 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1013 /* The number of bytes in a double. */
1014 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1016 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1018 /* Set the sizes of the core types. */
1019 #define SHORT_TYPE_SIZE 16
1020 #define INT_TYPE_SIZE 32
1021 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1022 #define LONG_LONG_TYPE_SIZE 64
1024 #define FLOAT_TYPE_SIZE 32
1025 #define DOUBLE_TYPE_SIZE 64
1026 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1028 /* long double is not a fixed mode, but the idea is that, if we
1029 support long double, we also want a 128-bit integer type. */
1030 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1033 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1034 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1035 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1037 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1041 /* Width in bits of a pointer. */
1042 #ifndef POINTER_SIZE
1043 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1046 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1047 #define PARM_BOUNDARY BITS_PER_WORD
1049 /* Allocation boundary (in *bits*) for the code of a function. */
1050 #define FUNCTION_BOUNDARY 32
1052 /* Alignment of field after `int : 0' in a structure. */
1053 #define EMPTY_FIELD_BOUNDARY 32
1055 /* Every structure's size must be a multiple of this. */
1056 /* 8 is observed right on a DECstation and on riscos 4.02. */
1057 #define STRUCTURE_SIZE_BOUNDARY 8
1059 /* There is no point aligning anything to a rounder boundary than this. */
1060 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1062 /* All accesses must be aligned. */
1063 #define STRICT_ALIGNMENT 1
1065 /* Define this if you wish to imitate the way many other C compilers
1066 handle alignment of bitfields and the structures that contain
1069 The behavior is that the type written for a bit-field (`int',
1070 `short', or other integer type) imposes an alignment for the
1071 entire structure, as if the structure really did contain an
1072 ordinary field of that type. In addition, the bit-field is placed
1073 within the structure so that it would fit within such a field,
1074 not crossing a boundary for it.
1076 Thus, on most machines, a bit-field whose type is written as `int'
1077 would not cross a four-byte boundary, and would force four-byte
1078 alignment for the whole structure. (The alignment used may not
1079 be four bytes; it is controlled by the other alignment
1082 If the macro is defined, its definition should be a C expression;
1083 a nonzero value for the expression enables this behavior. */
1085 #define PCC_BITFIELD_TYPE_MATTERS 1
1087 /* If defined, a C expression to compute the alignment given to a
1088 constant that is being placed in memory. CONSTANT is the constant
1089 and ALIGN is the alignment that the object would ordinarily have.
1090 The value of this macro is used instead of that alignment to align
1093 If this macro is not defined, then ALIGN is used.
1095 The typical use of this macro is to increase alignment for string
1096 constants to be word aligned so that `strcpy' calls that copy
1097 constants can be done inline. */
1099 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1100 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1101 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1103 /* If defined, a C expression to compute the alignment for a static
1104 variable. TYPE is the data type, and ALIGN is the alignment that
1105 the object would ordinarily have. The value of this macro is used
1106 instead of that alignment to align the object.
1108 If this macro is not defined, then ALIGN is used.
1110 One use of this macro is to increase alignment of medium-size
1111 data to make it all fit in fewer cache lines. Another is to
1112 cause character arrays to be word-aligned so that `strcpy' calls
1113 that copy constants to character arrays can be done inline. */
1115 #undef DATA_ALIGNMENT
1116 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1117 ((((ALIGN) < BITS_PER_WORD) \
1118 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1119 || TREE_CODE (TYPE) == UNION_TYPE \
1120 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1123 #define PAD_VARARGS_DOWN \
1124 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1126 /* Define if operations between registers always perform the operation
1127 on the full register even if a narrower mode is specified. */
1128 #define WORD_REGISTER_OPERATIONS
1130 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1131 moves. All other references are zero extended. */
1132 #define LOAD_EXTEND_OP(MODE) \
1133 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1134 ? SIGN_EXTEND : ZERO_EXTEND)
1136 /* Define this macro if it is advisable to hold scalars in registers
1137 in a wider mode than that declared by the program. In such cases,
1138 the value is constrained to be within the bounds of the declared
1139 type, but kept valid in the wider mode. The signedness of the
1140 extension may differ from that of the type. */
1142 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1143 if (GET_MODE_CLASS (MODE) == MODE_INT \
1144 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1146 if ((MODE) == SImode) \
1151 /* Define if loading short immediate values into registers sign extends. */
1152 #define SHORT_IMMEDIATES_SIGN_EXTEND
1154 /* The [d]clz instructions have the natural values at 0. */
1156 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1157 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1159 /* Standard register usage. */
1161 /* Number of hardware registers. We have:
1163 - 32 integer registers
1164 - 32 floating point registers
1165 - 8 condition code registers
1166 - 2 accumulator registers (hi and lo)
1167 - 32 registers each for coprocessors 0, 2 and 3
1169 - ARG_POINTER_REGNUM
1170 - FRAME_POINTER_REGNUM
1171 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1172 - 3 dummy entries that were used at various times in the past.
1173 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1174 - 6 DSP control registers */
1176 #define FIRST_PSEUDO_REGISTER 188
1178 /* By default, fix the kernel registers ($26 and $27), the global
1179 pointer ($28) and the stack pointer ($29). This can change
1180 depending on the command-line options.
1182 Regarding coprocessor registers: without evidence to the contrary,
1183 it's best to assume that each coprocessor register has a unique
1184 use. This can be overridden, in, e.g., override_options() or
1185 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1186 for a particular target. */
1188 #define FIXED_REGISTERS \
1190 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1192 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1194 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1195 /* COP0 registers */ \
1196 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1197 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1198 /* COP2 registers */ \
1199 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1200 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1201 /* COP3 registers */ \
1202 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1203 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1204 /* 6 DSP accumulator registers & 6 control registers */ \
1205 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1209 /* Set up this array for o32 by default.
1211 Note that we don't mark $31 as a call-clobbered register. The idea is
1212 that it's really the call instructions themselves which clobber $31.
1213 We don't care what the called function does with it afterwards.
1215 This approach makes it easier to implement sibcalls. Unlike normal
1216 calls, sibcalls don't clobber $31, so the register reaches the
1217 called function in tact. EPILOGUE_USES says that $31 is useful
1218 to the called function. */
1220 #define CALL_USED_REGISTERS \
1222 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1223 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1224 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1225 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1226 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1227 /* COP0 registers */ \
1228 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1229 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1230 /* COP2 registers */ \
1231 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1232 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1233 /* COP3 registers */ \
1234 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1235 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1236 /* 6 DSP accumulator registers & 6 control registers */ \
1237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1241 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1243 #define CALL_REALLY_USED_REGISTERS \
1244 { /* General registers. */ \
1245 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1246 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1247 /* Floating-point registers. */ \
1248 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1249 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1251 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1252 /* COP0 registers */ \
1253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1255 /* COP2 registers */ \
1256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1258 /* COP3 registers */ \
1259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1260 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1261 /* 6 DSP accumulator registers & 6 control registers */ \
1262 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1265 /* Internal macros to classify a register number as to whether it's a
1266 general purpose register, a floating point register, a
1267 multiply/divide register, or a status register. */
1269 #define GP_REG_FIRST 0
1270 #define GP_REG_LAST 31
1271 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1272 #define GP_DBX_FIRST 0
1274 #define FP_REG_FIRST 32
1275 #define FP_REG_LAST 63
1276 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1277 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1279 #define MD_REG_FIRST 64
1280 #define MD_REG_LAST 65
1281 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1282 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1284 #define ST_REG_FIRST 67
1285 #define ST_REG_LAST 74
1286 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1289 /* FIXME: renumber. */
1290 #define COP0_REG_FIRST 80
1291 #define COP0_REG_LAST 111
1292 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1294 #define COP2_REG_FIRST 112
1295 #define COP2_REG_LAST 143
1296 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1298 #define COP3_REG_FIRST 144
1299 #define COP3_REG_LAST 175
1300 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1301 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1302 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1304 #define DSP_ACC_REG_FIRST 176
1305 #define DSP_ACC_REG_LAST 181
1306 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1308 #define AT_REGNUM (GP_REG_FIRST + 1)
1309 #define HI_REGNUM (MD_REG_FIRST + 0)
1310 #define LO_REGNUM (MD_REG_FIRST + 1)
1311 #define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0)
1312 #define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1)
1313 #define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2)
1314 #define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3)
1315 #define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4)
1316 #define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5)
1318 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1319 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1320 should be used instead. */
1321 #define FPSW_REGNUM ST_REG_FIRST
1323 #define GP_REG_P(REGNO) \
1324 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1325 #define M16_REG_P(REGNO) \
1326 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1327 #define FP_REG_P(REGNO) \
1328 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1329 #define MD_REG_P(REGNO) \
1330 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1331 #define ST_REG_P(REGNO) \
1332 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1333 #define COP0_REG_P(REGNO) \
1334 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1335 #define COP2_REG_P(REGNO) \
1336 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1337 #define COP3_REG_P(REGNO) \
1338 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1339 #define ALL_COP_REG_P(REGNO) \
1340 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1341 /* Test if REGNO is one of the 6 new DSP accumulators. */
1342 #define DSP_ACC_REG_P(REGNO) \
1343 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1344 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1345 #define ACC_REG_P(REGNO) \
1346 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1347 /* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */
1348 #define ACC_HI_REG_P(REGNO) \
1349 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \
1350 || (REGNO) == AC3HI_REGNUM)
1352 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1354 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1355 to initialize the mips16 gp pseudo register. */
1356 #define CONST_GP_P(X) \
1357 (GET_CODE (X) == CONST \
1358 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1359 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1361 /* Return coprocessor number from register number. */
1363 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1364 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1365 : COP3_REG_P (REGNO) ? '3' : '?')
1368 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1370 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1371 array built in override_options. Because machmodes.h is not yet
1372 included before this file is processed, the MODE bound can't be
1375 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1377 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1378 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1380 /* Value is 1 if it is a good idea to tie two pseudo registers
1381 when one has mode MODE1 and one has mode MODE2.
1382 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1383 for any hard reg, then this must be 0 for correct output. */
1384 #define MODES_TIEABLE_P(MODE1, MODE2) \
1385 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1386 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1387 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1388 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1390 /* Register to use for pushing function arguments. */
1391 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1393 /* These two registers don't really exist: they get eliminated to either
1394 the stack or hard frame pointer. */
1395 #define ARG_POINTER_REGNUM 77
1396 #define FRAME_POINTER_REGNUM 78
1398 /* $30 is not available on the mips16, so we use $17 as the frame
1400 #define HARD_FRAME_POINTER_REGNUM \
1401 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1403 /* Value should be nonzero if functions must have frame pointers.
1404 Zero means the frame pointer need not be set up (and parms
1405 may be accessed via the stack pointer) in functions that seem suitable.
1406 This is computed in `reload', in reload1.c. */
1407 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1409 /* Register in which static-chain is passed to a function. */
1410 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1412 /* Registers used as temporaries in prologue/epilogue code. If we're
1413 generating mips16 code, these registers must come from the core set
1414 of 8. The prologue register mustn't conflict with any incoming
1415 arguments, the static chain pointer, or the frame pointer. The
1416 epilogue temporary mustn't conflict with the return registers, the
1417 frame pointer, the EH stack adjustment, or the EH data registers. */
1419 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1420 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1422 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1423 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1425 /* Define this macro if it is as good or better to call a constant
1426 function address than to call an address kept in a register. */
1427 #define NO_FUNCTION_CSE 1
1429 /* The ABI-defined global pointer. Sometimes we use a different
1430 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1431 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1433 /* We normally use $28 as the global pointer. However, when generating
1434 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1435 register instead. They can then avoid saving and restoring $28
1436 and perhaps avoid using a frame at all.
1438 When a leaf function uses something other than $28, mips_expand_prologue
1439 will modify pic_offset_table_rtx in place. Take the register number
1440 from there after reload. */
1441 #define PIC_OFFSET_TABLE_REGNUM \
1442 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1444 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1446 /* Define the classes of registers for register constraints in the
1447 machine description. Also define ranges of constants.
1449 One of the classes must always be named ALL_REGS and include all hard regs.
1450 If there is more than one class, another class must be named NO_REGS
1451 and contain no registers.
1453 The name GENERAL_REGS must be the name of a class (or an alias for
1454 another name such as ALL_REGS). This is the class of registers
1455 that is allowed by "g" or "r" in a register constraint.
1456 Also, registers outside this class are allocated only when
1457 instructions express preferences for them.
1459 The classes must be numbered in nondecreasing order; that is,
1460 a larger-numbered class must never be contained completely
1461 in a smaller-numbered class.
1463 For any two classes, it is very desirable that there be another
1464 class that represents their union. */
1468 NO_REGS, /* no registers in set */
1469 M16_NA_REGS, /* mips16 regs not used to pass args */
1470 M16_REGS, /* mips16 directly accessible registers */
1471 T_REG, /* mips16 T register ($24) */
1472 M16_T_REGS, /* mips16 registers plus T register */
1473 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1474 V1_REG, /* Register $v1 ($3) used for TLS access. */
1475 LEA_REGS, /* Every GPR except $25 */
1476 GR_REGS, /* integer registers */
1477 FP_REGS, /* floating point registers */
1478 HI_REG, /* hi register */
1479 LO_REG, /* lo register */
1480 MD_REGS, /* multiply/divide registers (hi/lo) */
1481 COP0_REGS, /* generic coprocessor classes */
1484 HI_AND_GR_REGS, /* union classes */
1491 ALL_COP_AND_GR_REGS,
1492 ST_REGS, /* status registers (fp status) */
1493 DSP_ACC_REGS, /* DSP accumulator registers */
1494 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1495 ALL_REGS, /* all registers */
1496 LIM_REG_CLASSES /* max value + 1 */
1499 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1501 #define GENERAL_REGS GR_REGS
1503 /* An initializer containing the names of the register classes as C
1504 string constants. These names are used in writing some of the
1507 #define REG_CLASS_NAMES \
1514 "PIC_FN_ADDR_REG", \
1522 /* coprocessor registers */ \
1529 "COP0_AND_GR_REGS", \
1530 "COP2_AND_GR_REGS", \
1531 "COP3_AND_GR_REGS", \
1533 "ALL_COP_AND_GR_REGS", \
1540 /* An initializer containing the contents of the register classes,
1541 as integers which are bit masks. The Nth integer specifies the
1542 contents of class N. The way the integer MASK is interpreted is
1543 that register R is in the class if `MASK & (1 << R)' is 1.
1545 When the machine has more than 32 registers, an integer does not
1546 suffice. Then the integers are replaced by sub-initializers,
1547 braced groupings containing several integers. Each
1548 sub-initializer must be suitable as an initializer for the type
1549 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1551 #define REG_CLASS_CONTENTS \
1553 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1554 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1555 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1556 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1557 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1558 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1559 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1560 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1561 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1562 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1563 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1564 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1565 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1566 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1567 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1568 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1569 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1570 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1571 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1572 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1573 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1574 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1575 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1576 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1577 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1578 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1579 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1580 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1584 /* A C expression whose value is a register class containing hard
1585 register REGNO. In general there is more that one such class;
1586 choose a class which is "minimal", meaning that no smaller class
1587 also contains the register. */
1589 extern const enum reg_class mips_regno_to_class[];
1591 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1593 /* A macro whose definition is the name of the class to which a
1594 valid base register must belong. A base register is one used in
1595 an address which is the register value plus a displacement. */
1597 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1599 /* A macro whose definition is the name of the class to which a
1600 valid index register must belong. An index register is one used
1601 in an address where its value is either multiplied by a scale
1602 factor or added to another register (as well as added to a
1605 #define INDEX_REG_CLASS NO_REGS
1607 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1608 registers explicitly used in the rtl to be used as spill registers
1609 but prevents the compiler from extending the lifetime of these
1612 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1614 /* This macro is used later on in the file. */
1615 #define GR_REG_CLASS_P(CLASS) \
1616 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1617 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1618 || (CLASS) == V1_REG \
1619 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1621 /* This macro is also used later on in the file. */
1622 #define COP_REG_CLASS_P(CLASS) \
1623 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1625 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1626 is the default value (allocate the registers in numeric order). We
1627 define it just so that we can override it for the mips16 target in
1628 ORDER_REGS_FOR_LOCAL_ALLOC. */
1630 #define REG_ALLOC_ORDER \
1631 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1632 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1633 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1634 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1635 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1636 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1637 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1638 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1639 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1640 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1641 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1642 176,177,178,179,180,181,182,183,184,185,186,187 \
1645 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1646 to be rearranged based on a particular function. On the mips16, we
1647 want to allocate $24 (T_REG) before other registers for
1648 instructions for which it is possible. */
1650 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1652 /* True if VALUE is an unsigned 6-bit number. */
1654 #define UIMM6_OPERAND(VALUE) \
1655 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1657 /* True if VALUE is a signed 10-bit number. */
1659 #define IMM10_OPERAND(VALUE) \
1660 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1662 /* True if VALUE is a signed 16-bit number. */
1664 #define SMALL_OPERAND(VALUE) \
1665 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1667 /* True if VALUE is an unsigned 16-bit number. */
1669 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1670 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1672 /* True if VALUE can be loaded into a register using LUI. */
1674 #define LUI_OPERAND(VALUE) \
1675 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1676 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1678 /* Return a value X with the low 16 bits clear, and such that
1679 VALUE - X is a signed 16-bit value. */
1681 #define CONST_HIGH_PART(VALUE) \
1682 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1684 #define CONST_LOW_PART(VALUE) \
1685 ((VALUE) - CONST_HIGH_PART (VALUE))
1687 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1688 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1689 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1691 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1692 mips_preferred_reload_class (X, CLASS)
1694 /* Certain machines have the property that some registers cannot be
1695 copied to some other registers without using memory. Define this
1696 macro on those machines to be a C expression that is nonzero if
1697 objects of mode MODE in registers of CLASS1 can only be copied to
1698 registers of class CLASS2 by storing a register of CLASS1 into
1699 memory and loading that memory location into a register of CLASS2.
1701 Do not define this macro if its value would always be zero. */
1703 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1704 ((!TARGET_DEBUG_H_MODE \
1705 && GET_MODE_CLASS (MODE) == MODE_INT \
1706 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1707 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1708 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1709 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1710 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1712 /* The HI and LO registers can only be reloaded via the general
1713 registers. Condition code registers can only be loaded to the
1714 general registers, and from the floating point registers. */
1716 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1717 mips_secondary_reload_class (CLASS, MODE, X, 1)
1718 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1719 mips_secondary_reload_class (CLASS, MODE, X, 0)
1721 /* Return the maximum number of consecutive registers
1722 needed to represent mode MODE in a register of class CLASS. */
1724 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1726 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1727 mips_cannot_change_mode_class (FROM, TO, CLASS)
1729 /* Stack layout; function entry, exit and calling. */
1731 #define STACK_GROWS_DOWNWARD
1733 /* The offset of the first local variable from the beginning of the frame.
1734 See compute_frame_size for details about the frame layout.
1736 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1737 we assume that we will need 16 bytes of argument space. This is because
1738 the value profiling code may emit calls to cmpdi2 in leaf functions.
1739 Without this hack, the local variables will start at sp+8 and the gp save
1740 area will be at sp+16, and thus they will overlap. compute_frame_size is
1741 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1742 will end up as 24 instead of 8. This won't be needed if profiling code is
1743 inserted before virtual register instantiation. */
1745 #define STARTING_FRAME_OFFSET \
1746 ((flag_profile_values && ! TARGET_64BIT \
1747 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1748 : current_function_outgoing_args_size) \
1749 + (TARGET_ABICALLS && !TARGET_NEWABI \
1750 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1752 #define RETURN_ADDR_RTX mips_return_addr
1754 /* Since the mips16 ISA mode is encoded in the least-significant bit
1755 of the address, mask it off return addresses for purposes of
1756 finding exception handling regions. */
1758 #define MASK_RETURN_ADDR GEN_INT (-2)
1761 /* Similarly, don't use the least-significant bit to tell pointers to
1762 code from vtable index. */
1764 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1766 /* The eliminations to $17 are only used for mips16 code. See the
1767 definition of HARD_FRAME_POINTER_REGNUM. */
1769 #define ELIMINABLE_REGS \
1770 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1771 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1772 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1773 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1774 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1775 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1777 /* We can always eliminate to the hard frame pointer. We can eliminate
1778 to the stack pointer unless a frame pointer is needed.
1780 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1781 reload may be unable to compute the address of a local variable,
1782 since there is no way to add a large constant to the stack pointer
1783 without using a temporary register. */
1784 #define CAN_ELIMINATE(FROM, TO) \
1785 ((TO) == HARD_FRAME_POINTER_REGNUM \
1786 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1787 && (!TARGET_MIPS16 \
1788 || compute_frame_size (get_frame_size ()) < 32768)))
1790 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1791 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1793 /* Allocate stack space for arguments at the beginning of each function. */
1794 #define ACCUMULATE_OUTGOING_ARGS 1
1796 /* The argument pointer always points to the first argument. */
1797 #define FIRST_PARM_OFFSET(FNDECL) 0
1799 /* o32 and o64 reserve stack space for all argument registers. */
1800 #define REG_PARM_STACK_SPACE(FNDECL) \
1802 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1805 /* Define this if it is the responsibility of the caller to
1806 allocate the area reserved for arguments passed in registers.
1807 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1808 of this macro is to determine whether the space is included in
1809 `current_function_outgoing_args_size'. */
1810 #define OUTGOING_REG_PARM_STACK_SPACE
1812 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1814 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1816 /* Symbolic macros for the registers used to return integer and floating
1819 #define GP_RETURN (GP_REG_FIRST + 2)
1820 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1822 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1824 /* Symbolic macros for the first/last argument registers. */
1826 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1827 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1828 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1829 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1831 #define LIBCALL_VALUE(MODE) \
1832 mips_function_value (NULL_TREE, NULL, (MODE))
1834 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1835 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1837 /* 1 if N is a possible register number for a function value.
1838 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1839 Currently, R2 and F0 are only implemented here (C has no complex type) */
1841 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1842 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1843 && (N) == FP_RETURN + 2))
1845 /* 1 if N is a possible register number for function argument passing.
1846 We have no FP argument registers when soft-float. When FP registers
1847 are 32 bits, we can't directly reference the odd numbered ones. */
1849 #define FUNCTION_ARG_REGNO_P(N) \
1850 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1851 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1854 /* This structure has to cope with two different argument allocation
1855 schemes. Most MIPS ABIs view the arguments as a structure, of which
1856 the first N words go in registers and the rest go on the stack. If I
1857 < N, the Ith word might go in Ith integer argument register or in a
1858 floating-point register. For these ABIs, we only need to remember
1859 the offset of the current argument into the structure.
1861 The EABI instead allocates the integer and floating-point arguments
1862 separately. The first N words of FP arguments go in FP registers,
1863 the rest go on the stack. Likewise, the first N words of the other
1864 arguments go in integer registers, and the rest go on the stack. We
1865 need to maintain three counts: the number of integer registers used,
1866 the number of floating-point registers used, and the number of words
1867 passed on the stack.
1869 We could keep separate information for the two ABIs (a word count for
1870 the standard ABIs, and three separate counts for the EABI). But it
1871 seems simpler to view the standard ABIs as forms of EABI that do not
1872 allocate floating-point registers.
1874 So for the standard ABIs, the first N words are allocated to integer
1875 registers, and function_arg decides on an argument-by-argument basis
1876 whether that argument should really go in an integer register, or in
1877 a floating-point one. */
1879 typedef struct mips_args {
1880 /* Always true for varargs functions. Otherwise true if at least
1881 one argument has been passed in an integer register. */
1884 /* The number of arguments seen so far. */
1885 unsigned int arg_number;
1887 /* The number of integer registers used so far. For all ABIs except
1888 EABI, this is the number of words that have been added to the
1889 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1890 unsigned int num_gprs;
1892 /* For EABI, the number of floating-point registers used so far. */
1893 unsigned int num_fprs;
1895 /* The number of words passed on the stack. */
1896 unsigned int stack_words;
1898 /* On the mips16, we need to keep track of which floating point
1899 arguments were passed in general registers, but would have been
1900 passed in the FP regs if this were a 32-bit function, so that we
1901 can move them to the FP regs if we wind up calling a 32-bit
1902 function. We record this information in fp_code, encoded in base
1903 four. A zero digit means no floating point argument, a one digit
1904 means an SFmode argument, and a two digit means a DFmode argument,
1905 and a three digit is not used. The low order digit is the first
1906 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1907 an SFmode argument. ??? A more sophisticated approach will be
1908 needed if MIPS_ABI != ABI_32. */
1911 /* True if the function has a prototype. */
1915 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1916 for a call to a function whose data type is FNTYPE.
1917 For a library call, FNTYPE is 0. */
1919 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1920 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1922 /* Update the data in CUM to advance over an argument
1923 of mode MODE and data type TYPE.
1924 (TYPE is null for libcalls where that information may not be available.) */
1926 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1927 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1929 /* Determine where to put an argument to a function.
1930 Value is zero to push the argument on the stack,
1931 or a hard register in which to store the argument.
1933 MODE is the argument's machine mode.
1934 TYPE is the data type of the argument (as a tree).
1935 This is null for libcalls where that information may
1937 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1938 the preceding args and about the function being called.
1939 NAMED is nonzero if this argument is a named parameter
1940 (otherwise it is an extra parameter matching an ellipsis). */
1942 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1943 function_arg( &CUM, MODE, TYPE, NAMED)
1945 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
1947 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1948 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
1950 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1951 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
1953 /* True if using EABI and varargs can be passed in floating-point
1954 registers. Under these conditions, we need a more complex form
1955 of va_list, which tracks GPR, FPR and stack arguments separately. */
1956 #define EABI_FLOAT_VARARGS_P \
1957 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
1960 /* Say that the epilogue uses the return address register. Note that
1961 in the case of sibcalls, the values "used by the epilogue" are
1962 considered live at the start of the called function. */
1963 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
1965 /* Treat LOC as a byte offset from the stack pointer and round it up
1966 to the next fully-aligned offset. */
1967 #define MIPS_STACK_ALIGN(LOC) \
1968 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
1971 /* Implement `va_start' for varargs and stdarg. */
1972 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1973 mips_va_start (valist, nextarg)
1975 /* Output assembler code to FILE to increment profiler label # LABELNO
1976 for profiling a function entry. */
1978 #define FUNCTION_PROFILER(FILE, LABELNO) \
1980 if (TARGET_MIPS16) \
1981 sorry ("mips16 function profiling"); \
1982 fprintf (FILE, "\t.set\tnoat\n"); \
1983 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
1984 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
1985 if (!TARGET_NEWABI) \
1988 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
1989 TARGET_64BIT ? "dsubu" : "subu", \
1990 reg_names[STACK_POINTER_REGNUM], \
1991 reg_names[STACK_POINTER_REGNUM], \
1992 Pmode == DImode ? 16 : 8); \
1994 fprintf (FILE, "\tjal\t_mcount\n"); \
1995 fprintf (FILE, "\t.set\tat\n"); \
1998 /* No mips port has ever used the profiler counter word, so don't emit it
1999 or the label for it. */
2001 #define NO_PROFILE_COUNTERS 1
2003 /* Define this macro if the code for function profiling should come
2004 before the function prologue. Normally, the profiling code comes
2007 /* #define PROFILE_BEFORE_PROLOGUE */
2009 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2010 the stack pointer does not matter. The value is tested only in
2011 functions that have frame pointers.
2012 No definition is equivalent to always zero. */
2014 #define EXIT_IGNORE_STACK 1
2017 /* A C statement to output, on the stream FILE, assembler code for a
2018 block of data that contains the constant parts of a trampoline.
2019 This code should not include a label--the label is taken care of
2022 #define TRAMPOLINE_TEMPLATE(STREAM) \
2024 if (ptr_mode == DImode) \
2025 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2027 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2028 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2029 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2030 if (ptr_mode == DImode) \
2032 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2033 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2034 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2038 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2039 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2040 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2042 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2043 if (ptr_mode == DImode) \
2045 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2046 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2047 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2051 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2052 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2053 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2057 /* A C expression for the size in bytes of the trampoline, as an
2060 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2062 /* Alignment required for trampolines, in bits. */
2064 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2066 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2067 program and data caches. */
2069 #ifndef CACHE_FLUSH_FUNC
2070 #define CACHE_FLUSH_FUNC "_flush_cache"
2073 /* A C statement to initialize the variable parts of a trampoline.
2074 ADDR is an RTX for the address of the trampoline; FNADDR is an
2075 RTX for the address of the nested function; STATIC_CHAIN is an
2076 RTX for the static chain value that should be passed to the
2077 function when it is called. */
2079 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2081 rtx func_addr, chain_addr; \
2083 func_addr = plus_constant (ADDR, 32); \
2084 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2085 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2086 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2088 /* Flush both caches. We need to flush the data cache in case \
2089 the system has a write-back cache. */ \
2090 /* ??? Should check the return value for errors. */ \
2091 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2092 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2093 0, VOIDmode, 3, ADDR, Pmode, \
2094 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2095 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2098 /* Addressing modes, and classification of registers for them. */
2100 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2101 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2102 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2104 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2105 and check its validity for a certain class.
2106 We have two alternate definitions for each of them.
2107 The usual definition accepts all pseudo regs; the other rejects them all.
2108 The symbol REG_OK_STRICT causes the latter definition to be used.
2110 Most source files want to accept pseudo regs in the hope that
2111 they will get allocated to the class that the insn wants them to be in.
2112 Some source files that are used after register allocation
2113 need to be strict. */
2115 #ifndef REG_OK_STRICT
2116 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2117 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2119 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2120 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2123 #define REG_OK_FOR_INDEX_P(X) 0
2126 /* Maximum number of registers that can appear in a valid memory address. */
2128 #define MAX_REGS_PER_ADDRESS 1
2130 #ifdef REG_OK_STRICT
2131 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2133 if (mips_legitimate_address_p (MODE, X, 1)) \
2137 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2139 if (mips_legitimate_address_p (MODE, X, 0)) \
2144 /* Check for constness inline but use mips_legitimate_address_p
2145 to check whether a constant really is an address. */
2147 #define CONSTANT_ADDRESS_P(X) \
2148 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2150 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2152 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2154 if (mips_legitimize_address (&(X), MODE)) \
2159 /* A C statement or compound statement with a conditional `goto
2160 LABEL;' executed if memory address X (an RTX) can have different
2161 meanings depending on the machine mode of the memory reference it
2164 Autoincrement and autodecrement addresses typically have
2165 mode-dependent effects because the amount of the increment or
2166 decrement is the size of the operand being addressed. Some
2167 machines have other mode-dependent addresses. Many RISC machines
2168 have no mode-dependent addresses.
2170 You may assume that ADDR is a valid address for the machine. */
2172 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2174 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2175 'the start of the function that this code is output in'. */
2177 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2178 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2179 asm_fprintf ((FILE), "%U%s", \
2180 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2182 asm_fprintf ((FILE), "%U%s", (NAME))
2184 /* Flag to mark a function decl symbol that requires a long call. */
2185 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2186 #define SYMBOL_REF_LONG_CALL_P(X) \
2187 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2189 /* Specify the machine mode that this machine uses
2190 for the index in the tablejump instruction.
2191 ??? Using HImode in mips16 mode can cause overflow. */
2192 #define CASE_VECTOR_MODE \
2193 (TARGET_MIPS16 ? HImode : ptr_mode)
2195 /* Define as C expression which evaluates to nonzero if the tablejump
2196 instruction expects the table to contain offsets from the address of the
2198 Do not define this if the table should contain absolute addresses. */
2199 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2201 /* Define this as 1 if `char' should by default be signed; else as 0. */
2202 #ifndef DEFAULT_SIGNED_CHAR
2203 #define DEFAULT_SIGNED_CHAR 1
2206 /* Max number of bytes we can move from memory to memory
2207 in one reasonably fast instruction. */
2208 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2209 #define MAX_MOVE_MAX 8
2211 /* Define this macro as a C expression which is nonzero if
2212 accessing less than a word of memory (i.e. a `char' or a
2213 `short') is no faster than accessing a word of memory, i.e., if
2214 such access require more than one instruction or if there is no
2215 difference in cost between byte and (aligned) word loads.
2217 On RISC machines, it tends to generate better code to define
2218 this as 1, since it avoids making a QI or HI mode register. */
2219 #define SLOW_BYTE_ACCESS 1
2221 /* Define this to be nonzero if shift instructions ignore all but the low-order
2223 #define SHIFT_COUNT_TRUNCATED 1
2225 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2226 is done just by pretending it is already truncated. */
2227 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2228 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2231 /* Specify the machine mode that pointers have.
2232 After generation of rtl, the compiler makes no further distinction
2233 between pointers and any other objects of this machine mode. */
2236 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2239 /* Give call MEMs SImode since it is the "most permissive" mode
2240 for both 32-bit and 64-bit targets. */
2242 #define FUNCTION_MODE SImode
2245 /* The cost of loading values from the constant pool. It should be
2246 larger than the cost of any constant we want to synthesize in-line. */
2248 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2250 /* A C expression for the cost of moving data from a register in
2251 class FROM to one in class TO. The classes are expressed using
2252 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2253 the default; other values are interpreted relative to that.
2255 It is not required that the cost always equal 2 when FROM is the
2256 same as TO; on some machines it is expensive to move between
2257 registers if they are not general registers.
2259 If reload sees an insn consisting of a single `set' between two
2260 hard registers, and if `REGISTER_MOVE_COST' applied to their
2261 classes returns a value of 2, reload does not check to ensure
2262 that the constraints of the insn are met. Setting a cost of
2263 other than 2 will allow reload to verify that the constraints are
2264 met. You should do this if the `movM' pattern's constraints do
2265 not allow such copying. */
2267 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2268 mips_register_move_cost (MODE, FROM, TO)
2270 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2271 (mips_cost->memory_latency \
2272 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2274 /* Define if copies to/from condition code registers should be avoided.
2276 This is needed for the MIPS because reload_outcc is not complete;
2277 it needs to handle cases where the source is a general or another
2278 condition code register. */
2279 #define AVOID_CCMODE_COPIES
2281 /* A C expression for the cost of a branch instruction. A value of
2282 1 is the default; other values are interpreted relative to that. */
2284 #define BRANCH_COST mips_cost->branch_cost
2285 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2287 /* If defined, modifies the length assigned to instruction INSN as a
2288 function of the context in which it is used. LENGTH is an lvalue
2289 that contains the initially computed length of the insn and should
2290 be updated with the correct length of the insn. */
2291 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2292 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2294 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2295 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2297 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2298 "%*" OPCODE "%?\t" OPERANDS "%/"
2300 /* Return the asm template for a call. INSN is the instruction's mnemonic
2301 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2304 When generating -mabicalls without explicit relocation operators,
2305 all calls should use assembly macros. Otherwise, all indirect
2306 calls should use "jr" or "jalr"; we will arrange to restore $gp
2307 afterwards if necessary. Finally, we can only generate direct
2308 calls for -mabicalls by temporarily switching to non-PIC mode. */
2309 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2310 (TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS \
2311 ? "%*" INSN "\t%" #OPNO "%/" \
2312 : REG_P (OPERANDS[OPNO]) \
2313 ? "%*" INSN "r\t%" #OPNO "%/" \
2315 ? (".option\tpic0\n\t" \
2316 "%*" INSN "\t%" #OPNO "%/\n\t" \
2318 : "%*" INSN "\t%" #OPNO "%/")
2320 /* Control the assembler format that we output. */
2322 /* Output to assembler file text saying following lines
2323 may contain character constants, extra white space, comments, etc. */
2326 #define ASM_APP_ON " #APP\n"
2329 /* Output to assembler file text saying following lines
2330 no longer contain unusual constructs. */
2333 #define ASM_APP_OFF " #NO_APP\n"
2336 #define REGISTER_NAMES \
2337 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2338 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2339 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2340 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2341 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2342 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2343 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2344 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2345 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2346 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2347 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2348 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2349 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2350 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2351 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2352 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2353 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2354 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2355 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2356 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2357 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2358 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2359 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2360 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2362 /* List the "software" names for each register. Also list the numerical
2363 names for $fp and $sp. */
2365 #define ADDITIONAL_REGISTER_NAMES \
2367 { "$29", 29 + GP_REG_FIRST }, \
2368 { "$30", 30 + GP_REG_FIRST }, \
2369 { "at", 1 + GP_REG_FIRST }, \
2370 { "v0", 2 + GP_REG_FIRST }, \
2371 { "v1", 3 + GP_REG_FIRST }, \
2372 { "a0", 4 + GP_REG_FIRST }, \
2373 { "a1", 5 + GP_REG_FIRST }, \
2374 { "a2", 6 + GP_REG_FIRST }, \
2375 { "a3", 7 + GP_REG_FIRST }, \
2376 { "t0", 8 + GP_REG_FIRST }, \
2377 { "t1", 9 + GP_REG_FIRST }, \
2378 { "t2", 10 + GP_REG_FIRST }, \
2379 { "t3", 11 + GP_REG_FIRST }, \
2380 { "t4", 12 + GP_REG_FIRST }, \
2381 { "t5", 13 + GP_REG_FIRST }, \
2382 { "t6", 14 + GP_REG_FIRST }, \
2383 { "t7", 15 + GP_REG_FIRST }, \
2384 { "s0", 16 + GP_REG_FIRST }, \
2385 { "s1", 17 + GP_REG_FIRST }, \
2386 { "s2", 18 + GP_REG_FIRST }, \
2387 { "s3", 19 + GP_REG_FIRST }, \
2388 { "s4", 20 + GP_REG_FIRST }, \
2389 { "s5", 21 + GP_REG_FIRST }, \
2390 { "s6", 22 + GP_REG_FIRST }, \
2391 { "s7", 23 + GP_REG_FIRST }, \
2392 { "t8", 24 + GP_REG_FIRST }, \
2393 { "t9", 25 + GP_REG_FIRST }, \
2394 { "k0", 26 + GP_REG_FIRST }, \
2395 { "k1", 27 + GP_REG_FIRST }, \
2396 { "gp", 28 + GP_REG_FIRST }, \
2397 { "sp", 29 + GP_REG_FIRST }, \
2398 { "fp", 30 + GP_REG_FIRST }, \
2399 { "ra", 31 + GP_REG_FIRST }, \
2400 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2403 /* This is meant to be redefined in the host dependent files. It is a
2404 set of alternative names and regnums for mips coprocessors. */
2406 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2408 /* A C compound statement to output to stdio stream STREAM the
2409 assembler syntax for an instruction operand X. X is an RTL
2412 CODE is a value that can be used to specify one of several ways
2413 of printing the operand. It is used when identical operands
2414 must be printed differently depending on the context. CODE
2415 comes from the `%' specification that was used to request
2416 printing of the operand. If the specification was just `%DIGIT'
2417 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2418 is the ASCII code for LTR.
2420 If X is a register, this macro should print the register's name.
2421 The names can be found in an array `reg_names' whose type is
2422 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2424 When the machine description has a specification `%PUNCT' (a `%'
2425 followed by a punctuation character), this macro is called with
2426 a null pointer for X and the punctuation character for CODE.
2428 See mips.c for the MIPS specific codes. */
2430 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2432 /* A C expression which evaluates to true if CODE is a valid
2433 punctuation character for use in the `PRINT_OPERAND' macro. If
2434 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2435 punctuation characters (except for the standard one, `%') are
2436 used in this way. */
2438 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2440 /* A C compound statement to output to stdio stream STREAM the
2441 assembler syntax for an instruction operand that is a memory
2442 reference whose address is ADDR. ADDR is an RTL expression. */
2444 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2447 /* A C statement, to be executed after all slot-filler instructions
2448 have been output. If necessary, call `dbr_sequence_length' to
2449 determine the number of slots filled in a sequence (zero if not
2450 currently outputting a sequence), to decide how many no-ops to
2451 output, or whatever.
2453 Don't define this macro if it has nothing to do, but it is
2454 helpful in reading assembly output if the extent of the delay
2455 sequence is made explicit (e.g. with white space).
2457 Note that output routines for instructions with delay slots must
2458 be prepared to deal with not being output as part of a sequence
2459 (i.e. when the scheduling pass is not run, or when no slot
2460 fillers could be found.) The variable `final_sequence' is null
2461 when not processing a sequence, otherwise it contains the
2462 `sequence' rtx being output. */
2464 #define DBR_OUTPUT_SEQEND(STREAM) \
2467 if (set_nomacro > 0 && --set_nomacro == 0) \
2468 fputs ("\t.set\tmacro\n", STREAM); \
2470 if (set_noreorder > 0 && --set_noreorder == 0) \
2471 fputs ("\t.set\treorder\n", STREAM); \
2473 fputs ("\n", STREAM); \
2478 /* How to tell the debugger about changes of source files. */
2479 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2480 mips_output_filename (STREAM, NAME)
2482 /* mips-tfile does not understand .stabd directives. */
2483 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2484 dbxout_begin_stabn_sline (LINE); \
2485 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2488 /* Use .loc directives for SDB line numbers. */
2489 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2490 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2492 /* The MIPS implementation uses some labels for its own purpose. The
2493 following lists what labels are created, and are all formed by the
2494 pattern $L[a-z].*. The machine independent portion of GCC creates
2495 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2497 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2498 $Lb[0-9]+ Begin blocks for MIPS debug support
2499 $Lc[0-9]+ Label for use in s<xx> operation.
2500 $Le[0-9]+ End blocks for MIPS debug support */
2502 #undef ASM_DECLARE_OBJECT_NAME
2503 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2504 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2506 /* Globalizing directive for a label. */
2507 #define GLOBAL_ASM_OP "\t.globl\t"
2509 /* This says how to define a global common symbol. */
2511 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2513 /* This says how to define a local common symbol (i.e., not visible to
2516 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2517 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2518 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2521 /* This says how to output an external. It would be possible not to
2522 output anything and let undefined symbol become external. However
2523 the assembler uses length information on externals to allocate in
2524 data/sdata bss/sbss, thereby saving exec time. */
2526 #undef ASM_OUTPUT_EXTERNAL
2527 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2528 mips_output_external(STREAM,DECL,NAME)
2530 /* This is how to declare a function name. The actual work of
2531 emitting the label is moved to function_prologue, so that we can
2532 get the line number correctly emitted before the .ent directive,
2533 and after any .file directives. Define as empty so that the function
2534 is not declared before the .ent directive elsewhere. */
2536 #undef ASM_DECLARE_FUNCTION_NAME
2537 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2539 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2540 #define FUNCTION_NAME_ALREADY_DECLARED 0
2543 /* This is how to store into the string LABEL
2544 the symbol_ref name of an internal numbered label where
2545 PREFIX is the class of label and NUM is the number within the class.
2546 This is suitable for output with `assemble_name'. */
2548 #undef ASM_GENERATE_INTERNAL_LABEL
2549 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2550 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2552 /* This is how to output an element of a case-vector that is absolute. */
2554 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2555 fprintf (STREAM, "\t%s\t%sL%d\n", \
2556 ptr_mode == DImode ? ".dword" : ".word", \
2557 LOCAL_LABEL_PREFIX, \
2560 /* This is how to output an element of a case-vector. We can make the
2561 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2564 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2566 if (TARGET_MIPS16) \
2567 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2568 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2569 else if (TARGET_GPWORD) \
2570 fprintf (STREAM, "\t%s\t%sL%d\n", \
2571 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2572 LOCAL_LABEL_PREFIX, VALUE); \
2574 fprintf (STREAM, "\t%s\t%sL%d\n", \
2575 ptr_mode == DImode ? ".dword" : ".word", \
2576 LOCAL_LABEL_PREFIX, VALUE); \
2579 /* When generating MIPS16 code, we want the jump table to be in the text
2580 section so that we can load its address using a PC-relative addition. */
2581 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2583 /* This is how to output an assembler line
2584 that says to advance the location counter
2585 to a multiple of 2**LOG bytes. */
2587 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2588 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2590 /* This is how to output an assembler line to advance the location
2591 counter by SIZE bytes. */
2593 #undef ASM_OUTPUT_SKIP
2594 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2595 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2597 /* This is how to output a string. */
2598 #undef ASM_OUTPUT_ASCII
2599 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2600 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2602 /* Output #ident as a in the read-only data section. */
2603 #undef ASM_OUTPUT_IDENT
2604 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2606 const char *p = STRING; \
2607 int size = strlen (p) + 1; \
2608 switch_to_section (readonly_data_section); \
2609 assemble_string (p, size); \
2612 /* Default to -G 8 */
2613 #ifndef MIPS_DEFAULT_GVALUE
2614 #define MIPS_DEFAULT_GVALUE 8
2617 /* Define the strings to put out for each section in the object file. */
2618 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2619 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2621 #undef READONLY_DATA_SECTION_ASM_OP
2622 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2624 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2627 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2628 TARGET_64BIT ? "dsubu" : "subu", \
2629 reg_names[STACK_POINTER_REGNUM], \
2630 reg_names[STACK_POINTER_REGNUM], \
2631 TARGET_64BIT ? "sd" : "sw", \
2633 reg_names[STACK_POINTER_REGNUM]); \
2637 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2640 if (! set_noreorder) \
2641 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2643 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2644 TARGET_64BIT ? "ld" : "lw", \
2646 reg_names[STACK_POINTER_REGNUM], \
2647 TARGET_64BIT ? "daddu" : "addu", \
2648 reg_names[STACK_POINTER_REGNUM], \
2649 reg_names[STACK_POINTER_REGNUM]); \
2651 if (! set_noreorder) \
2652 fprintf (STREAM, "\t.set\treorder\n"); \
2656 /* How to start an assembler comment.
2657 The leading space is important (the mips native assembler requires it). */
2658 #ifndef ASM_COMMENT_START
2659 #define ASM_COMMENT_START " #"
2662 /* Default definitions for size_t and ptrdiff_t. We must override the
2663 definitions from ../svr4.h on mips-*-linux-gnu. */
2666 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2669 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2672 /* Since the bits of the _init and _fini function is spread across
2673 many object files, each potentially with its own GP, we must assume
2674 we need to load our GP. We don't preserve $gp or $ra, since each
2675 init/fini chunk is supposed to initialize $gp, and crti/crtn
2676 already take care of preserving $ra and, when appropriate, $gp. */
2677 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2678 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2679 asm (SECTION_OP "\n\
2685 jal " USER_LABEL_PREFIX #FUNC "\n\
2686 " TEXT_SECTION_ASM_OP);
2687 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2688 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2689 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2690 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2691 asm (SECTION_OP "\n\
2696 .cpsetup $31, $2, 1b\n\
2697 jal " USER_LABEL_PREFIX #FUNC "\n\
2698 " TEXT_SECTION_ASM_OP);
2703 #define HAVE_AS_TLS 0
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