1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
83 /* Recast the cpu class to be the cpu attribute. */
84 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
86 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
87 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
88 to work on a 64 bit machine. */
95 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
96 which is not the same as the above EABI (defined by Cygnus,
97 Greenhills, and Toshiba?). MEABI is not yet complete or published,
98 but at this point it looks like N32 as far as calling conventions go,
99 but allows for either 32 or 64 bit registers.
101 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
102 EABI the legacy EABI. In the end we may end up calling both ABI's
103 EABI but give them different version numbers, but for now I'm going
104 with different names. */
107 /* Whether to emit abicalls code sequences or not. */
109 enum mips_abicalls_type {
114 /* Recast the abicalls class to be the abicalls attribute. */
115 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
117 /* Which type of block move to do (whether or not the last store is
118 split out so it can fill a branch delay slot). */
120 enum block_move_type {
121 BLOCK_MOVE_NORMAL, /* generate complete block move */
122 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
123 BLOCK_MOVE_LAST /* generate just the last store */
126 /* Information about one recognized processor. Defined here for the
127 benefit of TARGET_CPU_CPP_BUILTINS. */
128 struct mips_cpu_info {
129 /* The 'canonical' name of the processor as far as GCC is concerned.
130 It's typically a manufacturer's prefix followed by a numerical
131 designation. It should be lower case. */
134 /* The internal processor number that most closely matches this
135 entry. Several processors can have the same value, if there's no
136 difference between them from GCC's point of view. */
137 enum processor_type cpu;
139 /* The ISA level that the processor implements. */
143 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
144 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
145 extern const char *current_function_file; /* filename current function is in */
146 extern int num_source_filenames; /* current .file # */
147 extern int inside_function; /* != 0 if inside of a function */
148 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
149 extern int file_in_function_warning; /* warning given about .file in func */
150 extern int sdb_label_count; /* block start/end next label # */
151 extern int sdb_begin_function_line; /* Starting Line of current function */
152 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
153 extern int g_switch_value; /* value of the -G xx switch */
154 extern int g_switch_set; /* whether -G xx was passed. */
155 extern int sym_lineno; /* sgi next label # for each stmt */
156 extern int set_noreorder; /* # of nested .set noreorder's */
157 extern int set_nomacro; /* # of nested .set nomacro's */
158 extern int set_noat; /* # of nested .set noat's */
159 extern int set_volatile; /* # of nested .set volatile's */
160 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
161 extern int mips_dbx_regno[]; /* Map register # to debug register # */
162 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
163 extern enum cmp_type branch_type; /* what type of branch to use */
164 extern enum processor_type mips_arch; /* which cpu to codegen for */
165 extern enum processor_type mips_tune; /* which cpu to schedule for */
166 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
167 extern int mips_isa; /* architectural level */
168 extern int mips16; /* whether generating mips16 code */
169 extern int mips16_hard_float; /* mips16 without -msoft-float */
170 extern int mips_entry; /* generate entry/exit for mips16 */
171 extern const char *mips_arch_string; /* for -march=<xxx> */
172 extern const char *mips_tune_string; /* for -mtune=<xxx> */
173 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
174 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
175 extern const char *mips_entry_string; /* for -mentry */
176 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
177 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
178 extern int mips_split_addresses; /* perform high/lo_sum support */
179 extern int dslots_load_total; /* total # load related delay slots */
180 extern int dslots_load_filled; /* # filled load delay slots */
181 extern int dslots_jump_total; /* total # jump related delay slots */
182 extern int dslots_jump_filled; /* # filled jump delay slots */
183 extern int dslots_number_nops; /* # of nops needed by previous insn */
184 extern int num_refs[3]; /* # 1/2/3 word references */
185 extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
186 extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
187 extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
188 extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
189 extern int mips_string_length; /* length of strings for mips16 */
190 extern const struct mips_cpu_info mips_cpu_info_table[];
191 extern const struct mips_cpu_info *mips_arch_info;
192 extern const struct mips_cpu_info *mips_tune_info;
194 /* Functions to change what output section we are using. */
195 extern void sdata_section PARAMS ((void));
196 extern void sbss_section PARAMS ((void));
198 /* Macros to silence warnings about numbers being signed in traditional
199 C and unsigned in ISO C when compiled on 32-bit hosts. */
201 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
202 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
203 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
206 /* Run-time compilation parameters selecting different hardware subsets. */
208 /* Macros used in the machine description to test the flags. */
210 /* Bits for real switches */
211 #define MASK_INT64 0x00000001 /* ints are 64 bits */
212 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
213 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
214 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
215 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
216 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
217 #define MASK_STATS 0x00000040 /* print statistics to stderr */
218 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
219 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
220 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
221 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
222 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
223 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
224 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
225 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
226 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
227 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
228 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
229 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
230 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
231 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
232 #define MASK_NO_CHECK_ZERO_DIV \
233 0x00200000 /* divide by zero checking */
234 #define MASK_CHECK_RANGE_DIV \
235 0x00400000 /* divide result range checking */
236 #define MASK_UNINIT_CONST_IN_RODATA \
237 0x00800000 /* Store uninitialized
239 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
240 multiply-add operations. */
241 #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
244 /* Debug switches, not documented */
245 #define MASK_DEBUG 0 /* unused */
246 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
247 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
248 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
249 #define MASK_DEBUG_D 0 /* don't do define_split's */
250 #define MASK_DEBUG_E 0 /* function_arg debug */
251 #define MASK_DEBUG_F 0 /* ??? */
252 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
253 #define MASK_DEBUG_I 0 /* unused */
255 /* Dummy switches used only in specs */
256 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
258 /* r4000 64 bit sizes */
259 #define TARGET_INT64 (target_flags & MASK_INT64)
260 #define TARGET_LONG64 (target_flags & MASK_LONG64)
261 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
262 #define TARGET_64BIT (target_flags & MASK_64BIT)
264 /* Mips vs. GNU linker */
265 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
267 /* Mips vs. GNU assembler */
268 #define TARGET_GAS (target_flags & MASK_GAS)
269 #define TARGET_MIPS_AS (!TARGET_GAS)
272 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
273 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
274 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
275 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
276 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
277 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
278 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
279 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
280 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
282 /* Reg. Naming in .s ($21 vs. $a0) */
283 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
285 /* Optimize for Sdata/Sbss */
286 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
288 /* print program statistics */
289 #define TARGET_STATS (target_flags & MASK_STATS)
291 /* call memcpy instead of inline code */
292 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
294 /* .abicalls, etc from Pyramid V.4 */
295 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
297 /* software floating point */
298 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
299 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
301 /* always call through a register */
302 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
304 /* generate embedded PIC code;
306 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
308 /* for embedded systems, optimize for
309 reduced RAM space instead of for
311 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
313 /* always store uninitialized const
314 variables in rodata, requires
315 TARGET_EMBEDDED_DATA. */
316 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
318 /* generate big endian code. */
319 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
321 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
322 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
324 #define TARGET_MAD (target_flags & MASK_MAD)
326 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
328 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
330 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
331 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
333 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
335 /* This is true if we must enable the assembly language file switching
338 #define TARGET_FILE_SWITCHING \
339 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
341 /* We must disable the function end stabs when doing the file switching trick,
342 because the Lscope stabs end up in the wrong place, making it impossible
343 to debug the resulting code. */
344 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
346 /* Generate mips16 code */
347 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
349 /* Generic ISA defines. */
350 #define ISA_MIPS1 (mips_isa == 1)
351 #define ISA_MIPS2 (mips_isa == 2)
352 #define ISA_MIPS3 (mips_isa == 3)
353 #define ISA_MIPS4 (mips_isa == 4)
354 #define ISA_MIPS32 (mips_isa == 32)
355 #define ISA_MIPS32R2 (mips_isa == 33)
356 #define ISA_MIPS64 (mips_isa == 64)
358 /* Architecture target defines. */
359 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
360 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
361 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
362 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
363 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
364 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
365 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
366 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
367 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
368 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
369 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
371 /* Scheduling target defines. */
372 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
373 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
374 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
375 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
376 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
377 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
378 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
379 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
380 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
382 /* Define preprocessor macros for the -march and -mtune options.
383 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
384 processor. If INFO's canonical name is "foo", define PREFIX to
385 be "foo", and define an additional macro PREFIX_FOO. */
386 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
391 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
392 for (p = macro; *p != 0; p++) \
395 builtin_define (macro); \
396 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
401 /* Target CPU builtins. */
402 #define TARGET_CPU_CPP_BUILTINS() \
405 builtin_assert ("cpu=mips"); \
406 builtin_define ("__mips__"); \
407 builtin_define ("_mips"); \
409 /* We do this here because __mips is defined below \
410 and so we can't use builtin_define_std. */ \
412 builtin_define ("mips"); \
414 /* Treat _R3000 and _R4000 like register-size defines, \
415 which is how they've historically been used. */ \
418 builtin_define ("__mips64"); \
419 builtin_define_std ("R4000"); \
420 builtin_define ("_R4000"); \
424 builtin_define_std ("R3000"); \
425 builtin_define ("_R3000"); \
427 if (TARGET_FLOAT64) \
428 builtin_define ("__mips_fpr=64"); \
430 builtin_define ("__mips_fpr=32"); \
433 builtin_define ("__mips16"); \
435 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
436 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
440 builtin_define ("__mips=1"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
443 else if (ISA_MIPS2) \
445 builtin_define ("__mips=2"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
448 else if (ISA_MIPS3) \
450 builtin_define ("__mips=3"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
453 else if (ISA_MIPS4) \
455 builtin_define ("__mips=4"); \
456 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
458 else if (ISA_MIPS32) \
460 builtin_define ("__mips=32"); \
461 builtin_define ("__mips_isa_rev=1"); \
462 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
464 else if (ISA_MIPS32R2) \
466 builtin_define ("__mips=32"); \
467 builtin_define ("__mips_isa_rev=2"); \
468 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
470 else if (ISA_MIPS64) \
472 builtin_define ("__mips=64"); \
473 builtin_define ("__mips_isa_rev=1"); \
474 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
477 if (TARGET_HARD_FLOAT) \
478 builtin_define ("__mips_hard_float"); \
479 else if (TARGET_SOFT_FLOAT) \
480 builtin_define ("__mips_soft_float"); \
482 if (TARGET_SINGLE_FLOAT) \
483 builtin_define ("__mips_single_float"); \
485 if (TARGET_BIG_ENDIAN) \
487 builtin_define_std ("MIPSEB"); \
488 builtin_define ("_MIPSEB"); \
492 builtin_define_std ("MIPSEL"); \
493 builtin_define ("_MIPSEL"); \
496 /* Macros dependent on the C dialect. */ \
497 if (preprocessing_asm_p ()) \
499 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
500 builtin_define ("_LANGUAGE_ASSEMBLY"); \
502 else if (c_language == clk_c) \
504 builtin_define_std ("LANGUAGE_C"); \
505 builtin_define ("_LANGUAGE_C"); \
507 else if (c_language == clk_cplusplus) \
509 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
510 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
511 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
515 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
516 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
517 /* Bizzare, but needed at least for Irix. */ \
518 builtin_define_std ("LANGUAGE_C"); \
519 builtin_define ("_LANGUAGE_C"); \
522 if (mips_abi == ABI_EABI) \
523 builtin_define ("__mips_eabi"); \
529 /* Macro to define tables used to set the flags.
530 This is a list in braces of pairs in braces,
531 each pair being { "NAME", VALUE }
532 where VALUE is the bits to set or minus the bits to clear.
533 An empty string NAME is used to identify the default VALUE. */
535 #define TARGET_SWITCHES \
537 SUBTARGET_TARGET_SWITCHES \
539 N_("No default crt0.o") }, \
540 {"int64", MASK_INT64 | MASK_LONG64, \
541 N_("Use 64-bit int type")}, \
542 {"long64", MASK_LONG64, \
543 N_("Use 64-bit long type")}, \
544 {"long32", -(MASK_LONG64 | MASK_INT64), \
545 N_("Use 32-bit long type")}, \
546 {"split-addresses", MASK_SPLIT_ADDR, \
547 N_("Optimize lui/addiu address loads")}, \
548 {"no-split-addresses", -MASK_SPLIT_ADDR, \
549 N_("Don't optimize lui/addiu address loads")}, \
550 {"mips-as", -MASK_GAS, \
551 N_("Use MIPS as")}, \
554 {"rnames", MASK_NAME_REGS, \
555 N_("Use symbolic register names")}, \
556 {"no-rnames", -MASK_NAME_REGS, \
557 N_("Don't use symbolic register names")}, \
558 {"gpOPT", MASK_GPOPT, \
559 N_("Use GP relative sdata/sbss sections")}, \
560 {"gpopt", MASK_GPOPT, \
561 N_("Use GP relative sdata/sbss sections")}, \
562 {"no-gpOPT", -MASK_GPOPT, \
563 N_("Don't use GP relative sdata/sbss sections")}, \
564 {"no-gpopt", -MASK_GPOPT, \
565 N_("Don't use GP relative sdata/sbss sections")}, \
566 {"stats", MASK_STATS, \
567 N_("Output compiler statistics")}, \
568 {"no-stats", -MASK_STATS, \
569 N_("Don't output compiler statistics")}, \
570 {"memcpy", MASK_MEMCPY, \
571 N_("Don't optimize block moves")}, \
572 {"no-memcpy", -MASK_MEMCPY, \
573 N_("Optimize block moves")}, \
574 {"mips-tfile", MASK_MIPS_TFILE, \
575 N_("Use mips-tfile asm postpass")}, \
576 {"no-mips-tfile", -MASK_MIPS_TFILE, \
577 N_("Don't use mips-tfile asm postpass")}, \
578 {"soft-float", MASK_SOFT_FLOAT, \
579 N_("Use software floating point")}, \
580 {"hard-float", -MASK_SOFT_FLOAT, \
581 N_("Use hardware floating point")}, \
582 {"fp64", MASK_FLOAT64, \
583 N_("Use 64-bit FP registers")}, \
584 {"fp32", -MASK_FLOAT64, \
585 N_("Use 32-bit FP registers")}, \
586 {"gp64", MASK_64BIT, \
587 N_("Use 64-bit general registers")}, \
588 {"gp32", -MASK_64BIT, \
589 N_("Use 32-bit general registers")}, \
590 {"abicalls", MASK_ABICALLS, \
591 N_("Use Irix PIC")}, \
592 {"no-abicalls", -MASK_ABICALLS, \
593 N_("Don't use Irix PIC")}, \
594 {"long-calls", MASK_LONG_CALLS, \
595 N_("Use indirect calls")}, \
596 {"no-long-calls", -MASK_LONG_CALLS, \
597 N_("Don't use indirect calls")}, \
598 {"embedded-pic", MASK_EMBEDDED_PIC, \
599 N_("Use embedded PIC")}, \
600 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
601 N_("Don't use embedded PIC")}, \
602 {"embedded-data", MASK_EMBEDDED_DATA, \
603 N_("Use ROM instead of RAM")}, \
604 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
605 N_("Don't use ROM instead of RAM")}, \
606 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
607 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
608 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
609 N_("Don't put uninitialized constants in ROM")}, \
610 {"eb", MASK_BIG_ENDIAN, \
611 N_("Use big-endian byte order")}, \
612 {"el", -MASK_BIG_ENDIAN, \
613 N_("Use little-endian byte order")}, \
614 {"single-float", MASK_SINGLE_FLOAT, \
615 N_("Use single (32-bit) FP only")}, \
616 {"double-float", -MASK_SINGLE_FLOAT, \
617 N_("Don't use single (32-bit) FP only")}, \
619 N_("Use multiply accumulate")}, \
620 {"no-mad", -MASK_MAD, \
621 N_("Don't use multiply accumulate")}, \
622 {"no-fused-madd", MASK_NO_FUSED_MADD, \
623 N_("Don't generate fused multiply/add instructions")}, \
624 {"fused-madd", -MASK_NO_FUSED_MADD, \
625 N_("Generate fused multiply/add instructions")}, \
626 {"fix4300", MASK_4300_MUL_FIX, \
627 N_("Work around early 4300 hardware bug")}, \
628 {"no-fix4300", -MASK_4300_MUL_FIX, \
629 N_("Don't work around early 4300 hardware bug")}, \
630 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
631 N_("Trap on integer divide by zero")}, \
632 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
633 N_("Don't trap on integer divide by zero")}, \
634 {"check-range-division",MASK_CHECK_RANGE_DIV, \
635 N_("Trap on integer divide overflow")}, \
636 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
637 N_("Don't trap on integer divide overflow")}, \
638 { "branch-likely", MASK_BRANCHLIKELY, \
639 N_("Use Branch Likely instructions, overriding default for arch")}, \
640 { "no-branch-likely", -MASK_BRANCHLIKELY, \
641 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
642 {"debug", MASK_DEBUG, \
644 {"debuga", MASK_DEBUG_A, \
646 {"debugb", MASK_DEBUG_B, \
648 {"debugc", MASK_DEBUG_C, \
650 {"debugd", MASK_DEBUG_D, \
652 {"debuge", MASK_DEBUG_E, \
654 {"debugf", MASK_DEBUG_F, \
656 {"debugg", MASK_DEBUG_G, \
658 {"debugi", MASK_DEBUG_I, \
660 {"", (TARGET_DEFAULT \
661 | TARGET_CPU_DEFAULT \
662 | TARGET_ENDIAN_DEFAULT), \
666 /* Default target_flags if no switches are specified */
668 #ifndef TARGET_DEFAULT
669 #define TARGET_DEFAULT 0
672 #ifndef TARGET_CPU_DEFAULT
673 #define TARGET_CPU_DEFAULT 0
676 #ifndef TARGET_ENDIAN_DEFAULT
677 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
680 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
681 #ifndef MIPS_ISA_DEFAULT
682 #ifndef MIPS_CPU_STRING_DEFAULT
683 #define MIPS_CPU_STRING_DEFAULT "from-abi"
689 /* Make this compile time constant for libgcc2 */
691 #define TARGET_64BIT 1
693 #define TARGET_64BIT 0
695 #endif /* IN_LIBGCC2 */
697 #ifndef MULTILIB_ENDIAN_DEFAULT
698 #if TARGET_ENDIAN_DEFAULT == 0
699 #define MULTILIB_ENDIAN_DEFAULT "EL"
701 #define MULTILIB_ENDIAN_DEFAULT "EB"
705 #ifndef MULTILIB_ISA_DEFAULT
706 # if MIPS_ISA_DEFAULT == 1
707 # define MULTILIB_ISA_DEFAULT "mips1"
709 # if MIPS_ISA_DEFAULT == 2
710 # define MULTILIB_ISA_DEFAULT "mips2"
712 # if MIPS_ISA_DEFAULT == 3
713 # define MULTILIB_ISA_DEFAULT "mips3"
715 # if MIPS_ISA_DEFAULT == 4
716 # define MULTILIB_ISA_DEFAULT "mips4"
718 # if MIPS_ISA_DEFAULT == 32
719 # define MULTILIB_ISA_DEFAULT "mips32"
721 # if MIPS_ISA_DEFAULT == 33
722 # define MULTILIB_ISA_DEFAULT "mips32r2"
724 # if MIPS_ISA_DEFAULT == 64
725 # define MULTILIB_ISA_DEFAULT "mips64"
727 # define MULTILIB_ISA_DEFAULT "mips1"
737 #ifndef MULTILIB_DEFAULTS
738 #define MULTILIB_DEFAULTS \
739 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
742 /* We must pass -EL to the linker by default for little endian embedded
743 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
744 linker will default to using big-endian output files. The OUTPUT_FORMAT
745 line must be in the linker script, otherwise -EB/-EL will not work. */
748 #if TARGET_ENDIAN_DEFAULT == 0
749 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
751 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
755 #define TARGET_OPTIONS \
757 SUBTARGET_TARGET_OPTIONS \
758 { "tune=", &mips_tune_string, \
759 N_("Specify CPU for scheduling purposes")}, \
760 { "arch=", &mips_arch_string, \
761 N_("Specify CPU for code generation purposes")}, \
762 { "abi=", &mips_abi_string, \
763 N_("Specify an ABI")}, \
764 { "ips", &mips_isa_string, \
765 N_("Specify a Standard MIPS ISA")}, \
766 { "entry", &mips_entry_string, \
767 N_("Use mips16 entry/exit psuedo ops")}, \
768 { "no-mips16", &mips_no_mips16_string, \
769 N_("Don't use MIPS16 instructions")}, \
770 { "no-flush-func", &mips_cache_flush_func, \
771 N_("Don't call any cache flush functions")}, \
772 { "flush-func=", &mips_cache_flush_func, \
773 N_("Specify cache flush function")}, \
776 /* This is meant to be redefined in the host dependent files. */
777 #define SUBTARGET_TARGET_OPTIONS
779 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
783 /* Generate three-operand multiply instructions for SImode. */
784 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
792 /* Generate three-operand multiply instructions for DImode. */
793 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
796 /* Macros to decide whether certain features are available or not,
797 depending on the instruction set architecture level. */
799 #define HAVE_SQRT_P() (!ISA_MIPS1)
801 /* True if the ABI can only work with 64-bit integer registers. We
802 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
803 otherwise floating-point registers must also be 64-bit. */
804 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
805 || mips_abi == ABI_O64 \
806 || mips_abi == ABI_N32)
808 /* Likewise for 32-bit regs. */
809 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
811 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
812 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
816 /* ISA has branch likely instructions (eg. mips2). */
817 /* Disable branchlikely for tx39 until compare rewrite. They haven't
818 been generated up to this point. */
819 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
822 /* ISA has the conditional move instructions introduced in mips4. */
823 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
827 && !TARGET_MIPS5500 \
830 /* ISA has just the integer condition move instructions (movn,movz) */
831 #define ISA_HAS_INT_CONDMOVE 0
833 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
834 branch on CC, and move (both FP and non-FP) on CC. */
835 #define ISA_HAS_8CC (ISA_MIPS4 \
840 /* This is a catch all for the other new mips4 instructions: indexed load and
841 indexed prefetch instructions, the FP madd and msub instructions,
842 and the FP recip and recip sqrt instructions */
843 #define ISA_HAS_FP4 ((ISA_MIPS4 \
847 /* ISA has conditional trap instructions. */
848 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
851 /* ISA has integer multiply-accumulate instructions, madd and msub. */
852 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
857 /* ISA has floating-point nmadd and nmsub instructions. */
858 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
860 && (!TARGET_MIPS5400 || TARGET_MAD) \
863 /* ISA has count leading zeroes/ones instruction (not implemented). */
864 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
869 /* ISA has double-word count leading zeroes/ones instruction (not
871 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
874 /* ISA has three operand multiply instructions that put
875 the high part in an accumulator: mulhi or mulhiu. */
876 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
881 /* ISA has three operand multiply instructions that
882 negates the result and puts the result in an accumulator. */
883 #define ISA_HAS_MULS (TARGET_MIPS5400 \
888 /* ISA has three operand multiply instructions that subtracts the
889 result from a 4th operand and puts the result in an accumulator. */
890 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
894 /* ISA has three operand multiply instructions that the result
895 from a 4th operand and puts the result in an accumulator. */
896 #define ISA_HAS_MACC (TARGET_MIPS5400 \
901 /* ISA has 32-bit rotate right instruction. */
902 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
909 /* ISA has 64-bit rotate right instruction. */
910 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
912 && (TARGET_MIPS5400 \
917 /* ISA has data prefetch instruction. */
918 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
924 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
925 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
926 also requires TARGET_DOUBLE_FLOAT. */
927 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
929 /* ISA includes the MIPS32r2 seb and seh instructions. */
930 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
934 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
935 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
936 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
937 target_flags, and -mgp64 sets MASK_64BIT.
939 Setting MASK_64BIT in target_flags will cause gcc to assume that
940 registers are 64 bits wide. int, long and void * will be 32 bit;
941 this may be changed with -mint64 or -mlong64.
943 The gen* programs link code that refers to MASK_64BIT. They don't
944 actually use the information in target_flags; they just refer to
947 /* Switch Recognition by gcc.c. Add -G xx support */
949 #undef SWITCH_TAKES_ARG
950 #define SWITCH_TAKES_ARG(CHAR) \
951 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
953 /* Sometimes certain combinations of command options do not make sense
954 on a particular target machine. You can define a macro
955 `OVERRIDE_OPTIONS' to take account of this. This macro, if
956 defined, is executed once just after all the command options have
959 On the MIPS, it is used to handle -G. We also use it to set up all
960 of the tables referenced in the other macros. */
962 #define OVERRIDE_OPTIONS override_options ()
964 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
966 /* Show we can debug even without a frame pointer. */
967 #define CAN_DEBUG_WITHOUT_FP
969 /* Tell collect what flags to pass to nm. */
971 #define NM_FLAGS "-Bn"
975 /* Assembler specs. */
977 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
980 #define MIPS_AS_ASM_SPEC "\
981 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
982 %{pipe: %e-pipe is not supported} \
983 %{K} %(subtarget_mips_as_asm_spec)"
985 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
986 rather than gas. It may be overridden by subtargets. */
988 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
989 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
992 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
995 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
997 #define SUBTARGET_TARGET_SWITCHES
1001 #ifndef MIPS_ABI_DEFAULT
1002 #define MIPS_ABI_DEFAULT ABI_32
1005 /* Use the most portable ABI flag for the ASM specs. */
1007 #if MIPS_ABI_DEFAULT == ABI_32
1008 #define MULTILIB_ABI_DEFAULT "mabi=32"
1009 #define ASM_ABI_DEFAULT_SPEC "-32"
1012 #if MIPS_ABI_DEFAULT == ABI_O64
1013 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1014 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1017 #if MIPS_ABI_DEFAULT == ABI_N32
1018 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1019 #define ASM_ABI_DEFAULT_SPEC "-n32"
1022 #if MIPS_ABI_DEFAULT == ABI_64
1023 #define MULTILIB_ABI_DEFAULT "mabi=64"
1024 #define ASM_ABI_DEFAULT_SPEC "-64"
1027 #if MIPS_ABI_DEFAULT == ABI_EABI
1028 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1029 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1032 #if MIPS_ABI_DEFAULT == ABI_MEABI
1033 /* Most GAS don't know about MEABI. */
1034 #define MULTILIB_ABI_DEFAULT "mabi=meabi"
1035 #define ASM_ABI_DEFAULT_SPEC ""
1038 /* Only ELF targets can switch the ABI. */
1039 #ifndef OBJECT_FORMAT_ELF
1040 #undef ASM_ABI_DEFAULT_SPEC
1041 #define ASM_ABI_DEFAULT_SPEC ""
1044 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1045 GAS_ASM_SPEC as the default, depending upon the value of
1048 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1051 #define TARGET_ASM_SPEC "\
1052 %{mmips-as: %(mips_as_asm_spec)} \
1053 %{!mmips-as: %(gas_asm_spec)}"
1057 #define TARGET_ASM_SPEC "\
1058 %{!mgas: %(mips_as_asm_spec)} \
1059 %{mgas: %(gas_asm_spec)}"
1061 #endif /* not GAS */
1063 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1064 to the assembler. It may be overridden by subtargets. */
1065 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1066 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1068 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1071 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1072 the assembler. It may be overridden by subtargets. */
1073 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1074 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1075 %{g} %{g0} %{g1} %{g2} %{g3} \
1076 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1077 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1078 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1079 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1080 %{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1083 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1084 overridden by subtargets. */
1086 #ifndef SUBTARGET_ASM_SPEC
1087 #define SUBTARGET_ASM_SPEC ""
1090 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1091 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1092 whether we're using GAS. These options can only be used properly
1093 with GAS, and it is better to get an error from a non-GAS assembler
1094 than to silently generate bad code. */
1098 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1099 %{mips32} %{mips32r2} %{mips64} \
1100 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1101 %(subtarget_asm_optimizing_spec) \
1102 %(subtarget_asm_debugging_spec) \
1104 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1105 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1106 %{mgp32} %{mgp64} %{march=*} \
1107 %(target_asm_spec) \
1108 %(subtarget_asm_spec)"
1110 /* Specify to run a post-processor, mips-tfile after the assembler
1111 has run to stuff the mips debug information into the object file.
1112 This is needed because the $#!%^ MIPS assembler provides no way
1113 of specifying such information in the assembly file. If we are
1114 cross compiling, disable mips-tfile unless the user specifies
1117 #ifndef ASM_FINAL_SPEC
1118 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1120 #define ASM_FINAL_SPEC "\
1121 %{mmips-as: %{!mno-mips-tfile: \
1122 \n mips-tfile %{v*: -v} \
1124 %{!K: %{save-temps: -I %b.o~}} \
1125 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1126 %{.s:%i} %{!.s:%g.s}}}"
1130 #define ASM_FINAL_SPEC "\
1131 %{!mgas: %{!mno-mips-tfile: \
1132 \n mips-tfile %{v*: -v} \
1134 %{!K: %{save-temps: -I %b.o~}} \
1135 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1136 %{.s:%i} %{!.s:%g.s}}}"
1139 #endif /* ASM_FINAL_SPEC */
1141 /* Redefinition of libraries used. Mips doesn't support normal
1142 UNIX style profiling via calling _mcount. It does offer
1143 profiling that samples the PC, so do what we can... */
1146 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1149 /* Extra switches sometimes passed to the linker. */
1150 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1151 will interpret it as a -b option. */
1154 #define LINK_SPEC "\
1156 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1157 %{bestGnum} %{shared} %{non_shared}"
1158 #endif /* LINK_SPEC defined */
1161 /* Specs for the compiler proper */
1163 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1164 overridden by subtargets. */
1165 #ifndef SUBTARGET_CC1_SPEC
1166 #define SUBTARGET_CC1_SPEC ""
1169 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1170 /* Note, we will need to adjust the following if we ever find a MIPS variant
1171 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1172 that show up in this case. */
1176 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1177 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1179 %(subtarget_cc1_spec)"
1182 /* Preprocessor specs. */
1184 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1185 overridden by subtargets. */
1186 #ifndef SUBTARGET_CPP_SPEC
1187 #define SUBTARGET_CPP_SPEC ""
1190 #define CPP_SPEC "%(subtarget_cpp_spec)"
1192 /* This macro defines names of additional specifications to put in the specs
1193 that can be used in various specifications like CC1_SPEC. Its definition
1194 is an initializer with a subgrouping for each command option.
1196 Each subgrouping contains a string constant, that defines the
1197 specification name, and a string constant that used by the GNU CC driver
1200 Do not define this macro if it does not need to do anything. */
1202 #define EXTRA_SPECS \
1203 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1204 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1205 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1206 { "gas_asm_spec", GAS_ASM_SPEC }, \
1207 { "target_asm_spec", TARGET_ASM_SPEC }, \
1208 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1209 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1210 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1211 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1212 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1213 { "endian_spec", ENDIAN_SPEC }, \
1214 SUBTARGET_EXTRA_SPECS
1216 #ifndef SUBTARGET_EXTRA_SPECS
1217 #define SUBTARGET_EXTRA_SPECS
1220 /* If defined, this macro is an additional prefix to try after
1221 `STANDARD_EXEC_PREFIX'. */
1223 #ifndef MD_EXEC_PREFIX
1224 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1227 #ifndef MD_STARTFILE_PREFIX
1228 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1232 /* Print subsidiary information on the compiler version in use. */
1234 #define MIPS_VERSION "[AL 1.1, MM 40]"
1236 #ifndef MACHINE_TYPE
1237 #define MACHINE_TYPE "BSD Mips"
1240 #ifndef TARGET_VERSION_INTERNAL
1241 #define TARGET_VERSION_INTERNAL(STREAM) \
1242 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1245 #ifndef TARGET_VERSION
1246 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1250 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1251 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1252 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1254 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1255 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1258 /* By default, turn on GDB extensions. */
1259 #define DEFAULT_GDB_EXTENSIONS 1
1261 /* If we are passing smuggling stabs through the MIPS ECOFF object
1262 format, put a comment in front of the .stab<x> operation so
1263 that the MIPS assembler does not choke. The mips-tfile program
1264 will correctly put the stab into the object file. */
1266 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1267 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1268 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1270 /* Local compiler-generated symbols must have a prefix that the assembler
1271 understands. By default, this is $, although some targets (e.g.,
1272 NetBSD-ELF) need to override this. */
1274 #ifndef LOCAL_LABEL_PREFIX
1275 #define LOCAL_LABEL_PREFIX "$"
1278 /* By default on the mips, external symbols do not have an underscore
1279 prepended, but some targets (e.g., NetBSD) require this. */
1281 #ifndef USER_LABEL_PREFIX
1282 #define USER_LABEL_PREFIX ""
1285 /* Forward references to tags are allowed. */
1286 #define SDB_ALLOW_FORWARD_REFERENCES
1288 /* Unknown tags are also allowed. */
1289 #define SDB_ALLOW_UNKNOWN_REFERENCES
1291 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1292 since the length can run past this up to a continuation point. */
1293 #undef DBX_CONTIN_LENGTH
1294 #define DBX_CONTIN_LENGTH 1500
1296 /* How to renumber registers for dbx and gdb. */
1297 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1299 /* The mapping from gcc register number to DWARF 2 CFA column number.
1300 This mapping does not allow for tracking register 0, since SGI's broken
1301 dwarf reader thinks column 0 is used for the frame address, but since
1302 register 0 is fixed this is not a problem. */
1303 #define DWARF_FRAME_REGNUM(REG) \
1304 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1306 /* The DWARF 2 CFA column which tracks the return address. */
1307 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1309 /* Before the prologue, RA lives in r31. */
1310 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1312 /* Describe how we implement __builtin_eh_return. */
1313 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1314 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1316 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1317 The default for this in 64-bit mode is 8, which causes problems with
1318 SFmode register saves. */
1319 #define DWARF_CIE_DATA_ALIGNMENT 4
1321 /* Overrides for the COFF debug format. */
1322 #define PUT_SDB_SCL(a) \
1324 extern FILE *asm_out_text_file; \
1325 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1328 #define PUT_SDB_INT_VAL(a) \
1330 extern FILE *asm_out_text_file; \
1331 fprintf (asm_out_text_file, "\t.val\t"); \
1332 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1333 fprintf (asm_out_text_file, ";"); \
1336 #define PUT_SDB_VAL(a) \
1338 extern FILE *asm_out_text_file; \
1339 fputs ("\t.val\t", asm_out_text_file); \
1340 output_addr_const (asm_out_text_file, (a)); \
1341 fputc (';', asm_out_text_file); \
1344 #define PUT_SDB_DEF(a) \
1346 extern FILE *asm_out_text_file; \
1347 fprintf (asm_out_text_file, "\t%s.def\t", \
1348 (TARGET_GAS) ? "" : "#"); \
1349 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1350 fputc (';', asm_out_text_file); \
1353 #define PUT_SDB_PLAIN_DEF(a) \
1355 extern FILE *asm_out_text_file; \
1356 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1357 (TARGET_GAS) ? "" : "#", (a)); \
1360 #define PUT_SDB_ENDEF \
1362 extern FILE *asm_out_text_file; \
1363 fprintf (asm_out_text_file, "\t.endef\n"); \
1366 #define PUT_SDB_TYPE(a) \
1368 extern FILE *asm_out_text_file; \
1369 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1372 #define PUT_SDB_SIZE(a) \
1374 extern FILE *asm_out_text_file; \
1375 fprintf (asm_out_text_file, "\t.size\t"); \
1376 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1377 fprintf (asm_out_text_file, ";"); \
1380 #define PUT_SDB_DIM(a) \
1382 extern FILE *asm_out_text_file; \
1383 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1386 #ifndef PUT_SDB_START_DIM
1387 #define PUT_SDB_START_DIM \
1389 extern FILE *asm_out_text_file; \
1390 fprintf (asm_out_text_file, "\t.dim\t"); \
1394 #ifndef PUT_SDB_NEXT_DIM
1395 #define PUT_SDB_NEXT_DIM(a) \
1397 extern FILE *asm_out_text_file; \
1398 fprintf (asm_out_text_file, "%d,", a); \
1402 #ifndef PUT_SDB_LAST_DIM
1403 #define PUT_SDB_LAST_DIM(a) \
1405 extern FILE *asm_out_text_file; \
1406 fprintf (asm_out_text_file, "%d;", a); \
1410 #define PUT_SDB_TAG(a) \
1412 extern FILE *asm_out_text_file; \
1413 fprintf (asm_out_text_file, "\t.tag\t"); \
1414 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1415 fputc (';', asm_out_text_file); \
1418 /* For block start and end, we create labels, so that
1419 later we can figure out where the correct offset is.
1420 The normal .ent/.end serve well enough for functions,
1421 so those are just commented out. */
1423 #define PUT_SDB_BLOCK_START(LINE) \
1425 extern FILE *asm_out_text_file; \
1426 fprintf (asm_out_text_file, \
1427 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1428 LOCAL_LABEL_PREFIX, \
1430 (TARGET_GAS) ? "" : "#", \
1431 LOCAL_LABEL_PREFIX, \
1434 sdb_label_count++; \
1437 #define PUT_SDB_BLOCK_END(LINE) \
1439 extern FILE *asm_out_text_file; \
1440 fprintf (asm_out_text_file, \
1441 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1442 LOCAL_LABEL_PREFIX, \
1444 (TARGET_GAS) ? "" : "#", \
1445 LOCAL_LABEL_PREFIX, \
1448 sdb_label_count++; \
1451 #define PUT_SDB_FUNCTION_START(LINE)
1453 #define PUT_SDB_FUNCTION_END(LINE) \
1455 extern FILE *asm_out_text_file; \
1456 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1459 #define PUT_SDB_EPILOGUE_END(NAME)
1461 #define PUT_SDB_SRC_FILE(FILENAME) \
1463 extern FILE *asm_out_text_file; \
1464 output_file_directive (asm_out_text_file, (FILENAME));\
1467 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1468 sprintf ((BUFFER), ".%dfake", (NUMBER));
1470 /* Correct the offset of automatic variables and arguments. Note that
1471 the MIPS debug format wants all automatic variables and arguments
1472 to be in terms of the virtual frame pointer (stack pointer before
1473 any adjustment in the function), while the MIPS 3.0 linker wants
1474 the frame pointer to be the stack pointer after the initial
1477 #define DEBUGGER_AUTO_OFFSET(X) \
1478 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1479 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1480 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1482 /* Tell collect that the object format is ECOFF */
1483 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1484 #define EXTENDED_COFF /* ECOFF, not normal coff */
1486 /* Target machine storage layout */
1488 /* Define this if most significant bit is lowest numbered
1489 in instructions that operate on numbered bit-fields.
1491 #define BITS_BIG_ENDIAN 0
1493 /* Define this if most significant byte of a word is the lowest numbered. */
1494 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1496 /* Define this if most significant word of a multiword number is the lowest. */
1497 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1499 /* Define this to set the endianness to use in libgcc2.c, which can
1500 not depend on target_flags. */
1501 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1502 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1504 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1507 #define MAX_BITS_PER_WORD 64
1509 /* Width of a word, in units (bytes). */
1510 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1511 #define MIN_UNITS_PER_WORD 4
1513 /* For MIPS, width of a floating point register. */
1514 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1516 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1517 the next available register. */
1518 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1520 /* The largest size of value that can be held in floating-point
1521 registers and moved with a single instruction. */
1522 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1524 /* The largest size of value that can be held in floating-point
1526 #define UNITS_PER_FPVALUE \
1527 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1529 /* The number of bytes in a double. */
1530 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1532 /* A C expression for the size in bits of the type `int' on the
1533 target machine. If you don't define this, the default is one
1535 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1537 /* Tell the preprocessor the maximum size of wchar_t. */
1538 #ifndef MAX_WCHAR_TYPE_SIZE
1539 #ifndef WCHAR_TYPE_SIZE
1540 #define MAX_WCHAR_TYPE_SIZE 64
1544 /* A C expression for the size in bits of the type `short' on the
1545 target machine. If you don't define this, the default is half a
1546 word. (If this would be less than one storage unit, it is
1547 rounded up to one unit.) */
1548 #define SHORT_TYPE_SIZE 16
1550 /* A C expression for the size in bits of the type `long' on the
1551 target machine. If you don't define this, the default is one
1553 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1554 #define MAX_LONG_TYPE_SIZE 64
1556 /* A C expression for the size in bits of the type `long long' on the
1557 target machine. If you don't define this, the default is two
1559 #define LONG_LONG_TYPE_SIZE 64
1561 /* A C expression for the size in bits of the type `float' on the
1562 target machine. If you don't define this, the default is one
1564 #define FLOAT_TYPE_SIZE 32
1566 /* A C expression for the size in bits of the type `double' on the
1567 target machine. If you don't define this, the default is two
1569 #define DOUBLE_TYPE_SIZE 64
1571 /* A C expression for the size in bits of the type `long double' on
1572 the target machine. If you don't define this, the default is two
1574 #define LONG_DOUBLE_TYPE_SIZE \
1575 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1577 /* long double is not a fixed mode, but the idea is that, if we
1578 support long double, we also want a 128-bit integer type. */
1579 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1582 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1583 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1584 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1586 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1590 /* Width in bits of a pointer.
1591 See also the macro `Pmode' defined below. */
1592 #ifndef POINTER_SIZE
1593 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1596 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1597 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1599 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1600 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1601 || mips_abi == ABI_64 \
1602 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1604 /* Allocation boundary (in *bits*) for the code of a function. */
1605 #define FUNCTION_BOUNDARY 32
1607 /* Alignment of field after `int : 0' in a structure. */
1608 #define EMPTY_FIELD_BOUNDARY 32
1610 /* Every structure's size must be a multiple of this. */
1611 /* 8 is observed right on a DECstation and on riscos 4.02. */
1612 #define STRUCTURE_SIZE_BOUNDARY 8
1614 /* There is no point aligning anything to a rounder boundary than this. */
1615 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1617 /* Set this nonzero if move instructions will actually fail to work
1618 when given unaligned data. */
1619 #define STRICT_ALIGNMENT 1
1621 /* Define this if you wish to imitate the way many other C compilers
1622 handle alignment of bitfields and the structures that contain
1625 The behavior is that the type written for a bit-field (`int',
1626 `short', or other integer type) imposes an alignment for the
1627 entire structure, as if the structure really did contain an
1628 ordinary field of that type. In addition, the bit-field is placed
1629 within the structure so that it would fit within such a field,
1630 not crossing a boundary for it.
1632 Thus, on most machines, a bit-field whose type is written as `int'
1633 would not cross a four-byte boundary, and would force four-byte
1634 alignment for the whole structure. (The alignment used may not
1635 be four bytes; it is controlled by the other alignment
1638 If the macro is defined, its definition should be a C expression;
1639 a nonzero value for the expression enables this behavior. */
1641 #define PCC_BITFIELD_TYPE_MATTERS 1
1643 /* If defined, a C expression to compute the alignment given to a
1644 constant that is being placed in memory. CONSTANT is the constant
1645 and ALIGN is the alignment that the object would ordinarily have.
1646 The value of this macro is used instead of that alignment to align
1649 If this macro is not defined, then ALIGN is used.
1651 The typical use of this macro is to increase alignment for string
1652 constants to be word aligned so that `strcpy' calls that copy
1653 constants can be done inline. */
1655 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1656 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1657 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1659 /* If defined, a C expression to compute the alignment for a static
1660 variable. TYPE is the data type, and ALIGN is the alignment that
1661 the object would ordinarily have. The value of this macro is used
1662 instead of that alignment to align the object.
1664 If this macro is not defined, then ALIGN is used.
1666 One use of this macro is to increase alignment of medium-size
1667 data to make it all fit in fewer cache lines. Another is to
1668 cause character arrays to be word-aligned so that `strcpy' calls
1669 that copy constants to character arrays can be done inline. */
1671 #undef DATA_ALIGNMENT
1672 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1673 ((((ALIGN) < BITS_PER_WORD) \
1674 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1675 || TREE_CODE (TYPE) == UNION_TYPE \
1676 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1679 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1681 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1682 || mips_abi == ABI_MEABI \
1683 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1685 /* Define this macro if an argument declared as `char' or `short' in a
1686 prototype should actually be passed as an `int'. In addition to
1687 avoiding errors in certain cases of mismatch, it also makes for
1688 better code on certain machines. */
1690 #define PROMOTE_PROTOTYPES 1
1692 /* Define if operations between registers always perform the operation
1693 on the full register even if a narrower mode is specified. */
1694 #define WORD_REGISTER_OPERATIONS
1696 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1697 will either zero-extend or sign-extend. The value of this macro should
1698 be the code that says which one of the two operations is implicitly
1701 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1702 moves. All other referces are zero extended. */
1703 #define LOAD_EXTEND_OP(MODE) \
1704 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1705 ? SIGN_EXTEND : ZERO_EXTEND)
1707 /* Define this macro if it is advisable to hold scalars in registers
1708 in a wider mode than that declared by the program. In such cases,
1709 the value is constrained to be within the bounds of the declared
1710 type, but kept valid in the wider mode. The signedness of the
1711 extension may differ from that of the type.
1713 We promote any value smaller than SImode up to SImode. We don't
1714 want to promote to DImode when in 64 bit mode, because that would
1715 prevent us from using the faster SImode multiply and divide
1718 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1719 if (GET_MODE_CLASS (MODE) == MODE_INT \
1720 && GET_MODE_SIZE (MODE) < 4) \
1723 /* Define this if function arguments should also be promoted using the above
1726 #define PROMOTE_FUNCTION_ARGS
1728 /* Likewise, if the function return value is promoted. */
1730 #define PROMOTE_FUNCTION_RETURN
1732 /* Standard register usage. */
1734 /* Number of actual hardware registers.
1735 The hardware registers are assigned numbers for the compiler
1736 from 0 to just below FIRST_PSEUDO_REGISTER.
1737 All registers that the compiler knows about must be given numbers,
1738 even those that are not normally considered general registers.
1740 On the Mips, we have 32 integer registers, 32 floating point
1741 registers, 8 condition code registers, and the special registers
1742 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1743 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1744 processor.) The 8 condition code registers are only used if
1745 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1746 represents a 64 bit value stored as two 32 bit values in the hi and
1747 lo registers; this is the result of the mult instruction. rap is a
1748 pointer to the stack where the return address reg ($31) was stored.
1749 This is needed for C++ exception handling. */
1751 #define FIRST_PSEUDO_REGISTER 176
1753 /* 1 for registers that have pervasive standard uses
1754 and are not available for the register allocator.
1756 On the MIPS, see conventions, page D-2 */
1758 /* Regarding coprocessor registers: without evidence to the contrary,
1759 it's best to assume that each coprocessor register has a unique
1760 use. This can be overridden, in, e.g., override_options() or
1761 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1762 for a particular target. */
1764 #define FIXED_REGISTERS \
1766 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1767 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1769 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1770 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
1771 /* COP0 registers */ \
1772 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1773 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1774 /* COP2 registers */ \
1775 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1776 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1777 /* COP3 registers */ \
1778 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1779 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1783 /* 1 for registers not available across function calls.
1784 These must include the FIXED_REGISTERS and also any
1785 registers that can be used without being saved.
1786 The latter must include the registers where values are returned
1787 and the register where structure-value addresses are passed.
1788 Aside from that, you can include as many other registers as you like. */
1790 #define CALL_USED_REGISTERS \
1792 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1793 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1794 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1795 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1796 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1797 /* COP0 registers */ \
1798 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1799 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1800 /* COP2 registers */ \
1801 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1802 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1803 /* COP3 registers */ \
1804 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1805 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1808 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1809 problem which makes CALL_USED_REGISTERS *always* include
1810 all the FIXED_REGISTERS. Until this problem has been
1811 resolved this macro can be used to overcome this situation.
1812 In particular, block_propagate() requires this list
1813 be acurate, or we can remove registers which should be live.
1814 This macro is used in regs_invalidated_by_call. */
1817 #define CALL_REALLY_USED_REGISTERS \
1818 { /* General registers. */ \
1819 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1820 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1821 /* Floating-point registers. */ \
1822 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1823 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1825 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1826 /* COP0 registers */ \
1827 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1828 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1829 /* COP2 registers */ \
1830 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1831 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1832 /* COP3 registers */ \
1833 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1834 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1837 /* Internal macros to classify a register number as to whether it's a
1838 general purpose register, a floating point register, a
1839 multiply/divide register, or a status register. */
1841 #define GP_REG_FIRST 0
1842 #define GP_REG_LAST 31
1843 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1844 #define GP_DBX_FIRST 0
1846 #define FP_REG_FIRST 32
1847 #define FP_REG_LAST 63
1848 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1849 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1851 #define MD_REG_FIRST 64
1852 #define MD_REG_LAST 66
1853 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1855 #define ST_REG_FIRST 67
1856 #define ST_REG_LAST 74
1857 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1859 #define RAP_REG_NUM 75
1861 #define COP0_REG_FIRST 80
1862 #define COP0_REG_LAST 111
1863 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1865 #define COP2_REG_FIRST 112
1866 #define COP2_REG_LAST 143
1867 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1869 #define COP3_REG_FIRST 144
1870 #define COP3_REG_LAST 175
1871 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1872 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1873 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1875 #define AT_REGNUM (GP_REG_FIRST + 1)
1876 #define HI_REGNUM (MD_REG_FIRST + 0)
1877 #define LO_REGNUM (MD_REG_FIRST + 1)
1878 #define HILO_REGNUM (MD_REG_FIRST + 2)
1880 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1881 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1882 should be used instead. */
1883 #define FPSW_REGNUM ST_REG_FIRST
1885 #define GP_REG_P(REGNO) \
1886 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1887 #define M16_REG_P(REGNO) \
1888 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1889 #define FP_REG_P(REGNO) \
1890 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1891 #define MD_REG_P(REGNO) \
1892 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1893 #define ST_REG_P(REGNO) \
1894 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1895 #define COP0_REG_P(REGNO) \
1896 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1897 #define COP2_REG_P(REGNO) \
1898 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1899 #define COP3_REG_P(REGNO) \
1900 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1901 #define ALL_COP_REG_P(REGNO) \
1902 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1904 /* Return coprocessor number from register number. */
1906 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1907 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1908 : COP3_REG_P (REGNO) ? '3' : '?')
1910 /* Return number of consecutive hard regs needed starting at reg REGNO
1911 to hold something of mode MODE.
1912 This is ordinarily the length in words of a value of mode MODE
1913 but can be less for certain modes in special long registers.
1915 On the MIPS, all general registers are one word long. Except on
1916 the R4000 with the FR bit set, the floating point uses register
1917 pairs, with the second register not being allocable. */
1919 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1921 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1922 MODE. In 32 bit mode, require that DImode and DFmode be in even
1923 registers. For DImode, this makes some of the insns easier to
1924 write, since you don't have to worry about a DImode value in
1925 registers 3 & 4, producing a result in 4 & 5.
1927 To make the code simpler HARD_REGNO_MODE_OK now just references an
1928 array built in override_options. Because machmodes.h is not yet
1929 included before this file is processed, the MODE bound can't be
1932 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1934 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1935 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1937 /* Value is 1 if it is a good idea to tie two pseudo registers
1938 when one has mode MODE1 and one has mode MODE2.
1939 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1940 for any hard reg, then this must be 0 for correct output. */
1941 #define MODES_TIEABLE_P(MODE1, MODE2) \
1942 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1943 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1944 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1945 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1947 /* MIPS pc is not overloaded on a register. */
1948 /* #define PC_REGNUM xx */
1950 /* Register to use for pushing function arguments. */
1951 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1953 /* Offset from the stack pointer to the first available location. Use
1954 the default value zero. */
1955 /* #define STACK_POINTER_OFFSET 0 */
1957 /* Base register for access to local variables of the function. We
1958 pretend that the frame pointer is $1, and then eliminate it to
1959 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1960 a fixed register, and will not be used for anything else. */
1961 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1963 /* Temporary scratch register for use by the assembler. */
1964 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1966 /* $30 is not available on the mips16, so we use $17 as the frame
1968 #define HARD_FRAME_POINTER_REGNUM \
1969 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1971 /* Value should be nonzero if functions must have frame pointers.
1972 Zero means the frame pointer need not be set up (and parms
1973 may be accessed via the stack pointer) in functions that seem suitable.
1974 This is computed in `reload', in reload1.c. */
1975 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1977 /* Base register for access to arguments of the function. */
1978 #define ARG_POINTER_REGNUM GP_REG_FIRST
1980 /* Fake register that holds the address on the stack of the
1981 current function's return address. */
1982 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1984 /* Register in which static-chain is passed to a function. */
1985 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1987 /* If the structure value address is passed in a register, then
1988 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1989 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1991 /* If the structure value address is not passed in a register, define
1992 `STRUCT_VALUE' as an expression returning an RTX for the place
1993 where the address is passed. If it returns 0, the address is
1994 passed as an "invisible" first argument. */
1995 #define STRUCT_VALUE 0
1997 /* Mips registers used in prologue/epilogue code when the stack frame
1998 is larger than 32K bytes. These registers must come from the
1999 scratch register set, and not used for passing and returning
2000 arguments and any other information used in the calling sequence
2001 (such as pic). Must start at 12, since t0/t3 are parameter passing
2002 registers in the 64 bit ABI. */
2004 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
2005 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
2007 /* Define this macro if it is as good or better to call a constant
2008 function address than to call an address kept in a register. */
2009 #define NO_FUNCTION_CSE 1
2011 /* Define this macro if it is as good or better for a function to
2012 call itself with an explicit address than to call an address
2013 kept in a register. */
2014 #define NO_RECURSIVE_FUNCTION_CSE 1
2016 /* The register number of the register used to address a table of
2017 static data addresses in memory. In some cases this register is
2018 defined by a processor's "application binary interface" (ABI).
2019 When this macro is defined, RTL is generated for this register
2020 once, as with the stack pointer and frame pointer registers. If
2021 this macro is not defined, it is up to the machine-dependent
2022 files to allocate such a register (if necessary). */
2023 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
2025 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
2027 /* Define the classes of registers for register constraints in the
2028 machine description. Also define ranges of constants.
2030 One of the classes must always be named ALL_REGS and include all hard regs.
2031 If there is more than one class, another class must be named NO_REGS
2032 and contain no registers.
2034 The name GENERAL_REGS must be the name of a class (or an alias for
2035 another name such as ALL_REGS). This is the class of registers
2036 that is allowed by "g" or "r" in a register constraint.
2037 Also, registers outside this class are allocated only when
2038 instructions express preferences for them.
2040 The classes must be numbered in nondecreasing order; that is,
2041 a larger-numbered class must never be contained completely
2042 in a smaller-numbered class.
2044 For any two classes, it is very desirable that there be another
2045 class that represents their union. */
2049 NO_REGS, /* no registers in set */
2050 M16_NA_REGS, /* mips16 regs not used to pass args */
2051 M16_REGS, /* mips16 directly accessible registers */
2052 T_REG, /* mips16 T register ($24) */
2053 M16_T_REGS, /* mips16 registers plus T register */
2054 GR_REGS, /* integer registers */
2055 FP_REGS, /* floating point registers */
2056 HI_REG, /* hi register */
2057 LO_REG, /* lo register */
2058 HILO_REG, /* hilo register pair for 64 bit mode mult */
2059 MD_REGS, /* multiply/divide registers (hi/lo) */
2060 COP0_REGS, /* generic coprocessor classes */
2063 HI_AND_GR_REGS, /* union classes */
2071 ALL_COP_AND_GR_REGS,
2072 ST_REGS, /* status registers (fp status) */
2073 ALL_REGS, /* all registers */
2074 LIM_REG_CLASSES /* max value + 1 */
2077 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2079 #define GENERAL_REGS GR_REGS
2081 /* An initializer containing the names of the register classes as C
2082 string constants. These names are used in writing some of the
2085 #define REG_CLASS_NAMES \
2098 /* coprocessor registers */ \
2104 "HILO_AND_GR_REGS", \
2106 "COP0_AND_GR_REGS", \
2107 "COP2_AND_GR_REGS", \
2108 "COP3_AND_GR_REGS", \
2110 "ALL_COP_AND_GR_REGS", \
2115 /* An initializer containing the contents of the register classes,
2116 as integers which are bit masks. The Nth integer specifies the
2117 contents of class N. The way the integer MASK is interpreted is
2118 that register R is in the class if `MASK & (1 << R)' is 1.
2120 When the machine has more than 32 registers, an integer does not
2121 suffice. Then the integers are replaced by sub-initializers,
2122 braced groupings containing several integers. Each
2123 sub-initializer must be suitable as an initializer for the type
2124 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2126 #define REG_CLASS_CONTENTS \
2128 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2129 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2130 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2131 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2132 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2133 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2134 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2135 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2136 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2137 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2138 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2139 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2140 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2141 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2142 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2143 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2144 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2145 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2146 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2147 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2148 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2149 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2150 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2151 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2152 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2156 /* A C expression whose value is a register class containing hard
2157 register REGNO. In general there is more that one such class;
2158 choose a class which is "minimal", meaning that no smaller class
2159 also contains the register. */
2161 extern const enum reg_class mips_regno_to_class[];
2163 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2165 /* A macro whose definition is the name of the class to which a
2166 valid base register must belong. A base register is one used in
2167 an address which is the register value plus a displacement. */
2169 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2171 /* A macro whose definition is the name of the class to which a
2172 valid index register must belong. An index register is one used
2173 in an address where its value is either multiplied by a scale
2174 factor or added to another register (as well as added to a
2177 #define INDEX_REG_CLASS NO_REGS
2179 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2180 registers explicitly used in the rtl to be used as spill registers
2181 but prevents the compiler from extending the lifetime of these
2184 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2186 /* This macro is used later on in the file. */
2187 #define GR_REG_CLASS_P(CLASS) \
2188 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2189 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2191 /* This macro is also used later on in the file. */
2192 #define COP_REG_CLASS_P(CLASS) \
2193 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2195 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2196 is the default value (allocate the registers in numeric order). We
2197 define it just so that we can override it for the mips16 target in
2198 ORDER_REGS_FOR_LOCAL_ALLOC. */
2200 #define REG_ALLOC_ORDER \
2201 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2202 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2203 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2204 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2205 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2206 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2207 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2208 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2209 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2210 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2211 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2214 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2215 to be rearranged based on a particular function. On the mips16, we
2216 want to allocate $24 (T_REG) before other registers for
2217 instructions for which it is possible. */
2219 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2221 /* REGISTER AND CONSTANT CLASSES */
2223 /* Get reg_class from a letter such as appears in the machine
2226 DEFINED REGISTER CLASSES:
2228 'd' General (aka integer) registers
2229 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2230 'y' General registers (in both mips16 and non mips16 mode)
2231 'e' mips16 non argument registers (M16_NA_REGS)
2232 't' mips16 temporary register ($24)
2233 'f' Floating point registers
2236 'x' Multiply/divide registers
2238 'z' FP Status register
2242 'b' All registers */
2244 extern enum reg_class mips_char_to_class[256];
2246 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2248 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2249 string can be used to stand for particular ranges of immediate
2250 operands. This macro defines what the ranges are. C is the
2251 letter, and VALUE is a constant value. Return 1 if VALUE is
2252 in the range specified by C. */
2256 `I' is used for the range of constants an arithmetic insn can
2257 actually contain (16 bits signed integers).
2259 `J' is used for the range which is just zero (ie, $r0).
2261 `K' is used for the range of constants a logical insn can actually
2262 contain (16 bit zero-extended integers).
2264 `L' is used for the range of constants that be loaded with lui
2265 (ie, the bottom 16 bits are zero).
2267 `M' is used for the range of constants that take two words to load
2268 (ie, not matched by `I', `K', and `L').
2270 `N' is used for negative 16 bit constants other than -65536.
2272 `O' is a 15 bit signed integer.
2274 `P' is used for positive 16 bit constants. */
2276 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2277 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2279 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2280 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2281 : (C) == 'J' ? ((VALUE) == 0) \
2282 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2283 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2284 && (((VALUE) & ~2147483647) == 0 \
2285 || ((VALUE) & ~2147483647) == ~2147483647)) \
2286 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2287 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2288 && (((VALUE) & 0x0000ffff) != 0 \
2289 || (((VALUE) & ~2147483647) != 0 \
2290 && ((VALUE) & ~2147483647) != ~2147483647))) \
2291 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2292 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2293 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2296 /* Similar, but for floating constants, and defining letters G and H.
2297 Here VALUE is the CONST_DOUBLE rtx itself. */
2301 'G' : Floating point 0 */
2303 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2305 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2307 /* Letters in the range `Q' through `U' may be defined in a
2308 machine-dependent fashion to stand for arbitrary operand types.
2309 The machine description macro `EXTRA_CONSTRAINT' is passed the
2310 operand as its first argument and the constraint letter as its
2313 `Q' is for mips16 GP relative constants
2314 `R' is for memory references which take 1 word for the instruction.
2315 `T' is for memory addresses that can be used to load two words. */
2317 #define EXTRA_CONSTRAINT(OP,CODE) \
2318 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2319 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2320 && mips16_gp_offset_p (OP)) \
2321 : (GET_CODE (OP) != MEM) ? FALSE \
2322 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2325 /* Given an rtx X being reloaded into a reg required to be
2326 in class CLASS, return the class of reg to actually use.
2327 In general this is just CLASS; but on some machines
2328 in some cases it is preferable to use a more restrictive class. */
2330 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2331 ((CLASS) != ALL_REGS \
2332 ? (! TARGET_MIPS16 \
2334 : ((CLASS) != GR_REGS \
2337 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2338 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2339 ? (TARGET_SOFT_FLOAT \
2340 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2342 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2343 || GET_MODE (X) == VOIDmode) \
2344 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2347 /* Certain machines have the property that some registers cannot be
2348 copied to some other registers without using memory. Define this
2349 macro on those machines to be a C expression that is nonzero if
2350 objects of mode MODE in registers of CLASS1 can only be copied to
2351 registers of class CLASS2 by storing a register of CLASS1 into
2352 memory and loading that memory location into a register of CLASS2.
2354 Do not define this macro if its value would always be zero. */
2356 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2357 ((!TARGET_DEBUG_H_MODE \
2358 && GET_MODE_CLASS (MODE) == MODE_INT \
2359 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2360 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2361 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2362 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2363 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2365 /* The HI and LO registers can only be reloaded via the general
2366 registers. Condition code registers can only be loaded to the
2367 general registers, and from the floating point registers. */
2369 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2370 mips_secondary_reload_class (CLASS, MODE, X, 1)
2371 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2372 mips_secondary_reload_class (CLASS, MODE, X, 0)
2374 /* Return the maximum number of consecutive registers
2375 needed to represent mode MODE in a register of class CLASS. */
2377 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2379 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \
2380 mips_cannot_change_mode_class (FROM, TO)
2382 /* Stack layout; function entry, exit and calling. */
2384 /* Define this if pushing a word on the stack
2385 makes the stack pointer a smaller address. */
2386 #define STACK_GROWS_DOWNWARD
2388 /* Define this if the nominal address of the stack frame
2389 is at the high-address end of the local variables;
2390 that is, each additional local variable allocated
2391 goes at a more negative offset in the frame. */
2392 /* #define FRAME_GROWS_DOWNWARD */
2394 /* Offset within stack frame to start allocating local variables at.
2395 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2396 first local allocated. Otherwise, it is the offset to the BEGINNING
2397 of the first local allocated. */
2398 #define STARTING_FRAME_OFFSET \
2399 (current_function_outgoing_args_size \
2400 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2402 /* Offset from the stack pointer register to an item dynamically
2403 allocated on the stack, e.g., by `alloca'.
2405 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2406 length of the outgoing arguments. The default is correct for most
2407 machines. See `function.c' for details.
2409 The MIPS ABI states that functions which dynamically allocate the
2410 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2411 we are trying to create a second frame pointer to the function, so
2412 allocate some stack space to make it happy.
2414 However, the linker currently complains about linking any code that
2415 dynamically allocates stack space, and there seems to be a bug in
2416 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2419 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2420 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2421 ? 4*UNITS_PER_WORD \
2422 : current_function_outgoing_args_size)
2425 /* The return address for the current frame is in r31 if this is a leaf
2426 function. Otherwise, it is on the stack. It is at a variable offset
2427 from sp/fp/ap, so we define a fake hard register rap which is a
2428 poiner to the return address on the stack. This always gets eliminated
2429 during reload to be either the frame pointer or the stack pointer plus
2432 /* ??? This definition fails for leaf functions. There is currently no
2433 general solution for this problem. */
2435 /* ??? There appears to be no way to get the return address of any previous
2436 frame except by disassembling instructions in the prologue/epilogue.
2437 So currently we support only the current frame. */
2439 #define RETURN_ADDR_RTX(count, frame) \
2441 ? (leaf_function_p () \
2442 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
2443 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
2444 RETURN_ADDRESS_POINTER_REGNUM))) \
2447 /* Since the mips16 ISA mode is encoded in the least-significant bit
2448 of the address, mask it off return addresses for purposes of
2449 finding exception handling regions. */
2451 #define MASK_RETURN_ADDR GEN_INT (-2)
2453 /* Similarly, don't use the least-significant bit to tell pointers to
2454 code from vtable index. */
2456 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2458 /* If defined, this macro specifies a table of register pairs used to
2459 eliminate unneeded registers that point into the stack frame. If
2460 it is not defined, the only elimination attempted by the compiler
2461 is to replace references to the frame pointer with references to
2464 The definition of this macro is a list of structure
2465 initializations, each of which specifies an original and
2466 replacement register.
2468 On some machines, the position of the argument pointer is not
2469 known until the compilation is completed. In such a case, a
2470 separate hard register must be used for the argument pointer.
2471 This register can be eliminated by replacing it with either the
2472 frame pointer or the argument pointer, depending on whether or not
2473 the frame pointer has been eliminated.
2475 In this case, you might specify:
2476 #define ELIMINABLE_REGS \
2477 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2478 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2479 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2481 Note that the elimination of the argument pointer with the stack
2482 pointer is specified first since that is the preferred elimination.
2484 The eliminations to $17 are only used on the mips16. See the
2485 definition of HARD_FRAME_POINTER_REGNUM. */
2487 #define ELIMINABLE_REGS \
2488 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2489 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2490 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2491 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2492 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2493 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2494 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2495 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2496 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2498 /* A C expression that returns nonzero if the compiler is allowed to
2499 try to replace register number FROM-REG with register number
2500 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2501 defined, and will usually be the constant 1, since most of the
2502 cases preventing register elimination are things that the compiler
2503 already knows about.
2505 When not in mips16 and mips64, we can always eliminate to the
2506 frame pointer. We can eliminate to the stack pointer unless
2507 a frame pointer is needed. In mips16 mode, we need a frame
2508 pointer for a large frame; otherwise, reload may be unable
2509 to compute the address of a local variable, since there is
2510 no way to add a large constant to the stack pointer
2511 without using a temporary register.
2513 In mips16, for some instructions (eg lwu), we can't eliminate the
2514 frame pointer for the stack pointer. These instructions are
2515 only generated in TARGET_64BIT mode.
2518 #define CAN_ELIMINATE(FROM, TO) \
2519 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
2520 && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
2521 || (TO) == HARD_FRAME_POINTER_REGNUM)) \
2522 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2523 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2524 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2525 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2526 && (! TARGET_MIPS16 \
2527 || compute_frame_size (get_frame_size ()) < 32768)))))
2529 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2530 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2532 /* If we generate an insn to push BYTES bytes,
2533 this says how many the stack pointer really advances by.
2534 On the VAX, sp@- in a byte insn really pushes a word. */
2536 /* #define PUSH_ROUNDING(BYTES) 0 */
2538 /* If defined, the maximum amount of space required for outgoing
2539 arguments will be computed and placed into the variable
2540 `current_function_outgoing_args_size'. No space will be pushed
2541 onto the stack for each call; instead, the function prologue
2542 should increase the stack frame size by this amount.
2544 It is not proper to define both `PUSH_ROUNDING' and
2545 `ACCUMULATE_OUTGOING_ARGS'. */
2546 #define ACCUMULATE_OUTGOING_ARGS 1
2548 /* Offset from the argument pointer register to the first argument's
2549 address. On some machines it may depend on the data type of the
2552 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2553 the first argument's address.
2555 On the MIPS, we must skip the first argument position if we are
2556 returning a structure or a union, to account for its address being
2557 passed in $4. However, at the current time, this produces a compiler
2558 that can't bootstrap, so comment it out for now. */
2561 #define FIRST_PARM_OFFSET(FNDECL) \
2563 && TREE_TYPE (FNDECL) != 0 \
2564 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2565 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2566 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2570 #define FIRST_PARM_OFFSET(FNDECL) 0
2573 /* When a parameter is passed in a register, stack space is still
2574 allocated for it. For the MIPS, stack space must be allocated, cf
2575 Asm Lang Prog Guide page 7-8.
2577 BEWARE that some space is also allocated for non existing arguments
2578 in register. In case an argument list is of form GF used registers
2579 are a0 (a2,a3), but we should push over a1... */
2581 #define REG_PARM_STACK_SPACE(FNDECL) \
2582 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2583 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2586 /* Define this if it is the responsibility of the caller to
2587 allocate the area reserved for arguments passed in registers.
2588 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2589 of this macro is to determine whether the space is included in
2590 `current_function_outgoing_args_size'. */
2591 #define OUTGOING_REG_PARM_STACK_SPACE
2593 #define STACK_BOUNDARY \
2594 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2597 /* Make sure 4 words are always allocated on the stack. */
2599 #ifndef STACK_ARGS_ADJUST
2600 #define STACK_ARGS_ADJUST(SIZE) \
2602 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2603 SIZE.constant = 4 * UNITS_PER_WORD; \
2608 /* A C expression that should indicate the number of bytes of its
2609 own arguments that a function pops on returning, or 0
2610 if the function pops no arguments and the caller must therefore
2611 pop them all after the function returns.
2613 FUNDECL is the declaration node of the function (as a tree).
2615 FUNTYPE is a C variable whose value is a tree node that
2616 describes the function in question. Normally it is a node of
2617 type `FUNCTION_TYPE' that describes the data type of the function.
2618 From this it is possible to obtain the data types of the value
2619 and arguments (if known).
2621 When a call to a library function is being considered, FUNTYPE
2622 will contain an identifier node for the library function. Thus,
2623 if you need to distinguish among various library functions, you
2624 can do so by their names. Note that "library function" in this
2625 context means a function used to perform arithmetic, whose name
2626 is known specially in the compiler and was not mentioned in the
2627 C code being compiled.
2629 STACK-SIZE is the number of bytes of arguments passed on the
2630 stack. If a variable number of bytes is passed, it is zero, and
2631 argument popping will always be the responsibility of the
2632 calling function. */
2634 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2637 /* Symbolic macros for the registers used to return integer and floating
2640 #define GP_RETURN (GP_REG_FIRST + 2)
2641 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2643 #define MAX_ARGS_IN_REGISTERS \
2644 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2646 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2648 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2650 /* Symbolic macros for the first/last argument registers. */
2652 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2653 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2654 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2655 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2657 /* Define how to find the value returned by a library function
2658 assuming the value has mode MODE. Because we define
2659 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2660 PROMOTE_MODE does. */
2662 #define LIBCALL_VALUE(MODE) \
2663 mips_function_value (NULL_TREE, NULL, (MODE))
2665 /* Define how to find the value returned by a function.
2666 VALTYPE is the data type of the value (as a tree).
2667 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2668 otherwise, FUNC is 0. */
2670 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2671 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2673 /* 1 if N is a possible register number for a function value.
2674 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2675 Currently, R2 and F0 are only implemented here (C has no complex type) */
2677 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2678 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2679 && (N) == FP_RETURN + 2))
2681 /* 1 if N is a possible register number for function argument passing.
2682 We have no FP argument registers when soft-float. When FP registers
2683 are 32 bits, we can't directly reference the odd numbered ones. */
2685 #define FUNCTION_ARG_REGNO_P(N) \
2686 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2687 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2688 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2691 /* A C expression which can inhibit the returning of certain function
2692 values in registers, based on the type of value. A nonzero value says
2693 to return the function value in memory, just as large structures are
2694 always returned. Here TYPE will be a C expression of type
2695 `tree', representing the data type of the value.
2697 Note that values of mode `BLKmode' must be explicitly
2698 handled by this macro. Also, the option `-fpcc-struct-return'
2699 takes effect regardless of this macro. On most systems, it is
2700 possible to leave the macro undefined; this causes a default
2701 definition to be used, whose value is the constant 1 for BLKmode
2702 values, and 0 otherwise.
2704 GCC normally converts 1 byte structures into chars, 2 byte
2705 structs into shorts, and 4 byte structs into ints, and returns
2706 them this way. Defining the following macro overrides this,
2707 to give us MIPS cc compatibility. */
2709 #define RETURN_IN_MEMORY(TYPE) \
2710 mips_return_in_memory (TYPE)
2712 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2713 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2716 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2718 /* Define a data type for recording info about an argument list
2719 during the scan of that argument list. This data type should
2720 hold all necessary information about the function itself
2721 and about the args processed so far, enough to enable macros
2722 such as FUNCTION_ARG to determine where the next arg should go.
2724 This structure has to cope with two different argument allocation
2725 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2726 first N words go in registers and the rest go on the stack. If I < N,
2727 the Ith word might go in Ith integer argument register or the
2728 Ith floating-point one. In some cases, it has to go in both (see
2729 function_arg). For these ABIs, we only need to remember the number
2730 of words passed so far.
2732 The EABI instead allocates the integer and floating-point arguments
2733 separately. The first N words of FP arguments go in FP registers,
2734 the rest go on the stack. Likewise, the first N words of the other
2735 arguments go in integer registers, and the rest go on the stack. We
2736 need to maintain three counts: the number of integer registers used,
2737 the number of floating-point registers used, and the number of words
2738 passed on the stack.
2740 We could keep separate information for the two ABIs (a word count for
2741 the standard ABIs, and three separate counts for the EABI). But it
2742 seems simpler to view the standard ABIs as forms of EABI that do not
2743 allocate floating-point registers.
2745 So for the standard ABIs, the first N words are allocated to integer
2746 registers, and function_arg decides on an argument-by-argument basis
2747 whether that argument should really go in an integer register, or in
2748 a floating-point one. */
2750 typedef struct mips_args {
2751 /* Always true for varargs functions. Otherwise true if at least
2752 one argument has been passed in an integer register. */
2755 /* The number of arguments seen so far. */
2756 unsigned int arg_number;
2758 /* For EABI, the number of integer registers used so far. For other
2759 ABIs, the number of words passed in registers (whether integer
2760 or floating-point). */
2761 unsigned int num_gprs;
2763 /* For EABI, the number of floating-point registers used so far. */
2764 unsigned int num_fprs;
2766 /* The number of words passed on the stack. */
2767 unsigned int stack_words;
2769 /* On the mips16, we need to keep track of which floating point
2770 arguments were passed in general registers, but would have been
2771 passed in the FP regs if this were a 32 bit function, so that we
2772 can move them to the FP regs if we wind up calling a 32 bit
2773 function. We record this information in fp_code, encoded in base
2774 four. A zero digit means no floating point argument, a one digit
2775 means an SFmode argument, and a two digit means a DFmode argument,
2776 and a three digit is not used. The low order digit is the first
2777 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2778 an SFmode argument. ??? A more sophisticated approach will be
2779 needed if MIPS_ABI != ABI_32. */
2782 /* True if the function has a prototype. */
2785 /* When a structure does not take up a full register, the argument
2786 should sometimes be shifted left so that it occupies the high part
2787 of the register. These two fields describe an array of ashl
2788 patterns for doing this. See function_arg_advance, which creates
2789 the shift patterns, and function_arg, which returns them when given
2790 a VOIDmode argument. */
2791 unsigned int num_adjusts;
2792 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2795 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2796 for a call to a function whose data type is FNTYPE.
2797 For a library call, FNTYPE is 0.
2801 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2802 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2804 /* Update the data in CUM to advance over an argument
2805 of mode MODE and data type TYPE.
2806 (TYPE is null for libcalls where that information may not be available.) */
2808 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2809 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2811 /* Determine where to put an argument to a function.
2812 Value is zero to push the argument on the stack,
2813 or a hard register in which to store the argument.
2815 MODE is the argument's machine mode.
2816 TYPE is the data type of the argument (as a tree).
2817 This is null for libcalls where that information may
2819 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2820 the preceding args and about the function being called.
2821 NAMED is nonzero if this argument is a named parameter
2822 (otherwise it is an extra parameter matching an ellipsis). */
2824 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2825 function_arg( &CUM, MODE, TYPE, NAMED)
2827 /* For an arg passed partly in registers and partly in memory,
2828 this is the number of registers used.
2829 For args passed entirely in registers or entirely in memory, zero. */
2831 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2832 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2834 /* If defined, a C expression that gives the alignment boundary, in
2835 bits, of an argument with the specified mode and type. If it is
2836 not defined, `PARM_BOUNDARY' is used for all arguments. */
2838 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2840 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2842 : TYPE_ALIGN(TYPE)) \
2843 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2845 : GET_MODE_ALIGNMENT(MODE)))
2847 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2848 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2850 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2851 (! BYTES_BIG_ENDIAN \
2853 : (((MODE) == BLKmode \
2854 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2855 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2856 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2857 && (mips_abi == ABI_32 \
2858 || mips_abi == ABI_O64 \
2859 || mips_abi == ABI_EABI \
2860 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2861 ? downward : upward))
2863 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2864 (mips_abi == ABI_EABI && (NAMED) \
2865 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2867 /* Modified version of the macro in expr.h. */
2868 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2870 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2871 || TREE_ADDRESSABLE (TYPE) \
2872 || ((MODE) == BLKmode \
2873 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2874 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2875 && 0 == (int_size_in_bytes (TYPE) \
2876 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2877 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2878 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2880 /* True if using EABI and varargs can be passed in floating-point
2881 registers. Under these conditions, we need a more complex form
2882 of va_list, which tracks GPR, FPR and stack arguments separately. */
2883 #define EABI_FLOAT_VARARGS_P \
2884 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2887 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2889 #define MUST_SAVE_REGISTER(regno) \
2890 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2891 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2892 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2894 /* Treat LOC as a byte offset from the stack pointer and round it up
2895 to the next fully-aligned offset. */
2896 #define MIPS_STACK_ALIGN(LOC) \
2897 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2898 ? ((LOC) + 7) & ~7 \
2899 : ((LOC) + 15) & ~15)
2902 /* Define the `__builtin_va_list' type for the ABI. */
2903 #define BUILD_VA_LIST_TYPE(VALIST) \
2904 (VALIST) = mips_build_va_list ()
2906 /* Implement `va_start' for varargs and stdarg. */
2907 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2908 mips_va_start (valist, nextarg)
2910 /* Implement `va_arg'. */
2911 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2912 mips_va_arg (valist, type)
2914 /* Output assembler code to FILE to increment profiler label # LABELNO
2915 for profiling a function entry. */
2917 #define FUNCTION_PROFILER(FILE, LABELNO) \
2919 if (TARGET_MIPS16) \
2920 sorry ("mips16 function profiling"); \
2921 fprintf (FILE, "\t.set\tnoat\n"); \
2922 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2923 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2925 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2926 TARGET_64BIT ? "dsubu" : "subu", \
2927 reg_names[STACK_POINTER_REGNUM], \
2928 reg_names[STACK_POINTER_REGNUM], \
2929 Pmode == DImode ? 16 : 8); \
2930 fprintf (FILE, "\tjal\t_mcount\n"); \
2931 fprintf (FILE, "\t.set\tat\n"); \
2934 /* Define this macro if the code for function profiling should come
2935 before the function prologue. Normally, the profiling code comes
2938 /* #define PROFILE_BEFORE_PROLOGUE */
2940 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2941 the stack pointer does not matter. The value is tested only in
2942 functions that have frame pointers.
2943 No definition is equivalent to always zero. */
2945 #define EXIT_IGNORE_STACK 1
2948 /* A C statement to output, on the stream FILE, assembler code for a
2949 block of data that contains the constant parts of a trampoline.
2950 This code should not include a label--the label is taken care of
2953 #define TRAMPOLINE_TEMPLATE(STREAM) \
2955 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2956 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2957 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2958 if (Pmode == DImode) \
2960 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2961 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2965 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2966 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2968 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2969 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2970 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2971 if (Pmode == DImode) \
2973 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2974 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2978 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2979 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2983 /* A C expression for the size in bytes of the trampoline, as an
2986 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2988 /* Alignment required for trampolines, in bits. */
2990 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2992 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2993 program and data caches. */
2995 #ifndef CACHE_FLUSH_FUNC
2996 #define CACHE_FLUSH_FUNC "_flush_cache"
2999 /* A C statement to initialize the variable parts of a trampoline.
3000 ADDR is an RTX for the address of the trampoline; FNADDR is an
3001 RTX for the address of the nested function; STATIC_CHAIN is an
3002 RTX for the static chain value that should be passed to the
3003 function when it is called. */
3005 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
3008 if (Pmode == DImode) \
3010 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
3011 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
3015 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
3016 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
3019 /* Flush both caches. We need to flush the data cache in case \
3020 the system has a write-back cache. */ \
3021 /* ??? Should check the return value for errors. */ \
3022 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
3023 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
3024 0, VOIDmode, 3, addr, Pmode, \
3025 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
3026 GEN_INT (3), TYPE_MODE (integer_type_node)); \
3029 /* Addressing modes, and classification of registers for them. */
3031 /* These assume that REGNO is a hard or pseudo reg number.
3032 They give nonzero only if REGNO is a hard reg of the suitable class
3033 or a pseudo reg currently allocated to a suitable hard reg.
3034 These definitions are NOT overridden anywhere. */
3036 #define BASE_REG_P(regno, mode) \
3038 ? (M16_REG_P (regno) \
3039 || (regno) == FRAME_POINTER_REGNUM \
3040 || (regno) == ARG_POINTER_REGNUM \
3041 || ((regno) == STACK_POINTER_REGNUM \
3042 && (GET_MODE_SIZE (mode) == 4 \
3043 || GET_MODE_SIZE (mode) == 8))) \
3046 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
3047 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3050 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3051 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3053 #define REGNO_OK_FOR_INDEX_P(regno) 0
3054 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3055 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3057 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3058 and check its validity for a certain class.
3059 We have two alternate definitions for each of them.
3060 The usual definition accepts all pseudo regs; the other rejects them all.
3061 The symbol REG_OK_STRICT causes the latter definition to be used.
3063 Most source files want to accept pseudo regs in the hope that
3064 they will get allocated to the class that the insn wants them to be in.
3065 Some source files that are used after register allocation
3066 need to be strict. */
3068 #ifndef REG_OK_STRICT
3069 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3070 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3072 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3073 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3076 #define REG_OK_FOR_INDEX_P(X) 0
3079 /* Maximum number of registers that can appear in a valid memory address. */
3081 #define MAX_REGS_PER_ADDRESS 1
3083 /* A C compound statement with a conditional `goto LABEL;' executed
3084 if X (an RTX) is a legitimate memory address on the target
3085 machine for a memory operand of mode MODE. */
3088 #define GO_PRINTF(x) fprintf(stderr, (x))
3089 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3090 #define GO_DEBUG_RTX(x) debug_rtx(x)
3093 #define GO_PRINTF(x)
3094 #define GO_PRINTF2(x,y)
3095 #define GO_DEBUG_RTX(x)
3098 #ifdef REG_OK_STRICT
3099 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3101 if (mips_legitimate_address_p (MODE, X, 1)) \
3105 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3107 if (mips_legitimate_address_p (MODE, X, 0)) \
3112 /* A C expression that is 1 if the RTX X is a constant which is a
3113 valid address. This is defined to be the same as `CONSTANT_P (X)',
3114 but rejecting CONST_DOUBLE. */
3115 /* When pic, we must reject addresses of the form symbol+large int.
3116 This is because an instruction `sw $4,s+70000' needs to be converted
3117 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3118 assembler would use $at as a temp to load in the large offset. In this
3119 case $at is already in use. We convert such problem addresses to
3120 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3121 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them
3122 when !TARGET_GAS. */
3123 /* We should be rejecting everything but const addresses. */
3124 #define CONSTANT_ADDRESS_P(X) \
3125 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3126 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3127 || (GET_CODE (X) == CONST \
3128 && ! (flag_pic && pic_address_needs_scratch (X)) \
3130 && (mips_abi != ABI_N32 \
3131 && mips_abi != ABI_64)))
3134 /* Define this, so that when PIC, reload won't try to reload invalid
3135 addresses which require two reload registers. */
3137 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3139 /* Nonzero if the constant value X is a legitimate general operand.
3140 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3142 At present, GAS doesn't understand li.[sd], so don't allow it
3143 to be generated at present. Also, the MIPS assembler does not
3144 grok li.d Infinity. */
3146 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3147 Note that the Irix 6 assembler problem may already be fixed.
3148 Note also that the GET_CODE (X) == CONST test catches the mips16
3149 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3150 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3151 ABI_64 to work together, we'll need to fix this. */
3152 #define LEGITIMATE_CONSTANT_P(X) \
3153 ((GET_CODE (X) != CONST_DOUBLE \
3154 || mips_const_double_ok (X, GET_MODE (X))) \
3155 && ! (GET_CODE (X) == CONST \
3157 && (mips_abi == ABI_N32 \
3158 || mips_abi == ABI_64)) \
3159 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3161 /* A C compound statement that attempts to replace X with a valid
3162 memory address for an operand of mode MODE. WIN will be a C
3163 statement label elsewhere in the code; the macro definition may
3166 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3168 to avoid further processing if the address has become legitimate.
3170 X will always be the result of a call to `break_out_memory_refs',
3171 and OLDX will be the operand that was given to that function to
3174 The code generated by this macro should not alter the
3175 substructure of X. If it transforms X into a more legitimate
3176 form, it should assign X (which will always be a C variable) a
3179 It is not necessary for this macro to come up with a legitimate
3180 address. The compiler has standard ways of doing so in all
3181 cases. In fact, it is safe for this macro to do nothing. But
3182 often a machine-dependent strategy can generate better code.
3184 For the MIPS, transform:
3186 memory(X + <large int>)
3190 Y = <large int> & ~0x7fff;
3192 memory (Z + (<large int> & 0x7fff));
3194 This is for CSE to find several similar references, and only use one Z.
3196 When PIC, convert addresses of the form memory (symbol+large int) to
3197 memory (reg+large int). */
3200 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3202 register rtx xinsn = (X); \
3204 if (TARGET_DEBUG_B_MODE) \
3206 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3207 GO_DEBUG_RTX (xinsn); \
3210 if (mips_split_addresses && mips_check_split (X, MODE)) \
3212 /* ??? Is this ever executed? */ \
3213 X = gen_rtx_LO_SUM (Pmode, \
3214 copy_to_mode_reg (Pmode, \
3215 gen_rtx (HIGH, Pmode, X)), \
3220 if (GET_CODE (xinsn) == CONST \
3221 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3222 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3224 && (mips_abi == ABI_N32 \
3225 || mips_abi == ABI_64)))) \
3227 rtx ptr_reg = gen_reg_rtx (Pmode); \
3228 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3230 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3232 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3233 if (SMALL_INT (constant)) \
3235 /* Otherwise we fall through so the code below will fix the \
3240 if (GET_CODE (xinsn) == PLUS) \
3242 register rtx xplus0 = XEXP (xinsn, 0); \
3243 register rtx xplus1 = XEXP (xinsn, 1); \
3244 register enum rtx_code code0 = GET_CODE (xplus0); \
3245 register enum rtx_code code1 = GET_CODE (xplus1); \
3247 if (code0 != REG && code1 == REG) \
3249 xplus0 = XEXP (xinsn, 1); \
3250 xplus1 = XEXP (xinsn, 0); \
3251 code0 = GET_CODE (xplus0); \
3252 code1 = GET_CODE (xplus1); \
3255 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3256 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3258 rtx int_reg = gen_reg_rtx (Pmode); \
3259 rtx ptr_reg = gen_reg_rtx (Pmode); \
3261 emit_move_insn (int_reg, \
3262 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3264 emit_insn (gen_rtx_SET (VOIDmode, \
3266 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3268 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3273 if (TARGET_DEBUG_B_MODE) \
3274 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3278 /* A C statement or compound statement with a conditional `goto
3279 LABEL;' executed if memory address X (an RTX) can have different
3280 meanings depending on the machine mode of the memory reference it
3283 Autoincrement and autodecrement addresses typically have
3284 mode-dependent effects because the amount of the increment or
3285 decrement is the size of the operand being addressed. Some
3286 machines have other mode-dependent addresses. Many RISC machines
3287 have no mode-dependent addresses.
3289 You may assume that ADDR is a valid address for the machine. */
3291 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3293 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3294 'the start of the function that this code is output in'. */
3296 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3297 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3298 asm_fprintf ((FILE), "%U%s", \
3299 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3301 asm_fprintf ((FILE), "%U%s", (NAME))
3303 /* The mips16 wants the constant pool to be after the function,
3304 because the PC relative load instructions use unsigned offsets. */
3306 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3308 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3309 mips_string_length = 0;
3312 /* In mips16 mode, put most string constants after the function. */
3313 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3314 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3317 /* Specify the machine mode that this machine uses
3318 for the index in the tablejump instruction.
3319 ??? Using HImode in mips16 mode can cause overflow. However, the
3320 overflow is no more likely than the overflow in a branch
3321 instruction. Large functions can currently break in both ways. */
3322 #define CASE_VECTOR_MODE \
3323 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3325 /* Define as C expression which evaluates to nonzero if the tablejump
3326 instruction expects the table to contain offsets from the address of the
3328 Do not define this if the table should contain absolute addresses. */
3329 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3331 /* Define this as 1 if `char' should by default be signed; else as 0. */
3332 #ifndef DEFAULT_SIGNED_CHAR
3333 #define DEFAULT_SIGNED_CHAR 1
3336 /* Max number of bytes we can move from memory to memory
3337 in one reasonably fast instruction. */
3338 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3339 #define MAX_MOVE_MAX 8
3341 /* Define this macro as a C expression which is nonzero if
3342 accessing less than a word of memory (i.e. a `char' or a
3343 `short') is no faster than accessing a word of memory, i.e., if
3344 such access require more than one instruction or if there is no
3345 difference in cost between byte and (aligned) word loads.
3347 On RISC machines, it tends to generate better code to define
3348 this as 1, since it avoids making a QI or HI mode register. */
3349 #define SLOW_BYTE_ACCESS 1
3351 /* We assume that the store-condition-codes instructions store 0 for false
3352 and some other value for true. This is the value stored for true. */
3354 #define STORE_FLAG_VALUE 1
3356 /* Define this to be nonzero if shift instructions ignore all but the low-order
3358 #define SHIFT_COUNT_TRUNCATED 1
3360 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3361 is done just by pretending it is already truncated. */
3362 /* In 64 bit mode, 32 bit instructions require that register values be properly
3363 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3364 converts a value >32 bits to a value <32 bits. */
3365 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3366 Something needs to be done about this. Perhaps not use any 32 bit
3367 instructions? Perhaps use PROMOTE_MODE? */
3368 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3369 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3371 /* Specify the machine mode that pointers have.
3372 After generation of rtl, the compiler makes no further distinction
3373 between pointers and any other objects of this machine mode.
3375 For MIPS we make pointers are the smaller of longs and gp-registers. */
3378 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3381 /* A function address in a call instruction
3382 is a word address (for indexing purposes)
3383 so give the MEM rtx a words's mode. */
3385 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3388 /* An expression giving the cost of an addressing mode that
3389 contains ADDRESS. If not defined, the cost is computed from the
3390 form of the ADDRESS expression and the `CONST_COSTS' values.
3392 For most CISC machines, the default cost is a good approximation
3393 of the true cost of the addressing mode. However, on RISC
3394 machines, all instructions normally have the same length and
3395 execution time. Hence all addresses will have equal costs.
3397 In cases where more than one form of an address is known, the
3398 form with the lowest cost will be used. If multiple forms have
3399 the same, lowest, cost, the one that is the most complex will be
3402 For example, suppose an address that is equal to the sum of a
3403 register and a constant is used twice in the same basic block.
3404 When this macro is not defined, the address will be computed in
3405 a register and memory references will be indirect through that
3406 register. On machines where the cost of the addressing mode
3407 containing the sum is no higher than that of a simple indirect
3408 reference, this will produce an additional instruction and
3409 possibly require an additional register. Proper specification
3410 of this macro eliminates this overhead for such machines.
3412 Similar use of this macro is made in strength reduction of loops.
3414 ADDRESS need not be valid as an address. In such a case, the
3415 cost is not relevant and can be any value; invalid addresses
3416 need not be assigned a different cost.
3418 On machines where an address involving more than one register is
3419 as cheap as an address computation involving only one register,
3420 defining `ADDRESS_COST' to reflect this can cause two registers
3421 to be live over a region of code where only one would have been
3422 if `ADDRESS_COST' were not defined in that manner. This effect
3423 should be considered in the definition of this macro.
3424 Equivalent costs should probably only be given to addresses with
3425 different numbers of registers on machines with lots of registers.
3427 This macro will normally either not be defined or be defined as
3430 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3432 /* A C expression for the cost of moving data from a register in
3433 class FROM to one in class TO. The classes are expressed using
3434 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3435 the default; other values are interpreted relative to that.
3437 It is not required that the cost always equal 2 when FROM is the
3438 same as TO; on some machines it is expensive to move between
3439 registers if they are not general registers.
3441 If reload sees an insn consisting of a single `set' between two
3442 hard registers, and if `REGISTER_MOVE_COST' applied to their
3443 classes returns a value of 2, reload does not check to ensure
3444 that the constraints of the insn are met. Setting a cost of
3445 other than 2 will allow reload to verify that the constraints are
3446 met. You should do this if the `movM' pattern's constraints do
3447 not allow such copying. */
3449 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3450 mips_register_move_cost (MODE, FROM, TO)
3452 /* ??? Fix this to be right for the R8000. */
3453 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3454 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3455 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3457 /* Define if copies to/from condition code registers should be avoided.
3459 This is needed for the MIPS because reload_outcc is not complete;
3460 it needs to handle cases where the source is a general or another
3461 condition code register. */
3462 #define AVOID_CCMODE_COPIES
3464 /* A C expression for the cost of a branch instruction. A value of
3465 1 is the default; other values are interpreted relative to that. */
3467 /* ??? Fix this to be right for the R8000. */
3468 #define BRANCH_COST \
3470 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3473 /* If defined, modifies the length assigned to instruction INSN as a
3474 function of the context in which it is used. LENGTH is an lvalue
3475 that contains the initially computed length of the insn and should
3476 be updated with the correct length of the insn. */
3477 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3478 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3481 /* Optionally define this if you have added predicates to
3482 `MACHINE.c'. This macro is called within an initializer of an
3483 array of structures. The first field in the structure is the
3484 name of a predicate and the second field is an array of rtl
3485 codes. For each predicate, list all rtl codes that can be in
3486 expressions matched by the predicate. The list should have a
3487 trailing comma. Here is an example of two entries in the list
3488 for a typical RISC machine:
3490 #define PREDICATE_CODES \
3491 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3492 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3494 Defining this macro does not affect the generated code (however,
3495 incorrect definitions that omit an rtl code that may be matched
3496 by the predicate can cause the compiler to malfunction).
3497 Instead, it allows the table built by `genrecog' to be more
3498 compact and efficient, thus speeding up the compiler. The most
3499 important predicates to include in the list specified by this
3500 macro are thoses used in the most insn patterns. */
3502 #define PREDICATE_CODES \
3503 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3504 {"arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3505 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3506 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3508 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3510 {"small_int", { CONST_INT }}, \
3511 {"large_int", { CONST_INT }}, \
3512 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3513 {"const_float_1_operand", { CONST_DOUBLE }}, \
3514 {"simple_memory_operand", { MEM, SUBREG }}, \
3515 {"equality_op", { EQ, NE }}, \
3516 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3518 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3519 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3520 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3521 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3522 SYMBOL_REF, LABEL_REF, SUBREG, \
3523 REG, MEM, ADDRESSOF }}, \
3524 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3525 SYMBOL_REF, LABEL_REF, SUBREG, \
3526 REG, MEM, ADDRESSOF, SIGN_EXTEND }}, \
3527 {"se_register_operand", { SUBREG, REG, ADDRESSOF, \
3529 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3530 ADDRESSOF, SIGN_EXTEND }}, \
3531 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3532 ADDRESSOF, SIGN_EXTEND }}, \
3533 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3534 ADDRESSOF, SIGN_EXTEND }}, \
3535 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3536 SYMBOL_REF, LABEL_REF, SUBREG, \
3537 REG, ADDRESSOF, SIGN_EXTEND }}, \
3538 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3539 CONST_DOUBLE, CONST }}, \
3540 {"fcc_register_operand", { REG, SUBREG }}, \
3541 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3542 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3544 /* A list of predicates that do special things with modes, and so
3545 should not elicit warnings for VOIDmode match_operand. */
3547 #define SPECIAL_MODE_PREDICATES \
3548 "pc_or_label_operand",
3551 /* If defined, a C statement to be executed just prior to the
3552 output of assembler code for INSN, to modify the extracted
3553 operands so they will be output differently.
3555 Here the argument OPVEC is the vector containing the operands
3556 extracted from INSN, and NOPERANDS is the number of elements of
3557 the vector which contain meaningful data for this insn. The
3558 contents of this vector are what will be used to convert the
3559 insn template into assembler code, so you can change the
3560 assembler output by changing the contents of the vector.
3562 We use it to check if the current insn needs a nop in front of it
3563 because of load delays, and also to update the delay slot
3566 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3567 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3570 /* Control the assembler format that we output. */
3572 /* Output at beginning of assembler file.
3573 If we are optimizing to use the global pointer, create a temporary
3574 file to hold all of the text stuff, and write it out to the end.
3575 This is needed because the MIPS assembler is evidently one pass,
3576 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3577 declaration when the code is processed, it generates a two
3578 instruction sequence. */
3580 #undef ASM_FILE_START
3581 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3583 /* Output to assembler file text saying following lines
3584 may contain character constants, extra white space, comments, etc. */
3587 #define ASM_APP_ON " #APP\n"
3590 /* Output to assembler file text saying following lines
3591 no longer contain unusual constructs. */
3594 #define ASM_APP_OFF " #NO_APP\n"
3597 /* How to refer to registers in assembler output.
3598 This sequence is indexed by compiler's hard-register-number (see above).
3600 In order to support the two different conventions for register names,
3601 we use the name of a table set up in mips.c, which is overwritten
3602 if -mrnames is used. */
3604 #define REGISTER_NAMES \
3606 &mips_reg_names[ 0][0], \
3607 &mips_reg_names[ 1][0], \
3608 &mips_reg_names[ 2][0], \
3609 &mips_reg_names[ 3][0], \
3610 &mips_reg_names[ 4][0], \
3611 &mips_reg_names[ 5][0], \
3612 &mips_reg_names[ 6][0], \
3613 &mips_reg_names[ 7][0], \
3614 &mips_reg_names[ 8][0], \
3615 &mips_reg_names[ 9][0], \
3616 &mips_reg_names[10][0], \
3617 &mips_reg_names[11][0], \
3618 &mips_reg_names[12][0], \
3619 &mips_reg_names[13][0], \
3620 &mips_reg_names[14][0], \
3621 &mips_reg_names[15][0], \
3622 &mips_reg_names[16][0], \
3623 &mips_reg_names[17][0], \
3624 &mips_reg_names[18][0], \
3625 &mips_reg_names[19][0], \
3626 &mips_reg_names[20][0], \
3627 &mips_reg_names[21][0], \
3628 &mips_reg_names[22][0], \
3629 &mips_reg_names[23][0], \
3630 &mips_reg_names[24][0], \
3631 &mips_reg_names[25][0], \
3632 &mips_reg_names[26][0], \
3633 &mips_reg_names[27][0], \
3634 &mips_reg_names[28][0], \
3635 &mips_reg_names[29][0], \
3636 &mips_reg_names[30][0], \
3637 &mips_reg_names[31][0], \
3638 &mips_reg_names[32][0], \
3639 &mips_reg_names[33][0], \
3640 &mips_reg_names[34][0], \
3641 &mips_reg_names[35][0], \
3642 &mips_reg_names[36][0], \
3643 &mips_reg_names[37][0], \
3644 &mips_reg_names[38][0], \
3645 &mips_reg_names[39][0], \
3646 &mips_reg_names[40][0], \
3647 &mips_reg_names[41][0], \
3648 &mips_reg_names[42][0], \
3649 &mips_reg_names[43][0], \
3650 &mips_reg_names[44][0], \
3651 &mips_reg_names[45][0], \
3652 &mips_reg_names[46][0], \
3653 &mips_reg_names[47][0], \
3654 &mips_reg_names[48][0], \
3655 &mips_reg_names[49][0], \
3656 &mips_reg_names[50][0], \
3657 &mips_reg_names[51][0], \
3658 &mips_reg_names[52][0], \
3659 &mips_reg_names[53][0], \
3660 &mips_reg_names[54][0], \
3661 &mips_reg_names[55][0], \
3662 &mips_reg_names[56][0], \
3663 &mips_reg_names[57][0], \
3664 &mips_reg_names[58][0], \
3665 &mips_reg_names[59][0], \
3666 &mips_reg_names[60][0], \
3667 &mips_reg_names[61][0], \
3668 &mips_reg_names[62][0], \
3669 &mips_reg_names[63][0], \
3670 &mips_reg_names[64][0], \
3671 &mips_reg_names[65][0], \
3672 &mips_reg_names[66][0], \
3673 &mips_reg_names[67][0], \
3674 &mips_reg_names[68][0], \
3675 &mips_reg_names[69][0], \
3676 &mips_reg_names[70][0], \
3677 &mips_reg_names[71][0], \
3678 &mips_reg_names[72][0], \
3679 &mips_reg_names[73][0], \
3680 &mips_reg_names[74][0], \
3681 &mips_reg_names[75][0], \
3682 &mips_reg_names[76][0], \
3683 &mips_reg_names[77][0], \
3684 &mips_reg_names[78][0], \
3685 &mips_reg_names[79][0], \
3686 &mips_reg_names[80][0], \
3687 &mips_reg_names[81][0], \
3688 &mips_reg_names[82][0], \
3689 &mips_reg_names[83][0], \
3690 &mips_reg_names[84][0], \
3691 &mips_reg_names[85][0], \
3692 &mips_reg_names[86][0], \
3693 &mips_reg_names[87][0], \
3694 &mips_reg_names[88][0], \
3695 &mips_reg_names[89][0], \
3696 &mips_reg_names[90][0], \
3697 &mips_reg_names[91][0], \
3698 &mips_reg_names[92][0], \
3699 &mips_reg_names[93][0], \
3700 &mips_reg_names[94][0], \
3701 &mips_reg_names[95][0], \
3702 &mips_reg_names[96][0], \
3703 &mips_reg_names[97][0], \
3704 &mips_reg_names[98][0], \
3705 &mips_reg_names[99][0], \
3706 &mips_reg_names[100][0], \
3707 &mips_reg_names[101][0], \
3708 &mips_reg_names[102][0], \
3709 &mips_reg_names[103][0], \
3710 &mips_reg_names[104][0], \
3711 &mips_reg_names[105][0], \
3712 &mips_reg_names[106][0], \
3713 &mips_reg_names[107][0], \
3714 &mips_reg_names[108][0], \
3715 &mips_reg_names[109][0], \
3716 &mips_reg_names[110][0], \
3717 &mips_reg_names[111][0], \
3718 &mips_reg_names[112][0], \
3719 &mips_reg_names[113][0], \
3720 &mips_reg_names[114][0], \
3721 &mips_reg_names[115][0], \
3722 &mips_reg_names[116][0], \
3723 &mips_reg_names[117][0], \
3724 &mips_reg_names[118][0], \
3725 &mips_reg_names[119][0], \
3726 &mips_reg_names[120][0], \
3727 &mips_reg_names[121][0], \
3728 &mips_reg_names[122][0], \
3729 &mips_reg_names[123][0], \
3730 &mips_reg_names[124][0], \
3731 &mips_reg_names[125][0], \
3732 &mips_reg_names[126][0], \
3733 &mips_reg_names[127][0], \
3734 &mips_reg_names[128][0], \
3735 &mips_reg_names[129][0], \
3736 &mips_reg_names[130][0], \
3737 &mips_reg_names[131][0], \
3738 &mips_reg_names[132][0], \
3739 &mips_reg_names[133][0], \
3740 &mips_reg_names[134][0], \
3741 &mips_reg_names[135][0], \
3742 &mips_reg_names[136][0], \
3743 &mips_reg_names[137][0], \
3744 &mips_reg_names[138][0], \
3745 &mips_reg_names[139][0], \
3746 &mips_reg_names[140][0], \
3747 &mips_reg_names[141][0], \
3748 &mips_reg_names[142][0], \
3749 &mips_reg_names[143][0], \
3750 &mips_reg_names[144][0], \
3751 &mips_reg_names[145][0], \
3752 &mips_reg_names[146][0], \
3753 &mips_reg_names[147][0], \
3754 &mips_reg_names[148][0], \
3755 &mips_reg_names[149][0], \
3756 &mips_reg_names[150][0], \
3757 &mips_reg_names[151][0], \
3758 &mips_reg_names[152][0], \
3759 &mips_reg_names[153][0], \
3760 &mips_reg_names[154][0], \
3761 &mips_reg_names[155][0], \
3762 &mips_reg_names[156][0], \
3763 &mips_reg_names[157][0], \
3764 &mips_reg_names[158][0], \
3765 &mips_reg_names[159][0], \
3766 &mips_reg_names[160][0], \
3767 &mips_reg_names[161][0], \
3768 &mips_reg_names[162][0], \
3769 &mips_reg_names[163][0], \
3770 &mips_reg_names[164][0], \
3771 &mips_reg_names[165][0], \
3772 &mips_reg_names[166][0], \
3773 &mips_reg_names[167][0], \
3774 &mips_reg_names[168][0], \
3775 &mips_reg_names[169][0], \
3776 &mips_reg_names[170][0], \
3777 &mips_reg_names[171][0], \
3778 &mips_reg_names[172][0], \
3779 &mips_reg_names[173][0], \
3780 &mips_reg_names[174][0], \
3781 &mips_reg_names[175][0] \
3784 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3785 So define this for it. */
3786 #define DEBUG_REGISTER_NAMES \
3788 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3789 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3790 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3791 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3792 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3793 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3794 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3795 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3796 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3797 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3798 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3799 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3800 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3801 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3802 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3803 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3804 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3805 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3806 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3807 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3808 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3809 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3812 /* If defined, a C initializer for an array of structures
3813 containing a name and a register number. This macro defines
3814 additional names for hard registers, thus allowing the `asm'
3815 option in declarations to refer to registers using alternate
3818 We define both names for the integer registers here. */
3820 #define ADDITIONAL_REGISTER_NAMES \
3822 { "$0", 0 + GP_REG_FIRST }, \
3823 { "$1", 1 + GP_REG_FIRST }, \
3824 { "$2", 2 + GP_REG_FIRST }, \
3825 { "$3", 3 + GP_REG_FIRST }, \
3826 { "$4", 4 + GP_REG_FIRST }, \
3827 { "$5", 5 + GP_REG_FIRST }, \
3828 { "$6", 6 + GP_REG_FIRST }, \
3829 { "$7", 7 + GP_REG_FIRST }, \
3830 { "$8", 8 + GP_REG_FIRST }, \
3831 { "$9", 9 + GP_REG_FIRST }, \
3832 { "$10", 10 + GP_REG_FIRST }, \
3833 { "$11", 11 + GP_REG_FIRST }, \
3834 { "$12", 12 + GP_REG_FIRST }, \
3835 { "$13", 13 + GP_REG_FIRST }, \
3836 { "$14", 14 + GP_REG_FIRST }, \
3837 { "$15", 15 + GP_REG_FIRST }, \
3838 { "$16", 16 + GP_REG_FIRST }, \
3839 { "$17", 17 + GP_REG_FIRST }, \
3840 { "$18", 18 + GP_REG_FIRST }, \
3841 { "$19", 19 + GP_REG_FIRST }, \
3842 { "$20", 20 + GP_REG_FIRST }, \
3843 { "$21", 21 + GP_REG_FIRST }, \
3844 { "$22", 22 + GP_REG_FIRST }, \
3845 { "$23", 23 + GP_REG_FIRST }, \
3846 { "$24", 24 + GP_REG_FIRST }, \
3847 { "$25", 25 + GP_REG_FIRST }, \
3848 { "$26", 26 + GP_REG_FIRST }, \
3849 { "$27", 27 + GP_REG_FIRST }, \
3850 { "$28", 28 + GP_REG_FIRST }, \
3851 { "$29", 29 + GP_REG_FIRST }, \
3852 { "$30", 30 + GP_REG_FIRST }, \
3853 { "$31", 31 + GP_REG_FIRST }, \
3854 { "$sp", 29 + GP_REG_FIRST }, \
3855 { "$fp", 30 + GP_REG_FIRST }, \
3856 { "at", 1 + GP_REG_FIRST }, \
3857 { "v0", 2 + GP_REG_FIRST }, \
3858 { "v1", 3 + GP_REG_FIRST }, \
3859 { "a0", 4 + GP_REG_FIRST }, \
3860 { "a1", 5 + GP_REG_FIRST }, \
3861 { "a2", 6 + GP_REG_FIRST }, \
3862 { "a3", 7 + GP_REG_FIRST }, \
3863 { "t0", 8 + GP_REG_FIRST }, \
3864 { "t1", 9 + GP_REG_FIRST }, \
3865 { "t2", 10 + GP_REG_FIRST }, \
3866 { "t3", 11 + GP_REG_FIRST }, \
3867 { "t4", 12 + GP_REG_FIRST }, \
3868 { "t5", 13 + GP_REG_FIRST }, \
3869 { "t6", 14 + GP_REG_FIRST }, \
3870 { "t7", 15 + GP_REG_FIRST }, \
3871 { "s0", 16 + GP_REG_FIRST }, \
3872 { "s1", 17 + GP_REG_FIRST }, \
3873 { "s2", 18 + GP_REG_FIRST }, \
3874 { "s3", 19 + GP_REG_FIRST }, \
3875 { "s4", 20 + GP_REG_FIRST }, \
3876 { "s5", 21 + GP_REG_FIRST }, \
3877 { "s6", 22 + GP_REG_FIRST }, \
3878 { "s7", 23 + GP_REG_FIRST }, \
3879 { "t8", 24 + GP_REG_FIRST }, \
3880 { "t9", 25 + GP_REG_FIRST }, \
3881 { "k0", 26 + GP_REG_FIRST }, \
3882 { "k1", 27 + GP_REG_FIRST }, \
3883 { "gp", 28 + GP_REG_FIRST }, \
3884 { "sp", 29 + GP_REG_FIRST }, \
3885 { "fp", 30 + GP_REG_FIRST }, \
3886 { "ra", 31 + GP_REG_FIRST }, \
3887 { "$sp", 29 + GP_REG_FIRST }, \
3888 { "$fp", 30 + GP_REG_FIRST } \
3889 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3892 /* This is meant to be redefined in the host dependent files. It is a
3893 set of alternative names and regnums for mips coprocessors. */
3895 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3897 /* A C compound statement to output to stdio stream STREAM the
3898 assembler syntax for an instruction operand X. X is an RTL
3901 CODE is a value that can be used to specify one of several ways
3902 of printing the operand. It is used when identical operands
3903 must be printed differently depending on the context. CODE
3904 comes from the `%' specification that was used to request
3905 printing of the operand. If the specification was just `%DIGIT'
3906 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3907 is the ASCII code for LTR.
3909 If X is a register, this macro should print the register's name.
3910 The names can be found in an array `reg_names' whose type is
3911 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3913 When the machine description has a specification `%PUNCT' (a `%'
3914 followed by a punctuation character), this macro is called with
3915 a null pointer for X and the punctuation character for CODE.
3917 See mips.c for the MIPS specific codes. */
3919 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3921 /* A C expression which evaluates to true if CODE is a valid
3922 punctuation character for use in the `PRINT_OPERAND' macro. If
3923 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3924 punctuation characters (except for the standard one, `%') are
3925 used in this way. */
3927 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3929 /* A C compound statement to output to stdio stream STREAM the
3930 assembler syntax for an instruction operand that is a memory
3931 reference whose address is ADDR. ADDR is an RTL expression. */
3933 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3936 /* A C statement, to be executed after all slot-filler instructions
3937 have been output. If necessary, call `dbr_sequence_length' to
3938 determine the number of slots filled in a sequence (zero if not
3939 currently outputting a sequence), to decide how many no-ops to
3940 output, or whatever.
3942 Don't define this macro if it has nothing to do, but it is
3943 helpful in reading assembly output if the extent of the delay
3944 sequence is made explicit (e.g. with white space).
3946 Note that output routines for instructions with delay slots must
3947 be prepared to deal with not being output as part of a sequence
3948 (i.e. when the scheduling pass is not run, or when no slot
3949 fillers could be found.) The variable `final_sequence' is null
3950 when not processing a sequence, otherwise it contains the
3951 `sequence' rtx being output. */
3953 #define DBR_OUTPUT_SEQEND(STREAM) \
3956 if (set_nomacro > 0 && --set_nomacro == 0) \
3957 fputs ("\t.set\tmacro\n", STREAM); \
3959 if (set_noreorder > 0 && --set_noreorder == 0) \
3960 fputs ("\t.set\treorder\n", STREAM); \
3962 dslots_jump_filled++; \
3963 fputs ("\n", STREAM); \
3968 /* How to tell the debugger about changes of source files. Note, the
3969 mips ECOFF format cannot deal with changes of files inside of
3970 functions, which means the output of parser generators like bison
3971 is generally not debuggable without using the -l switch. Lose,
3972 lose, lose. Silicon graphics seems to want all .file's hardwired
3975 #ifndef SET_FILE_NUMBER
3976 #define SET_FILE_NUMBER() ++num_source_filenames
3979 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3980 mips_output_filename (STREAM, NAME)
3982 /* This is defined so that it can be overridden in iris6.h. */
3983 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3986 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3987 output_quoted_string (STREAM, NAME); \
3988 fputs ("\n", STREAM); \
3992 /* This is how to output a note the debugger telling it the line number
3993 to which the following sequence of instructions corresponds.
3994 Silicon graphics puts a label after each .loc. */
3996 #ifndef LABEL_AFTER_LOC
3997 #define LABEL_AFTER_LOC(STREAM)
4000 #ifndef ASM_OUTPUT_SOURCE_LINE
4001 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4002 mips_output_lineno (STREAM, LINE)
4005 /* The MIPS implementation uses some labels for its own purpose. The
4006 following lists what labels are created, and are all formed by the
4007 pattern $L[a-z].*. The machine independent portion of GCC creates
4008 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4010 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4011 $Lb[0-9]+ Begin blocks for MIPS debug support
4012 $Lc[0-9]+ Label for use in s<xx> operation.
4013 $Le[0-9]+ End blocks for MIPS debug support */
4015 /* A C statement (sans semicolon) to output to the stdio stream
4016 STREAM any text necessary for declaring the name NAME of an
4017 initialized variable which is being defined. This macro must
4018 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4019 The argument DECL is the `VAR_DECL' tree node representing the
4022 If this macro is not defined, then the variable name is defined
4023 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4025 #undef ASM_DECLARE_OBJECT_NAME
4026 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4029 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4033 /* Globalizing directive for a label. */
4034 #define GLOBAL_ASM_OP "\t.globl\t"
4036 /* This says how to define a global common symbol. */
4038 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4040 /* If the target wants uninitialized const declarations in \
4041 .rdata then don't put them in .comm */ \
4042 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4043 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4044 && (DECL_INITIAL (DECL) == 0 \
4045 || DECL_INITIAL (DECL) == error_mark_node)) \
4047 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4048 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
4050 readonly_data_section (); \
4051 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4052 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4056 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4061 /* This says how to define a local common symbol (ie, not visible to
4064 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4065 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4068 /* This says how to output an external. It would be possible not to
4069 output anything and let undefined symbol become external. However
4070 the assembler uses length information on externals to allocate in
4071 data/sdata bss/sbss, thereby saving exec time. */
4073 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4074 mips_output_external(STREAM,DECL,NAME)
4076 /* This says what to print at the end of the assembly file */
4078 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4081 /* Play switch file games if we're optimizing the global pointer. */
4084 #define TEXT_SECTION() \
4086 extern FILE *asm_out_text_file; \
4087 if (TARGET_FILE_SWITCHING) \
4088 asm_out_file = asm_out_text_file; \
4089 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4090 fputc ('\n', asm_out_file); \
4094 /* This is how to declare a function name. The actual work of
4095 emitting the label is moved to function_prologue, so that we can
4096 get the line number correctly emitted before the .ent directive,
4097 and after any .file directives. Define as empty so that the function
4098 is not declared before the .ent directive elsewhere. */
4100 #undef ASM_DECLARE_FUNCTION_NAME
4101 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4103 /* This is how to store into the string LABEL
4104 the symbol_ref name of an internal numbered label where
4105 PREFIX is the class of label and NUM is the number within the class.
4106 This is suitable for output with `assemble_name'. */
4108 #undef ASM_GENERATE_INTERNAL_LABEL
4109 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4110 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4112 /* This is how to output an element of a case-vector that is absolute. */
4114 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4115 fprintf (STREAM, "\t%s\t%sL%d\n", \
4116 Pmode == DImode ? ".dword" : ".word", \
4117 LOCAL_LABEL_PREFIX, \
4120 /* This is how to output an element of a case-vector that is relative.
4121 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4122 TARGET_EMBEDDED_PIC). */
4124 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4126 if (TARGET_MIPS16) \
4127 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4128 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4129 else if (TARGET_EMBEDDED_PIC) \
4130 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4131 Pmode == DImode ? ".dword" : ".word", \
4132 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4133 else if (mips_abi == ABI_32 || mips_abi == ABI_O64 \
4134 || (TARGET_GAS && mips_abi == ABI_N32) \
4135 || (TARGET_GAS && mips_abi == ABI_64)) \
4136 fprintf (STREAM, "\t%s\t%sL%d\n", \
4137 Pmode == DImode ? ".gpdword" : ".gpword", \
4138 LOCAL_LABEL_PREFIX, VALUE); \
4140 fprintf (STREAM, "\t%s\t%sL%d\n", \
4141 Pmode == DImode ? ".dword" : ".word", \
4142 LOCAL_LABEL_PREFIX, VALUE); \
4145 /* When generating embedded PIC or mips16 code we want to put the jump
4146 table in the .text section. In all other cases, we want to put the
4147 jump table in the .rdata section. Unfortunately, we can't use
4148 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4149 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4150 section if appropriate. */
4151 #undef ASM_OUTPUT_CASE_LABEL
4152 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4154 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4155 function_section (current_function_decl); \
4156 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
4159 /* This is how to output an assembler line
4160 that says to advance the location counter
4161 to a multiple of 2**LOG bytes. */
4163 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4164 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4166 /* This is how to output an assembler line to advance the location
4167 counter by SIZE bytes. */
4169 #undef ASM_OUTPUT_SKIP
4170 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4171 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4173 /* This is how to output a string. */
4174 #undef ASM_OUTPUT_ASCII
4175 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4176 mips_output_ascii (STREAM, STRING, LEN)
4178 /* Output #ident as a in the read-only data section. */
4179 #undef ASM_OUTPUT_IDENT
4180 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4182 const char *p = STRING; \
4183 int size = strlen (p) + 1; \
4184 readonly_data_section (); \
4185 assemble_string (p, size); \
4188 /* Default to -G 8 */
4189 #ifndef MIPS_DEFAULT_GVALUE
4190 #define MIPS_DEFAULT_GVALUE 8
4193 /* Define the strings to put out for each section in the object file. */
4194 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4195 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4196 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4198 #undef READONLY_DATA_SECTION_ASM_OP
4199 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4201 #define SMALL_DATA_SECTION sdata_section
4203 /* What other sections we support other than the normal .data/.text. */
4205 #undef EXTRA_SECTIONS
4206 #define EXTRA_SECTIONS in_sdata
4208 /* Define the additional functions to select our additional sections. */
4210 /* on the MIPS it is not a good idea to put constants in the text
4211 section, since this defeats the sdata/data mechanism. This is
4212 especially true when -O is used. In this case an effort is made to
4213 address with faster (gp) register relative addressing, which can
4214 only get at sdata and sbss items (there is no stext !!) However,
4215 if the constant is too large for sdata, and it's readonly, it
4216 will go into the .rdata section. */
4218 #undef EXTRA_SECTION_FUNCTIONS
4219 #define EXTRA_SECTION_FUNCTIONS \
4223 if (in_section != in_sdata) \
4225 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4226 in_section = in_sdata; \
4230 /* Given a decl node or constant node, choose the section to output it in
4231 and select that section. */
4233 #undef TARGET_ASM_SELECT_SECTION
4234 #define TARGET_ASM_SELECT_SECTION mips_select_section
4236 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4239 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4240 TARGET_64BIT ? "dsubu" : "subu", \
4241 reg_names[STACK_POINTER_REGNUM], \
4242 reg_names[STACK_POINTER_REGNUM], \
4243 TARGET_64BIT ? "sd" : "sw", \
4245 reg_names[STACK_POINTER_REGNUM]); \
4249 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4252 if (! set_noreorder) \
4253 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4255 dslots_load_total++; \
4256 dslots_load_filled++; \
4257 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4258 TARGET_64BIT ? "ld" : "lw", \
4260 reg_names[STACK_POINTER_REGNUM], \
4261 TARGET_64BIT ? "daddu" : "addu", \
4262 reg_names[STACK_POINTER_REGNUM], \
4263 reg_names[STACK_POINTER_REGNUM]); \
4265 if (! set_noreorder) \
4266 fprintf (STREAM, "\t.set\treorder\n"); \
4270 /* How to start an assembler comment.
4271 The leading space is important (the mips native assembler requires it). */
4272 #ifndef ASM_COMMENT_START
4273 #define ASM_COMMENT_START " #"
4277 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4278 and mips-tdump.c to print them out.
4280 These must match the corresponding definitions in gdb/mipsread.c.
4281 Unfortunately, gcc and gdb do not currently share any directories. */
4283 #define CODE_MASK 0x8F300
4284 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4285 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4286 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4289 /* Default definitions for size_t and ptrdiff_t. We must override the
4290 definitions from ../svr4.h on mips-*-linux-gnu. */
4293 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4296 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4298 /* See mips_expand_prologue's use of loadgp for when this should be
4301 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4302 && mips_abi != ABI_32 \
4303 && mips_abi != ABI_O64)
4305 /* In mips16 mode, we need to look through the function to check for
4306 PC relative loads that are out of range. */
4307 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4309 /* We need to use a special set of functions to handle hard floating
4310 point code in mips16 mode. */
4312 #ifndef INIT_SUBTARGET_OPTABS
4313 #define INIT_SUBTARGET_OPTABS
4316 #define INIT_TARGET_OPTABS \
4319 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4320 INIT_SUBTARGET_OPTABS; \
4323 add_optab->handlers[(int) SFmode].libfunc = \
4324 init_one_libfunc ("__mips16_addsf3"); \
4325 sub_optab->handlers[(int) SFmode].libfunc = \
4326 init_one_libfunc ("__mips16_subsf3"); \
4327 smul_optab->handlers[(int) SFmode].libfunc = \
4328 init_one_libfunc ("__mips16_mulsf3"); \
4329 sdiv_optab->handlers[(int) SFmode].libfunc = \
4330 init_one_libfunc ("__mips16_divsf3"); \
4332 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4333 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4334 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4335 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4336 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4337 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4339 floatsisf_libfunc = \
4340 init_one_libfunc ("__mips16_floatsisf"); \
4342 init_one_libfunc ("__mips16_fixsfsi"); \
4344 if (TARGET_DOUBLE_FLOAT) \
4346 add_optab->handlers[(int) DFmode].libfunc = \
4347 init_one_libfunc ("__mips16_adddf3"); \
4348 sub_optab->handlers[(int) DFmode].libfunc = \
4349 init_one_libfunc ("__mips16_subdf3"); \
4350 smul_optab->handlers[(int) DFmode].libfunc = \
4351 init_one_libfunc ("__mips16_muldf3"); \
4352 sdiv_optab->handlers[(int) DFmode].libfunc = \
4353 init_one_libfunc ("__mips16_divdf3"); \
4355 extendsfdf2_libfunc = \
4356 init_one_libfunc ("__mips16_extendsfdf2"); \
4357 truncdfsf2_libfunc = \
4358 init_one_libfunc ("__mips16_truncdfsf2"); \
4361 init_one_libfunc ("__mips16_eqdf2"); \
4363 init_one_libfunc ("__mips16_nedf2"); \
4365 init_one_libfunc ("__mips16_gtdf2"); \
4367 init_one_libfunc ("__mips16_gedf2"); \
4369 init_one_libfunc ("__mips16_ltdf2"); \
4371 init_one_libfunc ("__mips16_ledf2"); \
4373 floatsidf_libfunc = \
4374 init_one_libfunc ("__mips16_floatsidf"); \
4376 init_one_libfunc ("__mips16_fixdfsi"); \
4382 #define DFMODE_NAN \
4383 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4384 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4385 #define SFMODE_NAN \
4386 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4387 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4389 /* Generate calls to memcpy, etc., not bcopy, etc. */
4390 #define TARGET_MEM_FUNCTIONS
4392 /* Since the bits of the _init and _fini function is spread across
4393 many object files, each potentially with its own GP, we must assume
4394 we need to load our GP. We don't preserve $gp or $ra, since each
4395 init/fini chunk is supposed to initialize $gp, and crti/crtn
4396 already take care of preserving $ra and, when appropriate, $gp. */
4397 #if _MIPS_SIM == _MIPS_SIM_ABI32
4398 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4399 asm (SECTION_OP "\n\
4405 jal " USER_LABEL_PREFIX #FUNC "\n\
4406 " TEXT_SECTION_ASM_OP);
4407 #endif /* Switch to #elif when we're no longer limited by K&R C. */
4408 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4409 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4410 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4411 asm (SECTION_OP "\n\
4416 .cpsetup $31, $2, 1b\n\
4417 jal " USER_LABEL_PREFIX #FUNC "\n\
4418 " TEXT_SECTION_ASM_OP);