1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 /* MIPS external variables defined in mips.c. */
31 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
32 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
33 to work on a 64-bit machine. */
41 /* Masks that affect tuning.
43 PTF_AVOID_BRANCHLIKELY
44 Set if it is usually not profitable to use branch-likely instructions
45 for this target, typically because the branches are always predicted
46 taken and so incur a large overhead when not taken. */
47 #define PTF_AVOID_BRANCHLIKELY 0x1
49 /* Information about one recognized processor. Defined here for the
50 benefit of TARGET_CPU_CPP_BUILTINS. */
51 struct mips_cpu_info {
52 /* The 'canonical' name of the processor as far as GCC is concerned.
53 It's typically a manufacturer's prefix followed by a numerical
54 designation. It should be lowercase. */
57 /* The internal processor number that most closely matches this
58 entry. Several processors can have the same value, if there's no
59 difference between them from GCC's point of view. */
62 /* The ISA level that the processor implements. */
65 /* A mask of PTF_* values. */
66 unsigned int tune_flags;
69 /* Enumerates the setting of the -mcode-readable option. */
70 enum mips_code_readable_setting {
76 /* Macros to silence warnings about numbers being signed in traditional
77 C and unsigned in ISO C when compiled on 32-bit hosts. */
79 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
80 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
81 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
84 /* Run-time compilation parameters selecting different hardware subsets. */
86 /* True if we are generating position-independent VxWorks RTP code. */
87 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
89 /* True if the output file is marked as ".abicalls; .option pic0"
91 #define TARGET_ABICALLS_PIC0 \
92 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
94 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
95 #define TARGET_ABICALLS_PIC2 \
96 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
98 /* True if the call patterns should be split into a jalr followed by
99 an instruction to restore $gp. It is only safe to split the load
100 from the call when every use of $gp is explicit.
102 See mips_must_initialize_gp_p for details about how we manage the
105 #define TARGET_SPLIT_CALLS \
106 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
108 /* True if we're generating a form of -mabicalls in which we can use
109 operators like %hi and %lo to refer to locally-binding symbols.
110 We can only do this for -mno-shared, and only then if we can use
111 relocation operations instead of assembly macros. It isn't really
112 worth using absolute sequences for 64-bit symbols because GOT
113 accesses are so much shorter. */
115 #define TARGET_ABSOLUTE_ABICALLS \
118 && TARGET_EXPLICIT_RELOCS \
119 && !ABI_HAS_64BIT_SYMBOLS)
121 /* True if we can optimize sibling calls. For simplicity, we only
122 handle cases in which call_insn_operand will reject invalid
123 sibcall addresses. There are two cases in which this isn't true:
125 - TARGET_MIPS16. call_insn_operand accepts constant addresses
126 but there is no direct jump instruction. It isn't worth
127 using sibling calls in this case anyway; they would usually
128 be longer than normal calls.
130 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
131 accepts global constants, but all sibcalls must be indirect. */
132 #define TARGET_SIBCALLS \
133 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
135 /* True if we need to use a global offset table to access some symbols. */
136 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
138 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
139 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
141 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
142 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
144 /* True if we should use .cprestore to store to the cprestore slot.
146 We continue to use .cprestore for explicit-reloc code so that JALs
147 inside inline asms will work correctly. */
148 #define TARGET_CPRESTORE_DIRECTIVE \
149 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
151 /* True if we can use the J and JAL instructions. */
152 #define TARGET_ABSOLUTE_JUMPS \
153 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
155 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
156 This is true for both the PIC and non-PIC VxWorks RTP modes. */
157 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
159 /* True if .gpword or .gpdword should be used for switch tables.
161 Although GAS does understand .gpdword, the SGI linker mishandles
162 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
163 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
164 #define TARGET_GPWORD \
166 && !TARGET_ABSOLUTE_ABICALLS \
167 && !(mips_abi == ABI_64 && TARGET_IRIX6))
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
177 /* Generate mips16 code */
178 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
179 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
180 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
181 /* Generate mips16e register save/restore sequences. */
182 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
184 /* True if we're generating a form of MIPS16 code in which general
185 text loads are allowed. */
186 #define TARGET_MIPS16_TEXT_LOADS \
187 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
189 /* True if we're generating a form of MIPS16 code in which PC-relative
190 loads are allowed. */
191 #define TARGET_MIPS16_PCREL_LOADS \
192 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
194 /* Generic ISA defines. */
195 #define ISA_MIPS1 (mips_isa == 1)
196 #define ISA_MIPS2 (mips_isa == 2)
197 #define ISA_MIPS3 (mips_isa == 3)
198 #define ISA_MIPS4 (mips_isa == 4)
199 #define ISA_MIPS32 (mips_isa == 32)
200 #define ISA_MIPS32R2 (mips_isa == 33)
201 #define ISA_MIPS64 (mips_isa == 64)
202 #define ISA_MIPS64R2 (mips_isa == 65)
204 /* Architecture target defines. */
205 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
206 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
207 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
208 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
209 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
210 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
211 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
212 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
213 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
214 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
215 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
216 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
217 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
218 || mips_arch == PROCESSOR_SB1A)
219 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
221 /* Scheduling target defines. */
222 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
223 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
224 || mips_tune == PROCESSOR_24KF2_1 \
225 || mips_tune == PROCESSOR_24KF1_1)
226 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
227 || mips_tune == PROCESSOR_74KF2_1 \
228 || mips_tune == PROCESSOR_74KF1_1 \
229 || mips_tune == PROCESSOR_74KF3_2)
230 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
231 || mips_tune == PROCESSOR_LOONGSON_2F)
232 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
233 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
234 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
235 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
236 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
237 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
238 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
239 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
240 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
241 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
242 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
243 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
244 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
245 || mips_tune == PROCESSOR_SB1A)
247 /* Whether vector modes and intrinsics for ST Microelectronics
248 Loongson-2E/2F processors should be enabled. In o32 pairs of
249 floating-point registers provide 64-bit values. */
250 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
251 && TARGET_LOONGSON_2EF)
253 /* True if the pre-reload scheduler should try to create chains of
254 multiply-add or multiply-subtract instructions. For example,
262 t1 will have a higher priority than t2 and t3 will have a higher
263 priority than t4. However, before reload, there is no dependence
264 between t1 and t3, and they can often have similar priorities.
265 The scheduler will then tend to prefer:
272 which stops us from making full use of macc/madd-style instructions.
273 This sort of situation occurs frequently in Fourier transforms and
276 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
277 queue so that chained multiply-add and multiply-subtract instructions
278 appear ahead of any other instruction that is likely to clobber lo.
279 In the example above, if t2 and t3 become ready at the same time,
280 the code ensures that t2 is scheduled first.
282 Multiply-accumulate instructions are a bigger win for some targets
283 than others, so this macro is defined on an opt-in basis. */
284 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
289 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
290 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
292 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
293 directly accessible, while the command-line options select
294 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
296 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
297 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
299 /* False if SC acts as a memory barrier with respect to itself,
300 otherwise a SYNC will be emitted after SC for atomic operations
301 that require ordering between the SC and following loads and
302 stores. It does not tell anything about ordering of loads and
303 stores prior to and following the SC, only about the SC itself and
304 those loads and stores follow it. */
305 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
307 /* IRIX specific stuff. */
308 #define TARGET_IRIX6 0
310 /* Define preprocessor macros for the -march and -mtune options.
311 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
312 processor. If INFO's canonical name is "foo", define PREFIX to
313 be "foo", and define an additional macro PREFIX_FOO. */
314 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
319 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
320 for (p = macro; *p != 0; p++) \
323 builtin_define (macro); \
324 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
329 /* Target CPU builtins. */
330 #define TARGET_CPU_CPP_BUILTINS() \
333 /* Everyone but IRIX defines this to mips. */ \
335 builtin_assert ("machine=mips"); \
337 builtin_assert ("cpu=mips"); \
338 builtin_define ("__mips__"); \
339 builtin_define ("_mips"); \
341 /* We do this here because __mips is defined below and so we \
342 can't use builtin_define_std. We don't ever want to define \
343 "mips" for VxWorks because some of the VxWorks headers \
344 construct include filenames from a root directory macro, \
345 an architecture macro and a filename, where the architecture \
346 macro expands to 'mips'. If we define 'mips' to 1, the \
347 architecture macro expands to 1 as well. */ \
348 if (!flag_iso && !TARGET_VXWORKS) \
349 builtin_define ("mips"); \
352 builtin_define ("__mips64"); \
356 /* Treat _R3000 and _R4000 like register-size \
357 defines, which is how they've historically \
361 builtin_define_std ("R4000"); \
362 builtin_define ("_R4000"); \
366 builtin_define_std ("R3000"); \
367 builtin_define ("_R3000"); \
370 if (TARGET_FLOAT64) \
371 builtin_define ("__mips_fpr=64"); \
373 builtin_define ("__mips_fpr=32"); \
375 if (mips_base_mips16) \
376 builtin_define ("__mips16"); \
379 builtin_define ("__mips3d"); \
381 if (TARGET_SMARTMIPS) \
382 builtin_define ("__mips_smartmips"); \
386 builtin_define ("__mips_dsp"); \
389 builtin_define ("__mips_dspr2"); \
390 builtin_define ("__mips_dsp_rev=2"); \
393 builtin_define ("__mips_dsp_rev=1"); \
396 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
397 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
401 builtin_define ("__mips=1"); \
402 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
404 else if (ISA_MIPS2) \
406 builtin_define ("__mips=2"); \
407 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
409 else if (ISA_MIPS3) \
411 builtin_define ("__mips=3"); \
412 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
414 else if (ISA_MIPS4) \
416 builtin_define ("__mips=4"); \
417 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
419 else if (ISA_MIPS32) \
421 builtin_define ("__mips=32"); \
422 builtin_define ("__mips_isa_rev=1"); \
423 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
425 else if (ISA_MIPS32R2) \
427 builtin_define ("__mips=32"); \
428 builtin_define ("__mips_isa_rev=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
431 else if (ISA_MIPS64) \
433 builtin_define ("__mips=64"); \
434 builtin_define ("__mips_isa_rev=1"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
437 else if (ISA_MIPS64R2) \
439 builtin_define ("__mips=64"); \
440 builtin_define ("__mips_isa_rev=2"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
447 builtin_define ("_ABIO32=1"); \
448 builtin_define ("_MIPS_SIM=_ABIO32"); \
452 builtin_define ("_ABIN32=2"); \
453 builtin_define ("_MIPS_SIM=_ABIN32"); \
457 builtin_define ("_ABI64=3"); \
458 builtin_define ("_MIPS_SIM=_ABI64"); \
462 builtin_define ("_ABIO64=4"); \
463 builtin_define ("_MIPS_SIM=_ABIO64"); \
467 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
468 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
469 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
470 builtin_define_with_int_value ("_MIPS_FPSET", \
471 32 / MAX_FPRS_PER_FMT); \
473 /* These defines reflect the ABI in use, not whether the \
474 FPU is directly accessible. */ \
475 if (TARGET_NO_FLOAT) \
476 builtin_define ("__mips_no_float"); \
477 else if (TARGET_HARD_FLOAT_ABI) \
478 builtin_define ("__mips_hard_float"); \
480 builtin_define ("__mips_soft_float"); \
482 if (TARGET_SINGLE_FLOAT) \
483 builtin_define ("__mips_single_float"); \
485 if (TARGET_PAIRED_SINGLE_FLOAT) \
486 builtin_define ("__mips_paired_single_float"); \
488 if (TARGET_BIG_ENDIAN) \
490 builtin_define_std ("MIPSEB"); \
491 builtin_define ("_MIPSEB"); \
495 builtin_define_std ("MIPSEL"); \
496 builtin_define ("_MIPSEL"); \
499 /* Whether calls should go through $25. The separate __PIC__ \
500 macro indicates whether abicalls code might use a GOT. */ \
501 if (TARGET_ABICALLS) \
502 builtin_define ("__mips_abicalls"); \
504 /* Whether Loongson vector modes are enabled. */ \
505 if (TARGET_LOONGSON_VECTORS) \
506 builtin_define ("__mips_loongson_vector_rev"); \
508 /* Historical Octeon macro. */ \
510 builtin_define ("__OCTEON__"); \
512 /* Macros dependent on the C dialect. */ \
513 if (preprocessing_asm_p ()) \
515 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
516 builtin_define ("_LANGUAGE_ASSEMBLY"); \
518 else if (c_dialect_cxx ()) \
520 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
521 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
522 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
526 builtin_define_std ("LANGUAGE_C"); \
527 builtin_define ("_LANGUAGE_C"); \
529 if (c_dialect_objc ()) \
531 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
532 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
533 /* Bizarre, but needed at least for Irix. */ \
534 builtin_define_std ("LANGUAGE_C"); \
535 builtin_define ("_LANGUAGE_C"); \
538 if (mips_abi == ABI_EABI) \
539 builtin_define ("__mips_eabi"); \
541 if (TARGET_CACHE_BUILTIN) \
542 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
546 /* Default target_flags if no switches are specified */
548 #ifndef TARGET_DEFAULT
549 #define TARGET_DEFAULT 0
552 #ifndef TARGET_CPU_DEFAULT
553 #define TARGET_CPU_DEFAULT 0
556 #ifndef TARGET_ENDIAN_DEFAULT
557 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
560 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
561 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
564 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
565 #ifndef MIPS_ISA_DEFAULT
566 #ifndef MIPS_CPU_STRING_DEFAULT
567 #define MIPS_CPU_STRING_DEFAULT "from-abi"
573 /* Make this compile time constant for libgcc2 */
575 #define TARGET_64BIT 1
577 #define TARGET_64BIT 0
579 #endif /* IN_LIBGCC2 */
581 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
582 when compiled with hardware floating point. This is because MIPS16
583 code cannot save and restore the floating-point registers, which is
584 important if in a mixed MIPS16/non-MIPS16 environment. */
587 #if __mips_hard_float
588 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
590 #endif /* IN_LIBGCC2 */
592 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
594 #ifndef MULTILIB_ENDIAN_DEFAULT
595 #if TARGET_ENDIAN_DEFAULT == 0
596 #define MULTILIB_ENDIAN_DEFAULT "EL"
598 #define MULTILIB_ENDIAN_DEFAULT "EB"
602 #ifndef MULTILIB_ISA_DEFAULT
603 # if MIPS_ISA_DEFAULT == 1
604 # define MULTILIB_ISA_DEFAULT "mips1"
606 # if MIPS_ISA_DEFAULT == 2
607 # define MULTILIB_ISA_DEFAULT "mips2"
609 # if MIPS_ISA_DEFAULT == 3
610 # define MULTILIB_ISA_DEFAULT "mips3"
612 # if MIPS_ISA_DEFAULT == 4
613 # define MULTILIB_ISA_DEFAULT "mips4"
615 # if MIPS_ISA_DEFAULT == 32
616 # define MULTILIB_ISA_DEFAULT "mips32"
618 # if MIPS_ISA_DEFAULT == 33
619 # define MULTILIB_ISA_DEFAULT "mips32r2"
621 # if MIPS_ISA_DEFAULT == 64
622 # define MULTILIB_ISA_DEFAULT "mips64"
624 # if MIPS_ISA_DEFAULT == 65
625 # define MULTILIB_ISA_DEFAULT "mips64r2"
627 # define MULTILIB_ISA_DEFAULT "mips1"
638 #ifndef MIPS_ABI_DEFAULT
639 #define MIPS_ABI_DEFAULT ABI_32
642 /* Use the most portable ABI flag for the ASM specs. */
644 #if MIPS_ABI_DEFAULT == ABI_32
645 #define MULTILIB_ABI_DEFAULT "mabi=32"
648 #if MIPS_ABI_DEFAULT == ABI_O64
649 #define MULTILIB_ABI_DEFAULT "mabi=o64"
652 #if MIPS_ABI_DEFAULT == ABI_N32
653 #define MULTILIB_ABI_DEFAULT "mabi=n32"
656 #if MIPS_ABI_DEFAULT == ABI_64
657 #define MULTILIB_ABI_DEFAULT "mabi=64"
660 #if MIPS_ABI_DEFAULT == ABI_EABI
661 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
664 #ifndef MULTILIB_DEFAULTS
665 #define MULTILIB_DEFAULTS \
666 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
669 /* We must pass -EL to the linker by default for little endian embedded
670 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
671 linker will default to using big-endian output files. The OUTPUT_FORMAT
672 line must be in the linker script, otherwise -EB/-EL will not work. */
675 #if TARGET_ENDIAN_DEFAULT == 0
676 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
678 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
682 /* A spec condition that matches all non-mips16 -mips arguments. */
684 #define MIPS_ISA_LEVEL_OPTION_SPEC \
685 "mips1|mips2|mips3|mips4|mips32*|mips64*"
687 /* A spec condition that matches all non-mips16 architecture arguments. */
689 #define MIPS_ARCH_OPTION_SPEC \
690 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
692 /* A spec that infers a -mips argument from an -march argument,
693 or injects the default if no architecture is specified. */
695 #define MIPS_ISA_LEVEL_SPEC \
696 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
697 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
698 %{march=mips2|march=r6000:-mips2} \
699 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
700 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
701 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
702 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
703 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
704 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
705 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
706 |march=xlr: -mips64} \
707 %{march=mips64r2|march=octeon: -mips64r2} \
708 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
710 /* A spec that infers a -mhard-float or -msoft-float setting from an
711 -march argument. Note that soft-float and hard-float code are not
714 #define MIPS_ARCH_FLOAT_SPEC \
715 "%{mhard-float|msoft-float|march=mips*:; \
716 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
717 |march=34kc|march=74kc|march=1004kc|march=5kc \
718 |march=octeon|march=xlr: -msoft-float; \
719 march=*: -mhard-float}"
721 /* A spec condition that matches 32-bit options. It only works if
722 MIPS_ISA_LEVEL_SPEC has been applied. */
724 #define MIPS_32BIT_OPTION_SPEC \
725 "mips1|mips2|mips32*|mgp32"
727 #if MIPS_ABI_DEFAULT == ABI_O64 \
728 || MIPS_ABI_DEFAULT == ABI_N32 \
729 || MIPS_ABI_DEFAULT == ABI_64
730 #define OPT_ARCH64 "mabi=32|mgp32:;"
731 #define OPT_ARCH32 "mabi=32|mgp32"
733 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
734 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
737 /* Support for a compile-time default CPU, et cetera. The rules are:
738 --with-arch is ignored if -march is specified or a -mips is specified
739 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
740 --with-tune is ignored if -mtune is specified; likewise
741 --with-tune-32 and --with-tune-64.
742 --with-abi is ignored if -mabi is specified.
743 --with-float is ignored if -mhard-float or -msoft-float are
745 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
747 #define OPTION_DEFAULT_SPECS \
748 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
749 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
750 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
751 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
752 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
753 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
754 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
755 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
756 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
757 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
758 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
759 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
762 /* A spec that infers the -mdsp setting from an -march argument. */
763 #define BASE_DRIVER_SELF_SPECS \
765 %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
766 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
768 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
770 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
771 && ISA_HAS_COND_TRAP)
773 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
775 /* True if the ABI can only work with 64-bit integer registers. We
776 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
777 otherwise floating-point registers must also be 64-bit. */
778 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
780 /* Likewise for 32-bit regs. */
781 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
783 /* True if the file format uses 64-bit symbols. At present, this is
784 only true for n64, which uses 64-bit ELF. */
785 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
787 /* True if symbols are 64 bits wide. This is usually determined by
788 the ABI's file format, but it can be overridden by -msym32. Note that
789 overriding the size with -msym32 changes the ABI of relocatable objects,
790 although it doesn't change the ABI of a fully-linked object. */
791 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
793 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
794 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
799 /* ISA has branch likely instructions (e.g. mips2). */
800 /* Disable branchlikely for tx39 until compare rewrite. They haven't
801 been generated up to this point. */
802 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
804 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
805 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
817 /* ISA has a three-operand multiplication instruction. */
818 #define ISA_HAS_DMUL3 (TARGET_64BIT \
822 /* ISA has the floating-point conditional move instructions introduced
824 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
829 && !TARGET_MIPS5500 \
832 /* ISA has the integer conditional move instructions introduced in mips4 and
833 ST Loongson 2E/2F. */
834 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
836 /* ISA has LDC1 and SDC1. */
837 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
839 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
840 branch on CC, and move (both FP and non-FP) on CC. */
841 #define ISA_HAS_8CC (ISA_MIPS4 \
847 /* This is a catch all for other mips4 instructions: indexed load, the
848 FP madd and msub instructions, and the FP recip and recip sqrt
850 #define ISA_HAS_FP4 ((ISA_MIPS4 \
851 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
856 /* ISA has paired-single instructions. */
857 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
859 /* ISA has conditional trap instructions. */
860 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
863 /* ISA has integer multiply-accumulate instructions, madd and msub. */
864 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
870 /* Integer multiply-accumulate instructions should be generated. */
871 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
873 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
874 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
876 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
877 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
879 /* ISA has floating-point nmadd and nmsub instructions
880 'd = -((a * b) [+-] c)'. */
881 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
883 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
886 && (!TARGET_MIPS5400 || TARGET_MAD) \
889 /* ISA has floating-point nmadd and nmsub instructions
890 'c = -((a * b) [+-] c)'. */
891 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
894 /* ISA has count leading zeroes/ones instruction (not implemented). */
895 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
901 /* ISA has three operand multiply instructions that put
902 the high part in an accumulator: mulhi or mulhiu. */
903 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
908 /* ISA has three operand multiply instructions that
909 negates the result and puts the result in an accumulator. */
910 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
915 /* ISA has three operand multiply instructions that subtracts the
916 result from a 4th operand and puts the result in an accumulator. */
917 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
922 /* ISA has three operand multiply instructions that the result
923 from a 4th operand and puts the result in an accumulator. */
924 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
931 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
932 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
933 || TARGET_MIPS4130) \
936 /* ISA has the "ror" (rotate right) instructions. */
937 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
942 || TARGET_SMARTMIPS) \
945 /* ISA has data prefetch instructions. This controls use of 'pref'. */
946 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
947 || TARGET_LOONGSON_2EF \
954 /* ISA has data indexed prefetch instructions. This controls use of
955 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
956 (prefx is a cop1x instruction, so can only be used if FP is
958 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
964 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
965 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
966 also requires TARGET_DOUBLE_FLOAT. */
967 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
969 /* ISA includes the MIPS32r2 seb and seh instructions. */
970 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
974 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
975 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
979 /* ISA has instructions for accessing top part of 64-bit fp regs. */
980 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
984 /* ISA has lwxs instruction (load w/scaled index address. */
985 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
987 /* The DSP ASE is available. */
988 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
990 /* Revision 2 of the DSP ASE is available. */
991 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
993 /* True if the result of a load is not available to the next instruction.
994 A nop will then be needed between instructions like "lw $4,..."
995 and "addiu $4,$4,1". */
996 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
997 && !TARGET_MIPS3900 \
1000 /* Likewise mtc1 and mfc1. */
1001 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1002 && !TARGET_LOONGSON_2EF)
1004 /* Likewise floating-point comparisons. */
1005 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1006 && !TARGET_LOONGSON_2EF)
1008 /* True if mflo and mfhi can be immediately followed by instructions
1009 which write to the HI and LO registers.
1011 According to MIPS specifications, MIPS ISAs I, II, and III need
1012 (at least) two instructions between the reads of HI/LO and
1013 instructions which write them, and later ISAs do not. Contradicting
1014 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1015 the UM for the NEC Vr5000) document needing the instructions between
1016 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1017 MIPS64 and later ISAs to have the interlocks, plus any specific
1018 earlier-ISA CPUs for which CPU documentation declares that the
1019 instructions are really interlocked. */
1020 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1024 || TARGET_MIPS5500 \
1025 || TARGET_LOONGSON_2EF)
1027 /* ISA includes synci, jr.hb and jalr.hb. */
1028 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1032 /* ISA includes sync. */
1033 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1034 #define GENERATE_SYNC \
1035 (target_flags_explicit & MASK_LLSC \
1036 ? TARGET_LLSC && !TARGET_MIPS16 \
1039 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1040 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1042 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1043 #define GENERATE_LL_SC \
1044 (target_flags_explicit & MASK_LLSC \
1045 ? TARGET_LLSC && !TARGET_MIPS16 \
1048 /* ISA includes the baddu instruction. */
1049 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1051 /* ISA includes the bbit* instructions. */
1052 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1054 /* ISA includes the cins instruction. */
1055 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1057 /* ISA includes the exts instruction. */
1058 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1060 /* ISA includes the seq and sne instructions. */
1061 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1063 /* ISA includes the pop instruction. */
1064 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1066 /* The CACHE instruction is available in non-MIPS16 code. */
1067 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1069 /* The CACHE instruction is available. */
1070 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1072 /* Add -G xx support. */
1074 #undef SWITCH_TAKES_ARG
1075 #define SWITCH_TAKES_ARG(CHAR) \
1076 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1078 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1080 /* Show we can debug even without a frame pointer. */
1081 #define CAN_DEBUG_WITHOUT_FP
1083 /* Tell collect what flags to pass to nm. */
1085 #define NM_FLAGS "-Bn"
1089 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1090 to the assembler. It may be overridden by subtargets. */
1091 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1092 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1094 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1097 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1098 the assembler. It may be overridden by subtargets.
1100 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1101 COFF debugging info. */
1103 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1104 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1105 %{g} %{g0} %{g1} %{g2} %{g3} \
1106 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1107 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1108 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1109 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1110 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1113 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1114 overridden by subtargets. */
1116 #ifndef SUBTARGET_ASM_SPEC
1117 #define SUBTARGET_ASM_SPEC ""
1122 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1123 %{mips32*} %{mips64*} \
1124 %{mips16} %{mno-mips16:-no-mips16} \
1125 %{mips3d} %{mno-mips3d:-no-mips3d} \
1126 %{mdmx} %{mno-mdmx:-no-mdmx} \
1127 %{mdsp} %{mno-dsp} \
1128 %{mdspr2} %{mno-dspr2} \
1129 %{msmartmips} %{mno-smartmips} \
1131 %{mfix-vr4120} %{mfix-vr4130} \
1132 %(subtarget_asm_optimizing_spec) \
1133 %(subtarget_asm_debugging_spec) \
1134 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1135 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1137 %{mshared} %{mno-shared} \
1138 %{msym32} %{mno-sym32} \
1140 %(subtarget_asm_spec)"
1142 /* Extra switches sometimes passed to the linker. */
1143 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1144 will interpret it as a -b option. */
1147 #define LINK_SPEC "\
1149 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1150 %{bestGnum} %{shared} %{non_shared}"
1151 #endif /* LINK_SPEC defined */
1154 /* Specs for the compiler proper */
1156 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1157 overridden by subtargets. */
1158 #ifndef SUBTARGET_CC1_SPEC
1159 #define SUBTARGET_CC1_SPEC ""
1162 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1166 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1167 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1169 %(subtarget_cc1_spec)"
1171 /* Preprocessor specs. */
1173 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1174 overridden by subtargets. */
1175 #ifndef SUBTARGET_CPP_SPEC
1176 #define SUBTARGET_CPP_SPEC ""
1179 #define CPP_SPEC "%(subtarget_cpp_spec)"
1181 /* This macro defines names of additional specifications to put in the specs
1182 that can be used in various specifications like CC1_SPEC. Its definition
1183 is an initializer with a subgrouping for each command option.
1185 Each subgrouping contains a string constant, that defines the
1186 specification name, and a string constant that used by the GCC driver
1189 Do not define this macro if it does not need to do anything. */
1191 #define EXTRA_SPECS \
1192 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1193 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1194 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1195 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1196 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1197 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1198 { "endian_spec", ENDIAN_SPEC }, \
1199 SUBTARGET_EXTRA_SPECS
1201 #ifndef SUBTARGET_EXTRA_SPECS
1202 #define SUBTARGET_EXTRA_SPECS
1205 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1206 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1208 #ifndef PREFERRED_DEBUGGING_TYPE
1209 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1212 /* The size of DWARF addresses should be the same as the size of symbols
1213 in the target file format. They shouldn't depend on things like -msym32,
1214 because many DWARF consumers do not allow the mixture of address sizes
1215 that one would then get from linking -msym32 code with -msym64 code.
1217 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1218 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1219 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1221 /* By default, turn on GDB extensions. */
1222 #define DEFAULT_GDB_EXTENSIONS 1
1224 /* Local compiler-generated symbols must have a prefix that the assembler
1225 understands. By default, this is $, although some targets (e.g.,
1226 NetBSD-ELF) need to override this. */
1228 #ifndef LOCAL_LABEL_PREFIX
1229 #define LOCAL_LABEL_PREFIX "$"
1232 /* By default on the mips, external symbols do not have an underscore
1233 prepended, but some targets (e.g., NetBSD) require this. */
1235 #ifndef USER_LABEL_PREFIX
1236 #define USER_LABEL_PREFIX ""
1239 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1240 since the length can run past this up to a continuation point. */
1241 #undef DBX_CONTIN_LENGTH
1242 #define DBX_CONTIN_LENGTH 1500
1244 /* How to renumber registers for dbx and gdb. */
1245 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1247 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1248 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1250 /* The DWARF 2 CFA column which tracks the return address. */
1251 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1253 /* Before the prologue, RA lives in r31. */
1254 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1256 /* Describe how we implement __builtin_eh_return. */
1257 #define EH_RETURN_DATA_REGNO(N) \
1258 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1260 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1262 #define EH_USES(N) mips_eh_uses (N)
1264 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1265 The default for this in 64-bit mode is 8, which causes problems with
1266 SFmode register saves. */
1267 #define DWARF_CIE_DATA_ALIGNMENT -4
1269 /* Correct the offset of automatic variables and arguments. Note that
1270 the MIPS debug format wants all automatic variables and arguments
1271 to be in terms of the virtual frame pointer (stack pointer before
1272 any adjustment in the function), while the MIPS 3.0 linker wants
1273 the frame pointer to be the stack pointer after the initial
1276 #define DEBUGGER_AUTO_OFFSET(X) \
1277 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1278 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1279 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1281 /* Target machine storage layout */
1283 #define BITS_BIG_ENDIAN 0
1284 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1285 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1287 /* Define this to set the endianness to use in libgcc2.c, which can
1288 not depend on target_flags. */
1289 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1290 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1292 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1295 #define MAX_BITS_PER_WORD 64
1297 /* Width of a word, in units (bytes). */
1298 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1300 #define MIN_UNITS_PER_WORD 4
1303 /* For MIPS, width of a floating point register. */
1304 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1306 /* The number of consecutive floating-point registers needed to store the
1307 largest format supported by the FPU. */
1308 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1310 /* The number of consecutive floating-point registers needed to store the
1311 smallest format supported by the FPU. */
1312 #define MIN_FPRS_PER_FMT \
1313 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1314 ? 1 : MAX_FPRS_PER_FMT)
1316 /* The largest size of value that can be held in floating-point
1317 registers and moved with a single instruction. */
1318 #define UNITS_PER_HWFPVALUE \
1319 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1321 /* The largest size of value that can be held in floating-point
1323 #define UNITS_PER_FPVALUE \
1324 (TARGET_SOFT_FLOAT_ABI ? 0 \
1325 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1326 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1328 /* The number of bytes in a double. */
1329 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1331 /* Set the sizes of the core types. */
1332 #define SHORT_TYPE_SIZE 16
1333 #define INT_TYPE_SIZE 32
1334 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1335 #define LONG_LONG_TYPE_SIZE 64
1337 #define FLOAT_TYPE_SIZE 32
1338 #define DOUBLE_TYPE_SIZE 64
1339 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1341 /* Define the sizes of fixed-point types. */
1342 #define SHORT_FRACT_TYPE_SIZE 8
1343 #define FRACT_TYPE_SIZE 16
1344 #define LONG_FRACT_TYPE_SIZE 32
1345 #define LONG_LONG_FRACT_TYPE_SIZE 64
1347 #define SHORT_ACCUM_TYPE_SIZE 16
1348 #define ACCUM_TYPE_SIZE 32
1349 #define LONG_ACCUM_TYPE_SIZE 64
1350 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1351 doesn't support 128-bit integers for MIPS32 currently. */
1352 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1354 /* long double is not a fixed mode, but the idea is that, if we
1355 support long double, we also want a 128-bit integer type. */
1356 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1359 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1360 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1361 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1363 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1367 /* Width in bits of a pointer. */
1368 #ifndef POINTER_SIZE
1369 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1372 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1373 #define PARM_BOUNDARY BITS_PER_WORD
1375 /* Allocation boundary (in *bits*) for the code of a function. */
1376 #define FUNCTION_BOUNDARY 32
1378 /* Alignment of field after `int : 0' in a structure. */
1379 #define EMPTY_FIELD_BOUNDARY 32
1381 /* Every structure's size must be a multiple of this. */
1382 /* 8 is observed right on a DECstation and on riscos 4.02. */
1383 #define STRUCTURE_SIZE_BOUNDARY 8
1385 /* There is no point aligning anything to a rounder boundary than this. */
1386 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1388 /* All accesses must be aligned. */
1389 #define STRICT_ALIGNMENT 1
1391 /* Define this if you wish to imitate the way many other C compilers
1392 handle alignment of bitfields and the structures that contain
1395 The behavior is that the type written for a bit-field (`int',
1396 `short', or other integer type) imposes an alignment for the
1397 entire structure, as if the structure really did contain an
1398 ordinary field of that type. In addition, the bit-field is placed
1399 within the structure so that it would fit within such a field,
1400 not crossing a boundary for it.
1402 Thus, on most machines, a bit-field whose type is written as `int'
1403 would not cross a four-byte boundary, and would force four-byte
1404 alignment for the whole structure. (The alignment used may not
1405 be four bytes; it is controlled by the other alignment
1408 If the macro is defined, its definition should be a C expression;
1409 a nonzero value for the expression enables this behavior. */
1411 #define PCC_BITFIELD_TYPE_MATTERS 1
1413 /* If defined, a C expression to compute the alignment given to a
1414 constant that is being placed in memory. CONSTANT is the constant
1415 and ALIGN is the alignment that the object would ordinarily have.
1416 The value of this macro is used instead of that alignment to align
1419 If this macro is not defined, then ALIGN is used.
1421 The typical use of this macro is to increase alignment for string
1422 constants to be word aligned so that `strcpy' calls that copy
1423 constants can be done inline. */
1425 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1426 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1427 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1429 /* If defined, a C expression to compute the alignment for a static
1430 variable. TYPE is the data type, and ALIGN is the alignment that
1431 the object would ordinarily have. The value of this macro is used
1432 instead of that alignment to align the object.
1434 If this macro is not defined, then ALIGN is used.
1436 One use of this macro is to increase alignment of medium-size
1437 data to make it all fit in fewer cache lines. Another is to
1438 cause character arrays to be word-aligned so that `strcpy' calls
1439 that copy constants to character arrays can be done inline. */
1441 #undef DATA_ALIGNMENT
1442 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1443 ((((ALIGN) < BITS_PER_WORD) \
1444 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1445 || TREE_CODE (TYPE) == UNION_TYPE \
1446 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1448 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1449 character arrays to be word-aligned so that `strcpy' calls that copy
1450 constants to character arrays can be done inline, and 'strcmp' can be
1451 optimised to use word loads. */
1452 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1453 DATA_ALIGNMENT (TYPE, ALIGN)
1455 #define PAD_VARARGS_DOWN \
1456 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1458 /* Define if operations between registers always perform the operation
1459 on the full register even if a narrower mode is specified. */
1460 #define WORD_REGISTER_OPERATIONS
1462 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1463 moves. All other references are zero extended. */
1464 #define LOAD_EXTEND_OP(MODE) \
1465 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1466 ? SIGN_EXTEND : ZERO_EXTEND)
1468 /* Define this macro if it is advisable to hold scalars in registers
1469 in a wider mode than that declared by the program. In such cases,
1470 the value is constrained to be within the bounds of the declared
1471 type, but kept valid in the wider mode. The signedness of the
1472 extension may differ from that of the type. */
1474 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1475 if (GET_MODE_CLASS (MODE) == MODE_INT \
1476 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1478 if ((MODE) == SImode) \
1483 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1484 Extensions of pointers to word_mode must be signed. */
1485 #define POINTERS_EXTEND_UNSIGNED false
1487 /* Define if loading short immediate values into registers sign extends. */
1488 #define SHORT_IMMEDIATES_SIGN_EXTEND
1490 /* The [d]clz instructions have the natural values at 0. */
1492 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1493 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1495 /* Standard register usage. */
1497 /* Number of hardware registers. We have:
1499 - 32 integer registers
1500 - 32 floating point registers
1501 - 8 condition code registers
1502 - 2 accumulator registers (hi and lo)
1503 - 32 registers each for coprocessors 0, 2 and 3
1505 - ARG_POINTER_REGNUM
1506 - FRAME_POINTER_REGNUM
1507 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1508 - CPRESTORE_SLOT_REGNUM
1509 - 2 dummy entries that were used at various times in the past.
1510 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1511 - 6 DSP control registers */
1513 #define FIRST_PSEUDO_REGISTER 188
1515 /* By default, fix the kernel registers ($26 and $27), the global
1516 pointer ($28) and the stack pointer ($29). This can change
1517 depending on the command-line options.
1519 Regarding coprocessor registers: without evidence to the contrary,
1520 it's best to assume that each coprocessor register has a unique
1521 use. This can be overridden, in, e.g., mips_option_override or
1522 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1523 for a particular target. */
1525 #define FIXED_REGISTERS \
1527 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1531 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1532 /* COP0 registers */ \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1535 /* COP2 registers */ \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1538 /* COP3 registers */ \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1541 /* 6 DSP accumulator registers & 6 control registers */ \
1542 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1546 /* Set up this array for o32 by default.
1548 Note that we don't mark $31 as a call-clobbered register. The idea is
1549 that it's really the call instructions themselves which clobber $31.
1550 We don't care what the called function does with it afterwards.
1552 This approach makes it easier to implement sibcalls. Unlike normal
1553 calls, sibcalls don't clobber $31, so the register reaches the
1554 called function in tact. EPILOGUE_USES says that $31 is useful
1555 to the called function. */
1557 #define CALL_USED_REGISTERS \
1559 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1560 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1562 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 /* COP0 registers */ \
1565 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 /* COP2 registers */ \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1570 /* COP3 registers */ \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 /* 6 DSP accumulator registers & 6 control registers */ \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1578 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1580 #define CALL_REALLY_USED_REGISTERS \
1581 { /* General registers. */ \
1582 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1583 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1584 /* Floating-point registers. */ \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1586 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1589 /* COP0 registers */ \
1590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1591 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1592 /* COP2 registers */ \
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1595 /* COP3 registers */ \
1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1597 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1598 /* 6 DSP accumulator registers & 6 control registers */ \
1599 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1602 /* Internal macros to classify a register number as to whether it's a
1603 general purpose register, a floating point register, a
1604 multiply/divide register, or a status register. */
1606 #define GP_REG_FIRST 0
1607 #define GP_REG_LAST 31
1608 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1609 #define GP_DBX_FIRST 0
1610 #define K0_REG_NUM (GP_REG_FIRST + 26)
1611 #define K1_REG_NUM (GP_REG_FIRST + 27)
1612 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1614 #define FP_REG_FIRST 32
1615 #define FP_REG_LAST 63
1616 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1617 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1619 #define MD_REG_FIRST 64
1620 #define MD_REG_LAST 65
1621 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1622 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1624 /* The DWARF 2 CFA column which tracks the return address from a
1625 signal handler context. This means that to maintain backwards
1626 compatibility, no hard register can be assigned this column if it
1627 would need to be handled by the DWARF unwinder. */
1628 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1630 #define ST_REG_FIRST 67
1631 #define ST_REG_LAST 74
1632 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1635 /* FIXME: renumber. */
1636 #define COP0_REG_FIRST 80
1637 #define COP0_REG_LAST 111
1638 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1640 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1641 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1642 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1644 #define COP2_REG_FIRST 112
1645 #define COP2_REG_LAST 143
1646 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1648 #define COP3_REG_FIRST 144
1649 #define COP3_REG_LAST 175
1650 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1651 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1652 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1654 #define DSP_ACC_REG_FIRST 176
1655 #define DSP_ACC_REG_LAST 181
1656 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1658 #define AT_REGNUM (GP_REG_FIRST + 1)
1659 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1660 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1662 /* A few bitfield locations for the coprocessor registers. */
1663 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1664 the cause register for the EIC interrupt mode. */
1665 #define CAUSE_IPL 10
1666 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1668 /* Exception Level is at bit 1 of the status register. */
1670 /* Interrupt Enable is at bit 0 of the status register. */
1673 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1674 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1675 should be used instead. */
1676 #define FPSW_REGNUM ST_REG_FIRST
1678 #define GP_REG_P(REGNO) \
1679 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1680 #define M16_REG_P(REGNO) \
1681 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1682 #define FP_REG_P(REGNO) \
1683 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1684 #define MD_REG_P(REGNO) \
1685 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1686 #define ST_REG_P(REGNO) \
1687 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1688 #define COP0_REG_P(REGNO) \
1689 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1690 #define COP2_REG_P(REGNO) \
1691 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1692 #define COP3_REG_P(REGNO) \
1693 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1694 #define ALL_COP_REG_P(REGNO) \
1695 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1696 /* Test if REGNO is one of the 6 new DSP accumulators. */
1697 #define DSP_ACC_REG_P(REGNO) \
1698 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1699 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1700 #define ACC_REG_P(REGNO) \
1701 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1703 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1705 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1706 to initialize the mips16 gp pseudo register. */
1707 #define CONST_GP_P(X) \
1708 (GET_CODE (X) == CONST \
1709 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1710 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1712 /* Return coprocessor number from register number. */
1714 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1715 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1716 : COP3_REG_P (REGNO) ? '3' : '?')
1719 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1721 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1722 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1724 #define MODES_TIEABLE_P mips_modes_tieable_p
1726 /* Register to use for pushing function arguments. */
1727 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1729 /* These two registers don't really exist: they get eliminated to either
1730 the stack or hard frame pointer. */
1731 #define ARG_POINTER_REGNUM 77
1732 #define FRAME_POINTER_REGNUM 78
1734 /* $30 is not available on the mips16, so we use $17 as the frame
1736 #define HARD_FRAME_POINTER_REGNUM \
1737 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1739 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1740 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1742 /* Register in which static-chain is passed to a function. */
1743 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1745 /* Registers used as temporaries in prologue/epilogue code:
1747 - If a MIPS16 PIC function needs access to _gp, it first loads
1748 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1750 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1751 register. The register must not conflict with MIPS16_PIC_TEMP.
1753 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1756 If we're generating MIPS16 code, these registers must come from the
1757 core set of 8. The prologue registers mustn't conflict with any
1758 incoming arguments, the static chain pointer, or the frame pointer.
1759 The epilogue temporary mustn't conflict with the return registers,
1760 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1761 or the EH data registers.
1763 If we're generating interrupt handlers, we use K0 as a temporary register
1764 in prologue/epilogue code. */
1766 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1767 #define MIPS_PROLOGUE_TEMP_REGNUM \
1768 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1769 #define MIPS_EPILOGUE_TEMP_REGNUM \
1770 (cfun->machine->interrupt_handler_p \
1772 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1774 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1775 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1776 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1778 /* Define this macro if it is as good or better to call a constant
1779 function address than to call an address kept in a register. */
1780 #define NO_FUNCTION_CSE 1
1782 /* The ABI-defined global pointer. Sometimes we use a different
1783 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1784 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1786 /* We normally use $28 as the global pointer. However, when generating
1787 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1788 register instead. They can then avoid saving and restoring $28
1789 and perhaps avoid using a frame at all.
1791 When a leaf function uses something other than $28, mips_expand_prologue
1792 will modify pic_offset_table_rtx in place. Take the register number
1793 from there after reload. */
1794 #define PIC_OFFSET_TABLE_REGNUM \
1795 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1797 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1799 /* Define the classes of registers for register constraints in the
1800 machine description. Also define ranges of constants.
1802 One of the classes must always be named ALL_REGS and include all hard regs.
1803 If there is more than one class, another class must be named NO_REGS
1804 and contain no registers.
1806 The name GENERAL_REGS must be the name of a class (or an alias for
1807 another name such as ALL_REGS). This is the class of registers
1808 that is allowed by "g" or "r" in a register constraint.
1809 Also, registers outside this class are allocated only when
1810 instructions express preferences for them.
1812 The classes must be numbered in nondecreasing order; that is,
1813 a larger-numbered class must never be contained completely
1814 in a smaller-numbered class.
1816 For any two classes, it is very desirable that there be another
1817 class that represents their union. */
1821 NO_REGS, /* no registers in set */
1822 M16_REGS, /* mips16 directly accessible registers */
1823 T_REG, /* mips16 T register ($24) */
1824 M16_T_REGS, /* mips16 registers plus T register */
1825 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1826 V1_REG, /* Register $v1 ($3) used for TLS access. */
1827 LEA_REGS, /* Every GPR except $25 */
1828 GR_REGS, /* integer registers */
1829 FP_REGS, /* floating point registers */
1830 MD0_REG, /* first multiply/divide register */
1831 MD1_REG, /* second multiply/divide register */
1832 MD_REGS, /* multiply/divide registers (hi/lo) */
1833 COP0_REGS, /* generic coprocessor classes */
1836 ST_REGS, /* status registers (fp status) */
1837 DSP_ACC_REGS, /* DSP accumulator registers */
1838 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1839 FRAME_REGS, /* $arg and $frame */
1840 GR_AND_MD0_REGS, /* union classes */
1844 ALL_REGS, /* all registers */
1845 LIM_REG_CLASSES /* max value + 1 */
1848 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1850 #define GENERAL_REGS GR_REGS
1852 /* An initializer containing the names of the register classes as C
1853 string constants. These names are used in writing some of the
1856 #define REG_CLASS_NAMES \
1862 "PIC_FN_ADDR_REG", \
1870 /* coprocessor registers */ \
1878 "GR_AND_MD0_REGS", \
1879 "GR_AND_MD1_REGS", \
1881 "GR_AND_ACC_REGS", \
1885 /* An initializer containing the contents of the register classes,
1886 as integers which are bit masks. The Nth integer specifies the
1887 contents of class N. The way the integer MASK is interpreted is
1888 that register R is in the class if `MASK & (1 << R)' is 1.
1890 When the machine has more than 32 registers, an integer does not
1891 suffice. Then the integers are replaced by sub-initializers,
1892 braced groupings containing several integers. Each
1893 sub-initializer must be suitable as an initializer for the type
1894 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1896 #define REG_CLASS_CONTENTS \
1898 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1899 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1900 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1901 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1902 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1903 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1904 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1905 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1906 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1907 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1908 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1909 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1910 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1911 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1912 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1913 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1914 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1915 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1916 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1917 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1918 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1919 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1920 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1921 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1925 /* A C expression whose value is a register class containing hard
1926 register REGNO. In general there is more that one such class;
1927 choose a class which is "minimal", meaning that no smaller class
1928 also contains the register. */
1930 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1932 /* A macro whose definition is the name of the class to which a
1933 valid base register must belong. A base register is one used in
1934 an address which is the register value plus a displacement. */
1936 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1938 /* A macro whose definition is the name of the class to which a
1939 valid index register must belong. An index register is one used
1940 in an address where its value is either multiplied by a scale
1941 factor or added to another register (as well as added to a
1944 #define INDEX_REG_CLASS NO_REGS
1946 /* We generally want to put call-clobbered registers ahead of
1947 call-saved ones. (IRA expects this.) */
1949 #define REG_ALLOC_ORDER \
1950 { /* Accumulator registers. When GPRs and accumulators have equal \
1951 cost, we generally prefer to use accumulators. For example, \
1952 a division of multiplication result is better allocated to LO, \
1953 so that we put the MFLO at the point of use instead of at the \
1954 point of definition. It's also needed if we're to take advantage \
1955 of the extra accumulators available with -mdspr2. In some cases, \
1956 it can also help to reduce register pressure. */ \
1957 64, 65,176,177,178,179,180,181, \
1958 /* Call-clobbered GPRs. */ \
1959 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1961 /* The global pointer. This is call-clobbered for o32 and o64 \
1962 abicalls, call-saved for n32 and n64 abicalls, and a program \
1963 invariant otherwise. Putting it between the call-clobbered \
1964 and call-saved registers should cope with all eventualities. */ \
1966 /* Call-saved GPRs. */ \
1967 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1968 /* GPRs that can never be exposed to the register allocator. */ \
1970 /* Call-clobbered FPRs. */ \
1971 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1973 /* FPRs that are usually call-saved. The odd ones are actually \
1974 call-clobbered for n32, but listing them ahead of the even \
1975 registers might encourage the register allocator to fragment \
1976 the available FPR pairs. We need paired FPRs to store long \
1977 doubles, so it isn't clear that using a different order \
1978 for n32 would be a win. */ \
1979 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1980 /* None of the remaining classes have defined call-saved \
1982 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1983 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1984 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1985 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1986 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1987 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1988 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1989 182,183,184,185,186,187 \
1992 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1993 to be rearranged based on a particular function. On the mips16, we
1994 want to allocate $24 (T_REG) before other registers for
1995 instructions for which it is possible. */
1997 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1999 /* True if VALUE is an unsigned 6-bit number. */
2001 #define UIMM6_OPERAND(VALUE) \
2002 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2004 /* True if VALUE is a signed 10-bit number. */
2006 #define IMM10_OPERAND(VALUE) \
2007 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2009 /* True if VALUE is a signed 16-bit number. */
2011 #define SMALL_OPERAND(VALUE) \
2012 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2014 /* True if VALUE is an unsigned 16-bit number. */
2016 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2017 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2019 /* True if VALUE can be loaded into a register using LUI. */
2021 #define LUI_OPERAND(VALUE) \
2022 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2023 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2025 /* Return a value X with the low 16 bits clear, and such that
2026 VALUE - X is a signed 16-bit value. */
2028 #define CONST_HIGH_PART(VALUE) \
2029 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2031 #define CONST_LOW_PART(VALUE) \
2032 ((VALUE) - CONST_HIGH_PART (VALUE))
2034 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2035 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2036 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2038 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2039 mips_preferred_reload_class (X, CLASS)
2041 /* The HI and LO registers can only be reloaded via the general
2042 registers. Condition code registers can only be loaded to the
2043 general registers, and from the floating point registers. */
2045 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2046 mips_secondary_reload_class (CLASS, MODE, X, true)
2047 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2048 mips_secondary_reload_class (CLASS, MODE, X, false)
2050 /* Return the maximum number of consecutive registers
2051 needed to represent mode MODE in a register of class CLASS. */
2053 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2055 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2056 mips_cannot_change_mode_class (FROM, TO, CLASS)
2058 /* Stack layout; function entry, exit and calling. */
2060 #define STACK_GROWS_DOWNWARD
2062 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2064 /* Size of the area allocated in the frame to save the GP. */
2066 #define MIPS_GP_SAVE_AREA_SIZE \
2067 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2069 /* The offset of the first local variable from the frame pointer. See
2070 mips_compute_frame_info for details about the frame layout. */
2072 #define STARTING_FRAME_OFFSET \
2073 (FRAME_GROWS_DOWNWARD \
2075 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2077 #define RETURN_ADDR_RTX mips_return_addr
2079 /* Mask off the MIPS16 ISA bit in unwind addresses.
2081 The reason for this is a little subtle. When unwinding a call,
2082 we are given the call's return address, which on most targets
2083 is the address of the following instruction. However, what we
2084 actually want to find is the EH region for the call itself.
2085 The target-independent unwind code therefore searches for "RA - 1".
2087 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2088 RA - 1 is therefore the real (even-valued) start of the return
2089 instruction. EH region labels are usually odd-valued MIPS16 symbols
2090 too, so a search for an even address within a MIPS16 region would
2093 However, there is an exception. If the end of an EH region is also
2094 the end of a function, the end label is allowed to be even. This is
2095 necessary because a following non-MIPS16 function may also need EH
2096 information for its first instruction.
2098 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2099 non-ISA-encoded address. This probably isn't ideal, but it is
2100 the traditional (legacy) behavior. It is therefore only safe
2101 to search MIPS EH regions for an _odd-valued_ address.
2103 Masking off the ISA bit means that the target-independent code
2104 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2105 #define MASK_RETURN_ADDR GEN_INT (-2)
2108 /* Similarly, don't use the least-significant bit to tell pointers to
2109 code from vtable index. */
2111 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2113 /* The eliminations to $17 are only used for mips16 code. See the
2114 definition of HARD_FRAME_POINTER_REGNUM. */
2116 #define ELIMINABLE_REGS \
2117 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2118 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2119 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2120 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2121 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2122 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2124 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2125 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2127 /* Allocate stack space for arguments at the beginning of each function. */
2128 #define ACCUMULATE_OUTGOING_ARGS 1
2130 /* The argument pointer always points to the first argument. */
2131 #define FIRST_PARM_OFFSET(FNDECL) 0
2133 /* o32 and o64 reserve stack space for all argument registers. */
2134 #define REG_PARM_STACK_SPACE(FNDECL) \
2136 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2139 /* Define this if it is the responsibility of the caller to
2140 allocate the area reserved for arguments passed in registers.
2141 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2142 of this macro is to determine whether the space is included in
2143 `crtl->outgoing_args_size'. */
2144 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2146 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2148 /* Symbolic macros for the registers used to return integer and floating
2151 #define GP_RETURN (GP_REG_FIRST + 2)
2152 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2154 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2156 /* Symbolic macros for the first/last argument registers. */
2158 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2159 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2160 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2161 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2163 #define LIBCALL_VALUE(MODE) \
2164 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2166 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2167 mips_function_value (VALTYPE, FUNC, VOIDmode)
2169 /* 1 if N is a possible register number for a function value.
2170 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2171 Currently, R2 and F0 are only implemented here (C has no complex type) */
2173 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2174 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2175 && (N) == FP_RETURN + 2))
2177 /* 1 if N is a possible register number for function argument passing.
2178 We have no FP argument registers when soft-float. When FP registers
2179 are 32 bits, we can't directly reference the odd numbered ones. */
2181 #define FUNCTION_ARG_REGNO_P(N) \
2182 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2183 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2186 /* This structure has to cope with two different argument allocation
2187 schemes. Most MIPS ABIs view the arguments as a structure, of which
2188 the first N words go in registers and the rest go on the stack. If I
2189 < N, the Ith word might go in Ith integer argument register or in a
2190 floating-point register. For these ABIs, we only need to remember
2191 the offset of the current argument into the structure.
2193 The EABI instead allocates the integer and floating-point arguments
2194 separately. The first N words of FP arguments go in FP registers,
2195 the rest go on the stack. Likewise, the first N words of the other
2196 arguments go in integer registers, and the rest go on the stack. We
2197 need to maintain three counts: the number of integer registers used,
2198 the number of floating-point registers used, and the number of words
2199 passed on the stack.
2201 We could keep separate information for the two ABIs (a word count for
2202 the standard ABIs, and three separate counts for the EABI). But it
2203 seems simpler to view the standard ABIs as forms of EABI that do not
2204 allocate floating-point registers.
2206 So for the standard ABIs, the first N words are allocated to integer
2207 registers, and mips_function_arg decides on an argument-by-argument
2208 basis whether that argument should really go in an integer register,
2209 or in a floating-point one. */
2211 typedef struct mips_args {
2212 /* Always true for varargs functions. Otherwise true if at least
2213 one argument has been passed in an integer register. */
2216 /* The number of arguments seen so far. */
2217 unsigned int arg_number;
2219 /* The number of integer registers used so far. For all ABIs except
2220 EABI, this is the number of words that have been added to the
2221 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2222 unsigned int num_gprs;
2224 /* For EABI, the number of floating-point registers used so far. */
2225 unsigned int num_fprs;
2227 /* The number of words passed on the stack. */
2228 unsigned int stack_words;
2230 /* On the mips16, we need to keep track of which floating point
2231 arguments were passed in general registers, but would have been
2232 passed in the FP regs if this were a 32-bit function, so that we
2233 can move them to the FP regs if we wind up calling a 32-bit
2234 function. We record this information in fp_code, encoded in base
2235 four. A zero digit means no floating point argument, a one digit
2236 means an SFmode argument, and a two digit means a DFmode argument,
2237 and a three digit is not used. The low order digit is the first
2238 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2239 an SFmode argument. ??? A more sophisticated approach will be
2240 needed if MIPS_ABI != ABI_32. */
2243 /* True if the function has a prototype. */
2247 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2248 for a call to a function whose data type is FNTYPE.
2249 For a library call, FNTYPE is 0. */
2251 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2252 mips_init_cumulative_args (&CUM, FNTYPE)
2254 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2256 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2257 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2259 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2260 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2262 /* True if using EABI and varargs can be passed in floating-point
2263 registers. Under these conditions, we need a more complex form
2264 of va_list, which tracks GPR, FPR and stack arguments separately. */
2265 #define EABI_FLOAT_VARARGS_P \
2266 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2269 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2271 /* Treat LOC as a byte offset from the stack pointer and round it up
2272 to the next fully-aligned offset. */
2273 #define MIPS_STACK_ALIGN(LOC) \
2274 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2277 /* Output assembler code to FILE to increment profiler label # LABELNO
2278 for profiling a function entry. */
2280 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2282 /* The profiler preserves all interesting registers, including $31. */
2283 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2285 /* No mips port has ever used the profiler counter word, so don't emit it
2286 or the label for it. */
2288 #define NO_PROFILE_COUNTERS 1
2290 /* Define this macro if the code for function profiling should come
2291 before the function prologue. Normally, the profiling code comes
2294 /* #define PROFILE_BEFORE_PROLOGUE */
2296 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2297 the stack pointer does not matter. The value is tested only in
2298 functions that have frame pointers.
2299 No definition is equivalent to always zero. */
2301 #define EXIT_IGNORE_STACK 1
2304 /* Trampolines are a block of code followed by two pointers. */
2306 #define TRAMPOLINE_SIZE \
2307 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2309 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2310 pointers from a single LUI base. */
2312 #define TRAMPOLINE_ALIGNMENT 64
2314 /* mips_trampoline_init calls this library function to flush
2315 program and data caches. */
2317 #ifndef CACHE_FLUSH_FUNC
2318 #define CACHE_FLUSH_FUNC "_flush_cache"
2321 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2322 /* Flush both caches. We need to flush the data cache in case \
2323 the system has a write-back cache. */ \
2324 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2325 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2326 GEN_INT (3), TYPE_MODE (integer_type_node))
2329 /* Addressing modes, and classification of registers for them. */
2331 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2332 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2333 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2335 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2336 and check its validity for a certain class.
2337 We have two alternate definitions for each of them.
2338 The usual definition accepts all pseudo regs; the other rejects them all.
2339 The symbol REG_OK_STRICT causes the latter definition to be used.
2341 Most source files want to accept pseudo regs in the hope that
2342 they will get allocated to the class that the insn wants them to be in.
2343 Some source files that are used after register allocation
2344 need to be strict. */
2346 #ifndef REG_OK_STRICT
2347 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2348 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2350 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2351 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2354 #define REG_OK_FOR_INDEX_P(X) 0
2357 /* Maximum number of registers that can appear in a valid memory address. */
2359 #define MAX_REGS_PER_ADDRESS 1
2361 /* Check for constness inline but use mips_legitimate_address_p
2362 to check whether a constant really is an address. */
2364 #define CONSTANT_ADDRESS_P(X) \
2365 (CONSTANT_P (X) && memory_address_p (SImode, X))
2367 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2369 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2370 'the start of the function that this code is output in'. */
2372 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2373 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2374 asm_fprintf ((FILE), "%U%s", \
2375 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2377 asm_fprintf ((FILE), "%U%s", (NAME))
2379 /* Flag to mark a function decl symbol that requires a long call. */
2380 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2381 #define SYMBOL_REF_LONG_CALL_P(X) \
2382 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2384 /* This flag marks functions that cannot be lazily bound. */
2385 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2386 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2387 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2389 /* True if we're generating a form of MIPS16 code in which jump tables
2390 are stored in the text section and encoded as 16-bit PC-relative
2391 offsets. This is only possible when general text loads are allowed,
2392 since the table access itself will be an "lh" instruction. */
2393 /* ??? 16-bit offsets can overflow in large functions. */
2394 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2396 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2398 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2400 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2402 /* Define this as 1 if `char' should by default be signed; else as 0. */
2403 #ifndef DEFAULT_SIGNED_CHAR
2404 #define DEFAULT_SIGNED_CHAR 1
2407 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2408 we generally don't want to use them for copying arbitrary data.
2409 A single N-word move is usually the same cost as N single-word moves. */
2410 #define MOVE_MAX UNITS_PER_WORD
2411 #define MAX_MOVE_MAX 8
2413 /* Define this macro as a C expression which is nonzero if
2414 accessing less than a word of memory (i.e. a `char' or a
2415 `short') is no faster than accessing a word of memory, i.e., if
2416 such access require more than one instruction or if there is no
2417 difference in cost between byte and (aligned) word loads.
2419 On RISC machines, it tends to generate better code to define
2420 this as 1, since it avoids making a QI or HI mode register.
2422 But, generating word accesses for -mips16 is generally bad as shifts
2423 (often extended) would be needed for byte accesses. */
2424 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2426 /* Standard MIPS integer shifts truncate the shift amount to the
2427 width of the shifted operand. However, Loongson vector shifts
2428 do not truncate the shift amount at all. */
2429 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_2EF)
2431 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2432 is done just by pretending it is already truncated. */
2433 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2434 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2437 /* Specify the machine mode that pointers have.
2438 After generation of rtl, the compiler makes no further distinction
2439 between pointers and any other objects of this machine mode. */
2442 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2445 /* Give call MEMs SImode since it is the "most permissive" mode
2446 for both 32-bit and 64-bit targets. */
2448 #define FUNCTION_MODE SImode
2452 /* Define if copies to/from condition code registers should be avoided.
2454 This is needed for the MIPS because reload_outcc is not complete;
2455 it needs to handle cases where the source is a general or another
2456 condition code register. */
2457 #define AVOID_CCMODE_COPIES
2459 /* A C expression for the cost of a branch instruction. A value of
2460 1 is the default; other values are interpreted relative to that. */
2462 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2463 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2465 /* If defined, modifies the length assigned to instruction INSN as a
2466 function of the context in which it is used. LENGTH is an lvalue
2467 that contains the initially computed length of the insn and should
2468 be updated with the correct length of the insn. */
2469 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2470 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2472 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2473 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2475 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2476 "%*" OPCODE "%?\t" OPERANDS "%/"
2478 /* Return an asm string that forces INSN to be treated as an absolute
2479 J or JAL instruction instead of an assembler macro. */
2480 #define MIPS_ABSOLUTE_JUMP(INSN) \
2481 (TARGET_ABICALLS_PIC2 \
2482 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2485 /* Return the asm template for a call. INSN is the instruction's mnemonic
2486 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2487 number of the target. SIZE_OPNO is the operand number of the argument size
2488 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2489 -1 and the call is indirect, use the function symbol from the call
2490 attributes to attach a R_MIPS_JALR relocation to the call.
2492 When generating GOT code without explicit relocation operators,
2493 all calls should use assembly macros. Otherwise, all indirect
2494 calls should use "jr" or "jalr"; we will arrange to restore $gp
2495 afterwards if necessary. Finally, we can only generate direct
2496 calls for -mabicalls by temporarily switching to non-PIC mode. */
2497 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2498 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2499 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2500 : (REG_P (OPERANDS[TARGET_OPNO]) \
2501 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2502 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2503 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2504 : REG_P (OPERANDS[TARGET_OPNO]) \
2505 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2506 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2508 /* Control the assembler format that we output. */
2510 /* Output to assembler file text saying following lines
2511 may contain character constants, extra white space, comments, etc. */
2514 #define ASM_APP_ON " #APP\n"
2517 /* Output to assembler file text saying following lines
2518 no longer contain unusual constructs. */
2521 #define ASM_APP_OFF " #NO_APP\n"
2524 #define REGISTER_NAMES \
2525 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2526 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2527 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2528 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2529 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2530 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2531 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2532 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2533 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2534 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2535 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2536 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2537 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2538 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2539 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2540 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2541 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2542 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2543 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2544 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2545 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2546 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2547 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2548 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2550 /* List the "software" names for each register. Also list the numerical
2551 names for $fp and $sp. */
2553 #define ADDITIONAL_REGISTER_NAMES \
2555 { "$29", 29 + GP_REG_FIRST }, \
2556 { "$30", 30 + GP_REG_FIRST }, \
2557 { "at", 1 + GP_REG_FIRST }, \
2558 { "v0", 2 + GP_REG_FIRST }, \
2559 { "v1", 3 + GP_REG_FIRST }, \
2560 { "a0", 4 + GP_REG_FIRST }, \
2561 { "a1", 5 + GP_REG_FIRST }, \
2562 { "a2", 6 + GP_REG_FIRST }, \
2563 { "a3", 7 + GP_REG_FIRST }, \
2564 { "t0", 8 + GP_REG_FIRST }, \
2565 { "t1", 9 + GP_REG_FIRST }, \
2566 { "t2", 10 + GP_REG_FIRST }, \
2567 { "t3", 11 + GP_REG_FIRST }, \
2568 { "t4", 12 + GP_REG_FIRST }, \
2569 { "t5", 13 + GP_REG_FIRST }, \
2570 { "t6", 14 + GP_REG_FIRST }, \
2571 { "t7", 15 + GP_REG_FIRST }, \
2572 { "s0", 16 + GP_REG_FIRST }, \
2573 { "s1", 17 + GP_REG_FIRST }, \
2574 { "s2", 18 + GP_REG_FIRST }, \
2575 { "s3", 19 + GP_REG_FIRST }, \
2576 { "s4", 20 + GP_REG_FIRST }, \
2577 { "s5", 21 + GP_REG_FIRST }, \
2578 { "s6", 22 + GP_REG_FIRST }, \
2579 { "s7", 23 + GP_REG_FIRST }, \
2580 { "t8", 24 + GP_REG_FIRST }, \
2581 { "t9", 25 + GP_REG_FIRST }, \
2582 { "k0", 26 + GP_REG_FIRST }, \
2583 { "k1", 27 + GP_REG_FIRST }, \
2584 { "gp", 28 + GP_REG_FIRST }, \
2585 { "sp", 29 + GP_REG_FIRST }, \
2586 { "fp", 30 + GP_REG_FIRST }, \
2587 { "ra", 31 + GP_REG_FIRST }, \
2588 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2591 /* This is meant to be redefined in the host dependent files. It is a
2592 set of alternative names and regnums for mips coprocessors. */
2594 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2596 #define DBR_OUTPUT_SEQEND(STREAM) \
2599 /* Undo the effect of '%*'. */ \
2600 mips_pop_asm_switch (&mips_nomacro); \
2601 mips_pop_asm_switch (&mips_noreorder); \
2602 /* Emit a blank line after the delay slot for emphasis. */ \
2603 fputs ("\n", STREAM); \
2607 /* mips-tfile does not understand .stabd directives. */
2608 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2609 dbxout_begin_stabn_sline (LINE); \
2610 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2613 /* Use .loc directives for SDB line numbers. */
2614 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2615 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2617 /* The MIPS implementation uses some labels for its own purpose. The
2618 following lists what labels are created, and are all formed by the
2619 pattern $L[a-z].*. The machine independent portion of GCC creates
2620 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2622 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2623 $Lb[0-9]+ Begin blocks for MIPS debug support
2624 $Lc[0-9]+ Label for use in s<xx> operation.
2625 $Le[0-9]+ End blocks for MIPS debug support */
2627 #undef ASM_DECLARE_OBJECT_NAME
2628 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2629 mips_declare_object (STREAM, NAME, "", ":\n")
2631 /* Globalizing directive for a label. */
2632 #define GLOBAL_ASM_OP "\t.globl\t"
2634 /* This says how to define a global common symbol. */
2636 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2638 /* This says how to define a local common symbol (i.e., not visible to
2641 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2642 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2643 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2646 /* This says how to output an external. It would be possible not to
2647 output anything and let undefined symbol become external. However
2648 the assembler uses length information on externals to allocate in
2649 data/sdata bss/sbss, thereby saving exec time. */
2651 #undef ASM_OUTPUT_EXTERNAL
2652 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2653 mips_output_external(STREAM,DECL,NAME)
2655 /* This is how to declare a function name. The actual work of
2656 emitting the label is moved to function_prologue, so that we can
2657 get the line number correctly emitted before the .ent directive,
2658 and after any .file directives. Define as empty so that the function
2659 is not declared before the .ent directive elsewhere. */
2661 #undef ASM_DECLARE_FUNCTION_NAME
2662 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2664 /* This is how to store into the string LABEL
2665 the symbol_ref name of an internal numbered label where
2666 PREFIX is the class of label and NUM is the number within the class.
2667 This is suitable for output with `assemble_name'. */
2669 #undef ASM_GENERATE_INTERNAL_LABEL
2670 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2671 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2673 /* Print debug labels as "foo = ." rather than "foo:" because they should
2674 represent a byte pointer rather than an ISA-encoded address. This is
2675 particularly important for code like:
2680 .section .gcc_except_table,...
2682 .uleb128 foo-$LFBxxx
2684 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2685 likewise a byte pointer rather than an ISA-encoded address.
2687 At the time of writing, this hook is not used for the function end
2693 But this doesn't matter, because GAS doesn't treat a pre-.end label
2694 as a MIPS16 one anyway. */
2696 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2697 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2699 /* This is how to output an element of a case-vector that is absolute. */
2701 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2702 fprintf (STREAM, "\t%s\t%sL%d\n", \
2703 ptr_mode == DImode ? ".dword" : ".word", \
2704 LOCAL_LABEL_PREFIX, \
2707 /* This is how to output an element of a case-vector. We can make the
2708 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2711 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2713 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2714 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2715 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2716 else if (TARGET_GPWORD) \
2717 fprintf (STREAM, "\t%s\t%sL%d\n", \
2718 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2719 LOCAL_LABEL_PREFIX, VALUE); \
2720 else if (TARGET_RTP_PIC) \
2722 /* Make the entry relative to the start of the function. */ \
2723 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2724 fprintf (STREAM, "\t%s\t%sL%d-", \
2725 Pmode == DImode ? ".dword" : ".word", \
2726 LOCAL_LABEL_PREFIX, VALUE); \
2727 assemble_name (STREAM, XSTR (fnsym, 0)); \
2728 fprintf (STREAM, "\n"); \
2731 fprintf (STREAM, "\t%s\t%sL%d\n", \
2732 ptr_mode == DImode ? ".dword" : ".word", \
2733 LOCAL_LABEL_PREFIX, VALUE); \
2736 /* This is how to output an assembler line
2737 that says to advance the location counter
2738 to a multiple of 2**LOG bytes. */
2740 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2741 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2743 /* This is how to output an assembler line to advance the location
2744 counter by SIZE bytes. */
2746 #undef ASM_OUTPUT_SKIP
2747 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2748 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2750 /* This is how to output a string. */
2751 #undef ASM_OUTPUT_ASCII
2752 #define ASM_OUTPUT_ASCII mips_output_ascii
2754 /* Output #ident as a in the read-only data section. */
2755 #undef ASM_OUTPUT_IDENT
2756 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2758 const char *p = STRING; \
2759 int size = strlen (p) + 1; \
2760 switch_to_section (readonly_data_section); \
2761 assemble_string (p, size); \
2764 /* Default to -G 8 */
2765 #ifndef MIPS_DEFAULT_GVALUE
2766 #define MIPS_DEFAULT_GVALUE 8
2769 /* Define the strings to put out for each section in the object file. */
2770 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2771 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2773 #undef READONLY_DATA_SECTION_ASM_OP
2774 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2776 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2779 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2780 TARGET_64BIT ? "daddiu" : "addiu", \
2781 reg_names[STACK_POINTER_REGNUM], \
2782 reg_names[STACK_POINTER_REGNUM], \
2783 TARGET_64BIT ? "sd" : "sw", \
2785 reg_names[STACK_POINTER_REGNUM]); \
2789 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2792 mips_push_asm_switch (&mips_noreorder); \
2793 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2794 TARGET_64BIT ? "ld" : "lw", \
2796 reg_names[STACK_POINTER_REGNUM], \
2797 TARGET_64BIT ? "daddu" : "addu", \
2798 reg_names[STACK_POINTER_REGNUM], \
2799 reg_names[STACK_POINTER_REGNUM]); \
2800 mips_pop_asm_switch (&mips_noreorder); \
2804 /* How to start an assembler comment.
2805 The leading space is important (the mips native assembler requires it). */
2806 #ifndef ASM_COMMENT_START
2807 #define ASM_COMMENT_START " #"
2810 /* Default definitions for size_t and ptrdiff_t. We must override the
2811 definitions from ../svr4.h on mips-*-linux-gnu. */
2814 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2817 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2819 /* The maximum number of bytes that can be copied by one iteration of
2820 a movmemsi loop; see mips_block_move_loop. */
2821 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2822 (UNITS_PER_WORD * 4)
2824 /* The maximum number of bytes that can be copied by a straight-line
2825 implementation of movmemsi; see mips_block_move_straight. We want
2826 to make sure that any loop-based implementation will iterate at
2828 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2829 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2831 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2832 values were determined experimentally by benchmarking with CSiBE.
2833 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2834 for o32 where we have to restore $gp afterwards as well as make an
2835 indirect call), but in practice, bumping this up higher for
2836 TARGET_ABICALLS doesn't make much difference to code size. */
2838 #define MIPS_CALL_RATIO 8
2840 /* Any loop-based implementation of movmemsi will have at least
2841 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2842 moves, so allow individual copies of fewer elements.
2844 When movmemsi is not available, use a value approximating
2845 the length of a memcpy call sequence, so that move_by_pieces
2846 will generate inline code if it is shorter than a function call.
2847 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2848 we'll have to generate a load/store pair for each, halve the
2849 value of MIPS_CALL_RATIO to take that into account. */
2851 #define MOVE_RATIO(speed) \
2853 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2854 : MIPS_CALL_RATIO / 2)
2856 /* movmemsi is meant to generate code that is at least as good as
2857 move_by_pieces. However, movmemsi effectively uses a by-pieces
2858 implementation both for moves smaller than a word and for word-aligned
2859 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2860 allow the tree-level optimisers to do such moves by pieces, as it
2861 often exposes other optimization opportunities. We might as well
2862 continue to use movmemsi at the rtl level though, as it produces
2863 better code when scheduling is disabled (such as at -O). */
2865 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2867 ? (!currently_expanding_to_rtl \
2868 && ((ALIGN) < BITS_PER_WORD \
2869 ? (SIZE) < UNITS_PER_WORD \
2870 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2871 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2872 < (unsigned int) MOVE_RATIO (false)))
2874 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2875 of the length of a memset call, but use the default otherwise. */
2877 #define CLEAR_RATIO(speed)\
2878 ((speed) ? 15 : MIPS_CALL_RATIO)
2880 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2881 optimizing for size adjust the ratio to account for the overhead of
2882 loading the constant and replicating it across the word. */
2884 #define SET_RATIO(speed) \
2885 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2887 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2888 in that case each word takes 3 insns (lui, ori, sw), or more in
2889 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2890 and let the move_by_pieces code copy the string from read-only
2891 memory. In the future, this could be tuned further for multi-issue
2892 CPUs that can issue stores down one pipe and arithmetic instructions
2893 down another; in that case, the lui/ori/sw combination would be a
2894 win for long enough strings. */
2896 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2899 /* Since the bits of the _init and _fini function is spread across
2900 many object files, each potentially with its own GP, we must assume
2901 we need to load our GP. We don't preserve $gp or $ra, since each
2902 init/fini chunk is supposed to initialize $gp, and crti/crtn
2903 already take care of preserving $ra and, when appropriate, $gp. */
2904 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2905 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2906 asm (SECTION_OP "\n\
2912 jal " USER_LABEL_PREFIX #FUNC "\n\
2913 " TEXT_SECTION_ASM_OP);
2914 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2915 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2916 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2917 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2918 asm (SECTION_OP "\n\
2923 .cpsetup $31, $2, 1b\n\
2924 jal " USER_LABEL_PREFIX #FUNC "\n\
2925 " TEXT_SECTION_ASM_OP);
2930 #define HAVE_AS_TLS 0
2933 #ifndef USED_FOR_TARGET
2934 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2935 struct mips_asm_switch {
2936 /* The FOO in the description above. */
2939 /* The current block nesting level, or 0 if we aren't in a block. */
2943 extern const enum reg_class mips_regno_to_class[];
2944 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2945 extern const char *current_function_file; /* filename current function is in */
2946 extern int num_source_filenames; /* current .file # */
2947 extern struct mips_asm_switch mips_noreorder;
2948 extern struct mips_asm_switch mips_nomacro;
2949 extern struct mips_asm_switch mips_noat;
2950 extern int mips_dbx_regno[];
2951 extern int mips_dwarf_regno[];
2952 extern bool mips_split_p[];
2953 extern bool mips_split_hi_p[];
2954 extern enum processor mips_arch; /* which cpu to codegen for */
2955 extern enum processor mips_tune; /* which cpu to schedule for */
2956 extern int mips_isa; /* architectural level */
2957 extern int mips_abi; /* which ABI to use */
2958 extern const struct mips_cpu_info *mips_arch_info;
2959 extern const struct mips_cpu_info *mips_tune_info;
2960 extern bool mips_base_mips16;
2961 extern enum mips_code_readable_setting mips_code_readable;
2962 extern GTY(()) struct target_globals *mips16_globals;
2965 /* Enable querying of DFA units. */
2966 #define CPU_UNITS_QUERY 1
2968 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2969 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2971 /* As on most targets, we want the .eh_frame section to be read-only where
2972 possible. And as on most targets, this means two things:
2974 (a) Non-locally-binding pointers must have an indirect encoding,
2975 so that the addresses in the .eh_frame section itself become
2978 (b) A shared library's .eh_frame section must encode locally-binding
2979 pointers in a relative (relocation-free) form.
2981 However, MIPS has traditionally not allowed directives like:
2985 in cases where "x" is in a different section, or is not defined in the
2986 same assembly file. We are therefore unable to emit the PC-relative
2987 form required by (b) at assembly time.
2989 Fortunately, the linker is able to convert absolute addresses into
2990 PC-relative addresses on our behalf. Unfortunately, only certain
2991 versions of the linker know how to do this for indirect pointers,
2992 and for personality data. We must fall back on using writable
2993 .eh_frame sections for shared libraries if the linker does not
2994 support this feature. */
2995 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2996 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2998 /* For switching between MIPS16 and non-MIPS16 modes. */
2999 #define SWITCHABLE_TARGET 1
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