1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
27 /* MIPS external variables defined in mips.c. */
29 /* Which processor to schedule for. Since there is no difference between
30 a R2000 and R3000 in terms of the scheduler, we collapse them into
31 just an R3000. The elements of the enumeration must match exactly
32 the cpu attribute in the mips.md machine description. */
65 /* Costs of various operations on the different architectures. */
67 struct mips_rtx_cost_data
69 unsigned short fp_add;
70 unsigned short fp_mult_sf;
71 unsigned short fp_mult_df;
72 unsigned short fp_div_sf;
73 unsigned short fp_div_df;
74 unsigned short int_mult_si;
75 unsigned short int_mult_di;
76 unsigned short int_div_si;
77 unsigned short int_div_di;
78 unsigned short branch_cost;
79 unsigned short memory_latency;
82 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
83 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
84 to work on a 64 bit machine. */
92 /* Information about one recognized processor. Defined here for the
93 benefit of TARGET_CPU_CPP_BUILTINS. */
94 struct mips_cpu_info {
95 /* The 'canonical' name of the processor as far as GCC is concerned.
96 It's typically a manufacturer's prefix followed by a numerical
97 designation. It should be lower case. */
100 /* The internal processor number that most closely matches this
101 entry. Several processors can have the same value, if there's no
102 difference between them from GCC's point of view. */
103 enum processor_type cpu;
105 /* The ISA level that the processor implements. */
109 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
110 extern const char *current_function_file; /* filename current function is in */
111 extern int num_source_filenames; /* current .file # */
112 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
113 extern int sym_lineno; /* sgi next label # for each stmt */
114 extern int set_noreorder; /* # of nested .set noreorder's */
115 extern int set_nomacro; /* # of nested .set nomacro's */
116 extern int set_noat; /* # of nested .set noat's */
117 extern int set_volatile; /* # of nested .set volatile's */
118 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
119 extern int mips_dbx_regno[]; /* Map register # to debug register # */
120 extern GTY(()) rtx cmp_operands[2];
121 extern enum processor_type mips_arch; /* which cpu to codegen for */
122 extern enum processor_type mips_tune; /* which cpu to schedule for */
123 extern int mips_isa; /* architectural level */
124 extern int mips_abi; /* which ABI to use */
125 extern int mips16_hard_float; /* mips16 without -msoft-float */
126 extern const struct mips_cpu_info mips_cpu_info_table[];
127 extern const struct mips_cpu_info *mips_arch_info;
128 extern const struct mips_cpu_info *mips_tune_info;
129 extern const struct mips_rtx_cost_data *mips_cost;
131 /* Macros to silence warnings about numbers being signed in traditional
132 C and unsigned in ISO C when compiled on 32-bit hosts. */
134 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
135 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
136 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
139 /* Run-time compilation parameters selecting different hardware subsets. */
141 /* True if the call patterns should be split into a jalr followed by
142 an instruction to restore $gp. This is only ever true for SVR4 PIC,
143 in which $gp is call-clobbered. It is only safe to split the load
144 from the call when every use of $gp is explicit. */
146 #define TARGET_SPLIT_CALLS \
147 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
149 /* True if we can optimize sibling calls. For simplicity, we only
150 handle cases in which call_insn_operand will reject invalid
151 sibcall addresses. There are two cases in which this isn't true:
153 - TARGET_MIPS16. call_insn_operand accepts constant addresses
154 but there is no direct jump instruction. It isn't worth
155 using sibling calls in this case anyway; they would usually
156 be longer than normal calls.
158 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
159 accepts global constants, but "jr $25" is the only allowed
162 #define TARGET_SIBCALLS \
163 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
165 /* True if .gpword or .gpdword should be used for switch tables.
167 Although GAS does understand .gpdword, the SGI linker mishandles
168 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
169 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
170 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
172 /* Generate mips16 code */
173 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
174 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
175 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
177 /* Generic ISA defines. */
178 #define ISA_MIPS1 (mips_isa == 1)
179 #define ISA_MIPS2 (mips_isa == 2)
180 #define ISA_MIPS3 (mips_isa == 3)
181 #define ISA_MIPS4 (mips_isa == 4)
182 #define ISA_MIPS32 (mips_isa == 32)
183 #define ISA_MIPS32R2 (mips_isa == 33)
184 #define ISA_MIPS64 (mips_isa == 64)
186 /* Architecture target defines. */
187 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
188 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
189 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
190 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
191 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
192 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
193 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
194 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
195 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
196 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
198 /* Scheduling target defines. */
199 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
200 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
201 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
202 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
203 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
204 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
205 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
206 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
207 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
208 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
209 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
210 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
212 /* True if the pre-reload scheduler should try to create chains of
213 multiply-add or multiply-subtract instructions. For example,
221 t1 will have a higher priority than t2 and t3 will have a higher
222 priority than t4. However, before reload, there is no dependence
223 between t1 and t3, and they can often have similar priorities.
224 The scheduler will then tend to prefer:
231 which stops us from making full use of macc/madd-style instructions.
232 This sort of situation occurs frequently in Fourier transforms and
235 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
236 queue so that chained multiply-add and multiply-subtract instructions
237 appear ahead of any other instruction that is likely to clobber lo.
238 In the example above, if t2 and t3 become ready at the same time,
239 the code ensures that t2 is scheduled first.
241 Multiply-accumulate instructions are a bigger win for some targets
242 than others, so this macro is defined on an opt-in basis. */
243 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
247 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
248 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
250 /* IRIX specific stuff. */
251 #define TARGET_IRIX 0
252 #define TARGET_IRIX6 0
254 /* Define preprocessor macros for the -march and -mtune options.
255 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
256 processor. If INFO's canonical name is "foo", define PREFIX to
257 be "foo", and define an additional macro PREFIX_FOO. */
258 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
263 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
264 for (p = macro; *p != 0; p++) \
267 builtin_define (macro); \
268 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
273 /* Target CPU builtins. */
274 #define TARGET_CPU_CPP_BUILTINS() \
277 /* Everyone but IRIX defines this to mips. */ \
279 builtin_assert ("machine=mips"); \
281 builtin_assert ("cpu=mips"); \
282 builtin_define ("__mips__"); \
283 builtin_define ("_mips"); \
285 /* We do this here because __mips is defined below \
286 and so we can't use builtin_define_std. */ \
288 builtin_define ("mips"); \
291 builtin_define ("__mips64"); \
295 /* Treat _R3000 and _R4000 like register-size \
296 defines, which is how they've historically \
300 builtin_define_std ("R4000"); \
301 builtin_define ("_R4000"); \
305 builtin_define_std ("R3000"); \
306 builtin_define ("_R3000"); \
309 if (TARGET_FLOAT64) \
310 builtin_define ("__mips_fpr=64"); \
312 builtin_define ("__mips_fpr=32"); \
315 builtin_define ("__mips16"); \
318 builtin_define ("__mips3d"); \
321 builtin_define ("__mips_dsp"); \
323 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
324 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
328 builtin_define ("__mips=1"); \
329 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
331 else if (ISA_MIPS2) \
333 builtin_define ("__mips=2"); \
334 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
336 else if (ISA_MIPS3) \
338 builtin_define ("__mips=3"); \
339 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
341 else if (ISA_MIPS4) \
343 builtin_define ("__mips=4"); \
344 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
346 else if (ISA_MIPS32) \
348 builtin_define ("__mips=32"); \
349 builtin_define ("__mips_isa_rev=1"); \
350 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
352 else if (ISA_MIPS32R2) \
354 builtin_define ("__mips=32"); \
355 builtin_define ("__mips_isa_rev=2"); \
356 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
358 else if (ISA_MIPS64) \
360 builtin_define ("__mips=64"); \
361 builtin_define ("__mips_isa_rev=1"); \
362 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
365 if (TARGET_HARD_FLOAT) \
366 builtin_define ("__mips_hard_float"); \
367 else if (TARGET_SOFT_FLOAT) \
368 builtin_define ("__mips_soft_float"); \
370 if (TARGET_SINGLE_FLOAT) \
371 builtin_define ("__mips_single_float"); \
373 if (TARGET_PAIRED_SINGLE_FLOAT) \
374 builtin_define ("__mips_paired_single_float"); \
376 if (TARGET_BIG_ENDIAN) \
378 builtin_define_std ("MIPSEB"); \
379 builtin_define ("_MIPSEB"); \
383 builtin_define_std ("MIPSEL"); \
384 builtin_define ("_MIPSEL"); \
387 /* Macros dependent on the C dialect. */ \
388 if (preprocessing_asm_p ()) \
390 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
391 builtin_define ("_LANGUAGE_ASSEMBLY"); \
393 else if (c_dialect_cxx ()) \
395 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
396 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
397 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
401 builtin_define_std ("LANGUAGE_C"); \
402 builtin_define ("_LANGUAGE_C"); \
404 if (c_dialect_objc ()) \
406 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
407 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
408 /* Bizarre, but needed at least for Irix. */ \
409 builtin_define_std ("LANGUAGE_C"); \
410 builtin_define ("_LANGUAGE_C"); \
413 if (mips_abi == ABI_EABI) \
414 builtin_define ("__mips_eabi"); \
418 /* Default target_flags if no switches are specified */
420 #ifndef TARGET_DEFAULT
421 #define TARGET_DEFAULT 0
424 #ifndef TARGET_CPU_DEFAULT
425 #define TARGET_CPU_DEFAULT 0
428 #ifndef TARGET_ENDIAN_DEFAULT
429 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
432 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
433 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
436 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
437 #ifndef MIPS_ISA_DEFAULT
438 #ifndef MIPS_CPU_STRING_DEFAULT
439 #define MIPS_CPU_STRING_DEFAULT "from-abi"
445 /* Make this compile time constant for libgcc2 */
447 #define TARGET_64BIT 1
449 #define TARGET_64BIT 0
451 #endif /* IN_LIBGCC2 */
453 #ifndef MULTILIB_ENDIAN_DEFAULT
454 #if TARGET_ENDIAN_DEFAULT == 0
455 #define MULTILIB_ENDIAN_DEFAULT "EL"
457 #define MULTILIB_ENDIAN_DEFAULT "EB"
461 #ifndef MULTILIB_ISA_DEFAULT
462 # if MIPS_ISA_DEFAULT == 1
463 # define MULTILIB_ISA_DEFAULT "mips1"
465 # if MIPS_ISA_DEFAULT == 2
466 # define MULTILIB_ISA_DEFAULT "mips2"
468 # if MIPS_ISA_DEFAULT == 3
469 # define MULTILIB_ISA_DEFAULT "mips3"
471 # if MIPS_ISA_DEFAULT == 4
472 # define MULTILIB_ISA_DEFAULT "mips4"
474 # if MIPS_ISA_DEFAULT == 32
475 # define MULTILIB_ISA_DEFAULT "mips32"
477 # if MIPS_ISA_DEFAULT == 33
478 # define MULTILIB_ISA_DEFAULT "mips32r2"
480 # if MIPS_ISA_DEFAULT == 64
481 # define MULTILIB_ISA_DEFAULT "mips64"
483 # define MULTILIB_ISA_DEFAULT "mips1"
493 #ifndef MULTILIB_DEFAULTS
494 #define MULTILIB_DEFAULTS \
495 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
498 /* We must pass -EL to the linker by default for little endian embedded
499 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
500 linker will default to using big-endian output files. The OUTPUT_FORMAT
501 line must be in the linker script, otherwise -EB/-EL will not work. */
504 #if TARGET_ENDIAN_DEFAULT == 0
505 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
507 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
511 /* Support for a compile-time default CPU, et cetera. The rules are:
512 --with-arch is ignored if -march is specified or a -mips is specified
513 (other than -mips16).
514 --with-tune is ignored if -mtune is specified.
515 --with-abi is ignored if -mabi is specified.
516 --with-float is ignored if -mhard-float or -msoft-float are
518 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
520 #define OPTION_DEFAULT_SPECS \
521 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
522 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
523 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
524 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
525 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
528 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
529 && ISA_HAS_COND_TRAP)
531 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
535 /* Generate three-operand multiply instructions for SImode. */
536 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
547 /* Generate three-operand multiply instructions for DImode. */
548 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
551 /* True if the ABI can only work with 64-bit integer registers. We
552 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
553 otherwise floating-point registers must also be 64-bit. */
554 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
556 /* Likewise for 32-bit regs. */
557 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
559 /* True if symbols are 64 bits wide. At present, n64 is the only
560 ABI for which this is true. */
561 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
563 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
564 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
568 /* ISA has branch likely instructions (e.g. mips2). */
569 /* Disable branchlikely for tx39 until compare rewrite. They haven't
570 been generated up to this point. */
571 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
573 /* ISA has the conditional move instructions introduced in mips4. */
574 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
578 && !TARGET_MIPS5500 \
581 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
582 branch on CC, and move (both FP and non-FP) on CC. */
583 #define ISA_HAS_8CC (ISA_MIPS4 \
588 /* This is a catch all for other mips4 instructions: indexed load, the
589 FP madd and msub instructions, and the FP recip and recip sqrt
591 #define ISA_HAS_FP4 ((ISA_MIPS4 \
595 /* ISA has conditional trap instructions. */
596 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
599 /* ISA has integer multiply-accumulate instructions, madd and msub. */
600 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
605 /* ISA has floating-point nmadd and nmsub instructions. */
606 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
608 && (!TARGET_MIPS5400 || TARGET_MAD) \
611 /* ISA has count leading zeroes/ones instruction (not implemented). */
612 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
617 /* ISA has double-word count leading zeroes/ones instruction (not
619 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
622 /* ISA has three operand multiply instructions that put
623 the high part in an accumulator: mulhi or mulhiu. */
624 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
629 /* ISA has three operand multiply instructions that
630 negates the result and puts the result in an accumulator. */
631 #define ISA_HAS_MULS (TARGET_MIPS5400 \
636 /* ISA has three operand multiply instructions that subtracts the
637 result from a 4th operand and puts the result in an accumulator. */
638 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
642 /* ISA has three operand multiply instructions that the result
643 from a 4th operand and puts the result in an accumulator. */
644 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
645 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
651 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
652 #define ISA_HAS_MACCHI (!TARGET_MIPS16 \
653 && (TARGET_MIPS4120 \
656 /* ISA has 32-bit rotate right instruction. */
657 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
664 /* ISA has 64-bit rotate right instruction. */
665 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
667 && (TARGET_MIPS5400 \
672 /* ISA has data prefetch instructions. This controls use of 'pref'. */
673 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
679 /* ISA has data indexed prefetch instructions. This controls use of
680 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
681 (prefx is a cop1x instruction, so can only be used if FP is
683 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
687 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
688 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
689 also requires TARGET_DOUBLE_FLOAT. */
690 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
692 /* ISA includes the MIPS32r2 seb and seh instructions. */
693 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
697 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
698 #define ISA_HAS_EXT_INS (!TARGET_MIPS16 \
702 /* True if the result of a load is not available to the next instruction.
703 A nop will then be needed between instructions like "lw $4,..."
704 and "addiu $4,$4,1". */
705 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
706 && !TARGET_MIPS3900 \
709 /* Likewise mtc1 and mfc1. */
710 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
712 /* Likewise floating-point comparisons. */
713 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
715 /* True if mflo and mfhi can be immediately followed by instructions
716 which write to the HI and LO registers.
718 According to MIPS specifications, MIPS ISAs I, II, and III need
719 (at least) two instructions between the reads of HI/LO and
720 instructions which write them, and later ISAs do not. Contradicting
721 the MIPS specifications, some MIPS IV processor user manuals (e.g.
722 the UM for the NEC Vr5000) document needing the instructions between
723 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
724 MIPS64 and later ISAs to have the interlocks, plus any specific
725 earlier-ISA CPUs for which CPU documentation declares that the
726 instructions are really interlocked. */
727 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
732 /* Add -G xx support. */
734 #undef SWITCH_TAKES_ARG
735 #define SWITCH_TAKES_ARG(CHAR) \
736 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
738 #define OVERRIDE_OPTIONS override_options ()
740 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
742 /* Show we can debug even without a frame pointer. */
743 #define CAN_DEBUG_WITHOUT_FP
745 /* Tell collect what flags to pass to nm. */
747 #define NM_FLAGS "-Bn"
751 #ifndef MIPS_ABI_DEFAULT
752 #define MIPS_ABI_DEFAULT ABI_32
755 /* Use the most portable ABI flag for the ASM specs. */
757 #if MIPS_ABI_DEFAULT == ABI_32
758 #define MULTILIB_ABI_DEFAULT "mabi=32"
761 #if MIPS_ABI_DEFAULT == ABI_O64
762 #define MULTILIB_ABI_DEFAULT "mabi=o64"
765 #if MIPS_ABI_DEFAULT == ABI_N32
766 #define MULTILIB_ABI_DEFAULT "mabi=n32"
769 #if MIPS_ABI_DEFAULT == ABI_64
770 #define MULTILIB_ABI_DEFAULT "mabi=64"
773 #if MIPS_ABI_DEFAULT == ABI_EABI
774 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
777 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
778 to the assembler. It may be overridden by subtargets. */
779 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
780 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
782 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
785 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
786 the assembler. It may be overridden by subtargets.
788 Beginning with gas 2.13, -mdebug must be passed to correctly handle
789 COFF debugging info. */
791 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
792 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
793 %{g} %{g0} %{g1} %{g2} %{g3} \
794 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
795 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
796 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
797 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
798 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
801 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
802 overridden by subtargets. */
804 #ifndef SUBTARGET_ASM_SPEC
805 #define SUBTARGET_ASM_SPEC ""
810 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
811 %{mips32} %{mips32r2} %{mips64} \
812 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
815 %{mfix-vr4120} %{mfix-vr4130} \
816 %(subtarget_asm_optimizing_spec) \
817 %(subtarget_asm_debugging_spec) \
818 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
819 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
820 %{msym32} %{mno-sym32} \
822 %(subtarget_asm_spec)"
824 /* Extra switches sometimes passed to the linker. */
825 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
826 will interpret it as a -b option. */
831 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
832 %{bestGnum} %{shared} %{non_shared}"
833 #endif /* LINK_SPEC defined */
836 /* Specs for the compiler proper */
838 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
839 overridden by subtargets. */
840 #ifndef SUBTARGET_CC1_SPEC
841 #define SUBTARGET_CC1_SPEC ""
844 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
848 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
849 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
851 %(subtarget_cc1_spec)"
854 /* Preprocessor specs. */
856 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
857 overridden by subtargets. */
858 #ifndef SUBTARGET_CPP_SPEC
859 #define SUBTARGET_CPP_SPEC ""
862 #define CPP_SPEC "%(subtarget_cpp_spec)"
864 /* This macro defines names of additional specifications to put in the specs
865 that can be used in various specifications like CC1_SPEC. Its definition
866 is an initializer with a subgrouping for each command option.
868 Each subgrouping contains a string constant, that defines the
869 specification name, and a string constant that used by the GCC driver
872 Do not define this macro if it does not need to do anything. */
874 #define EXTRA_SPECS \
875 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
876 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
877 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
878 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
879 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
880 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
881 { "endian_spec", ENDIAN_SPEC }, \
882 SUBTARGET_EXTRA_SPECS
884 #ifndef SUBTARGET_EXTRA_SPECS
885 #define SUBTARGET_EXTRA_SPECS
888 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
889 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
890 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
892 #ifndef PREFERRED_DEBUGGING_TYPE
893 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
896 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
898 /* By default, turn on GDB extensions. */
899 #define DEFAULT_GDB_EXTENSIONS 1
901 /* Local compiler-generated symbols must have a prefix that the assembler
902 understands. By default, this is $, although some targets (e.g.,
903 NetBSD-ELF) need to override this. */
905 #ifndef LOCAL_LABEL_PREFIX
906 #define LOCAL_LABEL_PREFIX "$"
909 /* By default on the mips, external symbols do not have an underscore
910 prepended, but some targets (e.g., NetBSD) require this. */
912 #ifndef USER_LABEL_PREFIX
913 #define USER_LABEL_PREFIX ""
916 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
917 since the length can run past this up to a continuation point. */
918 #undef DBX_CONTIN_LENGTH
919 #define DBX_CONTIN_LENGTH 1500
921 /* How to renumber registers for dbx and gdb. */
922 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
924 /* The mapping from gcc register number to DWARF 2 CFA column number. */
925 #define DWARF_FRAME_REGNUM(REG) (REG)
927 /* The DWARF 2 CFA column which tracks the return address. */
928 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
930 /* The DWARF 2 CFA column which tracks the return address from a
931 signal handler context. */
932 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
934 /* Before the prologue, RA lives in r31. */
935 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
937 /* Describe how we implement __builtin_eh_return. */
938 #define EH_RETURN_DATA_REGNO(N) \
939 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
941 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
943 /* Offsets recorded in opcodes are a multiple of this alignment factor.
944 The default for this in 64-bit mode is 8, which causes problems with
945 SFmode register saves. */
946 #define DWARF_CIE_DATA_ALIGNMENT -4
948 /* Correct the offset of automatic variables and arguments. Note that
949 the MIPS debug format wants all automatic variables and arguments
950 to be in terms of the virtual frame pointer (stack pointer before
951 any adjustment in the function), while the MIPS 3.0 linker wants
952 the frame pointer to be the stack pointer after the initial
955 #define DEBUGGER_AUTO_OFFSET(X) \
956 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
957 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
958 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
960 /* Target machine storage layout */
962 #define BITS_BIG_ENDIAN 0
963 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
964 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
966 /* Define this to set the endianness to use in libgcc2.c, which can
967 not depend on target_flags. */
968 #if !defined(MIPSEL) && !defined(__MIPSEL__)
969 #define LIBGCC2_WORDS_BIG_ENDIAN 1
971 #define LIBGCC2_WORDS_BIG_ENDIAN 0
974 #define MAX_BITS_PER_WORD 64
976 /* Width of a word, in units (bytes). */
977 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
978 #define MIN_UNITS_PER_WORD 4
980 /* For MIPS, width of a floating point register. */
981 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
983 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
984 the next available register. */
985 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
987 /* The largest size of value that can be held in floating-point
988 registers and moved with a single instruction. */
989 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
991 /* The largest size of value that can be held in floating-point
993 #define UNITS_PER_FPVALUE \
994 (TARGET_SOFT_FLOAT ? 0 \
995 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
996 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
998 /* The number of bytes in a double. */
999 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1001 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1003 /* Set the sizes of the core types. */
1004 #define SHORT_TYPE_SIZE 16
1005 #define INT_TYPE_SIZE 32
1006 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1007 #define LONG_LONG_TYPE_SIZE 64
1009 #define FLOAT_TYPE_SIZE 32
1010 #define DOUBLE_TYPE_SIZE 64
1011 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1013 /* long double is not a fixed mode, but the idea is that, if we
1014 support long double, we also want a 128-bit integer type. */
1015 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1018 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1019 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1020 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1022 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1026 /* Width in bits of a pointer. */
1027 #ifndef POINTER_SIZE
1028 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1031 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1032 #define PARM_BOUNDARY BITS_PER_WORD
1034 /* Allocation boundary (in *bits*) for the code of a function. */
1035 #define FUNCTION_BOUNDARY 32
1037 /* Alignment of field after `int : 0' in a structure. */
1038 #define EMPTY_FIELD_BOUNDARY 32
1040 /* Every structure's size must be a multiple of this. */
1041 /* 8 is observed right on a DECstation and on riscos 4.02. */
1042 #define STRUCTURE_SIZE_BOUNDARY 8
1044 /* There is no point aligning anything to a rounder boundary than this. */
1045 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1047 /* All accesses must be aligned. */
1048 #define STRICT_ALIGNMENT 1
1050 /* Define this if you wish to imitate the way many other C compilers
1051 handle alignment of bitfields and the structures that contain
1054 The behavior is that the type written for a bit-field (`int',
1055 `short', or other integer type) imposes an alignment for the
1056 entire structure, as if the structure really did contain an
1057 ordinary field of that type. In addition, the bit-field is placed
1058 within the structure so that it would fit within such a field,
1059 not crossing a boundary for it.
1061 Thus, on most machines, a bit-field whose type is written as `int'
1062 would not cross a four-byte boundary, and would force four-byte
1063 alignment for the whole structure. (The alignment used may not
1064 be four bytes; it is controlled by the other alignment
1067 If the macro is defined, its definition should be a C expression;
1068 a nonzero value for the expression enables this behavior. */
1070 #define PCC_BITFIELD_TYPE_MATTERS 1
1072 /* If defined, a C expression to compute the alignment given to a
1073 constant that is being placed in memory. CONSTANT is the constant
1074 and ALIGN is the alignment that the object would ordinarily have.
1075 The value of this macro is used instead of that alignment to align
1078 If this macro is not defined, then ALIGN is used.
1080 The typical use of this macro is to increase alignment for string
1081 constants to be word aligned so that `strcpy' calls that copy
1082 constants can be done inline. */
1084 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1085 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1086 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1088 /* If defined, a C expression to compute the alignment for a static
1089 variable. TYPE is the data type, and ALIGN is the alignment that
1090 the object would ordinarily have. The value of this macro is used
1091 instead of that alignment to align the object.
1093 If this macro is not defined, then ALIGN is used.
1095 One use of this macro is to increase alignment of medium-size
1096 data to make it all fit in fewer cache lines. Another is to
1097 cause character arrays to be word-aligned so that `strcpy' calls
1098 that copy constants to character arrays can be done inline. */
1100 #undef DATA_ALIGNMENT
1101 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1102 ((((ALIGN) < BITS_PER_WORD) \
1103 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1104 || TREE_CODE (TYPE) == UNION_TYPE \
1105 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1108 #define PAD_VARARGS_DOWN \
1109 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1111 /* Define if operations between registers always perform the operation
1112 on the full register even if a narrower mode is specified. */
1113 #define WORD_REGISTER_OPERATIONS
1115 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1116 moves. All other references are zero extended. */
1117 #define LOAD_EXTEND_OP(MODE) \
1118 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1119 ? SIGN_EXTEND : ZERO_EXTEND)
1121 /* Define this macro if it is advisable to hold scalars in registers
1122 in a wider mode than that declared by the program. In such cases,
1123 the value is constrained to be within the bounds of the declared
1124 type, but kept valid in the wider mode. The signedness of the
1125 extension may differ from that of the type. */
1127 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1128 if (GET_MODE_CLASS (MODE) == MODE_INT \
1129 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1131 if ((MODE) == SImode) \
1136 /* Define if loading short immediate values into registers sign extends. */
1137 #define SHORT_IMMEDIATES_SIGN_EXTEND
1139 /* The [d]clz instructions have the natural values at 0. */
1141 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1142 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1144 /* Standard register usage. */
1146 /* Number of hardware registers. We have:
1148 - 32 integer registers
1149 - 32 floating point registers
1150 - 8 condition code registers
1151 - 2 accumulator registers (hi and lo)
1152 - 32 registers each for coprocessors 0, 2 and 3
1154 - ARG_POINTER_REGNUM
1155 - FRAME_POINTER_REGNUM
1156 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1157 - 3 dummy entries that were used at various times in the past.
1158 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1159 - 6 DSP control registers */
1161 #define FIRST_PSEUDO_REGISTER 188
1163 /* By default, fix the kernel registers ($26 and $27), the global
1164 pointer ($28) and the stack pointer ($29). This can change
1165 depending on the command-line options.
1167 Regarding coprocessor registers: without evidence to the contrary,
1168 it's best to assume that each coprocessor register has a unique
1169 use. This can be overridden, in, e.g., override_options() or
1170 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1171 for a particular target. */
1173 #define FIXED_REGISTERS \
1175 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1176 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1177 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1178 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1179 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1180 /* COP0 registers */ \
1181 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1182 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1183 /* COP2 registers */ \
1184 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1185 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1186 /* COP3 registers */ \
1187 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1188 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1189 /* 6 DSP accumulator registers & 6 control registers */ \
1190 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1194 /* Set up this array for o32 by default.
1196 Note that we don't mark $31 as a call-clobbered register. The idea is
1197 that it's really the call instructions themselves which clobber $31.
1198 We don't care what the called function does with it afterwards.
1200 This approach makes it easier to implement sibcalls. Unlike normal
1201 calls, sibcalls don't clobber $31, so the register reaches the
1202 called function in tact. EPILOGUE_USES says that $31 is useful
1203 to the called function. */
1205 #define CALL_USED_REGISTERS \
1207 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1208 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1209 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1210 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1211 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1212 /* COP0 registers */ \
1213 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1214 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1215 /* COP2 registers */ \
1216 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1217 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1218 /* COP3 registers */ \
1219 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1220 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1221 /* 6 DSP accumulator registers & 6 control registers */ \
1222 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1226 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1228 #define CALL_REALLY_USED_REGISTERS \
1229 { /* General registers. */ \
1230 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1231 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1232 /* Floating-point registers. */ \
1233 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1234 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1236 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1237 /* COP0 registers */ \
1238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1240 /* COP2 registers */ \
1241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1243 /* COP3 registers */ \
1244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1246 /* 6 DSP accumulator registers & 6 control registers */ \
1247 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1250 /* Internal macros to classify a register number as to whether it's a
1251 general purpose register, a floating point register, a
1252 multiply/divide register, or a status register. */
1254 #define GP_REG_FIRST 0
1255 #define GP_REG_LAST 31
1256 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1257 #define GP_DBX_FIRST 0
1259 #define FP_REG_FIRST 32
1260 #define FP_REG_LAST 63
1261 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1262 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1264 #define MD_REG_FIRST 64
1265 #define MD_REG_LAST 65
1266 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1267 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1269 #define ST_REG_FIRST 67
1270 #define ST_REG_LAST 74
1271 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1274 /* FIXME: renumber. */
1275 #define COP0_REG_FIRST 80
1276 #define COP0_REG_LAST 111
1277 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1279 #define COP2_REG_FIRST 112
1280 #define COP2_REG_LAST 143
1281 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1283 #define COP3_REG_FIRST 144
1284 #define COP3_REG_LAST 175
1285 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1286 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1287 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1289 #define DSP_ACC_REG_FIRST 176
1290 #define DSP_ACC_REG_LAST 181
1291 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1293 #define AT_REGNUM (GP_REG_FIRST + 1)
1294 #define HI_REGNUM (MD_REG_FIRST + 0)
1295 #define LO_REGNUM (MD_REG_FIRST + 1)
1296 #define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0)
1297 #define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1)
1298 #define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2)
1299 #define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3)
1300 #define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4)
1301 #define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5)
1303 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1304 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1305 should be used instead. */
1306 #define FPSW_REGNUM ST_REG_FIRST
1308 #define GP_REG_P(REGNO) \
1309 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1310 #define M16_REG_P(REGNO) \
1311 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1312 #define FP_REG_P(REGNO) \
1313 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1314 #define MD_REG_P(REGNO) \
1315 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1316 #define ST_REG_P(REGNO) \
1317 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1318 #define COP0_REG_P(REGNO) \
1319 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1320 #define COP2_REG_P(REGNO) \
1321 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1322 #define COP3_REG_P(REGNO) \
1323 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1324 #define ALL_COP_REG_P(REGNO) \
1325 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1326 /* Test if REGNO is one of the 6 new DSP accumulators. */
1327 #define DSP_ACC_REG_P(REGNO) \
1328 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1329 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1330 #define ACC_REG_P(REGNO) \
1331 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1332 /* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */
1333 #define ACC_HI_REG_P(REGNO) \
1334 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \
1335 || (REGNO) == AC3HI_REGNUM)
1337 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1339 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1340 to initialize the mips16 gp pseudo register. */
1341 #define CONST_GP_P(X) \
1342 (GET_CODE (X) == CONST \
1343 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1344 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1346 /* Return coprocessor number from register number. */
1348 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1349 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1350 : COP3_REG_P (REGNO) ? '3' : '?')
1353 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1355 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1356 array built in override_options. Because machmodes.h is not yet
1357 included before this file is processed, the MODE bound can't be
1360 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1362 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1363 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1365 /* Value is 1 if it is a good idea to tie two pseudo registers
1366 when one has mode MODE1 and one has mode MODE2.
1367 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1368 for any hard reg, then this must be 0 for correct output. */
1369 #define MODES_TIEABLE_P(MODE1, MODE2) \
1370 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1371 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1372 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1373 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1375 /* Register to use for pushing function arguments. */
1376 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1378 /* These two registers don't really exist: they get eliminated to either
1379 the stack or hard frame pointer. */
1380 #define ARG_POINTER_REGNUM 77
1381 #define FRAME_POINTER_REGNUM 78
1383 /* $30 is not available on the mips16, so we use $17 as the frame
1385 #define HARD_FRAME_POINTER_REGNUM \
1386 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1388 /* Value should be nonzero if functions must have frame pointers.
1389 Zero means the frame pointer need not be set up (and parms
1390 may be accessed via the stack pointer) in functions that seem suitable.
1391 This is computed in `reload', in reload1.c. */
1392 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1394 /* Register in which static-chain is passed to a function. */
1395 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1397 /* Registers used as temporaries in prologue/epilogue code. If we're
1398 generating mips16 code, these registers must come from the core set
1399 of 8. The prologue register mustn't conflict with any incoming
1400 arguments, the static chain pointer, or the frame pointer. The
1401 epilogue temporary mustn't conflict with the return registers, the
1402 frame pointer, the EH stack adjustment, or the EH data registers. */
1404 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1405 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1407 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1408 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1410 /* Define this macro if it is as good or better to call a constant
1411 function address than to call an address kept in a register. */
1412 #define NO_FUNCTION_CSE 1
1414 /* The ABI-defined global pointer. Sometimes we use a different
1415 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1416 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1418 /* We normally use $28 as the global pointer. However, when generating
1419 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1420 register instead. They can then avoid saving and restoring $28
1421 and perhaps avoid using a frame at all.
1423 When a leaf function uses something other than $28, mips_expand_prologue
1424 will modify pic_offset_table_rtx in place. Take the register number
1425 from there after reload. */
1426 #define PIC_OFFSET_TABLE_REGNUM \
1427 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1429 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1431 /* Define the classes of registers for register constraints in the
1432 machine description. Also define ranges of constants.
1434 One of the classes must always be named ALL_REGS and include all hard regs.
1435 If there is more than one class, another class must be named NO_REGS
1436 and contain no registers.
1438 The name GENERAL_REGS must be the name of a class (or an alias for
1439 another name such as ALL_REGS). This is the class of registers
1440 that is allowed by "g" or "r" in a register constraint.
1441 Also, registers outside this class are allocated only when
1442 instructions express preferences for them.
1444 The classes must be numbered in nondecreasing order; that is,
1445 a larger-numbered class must never be contained completely
1446 in a smaller-numbered class.
1448 For any two classes, it is very desirable that there be another
1449 class that represents their union. */
1453 NO_REGS, /* no registers in set */
1454 M16_NA_REGS, /* mips16 regs not used to pass args */
1455 M16_REGS, /* mips16 directly accessible registers */
1456 T_REG, /* mips16 T register ($24) */
1457 M16_T_REGS, /* mips16 registers plus T register */
1458 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1459 V1_REG, /* Register $v1 ($3) used for TLS access. */
1460 LEA_REGS, /* Every GPR except $25 */
1461 GR_REGS, /* integer registers */
1462 FP_REGS, /* floating point registers */
1463 HI_REG, /* hi register */
1464 LO_REG, /* lo register */
1465 MD_REGS, /* multiply/divide registers (hi/lo) */
1466 COP0_REGS, /* generic coprocessor classes */
1469 HI_AND_GR_REGS, /* union classes */
1476 ALL_COP_AND_GR_REGS,
1477 ST_REGS, /* status registers (fp status) */
1478 DSP_ACC_REGS, /* DSP accumulator registers */
1479 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1480 ALL_REGS, /* all registers */
1481 LIM_REG_CLASSES /* max value + 1 */
1484 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1486 #define GENERAL_REGS GR_REGS
1488 /* An initializer containing the names of the register classes as C
1489 string constants. These names are used in writing some of the
1492 #define REG_CLASS_NAMES \
1499 "PIC_FN_ADDR_REG", \
1507 /* coprocessor registers */ \
1514 "COP0_AND_GR_REGS", \
1515 "COP2_AND_GR_REGS", \
1516 "COP3_AND_GR_REGS", \
1518 "ALL_COP_AND_GR_REGS", \
1525 /* An initializer containing the contents of the register classes,
1526 as integers which are bit masks. The Nth integer specifies the
1527 contents of class N. The way the integer MASK is interpreted is
1528 that register R is in the class if `MASK & (1 << R)' is 1.
1530 When the machine has more than 32 registers, an integer does not
1531 suffice. Then the integers are replaced by sub-initializers,
1532 braced groupings containing several integers. Each
1533 sub-initializer must be suitable as an initializer for the type
1534 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1536 #define REG_CLASS_CONTENTS \
1538 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1539 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1540 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1541 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1542 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1543 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1544 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1545 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1546 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1547 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1548 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1549 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1550 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1551 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1552 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1553 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1554 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1555 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1556 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1557 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1558 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1559 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1560 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1561 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1562 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1563 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1564 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1565 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1569 /* A C expression whose value is a register class containing hard
1570 register REGNO. In general there is more that one such class;
1571 choose a class which is "minimal", meaning that no smaller class
1572 also contains the register. */
1574 extern const enum reg_class mips_regno_to_class[];
1576 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1578 /* A macro whose definition is the name of the class to which a
1579 valid base register must belong. A base register is one used in
1580 an address which is the register value plus a displacement. */
1582 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1584 /* A macro whose definition is the name of the class to which a
1585 valid index register must belong. An index register is one used
1586 in an address where its value is either multiplied by a scale
1587 factor or added to another register (as well as added to a
1590 #define INDEX_REG_CLASS NO_REGS
1592 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1593 registers explicitly used in the rtl to be used as spill registers
1594 but prevents the compiler from extending the lifetime of these
1597 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1599 /* This macro is used later on in the file. */
1600 #define GR_REG_CLASS_P(CLASS) \
1601 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1602 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1603 || (CLASS) == V1_REG \
1604 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1606 /* This macro is also used later on in the file. */
1607 #define COP_REG_CLASS_P(CLASS) \
1608 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1610 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1611 is the default value (allocate the registers in numeric order). We
1612 define it just so that we can override it for the mips16 target in
1613 ORDER_REGS_FOR_LOCAL_ALLOC. */
1615 #define REG_ALLOC_ORDER \
1616 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1617 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1618 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1619 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1620 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1621 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1622 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1623 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1624 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1625 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1626 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1627 176,177,178,179,180,181,182,183,184,185,186,187 \
1630 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1631 to be rearranged based on a particular function. On the mips16, we
1632 want to allocate $24 (T_REG) before other registers for
1633 instructions for which it is possible. */
1635 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1637 /* REGISTER AND CONSTANT CLASSES */
1639 /* Get reg_class from a letter such as appears in the machine
1642 DEFINED REGISTER CLASSES:
1644 'd' General (aka integer) registers
1645 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1646 'y' General registers (in both mips16 and non mips16 mode)
1647 'e' Effective address registers (general registers except $25)
1648 't' mips16 temporary register ($24)
1649 'f' Floating point registers
1653 'x' Multiply/divide registers
1654 'z' FP Status register
1658 'A' DSP accumulator registers
1659 'a' MD registers and DSP accumulator registers
1660 'b' All registers */
1662 extern enum reg_class mips_char_to_class[256];
1664 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1666 /* True if VALUE is an unsigned 6-bit number. */
1668 #define UIMM6_OPERAND(VALUE) \
1669 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1671 /* True if VALUE is a signed 10-bit number. */
1673 #define IMM10_OPERAND(VALUE) \
1674 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1676 /* True if VALUE is a signed 16-bit number. */
1678 #define SMALL_OPERAND(VALUE) \
1679 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1681 /* True if VALUE is an unsigned 16-bit number. */
1683 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1684 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1686 /* True if VALUE can be loaded into a register using LUI. */
1688 #define LUI_OPERAND(VALUE) \
1689 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1690 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1692 /* Return a value X with the low 16 bits clear, and such that
1693 VALUE - X is a signed 16-bit value. */
1695 #define CONST_HIGH_PART(VALUE) \
1696 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1698 #define CONST_LOW_PART(VALUE) \
1699 ((VALUE) - CONST_HIGH_PART (VALUE))
1701 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1702 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1703 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1705 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1706 string can be used to stand for particular ranges of immediate
1707 operands. This macro defines what the ranges are. C is the
1708 letter, and VALUE is a constant value. Return 1 if VALUE is
1709 in the range specified by C. */
1713 `I' is used for the range of constants an arithmetic insn can
1714 actually contain (16 bits signed integers).
1716 `J' is used for the range which is just zero (i.e., $r0).
1718 `K' is used for the range of constants a logical insn can actually
1719 contain (16 bit zero-extended integers).
1721 `L' is used for the range of constants that be loaded with lui
1722 (i.e., the bottom 16 bits are zero).
1724 `M' is used for the range of constants that take two words to load
1725 (i.e., not matched by `I', `K', and `L').
1727 `N' is used for negative 16 bit constants other than -65536.
1729 `O' is a 15 bit signed integer.
1731 `P' is used for positive 16 bit constants. */
1733 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1734 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1735 : (C) == 'J' ? ((VALUE) == 0) \
1736 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1737 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1738 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1739 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1740 && !LUI_OPERAND (VALUE)) \
1741 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1742 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1743 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1746 /* Similar, but for floating constants, and defining letters G and H.
1747 Here VALUE is the CONST_DOUBLE rtx itself. */
1751 'G' : Floating point 0 */
1753 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1755 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1757 /* Letters in the range `Q' through `U' may be defined in a
1758 machine-dependent fashion to stand for arbitrary operand types.
1759 The machine description macro `EXTRA_CONSTRAINT' is passed the
1760 operand as its first argument and the constraint letter as its
1763 `Q' is for signed 16-bit constants.
1764 `R' is for single-instruction memory references. Note that this
1765 constraint has often been used in linux and glibc code.
1766 `S' is for legitimate constant call addresses.
1767 `T' is for constant move_operands that cannot be safely loaded into $25.
1768 `U' is for constant move_operands that can be safely loaded into $25.
1769 `W' is for memory references that are based on a member of BASE_REG_CLASS.
1770 This is true for all non-mips16 references (although it can sometimes
1771 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
1772 stack and constant-pool references.
1773 `YG' is for 0 valued vector constants.
1774 `YA' is for unsigned 6-bit constants.
1775 `YB' is for signed 10-bit constants. */
1777 #define EXTRA_CONSTRAINT_Y(OP,STR) \
1778 (((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
1779 && (OP) == CONST0_RTX (GET_MODE (OP))) \
1780 : ((STR)[1] == 'A') ? (GET_CODE (OP) == CONST_INT \
1781 && UIMM6_OPERAND (INTVAL (OP))) \
1782 : ((STR)[1] == 'B') ? (GET_CODE (OP) == CONST_INT \
1783 && IMM10_OPERAND (INTVAL (OP))) \
1787 #define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
1788 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
1789 : ((CODE) == 'R') ? (MEM_P (OP) \
1790 && mips_fetch_insns (OP) == 1) \
1791 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
1792 && call_insn_operand (OP, VOIDmode)) \
1793 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
1794 && move_operand (OP, VOIDmode) \
1795 && mips_dangerous_for_la25_p (OP)) \
1796 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
1797 && move_operand (OP, VOIDmode) \
1798 && !mips_dangerous_for_la25_p (OP)) \
1799 : ((CODE) == 'W') ? (MEM_P (OP) \
1800 && memory_operand (OP, VOIDmode) \
1801 && (!TARGET_MIPS16 \
1802 || (!stack_operand (OP, VOIDmode) \
1803 && !CONSTANT_P (XEXP (OP, 0))))) \
1804 : ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
1807 /* Y is the only multi-letter constraint, and has length 2. */
1809 #define CONSTRAINT_LEN(C,STR) \
1811 : DEFAULT_CONSTRAINT_LEN (C, STR))
1813 /* Say which of the above are memory constraints. */
1814 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
1816 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1817 mips_preferred_reload_class (X, CLASS)
1819 /* Certain machines have the property that some registers cannot be
1820 copied to some other registers without using memory. Define this
1821 macro on those machines to be a C expression that is nonzero if
1822 objects of mode MODE in registers of CLASS1 can only be copied to
1823 registers of class CLASS2 by storing a register of CLASS1 into
1824 memory and loading that memory location into a register of CLASS2.
1826 Do not define this macro if its value would always be zero. */
1828 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1829 ((!TARGET_DEBUG_H_MODE \
1830 && GET_MODE_CLASS (MODE) == MODE_INT \
1831 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1832 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1833 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1834 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1835 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1837 /* The HI and LO registers can only be reloaded via the general
1838 registers. Condition code registers can only be loaded to the
1839 general registers, and from the floating point registers. */
1841 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1842 mips_secondary_reload_class (CLASS, MODE, X, 1)
1843 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1844 mips_secondary_reload_class (CLASS, MODE, X, 0)
1846 /* Return the maximum number of consecutive registers
1847 needed to represent mode MODE in a register of class CLASS. */
1849 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1851 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1852 mips_cannot_change_mode_class (FROM, TO, CLASS)
1854 /* Stack layout; function entry, exit and calling. */
1856 #define STACK_GROWS_DOWNWARD
1858 /* The offset of the first local variable from the beginning of the frame.
1859 See compute_frame_size for details about the frame layout.
1861 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1862 we assume that we will need 16 bytes of argument space. This is because
1863 the value profiling code may emit calls to cmpdi2 in leaf functions.
1864 Without this hack, the local variables will start at sp+8 and the gp save
1865 area will be at sp+16, and thus they will overlap. compute_frame_size is
1866 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1867 will end up as 24 instead of 8. This won't be needed if profiling code is
1868 inserted before virtual register instantiation. */
1870 #define STARTING_FRAME_OFFSET \
1871 ((flag_profile_values && ! TARGET_64BIT \
1872 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1873 : current_function_outgoing_args_size) \
1874 + (TARGET_ABICALLS && !TARGET_NEWABI \
1875 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1877 #define RETURN_ADDR_RTX mips_return_addr
1879 /* Since the mips16 ISA mode is encoded in the least-significant bit
1880 of the address, mask it off return addresses for purposes of
1881 finding exception handling regions. */
1883 #define MASK_RETURN_ADDR GEN_INT (-2)
1886 /* Similarly, don't use the least-significant bit to tell pointers to
1887 code from vtable index. */
1889 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1891 /* The eliminations to $17 are only used for mips16 code. See the
1892 definition of HARD_FRAME_POINTER_REGNUM. */
1894 #define ELIMINABLE_REGS \
1895 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1896 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1897 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1898 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1899 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1900 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1902 /* We can always eliminate to the hard frame pointer. We can eliminate
1903 to the stack pointer unless a frame pointer is needed.
1905 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1906 reload may be unable to compute the address of a local variable,
1907 since there is no way to add a large constant to the stack pointer
1908 without using a temporary register. */
1909 #define CAN_ELIMINATE(FROM, TO) \
1910 ((TO) == HARD_FRAME_POINTER_REGNUM \
1911 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1912 && (!TARGET_MIPS16 \
1913 || compute_frame_size (get_frame_size ()) < 32768)))
1915 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1916 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1918 /* Allocate stack space for arguments at the beginning of each function. */
1919 #define ACCUMULATE_OUTGOING_ARGS 1
1921 /* The argument pointer always points to the first argument. */
1922 #define FIRST_PARM_OFFSET(FNDECL) 0
1924 /* o32 and o64 reserve stack space for all argument registers. */
1925 #define REG_PARM_STACK_SPACE(FNDECL) \
1927 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1930 /* Define this if it is the responsibility of the caller to
1931 allocate the area reserved for arguments passed in registers.
1932 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1933 of this macro is to determine whether the space is included in
1934 `current_function_outgoing_args_size'. */
1935 #define OUTGOING_REG_PARM_STACK_SPACE
1937 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1939 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1941 /* Symbolic macros for the registers used to return integer and floating
1944 #define GP_RETURN (GP_REG_FIRST + 2)
1945 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1947 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1949 /* Symbolic macros for the first/last argument registers. */
1951 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1952 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1953 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1954 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1956 #define LIBCALL_VALUE(MODE) \
1957 mips_function_value (NULL_TREE, NULL, (MODE))
1959 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1960 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1962 /* 1 if N is a possible register number for a function value.
1963 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1964 Currently, R2 and F0 are only implemented here (C has no complex type) */
1966 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1967 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1968 && (N) == FP_RETURN + 2))
1970 /* 1 if N is a possible register number for function argument passing.
1971 We have no FP argument registers when soft-float. When FP registers
1972 are 32 bits, we can't directly reference the odd numbered ones. */
1974 #define FUNCTION_ARG_REGNO_P(N) \
1975 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1976 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1979 /* This structure has to cope with two different argument allocation
1980 schemes. Most MIPS ABIs view the arguments as a structure, of which
1981 the first N words go in registers and the rest go on the stack. If I
1982 < N, the Ith word might go in Ith integer argument register or in a
1983 floating-point register. For these ABIs, we only need to remember
1984 the offset of the current argument into the structure.
1986 The EABI instead allocates the integer and floating-point arguments
1987 separately. The first N words of FP arguments go in FP registers,
1988 the rest go on the stack. Likewise, the first N words of the other
1989 arguments go in integer registers, and the rest go on the stack. We
1990 need to maintain three counts: the number of integer registers used,
1991 the number of floating-point registers used, and the number of words
1992 passed on the stack.
1994 We could keep separate information for the two ABIs (a word count for
1995 the standard ABIs, and three separate counts for the EABI). But it
1996 seems simpler to view the standard ABIs as forms of EABI that do not
1997 allocate floating-point registers.
1999 So for the standard ABIs, the first N words are allocated to integer
2000 registers, and function_arg decides on an argument-by-argument basis
2001 whether that argument should really go in an integer register, or in
2002 a floating-point one. */
2004 typedef struct mips_args {
2005 /* Always true for varargs functions. Otherwise true if at least
2006 one argument has been passed in an integer register. */
2009 /* The number of arguments seen so far. */
2010 unsigned int arg_number;
2012 /* The number of integer registers used so far. For all ABIs except
2013 EABI, this is the number of words that have been added to the
2014 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2015 unsigned int num_gprs;
2017 /* For EABI, the number of floating-point registers used so far. */
2018 unsigned int num_fprs;
2020 /* The number of words passed on the stack. */
2021 unsigned int stack_words;
2023 /* On the mips16, we need to keep track of which floating point
2024 arguments were passed in general registers, but would have been
2025 passed in the FP regs if this were a 32 bit function, so that we
2026 can move them to the FP regs if we wind up calling a 32 bit
2027 function. We record this information in fp_code, encoded in base
2028 four. A zero digit means no floating point argument, a one digit
2029 means an SFmode argument, and a two digit means a DFmode argument,
2030 and a three digit is not used. The low order digit is the first
2031 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2032 an SFmode argument. ??? A more sophisticated approach will be
2033 needed if MIPS_ABI != ABI_32. */
2036 /* True if the function has a prototype. */
2040 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2041 for a call to a function whose data type is FNTYPE.
2042 For a library call, FNTYPE is 0. */
2044 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2045 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2047 /* Update the data in CUM to advance over an argument
2048 of mode MODE and data type TYPE.
2049 (TYPE is null for libcalls where that information may not be available.) */
2051 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2052 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2054 /* Determine where to put an argument to a function.
2055 Value is zero to push the argument on the stack,
2056 or a hard register in which to store the argument.
2058 MODE is the argument's machine mode.
2059 TYPE is the data type of the argument (as a tree).
2060 This is null for libcalls where that information may
2062 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2063 the preceding args and about the function being called.
2064 NAMED is nonzero if this argument is a named parameter
2065 (otherwise it is an extra parameter matching an ellipsis). */
2067 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2068 function_arg( &CUM, MODE, TYPE, NAMED)
2070 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2072 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2073 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2075 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2076 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2078 /* True if using EABI and varargs can be passed in floating-point
2079 registers. Under these conditions, we need a more complex form
2080 of va_list, which tracks GPR, FPR and stack arguments separately. */
2081 #define EABI_FLOAT_VARARGS_P \
2082 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2085 /* Say that the epilogue uses the return address register. Note that
2086 in the case of sibcalls, the values "used by the epilogue" are
2087 considered live at the start of the called function. */
2088 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2090 /* Treat LOC as a byte offset from the stack pointer and round it up
2091 to the next fully-aligned offset. */
2092 #define MIPS_STACK_ALIGN(LOC) \
2093 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2096 /* Implement `va_start' for varargs and stdarg. */
2097 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2098 mips_va_start (valist, nextarg)
2100 /* Output assembler code to FILE to increment profiler label # LABELNO
2101 for profiling a function entry. */
2103 #define FUNCTION_PROFILER(FILE, LABELNO) \
2105 if (TARGET_MIPS16) \
2106 sorry ("mips16 function profiling"); \
2107 fprintf (FILE, "\t.set\tnoat\n"); \
2108 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2109 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2110 if (!TARGET_NEWABI) \
2113 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2114 TARGET_64BIT ? "dsubu" : "subu", \
2115 reg_names[STACK_POINTER_REGNUM], \
2116 reg_names[STACK_POINTER_REGNUM], \
2117 Pmode == DImode ? 16 : 8); \
2119 fprintf (FILE, "\tjal\t_mcount\n"); \
2120 fprintf (FILE, "\t.set\tat\n"); \
2123 /* No mips port has ever used the profiler counter word, so don't emit it
2124 or the label for it. */
2126 #define NO_PROFILE_COUNTERS 1
2128 /* Define this macro if the code for function profiling should come
2129 before the function prologue. Normally, the profiling code comes
2132 /* #define PROFILE_BEFORE_PROLOGUE */
2134 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2135 the stack pointer does not matter. The value is tested only in
2136 functions that have frame pointers.
2137 No definition is equivalent to always zero. */
2139 #define EXIT_IGNORE_STACK 1
2142 /* A C statement to output, on the stream FILE, assembler code for a
2143 block of data that contains the constant parts of a trampoline.
2144 This code should not include a label--the label is taken care of
2147 #define TRAMPOLINE_TEMPLATE(STREAM) \
2149 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2150 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2151 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2152 if (ptr_mode == DImode) \
2154 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2155 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2159 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2160 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2162 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2163 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2164 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2165 if (ptr_mode == DImode) \
2167 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2168 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2172 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2173 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2177 /* A C expression for the size in bytes of the trampoline, as an
2180 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2182 /* Alignment required for trampolines, in bits. */
2184 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2186 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2187 program and data caches. */
2189 #ifndef CACHE_FLUSH_FUNC
2190 #define CACHE_FLUSH_FUNC "_flush_cache"
2193 /* A C statement to initialize the variable parts of a trampoline.
2194 ADDR is an RTX for the address of the trampoline; FNADDR is an
2195 RTX for the address of the nested function; STATIC_CHAIN is an
2196 RTX for the static chain value that should be passed to the
2197 function when it is called. */
2199 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2201 rtx func_addr, chain_addr; \
2203 func_addr = plus_constant (ADDR, 32); \
2204 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2205 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2206 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2208 /* Flush both caches. We need to flush the data cache in case \
2209 the system has a write-back cache. */ \
2210 /* ??? Should check the return value for errors. */ \
2211 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2212 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2213 0, VOIDmode, 3, ADDR, Pmode, \
2214 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2215 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2218 /* Addressing modes, and classification of registers for them. */
2220 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2221 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2222 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2224 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2225 and check its validity for a certain class.
2226 We have two alternate definitions for each of them.
2227 The usual definition accepts all pseudo regs; the other rejects them all.
2228 The symbol REG_OK_STRICT causes the latter definition to be used.
2230 Most source files want to accept pseudo regs in the hope that
2231 they will get allocated to the class that the insn wants them to be in.
2232 Some source files that are used after register allocation
2233 need to be strict. */
2235 #ifndef REG_OK_STRICT
2236 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2237 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2239 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2240 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2243 #define REG_OK_FOR_INDEX_P(X) 0
2246 /* Maximum number of registers that can appear in a valid memory address. */
2248 #define MAX_REGS_PER_ADDRESS 1
2250 #ifdef REG_OK_STRICT
2251 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2253 if (mips_legitimate_address_p (MODE, X, 1)) \
2257 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2259 if (mips_legitimate_address_p (MODE, X, 0)) \
2264 /* Check for constness inline but use mips_legitimate_address_p
2265 to check whether a constant really is an address. */
2267 #define CONSTANT_ADDRESS_P(X) \
2268 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2270 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2272 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2274 if (mips_legitimize_address (&(X), MODE)) \
2279 /* A C statement or compound statement with a conditional `goto
2280 LABEL;' executed if memory address X (an RTX) can have different
2281 meanings depending on the machine mode of the memory reference it
2284 Autoincrement and autodecrement addresses typically have
2285 mode-dependent effects because the amount of the increment or
2286 decrement is the size of the operand being addressed. Some
2287 machines have other mode-dependent addresses. Many RISC machines
2288 have no mode-dependent addresses.
2290 You may assume that ADDR is a valid address for the machine. */
2292 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2294 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2295 'the start of the function that this code is output in'. */
2297 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2298 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2299 asm_fprintf ((FILE), "%U%s", \
2300 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2302 asm_fprintf ((FILE), "%U%s", (NAME))
2304 /* Flag to mark a function decl symbol that requires a long call. */
2305 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2306 #define SYMBOL_REF_LONG_CALL_P(X) \
2307 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2309 /* Specify the machine mode that this machine uses
2310 for the index in the tablejump instruction.
2311 ??? Using HImode in mips16 mode can cause overflow. */
2312 #define CASE_VECTOR_MODE \
2313 (TARGET_MIPS16 ? HImode : ptr_mode)
2315 /* Define as C expression which evaluates to nonzero if the tablejump
2316 instruction expects the table to contain offsets from the address of the
2318 Do not define this if the table should contain absolute addresses. */
2319 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2321 /* Define this as 1 if `char' should by default be signed; else as 0. */
2322 #ifndef DEFAULT_SIGNED_CHAR
2323 #define DEFAULT_SIGNED_CHAR 1
2326 /* Max number of bytes we can move from memory to memory
2327 in one reasonably fast instruction. */
2328 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2329 #define MAX_MOVE_MAX 8
2331 /* Define this macro as a C expression which is nonzero if
2332 accessing less than a word of memory (i.e. a `char' or a
2333 `short') is no faster than accessing a word of memory, i.e., if
2334 such access require more than one instruction or if there is no
2335 difference in cost between byte and (aligned) word loads.
2337 On RISC machines, it tends to generate better code to define
2338 this as 1, since it avoids making a QI or HI mode register. */
2339 #define SLOW_BYTE_ACCESS 1
2341 /* Define this to be nonzero if shift instructions ignore all but the low-order
2343 #define SHIFT_COUNT_TRUNCATED 1
2345 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2346 is done just by pretending it is already truncated. */
2347 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2348 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2351 /* Specify the machine mode that pointers have.
2352 After generation of rtl, the compiler makes no further distinction
2353 between pointers and any other objects of this machine mode. */
2356 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2359 /* Give call MEMs SImode since it is the "most permissive" mode
2360 for both 32-bit and 64-bit targets. */
2362 #define FUNCTION_MODE SImode
2365 /* The cost of loading values from the constant pool. It should be
2366 larger than the cost of any constant we want to synthesize in-line. */
2368 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2370 /* A C expression for the cost of moving data from a register in
2371 class FROM to one in class TO. The classes are expressed using
2372 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2373 the default; other values are interpreted relative to that.
2375 It is not required that the cost always equal 2 when FROM is the
2376 same as TO; on some machines it is expensive to move between
2377 registers if they are not general registers.
2379 If reload sees an insn consisting of a single `set' between two
2380 hard registers, and if `REGISTER_MOVE_COST' applied to their
2381 classes returns a value of 2, reload does not check to ensure
2382 that the constraints of the insn are met. Setting a cost of
2383 other than 2 will allow reload to verify that the constraints are
2384 met. You should do this if the `movM' pattern's constraints do
2385 not allow such copying. */
2387 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2388 mips_register_move_cost (MODE, FROM, TO)
2390 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2391 (mips_cost->memory_latency \
2392 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2394 /* Define if copies to/from condition code registers should be avoided.
2396 This is needed for the MIPS because reload_outcc is not complete;
2397 it needs to handle cases where the source is a general or another
2398 condition code register. */
2399 #define AVOID_CCMODE_COPIES
2401 /* A C expression for the cost of a branch instruction. A value of
2402 1 is the default; other values are interpreted relative to that. */
2404 #define BRANCH_COST mips_cost->branch_cost
2405 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2407 /* If defined, modifies the length assigned to instruction INSN as a
2408 function of the context in which it is used. LENGTH is an lvalue
2409 that contains the initially computed length of the insn and should
2410 be updated with the correct length of the insn. */
2411 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2412 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2414 /* Control the assembler format that we output. */
2416 /* Output to assembler file text saying following lines
2417 may contain character constants, extra white space, comments, etc. */
2420 #define ASM_APP_ON " #APP\n"
2423 /* Output to assembler file text saying following lines
2424 no longer contain unusual constructs. */
2427 #define ASM_APP_OFF " #NO_APP\n"
2430 #define REGISTER_NAMES \
2431 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2432 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2433 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2434 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2435 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2436 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2437 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2438 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2439 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2440 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2441 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2442 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2443 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2444 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2445 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2446 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2447 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2448 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2449 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2450 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2451 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2452 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2453 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2454 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2456 /* List the "software" names for each register. Also list the numerical
2457 names for $fp and $sp. */
2459 #define ADDITIONAL_REGISTER_NAMES \
2461 { "$29", 29 + GP_REG_FIRST }, \
2462 { "$30", 30 + GP_REG_FIRST }, \
2463 { "at", 1 + GP_REG_FIRST }, \
2464 { "v0", 2 + GP_REG_FIRST }, \
2465 { "v1", 3 + GP_REG_FIRST }, \
2466 { "a0", 4 + GP_REG_FIRST }, \
2467 { "a1", 5 + GP_REG_FIRST }, \
2468 { "a2", 6 + GP_REG_FIRST }, \
2469 { "a3", 7 + GP_REG_FIRST }, \
2470 { "t0", 8 + GP_REG_FIRST }, \
2471 { "t1", 9 + GP_REG_FIRST }, \
2472 { "t2", 10 + GP_REG_FIRST }, \
2473 { "t3", 11 + GP_REG_FIRST }, \
2474 { "t4", 12 + GP_REG_FIRST }, \
2475 { "t5", 13 + GP_REG_FIRST }, \
2476 { "t6", 14 + GP_REG_FIRST }, \
2477 { "t7", 15 + GP_REG_FIRST }, \
2478 { "s0", 16 + GP_REG_FIRST }, \
2479 { "s1", 17 + GP_REG_FIRST }, \
2480 { "s2", 18 + GP_REG_FIRST }, \
2481 { "s3", 19 + GP_REG_FIRST }, \
2482 { "s4", 20 + GP_REG_FIRST }, \
2483 { "s5", 21 + GP_REG_FIRST }, \
2484 { "s6", 22 + GP_REG_FIRST }, \
2485 { "s7", 23 + GP_REG_FIRST }, \
2486 { "t8", 24 + GP_REG_FIRST }, \
2487 { "t9", 25 + GP_REG_FIRST }, \
2488 { "k0", 26 + GP_REG_FIRST }, \
2489 { "k1", 27 + GP_REG_FIRST }, \
2490 { "gp", 28 + GP_REG_FIRST }, \
2491 { "sp", 29 + GP_REG_FIRST }, \
2492 { "fp", 30 + GP_REG_FIRST }, \
2493 { "ra", 31 + GP_REG_FIRST }, \
2494 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2497 /* This is meant to be redefined in the host dependent files. It is a
2498 set of alternative names and regnums for mips coprocessors. */
2500 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2502 /* A C compound statement to output to stdio stream STREAM the
2503 assembler syntax for an instruction operand X. X is an RTL
2506 CODE is a value that can be used to specify one of several ways
2507 of printing the operand. It is used when identical operands
2508 must be printed differently depending on the context. CODE
2509 comes from the `%' specification that was used to request
2510 printing of the operand. If the specification was just `%DIGIT'
2511 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2512 is the ASCII code for LTR.
2514 If X is a register, this macro should print the register's name.
2515 The names can be found in an array `reg_names' whose type is
2516 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2518 When the machine description has a specification `%PUNCT' (a `%'
2519 followed by a punctuation character), this macro is called with
2520 a null pointer for X and the punctuation character for CODE.
2522 See mips.c for the MIPS specific codes. */
2524 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2526 /* A C expression which evaluates to true if CODE is a valid
2527 punctuation character for use in the `PRINT_OPERAND' macro. If
2528 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2529 punctuation characters (except for the standard one, `%') are
2530 used in this way. */
2532 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2534 /* A C compound statement to output to stdio stream STREAM the
2535 assembler syntax for an instruction operand that is a memory
2536 reference whose address is ADDR. ADDR is an RTL expression. */
2538 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2541 /* A C statement, to be executed after all slot-filler instructions
2542 have been output. If necessary, call `dbr_sequence_length' to
2543 determine the number of slots filled in a sequence (zero if not
2544 currently outputting a sequence), to decide how many no-ops to
2545 output, or whatever.
2547 Don't define this macro if it has nothing to do, but it is
2548 helpful in reading assembly output if the extent of the delay
2549 sequence is made explicit (e.g. with white space).
2551 Note that output routines for instructions with delay slots must
2552 be prepared to deal with not being output as part of a sequence
2553 (i.e. when the scheduling pass is not run, or when no slot
2554 fillers could be found.) The variable `final_sequence' is null
2555 when not processing a sequence, otherwise it contains the
2556 `sequence' rtx being output. */
2558 #define DBR_OUTPUT_SEQEND(STREAM) \
2561 if (set_nomacro > 0 && --set_nomacro == 0) \
2562 fputs ("\t.set\tmacro\n", STREAM); \
2564 if (set_noreorder > 0 && --set_noreorder == 0) \
2565 fputs ("\t.set\treorder\n", STREAM); \
2567 fputs ("\n", STREAM); \
2572 /* How to tell the debugger about changes of source files. */
2573 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2574 mips_output_filename (STREAM, NAME)
2576 /* mips-tfile does not understand .stabd directives. */
2577 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2578 dbxout_begin_stabn_sline (LINE); \
2579 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2582 /* Use .loc directives for SDB line numbers. */
2583 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2584 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2586 /* The MIPS implementation uses some labels for its own purpose. The
2587 following lists what labels are created, and are all formed by the
2588 pattern $L[a-z].*. The machine independent portion of GCC creates
2589 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2591 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2592 $Lb[0-9]+ Begin blocks for MIPS debug support
2593 $Lc[0-9]+ Label for use in s<xx> operation.
2594 $Le[0-9]+ End blocks for MIPS debug support */
2596 #undef ASM_DECLARE_OBJECT_NAME
2597 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2598 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2600 /* Globalizing directive for a label. */
2601 #define GLOBAL_ASM_OP "\t.globl\t"
2603 /* This says how to define a global common symbol. */
2605 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2607 /* This says how to define a local common symbol (i.e., not visible to
2610 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2611 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2612 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2615 /* This says how to output an external. It would be possible not to
2616 output anything and let undefined symbol become external. However
2617 the assembler uses length information on externals to allocate in
2618 data/sdata bss/sbss, thereby saving exec time. */
2620 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2621 mips_output_external(STREAM,DECL,NAME)
2623 /* This is how to declare a function name. The actual work of
2624 emitting the label is moved to function_prologue, so that we can
2625 get the line number correctly emitted before the .ent directive,
2626 and after any .file directives. Define as empty so that the function
2627 is not declared before the .ent directive elsewhere. */
2629 #undef ASM_DECLARE_FUNCTION_NAME
2630 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2632 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2633 #define FUNCTION_NAME_ALREADY_DECLARED 0
2636 /* This is how to store into the string LABEL
2637 the symbol_ref name of an internal numbered label where
2638 PREFIX is the class of label and NUM is the number within the class.
2639 This is suitable for output with `assemble_name'. */
2641 #undef ASM_GENERATE_INTERNAL_LABEL
2642 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2643 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2645 /* This is how to output an element of a case-vector that is absolute. */
2647 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2648 fprintf (STREAM, "\t%s\t%sL%d\n", \
2649 ptr_mode == DImode ? ".dword" : ".word", \
2650 LOCAL_LABEL_PREFIX, \
2653 /* This is how to output an element of a case-vector. We can make the
2654 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2657 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2659 if (TARGET_MIPS16) \
2660 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2661 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2662 else if (TARGET_GPWORD) \
2663 fprintf (STREAM, "\t%s\t%sL%d\n", \
2664 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2665 LOCAL_LABEL_PREFIX, VALUE); \
2667 fprintf (STREAM, "\t%s\t%sL%d\n", \
2668 ptr_mode == DImode ? ".dword" : ".word", \
2669 LOCAL_LABEL_PREFIX, VALUE); \
2672 /* When generating MIPS16 code, we want the jump table to be in the text
2673 section so that we can load its address using a PC-relative addition. */
2674 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2676 /* This is how to output an assembler line
2677 that says to advance the location counter
2678 to a multiple of 2**LOG bytes. */
2680 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2681 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2683 /* This is how to output an assembler line to advance the location
2684 counter by SIZE bytes. */
2686 #undef ASM_OUTPUT_SKIP
2687 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2688 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2690 /* This is how to output a string. */
2691 #undef ASM_OUTPUT_ASCII
2692 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2693 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2695 /* Output #ident as a in the read-only data section. */
2696 #undef ASM_OUTPUT_IDENT
2697 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2699 const char *p = STRING; \
2700 int size = strlen (p) + 1; \
2701 readonly_data_section (); \
2702 assemble_string (p, size); \
2705 /* Default to -G 8 */
2706 #ifndef MIPS_DEFAULT_GVALUE
2707 #define MIPS_DEFAULT_GVALUE 8
2710 /* Define the strings to put out for each section in the object file. */
2711 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2712 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2713 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
2715 #undef READONLY_DATA_SECTION_ASM_OP
2716 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2718 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2721 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2722 TARGET_64BIT ? "dsubu" : "subu", \
2723 reg_names[STACK_POINTER_REGNUM], \
2724 reg_names[STACK_POINTER_REGNUM], \
2725 TARGET_64BIT ? "sd" : "sw", \
2727 reg_names[STACK_POINTER_REGNUM]); \
2731 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2734 if (! set_noreorder) \
2735 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2737 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2738 TARGET_64BIT ? "ld" : "lw", \
2740 reg_names[STACK_POINTER_REGNUM], \
2741 TARGET_64BIT ? "daddu" : "addu", \
2742 reg_names[STACK_POINTER_REGNUM], \
2743 reg_names[STACK_POINTER_REGNUM]); \
2745 if (! set_noreorder) \
2746 fprintf (STREAM, "\t.set\treorder\n"); \
2750 /* How to start an assembler comment.
2751 The leading space is important (the mips native assembler requires it). */
2752 #ifndef ASM_COMMENT_START
2753 #define ASM_COMMENT_START " #"
2756 /* Default definitions for size_t and ptrdiff_t. We must override the
2757 definitions from ../svr4.h on mips-*-linux-gnu. */
2760 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2763 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2766 /* Since the bits of the _init and _fini function is spread across
2767 many object files, each potentially with its own GP, we must assume
2768 we need to load our GP. We don't preserve $gp or $ra, since each
2769 init/fini chunk is supposed to initialize $gp, and crti/crtn
2770 already take care of preserving $ra and, when appropriate, $gp. */
2771 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2772 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2773 asm (SECTION_OP "\n\
2779 jal " USER_LABEL_PREFIX #FUNC "\n\
2780 " TEXT_SECTION_ASM_OP);
2781 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2782 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2783 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2784 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2785 asm (SECTION_OP "\n\
2790 .cpsetup $31, $2, 1b\n\
2791 jal " USER_LABEL_PREFIX #FUNC "\n\
2792 " TEXT_SECTION_ASM_OP);
2797 #define HAVE_AS_TLS 0
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