1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
56 #define STAB_CODE_TYPE enum __stab_debug_code
58 #define STAB_CODE_TYPE int
61 extern tree lookup_name PARAMS ((tree));
63 /* Enumeration for all of the relational tests, so that we can build
64 arrays indexed by the test type, and not worry about the order
83 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
84 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
86 static int m16_check_op PARAMS ((rtx, int, int, int));
87 static void block_move_loop PARAMS ((rtx, rtx,
91 static void block_move_call PARAMS ((rtx, rtx, rtx));
92 static FILE *mips_make_temp_file PARAMS ((void));
93 static void save_restore_insns PARAMS ((int, rtx,
95 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
96 static void mips16_fp_args PARAMS ((FILE *, int, int));
97 static void build_mips16_function_stub PARAMS ((FILE *));
98 static void mips16_optimize_gp PARAMS ((rtx));
99 static rtx add_constant PARAMS ((struct constant **,
102 static void dump_constants PARAMS ((struct constant *,
104 static rtx mips_find_symbol PARAMS ((rtx));
105 static void abort_with_insn PARAMS ((rtx, const char *))
107 static int symbolic_expression_p PARAMS ((rtx));
108 static void mips_add_gc_roots PARAMS ((void));
110 /* Global variables for machine-dependent things. */
112 /* Threshold for data being put into the small data/bss area, instead
113 of the normal data area (references to the small data/bss area take
114 1 instruction, and use the global pointer, references to the normal
115 data area takes 2 instructions). */
116 int mips_section_threshold = -1;
118 /* Count the number of .file directives, so that .loc is up to date. */
119 int num_source_filenames = 0;
121 /* Count the number of sdb related labels are generated (to find block
122 start and end boundaries). */
123 int sdb_label_count = 0;
125 /* Next label # for each statement for Silicon Graphics IRIS systems. */
128 /* Non-zero if inside of a function, because the stupid MIPS asm can't
129 handle .files inside of functions. */
130 int inside_function = 0;
132 /* Files to separate the text and the data output, so that all of the data
133 can be emitted before the text, which will mean that the assembler will
134 generate smaller code, based on the global pointer. */
135 FILE *asm_out_data_file;
136 FILE *asm_out_text_file;
138 /* Linked list of all externals that are to be emitted when optimizing
139 for the global pointer if they haven't been declared by the end of
140 the program with an appropriate .comm or initialization. */
144 struct extern_list *next; /* next external */
145 const char *name; /* name of the external */
146 int size; /* size in bytes */
149 /* Name of the file containing the current function. */
150 const char *current_function_file = "";
152 /* Warning given that Mips ECOFF can't support changing files
153 within a function. */
154 int file_in_function_warning = FALSE;
156 /* Whether to suppress issuing .loc's because the user attempted
157 to change the filename within a function. */
158 int ignore_line_number = FALSE;
160 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
166 /* The next branch instruction is a branch likely, not branch normal. */
167 int mips_branch_likely;
169 /* Count of delay slots and how many are filled. */
170 int dslots_load_total;
171 int dslots_load_filled;
172 int dslots_jump_total;
173 int dslots_jump_filled;
175 /* # of nops needed by previous insn */
176 int dslots_number_nops;
178 /* Number of 1/2/3 word references to data items (ie, not jal's). */
181 /* registers to check for load delay */
182 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
184 /* Cached operands, and operator to compare for use in set/branch/trap
185 on condition codes. */
188 /* what type of branch to use */
189 enum cmp_type branch_type;
191 /* Number of previously seen half-pic pointers and references. */
192 static int prev_half_pic_ptrs = 0;
193 static int prev_half_pic_refs = 0;
195 /* which cpu are we scheduling for */
196 enum processor_type mips_cpu;
198 /* which instruction set architecture to use. */
201 #ifdef MIPS_ABI_DEFAULT
202 /* Which ABI to use. This is defined to a constant in mips.h if the target
203 doesn't support multiple ABIs. */
207 /* Strings to hold which cpu and instruction set architecture to use. */
208 const char *mips_cpu_string; /* for -mcpu=<xxx> */
209 const char *mips_isa_string; /* for -mips{1,2,3,4} */
210 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
212 /* Whether we are generating mips16 code. This is a synonym for
213 TARGET_MIPS16, and exists for use as an attribute. */
216 /* This variable is set by -mno-mips16. We only care whether
217 -mno-mips16 appears or not, and using a string in this fashion is
218 just a way to avoid using up another bit in target_flags. */
219 const char *mips_no_mips16_string;
221 /* This is only used to determine if an type size setting option was
222 explicitly specified (-mlong64, -mint64, -mlong32). The specs
223 set this option if such an option is used. */
224 const char *mips_explicit_type_size_string;
226 /* Whether we are generating mips16 hard float code. In mips16 mode
227 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
228 -msoft-float was not specified by the user, which means that we
229 should arrange to call mips32 hard floating point code. */
230 int mips16_hard_float;
232 /* This variable is set by -mentry. We only care whether -mentry
233 appears or not, and using a string in this fashion is just a way to
234 avoid using up another bit in target_flags. */
235 const char *mips_entry_string;
237 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
240 /* If TRUE, we split addresses into their high and low parts in the RTL. */
241 int mips_split_addresses;
243 /* Generating calls to position independent functions? */
244 enum mips_abicalls_type mips_abicalls;
246 /* High and low marks for floating point values which we will accept
247 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
248 initialized in override_options. */
249 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
251 /* Mode used for saving/restoring general purpose registers. */
252 static enum machine_mode gpr_mode;
254 /* Array giving truth value on whether or not a given hard register
255 can support a given mode. */
256 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
258 /* Current frame information calculated by compute_frame_size. */
259 struct mips_frame_info current_frame_info;
261 /* Zero structure to initialize current_frame_info. */
262 struct mips_frame_info zero_frame_info;
264 /* Temporary filename used to buffer .text until end of program
266 static char *temp_filename;
268 /* Pseudo-reg holding the address of the current function when
269 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
270 by mips_finalize_pic if it was created. */
271 rtx embedded_pic_fnaddr_rtx;
273 /* The length of all strings seen when compiling for the mips16. This
274 is used to tell how many strings are in the constant pool, so that
275 we can see if we may have an overflow. This is reset each time the
276 constant pool is output. */
277 int mips_string_length;
279 /* Pseudo-reg holding the value of $28 in a mips16 function which
280 refers to GP relative global variables. */
281 rtx mips16_gp_pseudo_rtx;
283 /* In mips16 mode, we build a list of all the string constants we see
284 in a particular function. */
286 struct string_constant
288 struct string_constant *next;
292 static struct string_constant *string_constants;
294 /* List of all MIPS punctuation characters used by print_operand. */
295 char mips_print_operand_punct[256];
297 /* Map GCC register number to debugger register number. */
298 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
300 /* Buffer to use to enclose a load/store operation with %{ %} to
301 turn on .set volatile. */
302 static char volatile_buffer[60];
304 /* Hardware names for the registers. If -mrnames is used, this
305 will be overwritten with mips_sw_reg_names. */
307 char mips_reg_names[][8] =
309 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
310 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
311 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
312 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
313 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
314 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
315 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
316 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
317 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
318 "$fcc5","$fcc6","$fcc7","$rap"
321 /* Mips software names for the registers, used to overwrite the
322 mips_reg_names array. */
324 char mips_sw_reg_names[][8] =
326 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
327 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
328 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
329 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
330 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
331 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
332 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
333 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
334 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
335 "$fcc5","$fcc6","$fcc7","$rap"
338 /* Map hard register number to register class */
339 enum reg_class mips_regno_to_class[] =
341 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
342 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
343 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
344 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
345 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
346 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
347 T_REG, GR_REGS, GR_REGS, GR_REGS,
348 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
349 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
350 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
351 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
352 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
353 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
354 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
355 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
356 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
357 HI_REG, LO_REG, HILO_REG, ST_REGS,
358 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
359 ST_REGS, ST_REGS, ST_REGS, GR_REGS
362 /* Map register constraint character to register class. */
363 enum reg_class mips_char_to_class[256] =
365 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
366 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
367 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
368 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
369 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
370 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
371 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
432 /* Return truth value of whether OP can be used as an operands
433 where a register or 16 bit unsigned integer is needed. */
436 uns_arith_operand (op, mode)
438 enum machine_mode mode;
440 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
443 return register_operand (op, mode);
446 /* Return truth value of whether OP can be used as an operands
447 where a 16 bit integer is needed */
450 arith_operand (op, mode)
452 enum machine_mode mode;
454 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
457 /* On the mips16, a GP relative value is a signed 16 bit offset. */
458 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
461 return register_operand (op, mode);
464 /* Return truth value of whether OP can be used as an operand in a two
465 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
468 arith32_operand (op, mode)
470 enum machine_mode mode;
472 if (GET_CODE (op) == CONST_INT)
475 return register_operand (op, mode);
478 /* Return truth value of whether OP is a integer which fits in 16 bits */
483 enum machine_mode mode ATTRIBUTE_UNUSED;
485 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
488 /* Return truth value of whether OP is a 32 bit integer which is too big to
489 be loaded with one instruction. */
494 enum machine_mode mode ATTRIBUTE_UNUSED;
498 if (GET_CODE (op) != CONST_INT)
503 /* ior reg,$r0,value */
504 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
507 /* subu reg,$r0,value */
508 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
511 /* lui reg,value>>16 */
512 if ((value & 0x0000ffff) == 0)
518 /* Return truth value of whether OP is a register or the constant 0.
519 In mips16 mode, we only accept a register, since the mips16 does
523 reg_or_0_operand (op, mode)
525 enum machine_mode mode;
527 switch (GET_CODE (op))
532 return INTVAL (op) == 0;
537 return op == CONST0_RTX (mode);
541 return register_operand (op, mode);
550 /* Return truth value of whether OP is a register or the constant 0,
551 even in mips16 mode. */
554 true_reg_or_0_operand (op, mode)
556 enum machine_mode mode;
558 switch (GET_CODE (op))
561 return INTVAL (op) == 0;
564 return op == CONST0_RTX (mode);
568 return register_operand (op, mode);
577 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
580 mips_const_double_ok (op, mode)
582 enum machine_mode mode;
586 if (GET_CODE (op) != CONST_DOUBLE)
589 if (mode == VOIDmode)
592 if (mode != SFmode && mode != DFmode)
595 if (op == CONST0_RTX (mode))
598 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
599 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
602 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
604 if (REAL_VALUE_ISNAN (d))
607 if (REAL_VALUE_NEGATIVE (d))
608 d = REAL_VALUE_NEGATE (d);
612 if (REAL_VALUES_LESS (d, dfhigh)
613 && REAL_VALUES_LESS (dflow, d))
618 if (REAL_VALUES_LESS (d, sfhigh)
619 && REAL_VALUES_LESS (sflow, d))
626 /* Accept the floating point constant 1 in the appropriate mode. */
629 const_float_1_operand (op, mode)
631 enum machine_mode mode;
634 static REAL_VALUE_TYPE onedf;
635 static REAL_VALUE_TYPE onesf;
636 static int one_initialized;
638 if (GET_CODE (op) != CONST_DOUBLE
639 || mode != GET_MODE (op)
640 || (mode != DFmode && mode != SFmode))
643 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
645 /* We only initialize these values if we need them, since we will
646 never get called unless mips_isa >= 4. */
647 if (! one_initialized)
649 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
650 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
655 return REAL_VALUES_EQUAL (d, onedf);
657 return REAL_VALUES_EQUAL (d, onesf);
660 /* Return true if a memory load or store of REG plus OFFSET in MODE
661 can be represented in a single word on the mips16. */
664 mips16_simple_memory_operand (reg, offset, mode)
667 enum machine_mode mode;
674 /* We can't tell, because we don't know how the value will
675 eventually be accessed. Returning 0 here does no great
676 harm; it just prevents some possible instruction scheduling. */
680 size = GET_MODE_SIZE (mode);
682 if (INTVAL (offset) % size != 0)
684 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
688 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
693 /* Return truth value if a memory operand fits in a single instruction
694 (ie, register + small offset). */
697 simple_memory_operand (op, mode)
699 enum machine_mode mode;
701 rtx addr, plus0, plus1;
703 /* Eliminate non-memory operations */
704 if (GET_CODE (op) != MEM)
707 /* dword operations really put out 2 instructions, so eliminate them. */
708 /* ??? This isn't strictly correct. It is OK to accept multiword modes
709 here, since the length attributes are being set correctly, but only
710 if the address is offsettable. LO_SUM is not offsettable. */
711 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
714 /* Decode the address now. */
716 switch (GET_CODE (addr))
725 return SMALL_INT (addr);
728 plus0 = XEXP (addr, 0);
729 plus1 = XEXP (addr, 1);
730 if (GET_CODE (plus0) == REG
731 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
733 || mips16_simple_memory_operand (plus0, plus1, mode)))
736 else if (GET_CODE (plus1) == REG
737 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
739 || mips16_simple_memory_operand (plus1, plus0, mode)))
746 /* We used to allow small symbol refs here (ie, stuff in .sdata
747 or .sbss), but this causes some bugs in G++. Also, it won't
748 interfere if the MIPS linker rewrites the store instruction
749 because the function is PIC. */
751 case LABEL_REF: /* never gp relative */
755 /* If -G 0, we can never have a GP relative memory operation.
756 Also, save some time if not optimizing. */
761 rtx offset = const0_rtx;
762 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
763 if (GET_CODE (op) != SYMBOL_REF)
766 /* let's be paranoid.... */
767 if (! SMALL_INT (offset))
774 return SYMBOL_REF_FLAG (addr);
777 /* This SYMBOL_REF case is for the mips16. If the above case is
778 reenabled, this one should be merged in. */
780 /* References to the constant pool on the mips16 use a small
781 offset if the function is small. The only time we care about
782 getting this right is during delayed branch scheduling, so
783 don't need to check until then. The machine_dependent_reorg
784 function will set the total length of the instructions used
785 in the function in current_frame_info. If that is small
786 enough, we know for sure that this is a small offset. It
787 would be better if we could take into account the location of
788 the instruction within the function, but we can't, because we
789 don't know where we are. */
791 && CONSTANT_POOL_ADDRESS_P (addr)
792 && current_frame_info.insns_len > 0)
796 size = current_frame_info.insns_len + get_pool_size ();
797 if (GET_MODE_SIZE (mode) == 4)
798 return size < 4 * 0x100;
799 else if (GET_MODE_SIZE (mode) == 8)
800 return size < 8 * 0x20;
814 /* Return nonzero for a memory address that can be used to load or store
818 double_memory_operand (op, mode)
820 enum machine_mode mode;
824 if (GET_CODE (op) != MEM
825 || ! memory_operand (op, mode))
827 /* During reload, we accept a pseudo register if it has an
828 appropriate memory address. If we don't do this, we will
829 wind up reloading into a register, and then reloading that
830 register from memory, when we could just reload directly from
832 if (reload_in_progress
833 && GET_CODE (op) == REG
834 && REGNO (op) >= FIRST_PSEUDO_REGISTER
835 && reg_renumber[REGNO (op)] < 0
836 && reg_equiv_mem[REGNO (op)] != 0
837 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
840 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
841 the same test performed for 'm' in find_reloads. */
843 if (reload_in_progress
845 && (GET_CODE (op) == MEM
846 || (GET_CODE (op) == REG
847 && REGNO (op) >= FIRST_PSEUDO_REGISTER
848 && reg_renumber[REGNO (op)] < 0)))
851 if (reload_in_progress
853 && GET_CODE (op) == MEM)
859 /* During reload on the mips16, we accept a large offset
860 from the frame pointer or the stack pointer. This large
861 address will get reloaded anyhow. */
862 if (GET_CODE (addr) == PLUS
863 && GET_CODE (XEXP (addr, 0)) == REG
864 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
865 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
866 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
867 && ! SMALL_INT (XEXP (addr, 1)))
868 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
869 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
872 /* Similarly, we accept a case where the memory address is
873 itself on the stack, and will be reloaded. */
874 if (GET_CODE (addr) == MEM)
878 maddr = XEXP (addr, 0);
879 if (GET_CODE (maddr) == PLUS
880 && GET_CODE (XEXP (maddr, 0)) == REG
881 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
882 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
883 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
884 && ! SMALL_INT (XEXP (maddr, 1)))
885 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
886 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
890 /* We also accept the same case when we have a 16 bit signed
891 offset mixed in as well. The large address will get
892 reloaded, and the 16 bit offset will be OK. */
893 if (GET_CODE (addr) == PLUS
894 && GET_CODE (XEXP (addr, 0)) == MEM
895 && GET_CODE (XEXP (addr, 1)) == CONST_INT
896 && SMALL_INT (XEXP (addr, 1)))
898 addr = XEXP (XEXP (addr, 0), 0);
899 if (GET_CODE (addr) == PLUS
900 && GET_CODE (XEXP (addr, 0)) == REG
901 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
902 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
903 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
904 && ! SMALL_INT (XEXP (addr, 1)))
905 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
906 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
916 /* In this case we can use an instruction like sd. */
920 /* Make sure that 4 added to the address is a valid memory address.
921 This essentially just checks for overflow in an added constant. */
925 if (CONSTANT_ADDRESS_P (addr))
928 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
931 plus_constant_for_output (addr, 4));
934 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
937 equality_op (op, mode)
939 enum machine_mode mode;
941 if (mode != GET_MODE (op))
944 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
947 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
952 enum machine_mode mode;
954 if (mode != GET_MODE (op))
957 return GET_RTX_CLASS (GET_CODE (op)) == '<';
960 /* Return nonzero if the code is a relational operation suitable for a
961 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
962 We need this in the insn that expands `trap_if' in order to prevent
963 combine from erroneously altering the condition. */
966 trap_cmp_op (op, mode)
968 enum machine_mode mode;
970 if (mode != GET_MODE (op))
973 switch (GET_CODE (op))
988 /* Return nonzero if the operand is either the PC or a label_ref. */
991 pc_or_label_operand (op, mode)
993 enum machine_mode mode ATTRIBUTE_UNUSED;
998 if (GET_CODE (op) == LABEL_REF)
1004 /* Test for a valid operand for a call instruction.
1005 Don't allow the arg pointer register or virtual regs
1006 since they may change into reg + const, which the patterns
1007 can't handle yet. */
1010 call_insn_operand (op, mode)
1012 enum machine_mode mode ATTRIBUTE_UNUSED;
1014 return (CONSTANT_ADDRESS_P (op)
1015 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1016 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1017 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1020 /* Return nonzero if OPERAND is valid as a source operand for a move
1024 move_operand (op, mode)
1026 enum machine_mode mode;
1028 /* Accept any general operand after reload has started; doing so
1029 avoids losing if reload does an in-place replacement of a register
1030 with a SYMBOL_REF or CONST. */
1031 return (general_operand (op, mode)
1032 && (! (mips_split_addresses && mips_check_split (op, mode))
1033 || reload_in_progress || reload_completed)
1035 && GET_CODE (op) == SYMBOL_REF
1036 && ! mips16_constant (op, mode, 1, 0)));
1039 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1040 This accepts not only general_operand, but also sign extended
1041 constants and registers. We need to accept sign extended constants
1042 in case a sign extended register which is used in an expression,
1043 and is equivalent to a constant, is spilled. */
1046 movdi_operand (op, mode)
1048 enum machine_mode mode;
1052 && GET_CODE (op) == SIGN_EXTEND
1053 && GET_MODE (op) == DImode
1054 && (GET_MODE (XEXP (op, 0)) == SImode
1055 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1056 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1057 && (register_operand (XEXP (op, 0), SImode)
1058 || immediate_operand (XEXP (op, 0), SImode)))
1061 return (general_operand (op, mode)
1063 && GET_CODE (op) == SYMBOL_REF
1064 && ! mips16_constant (op, mode, 1, 0)));
1067 /* Like register_operand, but when in 64 bit mode also accept a sign
1068 extend of a 32 bit register, since the value is known to be already
1072 se_register_operand (op, mode)
1074 enum machine_mode mode;
1078 && GET_CODE (op) == SIGN_EXTEND
1079 && GET_MODE (op) == DImode
1080 && GET_MODE (XEXP (op, 0)) == SImode
1081 && register_operand (XEXP (op, 0), SImode))
1084 return register_operand (op, mode);
1087 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1088 extend of a 32 bit register, since the value is known to be already
1092 se_reg_or_0_operand (op, mode)
1094 enum machine_mode mode;
1098 && GET_CODE (op) == SIGN_EXTEND
1099 && GET_MODE (op) == DImode
1100 && GET_MODE (XEXP (op, 0)) == SImode
1101 && register_operand (XEXP (op, 0), SImode))
1104 return reg_or_0_operand (op, mode);
1107 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1108 extend of a 32 bit register, since the value is known to be already
1112 se_uns_arith_operand (op, mode)
1114 enum machine_mode mode;
1118 && GET_CODE (op) == SIGN_EXTEND
1119 && GET_MODE (op) == DImode
1120 && GET_MODE (XEXP (op, 0)) == SImode
1121 && register_operand (XEXP (op, 0), SImode))
1124 return uns_arith_operand (op, mode);
1127 /* Like arith_operand, but when in 64 bit mode also accept a sign
1128 extend of a 32 bit register, since the value is known to be already
1132 se_arith_operand (op, mode)
1134 enum machine_mode mode;
1138 && GET_CODE (op) == SIGN_EXTEND
1139 && GET_MODE (op) == DImode
1140 && GET_MODE (XEXP (op, 0)) == SImode
1141 && register_operand (XEXP (op, 0), SImode))
1144 return arith_operand (op, mode);
1147 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1148 extend of a 32 bit register, since the value is known to be already
1152 se_nonmemory_operand (op, mode)
1154 enum machine_mode mode;
1158 && GET_CODE (op) == SIGN_EXTEND
1159 && GET_MODE (op) == DImode
1160 && GET_MODE (XEXP (op, 0)) == SImode
1161 && register_operand (XEXP (op, 0), SImode))
1164 return nonmemory_operand (op, mode);
1167 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1168 sign extend of a 32 bit register, since the value is known to be
1169 already sign extended. */
1172 se_nonimmediate_operand (op, mode)
1174 enum machine_mode mode;
1178 && GET_CODE (op) == SIGN_EXTEND
1179 && GET_MODE (op) == DImode
1180 && GET_MODE (XEXP (op, 0)) == SImode
1181 && register_operand (XEXP (op, 0), SImode))
1184 return nonimmediate_operand (op, mode);
1187 /* Accept any operand that can appear in a mips16 constant table
1188 instruction. We can't use any of the standard operand functions
1189 because for these instructions we accept values that are not
1190 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1193 consttable_operand (op, mode)
1195 enum machine_mode mode ATTRIBUTE_UNUSED;
1197 return CONSTANT_P (op);
1200 /* Return nonzero if we split the address into high and low parts. */
1202 /* ??? We should also handle reg+array somewhere. We get four
1203 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1204 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1205 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1206 out of the address, then we have 4 instructions to combine. Perhaps
1207 add a 3->2 define_split for combine. */
1209 /* ??? We could also split a CONST_INT here if it is a large_int().
1210 However, it doesn't seem to be very useful to have %hi(constant).
1211 We would be better off by doing the masking ourselves and then putting
1212 the explicit high part of the constant in the RTL. This will give better
1213 optimization. Also, %hi(constant) needs assembler changes to work.
1214 There is already a define_split that does this. */
1217 mips_check_split (address, mode)
1219 enum machine_mode mode;
1221 /* ??? This is the same check used in simple_memory_operand.
1222 We use it here because LO_SUM is not offsettable. */
1223 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1226 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1227 || (GET_CODE (address) == CONST
1228 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1229 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1230 || GET_CODE (address) == LABEL_REF)
1236 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1239 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1241 enum machine_mode mode;
1245 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1246 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1249 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1250 returns a nonzero value if XINSN is a legitimate address for a
1251 memory operand of the indicated MODE. STRICT is non-zero if this
1252 function is called during reload. */
1255 mips_legitimate_address_p (mode, xinsn, strict)
1256 enum machine_mode mode;
1260 if (TARGET_DEBUG_B_MODE)
1262 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1263 strict ? "" : "not ");
1264 GO_DEBUG_RTX (xinsn);
1267 /* Check for constant before stripping off SUBREG, so that we don't
1268 accept (subreg (const_int)) which will fail to reload. */
1269 if (CONSTANT_ADDRESS_P (xinsn)
1270 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1271 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1274 while (GET_CODE (xinsn) == SUBREG)
1275 xinsn = SUBREG_REG (xinsn);
1277 /* The mips16 can only use the stack pointer as a base register when
1278 loading SImode or DImode values. */
1279 if (GET_CODE (xinsn) == REG
1280 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1283 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1285 register rtx xlow0 = XEXP (xinsn, 0);
1286 register rtx xlow1 = XEXP (xinsn, 1);
1288 while (GET_CODE (xlow0) == SUBREG)
1289 xlow0 = SUBREG_REG (xlow0);
1290 if (GET_CODE (xlow0) == REG
1291 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1292 && mips_check_split (xlow1, mode))
1296 if (GET_CODE (xinsn) == PLUS)
1298 register rtx xplus0 = XEXP (xinsn, 0);
1299 register rtx xplus1 = XEXP (xinsn, 1);
1300 register enum rtx_code code0;
1301 register enum rtx_code code1;
1303 while (GET_CODE (xplus0) == SUBREG)
1304 xplus0 = SUBREG_REG (xplus0);
1305 code0 = GET_CODE (xplus0);
1307 while (GET_CODE (xplus1) == SUBREG)
1308 xplus1 = SUBREG_REG (xplus1);
1309 code1 = GET_CODE (xplus1);
1311 /* The mips16 can only use the stack pointer as a base register
1312 when loading SImode or DImode values. */
1314 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1316 if (code1 == CONST_INT && SMALL_INT (xplus1))
1319 /* On the mips16, we represent GP relative offsets in RTL.
1320 These are 16 bit signed values, and can serve as register
1323 && mips16_gp_offset_p (xplus1))
1326 /* For some code sequences, you actually get better code by
1327 pretending that the MIPS supports an address mode of a
1328 constant address + a register, even though the real
1329 machine doesn't support it. This is because the
1330 assembler can use $r1 to load just the high 16 bits, add
1331 in the register, and fold the low 16 bits into the memory
1332 reference, whereas the compiler generates a 4 instruction
1333 sequence. On the other hand, CSE is not as effective.
1334 It would be a win to generate the lui directly, but the
1335 MIPS assembler does not have syntax to generate the
1336 appropriate relocation. */
1338 /* Also accept CONST_INT addresses here, so no else. */
1339 /* Reject combining an embedded PIC text segment reference
1340 with a register. That requires an additional
1342 /* ??? Reject combining an address with a register for the MIPS
1343 64 bit ABI, because the SGI assembler can not handle this. */
1344 if (!TARGET_DEBUG_A_MODE
1345 && (mips_abi == ABI_32
1346 || mips_abi == ABI_O64
1347 || mips_abi == ABI_EABI)
1348 && CONSTANT_ADDRESS_P (xplus1)
1349 && ! mips_split_addresses
1350 && (!TARGET_EMBEDDED_PIC
1352 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1353 /* When assembling for machines with 64 bit registers,
1354 the assembler will not sign-extend the constant "foo"
1355 in "la x, foo(x)" */
1356 && (!TARGET_64BIT || (INTVAL (xplus1) > 0))
1362 if (TARGET_DEBUG_B_MODE)
1363 GO_PRINTF ("Not a legitimate address\n");
1365 /* The address was not legitimate. */
1370 /* We need a lot of little routines to check constant values on the
1371 mips16. These are used to figure out how long the instruction will
1372 be. It would be much better to do this using constraints, but
1373 there aren't nearly enough letters available. */
1376 m16_check_op (op, low, high, mask)
1382 return (GET_CODE (op) == CONST_INT
1383 && INTVAL (op) >= low
1384 && INTVAL (op) <= high
1385 && (INTVAL (op) & mask) == 0);
1389 m16_uimm3_b (op, mode)
1391 enum machine_mode mode ATTRIBUTE_UNUSED;
1393 return m16_check_op (op, 0x1, 0x8, 0);
1397 m16_simm4_1 (op, mode)
1399 enum machine_mode mode ATTRIBUTE_UNUSED;
1401 return m16_check_op (op, - 0x8, 0x7, 0);
1405 m16_nsimm4_1 (op, mode)
1407 enum machine_mode mode ATTRIBUTE_UNUSED;
1409 return m16_check_op (op, - 0x7, 0x8, 0);
1413 m16_simm5_1 (op, mode)
1415 enum machine_mode mode ATTRIBUTE_UNUSED;
1417 return m16_check_op (op, - 0x10, 0xf, 0);
1421 m16_nsimm5_1 (op, mode)
1423 enum machine_mode mode ATTRIBUTE_UNUSED;
1425 return m16_check_op (op, - 0xf, 0x10, 0);
1429 m16_uimm5_4 (op, mode)
1431 enum machine_mode mode ATTRIBUTE_UNUSED;
1433 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1437 m16_nuimm5_4 (op, mode)
1439 enum machine_mode mode ATTRIBUTE_UNUSED;
1441 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1445 m16_simm8_1 (op, mode)
1447 enum machine_mode mode ATTRIBUTE_UNUSED;
1449 return m16_check_op (op, - 0x80, 0x7f, 0);
1453 m16_nsimm8_1 (op, mode)
1455 enum machine_mode mode ATTRIBUTE_UNUSED;
1457 return m16_check_op (op, - 0x7f, 0x80, 0);
1461 m16_uimm8_1 (op, mode)
1463 enum machine_mode mode ATTRIBUTE_UNUSED;
1465 return m16_check_op (op, 0x0, 0xff, 0);
1469 m16_nuimm8_1 (op, mode)
1471 enum machine_mode mode ATTRIBUTE_UNUSED;
1473 return m16_check_op (op, - 0xff, 0x0, 0);
1477 m16_uimm8_m1_1 (op, mode)
1479 enum machine_mode mode ATTRIBUTE_UNUSED;
1481 return m16_check_op (op, - 0x1, 0xfe, 0);
1485 m16_uimm8_4 (op, mode)
1487 enum machine_mode mode ATTRIBUTE_UNUSED;
1489 return m16_check_op (op, 0x0, 0xff << 2, 3);
1493 m16_nuimm8_4 (op, mode)
1495 enum machine_mode mode ATTRIBUTE_UNUSED;
1497 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1501 m16_simm8_8 (op, mode)
1503 enum machine_mode mode ATTRIBUTE_UNUSED;
1505 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1509 m16_nsimm8_8 (op, mode)
1511 enum machine_mode mode ATTRIBUTE_UNUSED;
1513 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1516 /* References to the string table on the mips16 only use a small
1517 offset if the function is small. See the comment in the SYMBOL_REF
1518 case in simple_memory_operand. We can't check for LABEL_REF here,
1519 because the offset is always large if the label is before the
1520 referencing instruction. */
1523 m16_usym8_4 (op, mode)
1525 enum machine_mode mode ATTRIBUTE_UNUSED;
1527 if (GET_CODE (op) == SYMBOL_REF
1528 && SYMBOL_REF_FLAG (op)
1529 && current_frame_info.insns_len > 0
1530 && XSTR (op, 0)[0] == '*'
1531 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1532 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1533 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1536 struct string_constant *l;
1538 /* Make sure this symbol is on thelist of string constants to be
1539 output for this function. It is possible that it has already
1540 been output, in which case this requires a large offset. */
1541 for (l = string_constants; l != NULL; l = l->next)
1542 if (strcmp (l->label, XSTR (op, 0)) == 0)
1550 m16_usym5_4 (op, mode)
1552 enum machine_mode mode ATTRIBUTE_UNUSED;
1554 if (GET_CODE (op) == SYMBOL_REF
1555 && SYMBOL_REF_FLAG (op)
1556 && current_frame_info.insns_len > 0
1557 && XSTR (op, 0)[0] == '*'
1558 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1559 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1560 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1563 struct string_constant *l;
1565 /* Make sure this symbol is on thelist of string constants to be
1566 output for this function. It is possible that it has already
1567 been output, in which case this requires a large offset. */
1568 for (l = string_constants; l != NULL; l = l->next)
1569 if (strcmp (l->label, XSTR (op, 0)) == 0)
1576 /* Returns an operand string for the given instruction's delay slot,
1577 after updating filled delay slot statistics.
1579 We assume that operands[0] is the target register that is set.
1581 In order to check the next insn, most of this functionality is moved
1582 to FINAL_PRESCAN_INSN, and we just set the global variables that
1585 /* ??? This function no longer does anything useful, because final_prescan_insn
1586 now will never emit a nop. */
1589 mips_fill_delay_slot (ret, type, operands, cur_insn)
1590 const char *ret; /* normal string to return */
1591 enum delay_type type; /* type of delay */
1592 rtx operands[]; /* operands to use */
1593 rtx cur_insn; /* current insn */
1595 register rtx set_reg;
1596 register enum machine_mode mode;
1597 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1598 register int num_nops;
1600 if (type == DELAY_LOAD || type == DELAY_FCMP)
1603 else if (type == DELAY_HILO)
1609 /* Make sure that we don't put nop's after labels. */
1610 next_insn = NEXT_INSN (cur_insn);
1611 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1612 next_insn = NEXT_INSN (next_insn);
1614 dslots_load_total += num_nops;
1615 if (TARGET_DEBUG_F_MODE
1617 || type == DELAY_NONE
1621 || GET_CODE (next_insn) == CODE_LABEL
1622 || (set_reg = operands[0]) == 0)
1624 dslots_number_nops = 0;
1632 set_reg = operands[0];
1636 while (GET_CODE (set_reg) == SUBREG)
1637 set_reg = SUBREG_REG (set_reg);
1639 mode = GET_MODE (set_reg);
1640 dslots_number_nops = num_nops;
1641 mips_load_reg = set_reg;
1642 if (GET_MODE_SIZE (mode)
1643 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1644 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1648 if (type == DELAY_HILO)
1650 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1651 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1663 /* Determine whether a memory reference takes one (based off of the GP
1664 pointer), two (normal), or three (label + reg) instructions, and bump the
1665 appropriate counter for -mstats. */
1668 mips_count_memory_refs (op, num)
1674 rtx addr, plus0, plus1;
1675 enum rtx_code code0, code1;
1678 if (TARGET_DEBUG_B_MODE)
1680 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1684 /* Skip MEM if passed, otherwise handle movsi of address. */
1685 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1687 /* Loop, going through the address RTL. */
1691 switch (GET_CODE (addr))
1699 plus0 = XEXP (addr, 0);
1700 plus1 = XEXP (addr, 1);
1701 code0 = GET_CODE (plus0);
1702 code1 = GET_CODE (plus1);
1712 if (code0 == CONST_INT)
1727 if (code1 == CONST_INT)
1734 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1741 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1751 n_words = 2; /* always 2 words */
1755 addr = XEXP (addr, 0);
1760 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1772 n_words += additional;
1776 num_refs[n_words-1] += num;
1780 /* Return RTL for the offset from the current function to the argument.
1782 ??? Which argument is this? */
1785 embedded_pic_offset (x)
1788 if (embedded_pic_fnaddr_rtx == NULL)
1792 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1794 /* Output code at function start to initialize the pseudo-reg. */
1795 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1796 inline functions, because it is called after RTL for the function
1797 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1798 does not get copied, and ends up not matching the rest of the RTL.
1799 This solution works, but means that we get unnecessary code to
1800 initialize this value every time a function is inlined into another
1803 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1804 XEXP (DECL_RTL (current_function_decl), 0)));
1805 seq = gen_sequence ();
1807 push_topmost_sequence ();
1808 emit_insn_after (seq, get_insns ());
1809 pop_topmost_sequence ();
1813 gen_rtx_CONST (Pmode,
1814 gen_rtx_MINUS (Pmode, x,
1815 XEXP (DECL_RTL (current_function_decl), 0)));
1818 /* Return the appropriate instructions to move one operand to another. */
1821 mips_move_1word (operands, insn, unsignedp)
1826 const char *ret = 0;
1827 rtx op0 = operands[0];
1828 rtx op1 = operands[1];
1829 enum rtx_code code0 = GET_CODE (op0);
1830 enum rtx_code code1 = GET_CODE (op1);
1831 enum machine_mode mode = GET_MODE (op0);
1832 int subreg_offset0 = 0;
1833 int subreg_offset1 = 0;
1834 enum delay_type delay = DELAY_NONE;
1836 while (code0 == SUBREG)
1838 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
1839 GET_MODE (SUBREG_REG (op0)),
1842 op0 = SUBREG_REG (op0);
1843 code0 = GET_CODE (op0);
1846 while (code1 == SUBREG)
1848 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
1849 GET_MODE (SUBREG_REG (op1)),
1852 op1 = SUBREG_REG (op1);
1853 code1 = GET_CODE (op1);
1856 /* For our purposes, a condition code mode is the same as SImode. */
1862 int regno0 = REGNO (op0) + subreg_offset0;
1866 int regno1 = REGNO (op1) + subreg_offset1;
1868 /* Just in case, don't do anything for assigning a register
1869 to itself, unless we are filling a delay slot. */
1870 if (regno0 == regno1 && set_nomacro == 0)
1873 else if (GP_REG_P (regno0))
1875 if (GP_REG_P (regno1))
1876 ret = "move\t%0,%1";
1878 else if (MD_REG_P (regno1))
1881 if (regno1 != HILO_REGNUM)
1887 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
1888 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1893 if (FP_REG_P (regno1))
1894 ret = "mfc1\t%0,%1";
1896 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
1897 ret = "cfc1\t%0,$31";
1901 else if (FP_REG_P (regno0))
1903 if (GP_REG_P (regno1))
1906 ret = "mtc1\t%1,%0";
1909 if (FP_REG_P (regno1))
1910 ret = "mov.s\t%0,%1";
1913 else if (MD_REG_P (regno0))
1915 if (GP_REG_P (regno1))
1918 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1923 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
1925 if (GP_REG_P (regno1))
1928 ret = "ctc1\t%0,$31";
1933 else if (code1 == MEM)
1938 mips_count_memory_refs (op1, 1);
1940 if (GP_REG_P (regno0))
1942 /* For loads, use the mode of the memory item, instead of the
1943 target, so zero/sign extend can use this code as well. */
1944 switch (GET_MODE (op1))
1953 ret = ((unsignedp && TARGET_64BIT)
1958 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1961 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1966 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1969 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1971 size_t i = strlen (ret);
1972 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1975 sprintf (volatile_buffer, "%%{%s%%}", ret);
1976 ret = volatile_buffer;
1980 else if (code1 == CONST_INT
1981 || (code1 == CONST_DOUBLE
1982 && GET_MODE (op1) == VOIDmode))
1984 if (code1 == CONST_DOUBLE)
1986 /* This can happen when storing constants into long long
1987 bitfields. Just store the least significant word of
1989 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1992 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
1994 if (GP_REG_P (regno0))
1995 ret = "move\t%0,%z1";
1997 else if (FP_REG_P (regno0))
2000 ret = "mtc1\t%z1,%0";
2003 else if (MD_REG_P (regno0))
2010 else if (GP_REG_P (regno0))
2012 /* Don't use X format, because that will give out of
2013 range numbers for 64 bit host and 32 bit target. */
2014 if (! TARGET_MIPS16)
2015 ret = "li\t%0,%1\t\t\t# %X1";
2018 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2020 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2021 ret = "li\t%0,%n1\n\tneg\t%0";
2026 else if (code1 == CONST_DOUBLE && mode == SFmode)
2028 if (op1 == CONST0_RTX (SFmode))
2030 if (GP_REG_P (regno0))
2031 ret = "move\t%0,%.";
2033 else if (FP_REG_P (regno0))
2036 ret = "mtc1\t%.,%0";
2043 ret = "li.s\t%0,%1";
2047 else if (code1 == LABEL_REF)
2050 mips_count_memory_refs (op1, 1);
2055 else if (code1 == SYMBOL_REF || code1 == CONST)
2057 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
2059 rtx offset = const0_rtx;
2061 if (GET_CODE (op1) == CONST)
2062 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2064 if (GET_CODE (op1) == SYMBOL_REF)
2066 operands[2] = HALF_PIC_PTR (op1);
2069 mips_count_memory_refs (operands[2], 1);
2071 if (INTVAL (offset) == 0)
2074 ret = (unsignedp && TARGET_64BIT
2080 dslots_load_total++;
2081 operands[3] = offset;
2082 if (unsignedp && TARGET_64BIT)
2083 ret = (SMALL_INT (offset)
2084 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2085 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2087 ret = (SMALL_INT (offset)
2088 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2089 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2093 else if (TARGET_MIPS16
2095 && GET_CODE (XEXP (op1, 0)) == REG
2096 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2098 /* This case arises on the mips16; see
2099 mips16_gp_pseudo_reg. */
2100 ret = "move\t%0,%+";
2102 else if (TARGET_MIPS16
2103 && code1 == SYMBOL_REF
2104 && SYMBOL_REF_FLAG (op1)
2105 && (XSTR (op1, 0)[0] != '*'
2106 || strncmp (XSTR (op1, 0) + 1,
2108 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2110 /* This can occur when reloading the address of a GP
2111 relative symbol on the mips16. */
2112 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2117 mips_count_memory_refs (op1, 1);
2123 else if (code1 == PLUS)
2125 rtx add_op0 = XEXP (op1, 0);
2126 rtx add_op1 = XEXP (op1, 1);
2128 if (GET_CODE (XEXP (op1, 1)) == REG
2129 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2130 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2132 operands[2] = add_op0;
2133 operands[3] = add_op1;
2134 ret = "add%:\t%0,%2,%3";
2137 else if (code1 == HIGH)
2139 operands[1] = XEXP (op1, 0);
2140 ret = "lui\t%0,%%hi(%1)";
2144 else if (code0 == MEM)
2147 mips_count_memory_refs (op0, 1);
2151 int regno1 = REGNO (op1) + subreg_offset1;
2153 if (GP_REG_P (regno1))
2157 case SFmode: ret = "sw\t%1,%0"; break;
2158 case SImode: ret = "sw\t%1,%0"; break;
2159 case HImode: ret = "sh\t%1,%0"; break;
2160 case QImode: ret = "sb\t%1,%0"; break;
2165 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2169 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2173 case SFmode: ret = "sw\t%z1,%0"; break;
2174 case SImode: ret = "sw\t%z1,%0"; break;
2175 case HImode: ret = "sh\t%z1,%0"; break;
2176 case QImode: ret = "sb\t%z1,%0"; break;
2181 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2185 case SFmode: ret = "sw\t%.,%0"; break;
2186 case SImode: ret = "sw\t%.,%0"; break;
2187 case HImode: ret = "sh\t%.,%0"; break;
2188 case QImode: ret = "sb\t%.,%0"; break;
2193 if (ret != 0 && MEM_VOLATILE_P (op0))
2195 size_t i = strlen (ret);
2197 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2200 sprintf (volatile_buffer, "%%{%s%%}", ret);
2201 ret = volatile_buffer;
2207 abort_with_insn (insn, "Bad move");
2211 if (delay != DELAY_NONE)
2212 return mips_fill_delay_slot (ret, delay, operands, insn);
2218 /* Return the appropriate instructions to move 2 words */
2221 mips_move_2words (operands, insn)
2225 const char *ret = 0;
2226 rtx op0 = operands[0];
2227 rtx op1 = operands[1];
2228 enum rtx_code code0 = GET_CODE (operands[0]);
2229 enum rtx_code code1 = GET_CODE (operands[1]);
2230 int subreg_offset0 = 0;
2231 int subreg_offset1 = 0;
2232 enum delay_type delay = DELAY_NONE;
2234 while (code0 == SUBREG)
2236 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2237 GET_MODE (SUBREG_REG (op0)),
2240 op0 = SUBREG_REG (op0);
2241 code0 = GET_CODE (op0);
2244 if (code1 == SIGN_EXTEND)
2246 op1 = XEXP (op1, 0);
2247 code1 = GET_CODE (op1);
2250 while (code1 == SUBREG)
2252 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2253 GET_MODE (SUBREG_REG (op1)),
2256 op1 = SUBREG_REG (op1);
2257 code1 = GET_CODE (op1);
2261 if (GET_CODE (operands[1]) == SIGN_EXTEND
2263 && code1 != CONST_INT
2264 /* The following three can happen as the result of a questionable
2266 && code1 != LABEL_REF
2267 && code1 != SYMBOL_REF
2273 int regno0 = REGNO (op0) + subreg_offset0;
2277 int regno1 = REGNO (op1) + subreg_offset1;
2279 /* Just in case, don't do anything for assigning a register
2280 to itself, unless we are filling a delay slot. */
2281 if (regno0 == regno1 && set_nomacro == 0)
2284 else if (FP_REG_P (regno0))
2286 if (FP_REG_P (regno1))
2287 ret = "mov.d\t%0,%1";
2295 abort_with_insn (insn, "Bad move");
2297 #ifdef TARGET_FP_CALL_32
2298 if (FP_CALL_GP_REG_P (regno1))
2299 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2302 ret = "dmtc1\t%1,%0";
2305 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2309 else if (FP_REG_P (regno1))
2315 abort_with_insn (insn, "Bad move");
2317 #ifdef TARGET_FP_CALL_32
2318 if (FP_CALL_GP_REG_P (regno0))
2319 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2322 ret = "dmfc1\t%0,%1";
2325 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2328 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2333 if (regno0 != HILO_REGNUM)
2335 else if (regno1 == 0)
2336 ret = "mtlo\t%.\n\tmthi\t%.";
2339 ret = "mthi\t%M1\n\tmtlo\t%L1";
2342 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2347 if (regno1 != HILO_REGNUM)
2351 ret = "mfhi\t%M0\n\tmflo\t%L0";
2354 else if (TARGET_64BIT)
2355 ret = "move\t%0,%1";
2357 else if (regno0 != (regno1+1))
2358 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2361 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2364 else if (code1 == CONST_DOUBLE)
2366 /* Move zero from $0 unless !TARGET_64BIT and recipient
2367 is 64-bit fp reg, in which case generate a constant. */
2368 if (op1 != CONST0_RTX (GET_MODE (op1))
2369 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2371 if (GET_MODE (op1) == DFmode)
2375 #ifdef TARGET_FP_CALL_32
2376 if (FP_CALL_GP_REG_P (regno0))
2378 if (TARGET_FLOAT64 && !TARGET_64BIT)
2380 split_double (op1, operands + 2, operands + 3);
2381 ret = "li\t%0,%2\n\tli\t%D0,%3";
2384 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2388 /* GNU as emits 64-bit code for li.d if the ISA is 3
2389 or higher. For !TARGET_64BIT && gp registers we
2390 need to avoid this by using two li instructions
2392 if (ISA_HAS_64BIT_REGS
2394 && ! FP_REG_P (regno0))
2396 split_double (op1, operands + 2, operands + 3);
2397 ret = "li\t%0,%2\n\tli\t%D0,%3";
2400 ret = "li.d\t%0,%1";
2403 else if (TARGET_64BIT)
2405 if (! TARGET_MIPS16)
2411 split_double (op1, operands + 2, operands + 3);
2412 ret = "li\t%0,%2\n\tli\t%D0,%3";
2418 if (GP_REG_P (regno0))
2420 #ifdef TARGET_FP_CALL_32
2421 && ! FP_CALL_GP_REG_P (regno0)
2424 : "move\t%0,%.\n\tmove\t%D0,%.");
2426 else if (FP_REG_P (regno0))
2431 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2436 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2438 if (GP_REG_P (regno0))
2441 : "move\t%0,%.\n\tmove\t%D0,%.");
2443 else if (FP_REG_P (regno0))
2450 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2452 else if (MD_REG_P (regno0))
2455 ret = (regno0 == HILO_REGNUM
2456 ? "mtlo\t%.\n\tmthi\t%."
2461 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2462 && GP_REG_P (regno0))
2468 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2470 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2471 ret = "li\t%0,%n1\n\tneg\t%0";
2473 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2474 ret = "li\t%0,%1\t\t# %X1";
2475 else if (HOST_BITS_PER_WIDE_INT < 64)
2476 /* We can't use 'X' for negative numbers, because then we won't
2477 get the right value for the upper 32 bits. */
2478 ret = (INTVAL (op1) < 0
2479 ? "dli\t%0,%1\t\t\t# %X1"
2480 : "dli\t%0,%X1\t\t# %1");
2482 /* We must use 'X', because otherwise LONG_MIN will print as
2483 a number that the assembler won't accept. */
2484 ret = "dli\t%0,%X1\t\t# %1";
2486 else if (HOST_BITS_PER_WIDE_INT < 64)
2488 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2491 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2492 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2493 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2495 operands[2] = GEN_INT (1);
2496 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2500 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2504 /* We use multiple shifts here, to avoid warnings about out
2505 of range shifts on 32 bit hosts. */
2506 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2508 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2509 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2513 else if (code1 == MEM)
2518 mips_count_memory_refs (op1, 2);
2520 if (FP_REG_P (regno0))
2523 else if (TARGET_64BIT)
2526 #ifdef TARGET_FP_CALL_32
2527 if (FP_CALL_GP_REG_P (regno0))
2528 ret = (double_memory_operand (op1, GET_MODE (op1))
2529 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2530 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2536 else if (double_memory_operand (op1, GET_MODE (op1)))
2538 operands[2] = adj_offsettable_operand (op1, 4);
2539 ret = (reg_mentioned_p (op0, op1)
2540 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2541 : "lw\t%0,%1\n\tlw\t%D0,%2");
2544 if (ret != 0 && MEM_VOLATILE_P (op1))
2546 size_t i = strlen (ret);
2548 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2551 sprintf (volatile_buffer, "%%{%s%%}", ret);
2552 ret = volatile_buffer;
2556 else if (code1 == LABEL_REF)
2559 mips_count_memory_refs (op1, 2);
2561 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2562 /* We deliberately remove the 'a' from '%1', so that we don't
2563 have to add SIGN_EXTEND support to print_operand_address.
2564 print_operand will just call print_operand_address in this
2565 case, so there is no problem. */
2568 ret = "dla\t%0,%a1";
2570 else if (code1 == SYMBOL_REF || code1 == CONST)
2574 && GET_CODE (XEXP (op1, 0)) == REG
2575 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2577 /* This case arises on the mips16; see
2578 mips16_gp_pseudo_reg. */
2579 ret = "move\t%0,%+";
2581 else if (TARGET_MIPS16
2582 && code1 == SYMBOL_REF
2583 && SYMBOL_REF_FLAG (op1)
2584 && (XSTR (op1, 0)[0] != '*'
2585 || strncmp (XSTR (op1, 0) + 1,
2587 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2589 /* This can occur when reloading the address of a GP
2590 relative symbol on the mips16. */
2591 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2596 mips_count_memory_refs (op1, 2);
2598 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2599 /* We deliberately remove the 'a' from '%1', so that we don't
2600 have to add SIGN_EXTEND support to print_operand_address.
2601 print_operand will just call print_operand_address in this
2602 case, so there is no problem. */
2605 ret = "dla\t%0,%a1";
2610 else if (code0 == MEM)
2614 int regno1 = REGNO (op1) + subreg_offset1;
2616 if (FP_REG_P (regno1))
2619 else if (TARGET_64BIT)
2622 #ifdef TARGET_FP_CALL_32
2623 if (FP_CALL_GP_REG_P (regno1))
2624 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2630 else if (double_memory_operand (op0, GET_MODE (op0)))
2632 operands[2] = adj_offsettable_operand (op0, 4);
2633 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2637 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2638 || (code1 == CONST_DOUBLE
2639 && op1 == CONST0_RTX (GET_MODE (op1))))
2641 || double_memory_operand (op0, GET_MODE (op0))))
2647 operands[2] = adj_offsettable_operand (op0, 4);
2648 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2653 mips_count_memory_refs (op0, 2);
2655 if (ret != 0 && MEM_VOLATILE_P (op0))
2657 size_t i = strlen (ret);
2659 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2662 sprintf (volatile_buffer, "%%{%s%%}", ret);
2663 ret = volatile_buffer;
2669 abort_with_insn (insn, "Bad move");
2673 if (delay != DELAY_NONE)
2674 return mips_fill_delay_slot (ret, delay, operands, insn);
2679 /* Provide the costs of an addressing mode that contains ADDR.
2680 If ADDR is not a valid address, its cost is irrelevant. */
2683 mips_address_cost (addr)
2686 switch (GET_CODE (addr))
2696 rtx offset = const0_rtx;
2697 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2698 if (GET_CODE (addr) == LABEL_REF)
2701 if (GET_CODE (addr) != SYMBOL_REF)
2704 if (! SMALL_INT (offset))
2708 /* ... fall through ... */
2711 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2715 register rtx plus0 = XEXP (addr, 0);
2716 register rtx plus1 = XEXP (addr, 1);
2718 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2719 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2721 if (GET_CODE (plus0) != REG)
2724 switch (GET_CODE (plus1))
2727 return SMALL_INT (plus1) ? 1 : 2;
2734 return mips_address_cost (plus1) + 1;
2748 /* Return nonzero if X is an address which needs a temporary register when
2749 reloaded while generating PIC code. */
2752 pic_address_needs_scratch (x)
2755 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2756 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2757 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2758 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2759 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2765 /* Make normal rtx_code into something we can index from an array */
2767 static enum internal_test
2768 map_test_to_internal_test (test_code)
2769 enum rtx_code test_code;
2771 enum internal_test test = ITEST_MAX;
2775 case EQ: test = ITEST_EQ; break;
2776 case NE: test = ITEST_NE; break;
2777 case GT: test = ITEST_GT; break;
2778 case GE: test = ITEST_GE; break;
2779 case LT: test = ITEST_LT; break;
2780 case LE: test = ITEST_LE; break;
2781 case GTU: test = ITEST_GTU; break;
2782 case GEU: test = ITEST_GEU; break;
2783 case LTU: test = ITEST_LTU; break;
2784 case LEU: test = ITEST_LEU; break;
2792 /* Generate the code to compare two integer values. The return value is:
2793 (reg:SI xx) The pseudo register the comparison is in
2794 0 No register, generate a simple branch.
2796 ??? This is called with result nonzero by the Scond patterns in
2797 mips.md. These patterns are called with a target in the mode of
2798 the Scond instruction pattern. Since this must be a constant, we
2799 must use SImode. This means that if RESULT is non-zero, it will
2800 always be an SImode register, even if TARGET_64BIT is true. We
2801 cope with this by calling convert_move rather than emit_move_insn.
2802 This will sometimes lead to an unnecessary extension of the result;
2814 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2815 enum rtx_code test_code; /* relational test (EQ, etc) */
2816 rtx result; /* result to store comp. or 0 if branch */
2817 rtx cmp0; /* first operand to compare */
2818 rtx cmp1; /* second operand to compare */
2819 int *p_invert; /* NULL or ptr to hold whether branch needs */
2820 /* to reverse its test */
2824 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2825 int const_low; /* low bound of constant we can accept */
2826 int const_high; /* high bound of constant we can accept */
2827 int const_add; /* constant to add (convert LE -> LT) */
2828 int reverse_regs; /* reverse registers in test */
2829 int invert_const; /* != 0 if invert value if cmp1 is constant */
2830 int invert_reg; /* != 0 if invert value if cmp1 is register */
2831 int unsignedp; /* != 0 for unsigned comparisons. */
2834 static struct cmp_info info[ (int)ITEST_MAX ] = {
2836 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2837 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2838 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2839 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2840 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2841 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2842 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2843 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2844 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2845 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2848 enum internal_test test;
2849 enum machine_mode mode;
2850 struct cmp_info *p_info;
2857 test = map_test_to_internal_test (test_code);
2858 if (test == ITEST_MAX)
2861 p_info = &info[(int) test];
2862 eqne_p = (p_info->test_code == XOR);
2864 mode = GET_MODE (cmp0);
2865 if (mode == VOIDmode)
2866 mode = GET_MODE (cmp1);
2868 /* Eliminate simple branches */
2869 branch_p = (result == 0);
2872 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2874 /* Comparisons against zero are simple branches */
2875 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2876 && (! TARGET_MIPS16 || eqne_p))
2879 /* Test for beq/bne. */
2880 if (eqne_p && ! TARGET_MIPS16)
2884 /* allocate a pseudo to calculate the value in. */
2885 result = gen_reg_rtx (mode);
2888 /* Make sure we can handle any constants given to us. */
2889 if (GET_CODE (cmp0) == CONST_INT)
2890 cmp0 = force_reg (mode, cmp0);
2892 if (GET_CODE (cmp1) == CONST_INT)
2894 HOST_WIDE_INT value = INTVAL (cmp1);
2896 if (value < p_info->const_low
2897 || value > p_info->const_high
2898 /* ??? Why? And why wasn't the similar code below modified too? */
2900 && HOST_BITS_PER_WIDE_INT < 64
2901 && p_info->const_add != 0
2902 && ((p_info->unsignedp
2903 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2904 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2905 : (value + p_info->const_add) > INTVAL (cmp1))
2906 != (p_info->const_add > 0))))
2907 cmp1 = force_reg (mode, cmp1);
2910 /* See if we need to invert the result. */
2911 invert = (GET_CODE (cmp1) == CONST_INT
2912 ? p_info->invert_const : p_info->invert_reg);
2914 if (p_invert != (int *)0)
2920 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2921 Comparison between two registers, may involve switching operands. */
2922 if (GET_CODE (cmp1) == CONST_INT)
2924 if (p_info->const_add != 0)
2926 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2928 /* If modification of cmp1 caused overflow,
2929 we would get the wrong answer if we follow the usual path;
2930 thus, x > 0xffffffffU would turn into x > 0U. */
2931 if ((p_info->unsignedp
2932 ? (unsigned HOST_WIDE_INT) new >
2933 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2934 : new > INTVAL (cmp1))
2935 != (p_info->const_add > 0))
2937 /* This test is always true, but if INVERT is true then
2938 the result of the test needs to be inverted so 0 should
2939 be returned instead. */
2940 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2944 cmp1 = GEN_INT (new);
2948 else if (p_info->reverse_regs)
2955 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2959 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2960 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2963 if (test == ITEST_NE)
2965 if (! TARGET_MIPS16)
2967 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2972 reg2 = invert ? gen_reg_rtx (mode) : result;
2973 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2978 else if (test == ITEST_EQ)
2980 reg2 = invert ? gen_reg_rtx (mode) : result;
2981 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2989 if (! TARGET_MIPS16)
2993 /* The value is in $24. Copy it to another register, so
2994 that reload doesn't think it needs to store the $24 and
2995 the input to the XOR in the same location. */
2996 reg2 = gen_reg_rtx (mode);
2997 emit_move_insn (reg2, reg);
2999 one = force_reg (mode, const1_rtx);
3001 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3007 /* Emit the common code for doing conditional branches.
3008 operand[0] is the label to jump to.
3009 The comparison operands are saved away by cmp{si,di,sf,df}. */
3012 gen_conditional_branch (operands, test_code)
3014 enum rtx_code test_code;
3016 enum cmp_type type = branch_type;
3017 rtx cmp0 = branch_cmp[0];
3018 rtx cmp1 = branch_cmp[1];
3019 enum machine_mode mode;
3028 mode = type == CMP_SI ? SImode : DImode;
3030 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3038 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3039 /* We don't want to build a comparison against a non-zero
3041 cmp1 = force_reg (mode, cmp1);
3048 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3050 reg = gen_reg_rtx (CCmode);
3052 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3053 0 in the instruction built below. The MIPS FPU handles
3054 inequality testing by testing for equality and looking for a
3056 emit_insn (gen_rtx_SET (VOIDmode, reg,
3057 gen_rtx (test_code == NE ? EQ : test_code,
3058 CCmode, cmp0, cmp1)));
3060 test_code = test_code == NE ? EQ : NE;
3068 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3071 /* Generate the branch. */
3073 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3082 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3083 gen_rtx_IF_THEN_ELSE (VOIDmode,
3084 gen_rtx (test_code, mode,
3089 /* Emit the common code for conditional moves. OPERANDS is the array
3090 of operands passed to the conditional move defined_expand. */
3093 gen_conditional_move (operands)
3096 rtx op0 = branch_cmp[0];
3097 rtx op1 = branch_cmp[1];
3098 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3099 enum rtx_code cmp_code = GET_CODE (operands[1]);
3100 enum rtx_code move_code = NE;
3101 enum machine_mode op_mode = GET_MODE (operands[0]);
3102 enum machine_mode cmp_mode;
3105 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3124 op0 = force_reg (mode, branch_cmp[1]);
3125 op1 = branch_cmp[0];
3129 op0 = force_reg (mode, branch_cmp[1]);
3130 op1 = branch_cmp[0];
3141 op0 = force_reg (mode, branch_cmp[1]);
3142 op1 = branch_cmp[0];
3146 op0 = force_reg (mode, branch_cmp[1]);
3147 op1 = branch_cmp[0];
3154 else if (cmp_code == NE)
3155 cmp_code = EQ, move_code = EQ;
3157 if (mode == SImode || mode == DImode)
3159 else if (mode == SFmode || mode == DFmode)
3164 cmp_reg = gen_reg_rtx (cmp_mode);
3165 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3166 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3168 emit_insn (gen_rtx_SET (op_mode, operands[0],
3169 gen_rtx_IF_THEN_ELSE (op_mode,
3170 gen_rtx (move_code, VOIDmode,
3172 CONST0_RTX (SImode)),
3173 operands[2], operands[3])));
3176 /* Emit the common code for conditional moves. OPERANDS is the array
3177 of operands passed to the conditional move defined_expand. */
3180 mips_gen_conditional_trap (operands)
3184 enum rtx_code cmp_code = GET_CODE (operands[0]);
3185 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3187 /* MIPS conditional trap machine instructions don't have GT or LE
3188 flavors, so we must invert the comparison and convert to LT and
3189 GE, respectively. */
3192 case GT: cmp_code = LT; break;
3193 case LE: cmp_code = GE; break;
3194 case GTU: cmp_code = LTU; break;
3195 case LEU: cmp_code = GEU; break;
3198 if (cmp_code == GET_CODE (operands[0]))
3200 op0 = force_reg (mode, branch_cmp[0]);
3201 op1 = branch_cmp[1];
3205 op0 = force_reg (mode, branch_cmp[1]);
3206 op1 = branch_cmp[0];
3208 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3209 op1 = force_reg (mode, op1);
3211 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3212 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3216 /* Write a loop to move a constant number of bytes.
3217 Generate load/stores as follows:
3223 temp<last> = src[MAX_MOVE_REGS-1];
3227 dest[MAX_MOVE_REGS-1] = temp<last>;
3228 src += MAX_MOVE_REGS;
3229 dest += MAX_MOVE_REGS;
3230 } while (src != final);
3232 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3233 registers are needed.
3235 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3236 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3237 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3239 #define MAX_MOVE_REGS 4
3240 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3243 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3244 rtx dest_reg; /* register holding destination address */
3245 rtx src_reg; /* register holding source address */
3246 unsigned int bytes; /* # bytes to move */
3247 int align; /* alignment */
3248 rtx orig_dest; /* original dest for change_address */
3249 rtx orig_src; /* original source for making a reg note */
3251 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
3252 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
3253 rtx align_rtx = GEN_INT (align);
3259 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3262 leftover = bytes % MAX_MOVE_BYTES;
3265 label = gen_label_rtx ();
3266 final_src = gen_reg_rtx (Pmode);
3267 bytes_rtx = GEN_INT (bytes);
3271 if (Pmode == DImode)
3273 emit_insn (gen_movdi (final_src, bytes_rtx));
3274 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3278 emit_insn (gen_movsi (final_src, bytes_rtx));
3279 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3284 if (Pmode == DImode)
3285 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3287 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3292 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3293 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3295 if (Pmode == DImode)
3297 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3298 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3299 emit_insn (gen_cmpdi (src_reg, final_src));
3303 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3304 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3305 emit_insn (gen_cmpsi (src_reg, final_src));
3308 emit_jump_insn (gen_bne (label));
3311 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3315 /* Use a library function to move some bytes. */
3318 block_move_call (dest_reg, src_reg, bytes_rtx)
3323 /* We want to pass the size as Pmode, which will normally be SImode
3324 but will be DImode if we are using 64 bit longs and pointers. */
3325 if (GET_MODE (bytes_rtx) != VOIDmode
3326 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3327 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3329 #ifdef TARGET_MEM_FUNCTIONS
3330 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3331 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3332 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3333 TREE_UNSIGNED (sizetype)),
3334 TYPE_MODE (sizetype));
3336 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3337 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3338 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3339 TREE_UNSIGNED (integer_type_node)),
3340 TYPE_MODE (integer_type_node));
3344 /* Expand string/block move operations.
3346 operands[0] is the pointer to the destination.
3347 operands[1] is the pointer to the source.
3348 operands[2] is the number of bytes to move.
3349 operands[3] is the alignment. */
3352 expand_block_move (operands)
3355 rtx bytes_rtx = operands[2];
3356 rtx align_rtx = operands[3];
3357 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3358 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3359 unsigned int align = INTVAL (align_rtx);
3360 rtx orig_src = operands[1];
3361 rtx orig_dest = operands[0];
3365 if (constp && bytes == 0)
3368 if (align > (unsigned) UNITS_PER_WORD)
3369 align = UNITS_PER_WORD;
3371 /* Move the address into scratch registers. */
3372 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3373 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3376 block_move_call (dest_reg, src_reg, bytes_rtx);
3378 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3379 && align == (unsigned) UNITS_PER_WORD)
3380 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3382 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3383 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3385 change_address (orig_src, BLKmode,
3387 bytes_rtx, align_rtx));
3389 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3390 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3392 else if (constp && optimize)
3394 /* If the alignment is not word aligned, generate a test at
3395 runtime, to see whether things wound up aligned, and we
3396 can use the faster lw/sw instead ulw/usw. */
3398 rtx temp = gen_reg_rtx (Pmode);
3399 rtx aligned_label = gen_label_rtx ();
3400 rtx join_label = gen_label_rtx ();
3401 int leftover = bytes % MAX_MOVE_BYTES;
3405 if (Pmode == DImode)
3407 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3408 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3409 emit_insn (gen_cmpdi (temp, const0_rtx));
3413 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3414 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3415 emit_insn (gen_cmpsi (temp, const0_rtx));
3418 emit_jump_insn (gen_beq (aligned_label));
3420 /* Unaligned loop. */
3421 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3422 emit_jump_insn (gen_jump (join_label));
3426 emit_label (aligned_label);
3427 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3429 emit_label (join_label);
3431 /* Bytes at the end of the loop. */
3433 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3435 change_address (orig_src, BLKmode,
3442 block_move_call (dest_reg, src_reg, bytes_rtx);
3445 /* Emit load/stores for a small constant block_move.
3447 operands[0] is the memory address of the destination.
3448 operands[1] is the memory address of the source.
3449 operands[2] is the number of bytes to move.
3450 operands[3] is the alignment.
3451 operands[4] is a temp register.
3452 operands[5] is a temp register.
3454 operands[3+num_regs] is the last temp register.
3456 The block move type can be one of the following:
3457 BLOCK_MOVE_NORMAL Do all of the block move.
3458 BLOCK_MOVE_NOT_LAST Do all but the last store.
3459 BLOCK_MOVE_LAST Do just the last store. */
3462 output_block_move (insn, operands, num_regs, move_type)
3466 enum block_move_type move_type;
3468 rtx dest_reg = XEXP (operands[0], 0);
3469 rtx src_reg = XEXP (operands[1], 0);
3470 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3471 int align = INTVAL (operands[3]);
3474 int use_lwl_lwr = 0;
3475 int last_operand = num_regs + 4;
3481 const char *load; /* load insn without nop */
3482 const char *load_nop; /* load insn with trailing nop */
3483 const char *store; /* store insn */
3484 const char *final; /* if last_store used: NULL or swr */
3485 const char *last_store; /* last store instruction */
3486 int offset; /* current offset */
3487 enum machine_mode mode; /* mode to use on (MEM) */
3490 /* ??? Detect a bug in GCC, where it can give us a register
3491 the same as one of the addressing registers and reduce
3492 the number of registers available. */
3493 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3494 if (! reg_mentioned_p (operands[i], operands[0])
3495 && ! reg_mentioned_p (operands[i], operands[1]))
3496 xoperands[safe_regs++] = operands[i];
3498 if (safe_regs < last_operand)
3500 xoperands[0] = operands[0];
3501 xoperands[1] = operands[1];
3502 xoperands[2] = operands[2];
3503 xoperands[3] = operands[3];
3504 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3507 /* If we are given global or static addresses, and we would be
3508 emitting a few instructions, try to save time by using a
3509 temporary register for the pointer. */
3510 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3511 an ldl/ldr instruction pair. We play it safe, and always move
3512 constant addresses into registers when generating N32/N64 code, just
3513 in case we might emit an unaligned load instruction. */
3514 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3515 || mips_abi == ABI_N32 || mips_abi == ABI_64))
3517 if (CONSTANT_P (src_reg))
3520 mips_count_memory_refs (operands[1], 1);
3522 src_reg = operands[3 + num_regs--];
3523 if (move_type != BLOCK_MOVE_LAST)
3525 xoperands[1] = operands[1];
3526 xoperands[0] = src_reg;
3527 if (Pmode == DImode)
3528 output_asm_insn ("dla\t%0,%1", xoperands);
3530 output_asm_insn ("la\t%0,%1", xoperands);
3534 if (CONSTANT_P (dest_reg))
3537 mips_count_memory_refs (operands[0], 1);
3539 dest_reg = operands[3 + num_regs--];
3540 if (move_type != BLOCK_MOVE_LAST)
3542 xoperands[1] = operands[0];
3543 xoperands[0] = dest_reg;
3544 if (Pmode == DImode)
3545 output_asm_insn ("dla\t%0,%1", xoperands);
3547 output_asm_insn ("la\t%0,%1", xoperands);
3552 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3553 are not offsettable, however, offsettable_address_p says they are
3554 offsettable. I think this is a bug in offsettable_address_p.
3555 For expediency, we fix this by just loading the address into a register
3556 if we happen to get one. */
3558 if (GET_CODE (src_reg) == LO_SUM)
3560 src_reg = operands[3 + num_regs--];
3561 if (move_type != BLOCK_MOVE_LAST)
3563 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3564 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3565 xoperands[0] = src_reg;
3566 if (Pmode == DImode)
3567 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3569 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3573 if (GET_CODE (dest_reg) == LO_SUM)
3575 dest_reg = operands[3 + num_regs--];
3576 if (move_type != BLOCK_MOVE_LAST)
3578 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3579 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3580 xoperands[0] = dest_reg;
3581 if (Pmode == DImode)
3582 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3584 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3588 if (num_regs > (int) ARRAY_SIZE (load_store))
3589 num_regs = ARRAY_SIZE (load_store);
3591 else if (num_regs < 1)
3592 abort_with_insn (insn,
3593 "Cannot do block move, not enough scratch registers");
3597 load_store[num].offset = offset;
3599 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3601 load_store[num].load = "ld\t%0,%1";
3602 load_store[num].load_nop = "ld\t%0,%1%#";
3603 load_store[num].store = "sd\t%0,%1";
3604 load_store[num].last_store = "sd\t%0,%1";
3605 load_store[num].final = 0;
3606 load_store[num].mode = DImode;
3611 /* ??? Fails because of a MIPS assembler bug? */
3612 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3614 if (BYTES_BIG_ENDIAN)
3616 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3617 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3618 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3619 load_store[num].last_store = "sdr\t%0,%2";
3620 load_store[num].final = "sdl\t%0,%1";
3624 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3625 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3626 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3627 load_store[num].last_store = "sdr\t%0,%1";
3628 load_store[num].final = "sdl\t%0,%2";
3631 load_store[num].mode = DImode;
3637 else if (bytes >= 4 && align >= 4)
3639 load_store[num].load = "lw\t%0,%1";
3640 load_store[num].load_nop = "lw\t%0,%1%#";
3641 load_store[num].store = "sw\t%0,%1";
3642 load_store[num].last_store = "sw\t%0,%1";
3643 load_store[num].final = 0;
3644 load_store[num].mode = SImode;
3649 else if (bytes >= 4 && ! TARGET_MIPS16)
3651 if (BYTES_BIG_ENDIAN)
3653 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3654 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3655 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3656 load_store[num].last_store = "swr\t%0,%2";
3657 load_store[num].final = "swl\t%0,%1";
3661 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3662 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3663 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3664 load_store[num].last_store = "swr\t%0,%1";
3665 load_store[num].final = "swl\t%0,%2";
3668 load_store[num].mode = SImode;
3674 else if (bytes >= 2 && align >= 2)
3676 load_store[num].load = "lh\t%0,%1";
3677 load_store[num].load_nop = "lh\t%0,%1%#";
3678 load_store[num].store = "sh\t%0,%1";
3679 load_store[num].last_store = "sh\t%0,%1";
3680 load_store[num].final = 0;
3681 load_store[num].mode = HImode;
3687 load_store[num].load = "lb\t%0,%1";
3688 load_store[num].load_nop = "lb\t%0,%1%#";
3689 load_store[num].store = "sb\t%0,%1";
3690 load_store[num].last_store = "sb\t%0,%1";
3691 load_store[num].final = 0;
3692 load_store[num].mode = QImode;
3697 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3699 dslots_load_total++;
3700 dslots_load_filled++;
3702 if (CONSTANT_P (src_reg))
3703 mips_count_memory_refs (src_reg, 1);
3705 if (CONSTANT_P (dest_reg))
3706 mips_count_memory_refs (dest_reg, 1);
3709 /* Emit load/stores now if we have run out of registers or are
3710 at the end of the move. */
3712 if (++num == num_regs || bytes == 0)
3714 /* If only load/store, we need a NOP after the load. */
3717 load_store[0].load = load_store[0].load_nop;
3718 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3719 dslots_load_filled--;
3722 if (move_type != BLOCK_MOVE_LAST)
3724 for (i = 0; i < num; i++)
3728 if (!operands[i + 4])
3731 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3732 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3733 REGNO (operands[i + 4]));
3735 offset = load_store[i].offset;
3736 xoperands[0] = operands[i + 4];
3737 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3738 plus_constant (src_reg, offset));
3743 = GET_MODE_SIZE (load_store[i].mode) - 1;
3745 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3746 plus_constant (src_reg,
3751 output_asm_insn (load_store[i].load, xoperands);
3755 for (i = 0; i < num; i++)
3757 int last_p = (i == num-1 && bytes == 0);
3758 int offset = load_store[i].offset;
3760 xoperands[0] = operands[i + 4];
3761 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3762 plus_constant (dest_reg, offset));
3767 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3768 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3769 plus_constant (dest_reg,
3774 if (move_type == BLOCK_MOVE_NORMAL)
3775 output_asm_insn (load_store[i].store, xoperands);
3777 else if (move_type == BLOCK_MOVE_NOT_LAST)
3780 output_asm_insn (load_store[i].store, xoperands);
3782 else if (load_store[i].final != 0)
3783 output_asm_insn (load_store[i].final, xoperands);
3787 output_asm_insn (load_store[i].last_store, xoperands);
3790 num = 0; /* reset load_store */
3798 /* Argument support functions. */
3800 /* Initialize CUMULATIVE_ARGS for a function. */
3803 init_cumulative_args (cum, fntype, libname)
3804 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3805 tree fntype; /* tree ptr for function decl */
3806 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3808 static CUMULATIVE_ARGS zero_cum;
3809 tree param, next_param;
3811 if (TARGET_DEBUG_E_MODE)
3814 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3817 fputc ('\n', stderr);
3821 tree ret_type = TREE_TYPE (fntype);
3822 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3823 tree_code_name[(int)TREE_CODE (fntype)],
3824 tree_code_name[(int)TREE_CODE (ret_type)]);
3830 /* Determine if this function has variable arguments. This is
3831 indicated by the last argument being 'void_type_mode' if there
3832 are no variable arguments. The standard MIPS calling sequence
3833 passes all arguments in the general purpose registers in this case. */
3835 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3836 param != 0; param = next_param)
3838 next_param = TREE_CHAIN (param);
3839 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3840 cum->gp_reg_found = 1;
3844 /* Advance the argument to the next argument position. */
3847 function_arg_advance (cum, mode, type, named)
3848 CUMULATIVE_ARGS *cum; /* current arg information */
3849 enum machine_mode mode; /* current arg mode */
3850 tree type; /* type of the argument or 0 if lib support */
3851 int named; /* whether or not the argument was named */
3853 if (TARGET_DEBUG_E_MODE)
3856 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3857 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3858 GET_MODE_NAME (mode));
3859 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3860 fprintf (stderr, ", %d )\n\n", named);
3870 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3871 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3874 cum->gp_reg_found = 1;
3875 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3880 cum->gp_reg_found = 1;
3881 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3886 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3887 cum->fp_arg_words++;
3890 if (! cum->gp_reg_found && cum->arg_number <= 2)
3891 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3895 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3896 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3898 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3899 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3900 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3904 cum->gp_reg_found = 1;
3905 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3911 cum->gp_reg_found = 1;
3917 /* Return an RTL expression containing the register for the given mode,
3918 or 0 if the argument is to be passed on the stack. */
3921 function_arg (cum, mode, type, named)
3922 CUMULATIVE_ARGS *cum; /* current arg information */
3923 enum machine_mode mode; /* current arg mode */
3924 tree type; /* type of the argument or 0 if lib support */
3925 int named; /* != 0 for normal args, == 0 for ... args */
3930 unsigned int *arg_words = &cum->arg_words;
3931 int struct_p = (type != 0
3932 && (TREE_CODE (type) == RECORD_TYPE
3933 || TREE_CODE (type) == UNION_TYPE
3934 || TREE_CODE (type) == QUAL_UNION_TYPE));
3936 if (TARGET_DEBUG_E_MODE)
3939 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3940 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3941 GET_MODE_NAME (mode));
3942 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3943 fprintf (stderr, ", %d ) = ", named);
3947 cum->last_arg_fp = 0;
3951 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3953 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3954 regbase = GP_ARG_FIRST;
3957 regbase = FP_ARG_FIRST;
3959 /* If the first arg was a float in a floating point register,
3960 then set bias to align this float arg properly. */
3961 if (cum->arg_words == 1)
3965 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3968 cum->fp_arg_words += cum->fp_arg_words & 1;
3969 cum->last_arg_fp = 1;
3970 arg_words = &cum->fp_arg_words;
3971 regbase = FP_ARG_FIRST;
3974 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3980 if (mips_abi == ABI_EABI
3981 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3982 cum->fp_arg_words += cum->fp_arg_words & 1;
3984 cum->arg_words += cum->arg_words & 1;
3987 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3988 regbase = ((cum->gp_reg_found
3989 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
3990 || cum->arg_number >= 2)
3991 ? GP_ARG_FIRST : FP_ARG_FIRST);
3992 else if (mips_abi == ABI_EABI
3993 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3995 cum->last_arg_fp = 1;
3996 arg_words = &cum->fp_arg_words;
3997 regbase = FP_ARG_FIRST;
4000 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
4001 ? GP_ARG_FIRST : FP_ARG_FIRST);
4005 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4006 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4009 /* Drops through. */
4011 if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
4012 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4013 cum->arg_words += (cum->arg_words & 1);
4014 regbase = GP_ARG_FIRST;
4021 regbase = GP_ARG_FIRST;
4026 cum->arg_words += (cum->arg_words & 1);
4027 regbase = GP_ARG_FIRST;
4030 if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
4032 if (TARGET_DEBUG_E_MODE)
4033 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
4042 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
4043 || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named
4044 || ! TYPE_SIZE_UNIT (type)
4045 || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
4046 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4049 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4050 structure contains a double in its entirety, then that 64 bit
4051 chunk is passed in a floating point register. */
4054 /* First check to see if there is any such field. */
4055 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4056 if (TREE_CODE (field) == FIELD_DECL
4057 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4058 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4059 && host_integerp (bit_position (field), 0)
4060 && int_bit_position (field) % BITS_PER_WORD == 0)
4063 /* If the whole struct fits a DFmode register,
4064 we don't need the PARALLEL. */
4065 if (! field || mode == DFmode)
4066 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4069 /* Now handle the special case by returning a PARALLEL
4070 indicating where each 64 bit chunk goes. */
4071 unsigned int chunks;
4072 HOST_WIDE_INT bitpos;
4076 /* ??? If this is a packed structure, then the last hunk won't
4080 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
4081 if (chunks + *arg_words + bias > (unsigned) MAX_ARGS_IN_REGISTERS)
4082 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
4084 /* assign_parms checks the mode of ENTRY_PARM, so we must
4085 use the actual mode here. */
4086 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
4089 regno = regbase + *arg_words + bias;
4090 field = TYPE_FIELDS (type);
4091 for (i = 0; i < chunks; i++)
4095 for (; field; field = TREE_CHAIN (field))
4096 if (TREE_CODE (field) == FIELD_DECL
4097 && int_bit_position (field) >= bitpos)
4101 && int_bit_position (field) == bitpos
4102 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4103 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4104 reg = gen_rtx_REG (DFmode,
4105 regno + FP_ARG_FIRST - GP_ARG_FIRST);
4107 reg = gen_rtx_REG (word_mode, regno);
4110 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4111 GEN_INT (bitpos / BITS_PER_UNIT));
4119 if (TARGET_DEBUG_E_MODE)
4120 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
4121 struct_p ? ", [struct]" : "");
4123 /* The following is a hack in order to pass 1 byte structures
4124 the same way that the MIPS compiler does (namely by passing
4125 the structure in the high byte or half word of the register).
4126 This also makes varargs work. If we have such a structure,
4127 we save the adjustment RTL, and the call define expands will
4128 emit them. For the VOIDmode argument (argument after the
4129 last real argument), pass back a parallel vector holding each
4130 of the adjustments. */
4132 /* ??? function_arg can be called more than once for each argument.
4133 As a result, we compute more adjustments than we need here.
4134 See the CUMULATIVE_ARGS definition in mips.h. */
4136 /* ??? This scheme requires everything smaller than the word size to
4137 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4138 that would mean every int needs to be shifted left, which is very
4139 inefficient. Let's not carry this compatibility to the 64 bit
4140 calling convention for now. */
4142 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
4143 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4145 rtx amount = GEN_INT (BITS_PER_WORD
4146 - int_size_in_bytes (type) * BITS_PER_UNIT);
4147 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
4150 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
4152 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
4156 /* We will be called with a mode of VOIDmode after the last argument
4157 has been seen. Whatever we return will be passed to the call
4158 insn. If we need any shifts for small structures, return them in
4159 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4160 mode. Otherwise, if we have need a mips16 fp_code, return a REG
4161 with the code stored as the mode. */
4162 if (mode == VOIDmode)
4164 if (cum->num_adjusts > 0)
4165 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
4166 gen_rtvec_v (cum->num_adjusts, cum->adjust));
4167 else if (TARGET_MIPS16 && cum->fp_code != 0)
4168 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
4175 function_arg_partial_nregs (cum, mode, type, named)
4176 CUMULATIVE_ARGS *cum; /* current arg information */
4177 enum machine_mode mode; /* current arg mode */
4178 tree type; /* type of the argument or 0 if lib support */
4179 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
4181 if ((mode == BLKmode
4182 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4183 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4184 && cum->arg_words < (unsigned) MAX_ARGS_IN_REGISTERS
4185 && mips_abi != ABI_EABI)
4188 if (mode == BLKmode)
4189 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
4192 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4194 if (words + cum->arg_words <= (unsigned) MAX_ARGS_IN_REGISTERS)
4195 return 0; /* structure fits in registers */
4197 if (TARGET_DEBUG_E_MODE)
4198 fprintf (stderr, "function_arg_partial_nregs = %d\n",
4199 MAX_ARGS_IN_REGISTERS - cum->arg_words);
4201 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
4204 else if (mode == DImode
4205 && cum->arg_words == MAX_ARGS_IN_REGISTERS - (unsigned)1
4206 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4208 if (TARGET_DEBUG_E_MODE)
4209 fprintf (stderr, "function_arg_partial_nregs = 1\n");
4217 /* Create the va_list data type.
4218 We keep 3 pointers, and two offsets.
4219 Two pointers are to the overflow area, which starts at the CFA.
4220 One of these is constant, for addressing into the GPR save area below it.
4221 The other is advanced up the stack through the overflow region.
4222 The third pointer is to the GPR save area. Since the FPR save area
4223 is just below it, we can address FPR slots off this pointer.
4224 We also keep two one-byte offsets, which are to be subtracted from the
4225 constant pointers to yield addresses in the GPR and FPR save areas.
4226 These are downcounted as float or non-float arguments are used,
4227 and when they get to zero, the argument must be obtained from the
4229 If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
4230 and a single pointer is enough. It's started at the GPR save area,
4231 and is advanced, period.
4232 Note that the GPR save area is not constant size, due to optimization
4233 in the prologue. Hence, we can't use a design with two pointers
4234 and two offsets, although we could have designed this with two pointers
4235 and three offsets. */
4239 mips_build_va_list ()
4241 if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4243 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4245 record = make_node (RECORD_TYPE);
4247 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4249 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4251 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4253 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4254 unsigned_char_type_node);
4255 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4256 unsigned_char_type_node);
4259 DECL_FIELD_CONTEXT (f_ovfl) = record;
4260 DECL_FIELD_CONTEXT (f_gtop) = record;
4261 DECL_FIELD_CONTEXT (f_ftop) = record;
4262 DECL_FIELD_CONTEXT (f_goff) = record;
4263 DECL_FIELD_CONTEXT (f_foff) = record;
4265 TYPE_FIELDS (record) = f_ovfl;
4266 TREE_CHAIN (f_ovfl) = f_gtop;
4267 TREE_CHAIN (f_gtop) = f_ftop;
4268 TREE_CHAIN (f_ftop) = f_goff;
4269 TREE_CHAIN (f_goff) = f_foff;
4271 layout_type (record);
4275 return ptr_type_node;
4278 /* Implement va_start. stdarg_p is 0 if implementing
4279 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4280 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4281 (It doesn't have "...", so it inherits the pointers of its caller.) */
4284 mips_va_start (stdarg_p, valist, nextarg)
4292 /* Find out how many non-float named formals */
4293 int_arg_words = current_function_args_info.arg_words;
4295 if (mips_abi == ABI_EABI)
4297 int gpr_save_area_size;
4298 /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
4299 if (int_arg_words < 8 )
4300 /* Adjust for the prologue's economy measure */
4301 gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
4303 gpr_save_area_size = 0;
4305 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4307 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4308 tree ovfl, gtop, ftop, goff, foff;
4310 int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
4311 int fpr_save_offset;
4313 float_formals = current_function_args_info.fp_arg_words;
4314 /* If mips2, the number of formals is half the reported # of words */
4317 floats_passed_in_regs = (TARGET_64BIT ? 8 : 4);
4319 f_ovfl = TYPE_FIELDS (va_list_type_node);
4320 f_gtop = TREE_CHAIN (f_ovfl);
4321 f_ftop = TREE_CHAIN (f_gtop);
4322 f_goff = TREE_CHAIN (f_ftop);
4323 f_foff = TREE_CHAIN (f_goff);
4325 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4326 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4327 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4328 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4329 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4331 /* Emit code setting a pointer into the overflow (shared-stack) area.
4332 If there were more than 8 non-float formals, or more than 8
4333 float formals, then this pointer isn't to the base of the area.
4334 In that case, it must point to where the first vararg is. */
4336 if (float_formals > floats_passed_in_regs)
4337 size_excess += (float_formals-floats_passed_in_regs) * 8;
4338 if (int_arg_words > 8)
4339 size_excess += (int_arg_words-8) * UNITS_PER_WORD;
4341 /* FIXME: for mips2, the above size_excess can be wrong. Because the
4342 overflow stack holds mixed size items, there can be alignments,
4343 so that an 8 byte double following a 4 byte int will be on an
4344 8 byte boundary. This means that the above calculation should
4345 take into account the exact sequence of floats and non-floats
4346 which make up the excess. That calculation should be rolled
4347 into the code which sets the current_function_args_info struct.
4348 The above then reduces to a fetch from that struct. */
4351 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4353 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4354 build_int_2 (size_excess, 0));
4355 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4356 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4358 /* Emit code setting a ptr to the base of the overflow area. */
4359 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4360 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4361 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4363 /* Emit code setting a pointer to the GPR save area.
4364 More precisely, a pointer to off-the-end of the FPR save area.
4365 If mips4, this is gpr_save_area_size below the overflow area.
4366 If mips2, also round down to an 8-byte boundary, since the FPR
4367 save area is 8-byte aligned, and GPR is 4-byte-aligned.
4368 Therefore there can be a 4-byte gap between the save areas. */
4369 gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4370 fpr_save_offset = gpr_save_area_size;
4373 if (fpr_save_offset & 7)
4374 fpr_save_offset += 4;
4376 if (fpr_save_offset)
4377 gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
4378 build_int_2 (-fpr_save_offset,-1));
4379 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
4380 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4382 /* Emit code initting an offset to the size of the GPR save area */
4383 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4384 build_int_2 (gpr_save_area_size,0));
4385 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4387 /* Emit code initting an offset from ftop to the first float
4388 vararg. This varies in size, since any float
4389 varargs are put in the FPR save area after the formals.
4390 Note it's 8 bytes/formal regardless of TARGET_64BIT.
4391 However, mips2 stores 4 GPRs, mips4 stores 8 GPRs.
4392 If there are 8 or more float formals, init to zero.
4393 (In fact, the formals aren't stored in the bottom of the
4394 FPR save area: they are elsewhere, and the size of the FPR
4395 save area is economized by the prologue. But this code doesn't
4396 care. This design is unaffected by that fact.) */
4397 if (float_formals >= floats_passed_in_regs)
4400 fpr_offset = (floats_passed_in_regs - float_formals) * 8;
4401 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4402 build_int_2 (fpr_offset,0));
4403 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4407 /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
4409 /* Everything is in the GPR save area, or in the overflow
4410 area which is contiguous with it. */
4412 int offset = -gpr_save_area_size;
4413 if (gpr_save_area_size == 0)
4414 offset = (stdarg_p ? 0 : -UNITS_PER_WORD);
4415 nextarg = plus_constant (nextarg, offset);
4416 std_expand_builtin_va_start (1, valist, nextarg);
4428 /* ??? This had been conditional on
4429 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4430 and both iris5.h and iris6.h define _MIPS_SIM. */
4431 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4432 ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
4434 ofs = -UNITS_PER_WORD;
4437 nextarg = plus_constant (nextarg, ofs);
4438 std_expand_builtin_va_start (1, valist, nextarg);
4442 /* Implement va_arg. */
4445 mips_va_arg (valist, type)
4448 HOST_WIDE_INT size, rsize;
4452 size = int_size_in_bytes (type);
4453 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4455 if (mips_abi == ABI_EABI)
4458 rtx r, lab_over = NULL_RTX, lab_false;
4459 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4460 tree ovfl, gtop, ftop, goff, foff;
4463 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4466 size = POINTER_SIZE / BITS_PER_UNIT;
4467 rsize = UNITS_PER_WORD;
4470 addr_rtx = gen_reg_rtx (Pmode);
4472 if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
4474 /* Case of all args in a merged stack. No need to check bounds,
4475 just advance valist along the stack. */
4480 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4482 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4483 build_int_2 (2*UNITS_PER_WORD - 1, 0));
4484 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4485 build_int_2 (-2*UNITS_PER_WORD, -1));
4486 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4487 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4490 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4492 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4494 emit_move_insn (addr_rtx, r);
4496 /* flush the POSTINCREMENT */
4501 r = gen_rtx_MEM (Pmode, addr_rtx);
4502 MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4503 emit_move_insn (addr_rtx, r);
4507 if (BYTES_BIG_ENDIAN && rsize != size)
4508 addr_rtx = plus_constant (addr_rtx, rsize - size);
4513 /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
4515 f_ovfl = TYPE_FIELDS (va_list_type_node);
4516 f_gtop = TREE_CHAIN (f_ovfl);
4517 f_ftop = TREE_CHAIN (f_gtop);
4518 f_goff = TREE_CHAIN (f_ftop);
4519 f_foff = TREE_CHAIN (f_goff);
4521 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4522 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4523 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4524 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4525 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4527 lab_false = gen_label_rtx ();
4528 lab_over = gen_label_rtx ();
4530 if (TREE_CODE (type) == REAL_TYPE)
4533 /* Emit code to branch if foff == 0. */
4534 r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
4536 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4537 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4539 /* Emit code for addr_rtx = ftop - foff */
4540 t = build (MINUS_EXPR, TREE_TYPE (ftop), ftop, foff );
4541 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4543 emit_move_insn (addr_rtx, r);
4545 /* Emit code for foff-=8.
4546 Advances the offset up FPR save area by one double */
4547 t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
4548 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
4549 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4552 emit_jump (lab_over);
4554 emit_label (lab_false);
4558 /* For mips2, the overflow area contains mixed size items.
4559 If a 4-byte int is followed by an 8-byte float, then
4560 natural alignment causes a 4 byte gap.
4561 So, dynamically adjust ovfl up to a multiple of 8. */
4562 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
4563 build_int_2 (7, 0));
4564 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
4565 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4566 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4569 /* Emit code for addr_rtx = the ovfl pointer into overflow area.
4570 Regardless of mips2, postincrement the ovfl pointer by 8. */
4571 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4573 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4575 emit_move_insn (addr_rtx, r);
4578 emit_label (lab_over);
4587 && TREE_CODE (type) == INTEGER_TYPE
4588 && TYPE_PRECISION (type) == 64)
4590 /* In mips2, int takes 32 bits of the GPR save area, but
4591 longlong takes an aligned 64 bits. So, emit code
4592 to zero the low order bits of goff, thus aligning
4593 the later calculation of (gtop-goff) upwards. */
4594 t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
4595 build_int_2 (-8, -1));
4596 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4597 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4600 /* Emit code to branch if goff == 0. */
4601 r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
4603 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4604 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4606 /* Emit code for addr_rtx = gtop - goff. */
4607 t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
4608 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4610 emit_move_insn (addr_rtx, r);
4612 /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
4613 if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
4616 step_size = UNITS_PER_WORD;
4618 /* Emit code for goff = goff - step_size.
4619 Advances the offset up GPR save area over the item. */
4620 t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
4621 build_int_2 (step_size, 0));
4622 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4623 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4626 emit_jump (lab_over);
4628 emit_label (lab_false);
4630 /* Emit code for addr_rtx -> overflow area, postinc by step_size */
4631 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4632 size_int (step_size));
4633 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4635 emit_move_insn (addr_rtx, r);
4638 emit_label (lab_over);
4642 r = gen_rtx_MEM (Pmode, addr_rtx);
4643 MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4644 emit_move_insn (addr_rtx, r);
4648 if (BYTES_BIG_ENDIAN && rsize != size)
4649 addr_rtx = plus_constant (addr_rtx, rsize - size);
4659 /* ??? The original va-mips.h did always align, despite the fact
4660 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4661 increment mechanism. */
4665 else if (TYPE_ALIGN (type) > 32)
4670 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4671 build_int_2 (align - 1, 0));
4672 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4673 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4674 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4676 /* Everything past the alignment is standard. */
4677 return std_expand_builtin_va_arg (valist, type);
4681 /* Abort after printing out a specific insn. */
4684 abort_with_insn (insn, reason)
4693 /* Set up the threshold for data to go into the small data area, instead
4694 of the normal data area, and detect any conflicts in the switches. */
4699 register int i, start;
4701 register enum machine_mode mode;
4703 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4705 if (mips_section_threshold <= 0)
4706 target_flags &= ~MASK_GPOPT;
4708 target_flags |= MASK_GPOPT;
4710 /* If both single-float and soft-float are set, then clear the one that
4711 was set by TARGET_DEFAULT, leaving the one that was set by the
4712 user. We assume here that the specs prevent both being set by the
4714 #ifdef TARGET_DEFAULT
4715 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4716 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
4719 /* Get the architectural level. */
4720 if (mips_isa_string == 0)
4721 mips_isa = MIPS_ISA_DEFAULT;
4723 else if (ISDIGIT (*mips_isa_string))
4725 mips_isa = atoi (mips_isa_string);
4728 /* -mno-mips16 overrides -mips16. */
4729 if (mips_no_mips16_string == NULL)
4731 target_flags |= MASK_MIPS16;
4735 mips_isa = MIPS_ISA_DEFAULT;
4739 mips_isa = MIPS_ISA_DEFAULT;
4742 else if (mips_isa < 1 || mips_isa > 4)
4744 error ("-mips%d not supported", mips_isa);
4751 error ("bad value (%s) for -mips switch", mips_isa_string);
4755 #ifdef MIPS_ABI_DEFAULT
4756 /* Get the ABI to use. */
4757 if (mips_abi_string == (char *) 0)
4758 mips_abi = MIPS_ABI_DEFAULT;
4759 else if (! strcmp (mips_abi_string, "32"))
4761 else if (! strcmp (mips_abi_string, "o64"))
4763 else if (! strcmp (mips_abi_string, "n32"))
4765 else if (! strcmp (mips_abi_string, "64"))
4767 else if (! strcmp (mips_abi_string, "eabi"))
4768 mips_abi = ABI_EABI;
4770 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4772 /* A specified ISA defaults the ABI if it was not specified. */
4773 if (mips_abi_string == 0 && mips_isa_string
4774 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4776 if (! ISA_HAS_64BIT_REGS)
4782 /* A specified ABI defaults the ISA if it was not specified. */
4783 else if (mips_isa_string == 0 && mips_abi_string
4784 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4786 if (mips_abi == ABI_32)
4788 else if (mips_abi == ABI_N32)
4794 /* If both ABI and ISA were specified, check for conflicts. */
4795 else if (mips_isa_string && mips_abi_string)
4797 if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
4798 || mips_abi == ABI_O64))
4799 || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32))
4800 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4803 /* Override TARGET_DEFAULT if necessary. */
4804 if (mips_abi == ABI_32)
4805 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4807 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4808 then set the type sizes. In the EABI in 64 bit mode, longs and
4809 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4810 if (mips_explicit_type_size_string == NULL
4811 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4812 || mips_abi == ABI_64))
4813 target_flags |= MASK_LONG64;
4815 /* ??? This doesn't work yet, so don't let people try to use it. */
4816 if (mips_abi == ABI_32)
4817 error ("The -mabi=32 support does not work yet.");
4820 if (mips_abi_string)
4821 error ("This target does not support the -mabi switch.");
4824 #ifdef MIPS_CPU_STRING_DEFAULT
4825 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4826 greater than that supported by the default processor, then the user gets
4827 an error. Normally, the compiler will just default to the base level cpu
4828 for the indicated isa. */
4829 if (mips_cpu_string == 0)
4830 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4833 /* Identify the processor type. */
4834 if (mips_cpu_string == 0
4835 || ! strcmp (mips_cpu_string, "default")
4836 || ! strcmp (mips_cpu_string, "DEFAULT"))
4841 mips_cpu_string = "3000";
4842 mips_cpu = PROCESSOR_R3000;
4845 mips_cpu_string = "6000";
4846 mips_cpu = PROCESSOR_R6000;
4849 mips_cpu_string = "4000";
4850 mips_cpu = PROCESSOR_R4000;
4853 mips_cpu_string = "8000";
4854 mips_cpu = PROCESSOR_R8000;
4860 const char *p = mips_cpu_string;
4863 /* We need to cope with the various "vr" prefixes for the NEC 4300
4864 and 4100 processors. */
4865 if (*p == 'v' || *p == 'V')
4868 if (*p == 'r' || *p == 'R')
4871 /* Since there is no difference between a R2000 and R3000 in
4872 terms of the scheduler, we collapse them into just an R3000. */
4874 mips_cpu = PROCESSOR_DEFAULT;
4878 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4879 mips_cpu = PROCESSOR_R3000;
4883 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4884 mips_cpu = PROCESSOR_R3000;
4885 else if (!strcmp (p, "3900"))
4886 mips_cpu = PROCESSOR_R3900;
4890 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4891 mips_cpu = PROCESSOR_R4000;
4892 /* The vr4100 is a non-FP ISA III processor with some extra
4894 else if (!strcmp (p, "4100"))
4896 mips_cpu = PROCESSOR_R4100;
4897 target_flags |= MASK_SOFT_FLOAT ;
4899 /* The vr4300 is a standard ISA III processor, but with a different
4901 else if (!strcmp (p, "4300"))
4902 mips_cpu = PROCESSOR_R4300;
4903 /* The r4400 is exactly the same as the r4000 from the compiler's
4905 else if (!strcmp (p, "4400"))
4906 mips_cpu = PROCESSOR_R4000;
4907 else if (!strcmp (p, "4600"))
4908 mips_cpu = PROCESSOR_R4600;
4909 else if (!strcmp (p, "4650"))
4910 mips_cpu = PROCESSOR_R4650;
4914 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4915 mips_cpu = PROCESSOR_R5000;
4919 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4920 mips_cpu = PROCESSOR_R6000;
4924 if (!strcmp (p, "8000"))
4925 mips_cpu = PROCESSOR_R8000;
4929 if (!strcmp (p, "orion"))
4930 mips_cpu = PROCESSOR_R4600;
4935 && mips_cpu != PROCESSOR_R4300
4936 && mips_cpu != PROCESSOR_R4100
4937 && mips_cpu != PROCESSOR_R5000)
4938 mips_cpu = PROCESSOR_DEFAULT;
4940 if (mips_cpu == PROCESSOR_DEFAULT)
4942 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4943 mips_cpu_string = "default";
4947 if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
4948 || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
4949 || ((mips_cpu == PROCESSOR_R4000
4950 || mips_cpu == PROCESSOR_R4100
4951 || mips_cpu == PROCESSOR_R4300
4952 || mips_cpu == PROCESSOR_R4600
4953 || mips_cpu == PROCESSOR_R4650)
4954 && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
4955 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4957 /* make sure sizes of ints/longs/etc. are ok */
4958 if (! ISA_HAS_64BIT_REGS)
4962 error ("-mips%d does not support 64 bit fp registers", mips_isa);
4963 target_flags &= ~ MASK_FLOAT64;
4966 else if (TARGET_64BIT)
4968 error ("-mips%d does not support 64 bit gp registers", mips_isa);
4969 target_flags &= ~MASK_64BIT;
4973 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4974 flag_pcc_struct_return = 0;
4976 /* Tell halfpic.c that we have half-pic code if we do. */
4977 if (TARGET_HALF_PIC)
4980 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4981 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4982 /* ??? -non_shared turns off pic code generation, but this is not
4984 if (TARGET_ABICALLS)
4986 mips_abicalls = MIPS_ABICALLS_YES;
4988 if (mips_section_threshold > 0)
4989 warning ("-G is incompatible with PIC code which is the default");
4992 mips_abicalls = MIPS_ABICALLS_NO;
4994 /* -membedded-pic is a form of PIC code suitable for embedded
4995 systems. All calls are made using PC relative addressing, and
4996 all data is addressed using the $gp register. This requires gas,
4997 which does most of the work, and GNU ld, which automatically
4998 expands PC relative calls which are out of range into a longer
4999 instruction sequence. All gcc really does differently is
5000 generate a different sequence for a switch. */
5001 if (TARGET_EMBEDDED_PIC)
5004 if (TARGET_ABICALLS)
5005 warning ("-membedded-pic and -mabicalls are incompatible");
5008 warning ("-G and -membedded-pic are incompatible");
5010 /* Setting mips_section_threshold is not required, because gas
5011 will force everything to be GP addressable anyhow, but
5012 setting it will cause gcc to make better estimates of the
5013 number of instructions required to access a particular data
5015 mips_section_threshold = 0x7fffffff;
5018 /* This optimization requires a linker that can support a R_MIPS_LO16
5019 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5020 GNU ld has this support, but not all other MIPS linkers do, so we enable
5021 this optimization only if the user requests it, or if GNU ld is the
5022 standard linker for this configuration. */
5023 /* ??? This does not work when target addresses are DImode.
5024 This is because we are missing DImode high/lo_sum patterns. */
5025 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5027 mips_split_addresses = 1;
5029 mips_split_addresses = 0;
5031 /* -mrnames says to use the MIPS software convention for register
5032 names instead of the hardware names (ie, $a0 instead of $4).
5033 We do this by switching the names in mips_reg_names, which the
5034 reg_names points into via the REGISTER_NAMES macro. */
5036 if (TARGET_NAME_REGS)
5037 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
5039 /* When compiling for the mips16, we can not use floating point. We
5040 record the original hard float value in mips16_hard_float. */
5043 if (TARGET_SOFT_FLOAT)
5044 mips16_hard_float = 0;
5046 mips16_hard_float = 1;
5047 target_flags |= MASK_SOFT_FLOAT;
5049 /* Don't run the scheduler before reload, since it tends to
5050 increase register pressure. */
5051 flag_schedule_insns = 0;
5054 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5055 to avoid using up another bit in target_flags. */
5056 if (mips_entry_string != NULL)
5058 if (*mips_entry_string != '\0')
5059 error ("Invalid option `entry%s'", mips_entry_string);
5061 if (! TARGET_MIPS16)
5062 warning ("-mentry is only meaningful with -mips-16");
5067 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5068 attributes can access it. */
5074 /* Initialize the high and low values for legitimate floating point
5075 constants. Rather than trying to get the accuracy down to the
5076 last bit, just use approximate ranges. */
5077 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5078 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5079 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5080 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5082 mips_print_operand_punct['?'] = 1;
5083 mips_print_operand_punct['#'] = 1;
5084 mips_print_operand_punct['&'] = 1;
5085 mips_print_operand_punct['!'] = 1;
5086 mips_print_operand_punct['*'] = 1;
5087 mips_print_operand_punct['@'] = 1;
5088 mips_print_operand_punct['.'] = 1;
5089 mips_print_operand_punct['('] = 1;
5090 mips_print_operand_punct[')'] = 1;
5091 mips_print_operand_punct['['] = 1;
5092 mips_print_operand_punct[']'] = 1;
5093 mips_print_operand_punct['<'] = 1;
5094 mips_print_operand_punct['>'] = 1;
5095 mips_print_operand_punct['{'] = 1;
5096 mips_print_operand_punct['}'] = 1;
5097 mips_print_operand_punct['^'] = 1;
5098 mips_print_operand_punct['$'] = 1;
5099 mips_print_operand_punct['+'] = 1;
5100 mips_print_operand_punct['~'] = 1;
5102 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5103 mips_char_to_class['e'] = M16_NA_REGS;
5104 mips_char_to_class['t'] = T_REG;
5105 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5106 mips_char_to_class['h'] = HI_REG;
5107 mips_char_to_class['l'] = LO_REG;
5108 mips_char_to_class['a'] = HILO_REG;
5109 mips_char_to_class['x'] = MD_REGS;
5110 mips_char_to_class['b'] = ALL_REGS;
5111 mips_char_to_class['y'] = GR_REGS;
5112 mips_char_to_class['z'] = ST_REGS;
5114 /* Set up array to map GCC register number to debug register number.
5115 Ignore the special purpose register numbers. */
5117 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5118 mips_dbx_regno[i] = -1;
5120 start = GP_DBX_FIRST - GP_REG_FIRST;
5121 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5122 mips_dbx_regno[i] = i + start;
5124 start = FP_DBX_FIRST - FP_REG_FIRST;
5125 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5126 mips_dbx_regno[i] = i + start;
5128 /* Set up array giving whether a given register can hold a given mode.
5129 At present, restrict ints from being in FP registers, because reload
5130 is a little enthusiastic about storing extra values in FP registers,
5131 and this is not good for things like OS kernels. Also, due to the
5132 mandatory delay, it is as fast to load from cached memory as to move
5133 from the FP register. */
5135 for (mode = VOIDmode;
5136 mode != MAX_MACHINE_MODE;
5137 mode = (enum machine_mode) ((int)mode + 1))
5139 register int size = GET_MODE_SIZE (mode);
5140 register enum mode_class class = GET_MODE_CLASS (mode);
5142 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5149 temp = (regno == FPSW_REGNUM);
5151 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5152 || FP_REG_P (regno));
5155 else if (GP_REG_P (regno))
5156 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5158 else if (FP_REG_P (regno))
5159 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
5160 && (class == MODE_FLOAT
5161 || class == MODE_COMPLEX_FLOAT
5162 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
5163 && (! TARGET_SINGLE_FLOAT || size <= 4));
5165 else if (MD_REG_P (regno))
5166 temp = (class == MODE_INT
5167 && (size <= UNITS_PER_WORD
5168 || (regno == MD_REG_FIRST
5169 && size == 2 * UNITS_PER_WORD)));
5174 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5178 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5179 initialized yet, so we can't use that here. */
5180 gpr_mode = TARGET_64BIT ? DImode : SImode;
5182 /* Provide default values for align_* for 64-bit targets. */
5183 if (TARGET_64BIT && !TARGET_MIPS16)
5185 if (align_loops == 0)
5187 if (align_jumps == 0)
5189 if (align_functions == 0)
5190 align_functions = 8;
5193 /* Register global variables with the garbage collector. */
5194 mips_add_gc_roots ();
5197 /* On the mips16, we want to allocate $24 (T_REG) before other
5198 registers for instructions for which it is possible. This helps
5199 avoid shuffling registers around in order to set up for an xor,
5200 encouraging the compiler to use a cmp instead. */
5203 mips_order_regs_for_local_alloc ()
5207 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5208 reg_alloc_order[i] = i;
5212 /* It really doesn't matter where we put register 0, since it is
5213 a fixed register anyhow. */
5214 reg_alloc_order[0] = 24;
5215 reg_alloc_order[24] = 0;
5220 /* The MIPS debug format wants all automatic variables and arguments
5221 to be in terms of the virtual frame pointer (stack pointer before
5222 any adjustment in the function), while the MIPS 3.0 linker wants
5223 the frame pointer to be the stack pointer after the initial
5224 adjustment. So, we do the adjustment here. The arg pointer (which
5225 is eliminated) points to the virtual frame pointer, while the frame
5226 pointer (which may be eliminated) points to the stack pointer after
5227 the initial adjustments. */
5230 mips_debugger_offset (addr, offset)
5232 HOST_WIDE_INT offset;
5234 rtx offset2 = const0_rtx;
5235 rtx reg = eliminate_constant_term (addr, &offset2);
5238 offset = INTVAL (offset2);
5240 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5241 || reg == hard_frame_pointer_rtx)
5243 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
5244 ? compute_frame_size (get_frame_size ())
5245 : current_frame_info.total_size;
5247 /* MIPS16 frame is smaller */
5248 if (frame_pointer_needed && TARGET_MIPS16)
5249 frame_size -= current_function_outgoing_args_size;
5251 offset = offset - frame_size;
5254 /* sdbout_parms does not want this to crash for unrecognized cases. */
5256 else if (reg != arg_pointer_rtx)
5257 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
5263 /* A C compound statement to output to stdio stream STREAM the
5264 assembler syntax for an instruction operand X. X is an RTL
5267 CODE is a value that can be used to specify one of several ways
5268 of printing the operand. It is used when identical operands
5269 must be printed differently depending on the context. CODE
5270 comes from the `%' specification that was used to request
5271 printing of the operand. If the specification was just `%DIGIT'
5272 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5273 is the ASCII code for LTR.
5275 If X is a register, this macro should print the register's name.
5276 The names can be found in an array `reg_names' whose type is
5277 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5279 When the machine description has a specification `%PUNCT' (a `%'
5280 followed by a punctuation character), this macro is called with
5281 a null pointer for X and the punctuation character for CODE.
5283 The MIPS specific codes are:
5285 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5286 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5287 'd' output integer constant in decimal,
5288 'z' if the operand is 0, use $0 instead of normal operand.
5289 'D' print second register of double-word register operand.
5290 'L' print low-order register of double-word register operand.
5291 'M' print high-order register of double-word register operand.
5292 'C' print part of opcode for a branch condition.
5293 'F' print part of opcode for a floating-point branch condition.
5294 'N' print part of opcode for a branch condition, inverted.
5295 'W' print part of opcode for a floating-point branch condition, inverted.
5296 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5297 'B' print 'z' for EQ, 'n' for NE
5298 'b' print 'n' for EQ, 'z' for NE
5299 'T' print 'f' for EQ, 't' for NE
5300 't' print 't' for EQ, 'f' for NE
5301 'Z' print register and a comma, but print nothing for $fcc0
5302 '(' Turn on .set noreorder
5303 ')' Turn on .set reorder
5304 '[' Turn on .set noat
5306 '<' Turn on .set nomacro
5307 '>' Turn on .set macro
5308 '{' Turn on .set volatile (not GAS)
5309 '}' Turn on .set novolatile (not GAS)
5310 '&' Turn on .set noreorder if filling delay slots
5311 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5312 '!' Turn on .set nomacro if filling delay slots
5313 '#' Print nop if in a .set noreorder section.
5314 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5315 '@' Print the name of the assembler temporary register (at or $1).
5316 '.' Print the name of the register with a hard-wired zero (zero or $0).
5317 '^' Print the name of the pic call-through register (t9 or $25).
5318 '$' Print the name of the stack pointer register (sp or $29).
5319 '+' Print the name of the gp register (gp or $28).
5320 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5323 print_operand (file, op, letter)
5324 FILE *file; /* file to write to */
5325 rtx op; /* operand to print */
5326 int letter; /* %<letter> or 0 */
5328 register enum rtx_code code;
5330 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5335 if (mips_branch_likely)
5340 fputs (reg_names [GP_REG_FIRST + 1], file);
5344 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5348 fputs (reg_names [GP_REG_FIRST + 0], file);
5352 fputs (reg_names[STACK_POINTER_REGNUM], file);
5356 fputs (reg_names[GP_REG_FIRST + 28], file);
5360 if (final_sequence != 0 && set_noreorder++ == 0)
5361 fputs (".set\tnoreorder\n\t", file);
5365 if (final_sequence != 0)
5367 if (set_noreorder++ == 0)
5368 fputs (".set\tnoreorder\n\t", file);
5370 if (set_nomacro++ == 0)
5371 fputs (".set\tnomacro\n\t", file);
5376 if (final_sequence != 0 && set_nomacro++ == 0)
5377 fputs ("\n\t.set\tnomacro", file);
5381 if (set_noreorder != 0)
5382 fputs ("\n\tnop", file);
5383 else if (TARGET_STATS)
5384 fputs ("\n\t#nop", file);
5389 if (set_noreorder++ == 0)
5390 fputs (".set\tnoreorder\n\t", file);
5394 if (set_noreorder == 0)
5395 error ("internal error: %%) found without a %%( in assembler pattern");
5397 else if (--set_noreorder == 0)
5398 fputs ("\n\t.set\treorder", file);
5403 if (set_noat++ == 0)
5404 fputs (".set\tnoat\n\t", file);
5409 error ("internal error: %%] found without a %%[ in assembler pattern");
5410 else if (--set_noat == 0)
5411 fputs ("\n\t.set\tat", file);
5416 if (set_nomacro++ == 0)
5417 fputs (".set\tnomacro\n\t", file);
5421 if (set_nomacro == 0)
5422 error ("internal error: %%> found without a %%< in assembler pattern");
5423 else if (--set_nomacro == 0)
5424 fputs ("\n\t.set\tmacro", file);
5429 if (set_volatile++ == 0)
5430 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5434 if (set_volatile == 0)
5435 error ("internal error: %%} found without a %%{ in assembler pattern");
5436 else if (--set_volatile == 0)
5437 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5443 if (align_labels_log > 0)
5444 ASM_OUTPUT_ALIGN (file, align_labels_log);
5449 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
5458 error ("PRINT_OPERAND null pointer");
5462 code = GET_CODE (op);
5464 if (code == SIGN_EXTEND)
5465 op = XEXP (op, 0), code = GET_CODE (op);
5470 case EQ: fputs ("eq", file); break;
5471 case NE: fputs ("ne", file); break;
5472 case GT: fputs ("gt", file); break;
5473 case GE: fputs ("ge", file); break;
5474 case LT: fputs ("lt", file); break;
5475 case LE: fputs ("le", file); break;
5476 case GTU: fputs ("gtu", file); break;
5477 case GEU: fputs ("geu", file); break;
5478 case LTU: fputs ("ltu", file); break;
5479 case LEU: fputs ("leu", file); break;
5481 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5484 else if (letter == 'N')
5487 case EQ: fputs ("ne", file); break;
5488 case NE: fputs ("eq", file); break;
5489 case GT: fputs ("le", file); break;
5490 case GE: fputs ("lt", file); break;
5491 case LT: fputs ("ge", file); break;
5492 case LE: fputs ("gt", file); break;
5493 case GTU: fputs ("leu", file); break;
5494 case GEU: fputs ("ltu", file); break;
5495 case LTU: fputs ("geu", file); break;
5496 case LEU: fputs ("gtu", file); break;
5498 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5501 else if (letter == 'F')
5504 case EQ: fputs ("c1f", file); break;
5505 case NE: fputs ("c1t", file); break;
5507 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5510 else if (letter == 'W')
5513 case EQ: fputs ("c1t", file); break;
5514 case NE: fputs ("c1f", file); break;
5516 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5519 else if (letter == 'S')
5523 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5524 assemble_name (file, buffer);
5527 else if (letter == 'Z')
5529 register int regnum;
5534 regnum = REGNO (op);
5535 if (! ST_REG_P (regnum))
5538 if (regnum != ST_REG_FIRST)
5539 fprintf (file, "%s,", reg_names[regnum]);
5542 else if (code == REG || code == SUBREG)
5544 register int regnum;
5547 regnum = REGNO (op);
5549 regnum = true_regnum (op);
5551 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5552 || (letter == 'L' && WORDS_BIG_ENDIAN)
5556 fprintf (file, "%s", reg_names[regnum]);
5559 else if (code == MEM)
5560 output_address (XEXP (op, 0));
5562 else if (code == CONST_DOUBLE
5563 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5568 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5569 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5573 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5574 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5576 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5577 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5579 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5580 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5582 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5583 fputs (reg_names[GP_REG_FIRST], file);
5585 else if (letter == 'd' || letter == 'x' || letter == 'X')
5586 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5588 else if (letter == 'B')
5589 fputs (code == EQ ? "z" : "n", file);
5590 else if (letter == 'b')
5591 fputs (code == EQ ? "n" : "z", file);
5592 else if (letter == 'T')
5593 fputs (code == EQ ? "f" : "t", file);
5594 else if (letter == 't')
5595 fputs (code == EQ ? "t" : "f", file);
5597 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5599 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5600 print_operand (file, XEXP (op, 0), letter);
5603 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5605 fputs ("%gprel(", file);
5606 mips16_output_gp_offset (file, op);
5611 output_addr_const (file, op);
5614 /* A C compound statement to output to stdio stream STREAM the
5615 assembler syntax for an instruction operand that is a memory
5616 reference whose address is ADDR. ADDR is an RTL expression.
5618 On some machines, the syntax for a symbolic address depends on
5619 the section that the address refers to. On these machines,
5620 define the macro `ENCODE_SECTION_INFO' to store the information
5621 into the `symbol_ref', and then check for it here. */
5624 print_operand_address (file, addr)
5629 error ("PRINT_OPERAND_ADDRESS, null pointer");
5632 switch (GET_CODE (addr))
5635 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5636 abort_with_insn (addr, "Arg pointer not eliminated.");
5638 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5643 register rtx arg0 = XEXP (addr, 0);
5644 register rtx arg1 = XEXP (addr, 1);
5646 if (! mips_split_addresses)
5647 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5649 if (GET_CODE (arg0) != REG)
5650 abort_with_insn (addr,
5651 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
5653 fprintf (file, "%%lo(");
5654 print_operand_address (file, arg1);
5655 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5661 register rtx reg = 0;
5662 register rtx offset = 0;
5663 register rtx arg0 = XEXP (addr, 0);
5664 register rtx arg1 = XEXP (addr, 1);
5666 if (GET_CODE (arg0) == REG)
5670 if (GET_CODE (offset) == REG)
5671 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5674 else if (GET_CODE (arg1) == REG)
5675 reg = arg1, offset = arg0;
5676 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5678 output_addr_const (file, addr);
5682 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5684 if (! CONSTANT_P (offset))
5685 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5687 if (REGNO (reg) == ARG_POINTER_REGNUM)
5688 abort_with_insn (addr, "Arg pointer not eliminated.");
5691 && GET_CODE (offset) == CONST
5692 && mips16_gp_offset_p (offset))
5694 fputs ("%gprel(", file);
5695 mips16_output_gp_offset (file, offset);
5699 output_addr_const (file, offset);
5700 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5708 output_addr_const (file, addr);
5712 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5718 /* If optimizing for the global pointer, keep track of all of the externs, so
5719 that at the end of the file, we can emit the appropriate .extern
5720 declaration for them, before writing out the text section. We assume all
5721 names passed to us are in the permanent obstack, so they will be valid at
5722 the end of the compilation.
5724 If we have -G 0, or the extern size is unknown, or the object is in a user
5725 specified section that is not .sbss/.sdata, don't bother emitting the
5726 .externs. In the case of user specified sections this behaviour is
5727 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5730 mips_output_external (file, decl, name)
5731 FILE *file ATTRIBUTE_UNUSED;
5735 register struct extern_list *p;
5740 && TREE_CODE (decl) != FUNCTION_DECL
5741 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5742 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5743 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5744 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5746 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5747 p->next = extern_head;
5753 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5754 if (TREE_CODE (decl) == FUNCTION_DECL
5755 /* ??? Don't include alloca, since gcc will always expand it
5756 inline. If we don't do this, the C++ library fails to build. */
5757 && strcmp (name, "alloca")
5758 /* ??? Don't include __builtin_next_arg, because then gcc will not
5759 bootstrap under Irix 5.1. */
5760 && strcmp (name, "__builtin_next_arg"))
5762 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5763 p->next = extern_head;
5773 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5775 mips_output_external_libcall (file, name)
5779 register struct extern_list *p;
5781 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5782 p->next = extern_head;
5791 /* Compute a string to use as a temporary file name. */
5794 mips_make_temp_file ()
5798 temp_filename = make_temp_file (0);
5799 stream = fopen (temp_filename, "w+");
5801 fatal_io_error ("can't open %s", temp_filename);
5805 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5806 for .file's that start within a function. If we are smuggling stabs, try to
5807 put out a MIPS ECOFF file and a stab. */
5810 mips_output_filename (stream, name)
5814 static int first_time = 1;
5815 char ltext_label_name[100];
5821 current_function_file = name;
5822 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5823 /* This tells mips-tfile that stabs will follow. */
5824 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5825 fprintf (stream, "\t#@stabs\n");
5828 else if (write_symbols == DBX_DEBUG)
5830 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5831 fprintf (stream, "%s", ASM_STABS_OP);
5832 output_quoted_string (stream, name);
5833 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5836 else if (name != current_function_file
5837 && strcmp (name, current_function_file) != 0)
5839 if (inside_function && !TARGET_GAS)
5841 if (!file_in_function_warning)
5843 file_in_function_warning = 1;
5844 ignore_line_number = 1;
5845 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5851 current_function_file = name;
5852 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5857 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5858 as well as a .loc, since it is possible that MIPS ECOFF might not be
5859 able to represent the location for inlines that come from a different
5863 mips_output_lineno (stream, line)
5867 if (write_symbols == DBX_DEBUG)
5870 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5871 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5872 LOCAL_LABEL_PREFIX, sym_lineno);
5877 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5878 (ignore_line_number) ? "#" : "",
5879 num_source_filenames, line);
5881 LABEL_AFTER_LOC (stream);
5885 /* Output an ASCII string, in a space-saving way. */
5888 mips_output_ascii (stream, string_param, len)
5890 const char *string_param;
5895 register const unsigned char *string =
5896 (const unsigned char *)string_param;
5898 fprintf (stream, "\t.ascii\t\"");
5899 for (i = 0; i < len; i++)
5901 register int c = string[i];
5907 putc ('\\', stream);
5912 case TARGET_NEWLINE:
5913 fputs ("\\n", stream);
5915 && (((c = string[i+1]) >= '\040' && c <= '~')
5916 || c == TARGET_TAB))
5917 cur_pos = 32767; /* break right here */
5923 fputs ("\\t", stream);
5928 fputs ("\\f", stream);
5933 fputs ("\\b", stream);
5938 fputs ("\\r", stream);
5943 if (c >= ' ' && c < 0177)
5950 fprintf (stream, "\\%03o", c);
5955 if (cur_pos > 72 && i+1 < len)
5958 fprintf (stream, "\"\n\t.ascii\t\"");
5961 fprintf (stream, "\"\n");
5964 /* If defined, a C statement to be executed just prior to the output of
5965 assembler code for INSN, to modify the extracted operands so they will be
5968 Here the argument OPVEC is the vector containing the operands extracted
5969 from INSN, and NOPERANDS is the number of elements of the vector which
5970 contain meaningful data for this insn. The contents of this vector are
5971 what will be used to convert the insn template into assembler code, so you
5972 can change the assembler output by changing the contents of the vector.
5974 We use it to check if the current insn needs a nop in front of it because
5975 of load delays, and also to update the delay slot statistics. */
5977 /* ??? There is no real need for this function, because it never actually
5978 emits a NOP anymore. */
5981 final_prescan_insn (insn, opvec, noperands)
5983 rtx opvec[] ATTRIBUTE_UNUSED;
5984 int noperands ATTRIBUTE_UNUSED;
5986 if (dslots_number_nops > 0)
5988 rtx pattern = PATTERN (insn);
5989 int length = get_attr_length (insn);
5991 /* Do we need to emit a NOP? */
5993 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5994 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5995 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5996 || (mips_load_reg4 != 0
5997 && reg_mentioned_p (mips_load_reg4, pattern)))
5998 fputs ("\t#nop\n", asm_out_file);
6001 dslots_load_filled++;
6003 while (--dslots_number_nops > 0)
6004 fputs ("\t#nop\n", asm_out_file);
6013 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6014 dslots_jump_total++;
6017 /* Output at beginning of assembler file.
6019 If we are optimizing to use the global pointer, create a temporary file to
6020 hold all of the text stuff, and write it out to the end. This is needed
6021 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6022 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6023 processed, it generates a two instruction sequence. */
6026 mips_asm_file_start (stream)
6029 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6031 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6032 inside of a .set noreorder section jumps to a label outside of the .set
6033 noreorder section. Revision 2.20 just set nobopt silently rather than
6036 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6037 fprintf (stream, "\t.set\tnobopt\n");
6039 /* Generate the pseudo ops that System V.4 wants. */
6040 #ifndef ABICALLS_ASM_OP
6041 #define ABICALLS_ASM_OP "\t.abicalls"
6043 if (TARGET_ABICALLS)
6044 /* ??? but do not want this (or want pic0) if -non-shared? */
6045 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
6048 fprintf (stream, "\t.set\tmips16\n");
6050 /* Start a section, so that the first .popsection directive is guaranteed
6051 to have a previously defined section to pop back to. */
6052 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
6053 fprintf (stream, "\t.section\t.text\n");
6055 /* This code exists so that we can put all externs before all symbol
6056 references. This is necessary for the MIPS assembler's global pointer
6057 optimizations to work. */
6058 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
6060 asm_out_data_file = stream;
6061 asm_out_text_file = mips_make_temp_file ();
6065 asm_out_data_file = asm_out_text_file = stream;
6067 if (flag_verbose_asm)
6068 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
6070 mips_section_threshold, mips_cpu_string, mips_isa);
6073 /* If we are optimizing the global pointer, emit the text section now and any
6074 small externs which did not have .comm, etc that are needed. Also, give a
6075 warning if the data area is more than 32K and -pic because 3 instructions
6076 are needed to reference the data pointers. */
6079 mips_asm_file_end (file)
6084 struct extern_list *p;
6089 HALF_PIC_FINISH (file);
6096 for (p = extern_head; p != 0; p = p->next)
6098 name_tree = get_identifier (p->name);
6100 /* Positively ensure only one .extern for any given symbol. */
6101 if (! TREE_ASM_WRITTEN (name_tree))
6103 TREE_ASM_WRITTEN (name_tree) = 1;
6104 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6106 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6110 fputs ("\t.extern\t", file);
6111 assemble_name (file, p->name);
6112 fprintf (file, ", %d\n", p->size);
6118 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
6120 fprintf (file, "\n\t.text\n");
6121 rewind (asm_out_text_file);
6122 if (ferror (asm_out_text_file))
6123 fatal_io_error ("can't rewind %s", temp_filename);
6125 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
6126 if ((int) fwrite (buffer, 1, len, file) != len)
6127 fatal_io_error ("can't write to %s", asm_file_name);
6130 fatal_io_error ("can't read from %s", temp_filename);
6132 if (fclose (asm_out_text_file) != 0)
6133 fatal_io_error ("can't close %s", temp_filename);
6135 unlink (temp_filename);
6136 free (temp_filename);
6140 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6141 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6144 mips_declare_object (stream, name, init_string, final_string, size)
6147 const char *init_string;
6148 const char *final_string;
6151 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6152 assemble_name (stream, name);
6153 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6157 tree name_tree = get_identifier (name);
6158 TREE_ASM_WRITTEN (name_tree) = 1;
6162 /* Output a double precision value to the assembler. If both the
6163 host and target are IEEE, emit the values in hex. */
6166 mips_output_double (stream, value)
6168 REAL_VALUE_TYPE value;
6170 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
6172 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
6174 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
6175 value_long[0], value, value_long[1]);
6177 fprintf (stream, "\t.double\t%.20g\n", value);
6181 /* Output a single precision value to the assembler. If both the
6182 host and target are IEEE, emit the values in hex. */
6185 mips_output_float (stream, value)
6187 REAL_VALUE_TYPE value;
6189 #ifdef REAL_VALUE_TO_TARGET_SINGLE
6191 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
6193 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
6195 fprintf (stream, "\t.float\t%.12g\n", value);
6199 /* Return the bytes needed to compute the frame pointer from the current
6202 Mips stack frames look like:
6204 Before call After call
6205 +-----------------------+ +-----------------------+
6208 | caller's temps. | | caller's temps. |
6210 +-----------------------+ +-----------------------+
6212 | arguments on stack. | | arguments on stack. |
6214 +-----------------------+ +-----------------------+
6215 | 4 words to save | | 4 words to save |
6216 | arguments passed | | arguments passed |
6217 | in registers, even | | in registers, even |
6218 SP->| if not passed. | VFP->| if not passed. |
6219 +-----------------------+ +-----------------------+
6221 | fp register save |
6223 +-----------------------+
6225 | gp register save |
6227 +-----------------------+
6231 +-----------------------+
6233 | alloca allocations |
6235 +-----------------------+
6237 | GP save for V.4 abi |
6239 +-----------------------+
6241 | arguments on stack |
6243 +-----------------------+
6245 | arguments passed |
6246 | in registers, even |
6247 low SP->| if not passed. |
6248 memory +-----------------------+
6253 compute_frame_size (size)
6254 HOST_WIDE_INT size; /* # of var. bytes allocated */
6257 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6258 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6259 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6260 HOST_WIDE_INT extra_size; /* # extra bytes */
6261 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6262 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6263 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6264 long mask; /* mask of saved gp registers */
6265 long fmask; /* mask of saved fp registers */
6266 int fp_inc; /* 1 or 2 depending on the size of fp regs */
6267 long fp_bits; /* bitmask to use for each fp register */
6273 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6274 var_size = MIPS_STACK_ALIGN (size);
6275 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6277 /* The MIPS 3.0 linker does not like functions that dynamically
6278 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6279 looks like we are trying to create a second frame pointer to the
6280 function, so allocate some stack space to make it happy. */
6282 if (args_size == 0 && current_function_calls_alloca)
6283 args_size = 4 * UNITS_PER_WORD;
6285 total_size = var_size + args_size + extra_size;
6287 /* Calculate space needed for gp registers. */
6288 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6290 /* $18 is a special case on the mips16. It may be used to call
6291 a function which returns a floating point value, but it is
6292 marked in call_used_regs. $31 is also a special case. When
6293 not using -mentry, it will be used to copy a return value
6294 into the floating point registers if the return value is
6296 if (MUST_SAVE_REGISTER (regno)
6298 && regno == GP_REG_FIRST + 18
6299 && regs_ever_live[regno])
6301 && regno == GP_REG_FIRST + 31
6302 && mips16_hard_float
6304 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6305 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6307 && (! TARGET_SINGLE_FLOAT
6308 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6311 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6312 mask |= 1L << (regno - GP_REG_FIRST);
6314 /* The entry and exit pseudo instructions can not save $17
6315 without also saving $16. */
6317 && regno == GP_REG_FIRST + 17
6318 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6320 gp_reg_size += UNITS_PER_WORD;
6326 /* We need to restore these for the handler. */
6327 if (current_function_calls_eh_return)
6332 regno = EH_RETURN_DATA_REGNO (i);
6333 if (regno == INVALID_REGNUM)
6335 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6336 mask |= 1L << (regno - GP_REG_FIRST);
6340 /* Calculate space needed for fp registers. */
6341 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
6352 /* This loop must iterate over the same space as its companion in
6353 save_restore_regs. */
6354 for (regno = (FP_REG_LAST - fp_inc + 1);
6355 regno >= FP_REG_FIRST;
6358 if (regs_ever_live[regno] && !call_used_regs[regno])
6360 fp_reg_size += fp_inc * UNITS_PER_FPREG;
6361 fmask |= fp_bits << (regno - FP_REG_FIRST);
6365 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6366 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6368 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6369 for leaf routines (total_size == extra_size) to save the gp reg.
6370 The gp reg is callee saved in the 64 bit ABI, so all routines must
6371 save the gp reg. This is not a leaf routine if -p, because of the
6373 if (total_size == extra_size
6374 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6376 total_size = extra_size = 0;
6377 else if (TARGET_ABICALLS)
6379 /* Add the context-pointer to the saved registers. */
6380 gp_reg_size += UNITS_PER_WORD;
6381 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6382 total_size -= gp_reg_rounded;
6383 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6384 total_size += gp_reg_rounded;
6387 /* Add in space reserved on the stack by the callee for storing arguments
6388 passed in registers. */
6389 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6390 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6392 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6393 if (mips_entry && total_size > 0 && total_size < 32)
6396 /* Save other computed information. */
6397 current_frame_info.total_size = total_size;
6398 current_frame_info.var_size = var_size;
6399 current_frame_info.args_size = args_size;
6400 current_frame_info.extra_size = extra_size;
6401 current_frame_info.gp_reg_size = gp_reg_size;
6402 current_frame_info.fp_reg_size = fp_reg_size;
6403 current_frame_info.mask = mask;
6404 current_frame_info.fmask = fmask;
6405 current_frame_info.initialized = reload_completed;
6406 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6407 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
6411 unsigned long offset;
6413 /* When using mips_entry, the registers are always saved at the
6414 top of the stack. */
6416 offset = (args_size + extra_size + var_size
6417 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6419 offset = total_size - GET_MODE_SIZE (gpr_mode);
6421 current_frame_info.gp_sp_offset = offset;
6422 current_frame_info.gp_save_offset = offset - total_size;
6426 current_frame_info.gp_sp_offset = 0;
6427 current_frame_info.gp_save_offset = 0;
6432 unsigned long offset = (args_size + extra_size + var_size
6433 + gp_reg_rounded + fp_reg_size
6434 - fp_inc * UNITS_PER_FPREG);
6435 current_frame_info.fp_sp_offset = offset;
6436 current_frame_info.fp_save_offset = offset - total_size;
6440 current_frame_info.fp_sp_offset = 0;
6441 current_frame_info.fp_save_offset = 0;
6444 /* Ok, we're done. */
6448 /* Common code to emit the insns (or to write the instructions to a file)
6449 to save/restore registers.
6451 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6452 is not modified within save_restore_insns. */
6454 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6457 save_restore_insns (store_p, large_reg, large_offset, file)
6458 int store_p; /* true if this is prologue */
6459 rtx large_reg; /* register holding large offset constant or NULL */
6460 long large_offset; /* large constant offset value */
6461 FILE *file; /* file to write instructions instead of making RTL */
6463 long mask = current_frame_info.mask;
6464 long fmask = current_frame_info.fmask;
6467 HOST_WIDE_INT base_offset;
6468 HOST_WIDE_INT gp_offset;
6469 HOST_WIDE_INT fp_offset;
6470 HOST_WIDE_INT end_offset;
6473 if (frame_pointer_needed
6474 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6477 if (mask == 0 && fmask == 0)
6480 /* Save registers starting from high to low. The debuggers prefer at least
6481 the return register be stored at func+4, and also it allows us not to
6482 need a nop in the epilog if at least one register is reloaded in
6483 addition to return address. */
6485 /* Save GP registers if needed. */
6488 /* Pick which pointer to use as a base register. For small frames, just
6489 use the stack pointer. Otherwise, use a temporary register. Save 2
6490 cycles if the save area is near the end of a large frame, by reusing
6491 the constant created in the prologue/epilogue to adjust the stack
6494 gp_offset = current_frame_info.gp_sp_offset;
6496 = gp_offset - (current_frame_info.gp_reg_size
6497 - GET_MODE_SIZE (gpr_mode));
6499 if (gp_offset < 0 || end_offset < 0)
6501 ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6502 (long) gp_offset, (long) end_offset);
6504 /* If we see a large frame in mips16 mode, we save the registers
6505 before adjusting the stack pointer, and load them afterward. */
6506 else if (TARGET_MIPS16 && large_offset > 32767)
6507 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6509 else if (gp_offset < 32768)
6510 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6512 else if (large_reg != 0
6513 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6514 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6516 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6517 base_offset = large_offset;
6520 if (Pmode == DImode)
6521 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6522 stack_pointer_rtx));
6524 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6525 stack_pointer_rtx));
6527 RTX_FRAME_RELATED_P (insn) = 1;
6530 fprintf (file, "\t%s\t%s,%s,%s\n",
6531 Pmode == DImode ? "daddu" : "addu",
6532 reg_names[MIPS_TEMP2_REGNUM],
6533 reg_names[REGNO (large_reg)],
6534 reg_names[STACK_POINTER_REGNUM]);
6539 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6540 base_offset = gp_offset;
6543 rtx gp_offset_rtx = GEN_INT (gp_offset);
6545 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6546 bit, so make sure that we don't emit anything that can be
6548 /* ??? There is no DImode ori immediate pattern, so we can only
6549 do this for 32 bit code. */
6550 if (large_int (gp_offset_rtx, GET_MODE (gp_offset_rtx))
6551 && GET_MODE (base_reg_rtx) == SImode)
6553 insn = emit_move_insn (base_reg_rtx,
6554 GEN_INT (gp_offset & BITMASK_UPPER16));
6556 RTX_FRAME_RELATED_P (insn) = 1;
6558 = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6560 & BITMASK_LOWER16)));
6562 RTX_FRAME_RELATED_P (insn) = 1;
6566 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
6568 RTX_FRAME_RELATED_P (insn) = 1;
6571 if (Pmode == DImode)
6572 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6573 stack_pointer_rtx));
6575 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6576 stack_pointer_rtx));
6578 RTX_FRAME_RELATED_P (insn) = 1;
6582 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6583 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6584 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6585 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6586 Pmode == DImode ? "daddu" : "addu",
6587 reg_names[MIPS_TEMP2_REGNUM],
6588 reg_names[MIPS_TEMP2_REGNUM],
6589 reg_names[STACK_POINTER_REGNUM]);
6593 /* When we restore the registers in MIPS16 mode, then if we are
6594 using a frame pointer, and this is not a large frame, the
6595 current stack pointer will be offset by
6596 current_function_outgoing_args_size. Doing it this way lets
6597 us avoid offsetting the frame pointer before copying it into
6598 the stack pointer; there is no instruction to set the stack
6599 pointer to the sum of a register and a constant. */
6602 && frame_pointer_needed
6603 && large_offset <= 32767)
6604 base_offset += current_function_outgoing_args_size;
6606 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6607 if (BITSET_P (mask, regno - GP_REG_FIRST))
6613 = gen_rtx (MEM, gpr_mode,
6614 gen_rtx (PLUS, Pmode, base_reg_rtx,
6615 GEN_INT (gp_offset - base_offset)));
6617 RTX_UNCHANGING_P (mem_rtx) = 1;
6619 /* The mips16 does not have an instruction to load
6620 $31, so we load $7 instead, and work things out
6622 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6623 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6624 /* The mips16 sometimes needs to save $18. */
6625 else if (TARGET_MIPS16
6626 && regno != GP_REG_FIRST + 31
6627 && ! M16_REG_P (regno))
6630 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6633 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6634 emit_move_insn (reg_rtx,
6635 gen_rtx (REG, gpr_mode, regno));
6639 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6643 insn = emit_move_insn (mem_rtx, reg_rtx);
6644 RTX_FRAME_RELATED_P (insn) = 1;
6646 else if (!TARGET_ABICALLS
6647 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6648 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6650 emit_move_insn (reg_rtx, mem_rtx);
6652 && regno != GP_REG_FIRST + 31
6653 && ! M16_REG_P (regno))
6654 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6660 if (store_p || !TARGET_ABICALLS
6661 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6662 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6666 /* The mips16 does not have an instruction to
6667 load $31, so we load $7 instead, and work
6668 things out in the caller. */
6669 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6670 r = GP_REG_FIRST + 7;
6671 /* The mips16 sometimes needs to save $18. */
6673 && regno != GP_REG_FIRST + 31
6674 && ! M16_REG_P (regno))
6677 r = GP_REG_FIRST + 6;
6680 r = GP_REG_FIRST + 3;
6681 fprintf (file, "\tmove\t%s,%s\n",
6682 reg_names[r], reg_names[regno]);
6685 fprintf (file, "\t%s\t%s,",
6687 ? (store_p) ? "sd" : "ld"
6688 : (store_p) ? "sw" : "lw"),
6690 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6691 gp_offset - base_offset);
6692 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6695 && regno != GP_REG_FIRST + 31
6696 && ! M16_REG_P (regno))
6697 fprintf (file, "\tmove\t%s,%s\n",
6698 reg_names[regno], reg_names[r]);
6702 gp_offset -= GET_MODE_SIZE (gpr_mode);
6706 base_reg_rtx = 0, base_offset = 0;
6708 /* Save floating point registers if needed. */
6711 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
6712 int fp_size = fp_inc * UNITS_PER_FPREG;
6714 /* Pick which pointer to use as a base register. */
6715 fp_offset = current_frame_info.fp_sp_offset;
6716 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
6718 if (fp_offset < 0 || end_offset < 0)
6720 ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6721 (long) fp_offset, (long) end_offset);
6723 else if (fp_offset < 32768)
6724 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6726 else if (base_reg_rtx != 0
6727 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6728 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6729 ; /* already set up for gp registers above */
6731 else if (large_reg != 0
6732 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6733 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6735 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6736 base_offset = large_offset;
6739 if (Pmode == DImode)
6740 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6741 stack_pointer_rtx));
6743 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6744 stack_pointer_rtx));
6746 RTX_FRAME_RELATED_P (insn) = 1;
6750 fprintf (file, "\t%s\t%s,%s,%s\n",
6751 Pmode == DImode ? "daddu" : "addu",
6752 reg_names[MIPS_TEMP2_REGNUM],
6753 reg_names[REGNO (large_reg)],
6754 reg_names[STACK_POINTER_REGNUM]);
6759 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6760 base_offset = fp_offset;
6763 rtx fp_offset_rtx = GEN_INT (fp_offset);
6765 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6766 bit, so make sure that we don't emit anything that can be
6768 /* ??? There is no DImode ori immediate pattern, so we can only
6769 do this for 32 bit code. */
6770 if (large_int (fp_offset_rtx, GET_MODE (fp_offset_rtx))
6771 && GET_MODE (base_reg_rtx) == SImode)
6773 insn = emit_move_insn (base_reg_rtx,
6774 GEN_INT (fp_offset & BITMASK_UPPER16));
6776 RTX_FRAME_RELATED_P (insn) = 1;
6777 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6779 & BITMASK_LOWER16)));
6781 RTX_FRAME_RELATED_P (insn) = 1;
6785 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
6787 RTX_FRAME_RELATED_P (insn) = 1;
6791 RTX_FRAME_RELATED_P (insn) = 1;
6792 if (Pmode == DImode)
6793 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6794 stack_pointer_rtx));
6796 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6797 stack_pointer_rtx));
6799 RTX_FRAME_RELATED_P (insn) = 1;
6803 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6804 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6805 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6806 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6807 Pmode == DImode ? "daddu" : "addu",
6808 reg_names[MIPS_TEMP2_REGNUM],
6809 reg_names[MIPS_TEMP2_REGNUM],
6810 reg_names[STACK_POINTER_REGNUM]);
6814 /* This loop must iterate over the same space as its companion in
6815 compute_frame_size. */
6816 for (regno = (FP_REG_LAST - fp_inc + 1);
6817 regno >= FP_REG_FIRST;
6819 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6823 enum machine_mode sz
6824 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6825 rtx reg_rtx = gen_rtx (REG, sz, regno);
6826 rtx mem_rtx = gen_rtx (MEM, sz,
6827 gen_rtx (PLUS, Pmode, base_reg_rtx,
6830 RTX_UNCHANGING_P (mem_rtx) = 1;
6834 insn = emit_move_insn (mem_rtx, reg_rtx);
6835 RTX_FRAME_RELATED_P (insn) = 1;
6838 emit_move_insn (reg_rtx, mem_rtx);
6842 fprintf (file, "\t%s\t%s,",
6843 (TARGET_SINGLE_FLOAT
6844 ? (store_p ? "s.s" : "l.s")
6845 : (store_p ? "s.d" : "l.d")),
6847 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6848 fp_offset - base_offset);
6849 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6852 fp_offset -= fp_size;
6857 /* Set up the stack and frame (if desired) for the function. */
6860 function_prologue (file, size)
6862 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6864 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6867 long tsize = current_frame_info.total_size;
6869 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6871 #ifdef SDB_DEBUGGING_INFO
6872 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6873 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6876 /* In mips16 mode, we may need to generate a 32 bit to handle
6877 floating point arguments. The linker will arrange for any 32 bit
6878 functions to call this stub, which will then jump to the 16 bit
6880 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6881 && current_function_args_info.fp_code != 0)
6882 build_mips16_function_stub (file);
6884 inside_function = 1;
6886 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6887 /* Get the function name the same way that toplev.c does before calling
6888 assemble_start_function. This is needed so that the name used here
6889 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6890 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6892 if (!flag_inhibit_size_directive)
6894 fputs ("\t.ent\t", file);
6895 assemble_name (file, fnname);
6899 assemble_name (file, fnname);
6900 fputs (":\n", file);
6903 if (!flag_inhibit_size_directive)
6905 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6907 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6908 (reg_names[(frame_pointer_needed)
6909 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6910 ((frame_pointer_needed && TARGET_MIPS16)
6911 ? (tsize - current_function_outgoing_args_size)
6913 reg_names[31 + GP_REG_FIRST],
6914 current_frame_info.var_size,
6915 current_frame_info.num_gp,
6916 current_frame_info.num_fp,
6917 current_function_outgoing_args_size,
6918 current_frame_info.extra_size);
6920 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6921 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6922 current_frame_info.mask,
6923 current_frame_info.gp_save_offset,
6924 current_frame_info.fmask,
6925 current_frame_info.fp_save_offset);
6928 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6929 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6932 if (mips_entry && ! mips_can_use_return_insn ())
6934 int save16 = BITSET_P (current_frame_info.mask, 16);
6935 int save17 = BITSET_P (current_frame_info.mask, 17);
6936 int save31 = BITSET_P (current_frame_info.mask, 31);
6940 /* Look through the initial insns to see if any of them store
6941 the function parameters into the incoming parameter storage
6942 area. If they do, we delete the insn, and save the register
6943 using the entry pseudo-instruction instead. We don't try to
6944 look past a label, jump, or call. */
6945 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6947 rtx note, set, src, dest, base, offset;
6950 if (GET_CODE (insn) == CODE_LABEL
6951 || GET_CODE (insn) == JUMP_INSN
6952 || GET_CODE (insn) == CALL_INSN)
6954 if (GET_CODE (insn) != INSN)
6956 set = PATTERN (insn);
6957 if (GET_CODE (set) != SET)
6960 /* An insn storing a function parameter will still have a
6961 REG_EQUIV note on it mentioning the argument pointer. */
6962 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6963 if (note == NULL_RTX)
6965 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6968 src = SET_SRC (set);
6969 if (GET_CODE (src) != REG
6970 || REGNO (src) < GP_REG_FIRST + 4
6971 || REGNO (src) > GP_REG_FIRST + 7)
6974 dest = SET_DEST (set);
6975 if (GET_CODE (dest) != MEM)
6977 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
6979 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
6980 && REGNO (src) < GP_REG_FIRST + 7)
6984 offset = const0_rtx;
6985 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6986 if (GET_CODE (base) != REG
6987 || GET_CODE (offset) != CONST_INT)
6989 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
6990 && (unsigned HOST_WIDE_INT) INTVAL (offset)
6991 == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6993 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
6994 && ((unsigned HOST_WIDE_INT) INTVAL (offset)
6996 + (REGNO (src) - 4) * UNITS_PER_WORD
6997 - current_function_outgoing_args_size)))
7002 /* This insn stores a parameter onto the stack, in the same
7003 location where the entry pseudo-instruction will put it.
7004 Delete the insn, and arrange to tell the entry
7005 instruction to save the register. */
7006 PUT_CODE (insn, NOTE);
7007 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7008 NOTE_SOURCE_FILE (insn) = 0;
7010 hireg = (REGNO (src)
7011 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
7013 if (hireg > savearg)
7017 /* If this is a varargs function, we need to save all the
7018 registers onto the stack anyhow. */
7019 if (current_function_stdarg || current_function_varargs)
7020 savearg = GP_REG_FIRST + 7;
7022 fprintf (file, "\tentry\t");
7025 if (savearg == GP_REG_FIRST + 4)
7026 fprintf (file, "%s", reg_names[savearg]);
7028 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
7029 reg_names[savearg]);
7031 if (save16 || save17)
7034 fprintf (file, ",");
7035 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
7037 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
7041 if (savearg > 0 || save16 || save17)
7042 fprintf (file, ",");
7043 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
7045 fprintf (file, "\n");
7048 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
7050 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7052 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7053 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7056 fprintf (file, "\t%s\t%s,%s,%ld\n",
7057 (Pmode == DImode ? "dsubu" : "subu"),
7058 sp_str, sp_str, tsize);
7059 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
7062 if (dwarf2out_do_frame ())
7063 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
7067 /* Expand the prologue into a bunch of separate insns. */
7070 mips_expand_prologue ()
7073 HOST_WIDE_INT tsize;
7075 int last_arg_is_vararg_marker = 0;
7076 tree fndecl = current_function_decl;
7077 tree fntype = TREE_TYPE (fndecl);
7078 tree fnargs = DECL_ARGUMENTS (fndecl);
7083 CUMULATIVE_ARGS args_so_far;
7084 rtx reg_18_save = NULL_RTX;
7085 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7086 && (! mips_entry || mips_can_use_return_insn ());
7088 /* If struct value address is treated as the first argument, make it so. */
7089 if (aggregate_value_p (DECL_RESULT (fndecl))
7090 && ! current_function_returns_pcc_struct
7091 && struct_value_incoming_rtx == 0)
7093 tree type = build_pointer_type (fntype);
7094 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7096 DECL_ARG_TYPE (function_result_decl) = type;
7097 TREE_CHAIN (function_result_decl) = fnargs;
7098 fnargs = function_result_decl;
7101 /* For arguments passed in registers, find the register number
7102 of the first argument in the variable part of the argument list,
7103 otherwise GP_ARG_LAST+1. Note also if the last argument is
7104 the varargs special argument, and treat it as part of the
7107 This is only needed if store_args_on_stack is true. */
7109 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7110 regno = GP_ARG_FIRST;
7112 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7114 tree passed_type = DECL_ARG_TYPE (cur_arg);
7115 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7118 if (TREE_ADDRESSABLE (passed_type))
7120 passed_type = build_pointer_type (passed_type);
7121 passed_mode = Pmode;
7124 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7126 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7127 next_arg = TREE_CHAIN (cur_arg);
7129 if (entry_parm && store_args_on_stack)
7132 && DECL_NAME (cur_arg)
7133 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7134 "__builtin_va_alist"))
7135 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7138 last_arg_is_vararg_marker = 1;
7145 if (GET_CODE (entry_parm) != REG)
7148 /* passed in a register, so will get homed automatically */
7149 if (GET_MODE (entry_parm) == BLKmode)
7150 words = (int_size_in_bytes (passed_type) + 3) / 4;
7152 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
7154 regno = REGNO (entry_parm) + words - 1;
7159 regno = GP_ARG_LAST+1;
7164 /* In order to pass small structures by value in registers compatibly with
7165 the MIPS compiler, we need to shift the value into the high part of the
7166 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7167 adjustments to be made as the next_arg_reg variable, so we split up the
7168 insns, and emit them separately. */
7170 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7171 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7173 rtvec adjust = XVEC (next_arg_reg, 0);
7174 int num = GET_NUM_ELEM (adjust);
7176 for (i = 0; i < num; i++)
7180 pattern = RTVEC_ELT (adjust, i);
7181 if (GET_CODE (pattern) != SET
7182 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7183 abort_with_insn (pattern, "Insn is not a shift");
7184 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7186 insn = emit_insn (pattern);
7188 /* Global life information isn't valid at this point, so we
7189 can't check whether these shifts are actually used. Mark
7190 them MAYBE_DEAD so that flow2 will remove them, and not
7191 complain about dead code in the prologue. */
7192 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7197 tsize = compute_frame_size (get_frame_size ());
7199 /* If this function is a varargs function, store any registers that
7200 would normally hold arguments ($4 - $7) on the stack. */
7201 if (store_args_on_stack
7202 && ((TYPE_ARG_TYPES (fntype) != 0
7203 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7205 || last_arg_is_vararg_marker))
7207 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7208 rtx ptr = stack_pointer_rtx;
7210 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7211 if (TARGET_ABICALLS)
7214 for (; regno <= GP_ARG_LAST; regno++)
7217 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7218 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7219 gen_rtx (REG, gpr_mode, regno));
7221 offset += GET_MODE_SIZE (gpr_mode);
7225 /* If we are using the entry pseudo instruction, it will
7226 automatically subtract 32 from the stack pointer, so we don't
7227 need to. The entry pseudo instruction is emitted by
7228 function_prologue. */
7229 if (mips_entry && ! mips_can_use_return_insn ())
7231 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7235 /* If we are using a frame pointer with a small stack frame,
7236 we need to initialize it here since it won't be done
7238 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7240 rtx incr = GEN_INT (current_function_outgoing_args_size);
7241 if (Pmode == DImode)
7242 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7246 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7250 else if (Pmode == DImode)
7251 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7252 stack_pointer_rtx));
7254 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7255 stack_pointer_rtx));
7257 RTX_FRAME_RELATED_P (insn) = 1;
7260 /* We may need to save $18, if it is used to call a function
7261 which may return a floating point value. Set up a sequence
7262 of instructions to do so. Later on we emit them at the right
7264 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
7266 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7267 long gp_offset, base_offset;
7269 gp_offset = current_frame_info.gp_sp_offset;
7270 if (BITSET_P (current_frame_info.mask, 16))
7271 gp_offset -= UNITS_PER_WORD;
7272 if (BITSET_P (current_frame_info.mask, 17))
7273 gp_offset -= UNITS_PER_WORD;
7274 if (BITSET_P (current_frame_info.mask, 31))
7275 gp_offset -= UNITS_PER_WORD;
7277 base_offset = tsize;
7281 emit_move_insn (reg_rtx,
7282 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7283 emit_move_insn (gen_rtx (MEM, gpr_mode,
7284 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7288 reg_18_save = gen_sequence ();
7297 if (reg_18_save != NULL_RTX)
7298 emit_insn (reg_18_save);
7304 rtx tsize_rtx = GEN_INT (tsize);
7306 /* If we are doing svr4-abi, sp move is done by
7307 function_prologue. In mips16 mode with a large frame, we
7308 save the registers before adjusting the stack. */
7309 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7310 && (!TARGET_MIPS16 || tsize <= 32767))
7316 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7318 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
7319 bit, so make sure that we don't emit anything that can be
7321 /* ??? There is no DImode ori immediate pattern, so we can only
7322 do this for 32 bit code. */
7323 if (large_int (tsize_rtx, GET_MODE (tsize_rtx))
7324 && GET_MODE (tmp_rtx) == SImode)
7326 insn = emit_move_insn (tmp_rtx,
7327 GEN_INT (tsize & BITMASK_UPPER16));
7328 RTX_FRAME_RELATED_P (insn) = 1;
7329 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
7331 & BITMASK_LOWER16)));
7332 RTX_FRAME_RELATED_P (insn) = 1;
7336 insn = emit_move_insn (tmp_rtx, tsize_rtx);
7337 RTX_FRAME_RELATED_P (insn) = 1;
7340 tsize_rtx = tmp_rtx;
7343 if (Pmode == DImode)
7344 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7347 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7350 RTX_FRAME_RELATED_P (insn) = 1;
7354 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
7355 else if (reg_18_save != NULL_RTX)
7356 emit_insn (reg_18_save);
7358 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7364 if (!frame_pointer_needed)
7367 reg_rtx = gen_rtx (REG, Pmode, 3);
7368 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7369 emit_move_insn (reg_rtx, tsize_rtx);
7370 if (Pmode == DImode)
7371 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7372 hard_frame_pointer_rtx,
7375 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7376 hard_frame_pointer_rtx,
7378 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7381 if (frame_pointer_needed)
7385 /* On the mips16, we encourage the use of unextended
7386 instructions when using the frame pointer by pointing the
7387 frame pointer ahead of the argument space allocated on
7389 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7393 /* In this case, we have already copied the stack
7394 pointer into the frame pointer, above. We need only
7395 adjust for the outgoing argument size. */
7396 if (current_function_outgoing_args_size != 0)
7398 rtx incr = GEN_INT (current_function_outgoing_args_size);
7399 if (Pmode == DImode)
7400 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7401 hard_frame_pointer_rtx,
7404 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7405 hard_frame_pointer_rtx,
7409 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7411 rtx incr = GEN_INT (current_function_outgoing_args_size);
7412 if (Pmode == DImode)
7413 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7417 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7421 else if (Pmode == DImode)
7422 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7423 stack_pointer_rtx));
7425 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7426 stack_pointer_rtx));
7429 RTX_FRAME_RELATED_P (insn) = 1;
7432 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7433 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7434 gen_rtx_REG (DImode, 25)));
7437 /* If we are profiling, make sure no instructions are scheduled before
7438 the call to mcount. */
7440 if (profile_flag || profile_block_flag)
7441 emit_insn (gen_blockage ());
7444 /* Do any necessary cleanup after a function to restore stack, frame,
7447 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7448 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7451 function_epilogue (file, size)
7452 FILE *file ATTRIBUTE_UNUSED;
7453 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7457 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7458 /* Get the function name the same way that toplev.c does before calling
7459 assemble_start_function. This is needed so that the name used here
7460 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7461 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7463 if (!flag_inhibit_size_directive)
7465 fputs ("\t.end\t", file);
7466 assemble_name (file, fnname);
7473 int num_gp_regs = current_frame_info.gp_reg_size / 4;
7474 int num_fp_regs = current_frame_info.fp_reg_size / 8;
7475 int num_regs = num_gp_regs + num_fp_regs;
7476 const char *name = fnname;
7481 dslots_load_total += num_regs;
7484 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7485 name, frame_pointer_needed ? 'y' : 'n',
7486 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7487 current_function_calls_alloca ? 'y' : 'n',
7488 current_function_calls_setjmp ? 'y' : 'n',
7489 current_frame_info.total_size,
7490 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7491 dslots_load_total, dslots_load_filled,
7492 dslots_jump_total, dslots_jump_filled,
7493 num_refs[0], num_refs[1], num_refs[2]);
7495 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7498 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7499 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7502 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7505 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7506 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7509 fputc ('\n', stderr);
7512 /* Reset state info for each function. */
7513 inside_function = 0;
7514 ignore_line_number = 0;
7515 dslots_load_total = 0;
7516 dslots_jump_total = 0;
7517 dslots_load_filled = 0;
7518 dslots_jump_filled = 0;
7524 current_frame_info = zero_frame_info;
7526 while (string_constants != NULL)
7528 struct string_constant *next;
7530 next = string_constants->next;
7531 free (string_constants);
7532 string_constants = next;
7535 /* Restore the output file if optimizing the GP (optimizing the GP causes
7536 the text to be diverted to a tempfile, so that data decls come before
7537 references to the data). */
7539 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
7540 asm_out_file = asm_out_data_file;
7543 /* Expand the epilogue into a bunch of separate insns. */
7546 mips_expand_epilogue ()
7548 HOST_WIDE_INT tsize = current_frame_info.total_size;
7549 rtx tsize_rtx = GEN_INT (tsize);
7550 rtx tmp_rtx = (rtx)0;
7552 if (mips_can_use_return_insn ())
7554 emit_insn (gen_return ());
7558 if (mips_entry && ! mips_can_use_return_insn ())
7561 if (tsize > 32767 && ! TARGET_MIPS16)
7563 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7564 emit_move_insn (tmp_rtx, tsize_rtx);
7565 tsize_rtx = tmp_rtx;
7570 long orig_tsize = tsize;
7572 if (frame_pointer_needed)
7574 emit_insn (gen_blockage ());
7576 /* On the mips16, the frame pointer is offset from the stack
7577 pointer by current_function_outgoing_args_size. We
7578 account for that by changing tsize. Note that this can
7579 actually make tsize negative. */
7582 tsize -= current_function_outgoing_args_size;
7584 /* If we have a large frame, it's easier to add to $17
7585 than to $sp, since the mips16 has no instruction to
7586 add a register to $sp. */
7587 if (orig_tsize > 32767)
7589 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7591 emit_move_insn (g6_rtx, GEN_INT (tsize));
7592 if (Pmode == DImode)
7593 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7594 hard_frame_pointer_rtx,
7597 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7598 hard_frame_pointer_rtx,
7603 if (tsize && tsize != orig_tsize)
7604 tsize_rtx = GEN_INT (tsize);
7607 if (Pmode == DImode)
7608 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7610 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7613 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7614 are going to restore it, then we must emit a blockage insn to
7615 prevent the scheduler from moving the restore out of the epilogue. */
7616 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7617 && (current_frame_info.mask
7618 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7619 emit_insn (gen_blockage ());
7621 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
7623 /* In mips16 mode with a large frame, we adjust the stack
7624 pointer before restoring the registers. In this case, we
7625 should always be using a frame pointer, so everything should
7626 have been handled above. */
7627 if (tsize > 32767 && TARGET_MIPS16)
7630 if (current_function_calls_eh_return)
7632 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
7633 if (Pmode == DImode)
7634 emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
7636 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
7640 emit_insn (gen_blockage ());
7642 if (tsize != 0 || current_function_calls_eh_return)
7644 if (Pmode == DImode)
7645 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7648 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7653 /* The mips16 loads the return address into $7, not $31. */
7654 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7655 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7656 GP_REG_FIRST + 7)));
7658 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7659 GP_REG_FIRST + 31)));
7662 /* Return nonzero if this function is known to have a null epilogue.
7663 This allows the optimizer to omit jumps to jumps if no stack
7667 mips_can_use_return_insn ()
7669 if (! reload_completed)
7672 if (regs_ever_live[31] || profile_flag)
7675 /* In mips16 mode, a function which returns a floating point value
7676 needs to arrange to copy the return value into the floating point
7679 && mips16_hard_float
7680 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7681 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7683 && (! TARGET_SINGLE_FLOAT
7684 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7688 if (current_frame_info.initialized)
7689 return current_frame_info.total_size == 0;
7691 return compute_frame_size (get_frame_size ()) == 0;
7694 /* Returns non-zero if X contains a SYMBOL_REF. */
7697 symbolic_expression_p (x)
7700 if (GET_CODE (x) == SYMBOL_REF)
7703 if (GET_CODE (x) == CONST)
7704 return symbolic_expression_p (XEXP (x, 0));
7706 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7707 return symbolic_expression_p (XEXP (x, 0));
7709 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7710 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7711 return (symbolic_expression_p (XEXP (x, 0))
7712 || symbolic_expression_p (XEXP (x, 1)));
7717 /* Choose the section to use for the constant rtx expression X that has
7721 mips_select_rtx_section (mode, x)
7722 enum machine_mode mode;
7723 rtx x ATTRIBUTE_UNUSED;
7727 /* In mips16 mode, the constant table always goes in the same section
7728 as the function, so that constants can be loaded using PC relative
7730 function_section (current_function_decl);
7732 else if (TARGET_EMBEDDED_DATA)
7734 /* For embedded applications, always put constants in read-only data,
7735 in order to reduce RAM usage. */
7736 READONLY_DATA_SECTION ();
7740 /* For hosted applications, always put constants in small data if
7741 possible, as this gives the best performance. */
7743 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7744 && mips_section_threshold > 0)
7745 SMALL_DATA_SECTION ();
7746 else if (flag_pic && symbolic_expression_p (x))
7747 /* Any expression involving a SYMBOL_REF might need a run-time
7748 relocation. (The symbol might be defined in a shared
7749 library loaded at an unexpected base address.) So, we must
7750 put such expressions in the data segment (which is
7751 writable), rather than the text segment (which is
7755 READONLY_DATA_SECTION ();
7759 /* Choose the section to use for DECL. RELOC is true if its value contains
7760 any relocatable expression.
7762 Some of the logic used here needs to be replicated in
7763 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7764 are done correctly. Specifically, at least all symbols assigned
7765 here to rom (.text and/or .rodata) must not be referenced via
7766 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7768 If you need to make a change here, you probably should check
7769 ENCODE_SECTION_INFO to see if it needs a similar change. */
7772 mips_select_section (decl, reloc)
7776 int size = int_size_in_bytes (TREE_TYPE (decl));
7778 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7779 && TREE_CODE (decl) == STRING_CST
7780 && !flag_writable_strings)
7781 /* For embedded position independent code, put constant strings in the
7782 text section, because the data section is limited to 64K in size.
7783 For mips16 code, put strings in the text section so that a PC
7784 relative load instruction can be used to get their address. */
7786 else if (TARGET_EMBEDDED_DATA)
7788 /* For embedded applications, always put an object in read-only data
7789 if possible, in order to reduce RAM usage. */
7791 if (((TREE_CODE (decl) == VAR_DECL
7792 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7793 && DECL_INITIAL (decl)
7794 && (DECL_INITIAL (decl) == error_mark_node
7795 || TREE_CONSTANT (DECL_INITIAL (decl))))
7796 /* Deal with calls from output_constant_def_contents. */
7797 || (TREE_CODE (decl) != VAR_DECL
7798 && (TREE_CODE (decl) != STRING_CST
7799 || !flag_writable_strings)))
7800 && ! (flag_pic && reloc))
7801 READONLY_DATA_SECTION ();
7802 else if (size > 0 && size <= mips_section_threshold)
7803 SMALL_DATA_SECTION ();
7809 /* For hosted applications, always put an object in small data if
7810 possible, as this gives the best performance. */
7812 if (size > 0 && size <= mips_section_threshold)
7813 SMALL_DATA_SECTION ();
7814 else if (((TREE_CODE (decl) == VAR_DECL
7815 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7816 && DECL_INITIAL (decl)
7817 && (DECL_INITIAL (decl) == error_mark_node
7818 || TREE_CONSTANT (DECL_INITIAL (decl))))
7819 /* Deal with calls from output_constant_def_contents. */
7820 || (TREE_CODE (decl) != VAR_DECL
7821 && (TREE_CODE (decl) != STRING_CST
7822 || !flag_writable_strings)))
7823 && ! (flag_pic && reloc))
7824 READONLY_DATA_SECTION ();
7830 #ifdef MIPS_ABI_DEFAULT
7832 /* Support functions for the 64 bit ABI. */
7834 /* Return register to use for a function return value with VALTYPE for function
7838 mips_function_value (valtype, func)
7840 tree func ATTRIBUTE_UNUSED;
7842 int reg = GP_RETURN;
7843 enum machine_mode mode = TYPE_MODE (valtype);
7844 enum mode_class mclass = GET_MODE_CLASS (mode);
7845 int unsignedp = TREE_UNSIGNED (valtype);
7847 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7848 just as PROMOTE_MODE does. */
7849 mode = promote_mode (valtype, mode, &unsignedp, 1);
7851 /* ??? How should we return complex float? */
7852 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
7854 if (TARGET_SINGLE_FLOAT
7855 && (mclass == MODE_FLOAT
7856 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7862 else if (TREE_CODE (valtype) == RECORD_TYPE
7863 && mips_abi != ABI_32
7864 && mips_abi != ABI_O64
7865 && mips_abi != ABI_EABI)
7867 /* A struct with only one or two floating point fields is returned in
7868 the floating point registers. */
7869 tree field, fields[2];
7872 for (i = 0, field = TYPE_FIELDS (valtype); field;
7873 field = TREE_CHAIN (field))
7875 if (TREE_CODE (field) != FIELD_DECL)
7878 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7881 fields[i++] = field;
7884 /* Must check i, so that we reject structures with no elements. */
7889 /* The structure has DImode, but we don't allow DImode values
7890 in FP registers, so we use a PARALLEL even though it isn't
7891 strictly necessary. */
7892 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7894 return gen_rtx_PARALLEL
7897 gen_rtx_EXPR_LIST (VOIDmode,
7898 gen_rtx_REG (field_mode,
7905 enum machine_mode first_mode
7906 = TYPE_MODE (TREE_TYPE (fields[0]));
7907 enum machine_mode second_mode
7908 = TYPE_MODE (TREE_TYPE (fields[1]));
7909 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
7910 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
7912 return gen_rtx_PARALLEL
7915 gen_rtx_EXPR_LIST (VOIDmode,
7916 gen_rtx_REG (first_mode,
7918 GEN_INT (first_offset)),
7919 gen_rtx_EXPR_LIST (VOIDmode,
7920 gen_rtx_REG (second_mode,
7922 GEN_INT (second_offset))));
7927 return gen_rtx_REG (mode, reg);
7931 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7932 nonzero when an argument must be passed by reference. */
7935 function_arg_pass_by_reference (cum, mode, type, named)
7936 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
7937 enum machine_mode mode;
7939 int named ATTRIBUTE_UNUSED;
7943 /* We must pass by reference if we would be both passing in registers
7944 and the stack. This is because any subsequent partial arg would be
7945 handled incorrectly in this case.
7947 ??? This is really a kludge. We should either fix GCC so that such
7948 a situation causes an abort and then do something in the MIPS port
7949 to prevent it, or add code to function.c to properly handle the case. */
7950 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
7951 here hopefully is not relevant to mips_va_arg. */
7952 if (cum && MUST_PASS_IN_STACK (mode, type))
7954 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
7955 get double copies of any offsets generated for small structs
7956 passed in registers. */
7957 CUMULATIVE_ARGS temp;
7959 if (FUNCTION_ARG (temp, mode, type, named) != 0)
7963 /* Otherwise, we only do this if EABI is selected. */
7964 if (mips_abi != ABI_EABI)
7967 /* ??? How should SCmode be handled? */
7968 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7971 size = int_size_in_bytes (type);
7972 return size == -1 || size > UNITS_PER_WORD;
7975 /* This function returns the register class required for a secondary
7976 register when copying between one of the registers in CLASS, and X,
7977 using MODE. If IN_P is nonzero, the copy is going from X to the
7978 register, otherwise the register is the source. A return value of
7979 NO_REGS means that no secondary register is required. */
7982 mips_secondary_reload_class (class, mode, x, in_p)
7983 enum reg_class class;
7984 enum machine_mode mode;
7988 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7992 if (GET_CODE (x) == SIGN_EXTEND)
7998 /* We may be called with reg_renumber NULL from regclass.
7999 ??? This is probably a bug. */
8001 regno = true_regnum (x);
8004 while (GET_CODE (x) == SUBREG)
8006 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
8007 GET_MODE (SUBREG_REG (x)),
8013 if (GET_CODE (x) == REG)
8014 regno = REGNO (x) + off;
8018 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
8019 regno = true_regnum (x);
8021 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8023 /* We always require a general register when copying anything to
8024 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8025 to a general register, or when copying from register 0. */
8026 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
8029 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8030 ? NO_REGS : gr_regs);
8031 else if (regno == HILO_REGNUM)
8034 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8035 ? NO_REGS : gr_regs);
8037 /* Copying from HI or LO to anywhere other than a general register
8038 requires a general register. */
8039 if (class == HI_REG || class == LO_REG || class == MD_REGS)
8041 if (TARGET_MIPS16 && in_p)
8043 /* We can't really copy to HI or LO at all in mips16 mode. */
8046 return gp_reg_p ? NO_REGS : gr_regs;
8048 if (MD_REG_P (regno))
8050 if (TARGET_MIPS16 && ! in_p)
8052 /* We can't really copy to HI or LO at all in mips16 mode. */
8055 return class == gr_regs ? NO_REGS : gr_regs;
8058 /* We can only copy a value to a condition code register from a
8059 floating point register, and even then we require a scratch
8060 floating point register. We can only copy a value out of a
8061 condition code register into a general register. */
8062 if (class == ST_REGS)
8066 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8068 if (ST_REG_P (regno))
8072 return class == GR_REGS ? NO_REGS : GR_REGS;
8075 /* In mips16 mode, going between memory and anything but M16_REGS
8076 requires an M16_REG. */
8079 if (class != M16_REGS && class != M16_NA_REGS)
8087 /* The stack pointer isn't a valid operand to an add instruction,
8088 so we need to load it into M16_REGS first. This can happen as
8089 a result of register elimination and form_sum converting
8090 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8091 need an extra register if the dest is the same as the other
8092 register. In that case, we can't fix the problem by loading SP
8093 into the dest first. */
8094 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8095 && GET_CODE (XEXP (x, 1)) == REG
8096 && (XEXP (x, 0) == stack_pointer_rtx
8097 || XEXP (x, 1) == stack_pointer_rtx))
8098 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8100 if (class == M16_REGS || class == M16_NA_REGS)
8109 /* For each mips16 function which refers to GP relative symbols, we
8110 use a pseudo register, initialized at the start of the function, to
8111 hold the $gp value. */
8114 mips16_gp_pseudo_reg ()
8116 if (mips16_gp_pseudo_rtx == NULL_RTX)
8121 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8122 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
8124 /* We want to initialize this to a value which gcc will believe
8126 const_gp = gen_rtx (CONST, Pmode,
8127 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8130 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
8131 insn = gen_sequence ();
8134 push_topmost_sequence ();
8135 /* We need to emit the initialization after the FUNCTION_BEG
8136 note, so that it will be integrated. */
8137 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8138 if (GET_CODE (scan) == NOTE
8139 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8141 if (scan == NULL_RTX)
8142 scan = get_insns ();
8143 insn = emit_insn_after (insn, scan);
8144 pop_topmost_sequence ();
8147 return mips16_gp_pseudo_rtx;
8150 /* Return an RTX which represents the signed 16 bit offset from the
8151 $gp register for the given symbol. This is only used on the
8155 mips16_gp_offset (sym)
8160 if (GET_CODE (sym) != SYMBOL_REF
8161 || ! SYMBOL_REF_FLAG (sym))
8164 /* We use a special identifier to represent the value of the gp
8166 gp = get_identifier ("__mips16_gp_value");
8168 return gen_rtx (CONST, Pmode,
8169 gen_rtx (MINUS, Pmode, sym,
8170 gen_rtx (SYMBOL_REF, Pmode,
8171 IDENTIFIER_POINTER (gp))));
8174 /* Return nonzero if the given RTX represents a signed 16 bit offset
8175 from the $gp register. */
8178 mips16_gp_offset_p (x)
8181 if (GET_CODE (x) == CONST)
8184 /* It's OK to add a small integer value to a gp offset. */
8185 if (GET_CODE (x) == PLUS)
8187 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8188 && SMALL_INT (XEXP (x, 1)))
8189 return mips16_gp_offset_p (XEXP (x, 0));
8190 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8191 && SMALL_INT (XEXP (x, 0)))
8192 return mips16_gp_offset_p (XEXP (x, 1));
8196 /* Make sure it is in the form SYM - __mips16_gp_value. */
8197 return (GET_CODE (x) == MINUS
8198 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8199 && SYMBOL_REF_FLAG (XEXP (x, 0))
8200 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8201 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8204 /* Output a GP offset. We don't want to print the subtraction of
8205 __mips16_gp_value; it is implicitly represented by the %gprel which
8206 should have been printed by the caller. */
8209 mips16_output_gp_offset (file, x)
8213 if (GET_CODE (x) == CONST)
8216 if (GET_CODE (x) == PLUS)
8218 mips16_output_gp_offset (file, XEXP (x, 0));
8220 mips16_output_gp_offset (file, XEXP (x, 1));
8224 if (GET_CODE (x) == MINUS
8225 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8226 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8228 mips16_output_gp_offset (file, XEXP (x, 0));
8232 output_addr_const (file, x);
8235 /* Return nonzero if a constant should not be output until after the
8236 function. This is true of most string constants, so that we can
8237 use a more efficient PC relative reference. However, a static
8238 inline function may never call assemble_function_end to write out
8239 the constant pool, so don't try to postpone the constant in that
8242 ??? It's really a bug that a static inline function can put stuff
8243 in the constant pool even if the function itself is not output.
8245 We record which string constants we've seen, so that we know which
8246 ones might use the more efficient reference. */
8249 mips16_constant_after_function_p (x)
8252 if (TREE_CODE (x) == STRING_CST
8253 && ! flag_writable_strings
8254 && current_function_decl != 0
8255 && ! DECL_DEFER_OUTPUT (current_function_decl)
8256 && ! (DECL_INLINE (current_function_decl)
8257 && ((! TREE_PUBLIC (current_function_decl)
8258 && ! TREE_ADDRESSABLE (current_function_decl)
8259 && ! flag_keep_inline_functions)
8260 || DECL_EXTERNAL (current_function_decl))))
8262 struct string_constant *n;
8264 n = (struct string_constant *) xmalloc (sizeof *n);
8265 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8266 n->next = string_constants;
8267 string_constants = n;
8275 /* Validate a constant for the mips16. This rejects general symbolic
8276 addresses, which must be loaded from memory. If ADDR is nonzero,
8277 this should reject anything which is not a legal address. If
8278 ADDEND is nonzero, this is being added to something else. */
8281 mips16_constant (x, mode, addr, addend)
8283 enum machine_mode mode;
8287 while (GET_CODE (x) == CONST)
8290 switch (GET_CODE (x))
8296 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8297 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8300 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8302 if (CONSTANT_POOL_ADDRESS_P (x))
8305 /* If we aren't looking for a memory address, we can accept a GP
8306 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8307 knows how to handle this. We can always accept a string
8308 constant, which is the other case in which SYMBOL_REF_FLAG
8312 && SYMBOL_REF_FLAG (x)
8313 && mode == (enum machine_mode) Pmode)
8316 /* We can accept a string constant, which will have
8317 SYMBOL_REF_FLAG set but must be recognized by name to
8318 distinguish from a GP accessible symbol. The name of a
8319 string constant will have been generated by
8320 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8321 if (SYMBOL_REF_FLAG (x))
8323 const char *name = XSTR (x, 0);
8325 return (name[0] == '*'
8326 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8327 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8333 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8338 if (addr && ! addend)
8340 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8343 /* We need to treat $gp as a legitimate constant, because
8344 mips16_gp_pseudo_reg assumes that. */
8345 return REGNO (x) == GP_REG_FIRST + 28;
8349 /* Write out code to move floating point arguments in or out of
8350 general registers. Output the instructions to FILE. FP_CODE is
8351 the code describing which arguments are present (see the comment at
8352 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8353 we are copying from the floating point registers. */
8356 mips16_fp_args (file, fp_code, from_fp_p)
8365 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8366 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8373 gparg = GP_ARG_FIRST;
8374 fparg = FP_ARG_FIRST;
8375 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8379 if ((fparg & 1) != 0)
8381 fprintf (file, "\t%s\t%s,%s\n", s,
8382 reg_names[gparg], reg_names[fparg]);
8384 else if ((f & 3) == 2)
8387 fprintf (file, "\td%s\t%s,%s\n", s,
8388 reg_names[gparg], reg_names[fparg]);
8391 if ((fparg & 1) != 0)
8393 if (TARGET_BIG_ENDIAN)
8394 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8395 reg_names[gparg], reg_names[fparg + 1], s,
8396 reg_names[gparg + 1], reg_names[fparg]);
8398 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8399 reg_names[gparg], reg_names[fparg], s,
8400 reg_names[gparg + 1], reg_names[fparg + 1]);
8413 /* Build a mips16 function stub. This is used for functions which
8414 take aruments in the floating point registers. It is 32 bit code
8415 that moves the floating point args into the general registers, and
8416 then jumps to the 16 bit code. */
8419 build_mips16_function_stub (file)
8423 char *secname, *stubname;
8424 tree stubid, stubdecl;
8428 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8429 secname = (char *) alloca (strlen (fnname) + 20);
8430 sprintf (secname, ".mips16.fn.%s", fnname);
8431 stubname = (char *) alloca (strlen (fnname) + 20);
8432 sprintf (stubname, "__fn_stub_%s", fnname);
8433 stubid = get_identifier (stubname);
8434 stubdecl = build_decl (FUNCTION_DECL, stubid,
8435 build_function_type (void_type_node, NULL_TREE));
8436 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8438 fprintf (file, "\t# Stub function for %s (", current_function_name);
8440 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8442 fprintf (file, "%s%s",
8443 need_comma ? ", " : "",
8444 (f & 3) == 1 ? "float" : "double");
8447 fprintf (file, ")\n");
8449 fprintf (file, "\t.set\tnomips16\n");
8450 function_section (stubdecl);
8451 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8453 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8454 within a .ent, and we can not emit another .ent. */
8455 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8456 fputs ("\t.ent\t", file);
8457 assemble_name (file, stubname);
8461 assemble_name (file, stubname);
8462 fputs (":\n", file);
8464 /* We don't want the assembler to insert any nops here. */
8465 fprintf (file, "\t.set\tnoreorder\n");
8467 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8469 fprintf (asm_out_file, "\t.set\tnoat\n");
8470 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8471 assemble_name (file, fnname);
8472 fprintf (file, "\n");
8473 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8474 fprintf (asm_out_file, "\t.set\tat\n");
8476 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8477 with one of the mfc1 instructions, because the result is not
8478 available for one instruction, so if the very first instruction
8479 in the function refers to the register, it will see the wrong
8481 fprintf (file, "\tnop\n");
8483 fprintf (file, "\t.set\treorder\n");
8485 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8486 fputs ("\t.end\t", file);
8487 assemble_name (file, stubname);
8491 fprintf (file, "\t.set\tmips16\n");
8493 function_section (current_function_decl);
8496 /* We keep a list of functions for which we have already built stubs
8497 in build_mips16_call_stub. */
8501 struct mips16_stub *next;
8506 static struct mips16_stub *mips16_stubs;
8508 /* Build a call stub for a mips16 call. A stub is needed if we are
8509 passing any floating point values which should go into the floating
8510 point registers. If we are, and the call turns out to be to a 32
8511 bit function, the stub will be used to move the values into the
8512 floating point registers before calling the 32 bit function. The
8513 linker will magically adjust the function call to either the 16 bit
8514 function or the 32 bit stub, depending upon where the function call
8515 is actually defined.
8517 Similarly, we need a stub if the return value might come back in a
8518 floating point register.
8520 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8521 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8522 is the code built by function_arg. This function returns a nonzero
8523 value if it builds the call instruction itself. */
8526 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8535 char *secname, *stubname;
8536 struct mips16_stub *l;
8537 tree stubid, stubdecl;
8541 /* We don't need to do anything if we aren't in mips16 mode, or if
8542 we were invoked with the -msoft-float option. */
8543 if (! TARGET_MIPS16 || ! mips16_hard_float)
8546 /* Figure out whether the value might come back in a floating point
8548 fpret = (retval != 0
8549 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8550 && (! TARGET_SINGLE_FLOAT
8551 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8553 /* We don't need to do anything if there were no floating point
8554 arguments and the value will not be returned in a floating point
8556 if (fp_code == 0 && ! fpret)
8559 if (GET_CODE (fnmem) != MEM)
8561 fn = XEXP (fnmem, 0);
8563 /* We don't need to do anything if this is a call to a special
8564 mips16 support function. */
8565 if (GET_CODE (fn) == SYMBOL_REF
8566 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8569 /* This code will only work for o32 and o64 abis. The other ABI's
8570 require more sophisticated support. */
8571 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8574 /* We can only handle SFmode and DFmode floating point return
8576 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8579 /* If we're calling via a function pointer, then we must always call
8580 via a stub. There are magic stubs provided in libgcc.a for each
8581 of the required cases. Each of them expects the function address
8582 to arrive in register $2. */
8584 if (GET_CODE (fn) != SYMBOL_REF)
8588 rtx stub_fn, stub_mem, insn;
8590 /* ??? If this code is modified to support other ABI's, we need
8591 to handle PARALLEL return values here. */
8593 sprintf (buf, "__mips16_call_stub_%s%d",
8595 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8598 id = get_identifier (buf);
8599 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8600 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8602 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8604 if (retval == NULL_RTX)
8605 insn = gen_call_internal0 (stub_mem, arg_size,
8606 gen_rtx (REG, SImode,
8607 GP_REG_FIRST + 31));
8609 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8610 gen_rtx (REG, SImode,
8611 GP_REG_FIRST + 31));
8612 insn = emit_call_insn (insn);
8614 /* Put the register usage information on the CALL. */
8615 if (GET_CODE (insn) != CALL_INSN)
8617 CALL_INSN_FUNCTION_USAGE (insn) =
8618 gen_rtx (EXPR_LIST, VOIDmode,
8619 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8620 CALL_INSN_FUNCTION_USAGE (insn));
8622 /* If we are handling a floating point return value, we need to
8623 save $18 in the function prologue. Putting a note on the
8624 call will mean that regs_ever_live[$18] will be true if the
8625 call is not eliminated, and we can check that in the prologue
8628 CALL_INSN_FUNCTION_USAGE (insn) =
8629 gen_rtx (EXPR_LIST, VOIDmode,
8630 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8631 CALL_INSN_FUNCTION_USAGE (insn));
8633 /* Return 1 to tell the caller that we've generated the call
8638 /* We know the function we are going to call. If we have already
8639 built a stub, we don't need to do anything further. */
8641 fnname = XSTR (fn, 0);
8642 for (l = mips16_stubs; l != NULL; l = l->next)
8643 if (strcmp (l->name, fnname) == 0)
8648 /* Build a special purpose stub. When the linker sees a
8649 function call in mips16 code, it will check where the target
8650 is defined. If the target is a 32 bit call, the linker will
8651 search for the section defined here. It can tell which
8652 symbol this section is associated with by looking at the
8653 relocation information (the name is unreliable, since this
8654 might be a static function). If such a section is found, the
8655 linker will redirect the call to the start of the magic
8658 If the function does not return a floating point value, the
8659 special stub section is named
8662 If the function does return a floating point value, the stub
8664 .mips16.call.fp.FNNAME
8667 secname = (char *) alloca (strlen (fnname) + 40);
8668 sprintf (secname, ".mips16.call.%s%s",
8671 stubname = (char *) alloca (strlen (fnname) + 20);
8672 sprintf (stubname, "__call_stub_%s%s",
8675 stubid = get_identifier (stubname);
8676 stubdecl = build_decl (FUNCTION_DECL, stubid,
8677 build_function_type (void_type_node, NULL_TREE));
8678 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8680 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8682 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8686 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8688 fprintf (asm_out_file, "%s%s",
8689 need_comma ? ", " : "",
8690 (f & 3) == 1 ? "float" : "double");
8693 fprintf (asm_out_file, ")\n");
8695 fprintf (asm_out_file, "\t.set\tnomips16\n");
8696 assemble_start_function (stubdecl, stubname);
8698 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8699 fputs ("\t.ent\t", asm_out_file);
8700 assemble_name (asm_out_file, stubname);
8701 fputs ("\n", asm_out_file);
8703 assemble_name (asm_out_file, stubname);
8704 fputs (":\n", asm_out_file);
8707 /* We build the stub code by hand. That's the only way we can
8708 do it, since we can't generate 32 bit code during a 16 bit
8711 /* We don't want the assembler to insert any nops here. */
8712 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8714 mips16_fp_args (asm_out_file, fp_code, 0);
8718 fprintf (asm_out_file, "\t.set\tnoat\n");
8719 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8721 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8722 fprintf (asm_out_file, "\t.set\tat\n");
8723 /* Unfortunately, we can't fill the jump delay slot. We
8724 can't fill with one of the mtc1 instructions, because the
8725 result is not available for one instruction, so if the
8726 very first instruction in the function refers to the
8727 register, it will see the wrong value. */
8728 fprintf (asm_out_file, "\tnop\n");
8732 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8733 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8734 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8735 /* As above, we can't fill the delay slot. */
8736 fprintf (asm_out_file, "\tnop\n");
8737 if (GET_MODE (retval) == SFmode)
8738 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8739 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8742 if (TARGET_BIG_ENDIAN)
8744 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8745 reg_names[GP_REG_FIRST + 2],
8746 reg_names[FP_REG_FIRST + 1]);
8747 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8748 reg_names[GP_REG_FIRST + 3],
8749 reg_names[FP_REG_FIRST + 0]);
8753 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8754 reg_names[GP_REG_FIRST + 2],
8755 reg_names[FP_REG_FIRST + 0]);
8756 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8757 reg_names[GP_REG_FIRST + 3],
8758 reg_names[FP_REG_FIRST + 1]);
8761 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8762 /* As above, we can't fill the delay slot. */
8763 fprintf (asm_out_file, "\tnop\n");
8766 fprintf (asm_out_file, "\t.set\treorder\n");
8768 #ifdef ASM_DECLARE_FUNCTION_SIZE
8769 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8772 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8773 fputs ("\t.end\t", asm_out_file);
8774 assemble_name (asm_out_file, stubname);
8775 fputs ("\n", asm_out_file);
8778 fprintf (asm_out_file, "\t.set\tmips16\n");
8780 /* Record this stub. */
8781 l = (struct mips16_stub *) xmalloc (sizeof *l);
8782 l->name = xstrdup (fnname);
8784 l->next = mips16_stubs;
8788 /* If we expect a floating point return value, but we've built a
8789 stub which does not expect one, then we're in trouble. We can't
8790 use the existing stub, because it won't handle the floating point
8791 value. We can't build a new stub, because the linker won't know
8792 which stub to use for the various calls in this object file.
8793 Fortunately, this case is illegal, since it means that a function
8794 was declared in two different ways in a single compilation. */
8795 if (fpret && ! l->fpret)
8796 error ("can not handle inconsistent calls to `%s'", fnname);
8798 /* If we are calling a stub which handles a floating point return
8799 value, we need to arrange to save $18 in the prologue. We do
8800 this by marking the function call as using the register. The
8801 prologue will later see that it is used, and emit code to save
8808 if (retval == NULL_RTX)
8809 insn = gen_call_internal0 (fnmem, arg_size,
8810 gen_rtx (REG, SImode,
8811 GP_REG_FIRST + 31));
8813 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8814 gen_rtx (REG, SImode,
8815 GP_REG_FIRST + 31));
8816 insn = emit_call_insn (insn);
8818 if (GET_CODE (insn) != CALL_INSN)
8821 CALL_INSN_FUNCTION_USAGE (insn) =
8822 gen_rtx (EXPR_LIST, VOIDmode,
8823 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8824 CALL_INSN_FUNCTION_USAGE (insn));
8826 /* Return 1 to tell the caller that we've generated the call
8831 /* Return 0 to let the caller generate the call insn. */
8835 /* This function looks through the code for a function, and tries to
8836 optimize the usage of the $gp register. We arrange to copy $gp
8837 into a pseudo-register, and then let gcc's normal reload handling
8838 deal with the pseudo-register. Unfortunately, if reload choose to
8839 put the pseudo-register into a call-clobbered register, it will
8840 emit saves and restores for that register around any function
8841 calls. We don't need the saves, and it's faster to copy $gp than
8842 to do an actual restore. ??? This still means that we waste a
8845 This is an optimization, and the code which gcc has actually
8846 generated is correct, so we do not need to catch all cases. */
8849 mips16_optimize_gp (first)
8852 rtx gpcopy, slot, insn;
8854 /* Look through the instructions. Set GPCOPY to the register which
8855 holds a copy of $gp. Set SLOT to the stack slot where it is
8856 saved. If we find an instruction which sets GPCOPY to anything
8857 other than $gp or SLOT, then we can't use it. If we find an
8858 instruction which sets SLOT to anything other than GPCOPY, we
8863 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8867 if (! INSN_P (insn))
8870 set = PATTERN (insn);
8872 /* We know that all references to memory will be inside a SET,
8873 because there is no other way to access memory on the mips16.
8874 We don't have to worry about a PARALLEL here, because the
8875 mips.md file will never generate them for memory references. */
8876 if (GET_CODE (set) != SET)
8879 if (gpcopy == NULL_RTX
8880 && GET_CODE (SET_SRC (set)) == CONST
8881 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8882 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8883 && GET_CODE (SET_DEST (set)) == REG
8884 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8885 gpcopy = SET_DEST (set);
8886 else if (slot == NULL_RTX
8887 && gpcopy != NULL_RTX
8888 && GET_CODE (SET_DEST (set)) == MEM
8889 && GET_CODE (SET_SRC (set)) == REG
8890 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8891 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8895 offset = const0_rtx;
8896 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8897 if (GET_CODE (base) == REG
8898 && (REGNO (base) == STACK_POINTER_REGNUM
8899 || REGNO (base) == FRAME_POINTER_REGNUM))
8900 slot = SET_DEST (set);
8902 else if (gpcopy != NULL_RTX
8903 && (GET_CODE (SET_DEST (set)) == REG
8904 || GET_CODE (SET_DEST (set)) == SUBREG)
8905 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8906 && (GET_CODE (SET_DEST (set)) != REG
8907 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8908 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
8909 || ((GET_CODE (SET_SRC (set)) != CONST
8910 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8911 || (REGNO (XEXP (SET_SRC (set), 0))
8912 != GP_REG_FIRST + 28))
8913 && ! rtx_equal_p (SET_SRC (set), slot))))
8915 else if (slot != NULL_RTX
8916 && GET_CODE (SET_DEST (set)) == MEM
8917 && rtx_equal_p (SET_DEST (set), slot)
8918 && (GET_CODE (SET_SRC (set)) != REG
8919 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8923 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8924 different optimization. Any time we find a copy of $28 into a
8925 register, followed by an add of a symbol_ref to that register, we
8926 convert it to load the value from the constant table instead.
8927 The copy and add will take six bytes, just as the load and
8928 constant table entry will take six bytes. However, it is
8929 possible that the constant table entry will be shared.
8931 This could be a peephole optimization, but I don't know if the
8932 peephole code can call force_const_mem.
8934 Using the same register for the copy of $28 and the add of the
8935 symbol_ref is actually pretty likely, since the add instruction
8936 requires the destination and the first addend to be the same
8939 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8943 /* This optimization is only reasonable if the constant table
8944 entries are only 4 bytes. */
8945 if (Pmode != SImode)
8948 for (insn = first; insn != NULL_RTX; insn = next)
8955 next = NEXT_INSN (next);
8957 while (next != NULL_RTX
8958 && (GET_CODE (next) == NOTE
8959 || (GET_CODE (next) == INSN
8960 && (GET_CODE (PATTERN (next)) == USE
8961 || GET_CODE (PATTERN (next)) == CLOBBER))));
8963 if (next == NULL_RTX)
8966 if (! INSN_P (insn))
8969 if (! INSN_P (next))
8972 set1 = PATTERN (insn);
8973 if (GET_CODE (set1) != SET)
8975 set2 = PATTERN (next);
8976 if (GET_CODE (set2) != SET)
8979 if (GET_CODE (SET_DEST (set1)) == REG
8980 && GET_CODE (SET_SRC (set1)) == CONST
8981 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8982 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8983 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8984 && GET_CODE (SET_SRC (set2)) == PLUS
8985 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8986 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8987 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8991 /* We've found a case we can change to load from the
8994 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8995 if (GET_CODE (sym) != SYMBOL_REF)
8997 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8998 force_const_mem (Pmode, sym)),
9001 PUT_CODE (insn, NOTE);
9002 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9003 NOTE_SOURCE_FILE (insn) = 0;
9005 PUT_CODE (next, NOTE);
9006 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
9007 NOTE_SOURCE_FILE (next) = 0;
9014 /* We can safely remove all assignments to SLOT from GPCOPY, and
9015 replace all assignments from SLOT to GPCOPY with assignments from
9018 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9022 if (! INSN_P (insn))
9025 set = PATTERN (insn);
9026 if (GET_CODE (set) != SET
9027 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
9030 if (GET_CODE (SET_DEST (set)) == MEM
9031 && rtx_equal_p (SET_DEST (set), slot)
9032 && GET_CODE (SET_SRC (set)) == REG
9033 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
9035 PUT_CODE (insn, NOTE);
9036 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9037 NOTE_SOURCE_FILE (insn) = 0;
9039 else if (GET_CODE (SET_DEST (set)) == REG
9040 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9041 && GET_CODE (SET_SRC (set)) == MEM
9042 && rtx_equal_p (SET_SRC (set), slot))
9044 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
9045 gen_rtx (CONST, Pmode,
9046 gen_rtx (REG, Pmode,
9047 GP_REG_FIRST + 28))),
9049 PUT_CODE (insn, NOTE);
9050 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9051 NOTE_SOURCE_FILE (insn) = 0;
9056 /* We keep a list of constants we which we have to add to internal
9057 constant tables in the middle of large functions. */
9061 struct constant *next;
9064 enum machine_mode mode;
9067 /* Add a constant to the list in *PCONSTANTS. */
9070 add_constant (pconstants, val, mode)
9071 struct constant **pconstants;
9073 enum machine_mode mode;
9077 for (c = *pconstants; c != NULL; c = c->next)
9078 if (mode == c->mode && rtx_equal_p (val, c->value))
9081 c = (struct constant *) xmalloc (sizeof *c);
9084 c->label = gen_label_rtx ();
9085 c->next = *pconstants;
9090 /* Dump out the constants in CONSTANTS after INSN. */
9093 dump_constants (constants, insn)
9094 struct constant *constants;
9105 struct constant *next;
9107 switch (GET_MODE_SIZE (c->mode))
9114 insn = emit_insn_after (gen_align_2 (), insn);
9119 insn = emit_insn_after (gen_align_4 (), insn);
9124 insn = emit_insn_after (gen_align_8 (), insn);
9129 insn = emit_label_after (c->label, insn);
9134 r = gen_consttable_qi (c->value);
9137 r = gen_consttable_hi (c->value);
9140 r = gen_consttable_si (c->value);
9143 r = gen_consttable_sf (c->value);
9146 r = gen_consttable_di (c->value);
9149 r = gen_consttable_df (c->value);
9155 insn = emit_insn_after (r, insn);
9162 emit_barrier_after (insn);
9165 /* Find the symbol in an address expression. */
9168 mips_find_symbol (addr)
9171 if (GET_CODE (addr) == MEM)
9172 addr = XEXP (addr, 0);
9173 while (GET_CODE (addr) == CONST)
9174 addr = XEXP (addr, 0);
9175 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9177 if (GET_CODE (addr) == PLUS)
9181 l1 = mips_find_symbol (XEXP (addr, 0));
9182 l2 = mips_find_symbol (XEXP (addr, 1));
9183 if (l1 != NULL_RTX && l2 == NULL_RTX)
9185 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9191 /* Exported to toplev.c.
9193 Do a final pass over the function, just before delayed branch
9197 machine_dependent_reorg (first)
9200 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9202 struct constant *constants;
9204 if (! TARGET_MIPS16)
9207 /* If $gp is used, try to remove stores, and replace loads with
9210 mips16_optimize_gp (first);
9212 /* Scan the function looking for PC relative loads which may be out
9213 of range. All such loads will either be from the constant table,
9214 or be getting the address of a constant string. If the size of
9215 the function plus the size of the constant table is less than
9216 0x8000, then all loads are in range. */
9219 for (insn = first; insn; insn = NEXT_INSN (insn))
9221 insns_len += get_attr_length (insn);
9223 /* ??? We put switch tables in .text, but we don't define
9224 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9225 compute their lengths correctly. */
9226 if (GET_CODE (insn) == JUMP_INSN)
9230 body = PATTERN (insn);
9231 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9232 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9233 * GET_MODE_SIZE (GET_MODE (body)));
9234 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9238 /* Store the original value of insns_len in current_frame_info, so
9239 that simple_memory_operand can look at it. */
9240 current_frame_info.insns_len = insns_len;
9242 pool_size = get_pool_size ();
9243 if (insns_len + pool_size + mips_string_length < 0x8000)
9246 /* Loop over the insns and figure out what the maximum internal pool
9248 max_internal_pool_size = 0;
9249 for (insn = first; insn; insn = NEXT_INSN (insn))
9251 if (GET_CODE (insn) == INSN
9252 && GET_CODE (PATTERN (insn)) == SET)
9256 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9257 if (src == NULL_RTX)
9259 if (CONSTANT_POOL_ADDRESS_P (src))
9260 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9261 else if (SYMBOL_REF_FLAG (src))
9262 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9268 first_constant_ref = -1;
9270 for (insn = first; insn; insn = NEXT_INSN (insn))
9272 if (GET_CODE (insn) == INSN
9273 && GET_CODE (PATTERN (insn)) == SET)
9276 enum machine_mode mode = VOIDmode;
9279 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9280 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9282 /* ??? This is very conservative, which means that we
9283 will generate too many copies of the constant table.
9284 The only solution would seem to be some form of
9286 if (((insns_len - addr)
9287 + max_internal_pool_size
9288 + get_pool_offset (src))
9291 val = get_pool_constant (src);
9292 mode = get_pool_mode (src);
9294 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9296 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9298 /* Including all of mips_string_length is conservative,
9299 and so is including all of max_internal_pool_size. */
9300 if (((insns_len - addr)
9301 + max_internal_pool_size
9303 + mips_string_length)
9309 max_internal_pool_size -= Pmode;
9312 if (val != NULL_RTX)
9316 /* This PC relative load is out of range. ??? In the
9317 case of a string constant, we are only guessing that
9318 it is range, since we don't know the offset of a
9319 particular string constant. */
9321 lab = add_constant (&constants, val, mode);
9322 newsrc = gen_rtx (MEM, mode,
9323 gen_rtx (LABEL_REF, VOIDmode, lab));
9324 RTX_UNCHANGING_P (newsrc) = 1;
9325 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9326 SET_DEST (PATTERN (insn)),
9328 INSN_CODE (insn) = -1;
9330 if (first_constant_ref < 0)
9331 first_constant_ref = addr;
9335 addr += get_attr_length (insn);
9337 /* ??? We put switch tables in .text, but we don't define
9338 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9339 compute their lengths correctly. */
9340 if (GET_CODE (insn) == JUMP_INSN)
9344 body = PATTERN (insn);
9345 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9346 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9347 * GET_MODE_SIZE (GET_MODE (body)));
9348 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9351 if (GET_CODE (insn) == BARRIER)
9353 /* Output any constants we have accumulated. Note that we
9354 don't need to change ADDR, since its only use is
9355 subtraction from INSNS_LEN, and both would be changed by
9357 ??? If the instructions up to the next barrier reuse a
9358 constant, it would often be better to continue
9360 if (constants != NULL)
9361 dump_constants (constants, insn);
9363 first_constant_ref = -1;
9366 if (constants != NULL
9367 && (NEXT_INSN (insn) == NULL
9368 || (first_constant_ref >= 0
9369 && (((addr - first_constant_ref)
9370 + 2 /* for alignment */
9371 + 2 /* for a short jump insn */
9375 /* If we haven't had a barrier within 0x8000 bytes of a
9376 constant reference or we are at the end of the function,
9377 emit a barrier now. */
9379 rtx label, jump, barrier;
9381 label = gen_label_rtx ();
9382 jump = emit_jump_insn_after (gen_jump (label), insn);
9383 JUMP_LABEL (jump) = label;
9384 LABEL_NUSES (label) = 1;
9385 barrier = emit_barrier_after (jump);
9386 emit_label_after (label, barrier);
9387 first_constant_ref = -1;
9391 /* ??? If we output all references to a constant in internal
9392 constants table, we don't need to output the constant in the real
9393 constant table, but we have no way to prevent that. */
9396 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9398 extend_operator (x, mode)
9400 enum machine_mode mode ATTRIBUTE_UNUSED;
9402 enum rtx_code code = GET_CODE (x);
9403 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9406 /* Accept any operator that can be used to shift the high half of the
9407 input value to the lower half, suitable for truncation. The
9408 remainder (the lower half of the input, and the upper half of the
9409 output) will be discarded. */
9411 highpart_shift_operator (x, mode)
9413 enum machine_mode mode ATTRIBUTE_UNUSED;
9415 enum rtx_code code = GET_CODE (x);
9416 return (code == LSHIFTRT
9422 /* Return the length of INSN. LENGTH is the initial length computed by
9423 attributes in the machine-description file. */
9426 mips_adjust_insn_length (insn, length)
9430 /* A unconditional jump has an unfilled delay slot if it is not part
9431 of a sequence. A conditional jump normally has a delay slot, but
9432 does not on MIPS16. */
9433 if (simplejump_p (insn)
9434 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9435 || GET_CODE (insn) == CALL_INSN)))
9438 /* All MIPS16 instructions are a measly two bytes. */
9445 /* Output assembly instructions to peform a conditional branch.
9447 INSN is the branch instruction. OPERANDS[0] is the condition.
9448 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9449 of the first operand to the condition. If TWO_OPERANDS_P is
9450 non-zero the comparison takes two operands; OPERANDS[3] will be the
9453 If INVERTED_P is non-zero we are to branch if the condition does
9454 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9456 LENGTH is the length (in bytes) of the sequence we are to generate.
9457 That tells us whether to generate a simple conditional branch, or a
9458 reversed conditional branch around a `jr' instruction. */
9460 mips_output_conditional_branch (insn,
9473 static char buffer[200];
9474 /* The kind of comparison we are doing. */
9475 enum rtx_code code = GET_CODE (operands[0]);
9476 /* Non-zero if the opcode for the comparison needs a `z' indicating
9477 that it is a comparision against zero. */
9479 /* A string to use in the assembly output to represent the first
9481 const char *op1 = "%z2";
9482 /* A string to use in the assembly output to represent the second
9483 operand. Use the hard-wired zero register if there's no second
9485 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9486 /* The operand-printing string for the comparison. */
9487 const char *comp = (float_p ? "%F0" : "%C0");
9488 /* The operand-printing string for the inverted comparison. */
9489 const char *inverted_comp = (float_p ? "%W0" : "%N0");
9491 /* The MIPS processors (for levels of the ISA at least two), have
9492 "likely" variants of each branch instruction. These instructions
9493 annul the instruction in the delay slot if the branch is not
9495 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9497 if (!two_operands_p)
9499 /* To compute whether than A > B, for example, we normally
9500 subtract B from A and then look at the sign bit. But, if we
9501 are doing an unsigned comparison, and B is zero, we don't
9502 have to do the subtraction. Instead, we can just check to
9503 see if A is non-zero. Thus, we change the CODE here to
9504 reflect the simpler comparison operation. */
9516 /* A condition which will always be true. */
9522 /* A condition which will always be false. */
9528 /* Not a special case. */
9533 /* Relative comparisons are always done against zero. But
9534 equality comparisons are done between two operands, and therefore
9535 do not require a `z' in the assembly language output. */
9536 need_z_p = (!float_p && code != EQ && code != NE);
9537 /* For comparisons against zero, the zero is not provided
9542 /* Begin by terminating the buffer. That way we can always use
9543 strcat to add to it. */
9550 /* Just a simple conditional branch. */
9552 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9553 inverted_p ? inverted_comp : comp);
9555 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9556 inverted_p ? inverted_comp : comp,
9557 need_z_p ? "z" : "",
9565 /* Generate a reversed conditional branch around ` j'
9577 Because we have to jump four bytes *past* the following
9578 instruction if this branch was annulled, we can't just use
9579 a label, as in the picture above; there's no way to put the
9580 label after the next instruction, as the assembler does not
9581 accept `.L+4' as the target of a branch. (We can't just
9582 wait until the next instruction is output; it might be a
9583 macro and take up more than four bytes. Once again, we see
9584 why we want to eliminate macros.)
9586 If the branch is annulled, we jump four more bytes that we
9587 would otherwise; that way we skip the annulled instruction
9588 in the delay slot. */
9591 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
9594 strcpy (buffer, "%(%<");
9595 c = strchr (buffer, '\0');
9596 /* Generate the reversed comparision. This takes four
9599 sprintf (c, "%%*b%s\t%%Z2%s",
9600 inverted_p ? comp : inverted_comp,
9603 sprintf (c, "%%*b%s%s\t%s%s,%s",
9604 inverted_p ? comp : inverted_comp,
9605 need_z_p ? "z" : "",
9609 strcat (c, "\n\tnop\n\tj\t%1");
9611 /* The delay slot was unfilled. Since we're inside
9612 .noreorder, the assembler will not fill in the NOP for
9613 us, so we must do it ourselves. */
9614 strcat (buffer, "\n\tnop");
9615 strcat (buffer, "%>%)");
9619 /* We do not currently use this code. It handles jumps to
9620 arbitrary locations, using `jr', even across a 256MB boundary.
9621 We could add a -mhuge switch, and then use this code instead of
9622 the `j' alternative above when -mhuge was used. */
9627 /* Generate a reversed conditional branch around a `jr'
9641 Not pretty, but allows a conditional branch anywhere in the
9642 32-bit address space. If the original branch is annulled,
9643 then the instruction in the delay slot should be executed
9644 only if the branch is taken. The la instruction is really
9645 a macro which will usually take eight bytes, but sometimes
9646 takes only four, if the instruction to which we're jumping
9647 gets its own entry in the global pointer table, which will
9648 happen if its a case label. The assembler will then
9649 generate only a four-byte sequence, rather than eight, and
9650 there seems to be no way to tell it not to. Thus, we can't
9651 just use a `.+x' addressing form; we don't know what value
9654 So, we resort to using the explicit relocation syntax
9655 available in the assembler and do:
9657 lw $at,%got_page(target)($gp)
9658 daddiu $at,$at,%got_ofst(target)
9660 That way, this always takes up eight bytes, and we can use
9661 the `.+x' form. Of course, these explicit machinations
9662 with relocation will not work with old assemblers. Then
9663 again, neither do out-of-range branches, so we haven't lost
9666 /* The target of the reversed branch. */
9668 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9669 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9670 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9673 strcpy (buffer, "%(%<%[");
9674 c = strchr (buffer, '\0');
9675 /* Generate the reversed comparision. This takes four
9678 sprintf (c, "%%*b%s\t%%Z2%s",
9679 inverted_p ? comp : inverted_comp,
9682 sprintf (c, "%%*b%s%s\t%s%s,%s",
9683 inverted_p ? comp : inverted_comp,
9684 need_z_p ? "z" : "",
9688 c = strchr (buffer, '\0');
9689 /* Generate the load-address, and jump. This takes twelve
9690 bytes, for a total of 16. */
9692 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9699 /* The delay slot was unfilled. Since we're inside
9700 .noreorder, the assembler will not fill in the NOP for
9701 us, so we must do it ourselves. */
9702 strcat (buffer, "\n\tnop");
9703 strcat (buffer, "%]%>%)");
9716 /* Called to register all of our global variables with the garbage
9720 mips_add_gc_roots ()
9722 ggc_add_rtx_root (&mips_load_reg, 1);
9723 ggc_add_rtx_root (&mips_load_reg2, 1);
9724 ggc_add_rtx_root (&mips_load_reg3, 1);
9725 ggc_add_rtx_root (&mips_load_reg4, 1);
9726 ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9727 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9728 ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);