1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-flags.h"
40 #include "insn-attr.h"
41 #include "insn-codes.h"
45 #undef MAX /* sys/param.h may also define these */
54 #if defined(USG) || !defined(HAVE_STAB_H)
55 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
57 #include <stab.h> /* On BSD, use the system's stab.h. */
61 #define STAB_CODE_TYPE enum __stab_debug_code
63 #define STAB_CODE_TYPE int
66 extern char *mktemp ();
67 extern tree lookup_name ();
69 /* Enumeration for all of the relational tests, so that we can build
70 arrays indexed by the test type, and not worry about the order
89 static enum internal_test map_test_to_internal_test PROTO ((enum rtx_code));
90 static int mips16_simple_memory_operand PROTO ((rtx, rtx,
92 static int m16_check_op PROTO ((rtx, int, int, int));
93 static void block_move_loop PROTO ((rtx, rtx, int, int,
95 static void block_move_call PROTO ((rtx, rtx, rtx));
96 static FILE *make_temp_file PROTO ((void));
97 static void save_restore_insns PROTO ((int, rtx,
99 static void mips16_output_gp_offset PROTO ((FILE *, rtx));
100 static void mips16_fp_args PROTO ((FILE *, int, int));
101 static void build_mips16_function_stub PROTO ((FILE *));
102 static void mips16_optimize_gp PROTO ((rtx));
103 static rtx add_constant PROTO ((struct constant **,
106 static void dump_constants PROTO ((struct constant *,
108 static rtx mips_find_symbol PROTO ((rtx));
111 /* Global variables for machine-dependent things. */
113 /* Threshold for data being put into the small data/bss area, instead
114 of the normal data area (references to the small data/bss area take
115 1 instruction, and use the global pointer, references to the normal
116 data area takes 2 instructions). */
117 int mips_section_threshold = -1;
119 /* Count the number of .file directives, so that .loc is up to date. */
120 int num_source_filenames = 0;
122 /* Count the number of sdb related labels are generated (to find block
123 start and end boundaries). */
124 int sdb_label_count = 0;
126 /* Next label # for each statement for Silicon Graphics IRIS systems. */
129 /* Non-zero if inside of a function, because the stupid MIPS asm can't
130 handle .files inside of functions. */
131 int inside_function = 0;
133 /* Files to separate the text and the data output, so that all of the data
134 can be emitted before the text, which will mean that the assembler will
135 generate smaller code, based on the global pointer. */
136 FILE *asm_out_data_file;
137 FILE *asm_out_text_file;
139 /* Linked list of all externals that are to be emitted when optimizing
140 for the global pointer if they haven't been declared by the end of
141 the program with an appropriate .comm or initialization. */
145 struct extern_list *next; /* next external */
146 char *name; /* name of the external */
147 int size; /* size in bytes */
150 /* Name of the file containing the current function. */
151 char *current_function_file = "";
153 /* Warning given that Mips ECOFF can't support changing files
154 within a function. */
155 int file_in_function_warning = FALSE;
157 /* Whether to suppress issuing .loc's because the user attempted
158 to change the filename within a function. */
159 int ignore_line_number = FALSE;
161 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
167 /* The next branch instruction is a branch likely, not branch normal. */
168 int mips_branch_likely;
170 /* Count of delay slots and how many are filled. */
171 int dslots_load_total;
172 int dslots_load_filled;
173 int dslots_jump_total;
174 int dslots_jump_filled;
176 /* # of nops needed by previous insn */
177 int dslots_number_nops;
179 /* Number of 1/2/3 word references to data items (ie, not jal's). */
182 /* registers to check for load delay */
183 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
185 /* Cached operands, and operator to compare for use in set/branch on
189 /* what type of branch to use */
190 enum cmp_type branch_type;
192 /* Number of previously seen half-pic pointers and references. */
193 static int prev_half_pic_ptrs = 0;
194 static int prev_half_pic_refs = 0;
196 /* which cpu are we scheduling for */
197 enum processor_type mips_cpu;
199 /* which instruction set architecture to use. */
202 #ifdef MIPS_ABI_DEFAULT
203 /* Which ABI to use. This is defined to a constant in mips.h if the target
204 doesn't support multiple ABIs. */
208 /* Strings to hold which cpu and instruction set architecture to use. */
209 char *mips_cpu_string; /* for -mcpu=<xxx> */
210 char *mips_isa_string; /* for -mips{1,2,3,4} */
211 char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
213 /* Whether we are generating mips16 code. This is a synonym for
214 TARGET_MIPS16, and exists for use as an attribute. */
217 /* This variable is set by -mno-mips16. We only care whether
218 -mno-mips16 appears or not, and using a string in this fashion is
219 just a way to avoid using up another bit in target_flags. */
220 char *mips_no_mips16_string;
222 /* Whether we are generating mips16 hard float code. In mips16 mode
223 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
224 -msoft-float was not specified by the user, which means that we
225 should arrange to call mips32 hard floating point code. */
226 int mips16_hard_float;
228 /* This variable is set by -mentry. We only care whether -mentry
229 appears or not, and using a string in this fashion is just a way to
230 avoid using up another bit in target_flags. */
231 char *mips_entry_string;
233 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
236 /* If TRUE, we split addresses into their high and low parts in the RTL. */
237 int mips_split_addresses;
239 /* Generating calls to position independent functions? */
240 enum mips_abicalls_type mips_abicalls;
242 /* High and low marks for floating point values which we will accept
243 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
244 initialized in override_options. */
245 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
247 /* Mode used for saving/restoring general purpose registers. */
248 static static enum machine_mode gpr_mode;
250 /* Array giving truth value on whether or not a given hard register
251 can support a given mode. */
252 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
254 /* Current frame information calculated by compute_frame_size. */
255 struct mips_frame_info current_frame_info;
257 /* Zero structure to initialize current_frame_info. */
258 struct mips_frame_info zero_frame_info;
260 /* Temporary filename used to buffer .text until end of program
262 static char *temp_filename;
264 /* Pseudo-reg holding the address of the current function when
265 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
266 by mips_finalize_pic if it was created. */
267 rtx embedded_pic_fnaddr_rtx;
269 /* The length of all strings seen when compiling for the mips16. This
270 is used to tell how many strings are in the constant pool, so that
271 we can see if we may have an overflow. This is reset each time the
272 constant pool is output. */
273 int mips_string_length;
275 /* Pseudo-reg holding the value of $28 in a mips16 function which
276 refers to GP relative global variables. */
277 rtx mips16_gp_pseudo_rtx;
279 /* In mips16 mode, we build a list of all the string constants we see
280 in a particular function. */
282 struct string_constant
284 struct string_constant *next;
288 static struct string_constant *string_constants;
290 /* List of all MIPS punctuation characters used by print_operand. */
291 char mips_print_operand_punct[256];
293 /* Map GCC register number to debugger register number. */
294 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
296 /* Buffer to use to enclose a load/store operation with %{ %} to
297 turn on .set volatile. */
298 static char volatile_buffer[60];
300 /* Hardware names for the registers. If -mrnames is used, this
301 will be overwritten with mips_sw_reg_names. */
303 char mips_reg_names[][8] =
305 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
306 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
307 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
308 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
309 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
310 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
311 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
312 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
313 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
314 "$fcc5","$fcc6","$fcc7","$rap"
317 /* Mips software names for the registers, used to overwrite the
318 mips_reg_names array. */
320 char mips_sw_reg_names[][8] =
322 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
323 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
324 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
325 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
326 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
327 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
328 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
329 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
330 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
331 "$fcc5","$fcc6","$fcc7","$rap"
334 /* Map hard register number to register class */
335 enum reg_class mips_regno_to_class[] =
337 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
338 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
339 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
340 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
341 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
342 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
343 T_REG, GR_REGS, GR_REGS, GR_REGS,
344 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
345 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
346 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
347 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
348 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
349 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
350 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
351 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
352 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
353 HI_REG, LO_REG, HILO_REG, ST_REGS,
354 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
355 ST_REGS, ST_REGS, ST_REGS, GR_REGS
358 /* Map register constraint character to register class. */
359 enum reg_class mips_char_to_class[256] =
361 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
362 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
363 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
364 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
365 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
366 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
367 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
368 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
369 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
370 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
371 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 /* Return truth value of whether OP can be used as an operands
429 where a register or 16 bit unsigned integer is needed. */
432 uns_arith_operand (op, mode)
434 enum machine_mode mode;
436 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
439 return register_operand (op, mode);
442 /* Return truth value of whether OP can be used as an operands
443 where a 16 bit integer is needed */
446 arith_operand (op, mode)
448 enum machine_mode mode;
450 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
453 /* On the mips16, a GP relative value is a signed 16 bit offset. */
454 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
457 return register_operand (op, mode);
460 /* Return truth value of whether OP can be used as an operand in a two
461 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
464 arith32_operand (op, mode)
466 enum machine_mode mode;
468 if (GET_CODE (op) == CONST_INT)
471 return register_operand (op, mode);
474 /* Return truth value of whether OP is a integer which fits in 16 bits */
479 enum machine_mode mode ATTRIBUTE_UNUSED;
481 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
484 /* Return truth value of whether OP is a 32 bit integer which is too big to
485 be loaded with one instruction. */
490 enum machine_mode mode ATTRIBUTE_UNUSED;
494 if (GET_CODE (op) != CONST_INT)
499 /* ior reg,$r0,value */
500 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
503 /* subu reg,$r0,value */
504 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
507 /* lui reg,value>>16 */
508 if ((value & 0x0000ffff) == 0)
514 /* Return truth value of whether OP is a register or the constant 0.
515 In mips16 mode, we only accept a register, since the mips16 does
519 reg_or_0_operand (op, mode)
521 enum machine_mode mode;
523 switch (GET_CODE (op))
528 return INTVAL (op) == 0;
533 return op == CONST0_RTX (mode);
537 return register_operand (op, mode);
546 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
549 mips_const_double_ok (op, mode)
551 enum machine_mode mode;
555 if (GET_CODE (op) != CONST_DOUBLE)
558 if (mode == VOIDmode)
561 if (mode != SFmode && mode != DFmode)
564 if (op == CONST0_RTX (mode))
567 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
568 if (mips_abi != ABI_32 && mips_abi != ABI_EABI)
571 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
573 if (REAL_VALUE_ISNAN (d))
576 if (REAL_VALUE_NEGATIVE (d))
577 d = REAL_VALUE_NEGATE (d);
581 if (REAL_VALUES_LESS (d, dfhigh)
582 && REAL_VALUES_LESS (dflow, d))
587 if (REAL_VALUES_LESS (d, sfhigh)
588 && REAL_VALUES_LESS (sflow, d))
595 /* Accept the floating point constant 1 in the appropriate mode. */
598 const_float_1_operand (op, mode)
600 enum machine_mode mode;
603 static REAL_VALUE_TYPE onedf;
604 static REAL_VALUE_TYPE onesf;
605 static int one_initialized;
607 if (GET_CODE (op) != CONST_DOUBLE
608 || mode != GET_MODE (op)
609 || (mode != DFmode && mode != SFmode))
612 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
614 /* We only initialize these values if we need them, since we will
615 never get called unless mips_isa >= 4. */
616 if (! one_initialized)
618 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
619 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
624 return REAL_VALUES_EQUAL (d, onedf);
626 return REAL_VALUES_EQUAL (d, onesf);
629 /* Return true if a memory load or store of REG plus OFFSET in MODE
630 can be represented in a single word on the mips16. */
633 mips16_simple_memory_operand (reg, offset, mode)
636 enum machine_mode mode;
642 /* We can't tell, because we don't know how the value will
643 eventually be accessed. Returning 0 here does no great
644 harm; it just prevents some possible instruction scheduling. */
648 size = GET_MODE_SIZE (mode);
650 if (INTVAL (offset) % size != 0)
652 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
656 if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size)
661 /* Return truth value if a memory operand fits in a single instruction
662 (ie, register + small offset). */
665 simple_memory_operand (op, mode)
667 enum machine_mode mode;
669 rtx addr, plus0, plus1;
671 /* Eliminate non-memory operations */
672 if (GET_CODE (op) != MEM)
675 /* dword operations really put out 2 instructions, so eliminate them. */
676 /* ??? This isn't strictly correct. It is OK to accept multiword modes
677 here, since the length attributes are being set correctly, but only
678 if the address is offsettable. LO_SUM is not offsettable. */
679 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
682 /* Decode the address now. */
684 switch (GET_CODE (addr))
693 return SMALL_INT (op);
696 plus0 = XEXP (addr, 0);
697 plus1 = XEXP (addr, 1);
698 if (GET_CODE (plus0) == REG
699 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
701 || mips16_simple_memory_operand (plus0, plus1, mode)))
704 else if (GET_CODE (plus1) == REG
705 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
707 || mips16_simple_memory_operand (plus1, plus0, mode)))
714 /* We used to allow small symbol refs here (ie, stuff in .sdata
715 or .sbss), but this causes some bugs in G++. Also, it won't
716 interfere if the MIPS linker rewrites the store instruction
717 because the function is PIC. */
719 case LABEL_REF: /* never gp relative */
723 /* If -G 0, we can never have a GP relative memory operation.
724 Also, save some time if not optimizing. */
729 rtx offset = const0_rtx;
730 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
731 if (GET_CODE (op) != SYMBOL_REF)
734 /* let's be paranoid.... */
735 if (! SMALL_INT (offset))
742 return SYMBOL_REF_FLAG (addr);
745 /* This SYMBOL_REF case is for the mips16. If the above case is
746 reenabled, this one should be merged in. */
748 /* References to the constant pool on the mips16 use a small
749 offset if the function is small. The only time we care about
750 getting this right is during delayed branch scheduling, so
751 don't need to check until then. The machine_dependent_reorg
752 function will set the total length of the instructions used
753 in the function in current_frame_info. If that is small
754 enough, we know for sure that this is a small offset. It
755 would be better if we could take into account the location of
756 the instruction within the function, but we can't, because we
757 don't know where we are. */
759 && CONSTANT_POOL_ADDRESS_P (addr)
760 && current_frame_info.insns_len > 0)
764 size = current_frame_info.insns_len + get_pool_size ();
765 if (GET_MODE_SIZE (mode) == 4)
766 return size < 4 * 0x100;
767 else if (GET_MODE_SIZE (mode) == 8)
768 return size < 8 * 0x20;
782 /* Return nonzero for a memory address that can be used to load or store
786 double_memory_operand (op, mode)
788 enum machine_mode mode;
792 if (GET_CODE (op) != MEM
793 || ! memory_operand (op, mode))
795 /* During reload, we accept a pseudo register if it has an
796 appropriate memory address. If we don't do this, we will
797 wind up reloading into a register, and then reloading that
798 register from memory, when we could just reload directly from
800 if (reload_in_progress
801 && GET_CODE (op) == REG
802 && REGNO (op) >= FIRST_PSEUDO_REGISTER
803 && reg_renumber[REGNO (op)] < 0
804 && reg_equiv_mem[REGNO (op)] != 0
805 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
808 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
809 the same test performed for 'm' in find_reloads. */
811 if (reload_in_progress
813 && (GET_CODE (op) == MEM
814 || (GET_CODE (op) == REG
815 && REGNO (op) >= FIRST_PSEUDO_REGISTER
816 && reg_renumber[REGNO (op)] < 0)))
819 if (reload_in_progress
821 && GET_CODE (op) == MEM)
827 /* During reload on the mips16, we accept a large offset
828 from the frame pointer or the stack pointer. This large
829 address will get reloaded anyhow. */
830 if (GET_CODE (addr) == PLUS
831 && GET_CODE (XEXP (addr, 0)) == REG
832 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
833 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
834 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
835 && ! SMALL_INT (XEXP (addr, 1)))
836 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
837 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
840 /* Similarly, we accept a case where the memory address is
841 itself on the stack, and will be reloaded. */
842 if (GET_CODE (addr) == MEM)
846 maddr = XEXP (addr, 0);
847 if (GET_CODE (maddr) == PLUS
848 && GET_CODE (XEXP (maddr, 0)) == REG
849 && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM
850 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
851 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
852 && ! SMALL_INT (XEXP (maddr, 1)))
853 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
854 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
858 /* We also accept the same case when we have a 16 bit signed
859 offset mixed in as well. The large address will get
860 reloaded, and the 16 bit offset will be OK. */
861 if (GET_CODE (addr) == PLUS
862 && GET_CODE (XEXP (addr, 0)) == MEM
863 && GET_CODE (XEXP (addr, 1)) == CONST_INT
864 && SMALL_INT (XEXP (addr, 1)))
866 addr = XEXP (XEXP (addr, 0), 0);
867 if (GET_CODE (addr) == PLUS
868 && GET_CODE (XEXP (addr, 0)) == REG
869 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
870 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
871 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
872 && ! SMALL_INT (XEXP (addr, 1)))
873 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
874 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
884 /* In this case we can use an instruction like sd. */
888 /* Make sure that 4 added to the address is a valid memory address.
889 This essentially just checks for overflow in an added constant. */
893 if (CONSTANT_ADDRESS_P (addr))
896 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
899 plus_constant_for_output (addr, 4));
902 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
905 equality_op (op, mode)
907 enum machine_mode mode;
909 if (mode != GET_MODE (op))
912 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
915 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
920 enum machine_mode mode;
922 if (mode != GET_MODE (op))
925 return GET_RTX_CLASS (GET_CODE (op)) == '<';
928 /* Return nonzero if the operand is either the PC or a label_ref. */
931 pc_or_label_operand (op, mode)
933 enum machine_mode mode ATTRIBUTE_UNUSED;
938 if (GET_CODE (op) == LABEL_REF)
944 /* Test for a valid operand for a call instruction.
945 Don't allow the arg pointer register or virtual regs
946 since they may change into reg + const, which the patterns
950 call_insn_operand (op, mode)
952 enum machine_mode mode ATTRIBUTE_UNUSED;
954 return (CONSTANT_ADDRESS_P (op)
955 || (GET_CODE (op) == REG && op != arg_pointer_rtx
956 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
957 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
960 /* Return nonzero if OPERAND is valid as a source operand for a move
964 move_operand (op, mode)
966 enum machine_mode mode;
968 /* Accept any general operand after reload has started; doing so
969 avoids losing if reload does an in-place replacement of a register
970 with a SYMBOL_REF or CONST. */
971 return (general_operand (op, mode)
972 && (! (mips_split_addresses && mips_check_split (op, mode))
973 || reload_in_progress || reload_completed)
975 && GET_CODE (op) == SYMBOL_REF
976 && ! mips16_constant (op, mode, 1, 0)));
979 /* Return nonzero if OPERAND is valid as a source operand for movdi.
980 This accepts not only general_operand, but also sign extended
981 constants and registers. We need to accept sign extended constants
982 in case a sign extended register which is used in an expression,
983 and is equivalent to a constant, is spilled. */
986 movdi_operand (op, mode)
988 enum machine_mode mode;
992 && GET_CODE (op) == SIGN_EXTEND
993 && GET_MODE (op) == DImode
994 && (GET_MODE (XEXP (op, 0)) == SImode
995 || (GET_CODE (XEXP (op, 0)) == CONST_INT
996 && GET_MODE (XEXP (op, 0)) == VOIDmode))
997 && (register_operand (XEXP (op, 0), SImode)
998 || immediate_operand (XEXP (op, 0), SImode)))
1001 return (general_operand (op, mode)
1003 && GET_CODE (op) == SYMBOL_REF
1004 && ! mips16_constant (op, mode, 1, 0)));
1007 /* Like register_operand, but when in 64 bit mode also accept a sign
1008 extend of a 32 bit register, since the value is known to be already
1012 se_register_operand (op, mode)
1014 enum machine_mode mode;
1018 && GET_CODE (op) == SIGN_EXTEND
1019 && GET_MODE (op) == DImode
1020 && GET_MODE (XEXP (op, 0)) == SImode
1021 && register_operand (XEXP (op, 0), SImode))
1024 return register_operand (op, mode);
1027 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1028 extend of a 32 bit register, since the value is known to be already
1032 se_reg_or_0_operand (op, mode)
1034 enum machine_mode mode;
1038 && GET_CODE (op) == SIGN_EXTEND
1039 && GET_MODE (op) == DImode
1040 && GET_MODE (XEXP (op, 0)) == SImode
1041 && register_operand (XEXP (op, 0), SImode))
1044 return reg_or_0_operand (op, mode);
1047 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1048 extend of a 32 bit register, since the value is known to be already
1052 se_uns_arith_operand (op, mode)
1054 enum machine_mode mode;
1058 && GET_CODE (op) == SIGN_EXTEND
1059 && GET_MODE (op) == DImode
1060 && GET_MODE (XEXP (op, 0)) == SImode
1061 && register_operand (XEXP (op, 0), SImode))
1064 return uns_arith_operand (op, mode);
1067 /* Like arith_operand, but when in 64 bit mode also accept a sign
1068 extend of a 32 bit register, since the value is known to be already
1072 se_arith_operand (op, mode)
1074 enum machine_mode mode;
1078 && GET_CODE (op) == SIGN_EXTEND
1079 && GET_MODE (op) == DImode
1080 && GET_MODE (XEXP (op, 0)) == SImode
1081 && register_operand (XEXP (op, 0), SImode))
1084 return arith_operand (op, mode);
1087 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1088 extend of a 32 bit register, since the value is known to be already
1092 se_nonmemory_operand (op, mode)
1094 enum machine_mode mode;
1098 && GET_CODE (op) == SIGN_EXTEND
1099 && GET_MODE (op) == DImode
1100 && GET_MODE (XEXP (op, 0)) == SImode
1101 && register_operand (XEXP (op, 0), SImode))
1104 return nonmemory_operand (op, mode);
1107 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1108 sign extend of a 32 bit register, since the value is known to be
1109 already sign extended. */
1112 se_nonimmediate_operand (op, mode)
1114 enum machine_mode mode;
1118 && GET_CODE (op) == SIGN_EXTEND
1119 && GET_MODE (op) == DImode
1120 && GET_MODE (XEXP (op, 0)) == SImode
1121 && register_operand (XEXP (op, 0), SImode))
1124 return nonimmediate_operand (op, mode);
1127 /* Accept any operand that can appear in a mips16 constant table
1128 instruction. We can't use any of the standard operand functions
1129 because for these instructions we accept values that are not
1130 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1133 consttable_operand (op, mode)
1135 enum machine_mode mode ATTRIBUTE_UNUSED;
1137 return CONSTANT_P (op);
1140 /* Return nonzero if we split the address into high and low parts. */
1142 /* ??? We should also handle reg+array somewhere. We get four
1143 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1144 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1145 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1146 out of the address, then we have 4 instructions to combine. Perhaps
1147 add a 3->2 define_split for combine. */
1149 /* ??? We could also split a CONST_INT here if it is a large_int().
1150 However, it doesn't seem to be very useful to have %hi(constant).
1151 We would be better off by doing the masking ourselves and then putting
1152 the explicit high part of the constant in the RTL. This will give better
1153 optimization. Also, %hi(constant) needs assembler changes to work.
1154 There is already a define_split that does this. */
1157 mips_check_split (address, mode)
1159 enum machine_mode mode;
1161 /* ??? This is the same check used in simple_memory_operand.
1162 We use it here because LO_SUM is not offsettable. */
1163 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1166 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1167 || (GET_CODE (address) == CONST
1168 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1169 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1170 || GET_CODE (address) == LABEL_REF)
1176 /* We need a lot of little routines to check constant values on the
1177 mips16. These are used to figure out how long the instruction will
1178 be. It would be much better to do this using constraints, but
1179 there aren't nearly enough letters available. */
1182 m16_check_op (op, low, high, mask)
1188 return (GET_CODE (op) == CONST_INT
1189 && INTVAL (op) >= low
1190 && INTVAL (op) <= high
1191 && (INTVAL (op) & mask) == 0);
1195 m16_uimm3_b (op, mode)
1197 enum machine_mode mode ATTRIBUTE_UNUSED;
1199 return m16_check_op (op, 0x1, 0x8, 0);
1203 m16_simm4_1 (op, mode)
1205 enum machine_mode mode ATTRIBUTE_UNUSED;
1207 return m16_check_op (op, - 0x8, 0x7, 0);
1211 m16_nsimm4_1 (op, mode)
1213 enum machine_mode mode ATTRIBUTE_UNUSED;
1215 return m16_check_op (op, - 0x7, 0x8, 0);
1219 m16_simm5_1 (op, mode)
1221 enum machine_mode mode ATTRIBUTE_UNUSED;
1223 return m16_check_op (op, - 0x10, 0xf, 0);
1227 m16_nsimm5_1 (op, mode)
1229 enum machine_mode mode ATTRIBUTE_UNUSED;
1231 return m16_check_op (op, - 0xf, 0x10, 0);
1235 m16_uimm5_4 (op, mode)
1237 enum machine_mode mode ATTRIBUTE_UNUSED;
1239 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1243 m16_nuimm5_4 (op, mode)
1245 enum machine_mode mode ATTRIBUTE_UNUSED;
1247 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1251 m16_simm8_1 (op, mode)
1253 enum machine_mode mode ATTRIBUTE_UNUSED;
1255 return m16_check_op (op, - 0x80, 0x7f, 0);
1259 m16_nsimm8_1 (op, mode)
1261 enum machine_mode mode ATTRIBUTE_UNUSED;
1263 return m16_check_op (op, - 0x7f, 0x80, 0);
1267 m16_uimm8_1 (op, mode)
1269 enum machine_mode mode ATTRIBUTE_UNUSED;
1271 return m16_check_op (op, 0x0, 0xff, 0);
1275 m16_nuimm8_1 (op, mode)
1277 enum machine_mode mode ATTRIBUTE_UNUSED;
1279 return m16_check_op (op, - 0xff, 0x0, 0);
1283 m16_uimm8_m1_1 (op, mode)
1285 enum machine_mode mode ATTRIBUTE_UNUSED;
1287 return m16_check_op (op, - 0x1, 0xfe, 0);
1291 m16_uimm8_4 (op, mode)
1293 enum machine_mode mode ATTRIBUTE_UNUSED;
1295 return m16_check_op (op, 0x0, 0xff << 2, 3);
1299 m16_nuimm8_4 (op, mode)
1301 enum machine_mode mode ATTRIBUTE_UNUSED;
1303 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1307 m16_simm8_8 (op, mode)
1309 enum machine_mode mode ATTRIBUTE_UNUSED;
1311 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1315 m16_nsimm8_8 (op, mode)
1317 enum machine_mode mode ATTRIBUTE_UNUSED;
1319 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1322 /* References to the string table on the mips16 only use a small
1323 offset if the function is small. See the comment in the SYMBOL_REF
1324 case in simple_memory_operand. We can't check for LABEL_REF here,
1325 because the offset is always large if the label is before the
1326 referencing instruction. */
1329 m16_usym8_4 (op, mode)
1331 enum machine_mode mode ATTRIBUTE_UNUSED;
1333 if (GET_CODE (op) == SYMBOL_REF
1334 && SYMBOL_REF_FLAG (op)
1335 && current_frame_info.insns_len > 0
1336 && XSTR (op, 0)[0] == '*'
1337 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1338 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1339 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1342 struct string_constant *l;
1344 /* Make sure this symbol is on thelist of string constants to be
1345 output for this function. It is possible that it has already
1346 been output, in which case this requires a large offset. */
1347 for (l = string_constants; l != NULL; l = l->next)
1348 if (strcmp (l->label, XSTR (op, 0)) == 0)
1356 m16_usym5_4 (op, mode)
1358 enum machine_mode mode ATTRIBUTE_UNUSED;
1360 if (GET_CODE (op) == SYMBOL_REF
1361 && SYMBOL_REF_FLAG (op)
1362 && current_frame_info.insns_len > 0
1363 && XSTR (op, 0)[0] == '*'
1364 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1365 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1366 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1369 struct string_constant *l;
1371 /* Make sure this symbol is on thelist of string constants to be
1372 output for this function. It is possible that it has already
1373 been output, in which case this requires a large offset. */
1374 for (l = string_constants; l != NULL; l = l->next)
1375 if (strcmp (l->label, XSTR (op, 0)) == 0)
1382 /* Returns an operand string for the given instruction's delay slot,
1383 after updating filled delay slot statistics.
1385 We assume that operands[0] is the target register that is set.
1387 In order to check the next insn, most of this functionality is moved
1388 to FINAL_PRESCAN_INSN, and we just set the global variables that
1391 /* ??? This function no longer does anything useful, because final_prescan_insn
1392 now will never emit a nop. */
1395 mips_fill_delay_slot (ret, type, operands, cur_insn)
1396 char *ret; /* normal string to return */
1397 enum delay_type type; /* type of delay */
1398 rtx operands[]; /* operands to use */
1399 rtx cur_insn; /* current insn */
1401 register rtx set_reg;
1402 register enum machine_mode mode;
1403 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1404 register int num_nops;
1406 if (type == DELAY_LOAD || type == DELAY_FCMP)
1409 else if (type == DELAY_HILO)
1415 /* Make sure that we don't put nop's after labels. */
1416 next_insn = NEXT_INSN (cur_insn);
1417 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1418 next_insn = NEXT_INSN (next_insn);
1420 dslots_load_total += num_nops;
1421 if (TARGET_DEBUG_F_MODE
1423 || type == DELAY_NONE
1427 || GET_CODE (next_insn) == CODE_LABEL
1428 || (set_reg = operands[0]) == 0)
1430 dslots_number_nops = 0;
1438 set_reg = operands[0];
1442 while (GET_CODE (set_reg) == SUBREG)
1443 set_reg = SUBREG_REG (set_reg);
1445 mode = GET_MODE (set_reg);
1446 dslots_number_nops = num_nops;
1447 mips_load_reg = set_reg;
1448 if (GET_MODE_SIZE (mode)
1449 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1450 mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
1454 if (type == DELAY_HILO)
1456 mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
1457 mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
1469 /* Determine whether a memory reference takes one (based off of the GP
1470 pointer), two (normal), or three (label + reg) instructions, and bump the
1471 appropriate counter for -mstats. */
1474 mips_count_memory_refs (op, num)
1480 rtx addr, plus0, plus1;
1481 enum rtx_code code0, code1;
1484 if (TARGET_DEBUG_B_MODE)
1486 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1490 /* Skip MEM if passed, otherwise handle movsi of address. */
1491 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1493 /* Loop, going through the address RTL. */
1497 switch (GET_CODE (addr))
1505 plus0 = XEXP (addr, 0);
1506 plus1 = XEXP (addr, 1);
1507 code0 = GET_CODE (plus0);
1508 code1 = GET_CODE (plus1);
1518 if (code0 == CONST_INT)
1533 if (code1 == CONST_INT)
1540 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1547 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1557 n_words = 2; /* always 2 words */
1561 addr = XEXP (addr, 0);
1566 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1578 n_words += additional;
1582 num_refs[n_words-1] += num;
1586 /* Return RTL for the offset from the current function to the argument.
1588 ??? Which argument is this? */
1591 embedded_pic_offset (x)
1594 if (embedded_pic_fnaddr_rtx == NULL)
1598 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1600 /* Output code at function start to initialize the pseudo-reg. */
1601 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1602 inline functions, because it is called after RTL for the function
1603 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1604 does not get copied, and ends up not matching the rest of the RTL.
1605 This solution works, but means that we get unnecessary code to
1606 initialize this value every time a function is inlined into another
1609 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1610 XEXP (DECL_RTL (current_function_decl), 0)));
1611 seq = gen_sequence ();
1613 push_topmost_sequence ();
1614 emit_insn_after (seq, get_insns ());
1615 pop_topmost_sequence ();
1618 return gen_rtx (CONST, Pmode,
1619 gen_rtx (MINUS, Pmode, x,
1620 XEXP (DECL_RTL (current_function_decl), 0)));
1623 /* Return the appropriate instructions to move one operand to another. */
1626 mips_move_1word (operands, insn, unsignedp)
1632 rtx op0 = operands[0];
1633 rtx op1 = operands[1];
1634 enum rtx_code code0 = GET_CODE (op0);
1635 enum rtx_code code1 = GET_CODE (op1);
1636 enum machine_mode mode = GET_MODE (op0);
1637 int subreg_word0 = 0;
1638 int subreg_word1 = 0;
1639 enum delay_type delay = DELAY_NONE;
1641 while (code0 == SUBREG)
1643 subreg_word0 += SUBREG_WORD (op0);
1644 op0 = SUBREG_REG (op0);
1645 code0 = GET_CODE (op0);
1648 while (code1 == SUBREG)
1650 subreg_word1 += SUBREG_WORD (op1);
1651 op1 = SUBREG_REG (op1);
1652 code1 = GET_CODE (op1);
1655 /* For our purposes, a condition code mode is the same as SImode. */
1661 int regno0 = REGNO (op0) + subreg_word0;
1665 int regno1 = REGNO (op1) + subreg_word1;
1667 /* Just in case, don't do anything for assigning a register
1668 to itself, unless we are filling a delay slot. */
1669 if (regno0 == regno1 && set_nomacro == 0)
1672 else if (GP_REG_P (regno0))
1674 if (GP_REG_P (regno1))
1675 ret = "move\t%0,%1";
1677 else if (MD_REG_P (regno1))
1680 if (regno1 != HILO_REGNUM)
1686 else if (ST_REG_P (regno1) && mips_isa >= 4)
1687 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1692 if (FP_REG_P (regno1))
1693 ret = "mfc1\t%0,%1";
1695 else if (regno1 == FPSW_REGNUM && mips_isa < 4)
1696 ret = "cfc1\t%0,$31";
1700 else if (FP_REG_P (regno0))
1702 if (GP_REG_P (regno1))
1705 ret = "mtc1\t%1,%0";
1708 if (FP_REG_P (regno1))
1709 ret = "mov.s\t%0,%1";
1712 else if (MD_REG_P (regno0))
1714 if (GP_REG_P (regno1))
1717 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1722 else if (regno0 == FPSW_REGNUM && mips_isa < 4)
1724 if (GP_REG_P (regno1))
1727 ret = "ctc1\t%0,$31";
1732 else if (code1 == MEM)
1737 mips_count_memory_refs (op1, 1);
1739 if (GP_REG_P (regno0))
1741 /* For loads, use the mode of the memory item, instead of the
1742 target, so zero/sign extend can use this code as well. */
1743 switch (GET_MODE (op1))
1752 ret = ((unsignedp && TARGET_64BIT)
1757 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1760 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1765 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1768 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1770 size_t i = strlen (ret);
1771 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1774 sprintf (volatile_buffer, "%%{%s%%}", ret);
1775 ret = volatile_buffer;
1779 else if (code1 == CONST_INT
1780 || (code1 == CONST_DOUBLE
1781 && GET_MODE (op1) == VOIDmode))
1783 if (code1 == CONST_DOUBLE)
1785 /* This can happen when storing constants into long long
1786 bitfields. Just store the least significant word of
1788 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1791 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
1793 if (GP_REG_P (regno0))
1794 ret = "move\t%0,%z1";
1796 else if (FP_REG_P (regno0))
1799 ret = "mtc1\t%z1,%0";
1802 else if (MD_REG_P (regno0))
1809 else if (GP_REG_P (regno0))
1811 /* Don't use X format, because that will give out of
1812 range numbers for 64 bit host and 32 bit target. */
1813 if (! TARGET_MIPS16)
1814 ret = "li\t%0,%1\t\t\t# %X1";
1817 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
1819 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
1820 ret = "li\t%0,%n1\n\tneg\t%0";
1825 else if (code1 == CONST_DOUBLE && mode == SFmode)
1827 if (op1 == CONST0_RTX (SFmode))
1829 if (GP_REG_P (regno0))
1830 ret = "move\t%0,%.";
1832 else if (FP_REG_P (regno0))
1835 ret = "mtc1\t%.,%0";
1842 ret = "li.s\t%0,%1";
1846 else if (code1 == LABEL_REF)
1849 mips_count_memory_refs (op1, 1);
1854 else if (code1 == SYMBOL_REF || code1 == CONST)
1856 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
1858 rtx offset = const0_rtx;
1860 if (GET_CODE (op1) == CONST)
1861 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1863 if (GET_CODE (op1) == SYMBOL_REF)
1865 operands[2] = HALF_PIC_PTR (op1);
1868 mips_count_memory_refs (operands[2], 1);
1870 if (INTVAL (offset) == 0)
1873 ret = (unsignedp && TARGET_64BIT
1879 dslots_load_total++;
1880 operands[3] = offset;
1881 if (unsignedp && TARGET_64BIT)
1882 ret = (SMALL_INT (offset)
1883 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1884 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1886 ret = (SMALL_INT (offset)
1887 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1888 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1892 else if (TARGET_MIPS16
1894 && GET_CODE (XEXP (op1, 0)) == REG
1895 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
1897 /* This case arises on the mips16; see
1898 mips16_gp_pseudo_reg. */
1899 ret = "move\t%0,%+";
1901 else if (TARGET_MIPS16
1902 && code1 == SYMBOL_REF
1903 && SYMBOL_REF_FLAG (op1)
1904 && (XSTR (op1, 0)[0] != '*'
1905 || strncmp (XSTR (op1, 0) + 1,
1907 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
1909 /* This can occur when reloading the address of a GP
1910 relative symbol on the mips16. */
1911 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
1916 mips_count_memory_refs (op1, 1);
1922 else if (code1 == PLUS)
1924 rtx add_op0 = XEXP (op1, 0);
1925 rtx add_op1 = XEXP (op1, 1);
1927 if (GET_CODE (XEXP (op1, 1)) == REG
1928 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1929 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
1931 operands[2] = add_op0;
1932 operands[3] = add_op1;
1933 ret = "add%:\t%0,%2,%3";
1936 else if (code1 == HIGH)
1938 operands[1] = XEXP (op1, 0);
1939 ret = "lui\t%0,%%hi(%1)";
1943 else if (code0 == MEM)
1946 mips_count_memory_refs (op0, 1);
1950 int regno1 = REGNO (op1) + subreg_word1;
1952 if (GP_REG_P (regno1))
1956 case SFmode: ret = "sw\t%1,%0"; break;
1957 case SImode: ret = "sw\t%1,%0"; break;
1958 case HImode: ret = "sh\t%1,%0"; break;
1959 case QImode: ret = "sb\t%1,%0"; break;
1964 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
1968 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1972 case SFmode: ret = "sw\t%z1,%0"; break;
1973 case SImode: ret = "sw\t%z1,%0"; break;
1974 case HImode: ret = "sh\t%z1,%0"; break;
1975 case QImode: ret = "sb\t%z1,%0"; break;
1980 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
1984 case SFmode: ret = "sw\t%.,%0"; break;
1985 case SImode: ret = "sw\t%.,%0"; break;
1986 case HImode: ret = "sh\t%.,%0"; break;
1987 case QImode: ret = "sb\t%.,%0"; break;
1992 if (ret != 0 && MEM_VOLATILE_P (op0))
1994 size_t i = strlen (ret);
1996 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1999 sprintf (volatile_buffer, "%%{%s%%}", ret);
2000 ret = volatile_buffer;
2006 abort_with_insn (insn, "Bad move");
2010 if (delay != DELAY_NONE)
2011 return mips_fill_delay_slot (ret, delay, operands, insn);
2017 /* Return the appropriate instructions to move 2 words */
2020 mips_move_2words (operands, insn)
2025 rtx op0 = operands[0];
2026 rtx op1 = operands[1];
2027 enum rtx_code code0 = GET_CODE (operands[0]);
2028 enum rtx_code code1 = GET_CODE (operands[1]);
2029 int subreg_word0 = 0;
2030 int subreg_word1 = 0;
2031 enum delay_type delay = DELAY_NONE;
2033 while (code0 == SUBREG)
2035 subreg_word0 += SUBREG_WORD (op0);
2036 op0 = SUBREG_REG (op0);
2037 code0 = GET_CODE (op0);
2040 if (code1 == SIGN_EXTEND)
2042 op1 = XEXP (op1, 0);
2043 code1 = GET_CODE (op1);
2046 while (code1 == SUBREG)
2048 subreg_word1 += SUBREG_WORD (op1);
2049 op1 = SUBREG_REG (op1);
2050 code1 = GET_CODE (op1);
2054 if (GET_CODE (operands[1]) == SIGN_EXTEND
2056 && code1 != CONST_INT
2057 /* The following three can happen as the result of a questionable
2059 && code1 != LABEL_REF
2060 && code1 != SYMBOL_REF
2066 int regno0 = REGNO (op0) + subreg_word0;
2070 int regno1 = REGNO (op1) + subreg_word1;
2072 /* Just in case, don't do anything for assigning a register
2073 to itself, unless we are filling a delay slot. */
2074 if (regno0 == regno1 && set_nomacro == 0)
2077 else if (FP_REG_P (regno0))
2079 if (FP_REG_P (regno1))
2080 ret = "mov.d\t%0,%1";
2088 abort_with_insn (insn, "Bad move");
2090 #ifdef TARGET_FP_CALL_32
2091 if (FP_CALL_GP_REG_P (regno1))
2092 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2095 ret = "dmtc1\t%1,%0";
2098 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2102 else if (FP_REG_P (regno1))
2108 abort_with_insn (insn, "Bad move");
2110 #ifdef TARGET_FP_CALL_32
2111 if (FP_CALL_GP_REG_P (regno0))
2112 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2115 ret = "dmfc1\t%0,%1";
2118 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2121 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2126 if (regno0 != HILO_REGNUM)
2128 else if (regno1 == 0)
2129 ret = "mtlo\t%.\n\tmthi\t%.";
2132 ret = "mthi\t%M1\n\tmtlo\t%L1";
2135 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2140 if (regno1 != HILO_REGNUM)
2144 ret = "mfhi\t%M0\n\tmflo\t%L0";
2147 else if (TARGET_64BIT)
2148 ret = "move\t%0,%1";
2150 else if (regno0 != (regno1+1))
2151 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2154 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2157 else if (code1 == CONST_DOUBLE)
2159 /* Move zero from $0 unless !TARGET_64BIT and recipient
2160 is 64-bit fp reg, in which case generate a constant. */
2161 if (op1 != CONST0_RTX (GET_MODE (op1))
2162 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2164 if (GET_MODE (op1) == DFmode)
2168 #ifdef TARGET_FP_CALL_32
2169 if (FP_CALL_GP_REG_P (regno0))
2171 if (TARGET_FLOAT64 && !TARGET_64BIT)
2173 split_double (op1, operands + 2, operands + 3);
2174 ret = "li\t%0,%2\n\tli\t%D0,%3";
2177 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2181 ret = "li.d\t%0,%1";
2184 else if (TARGET_64BIT)
2186 if (! TARGET_MIPS16)
2192 split_double (op1, operands + 2, operands + 3);
2193 ret = "li\t%0,%2\n\tli\t%D0,%3";
2199 if (GP_REG_P (regno0))
2201 #ifdef TARGET_FP_CALL_32
2202 && ! FP_CALL_GP_REG_P (regno0)
2205 : "move\t%0,%.\n\tmove\t%D0,%.");
2207 else if (FP_REG_P (regno0))
2212 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2217 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2219 if (GP_REG_P (regno0))
2222 : "move\t%0,%.\n\tmove\t%D0,%.");
2224 else if (FP_REG_P (regno0))
2231 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2233 else if (MD_REG_P (regno0))
2236 ret = (regno0 == HILO_REGNUM
2237 ? "mtlo\t%.\n\tmthi\t%."
2242 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2243 && GP_REG_P (regno0))
2249 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2251 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2252 ret = "li\t%0,%n1\n\tneg\t%0";
2254 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2255 ret = "li\t%0,%1\t\t# %X1";
2256 else if (HOST_BITS_PER_WIDE_INT < 64)
2257 /* We can't use 'X' for negative numbers, because then we won't
2258 get the right value for the upper 32 bits. */
2259 ret = (INTVAL (op1) < 0
2260 ? "dli\t%0,%1\t\t\t# %X1"
2261 : "dli\t%0,%X1\t\t# %1");
2263 /* We must use 'X', because otherwise LONG_MIN will print as
2264 a number that the assembler won't accept. */
2265 ret = "dli\t%0,%X1\t\t# %1";
2267 else if (HOST_BITS_PER_WIDE_INT < 64)
2269 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2272 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2273 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2274 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2276 operands[2] = GEN_INT (1);
2277 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2281 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2285 /* We use multiple shifts here, to avoid warnings about out
2286 of range shifts on 32 bit hosts. */
2287 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2289 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2290 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2294 else if (code1 == MEM)
2299 mips_count_memory_refs (op1, 2);
2301 if (FP_REG_P (regno0))
2304 else if (TARGET_64BIT)
2307 #ifdef TARGET_FP_CALL_32
2308 if (FP_CALL_GP_REG_P (regno0))
2309 ret = (double_memory_operand (op1, GET_MODE (op1))
2310 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2311 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2317 else if (double_memory_operand (op1, GET_MODE (op1)))
2319 operands[2] = adj_offsettable_operand (op1, 4);
2320 ret = (reg_mentioned_p (op0, op1)
2321 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2322 : "lw\t%0,%1\n\tlw\t%D0,%2");
2325 if (ret != 0 && MEM_VOLATILE_P (op1))
2327 size_t i = strlen (ret);
2329 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2332 sprintf (volatile_buffer, "%%{%s%%}", ret);
2333 ret = volatile_buffer;
2337 else if (code1 == LABEL_REF)
2340 mips_count_memory_refs (op1, 2);
2342 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2343 /* We deliberately remove the 'a' from '%1', so that we don't
2344 have to add SIGN_EXTEND support to print_operand_address.
2345 print_operand will just call print_operand_address in this
2346 case, so there is no problem. */
2349 ret = "dla\t%0,%a1";
2351 else if (code1 == SYMBOL_REF || code1 == CONST)
2355 && GET_CODE (XEXP (op1, 0)) == REG
2356 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2358 /* This case arises on the mips16; see
2359 mips16_gp_pseudo_reg. */
2360 ret = "move\t%0,%+";
2362 else if (TARGET_MIPS16
2363 && code1 == SYMBOL_REF
2364 && SYMBOL_REF_FLAG (op1)
2365 && (XSTR (op1, 0)[0] != '*'
2366 || strncmp (XSTR (op1, 0) + 1,
2368 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2370 /* This can occur when reloading the address of a GP
2371 relative symbol on the mips16. */
2372 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2377 mips_count_memory_refs (op1, 2);
2379 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2380 /* We deliberately remove the 'a' from '%1', so that we don't
2381 have to add SIGN_EXTEND support to print_operand_address.
2382 print_operand will just call print_operand_address in this
2383 case, so there is no problem. */
2386 ret = "dla\t%0,%a1";
2391 else if (code0 == MEM)
2395 int regno1 = REGNO (op1) + subreg_word1;
2397 if (FP_REG_P (regno1))
2400 else if (TARGET_64BIT)
2403 #ifdef TARGET_FP_CALL_32
2404 if (FP_CALL_GP_REG_P (regno1))
2405 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2411 else if (double_memory_operand (op0, GET_MODE (op0)))
2413 operands[2] = adj_offsettable_operand (op0, 4);
2414 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2418 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2419 || (code1 == CONST_DOUBLE
2420 && op1 == CONST0_RTX (GET_MODE (op1))))
2422 || double_memory_operand (op0, GET_MODE (op0))))
2428 operands[2] = adj_offsettable_operand (op0, 4);
2429 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2434 mips_count_memory_refs (op0, 2);
2436 if (ret != 0 && MEM_VOLATILE_P (op0))
2438 size_t i = strlen (ret);
2440 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2443 sprintf (volatile_buffer, "%%{%s%%}", ret);
2444 ret = volatile_buffer;
2450 abort_with_insn (insn, "Bad move");
2454 if (delay != DELAY_NONE)
2455 return mips_fill_delay_slot (ret, delay, operands, insn);
2460 /* Provide the costs of an addressing mode that contains ADDR.
2461 If ADDR is not a valid address, its cost is irrelevant. */
2464 mips_address_cost (addr)
2467 switch (GET_CODE (addr))
2477 rtx offset = const0_rtx;
2478 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2479 if (GET_CODE (addr) == LABEL_REF)
2482 if (GET_CODE (addr) != SYMBOL_REF)
2485 if (! SMALL_INT (offset))
2489 /* ... fall through ... */
2492 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2496 register rtx plus0 = XEXP (addr, 0);
2497 register rtx plus1 = XEXP (addr, 1);
2499 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2500 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2502 if (GET_CODE (plus0) != REG)
2505 switch (GET_CODE (plus1))
2508 return SMALL_INT (plus1) ? 1 : 2;
2515 return mips_address_cost (plus1) + 1;
2529 /* Return nonzero if X is an address which needs a temporary register when
2530 reloaded while generating PIC code. */
2533 pic_address_needs_scratch (x)
2536 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2537 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2538 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2539 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2540 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2546 /* Make normal rtx_code into something we can index from an array */
2548 static enum internal_test
2549 map_test_to_internal_test (test_code)
2550 enum rtx_code test_code;
2552 enum internal_test test = ITEST_MAX;
2556 case EQ: test = ITEST_EQ; break;
2557 case NE: test = ITEST_NE; break;
2558 case GT: test = ITEST_GT; break;
2559 case GE: test = ITEST_GE; break;
2560 case LT: test = ITEST_LT; break;
2561 case LE: test = ITEST_LE; break;
2562 case GTU: test = ITEST_GTU; break;
2563 case GEU: test = ITEST_GEU; break;
2564 case LTU: test = ITEST_LTU; break;
2565 case LEU: test = ITEST_LEU; break;
2573 /* Generate the code to compare two integer values. The return value is:
2574 (reg:SI xx) The pseudo register the comparison is in
2575 0 No register, generate a simple branch.
2577 ??? This is called with result nonzero by the Scond patterns in
2578 mips.md. These patterns are called with a target in the mode of
2579 the Scond instruction pattern. Since this must be a constant, we
2580 must use SImode. This means that if RESULT is non-zero, it will
2581 always be an SImode register, even if TARGET_64BIT is true. We
2582 cope with this by calling convert_move rather than emit_move_insn.
2583 This will sometimes lead to an unnecessary extension of the result;
2595 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2596 enum rtx_code test_code; /* relational test (EQ, etc) */
2597 rtx result; /* result to store comp. or 0 if branch */
2598 rtx cmp0; /* first operand to compare */
2599 rtx cmp1; /* second operand to compare */
2600 int *p_invert; /* NULL or ptr to hold whether branch needs */
2601 /* to reverse its test */
2605 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2606 int const_low; /* low bound of constant we can accept */
2607 int const_high; /* high bound of constant we can accept */
2608 int const_add; /* constant to add (convert LE -> LT) */
2609 int reverse_regs; /* reverse registers in test */
2610 int invert_const; /* != 0 if invert value if cmp1 is constant */
2611 int invert_reg; /* != 0 if invert value if cmp1 is register */
2612 int unsignedp; /* != 0 for unsigned comparisons. */
2615 static struct cmp_info info[ (int)ITEST_MAX ] = {
2617 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2618 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2619 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2620 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2621 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2622 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2623 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2624 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2625 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2626 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2629 enum internal_test test;
2630 enum machine_mode mode;
2631 struct cmp_info *p_info;
2638 test = map_test_to_internal_test (test_code);
2639 if (test == ITEST_MAX)
2642 p_info = &info[(int) test];
2643 eqne_p = (p_info->test_code == XOR);
2645 mode = GET_MODE (cmp0);
2646 if (mode == VOIDmode)
2647 mode = GET_MODE (cmp1);
2649 /* Eliminate simple branches */
2650 branch_p = (result == 0);
2653 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2655 /* Comparisons against zero are simple branches */
2656 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2657 && (! TARGET_MIPS16 || eqne_p))
2660 /* Test for beq/bne. */
2661 if (eqne_p && ! TARGET_MIPS16)
2665 /* allocate a pseudo to calculate the value in. */
2666 result = gen_reg_rtx (mode);
2669 /* Make sure we can handle any constants given to us. */
2670 if (GET_CODE (cmp0) == CONST_INT)
2671 cmp0 = force_reg (mode, cmp0);
2673 if (GET_CODE (cmp1) == CONST_INT)
2675 HOST_WIDE_INT value = INTVAL (cmp1);
2677 if (value < p_info->const_low
2678 || value > p_info->const_high
2679 /* ??? Why? And why wasn't the similar code below modified too? */
2681 && HOST_BITS_PER_WIDE_INT < 64
2682 && p_info->const_add != 0
2683 && ((p_info->unsignedp
2684 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2686 : (value + p_info->const_add) > INTVAL (cmp1))
2687 != (p_info->const_add > 0))))
2688 cmp1 = force_reg (mode, cmp1);
2691 /* See if we need to invert the result. */
2692 invert = (GET_CODE (cmp1) == CONST_INT
2693 ? p_info->invert_const : p_info->invert_reg);
2695 if (p_invert != (int *)0)
2701 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2702 Comparison between two registers, may involve switching operands. */
2703 if (GET_CODE (cmp1) == CONST_INT)
2705 if (p_info->const_add != 0)
2707 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2709 /* If modification of cmp1 caused overflow,
2710 we would get the wrong answer if we follow the usual path;
2711 thus, x > 0xffffffffU would turn into x > 0U. */
2712 if ((p_info->unsignedp
2713 ? (unsigned HOST_WIDE_INT) new > INTVAL (cmp1)
2714 : new > INTVAL (cmp1))
2715 != (p_info->const_add > 0))
2717 /* This test is always true, but if INVERT is true then
2718 the result of the test needs to be inverted so 0 should
2719 be returned instead. */
2720 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2724 cmp1 = GEN_INT (new);
2728 else if (p_info->reverse_regs)
2735 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2739 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2740 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2743 if (test == ITEST_NE)
2745 if (! TARGET_MIPS16)
2747 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2752 reg2 = invert ? gen_reg_rtx (mode) : result;
2753 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2758 else if (test == ITEST_EQ)
2760 reg2 = invert ? gen_reg_rtx (mode) : result;
2761 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2769 if (! TARGET_MIPS16)
2773 /* The value is in $24. Copy it to another register, so
2774 that reload doesn't think it needs to store the $24 and
2775 the input to the XOR in the same location. */
2776 reg2 = gen_reg_rtx (mode);
2777 emit_move_insn (reg2, reg);
2779 one = force_reg (mode, const1_rtx);
2781 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
2787 /* Emit the common code for doing conditional branches.
2788 operand[0] is the label to jump to.
2789 The comparison operands are saved away by cmp{si,di,sf,df}. */
2792 gen_conditional_branch (operands, test_code)
2794 enum rtx_code test_code;
2796 enum cmp_type type = branch_type;
2797 rtx cmp0 = branch_cmp[0];
2798 rtx cmp1 = branch_cmp[1];
2799 enum machine_mode mode;
2808 mode = type == CMP_SI ? SImode : DImode;
2810 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
2818 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
2819 /* We don't want to build a comparison against a non-zero
2821 cmp1 = force_reg (mode, cmp1);
2828 reg = gen_rtx (REG, CCmode, FPSW_REGNUM);
2830 reg = gen_reg_rtx (CCmode);
2832 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2833 0 in the instruction built below. The MIPS FPU handles
2834 inequality testing by testing for equality and looking for a
2836 emit_insn (gen_rtx (SET, VOIDmode, reg,
2837 gen_rtx (test_code == NE ? EQ : test_code,
2838 CCmode, cmp0, cmp1)));
2840 test_code = test_code == NE ? EQ : NE;
2848 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
2851 /* Generate the branch. */
2853 label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
2862 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2863 gen_rtx (IF_THEN_ELSE, VOIDmode,
2864 gen_rtx (test_code, mode, cmp0, cmp1),
2868 /* Emit the common code for conditional moves. OPERANDS is the array
2869 of operands passed to the conditional move defined_expand. */
2872 gen_conditional_move (operands)
2875 rtx op0 = branch_cmp[0];
2876 rtx op1 = branch_cmp[1];
2877 enum machine_mode mode = GET_MODE (branch_cmp[0]);
2878 enum rtx_code cmp_code = GET_CODE (operands[1]);
2879 enum rtx_code move_code = NE;
2880 enum machine_mode op_mode = GET_MODE (operands[0]);
2881 enum machine_mode cmp_mode;
2884 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
2903 op0 = force_reg (mode, branch_cmp[1]);
2904 op1 = branch_cmp[0];
2908 op0 = force_reg (mode, branch_cmp[1]);
2909 op1 = branch_cmp[0];
2920 op0 = force_reg (mode, branch_cmp[1]);
2921 op1 = branch_cmp[0];
2925 op0 = force_reg (mode, branch_cmp[1]);
2926 op1 = branch_cmp[0];
2933 else if (cmp_code == NE)
2934 cmp_code = EQ, move_code = EQ;
2936 if (mode == SImode || mode == DImode)
2938 else if (mode == SFmode || mode == DFmode)
2943 cmp_reg = gen_reg_rtx (cmp_mode);
2944 emit_insn (gen_rtx (SET, cmp_mode, cmp_reg,
2945 gen_rtx (cmp_code, cmp_mode, op0, op1)));
2947 emit_insn (gen_rtx (SET, op_mode, operands[0],
2948 gen_rtx (IF_THEN_ELSE, op_mode,
2949 gen_rtx (move_code, VOIDmode,
2950 cmp_reg, CONST0_RTX (SImode)),
2951 operands[2], operands[3])));
2954 /* Write a loop to move a constant number of bytes.
2955 Generate load/stores as follows:
2961 temp<last> = src[MAX_MOVE_REGS-1];
2965 dest[MAX_MOVE_REGS-1] = temp<last>;
2966 src += MAX_MOVE_REGS;
2967 dest += MAX_MOVE_REGS;
2968 } while (src != final);
2970 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2971 registers are needed.
2973 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2974 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2975 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2977 #define MAX_MOVE_REGS 4
2978 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2981 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
2982 rtx dest_reg; /* register holding destination address */
2983 rtx src_reg; /* register holding source address */
2984 int bytes; /* # bytes to move */
2985 int align; /* alignment */
2986 rtx orig_dest; /* original dest for change_address */
2987 rtx orig_src; /* original source for making a reg note */
2989 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
2990 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
2991 rtx align_rtx = GEN_INT (align);
2997 if (bytes < 2 * MAX_MOVE_BYTES)
3000 leftover = bytes % MAX_MOVE_BYTES;
3003 label = gen_label_rtx ();
3004 final_src = gen_reg_rtx (Pmode);
3005 bytes_rtx = GEN_INT (bytes);
3009 if (Pmode == DImode)
3011 emit_insn (gen_movdi (final_src, bytes_rtx));
3012 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3016 emit_insn (gen_movsi (final_src, bytes_rtx));
3017 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3022 if (Pmode == DImode)
3023 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3025 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3030 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3031 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3033 if (Pmode == DImode)
3035 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3036 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3037 emit_insn (gen_cmpdi (src_reg, final_src));
3041 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3042 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3043 emit_insn (gen_cmpsi (src_reg, final_src));
3046 emit_jump_insn (gen_bne (label));
3049 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3053 /* Use a library function to move some bytes. */
3056 block_move_call (dest_reg, src_reg, bytes_rtx)
3061 /* We want to pass the size as Pmode, which will normally be SImode
3062 but will be DImode if we are using 64 bit longs and pointers. */
3063 if (GET_MODE (bytes_rtx) != VOIDmode
3064 && GET_MODE (bytes_rtx) != Pmode)
3065 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3067 #ifdef TARGET_MEM_FUNCTIONS
3068 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
3069 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3070 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3071 TREE_UNSIGNED (sizetype)),
3072 TYPE_MODE (sizetype));
3074 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
3075 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3076 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3077 TREE_UNSIGNED (integer_type_node)),
3078 TYPE_MODE (integer_type_node));
3082 /* Expand string/block move operations.
3084 operands[0] is the pointer to the destination.
3085 operands[1] is the pointer to the source.
3086 operands[2] is the number of bytes to move.
3087 operands[3] is the alignment. */
3090 expand_block_move (operands)
3093 rtx bytes_rtx = operands[2];
3094 rtx align_rtx = operands[3];
3095 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3096 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3097 int align = INTVAL (align_rtx);
3098 rtx orig_src = operands[1];
3099 rtx orig_dest = operands[0];
3103 if (constp && bytes <= 0)
3106 if (align > UNITS_PER_WORD)
3107 align = UNITS_PER_WORD;
3109 /* Move the address into scratch registers. */
3110 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3111 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3114 block_move_call (dest_reg, src_reg, bytes_rtx);
3116 else if (constp && bytes <= 2 * MAX_MOVE_BYTES)
3117 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3119 change_address (orig_src, BLKmode,
3121 bytes_rtx, align_rtx));
3123 else if (constp && align >= UNITS_PER_WORD && optimize)
3124 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3126 else if (constp && optimize)
3128 /* If the alignment is not word aligned, generate a test at
3129 runtime, to see whether things wound up aligned, and we
3130 can use the faster lw/sw instead ulw/usw. */
3132 rtx temp = gen_reg_rtx (Pmode);
3133 rtx aligned_label = gen_label_rtx ();
3134 rtx join_label = gen_label_rtx ();
3135 int leftover = bytes % MAX_MOVE_BYTES;
3139 if (Pmode == DImode)
3141 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3142 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3143 emit_insn (gen_cmpdi (temp, const0_rtx));
3147 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3148 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3149 emit_insn (gen_cmpsi (temp, const0_rtx));
3152 emit_jump_insn (gen_beq (aligned_label));
3154 /* Unaligned loop. */
3155 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3156 emit_jump_insn (gen_jump (join_label));
3160 emit_label (aligned_label);
3161 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3163 emit_label (join_label);
3165 /* Bytes at the end of the loop. */
3167 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3169 change_address (orig_src, BLKmode,
3176 block_move_call (dest_reg, src_reg, bytes_rtx);
3179 /* Emit load/stores for a small constant block_move.
3181 operands[0] is the memory address of the destination.
3182 operands[1] is the memory address of the source.
3183 operands[2] is the number of bytes to move.
3184 operands[3] is the alignment.
3185 operands[4] is a temp register.
3186 operands[5] is a temp register.
3188 operands[3+num_regs] is the last temp register.
3190 The block move type can be one of the following:
3191 BLOCK_MOVE_NORMAL Do all of the block move.
3192 BLOCK_MOVE_NOT_LAST Do all but the last store.
3193 BLOCK_MOVE_LAST Do just the last store. */
3196 output_block_move (insn, operands, num_regs, move_type)
3200 enum block_move_type move_type;
3202 rtx dest_reg = XEXP (operands[0], 0);
3203 rtx src_reg = XEXP (operands[1], 0);
3204 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3205 int align = INTVAL (operands[3]);
3208 int use_lwl_lwr = 0;
3209 int last_operand = num_regs + 4;
3215 char *load; /* load insn without nop */
3216 char *load_nop; /* load insn with trailing nop */
3217 char *store; /* store insn */
3218 char *final; /* if last_store used: NULL or swr */
3219 char *last_store; /* last store instruction */
3220 int offset; /* current offset */
3221 enum machine_mode mode; /* mode to use on (MEM) */
3224 /* ??? Detect a bug in GCC, where it can give us a register
3225 the same as one of the addressing registers and reduce
3226 the number of registers available. */
3229 && safe_regs < (sizeof(xoperands) / sizeof(xoperands[0]));
3231 if (! reg_mentioned_p (operands[i], operands[0])
3232 && ! reg_mentioned_p (operands[i], operands[1]))
3233 xoperands[safe_regs++] = operands[i];
3235 if (safe_regs < last_operand)
3237 xoperands[0] = operands[0];
3238 xoperands[1] = operands[1];
3239 xoperands[2] = operands[2];
3240 xoperands[3] = operands[3];
3241 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3244 /* If we are given global or static addresses, and we would be
3245 emitting a few instructions, try to save time by using a
3246 temporary register for the pointer. */
3247 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3248 an ldl/ldr instruction pair. We play it safe, and always move
3249 constant addresses into registers when generating N32/N64 code, just
3250 in case we might emit an unaligned load instruction. */
3251 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3252 || mips_abi == ABI_N32 || mips_abi == ABI_64))
3254 if (CONSTANT_P (src_reg))
3257 mips_count_memory_refs (operands[1], 1);
3259 src_reg = operands[3 + num_regs--];
3260 if (move_type != BLOCK_MOVE_LAST)
3262 xoperands[1] = operands[1];
3263 xoperands[0] = src_reg;
3264 if (Pmode == DImode)
3265 output_asm_insn ("dla\t%0,%1", xoperands);
3267 output_asm_insn ("la\t%0,%1", xoperands);
3271 if (CONSTANT_P (dest_reg))
3274 mips_count_memory_refs (operands[0], 1);
3276 dest_reg = operands[3 + num_regs--];
3277 if (move_type != BLOCK_MOVE_LAST)
3279 xoperands[1] = operands[0];
3280 xoperands[0] = dest_reg;
3281 if (Pmode == DImode)
3282 output_asm_insn ("dla\t%0,%1", xoperands);
3284 output_asm_insn ("la\t%0,%1", xoperands);
3289 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3290 are not offsettable, however, offsettable_address_p says they are
3291 offsettable. I think this is a bug in offsettable_address_p.
3292 For expediency, we fix this by just loading the address into a register
3293 if we happen to get one. */
3295 if (GET_CODE (src_reg) == LO_SUM)
3297 src_reg = operands[3 + num_regs--];
3298 if (move_type != BLOCK_MOVE_LAST)
3300 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3301 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3302 xoperands[0] = src_reg;
3303 if (Pmode == DImode)
3304 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3306 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3310 if (GET_CODE (dest_reg) == LO_SUM)
3312 dest_reg = operands[3 + num_regs--];
3313 if (move_type != BLOCK_MOVE_LAST)
3315 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3316 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3317 xoperands[0] = dest_reg;
3318 if (Pmode == DImode)
3319 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3321 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3325 if (num_regs > sizeof (load_store) / sizeof (load_store[0]))
3326 num_regs = sizeof (load_store) / sizeof (load_store[0]);
3328 else if (num_regs < 1)
3329 abort_with_insn (insn,
3330 "Cannot do block move, not enough scratch registers");
3334 load_store[num].offset = offset;
3336 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3338 load_store[num].load = "ld\t%0,%1";
3339 load_store[num].load_nop = "ld\t%0,%1%#";
3340 load_store[num].store = "sd\t%0,%1";
3341 load_store[num].last_store = "sd\t%0,%1";
3342 load_store[num].final = 0;
3343 load_store[num].mode = DImode;
3348 /* ??? Fails because of a MIPS assembler bug? */
3349 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3351 if (BYTES_BIG_ENDIAN)
3353 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3354 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3355 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3356 load_store[num].last_store = "sdr\t%0,%2";
3357 load_store[num].final = "sdl\t%0,%1";
3361 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3362 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3363 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3364 load_store[num].last_store = "sdr\t%0,%1";
3365 load_store[num].final = "sdl\t%0,%2";
3368 load_store[num].mode = DImode;
3374 else if (bytes >= 4 && align >= 4)
3376 load_store[num].load = "lw\t%0,%1";
3377 load_store[num].load_nop = "lw\t%0,%1%#";
3378 load_store[num].store = "sw\t%0,%1";
3379 load_store[num].last_store = "sw\t%0,%1";
3380 load_store[num].final = 0;
3381 load_store[num].mode = SImode;
3386 else if (bytes >= 4 && ! TARGET_MIPS16)
3388 if (BYTES_BIG_ENDIAN)
3390 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3391 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3392 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3393 load_store[num].last_store = "swr\t%0,%2";
3394 load_store[num].final = "swl\t%0,%1";
3398 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3399 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3400 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3401 load_store[num].last_store = "swr\t%0,%1";
3402 load_store[num].final = "swl\t%0,%2";
3405 load_store[num].mode = SImode;
3411 else if (bytes >= 2 && align >= 2)
3413 load_store[num].load = "lh\t%0,%1";
3414 load_store[num].load_nop = "lh\t%0,%1%#";
3415 load_store[num].store = "sh\t%0,%1";
3416 load_store[num].last_store = "sh\t%0,%1";
3417 load_store[num].final = 0;
3418 load_store[num].mode = HImode;
3424 load_store[num].load = "lb\t%0,%1";
3425 load_store[num].load_nop = "lb\t%0,%1%#";
3426 load_store[num].store = "sb\t%0,%1";
3427 load_store[num].last_store = "sb\t%0,%1";
3428 load_store[num].final = 0;
3429 load_store[num].mode = QImode;
3434 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3436 dslots_load_total++;
3437 dslots_load_filled++;
3439 if (CONSTANT_P (src_reg))
3440 mips_count_memory_refs (src_reg, 1);
3442 if (CONSTANT_P (dest_reg))
3443 mips_count_memory_refs (dest_reg, 1);
3446 /* Emit load/stores now if we have run out of registers or are
3447 at the end of the move. */
3449 if (++num == num_regs || bytes == 0)
3451 /* If only load/store, we need a NOP after the load. */
3454 load_store[0].load = load_store[0].load_nop;
3455 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3456 dslots_load_filled--;
3459 if (move_type != BLOCK_MOVE_LAST)
3461 for (i = 0; i < num; i++)
3465 if (!operands[i + 4])
3468 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3469 operands[i + 4] = gen_rtx (REG, load_store[i].mode,
3470 REGNO (operands[i + 4]));
3472 offset = load_store[i].offset;
3473 xoperands[0] = operands[i + 4];
3474 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
3475 plus_constant (src_reg, offset));
3480 = GET_MODE_SIZE (load_store[i].mode) - 1;
3482 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
3483 plus_constant (src_reg,
3488 output_asm_insn (load_store[i].load, xoperands);
3492 for (i = 0; i < num; i++)
3494 int last_p = (i == num-1 && bytes == 0);
3495 int offset = load_store[i].offset;
3497 xoperands[0] = operands[i + 4];
3498 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
3499 plus_constant (dest_reg, offset));
3504 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3505 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
3506 plus_constant (dest_reg,
3511 if (move_type == BLOCK_MOVE_NORMAL)
3512 output_asm_insn (load_store[i].store, xoperands);
3514 else if (move_type == BLOCK_MOVE_NOT_LAST)
3517 output_asm_insn (load_store[i].store, xoperands);
3519 else if (load_store[i].final != 0)
3520 output_asm_insn (load_store[i].final, xoperands);
3524 output_asm_insn (load_store[i].last_store, xoperands);
3527 num = 0; /* reset load_store */
3535 /* Argument support functions. */
3537 /* Initialize CUMULATIVE_ARGS for a function. */
3540 init_cumulative_args (cum, fntype, libname)
3541 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3542 tree fntype; /* tree ptr for function decl */
3543 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3545 static CUMULATIVE_ARGS zero_cum;
3546 tree param, next_param;
3548 if (TARGET_DEBUG_E_MODE)
3551 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3554 fputc ('\n', stderr);
3558 tree ret_type = TREE_TYPE (fntype);
3559 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3560 tree_code_name[(int)TREE_CODE (fntype)],
3561 tree_code_name[(int)TREE_CODE (ret_type)]);
3567 /* Determine if this function has variable arguments. This is
3568 indicated by the last argument being 'void_type_mode' if there
3569 are no variable arguments. The standard MIPS calling sequence
3570 passes all arguments in the general purpose registers in this case. */
3572 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3573 param != 0; param = next_param)
3575 next_param = TREE_CHAIN (param);
3576 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3577 cum->gp_reg_found = 1;
3581 /* Advance the argument to the next argument position. */
3584 function_arg_advance (cum, mode, type, named)
3585 CUMULATIVE_ARGS *cum; /* current arg information */
3586 enum machine_mode mode; /* current arg mode */
3587 tree type; /* type of the argument or 0 if lib support */
3588 int named; /* whether or not the argument was named */
3590 if (TARGET_DEBUG_E_MODE)
3593 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3594 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3595 GET_MODE_NAME (mode));
3596 fprintf (stderr, HOST_PTR_PRINTF, type);
3597 fprintf (stderr, ", %d )\n\n", named);
3607 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3608 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3611 cum->gp_reg_found = 1;
3612 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3617 cum->gp_reg_found = 1;
3618 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3623 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3624 cum->fp_arg_words++;
3627 if (! cum->gp_reg_found && cum->arg_number <= 2)
3628 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3632 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3633 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3635 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3636 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3637 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3641 cum->gp_reg_found = 1;
3642 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3648 cum->gp_reg_found = 1;
3654 /* Return an RTL expression containing the register for the given mode,
3655 or 0 if the argument is to be passed on the stack. */
3658 function_arg (cum, mode, type, named)
3659 CUMULATIVE_ARGS *cum; /* current arg information */
3660 enum machine_mode mode; /* current arg mode */
3661 tree type; /* type of the argument or 0 if lib support */
3662 int named; /* != 0 for normal args, == 0 for ... args */
3667 int *arg_words = &cum->arg_words;
3668 int struct_p = (type != 0
3669 && (TREE_CODE (type) == RECORD_TYPE
3670 || TREE_CODE (type) == UNION_TYPE
3671 || TREE_CODE (type) == QUAL_UNION_TYPE));
3673 if (TARGET_DEBUG_E_MODE)
3676 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3677 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3678 GET_MODE_NAME (mode));
3679 fprintf (stderr, HOST_PTR_PRINTF, type);
3680 fprintf (stderr, ", %d ) = ", named);
3684 cum->last_arg_fp = 0;
3688 if (mips_abi == ABI_32)
3690 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3691 regbase = GP_ARG_FIRST;
3694 regbase = FP_ARG_FIRST;
3696 /* If the first arg was a float in a floating point register,
3697 then set bias to align this float arg properly. */
3698 if (cum->arg_words == 1)
3702 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3705 cum->fp_arg_words += cum->fp_arg_words & 1;
3706 cum->last_arg_fp = 1;
3707 arg_words = &cum->fp_arg_words;
3708 regbase = FP_ARG_FIRST;
3711 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3717 if (mips_abi == ABI_EABI
3718 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3719 cum->fp_arg_words += cum->fp_arg_words & 1;
3721 cum->arg_words += cum->arg_words & 1;
3724 if (mips_abi == ABI_32)
3725 regbase = ((cum->gp_reg_found
3726 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
3727 || cum->arg_number >= 2)
3728 ? GP_ARG_FIRST : FP_ARG_FIRST);
3729 else if (mips_abi == ABI_EABI
3730 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3732 cum->last_arg_fp = 1;
3733 arg_words = &cum->fp_arg_words;
3734 regbase = FP_ARG_FIRST;
3737 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3738 ? GP_ARG_FIRST : FP_ARG_FIRST);
3742 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3743 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3746 /* Drops through. */
3748 if (type != (tree)0 && TYPE_ALIGN (type) > BITS_PER_WORD
3749 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3750 cum->arg_words += (cum->arg_words & 1);
3751 regbase = GP_ARG_FIRST;
3758 regbase = GP_ARG_FIRST;
3763 cum->arg_words += (cum->arg_words & 1);
3764 regbase = GP_ARG_FIRST;
3767 if (*arg_words >= MAX_ARGS_IN_REGISTERS)
3769 if (TARGET_DEBUG_E_MODE)
3770 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
3779 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
3780 || mips_abi == ABI_EABI || ! named)
3781 ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
3784 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3785 structure contains a double in its entirety, then that 64 bit
3786 chunk is passed in a floating point register. */
3789 /* First check to see if there is any such field. */
3790 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3791 if (TREE_CODE (field) == FIELD_DECL
3792 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3793 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3794 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3795 % BITS_PER_WORD == 0))
3798 /* If the whole struct fits a DFmode register,
3799 we don't need the PARALLEL. */
3800 if (! field || mode == DFmode)
3801 ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
3804 /* Now handle the special case by returning a PARALLEL
3805 indicating where each 64 bit chunk goes. */
3811 /* ??? If this is a packed structure, then the last hunk won't
3814 chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
3815 if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
3816 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
3818 /* assign_parms checks the mode of ENTRY_PARM, so we must
3819 use the actual mode here. */
3820 ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks));
3823 regno = regbase + *arg_words + bias;
3824 field = TYPE_FIELDS (type);
3825 for (i = 0; i < chunks; i++)
3829 for (; field; field = TREE_CHAIN (field))
3830 if (TREE_CODE (field) == FIELD_DECL
3831 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3836 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
3837 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3838 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3839 reg = gen_rtx (REG, DFmode,
3840 regno + FP_ARG_FIRST - GP_ARG_FIRST);
3842 reg = gen_rtx (REG, word_mode, regno);
3845 = gen_rtx (EXPR_LIST, VOIDmode, reg,
3846 GEN_INT (bitpos / BITS_PER_UNIT));
3854 if (TARGET_DEBUG_E_MODE)
3855 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
3856 struct_p ? ", [struct]" : "");
3858 /* The following is a hack in order to pass 1 byte structures
3859 the same way that the MIPS compiler does (namely by passing
3860 the structure in the high byte or half word of the register).
3861 This also makes varargs work. If we have such a structure,
3862 we save the adjustment RTL, and the call define expands will
3863 emit them. For the VOIDmode argument (argument after the
3864 last real argument), pass back a parallel vector holding each
3865 of the adjustments. */
3867 /* ??? function_arg can be called more than once for each argument.
3868 As a result, we compute more adjustments than we need here.
3869 See the CUMULATIVE_ARGS definition in mips.h. */
3871 /* ??? This scheme requires everything smaller than the word size to
3872 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3873 that would mean every int needs to be shifted left, which is very
3874 inefficient. Let's not carry this compatibility to the 64 bit
3875 calling convention for now. */
3877 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
3878 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3880 rtx amount = GEN_INT (BITS_PER_WORD
3881 - int_size_in_bytes (type) * BITS_PER_UNIT);
3882 rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias);
3885 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
3887 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
3891 /* We will be called with a mode of VOIDmode after the last argument
3892 has been seen. Whatever we return will be passed to the call
3893 insn. If we need any shifts for small structures, return them in
3894 a PARALLEL; in that case, stuff the mips16 fp_code in as the
3895 mode. Otherwise, if we have need a mips16 fp_code, return a REG
3896 with the code stored as the mode. */
3897 if (mode == VOIDmode)
3899 if (cum->num_adjusts > 0)
3900 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
3901 gen_rtvec_v (cum->num_adjusts, cum->adjust));
3902 else if (TARGET_MIPS16 && cum->fp_code != 0)
3903 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
3910 function_arg_partial_nregs (cum, mode, type, named)
3911 CUMULATIVE_ARGS *cum; /* current arg information */
3912 enum machine_mode mode; /* current arg mode */
3913 tree type; /* type of the argument or 0 if lib support */
3914 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
3916 if ((mode == BLKmode
3917 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3918 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3919 && cum->arg_words < MAX_ARGS_IN_REGISTERS
3920 && mips_abi != ABI_EABI)
3923 if (mode == BLKmode)
3924 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3927 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3929 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
3930 return 0; /* structure fits in registers */
3932 if (TARGET_DEBUG_E_MODE)
3933 fprintf (stderr, "function_arg_partial_nregs = %d\n",
3934 MAX_ARGS_IN_REGISTERS - cum->arg_words);
3936 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
3939 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
3940 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3942 if (TARGET_DEBUG_E_MODE)
3943 fprintf (stderr, "function_arg_partial_nregs = 1\n");
3951 /* Abort after printing out a specific insn. */
3954 abort_with_insn (insn, reason)
3963 /* Write a message to stderr (for use in macros expanded in files that do not
3964 include stdio.h). */
3970 fprintf (stderr, s, s1, s2);
3973 /* Set up the threshold for data to go into the small data area, instead
3974 of the normal data area, and detect any conflicts in the switches. */
3979 register int i, start;
3981 register enum machine_mode mode;
3983 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
3985 if (mips_section_threshold <= 0)
3986 target_flags &= ~MASK_GPOPT;
3988 target_flags |= MASK_GPOPT;
3990 #ifndef MIPS_ISA_DEFAULT
3991 #define MIPS_ISA_DEFAULT 1
3994 /* If both single-float and soft-float are set, then clear the one that
3995 was set by TARGET_DEFAULT, leaving the one that was set by the
3996 user. We assume here that the specs prevent both being set by the
3998 #ifdef TARGET_DEFAULT
3999 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4000 target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT));
4003 /* Get the architectural level. */
4004 if (mips_isa_string == 0)
4005 mips_isa = MIPS_ISA_DEFAULT;
4007 else if (ISDIGIT (*mips_isa_string))
4009 mips_isa = atoi (mips_isa_string);
4012 /* -mno-mips16 overrides -mips16. */
4013 if (mips_no_mips16_string == NULL)
4015 target_flags |= MASK_MIPS16;
4019 mips_isa = MIPS_ISA_DEFAULT;
4023 mips_isa = MIPS_ISA_DEFAULT;
4026 else if (mips_isa < 1 || mips_isa > 4)
4028 error ("-mips%d not supported", mips_isa);
4035 error ("bad value (%s) for -mips switch", mips_isa_string);
4039 #ifdef MIPS_ABI_DEFAULT
4040 /* Get the ABI to use. Currently this code is only used for Irix 6. */
4041 if (mips_abi_string == (char *) 0)
4042 mips_abi = MIPS_ABI_DEFAULT;
4043 else if (! strcmp (mips_abi_string, "32"))
4045 else if (! strcmp (mips_abi_string, "n32"))
4047 else if (! strcmp (mips_abi_string, "64"))
4049 else if (! strcmp (mips_abi_string, "eabi"))
4050 mips_abi = ABI_EABI;
4052 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4054 /* A specified ISA defaults the ABI if it was not specified. */
4055 if (mips_abi_string == 0 && mips_isa_string && mips_abi != ABI_EABI)
4063 /* A specified ABI defaults the ISA if it was not specified. */
4064 else if (mips_isa_string == 0 && mips_abi_string && mips_abi != ABI_EABI)
4066 if (mips_abi == ABI_32)
4068 else if (mips_abi == ABI_N32)
4074 /* If both ABI and ISA were specified, check for conflicts. */
4075 else if (mips_isa_string && mips_abi_string)
4077 if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64))
4078 || (mips_isa >= 3 && mips_abi == ABI_32))
4079 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4082 /* Override TARGET_DEFAULT if necessary. */
4083 if (mips_abi == ABI_32)
4084 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4086 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. Likewise
4087 for the SGI Irix6 N64 ABI. */
4088 if ((mips_abi == ABI_EABI && TARGET_64BIT)
4089 || mips_abi == ABI_64)
4090 target_flags |= MASK_LONG64;
4092 /* ??? This doesn't work yet, so don't let people try to use it. */
4093 if (mips_abi == ABI_32)
4094 error ("The -mabi=32 support does not work yet.");
4097 if (mips_abi_string)
4098 error ("This target does not support the -mabi switch.");
4101 #ifdef MIPS_CPU_STRING_DEFAULT
4102 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4103 greater than that supported by the default processor, then the user gets
4104 an error. Normally, the compiler will just default to the base level cpu
4105 for the indicated isa. */
4106 if (mips_cpu_string == 0)
4107 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4110 /* Identify the processor type */
4111 if (mips_cpu_string == 0
4112 || !strcmp (mips_cpu_string, "default")
4113 || !strcmp (mips_cpu_string, "DEFAULT"))
4118 mips_cpu_string = "3000";
4119 mips_cpu = PROCESSOR_R3000;
4122 mips_cpu_string = "6000";
4123 mips_cpu = PROCESSOR_R6000;
4126 mips_cpu_string = "4000";
4127 mips_cpu = PROCESSOR_R4000;
4130 mips_cpu_string = "8000";
4131 mips_cpu = PROCESSOR_R8000;
4138 char *p = mips_cpu_string;
4141 /* We need to cope with the various "vr" prefixes for the NEC 4300
4142 and 4100 processors. */
4143 if (*p == 'v' || *p == 'V')
4146 if (*p == 'r' || *p == 'R')
4149 /* Since there is no difference between a R2000 and R3000 in
4150 terms of the scheduler, we collapse them into just an R3000. */
4152 mips_cpu = PROCESSOR_DEFAULT;
4155 /* start-sanitize-tx19 */
4157 if (!strcmp (p, "1900"))
4158 mips_cpu = PROCESSOR_R3900;
4160 /* end-sanitize-tx19 */
4163 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4164 mips_cpu = PROCESSOR_R3000;
4168 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4169 mips_cpu = PROCESSOR_R3000;
4170 else if (!strcmp (p, "3900"))
4171 mips_cpu = PROCESSOR_R3900;
4175 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4176 mips_cpu = PROCESSOR_R4000;
4177 /* The vr4100 is a non-FP ISA III processor with some extra
4179 else if (!strcmp (p, "4100"))
4181 mips_cpu = PROCESSOR_R4100;
4182 target_flags |= MASK_SOFT_FLOAT ;
4184 /* The vr4300 is a standard ISA III processor, but with a different
4186 else if (!strcmp (p, "4300"))
4187 mips_cpu = PROCESSOR_R4300;
4188 /* The r4400 is exactly the same as the r4000 from the compiler's
4190 else if (!strcmp (p, "4400"))
4191 mips_cpu = PROCESSOR_R4000;
4192 else if (!strcmp (p, "4600"))
4193 mips_cpu = PROCESSOR_R4600;
4194 else if (!strcmp (p, "4650"))
4195 mips_cpu = PROCESSOR_R4650;
4199 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4200 mips_cpu = PROCESSOR_R5000;
4204 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4205 mips_cpu = PROCESSOR_R6000;
4209 if (!strcmp (p, "8000"))
4210 mips_cpu = PROCESSOR_R8000;
4214 if (!strcmp (p, "orion"))
4215 mips_cpu = PROCESSOR_R4600;
4220 && mips_cpu != PROCESSOR_R4300
4221 && mips_cpu != PROCESSOR_R4100
4222 && mips_cpu != PROCESSOR_R5000)
4223 mips_cpu = PROCESSOR_DEFAULT;
4225 if (mips_cpu == PROCESSOR_DEFAULT)
4227 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4228 mips_cpu_string = "default";
4232 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
4233 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
4234 || ((mips_cpu == PROCESSOR_R4000
4235 || mips_cpu == PROCESSOR_R4100
4236 || mips_cpu == PROCESSOR_R4300
4237 || mips_cpu == PROCESSOR_R4600
4238 || mips_cpu == PROCESSOR_R4650)
4240 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4242 /* make sure sizes of ints/longs/etc. are ok */
4246 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
4248 else if (TARGET_LONG64)
4249 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
4251 else if (TARGET_FLOAT64)
4252 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
4254 else if (TARGET_64BIT)
4255 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
4258 if (mips_abi != ABI_32)
4259 flag_pcc_struct_return = 0;
4261 /* Tell halfpic.c that we have half-pic code if we do. */
4262 if (TARGET_HALF_PIC)
4265 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4266 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4267 /* ??? -non_shared turns off pic code generation, but this is not
4269 if (TARGET_ABICALLS)
4271 mips_abicalls = MIPS_ABICALLS_YES;
4273 if (mips_section_threshold > 0)
4274 warning ("-G is incompatible with PIC code which is the default");
4277 mips_abicalls = MIPS_ABICALLS_NO;
4279 /* -membedded-pic is a form of PIC code suitable for embedded
4280 systems. All calls are made using PC relative addressing, and
4281 all data is addressed using the $gp register. This requires gas,
4282 which does most of the work, and GNU ld, which automatically
4283 expands PC relative calls which are out of range into a longer
4284 instruction sequence. All gcc really does differently is
4285 generate a different sequence for a switch. */
4286 if (TARGET_EMBEDDED_PIC)
4289 if (TARGET_ABICALLS)
4290 warning ("-membedded-pic and -mabicalls are incompatible");
4293 warning ("-G and -membedded-pic are incompatible");
4295 /* Setting mips_section_threshold is not required, because gas
4296 will force everything to be GP addressable anyhow, but
4297 setting it will cause gcc to make better estimates of the
4298 number of instructions required to access a particular data
4300 mips_section_threshold = 0x7fffffff;
4303 /* This optimization requires a linker that can support a R_MIPS_LO16
4304 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
4305 GNU ld has this support, but not all other MIPS linkers do, so we enable
4306 this optimization only if the user requests it, or if GNU ld is the
4307 standard linker for this configuration. */
4308 /* ??? This does not work when target addresses are DImode.
4309 This is because we are missing DImode high/lo_sum patterns. */
4310 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
4312 mips_split_addresses = 1;
4314 mips_split_addresses = 0;
4316 /* -mrnames says to use the MIPS software convention for register
4317 names instead of the hardware names (ie, $a0 instead of $4).
4318 We do this by switching the names in mips_reg_names, which the
4319 reg_names points into via the REGISTER_NAMES macro. */
4321 if (TARGET_NAME_REGS)
4322 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names,
4323 sizeof (mips_reg_names));
4325 /* When compiling for the mips16, we can not use floating point. We
4326 record the original hard float value in mips16_hard_float. */
4329 if (TARGET_SOFT_FLOAT)
4330 mips16_hard_float = 0;
4332 mips16_hard_float = 1;
4333 target_flags |= MASK_SOFT_FLOAT;
4335 /* Don't run the scheduler before reload, since it tends to
4336 increase register pressure. */
4337 flag_schedule_insns = 0;
4340 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
4341 to avoid using up another bit in target_flags. */
4342 if (mips_entry_string != NULL)
4344 if (*mips_entry_string != '\0')
4345 error ("Invalid option `entry%s'", mips_entry_string);
4347 if (! TARGET_MIPS16)
4348 warning ("-mentry is only meaningful with -mips-16");
4353 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
4354 attributes can access it. */
4360 /* Initialize the high and low values for legitimate floating point
4361 constants. Rather than trying to get the accuracy down to the
4362 last bit, just use approximate ranges. */
4363 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
4364 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
4365 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
4366 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
4368 mips_print_operand_punct['?'] = 1;
4369 mips_print_operand_punct['#'] = 1;
4370 mips_print_operand_punct['&'] = 1;
4371 mips_print_operand_punct['!'] = 1;
4372 mips_print_operand_punct['*'] = 1;
4373 mips_print_operand_punct['@'] = 1;
4374 mips_print_operand_punct['.'] = 1;
4375 mips_print_operand_punct['('] = 1;
4376 mips_print_operand_punct[')'] = 1;
4377 mips_print_operand_punct['['] = 1;
4378 mips_print_operand_punct[']'] = 1;
4379 mips_print_operand_punct['<'] = 1;
4380 mips_print_operand_punct['>'] = 1;
4381 mips_print_operand_punct['{'] = 1;
4382 mips_print_operand_punct['}'] = 1;
4383 mips_print_operand_punct['^'] = 1;
4384 mips_print_operand_punct['$'] = 1;
4385 mips_print_operand_punct['+'] = 1;
4387 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4388 mips_char_to_class['e'] = M16_NA_REGS;
4389 mips_char_to_class['t'] = T_REG;
4390 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4391 mips_char_to_class['h'] = HI_REG;
4392 mips_char_to_class['l'] = LO_REG;
4393 mips_char_to_class['a'] = HILO_REG;
4394 mips_char_to_class['x'] = MD_REGS;
4395 mips_char_to_class['b'] = ALL_REGS;
4396 mips_char_to_class['y'] = GR_REGS;
4397 mips_char_to_class['z'] = ST_REGS;
4399 /* Set up array to map GCC register number to debug register number.
4400 Ignore the special purpose register numbers. */
4402 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4403 mips_dbx_regno[i] = -1;
4405 start = GP_DBX_FIRST - GP_REG_FIRST;
4406 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4407 mips_dbx_regno[i] = i + start;
4409 start = FP_DBX_FIRST - FP_REG_FIRST;
4410 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4411 mips_dbx_regno[i] = i + start;
4413 /* Set up array giving whether a given register can hold a given mode.
4414 At present, restrict ints from being in FP registers, because reload
4415 is a little enthusiastic about storing extra values in FP registers,
4416 and this is not good for things like OS kernels. Also, due to the
4417 mandatory delay, it is as fast to load from cached memory as to move
4418 from the FP register. */
4420 for (mode = VOIDmode;
4421 mode != MAX_MACHINE_MODE;
4422 mode = (enum machine_mode) ((int)mode + 1))
4424 register int size = GET_MODE_SIZE (mode);
4425 register enum mode_class class = GET_MODE_CLASS (mode);
4427 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4434 temp = (regno == FPSW_REGNUM);
4436 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4437 || FP_REG_P (regno));
4440 else if (GP_REG_P (regno))
4441 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4443 else if (FP_REG_P (regno))
4444 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
4445 && (class == MODE_FLOAT
4446 || class == MODE_COMPLEX_FLOAT
4447 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
4448 && (! TARGET_SINGLE_FLOAT || size <= 4));
4450 else if (MD_REG_P (regno))
4451 temp = (class == MODE_INT
4452 && (size <= UNITS_PER_WORD
4453 || (regno == MD_REG_FIRST
4454 && size == 2 * UNITS_PER_WORD)));
4459 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4463 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4464 initialized yet, so we can't use that here. */
4465 gpr_mode = TARGET_64BIT ? DImode : SImode;
4468 /* On the mips16, we want to allocate $24 (T_REG) before other
4469 registers for instructions for which it is possible. This helps
4470 avoid shuffling registers around in order to set up for an xor,
4471 encouraging the compiler to use a cmp instead. */
4474 mips_order_regs_for_local_alloc ()
4478 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4479 reg_alloc_order[i] = i;
4483 /* It really doesn't matter where we put register 0, since it is
4484 a fixed register anyhow. */
4485 reg_alloc_order[0] = 24;
4486 reg_alloc_order[24] = 0;
4491 /* The MIPS debug format wants all automatic variables and arguments
4492 to be in terms of the virtual frame pointer (stack pointer before
4493 any adjustment in the function), while the MIPS 3.0 linker wants
4494 the frame pointer to be the stack pointer after the initial
4495 adjustment. So, we do the adjustment here. The arg pointer (which
4496 is eliminated) points to the virtual frame pointer, while the frame
4497 pointer (which may be eliminated) points to the stack pointer after
4498 the initial adjustments. */
4501 mips_debugger_offset (addr, offset)
4503 HOST_WIDE_INT offset;
4505 rtx offset2 = const0_rtx;
4506 rtx reg = eliminate_constant_term (addr, &offset2);
4509 offset = INTVAL (offset2);
4511 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4512 || reg == hard_frame_pointer_rtx)
4514 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
4515 ? compute_frame_size (get_frame_size ())
4516 : current_frame_info.total_size;
4518 offset = offset - frame_size;
4521 /* sdbout_parms does not want this to crash for unrecognized cases. */
4523 else if (reg != arg_pointer_rtx)
4524 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
4530 /* A C compound statement to output to stdio stream STREAM the
4531 assembler syntax for an instruction operand X. X is an RTL
4534 CODE is a value that can be used to specify one of several ways
4535 of printing the operand. It is used when identical operands
4536 must be printed differently depending on the context. CODE
4537 comes from the `%' specification that was used to request
4538 printing of the operand. If the specification was just `%DIGIT'
4539 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4540 is the ASCII code for LTR.
4542 If X is a register, this macro should print the register's name.
4543 The names can be found in an array `reg_names' whose type is
4544 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4546 When the machine description has a specification `%PUNCT' (a `%'
4547 followed by a punctuation character), this macro is called with
4548 a null pointer for X and the punctuation character for CODE.
4550 The MIPS specific codes are:
4552 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4553 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4554 'd' output integer constant in decimal,
4555 'z' if the operand is 0, use $0 instead of normal operand.
4556 'D' print second register of double-word register operand.
4557 'L' print low-order register of double-word register operand.
4558 'M' print high-order register of double-word register operand.
4559 'C' print part of opcode for a branch condition.
4560 'N' print part of opcode for a branch condition, inverted.
4561 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
4562 'B' print 'z' for EQ, 'n' for NE
4563 'b' print 'n' for EQ, 'z' for NE
4564 'T' print 'f' for EQ, 't' for NE
4565 't' print 't' for EQ, 'f' for NE
4566 'Z' print register and a comma, but print nothing for $fcc0
4567 '(' Turn on .set noreorder
4568 ')' Turn on .set reorder
4569 '[' Turn on .set noat
4571 '<' Turn on .set nomacro
4572 '>' Turn on .set macro
4573 '{' Turn on .set volatile (not GAS)
4574 '}' Turn on .set novolatile (not GAS)
4575 '&' Turn on .set noreorder if filling delay slots
4576 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4577 '!' Turn on .set nomacro if filling delay slots
4578 '#' Print nop if in a .set noreorder section.
4579 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4580 '@' Print the name of the assembler temporary register (at or $1).
4581 '.' Print the name of the register with a hard-wired zero (zero or $0).
4582 '^' Print the name of the pic call-through register (t9 or $25).
4583 '$' Print the name of the stack pointer register (sp or $29).
4584 '+' Print the name of the gp register (gp or $28). */
4587 print_operand (file, op, letter)
4588 FILE *file; /* file to write to */
4589 rtx op; /* operand to print */
4590 int letter; /* %<letter> or 0 */
4592 register enum rtx_code code;
4594 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
4599 if (mips_branch_likely)
4604 fputs (reg_names [GP_REG_FIRST + 1], file);
4608 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
4612 fputs (reg_names [GP_REG_FIRST + 0], file);
4616 fputs (reg_names[STACK_POINTER_REGNUM], file);
4620 fputs (reg_names[GP_REG_FIRST + 28], file);
4624 if (final_sequence != 0 && set_noreorder++ == 0)
4625 fputs (".set\tnoreorder\n\t", file);
4629 if (final_sequence != 0)
4631 if (set_noreorder++ == 0)
4632 fputs (".set\tnoreorder\n\t", file);
4634 if (set_nomacro++ == 0)
4635 fputs (".set\tnomacro\n\t", file);
4640 if (final_sequence != 0 && set_nomacro++ == 0)
4641 fputs ("\n\t.set\tnomacro", file);
4645 if (set_noreorder != 0)
4646 fputs ("\n\tnop", file);
4647 else if (TARGET_STATS)
4648 fputs ("\n\t#nop", file);
4653 if (set_noreorder++ == 0)
4654 fputs (".set\tnoreorder\n\t", file);
4658 if (set_noreorder == 0)
4659 error ("internal error: %%) found without a %%( in assembler pattern");
4661 else if (--set_noreorder == 0)
4662 fputs ("\n\t.set\treorder", file);
4667 if (set_noat++ == 0)
4668 fputs (".set\tnoat\n\t", file);
4673 error ("internal error: %%] found without a %%[ in assembler pattern");
4674 else if (--set_noat == 0)
4675 fputs ("\n\t.set\tat", file);
4680 if (set_nomacro++ == 0)
4681 fputs (".set\tnomacro\n\t", file);
4685 if (set_nomacro == 0)
4686 error ("internal error: %%> found without a %%< in assembler pattern");
4687 else if (--set_nomacro == 0)
4688 fputs ("\n\t.set\tmacro", file);
4693 if (set_volatile++ == 0)
4694 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
4698 if (set_volatile == 0)
4699 error ("internal error: %%} found without a %%{ in assembler pattern");
4700 else if (--set_volatile == 0)
4701 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
4706 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
4715 error ("PRINT_OPERAND null pointer");
4719 code = GET_CODE (op);
4721 if (code == SIGN_EXTEND)
4722 op = XEXP (op, 0), code = GET_CODE (op);
4727 case EQ: fputs ("eq", file); break;
4728 case NE: fputs ("ne", file); break;
4729 case GT: fputs ("gt", file); break;
4730 case GE: fputs ("ge", file); break;
4731 case LT: fputs ("lt", file); break;
4732 case LE: fputs ("le", file); break;
4733 case GTU: fputs ("gtu", file); break;
4734 case GEU: fputs ("geu", file); break;
4735 case LTU: fputs ("ltu", file); break;
4736 case LEU: fputs ("leu", file); break;
4738 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
4741 else if (letter == 'N')
4744 case EQ: fputs ("ne", file); break;
4745 case NE: fputs ("eq", file); break;
4746 case GT: fputs ("le", file); break;
4747 case GE: fputs ("lt", file); break;
4748 case LT: fputs ("ge", file); break;
4749 case LE: fputs ("gt", file); break;
4750 case GTU: fputs ("leu", file); break;
4751 case GEU: fputs ("ltu", file); break;
4752 case LTU: fputs ("geu", file); break;
4753 case LEU: fputs ("gtu", file); break;
4755 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
4758 else if (letter == 'S')
4762 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
4763 assemble_name (file, buffer);
4766 else if (letter == 'Z')
4768 register int regnum;
4773 regnum = REGNO (op);
4774 if (! ST_REG_P (regnum))
4777 if (regnum != ST_REG_FIRST)
4778 fprintf (file, "%s,", reg_names[regnum]);
4781 else if (code == REG || code == SUBREG)
4783 register int regnum;
4786 regnum = REGNO (op);
4788 regnum = true_regnum (op);
4790 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
4791 || (letter == 'L' && WORDS_BIG_ENDIAN)
4795 fprintf (file, "%s", reg_names[regnum]);
4798 else if (code == MEM)
4799 output_address (XEXP (op, 0));
4801 else if (code == CONST_DOUBLE
4802 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
4807 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
4808 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
4812 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
4813 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
4815 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
4816 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
4818 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
4819 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
4821 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
4822 fputs (reg_names[GP_REG_FIRST], file);
4824 else if (letter == 'd' || letter == 'x' || letter == 'X')
4825 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
4828 else if (letter == 'B')
4829 fputs (code == EQ ? "z" : "n", file);
4830 else if (letter == 'b')
4831 fputs (code == EQ ? "n" : "z", file);
4832 else if (letter == 'T')
4833 fputs (code == EQ ? "f" : "t", file);
4834 else if (letter == 't')
4835 fputs (code == EQ ? "t" : "f", file);
4837 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
4839 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
4840 print_operand (file, XEXP (op, 0), letter);
4843 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
4845 fputs ("%gprel(", file);
4846 mips16_output_gp_offset (file, op);
4851 output_addr_const (file, op);
4854 /* A C compound statement to output to stdio stream STREAM the
4855 assembler syntax for an instruction operand that is a memory
4856 reference whose address is ADDR. ADDR is an RTL expression.
4858 On some machines, the syntax for a symbolic address depends on
4859 the section that the address refers to. On these machines,
4860 define the macro `ENCODE_SECTION_INFO' to store the information
4861 into the `symbol_ref', and then check for it here. */
4864 print_operand_address (file, addr)
4869 error ("PRINT_OPERAND_ADDRESS, null pointer");
4872 switch (GET_CODE (addr))
4875 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
4876 abort_with_insn (addr, "Arg pointer not eliminated.");
4878 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
4883 register rtx arg0 = XEXP (addr, 0);
4884 register rtx arg1 = XEXP (addr, 1);
4886 if (! mips_split_addresses)
4887 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4889 if (GET_CODE (arg0) != REG)
4890 abort_with_insn (addr,
4891 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4893 fprintf (file, "%%lo(");
4894 print_operand_address (file, arg1);
4895 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
4901 register rtx reg = 0;
4902 register rtx offset = 0;
4903 register rtx arg0 = XEXP (addr, 0);
4904 register rtx arg1 = XEXP (addr, 1);
4906 if (GET_CODE (arg0) == REG)
4910 if (GET_CODE (offset) == REG)
4911 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
4914 else if (GET_CODE (arg1) == REG)
4915 reg = arg1, offset = arg0;
4916 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
4918 output_addr_const (file, addr);
4922 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
4924 if (! CONSTANT_P (offset))
4925 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4927 if (REGNO (reg) == ARG_POINTER_REGNUM)
4928 abort_with_insn (addr, "Arg pointer not eliminated.");
4931 && GET_CODE (offset) == CONST
4932 && mips16_gp_offset_p (offset))
4934 fputs ("%gprel(", file);
4935 mips16_output_gp_offset (file, offset);
4939 output_addr_const (file, offset);
4940 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
4948 output_addr_const (file, addr);
4952 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4958 /* If optimizing for the global pointer, keep track of all of the externs, so
4959 that at the end of the file, we can emit the appropriate .extern
4960 declaration for them, before writing out the text section. We assume all
4961 names passed to us are in the permanent obstack, so they will be valid at
4962 the end of the compilation.
4964 If we have -G 0, or the extern size is unknown, or the object is in a user
4965 specified section that is not .sbss/.sdata, don't bother emitting the
4966 .externs. In the case of user specified sections this behaviour is
4967 required as otherwise GAS will think the object lives in .sbss/.sdata. */
4970 mips_output_external (file, decl, name)
4971 FILE *file ATTRIBUTE_UNUSED;
4975 register struct extern_list *p;
4980 && TREE_CODE (decl) != FUNCTION_DECL
4981 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
4982 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
4983 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
4984 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
4986 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
4987 p->next = extern_head;
4993 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4994 if (TREE_CODE (decl) == FUNCTION_DECL
4995 /* ??? Don't include alloca, since gcc will always expand it
4996 inline. If we don't do this, the C++ library fails to build. */
4997 && strcmp (name, "alloca")
4998 /* ??? Don't include __builtin_next_arg, because then gcc will not
4999 bootstrap under Irix 5.1. */
5000 && strcmp (name, "__builtin_next_arg"))
5002 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5003 p->next = extern_head;
5013 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5015 mips_output_external_libcall (file, name)
5019 register struct extern_list *p;
5021 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5022 p->next = extern_head;
5031 /* Compute a string to use as a temporary file name. */
5033 /* On MSDOS, write temp files in current dir
5034 because there's no place else we can expect to use. */
5037 #define P_tmpdir "./"
5045 char *base = getenv ("TMPDIR");
5051 if (access (P_tmpdir, R_OK | W_OK) == 0)
5055 if (access ("/usr/tmp", R_OK | W_OK) == 0)
5061 len = strlen (base);
5062 /* temp_filename is global, so we must use malloc, not alloca. */
5063 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
5064 strcpy (temp_filename, base);
5065 if (len > 0 && temp_filename[len-1] != '/')
5066 temp_filename[len++] = '/';
5068 strcpy (temp_filename + len, "ctXXXXXX");
5069 mktemp (temp_filename);
5071 stream = fopen (temp_filename, "w+");
5073 pfatal_with_name (temp_filename);
5076 /* In MSDOS, we cannot unlink the temporary file until we are finished using
5077 it. Otherwise, we delete it now, so that it will be gone even if the
5078 compiler happens to crash. */
5079 unlink (temp_filename);
5084 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5085 for .file's that start within a function. If we are smuggling stabs, try to
5086 put out a MIPS ECOFF file and a stab. */
5089 mips_output_filename (stream, name)
5093 static int first_time = 1;
5094 char ltext_label_name[100];
5100 current_function_file = name;
5101 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5102 /* This tells mips-tfile that stabs will follow. */
5103 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5104 fprintf (stream, "\t#@stabs\n");
5107 else if (write_symbols == DBX_DEBUG)
5109 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5110 fprintf (stream, "%s ", ASM_STABS_OP);
5111 output_quoted_string (stream, name);
5112 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5115 else if (name != current_function_file
5116 && strcmp (name, current_function_file) != 0)
5118 if (inside_function && !TARGET_GAS)
5120 if (!file_in_function_warning)
5122 file_in_function_warning = 1;
5123 ignore_line_number = 1;
5124 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5130 current_function_file = name;
5131 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5136 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5137 as well as a .loc, since it is possible that MIPS ECOFF might not be
5138 able to represent the location for inlines that come from a different
5142 mips_output_lineno (stream, line)
5146 if (write_symbols == DBX_DEBUG)
5149 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
5150 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5151 LOCAL_LABEL_PREFIX, sym_lineno);
5156 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5157 (ignore_line_number) ? "#" : "",
5158 num_source_filenames, line);
5160 LABEL_AFTER_LOC (stream);
5164 /* If defined, a C statement to be executed just prior to the output of
5165 assembler code for INSN, to modify the extracted operands so they will be
5168 Here the argument OPVEC is the vector containing the operands extracted
5169 from INSN, and NOPERANDS is the number of elements of the vector which
5170 contain meaningful data for this insn. The contents of this vector are
5171 what will be used to convert the insn template into assembler code, so you
5172 can change the assembler output by changing the contents of the vector.
5174 We use it to check if the current insn needs a nop in front of it because
5175 of load delays, and also to update the delay slot statistics. */
5177 /* ??? There is no real need for this function, because it never actually
5178 emits a NOP anymore. */
5181 final_prescan_insn (insn, opvec, noperands)
5183 rtx opvec[] ATTRIBUTE_UNUSED;
5184 int noperands ATTRIBUTE_UNUSED;
5186 if (dslots_number_nops > 0)
5188 rtx pattern = PATTERN (insn);
5189 int length = get_attr_length (insn);
5191 /* Do we need to emit a NOP? */
5193 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5194 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5195 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5196 || (mips_load_reg4 != 0
5197 && reg_mentioned_p (mips_load_reg4, pattern)))
5198 fputs ("\t#nop\n", asm_out_file);
5201 dslots_load_filled++;
5203 while (--dslots_number_nops > 0)
5204 fputs ("\t#nop\n", asm_out_file);
5213 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
5214 dslots_jump_total++;
5217 /* Output at beginning of assembler file.
5219 If we are optimizing to use the global pointer, create a temporary file to
5220 hold all of the text stuff, and write it out to the end. This is needed
5221 because the MIPS assembler is evidently one pass, and if it hasn't seen the
5222 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
5223 processed, it generates a two instruction sequence. */
5226 mips_asm_file_start (stream)
5229 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
5231 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5232 inside of a .set noreorder section jumps to a label outside of the .set
5233 noreorder section. Revision 2.20 just set nobopt silently rather than
5236 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5237 fprintf (stream, "\t.set\tnobopt\n");
5239 /* Generate the pseudo ops that System V.4 wants. */
5240 #ifndef ABICALLS_ASM_OP
5241 #define ABICALLS_ASM_OP ".abicalls"
5243 if (TARGET_ABICALLS)
5244 /* ??? but do not want this (or want pic0) if -non-shared? */
5245 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
5248 fprintf (stream, "\t.set\tmips16\n");
5250 /* Start a section, so that the first .popsection directive is guaranteed
5251 to have a previously defined section to pop back to. */
5252 if (mips_abi != ABI_32 && mips_abi != ABI_EABI)
5253 fprintf (stream, "\t.section\t.text\n");
5255 /* This code exists so that we can put all externs before all symbol
5256 references. This is necessary for the MIPS assembler's global pointer
5257 optimizations to work. */
5258 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5260 asm_out_data_file = stream;
5261 asm_out_text_file = make_temp_file ();
5265 asm_out_data_file = asm_out_text_file = stream;
5267 if (flag_verbose_asm)
5268 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
5270 mips_section_threshold, mips_cpu_string, mips_isa);
5273 /* If we are optimizing the global pointer, emit the text section now and any
5274 small externs which did not have .comm, etc that are needed. Also, give a
5275 warning if the data area is more than 32K and -pic because 3 instructions
5276 are needed to reference the data pointers. */
5279 mips_asm_file_end (file)
5284 struct extern_list *p;
5289 HALF_PIC_FINISH (file);
5296 for (p = extern_head; p != 0; p = p->next)
5298 name_tree = get_identifier (p->name);
5300 /* Positively ensure only one .extern for any given symbol. */
5301 if (! TREE_ASM_WRITTEN (name_tree))
5303 TREE_ASM_WRITTEN (name_tree) = 1;
5304 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5306 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
5310 fputs ("\t.extern\t", file);
5311 assemble_name (file, p->name);
5312 fprintf (file, ", %d\n", p->size);
5318 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5320 fprintf (file, "\n\t.text\n");
5321 rewind (asm_out_text_file);
5322 if (ferror (asm_out_text_file))
5323 fatal_io_error (temp_filename);
5325 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
5326 if (fwrite (buffer, 1, len, file) != len)
5327 pfatal_with_name (asm_file_name);
5330 pfatal_with_name (temp_filename);
5332 if (fclose (asm_out_text_file) != 0)
5333 pfatal_with_name (temp_filename);
5336 unlink (temp_filename);
5341 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
5342 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
5345 mips_declare_object (stream, name, init_string, final_string, size)
5352 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
5353 assemble_name (stream, name);
5354 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
5358 tree name_tree = get_identifier (name);
5359 TREE_ASM_WRITTEN (name_tree) = 1;
5363 /* Output a double precision value to the assembler. If both the
5364 host and target are IEEE, emit the values in hex. */
5367 mips_output_double (stream, value)
5369 REAL_VALUE_TYPE value;
5371 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
5373 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
5375 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
5376 value_long[0], value, value_long[1]);
5378 fprintf (stream, "\t.double\t%.20g\n", value);
5382 /* Output a single precision value to the assembler. If both the
5383 host and target are IEEE, emit the values in hex. */
5386 mips_output_float (stream, value)
5388 REAL_VALUE_TYPE value;
5390 #ifdef REAL_VALUE_TO_TARGET_SINGLE
5392 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
5394 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
5396 fprintf (stream, "\t.float\t%.12g\n", value);
5400 /* Return the bytes needed to compute the frame pointer from the current
5403 Mips stack frames look like:
5405 Before call After call
5406 +-----------------------+ +-----------------------+
5409 | caller's temps. | | caller's temps. |
5411 +-----------------------+ +-----------------------+
5413 | arguments on stack. | | arguments on stack. |
5415 +-----------------------+ +-----------------------+
5416 | 4 words to save | | 4 words to save |
5417 | arguments passed | | arguments passed |
5418 | in registers, even | | in registers, even |
5419 SP->| if not passed. | VFP->| if not passed. |
5420 +-----------------------+ +-----------------------+
5422 | fp register save |
5424 +-----------------------+
5426 | gp register save |
5428 +-----------------------+
5432 +-----------------------+
5434 | alloca allocations |
5436 +-----------------------+
5438 | GP save for V.4 abi |
5440 +-----------------------+
5442 | arguments on stack |
5444 +-----------------------+
5446 | arguments passed |
5447 | in registers, even |
5448 low SP->| if not passed. |
5449 memory +-----------------------+
5454 compute_frame_size (size)
5455 HOST_WIDE_INT size; /* # of var. bytes allocated */
5458 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
5459 HOST_WIDE_INT var_size; /* # bytes that variables take up */
5460 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
5461 HOST_WIDE_INT extra_size; /* # extra bytes */
5462 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
5463 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
5464 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
5465 long mask; /* mask of saved gp registers */
5466 long fmask; /* mask of saved fp registers */
5467 int fp_inc; /* 1 or 2 depending on the size of fp regs */
5468 long fp_bits; /* bitmask to use for each fp register */
5474 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
5475 var_size = MIPS_STACK_ALIGN (size);
5476 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
5478 /* The MIPS 3.0 linker does not like functions that dynamically
5479 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5480 looks like we are trying to create a second frame pointer to the
5481 function, so allocate some stack space to make it happy. */
5483 if (args_size == 0 && current_function_calls_alloca)
5484 args_size = 4 * UNITS_PER_WORD;
5486 total_size = var_size + args_size + extra_size;
5488 /* Calculate space needed for gp registers. */
5489 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5491 /* $18 is a special case on the mips16. It may be used to call
5492 a function which returns a floating point value, but it is
5493 marked in call_used_regs. $31 is also a special case. When
5494 not using -mentry, it will be used to copy a return value
5495 into the floating point registers if the return value is
5497 if (MUST_SAVE_REGISTER (regno)
5499 && regno == GP_REG_FIRST + 18
5500 && regs_ever_live[regno])
5502 && regno == GP_REG_FIRST + 31
5503 && mips16_hard_float
5505 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
5506 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
5508 && (! TARGET_SINGLE_FLOAT
5509 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
5512 gp_reg_size += GET_MODE_SIZE (gpr_mode);
5513 mask |= 1L << (regno - GP_REG_FIRST);
5515 /* The entry and exit pseudo instructions can not save $17
5516 without also saving $16. */
5518 && regno == GP_REG_FIRST + 17
5519 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
5521 gp_reg_size += UNITS_PER_WORD;
5527 /* Calculate space needed for fp registers. */
5528 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
5539 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += fp_inc)
5541 if (regs_ever_live[regno] && !call_used_regs[regno])
5543 fp_reg_size += fp_inc * UNITS_PER_FPREG;
5544 fmask |= fp_bits << (regno - FP_REG_FIRST);
5548 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5549 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
5551 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
5552 for leaf routines (total_size == extra_size) to save the gp reg.
5553 The gp reg is callee saved in the 64 bit ABI, so all routines must
5554 save the gp reg. This is not a leaf routine if -p, because of the
5556 if (total_size == extra_size && (mips_abi == ABI_32 || mips_abi == ABI_EABI)
5558 total_size = extra_size = 0;
5559 else if (TARGET_ABICALLS)
5561 /* Add the context-pointer to the saved registers. */
5562 gp_reg_size += UNITS_PER_WORD;
5563 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
5564 total_size -= gp_reg_rounded;
5565 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5566 total_size += gp_reg_rounded;
5569 /* Add in space reserved on the stack by the callee for storing arguments
5570 passed in registers. */
5571 if (mips_abi != ABI_32)
5572 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
5574 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
5575 if (mips_entry && total_size > 0 && total_size < 32)
5578 /* Save other computed information. */
5579 current_frame_info.total_size = total_size;
5580 current_frame_info.var_size = var_size;
5581 current_frame_info.args_size = args_size;
5582 current_frame_info.extra_size = extra_size;
5583 current_frame_info.gp_reg_size = gp_reg_size;
5584 current_frame_info.fp_reg_size = fp_reg_size;
5585 current_frame_info.mask = mask;
5586 current_frame_info.fmask = fmask;
5587 current_frame_info.initialized = reload_completed;
5588 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
5589 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
5593 unsigned long offset;
5595 /* When using mips_entry, the registers are always saved at the
5596 top of the stack. */
5598 offset = (args_size + extra_size + var_size
5599 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
5601 offset = total_size - GET_MODE_SIZE (gpr_mode);
5603 current_frame_info.gp_sp_offset = offset;
5604 current_frame_info.gp_save_offset = offset - total_size;
5608 current_frame_info.gp_sp_offset = 0;
5609 current_frame_info.gp_save_offset = 0;
5614 unsigned long offset = (args_size + extra_size + var_size
5615 + gp_reg_rounded + fp_reg_size
5616 - fp_inc * UNITS_PER_FPREG);
5617 current_frame_info.fp_sp_offset = offset;
5618 current_frame_info.fp_save_offset = offset - total_size;
5622 current_frame_info.fp_sp_offset = 0;
5623 current_frame_info.fp_save_offset = 0;
5626 /* Ok, we're done. */
5630 /* Common code to emit the insns (or to write the instructions to a file)
5631 to save/restore registers.
5633 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
5634 is not modified within save_restore_insns. */
5636 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
5639 save_restore_insns (store_p, large_reg, large_offset, file)
5640 int store_p; /* true if this is prologue */
5641 rtx large_reg; /* register holding large offset constant or NULL */
5642 long large_offset; /* large constant offset value */
5643 FILE *file; /* file to write instructions instead of making RTL */
5645 long mask = current_frame_info.mask;
5646 long fmask = current_frame_info.fmask;
5649 HOST_WIDE_INT base_offset;
5650 HOST_WIDE_INT gp_offset;
5651 HOST_WIDE_INT fp_offset;
5652 HOST_WIDE_INT end_offset;
5655 if (frame_pointer_needed
5656 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
5659 if (mask == 0 && fmask == 0)
5662 /* Save registers starting from high to low. The debuggers prefer at least
5663 the return register be stored at func+4, and also it allows us not to
5664 need a nop in the epilog if at least one register is reloaded in
5665 addition to return address. */
5667 /* Save GP registers if needed. */
5670 /* Pick which pointer to use as a base register. For small frames, just
5671 use the stack pointer. Otherwise, use a temporary register. Save 2
5672 cycles if the save area is near the end of a large frame, by reusing
5673 the constant created in the prologue/epilogue to adjust the stack
5676 gp_offset = current_frame_info.gp_sp_offset;
5678 = gp_offset - (current_frame_info.gp_reg_size
5679 - GET_MODE_SIZE (gpr_mode));
5681 if (gp_offset < 0 || end_offset < 0)
5682 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
5683 (long) gp_offset, (long) end_offset);
5685 /* If we see a large frame in mips16 mode, we save the registers
5686 before adjusting the stack pointer, and load them afterward. */
5687 else if (TARGET_MIPS16 && large_offset > 32767)
5688 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
5690 else if (gp_offset < 32768)
5691 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
5693 else if (large_reg != 0
5694 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
5695 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
5697 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5698 base_offset = large_offset;
5701 if (Pmode == DImode)
5702 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
5703 stack_pointer_rtx));
5705 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
5706 stack_pointer_rtx));
5708 RTX_FRAME_RELATED_P (insn) = 1;
5711 fprintf (file, "\t%s\t%s,%s,%s\n",
5712 Pmode == DImode ? "daddu" : "addu",
5713 reg_names[MIPS_TEMP2_REGNUM],
5714 reg_names[REGNO (large_reg)],
5715 reg_names[STACK_POINTER_REGNUM]);
5720 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5721 base_offset = gp_offset;
5724 rtx gp_offset_rtx = GEN_INT (gp_offset);
5726 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5727 bit, so make sure that we don't emit anything that can be
5729 /* ??? There is no DImode ori immediate pattern, so we can only
5730 do this for 32 bit code. */
5731 if (large_int (gp_offset_rtx)
5732 && GET_MODE (base_reg_rtx) == SImode)
5734 insn = emit_move_insn (base_reg_rtx,
5735 GEN_INT (gp_offset & 0xffff0000));
5737 RTX_FRAME_RELATED_P (insn) = 1;
5739 = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
5740 GEN_INT (gp_offset & 0x0000ffff)));
5742 RTX_FRAME_RELATED_P (insn) = 1;
5746 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
5748 RTX_FRAME_RELATED_P (insn) = 1;
5751 if (Pmode == DImode)
5752 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
5753 stack_pointer_rtx));
5755 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
5756 stack_pointer_rtx));
5758 RTX_FRAME_RELATED_P (insn) = 1;
5762 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
5763 reg_names[MIPS_TEMP2_REGNUM], base_offset);
5764 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
5765 fprintf (file, "\n\t%s\t%s,%s,%s\n",
5766 Pmode == DImode ? "daddu" : "addu",
5767 reg_names[MIPS_TEMP2_REGNUM],
5768 reg_names[MIPS_TEMP2_REGNUM],
5769 reg_names[STACK_POINTER_REGNUM]);
5773 /* When we restore the registers in MIPS16 mode, then if we are
5774 using a frame pointer, and this is not a large frame, the
5775 current stack pointer will be offset by
5776 current_function_outgoing_args_size. Doing it this way lets
5777 us avoid offsetting the frame pointer before copying it into
5778 the stack pointer; there is no instruction to set the stack
5779 pointer to the sum of a register and a constant. */
5782 && frame_pointer_needed
5783 && large_offset <= 32767)
5784 base_offset += current_function_outgoing_args_size;
5786 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
5787 if (BITSET_P (mask, regno - GP_REG_FIRST))
5793 = gen_rtx (MEM, gpr_mode,
5794 gen_rtx (PLUS, Pmode, base_reg_rtx,
5795 GEN_INT (gp_offset - base_offset)));
5797 RTX_UNCHANGING_P (mem_rtx) = 1;
5799 /* The mips16 does not have an instruction to load
5800 $31, so we load $7 instead, and work things out
5802 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
5803 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
5804 /* The mips16 sometimes needs to save $18. */
5805 else if (TARGET_MIPS16
5806 && regno != GP_REG_FIRST + 31
5807 && ! M16_REG_P (regno))
5810 reg_rtx = gen_rtx (REG, gpr_mode, 6);
5813 reg_rtx = gen_rtx (REG, gpr_mode, 3);
5814 emit_move_insn (reg_rtx,
5815 gen_rtx (REG, gpr_mode, regno));
5819 reg_rtx = gen_rtx (REG, gpr_mode, regno);
5823 insn = emit_move_insn (mem_rtx, reg_rtx);
5824 RTX_FRAME_RELATED_P (insn) = 1;
5826 else if (!TARGET_ABICALLS || mips_abi != ABI_32
5827 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5829 emit_move_insn (reg_rtx, mem_rtx);
5831 && regno != GP_REG_FIRST + 31
5832 && ! M16_REG_P (regno))
5833 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
5839 if (store_p || !TARGET_ABICALLS || mips_abi != ABI_32
5840 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5844 /* The mips16 does not have an instruction to
5845 load $31, so we load $7 instead, and work
5846 things out in the caller. */
5847 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
5848 r = GP_REG_FIRST + 7;
5849 /* The mips16 sometimes needs to save $18. */
5851 && regno != GP_REG_FIRST + 31
5852 && ! M16_REG_P (regno))
5855 r = GP_REG_FIRST + 6;
5858 r = GP_REG_FIRST + 3;
5859 fprintf (file, "\tmove\t%s,%s\n",
5860 reg_names[r], reg_names[regno]);
5863 fprintf (file, "\t%s\t%s,",
5865 ? (store_p) ? "sd" : "ld"
5866 : (store_p) ? "sw" : "lw"),
5868 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5869 gp_offset - base_offset);
5870 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
5873 && regno != GP_REG_FIRST + 31
5874 && ! M16_REG_P (regno))
5875 fprintf (file, "\tmove\t%s,%s\n",
5876 reg_names[regno], reg_names[r]);
5880 gp_offset -= GET_MODE_SIZE (gpr_mode);
5884 base_reg_rtx = 0, base_offset = 0;
5886 /* Save floating point registers if needed. */
5889 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
5890 int fp_size = fp_inc * UNITS_PER_FPREG;
5892 /* Pick which pointer to use as a base register. */
5893 fp_offset = current_frame_info.fp_sp_offset;
5894 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
5896 if (fp_offset < 0 || end_offset < 0)
5897 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5898 (long) fp_offset, (long) end_offset);
5900 else if (fp_offset < 32768)
5901 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
5903 else if (base_reg_rtx != 0
5904 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
5905 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
5906 ; /* already set up for gp registers above */
5908 else if (large_reg != 0
5909 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
5910 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
5912 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5913 base_offset = large_offset;
5916 if (Pmode == DImode)
5917 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
5918 stack_pointer_rtx));
5920 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
5921 stack_pointer_rtx));
5923 RTX_FRAME_RELATED_P (insn) = 1;
5927 fprintf (file, "\t%s\t%s,%s,%s\n",
5928 Pmode == DImode ? "daddu" : "addu",
5929 reg_names[MIPS_TEMP2_REGNUM],
5930 reg_names[REGNO (large_reg)],
5931 reg_names[STACK_POINTER_REGNUM]);
5936 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5937 base_offset = fp_offset;
5940 rtx fp_offset_rtx = GEN_INT (fp_offset);
5942 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5943 bit, so make sure that we don't emit anything that can be
5945 /* ??? There is no DImode ori immediate pattern, so we can only
5946 do this for 32 bit code. */
5947 if (large_int (fp_offset_rtx)
5948 && GET_MODE (base_reg_rtx) == SImode)
5950 insn = emit_move_insn (base_reg_rtx,
5951 GEN_INT (fp_offset & 0xffff0000));
5953 RTX_FRAME_RELATED_P (insn) = 1;
5954 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
5955 GEN_INT (fp_offset & 0x0000ffff)));
5957 RTX_FRAME_RELATED_P (insn) = 1;
5961 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
5963 RTX_FRAME_RELATED_P (insn) = 1;
5967 RTX_FRAME_RELATED_P (insn) = 1;
5968 if (Pmode == DImode)
5969 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
5970 stack_pointer_rtx));
5972 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
5973 stack_pointer_rtx));
5975 RTX_FRAME_RELATED_P (insn) = 1;
5979 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
5980 reg_names[MIPS_TEMP2_REGNUM], base_offset);
5981 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
5982 fprintf (file, "\n\t%s\t%s,%s,%s\n",
5983 Pmode == DImode ? "daddu" : "addu",
5984 reg_names[MIPS_TEMP2_REGNUM],
5985 reg_names[MIPS_TEMP2_REGNUM],
5986 reg_names[STACK_POINTER_REGNUM]);
5990 for (regno = FP_REG_LAST-1; regno >= FP_REG_FIRST; regno -= fp_inc)
5991 if (BITSET_P (fmask, regno - FP_REG_FIRST))
5995 enum machine_mode sz
5996 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5997 rtx reg_rtx = gen_rtx (REG, sz, regno);
5998 rtx mem_rtx = gen_rtx (MEM, sz,
5999 gen_rtx (PLUS, Pmode, base_reg_rtx,
6002 RTX_UNCHANGING_P (mem_rtx) = 1;
6006 insn = emit_move_insn (mem_rtx, reg_rtx);
6007 RTX_FRAME_RELATED_P (insn) = 1;
6010 emit_move_insn (reg_rtx, mem_rtx);
6014 fprintf (file, "\t%s\t%s,",
6015 (TARGET_SINGLE_FLOAT
6016 ? (store_p ? "s.s" : "l.s")
6017 : (store_p ? "s.d" : "l.d")),
6019 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6020 fp_offset - base_offset);
6021 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6024 fp_offset -= fp_size;
6029 /* Set up the stack and frame (if desired) for the function. */
6032 function_prologue (file, size)
6034 int size ATTRIBUTE_UNUSED;
6036 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6039 long tsize = current_frame_info.total_size;
6041 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6043 #ifdef SDB_DEBUGGING_INFO
6044 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6045 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6048 /* In mips16 mode, we may need to generate a 32 bit to handle
6049 floating point arguments. The linker will arrange for any 32 bit
6050 functions to call this stub, which will then jump to the 16 bit
6052 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6053 && current_function_args_info.fp_code != 0)
6054 build_mips16_function_stub (file);
6056 inside_function = 1;
6058 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6059 /* Get the function name the same way that toplev.c does before calling
6060 assemble_start_function. This is needed so that the name used here
6061 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6062 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6064 if (!flag_inhibit_size_directive)
6066 fputs ("\t.ent\t", file);
6067 assemble_name (file, fnname);
6071 assemble_name (file, fnname);
6072 fputs (":\n", file);
6075 if (!flag_inhibit_size_directive)
6078 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6079 (reg_names[(frame_pointer_needed)
6080 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6081 tsize, reg_names[31 + GP_REG_FIRST],
6082 current_frame_info.var_size,
6083 current_frame_info.num_gp,
6084 current_frame_info.num_fp,
6085 current_function_outgoing_args_size,
6086 current_frame_info.extra_size);
6088 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6089 current_frame_info.mask,
6090 current_frame_info.gp_save_offset,
6091 current_frame_info.fmask,
6092 current_frame_info.fp_save_offset);
6095 if (mips_entry && ! mips_can_use_return_insn ())
6097 int save16 = BITSET_P (current_frame_info.mask, 16);
6098 int save17 = BITSET_P (current_frame_info.mask, 17);
6099 int save31 = BITSET_P (current_frame_info.mask, 31);
6103 /* Look through the initial insns to see if any of them store
6104 the function parameters into the incoming parameter storage
6105 area. If they do, we delete the insn, and save the register
6106 using the entry pseudo-instruction instead. We don't try to
6107 look past a label, jump, or call. */
6108 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6110 rtx note, set, src, dest, base, offset;
6113 if (GET_CODE (insn) == CODE_LABEL
6114 || GET_CODE (insn) == JUMP_INSN
6115 || GET_CODE (insn) == CALL_INSN)
6117 if (GET_CODE (insn) != INSN)
6119 set = PATTERN (insn);
6120 if (GET_CODE (set) != SET)
6123 /* An insn storing a function parameter will still have a
6124 REG_EQUIV note on it mentioning the argument pointer. */
6125 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6126 if (note == NULL_RTX)
6128 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6131 src = SET_SRC (set);
6132 if (GET_CODE (src) != REG
6133 || REGNO (src) < GP_REG_FIRST + 4
6134 || REGNO (src) > GP_REG_FIRST + 7)
6137 dest = SET_DEST (set);
6138 if (GET_CODE (dest) != MEM)
6140 if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD)
6142 else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
6143 && REGNO (src) < GP_REG_FIRST + 7)
6147 offset = const0_rtx;
6148 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6149 if (GET_CODE (base) != REG
6150 || GET_CODE (offset) != CONST_INT)
6152 if (REGNO (base) == STACK_POINTER_REGNUM
6153 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6155 else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM
6158 + (REGNO (src) - 4) * UNITS_PER_WORD
6159 - current_function_outgoing_args_size)))
6164 /* This insn stores a parameter onto the stack, in the same
6165 location where the entry pseudo-instruction will put it.
6166 Delete the insn, and arrange to tell the entry
6167 instruction to save the register. */
6168 PUT_CODE (insn, NOTE);
6169 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6170 NOTE_SOURCE_FILE (insn) = 0;
6172 hireg = (REGNO (src)
6173 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6175 if (hireg > savearg)
6179 /* If this is a varargs function, we need to save all the
6180 registers onto the stack anyhow. */
6181 if (current_function_stdarg || current_function_varargs)
6182 savearg = GP_REG_FIRST + 7;
6184 fprintf (file, "\tentry\t");
6187 if (savearg == GP_REG_FIRST + 4)
6188 fprintf (file, "%s", reg_names[savearg]);
6190 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6191 reg_names[savearg]);
6193 if (save16 || save17)
6196 fprintf (file, ",");
6197 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6199 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6203 if (savearg > 0 || save16 || save17)
6204 fprintf (file, ",");
6205 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6207 fprintf (file, "\n");
6210 if (TARGET_ABICALLS && mips_abi == ABI_32)
6212 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6214 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6215 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
6218 fprintf (file, "\t%s\t%s,%s,%ld\n",
6219 (Pmode == DImode ? "dsubu" : "subu"),
6220 sp_str, sp_str, tsize);
6221 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
6224 if (dwarf2out_do_frame ())
6225 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
6229 /* Expand the prologue into a bunch of separate insns. */
6232 mips_expand_prologue ()
6235 HOST_WIDE_INT tsize;
6238 tree fndecl = current_function_decl;
6239 tree fntype = TREE_TYPE (fndecl);
6240 tree fnargs = DECL_ARGUMENTS (fndecl);
6245 CUMULATIVE_ARGS args_so_far;
6246 rtx reg_18_save = NULL_RTX;
6248 /* If struct value address is treated as the first argument, make it so. */
6249 if (aggregate_value_p (DECL_RESULT (fndecl))
6250 && ! current_function_returns_pcc_struct
6251 && struct_value_incoming_rtx == 0)
6253 tree type = build_pointer_type (fntype);
6254 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
6256 DECL_ARG_TYPE (function_result_decl) = type;
6257 TREE_CHAIN (function_result_decl) = fnargs;
6258 fnargs = function_result_decl;
6261 /* Determine the last argument, and get its name. */
6263 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
6264 regno = GP_ARG_FIRST;
6266 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
6268 tree passed_type = DECL_ARG_TYPE (cur_arg);
6269 enum machine_mode passed_mode = TYPE_MODE (passed_type);
6272 if (TREE_ADDRESSABLE (passed_type))
6274 passed_type = build_pointer_type (passed_type);
6275 passed_mode = Pmode;
6278 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
6284 /* passed in a register, so will get homed automatically */
6285 if (GET_MODE (entry_parm) == BLKmode)
6286 words = (int_size_in_bytes (passed_type) + 3) / 4;
6288 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
6290 regno = REGNO (entry_parm) + words - 1;
6294 regno = GP_ARG_LAST+1;
6298 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
6300 next_arg = TREE_CHAIN (cur_arg);
6303 if (DECL_NAME (cur_arg))
6304 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
6310 /* In order to pass small structures by value in registers compatibly with
6311 the MIPS compiler, we need to shift the value into the high part of the
6312 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
6313 adjustments to be made as the next_arg_reg variable, so we split up the
6314 insns, and emit them separately. */
6316 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
6317 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
6319 rtvec adjust = XVEC (next_arg_reg, 0);
6320 int num = GET_NUM_ELEM (adjust);
6322 for (i = 0; i < num; i++)
6324 rtx pattern = RTVEC_ELT (adjust, i);
6325 if (GET_CODE (pattern) != SET
6326 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
6327 abort_with_insn (pattern, "Insn is not a shift");
6329 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
6330 emit_insn (pattern);
6334 tsize = compute_frame_size (get_frame_size ());
6336 /* If this function is a varargs function, store any registers that
6337 would normally hold arguments ($4 - $7) on the stack. */
6338 if (mips_abi == ABI_32
6339 && (! mips_entry || mips_can_use_return_insn ())
6340 && ((TYPE_ARG_TYPES (fntype) != 0
6341 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6344 && ((arg_name[0] == '_'
6345 && strcmp (arg_name, "__builtin_va_alist") == 0)
6346 || (arg_name[0] == 'v'
6347 && strcmp (arg_name, "va_alist") == 0)))))
6349 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
6350 rtx ptr = stack_pointer_rtx;
6352 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
6353 if (TARGET_ABICALLS)
6356 for (; regno <= GP_ARG_LAST; regno++)
6359 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
6360 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
6361 gen_rtx (REG, gpr_mode, regno));
6363 offset += GET_MODE_SIZE (gpr_mode);
6367 /* If we are using the entry pseudo instruction, it will
6368 automatically subtract 32 from the stack pointer, so we don't
6369 need to. The entry pseudo instruction is emitted by
6370 function_prologue. */
6371 if (mips_entry && ! mips_can_use_return_insn ())
6373 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
6377 /* If we are using a frame pointer with a small stack frame,
6378 we need to initialize it here since it won't be done
6380 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6382 rtx incr = GEN_INT (current_function_outgoing_args_size);
6383 if (Pmode == DImode)
6384 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6388 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6392 else if (Pmode == DImode)
6393 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6394 stack_pointer_rtx));
6396 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6397 stack_pointer_rtx));
6399 RTX_FRAME_RELATED_P (insn) = 1;
6402 /* We may need to save $18, if it is used to call a function
6403 which may return a floating point value. Set up a sequence
6404 of instructions to do so. Later on we emit them at the right
6406 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
6408 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
6409 long gp_offset, base_offset;
6411 gp_offset = current_frame_info.gp_sp_offset;
6412 if (BITSET_P (current_frame_info.mask, 16))
6413 gp_offset -= UNITS_PER_WORD;
6414 if (BITSET_P (current_frame_info.mask, 17))
6415 gp_offset -= UNITS_PER_WORD;
6416 if (BITSET_P (current_frame_info.mask, 31))
6417 gp_offset -= UNITS_PER_WORD;
6419 base_offset = tsize;
6423 emit_move_insn (reg_rtx,
6424 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
6425 emit_move_insn (gen_rtx (MEM, gpr_mode,
6426 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
6430 reg_18_save = gen_sequence ();
6439 if (reg_18_save != NULL_RTX)
6440 emit_insn (reg_18_save);
6446 rtx tsize_rtx = GEN_INT (tsize);
6448 /* If we are doing svr4-abi, sp move is done by
6449 function_prologue. In mips16 mode with a large frame, we
6450 save the registers before adjusting the stack. */
6451 if ((!TARGET_ABICALLS || mips_abi != ABI_32)
6452 && (!TARGET_MIPS16 || tsize <= 32767))
6458 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
6460 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6461 bit, so make sure that we don't emit anything that can be
6463 /* ??? There is no DImode ori immediate pattern, so we can only
6464 do this for 32 bit code. */
6465 if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode)
6467 insn = emit_move_insn (tmp_rtx,
6468 GEN_INT (tsize & 0xffff0000));
6469 RTX_FRAME_RELATED_P (insn) = 1;
6470 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
6471 GEN_INT (tsize & 0x0000ffff)));
6472 RTX_FRAME_RELATED_P (insn) = 1;
6476 insn = emit_move_insn (tmp_rtx, tsize_rtx);
6477 RTX_FRAME_RELATED_P (insn) = 1;
6480 tsize_rtx = tmp_rtx;
6483 if (Pmode == DImode)
6484 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
6487 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
6490 RTX_FRAME_RELATED_P (insn) = 1;
6494 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
6495 else if (reg_18_save != NULL_RTX)
6496 emit_insn (reg_18_save);
6498 if ((!TARGET_ABICALLS || mips_abi != ABI_32)
6504 if (!frame_pointer_needed)
6507 reg_rtx = gen_rtx (REG, Pmode, 3);
6508 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6509 emit_move_insn (reg_rtx, tsize_rtx);
6510 if (Pmode == DImode)
6511 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
6512 hard_frame_pointer_rtx,
6515 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
6516 hard_frame_pointer_rtx,
6518 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6521 if (frame_pointer_needed)
6525 /* On the mips16, we encourage the use of unextended
6526 instructions when using the frame pointer by pointing the
6527 frame pointer ahead of the argument space allocated on
6529 if ((! TARGET_ABICALLS || mips_abi != ABI_32)
6533 /* In this case, we have already copied the stack
6534 pointer into the frame pointer, above. We need only
6535 adjust for the outgoing argument size. */
6536 if (current_function_outgoing_args_size != 0)
6538 rtx incr = GEN_INT (current_function_outgoing_args_size);
6539 if (Pmode == DImode)
6540 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6541 hard_frame_pointer_rtx,
6544 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6545 hard_frame_pointer_rtx,
6549 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6551 rtx incr = GEN_INT (current_function_outgoing_args_size);
6552 if (Pmode == DImode)
6553 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6557 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6561 else if (Pmode == DImode)
6562 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6563 stack_pointer_rtx));
6565 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6566 stack_pointer_rtx));
6569 RTX_FRAME_RELATED_P (insn) = 1;
6572 if (TARGET_ABICALLS && mips_abi != ABI_32)
6573 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
6574 gen_rtx (REG, DImode, 25)));
6577 /* If we are profiling, make sure no instructions are scheduled before
6578 the call to mcount. */
6580 if (profile_flag || profile_block_flag)
6581 emit_insn (gen_blockage ());
6584 /* Do any necessary cleanup after a function to restore stack, frame,
6587 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
6588 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6591 function_epilogue (file, size)
6592 FILE *file ATTRIBUTE_UNUSED;
6593 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6597 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6598 /* Get the function name the same way that toplev.c does before calling
6599 assemble_start_function. This is needed so that the name used here
6600 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6601 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6603 if (!flag_inhibit_size_directive)
6605 fputs ("\t.end\t", file);
6606 assemble_name (file, fnname);
6613 int num_gp_regs = current_frame_info.gp_reg_size / 4;
6614 int num_fp_regs = current_frame_info.fp_reg_size / 8;
6615 int num_regs = num_gp_regs + num_fp_regs;
6616 char *name = fnname;
6621 dslots_load_total += num_regs;
6624 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
6625 name, frame_pointer_needed ? 'y' : 'n',
6626 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
6627 current_function_calls_alloca ? 'y' : 'n',
6628 current_function_calls_setjmp ? 'y' : 'n',
6629 current_frame_info.total_size,
6630 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
6631 dslots_load_total, dslots_load_filled,
6632 dslots_jump_total, dslots_jump_filled,
6633 num_refs[0], num_refs[1], num_refs[2]);
6635 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
6638 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
6639 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
6642 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
6645 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
6646 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
6649 fputc ('\n', stderr);
6652 /* Reset state info for each function. */
6653 inside_function = 0;
6654 ignore_line_number = 0;
6655 dslots_load_total = 0;
6656 dslots_jump_total = 0;
6657 dslots_load_filled = 0;
6658 dslots_jump_filled = 0;
6664 current_frame_info = zero_frame_info;
6666 while (string_constants != NULL)
6668 struct string_constant *next;
6670 next = string_constants->next;
6671 free (string_constants);
6672 string_constants = next;
6675 /* Restore the output file if optimizing the GP (optimizing the GP causes
6676 the text to be diverted to a tempfile, so that data decls come before
6677 references to the data). */
6679 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
6680 asm_out_file = asm_out_data_file;
6683 /* Expand the epilogue into a bunch of separate insns. */
6686 mips_expand_epilogue ()
6688 HOST_WIDE_INT tsize = current_frame_info.total_size;
6689 rtx tsize_rtx = GEN_INT (tsize);
6690 rtx tmp_rtx = (rtx)0;
6692 if (mips_can_use_return_insn ())
6694 emit_insn (gen_return ());
6698 if (mips_entry && ! mips_can_use_return_insn ())
6701 if (tsize > 32767 && ! TARGET_MIPS16)
6703 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
6704 emit_move_insn (tmp_rtx, tsize_rtx);
6705 tsize_rtx = tmp_rtx;
6710 long orig_tsize = tsize;
6712 if (frame_pointer_needed)
6714 emit_insn (gen_blockage ());
6716 /* On the mips16, the frame pointer is offset from the stack
6717 pointer by current_function_outgoing_args_size. We
6718 account for that by changing tsize. Note that this can
6719 actually make tsize negative. */
6722 tsize -= current_function_outgoing_args_size;
6724 /* If we have a large frame, it's easier to add to $17
6725 than to $sp, since the mips16 has no instruction to
6726 add a register to $sp. */
6727 if (orig_tsize > 32767)
6729 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
6731 emit_move_insn (g6_rtx, GEN_INT (tsize));
6732 if (Pmode == DImode)
6733 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6734 hard_frame_pointer_rtx,
6737 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6738 hard_frame_pointer_rtx,
6743 if (tsize && tsize != orig_tsize)
6744 tsize_rtx = GEN_INT (tsize);
6747 if (Pmode == DImode)
6748 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
6750 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
6753 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
6754 are going to restore it, then we must emit a blockage insn to
6755 prevent the scheduler from moving the restore out of the epilogue. */
6756 else if (TARGET_ABICALLS && mips_abi != ABI_32
6757 && (current_frame_info.mask
6758 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
6759 emit_insn (gen_blockage ());
6761 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
6763 /* In mips16 mode with a large frame, we adjust the stack
6764 pointer before restoring the registers. In this case, we
6765 should always be using a frame pointer, so everything should
6766 have been handled above. */
6767 if (tsize > 32767 && TARGET_MIPS16)
6770 emit_insn (gen_blockage ());
6771 if (Pmode == DImode && tsize != 0)
6772 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
6774 else if (tsize != 0)
6775 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6779 /* The mips16 loads the return address into $7, not $31. */
6780 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
6781 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6782 GP_REG_FIRST + 7)));
6784 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6785 GP_REG_FIRST + 31)));
6788 /* Return nonzero if this function is known to have a null epilogue.
6789 This allows the optimizer to omit jumps to jumps if no stack
6793 mips_can_use_return_insn ()
6795 if (! reload_completed)
6798 if (regs_ever_live[31] || profile_flag)
6801 /* In mips16 mode, a function which returns a floating point value
6802 needs to arrange to copy the return value into the floating point
6805 && mips16_hard_float
6806 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6807 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6809 && (! TARGET_SINGLE_FLOAT
6810 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6814 if (current_frame_info.initialized)
6815 return current_frame_info.total_size == 0;
6817 return compute_frame_size (get_frame_size ()) == 0;
6820 /* Choose the section to use for the constant rtx expression X that has
6824 mips_select_rtx_section (mode, x)
6825 enum machine_mode mode;
6826 rtx x ATTRIBUTE_UNUSED;
6830 /* In mips16 mode, the constant table always goes in the .text
6831 section, so that constants can be loaded using PC relative
6835 else if (TARGET_EMBEDDED_DATA)
6837 /* For embedded applications, always put constants in read-only data,
6838 in order to reduce RAM usage. */
6839 READONLY_DATA_SECTION ();
6843 /* For hosted applications, always put constants in small data if
6844 possible, as this gives the best performance. */
6846 if (GET_MODE_SIZE (mode) <= mips_section_threshold
6847 && mips_section_threshold > 0)
6848 SMALL_DATA_SECTION ();
6850 READONLY_DATA_SECTION ();
6854 /* Choose the section to use for DECL. RELOC is true if its value contains
6855 any relocatable expression. */
6858 mips_select_section (decl, reloc)
6862 int size = int_size_in_bytes (TREE_TYPE (decl));
6864 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
6865 && TREE_CODE (decl) == STRING_CST
6866 && !flag_writable_strings)
6867 /* For embedded position independent code, put constant strings in the
6868 text section, because the data section is limited to 64K in size.
6869 For mips16 code, put strings in the text section so that a PC
6870 relative load instruction can be used to get their address. */
6872 else if (TARGET_EMBEDDED_DATA)
6874 /* For embedded applications, always put an object in read-only data
6875 if possible, in order to reduce RAM usage. */
6877 if (((TREE_CODE (decl) == VAR_DECL
6878 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
6879 && DECL_INITIAL (decl)
6880 && (DECL_INITIAL (decl) == error_mark_node
6881 || TREE_CONSTANT (DECL_INITIAL (decl))))
6882 /* Deal with calls from output_constant_def_contents. */
6883 || (TREE_CODE (decl) != VAR_DECL
6884 && (TREE_CODE (decl) != STRING_CST
6885 || !flag_writable_strings)))
6886 && ! (flag_pic && reloc))
6887 READONLY_DATA_SECTION ();
6888 else if (size > 0 && size <= mips_section_threshold)
6889 SMALL_DATA_SECTION ();
6895 /* For hosted applications, always put an object in small data if
6896 possible, as this gives the best performance. */
6898 if (size > 0 && size <= mips_section_threshold)
6899 SMALL_DATA_SECTION ();
6900 else if (((TREE_CODE (decl) == VAR_DECL
6901 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
6902 && DECL_INITIAL (decl)
6903 && (DECL_INITIAL (decl) == error_mark_node
6904 || TREE_CONSTANT (DECL_INITIAL (decl))))
6905 /* Deal with calls from output_constant_def_contents. */
6906 || (TREE_CODE (decl) != VAR_DECL
6907 && (TREE_CODE (decl) != STRING_CST
6908 || !flag_writable_strings)))
6909 && ! (flag_pic && reloc))
6910 READONLY_DATA_SECTION ();
6916 #ifdef MIPS_ABI_DEFAULT
6918 /* Support functions for the 64 bit ABI. */
6920 /* Return register to use for a function return value with VALTYPE for function
6924 mips_function_value (valtype, func)
6926 tree func ATTRIBUTE_UNUSED;
6928 int reg = GP_RETURN;
6929 enum machine_mode mode = TYPE_MODE (valtype);
6930 enum mode_class mclass = GET_MODE_CLASS (mode);
6931 int unsignedp = TREE_UNSIGNED (valtype);
6933 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
6934 just as PROMOTE_MODE does. */
6935 mode = promote_mode (valtype, mode, &unsignedp, 1);
6937 /* ??? How should we return complex float? */
6938 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6940 if (TARGET_SINGLE_FLOAT
6941 && (mclass == MODE_FLOAT
6942 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
6948 else if (TREE_CODE (valtype) == RECORD_TYPE
6949 && mips_abi != ABI_32 && mips_abi != ABI_EABI)
6951 /* A struct with only one or two floating point fields is returned in
6952 the floating point registers. */
6953 tree field, fields[2];
6956 for (i = 0, field = TYPE_FIELDS (valtype); field;
6957 field = TREE_CHAIN (field))
6959 if (TREE_CODE (field) != FIELD_DECL)
6962 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
6965 fields[i++] = field;
6968 /* Must check i, so that we reject structures with no elements. */
6973 /* The structure has DImode, but we don't allow DImode values
6974 in FP registers, so we use a PARALLEL even though it isn't
6975 strictly necessary. */
6976 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
6978 return gen_rtx (PARALLEL, mode,
6980 gen_rtx (EXPR_LIST, VOIDmode,
6981 gen_rtx (REG, field_mode,
6988 enum machine_mode first_mode
6989 = TYPE_MODE (TREE_TYPE (fields[0]));
6990 enum machine_mode second_mode
6991 = TYPE_MODE (TREE_TYPE (fields[1]));
6993 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
6995 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
6997 return gen_rtx (PARALLEL, mode,
6999 gen_rtx (EXPR_LIST, VOIDmode,
7000 gen_rtx (REG, first_mode,
7002 GEN_INT (first_offset
7004 gen_rtx (EXPR_LIST, VOIDmode,
7005 gen_rtx (REG, second_mode,
7007 GEN_INT (second_offset
7008 / BITS_PER_UNIT))));
7013 return gen_rtx (REG, mode, reg);
7016 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7017 nonzero when an argument must be passed by reference. */
7020 function_arg_pass_by_reference (cum, mode, type, named)
7021 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
7022 enum machine_mode mode;
7024 int named ATTRIBUTE_UNUSED;
7028 if (mips_abi != ABI_EABI)
7031 /* ??? How should SCmode be handled? */
7032 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7035 size = int_size_in_bytes (type);
7036 return size == -1 || size > UNITS_PER_WORD;
7040 /* This function returns the register class required for a secondary
7041 register when copying between one of the registers in CLASS, and X,
7042 using MODE. If IN_P is nonzero, the copy is going from X to the
7043 register, otherwise the register is the source. A return value of
7044 NO_REGS means that no secondary register is required. */
7047 mips_secondary_reload_class (class, mode, x, in_p)
7048 enum reg_class class;
7049 enum machine_mode mode;
7053 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7057 if (GET_CODE (x) == SIGN_EXTEND)
7063 /* We may be called with reg_renumber NULL from regclass.
7064 ??? This is probably a bug. */
7066 regno = true_regnum (x);
7069 while (GET_CODE (x) == SUBREG)
7071 off += SUBREG_WORD (x);
7075 if (GET_CODE (x) == REG)
7076 regno = REGNO (x) + off;
7080 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7081 regno = true_regnum (x);
7083 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7085 /* We always require a general register when copying anything to
7086 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7087 to a general register, or when copying from register 0. */
7088 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
7091 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7092 ? NO_REGS : gr_regs);
7093 else if (regno == HILO_REGNUM)
7096 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7097 ? NO_REGS : gr_regs);
7099 /* Copying from HI or LO to anywhere other than a general register
7100 requires a general register. */
7101 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7103 if (TARGET_MIPS16 && in_p)
7105 /* We can't really copy to HI or LO at all in mips16 mode. */
7108 return gp_reg_p ? NO_REGS : gr_regs;
7110 if (MD_REG_P (regno))
7112 if (TARGET_MIPS16 && ! in_p)
7114 /* We can't really copy to HI or LO at all in mips16 mode. */
7117 return class == gr_regs ? NO_REGS : gr_regs;
7120 /* We can only copy a value to a condition code register from a
7121 floating point register, and even then we require a scratch
7122 floating point register. We can only copy a value out of a
7123 condition code register into a general register. */
7124 if (class == ST_REGS)
7128 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
7130 if (ST_REG_P (regno))
7134 return class == GR_REGS ? NO_REGS : GR_REGS;
7137 /* In mips16 mode, going between memory and anything but M16_REGS
7138 requires an M16_REG. */
7141 if (class != M16_REGS && class != M16_NA_REGS)
7149 if (class == M16_REGS || class == M16_NA_REGS)
7158 /* For each mips16 function which refers to GP relative symbols, we
7159 use a pseudo register, initialized at the start of the function, to
7160 hold the $gp value. */
7163 mips16_gp_pseudo_reg ()
7165 if (mips16_gp_pseudo_rtx == NULL_RTX)
7170 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7171 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
7173 /* We want to initialize this to a value which gcc will believe
7175 const_gp = gen_rtx (CONST, Pmode,
7176 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
7179 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
7180 insn = gen_sequence ();
7183 push_topmost_sequence ();
7184 /* We need to emit the initialization after the FUNCTION_BEG
7185 note, so that it will be integrated. */
7186 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7187 if (GET_CODE (scan) == NOTE
7188 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7190 if (scan == NULL_RTX)
7191 scan = get_insns ();
7192 insn = emit_insn_after (insn, scan);
7193 pop_topmost_sequence ();
7196 return mips16_gp_pseudo_rtx;
7199 /* Return an RTX which represents the signed 16 bit offset from the
7200 $gp register for the given symbol. This is only used on the
7204 mips16_gp_offset (sym)
7209 if (GET_CODE (sym) != SYMBOL_REF
7210 || ! SYMBOL_REF_FLAG (sym))
7213 /* We use a special identifier to represent the value of the gp
7215 gp = get_identifier ("__mips16_gp_value");
7217 return gen_rtx (CONST, Pmode,
7218 gen_rtx (MINUS, Pmode, sym,
7219 gen_rtx (SYMBOL_REF, Pmode,
7220 IDENTIFIER_POINTER (gp))));
7223 /* Return nonzero if the given RTX represents a signed 16 bit offset
7224 from the $gp register. */
7227 mips16_gp_offset_p (x)
7230 if (GET_CODE (x) == CONST)
7233 /* It's OK to add a small integer value to a gp offset. */
7234 if (GET_CODE (x) == PLUS)
7236 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7237 && SMALL_INT (XEXP (x, 1)))
7238 return mips16_gp_offset_p (XEXP (x, 0));
7239 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7240 && SMALL_INT (XEXP (x, 0)))
7241 return mips16_gp_offset_p (XEXP (x, 1));
7245 /* Make sure it is in the form SYM - __mips16_gp_value. */
7246 return (GET_CODE (x) == MINUS
7247 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
7248 && SYMBOL_REF_FLAG (XEXP (x, 0))
7249 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7250 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
7253 /* Output a GP offset. We don't want to print the subtraction of
7254 __mips16_gp_value; it is implicitly represented by the %gprel which
7255 should have been printed by the caller. */
7258 mips16_output_gp_offset (file, x)
7262 if (GET_CODE (x) == CONST)
7265 if (GET_CODE (x) == PLUS)
7267 mips16_output_gp_offset (file, XEXP (x, 0));
7269 mips16_output_gp_offset (file, XEXP (x, 1));
7273 if (GET_CODE (x) == MINUS
7274 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7275 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
7277 mips16_output_gp_offset (file, XEXP (x, 0));
7281 output_addr_const (file, x);
7284 /* Return nonzero if a constant should not be output until after the
7285 function. This is true of most string constants, so that we can
7286 use a more efficient PC relative reference. However, a static
7287 inline function may never call assemble_function_end to write out
7288 the constant pool, so don't try to postpone the constant in that
7291 ??? It's really a bug that a static inline function can put stuff
7292 in the constant pool even if the function itself is not output.
7294 We record which string constants we've seen, so that we know which
7295 ones might use the more efficient reference. */
7298 mips16_constant_after_function_p (x)
7301 if (TREE_CODE (x) == STRING_CST
7302 && ! flag_writable_strings
7303 && current_function_decl != 0
7304 && ! DECL_DEFER_OUTPUT (current_function_decl)
7305 && ! (DECL_INLINE (current_function_decl)
7306 && ((! TREE_PUBLIC (current_function_decl)
7307 && ! TREE_ADDRESSABLE (current_function_decl)
7308 && ! flag_keep_inline_functions)
7309 || DECL_EXTERNAL (current_function_decl))))
7311 struct string_constant *n;
7313 n = (struct string_constant *) xmalloc (sizeof *n);
7314 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
7315 n->next = string_constants;
7316 string_constants = n;
7324 /* Validate a constant for the mips16. This rejects general symbolic
7325 addresses, which must be loaded from memory. If ADDR is nonzero,
7326 this should reject anything which is not a legal address. If
7327 ADDEND is nonzero, this is being added to something else. */
7330 mips16_constant (x, mode, addr, addend)
7332 enum machine_mode mode;
7336 while (GET_CODE (x) == CONST)
7339 switch (GET_CODE (x))
7345 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
7346 && mips16_constant (XEXP (x, 1), mode, addr, 1));
7349 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7351 if (CONSTANT_POOL_ADDRESS_P (x))
7354 /* If we aren't looking for a memory address, we can accept a GP
7355 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
7356 knows how to handle this. We can always accept a string
7357 constant, which is the other case in which SYMBOL_REF_FLAG
7359 if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode)
7362 /* We can accept a string constant, which will have
7363 SYMBOL_REF_FLAG set but must be recognized by name to
7364 distinguish from a GP accessible symbol. The name of a
7365 string constant will have been generated by
7366 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
7367 if (SYMBOL_REF_FLAG (x))
7369 char *name = XSTR (x, 0);
7371 return (name[0] == '*'
7372 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
7373 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
7379 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7384 if (addr && ! addend)
7386 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
7389 /* We need to treat $gp as a legitimate constant, because
7390 mips16_gp_pseudo_reg assumes that. */
7391 return REGNO (x) == GP_REG_FIRST + 28;
7395 /* Write out code to move floating point arguments in or out of
7396 general registers. Output the instructions to FILE. FP_CODE is
7397 the code describing which arguments are present (see the comment at
7398 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
7399 we are copying from the floating point registers. */
7402 mips16_fp_args (file, fp_code, from_fp_p)
7411 /* This code only works for the original 32 bit ABI. */
7412 if (mips_abi != ABI_32)
7419 gparg = GP_ARG_FIRST;
7420 fparg = FP_ARG_FIRST;
7421 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7425 if ((fparg & 1) != 0)
7427 fprintf (file, "\t%s\t%s,%s\n", s,
7428 reg_names[gparg], reg_names[fparg]);
7430 else if ((f & 3) == 2)
7433 fprintf (file, "\td%s\t%s,%s\n", s,
7434 reg_names[gparg], reg_names[fparg]);
7437 if ((fparg & 1) != 0)
7439 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7440 reg_names[gparg], reg_names[fparg + 1], s,
7441 reg_names[gparg + 1], reg_names[fparg]);
7454 /* Build a mips16 function stub. This is used for functions which
7455 take aruments in the floating point registers. It is 32 bit code
7456 that moves the floating point args into the general registers, and
7457 then jumps to the 16 bit code. */
7460 build_mips16_function_stub (file)
7464 char *secname, *stubname;
7465 tree stubid, stubdecl;
7469 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7470 secname = (char *) alloca (strlen (fnname) + 20);
7471 sprintf (secname, ".mips16.fn.%s", fnname);
7472 stubname = (char *) alloca (strlen (fnname) + 20);
7473 sprintf (stubname, "__fn_stub_%s", fnname);
7474 stubid = get_identifier (stubname);
7475 stubdecl = build_decl (FUNCTION_DECL, stubid,
7476 build_function_type (void_type_node, NULL_TREE));
7477 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7479 fprintf (file, "\t# Stub function for %s (", current_function_name);
7481 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7483 fprintf (file, "%s%s",
7484 need_comma ? ", " : "",
7485 (f & 3) == 1 ? "float" : "double");
7488 fprintf (file, ")\n");
7490 fprintf (file, "\t.set\tnomips16\n");
7491 function_section (stubdecl);
7492 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7494 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7495 within a .ent, and we can not emit another .ent. */
7496 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7497 fputs ("\t.ent\t", file);
7498 assemble_name (file, stubname);
7502 assemble_name (file, stubname);
7503 fputs (":\n", file);
7505 /* We don't want the assembler to insert any nops here. */
7506 fprintf (file, "\t.set\tnoreorder\n");
7508 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7510 fprintf (asm_out_file, "\t.set\tnoat\n");
7511 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7512 assemble_name (file, fnname);
7513 fprintf (file, "\n");
7514 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7515 fprintf (asm_out_file, "\t.set\tat\n");
7517 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7518 with one of the mfc1 instructions, because the result is not
7519 available for one instruction, so if the very first instruction
7520 in the function refers to the register, it will see the wrong
7522 fprintf (file, "\tnop\n");
7524 fprintf (file, "\t.set\treorder\n");
7526 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7527 fputs ("\t.end\t", file);
7528 assemble_name (file, stubname);
7532 fprintf (file, "\t.set\tmips16\n");
7534 function_section (current_function_decl);
7537 /* We keep a list of functions for which we have already built stubs
7538 in build_mips16_call_stub. */
7542 struct mips16_stub *next;
7547 static struct mips16_stub *mips16_stubs;
7549 /* Build a call stub for a mips16 call. A stub is needed if we are
7550 passing any floating point values which should go into the floating
7551 point registers. If we are, and the call turns out to be to a 32
7552 bit function, the stub will be used to move the values into the
7553 floating point registers before calling the 32 bit function. The
7554 linker will magically adjust the function call to either the 16 bit
7555 function or the 32 bit stub, depending upon where the function call
7556 is actually defined.
7558 Similarly, we need a stub if the return value might come back in a
7559 floating point register.
7561 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
7562 (RETVAL is NULL if this is call rather than call_value). FP_CODE
7563 is the code built by function_arg. This function returns a nonzero
7564 value if it builds the call instruction itself. */
7567 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
7575 char *fnname, *secname, *stubname;
7576 struct mips16_stub *l;
7577 tree stubid, stubdecl;
7581 /* We don't need to do anything if we aren't in mips16 mode, or if
7582 we were invoked with the -msoft-float option. */
7583 if (! TARGET_MIPS16 || ! mips16_hard_float)
7586 /* Figure out whether the value might come back in a floating point
7588 fpret = (retval != 0
7589 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7590 && (! TARGET_SINGLE_FLOAT
7591 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
7593 /* We don't need to do anything if there were no floating point
7594 arguments and the value will not be returned in a floating point
7596 if (fp_code == 0 && ! fpret)
7599 if (GET_CODE (fnmem) != MEM)
7601 fn = XEXP (fnmem, 0);
7603 /* We don't need to do anything if this is a call to a special
7604 mips16 support function. */
7605 if (GET_CODE (fn) == SYMBOL_REF
7606 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7609 /* This code will only work for the standard ABI. The other ABI's
7610 require more sophisticated support. */
7611 if (mips_abi != ABI_32)
7614 /* We can only handle SFmode and DFmode floating point return
7616 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
7619 /* If we're calling via a function pointer, then we must always call
7620 via a stub. There are magic stubs provided in libgcc.a for each
7621 of the required cases. Each of them expects the function address
7622 to arrive in register $2. */
7624 if (GET_CODE (fn) != SYMBOL_REF)
7628 rtx stub_fn, stub_mem, insn;
7630 /* ??? If this code is modified to support other ABI's, we need
7631 to handle PARALLEL return values here. */
7633 sprintf (buf, "__mips16_call_stub_%s%d",
7635 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7638 id = get_identifier (buf);
7639 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
7640 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
7642 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
7644 if (retval == NULL_RTX)
7645 insn = gen_call_internal0 (stub_mem, arg_size,
7646 gen_rtx (REG, SImode,
7647 GP_REG_FIRST + 31));
7649 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
7650 gen_rtx (REG, SImode,
7651 GP_REG_FIRST + 31));
7652 insn = emit_call_insn (insn);
7654 /* Put the register usage information on the CALL. */
7655 if (GET_CODE (insn) != CALL_INSN)
7657 CALL_INSN_FUNCTION_USAGE (insn) =
7658 gen_rtx (EXPR_LIST, VOIDmode,
7659 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
7660 CALL_INSN_FUNCTION_USAGE (insn));
7662 /* If we are handling a floating point return value, we need to
7663 save $18 in the function prologue. Putting a note on the
7664 call will mean that regs_ever_live[$18] will be true if the
7665 call is not eliminated, and we can check that in the prologue
7668 CALL_INSN_FUNCTION_USAGE (insn) =
7669 gen_rtx (EXPR_LIST, VOIDmode,
7670 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7671 CALL_INSN_FUNCTION_USAGE (insn));
7673 /* Return 1 to tell the caller that we've generated the call
7678 /* We know the function we are going to call. If we have already
7679 built a stub, we don't need to do anything further. */
7681 fnname = XSTR (fn, 0);
7682 for (l = mips16_stubs; l != NULL; l = l->next)
7683 if (strcmp (l->name, fnname) == 0)
7688 /* Build a special purpose stub. When the linker sees a
7689 function call in mips16 code, it will check where the target
7690 is defined. If the target is a 32 bit call, the linker will
7691 search for the section defined here. It can tell which
7692 symbol this section is associated with by looking at the
7693 relocation information (the name is unreliable, since this
7694 might be a static function). If such a section is found, the
7695 linker will redirect the call to the start of the magic
7698 If the function does not return a floating point value, the
7699 special stub section is named
7702 If the function does return a floating point value, the stub
7704 .mips16.call.fp.FNNAME
7707 secname = (char *) alloca (strlen (fnname) + 40);
7708 sprintf (secname, ".mips16.call.%s%s",
7711 stubname = (char *) alloca (strlen (fnname) + 20);
7712 sprintf (stubname, "__call_stub_%s%s",
7715 stubid = get_identifier (stubname);
7716 stubdecl = build_decl (FUNCTION_DECL, stubid,
7717 build_function_type (void_type_node, NULL_TREE));
7718 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7720 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7722 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7726 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7728 fprintf (asm_out_file, "%s%s",
7729 need_comma ? ", " : "",
7730 (f & 3) == 1 ? "float" : "double");
7733 fprintf (asm_out_file, ")\n");
7735 fprintf (asm_out_file, "\t.set\tnomips16\n");
7736 assemble_start_function (stubdecl, stubname);
7738 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7739 fputs ("\t.ent\t", asm_out_file);
7740 assemble_name (asm_out_file, stubname);
7741 fputs ("\n", asm_out_file);
7743 assemble_name (asm_out_file, stubname);
7744 fputs (":\n", asm_out_file);
7747 /* We build the stub code by hand. That's the only way we can
7748 do it, since we can't generate 32 bit code during a 16 bit
7751 /* We don't want the assembler to insert any nops here. */
7752 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7754 mips16_fp_args (asm_out_file, fp_code, 0);
7758 fprintf (asm_out_file, "\t.set\tnoat\n");
7759 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7761 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7762 fprintf (asm_out_file, "\t.set\tat\n");
7763 /* Unfortunately, we can't fill the jump delay slot. We
7764 can't fill with one of the mtc1 instructions, because the
7765 result is not available for one instruction, so if the
7766 very first instruction in the function refers to the
7767 register, it will see the wrong value. */
7768 fprintf (asm_out_file, "\tnop\n");
7772 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7773 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7774 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7775 /* As above, we can't fill the delay slot. */
7776 fprintf (asm_out_file, "\tnop\n");
7777 if (GET_MODE (retval) == SFmode)
7778 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7779 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7782 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7783 reg_names[GP_REG_FIRST + 2],
7784 reg_names[FP_REG_FIRST + 1]);
7785 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7786 reg_names[GP_REG_FIRST + 3],
7787 reg_names[FP_REG_FIRST + 0]);
7789 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7790 /* As above, we can't fill the delay slot. */
7791 fprintf (asm_out_file, "\tnop\n");
7794 fprintf (asm_out_file, "\t.set\treorder\n");
7796 #ifdef ASM_DECLARE_FUNCTION_SIZE
7797 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7800 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7801 fputs ("\t.end\t", asm_out_file);
7802 assemble_name (asm_out_file, stubname);
7803 fputs ("\n", asm_out_file);
7806 fprintf (asm_out_file, "\t.set\tmips16\n");
7808 /* Record this stub. */
7809 l = (struct mips16_stub *) xmalloc (sizeof *l);
7810 l->name = (char *) xmalloc (strlen (fnname) + 1);
7811 strcpy (l->name, fnname);
7813 l->next = mips16_stubs;
7817 /* If we expect a floating point return value, but we've built a
7818 stub which does not expect one, then we're in trouble. We can't
7819 use the existing stub, because it won't handle the floating point
7820 value. We can't build a new stub, because the linker won't know
7821 which stub to use for the various calls in this object file.
7822 Fortunately, this case is illegal, since it means that a function
7823 was declared in two different ways in a single compilation. */
7824 if (fpret && ! l->fpret)
7825 error ("can not handle inconsistent calls to `%s'", fnname);
7827 /* If we are calling a stub which handles a floating point return
7828 value, we need to arrange to save $18 in the prologue. We do
7829 this by marking the function call as using the register. The
7830 prologue will later see that it is used, and emit code to save
7837 if (retval == NULL_RTX)
7838 insn = gen_call_internal0 (fnmem, arg_size,
7839 gen_rtx (REG, SImode,
7840 GP_REG_FIRST + 31));
7842 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
7843 gen_rtx (REG, SImode,
7844 GP_REG_FIRST + 31));
7845 insn = emit_call_insn (insn);
7847 if (GET_CODE (insn) != CALL_INSN)
7850 CALL_INSN_FUNCTION_USAGE (insn) =
7851 gen_rtx (EXPR_LIST, VOIDmode,
7852 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7853 CALL_INSN_FUNCTION_USAGE (insn));
7855 /* Return 1 to tell the caller that we've generated the call
7860 /* Return 0 to let the caller generate the call insn. */
7864 /* This function looks through the code for a function, and tries to
7865 optimize the usage of the $gp register. We arrange to copy $gp
7866 into a pseudo-register, and then let gcc's normal reload handling
7867 deal with the pseudo-register. Unfortunately, if reload choose to
7868 put the pseudo-register into a call-clobbered register, it will
7869 emit saves and restores for that register around any function
7870 calls. We don't need the saves, and it's faster to copy $gp than
7871 to do an actual restore. ??? This still means that we waste a
7874 This is an optimization, and the code which gcc has actually
7875 generated is correct, so we do not need to catch all cases. */
7878 mips16_optimize_gp (first)
7881 rtx gpcopy, slot, insn;
7883 /* Look through the instructions. Set GPCOPY to the register which
7884 holds a copy of $gp. Set SLOT to the stack slot where it is
7885 saved. If we find an instruction which sets GPCOPY to anything
7886 other than $gp or SLOT, then we can't use it. If we find an
7887 instruction which sets SLOT to anything other than GPCOPY, we
7892 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
7896 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7899 set = PATTERN (insn);
7901 /* We know that all references to memory will be inside a SET,
7902 because there is no other way to access memory on the mips16.
7903 We don't have to worry about a PARALLEL here, because the
7904 mips.md file will never generate them for memory references. */
7905 if (GET_CODE (set) != SET)
7908 if (gpcopy == NULL_RTX
7909 && GET_CODE (SET_SRC (set)) == CONST
7910 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
7911 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
7912 && GET_CODE (SET_DEST (set)) == REG
7913 && GET_MODE (SET_DEST (set)) == Pmode)
7914 gpcopy = SET_DEST (set);
7915 else if (slot == NULL_RTX
7916 && gpcopy != NULL_RTX
7917 && GET_CODE (SET_DEST (set)) == MEM
7918 && GET_CODE (SET_SRC (set)) == REG
7919 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
7920 && GET_MODE (SET_DEST (set)) == Pmode)
7924 offset = const0_rtx;
7925 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
7926 if (GET_CODE (base) == REG
7927 && (REGNO (base) == STACK_POINTER_REGNUM
7928 || REGNO (base) == FRAME_POINTER_REGNUM))
7929 slot = SET_DEST (set);
7931 else if (gpcopy != NULL_RTX
7932 && (GET_CODE (SET_DEST (set)) == REG
7933 || GET_CODE (SET_DEST (set)) == SUBREG)
7934 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
7935 && (GET_CODE (SET_DEST (set)) != REG
7936 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
7937 || GET_MODE (SET_DEST (set)) != Pmode
7938 || ((GET_CODE (SET_SRC (set)) != CONST
7939 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
7940 || (REGNO (XEXP (SET_SRC (set), 0))
7941 != GP_REG_FIRST + 28))
7942 && ! rtx_equal_p (SET_SRC (set), slot))))
7944 else if (slot != NULL_RTX
7945 && GET_CODE (SET_DEST (set)) == MEM
7946 && rtx_equal_p (SET_DEST (set), slot)
7947 && (GET_CODE (SET_SRC (set)) != REG
7948 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
7952 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
7953 different optimization. Any time we find a copy of $28 into a
7954 register, followed by an add of a symbol_ref to that register, we
7955 convert it to load the value from the constant table instead.
7956 The copy and add will take six bytes, just as the load and
7957 constant table entry will take six bytes. However, it is
7958 possible that the constant table entry will be shared.
7960 This could be a peephole optimization, but I don't know if the
7961 peephole code can call force_const_mem.
7963 Using the same register for the copy of $28 and the add of the
7964 symbol_ref is actually pretty likely, since the add instruction
7965 requires the destination and the first addend to be the same
7968 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
7972 /* This optimization is only reasonable if the constant table
7973 entries are only 4 bytes. */
7974 if (Pmode != SImode)
7977 for (insn = first; insn != NULL_RTX; insn = next)
7984 next = NEXT_INSN (next);
7986 while (next != NULL_RTX
7987 && (GET_CODE (next) == NOTE
7988 || (GET_CODE (next) == INSN
7989 && (GET_CODE (PATTERN (next)) == USE
7990 || GET_CODE (PATTERN (next)) == CLOBBER))));
7992 if (next == NULL_RTX)
7995 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7998 if (GET_RTX_CLASS (GET_CODE (next)) != 'i')
8001 set1 = PATTERN (insn);
8002 if (GET_CODE (set1) != SET)
8004 set2 = PATTERN (next);
8005 if (GET_CODE (set2) != SET)
8008 if (GET_CODE (SET_DEST (set1)) == REG
8009 && GET_CODE (SET_SRC (set1)) == CONST
8010 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8011 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8012 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8013 && GET_CODE (SET_SRC (set2)) == PLUS
8014 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8015 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8016 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8020 /* We've found a case we can change to load from the
8023 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8024 if (GET_CODE (sym) != SYMBOL_REF)
8026 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8027 force_const_mem (Pmode, sym)),
8030 PUT_CODE (insn, NOTE);
8031 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8032 NOTE_SOURCE_FILE (insn) = 0;
8034 PUT_CODE (next, NOTE);
8035 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8036 NOTE_SOURCE_FILE (next) = 0;
8043 /* We can safely remove all assignments to SLOT from GPCOPY, and
8044 replace all assignments from SLOT to GPCOPY with assignments from
8047 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8051 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8054 set = PATTERN (insn);
8055 if (GET_CODE (set) != SET
8056 || GET_MODE (SET_DEST (set)) != Pmode)
8059 if (GET_CODE (SET_DEST (set)) == MEM
8060 && rtx_equal_p (SET_DEST (set), slot)
8061 && GET_CODE (SET_SRC (set)) == REG
8062 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8064 PUT_CODE (insn, NOTE);
8065 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8066 NOTE_SOURCE_FILE (insn) = 0;
8068 else if (GET_CODE (SET_DEST (set)) == REG
8069 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8070 && GET_CODE (SET_SRC (set)) == MEM
8071 && rtx_equal_p (SET_SRC (set), slot))
8073 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
8074 gen_rtx (CONST, Pmode,
8075 gen_rtx (REG, Pmode,
8076 GP_REG_FIRST + 28))),
8078 PUT_CODE (insn, NOTE);
8079 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8080 NOTE_SOURCE_FILE (insn) = 0;
8085 /* We keep a list of constants we which we have to add to internal
8086 constant tables in the middle of large functions. */
8090 struct constant *next;
8093 enum machine_mode mode;
8096 /* Add a constant to the list in *PCONSTANTS. */
8099 add_constant (pconstants, val, mode)
8100 struct constant **pconstants;
8102 enum machine_mode mode;
8106 for (c = *pconstants; c != NULL; c = c->next)
8107 if (mode == c->mode && rtx_equal_p (val, c->value))
8110 c = (struct constant *) xmalloc (sizeof *c);
8113 c->label = gen_label_rtx ();
8114 c->next = *pconstants;
8119 /* Dump out the constants in CONSTANTS after INSN. */
8122 dump_constants (constants, insn)
8123 struct constant *constants;
8134 struct constant *next;
8136 switch (GET_MODE_SIZE (c->mode))
8143 insn = emit_insn_after (gen_align_2 (), insn);
8148 insn = emit_insn_after (gen_align_4 (), insn);
8153 insn = emit_insn_after (gen_align_8 (), insn);
8158 insn = emit_label_after (c->label, insn);
8163 r = gen_consttable_qi (c->value);
8166 r = gen_consttable_hi (c->value);
8169 r = gen_consttable_si (c->value);
8172 r = gen_consttable_sf (c->value);
8175 r = gen_consttable_di (c->value);
8178 r = gen_consttable_df (c->value);
8184 insn = emit_insn_after (r, insn);
8191 emit_barrier_after (insn);
8194 /* Find the symbol in an address expression. */
8197 mips_find_symbol (addr)
8200 if (GET_CODE (addr) == MEM)
8201 addr = XEXP (addr, 0);
8202 while (GET_CODE (addr) == CONST)
8203 addr = XEXP (addr, 0);
8204 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8206 if (GET_CODE (addr) == PLUS)
8210 l1 = mips_find_symbol (XEXP (addr, 0));
8211 l2 = mips_find_symbol (XEXP (addr, 1));
8212 if (l1 != NULL_RTX && l2 == NULL_RTX)
8214 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8220 /* Exported to toplev.c.
8222 Do a final pass over the function, just before delayed branch
8226 machine_dependent_reorg (first)
8229 int insns_len, max_internal_pool_size, pool_size, addr;
8231 struct constant *constants;
8233 if (! TARGET_MIPS16)
8236 /* If $gp is used, try to remove stores, and replace loads with
8239 mips16_optimize_gp (first);
8241 /* Scan the function looking for PC relative loads which may be out
8242 of range. All such loads will either be from the constant table,
8243 or be getting the address of a constant string. If the size of
8244 the function plus the size of the constant table is less than
8245 0x8000, then all loads are in range. */
8248 for (insn = first; insn; insn = NEXT_INSN (insn))
8250 insns_len += get_attr_length (insn) * 2;
8252 /* ??? We put switch tables in .text, but we don't define
8253 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8254 compute their lengths correctly. */
8255 if (GET_CODE (insn) == JUMP_INSN)
8259 body = PATTERN (insn);
8260 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8261 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8262 * GET_MODE_SIZE (GET_MODE (body)));
8263 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8267 /* Store the original value of insns_len in current_frame_info, so
8268 that simple_memory_operand can look at it. */
8269 current_frame_info.insns_len = insns_len;
8271 pool_size = get_pool_size ();
8272 if (insns_len + pool_size + mips_string_length < 0x8000)
8275 /* Loop over the insns and figure out what the maximum internal pool
8277 max_internal_pool_size = 0;
8278 for (insn = first; insn; insn = NEXT_INSN (insn))
8280 if (GET_CODE (insn) == INSN
8281 && GET_CODE (PATTERN (insn)) == SET)
8285 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8286 if (src == NULL_RTX)
8288 if (CONSTANT_POOL_ADDRESS_P (src))
8289 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8290 else if (SYMBOL_REF_FLAG (src))
8291 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8298 for (insn = first; insn; insn = NEXT_INSN (insn))
8300 if (GET_CODE (insn) == INSN
8301 && GET_CODE (PATTERN (insn)) == SET)
8304 enum machine_mode mode;
8307 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8308 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8310 /* ??? This is very conservative, which means that we
8311 will generate too many copies of the constant table.
8312 The only solution would seem to be some form of
8314 if (((insns_len - addr)
8315 + max_internal_pool_size
8316 + get_pool_offset (src))
8319 val = get_pool_constant (src);
8320 mode = get_pool_mode (src);
8322 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8324 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8326 /* Including all of mips_string_length is conservative,
8327 and so is including all of max_internal_pool_size. */
8328 if (((insns_len - addr)
8329 + max_internal_pool_size
8331 + mips_string_length)
8335 max_internal_pool_size -= Pmode;
8338 if (val != NULL_RTX)
8342 /* This PC relative load is out of range. ??? In the
8343 case of a string constant, we are only guessing that
8344 it is range, since we don't know the offset of a
8345 particular string constant. */
8347 lab = add_constant (&constants, val, mode);
8348 newsrc = gen_rtx (MEM, mode,
8349 gen_rtx (LABEL_REF, VOIDmode, lab));
8350 RTX_UNCHANGING_P (newsrc) = 1;
8351 PATTERN (insn) = gen_rtx (SET, VOIDmode,
8352 SET_DEST (PATTERN (insn)),
8354 INSN_CODE (insn) = -1;
8358 addr += get_attr_length (insn) * 2;
8360 /* ??? We put switch tables in .text, but we don't define
8361 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8362 compute their lengths correctly. */
8363 if (GET_CODE (insn) == JUMP_INSN)
8367 body = PATTERN (insn);
8368 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8369 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8370 * GET_MODE_SIZE (GET_MODE (body)));
8371 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8374 if (GET_CODE (insn) == BARRIER)
8376 /* Output any constants we have accumulated. Note that we
8377 don't need to change ADDR, since its only use is
8378 subtraction from INSNS_LEN, and both would be changed by
8380 ??? If the instructions up to the next barrier reuse a
8381 constant, it would often be better to continue
8383 if (constants != NULL)
8384 dump_constants (constants, insn);
8388 /* ??? If we don't find a barrier within 0x8000 bytes of
8389 instructions and constants in CONSTANTS, we need to invent
8390 one. This seems sufficiently unlikely that I am not going to
8394 if (constants != NULL)
8396 rtx label, jump, barrier;
8398 label = gen_label_rtx ();
8399 jump = emit_jump_insn_after (gen_jump (label), get_last_insn ());
8400 JUMP_LABEL (jump) = label;
8401 LABEL_NUSES (label) = 1;
8402 barrier = emit_barrier_after (jump);
8403 emit_label_after (label, barrier);
8404 dump_constants (constants, barrier);
8408 /* ??? If we output all references to a constant in internal
8409 constants table, we don't need to output the constant in the real
8410 constant table, but we have no way to prevent that. */
8413 /* Return nonzero if X is a SIGN or ZERO extend operator. */
8415 extend_operator (x, mode)
8417 enum machine_mode mode ATTRIBUTE_UNUSED;
8419 enum rtx_code code = GET_CODE (x);
8420 return code == SIGN_EXTEND || code == ZERO_EXTEND;
8423 /* Accept any operator that can be used to shift the high half of the
8424 input value to the lower half, suitable for truncation. The
8425 remainder (the lower half of the input, and the upper half of the
8426 output) will be discarded. */
8428 highpart_shift_operator (x, mode)
8430 enum machine_mode mode ATTRIBUTE_UNUSED;
8432 enum rtx_code code = GET_CODE (x);
8433 return (code == LSHIFTRT