1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-flags.h"
40 #include "insn-attr.h"
41 #include "insn-codes.h"
55 #if defined(USG) || !defined(HAVE_STAB_H)
56 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
58 #include <stab.h> /* On BSD, use the system's stab.h. */
62 #define STAB_CODE_TYPE enum __stab_debug_code
64 #define STAB_CODE_TYPE int
67 extern char *mktemp PARAMS ((char *));
68 extern tree lookup_name PARAMS ((tree));
70 /* Enumeration for all of the relational tests, so that we can build
71 arrays indexed by the test type, and not worry about the order
90 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
91 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
93 static int m16_check_op PARAMS ((rtx, int, int, int));
94 static void block_move_loop PARAMS ((rtx, rtx,
98 static void block_move_call PARAMS ((rtx, rtx, rtx));
99 static FILE *mips_make_temp_file PARAMS ((void));
100 static void save_restore_insns PARAMS ((int, rtx,
102 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
103 static void mips16_fp_args PARAMS ((FILE *, int, int));
104 static void build_mips16_function_stub PARAMS ((FILE *));
105 static void mips16_optimize_gp PARAMS ((rtx));
106 static rtx add_constant PARAMS ((struct constant **,
109 static void dump_constants PARAMS ((struct constant *,
111 static rtx mips_find_symbol PARAMS ((rtx));
112 static void abort_with_insn PARAMS ((rtx, const char *))
114 static int symbolic_expression_p PARAMS ((rtx));
115 static void mips_add_gc_roots PARAMS ((void));
117 /* Global variables for machine-dependent things. */
119 /* Threshold for data being put into the small data/bss area, instead
120 of the normal data area (references to the small data/bss area take
121 1 instruction, and use the global pointer, references to the normal
122 data area takes 2 instructions). */
123 int mips_section_threshold = -1;
125 /* Count the number of .file directives, so that .loc is up to date. */
126 int num_source_filenames = 0;
128 /* Count the number of sdb related labels are generated (to find block
129 start and end boundaries). */
130 int sdb_label_count = 0;
132 /* Next label # for each statement for Silicon Graphics IRIS systems. */
135 /* Non-zero if inside of a function, because the stupid MIPS asm can't
136 handle .files inside of functions. */
137 int inside_function = 0;
139 /* Files to separate the text and the data output, so that all of the data
140 can be emitted before the text, which will mean that the assembler will
141 generate smaller code, based on the global pointer. */
142 FILE *asm_out_data_file;
143 FILE *asm_out_text_file;
145 /* Linked list of all externals that are to be emitted when optimizing
146 for the global pointer if they haven't been declared by the end of
147 the program with an appropriate .comm or initialization. */
151 struct extern_list *next; /* next external */
152 const char *name; /* name of the external */
153 int size; /* size in bytes */
156 /* Name of the file containing the current function. */
157 const char *current_function_file = "";
159 /* Warning given that Mips ECOFF can't support changing files
160 within a function. */
161 int file_in_function_warning = FALSE;
163 /* Whether to suppress issuing .loc's because the user attempted
164 to change the filename within a function. */
165 int ignore_line_number = FALSE;
167 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
173 /* The next branch instruction is a branch likely, not branch normal. */
174 int mips_branch_likely;
176 /* Count of delay slots and how many are filled. */
177 int dslots_load_total;
178 int dslots_load_filled;
179 int dslots_jump_total;
180 int dslots_jump_filled;
182 /* # of nops needed by previous insn */
183 int dslots_number_nops;
185 /* Number of 1/2/3 word references to data items (ie, not jal's). */
188 /* registers to check for load delay */
189 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
191 /* Cached operands, and operator to compare for use in set/branch/trap
192 on condition codes. */
195 /* what type of branch to use */
196 enum cmp_type branch_type;
198 /* Number of previously seen half-pic pointers and references. */
199 static int prev_half_pic_ptrs = 0;
200 static int prev_half_pic_refs = 0;
202 /* which cpu are we scheduling for */
203 enum processor_type mips_cpu;
205 /* which instruction set architecture to use. */
208 #ifdef MIPS_ABI_DEFAULT
209 /* Which ABI to use. This is defined to a constant in mips.h if the target
210 doesn't support multiple ABIs. */
214 /* Strings to hold which cpu and instruction set architecture to use. */
215 const char *mips_cpu_string; /* for -mcpu=<xxx> */
216 const char *mips_isa_string; /* for -mips{1,2,3,4} */
217 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
219 /* Whether we are generating mips16 code. This is a synonym for
220 TARGET_MIPS16, and exists for use as an attribute. */
223 /* This variable is set by -mno-mips16. We only care whether
224 -mno-mips16 appears or not, and using a string in this fashion is
225 just a way to avoid using up another bit in target_flags. */
226 const char *mips_no_mips16_string;
228 /* This is only used to determine if an type size setting option was
229 explicitly specified (-mlong64, -mint64, -mlong32). The specs
230 set this option if such an option is used. */
231 const char *mips_explicit_type_size_string;
233 /* Whether we are generating mips16 hard float code. In mips16 mode
234 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
235 -msoft-float was not specified by the user, which means that we
236 should arrange to call mips32 hard floating point code. */
237 int mips16_hard_float;
239 /* This variable is set by -mentry. We only care whether -mentry
240 appears or not, and using a string in this fashion is just a way to
241 avoid using up another bit in target_flags. */
242 const char *mips_entry_string;
244 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
247 /* If TRUE, we split addresses into their high and low parts in the RTL. */
248 int mips_split_addresses;
250 /* Generating calls to position independent functions? */
251 enum mips_abicalls_type mips_abicalls;
253 /* High and low marks for floating point values which we will accept
254 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
255 initialized in override_options. */
256 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
258 /* Mode used for saving/restoring general purpose registers. */
259 static enum machine_mode gpr_mode;
261 /* Array giving truth value on whether or not a given hard register
262 can support a given mode. */
263 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
265 /* Current frame information calculated by compute_frame_size. */
266 struct mips_frame_info current_frame_info;
268 /* Zero structure to initialize current_frame_info. */
269 struct mips_frame_info zero_frame_info;
271 /* Temporary filename used to buffer .text until end of program
273 static char *temp_filename;
275 /* Pseudo-reg holding the address of the current function when
276 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
277 by mips_finalize_pic if it was created. */
278 rtx embedded_pic_fnaddr_rtx;
280 /* The length of all strings seen when compiling for the mips16. This
281 is used to tell how many strings are in the constant pool, so that
282 we can see if we may have an overflow. This is reset each time the
283 constant pool is output. */
284 int mips_string_length;
286 /* Pseudo-reg holding the value of $28 in a mips16 function which
287 refers to GP relative global variables. */
288 rtx mips16_gp_pseudo_rtx;
290 /* In mips16 mode, we build a list of all the string constants we see
291 in a particular function. */
293 struct string_constant
295 struct string_constant *next;
299 static struct string_constant *string_constants;
301 /* List of all MIPS punctuation characters used by print_operand. */
302 char mips_print_operand_punct[256];
304 /* Map GCC register number to debugger register number. */
305 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
307 /* Buffer to use to enclose a load/store operation with %{ %} to
308 turn on .set volatile. */
309 static char volatile_buffer[60];
311 /* Hardware names for the registers. If -mrnames is used, this
312 will be overwritten with mips_sw_reg_names. */
314 char mips_reg_names[][8] =
316 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
317 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
318 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
319 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
320 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
321 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
322 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
323 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
324 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
325 "$fcc5","$fcc6","$fcc7","$rap"
328 /* Mips software names for the registers, used to overwrite the
329 mips_reg_names array. */
331 char mips_sw_reg_names[][8] =
333 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
334 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
335 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
336 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
337 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
338 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
339 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
340 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
341 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
342 "$fcc5","$fcc6","$fcc7","$rap"
345 /* Map hard register number to register class */
346 enum reg_class mips_regno_to_class[] =
348 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
349 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
350 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
351 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
352 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
353 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
354 T_REG, GR_REGS, GR_REGS, GR_REGS,
355 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
356 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
357 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
358 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
359 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
360 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
361 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
362 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
363 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
364 HI_REG, LO_REG, HILO_REG, ST_REGS,
365 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
366 ST_REGS, ST_REGS, ST_REGS, GR_REGS
369 /* Map register constraint character to register class. */
370 enum reg_class mips_char_to_class[256] =
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
431 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
432 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
433 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
434 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
435 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
439 /* Return truth value of whether OP can be used as an operands
440 where a register or 16 bit unsigned integer is needed. */
443 uns_arith_operand (op, mode)
445 enum machine_mode mode;
447 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
450 return register_operand (op, mode);
453 /* Return truth value of whether OP can be used as an operands
454 where a 16 bit integer is needed */
457 arith_operand (op, mode)
459 enum machine_mode mode;
461 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
464 /* On the mips16, a GP relative value is a signed 16 bit offset. */
465 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
468 return register_operand (op, mode);
471 /* Return truth value of whether OP can be used as an operand in a two
472 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
475 arith32_operand (op, mode)
477 enum machine_mode mode;
479 if (GET_CODE (op) == CONST_INT)
482 return register_operand (op, mode);
485 /* Return truth value of whether OP is a integer which fits in 16 bits */
490 enum machine_mode mode ATTRIBUTE_UNUSED;
492 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
495 /* Return truth value of whether OP is a 32 bit integer which is too big to
496 be loaded with one instruction. */
501 enum machine_mode mode ATTRIBUTE_UNUSED;
505 if (GET_CODE (op) != CONST_INT)
510 /* ior reg,$r0,value */
511 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
514 /* subu reg,$r0,value */
515 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
518 /* lui reg,value>>16 */
519 if ((value & 0x0000ffff) == 0)
525 /* Return truth value of whether OP is a register or the constant 0.
526 In mips16 mode, we only accept a register, since the mips16 does
530 reg_or_0_operand (op, mode)
532 enum machine_mode mode;
534 switch (GET_CODE (op))
539 return INTVAL (op) == 0;
544 return op == CONST0_RTX (mode);
548 return register_operand (op, mode);
557 /* Return truth value of whether OP is a register or the constant 0,
558 even in mips16 mode. */
561 true_reg_or_0_operand (op, mode)
563 enum machine_mode mode;
565 switch (GET_CODE (op))
568 return INTVAL (op) == 0;
571 return op == CONST0_RTX (mode);
575 return register_operand (op, mode);
584 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
587 mips_const_double_ok (op, mode)
589 enum machine_mode mode;
593 if (GET_CODE (op) != CONST_DOUBLE)
596 if (mode == VOIDmode)
599 if (mode != SFmode && mode != DFmode)
602 if (op == CONST0_RTX (mode))
605 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
606 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
609 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
611 if (REAL_VALUE_ISNAN (d))
614 if (REAL_VALUE_NEGATIVE (d))
615 d = REAL_VALUE_NEGATE (d);
619 if (REAL_VALUES_LESS (d, dfhigh)
620 && REAL_VALUES_LESS (dflow, d))
625 if (REAL_VALUES_LESS (d, sfhigh)
626 && REAL_VALUES_LESS (sflow, d))
633 /* Accept the floating point constant 1 in the appropriate mode. */
636 const_float_1_operand (op, mode)
638 enum machine_mode mode;
641 static REAL_VALUE_TYPE onedf;
642 static REAL_VALUE_TYPE onesf;
643 static int one_initialized;
645 if (GET_CODE (op) != CONST_DOUBLE
646 || mode != GET_MODE (op)
647 || (mode != DFmode && mode != SFmode))
650 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
652 /* We only initialize these values if we need them, since we will
653 never get called unless mips_isa >= 4. */
654 if (! one_initialized)
656 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
657 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
662 return REAL_VALUES_EQUAL (d, onedf);
664 return REAL_VALUES_EQUAL (d, onesf);
667 /* Return true if a memory load or store of REG plus OFFSET in MODE
668 can be represented in a single word on the mips16. */
671 mips16_simple_memory_operand (reg, offset, mode)
674 enum machine_mode mode;
681 /* We can't tell, because we don't know how the value will
682 eventually be accessed. Returning 0 here does no great
683 harm; it just prevents some possible instruction scheduling. */
687 size = GET_MODE_SIZE (mode);
689 if (INTVAL (offset) % size != 0)
691 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
695 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
700 /* Return truth value if a memory operand fits in a single instruction
701 (ie, register + small offset). */
704 simple_memory_operand (op, mode)
706 enum machine_mode mode;
708 rtx addr, plus0, plus1;
710 /* Eliminate non-memory operations */
711 if (GET_CODE (op) != MEM)
714 /* dword operations really put out 2 instructions, so eliminate them. */
715 /* ??? This isn't strictly correct. It is OK to accept multiword modes
716 here, since the length attributes are being set correctly, but only
717 if the address is offsettable. LO_SUM is not offsettable. */
718 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
721 /* Decode the address now. */
723 switch (GET_CODE (addr))
732 return SMALL_INT (addr);
735 plus0 = XEXP (addr, 0);
736 plus1 = XEXP (addr, 1);
737 if (GET_CODE (plus0) == REG
738 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
740 || mips16_simple_memory_operand (plus0, plus1, mode)))
743 else if (GET_CODE (plus1) == REG
744 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
746 || mips16_simple_memory_operand (plus1, plus0, mode)))
753 /* We used to allow small symbol refs here (ie, stuff in .sdata
754 or .sbss), but this causes some bugs in G++. Also, it won't
755 interfere if the MIPS linker rewrites the store instruction
756 because the function is PIC. */
758 case LABEL_REF: /* never gp relative */
762 /* If -G 0, we can never have a GP relative memory operation.
763 Also, save some time if not optimizing. */
768 rtx offset = const0_rtx;
769 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
770 if (GET_CODE (op) != SYMBOL_REF)
773 /* let's be paranoid.... */
774 if (! SMALL_INT (offset))
781 return SYMBOL_REF_FLAG (addr);
784 /* This SYMBOL_REF case is for the mips16. If the above case is
785 reenabled, this one should be merged in. */
787 /* References to the constant pool on the mips16 use a small
788 offset if the function is small. The only time we care about
789 getting this right is during delayed branch scheduling, so
790 don't need to check until then. The machine_dependent_reorg
791 function will set the total length of the instructions used
792 in the function in current_frame_info. If that is small
793 enough, we know for sure that this is a small offset. It
794 would be better if we could take into account the location of
795 the instruction within the function, but we can't, because we
796 don't know where we are. */
798 && CONSTANT_POOL_ADDRESS_P (addr)
799 && current_frame_info.insns_len > 0)
803 size = current_frame_info.insns_len + get_pool_size ();
804 if (GET_MODE_SIZE (mode) == 4)
805 return size < 4 * 0x100;
806 else if (GET_MODE_SIZE (mode) == 8)
807 return size < 8 * 0x20;
821 /* Return nonzero for a memory address that can be used to load or store
825 double_memory_operand (op, mode)
827 enum machine_mode mode;
831 if (GET_CODE (op) != MEM
832 || ! memory_operand (op, mode))
834 /* During reload, we accept a pseudo register if it has an
835 appropriate memory address. If we don't do this, we will
836 wind up reloading into a register, and then reloading that
837 register from memory, when we could just reload directly from
839 if (reload_in_progress
840 && GET_CODE (op) == REG
841 && REGNO (op) >= FIRST_PSEUDO_REGISTER
842 && reg_renumber[REGNO (op)] < 0
843 && reg_equiv_mem[REGNO (op)] != 0
844 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
847 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
848 the same test performed for 'm' in find_reloads. */
850 if (reload_in_progress
852 && (GET_CODE (op) == MEM
853 || (GET_CODE (op) == REG
854 && REGNO (op) >= FIRST_PSEUDO_REGISTER
855 && reg_renumber[REGNO (op)] < 0)))
858 if (reload_in_progress
860 && GET_CODE (op) == MEM)
866 /* During reload on the mips16, we accept a large offset
867 from the frame pointer or the stack pointer. This large
868 address will get reloaded anyhow. */
869 if (GET_CODE (addr) == PLUS
870 && GET_CODE (XEXP (addr, 0)) == REG
871 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
872 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
873 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
874 && ! SMALL_INT (XEXP (addr, 1)))
875 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
876 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
879 /* Similarly, we accept a case where the memory address is
880 itself on the stack, and will be reloaded. */
881 if (GET_CODE (addr) == MEM)
885 maddr = XEXP (addr, 0);
886 if (GET_CODE (maddr) == PLUS
887 && GET_CODE (XEXP (maddr, 0)) == REG
888 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
889 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
890 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
891 && ! SMALL_INT (XEXP (maddr, 1)))
892 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
893 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
897 /* We also accept the same case when we have a 16 bit signed
898 offset mixed in as well. The large address will get
899 reloaded, and the 16 bit offset will be OK. */
900 if (GET_CODE (addr) == PLUS
901 && GET_CODE (XEXP (addr, 0)) == MEM
902 && GET_CODE (XEXP (addr, 1)) == CONST_INT
903 && SMALL_INT (XEXP (addr, 1)))
905 addr = XEXP (XEXP (addr, 0), 0);
906 if (GET_CODE (addr) == PLUS
907 && GET_CODE (XEXP (addr, 0)) == REG
908 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
909 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
910 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
911 && ! SMALL_INT (XEXP (addr, 1)))
912 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
913 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
923 /* In this case we can use an instruction like sd. */
927 /* Make sure that 4 added to the address is a valid memory address.
928 This essentially just checks for overflow in an added constant. */
932 if (CONSTANT_ADDRESS_P (addr))
935 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
938 plus_constant_for_output (addr, 4));
941 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
944 equality_op (op, mode)
946 enum machine_mode mode;
948 if (mode != GET_MODE (op))
951 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
954 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
959 enum machine_mode mode;
961 if (mode != GET_MODE (op))
964 return GET_RTX_CLASS (GET_CODE (op)) == '<';
967 /* Return nonzero if the code is a relational operation suitable for a
968 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
969 We need this in the insn that expands `trap_if' in order to prevent
970 combine from erroneously altering the condition. */
973 trap_cmp_op (op, mode)
975 enum machine_mode mode;
977 if (mode != GET_MODE (op))
980 switch (GET_CODE (op))
995 /* Return nonzero if the operand is either the PC or a label_ref. */
998 pc_or_label_operand (op, mode)
1000 enum machine_mode mode ATTRIBUTE_UNUSED;
1005 if (GET_CODE (op) == LABEL_REF)
1011 /* Test for a valid operand for a call instruction.
1012 Don't allow the arg pointer register or virtual regs
1013 since they may change into reg + const, which the patterns
1014 can't handle yet. */
1017 call_insn_operand (op, mode)
1019 enum machine_mode mode ATTRIBUTE_UNUSED;
1021 return (CONSTANT_ADDRESS_P (op)
1022 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1023 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1024 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1027 /* Return nonzero if OPERAND is valid as a source operand for a move
1031 move_operand (op, mode)
1033 enum machine_mode mode;
1035 /* Accept any general operand after reload has started; doing so
1036 avoids losing if reload does an in-place replacement of a register
1037 with a SYMBOL_REF or CONST. */
1038 return (general_operand (op, mode)
1039 && (! (mips_split_addresses && mips_check_split (op, mode))
1040 || reload_in_progress || reload_completed)
1042 && GET_CODE (op) == SYMBOL_REF
1043 && ! mips16_constant (op, mode, 1, 0)));
1046 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1047 This accepts not only general_operand, but also sign extended
1048 constants and registers. We need to accept sign extended constants
1049 in case a sign extended register which is used in an expression,
1050 and is equivalent to a constant, is spilled. */
1053 movdi_operand (op, mode)
1055 enum machine_mode mode;
1059 && GET_CODE (op) == SIGN_EXTEND
1060 && GET_MODE (op) == DImode
1061 && (GET_MODE (XEXP (op, 0)) == SImode
1062 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1063 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1064 && (register_operand (XEXP (op, 0), SImode)
1065 || immediate_operand (XEXP (op, 0), SImode)))
1068 return (general_operand (op, mode)
1070 && GET_CODE (op) == SYMBOL_REF
1071 && ! mips16_constant (op, mode, 1, 0)));
1074 /* Like register_operand, but when in 64 bit mode also accept a sign
1075 extend of a 32 bit register, since the value is known to be already
1079 se_register_operand (op, mode)
1081 enum machine_mode mode;
1085 && GET_CODE (op) == SIGN_EXTEND
1086 && GET_MODE (op) == DImode
1087 && GET_MODE (XEXP (op, 0)) == SImode
1088 && register_operand (XEXP (op, 0), SImode))
1091 return register_operand (op, mode);
1094 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1095 extend of a 32 bit register, since the value is known to be already
1099 se_reg_or_0_operand (op, mode)
1101 enum machine_mode mode;
1105 && GET_CODE (op) == SIGN_EXTEND
1106 && GET_MODE (op) == DImode
1107 && GET_MODE (XEXP (op, 0)) == SImode
1108 && register_operand (XEXP (op, 0), SImode))
1111 return reg_or_0_operand (op, mode);
1114 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1115 extend of a 32 bit register, since the value is known to be already
1119 se_uns_arith_operand (op, mode)
1121 enum machine_mode mode;
1125 && GET_CODE (op) == SIGN_EXTEND
1126 && GET_MODE (op) == DImode
1127 && GET_MODE (XEXP (op, 0)) == SImode
1128 && register_operand (XEXP (op, 0), SImode))
1131 return uns_arith_operand (op, mode);
1134 /* Like arith_operand, but when in 64 bit mode also accept a sign
1135 extend of a 32 bit register, since the value is known to be already
1139 se_arith_operand (op, mode)
1141 enum machine_mode mode;
1145 && GET_CODE (op) == SIGN_EXTEND
1146 && GET_MODE (op) == DImode
1147 && GET_MODE (XEXP (op, 0)) == SImode
1148 && register_operand (XEXP (op, 0), SImode))
1151 return arith_operand (op, mode);
1154 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1155 extend of a 32 bit register, since the value is known to be already
1159 se_nonmemory_operand (op, mode)
1161 enum machine_mode mode;
1165 && GET_CODE (op) == SIGN_EXTEND
1166 && GET_MODE (op) == DImode
1167 && GET_MODE (XEXP (op, 0)) == SImode
1168 && register_operand (XEXP (op, 0), SImode))
1171 return nonmemory_operand (op, mode);
1174 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1175 sign extend of a 32 bit register, since the value is known to be
1176 already sign extended. */
1179 se_nonimmediate_operand (op, mode)
1181 enum machine_mode mode;
1185 && GET_CODE (op) == SIGN_EXTEND
1186 && GET_MODE (op) == DImode
1187 && GET_MODE (XEXP (op, 0)) == SImode
1188 && register_operand (XEXP (op, 0), SImode))
1191 return nonimmediate_operand (op, mode);
1194 /* Accept any operand that can appear in a mips16 constant table
1195 instruction. We can't use any of the standard operand functions
1196 because for these instructions we accept values that are not
1197 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1200 consttable_operand (op, mode)
1202 enum machine_mode mode ATTRIBUTE_UNUSED;
1204 return CONSTANT_P (op);
1207 /* Return nonzero if we split the address into high and low parts. */
1209 /* ??? We should also handle reg+array somewhere. We get four
1210 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1211 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1212 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1213 out of the address, then we have 4 instructions to combine. Perhaps
1214 add a 3->2 define_split for combine. */
1216 /* ??? We could also split a CONST_INT here if it is a large_int().
1217 However, it doesn't seem to be very useful to have %hi(constant).
1218 We would be better off by doing the masking ourselves and then putting
1219 the explicit high part of the constant in the RTL. This will give better
1220 optimization. Also, %hi(constant) needs assembler changes to work.
1221 There is already a define_split that does this. */
1224 mips_check_split (address, mode)
1226 enum machine_mode mode;
1228 /* ??? This is the same check used in simple_memory_operand.
1229 We use it here because LO_SUM is not offsettable. */
1230 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1233 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1234 || (GET_CODE (address) == CONST
1235 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1236 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1237 || GET_CODE (address) == LABEL_REF)
1243 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1246 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1248 enum machine_mode mode;
1252 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1253 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1256 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1257 returns a nonzero value if XINSN is a legitimate address for a
1258 memory operand of the indicated MODE. STRICT is non-zero if this
1259 function is called during reload. */
1262 mips_legitimate_address_p (mode, xinsn, strict)
1263 enum machine_mode mode;
1267 if (TARGET_DEBUG_B_MODE)
1269 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1270 strict ? "" : "not ");
1271 GO_DEBUG_RTX (xinsn);
1274 /* Check for constant before stripping off SUBREG, so that we don't
1275 accept (subreg (const_int)) which will fail to reload. */
1276 if (CONSTANT_ADDRESS_P (xinsn)
1277 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1278 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1281 while (GET_CODE (xinsn) == SUBREG)
1282 xinsn = SUBREG_REG (xinsn);
1284 /* The mips16 can only use the stack pointer as a base register when
1285 loading SImode or DImode values. */
1286 if (GET_CODE (xinsn) == REG
1287 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1290 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1292 register rtx xlow0 = XEXP (xinsn, 0);
1293 register rtx xlow1 = XEXP (xinsn, 1);
1295 while (GET_CODE (xlow0) == SUBREG)
1296 xlow0 = SUBREG_REG (xlow0);
1297 if (GET_CODE (xlow0) == REG
1298 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1299 && mips_check_split (xlow1, mode))
1303 if (GET_CODE (xinsn) == PLUS)
1305 register rtx xplus0 = XEXP (xinsn, 0);
1306 register rtx xplus1 = XEXP (xinsn, 1);
1307 register enum rtx_code code0;
1308 register enum rtx_code code1;
1310 while (GET_CODE (xplus0) == SUBREG)
1311 xplus0 = SUBREG_REG (xplus0);
1312 code0 = GET_CODE (xplus0);
1314 while (GET_CODE (xplus1) == SUBREG)
1315 xplus1 = SUBREG_REG (xplus1);
1316 code1 = GET_CODE (xplus1);
1318 /* The mips16 can only use the stack pointer as a base register
1319 when loading SImode or DImode values. */
1321 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1323 if (code1 == CONST_INT && SMALL_INT (xplus1))
1326 /* On the mips16, we represent GP relative offsets in RTL.
1327 These are 16 bit signed values, and can serve as register
1330 && mips16_gp_offset_p (xplus1))
1333 /* For some code sequences, you actually get better code by
1334 pretending that the MIPS supports an address mode of a
1335 constant address + a register, even though the real
1336 machine doesn't support it. This is because the
1337 assembler can use $r1 to load just the high 16 bits, add
1338 in the register, and fold the low 16 bits into the memory
1339 reference, whereas the compiler generates a 4 instruction
1340 sequence. On the other hand, CSE is not as effective.
1341 It would be a win to generate the lui directly, but the
1342 MIPS assembler does not have syntax to generate the
1343 appropriate relocation. */
1345 /* Also accept CONST_INT addresses here, so no else. */
1346 /* Reject combining an embedded PIC text segment reference
1347 with a register. That requires an additional
1349 /* ??? Reject combining an address with a register for the MIPS
1350 64 bit ABI, because the SGI assembler can not handle this. */
1351 if (!TARGET_DEBUG_A_MODE
1352 && (mips_abi == ABI_32
1353 || mips_abi == ABI_O64
1354 || mips_abi == ABI_EABI)
1355 && CONSTANT_ADDRESS_P (xplus1)
1356 && ! mips_split_addresses
1357 && (!TARGET_EMBEDDED_PIC
1359 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1360 /* When assembling for machines with 64 bit registers,
1361 the assembler will not sign-extend the constant "foo"
1362 in "la x, foo(x)" */
1363 && (!TARGET_64BIT || (INTVAL (xplus1) > 0))
1369 if (TARGET_DEBUG_B_MODE)
1370 GO_PRINTF ("Not a legitimate address\n");
1372 /* The address was not legitimate. */
1377 /* We need a lot of little routines to check constant values on the
1378 mips16. These are used to figure out how long the instruction will
1379 be. It would be much better to do this using constraints, but
1380 there aren't nearly enough letters available. */
1383 m16_check_op (op, low, high, mask)
1389 return (GET_CODE (op) == CONST_INT
1390 && INTVAL (op) >= low
1391 && INTVAL (op) <= high
1392 && (INTVAL (op) & mask) == 0);
1396 m16_uimm3_b (op, mode)
1398 enum machine_mode mode ATTRIBUTE_UNUSED;
1400 return m16_check_op (op, 0x1, 0x8, 0);
1404 m16_simm4_1 (op, mode)
1406 enum machine_mode mode ATTRIBUTE_UNUSED;
1408 return m16_check_op (op, - 0x8, 0x7, 0);
1412 m16_nsimm4_1 (op, mode)
1414 enum machine_mode mode ATTRIBUTE_UNUSED;
1416 return m16_check_op (op, - 0x7, 0x8, 0);
1420 m16_simm5_1 (op, mode)
1422 enum machine_mode mode ATTRIBUTE_UNUSED;
1424 return m16_check_op (op, - 0x10, 0xf, 0);
1428 m16_nsimm5_1 (op, mode)
1430 enum machine_mode mode ATTRIBUTE_UNUSED;
1432 return m16_check_op (op, - 0xf, 0x10, 0);
1436 m16_uimm5_4 (op, mode)
1438 enum machine_mode mode ATTRIBUTE_UNUSED;
1440 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1444 m16_nuimm5_4 (op, mode)
1446 enum machine_mode mode ATTRIBUTE_UNUSED;
1448 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1452 m16_simm8_1 (op, mode)
1454 enum machine_mode mode ATTRIBUTE_UNUSED;
1456 return m16_check_op (op, - 0x80, 0x7f, 0);
1460 m16_nsimm8_1 (op, mode)
1462 enum machine_mode mode ATTRIBUTE_UNUSED;
1464 return m16_check_op (op, - 0x7f, 0x80, 0);
1468 m16_uimm8_1 (op, mode)
1470 enum machine_mode mode ATTRIBUTE_UNUSED;
1472 return m16_check_op (op, 0x0, 0xff, 0);
1476 m16_nuimm8_1 (op, mode)
1478 enum machine_mode mode ATTRIBUTE_UNUSED;
1480 return m16_check_op (op, - 0xff, 0x0, 0);
1484 m16_uimm8_m1_1 (op, mode)
1486 enum machine_mode mode ATTRIBUTE_UNUSED;
1488 return m16_check_op (op, - 0x1, 0xfe, 0);
1492 m16_uimm8_4 (op, mode)
1494 enum machine_mode mode ATTRIBUTE_UNUSED;
1496 return m16_check_op (op, 0x0, 0xff << 2, 3);
1500 m16_nuimm8_4 (op, mode)
1502 enum machine_mode mode ATTRIBUTE_UNUSED;
1504 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1508 m16_simm8_8 (op, mode)
1510 enum machine_mode mode ATTRIBUTE_UNUSED;
1512 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1516 m16_nsimm8_8 (op, mode)
1518 enum machine_mode mode ATTRIBUTE_UNUSED;
1520 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1523 /* References to the string table on the mips16 only use a small
1524 offset if the function is small. See the comment in the SYMBOL_REF
1525 case in simple_memory_operand. We can't check for LABEL_REF here,
1526 because the offset is always large if the label is before the
1527 referencing instruction. */
1530 m16_usym8_4 (op, mode)
1532 enum machine_mode mode ATTRIBUTE_UNUSED;
1534 if (GET_CODE (op) == SYMBOL_REF
1535 && SYMBOL_REF_FLAG (op)
1536 && current_frame_info.insns_len > 0
1537 && XSTR (op, 0)[0] == '*'
1538 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1539 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1540 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1543 struct string_constant *l;
1545 /* Make sure this symbol is on thelist of string constants to be
1546 output for this function. It is possible that it has already
1547 been output, in which case this requires a large offset. */
1548 for (l = string_constants; l != NULL; l = l->next)
1549 if (strcmp (l->label, XSTR (op, 0)) == 0)
1557 m16_usym5_4 (op, mode)
1559 enum machine_mode mode ATTRIBUTE_UNUSED;
1561 if (GET_CODE (op) == SYMBOL_REF
1562 && SYMBOL_REF_FLAG (op)
1563 && current_frame_info.insns_len > 0
1564 && XSTR (op, 0)[0] == '*'
1565 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1566 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1567 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1570 struct string_constant *l;
1572 /* Make sure this symbol is on thelist of string constants to be
1573 output for this function. It is possible that it has already
1574 been output, in which case this requires a large offset. */
1575 for (l = string_constants; l != NULL; l = l->next)
1576 if (strcmp (l->label, XSTR (op, 0)) == 0)
1583 /* Returns an operand string for the given instruction's delay slot,
1584 after updating filled delay slot statistics.
1586 We assume that operands[0] is the target register that is set.
1588 In order to check the next insn, most of this functionality is moved
1589 to FINAL_PRESCAN_INSN, and we just set the global variables that
1592 /* ??? This function no longer does anything useful, because final_prescan_insn
1593 now will never emit a nop. */
1596 mips_fill_delay_slot (ret, type, operands, cur_insn)
1597 const char *ret; /* normal string to return */
1598 enum delay_type type; /* type of delay */
1599 rtx operands[]; /* operands to use */
1600 rtx cur_insn; /* current insn */
1602 register rtx set_reg;
1603 register enum machine_mode mode;
1604 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1605 register int num_nops;
1607 if (type == DELAY_LOAD || type == DELAY_FCMP)
1610 else if (type == DELAY_HILO)
1616 /* Make sure that we don't put nop's after labels. */
1617 next_insn = NEXT_INSN (cur_insn);
1618 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1619 next_insn = NEXT_INSN (next_insn);
1621 dslots_load_total += num_nops;
1622 if (TARGET_DEBUG_F_MODE
1624 || type == DELAY_NONE
1628 || GET_CODE (next_insn) == CODE_LABEL
1629 || (set_reg = operands[0]) == 0)
1631 dslots_number_nops = 0;
1639 set_reg = operands[0];
1643 while (GET_CODE (set_reg) == SUBREG)
1644 set_reg = SUBREG_REG (set_reg);
1646 mode = GET_MODE (set_reg);
1647 dslots_number_nops = num_nops;
1648 mips_load_reg = set_reg;
1649 if (GET_MODE_SIZE (mode)
1650 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1651 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1655 if (type == DELAY_HILO)
1657 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1658 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1670 /* Determine whether a memory reference takes one (based off of the GP
1671 pointer), two (normal), or three (label + reg) instructions, and bump the
1672 appropriate counter for -mstats. */
1675 mips_count_memory_refs (op, num)
1681 rtx addr, plus0, plus1;
1682 enum rtx_code code0, code1;
1685 if (TARGET_DEBUG_B_MODE)
1687 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1691 /* Skip MEM if passed, otherwise handle movsi of address. */
1692 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1694 /* Loop, going through the address RTL. */
1698 switch (GET_CODE (addr))
1706 plus0 = XEXP (addr, 0);
1707 plus1 = XEXP (addr, 1);
1708 code0 = GET_CODE (plus0);
1709 code1 = GET_CODE (plus1);
1719 if (code0 == CONST_INT)
1734 if (code1 == CONST_INT)
1741 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1748 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1758 n_words = 2; /* always 2 words */
1762 addr = XEXP (addr, 0);
1767 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1779 n_words += additional;
1783 num_refs[n_words-1] += num;
1787 /* Return RTL for the offset from the current function to the argument.
1789 ??? Which argument is this? */
1792 embedded_pic_offset (x)
1795 if (embedded_pic_fnaddr_rtx == NULL)
1799 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1801 /* Output code at function start to initialize the pseudo-reg. */
1802 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1803 inline functions, because it is called after RTL for the function
1804 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1805 does not get copied, and ends up not matching the rest of the RTL.
1806 This solution works, but means that we get unnecessary code to
1807 initialize this value every time a function is inlined into another
1810 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1811 XEXP (DECL_RTL (current_function_decl), 0)));
1812 seq = gen_sequence ();
1814 push_topmost_sequence ();
1815 emit_insn_after (seq, get_insns ());
1816 pop_topmost_sequence ();
1820 gen_rtx_CONST (Pmode,
1821 gen_rtx_MINUS (Pmode, x,
1822 XEXP (DECL_RTL (current_function_decl), 0)));
1825 /* Return the appropriate instructions to move one operand to another. */
1828 mips_move_1word (operands, insn, unsignedp)
1833 const char *ret = 0;
1834 rtx op0 = operands[0];
1835 rtx op1 = operands[1];
1836 enum rtx_code code0 = GET_CODE (op0);
1837 enum rtx_code code1 = GET_CODE (op1);
1838 enum machine_mode mode = GET_MODE (op0);
1839 int subreg_word0 = 0;
1840 int subreg_word1 = 0;
1841 enum delay_type delay = DELAY_NONE;
1843 while (code0 == SUBREG)
1845 subreg_word0 += SUBREG_WORD (op0);
1846 op0 = SUBREG_REG (op0);
1847 code0 = GET_CODE (op0);
1850 while (code1 == SUBREG)
1852 subreg_word1 += SUBREG_WORD (op1);
1853 op1 = SUBREG_REG (op1);
1854 code1 = GET_CODE (op1);
1857 /* For our purposes, a condition code mode is the same as SImode. */
1863 int regno0 = REGNO (op0) + subreg_word0;
1867 int regno1 = REGNO (op1) + subreg_word1;
1869 /* Just in case, don't do anything for assigning a register
1870 to itself, unless we are filling a delay slot. */
1871 if (regno0 == regno1 && set_nomacro == 0)
1874 else if (GP_REG_P (regno0))
1876 if (GP_REG_P (regno1))
1877 ret = "move\t%0,%1";
1879 else if (MD_REG_P (regno1))
1882 if (regno1 != HILO_REGNUM)
1888 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
1889 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1894 if (FP_REG_P (regno1))
1895 ret = "mfc1\t%0,%1";
1897 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
1898 ret = "cfc1\t%0,$31";
1902 else if (FP_REG_P (regno0))
1904 if (GP_REG_P (regno1))
1907 ret = "mtc1\t%1,%0";
1910 if (FP_REG_P (regno1))
1911 ret = "mov.s\t%0,%1";
1914 else if (MD_REG_P (regno0))
1916 if (GP_REG_P (regno1))
1919 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1924 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
1926 if (GP_REG_P (regno1))
1929 ret = "ctc1\t%0,$31";
1934 else if (code1 == MEM)
1939 mips_count_memory_refs (op1, 1);
1941 if (GP_REG_P (regno0))
1943 /* For loads, use the mode of the memory item, instead of the
1944 target, so zero/sign extend can use this code as well. */
1945 switch (GET_MODE (op1))
1954 ret = ((unsignedp && TARGET_64BIT)
1959 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1962 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1967 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1970 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1972 size_t i = strlen (ret);
1973 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1976 sprintf (volatile_buffer, "%%{%s%%}", ret);
1977 ret = volatile_buffer;
1981 else if (code1 == CONST_INT
1982 || (code1 == CONST_DOUBLE
1983 && GET_MODE (op1) == VOIDmode))
1985 if (code1 == CONST_DOUBLE)
1987 /* This can happen when storing constants into long long
1988 bitfields. Just store the least significant word of
1990 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1993 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
1995 if (GP_REG_P (regno0))
1996 ret = "move\t%0,%z1";
1998 else if (FP_REG_P (regno0))
2001 ret = "mtc1\t%z1,%0";
2004 else if (MD_REG_P (regno0))
2011 else if (GP_REG_P (regno0))
2013 /* Don't use X format, because that will give out of
2014 range numbers for 64 bit host and 32 bit target. */
2015 if (! TARGET_MIPS16)
2016 ret = "li\t%0,%1\t\t\t# %X1";
2019 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2021 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2022 ret = "li\t%0,%n1\n\tneg\t%0";
2027 else if (code1 == CONST_DOUBLE && mode == SFmode)
2029 if (op1 == CONST0_RTX (SFmode))
2031 if (GP_REG_P (regno0))
2032 ret = "move\t%0,%.";
2034 else if (FP_REG_P (regno0))
2037 ret = "mtc1\t%.,%0";
2044 ret = "li.s\t%0,%1";
2048 else if (code1 == LABEL_REF)
2051 mips_count_memory_refs (op1, 1);
2056 else if (code1 == SYMBOL_REF || code1 == CONST)
2058 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
2060 rtx offset = const0_rtx;
2062 if (GET_CODE (op1) == CONST)
2063 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2065 if (GET_CODE (op1) == SYMBOL_REF)
2067 operands[2] = HALF_PIC_PTR (op1);
2070 mips_count_memory_refs (operands[2], 1);
2072 if (INTVAL (offset) == 0)
2075 ret = (unsignedp && TARGET_64BIT
2081 dslots_load_total++;
2082 operands[3] = offset;
2083 if (unsignedp && TARGET_64BIT)
2084 ret = (SMALL_INT (offset)
2085 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2086 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2088 ret = (SMALL_INT (offset)
2089 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2090 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2094 else if (TARGET_MIPS16
2096 && GET_CODE (XEXP (op1, 0)) == REG
2097 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2099 /* This case arises on the mips16; see
2100 mips16_gp_pseudo_reg. */
2101 ret = "move\t%0,%+";
2103 else if (TARGET_MIPS16
2104 && code1 == SYMBOL_REF
2105 && SYMBOL_REF_FLAG (op1)
2106 && (XSTR (op1, 0)[0] != '*'
2107 || strncmp (XSTR (op1, 0) + 1,
2109 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2111 /* This can occur when reloading the address of a GP
2112 relative symbol on the mips16. */
2113 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2118 mips_count_memory_refs (op1, 1);
2124 else if (code1 == PLUS)
2126 rtx add_op0 = XEXP (op1, 0);
2127 rtx add_op1 = XEXP (op1, 1);
2129 if (GET_CODE (XEXP (op1, 1)) == REG
2130 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2131 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2133 operands[2] = add_op0;
2134 operands[3] = add_op1;
2135 ret = "add%:\t%0,%2,%3";
2138 else if (code1 == HIGH)
2140 operands[1] = XEXP (op1, 0);
2141 ret = "lui\t%0,%%hi(%1)";
2145 else if (code0 == MEM)
2148 mips_count_memory_refs (op0, 1);
2152 int regno1 = REGNO (op1) + subreg_word1;
2154 if (GP_REG_P (regno1))
2158 case SFmode: ret = "sw\t%1,%0"; break;
2159 case SImode: ret = "sw\t%1,%0"; break;
2160 case HImode: ret = "sh\t%1,%0"; break;
2161 case QImode: ret = "sb\t%1,%0"; break;
2166 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2170 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2174 case SFmode: ret = "sw\t%z1,%0"; break;
2175 case SImode: ret = "sw\t%z1,%0"; break;
2176 case HImode: ret = "sh\t%z1,%0"; break;
2177 case QImode: ret = "sb\t%z1,%0"; break;
2182 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2186 case SFmode: ret = "sw\t%.,%0"; break;
2187 case SImode: ret = "sw\t%.,%0"; break;
2188 case HImode: ret = "sh\t%.,%0"; break;
2189 case QImode: ret = "sb\t%.,%0"; break;
2194 if (ret != 0 && MEM_VOLATILE_P (op0))
2196 size_t i = strlen (ret);
2198 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2201 sprintf (volatile_buffer, "%%{%s%%}", ret);
2202 ret = volatile_buffer;
2208 abort_with_insn (insn, "Bad move");
2212 if (delay != DELAY_NONE)
2213 return mips_fill_delay_slot (ret, delay, operands, insn);
2219 /* Return the appropriate instructions to move 2 words */
2222 mips_move_2words (operands, insn)
2226 const char *ret = 0;
2227 rtx op0 = operands[0];
2228 rtx op1 = operands[1];
2229 enum rtx_code code0 = GET_CODE (operands[0]);
2230 enum rtx_code code1 = GET_CODE (operands[1]);
2231 int subreg_word0 = 0;
2232 int subreg_word1 = 0;
2233 enum delay_type delay = DELAY_NONE;
2235 while (code0 == SUBREG)
2237 subreg_word0 += SUBREG_WORD (op0);
2238 op0 = SUBREG_REG (op0);
2239 code0 = GET_CODE (op0);
2242 if (code1 == SIGN_EXTEND)
2244 op1 = XEXP (op1, 0);
2245 code1 = GET_CODE (op1);
2248 while (code1 == SUBREG)
2250 subreg_word1 += SUBREG_WORD (op1);
2251 op1 = SUBREG_REG (op1);
2252 code1 = GET_CODE (op1);
2256 if (GET_CODE (operands[1]) == SIGN_EXTEND
2258 && code1 != CONST_INT
2259 /* The following three can happen as the result of a questionable
2261 && code1 != LABEL_REF
2262 && code1 != SYMBOL_REF
2268 int regno0 = REGNO (op0) + subreg_word0;
2272 int regno1 = REGNO (op1) + subreg_word1;
2274 /* Just in case, don't do anything for assigning a register
2275 to itself, unless we are filling a delay slot. */
2276 if (regno0 == regno1 && set_nomacro == 0)
2279 else if (FP_REG_P (regno0))
2281 if (FP_REG_P (regno1))
2282 ret = "mov.d\t%0,%1";
2290 abort_with_insn (insn, "Bad move");
2292 #ifdef TARGET_FP_CALL_32
2293 if (FP_CALL_GP_REG_P (regno1))
2294 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2297 ret = "dmtc1\t%1,%0";
2300 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2304 else if (FP_REG_P (regno1))
2310 abort_with_insn (insn, "Bad move");
2312 #ifdef TARGET_FP_CALL_32
2313 if (FP_CALL_GP_REG_P (regno0))
2314 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2317 ret = "dmfc1\t%0,%1";
2320 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2323 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2328 if (regno0 != HILO_REGNUM)
2330 else if (regno1 == 0)
2331 ret = "mtlo\t%.\n\tmthi\t%.";
2334 ret = "mthi\t%M1\n\tmtlo\t%L1";
2337 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2342 if (regno1 != HILO_REGNUM)
2346 ret = "mfhi\t%M0\n\tmflo\t%L0";
2349 else if (TARGET_64BIT)
2350 ret = "move\t%0,%1";
2352 else if (regno0 != (regno1+1))
2353 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2356 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2359 else if (code1 == CONST_DOUBLE)
2361 /* Move zero from $0 unless !TARGET_64BIT and recipient
2362 is 64-bit fp reg, in which case generate a constant. */
2363 if (op1 != CONST0_RTX (GET_MODE (op1))
2364 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2366 if (GET_MODE (op1) == DFmode)
2370 #ifdef TARGET_FP_CALL_32
2371 if (FP_CALL_GP_REG_P (regno0))
2373 if (TARGET_FLOAT64 && !TARGET_64BIT)
2375 split_double (op1, operands + 2, operands + 3);
2376 ret = "li\t%0,%2\n\tli\t%D0,%3";
2379 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2383 /* GNU as emits 64-bit code for li.d if the ISA is 3
2384 or higher. For !TARGET_64BIT && gp registers we
2385 need to avoid this by using two li instructions
2387 if (ISA_HAS_64BIT_REGS
2389 && ! FP_REG_P (regno0))
2391 split_double (op1, operands + 2, operands + 3);
2392 ret = "li\t%0,%2\n\tli\t%D0,%3";
2395 ret = "li.d\t%0,%1";
2398 else if (TARGET_64BIT)
2400 if (! TARGET_MIPS16)
2406 split_double (op1, operands + 2, operands + 3);
2407 ret = "li\t%0,%2\n\tli\t%D0,%3";
2413 if (GP_REG_P (regno0))
2415 #ifdef TARGET_FP_CALL_32
2416 && ! FP_CALL_GP_REG_P (regno0)
2419 : "move\t%0,%.\n\tmove\t%D0,%.");
2421 else if (FP_REG_P (regno0))
2426 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2431 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2433 if (GP_REG_P (regno0))
2436 : "move\t%0,%.\n\tmove\t%D0,%.");
2438 else if (FP_REG_P (regno0))
2445 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2447 else if (MD_REG_P (regno0))
2450 ret = (regno0 == HILO_REGNUM
2451 ? "mtlo\t%.\n\tmthi\t%."
2456 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2457 && GP_REG_P (regno0))
2463 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2465 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2466 ret = "li\t%0,%n1\n\tneg\t%0";
2468 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2469 ret = "li\t%0,%1\t\t# %X1";
2470 else if (HOST_BITS_PER_WIDE_INT < 64)
2471 /* We can't use 'X' for negative numbers, because then we won't
2472 get the right value for the upper 32 bits. */
2473 ret = (INTVAL (op1) < 0
2474 ? "dli\t%0,%1\t\t\t# %X1"
2475 : "dli\t%0,%X1\t\t# %1");
2477 /* We must use 'X', because otherwise LONG_MIN will print as
2478 a number that the assembler won't accept. */
2479 ret = "dli\t%0,%X1\t\t# %1";
2481 else if (HOST_BITS_PER_WIDE_INT < 64)
2483 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2486 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2487 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2488 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2490 operands[2] = GEN_INT (1);
2491 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2495 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2499 /* We use multiple shifts here, to avoid warnings about out
2500 of range shifts on 32 bit hosts. */
2501 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2503 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2504 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2508 else if (code1 == MEM)
2513 mips_count_memory_refs (op1, 2);
2515 if (FP_REG_P (regno0))
2518 else if (TARGET_64BIT)
2521 #ifdef TARGET_FP_CALL_32
2522 if (FP_CALL_GP_REG_P (regno0))
2523 ret = (double_memory_operand (op1, GET_MODE (op1))
2524 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2525 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2531 else if (double_memory_operand (op1, GET_MODE (op1)))
2533 operands[2] = adj_offsettable_operand (op1, 4);
2534 ret = (reg_mentioned_p (op0, op1)
2535 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2536 : "lw\t%0,%1\n\tlw\t%D0,%2");
2539 if (ret != 0 && MEM_VOLATILE_P (op1))
2541 size_t i = strlen (ret);
2543 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2546 sprintf (volatile_buffer, "%%{%s%%}", ret);
2547 ret = volatile_buffer;
2551 else if (code1 == LABEL_REF)
2554 mips_count_memory_refs (op1, 2);
2556 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2557 /* We deliberately remove the 'a' from '%1', so that we don't
2558 have to add SIGN_EXTEND support to print_operand_address.
2559 print_operand will just call print_operand_address in this
2560 case, so there is no problem. */
2563 ret = "dla\t%0,%a1";
2565 else if (code1 == SYMBOL_REF || code1 == CONST)
2569 && GET_CODE (XEXP (op1, 0)) == REG
2570 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2572 /* This case arises on the mips16; see
2573 mips16_gp_pseudo_reg. */
2574 ret = "move\t%0,%+";
2576 else if (TARGET_MIPS16
2577 && code1 == SYMBOL_REF
2578 && SYMBOL_REF_FLAG (op1)
2579 && (XSTR (op1, 0)[0] != '*'
2580 || strncmp (XSTR (op1, 0) + 1,
2582 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2584 /* This can occur when reloading the address of a GP
2585 relative symbol on the mips16. */
2586 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2591 mips_count_memory_refs (op1, 2);
2593 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2594 /* We deliberately remove the 'a' from '%1', so that we don't
2595 have to add SIGN_EXTEND support to print_operand_address.
2596 print_operand will just call print_operand_address in this
2597 case, so there is no problem. */
2600 ret = "dla\t%0,%a1";
2605 else if (code0 == MEM)
2609 int regno1 = REGNO (op1) + subreg_word1;
2611 if (FP_REG_P (regno1))
2614 else if (TARGET_64BIT)
2617 #ifdef TARGET_FP_CALL_32
2618 if (FP_CALL_GP_REG_P (regno1))
2619 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2625 else if (double_memory_operand (op0, GET_MODE (op0)))
2627 operands[2] = adj_offsettable_operand (op0, 4);
2628 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2632 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2633 || (code1 == CONST_DOUBLE
2634 && op1 == CONST0_RTX (GET_MODE (op1))))
2636 || double_memory_operand (op0, GET_MODE (op0))))
2642 operands[2] = adj_offsettable_operand (op0, 4);
2643 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2648 mips_count_memory_refs (op0, 2);
2650 if (ret != 0 && MEM_VOLATILE_P (op0))
2652 size_t i = strlen (ret);
2654 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2657 sprintf (volatile_buffer, "%%{%s%%}", ret);
2658 ret = volatile_buffer;
2664 abort_with_insn (insn, "Bad move");
2668 if (delay != DELAY_NONE)
2669 return mips_fill_delay_slot (ret, delay, operands, insn);
2674 /* Provide the costs of an addressing mode that contains ADDR.
2675 If ADDR is not a valid address, its cost is irrelevant. */
2678 mips_address_cost (addr)
2681 switch (GET_CODE (addr))
2691 rtx offset = const0_rtx;
2692 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2693 if (GET_CODE (addr) == LABEL_REF)
2696 if (GET_CODE (addr) != SYMBOL_REF)
2699 if (! SMALL_INT (offset))
2703 /* ... fall through ... */
2706 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2710 register rtx plus0 = XEXP (addr, 0);
2711 register rtx plus1 = XEXP (addr, 1);
2713 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2714 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2716 if (GET_CODE (plus0) != REG)
2719 switch (GET_CODE (plus1))
2722 return SMALL_INT (plus1) ? 1 : 2;
2729 return mips_address_cost (plus1) + 1;
2743 /* Return nonzero if X is an address which needs a temporary register when
2744 reloaded while generating PIC code. */
2747 pic_address_needs_scratch (x)
2750 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2751 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2752 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2753 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2754 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2760 /* Make normal rtx_code into something we can index from an array */
2762 static enum internal_test
2763 map_test_to_internal_test (test_code)
2764 enum rtx_code test_code;
2766 enum internal_test test = ITEST_MAX;
2770 case EQ: test = ITEST_EQ; break;
2771 case NE: test = ITEST_NE; break;
2772 case GT: test = ITEST_GT; break;
2773 case GE: test = ITEST_GE; break;
2774 case LT: test = ITEST_LT; break;
2775 case LE: test = ITEST_LE; break;
2776 case GTU: test = ITEST_GTU; break;
2777 case GEU: test = ITEST_GEU; break;
2778 case LTU: test = ITEST_LTU; break;
2779 case LEU: test = ITEST_LEU; break;
2787 /* Generate the code to compare two integer values. The return value is:
2788 (reg:SI xx) The pseudo register the comparison is in
2789 0 No register, generate a simple branch.
2791 ??? This is called with result nonzero by the Scond patterns in
2792 mips.md. These patterns are called with a target in the mode of
2793 the Scond instruction pattern. Since this must be a constant, we
2794 must use SImode. This means that if RESULT is non-zero, it will
2795 always be an SImode register, even if TARGET_64BIT is true. We
2796 cope with this by calling convert_move rather than emit_move_insn.
2797 This will sometimes lead to an unnecessary extension of the result;
2809 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2810 enum rtx_code test_code; /* relational test (EQ, etc) */
2811 rtx result; /* result to store comp. or 0 if branch */
2812 rtx cmp0; /* first operand to compare */
2813 rtx cmp1; /* second operand to compare */
2814 int *p_invert; /* NULL or ptr to hold whether branch needs */
2815 /* to reverse its test */
2819 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2820 int const_low; /* low bound of constant we can accept */
2821 int const_high; /* high bound of constant we can accept */
2822 int const_add; /* constant to add (convert LE -> LT) */
2823 int reverse_regs; /* reverse registers in test */
2824 int invert_const; /* != 0 if invert value if cmp1 is constant */
2825 int invert_reg; /* != 0 if invert value if cmp1 is register */
2826 int unsignedp; /* != 0 for unsigned comparisons. */
2829 static struct cmp_info info[ (int)ITEST_MAX ] = {
2831 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2832 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2833 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2834 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2835 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2836 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2837 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2838 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2839 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2840 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2843 enum internal_test test;
2844 enum machine_mode mode;
2845 struct cmp_info *p_info;
2852 test = map_test_to_internal_test (test_code);
2853 if (test == ITEST_MAX)
2856 p_info = &info[(int) test];
2857 eqne_p = (p_info->test_code == XOR);
2859 mode = GET_MODE (cmp0);
2860 if (mode == VOIDmode)
2861 mode = GET_MODE (cmp1);
2863 /* Eliminate simple branches */
2864 branch_p = (result == 0);
2867 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2869 /* Comparisons against zero are simple branches */
2870 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2871 && (! TARGET_MIPS16 || eqne_p))
2874 /* Test for beq/bne. */
2875 if (eqne_p && ! TARGET_MIPS16)
2879 /* allocate a pseudo to calculate the value in. */
2880 result = gen_reg_rtx (mode);
2883 /* Make sure we can handle any constants given to us. */
2884 if (GET_CODE (cmp0) == CONST_INT)
2885 cmp0 = force_reg (mode, cmp0);
2887 if (GET_CODE (cmp1) == CONST_INT)
2889 HOST_WIDE_INT value = INTVAL (cmp1);
2891 if (value < p_info->const_low
2892 || value > p_info->const_high
2893 /* ??? Why? And why wasn't the similar code below modified too? */
2895 && HOST_BITS_PER_WIDE_INT < 64
2896 && p_info->const_add != 0
2897 && ((p_info->unsignedp
2898 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2899 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2900 : (value + p_info->const_add) > INTVAL (cmp1))
2901 != (p_info->const_add > 0))))
2902 cmp1 = force_reg (mode, cmp1);
2905 /* See if we need to invert the result. */
2906 invert = (GET_CODE (cmp1) == CONST_INT
2907 ? p_info->invert_const : p_info->invert_reg);
2909 if (p_invert != (int *)0)
2915 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2916 Comparison between two registers, may involve switching operands. */
2917 if (GET_CODE (cmp1) == CONST_INT)
2919 if (p_info->const_add != 0)
2921 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2923 /* If modification of cmp1 caused overflow,
2924 we would get the wrong answer if we follow the usual path;
2925 thus, x > 0xffffffffU would turn into x > 0U. */
2926 if ((p_info->unsignedp
2927 ? (unsigned HOST_WIDE_INT) new >
2928 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2929 : new > INTVAL (cmp1))
2930 != (p_info->const_add > 0))
2932 /* This test is always true, but if INVERT is true then
2933 the result of the test needs to be inverted so 0 should
2934 be returned instead. */
2935 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2939 cmp1 = GEN_INT (new);
2943 else if (p_info->reverse_regs)
2950 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2954 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2955 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2958 if (test == ITEST_NE)
2960 if (! TARGET_MIPS16)
2962 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2967 reg2 = invert ? gen_reg_rtx (mode) : result;
2968 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2973 else if (test == ITEST_EQ)
2975 reg2 = invert ? gen_reg_rtx (mode) : result;
2976 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2984 if (! TARGET_MIPS16)
2988 /* The value is in $24. Copy it to another register, so
2989 that reload doesn't think it needs to store the $24 and
2990 the input to the XOR in the same location. */
2991 reg2 = gen_reg_rtx (mode);
2992 emit_move_insn (reg2, reg);
2994 one = force_reg (mode, const1_rtx);
2996 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3002 /* Emit the common code for doing conditional branches.
3003 operand[0] is the label to jump to.
3004 The comparison operands are saved away by cmp{si,di,sf,df}. */
3007 gen_conditional_branch (operands, test_code)
3009 enum rtx_code test_code;
3011 enum cmp_type type = branch_type;
3012 rtx cmp0 = branch_cmp[0];
3013 rtx cmp1 = branch_cmp[1];
3014 enum machine_mode mode;
3023 mode = type == CMP_SI ? SImode : DImode;
3025 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3033 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3034 /* We don't want to build a comparison against a non-zero
3036 cmp1 = force_reg (mode, cmp1);
3043 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3045 reg = gen_reg_rtx (CCmode);
3047 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3048 0 in the instruction built below. The MIPS FPU handles
3049 inequality testing by testing for equality and looking for a
3051 emit_insn (gen_rtx_SET (VOIDmode, reg,
3052 gen_rtx (test_code == NE ? EQ : test_code,
3053 CCmode, cmp0, cmp1)));
3055 test_code = test_code == NE ? EQ : NE;
3063 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3066 /* Generate the branch. */
3068 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3077 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3078 gen_rtx_IF_THEN_ELSE (VOIDmode,
3079 gen_rtx (test_code, mode,
3084 /* Emit the common code for conditional moves. OPERANDS is the array
3085 of operands passed to the conditional move defined_expand. */
3088 gen_conditional_move (operands)
3091 rtx op0 = branch_cmp[0];
3092 rtx op1 = branch_cmp[1];
3093 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3094 enum rtx_code cmp_code = GET_CODE (operands[1]);
3095 enum rtx_code move_code = NE;
3096 enum machine_mode op_mode = GET_MODE (operands[0]);
3097 enum machine_mode cmp_mode;
3100 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3119 op0 = force_reg (mode, branch_cmp[1]);
3120 op1 = branch_cmp[0];
3124 op0 = force_reg (mode, branch_cmp[1]);
3125 op1 = branch_cmp[0];
3136 op0 = force_reg (mode, branch_cmp[1]);
3137 op1 = branch_cmp[0];
3141 op0 = force_reg (mode, branch_cmp[1]);
3142 op1 = branch_cmp[0];
3149 else if (cmp_code == NE)
3150 cmp_code = EQ, move_code = EQ;
3152 if (mode == SImode || mode == DImode)
3154 else if (mode == SFmode || mode == DFmode)
3159 cmp_reg = gen_reg_rtx (cmp_mode);
3160 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3161 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3163 emit_insn (gen_rtx_SET (op_mode, operands[0],
3164 gen_rtx_IF_THEN_ELSE (op_mode,
3165 gen_rtx (move_code, VOIDmode,
3167 CONST0_RTX (SImode)),
3168 operands[2], operands[3])));
3171 /* Emit the common code for conditional moves. OPERANDS is the array
3172 of operands passed to the conditional move defined_expand. */
3175 mips_gen_conditional_trap (operands)
3179 enum rtx_code cmp_code = GET_CODE (operands[0]);
3180 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3182 /* MIPS conditional trap machine instructions don't have GT or LE
3183 flavors, so we must invert the comparison and convert to LT and
3184 GE, respectively. */
3187 case GT: cmp_code = LT; break;
3188 case LE: cmp_code = GE; break;
3189 case GTU: cmp_code = LTU; break;
3190 case LEU: cmp_code = GEU; break;
3193 if (cmp_code == GET_CODE (operands[0]))
3195 op0 = force_reg (mode, branch_cmp[0]);
3196 op1 = branch_cmp[1];
3200 op0 = force_reg (mode, branch_cmp[1]);
3201 op1 = branch_cmp[0];
3203 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3204 op1 = force_reg (mode, op1);
3206 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3207 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3211 /* Write a loop to move a constant number of bytes.
3212 Generate load/stores as follows:
3218 temp<last> = src[MAX_MOVE_REGS-1];
3222 dest[MAX_MOVE_REGS-1] = temp<last>;
3223 src += MAX_MOVE_REGS;
3224 dest += MAX_MOVE_REGS;
3225 } while (src != final);
3227 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3228 registers are needed.
3230 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3231 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3232 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3234 #define MAX_MOVE_REGS 4
3235 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3238 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3239 rtx dest_reg; /* register holding destination address */
3240 rtx src_reg; /* register holding source address */
3241 unsigned int bytes; /* # bytes to move */
3242 int align; /* alignment */
3243 rtx orig_dest; /* original dest for change_address */
3244 rtx orig_src; /* original source for making a reg note */
3246 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
3247 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
3248 rtx align_rtx = GEN_INT (align);
3254 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3257 leftover = bytes % MAX_MOVE_BYTES;
3260 label = gen_label_rtx ();
3261 final_src = gen_reg_rtx (Pmode);
3262 bytes_rtx = GEN_INT (bytes);
3266 if (Pmode == DImode)
3268 emit_insn (gen_movdi (final_src, bytes_rtx));
3269 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3273 emit_insn (gen_movsi (final_src, bytes_rtx));
3274 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3279 if (Pmode == DImode)
3280 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3282 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3287 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3288 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3290 if (Pmode == DImode)
3292 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3293 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3294 emit_insn (gen_cmpdi (src_reg, final_src));
3298 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3299 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3300 emit_insn (gen_cmpsi (src_reg, final_src));
3303 emit_jump_insn (gen_bne (label));
3306 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3310 /* Use a library function to move some bytes. */
3313 block_move_call (dest_reg, src_reg, bytes_rtx)
3318 /* We want to pass the size as Pmode, which will normally be SImode
3319 but will be DImode if we are using 64 bit longs and pointers. */
3320 if (GET_MODE (bytes_rtx) != VOIDmode
3321 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3322 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3324 #ifdef TARGET_MEM_FUNCTIONS
3325 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3326 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3327 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3328 TREE_UNSIGNED (sizetype)),
3329 TYPE_MODE (sizetype));
3331 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3332 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3333 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3334 TREE_UNSIGNED (integer_type_node)),
3335 TYPE_MODE (integer_type_node));
3339 /* Expand string/block move operations.
3341 operands[0] is the pointer to the destination.
3342 operands[1] is the pointer to the source.
3343 operands[2] is the number of bytes to move.
3344 operands[3] is the alignment. */
3347 expand_block_move (operands)
3350 rtx bytes_rtx = operands[2];
3351 rtx align_rtx = operands[3];
3352 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3353 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3354 unsigned int align = INTVAL (align_rtx);
3355 rtx orig_src = operands[1];
3356 rtx orig_dest = operands[0];
3360 if (constp && bytes == 0)
3363 if (align > (unsigned) UNITS_PER_WORD)
3364 align = UNITS_PER_WORD;
3366 /* Move the address into scratch registers. */
3367 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3368 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3371 block_move_call (dest_reg, src_reg, bytes_rtx);
3373 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3374 && align == (unsigned) UNITS_PER_WORD)
3375 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3377 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3378 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3380 change_address (orig_src, BLKmode,
3382 bytes_rtx, align_rtx));
3384 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3385 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3387 else if (constp && optimize)
3389 /* If the alignment is not word aligned, generate a test at
3390 runtime, to see whether things wound up aligned, and we
3391 can use the faster lw/sw instead ulw/usw. */
3393 rtx temp = gen_reg_rtx (Pmode);
3394 rtx aligned_label = gen_label_rtx ();
3395 rtx join_label = gen_label_rtx ();
3396 int leftover = bytes % MAX_MOVE_BYTES;
3400 if (Pmode == DImode)
3402 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3403 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3404 emit_insn (gen_cmpdi (temp, const0_rtx));
3408 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3409 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3410 emit_insn (gen_cmpsi (temp, const0_rtx));
3413 emit_jump_insn (gen_beq (aligned_label));
3415 /* Unaligned loop. */
3416 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3417 emit_jump_insn (gen_jump (join_label));
3421 emit_label (aligned_label);
3422 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3424 emit_label (join_label);
3426 /* Bytes at the end of the loop. */
3428 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3430 change_address (orig_src, BLKmode,
3437 block_move_call (dest_reg, src_reg, bytes_rtx);
3440 /* Emit load/stores for a small constant block_move.
3442 operands[0] is the memory address of the destination.
3443 operands[1] is the memory address of the source.
3444 operands[2] is the number of bytes to move.
3445 operands[3] is the alignment.
3446 operands[4] is a temp register.
3447 operands[5] is a temp register.
3449 operands[3+num_regs] is the last temp register.
3451 The block move type can be one of the following:
3452 BLOCK_MOVE_NORMAL Do all of the block move.
3453 BLOCK_MOVE_NOT_LAST Do all but the last store.
3454 BLOCK_MOVE_LAST Do just the last store. */
3457 output_block_move (insn, operands, num_regs, move_type)
3461 enum block_move_type move_type;
3463 rtx dest_reg = XEXP (operands[0], 0);
3464 rtx src_reg = XEXP (operands[1], 0);
3465 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3466 int align = INTVAL (operands[3]);
3469 int use_lwl_lwr = 0;
3470 int last_operand = num_regs + 4;
3476 const char *load; /* load insn without nop */
3477 const char *load_nop; /* load insn with trailing nop */
3478 const char *store; /* store insn */
3479 const char *final; /* if last_store used: NULL or swr */
3480 const char *last_store; /* last store instruction */
3481 int offset; /* current offset */
3482 enum machine_mode mode; /* mode to use on (MEM) */
3485 /* ??? Detect a bug in GCC, where it can give us a register
3486 the same as one of the addressing registers and reduce
3487 the number of registers available. */
3488 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3489 if (! reg_mentioned_p (operands[i], operands[0])
3490 && ! reg_mentioned_p (operands[i], operands[1]))
3491 xoperands[safe_regs++] = operands[i];
3493 if (safe_regs < last_operand)
3495 xoperands[0] = operands[0];
3496 xoperands[1] = operands[1];
3497 xoperands[2] = operands[2];
3498 xoperands[3] = operands[3];
3499 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3502 /* If we are given global or static addresses, and we would be
3503 emitting a few instructions, try to save time by using a
3504 temporary register for the pointer. */
3505 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3506 an ldl/ldr instruction pair. We play it safe, and always move
3507 constant addresses into registers when generating N32/N64 code, just
3508 in case we might emit an unaligned load instruction. */
3509 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3510 || mips_abi == ABI_N32 || mips_abi == ABI_64))
3512 if (CONSTANT_P (src_reg))
3515 mips_count_memory_refs (operands[1], 1);
3517 src_reg = operands[3 + num_regs--];
3518 if (move_type != BLOCK_MOVE_LAST)
3520 xoperands[1] = operands[1];
3521 xoperands[0] = src_reg;
3522 if (Pmode == DImode)
3523 output_asm_insn ("dla\t%0,%1", xoperands);
3525 output_asm_insn ("la\t%0,%1", xoperands);
3529 if (CONSTANT_P (dest_reg))
3532 mips_count_memory_refs (operands[0], 1);
3534 dest_reg = operands[3 + num_regs--];
3535 if (move_type != BLOCK_MOVE_LAST)
3537 xoperands[1] = operands[0];
3538 xoperands[0] = dest_reg;
3539 if (Pmode == DImode)
3540 output_asm_insn ("dla\t%0,%1", xoperands);
3542 output_asm_insn ("la\t%0,%1", xoperands);
3547 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3548 are not offsettable, however, offsettable_address_p says they are
3549 offsettable. I think this is a bug in offsettable_address_p.
3550 For expediency, we fix this by just loading the address into a register
3551 if we happen to get one. */
3553 if (GET_CODE (src_reg) == LO_SUM)
3555 src_reg = operands[3 + num_regs--];
3556 if (move_type != BLOCK_MOVE_LAST)
3558 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3559 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3560 xoperands[0] = src_reg;
3561 if (Pmode == DImode)
3562 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3564 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3568 if (GET_CODE (dest_reg) == LO_SUM)
3570 dest_reg = operands[3 + num_regs--];
3571 if (move_type != BLOCK_MOVE_LAST)
3573 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3574 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3575 xoperands[0] = dest_reg;
3576 if (Pmode == DImode)
3577 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3579 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3583 if (num_regs > (int) ARRAY_SIZE (load_store))
3584 num_regs = ARRAY_SIZE (load_store);
3586 else if (num_regs < 1)
3587 abort_with_insn (insn,
3588 "Cannot do block move, not enough scratch registers");
3592 load_store[num].offset = offset;
3594 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3596 load_store[num].load = "ld\t%0,%1";
3597 load_store[num].load_nop = "ld\t%0,%1%#";
3598 load_store[num].store = "sd\t%0,%1";
3599 load_store[num].last_store = "sd\t%0,%1";
3600 load_store[num].final = 0;
3601 load_store[num].mode = DImode;
3606 /* ??? Fails because of a MIPS assembler bug? */
3607 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3609 if (BYTES_BIG_ENDIAN)
3611 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3612 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3613 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3614 load_store[num].last_store = "sdr\t%0,%2";
3615 load_store[num].final = "sdl\t%0,%1";
3619 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3620 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3621 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3622 load_store[num].last_store = "sdr\t%0,%1";
3623 load_store[num].final = "sdl\t%0,%2";
3626 load_store[num].mode = DImode;
3632 else if (bytes >= 4 && align >= 4)
3634 load_store[num].load = "lw\t%0,%1";
3635 load_store[num].load_nop = "lw\t%0,%1%#";
3636 load_store[num].store = "sw\t%0,%1";
3637 load_store[num].last_store = "sw\t%0,%1";
3638 load_store[num].final = 0;
3639 load_store[num].mode = SImode;
3644 else if (bytes >= 4 && ! TARGET_MIPS16)
3646 if (BYTES_BIG_ENDIAN)
3648 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3649 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3650 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3651 load_store[num].last_store = "swr\t%0,%2";
3652 load_store[num].final = "swl\t%0,%1";
3656 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3657 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3658 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3659 load_store[num].last_store = "swr\t%0,%1";
3660 load_store[num].final = "swl\t%0,%2";
3663 load_store[num].mode = SImode;
3669 else if (bytes >= 2 && align >= 2)
3671 load_store[num].load = "lh\t%0,%1";
3672 load_store[num].load_nop = "lh\t%0,%1%#";
3673 load_store[num].store = "sh\t%0,%1";
3674 load_store[num].last_store = "sh\t%0,%1";
3675 load_store[num].final = 0;
3676 load_store[num].mode = HImode;
3682 load_store[num].load = "lb\t%0,%1";
3683 load_store[num].load_nop = "lb\t%0,%1%#";
3684 load_store[num].store = "sb\t%0,%1";
3685 load_store[num].last_store = "sb\t%0,%1";
3686 load_store[num].final = 0;
3687 load_store[num].mode = QImode;
3692 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3694 dslots_load_total++;
3695 dslots_load_filled++;
3697 if (CONSTANT_P (src_reg))
3698 mips_count_memory_refs (src_reg, 1);
3700 if (CONSTANT_P (dest_reg))
3701 mips_count_memory_refs (dest_reg, 1);
3704 /* Emit load/stores now if we have run out of registers or are
3705 at the end of the move. */
3707 if (++num == num_regs || bytes == 0)
3709 /* If only load/store, we need a NOP after the load. */
3712 load_store[0].load = load_store[0].load_nop;
3713 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3714 dslots_load_filled--;
3717 if (move_type != BLOCK_MOVE_LAST)
3719 for (i = 0; i < num; i++)
3723 if (!operands[i + 4])
3726 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3727 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3728 REGNO (operands[i + 4]));
3730 offset = load_store[i].offset;
3731 xoperands[0] = operands[i + 4];
3732 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3733 plus_constant (src_reg, offset));
3738 = GET_MODE_SIZE (load_store[i].mode) - 1;
3740 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3741 plus_constant (src_reg,
3746 output_asm_insn (load_store[i].load, xoperands);
3750 for (i = 0; i < num; i++)
3752 int last_p = (i == num-1 && bytes == 0);
3753 int offset = load_store[i].offset;
3755 xoperands[0] = operands[i + 4];
3756 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3757 plus_constant (dest_reg, offset));
3762 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3763 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3764 plus_constant (dest_reg,
3769 if (move_type == BLOCK_MOVE_NORMAL)
3770 output_asm_insn (load_store[i].store, xoperands);
3772 else if (move_type == BLOCK_MOVE_NOT_LAST)
3775 output_asm_insn (load_store[i].store, xoperands);
3777 else if (load_store[i].final != 0)
3778 output_asm_insn (load_store[i].final, xoperands);
3782 output_asm_insn (load_store[i].last_store, xoperands);
3785 num = 0; /* reset load_store */
3793 /* Argument support functions. */
3795 /* Initialize CUMULATIVE_ARGS for a function. */
3798 init_cumulative_args (cum, fntype, libname)
3799 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3800 tree fntype; /* tree ptr for function decl */
3801 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3803 static CUMULATIVE_ARGS zero_cum;
3804 tree param, next_param;
3806 if (TARGET_DEBUG_E_MODE)
3809 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3812 fputc ('\n', stderr);
3816 tree ret_type = TREE_TYPE (fntype);
3817 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3818 tree_code_name[(int)TREE_CODE (fntype)],
3819 tree_code_name[(int)TREE_CODE (ret_type)]);
3825 /* Determine if this function has variable arguments. This is
3826 indicated by the last argument being 'void_type_mode' if there
3827 are no variable arguments. The standard MIPS calling sequence
3828 passes all arguments in the general purpose registers in this case. */
3830 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3831 param != 0; param = next_param)
3833 next_param = TREE_CHAIN (param);
3834 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3835 cum->gp_reg_found = 1;
3839 /* Advance the argument to the next argument position. */
3842 function_arg_advance (cum, mode, type, named)
3843 CUMULATIVE_ARGS *cum; /* current arg information */
3844 enum machine_mode mode; /* current arg mode */
3845 tree type; /* type of the argument or 0 if lib support */
3846 int named; /* whether or not the argument was named */
3848 if (TARGET_DEBUG_E_MODE)
3851 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3852 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3853 GET_MODE_NAME (mode));
3854 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3855 fprintf (stderr, ", %d )\n\n", named);
3865 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3866 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3869 cum->gp_reg_found = 1;
3870 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3875 cum->gp_reg_found = 1;
3876 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3881 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3882 cum->fp_arg_words++;
3885 if (! cum->gp_reg_found && cum->arg_number <= 2)
3886 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3890 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3891 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3893 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3894 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3895 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3899 cum->gp_reg_found = 1;
3900 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3906 cum->gp_reg_found = 1;
3912 /* Return an RTL expression containing the register for the given mode,
3913 or 0 if the argument is to be passed on the stack. */
3916 function_arg (cum, mode, type, named)
3917 CUMULATIVE_ARGS *cum; /* current arg information */
3918 enum machine_mode mode; /* current arg mode */
3919 tree type; /* type of the argument or 0 if lib support */
3920 int named; /* != 0 for normal args, == 0 for ... args */
3925 unsigned int *arg_words = &cum->arg_words;
3926 int struct_p = (type != 0
3927 && (TREE_CODE (type) == RECORD_TYPE
3928 || TREE_CODE (type) == UNION_TYPE
3929 || TREE_CODE (type) == QUAL_UNION_TYPE));
3931 if (TARGET_DEBUG_E_MODE)
3934 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3935 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3936 GET_MODE_NAME (mode));
3937 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3938 fprintf (stderr, ", %d ) = ", named);
3942 cum->last_arg_fp = 0;
3946 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3948 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3949 regbase = GP_ARG_FIRST;
3952 regbase = FP_ARG_FIRST;
3954 /* If the first arg was a float in a floating point register,
3955 then set bias to align this float arg properly. */
3956 if (cum->arg_words == 1)
3960 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3963 cum->fp_arg_words += cum->fp_arg_words & 1;
3964 cum->last_arg_fp = 1;
3965 arg_words = &cum->fp_arg_words;
3966 regbase = FP_ARG_FIRST;
3969 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3975 if (mips_abi == ABI_EABI
3976 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3977 cum->fp_arg_words += cum->fp_arg_words & 1;
3979 cum->arg_words += cum->arg_words & 1;
3982 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3983 regbase = ((cum->gp_reg_found
3984 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
3985 || cum->arg_number >= 2)
3986 ? GP_ARG_FIRST : FP_ARG_FIRST);
3987 else if (mips_abi == ABI_EABI
3988 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3990 cum->last_arg_fp = 1;
3991 arg_words = &cum->fp_arg_words;
3992 regbase = FP_ARG_FIRST;
3995 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3996 ? GP_ARG_FIRST : FP_ARG_FIRST);
4000 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4001 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4004 /* Drops through. */
4006 if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
4007 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4008 cum->arg_words += (cum->arg_words & 1);
4009 regbase = GP_ARG_FIRST;
4016 regbase = GP_ARG_FIRST;
4021 cum->arg_words += (cum->arg_words & 1);
4022 regbase = GP_ARG_FIRST;
4025 if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
4027 if (TARGET_DEBUG_E_MODE)
4028 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
4037 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
4038 || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named
4039 || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
4040 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4043 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4044 structure contains a double in its entirety, then that 64 bit
4045 chunk is passed in a floating point register. */
4048 /* First check to see if there is any such field. */
4049 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4050 if (TREE_CODE (field) == FIELD_DECL
4051 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4052 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4053 && host_integerp (bit_position (field), 0)
4054 && int_bit_position (field) % BITS_PER_WORD == 0)
4057 /* If the whole struct fits a DFmode register,
4058 we don't need the PARALLEL. */
4059 if (! field || mode == DFmode)
4060 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4063 /* Now handle the special case by returning a PARALLEL
4064 indicating where each 64 bit chunk goes. */
4065 unsigned int chunks;
4066 HOST_WIDE_INT bitpos;
4070 /* ??? If this is a packed structure, then the last hunk won't
4074 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
4075 if (chunks + *arg_words + bias > (unsigned) MAX_ARGS_IN_REGISTERS)
4076 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
4078 /* assign_parms checks the mode of ENTRY_PARM, so we must
4079 use the actual mode here. */
4080 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
4083 regno = regbase + *arg_words + bias;
4084 field = TYPE_FIELDS (type);
4085 for (i = 0; i < chunks; i++)
4089 for (; field; field = TREE_CHAIN (field))
4090 if (TREE_CODE (field) == FIELD_DECL
4091 && int_bit_position (field) >= bitpos)
4095 && int_bit_position (field) == bitpos
4096 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4097 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4098 reg = gen_rtx_REG (DFmode,
4099 regno + FP_ARG_FIRST - GP_ARG_FIRST);
4101 reg = gen_rtx_REG (word_mode, regno);
4104 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4105 GEN_INT (bitpos / BITS_PER_UNIT));
4113 if (TARGET_DEBUG_E_MODE)
4114 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
4115 struct_p ? ", [struct]" : "");
4117 /* The following is a hack in order to pass 1 byte structures
4118 the same way that the MIPS compiler does (namely by passing
4119 the structure in the high byte or half word of the register).
4120 This also makes varargs work. If we have such a structure,
4121 we save the adjustment RTL, and the call define expands will
4122 emit them. For the VOIDmode argument (argument after the
4123 last real argument), pass back a parallel vector holding each
4124 of the adjustments. */
4126 /* ??? function_arg can be called more than once for each argument.
4127 As a result, we compute more adjustments than we need here.
4128 See the CUMULATIVE_ARGS definition in mips.h. */
4130 /* ??? This scheme requires everything smaller than the word size to
4131 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4132 that would mean every int needs to be shifted left, which is very
4133 inefficient. Let's not carry this compatibility to the 64 bit
4134 calling convention for now. */
4136 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
4137 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4139 rtx amount = GEN_INT (BITS_PER_WORD
4140 - int_size_in_bytes (type) * BITS_PER_UNIT);
4141 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
4144 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
4146 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
4150 /* We will be called with a mode of VOIDmode after the last argument
4151 has been seen. Whatever we return will be passed to the call
4152 insn. If we need any shifts for small structures, return them in
4153 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4154 mode. Otherwise, if we have need a mips16 fp_code, return a REG
4155 with the code stored as the mode. */
4156 if (mode == VOIDmode)
4158 if (cum->num_adjusts > 0)
4159 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
4160 gen_rtvec_v (cum->num_adjusts, cum->adjust));
4161 else if (TARGET_MIPS16 && cum->fp_code != 0)
4162 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
4169 function_arg_partial_nregs (cum, mode, type, named)
4170 CUMULATIVE_ARGS *cum; /* current arg information */
4171 enum machine_mode mode; /* current arg mode */
4172 tree type; /* type of the argument or 0 if lib support */
4173 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
4175 if ((mode == BLKmode
4176 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4177 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4178 && cum->arg_words < (unsigned) MAX_ARGS_IN_REGISTERS
4179 && mips_abi != ABI_EABI)
4182 if (mode == BLKmode)
4183 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
4186 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4188 if (words + cum->arg_words <= (unsigned) MAX_ARGS_IN_REGISTERS)
4189 return 0; /* structure fits in registers */
4191 if (TARGET_DEBUG_E_MODE)
4192 fprintf (stderr, "function_arg_partial_nregs = %d\n",
4193 MAX_ARGS_IN_REGISTERS - cum->arg_words);
4195 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
4198 else if (mode == DImode
4199 && cum->arg_words == MAX_ARGS_IN_REGISTERS - (unsigned)1
4200 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4202 if (TARGET_DEBUG_E_MODE)
4203 fprintf (stderr, "function_arg_partial_nregs = 1\n");
4211 /* Create the va_list data type.
4212 We keep 3 pointers, and two offsets.
4213 Two pointers are to the overflow area, which starts at the CFA.
4214 One of these is constant, for addressing into the GPR save area below it.
4215 The other is advanced up the stack through the overflow region.
4216 The third pointer is to the GPR save area. Since the FPR save area
4217 is just below it, we can address FPR slots off this pointer.
4218 We also keep two one-byte offsets, which are to be subtracted from the
4219 constant pointers to yield addresses in the GPR and FPR save areas.
4220 These are downcounted as float or non-float arguments are used,
4221 and when they get to zero, the argument must be obtained from the
4223 If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
4224 and a single pointer is enough. It's started at the GPR save area,
4225 and is advanced, period.
4226 Note that the GPR save area is not constant size, due to optimization
4227 in the prologue. Hence, we can't use a design with two pointers
4228 and two offsets, although we could have designed this with two pointers
4229 and three offsets. */
4233 mips_build_va_list ()
4235 if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4237 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4239 record = make_node (RECORD_TYPE);
4241 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4243 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4245 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4247 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4248 unsigned_char_type_node);
4249 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4250 unsigned_char_type_node);
4253 DECL_FIELD_CONTEXT (f_ovfl) = record;
4254 DECL_FIELD_CONTEXT (f_gtop) = record;
4255 DECL_FIELD_CONTEXT (f_ftop) = record;
4256 DECL_FIELD_CONTEXT (f_goff) = record;
4257 DECL_FIELD_CONTEXT (f_foff) = record;
4259 TYPE_FIELDS (record) = f_ovfl;
4260 TREE_CHAIN (f_ovfl) = f_gtop;
4261 TREE_CHAIN (f_gtop) = f_ftop;
4262 TREE_CHAIN (f_ftop) = f_goff;
4263 TREE_CHAIN (f_goff) = f_foff;
4265 layout_type (record);
4269 return ptr_type_node;
4272 /* Implement va_start. stdarg_p is 0 if implementing
4273 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4274 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4275 (It doesn't have "...", so it inherits the pointers of its caller.) */
4278 mips_va_start (stdarg_p, valist, nextarg)
4286 /* Find out how many non-float named formals */
4287 int_arg_words = current_function_args_info.arg_words;
4289 if (mips_abi == ABI_EABI)
4291 int gpr_save_area_size;
4292 /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
4293 if (int_arg_words < 8 )
4294 /* Adjust for the prologue's economy measure */
4295 gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
4297 gpr_save_area_size = 0;
4299 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4301 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4302 tree ovfl, gtop, ftop, goff, foff;
4304 int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
4305 int fpr_save_offset;
4307 float_formals = current_function_args_info.fp_arg_words;
4308 /* If mips2, the number of formals is half the reported # of words */
4311 floats_passed_in_regs = (TARGET_64BIT ? 8 : 4);
4313 f_ovfl = TYPE_FIELDS (va_list_type_node);
4314 f_gtop = TREE_CHAIN (f_ovfl);
4315 f_ftop = TREE_CHAIN (f_gtop);
4316 f_goff = TREE_CHAIN (f_ftop);
4317 f_foff = TREE_CHAIN (f_goff);
4319 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4320 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4321 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4322 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4323 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4325 /* Emit code setting a pointer into the overflow (shared-stack) area.
4326 If there were more than 8 non-float formals, or more than 8
4327 float formals, then this pointer isn't to the base of the area.
4328 In that case, it must point to where the first vararg is. */
4330 if (float_formals > floats_passed_in_regs)
4331 size_excess += (float_formals-floats_passed_in_regs) * 8;
4332 if (int_arg_words > 8)
4333 size_excess += (int_arg_words-8) * UNITS_PER_WORD;
4335 /* FIXME: for mips2, the above size_excess can be wrong. Because the
4336 overflow stack holds mixed size items, there can be alignments,
4337 so that an 8 byte double following a 4 byte int will be on an
4338 8 byte boundary. This means that the above calculation should
4339 take into account the exact sequence of floats and non-floats
4340 which make up the excess. That calculation should be rolled
4341 into the code which sets the current_function_args_info struct.
4342 The above then reduces to a fetch from that struct. */
4345 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4347 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4348 build_int_2 (size_excess, 0));
4349 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4350 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4352 /* Emit code setting a ptr to the base of the overflow area. */
4353 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4354 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4355 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4357 /* Emit code setting a pointer to the GPR save area.
4358 More precisely, a pointer to off-the-end of the FPR save area.
4359 If mips4, this is gpr_save_area_size below the overflow area.
4360 If mips2, also round down to an 8-byte boundary, since the FPR
4361 save area is 8-byte aligned, and GPR is 4-byte-aligned.
4362 Therefore there can be a 4-byte gap between the save areas. */
4363 gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4364 fpr_save_offset = gpr_save_area_size;
4367 if (fpr_save_offset & 7)
4368 fpr_save_offset += 4;
4370 if (fpr_save_offset)
4371 gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
4372 build_int_2 (-fpr_save_offset,-1));
4373 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
4374 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4376 /* Emit code initting an offset to the size of the GPR save area */
4377 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4378 build_int_2 (gpr_save_area_size,0));
4379 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4381 /* Emit code initting an offset from ftop to the first float
4382 vararg. This varies in size, since any float
4383 varargs are put in the FPR save area after the formals.
4384 Note it's 8 bytes/formal regardless of TARGET_64BIT.
4385 However, mips2 stores 4 GPRs, mips4 stores 8 GPRs.
4386 If there are 8 or more float formals, init to zero.
4387 (In fact, the formals aren't stored in the bottom of the
4388 FPR save area: they are elsewhere, and the size of the FPR
4389 save area is economized by the prologue. But this code doesn't
4390 care. This design is unaffected by that fact.) */
4391 if (float_formals >= floats_passed_in_regs)
4394 fpr_offset = (floats_passed_in_regs - float_formals) * 8;
4395 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4396 build_int_2 (fpr_offset,0));
4397 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4401 /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
4403 /* Everything is in the GPR save area, or in the overflow
4404 area which is contiguous with it. */
4406 int offset = -gpr_save_area_size;
4407 if (gpr_save_area_size == 0)
4408 offset = (stdarg_p ? 0 : -UNITS_PER_WORD);
4409 nextarg = plus_constant (nextarg, offset);
4410 std_expand_builtin_va_start (1, valist, nextarg);
4422 /* ??? This had been conditional on
4423 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4424 and both iris5.h and iris6.h define _MIPS_SIM. */
4425 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4426 ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
4428 ofs = -UNITS_PER_WORD;
4431 nextarg = plus_constant (nextarg, ofs);
4432 std_expand_builtin_va_start (1, valist, nextarg);
4436 /* Implement va_arg. */
4439 mips_va_arg (valist, type)
4442 HOST_WIDE_INT size, rsize;
4446 size = int_size_in_bytes (type);
4447 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4449 if (mips_abi == ABI_EABI)
4452 rtx r, lab_over = NULL_RTX, lab_false;
4453 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4454 tree ovfl, gtop, ftop, goff, foff;
4457 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4459 size = rsize = POINTER_SIZE / BITS_PER_UNIT;
4461 addr_rtx = gen_reg_rtx (Pmode);
4463 if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
4465 /* Case of all args in a merged stack. No need to check bounds,
4466 just advance valist along the stack. */
4471 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4473 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4474 build_int_2 (2*UNITS_PER_WORD - 1, 0));
4475 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4476 build_int_2 (-2*UNITS_PER_WORD, -1));
4477 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4478 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4481 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4483 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4485 emit_move_insn (addr_rtx, r);
4487 /* flush the POSTINCREMENT */
4492 r = gen_rtx_MEM (Pmode, addr_rtx);
4493 MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4494 emit_move_insn (addr_rtx, r);
4498 if (BYTES_BIG_ENDIAN && rsize != size)
4499 addr_rtx = plus_constant (addr_rtx, rsize - size);
4504 /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
4506 f_ovfl = TYPE_FIELDS (va_list_type_node);
4507 f_gtop = TREE_CHAIN (f_ovfl);
4508 f_ftop = TREE_CHAIN (f_gtop);
4509 f_goff = TREE_CHAIN (f_ftop);
4510 f_foff = TREE_CHAIN (f_goff);
4512 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4513 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4514 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4515 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4516 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4518 lab_false = gen_label_rtx ();
4519 lab_over = gen_label_rtx ();
4521 if (TREE_CODE (type) == REAL_TYPE)
4524 /* Emit code to branch if foff == 0. */
4525 r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
4527 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4528 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4530 /* Emit code for addr_rtx = ftop - foff */
4531 t = build (MINUS_EXPR, TREE_TYPE (ftop), ftop, foff );
4532 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4534 emit_move_insn (addr_rtx, r);
4536 /* Emit code for foff-=8.
4537 Advances the offset up FPR save area by one double */
4538 t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
4539 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
4540 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4543 emit_jump (lab_over);
4545 emit_label (lab_false);
4549 /* For mips2, the overflow area contains mixed size items.
4550 If a 4-byte int is followed by an 8-byte float, then
4551 natural alignment causes a 4 byte gap.
4552 So, dynamically adjust ovfl up to a multiple of 8. */
4553 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
4554 build_int_2 (7, 0));
4555 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
4556 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4557 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4560 /* Emit code for addr_rtx = the ovfl pointer into overflow area.
4561 Regardless of mips2, postincrement the ovfl pointer by 8. */
4562 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4564 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4566 emit_move_insn (addr_rtx, r);
4569 emit_label (lab_over);
4578 && TREE_CODE (type) == INTEGER_TYPE
4579 && TYPE_PRECISION (type) == 64)
4581 /* In mips2, int takes 32 bits of the GPR save area, but
4582 longlong takes an aligned 64 bits. So, emit code
4583 to zero the low order bits of goff, thus aligning
4584 the later calculation of (gtop-goff) upwards. */
4585 t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
4586 build_int_2 (-8, -1));
4587 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4588 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4591 /* Emit code to branch if goff == 0. */
4592 r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
4594 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4595 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4597 /* Emit code for addr_rtx = gtop - goff. */
4598 t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
4599 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4601 emit_move_insn (addr_rtx, r);
4603 /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
4604 if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
4607 step_size = UNITS_PER_WORD;
4609 /* Emit code for goff = goff - step_size.
4610 Advances the offset up GPR save area over the item. */
4611 t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
4612 build_int_2 (step_size, 0));
4613 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4614 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4617 emit_jump (lab_over);
4619 emit_label (lab_false);
4621 /* Emit code for addr_rtx -> overflow area, postinc by step_size */
4622 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4623 size_int (step_size));
4624 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4626 emit_move_insn (addr_rtx, r);
4629 emit_label (lab_over);
4633 r = gen_rtx_MEM (Pmode, addr_rtx);
4634 MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4635 emit_move_insn (addr_rtx, r);
4639 if (BYTES_BIG_ENDIAN && rsize != size)
4640 addr_rtx = plus_constant (addr_rtx, rsize - size);
4650 /* ??? The original va-mips.h did always align, despite the fact
4651 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4652 increment mechanism. */
4656 else if (TYPE_ALIGN (type) > 32)
4661 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4662 build_int_2 (align - 1, 0));
4663 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4664 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4665 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4667 /* Everything past the alignment is standard. */
4668 return std_expand_builtin_va_arg (valist, type);
4672 /* Abort after printing out a specific insn. */
4675 abort_with_insn (insn, reason)
4684 /* Set up the threshold for data to go into the small data area, instead
4685 of the normal data area, and detect any conflicts in the switches. */
4690 register int i, start;
4692 register enum machine_mode mode;
4694 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4696 if (mips_section_threshold <= 0)
4697 target_flags &= ~MASK_GPOPT;
4699 target_flags |= MASK_GPOPT;
4701 /* If both single-float and soft-float are set, then clear the one that
4702 was set by TARGET_DEFAULT, leaving the one that was set by the
4703 user. We assume here that the specs prevent both being set by the
4705 #ifdef TARGET_DEFAULT
4706 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4707 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
4710 /* Get the architectural level. */
4711 if (mips_isa_string == 0)
4712 mips_isa = MIPS_ISA_DEFAULT;
4714 else if (ISDIGIT (*mips_isa_string))
4716 mips_isa = atoi (mips_isa_string);
4719 /* -mno-mips16 overrides -mips16. */
4720 if (mips_no_mips16_string == NULL)
4722 target_flags |= MASK_MIPS16;
4726 mips_isa = MIPS_ISA_DEFAULT;
4730 mips_isa = MIPS_ISA_DEFAULT;
4733 else if (mips_isa < 1 || mips_isa > 4)
4735 error ("-mips%d not supported", mips_isa);
4742 error ("bad value (%s) for -mips switch", mips_isa_string);
4746 #ifdef MIPS_ABI_DEFAULT
4747 /* Get the ABI to use. */
4748 if (mips_abi_string == (char *) 0)
4749 mips_abi = MIPS_ABI_DEFAULT;
4750 else if (! strcmp (mips_abi_string, "32"))
4752 else if (! strcmp (mips_abi_string, "o64"))
4754 else if (! strcmp (mips_abi_string, "n32"))
4756 else if (! strcmp (mips_abi_string, "64"))
4758 else if (! strcmp (mips_abi_string, "eabi"))
4759 mips_abi = ABI_EABI;
4761 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4763 /* A specified ISA defaults the ABI if it was not specified. */
4764 if (mips_abi_string == 0 && mips_isa_string
4765 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4767 if (! ISA_HAS_64BIT_REGS)
4773 /* A specified ABI defaults the ISA if it was not specified. */
4774 else if (mips_isa_string == 0 && mips_abi_string
4775 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4777 if (mips_abi == ABI_32)
4779 else if (mips_abi == ABI_N32)
4785 /* If both ABI and ISA were specified, check for conflicts. */
4786 else if (mips_isa_string && mips_abi_string)
4788 if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
4789 || mips_abi == ABI_O64))
4790 || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32))
4791 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4794 /* Override TARGET_DEFAULT if necessary. */
4795 if (mips_abi == ABI_32)
4796 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4798 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4799 then set the type sizes. In the EABI in 64 bit mode, longs and
4800 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4801 if (mips_explicit_type_size_string == NULL
4802 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4803 || mips_abi == ABI_64))
4804 target_flags |= MASK_LONG64;
4806 /* ??? This doesn't work yet, so don't let people try to use it. */
4807 if (mips_abi == ABI_32)
4808 error ("The -mabi=32 support does not work yet.");
4811 if (mips_abi_string)
4812 error ("This target does not support the -mabi switch.");
4815 #ifdef MIPS_CPU_STRING_DEFAULT
4816 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4817 greater than that supported by the default processor, then the user gets
4818 an error. Normally, the compiler will just default to the base level cpu
4819 for the indicated isa. */
4820 if (mips_cpu_string == 0)
4821 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4824 /* Identify the processor type. */
4825 if (mips_cpu_string == 0
4826 || ! strcmp (mips_cpu_string, "default")
4827 || ! strcmp (mips_cpu_string, "DEFAULT"))
4832 mips_cpu_string = "3000";
4833 mips_cpu = PROCESSOR_R3000;
4836 mips_cpu_string = "6000";
4837 mips_cpu = PROCESSOR_R6000;
4840 mips_cpu_string = "4000";
4841 mips_cpu = PROCESSOR_R4000;
4844 mips_cpu_string = "8000";
4845 mips_cpu = PROCESSOR_R8000;
4851 const char *p = mips_cpu_string;
4854 /* We need to cope with the various "vr" prefixes for the NEC 4300
4855 and 4100 processors. */
4856 if (*p == 'v' || *p == 'V')
4859 if (*p == 'r' || *p == 'R')
4862 /* Since there is no difference between a R2000 and R3000 in
4863 terms of the scheduler, we collapse them into just an R3000. */
4865 mips_cpu = PROCESSOR_DEFAULT;
4869 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4870 mips_cpu = PROCESSOR_R3000;
4874 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4875 mips_cpu = PROCESSOR_R3000;
4876 else if (!strcmp (p, "3900"))
4877 mips_cpu = PROCESSOR_R3900;
4881 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4882 mips_cpu = PROCESSOR_R4000;
4883 /* The vr4100 is a non-FP ISA III processor with some extra
4885 else if (!strcmp (p, "4100"))
4887 mips_cpu = PROCESSOR_R4100;
4888 target_flags |= MASK_SOFT_FLOAT ;
4890 /* The vr4300 is a standard ISA III processor, but with a different
4892 else if (!strcmp (p, "4300"))
4893 mips_cpu = PROCESSOR_R4300;
4894 /* The r4400 is exactly the same as the r4000 from the compiler's
4896 else if (!strcmp (p, "4400"))
4897 mips_cpu = PROCESSOR_R4000;
4898 else if (!strcmp (p, "4600"))
4899 mips_cpu = PROCESSOR_R4600;
4900 else if (!strcmp (p, "4650"))
4901 mips_cpu = PROCESSOR_R4650;
4905 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4906 mips_cpu = PROCESSOR_R5000;
4910 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4911 mips_cpu = PROCESSOR_R6000;
4915 if (!strcmp (p, "8000"))
4916 mips_cpu = PROCESSOR_R8000;
4920 if (!strcmp (p, "orion"))
4921 mips_cpu = PROCESSOR_R4600;
4926 && mips_cpu != PROCESSOR_R4300
4927 && mips_cpu != PROCESSOR_R4100
4928 && mips_cpu != PROCESSOR_R5000)
4929 mips_cpu = PROCESSOR_DEFAULT;
4931 if (mips_cpu == PROCESSOR_DEFAULT)
4933 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4934 mips_cpu_string = "default";
4938 if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
4939 || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
4940 || ((mips_cpu == PROCESSOR_R4000
4941 || mips_cpu == PROCESSOR_R4100
4942 || mips_cpu == PROCESSOR_R4300
4943 || mips_cpu == PROCESSOR_R4600
4944 || mips_cpu == PROCESSOR_R4650)
4945 && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
4946 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4948 /* make sure sizes of ints/longs/etc. are ok */
4949 if (! ISA_HAS_64BIT_REGS)
4952 fatal ("-mips%d does not support 64 bit fp registers", mips_isa);
4954 else if (TARGET_64BIT)
4955 fatal ("-mips%d does not support 64 bit gp registers", mips_isa);
4958 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4959 flag_pcc_struct_return = 0;
4961 /* Tell halfpic.c that we have half-pic code if we do. */
4962 if (TARGET_HALF_PIC)
4965 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4966 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4967 /* ??? -non_shared turns off pic code generation, but this is not
4969 if (TARGET_ABICALLS)
4971 mips_abicalls = MIPS_ABICALLS_YES;
4973 if (mips_section_threshold > 0)
4974 warning ("-G is incompatible with PIC code which is the default");
4977 mips_abicalls = MIPS_ABICALLS_NO;
4979 /* -membedded-pic is a form of PIC code suitable for embedded
4980 systems. All calls are made using PC relative addressing, and
4981 all data is addressed using the $gp register. This requires gas,
4982 which does most of the work, and GNU ld, which automatically
4983 expands PC relative calls which are out of range into a longer
4984 instruction sequence. All gcc really does differently is
4985 generate a different sequence for a switch. */
4986 if (TARGET_EMBEDDED_PIC)
4989 if (TARGET_ABICALLS)
4990 warning ("-membedded-pic and -mabicalls are incompatible");
4993 warning ("-G and -membedded-pic are incompatible");
4995 /* Setting mips_section_threshold is not required, because gas
4996 will force everything to be GP addressable anyhow, but
4997 setting it will cause gcc to make better estimates of the
4998 number of instructions required to access a particular data
5000 mips_section_threshold = 0x7fffffff;
5003 /* This optimization requires a linker that can support a R_MIPS_LO16
5004 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5005 GNU ld has this support, but not all other MIPS linkers do, so we enable
5006 this optimization only if the user requests it, or if GNU ld is the
5007 standard linker for this configuration. */
5008 /* ??? This does not work when target addresses are DImode.
5009 This is because we are missing DImode high/lo_sum patterns. */
5010 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5012 mips_split_addresses = 1;
5014 mips_split_addresses = 0;
5016 /* -mrnames says to use the MIPS software convention for register
5017 names instead of the hardware names (ie, $a0 instead of $4).
5018 We do this by switching the names in mips_reg_names, which the
5019 reg_names points into via the REGISTER_NAMES macro. */
5021 if (TARGET_NAME_REGS)
5022 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names,
5023 sizeof (mips_reg_names));
5025 /* When compiling for the mips16, we can not use floating point. We
5026 record the original hard float value in mips16_hard_float. */
5029 if (TARGET_SOFT_FLOAT)
5030 mips16_hard_float = 0;
5032 mips16_hard_float = 1;
5033 target_flags |= MASK_SOFT_FLOAT;
5035 /* Don't run the scheduler before reload, since it tends to
5036 increase register pressure. */
5037 flag_schedule_insns = 0;
5040 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5041 to avoid using up another bit in target_flags. */
5042 if (mips_entry_string != NULL)
5044 if (*mips_entry_string != '\0')
5045 error ("Invalid option `entry%s'", mips_entry_string);
5047 if (! TARGET_MIPS16)
5048 warning ("-mentry is only meaningful with -mips-16");
5053 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5054 attributes can access it. */
5060 /* Initialize the high and low values for legitimate floating point
5061 constants. Rather than trying to get the accuracy down to the
5062 last bit, just use approximate ranges. */
5063 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5064 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5065 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5066 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5068 mips_print_operand_punct['?'] = 1;
5069 mips_print_operand_punct['#'] = 1;
5070 mips_print_operand_punct['&'] = 1;
5071 mips_print_operand_punct['!'] = 1;
5072 mips_print_operand_punct['*'] = 1;
5073 mips_print_operand_punct['@'] = 1;
5074 mips_print_operand_punct['.'] = 1;
5075 mips_print_operand_punct['('] = 1;
5076 mips_print_operand_punct[')'] = 1;
5077 mips_print_operand_punct['['] = 1;
5078 mips_print_operand_punct[']'] = 1;
5079 mips_print_operand_punct['<'] = 1;
5080 mips_print_operand_punct['>'] = 1;
5081 mips_print_operand_punct['{'] = 1;
5082 mips_print_operand_punct['}'] = 1;
5083 mips_print_operand_punct['^'] = 1;
5084 mips_print_operand_punct['$'] = 1;
5085 mips_print_operand_punct['+'] = 1;
5086 mips_print_operand_punct['~'] = 1;
5088 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5089 mips_char_to_class['e'] = M16_NA_REGS;
5090 mips_char_to_class['t'] = T_REG;
5091 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5092 mips_char_to_class['h'] = HI_REG;
5093 mips_char_to_class['l'] = LO_REG;
5094 mips_char_to_class['a'] = HILO_REG;
5095 mips_char_to_class['x'] = MD_REGS;
5096 mips_char_to_class['b'] = ALL_REGS;
5097 mips_char_to_class['y'] = GR_REGS;
5098 mips_char_to_class['z'] = ST_REGS;
5100 /* Set up array to map GCC register number to debug register number.
5101 Ignore the special purpose register numbers. */
5103 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5104 mips_dbx_regno[i] = -1;
5106 start = GP_DBX_FIRST - GP_REG_FIRST;
5107 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5108 mips_dbx_regno[i] = i + start;
5110 start = FP_DBX_FIRST - FP_REG_FIRST;
5111 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5112 mips_dbx_regno[i] = i + start;
5114 /* Set up array giving whether a given register can hold a given mode.
5115 At present, restrict ints from being in FP registers, because reload
5116 is a little enthusiastic about storing extra values in FP registers,
5117 and this is not good for things like OS kernels. Also, due to the
5118 mandatory delay, it is as fast to load from cached memory as to move
5119 from the FP register. */
5121 for (mode = VOIDmode;
5122 mode != MAX_MACHINE_MODE;
5123 mode = (enum machine_mode) ((int)mode + 1))
5125 register int size = GET_MODE_SIZE (mode);
5126 register enum mode_class class = GET_MODE_CLASS (mode);
5128 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5135 temp = (regno == FPSW_REGNUM);
5137 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5138 || FP_REG_P (regno));
5141 else if (GP_REG_P (regno))
5142 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5144 else if (FP_REG_P (regno))
5145 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
5146 && (class == MODE_FLOAT
5147 || class == MODE_COMPLEX_FLOAT
5148 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
5149 && (! TARGET_SINGLE_FLOAT || size <= 4));
5151 else if (MD_REG_P (regno))
5152 temp = (class == MODE_INT
5153 && (size <= UNITS_PER_WORD
5154 || (regno == MD_REG_FIRST
5155 && size == 2 * UNITS_PER_WORD)));
5160 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5164 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5165 initialized yet, so we can't use that here. */
5166 gpr_mode = TARGET_64BIT ? DImode : SImode;
5168 /* Provide default values for align_* for 64-bit targets. */
5169 if (TARGET_64BIT && !TARGET_MIPS16)
5171 if (align_loops == 0)
5173 if (align_jumps == 0)
5175 if (align_functions == 0)
5176 align_functions = 8;
5179 /* Register global variables with the garbage collector. */
5180 mips_add_gc_roots ();
5183 /* On the mips16, we want to allocate $24 (T_REG) before other
5184 registers for instructions for which it is possible. This helps
5185 avoid shuffling registers around in order to set up for an xor,
5186 encouraging the compiler to use a cmp instead. */
5189 mips_order_regs_for_local_alloc ()
5193 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5194 reg_alloc_order[i] = i;
5198 /* It really doesn't matter where we put register 0, since it is
5199 a fixed register anyhow. */
5200 reg_alloc_order[0] = 24;
5201 reg_alloc_order[24] = 0;
5206 /* The MIPS debug format wants all automatic variables and arguments
5207 to be in terms of the virtual frame pointer (stack pointer before
5208 any adjustment in the function), while the MIPS 3.0 linker wants
5209 the frame pointer to be the stack pointer after the initial
5210 adjustment. So, we do the adjustment here. The arg pointer (which
5211 is eliminated) points to the virtual frame pointer, while the frame
5212 pointer (which may be eliminated) points to the stack pointer after
5213 the initial adjustments. */
5216 mips_debugger_offset (addr, offset)
5218 HOST_WIDE_INT offset;
5220 rtx offset2 = const0_rtx;
5221 rtx reg = eliminate_constant_term (addr, &offset2);
5224 offset = INTVAL (offset2);
5226 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5227 || reg == hard_frame_pointer_rtx)
5229 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
5230 ? compute_frame_size (get_frame_size ())
5231 : current_frame_info.total_size;
5233 /* MIPS16 frame is smaller */
5234 if (frame_pointer_needed && TARGET_MIPS16)
5235 frame_size -= current_function_outgoing_args_size;
5237 offset = offset - frame_size;
5240 /* sdbout_parms does not want this to crash for unrecognized cases. */
5242 else if (reg != arg_pointer_rtx)
5243 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
5249 /* A C compound statement to output to stdio stream STREAM the
5250 assembler syntax for an instruction operand X. X is an RTL
5253 CODE is a value that can be used to specify one of several ways
5254 of printing the operand. It is used when identical operands
5255 must be printed differently depending on the context. CODE
5256 comes from the `%' specification that was used to request
5257 printing of the operand. If the specification was just `%DIGIT'
5258 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5259 is the ASCII code for LTR.
5261 If X is a register, this macro should print the register's name.
5262 The names can be found in an array `reg_names' whose type is
5263 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5265 When the machine description has a specification `%PUNCT' (a `%'
5266 followed by a punctuation character), this macro is called with
5267 a null pointer for X and the punctuation character for CODE.
5269 The MIPS specific codes are:
5271 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5272 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5273 'd' output integer constant in decimal,
5274 'z' if the operand is 0, use $0 instead of normal operand.
5275 'D' print second register of double-word register operand.
5276 'L' print low-order register of double-word register operand.
5277 'M' print high-order register of double-word register operand.
5278 'C' print part of opcode for a branch condition.
5279 'F' print part of opcode for a floating-point branch condition.
5280 'N' print part of opcode for a branch condition, inverted.
5281 'W' print part of opcode for a floating-point branch condition, inverted.
5282 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5283 'B' print 'z' for EQ, 'n' for NE
5284 'b' print 'n' for EQ, 'z' for NE
5285 'T' print 'f' for EQ, 't' for NE
5286 't' print 't' for EQ, 'f' for NE
5287 'Z' print register and a comma, but print nothing for $fcc0
5288 '(' Turn on .set noreorder
5289 ')' Turn on .set reorder
5290 '[' Turn on .set noat
5292 '<' Turn on .set nomacro
5293 '>' Turn on .set macro
5294 '{' Turn on .set volatile (not GAS)
5295 '}' Turn on .set novolatile (not GAS)
5296 '&' Turn on .set noreorder if filling delay slots
5297 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5298 '!' Turn on .set nomacro if filling delay slots
5299 '#' Print nop if in a .set noreorder section.
5300 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5301 '@' Print the name of the assembler temporary register (at or $1).
5302 '.' Print the name of the register with a hard-wired zero (zero or $0).
5303 '^' Print the name of the pic call-through register (t9 or $25).
5304 '$' Print the name of the stack pointer register (sp or $29).
5305 '+' Print the name of the gp register (gp or $28).
5306 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5309 print_operand (file, op, letter)
5310 FILE *file; /* file to write to */
5311 rtx op; /* operand to print */
5312 int letter; /* %<letter> or 0 */
5314 register enum rtx_code code;
5316 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5321 if (mips_branch_likely)
5326 fputs (reg_names [GP_REG_FIRST + 1], file);
5330 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5334 fputs (reg_names [GP_REG_FIRST + 0], file);
5338 fputs (reg_names[STACK_POINTER_REGNUM], file);
5342 fputs (reg_names[GP_REG_FIRST + 28], file);
5346 if (final_sequence != 0 && set_noreorder++ == 0)
5347 fputs (".set\tnoreorder\n\t", file);
5351 if (final_sequence != 0)
5353 if (set_noreorder++ == 0)
5354 fputs (".set\tnoreorder\n\t", file);
5356 if (set_nomacro++ == 0)
5357 fputs (".set\tnomacro\n\t", file);
5362 if (final_sequence != 0 && set_nomacro++ == 0)
5363 fputs ("\n\t.set\tnomacro", file);
5367 if (set_noreorder != 0)
5368 fputs ("\n\tnop", file);
5369 else if (TARGET_STATS)
5370 fputs ("\n\t#nop", file);
5375 if (set_noreorder++ == 0)
5376 fputs (".set\tnoreorder\n\t", file);
5380 if (set_noreorder == 0)
5381 error ("internal error: %%) found without a %%( in assembler pattern");
5383 else if (--set_noreorder == 0)
5384 fputs ("\n\t.set\treorder", file);
5389 if (set_noat++ == 0)
5390 fputs (".set\tnoat\n\t", file);
5395 error ("internal error: %%] found without a %%[ in assembler pattern");
5396 else if (--set_noat == 0)
5397 fputs ("\n\t.set\tat", file);
5402 if (set_nomacro++ == 0)
5403 fputs (".set\tnomacro\n\t", file);
5407 if (set_nomacro == 0)
5408 error ("internal error: %%> found without a %%< in assembler pattern");
5409 else if (--set_nomacro == 0)
5410 fputs ("\n\t.set\tmacro", file);
5415 if (set_volatile++ == 0)
5416 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5420 if (set_volatile == 0)
5421 error ("internal error: %%} found without a %%{ in assembler pattern");
5422 else if (--set_volatile == 0)
5423 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5429 if (align_labels_log > 0)
5430 ASM_OUTPUT_ALIGN (file, align_labels_log);
5435 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
5444 error ("PRINT_OPERAND null pointer");
5448 code = GET_CODE (op);
5450 if (code == SIGN_EXTEND)
5451 op = XEXP (op, 0), code = GET_CODE (op);
5456 case EQ: fputs ("eq", file); break;
5457 case NE: fputs ("ne", file); break;
5458 case GT: fputs ("gt", file); break;
5459 case GE: fputs ("ge", file); break;
5460 case LT: fputs ("lt", file); break;
5461 case LE: fputs ("le", file); break;
5462 case GTU: fputs ("gtu", file); break;
5463 case GEU: fputs ("geu", file); break;
5464 case LTU: fputs ("ltu", file); break;
5465 case LEU: fputs ("leu", file); break;
5467 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5470 else if (letter == 'N')
5473 case EQ: fputs ("ne", file); break;
5474 case NE: fputs ("eq", file); break;
5475 case GT: fputs ("le", file); break;
5476 case GE: fputs ("lt", file); break;
5477 case LT: fputs ("ge", file); break;
5478 case LE: fputs ("gt", file); break;
5479 case GTU: fputs ("leu", file); break;
5480 case GEU: fputs ("ltu", file); break;
5481 case LTU: fputs ("geu", file); break;
5482 case LEU: fputs ("gtu", file); break;
5484 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5487 else if (letter == 'F')
5490 case EQ: fputs ("c1f", file); break;
5491 case NE: fputs ("c1t", file); break;
5493 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5496 else if (letter == 'W')
5499 case EQ: fputs ("c1t", file); break;
5500 case NE: fputs ("c1f", file); break;
5502 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5505 else if (letter == 'S')
5509 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5510 assemble_name (file, buffer);
5513 else if (letter == 'Z')
5515 register int regnum;
5520 regnum = REGNO (op);
5521 if (! ST_REG_P (regnum))
5524 if (regnum != ST_REG_FIRST)
5525 fprintf (file, "%s,", reg_names[regnum]);
5528 else if (code == REG || code == SUBREG)
5530 register int regnum;
5533 regnum = REGNO (op);
5535 regnum = true_regnum (op);
5537 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5538 || (letter == 'L' && WORDS_BIG_ENDIAN)
5542 fprintf (file, "%s", reg_names[regnum]);
5545 else if (code == MEM)
5546 output_address (XEXP (op, 0));
5548 else if (code == CONST_DOUBLE
5549 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5554 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5555 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5559 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5560 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5562 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5563 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5565 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5566 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5568 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5569 fputs (reg_names[GP_REG_FIRST], file);
5571 else if (letter == 'd' || letter == 'x' || letter == 'X')
5572 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
5575 else if (letter == 'B')
5576 fputs (code == EQ ? "z" : "n", file);
5577 else if (letter == 'b')
5578 fputs (code == EQ ? "n" : "z", file);
5579 else if (letter == 'T')
5580 fputs (code == EQ ? "f" : "t", file);
5581 else if (letter == 't')
5582 fputs (code == EQ ? "t" : "f", file);
5584 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5586 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5587 print_operand (file, XEXP (op, 0), letter);
5590 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5592 fputs ("%gprel(", file);
5593 mips16_output_gp_offset (file, op);
5598 output_addr_const (file, op);
5601 /* A C compound statement to output to stdio stream STREAM the
5602 assembler syntax for an instruction operand that is a memory
5603 reference whose address is ADDR. ADDR is an RTL expression.
5605 On some machines, the syntax for a symbolic address depends on
5606 the section that the address refers to. On these machines,
5607 define the macro `ENCODE_SECTION_INFO' to store the information
5608 into the `symbol_ref', and then check for it here. */
5611 print_operand_address (file, addr)
5616 error ("PRINT_OPERAND_ADDRESS, null pointer");
5619 switch (GET_CODE (addr))
5622 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5623 abort_with_insn (addr, "Arg pointer not eliminated.");
5625 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5630 register rtx arg0 = XEXP (addr, 0);
5631 register rtx arg1 = XEXP (addr, 1);
5633 if (! mips_split_addresses)
5634 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5636 if (GET_CODE (arg0) != REG)
5637 abort_with_insn (addr,
5638 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
5640 fprintf (file, "%%lo(");
5641 print_operand_address (file, arg1);
5642 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5648 register rtx reg = 0;
5649 register rtx offset = 0;
5650 register rtx arg0 = XEXP (addr, 0);
5651 register rtx arg1 = XEXP (addr, 1);
5653 if (GET_CODE (arg0) == REG)
5657 if (GET_CODE (offset) == REG)
5658 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5661 else if (GET_CODE (arg1) == REG)
5662 reg = arg1, offset = arg0;
5663 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5665 output_addr_const (file, addr);
5669 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5671 if (! CONSTANT_P (offset))
5672 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5674 if (REGNO (reg) == ARG_POINTER_REGNUM)
5675 abort_with_insn (addr, "Arg pointer not eliminated.");
5678 && GET_CODE (offset) == CONST
5679 && mips16_gp_offset_p (offset))
5681 fputs ("%gprel(", file);
5682 mips16_output_gp_offset (file, offset);
5686 output_addr_const (file, offset);
5687 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5695 output_addr_const (file, addr);
5699 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5705 /* If optimizing for the global pointer, keep track of all of the externs, so
5706 that at the end of the file, we can emit the appropriate .extern
5707 declaration for them, before writing out the text section. We assume all
5708 names passed to us are in the permanent obstack, so they will be valid at
5709 the end of the compilation.
5711 If we have -G 0, or the extern size is unknown, or the object is in a user
5712 specified section that is not .sbss/.sdata, don't bother emitting the
5713 .externs. In the case of user specified sections this behaviour is
5714 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5717 mips_output_external (file, decl, name)
5718 FILE *file ATTRIBUTE_UNUSED;
5722 register struct extern_list *p;
5727 && TREE_CODE (decl) != FUNCTION_DECL
5728 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5729 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5730 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5731 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5733 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5734 p->next = extern_head;
5740 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5741 if (TREE_CODE (decl) == FUNCTION_DECL
5742 /* ??? Don't include alloca, since gcc will always expand it
5743 inline. If we don't do this, the C++ library fails to build. */
5744 && strcmp (name, "alloca")
5745 /* ??? Don't include __builtin_next_arg, because then gcc will not
5746 bootstrap under Irix 5.1. */
5747 && strcmp (name, "__builtin_next_arg"))
5749 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5750 p->next = extern_head;
5760 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5762 mips_output_external_libcall (file, name)
5766 register struct extern_list *p;
5768 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5769 p->next = extern_head;
5778 /* Compute a string to use as a temporary file name. */
5780 /* On MSDOS, write temp files in current dir
5781 because there's no place else we can expect to use. */
5784 #define P_tmpdir "./"
5789 mips_make_temp_file ()
5792 const char *base = getenv ("TMPDIR");
5798 if (access (P_tmpdir, R_OK | W_OK) == 0)
5802 if (access ("/usr/tmp", R_OK | W_OK) == 0)
5808 len = strlen (base);
5809 /* temp_filename is global, so we must use malloc, not alloca. */
5810 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
5811 strcpy (temp_filename, base);
5812 if (len > 0 && temp_filename[len-1] != '/')
5813 temp_filename[len++] = '/';
5815 strcpy (temp_filename + len, "ctXXXXXX");
5816 mktemp (temp_filename);
5818 stream = fopen (temp_filename, "w+");
5820 pfatal_with_name (temp_filename);
5823 /* In MSDOS, we cannot unlink the temporary file until we are finished using
5824 it. Otherwise, we delete it now, so that it will be gone even if the
5825 compiler happens to crash. */
5826 unlink (temp_filename);
5831 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5832 for .file's that start within a function. If we are smuggling stabs, try to
5833 put out a MIPS ECOFF file and a stab. */
5836 mips_output_filename (stream, name)
5840 static int first_time = 1;
5841 char ltext_label_name[100];
5847 current_function_file = name;
5848 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5849 /* This tells mips-tfile that stabs will follow. */
5850 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5851 fprintf (stream, "\t#@stabs\n");
5854 else if (write_symbols == DBX_DEBUG)
5856 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5857 fprintf (stream, "%s ", ASM_STABS_OP);
5858 output_quoted_string (stream, name);
5859 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5862 else if (name != current_function_file
5863 && strcmp (name, current_function_file) != 0)
5865 if (inside_function && !TARGET_GAS)
5867 if (!file_in_function_warning)
5869 file_in_function_warning = 1;
5870 ignore_line_number = 1;
5871 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5877 current_function_file = name;
5878 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5883 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5884 as well as a .loc, since it is possible that MIPS ECOFF might not be
5885 able to represent the location for inlines that come from a different
5889 mips_output_lineno (stream, line)
5893 if (write_symbols == DBX_DEBUG)
5896 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
5897 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5898 LOCAL_LABEL_PREFIX, sym_lineno);
5903 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5904 (ignore_line_number) ? "#" : "",
5905 num_source_filenames, line);
5907 LABEL_AFTER_LOC (stream);
5911 /* If defined, a C statement to be executed just prior to the output of
5912 assembler code for INSN, to modify the extracted operands so they will be
5915 Here the argument OPVEC is the vector containing the operands extracted
5916 from INSN, and NOPERANDS is the number of elements of the vector which
5917 contain meaningful data for this insn. The contents of this vector are
5918 what will be used to convert the insn template into assembler code, so you
5919 can change the assembler output by changing the contents of the vector.
5921 We use it to check if the current insn needs a nop in front of it because
5922 of load delays, and also to update the delay slot statistics. */
5924 /* ??? There is no real need for this function, because it never actually
5925 emits a NOP anymore. */
5928 final_prescan_insn (insn, opvec, noperands)
5930 rtx opvec[] ATTRIBUTE_UNUSED;
5931 int noperands ATTRIBUTE_UNUSED;
5933 if (dslots_number_nops > 0)
5935 rtx pattern = PATTERN (insn);
5936 int length = get_attr_length (insn);
5938 /* Do we need to emit a NOP? */
5940 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5941 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5942 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5943 || (mips_load_reg4 != 0
5944 && reg_mentioned_p (mips_load_reg4, pattern)))
5945 fputs ("\t#nop\n", asm_out_file);
5948 dslots_load_filled++;
5950 while (--dslots_number_nops > 0)
5951 fputs ("\t#nop\n", asm_out_file);
5960 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
5961 dslots_jump_total++;
5964 /* Output at beginning of assembler file.
5966 If we are optimizing to use the global pointer, create a temporary file to
5967 hold all of the text stuff, and write it out to the end. This is needed
5968 because the MIPS assembler is evidently one pass, and if it hasn't seen the
5969 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
5970 processed, it generates a two instruction sequence. */
5973 mips_asm_file_start (stream)
5976 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
5978 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5979 inside of a .set noreorder section jumps to a label outside of the .set
5980 noreorder section. Revision 2.20 just set nobopt silently rather than
5983 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5984 fprintf (stream, "\t.set\tnobopt\n");
5986 /* Generate the pseudo ops that System V.4 wants. */
5987 #ifndef ABICALLS_ASM_OP
5988 #define ABICALLS_ASM_OP ".abicalls"
5990 if (TARGET_ABICALLS)
5991 /* ??? but do not want this (or want pic0) if -non-shared? */
5992 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
5995 fprintf (stream, "\t.set\tmips16\n");
5997 /* Start a section, so that the first .popsection directive is guaranteed
5998 to have a previously defined section to pop back to. */
5999 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
6000 fprintf (stream, "\t.section\t.text\n");
6002 /* This code exists so that we can put all externs before all symbol
6003 references. This is necessary for the MIPS assembler's global pointer
6004 optimizations to work. */
6005 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
6007 asm_out_data_file = stream;
6008 asm_out_text_file = mips_make_temp_file ();
6012 asm_out_data_file = asm_out_text_file = stream;
6014 if (flag_verbose_asm)
6015 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
6017 mips_section_threshold, mips_cpu_string, mips_isa);
6020 /* If we are optimizing the global pointer, emit the text section now and any
6021 small externs which did not have .comm, etc that are needed. Also, give a
6022 warning if the data area is more than 32K and -pic because 3 instructions
6023 are needed to reference the data pointers. */
6026 mips_asm_file_end (file)
6031 struct extern_list *p;
6036 HALF_PIC_FINISH (file);
6043 for (p = extern_head; p != 0; p = p->next)
6045 name_tree = get_identifier (p->name);
6047 /* Positively ensure only one .extern for any given symbol. */
6048 if (! TREE_ASM_WRITTEN (name_tree))
6050 TREE_ASM_WRITTEN (name_tree) = 1;
6051 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6053 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6057 fputs ("\t.extern\t", file);
6058 assemble_name (file, p->name);
6059 fprintf (file, ", %d\n", p->size);
6065 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
6067 fprintf (file, "\n\t.text\n");
6068 rewind (asm_out_text_file);
6069 if (ferror (asm_out_text_file))
6070 fatal_io_error (temp_filename);
6072 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
6073 if ((int) fwrite (buffer, 1, len, file) != len)
6074 pfatal_with_name (asm_file_name);
6077 pfatal_with_name (temp_filename);
6079 if (fclose (asm_out_text_file) != 0)
6080 pfatal_with_name (temp_filename);
6083 unlink (temp_filename);
6088 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6089 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6092 mips_declare_object (stream, name, init_string, final_string, size)
6095 const char *init_string;
6096 const char *final_string;
6099 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6100 assemble_name (stream, name);
6101 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6105 tree name_tree = get_identifier (name);
6106 TREE_ASM_WRITTEN (name_tree) = 1;
6110 /* Output a double precision value to the assembler. If both the
6111 host and target are IEEE, emit the values in hex. */
6114 mips_output_double (stream, value)
6116 REAL_VALUE_TYPE value;
6118 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
6120 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
6122 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
6123 value_long[0], value, value_long[1]);
6125 fprintf (stream, "\t.double\t%.20g\n", value);
6129 /* Output a single precision value to the assembler. If both the
6130 host and target are IEEE, emit the values in hex. */
6133 mips_output_float (stream, value)
6135 REAL_VALUE_TYPE value;
6137 #ifdef REAL_VALUE_TO_TARGET_SINGLE
6139 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
6141 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
6143 fprintf (stream, "\t.float\t%.12g\n", value);
6147 /* Return the bytes needed to compute the frame pointer from the current
6150 Mips stack frames look like:
6152 Before call After call
6153 +-----------------------+ +-----------------------+
6156 | caller's temps. | | caller's temps. |
6158 +-----------------------+ +-----------------------+
6160 | arguments on stack. | | arguments on stack. |
6162 +-----------------------+ +-----------------------+
6163 | 4 words to save | | 4 words to save |
6164 | arguments passed | | arguments passed |
6165 | in registers, even | | in registers, even |
6166 SP->| if not passed. | VFP->| if not passed. |
6167 +-----------------------+ +-----------------------+
6169 | fp register save |
6171 +-----------------------+
6173 | gp register save |
6175 +-----------------------+
6179 +-----------------------+
6181 | alloca allocations |
6183 +-----------------------+
6185 | GP save for V.4 abi |
6187 +-----------------------+
6189 | arguments on stack |
6191 +-----------------------+
6193 | arguments passed |
6194 | in registers, even |
6195 low SP->| if not passed. |
6196 memory +-----------------------+
6201 compute_frame_size (size)
6202 HOST_WIDE_INT size; /* # of var. bytes allocated */
6205 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6206 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6207 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6208 HOST_WIDE_INT extra_size; /* # extra bytes */
6209 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6210 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6211 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6212 long mask; /* mask of saved gp registers */
6213 long fmask; /* mask of saved fp registers */
6214 int fp_inc; /* 1 or 2 depending on the size of fp regs */
6215 long fp_bits; /* bitmask to use for each fp register */
6221 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6222 var_size = MIPS_STACK_ALIGN (size);
6223 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6225 /* The MIPS 3.0 linker does not like functions that dynamically
6226 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6227 looks like we are trying to create a second frame pointer to the
6228 function, so allocate some stack space to make it happy. */
6230 if (args_size == 0 && current_function_calls_alloca)
6231 args_size = 4 * UNITS_PER_WORD;
6233 total_size = var_size + args_size + extra_size;
6235 /* Calculate space needed for gp registers. */
6236 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6238 /* $18 is a special case on the mips16. It may be used to call
6239 a function which returns a floating point value, but it is
6240 marked in call_used_regs. $31 is also a special case. When
6241 not using -mentry, it will be used to copy a return value
6242 into the floating point registers if the return value is
6244 if (MUST_SAVE_REGISTER (regno)
6246 && regno == GP_REG_FIRST + 18
6247 && regs_ever_live[regno])
6249 && regno == GP_REG_FIRST + 31
6250 && mips16_hard_float
6252 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6253 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6255 && (! TARGET_SINGLE_FLOAT
6256 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6259 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6260 mask |= 1L << (regno - GP_REG_FIRST);
6262 /* The entry and exit pseudo instructions can not save $17
6263 without also saving $16. */
6265 && regno == GP_REG_FIRST + 17
6266 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6268 gp_reg_size += UNITS_PER_WORD;
6274 /* Calculate space needed for fp registers. */
6275 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
6286 /* This loop must iterate over the same space as its companion in
6287 save_restore_regs. */
6288 for (regno = (FP_REG_LAST - fp_inc + 1);
6289 regno >= FP_REG_FIRST;
6292 if (regs_ever_live[regno] && !call_used_regs[regno])
6294 fp_reg_size += fp_inc * UNITS_PER_FPREG;
6295 fmask |= fp_bits << (regno - FP_REG_FIRST);
6299 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6300 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6302 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6303 for leaf routines (total_size == extra_size) to save the gp reg.
6304 The gp reg is callee saved in the 64 bit ABI, so all routines must
6305 save the gp reg. This is not a leaf routine if -p, because of the
6307 if (total_size == extra_size
6308 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6310 total_size = extra_size = 0;
6311 else if (TARGET_ABICALLS)
6313 /* Add the context-pointer to the saved registers. */
6314 gp_reg_size += UNITS_PER_WORD;
6315 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6316 total_size -= gp_reg_rounded;
6317 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6318 total_size += gp_reg_rounded;
6321 /* Add in space reserved on the stack by the callee for storing arguments
6322 passed in registers. */
6323 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6324 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6326 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6327 if (mips_entry && total_size > 0 && total_size < 32)
6330 /* Save other computed information. */
6331 current_frame_info.total_size = total_size;
6332 current_frame_info.var_size = var_size;
6333 current_frame_info.args_size = args_size;
6334 current_frame_info.extra_size = extra_size;
6335 current_frame_info.gp_reg_size = gp_reg_size;
6336 current_frame_info.fp_reg_size = fp_reg_size;
6337 current_frame_info.mask = mask;
6338 current_frame_info.fmask = fmask;
6339 current_frame_info.initialized = reload_completed;
6340 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6341 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
6345 unsigned long offset;
6347 /* When using mips_entry, the registers are always saved at the
6348 top of the stack. */
6350 offset = (args_size + extra_size + var_size
6351 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6353 offset = total_size - GET_MODE_SIZE (gpr_mode);
6355 current_frame_info.gp_sp_offset = offset;
6356 current_frame_info.gp_save_offset = offset - total_size;
6360 current_frame_info.gp_sp_offset = 0;
6361 current_frame_info.gp_save_offset = 0;
6366 unsigned long offset = (args_size + extra_size + var_size
6367 + gp_reg_rounded + fp_reg_size
6368 - fp_inc * UNITS_PER_FPREG);
6369 current_frame_info.fp_sp_offset = offset;
6370 current_frame_info.fp_save_offset = offset - total_size;
6374 current_frame_info.fp_sp_offset = 0;
6375 current_frame_info.fp_save_offset = 0;
6378 /* Ok, we're done. */
6382 /* Common code to emit the insns (or to write the instructions to a file)
6383 to save/restore registers.
6385 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6386 is not modified within save_restore_insns. */
6388 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6391 save_restore_insns (store_p, large_reg, large_offset, file)
6392 int store_p; /* true if this is prologue */
6393 rtx large_reg; /* register holding large offset constant or NULL */
6394 long large_offset; /* large constant offset value */
6395 FILE *file; /* file to write instructions instead of making RTL */
6397 long mask = current_frame_info.mask;
6398 long fmask = current_frame_info.fmask;
6401 HOST_WIDE_INT base_offset;
6402 HOST_WIDE_INT gp_offset;
6403 HOST_WIDE_INT fp_offset;
6404 HOST_WIDE_INT end_offset;
6407 if (frame_pointer_needed
6408 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6411 if (mask == 0 && fmask == 0)
6414 /* Save registers starting from high to low. The debuggers prefer at least
6415 the return register be stored at func+4, and also it allows us not to
6416 need a nop in the epilog if at least one register is reloaded in
6417 addition to return address. */
6419 /* Save GP registers if needed. */
6422 /* Pick which pointer to use as a base register. For small frames, just
6423 use the stack pointer. Otherwise, use a temporary register. Save 2
6424 cycles if the save area is near the end of a large frame, by reusing
6425 the constant created in the prologue/epilogue to adjust the stack
6428 gp_offset = current_frame_info.gp_sp_offset;
6430 = gp_offset - (current_frame_info.gp_reg_size
6431 - GET_MODE_SIZE (gpr_mode));
6433 if (gp_offset < 0 || end_offset < 0)
6434 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6435 (long) gp_offset, (long) end_offset);
6437 /* If we see a large frame in mips16 mode, we save the registers
6438 before adjusting the stack pointer, and load them afterward. */
6439 else if (TARGET_MIPS16 && large_offset > 32767)
6440 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6442 else if (gp_offset < 32768)
6443 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6445 else if (large_reg != 0
6446 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6447 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6449 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6450 base_offset = large_offset;
6453 if (Pmode == DImode)
6454 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6455 stack_pointer_rtx));
6457 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6458 stack_pointer_rtx));
6460 RTX_FRAME_RELATED_P (insn) = 1;
6463 fprintf (file, "\t%s\t%s,%s,%s\n",
6464 Pmode == DImode ? "daddu" : "addu",
6465 reg_names[MIPS_TEMP2_REGNUM],
6466 reg_names[REGNO (large_reg)],
6467 reg_names[STACK_POINTER_REGNUM]);
6472 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6473 base_offset = gp_offset;
6476 rtx gp_offset_rtx = GEN_INT (gp_offset);
6478 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6479 bit, so make sure that we don't emit anything that can be
6481 /* ??? There is no DImode ori immediate pattern, so we can only
6482 do this for 32 bit code. */
6483 if (large_int (gp_offset_rtx, GET_MODE (gp_offset_rtx))
6484 && GET_MODE (base_reg_rtx) == SImode)
6486 insn = emit_move_insn (base_reg_rtx,
6487 GEN_INT (gp_offset & 0xffff0000));
6489 RTX_FRAME_RELATED_P (insn) = 1;
6491 = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6492 GEN_INT (gp_offset & 0x0000ffff)));
6494 RTX_FRAME_RELATED_P (insn) = 1;
6498 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
6500 RTX_FRAME_RELATED_P (insn) = 1;
6503 if (Pmode == DImode)
6504 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6505 stack_pointer_rtx));
6507 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6508 stack_pointer_rtx));
6510 RTX_FRAME_RELATED_P (insn) = 1;
6514 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6515 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6516 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6517 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6518 Pmode == DImode ? "daddu" : "addu",
6519 reg_names[MIPS_TEMP2_REGNUM],
6520 reg_names[MIPS_TEMP2_REGNUM],
6521 reg_names[STACK_POINTER_REGNUM]);
6525 /* When we restore the registers in MIPS16 mode, then if we are
6526 using a frame pointer, and this is not a large frame, the
6527 current stack pointer will be offset by
6528 current_function_outgoing_args_size. Doing it this way lets
6529 us avoid offsetting the frame pointer before copying it into
6530 the stack pointer; there is no instruction to set the stack
6531 pointer to the sum of a register and a constant. */
6534 && frame_pointer_needed
6535 && large_offset <= 32767)
6536 base_offset += current_function_outgoing_args_size;
6538 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6539 if (BITSET_P (mask, regno - GP_REG_FIRST))
6545 = gen_rtx (MEM, gpr_mode,
6546 gen_rtx (PLUS, Pmode, base_reg_rtx,
6547 GEN_INT (gp_offset - base_offset)));
6549 RTX_UNCHANGING_P (mem_rtx) = 1;
6551 /* The mips16 does not have an instruction to load
6552 $31, so we load $7 instead, and work things out
6554 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6555 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6556 /* The mips16 sometimes needs to save $18. */
6557 else if (TARGET_MIPS16
6558 && regno != GP_REG_FIRST + 31
6559 && ! M16_REG_P (regno))
6562 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6565 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6566 emit_move_insn (reg_rtx,
6567 gen_rtx (REG, gpr_mode, regno));
6571 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6575 insn = emit_move_insn (mem_rtx, reg_rtx);
6576 RTX_FRAME_RELATED_P (insn) = 1;
6578 else if (!TARGET_ABICALLS
6579 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6580 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6582 emit_move_insn (reg_rtx, mem_rtx);
6584 && regno != GP_REG_FIRST + 31
6585 && ! M16_REG_P (regno))
6586 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6592 if (store_p || !TARGET_ABICALLS
6593 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6594 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6598 /* The mips16 does not have an instruction to
6599 load $31, so we load $7 instead, and work
6600 things out in the caller. */
6601 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6602 r = GP_REG_FIRST + 7;
6603 /* The mips16 sometimes needs to save $18. */
6605 && regno != GP_REG_FIRST + 31
6606 && ! M16_REG_P (regno))
6609 r = GP_REG_FIRST + 6;
6612 r = GP_REG_FIRST + 3;
6613 fprintf (file, "\tmove\t%s,%s\n",
6614 reg_names[r], reg_names[regno]);
6617 fprintf (file, "\t%s\t%s,",
6619 ? (store_p) ? "sd" : "ld"
6620 : (store_p) ? "sw" : "lw"),
6622 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6623 gp_offset - base_offset);
6624 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6627 && regno != GP_REG_FIRST + 31
6628 && ! M16_REG_P (regno))
6629 fprintf (file, "\tmove\t%s,%s\n",
6630 reg_names[regno], reg_names[r]);
6634 gp_offset -= GET_MODE_SIZE (gpr_mode);
6638 base_reg_rtx = 0, base_offset = 0;
6640 /* Save floating point registers if needed. */
6643 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
6644 int fp_size = fp_inc * UNITS_PER_FPREG;
6646 /* Pick which pointer to use as a base register. */
6647 fp_offset = current_frame_info.fp_sp_offset;
6648 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
6650 if (fp_offset < 0 || end_offset < 0)
6651 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6652 (long) fp_offset, (long) end_offset);
6654 else if (fp_offset < 32768)
6655 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6657 else if (base_reg_rtx != 0
6658 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6659 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6660 ; /* already set up for gp registers above */
6662 else if (large_reg != 0
6663 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6664 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6666 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6667 base_offset = large_offset;
6670 if (Pmode == DImode)
6671 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6672 stack_pointer_rtx));
6674 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6675 stack_pointer_rtx));
6677 RTX_FRAME_RELATED_P (insn) = 1;
6681 fprintf (file, "\t%s\t%s,%s,%s\n",
6682 Pmode == DImode ? "daddu" : "addu",
6683 reg_names[MIPS_TEMP2_REGNUM],
6684 reg_names[REGNO (large_reg)],
6685 reg_names[STACK_POINTER_REGNUM]);
6690 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6691 base_offset = fp_offset;
6694 rtx fp_offset_rtx = GEN_INT (fp_offset);
6696 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6697 bit, so make sure that we don't emit anything that can be
6699 /* ??? There is no DImode ori immediate pattern, so we can only
6700 do this for 32 bit code. */
6701 if (large_int (fp_offset_rtx, GET_MODE (fp_offset_rtx))
6702 && GET_MODE (base_reg_rtx) == SImode)
6704 insn = emit_move_insn (base_reg_rtx,
6705 GEN_INT (fp_offset & 0xffff0000));
6707 RTX_FRAME_RELATED_P (insn) = 1;
6708 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6709 GEN_INT (fp_offset & 0x0000ffff)));
6711 RTX_FRAME_RELATED_P (insn) = 1;
6715 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
6717 RTX_FRAME_RELATED_P (insn) = 1;
6721 RTX_FRAME_RELATED_P (insn) = 1;
6722 if (Pmode == DImode)
6723 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6724 stack_pointer_rtx));
6726 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6727 stack_pointer_rtx));
6729 RTX_FRAME_RELATED_P (insn) = 1;
6733 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6734 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6735 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6736 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6737 Pmode == DImode ? "daddu" : "addu",
6738 reg_names[MIPS_TEMP2_REGNUM],
6739 reg_names[MIPS_TEMP2_REGNUM],
6740 reg_names[STACK_POINTER_REGNUM]);
6744 /* This loop must iterate over the same space as its companion in
6745 compute_frame_size. */
6746 for (regno = (FP_REG_LAST - fp_inc + 1);
6747 regno >= FP_REG_FIRST;
6749 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6753 enum machine_mode sz
6754 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6755 rtx reg_rtx = gen_rtx (REG, sz, regno);
6756 rtx mem_rtx = gen_rtx (MEM, sz,
6757 gen_rtx (PLUS, Pmode, base_reg_rtx,
6760 RTX_UNCHANGING_P (mem_rtx) = 1;
6764 insn = emit_move_insn (mem_rtx, reg_rtx);
6765 RTX_FRAME_RELATED_P (insn) = 1;
6768 emit_move_insn (reg_rtx, mem_rtx);
6772 fprintf (file, "\t%s\t%s,",
6773 (TARGET_SINGLE_FLOAT
6774 ? (store_p ? "s.s" : "l.s")
6775 : (store_p ? "s.d" : "l.d")),
6777 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6778 fp_offset - base_offset);
6779 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6782 fp_offset -= fp_size;
6787 /* Set up the stack and frame (if desired) for the function. */
6790 function_prologue (file, size)
6792 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6794 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6797 long tsize = current_frame_info.total_size;
6799 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6801 #ifdef SDB_DEBUGGING_INFO
6802 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6803 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6806 /* In mips16 mode, we may need to generate a 32 bit to handle
6807 floating point arguments. The linker will arrange for any 32 bit
6808 functions to call this stub, which will then jump to the 16 bit
6810 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6811 && current_function_args_info.fp_code != 0)
6812 build_mips16_function_stub (file);
6814 inside_function = 1;
6816 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6817 /* Get the function name the same way that toplev.c does before calling
6818 assemble_start_function. This is needed so that the name used here
6819 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6820 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6822 if (!flag_inhibit_size_directive)
6824 fputs ("\t.ent\t", file);
6825 assemble_name (file, fnname);
6829 assemble_name (file, fnname);
6830 fputs (":\n", file);
6833 if (!flag_inhibit_size_directive)
6835 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6837 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6838 (reg_names[(frame_pointer_needed)
6839 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6840 ((frame_pointer_needed && TARGET_MIPS16)
6841 ? (tsize - current_function_outgoing_args_size)
6843 reg_names[31 + GP_REG_FIRST],
6844 current_frame_info.var_size,
6845 current_frame_info.num_gp,
6846 current_frame_info.num_fp,
6847 current_function_outgoing_args_size,
6848 current_frame_info.extra_size);
6850 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6851 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6852 current_frame_info.mask,
6853 current_frame_info.gp_save_offset,
6854 current_frame_info.fmask,
6855 current_frame_info.fp_save_offset);
6858 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6859 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6862 if (mips_entry && ! mips_can_use_return_insn ())
6864 int save16 = BITSET_P (current_frame_info.mask, 16);
6865 int save17 = BITSET_P (current_frame_info.mask, 17);
6866 int save31 = BITSET_P (current_frame_info.mask, 31);
6870 /* Look through the initial insns to see if any of them store
6871 the function parameters into the incoming parameter storage
6872 area. If they do, we delete the insn, and save the register
6873 using the entry pseudo-instruction instead. We don't try to
6874 look past a label, jump, or call. */
6875 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6877 rtx note, set, src, dest, base, offset;
6880 if (GET_CODE (insn) == CODE_LABEL
6881 || GET_CODE (insn) == JUMP_INSN
6882 || GET_CODE (insn) == CALL_INSN)
6884 if (GET_CODE (insn) != INSN)
6886 set = PATTERN (insn);
6887 if (GET_CODE (set) != SET)
6890 /* An insn storing a function parameter will still have a
6891 REG_EQUIV note on it mentioning the argument pointer. */
6892 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6893 if (note == NULL_RTX)
6895 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6898 src = SET_SRC (set);
6899 if (GET_CODE (src) != REG
6900 || REGNO (src) < GP_REG_FIRST + 4
6901 || REGNO (src) > GP_REG_FIRST + 7)
6904 dest = SET_DEST (set);
6905 if (GET_CODE (dest) != MEM)
6907 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
6909 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
6910 && REGNO (src) < GP_REG_FIRST + 7)
6914 offset = const0_rtx;
6915 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6916 if (GET_CODE (base) != REG
6917 || GET_CODE (offset) != CONST_INT)
6919 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
6920 && (unsigned HOST_WIDE_INT) INTVAL (offset)
6921 == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6923 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
6924 && ((unsigned HOST_WIDE_INT) INTVAL (offset)
6926 + (REGNO (src) - 4) * UNITS_PER_WORD
6927 - current_function_outgoing_args_size)))
6932 /* This insn stores a parameter onto the stack, in the same
6933 location where the entry pseudo-instruction will put it.
6934 Delete the insn, and arrange to tell the entry
6935 instruction to save the register. */
6936 PUT_CODE (insn, NOTE);
6937 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6938 NOTE_SOURCE_FILE (insn) = 0;
6940 hireg = (REGNO (src)
6941 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6943 if (hireg > savearg)
6947 /* If this is a varargs function, we need to save all the
6948 registers onto the stack anyhow. */
6949 if (current_function_stdarg || current_function_varargs)
6950 savearg = GP_REG_FIRST + 7;
6952 fprintf (file, "\tentry\t");
6955 if (savearg == GP_REG_FIRST + 4)
6956 fprintf (file, "%s", reg_names[savearg]);
6958 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6959 reg_names[savearg]);
6961 if (save16 || save17)
6964 fprintf (file, ",");
6965 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6967 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6971 if (savearg > 0 || save16 || save17)
6972 fprintf (file, ",");
6973 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6975 fprintf (file, "\n");
6978 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
6980 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
6982 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6983 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
6986 fprintf (file, "\t%s\t%s,%s,%ld\n",
6987 (Pmode == DImode ? "dsubu" : "subu"),
6988 sp_str, sp_str, tsize);
6989 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
6992 if (dwarf2out_do_frame ())
6993 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
6997 /* Expand the prologue into a bunch of separate insns. */
7000 mips_expand_prologue ()
7003 HOST_WIDE_INT tsize;
7005 int last_arg_is_vararg_marker = 0;
7006 tree fndecl = current_function_decl;
7007 tree fntype = TREE_TYPE (fndecl);
7008 tree fnargs = DECL_ARGUMENTS (fndecl);
7013 CUMULATIVE_ARGS args_so_far;
7014 rtx reg_18_save = NULL_RTX;
7015 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7016 && (! mips_entry || mips_can_use_return_insn ());
7018 /* If struct value address is treated as the first argument, make it so. */
7019 if (aggregate_value_p (DECL_RESULT (fndecl))
7020 && ! current_function_returns_pcc_struct
7021 && struct_value_incoming_rtx == 0)
7023 tree type = build_pointer_type (fntype);
7024 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7026 DECL_ARG_TYPE (function_result_decl) = type;
7027 TREE_CHAIN (function_result_decl) = fnargs;
7028 fnargs = function_result_decl;
7031 /* For arguments passed in registers, find the register number
7032 of the first argument in the variable part of the argument list,
7033 otherwise GP_ARG_LAST+1. Note also if the last argument is
7034 the varargs special argument, and treat it as part of the
7037 This is only needed if store_args_on_stack is true. */
7039 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7040 regno = GP_ARG_FIRST;
7042 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7044 tree passed_type = DECL_ARG_TYPE (cur_arg);
7045 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7048 if (TREE_ADDRESSABLE (passed_type))
7050 passed_type = build_pointer_type (passed_type);
7051 passed_mode = Pmode;
7054 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7056 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7057 next_arg = TREE_CHAIN (cur_arg);
7059 if (entry_parm && store_args_on_stack)
7062 && DECL_NAME (cur_arg)
7063 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7064 "__builtin_va_alist"))
7065 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7068 last_arg_is_vararg_marker = 1;
7075 if (GET_CODE (entry_parm) != REG)
7078 /* passed in a register, so will get homed automatically */
7079 if (GET_MODE (entry_parm) == BLKmode)
7080 words = (int_size_in_bytes (passed_type) + 3) / 4;
7082 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
7084 regno = REGNO (entry_parm) + words - 1;
7089 regno = GP_ARG_LAST+1;
7094 /* In order to pass small structures by value in registers compatibly with
7095 the MIPS compiler, we need to shift the value into the high part of the
7096 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7097 adjustments to be made as the next_arg_reg variable, so we split up the
7098 insns, and emit them separately. */
7100 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7101 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7103 rtvec adjust = XVEC (next_arg_reg, 0);
7104 int num = GET_NUM_ELEM (adjust);
7106 for (i = 0; i < num; i++)
7108 rtx pattern = RTVEC_ELT (adjust, i);
7109 if (GET_CODE (pattern) != SET
7110 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7111 abort_with_insn (pattern, "Insn is not a shift");
7113 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7114 emit_insn (pattern);
7118 tsize = compute_frame_size (get_frame_size ());
7120 /* If this function is a varargs function, store any registers that
7121 would normally hold arguments ($4 - $7) on the stack. */
7122 if (store_args_on_stack
7123 && ((TYPE_ARG_TYPES (fntype) != 0
7124 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7126 || last_arg_is_vararg_marker))
7128 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7129 rtx ptr = stack_pointer_rtx;
7131 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7132 if (TARGET_ABICALLS)
7135 for (; regno <= GP_ARG_LAST; regno++)
7138 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7139 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7140 gen_rtx (REG, gpr_mode, regno));
7142 offset += GET_MODE_SIZE (gpr_mode);
7146 /* If we are using the entry pseudo instruction, it will
7147 automatically subtract 32 from the stack pointer, so we don't
7148 need to. The entry pseudo instruction is emitted by
7149 function_prologue. */
7150 if (mips_entry && ! mips_can_use_return_insn ())
7152 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7156 /* If we are using a frame pointer with a small stack frame,
7157 we need to initialize it here since it won't be done
7159 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7161 rtx incr = GEN_INT (current_function_outgoing_args_size);
7162 if (Pmode == DImode)
7163 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7167 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7171 else if (Pmode == DImode)
7172 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7173 stack_pointer_rtx));
7175 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7176 stack_pointer_rtx));
7178 RTX_FRAME_RELATED_P (insn) = 1;
7181 /* We may need to save $18, if it is used to call a function
7182 which may return a floating point value. Set up a sequence
7183 of instructions to do so. Later on we emit them at the right
7185 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
7187 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7188 long gp_offset, base_offset;
7190 gp_offset = current_frame_info.gp_sp_offset;
7191 if (BITSET_P (current_frame_info.mask, 16))
7192 gp_offset -= UNITS_PER_WORD;
7193 if (BITSET_P (current_frame_info.mask, 17))
7194 gp_offset -= UNITS_PER_WORD;
7195 if (BITSET_P (current_frame_info.mask, 31))
7196 gp_offset -= UNITS_PER_WORD;
7198 base_offset = tsize;
7202 emit_move_insn (reg_rtx,
7203 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7204 emit_move_insn (gen_rtx (MEM, gpr_mode,
7205 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7209 reg_18_save = gen_sequence ();
7218 if (reg_18_save != NULL_RTX)
7219 emit_insn (reg_18_save);
7225 rtx tsize_rtx = GEN_INT (tsize);
7227 /* If we are doing svr4-abi, sp move is done by
7228 function_prologue. In mips16 mode with a large frame, we
7229 save the registers before adjusting the stack. */
7230 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7231 && (!TARGET_MIPS16 || tsize <= 32767))
7237 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7239 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
7240 bit, so make sure that we don't emit anything that can be
7242 /* ??? There is no DImode ori immediate pattern, so we can only
7243 do this for 32 bit code. */
7244 if (large_int (tsize_rtx, GET_MODE (tsize_rtx))
7245 && GET_MODE (tmp_rtx) == SImode)
7247 insn = emit_move_insn (tmp_rtx,
7248 GEN_INT (tsize & 0xffff0000));
7249 RTX_FRAME_RELATED_P (insn) = 1;
7250 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
7251 GEN_INT (tsize & 0x0000ffff)));
7252 RTX_FRAME_RELATED_P (insn) = 1;
7256 insn = emit_move_insn (tmp_rtx, tsize_rtx);
7257 RTX_FRAME_RELATED_P (insn) = 1;
7260 tsize_rtx = tmp_rtx;
7263 if (Pmode == DImode)
7264 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7267 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7270 RTX_FRAME_RELATED_P (insn) = 1;
7274 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
7275 else if (reg_18_save != NULL_RTX)
7276 emit_insn (reg_18_save);
7278 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7284 if (!frame_pointer_needed)
7287 reg_rtx = gen_rtx (REG, Pmode, 3);
7288 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7289 emit_move_insn (reg_rtx, tsize_rtx);
7290 if (Pmode == DImode)
7291 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7292 hard_frame_pointer_rtx,
7295 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7296 hard_frame_pointer_rtx,
7298 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7301 if (frame_pointer_needed)
7305 /* On the mips16, we encourage the use of unextended
7306 instructions when using the frame pointer by pointing the
7307 frame pointer ahead of the argument space allocated on
7309 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7313 /* In this case, we have already copied the stack
7314 pointer into the frame pointer, above. We need only
7315 adjust for the outgoing argument size. */
7316 if (current_function_outgoing_args_size != 0)
7318 rtx incr = GEN_INT (current_function_outgoing_args_size);
7319 if (Pmode == DImode)
7320 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7321 hard_frame_pointer_rtx,
7324 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7325 hard_frame_pointer_rtx,
7329 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7331 rtx incr = GEN_INT (current_function_outgoing_args_size);
7332 if (Pmode == DImode)
7333 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7337 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7341 else if (Pmode == DImode)
7342 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7343 stack_pointer_rtx));
7345 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7346 stack_pointer_rtx));
7349 RTX_FRAME_RELATED_P (insn) = 1;
7352 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7353 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7354 gen_rtx_REG (DImode, 25)));
7357 /* If we are profiling, make sure no instructions are scheduled before
7358 the call to mcount. */
7360 if (profile_flag || profile_block_flag)
7361 emit_insn (gen_blockage ());
7364 /* Do any necessary cleanup after a function to restore stack, frame,
7367 #define RA_MASK 0x80000000L /* 1 << 31 */
7368 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7371 function_epilogue (file, size)
7372 FILE *file ATTRIBUTE_UNUSED;
7373 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7377 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7378 /* Get the function name the same way that toplev.c does before calling
7379 assemble_start_function. This is needed so that the name used here
7380 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7381 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7383 if (!flag_inhibit_size_directive)
7385 fputs ("\t.end\t", file);
7386 assemble_name (file, fnname);
7393 int num_gp_regs = current_frame_info.gp_reg_size / 4;
7394 int num_fp_regs = current_frame_info.fp_reg_size / 8;
7395 int num_regs = num_gp_regs + num_fp_regs;
7396 const char *name = fnname;
7401 dslots_load_total += num_regs;
7404 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7405 name, frame_pointer_needed ? 'y' : 'n',
7406 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7407 current_function_calls_alloca ? 'y' : 'n',
7408 current_function_calls_setjmp ? 'y' : 'n',
7409 current_frame_info.total_size,
7410 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7411 dslots_load_total, dslots_load_filled,
7412 dslots_jump_total, dslots_jump_filled,
7413 num_refs[0], num_refs[1], num_refs[2]);
7415 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7418 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7419 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7422 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7425 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7426 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7429 fputc ('\n', stderr);
7432 /* Reset state info for each function. */
7433 inside_function = 0;
7434 ignore_line_number = 0;
7435 dslots_load_total = 0;
7436 dslots_jump_total = 0;
7437 dslots_load_filled = 0;
7438 dslots_jump_filled = 0;
7444 current_frame_info = zero_frame_info;
7446 while (string_constants != NULL)
7448 struct string_constant *next;
7450 next = string_constants->next;
7451 free (string_constants);
7452 string_constants = next;
7455 /* Restore the output file if optimizing the GP (optimizing the GP causes
7456 the text to be diverted to a tempfile, so that data decls come before
7457 references to the data). */
7459 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
7460 asm_out_file = asm_out_data_file;
7463 /* Expand the epilogue into a bunch of separate insns. */
7466 mips_expand_epilogue ()
7468 HOST_WIDE_INT tsize = current_frame_info.total_size;
7469 rtx tsize_rtx = GEN_INT (tsize);
7470 rtx tmp_rtx = (rtx)0;
7472 if (mips_can_use_return_insn ())
7474 emit_insn (gen_return ());
7478 if (mips_entry && ! mips_can_use_return_insn ())
7481 if (tsize > 32767 && ! TARGET_MIPS16)
7483 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7484 emit_move_insn (tmp_rtx, tsize_rtx);
7485 tsize_rtx = tmp_rtx;
7490 long orig_tsize = tsize;
7492 if (frame_pointer_needed)
7494 emit_insn (gen_blockage ());
7496 /* On the mips16, the frame pointer is offset from the stack
7497 pointer by current_function_outgoing_args_size. We
7498 account for that by changing tsize. Note that this can
7499 actually make tsize negative. */
7502 tsize -= current_function_outgoing_args_size;
7504 /* If we have a large frame, it's easier to add to $17
7505 than to $sp, since the mips16 has no instruction to
7506 add a register to $sp. */
7507 if (orig_tsize > 32767)
7509 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7511 emit_move_insn (g6_rtx, GEN_INT (tsize));
7512 if (Pmode == DImode)
7513 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7514 hard_frame_pointer_rtx,
7517 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7518 hard_frame_pointer_rtx,
7523 if (tsize && tsize != orig_tsize)
7524 tsize_rtx = GEN_INT (tsize);
7527 if (Pmode == DImode)
7528 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7530 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7533 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7534 are going to restore it, then we must emit a blockage insn to
7535 prevent the scheduler from moving the restore out of the epilogue. */
7536 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7537 && (current_frame_info.mask
7538 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7539 emit_insn (gen_blockage ());
7541 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
7543 /* In mips16 mode with a large frame, we adjust the stack
7544 pointer before restoring the registers. In this case, we
7545 should always be using a frame pointer, so everything should
7546 have been handled above. */
7547 if (tsize > 32767 && TARGET_MIPS16)
7550 emit_insn (gen_blockage ());
7551 if (Pmode == DImode && tsize != 0)
7552 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7554 else if (tsize != 0)
7555 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7559 /* The mips16 loads the return address into $7, not $31. */
7560 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7561 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7562 GP_REG_FIRST + 7)));
7564 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7565 GP_REG_FIRST + 31)));
7568 /* Return nonzero if this function is known to have a null epilogue.
7569 This allows the optimizer to omit jumps to jumps if no stack
7573 mips_can_use_return_insn ()
7575 if (! reload_completed)
7578 if (regs_ever_live[31] || profile_flag)
7581 /* In mips16 mode, a function which returns a floating point value
7582 needs to arrange to copy the return value into the floating point
7585 && mips16_hard_float
7586 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7587 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7589 && (! TARGET_SINGLE_FLOAT
7590 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7594 if (current_frame_info.initialized)
7595 return current_frame_info.total_size == 0;
7597 return compute_frame_size (get_frame_size ()) == 0;
7600 /* Returns non-zero if X contains a SYMBOL_REF. */
7603 symbolic_expression_p (x)
7606 if (GET_CODE (x) == SYMBOL_REF)
7609 if (GET_CODE (x) == CONST)
7610 return symbolic_expression_p (XEXP (x, 0));
7612 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7613 return symbolic_expression_p (XEXP (x, 0));
7615 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7616 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7617 return (symbolic_expression_p (XEXP (x, 0))
7618 || symbolic_expression_p (XEXP (x, 1)));
7623 /* Choose the section to use for the constant rtx expression X that has
7627 mips_select_rtx_section (mode, x)
7628 enum machine_mode mode;
7629 rtx x ATTRIBUTE_UNUSED;
7633 /* In mips16 mode, the constant table always goes in the same section
7634 as the function, so that constants can be loaded using PC relative
7636 function_section (current_function_decl);
7638 else if (TARGET_EMBEDDED_DATA)
7640 /* For embedded applications, always put constants in read-only data,
7641 in order to reduce RAM usage. */
7642 READONLY_DATA_SECTION ();
7646 /* For hosted applications, always put constants in small data if
7647 possible, as this gives the best performance. */
7649 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7650 && mips_section_threshold > 0)
7651 SMALL_DATA_SECTION ();
7652 else if (flag_pic && symbolic_expression_p (x))
7653 /* Any expression involving a SYMBOL_REF might need a run-time
7654 relocation. (The symbol might be defined in a shared
7655 library loaded at an unexpected base address.) So, we must
7656 put such expressions in the data segment (which is
7657 writable), rather than the text segment (which is
7661 READONLY_DATA_SECTION ();
7665 /* Choose the section to use for DECL. RELOC is true if its value contains
7666 any relocatable expression.
7668 Some of the logic used here needs to be replicated in
7669 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7670 are done correctly. Specifically, at least all symbols assigned
7671 here to rom (.text and/or .rodata) must not be referenced via
7672 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7674 If you need to make a change here, you probably should check
7675 ENCODE_SECTION_INFO to see if it needs a similar change. */
7678 mips_select_section (decl, reloc)
7682 int size = int_size_in_bytes (TREE_TYPE (decl));
7684 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7685 && TREE_CODE (decl) == STRING_CST
7686 && !flag_writable_strings)
7687 /* For embedded position independent code, put constant strings in the
7688 text section, because the data section is limited to 64K in size.
7689 For mips16 code, put strings in the text section so that a PC
7690 relative load instruction can be used to get their address. */
7692 else if (TARGET_EMBEDDED_DATA)
7694 /* For embedded applications, always put an object in read-only data
7695 if possible, in order to reduce RAM usage. */
7697 if (((TREE_CODE (decl) == VAR_DECL
7698 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7699 && DECL_INITIAL (decl)
7700 && (DECL_INITIAL (decl) == error_mark_node
7701 || TREE_CONSTANT (DECL_INITIAL (decl))))
7702 /* Deal with calls from output_constant_def_contents. */
7703 || (TREE_CODE (decl) != VAR_DECL
7704 && (TREE_CODE (decl) != STRING_CST
7705 || !flag_writable_strings)))
7706 && ! (flag_pic && reloc))
7707 READONLY_DATA_SECTION ();
7708 else if (size > 0 && size <= mips_section_threshold)
7709 SMALL_DATA_SECTION ();
7715 /* For hosted applications, always put an object in small data if
7716 possible, as this gives the best performance. */
7718 if (size > 0 && size <= mips_section_threshold)
7719 SMALL_DATA_SECTION ();
7720 else if (((TREE_CODE (decl) == VAR_DECL
7721 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7722 && DECL_INITIAL (decl)
7723 && (DECL_INITIAL (decl) == error_mark_node
7724 || TREE_CONSTANT (DECL_INITIAL (decl))))
7725 /* Deal with calls from output_constant_def_contents. */
7726 || (TREE_CODE (decl) != VAR_DECL
7727 && (TREE_CODE (decl) != STRING_CST
7728 || !flag_writable_strings)))
7729 && ! (flag_pic && reloc))
7730 READONLY_DATA_SECTION ();
7736 #ifdef MIPS_ABI_DEFAULT
7738 /* Support functions for the 64 bit ABI. */
7740 /* Return register to use for a function return value with VALTYPE for function
7744 mips_function_value (valtype, func)
7746 tree func ATTRIBUTE_UNUSED;
7748 int reg = GP_RETURN;
7749 enum machine_mode mode = TYPE_MODE (valtype);
7750 enum mode_class mclass = GET_MODE_CLASS (mode);
7751 int unsignedp = TREE_UNSIGNED (valtype);
7753 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7754 just as PROMOTE_MODE does. */
7755 mode = promote_mode (valtype, mode, &unsignedp, 1);
7757 /* ??? How should we return complex float? */
7758 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
7760 if (TARGET_SINGLE_FLOAT
7761 && (mclass == MODE_FLOAT
7762 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7768 else if (TREE_CODE (valtype) == RECORD_TYPE
7769 && mips_abi != ABI_32
7770 && mips_abi != ABI_O64
7771 && mips_abi != ABI_EABI)
7773 /* A struct with only one or two floating point fields is returned in
7774 the floating point registers. */
7775 tree field, fields[2];
7778 for (i = 0, field = TYPE_FIELDS (valtype); field;
7779 field = TREE_CHAIN (field))
7781 if (TREE_CODE (field) != FIELD_DECL)
7784 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7787 fields[i++] = field;
7790 /* Must check i, so that we reject structures with no elements. */
7795 /* The structure has DImode, but we don't allow DImode values
7796 in FP registers, so we use a PARALLEL even though it isn't
7797 strictly necessary. */
7798 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7800 return gen_rtx_PARALLEL
7803 gen_rtx_EXPR_LIST (VOIDmode,
7804 gen_rtx_REG (field_mode,
7811 enum machine_mode first_mode
7812 = TYPE_MODE (TREE_TYPE (fields[0]));
7813 enum machine_mode second_mode
7814 = TYPE_MODE (TREE_TYPE (fields[1]));
7815 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
7816 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
7818 return gen_rtx_PARALLEL
7821 gen_rtx_EXPR_LIST (VOIDmode,
7822 gen_rtx_REG (first_mode,
7824 GEN_INT (first_offset)),
7825 gen_rtx_EXPR_LIST (VOIDmode,
7826 gen_rtx_REG (second_mode,
7828 GEN_INT (second_offset))));
7833 return gen_rtx_REG (mode, reg);
7837 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7838 nonzero when an argument must be passed by reference. */
7841 function_arg_pass_by_reference (cum, mode, type, named)
7842 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
7843 enum machine_mode mode;
7845 int named ATTRIBUTE_UNUSED;
7849 /* We must pass by reference if we would be both passing in registers
7850 and the stack. This is because any subsequent partial arg would be
7851 handled incorrectly in this case.
7853 ??? This is really a kludge. We should either fix GCC so that such
7854 a situation causes an abort and then do something in the MIPS port
7855 to prevent it, or add code to function.c to properly handle the case. */
7856 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
7857 here hopefully is not relevant to mips_va_arg. */
7858 if (cum && MUST_PASS_IN_STACK (mode, type))
7860 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
7861 get double copies of any offsets generated for small structs
7862 passed in registers. */
7863 CUMULATIVE_ARGS temp;
7865 if (FUNCTION_ARG (temp, mode, type, named) != 0)
7869 /* Otherwise, we only do this if EABI is selected. */
7870 if (mips_abi != ABI_EABI)
7873 /* ??? How should SCmode be handled? */
7874 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7877 size = int_size_in_bytes (type);
7878 return size == -1 || size > UNITS_PER_WORD;
7881 /* This function returns the register class required for a secondary
7882 register when copying between one of the registers in CLASS, and X,
7883 using MODE. If IN_P is nonzero, the copy is going from X to the
7884 register, otherwise the register is the source. A return value of
7885 NO_REGS means that no secondary register is required. */
7888 mips_secondary_reload_class (class, mode, x, in_p)
7889 enum reg_class class;
7890 enum machine_mode mode;
7894 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7898 if (GET_CODE (x) == SIGN_EXTEND)
7904 /* We may be called with reg_renumber NULL from regclass.
7905 ??? This is probably a bug. */
7907 regno = true_regnum (x);
7910 while (GET_CODE (x) == SUBREG)
7912 off += SUBREG_WORD (x);
7916 if (GET_CODE (x) == REG)
7917 regno = REGNO (x) + off;
7921 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7922 regno = true_regnum (x);
7924 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7926 /* We always require a general register when copying anything to
7927 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7928 to a general register, or when copying from register 0. */
7929 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
7932 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7933 ? NO_REGS : gr_regs);
7934 else if (regno == HILO_REGNUM)
7937 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7938 ? NO_REGS : gr_regs);
7940 /* Copying from HI or LO to anywhere other than a general register
7941 requires a general register. */
7942 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7944 if (TARGET_MIPS16 && in_p)
7946 /* We can't really copy to HI or LO at all in mips16 mode. */
7949 return gp_reg_p ? NO_REGS : gr_regs;
7951 if (MD_REG_P (regno))
7953 if (TARGET_MIPS16 && ! in_p)
7955 /* We can't really copy to HI or LO at all in mips16 mode. */
7958 return class == gr_regs ? NO_REGS : gr_regs;
7961 /* We can only copy a value to a condition code register from a
7962 floating point register, and even then we require a scratch
7963 floating point register. We can only copy a value out of a
7964 condition code register into a general register. */
7965 if (class == ST_REGS)
7969 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
7971 if (ST_REG_P (regno))
7975 return class == GR_REGS ? NO_REGS : GR_REGS;
7978 /* In mips16 mode, going between memory and anything but M16_REGS
7979 requires an M16_REG. */
7982 if (class != M16_REGS && class != M16_NA_REGS)
7990 /* The stack pointer isn't a valid operand to an add instruction,
7991 so we need to load it into M16_REGS first. This can happen as
7992 a result of register elimination and form_sum converting
7993 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
7994 need an extra register if the dest is the same as the other
7995 register. In that case, we can't fix the problem by loading SP
7996 into the dest first. */
7997 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
7998 && GET_CODE (XEXP (x, 1)) == REG
7999 && (XEXP (x, 0) == stack_pointer_rtx
8000 || XEXP (x, 1) == stack_pointer_rtx))
8001 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8003 if (class == M16_REGS || class == M16_NA_REGS)
8012 /* For each mips16 function which refers to GP relative symbols, we
8013 use a pseudo register, initialized at the start of the function, to
8014 hold the $gp value. */
8017 mips16_gp_pseudo_reg ()
8019 if (mips16_gp_pseudo_rtx == NULL_RTX)
8024 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8025 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
8027 /* We want to initialize this to a value which gcc will believe
8029 const_gp = gen_rtx (CONST, Pmode,
8030 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8033 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
8034 insn = gen_sequence ();
8037 push_topmost_sequence ();
8038 /* We need to emit the initialization after the FUNCTION_BEG
8039 note, so that it will be integrated. */
8040 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8041 if (GET_CODE (scan) == NOTE
8042 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8044 if (scan == NULL_RTX)
8045 scan = get_insns ();
8046 insn = emit_insn_after (insn, scan);
8047 pop_topmost_sequence ();
8050 return mips16_gp_pseudo_rtx;
8053 /* Return an RTX which represents the signed 16 bit offset from the
8054 $gp register for the given symbol. This is only used on the
8058 mips16_gp_offset (sym)
8063 if (GET_CODE (sym) != SYMBOL_REF
8064 || ! SYMBOL_REF_FLAG (sym))
8067 /* We use a special identifier to represent the value of the gp
8069 gp = get_identifier ("__mips16_gp_value");
8071 return gen_rtx (CONST, Pmode,
8072 gen_rtx (MINUS, Pmode, sym,
8073 gen_rtx (SYMBOL_REF, Pmode,
8074 IDENTIFIER_POINTER (gp))));
8077 /* Return nonzero if the given RTX represents a signed 16 bit offset
8078 from the $gp register. */
8081 mips16_gp_offset_p (x)
8084 if (GET_CODE (x) == CONST)
8087 /* It's OK to add a small integer value to a gp offset. */
8088 if (GET_CODE (x) == PLUS)
8090 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8091 && SMALL_INT (XEXP (x, 1)))
8092 return mips16_gp_offset_p (XEXP (x, 0));
8093 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8094 && SMALL_INT (XEXP (x, 0)))
8095 return mips16_gp_offset_p (XEXP (x, 1));
8099 /* Make sure it is in the form SYM - __mips16_gp_value. */
8100 return (GET_CODE (x) == MINUS
8101 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8102 && SYMBOL_REF_FLAG (XEXP (x, 0))
8103 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8104 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8107 /* Output a GP offset. We don't want to print the subtraction of
8108 __mips16_gp_value; it is implicitly represented by the %gprel which
8109 should have been printed by the caller. */
8112 mips16_output_gp_offset (file, x)
8116 if (GET_CODE (x) == CONST)
8119 if (GET_CODE (x) == PLUS)
8121 mips16_output_gp_offset (file, XEXP (x, 0));
8123 mips16_output_gp_offset (file, XEXP (x, 1));
8127 if (GET_CODE (x) == MINUS
8128 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8129 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8131 mips16_output_gp_offset (file, XEXP (x, 0));
8135 output_addr_const (file, x);
8138 /* Return nonzero if a constant should not be output until after the
8139 function. This is true of most string constants, so that we can
8140 use a more efficient PC relative reference. However, a static
8141 inline function may never call assemble_function_end to write out
8142 the constant pool, so don't try to postpone the constant in that
8145 ??? It's really a bug that a static inline function can put stuff
8146 in the constant pool even if the function itself is not output.
8148 We record which string constants we've seen, so that we know which
8149 ones might use the more efficient reference. */
8152 mips16_constant_after_function_p (x)
8155 if (TREE_CODE (x) == STRING_CST
8156 && ! flag_writable_strings
8157 && current_function_decl != 0
8158 && ! DECL_DEFER_OUTPUT (current_function_decl)
8159 && ! (DECL_INLINE (current_function_decl)
8160 && ((! TREE_PUBLIC (current_function_decl)
8161 && ! TREE_ADDRESSABLE (current_function_decl)
8162 && ! flag_keep_inline_functions)
8163 || DECL_EXTERNAL (current_function_decl))))
8165 struct string_constant *n;
8167 n = (struct string_constant *) xmalloc (sizeof *n);
8168 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8169 n->next = string_constants;
8170 string_constants = n;
8178 /* Validate a constant for the mips16. This rejects general symbolic
8179 addresses, which must be loaded from memory. If ADDR is nonzero,
8180 this should reject anything which is not a legal address. If
8181 ADDEND is nonzero, this is being added to something else. */
8184 mips16_constant (x, mode, addr, addend)
8186 enum machine_mode mode;
8190 while (GET_CODE (x) == CONST)
8193 switch (GET_CODE (x))
8199 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8200 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8203 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8205 if (CONSTANT_POOL_ADDRESS_P (x))
8208 /* If we aren't looking for a memory address, we can accept a GP
8209 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8210 knows how to handle this. We can always accept a string
8211 constant, which is the other case in which SYMBOL_REF_FLAG
8215 && SYMBOL_REF_FLAG (x)
8216 && mode == (enum machine_mode) Pmode)
8219 /* We can accept a string constant, which will have
8220 SYMBOL_REF_FLAG set but must be recognized by name to
8221 distinguish from a GP accessible symbol. The name of a
8222 string constant will have been generated by
8223 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8224 if (SYMBOL_REF_FLAG (x))
8226 const char *name = XSTR (x, 0);
8228 return (name[0] == '*'
8229 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8230 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8236 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8241 if (addr && ! addend)
8243 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8246 /* We need to treat $gp as a legitimate constant, because
8247 mips16_gp_pseudo_reg assumes that. */
8248 return REGNO (x) == GP_REG_FIRST + 28;
8252 /* Write out code to move floating point arguments in or out of
8253 general registers. Output the instructions to FILE. FP_CODE is
8254 the code describing which arguments are present (see the comment at
8255 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8256 we are copying from the floating point registers. */
8259 mips16_fp_args (file, fp_code, from_fp_p)
8268 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8269 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8276 gparg = GP_ARG_FIRST;
8277 fparg = FP_ARG_FIRST;
8278 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8282 if ((fparg & 1) != 0)
8284 fprintf (file, "\t%s\t%s,%s\n", s,
8285 reg_names[gparg], reg_names[fparg]);
8287 else if ((f & 3) == 2)
8290 fprintf (file, "\td%s\t%s,%s\n", s,
8291 reg_names[gparg], reg_names[fparg]);
8294 if ((fparg & 1) != 0)
8296 if (TARGET_BIG_ENDIAN)
8297 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8298 reg_names[gparg], reg_names[fparg + 1], s,
8299 reg_names[gparg + 1], reg_names[fparg]);
8301 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8302 reg_names[gparg], reg_names[fparg], s,
8303 reg_names[gparg + 1], reg_names[fparg + 1]);
8316 /* Build a mips16 function stub. This is used for functions which
8317 take aruments in the floating point registers. It is 32 bit code
8318 that moves the floating point args into the general registers, and
8319 then jumps to the 16 bit code. */
8322 build_mips16_function_stub (file)
8326 char *secname, *stubname;
8327 tree stubid, stubdecl;
8331 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8332 secname = (char *) alloca (strlen (fnname) + 20);
8333 sprintf (secname, ".mips16.fn.%s", fnname);
8334 stubname = (char *) alloca (strlen (fnname) + 20);
8335 sprintf (stubname, "__fn_stub_%s", fnname);
8336 stubid = get_identifier (stubname);
8337 stubdecl = build_decl (FUNCTION_DECL, stubid,
8338 build_function_type (void_type_node, NULL_TREE));
8339 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8341 fprintf (file, "\t# Stub function for %s (", current_function_name);
8343 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8345 fprintf (file, "%s%s",
8346 need_comma ? ", " : "",
8347 (f & 3) == 1 ? "float" : "double");
8350 fprintf (file, ")\n");
8352 fprintf (file, "\t.set\tnomips16\n");
8353 function_section (stubdecl);
8354 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8356 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8357 within a .ent, and we can not emit another .ent. */
8358 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8359 fputs ("\t.ent\t", file);
8360 assemble_name (file, stubname);
8364 assemble_name (file, stubname);
8365 fputs (":\n", file);
8367 /* We don't want the assembler to insert any nops here. */
8368 fprintf (file, "\t.set\tnoreorder\n");
8370 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8372 fprintf (asm_out_file, "\t.set\tnoat\n");
8373 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8374 assemble_name (file, fnname);
8375 fprintf (file, "\n");
8376 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8377 fprintf (asm_out_file, "\t.set\tat\n");
8379 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8380 with one of the mfc1 instructions, because the result is not
8381 available for one instruction, so if the very first instruction
8382 in the function refers to the register, it will see the wrong
8384 fprintf (file, "\tnop\n");
8386 fprintf (file, "\t.set\treorder\n");
8388 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8389 fputs ("\t.end\t", file);
8390 assemble_name (file, stubname);
8394 fprintf (file, "\t.set\tmips16\n");
8396 function_section (current_function_decl);
8399 /* We keep a list of functions for which we have already built stubs
8400 in build_mips16_call_stub. */
8404 struct mips16_stub *next;
8409 static struct mips16_stub *mips16_stubs;
8411 /* Build a call stub for a mips16 call. A stub is needed if we are
8412 passing any floating point values which should go into the floating
8413 point registers. If we are, and the call turns out to be to a 32
8414 bit function, the stub will be used to move the values into the
8415 floating point registers before calling the 32 bit function. The
8416 linker will magically adjust the function call to either the 16 bit
8417 function or the 32 bit stub, depending upon where the function call
8418 is actually defined.
8420 Similarly, we need a stub if the return value might come back in a
8421 floating point register.
8423 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8424 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8425 is the code built by function_arg. This function returns a nonzero
8426 value if it builds the call instruction itself. */
8429 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8438 char *secname, *stubname;
8439 struct mips16_stub *l;
8440 tree stubid, stubdecl;
8444 /* We don't need to do anything if we aren't in mips16 mode, or if
8445 we were invoked with the -msoft-float option. */
8446 if (! TARGET_MIPS16 || ! mips16_hard_float)
8449 /* Figure out whether the value might come back in a floating point
8451 fpret = (retval != 0
8452 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8453 && (! TARGET_SINGLE_FLOAT
8454 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8456 /* We don't need to do anything if there were no floating point
8457 arguments and the value will not be returned in a floating point
8459 if (fp_code == 0 && ! fpret)
8462 if (GET_CODE (fnmem) != MEM)
8464 fn = XEXP (fnmem, 0);
8466 /* We don't need to do anything if this is a call to a special
8467 mips16 support function. */
8468 if (GET_CODE (fn) == SYMBOL_REF
8469 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8472 /* This code will only work for o32 and o64 abis. The other ABI's
8473 require more sophisticated support. */
8474 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8477 /* We can only handle SFmode and DFmode floating point return
8479 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8482 /* If we're calling via a function pointer, then we must always call
8483 via a stub. There are magic stubs provided in libgcc.a for each
8484 of the required cases. Each of them expects the function address
8485 to arrive in register $2. */
8487 if (GET_CODE (fn) != SYMBOL_REF)
8491 rtx stub_fn, stub_mem, insn;
8493 /* ??? If this code is modified to support other ABI's, we need
8494 to handle PARALLEL return values here. */
8496 sprintf (buf, "__mips16_call_stub_%s%d",
8498 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8501 id = get_identifier (buf);
8502 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8503 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8505 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8507 if (retval == NULL_RTX)
8508 insn = gen_call_internal0 (stub_mem, arg_size,
8509 gen_rtx (REG, SImode,
8510 GP_REG_FIRST + 31));
8512 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8513 gen_rtx (REG, SImode,
8514 GP_REG_FIRST + 31));
8515 insn = emit_call_insn (insn);
8517 /* Put the register usage information on the CALL. */
8518 if (GET_CODE (insn) != CALL_INSN)
8520 CALL_INSN_FUNCTION_USAGE (insn) =
8521 gen_rtx (EXPR_LIST, VOIDmode,
8522 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8523 CALL_INSN_FUNCTION_USAGE (insn));
8525 /* If we are handling a floating point return value, we need to
8526 save $18 in the function prologue. Putting a note on the
8527 call will mean that regs_ever_live[$18] will be true if the
8528 call is not eliminated, and we can check that in the prologue
8531 CALL_INSN_FUNCTION_USAGE (insn) =
8532 gen_rtx (EXPR_LIST, VOIDmode,
8533 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8534 CALL_INSN_FUNCTION_USAGE (insn));
8536 /* Return 1 to tell the caller that we've generated the call
8541 /* We know the function we are going to call. If we have already
8542 built a stub, we don't need to do anything further. */
8544 fnname = XSTR (fn, 0);
8545 for (l = mips16_stubs; l != NULL; l = l->next)
8546 if (strcmp (l->name, fnname) == 0)
8551 /* Build a special purpose stub. When the linker sees a
8552 function call in mips16 code, it will check where the target
8553 is defined. If the target is a 32 bit call, the linker will
8554 search for the section defined here. It can tell which
8555 symbol this section is associated with by looking at the
8556 relocation information (the name is unreliable, since this
8557 might be a static function). If such a section is found, the
8558 linker will redirect the call to the start of the magic
8561 If the function does not return a floating point value, the
8562 special stub section is named
8565 If the function does return a floating point value, the stub
8567 .mips16.call.fp.FNNAME
8570 secname = (char *) alloca (strlen (fnname) + 40);
8571 sprintf (secname, ".mips16.call.%s%s",
8574 stubname = (char *) alloca (strlen (fnname) + 20);
8575 sprintf (stubname, "__call_stub_%s%s",
8578 stubid = get_identifier (stubname);
8579 stubdecl = build_decl (FUNCTION_DECL, stubid,
8580 build_function_type (void_type_node, NULL_TREE));
8581 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8583 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8585 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8589 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8591 fprintf (asm_out_file, "%s%s",
8592 need_comma ? ", " : "",
8593 (f & 3) == 1 ? "float" : "double");
8596 fprintf (asm_out_file, ")\n");
8598 fprintf (asm_out_file, "\t.set\tnomips16\n");
8599 assemble_start_function (stubdecl, stubname);
8601 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8602 fputs ("\t.ent\t", asm_out_file);
8603 assemble_name (asm_out_file, stubname);
8604 fputs ("\n", asm_out_file);
8606 assemble_name (asm_out_file, stubname);
8607 fputs (":\n", asm_out_file);
8610 /* We build the stub code by hand. That's the only way we can
8611 do it, since we can't generate 32 bit code during a 16 bit
8614 /* We don't want the assembler to insert any nops here. */
8615 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8617 mips16_fp_args (asm_out_file, fp_code, 0);
8621 fprintf (asm_out_file, "\t.set\tnoat\n");
8622 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8624 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8625 fprintf (asm_out_file, "\t.set\tat\n");
8626 /* Unfortunately, we can't fill the jump delay slot. We
8627 can't fill with one of the mtc1 instructions, because the
8628 result is not available for one instruction, so if the
8629 very first instruction in the function refers to the
8630 register, it will see the wrong value. */
8631 fprintf (asm_out_file, "\tnop\n");
8635 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8636 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8637 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8638 /* As above, we can't fill the delay slot. */
8639 fprintf (asm_out_file, "\tnop\n");
8640 if (GET_MODE (retval) == SFmode)
8641 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8642 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8645 if (TARGET_BIG_ENDIAN)
8647 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8648 reg_names[GP_REG_FIRST + 2],
8649 reg_names[FP_REG_FIRST + 1]);
8650 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8651 reg_names[GP_REG_FIRST + 3],
8652 reg_names[FP_REG_FIRST + 0]);
8656 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8657 reg_names[GP_REG_FIRST + 2],
8658 reg_names[FP_REG_FIRST + 0]);
8659 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8660 reg_names[GP_REG_FIRST + 3],
8661 reg_names[FP_REG_FIRST + 1]);
8664 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8665 /* As above, we can't fill the delay slot. */
8666 fprintf (asm_out_file, "\tnop\n");
8669 fprintf (asm_out_file, "\t.set\treorder\n");
8671 #ifdef ASM_DECLARE_FUNCTION_SIZE
8672 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8675 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8676 fputs ("\t.end\t", asm_out_file);
8677 assemble_name (asm_out_file, stubname);
8678 fputs ("\n", asm_out_file);
8681 fprintf (asm_out_file, "\t.set\tmips16\n");
8683 /* Record this stub. */
8684 l = (struct mips16_stub *) xmalloc (sizeof *l);
8685 l->name = xstrdup (fnname);
8687 l->next = mips16_stubs;
8691 /* If we expect a floating point return value, but we've built a
8692 stub which does not expect one, then we're in trouble. We can't
8693 use the existing stub, because it won't handle the floating point
8694 value. We can't build a new stub, because the linker won't know
8695 which stub to use for the various calls in this object file.
8696 Fortunately, this case is illegal, since it means that a function
8697 was declared in two different ways in a single compilation. */
8698 if (fpret && ! l->fpret)
8699 error ("can not handle inconsistent calls to `%s'", fnname);
8701 /* If we are calling a stub which handles a floating point return
8702 value, we need to arrange to save $18 in the prologue. We do
8703 this by marking the function call as using the register. The
8704 prologue will later see that it is used, and emit code to save
8711 if (retval == NULL_RTX)
8712 insn = gen_call_internal0 (fnmem, arg_size,
8713 gen_rtx (REG, SImode,
8714 GP_REG_FIRST + 31));
8716 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8717 gen_rtx (REG, SImode,
8718 GP_REG_FIRST + 31));
8719 insn = emit_call_insn (insn);
8721 if (GET_CODE (insn) != CALL_INSN)
8724 CALL_INSN_FUNCTION_USAGE (insn) =
8725 gen_rtx (EXPR_LIST, VOIDmode,
8726 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8727 CALL_INSN_FUNCTION_USAGE (insn));
8729 /* Return 1 to tell the caller that we've generated the call
8734 /* Return 0 to let the caller generate the call insn. */
8738 /* This function looks through the code for a function, and tries to
8739 optimize the usage of the $gp register. We arrange to copy $gp
8740 into a pseudo-register, and then let gcc's normal reload handling
8741 deal with the pseudo-register. Unfortunately, if reload choose to
8742 put the pseudo-register into a call-clobbered register, it will
8743 emit saves and restores for that register around any function
8744 calls. We don't need the saves, and it's faster to copy $gp than
8745 to do an actual restore. ??? This still means that we waste a
8748 This is an optimization, and the code which gcc has actually
8749 generated is correct, so we do not need to catch all cases. */
8752 mips16_optimize_gp (first)
8755 rtx gpcopy, slot, insn;
8757 /* Look through the instructions. Set GPCOPY to the register which
8758 holds a copy of $gp. Set SLOT to the stack slot where it is
8759 saved. If we find an instruction which sets GPCOPY to anything
8760 other than $gp or SLOT, then we can't use it. If we find an
8761 instruction which sets SLOT to anything other than GPCOPY, we
8766 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8770 if (! INSN_P (insn))
8773 set = PATTERN (insn);
8775 /* We know that all references to memory will be inside a SET,
8776 because there is no other way to access memory on the mips16.
8777 We don't have to worry about a PARALLEL here, because the
8778 mips.md file will never generate them for memory references. */
8779 if (GET_CODE (set) != SET)
8782 if (gpcopy == NULL_RTX
8783 && GET_CODE (SET_SRC (set)) == CONST
8784 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8785 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8786 && GET_CODE (SET_DEST (set)) == REG
8787 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8788 gpcopy = SET_DEST (set);
8789 else if (slot == NULL_RTX
8790 && gpcopy != NULL_RTX
8791 && GET_CODE (SET_DEST (set)) == MEM
8792 && GET_CODE (SET_SRC (set)) == REG
8793 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8794 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8798 offset = const0_rtx;
8799 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8800 if (GET_CODE (base) == REG
8801 && (REGNO (base) == STACK_POINTER_REGNUM
8802 || REGNO (base) == FRAME_POINTER_REGNUM))
8803 slot = SET_DEST (set);
8805 else if (gpcopy != NULL_RTX
8806 && (GET_CODE (SET_DEST (set)) == REG
8807 || GET_CODE (SET_DEST (set)) == SUBREG)
8808 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8809 && (GET_CODE (SET_DEST (set)) != REG
8810 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8811 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
8812 || ((GET_CODE (SET_SRC (set)) != CONST
8813 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8814 || (REGNO (XEXP (SET_SRC (set), 0))
8815 != GP_REG_FIRST + 28))
8816 && ! rtx_equal_p (SET_SRC (set), slot))))
8818 else if (slot != NULL_RTX
8819 && GET_CODE (SET_DEST (set)) == MEM
8820 && rtx_equal_p (SET_DEST (set), slot)
8821 && (GET_CODE (SET_SRC (set)) != REG
8822 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8826 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8827 different optimization. Any time we find a copy of $28 into a
8828 register, followed by an add of a symbol_ref to that register, we
8829 convert it to load the value from the constant table instead.
8830 The copy and add will take six bytes, just as the load and
8831 constant table entry will take six bytes. However, it is
8832 possible that the constant table entry will be shared.
8834 This could be a peephole optimization, but I don't know if the
8835 peephole code can call force_const_mem.
8837 Using the same register for the copy of $28 and the add of the
8838 symbol_ref is actually pretty likely, since the add instruction
8839 requires the destination and the first addend to be the same
8842 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8846 /* This optimization is only reasonable if the constant table
8847 entries are only 4 bytes. */
8848 if (Pmode != SImode)
8851 for (insn = first; insn != NULL_RTX; insn = next)
8858 next = NEXT_INSN (next);
8860 while (next != NULL_RTX
8861 && (GET_CODE (next) == NOTE
8862 || (GET_CODE (next) == INSN
8863 && (GET_CODE (PATTERN (next)) == USE
8864 || GET_CODE (PATTERN (next)) == CLOBBER))));
8866 if (next == NULL_RTX)
8869 if (! INSN_P (insn))
8872 if (! INSN_P (next))
8875 set1 = PATTERN (insn);
8876 if (GET_CODE (set1) != SET)
8878 set2 = PATTERN (next);
8879 if (GET_CODE (set2) != SET)
8882 if (GET_CODE (SET_DEST (set1)) == REG
8883 && GET_CODE (SET_SRC (set1)) == CONST
8884 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8885 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8886 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8887 && GET_CODE (SET_SRC (set2)) == PLUS
8888 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8889 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8890 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8894 /* We've found a case we can change to load from the
8897 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8898 if (GET_CODE (sym) != SYMBOL_REF)
8900 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8901 force_const_mem (Pmode, sym)),
8904 PUT_CODE (insn, NOTE);
8905 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8906 NOTE_SOURCE_FILE (insn) = 0;
8908 PUT_CODE (next, NOTE);
8909 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8910 NOTE_SOURCE_FILE (next) = 0;
8917 /* We can safely remove all assignments to SLOT from GPCOPY, and
8918 replace all assignments from SLOT to GPCOPY with assignments from
8921 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8925 if (! INSN_P (insn))
8928 set = PATTERN (insn);
8929 if (GET_CODE (set) != SET
8930 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
8933 if (GET_CODE (SET_DEST (set)) == MEM
8934 && rtx_equal_p (SET_DEST (set), slot)
8935 && GET_CODE (SET_SRC (set)) == REG
8936 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8938 PUT_CODE (insn, NOTE);
8939 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8940 NOTE_SOURCE_FILE (insn) = 0;
8942 else if (GET_CODE (SET_DEST (set)) == REG
8943 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8944 && GET_CODE (SET_SRC (set)) == MEM
8945 && rtx_equal_p (SET_SRC (set), slot))
8947 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
8948 gen_rtx (CONST, Pmode,
8949 gen_rtx (REG, Pmode,
8950 GP_REG_FIRST + 28))),
8952 PUT_CODE (insn, NOTE);
8953 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8954 NOTE_SOURCE_FILE (insn) = 0;
8959 /* We keep a list of constants we which we have to add to internal
8960 constant tables in the middle of large functions. */
8964 struct constant *next;
8967 enum machine_mode mode;
8970 /* Add a constant to the list in *PCONSTANTS. */
8973 add_constant (pconstants, val, mode)
8974 struct constant **pconstants;
8976 enum machine_mode mode;
8980 for (c = *pconstants; c != NULL; c = c->next)
8981 if (mode == c->mode && rtx_equal_p (val, c->value))
8984 c = (struct constant *) xmalloc (sizeof *c);
8987 c->label = gen_label_rtx ();
8988 c->next = *pconstants;
8993 /* Dump out the constants in CONSTANTS after INSN. */
8996 dump_constants (constants, insn)
8997 struct constant *constants;
9008 struct constant *next;
9010 switch (GET_MODE_SIZE (c->mode))
9017 insn = emit_insn_after (gen_align_2 (), insn);
9022 insn = emit_insn_after (gen_align_4 (), insn);
9027 insn = emit_insn_after (gen_align_8 (), insn);
9032 insn = emit_label_after (c->label, insn);
9037 r = gen_consttable_qi (c->value);
9040 r = gen_consttable_hi (c->value);
9043 r = gen_consttable_si (c->value);
9046 r = gen_consttable_sf (c->value);
9049 r = gen_consttable_di (c->value);
9052 r = gen_consttable_df (c->value);
9058 insn = emit_insn_after (r, insn);
9065 emit_barrier_after (insn);
9068 /* Find the symbol in an address expression. */
9071 mips_find_symbol (addr)
9074 if (GET_CODE (addr) == MEM)
9075 addr = XEXP (addr, 0);
9076 while (GET_CODE (addr) == CONST)
9077 addr = XEXP (addr, 0);
9078 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9080 if (GET_CODE (addr) == PLUS)
9084 l1 = mips_find_symbol (XEXP (addr, 0));
9085 l2 = mips_find_symbol (XEXP (addr, 1));
9086 if (l1 != NULL_RTX && l2 == NULL_RTX)
9088 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9094 /* Exported to toplev.c.
9096 Do a final pass over the function, just before delayed branch
9100 machine_dependent_reorg (first)
9103 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9105 struct constant *constants;
9107 if (! TARGET_MIPS16)
9110 /* If $gp is used, try to remove stores, and replace loads with
9113 mips16_optimize_gp (first);
9115 /* Scan the function looking for PC relative loads which may be out
9116 of range. All such loads will either be from the constant table,
9117 or be getting the address of a constant string. If the size of
9118 the function plus the size of the constant table is less than
9119 0x8000, then all loads are in range. */
9122 for (insn = first; insn; insn = NEXT_INSN (insn))
9124 insns_len += get_attr_length (insn);
9126 /* ??? We put switch tables in .text, but we don't define
9127 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9128 compute their lengths correctly. */
9129 if (GET_CODE (insn) == JUMP_INSN)
9133 body = PATTERN (insn);
9134 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9135 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9136 * GET_MODE_SIZE (GET_MODE (body)));
9137 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9141 /* Store the original value of insns_len in current_frame_info, so
9142 that simple_memory_operand can look at it. */
9143 current_frame_info.insns_len = insns_len;
9145 pool_size = get_pool_size ();
9146 if (insns_len + pool_size + mips_string_length < 0x8000)
9149 /* Loop over the insns and figure out what the maximum internal pool
9151 max_internal_pool_size = 0;
9152 for (insn = first; insn; insn = NEXT_INSN (insn))
9154 if (GET_CODE (insn) == INSN
9155 && GET_CODE (PATTERN (insn)) == SET)
9159 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9160 if (src == NULL_RTX)
9162 if (CONSTANT_POOL_ADDRESS_P (src))
9163 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9164 else if (SYMBOL_REF_FLAG (src))
9165 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9171 first_constant_ref = -1;
9173 for (insn = first; insn; insn = NEXT_INSN (insn))
9175 if (GET_CODE (insn) == INSN
9176 && GET_CODE (PATTERN (insn)) == SET)
9179 enum machine_mode mode = VOIDmode;
9182 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9183 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9185 /* ??? This is very conservative, which means that we
9186 will generate too many copies of the constant table.
9187 The only solution would seem to be some form of
9189 if (((insns_len - addr)
9190 + max_internal_pool_size
9191 + get_pool_offset (src))
9194 val = get_pool_constant (src);
9195 mode = get_pool_mode (src);
9197 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9199 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9201 /* Including all of mips_string_length is conservative,
9202 and so is including all of max_internal_pool_size. */
9203 if (((insns_len - addr)
9204 + max_internal_pool_size
9206 + mips_string_length)
9212 max_internal_pool_size -= Pmode;
9215 if (val != NULL_RTX)
9219 /* This PC relative load is out of range. ??? In the
9220 case of a string constant, we are only guessing that
9221 it is range, since we don't know the offset of a
9222 particular string constant. */
9224 lab = add_constant (&constants, val, mode);
9225 newsrc = gen_rtx (MEM, mode,
9226 gen_rtx (LABEL_REF, VOIDmode, lab));
9227 RTX_UNCHANGING_P (newsrc) = 1;
9228 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9229 SET_DEST (PATTERN (insn)),
9231 INSN_CODE (insn) = -1;
9233 if (first_constant_ref < 0)
9234 first_constant_ref = addr;
9238 addr += get_attr_length (insn);
9240 /* ??? We put switch tables in .text, but we don't define
9241 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9242 compute their lengths correctly. */
9243 if (GET_CODE (insn) == JUMP_INSN)
9247 body = PATTERN (insn);
9248 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9249 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9250 * GET_MODE_SIZE (GET_MODE (body)));
9251 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9254 if (GET_CODE (insn) == BARRIER)
9256 /* Output any constants we have accumulated. Note that we
9257 don't need to change ADDR, since its only use is
9258 subtraction from INSNS_LEN, and both would be changed by
9260 ??? If the instructions up to the next barrier reuse a
9261 constant, it would often be better to continue
9263 if (constants != NULL)
9264 dump_constants (constants, insn);
9266 first_constant_ref = -1;
9269 if (constants != NULL
9270 && (NEXT_INSN (insn) == NULL
9271 || (first_constant_ref >= 0
9272 && (((addr - first_constant_ref)
9273 + 2 /* for alignment */
9274 + 2 /* for a short jump insn */
9278 /* If we haven't had a barrier within 0x8000 bytes of a
9279 constant reference or we are at the end of the function,
9280 emit a barrier now. */
9282 rtx label, jump, barrier;
9284 label = gen_label_rtx ();
9285 jump = emit_jump_insn_after (gen_jump (label), insn);
9286 JUMP_LABEL (jump) = label;
9287 LABEL_NUSES (label) = 1;
9288 barrier = emit_barrier_after (jump);
9289 emit_label_after (label, barrier);
9290 first_constant_ref = -1;
9294 /* ??? If we output all references to a constant in internal
9295 constants table, we don't need to output the constant in the real
9296 constant table, but we have no way to prevent that. */
9299 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9301 extend_operator (x, mode)
9303 enum machine_mode mode ATTRIBUTE_UNUSED;
9305 enum rtx_code code = GET_CODE (x);
9306 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9309 /* Accept any operator that can be used to shift the high half of the
9310 input value to the lower half, suitable for truncation. The
9311 remainder (the lower half of the input, and the upper half of the
9312 output) will be discarded. */
9314 highpart_shift_operator (x, mode)
9316 enum machine_mode mode ATTRIBUTE_UNUSED;
9318 enum rtx_code code = GET_CODE (x);
9319 return (code == LSHIFTRT
9325 /* Return the length of INSN. LENGTH is the initial length computed by
9326 attributes in the machine-description file. */
9329 mips_adjust_insn_length (insn, length)
9333 /* A unconditional jump has an unfilled delay slot if it is not part
9334 of a sequence. A conditional jump normally has a delay slot, but
9335 does not on MIPS16. */
9336 if (simplejump_p (insn)
9337 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9338 || GET_CODE (insn) == CALL_INSN)))
9341 /* All MIPS16 instructions are a measly two bytes. */
9348 /* Output assembly instructions to peform a conditional branch.
9350 INSN is the branch instruction. OPERANDS[0] is the condition.
9351 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9352 of the first operand to the condition. If TWO_OPERANDS_P is
9353 non-zero the comparison takes two operands; OPERANDS[3] will be the
9356 If INVERTED_P is non-zero we are to branch if the condition does
9357 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9359 LENGTH is the length (in bytes) of the sequence we are to generate.
9360 That tells us whether to generate a simple conditional branch, or a
9361 reversed conditional branch around a `jr' instruction. */
9363 mips_output_conditional_branch (insn,
9376 static char buffer[200];
9377 /* The kind of comparison we are doing. */
9378 enum rtx_code code = GET_CODE (operands[0]);
9379 /* Non-zero if the opcode for the comparison needs a `z' indicating
9380 that it is a comparision against zero. */
9382 /* A string to use in the assembly output to represent the first
9384 const char *op1 = "%z2";
9385 /* A string to use in the assembly output to represent the second
9386 operand. Use the hard-wired zero register if there's no second
9388 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9389 /* The operand-printing string for the comparison. */
9390 const char *comp = (float_p ? "%F0" : "%C0");
9391 /* The operand-printing string for the inverted comparison. */
9392 const char *inverted_comp = (float_p ? "%W0" : "%N0");
9394 /* The MIPS processors (for levels of the ISA at least two), have
9395 "likely" variants of each branch instruction. These instructions
9396 annul the instruction in the delay slot if the branch is not
9398 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9400 if (!two_operands_p)
9402 /* To compute whether than A > B, for example, we normally
9403 subtract B from A and then look at the sign bit. But, if we
9404 are doing an unsigned comparison, and B is zero, we don't
9405 have to do the subtraction. Instead, we can just check to
9406 see if A is non-zero. Thus, we change the CODE here to
9407 reflect the simpler comparison operation. */
9419 /* A condition which will always be true. */
9425 /* A condition which will always be false. */
9431 /* Not a special case. */
9436 /* Relative comparisons are always done against zero. But
9437 equality comparisons are done between two operands, and therefore
9438 do not require a `z' in the assembly language output. */
9439 need_z_p = (!float_p && code != EQ && code != NE);
9440 /* For comparisons against zero, the zero is not provided
9445 /* Begin by terminating the buffer. That way we can always use
9446 strcat to add to it. */
9453 /* Just a simple conditional branch. */
9455 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9456 inverted_p ? inverted_comp : comp);
9458 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9459 inverted_p ? inverted_comp : comp,
9460 need_z_p ? "z" : "",
9468 /* Generate a reversed conditional branch around ` j'
9480 Because we have to jump four bytes *past* the following
9481 instruction if this branch was annulled, we can't just use
9482 a label, as in the picture above; there's no way to put the
9483 label after the next instruction, as the assembler does not
9484 accept `.L+4' as the target of a branch. (We can't just
9485 wait until the next instruction is output; it might be a
9486 macro and take up more than four bytes. Once again, we see
9487 why we want to eliminate macros.)
9489 If the branch is annulled, we jump four more bytes that we
9490 would otherwise; that way we skip the annulled instruction
9491 in the delay slot. */
9494 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
9497 strcpy (buffer, "%(%<");
9498 c = strchr (buffer, '\0');
9499 /* Generate the reversed comparision. This takes four
9502 sprintf (c, "%%*b%s\t%%Z2%s",
9503 inverted_p ? comp : inverted_comp,
9506 sprintf (c, "%%*b%s%s\t%s%s,%s",
9507 inverted_p ? comp : inverted_comp,
9508 need_z_p ? "z" : "",
9512 strcat (c, "\n\tnop\n\tj\t%1");
9514 /* The delay slot was unfilled. Since we're inside
9515 .noreorder, the assembler will not fill in the NOP for
9516 us, so we must do it ourselves. */
9517 strcat (buffer, "\n\tnop");
9518 strcat (buffer, "%>%)");
9522 /* We do not currently use this code. It handles jumps to
9523 arbitrary locations, using `jr', even across a 256MB boundary.
9524 We could add a -mhuge switch, and then use this code instead of
9525 the `j' alternative above when -mhuge was used. */
9530 /* Generate a reversed conditional branch around a `jr'
9544 Not pretty, but allows a conditional branch anywhere in the
9545 32-bit address space. If the original branch is annulled,
9546 then the instruction in the delay slot should be executed
9547 only if the branch is taken. The la instruction is really
9548 a macro which will usually take eight bytes, but sometimes
9549 takes only four, if the instruction to which we're jumping
9550 gets its own entry in the global pointer table, which will
9551 happen if its a case label. The assembler will then
9552 generate only a four-byte sequence, rather than eight, and
9553 there seems to be no way to tell it not to. Thus, we can't
9554 just use a `.+x' addressing form; we don't know what value
9557 So, we resort to using the explicit relocation syntax
9558 available in the assembler and do:
9560 lw $at,%got_page(target)($gp)
9561 daddiu $at,$at,%got_ofst(target)
9563 That way, this always takes up eight bytes, and we can use
9564 the `.+x' form. Of course, these explicit machinations
9565 with relocation will not work with old assemblers. Then
9566 again, neither do out-of-range branches, so we haven't lost
9569 /* The target of the reversed branch. */
9571 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9572 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9573 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9576 strcpy (buffer, "%(%<%[");
9577 c = strchr (buffer, '\0');
9578 /* Generate the reversed comparision. This takes four
9581 sprintf (c, "%%*b%s\t%%Z2%s",
9582 inverted_p ? comp : inverted_comp,
9585 sprintf (c, "%%*b%s%s\t%s%s,%s",
9586 inverted_p ? comp : inverted_comp,
9587 need_z_p ? "z" : "",
9591 c = strchr (buffer, '\0');
9592 /* Generate the load-address, and jump. This takes twelve
9593 bytes, for a total of 16. */
9595 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9602 /* The delay slot was unfilled. Since we're inside
9603 .noreorder, the assembler will not fill in the NOP for
9604 us, so we must do it ourselves. */
9605 strcat (buffer, "\n\tnop");
9606 strcat (buffer, "%]%>%)");
9619 /* Called to register all of our global variables with the garbage
9623 mips_add_gc_roots ()
9625 ggc_add_rtx_root (&mips_load_reg, 1);
9626 ggc_add_rtx_root (&mips_load_reg2, 1);
9627 ggc_add_rtx_root (&mips_load_reg3, 1);
9628 ggc_add_rtx_root (&mips_load_reg4, 1);
9629 ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9630 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9631 ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);