1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
140 A signed 16-bit constant address.
143 A constant symbolic address. */
144 enum mips_address_type {
151 /* Enumerates the setting of the -mr10k-cache-barrier option. */
152 enum mips_r10k_cache_barrier_setting {
153 R10K_CACHE_BARRIER_NONE,
154 R10K_CACHE_BARRIER_STORE,
155 R10K_CACHE_BARRIER_LOAD_STORE
158 /* Macros to create an enumeration identifier for a function prototype. */
159 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
160 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
161 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
162 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
164 /* Classifies the prototype of a built-in function. */
165 enum mips_function_type {
166 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
167 #include "config/mips/mips-ftypes.def"
168 #undef DEF_MIPS_FTYPE
172 /* Specifies how a built-in function should be converted into rtl. */
173 enum mips_builtin_type {
174 /* The function corresponds directly to an .md pattern. The return
175 value is mapped to operand 0 and the arguments are mapped to
176 operands 1 and above. */
179 /* The function corresponds directly to an .md pattern. There is no return
180 value and the arguments are mapped to operands 0 and above. */
181 MIPS_BUILTIN_DIRECT_NO_TARGET,
183 /* The function corresponds to a comparison instruction followed by
184 a mips_cond_move_tf_ps pattern. The first two arguments are the
185 values to compare and the second two arguments are the vector
186 operands for the movt.ps or movf.ps instruction (in assembly order). */
190 /* The function corresponds to a V2SF comparison instruction. Operand 0
191 of this instruction is the result of the comparison, which has mode
192 CCV2 or CCV4. The function arguments are mapped to operands 1 and
193 above. The function's return value is an SImode boolean that is
194 true under the following conditions:
196 MIPS_BUILTIN_CMP_ANY: one of the registers is true
197 MIPS_BUILTIN_CMP_ALL: all of the registers are true
198 MIPS_BUILTIN_CMP_LOWER: the first register is true
199 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
200 MIPS_BUILTIN_CMP_ANY,
201 MIPS_BUILTIN_CMP_ALL,
202 MIPS_BUILTIN_CMP_UPPER,
203 MIPS_BUILTIN_CMP_LOWER,
205 /* As above, but the instruction only sets a single $fcc register. */
206 MIPS_BUILTIN_CMP_SINGLE,
208 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
209 MIPS_BUILTIN_BPOSGE32
212 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
213 #define MIPS_FP_CONDITIONS(MACRO) \
231 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
232 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
233 enum mips_fp_condition {
234 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
237 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
238 #define STRINGIFY(X) #X
239 static const char *const mips_fp_conditions[] = {
240 MIPS_FP_CONDITIONS (STRINGIFY)
243 /* Information about a function's frame layout. */
244 struct mips_frame_info GTY(()) {
245 /* The size of the frame in bytes. */
246 HOST_WIDE_INT total_size;
248 /* The number of bytes allocated to variables. */
249 HOST_WIDE_INT var_size;
251 /* The number of bytes allocated to outgoing function arguments. */
252 HOST_WIDE_INT args_size;
254 /* The number of bytes allocated to the .cprestore slot, or 0 if there
256 HOST_WIDE_INT cprestore_size;
258 /* Bit X is set if the function saves or restores GPR X. */
261 /* Likewise FPR X. */
264 /* The number of GPRs and FPRs saved. */
268 /* The offset of the topmost GPR and FPR save slots from the top of
269 the frame, or zero if no such slots are needed. */
270 HOST_WIDE_INT gp_save_offset;
271 HOST_WIDE_INT fp_save_offset;
273 /* Likewise, but giving offsets from the bottom of the frame. */
274 HOST_WIDE_INT gp_sp_offset;
275 HOST_WIDE_INT fp_sp_offset;
277 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
278 HOST_WIDE_INT arg_pointer_offset;
280 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
281 HOST_WIDE_INT hard_frame_pointer_offset;
284 struct machine_function GTY(()) {
285 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
286 rtx mips16_gp_pseudo_rtx;
288 /* The number of extra stack bytes taken up by register varargs.
289 This area is allocated by the callee at the very top of the frame. */
292 /* The current frame information, calculated by mips_compute_frame_info. */
293 struct mips_frame_info frame;
295 /* The register to use as the function's global pointer, or INVALID_REGNUM
296 if the function doesn't need one. */
297 unsigned int global_pointer;
299 /* True if mips_adjust_insn_length should ignore an instruction's
301 bool ignore_hazard_length_p;
303 /* True if the whole function is suitable for .set noreorder and
305 bool all_noreorder_p;
307 /* True if the function is known to have an instruction that needs $gp. */
310 /* True if we have emitted an instruction to initialize
311 mips16_gp_pseudo_rtx. */
312 bool initialized_mips16_gp_pseudo_p;
315 /* Information about a single argument. */
316 struct mips_arg_info {
317 /* True if the argument is passed in a floating-point register, or
318 would have been if we hadn't run out of registers. */
321 /* The number of words passed in registers, rounded up. */
322 unsigned int reg_words;
324 /* For EABI, the offset of the first register from GP_ARG_FIRST or
325 FP_ARG_FIRST. For other ABIs, the offset of the first register from
326 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
327 comment for details).
329 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
331 unsigned int reg_offset;
333 /* The number of words that must be passed on the stack, rounded up. */
334 unsigned int stack_words;
336 /* The offset from the start of the stack overflow area of the argument's
337 first stack word. Only meaningful when STACK_WORDS is nonzero. */
338 unsigned int stack_offset;
341 /* Information about an address described by mips_address_type.
347 REG is the base register and OFFSET is the constant offset.
350 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
351 is the type of symbol it references.
354 SYMBOL_TYPE is the type of symbol that the address references. */
355 struct mips_address_info {
356 enum mips_address_type type;
359 enum mips_symbol_type symbol_type;
362 /* One stage in a constant building sequence. These sequences have
366 A = A CODE[1] VALUE[1]
367 A = A CODE[2] VALUE[2]
370 where A is an accumulator, each CODE[i] is a binary rtl operation
371 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
372 struct mips_integer_op {
374 unsigned HOST_WIDE_INT value;
377 /* The largest number of operations needed to load an integer constant.
378 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
379 When the lowest bit is clear, we can try, but reject a sequence with
380 an extra SLL at the end. */
381 #define MIPS_MAX_INTEGER_OPS 7
383 /* Information about a MIPS16e SAVE or RESTORE instruction. */
384 struct mips16e_save_restore_info {
385 /* The number of argument registers saved by a SAVE instruction.
386 0 for RESTORE instructions. */
389 /* Bit X is set if the instruction saves or restores GPR X. */
392 /* The total number of bytes to allocate. */
396 /* Global variables for machine-dependent things. */
398 /* The -G setting, or the configuration's default small-data limit if
399 no -G option is given. */
400 static unsigned int mips_small_data_threshold;
402 /* The number of file directives written by mips_output_filename. */
403 int num_source_filenames;
405 /* The name that appeared in the last .file directive written by
406 mips_output_filename, or "" if mips_output_filename hasn't
407 written anything yet. */
408 const char *current_function_file = "";
410 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
413 /* Arrays that map GCC register numbers to debugger register numbers. */
414 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
415 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
417 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
422 /* True if we're writing out a branch-likely instruction rather than a
424 static bool mips_branch_likely;
426 /* The operands passed to the last cmpMM expander. */
429 /* The current instruction-set architecture. */
430 enum processor_type mips_arch;
431 const struct mips_cpu_info *mips_arch_info;
433 /* The processor that we should tune the code for. */
434 enum processor_type mips_tune;
435 const struct mips_cpu_info *mips_tune_info;
437 /* The ISA level associated with mips_arch. */
440 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
441 static const struct mips_cpu_info *mips_isa_option_info;
443 /* Which ABI to use. */
444 int mips_abi = MIPS_ABI_DEFAULT;
446 /* Which cost information to use. */
447 const struct mips_rtx_cost_data *mips_cost;
449 /* The ambient target flags, excluding MASK_MIPS16. */
450 static int mips_base_target_flags;
452 /* True if MIPS16 is the default mode. */
453 bool mips_base_mips16;
455 /* The ambient values of other global variables. */
456 static int mips_base_schedule_insns; /* flag_schedule_insns */
457 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
458 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
459 static int mips_base_align_loops; /* align_loops */
460 static int mips_base_align_jumps; /* align_jumps */
461 static int mips_base_align_functions; /* align_functions */
463 /* The -mcode-readable setting. */
464 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
466 /* The -mr10k-cache-barrier setting. */
467 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
469 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
470 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
472 /* Index C is true if character C is a valid PRINT_OPERAND punctation
474 bool mips_print_operand_punct[256];
476 static GTY (()) int mips_output_filename_first_time = 1;
478 /* mips_split_p[X] is true if symbols of type X can be split by
479 mips_split_symbol. */
480 bool mips_split_p[NUM_SYMBOL_TYPES];
482 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
483 can be split by mips_split_symbol. */
484 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
486 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
487 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
488 if they are matched by a special .md file pattern. */
489 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
491 /* Likewise for HIGHs. */
492 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
494 /* Index R is the smallest register class that contains register R. */
495 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
496 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
497 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
498 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
499 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
500 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
501 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
502 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
503 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
504 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
505 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
506 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
507 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
508 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
509 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
510 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
511 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
512 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
513 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
514 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
515 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
516 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
517 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
518 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
519 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
520 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
521 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
522 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
523 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
524 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
525 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
526 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
527 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
528 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
529 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
530 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
531 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
532 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
533 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
534 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
535 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
536 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
537 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
538 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
539 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
540 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
541 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
542 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
545 /* The value of TARGET_ATTRIBUTE_TABLE. */
546 const struct attribute_spec mips_attribute_table[] = {
547 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
548 { "long_call", 0, 0, false, true, true, NULL },
549 { "far", 0, 0, false, true, true, NULL },
550 { "near", 0, 0, false, true, true, NULL },
551 /* We would really like to treat "mips16" and "nomips16" as type
552 attributes, but GCC doesn't provide the hooks we need to support
553 the right conversion rules. As declaration attributes, they affect
554 code generation but don't carry other semantics. */
555 { "mips16", 0, 0, true, false, false, NULL },
556 { "nomips16", 0, 0, true, false, false, NULL },
557 { NULL, 0, 0, false, false, false, NULL }
560 /* A table describing all the processors GCC knows about. Names are
561 matched in the order listed. The first mention of an ISA level is
562 taken as the canonical name for that ISA.
564 To ease comparison, please keep this table in the same order
565 as GAS's mips_cpu_info_table. Please also make sure that
566 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
567 options correctly. */
568 static const struct mips_cpu_info mips_cpu_info_table[] = {
569 /* Entries for generic ISAs. */
570 { "mips1", PROCESSOR_R3000, 1, 0 },
571 { "mips2", PROCESSOR_R6000, 2, 0 },
572 { "mips3", PROCESSOR_R4000, 3, 0 },
573 { "mips4", PROCESSOR_R8000, 4, 0 },
574 /* Prefer not to use branch-likely instructions for generic MIPS32rX
575 and MIPS64rX code. The instructions were officially deprecated
576 in revisions 2 and earlier, but revision 3 is likely to downgrade
577 that to a recommendation to avoid the instructions in code that
578 isn't tuned to a specific processor. */
579 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
580 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
581 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
582 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
583 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
585 /* MIPS I processors. */
586 { "r3000", PROCESSOR_R3000, 1, 0 },
587 { "r2000", PROCESSOR_R3000, 1, 0 },
588 { "r3900", PROCESSOR_R3900, 1, 0 },
590 /* MIPS II processors. */
591 { "r6000", PROCESSOR_R6000, 2, 0 },
593 /* MIPS III processors. */
594 { "r4000", PROCESSOR_R4000, 3, 0 },
595 { "vr4100", PROCESSOR_R4100, 3, 0 },
596 { "vr4111", PROCESSOR_R4111, 3, 0 },
597 { "vr4120", PROCESSOR_R4120, 3, 0 },
598 { "vr4130", PROCESSOR_R4130, 3, 0 },
599 { "vr4300", PROCESSOR_R4300, 3, 0 },
600 { "r4400", PROCESSOR_R4000, 3, 0 },
601 { "r4600", PROCESSOR_R4600, 3, 0 },
602 { "orion", PROCESSOR_R4600, 3, 0 },
603 { "r4650", PROCESSOR_R4650, 3, 0 },
604 /* ST Loongson 2E/2F processors. */
605 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
606 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
608 /* MIPS IV processors. */
609 { "r8000", PROCESSOR_R8000, 4, 0 },
610 { "r10000", PROCESSOR_R10000, 4, 0 },
611 { "r12000", PROCESSOR_R10000, 4, 0 },
612 { "r14000", PROCESSOR_R10000, 4, 0 },
613 { "r16000", PROCESSOR_R10000, 4, 0 },
614 { "vr5000", PROCESSOR_R5000, 4, 0 },
615 { "vr5400", PROCESSOR_R5400, 4, 0 },
616 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
617 { "rm7000", PROCESSOR_R7000, 4, 0 },
618 { "rm9000", PROCESSOR_R9000, 4, 0 },
620 /* MIPS32 processors. */
621 { "4kc", PROCESSOR_4KC, 32, 0 },
622 { "4km", PROCESSOR_4KC, 32, 0 },
623 { "4kp", PROCESSOR_4KP, 32, 0 },
624 { "4ksc", PROCESSOR_4KC, 32, 0 },
626 /* MIPS32 Release 2 processors. */
627 { "m4k", PROCESSOR_M4K, 33, 0 },
628 { "4kec", PROCESSOR_4KC, 33, 0 },
629 { "4kem", PROCESSOR_4KC, 33, 0 },
630 { "4kep", PROCESSOR_4KP, 33, 0 },
631 { "4ksd", PROCESSOR_4KC, 33, 0 },
633 { "24kc", PROCESSOR_24KC, 33, 0 },
634 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
635 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
636 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
637 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
638 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
640 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
641 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
642 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
643 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
644 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
645 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
647 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
648 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
649 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
650 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
651 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
652 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
654 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
655 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
656 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
657 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
658 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
659 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
660 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
662 /* MIPS64 processors. */
663 { "5kc", PROCESSOR_5KC, 64, 0 },
664 { "5kf", PROCESSOR_5KF, 64, 0 },
665 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
666 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
667 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
668 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
669 { "xlr", PROCESSOR_XLR, 64, 0 },
671 /* MIPS64 Release 2 processors. */
672 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
675 /* Default costs. If these are used for a processor we should look
676 up the actual costs. */
677 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
678 COSTS_N_INSNS (7), /* fp_mult_sf */ \
679 COSTS_N_INSNS (8), /* fp_mult_df */ \
680 COSTS_N_INSNS (23), /* fp_div_sf */ \
681 COSTS_N_INSNS (36), /* fp_div_df */ \
682 COSTS_N_INSNS (10), /* int_mult_si */ \
683 COSTS_N_INSNS (10), /* int_mult_di */ \
684 COSTS_N_INSNS (69), /* int_div_si */ \
685 COSTS_N_INSNS (69), /* int_div_di */ \
686 2, /* branch_cost */ \
687 4 /* memory_latency */
689 /* Floating-point costs for processors without an FPU. Just assume that
690 all floating-point libcalls are very expensive. */
691 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
692 COSTS_N_INSNS (256), /* fp_mult_sf */ \
693 COSTS_N_INSNS (256), /* fp_mult_df */ \
694 COSTS_N_INSNS (256), /* fp_div_sf */ \
695 COSTS_N_INSNS (256) /* fp_div_df */
697 /* Costs to use when optimizing for size. */
698 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
699 COSTS_N_INSNS (1), /* fp_add */
700 COSTS_N_INSNS (1), /* fp_mult_sf */
701 COSTS_N_INSNS (1), /* fp_mult_df */
702 COSTS_N_INSNS (1), /* fp_div_sf */
703 COSTS_N_INSNS (1), /* fp_div_df */
704 COSTS_N_INSNS (1), /* int_mult_si */
705 COSTS_N_INSNS (1), /* int_mult_di */
706 COSTS_N_INSNS (1), /* int_div_si */
707 COSTS_N_INSNS (1), /* int_div_di */
709 4 /* memory_latency */
712 /* Costs to use when optimizing for speed, indexed by processor. */
713 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
715 COSTS_N_INSNS (2), /* fp_add */
716 COSTS_N_INSNS (4), /* fp_mult_sf */
717 COSTS_N_INSNS (5), /* fp_mult_df */
718 COSTS_N_INSNS (12), /* fp_div_sf */
719 COSTS_N_INSNS (19), /* fp_div_df */
720 COSTS_N_INSNS (12), /* int_mult_si */
721 COSTS_N_INSNS (12), /* int_mult_di */
722 COSTS_N_INSNS (35), /* int_div_si */
723 COSTS_N_INSNS (35), /* int_div_di */
725 4 /* memory_latency */
729 COSTS_N_INSNS (6), /* int_mult_si */
730 COSTS_N_INSNS (6), /* int_mult_di */
731 COSTS_N_INSNS (36), /* int_div_si */
732 COSTS_N_INSNS (36), /* int_div_di */
734 4 /* memory_latency */
738 COSTS_N_INSNS (36), /* int_mult_si */
739 COSTS_N_INSNS (36), /* int_mult_di */
740 COSTS_N_INSNS (37), /* int_div_si */
741 COSTS_N_INSNS (37), /* int_div_di */
743 4 /* memory_latency */
747 COSTS_N_INSNS (4), /* int_mult_si */
748 COSTS_N_INSNS (11), /* int_mult_di */
749 COSTS_N_INSNS (36), /* int_div_si */
750 COSTS_N_INSNS (68), /* int_div_di */
752 4 /* memory_latency */
755 COSTS_N_INSNS (4), /* fp_add */
756 COSTS_N_INSNS (4), /* fp_mult_sf */
757 COSTS_N_INSNS (5), /* fp_mult_df */
758 COSTS_N_INSNS (17), /* fp_div_sf */
759 COSTS_N_INSNS (32), /* fp_div_df */
760 COSTS_N_INSNS (4), /* int_mult_si */
761 COSTS_N_INSNS (11), /* int_mult_di */
762 COSTS_N_INSNS (36), /* int_div_si */
763 COSTS_N_INSNS (68), /* int_div_di */
765 4 /* memory_latency */
768 COSTS_N_INSNS (4), /* fp_add */
769 COSTS_N_INSNS (4), /* fp_mult_sf */
770 COSTS_N_INSNS (5), /* fp_mult_df */
771 COSTS_N_INSNS (17), /* fp_div_sf */
772 COSTS_N_INSNS (32), /* fp_div_df */
773 COSTS_N_INSNS (4), /* int_mult_si */
774 COSTS_N_INSNS (7), /* int_mult_di */
775 COSTS_N_INSNS (42), /* int_div_si */
776 COSTS_N_INSNS (72), /* int_div_di */
778 4 /* memory_latency */
782 COSTS_N_INSNS (5), /* int_mult_si */
783 COSTS_N_INSNS (5), /* int_mult_di */
784 COSTS_N_INSNS (41), /* int_div_si */
785 COSTS_N_INSNS (41), /* int_div_di */
787 4 /* memory_latency */
790 COSTS_N_INSNS (8), /* fp_add */
791 COSTS_N_INSNS (8), /* fp_mult_sf */
792 COSTS_N_INSNS (10), /* fp_mult_df */
793 COSTS_N_INSNS (34), /* fp_div_sf */
794 COSTS_N_INSNS (64), /* fp_div_df */
795 COSTS_N_INSNS (5), /* int_mult_si */
796 COSTS_N_INSNS (5), /* int_mult_di */
797 COSTS_N_INSNS (41), /* int_div_si */
798 COSTS_N_INSNS (41), /* int_div_di */
800 4 /* memory_latency */
803 COSTS_N_INSNS (4), /* fp_add */
804 COSTS_N_INSNS (4), /* fp_mult_sf */
805 COSTS_N_INSNS (5), /* fp_mult_df */
806 COSTS_N_INSNS (17), /* fp_div_sf */
807 COSTS_N_INSNS (32), /* fp_div_df */
808 COSTS_N_INSNS (5), /* int_mult_si */
809 COSTS_N_INSNS (5), /* int_mult_di */
810 COSTS_N_INSNS (41), /* int_div_si */
811 COSTS_N_INSNS (41), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (5), /* int_mult_si */
818 COSTS_N_INSNS (5), /* int_mult_di */
819 COSTS_N_INSNS (41), /* int_div_si */
820 COSTS_N_INSNS (41), /* int_div_di */
822 4 /* memory_latency */
825 COSTS_N_INSNS (8), /* fp_add */
826 COSTS_N_INSNS (8), /* fp_mult_sf */
827 COSTS_N_INSNS (10), /* fp_mult_df */
828 COSTS_N_INSNS (34), /* fp_div_sf */
829 COSTS_N_INSNS (64), /* fp_div_df */
830 COSTS_N_INSNS (5), /* int_mult_si */
831 COSTS_N_INSNS (5), /* int_mult_di */
832 COSTS_N_INSNS (41), /* int_div_si */
833 COSTS_N_INSNS (41), /* int_div_di */
835 4 /* memory_latency */
838 COSTS_N_INSNS (4), /* fp_add */
839 COSTS_N_INSNS (4), /* fp_mult_sf */
840 COSTS_N_INSNS (5), /* fp_mult_df */
841 COSTS_N_INSNS (17), /* fp_div_sf */
842 COSTS_N_INSNS (32), /* fp_div_df */
843 COSTS_N_INSNS (5), /* int_mult_si */
844 COSTS_N_INSNS (5), /* int_mult_di */
845 COSTS_N_INSNS (41), /* int_div_si */
846 COSTS_N_INSNS (41), /* int_div_di */
848 4 /* memory_latency */
851 COSTS_N_INSNS (6), /* fp_add */
852 COSTS_N_INSNS (6), /* fp_mult_sf */
853 COSTS_N_INSNS (7), /* fp_mult_df */
854 COSTS_N_INSNS (25), /* fp_div_sf */
855 COSTS_N_INSNS (48), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
875 COSTS_N_INSNS (5), /* int_mult_si */
876 COSTS_N_INSNS (5), /* int_mult_di */
877 COSTS_N_INSNS (72), /* int_div_si */
878 COSTS_N_INSNS (72), /* int_div_di */
880 4 /* memory_latency */
883 COSTS_N_INSNS (2), /* fp_add */
884 COSTS_N_INSNS (4), /* fp_mult_sf */
885 COSTS_N_INSNS (5), /* fp_mult_df */
886 COSTS_N_INSNS (12), /* fp_div_sf */
887 COSTS_N_INSNS (19), /* fp_div_df */
888 COSTS_N_INSNS (2), /* int_mult_si */
889 COSTS_N_INSNS (2), /* int_mult_di */
890 COSTS_N_INSNS (35), /* int_div_si */
891 COSTS_N_INSNS (35), /* int_div_di */
893 4 /* memory_latency */
896 COSTS_N_INSNS (3), /* fp_add */
897 COSTS_N_INSNS (5), /* fp_mult_sf */
898 COSTS_N_INSNS (6), /* fp_mult_df */
899 COSTS_N_INSNS (15), /* fp_div_sf */
900 COSTS_N_INSNS (16), /* fp_div_df */
901 COSTS_N_INSNS (17), /* int_mult_si */
902 COSTS_N_INSNS (17), /* int_mult_di */
903 COSTS_N_INSNS (38), /* int_div_si */
904 COSTS_N_INSNS (38), /* int_div_di */
906 6 /* memory_latency */
909 COSTS_N_INSNS (6), /* fp_add */
910 COSTS_N_INSNS (7), /* fp_mult_sf */
911 COSTS_N_INSNS (8), /* fp_mult_df */
912 COSTS_N_INSNS (23), /* fp_div_sf */
913 COSTS_N_INSNS (36), /* fp_div_df */
914 COSTS_N_INSNS (10), /* int_mult_si */
915 COSTS_N_INSNS (10), /* int_mult_di */
916 COSTS_N_INSNS (69), /* int_div_si */
917 COSTS_N_INSNS (69), /* int_div_di */
919 6 /* memory_latency */
931 /* The only costs that appear to be updated here are
932 integer multiplication. */
934 COSTS_N_INSNS (4), /* int_mult_si */
935 COSTS_N_INSNS (6), /* int_mult_di */
936 COSTS_N_INSNS (69), /* int_div_si */
937 COSTS_N_INSNS (69), /* int_div_di */
939 4 /* memory_latency */
951 COSTS_N_INSNS (6), /* fp_add */
952 COSTS_N_INSNS (4), /* fp_mult_sf */
953 COSTS_N_INSNS (5), /* fp_mult_df */
954 COSTS_N_INSNS (23), /* fp_div_sf */
955 COSTS_N_INSNS (36), /* fp_div_df */
956 COSTS_N_INSNS (5), /* int_mult_si */
957 COSTS_N_INSNS (5), /* int_mult_di */
958 COSTS_N_INSNS (36), /* int_div_si */
959 COSTS_N_INSNS (36), /* int_div_di */
961 4 /* memory_latency */
964 COSTS_N_INSNS (6), /* fp_add */
965 COSTS_N_INSNS (5), /* fp_mult_sf */
966 COSTS_N_INSNS (6), /* fp_mult_df */
967 COSTS_N_INSNS (30), /* fp_div_sf */
968 COSTS_N_INSNS (59), /* fp_div_df */
969 COSTS_N_INSNS (3), /* int_mult_si */
970 COSTS_N_INSNS (4), /* int_mult_di */
971 COSTS_N_INSNS (42), /* int_div_si */
972 COSTS_N_INSNS (74), /* int_div_di */
974 4 /* memory_latency */
977 COSTS_N_INSNS (6), /* fp_add */
978 COSTS_N_INSNS (5), /* fp_mult_sf */
979 COSTS_N_INSNS (6), /* fp_mult_df */
980 COSTS_N_INSNS (30), /* fp_div_sf */
981 COSTS_N_INSNS (59), /* fp_div_df */
982 COSTS_N_INSNS (5), /* int_mult_si */
983 COSTS_N_INSNS (9), /* int_mult_di */
984 COSTS_N_INSNS (42), /* int_div_si */
985 COSTS_N_INSNS (74), /* int_div_di */
987 4 /* memory_latency */
990 /* The only costs that are changed here are
991 integer multiplication. */
992 COSTS_N_INSNS (6), /* fp_add */
993 COSTS_N_INSNS (7), /* fp_mult_sf */
994 COSTS_N_INSNS (8), /* fp_mult_df */
995 COSTS_N_INSNS (23), /* fp_div_sf */
996 COSTS_N_INSNS (36), /* fp_div_df */
997 COSTS_N_INSNS (5), /* int_mult_si */
998 COSTS_N_INSNS (9), /* int_mult_di */
999 COSTS_N_INSNS (69), /* int_div_si */
1000 COSTS_N_INSNS (69), /* int_div_di */
1001 1, /* branch_cost */
1002 4 /* memory_latency */
1008 /* The only costs that are changed here are
1009 integer multiplication. */
1010 COSTS_N_INSNS (6), /* fp_add */
1011 COSTS_N_INSNS (7), /* fp_mult_sf */
1012 COSTS_N_INSNS (8), /* fp_mult_df */
1013 COSTS_N_INSNS (23), /* fp_div_sf */
1014 COSTS_N_INSNS (36), /* fp_div_df */
1015 COSTS_N_INSNS (3), /* int_mult_si */
1016 COSTS_N_INSNS (8), /* int_mult_di */
1017 COSTS_N_INSNS (69), /* int_div_si */
1018 COSTS_N_INSNS (69), /* int_div_di */
1019 1, /* branch_cost */
1020 4 /* memory_latency */
1023 COSTS_N_INSNS (2), /* fp_add */
1024 COSTS_N_INSNS (2), /* fp_mult_sf */
1025 COSTS_N_INSNS (2), /* fp_mult_df */
1026 COSTS_N_INSNS (12), /* fp_div_sf */
1027 COSTS_N_INSNS (19), /* fp_div_df */
1028 COSTS_N_INSNS (5), /* int_mult_si */
1029 COSTS_N_INSNS (9), /* int_mult_di */
1030 COSTS_N_INSNS (34), /* int_div_si */
1031 COSTS_N_INSNS (66), /* int_div_di */
1032 1, /* branch_cost */
1033 4 /* memory_latency */
1036 /* These costs are the same as the SB-1A below. */
1037 COSTS_N_INSNS (4), /* fp_add */
1038 COSTS_N_INSNS (4), /* fp_mult_sf */
1039 COSTS_N_INSNS (4), /* fp_mult_df */
1040 COSTS_N_INSNS (24), /* fp_div_sf */
1041 COSTS_N_INSNS (32), /* fp_div_df */
1042 COSTS_N_INSNS (3), /* int_mult_si */
1043 COSTS_N_INSNS (4), /* int_mult_di */
1044 COSTS_N_INSNS (36), /* int_div_si */
1045 COSTS_N_INSNS (68), /* int_div_di */
1046 1, /* branch_cost */
1047 4 /* memory_latency */
1050 /* These costs are the same as the SB-1 above. */
1051 COSTS_N_INSNS (4), /* fp_add */
1052 COSTS_N_INSNS (4), /* fp_mult_sf */
1053 COSTS_N_INSNS (4), /* fp_mult_df */
1054 COSTS_N_INSNS (24), /* fp_div_sf */
1055 COSTS_N_INSNS (32), /* fp_div_df */
1056 COSTS_N_INSNS (3), /* int_mult_si */
1057 COSTS_N_INSNS (4), /* int_mult_di */
1058 COSTS_N_INSNS (36), /* int_div_si */
1059 COSTS_N_INSNS (68), /* int_div_di */
1060 1, /* branch_cost */
1061 4 /* memory_latency */
1067 /* Need to replace first five with the costs of calling the appropriate
1069 COSTS_N_INSNS (256), /* fp_add */
1070 COSTS_N_INSNS (256), /* fp_mult_sf */
1071 COSTS_N_INSNS (256), /* fp_mult_df */
1072 COSTS_N_INSNS (256), /* fp_div_sf */
1073 COSTS_N_INSNS (256), /* fp_div_df */
1074 COSTS_N_INSNS (8), /* int_mult_si */
1075 COSTS_N_INSNS (8), /* int_mult_di */
1076 COSTS_N_INSNS (72), /* int_div_si */
1077 COSTS_N_INSNS (72), /* int_div_di */
1078 1, /* branch_cost */
1079 4 /* memory_latency */
1083 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1084 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1085 struct mflip_mips16_entry GTY (()) {
1089 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1091 /* Hash table callbacks for mflip_mips16_htab. */
1094 mflip_mips16_htab_hash (const void *entry)
1096 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1100 mflip_mips16_htab_eq (const void *entry, const void *name)
1102 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1103 (const char *) name) == 0;
1106 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1107 mode, false if it should next add an attribute for the opposite mode. */
1108 static GTY(()) bool mips16_flipper;
1110 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1111 for -mflip-mips16. Return true if it should use "mips16" and false if
1112 it should use "nomips16". */
1115 mflip_mips16_use_mips16_p (tree decl)
1117 struct mflip_mips16_entry *entry;
1122 /* Use the opposite of the command-line setting for anonymous decls. */
1123 if (!DECL_NAME (decl))
1124 return !mips_base_mips16;
1126 if (!mflip_mips16_htab)
1127 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1128 mflip_mips16_htab_eq, NULL);
1130 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1131 hash = htab_hash_string (name);
1132 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1133 entry = (struct mflip_mips16_entry *) *slot;
1136 mips16_flipper = !mips16_flipper;
1137 entry = GGC_NEW (struct mflip_mips16_entry);
1139 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1142 return entry->mips16_p;
1145 /* Predicates to test for presence of "near" and "far"/"long_call"
1146 attributes on the given TYPE. */
1149 mips_near_type_p (const_tree type)
1151 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1155 mips_far_type_p (const_tree type)
1157 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1158 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1161 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1164 mips_mips16_decl_p (const_tree decl)
1166 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1170 mips_nomips16_decl_p (const_tree decl)
1172 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1175 /* Return true if function DECL is a MIPS16 function. Return the ambient
1176 setting if DECL is null. */
1179 mips_use_mips16_mode_p (tree decl)
1183 /* Nested functions must use the same frame pointer as their
1184 parent and must therefore use the same ISA mode. */
1185 tree parent = decl_function_context (decl);
1188 if (mips_mips16_decl_p (decl))
1190 if (mips_nomips16_decl_p (decl))
1193 return mips_base_mips16;
1196 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1199 mips_comp_type_attributes (const_tree type1, const_tree type2)
1201 /* Disallow mixed near/far attributes. */
1202 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1204 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1209 /* Implement TARGET_INSERT_ATTRIBUTES. */
1212 mips_insert_attributes (tree decl, tree *attributes)
1215 bool mips16_p, nomips16_p;
1217 /* Check for "mips16" and "nomips16" attributes. */
1218 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1219 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1220 if (TREE_CODE (decl) != FUNCTION_DECL)
1223 error ("%qs attribute only applies to functions", "mips16");
1225 error ("%qs attribute only applies to functions", "nomips16");
1229 mips16_p |= mips_mips16_decl_p (decl);
1230 nomips16_p |= mips_nomips16_decl_p (decl);
1231 if (mips16_p || nomips16_p)
1233 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1234 if (mips16_p && nomips16_p)
1235 error ("%qs cannot have both %<mips16%> and "
1236 "%<nomips16%> attributes",
1237 IDENTIFIER_POINTER (DECL_NAME (decl)));
1239 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1241 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1242 "mips16" attribute, arbitrarily pick one. We must pick the same
1243 setting for duplicate declarations of a function. */
1244 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1245 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1250 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1253 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1255 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1256 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1257 error ("%qs redeclared with conflicting %qs attributes",
1258 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1259 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1260 error ("%qs redeclared with conflicting %qs attributes",
1261 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1263 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1264 DECL_ATTRIBUTES (newdecl));
1267 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1268 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1271 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1273 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1275 *base_ptr = XEXP (x, 0);
1276 *offset_ptr = INTVAL (XEXP (x, 1));
1285 static unsigned int mips_build_integer (struct mips_integer_op *,
1286 unsigned HOST_WIDE_INT);
1288 /* A subroutine of mips_build_integer, with the same interface.
1289 Assume that the final action in the sequence should be a left shift. */
1292 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1294 unsigned int i, shift;
1296 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1297 since signed numbers are easier to load than unsigned ones. */
1299 while ((value & 1) == 0)
1300 value /= 2, shift++;
1302 i = mips_build_integer (codes, value);
1303 codes[i].code = ASHIFT;
1304 codes[i].value = shift;
1308 /* As for mips_build_shift, but assume that the final action will be
1309 an IOR or PLUS operation. */
1312 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1314 unsigned HOST_WIDE_INT high;
1317 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1318 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1320 /* The constant is too complex to load with a simple LUI/ORI pair,
1321 so we want to give the recursive call as many trailing zeros as
1322 possible. In this case, we know bit 16 is set and that the
1323 low 16 bits form a negative number. If we subtract that number
1324 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1325 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1326 codes[i].code = PLUS;
1327 codes[i].value = CONST_LOW_PART (value);
1331 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1332 bits gives a value with at least 17 trailing zeros. */
1333 i = mips_build_integer (codes, high);
1334 codes[i].code = IOR;
1335 codes[i].value = value & 0xffff;
1340 /* Fill CODES with a sequence of rtl operations to load VALUE.
1341 Return the number of operations needed. */
1344 mips_build_integer (struct mips_integer_op *codes,
1345 unsigned HOST_WIDE_INT value)
1347 if (SMALL_OPERAND (value)
1348 || SMALL_OPERAND_UNSIGNED (value)
1349 || LUI_OPERAND (value))
1351 /* The value can be loaded with a single instruction. */
1352 codes[0].code = UNKNOWN;
1353 codes[0].value = value;
1356 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1358 /* Either the constant is a simple LUI/ORI combination or its
1359 lowest bit is set. We don't want to shift in this case. */
1360 return mips_build_lower (codes, value);
1362 else if ((value & 0xffff) == 0)
1364 /* The constant will need at least three actions. The lowest
1365 16 bits are clear, so the final action will be a shift. */
1366 return mips_build_shift (codes, value);
1370 /* The final action could be a shift, add or inclusive OR.
1371 Rather than use a complex condition to select the best
1372 approach, try both mips_build_shift and mips_build_lower
1373 and pick the one that gives the shortest sequence.
1374 Note that this case is only used once per constant. */
1375 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1376 unsigned int cost, alt_cost;
1378 cost = mips_build_shift (codes, value);
1379 alt_cost = mips_build_lower (alt_codes, value);
1380 if (alt_cost < cost)
1382 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1389 /* Return true if symbols of type TYPE require a GOT access. */
1392 mips_got_symbol_type_p (enum mips_symbol_type type)
1396 case SYMBOL_GOT_PAGE_OFST:
1397 case SYMBOL_GOT_DISP:
1405 /* Return true if X is a thread-local symbol. */
1408 mips_tls_symbol_p (rtx x)
1410 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1413 /* Return true if SYMBOL_REF X is associated with a global symbol
1414 (in the STB_GLOBAL sense). */
1417 mips_global_symbol_p (const_rtx x)
1419 const_tree decl = SYMBOL_REF_DECL (x);
1422 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1424 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1425 or weak symbols. Relocations in the object file will be against
1426 the target symbol, so it's that symbol's binding that matters here. */
1427 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1430 /* Return true if function X is a libgcc MIPS16 stub function. */
1433 mips16_stub_function_p (const_rtx x)
1435 return (GET_CODE (x) == SYMBOL_REF
1436 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1439 /* Return true if function X is a locally-defined and locally-binding
1443 mips16_local_function_p (const_rtx x)
1445 return (GET_CODE (x) == SYMBOL_REF
1446 && SYMBOL_REF_LOCAL_P (x)
1447 && !SYMBOL_REF_EXTERNAL_P (x)
1448 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1451 /* Return true if SYMBOL_REF X binds locally. */
1454 mips_symbol_binds_local_p (const_rtx x)
1456 return (SYMBOL_REF_DECL (x)
1457 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1458 : SYMBOL_REF_LOCAL_P (x));
1461 /* Return true if rtx constants of mode MODE should be put into a small
1465 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1467 return (!TARGET_EMBEDDED_DATA
1468 && TARGET_LOCAL_SDATA
1469 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1472 /* Return true if X should not be moved directly into register $25.
1473 We need this because many versions of GAS will treat "la $25,foo" as
1474 part of a call sequence and so allow a global "foo" to be lazily bound. */
1477 mips_dangerous_for_la25_p (rtx x)
1479 return (!TARGET_EXPLICIT_RELOCS
1481 && GET_CODE (x) == SYMBOL_REF
1482 && mips_global_symbol_p (x));
1485 /* Return true if calls to X might need $25 to be valid on entry. */
1488 mips_use_pic_fn_addr_reg_p (const_rtx x)
1490 if (!TARGET_USE_PIC_FN_ADDR_REG)
1493 /* MIPS16 stub functions are guaranteed not to use $25. */
1494 if (mips16_stub_function_p (x))
1497 if (GET_CODE (x) == SYMBOL_REF)
1499 /* If PLTs and copy relocations are available, the static linker
1500 will make sure that $25 is valid on entry to the target function. */
1501 if (TARGET_ABICALLS_PIC0)
1504 /* Locally-defined functions use absolute accesses to set up
1505 the global pointer. */
1506 if (TARGET_ABSOLUTE_ABICALLS
1507 && mips_symbol_binds_local_p (x)
1508 && !SYMBOL_REF_EXTERNAL_P (x))
1515 /* Return the method that should be used to access SYMBOL_REF or
1516 LABEL_REF X in context CONTEXT. */
1518 static enum mips_symbol_type
1519 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1522 return SYMBOL_GOT_DISP;
1524 if (GET_CODE (x) == LABEL_REF)
1526 /* LABEL_REFs are used for jump tables as well as text labels.
1527 Only return SYMBOL_PC_RELATIVE if we know the label is in
1528 the text section. */
1529 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1530 return SYMBOL_PC_RELATIVE;
1532 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1533 return SYMBOL_GOT_PAGE_OFST;
1535 return SYMBOL_ABSOLUTE;
1538 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1540 if (SYMBOL_REF_TLS_MODEL (x))
1543 if (CONSTANT_POOL_ADDRESS_P (x))
1545 if (TARGET_MIPS16_TEXT_LOADS)
1546 return SYMBOL_PC_RELATIVE;
1548 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1549 return SYMBOL_PC_RELATIVE;
1551 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1552 return SYMBOL_GP_RELATIVE;
1555 /* Do not use small-data accesses for weak symbols; they may end up
1557 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1558 return SYMBOL_GP_RELATIVE;
1560 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1562 if (TARGET_ABICALLS_PIC2
1563 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1565 /* There are three cases to consider:
1567 - o32 PIC (either with or without explicit relocs)
1568 - n32/n64 PIC without explicit relocs
1569 - n32/n64 PIC with explicit relocs
1571 In the first case, both local and global accesses will use an
1572 R_MIPS_GOT16 relocation. We must correctly predict which of
1573 the two semantics (local or global) the assembler and linker
1574 will apply. The choice depends on the symbol's binding rather
1575 than its visibility.
1577 In the second case, the assembler will not use R_MIPS_GOT16
1578 relocations, but it chooses between local and global accesses
1579 in the same way as for o32 PIC.
1581 In the third case we have more freedom since both forms of
1582 access will work for any kind of symbol. However, there seems
1583 little point in doing things differently. */
1584 if (mips_global_symbol_p (x))
1585 return SYMBOL_GOT_DISP;
1587 return SYMBOL_GOT_PAGE_OFST;
1590 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1591 return SYMBOL_FORCE_TO_MEM;
1593 return SYMBOL_ABSOLUTE;
1596 /* Classify the base of symbolic expression X, given that X appears in
1599 static enum mips_symbol_type
1600 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1604 split_const (x, &x, &offset);
1605 if (UNSPEC_ADDRESS_P (x))
1606 return UNSPEC_ADDRESS_TYPE (x);
1608 return mips_classify_symbol (x, context);
1611 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1612 is the alignment in bytes of SYMBOL_REF X. */
1615 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1617 HOST_WIDE_INT align;
1619 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1620 return IN_RANGE (offset, 0, align - 1);
1623 /* Return true if X is a symbolic constant that can be used in context
1624 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1627 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1628 enum mips_symbol_type *symbol_type)
1632 split_const (x, &x, &offset);
1633 if (UNSPEC_ADDRESS_P (x))
1635 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1636 x = UNSPEC_ADDRESS (x);
1638 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1640 *symbol_type = mips_classify_symbol (x, context);
1641 if (*symbol_type == SYMBOL_TLS)
1647 if (offset == const0_rtx)
1650 /* Check whether a nonzero offset is valid for the underlying
1652 switch (*symbol_type)
1654 case SYMBOL_ABSOLUTE:
1655 case SYMBOL_FORCE_TO_MEM:
1656 case SYMBOL_32_HIGH:
1657 case SYMBOL_64_HIGH:
1660 /* If the target has 64-bit pointers and the object file only
1661 supports 32-bit symbols, the values of those symbols will be
1662 sign-extended. In this case we can't allow an arbitrary offset
1663 in case the 32-bit value X + OFFSET has a different sign from X. */
1664 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1665 return offset_within_block_p (x, INTVAL (offset));
1667 /* In other cases the relocations can handle any offset. */
1670 case SYMBOL_PC_RELATIVE:
1671 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1672 In this case, we no longer have access to the underlying constant,
1673 but the original symbol-based access was known to be valid. */
1674 if (GET_CODE (x) == LABEL_REF)
1679 case SYMBOL_GP_RELATIVE:
1680 /* Make sure that the offset refers to something within the
1681 same object block. This should guarantee that the final
1682 PC- or GP-relative offset is within the 16-bit limit. */
1683 return offset_within_block_p (x, INTVAL (offset));
1685 case SYMBOL_GOT_PAGE_OFST:
1686 case SYMBOL_GOTOFF_PAGE:
1687 /* If the symbol is global, the GOT entry will contain the symbol's
1688 address, and we will apply a 16-bit offset after loading it.
1689 If the symbol is local, the linker should provide enough local
1690 GOT entries for a 16-bit offset, but larger offsets may lead
1692 return SMALL_INT (offset);
1696 /* There is no carry between the HI and LO REL relocations, so the
1697 offset is only valid if we know it won't lead to such a carry. */
1698 return mips_offset_within_alignment_p (x, INTVAL (offset));
1700 case SYMBOL_GOT_DISP:
1701 case SYMBOL_GOTOFF_DISP:
1702 case SYMBOL_GOTOFF_CALL:
1703 case SYMBOL_GOTOFF_LOADGP:
1706 case SYMBOL_GOTTPREL:
1714 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1715 single instruction. We rely on the fact that, in the worst case,
1716 all instructions involved in a MIPS16 address calculation are usually
1720 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1724 case SYMBOL_ABSOLUTE:
1725 /* When using 64-bit symbols, we need 5 preparatory instructions,
1728 lui $at,%highest(symbol)
1729 daddiu $at,$at,%higher(symbol)
1731 daddiu $at,$at,%hi(symbol)
1734 The final address is then $at + %lo(symbol). With 32-bit
1735 symbols we just need a preparatory LUI for normal mode and
1736 a preparatory LI and SLL for MIPS16. */
1737 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1739 case SYMBOL_GP_RELATIVE:
1740 /* Treat GP-relative accesses as taking a single instruction on
1741 MIPS16 too; the copy of $gp can often be shared. */
1744 case SYMBOL_PC_RELATIVE:
1745 /* PC-relative constants can be only be used with ADDIUPC,
1746 DADDIUPC, LWPC and LDPC. */
1747 if (mode == MAX_MACHINE_MODE
1748 || GET_MODE_SIZE (mode) == 4
1749 || GET_MODE_SIZE (mode) == 8)
1752 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1755 case SYMBOL_FORCE_TO_MEM:
1756 /* LEAs will be converted into constant-pool references by
1758 if (mode == MAX_MACHINE_MODE)
1761 /* The constant must be loaded and then dereferenced. */
1764 case SYMBOL_GOT_DISP:
1765 /* The constant will have to be loaded from the GOT before it
1766 is used in an address. */
1767 if (mode != MAX_MACHINE_MODE)
1772 case SYMBOL_GOT_PAGE_OFST:
1773 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1774 local/global classification is accurate. The worst cases are:
1776 (1) For local symbols when generating o32 or o64 code. The assembler
1782 ...and the final address will be $at + %lo(symbol).
1784 (2) For global symbols when -mxgot. The assembler will use:
1786 lui $at,%got_hi(symbol)
1789 ...and the final address will be $at + %got_lo(symbol). */
1792 case SYMBOL_GOTOFF_PAGE:
1793 case SYMBOL_GOTOFF_DISP:
1794 case SYMBOL_GOTOFF_CALL:
1795 case SYMBOL_GOTOFF_LOADGP:
1796 case SYMBOL_32_HIGH:
1797 case SYMBOL_64_HIGH:
1803 case SYMBOL_GOTTPREL:
1806 /* A 16-bit constant formed by a single relocation, or a 32-bit
1807 constant formed from a high 16-bit relocation and a low 16-bit
1808 relocation. Use mips_split_p to determine which. 32-bit
1809 constants need an "lui; addiu" sequence for normal mode and
1810 an "li; sll; addiu" sequence for MIPS16 mode. */
1811 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1814 /* We don't treat a bare TLS symbol as a constant. */
1820 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1821 to load symbols of type TYPE into a register. Return 0 if the given
1822 type of symbol cannot be used as an immediate operand.
1824 Otherwise, return the number of instructions needed to load or store
1825 values of mode MODE to or from addresses of type TYPE. Return 0 if
1826 the given type of symbol is not valid in addresses.
1828 In both cases, treat extended MIPS16 instructions as two instructions. */
1831 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1833 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1836 /* A for_each_rtx callback. Stop the search if *X references a
1837 thread-local symbol. */
1840 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1842 return mips_tls_symbol_p (*x);
1845 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1848 mips_cannot_force_const_mem (rtx x)
1850 enum mips_symbol_type type;
1853 /* There is no assembler syntax for expressing an address-sized
1855 if (GET_CODE (x) == HIGH)
1858 /* As an optimization, reject constants that mips_legitimize_move
1861 Suppose we have a multi-instruction sequence that loads constant C
1862 into register R. If R does not get allocated a hard register, and
1863 R is used in an operand that allows both registers and memory
1864 references, reload will consider forcing C into memory and using
1865 one of the instruction's memory alternatives. Returning false
1866 here will force it to use an input reload instead. */
1867 if (GET_CODE (x) == CONST_INT && LEGITIMATE_CONSTANT_P (x))
1870 split_const (x, &base, &offset);
1871 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1872 && type != SYMBOL_FORCE_TO_MEM)
1874 /* The same optimization as for CONST_INT. */
1875 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1878 /* If MIPS16 constant pools live in the text section, they should
1879 not refer to anything that might need run-time relocation. */
1880 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1884 /* TLS symbols must be computed by mips_legitimize_move. */
1885 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1891 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1892 constants when we're using a per-function constant pool. */
1895 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1896 const_rtx x ATTRIBUTE_UNUSED)
1898 return !TARGET_MIPS16_PCREL_LOADS;
1901 /* Return true if register REGNO is a valid base register for mode MODE.
1902 STRICT_P is true if REG_OK_STRICT is in effect. */
1905 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1908 if (!HARD_REGISTER_NUM_P (regno))
1912 regno = reg_renumber[regno];
1915 /* These fake registers will be eliminated to either the stack or
1916 hard frame pointer, both of which are usually valid base registers.
1917 Reload deals with the cases where the eliminated form isn't valid. */
1918 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1921 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1922 values, nothing smaller. There are two problems here:
1924 (a) Instantiating virtual registers can introduce new uses of the
1925 stack pointer. If these virtual registers are valid addresses,
1926 the stack pointer should be too.
1928 (b) Most uses of the stack pointer are not made explicit until
1929 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1930 We don't know until that stage whether we'll be eliminating to the
1931 stack pointer (which needs the restriction) or the hard frame
1932 pointer (which doesn't).
1934 All in all, it seems more consistent to only enforce this restriction
1935 during and after reload. */
1936 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1937 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1939 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1942 /* Return true if X is a valid base register for mode MODE.
1943 STRICT_P is true if REG_OK_STRICT is in effect. */
1946 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1948 if (!strict_p && GET_CODE (x) == SUBREG)
1952 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
1955 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1956 can address a value of mode MODE. */
1959 mips_valid_offset_p (rtx x, enum machine_mode mode)
1961 /* Check that X is a signed 16-bit number. */
1962 if (!const_arith_operand (x, Pmode))
1965 /* We may need to split multiword moves, so make sure that every word
1967 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1968 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
1974 /* Return true if a LO_SUM can address a value of mode MODE when the
1975 LO_SUM symbol has type SYMBOL_TYPE. */
1978 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
1980 /* Check that symbols of type SYMBOL_TYPE can be used to access values
1982 if (mips_symbol_insns (symbol_type, mode) == 0)
1985 /* Check that there is a known low-part relocation. */
1986 if (mips_lo_relocs[symbol_type] == NULL)
1989 /* We may need to split multiword moves, so make sure that each word
1990 can be accessed without inducing a carry. This is mainly needed
1991 for o64, which has historically only guaranteed 64-bit alignment
1992 for 128-bit types. */
1993 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1994 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2000 /* Return true if X is a valid address for machine mode MODE. If it is,
2001 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2005 mips_classify_address (struct mips_address_info *info, rtx x,
2006 enum machine_mode mode, bool strict_p)
2008 switch (GET_CODE (x))
2012 info->type = ADDRESS_REG;
2014 info->offset = const0_rtx;
2015 return mips_valid_base_register_p (info->reg, mode, strict_p);
2018 info->type = ADDRESS_REG;
2019 info->reg = XEXP (x, 0);
2020 info->offset = XEXP (x, 1);
2021 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2022 && mips_valid_offset_p (info->offset, mode));
2025 info->type = ADDRESS_LO_SUM;
2026 info->reg = XEXP (x, 0);
2027 info->offset = XEXP (x, 1);
2028 /* We have to trust the creator of the LO_SUM to do something vaguely
2029 sane. Target-independent code that creates a LO_SUM should also
2030 create and verify the matching HIGH. Target-independent code that
2031 adds an offset to a LO_SUM must prove that the offset will not
2032 induce a carry. Failure to do either of these things would be
2033 a bug, and we are not required to check for it here. The MIPS
2034 backend itself should only create LO_SUMs for valid symbolic
2035 constants, with the high part being either a HIGH or a copy
2038 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2039 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2040 && mips_valid_lo_sum_p (info->symbol_type, mode));
2043 /* Small-integer addresses don't occur very often, but they
2044 are legitimate if $0 is a valid base register. */
2045 info->type = ADDRESS_CONST_INT;
2046 return !TARGET_MIPS16 && SMALL_INT (x);
2051 info->type = ADDRESS_SYMBOLIC;
2052 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2054 && mips_symbol_insns (info->symbol_type, mode) > 0
2055 && !mips_split_p[info->symbol_type]);
2062 /* Return true if X is a legitimate address for a memory operand of mode
2063 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
2066 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2068 struct mips_address_info addr;
2070 return mips_classify_address (&addr, x, mode, strict_p);
2073 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2076 mips_stack_address_p (rtx x, enum machine_mode mode)
2078 struct mips_address_info addr;
2080 return (mips_classify_address (&addr, x, mode, false)
2081 && addr.type == ADDRESS_REG
2082 && addr.reg == stack_pointer_rtx);
2085 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2086 address instruction. Note that such addresses are not considered
2087 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
2088 is so restricted. */
2091 mips_lwxs_address_p (rtx addr)
2094 && GET_CODE (addr) == PLUS
2095 && REG_P (XEXP (addr, 1)))
2097 rtx offset = XEXP (addr, 0);
2098 if (GET_CODE (offset) == MULT
2099 && REG_P (XEXP (offset, 0))
2100 && GET_CODE (XEXP (offset, 1)) == CONST_INT
2101 && INTVAL (XEXP (offset, 1)) == 4)
2107 /* Return true if a value at OFFSET bytes from base register BASE can be
2108 accessed using an unextended MIPS16 instruction. MODE is the mode of
2111 Usually the offset in an unextended instruction is a 5-bit field.
2112 The offset is unsigned and shifted left once for LH and SH, twice
2113 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2114 an 8-bit immediate field that's shifted left twice. */
2117 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2118 unsigned HOST_WIDE_INT offset)
2120 if (offset % GET_MODE_SIZE (mode) == 0)
2122 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2123 return offset < 256U * GET_MODE_SIZE (mode);
2124 return offset < 32U * GET_MODE_SIZE (mode);
2129 /* Return the number of instructions needed to load or store a value
2130 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2131 Assume that multiword moves may need to be split into word moves
2132 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2135 For MIPS16 code, count extended instructions as two instructions. */
2138 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2140 struct mips_address_info addr;
2143 /* BLKmode is used for single unaligned loads and stores and should
2144 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2145 meaningless, so we have to single it out as a special case one way
2147 if (mode != BLKmode && might_split_p)
2148 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2152 if (mips_classify_address (&addr, x, mode, false))
2157 && !mips16_unextended_reference_p (mode, addr.reg,
2158 UINTVAL (addr.offset)))
2162 case ADDRESS_LO_SUM:
2163 return TARGET_MIPS16 ? factor * 2 : factor;
2165 case ADDRESS_CONST_INT:
2168 case ADDRESS_SYMBOLIC:
2169 return factor * mips_symbol_insns (addr.symbol_type, mode);
2174 /* Return the number of instructions needed to load constant X.
2175 Return 0 if X isn't a valid constant. */
2178 mips_const_insns (rtx x)
2180 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2181 enum mips_symbol_type symbol_type;
2184 switch (GET_CODE (x))
2187 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2189 || !mips_split_p[symbol_type])
2192 /* This is simply an LUI for normal mode. It is an extended
2193 LI followed by an extended SLL for MIPS16. */
2194 return TARGET_MIPS16 ? 4 : 1;
2198 /* Unsigned 8-bit constants can be loaded using an unextended
2199 LI instruction. Unsigned 16-bit constants can be loaded
2200 using an extended LI. Negative constants must be loaded
2201 using LI and then negated. */
2202 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2203 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2204 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2205 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2208 return mips_build_integer (codes, INTVAL (x));
2212 /* Allow zeros for normal mode, where we can use $0. */
2213 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2219 /* See if we can refer to X directly. */
2220 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2221 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2223 /* Otherwise try splitting the constant into a base and offset.
2224 If the offset is a 16-bit value, we can load the base address
2225 into a register and then use (D)ADDIU to add in the offset.
2226 If the offset is larger, we can load the base and offset
2227 into separate registers and add them together with (D)ADDU.
2228 However, the latter is only possible before reload; during
2229 and after reload, we must have the option of forcing the
2230 constant into the pool instead. */
2231 split_const (x, &x, &offset);
2234 int n = mips_const_insns (x);
2237 if (SMALL_INT (offset))
2239 else if (!targetm.cannot_force_const_mem (x))
2240 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2247 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2255 /* X is a doubleword constant that can be handled by splitting it into
2256 two words and loading each word separately. Return the number of
2257 instructions required to do this. */
2260 mips_split_const_insns (rtx x)
2262 unsigned int low, high;
2264 low = mips_const_insns (mips_subword (x, false));
2265 high = mips_const_insns (mips_subword (x, true));
2266 gcc_assert (low > 0 && high > 0);
2270 /* Return the number of instructions needed to implement INSN,
2271 given that it loads from or stores to MEM. Count extended
2272 MIPS16 instructions as two instructions. */
2275 mips_load_store_insns (rtx mem, rtx insn)
2277 enum machine_mode mode;
2281 gcc_assert (MEM_P (mem));
2282 mode = GET_MODE (mem);
2284 /* Try to prove that INSN does not need to be split. */
2285 might_split_p = true;
2286 if (GET_MODE_BITSIZE (mode) == 64)
2288 set = single_set (insn);
2289 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2290 might_split_p = false;
2293 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2296 /* Return the number of instructions needed for an integer division. */
2299 mips_idiv_insns (void)
2304 if (TARGET_CHECK_ZERO_DIV)
2306 if (GENERATE_DIVIDE_TRAPS)
2312 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2317 /* Emit a move from SRC to DEST. Assume that the move expanders can
2318 handle all moves if !can_create_pseudo_p (). The distinction is
2319 important because, unlike emit_move_insn, the move expanders know
2320 how to force Pmode objects into the constant pool even when the
2321 constant pool address is not itself legitimate. */
2324 mips_emit_move (rtx dest, rtx src)
2326 return (can_create_pseudo_p ()
2327 ? emit_move_insn (dest, src)
2328 : emit_move_insn_1 (dest, src));
2331 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2334 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2336 emit_insn (gen_rtx_SET (VOIDmode, target,
2337 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2340 /* Compute (CODE OP0 OP1) and store the result in a new register
2341 of mode MODE. Return that new register. */
2344 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2348 reg = gen_reg_rtx (mode);
2349 mips_emit_binary (code, reg, op0, op1);
2353 /* Copy VALUE to a register and return that register. If new pseudos
2354 are allowed, copy it into a new register, otherwise use DEST. */
2357 mips_force_temporary (rtx dest, rtx value)
2359 if (can_create_pseudo_p ())
2360 return force_reg (Pmode, value);
2363 mips_emit_move (dest, value);
2368 /* Emit a call sequence with call pattern PATTERN and return the call
2369 instruction itself (which is not necessarily the last instruction
2370 emitted). ORIG_ADDR is the original, unlegitimized address,
2371 ADDR is the legitimized form, and LAZY_P is true if the call
2372 address is lazily-bound. */
2375 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2379 insn = emit_call_insn (pattern);
2381 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2383 /* MIPS16 JALRs only take MIPS16 registers. If the target
2384 function requires $25 to be valid on entry, we must copy it
2385 there separately. The move instruction can be put in the
2386 call's delay slot. */
2387 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2388 emit_insn_before (gen_move_insn (reg, addr), insn);
2389 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2393 /* Lazy-binding stubs require $gp to be valid on entry. */
2394 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2398 /* See the comment above load_call<mode> for details. */
2399 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2400 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2401 emit_insn (gen_update_got_version ());
2406 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2407 then add CONST_INT OFFSET to the result. */
2410 mips_unspec_address_offset (rtx base, rtx offset,
2411 enum mips_symbol_type symbol_type)
2413 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2414 UNSPEC_ADDRESS_FIRST + symbol_type);
2415 if (offset != const0_rtx)
2416 base = gen_rtx_PLUS (Pmode, base, offset);
2417 return gen_rtx_CONST (Pmode, base);
2420 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2421 type SYMBOL_TYPE. */
2424 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2428 split_const (address, &base, &offset);
2429 return mips_unspec_address_offset (base, offset, symbol_type);
2432 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2433 high part to BASE and return the result. Just return BASE otherwise.
2434 TEMP is as for mips_force_temporary.
2436 The returned expression can be used as the first operand to a LO_SUM. */
2439 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2440 enum mips_symbol_type symbol_type)
2442 if (mips_split_p[symbol_type])
2444 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2445 addr = mips_force_temporary (temp, addr);
2446 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2451 /* Return an instruction that copies $gp into register REG. We want
2452 GCC to treat the register's value as constant, so that its value
2453 can be rematerialized on demand. */
2456 gen_load_const_gp (rtx reg)
2458 return (Pmode == SImode
2459 ? gen_load_const_gp_si (reg)
2460 : gen_load_const_gp_di (reg));
2463 /* Return a pseudo register that contains the value of $gp throughout
2464 the current function. Such registers are needed by MIPS16 functions,
2465 for which $gp itself is not a valid base register or addition operand. */
2468 mips16_gp_pseudo_reg (void)
2470 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2471 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2473 /* Don't emit an instruction to initialize the pseudo register if
2474 we are being called from the tree optimizers' cost-calculation
2476 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2477 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2481 push_topmost_sequence ();
2483 scan = get_insns ();
2484 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2485 scan = NEXT_INSN (scan);
2487 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2488 emit_insn_after (insn, scan);
2490 pop_topmost_sequence ();
2492 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2495 return cfun->machine->mips16_gp_pseudo_rtx;
2498 /* Return a base register that holds pic_offset_table_rtx.
2499 TEMP, if nonnull, is a scratch Pmode base register. */
2502 mips_pic_base_register (rtx temp)
2505 return pic_offset_table_rtx;
2507 if (can_create_pseudo_p ())
2508 return mips16_gp_pseudo_reg ();
2511 /* The first post-reload split exposes all references to $gp
2512 (both uses and definitions). All references must remain
2513 explicit after that point.
2515 It is safe to introduce uses of $gp at any time, so for
2516 simplicity, we do that before the split too. */
2517 mips_emit_move (temp, pic_offset_table_rtx);
2519 emit_insn (gen_load_const_gp (temp));
2523 /* Create and return a GOT reference of type TYPE for address ADDR.
2524 TEMP, if nonnull, is a scratch Pmode base register. */
2527 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2529 rtx base, high, lo_sum_symbol;
2531 base = mips_pic_base_register (temp);
2533 /* If we used the temporary register to load $gp, we can't use
2534 it for the high part as well. */
2535 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2538 high = mips_unspec_offset_high (temp, base, addr, type);
2539 lo_sum_symbol = mips_unspec_address (addr, type);
2541 if (type == SYMBOL_GOTOFF_CALL)
2542 return (Pmode == SImode
2543 ? gen_unspec_callsi (high, lo_sum_symbol)
2544 : gen_unspec_calldi (high, lo_sum_symbol));
2546 return (Pmode == SImode
2547 ? gen_unspec_gotsi (high, lo_sum_symbol)
2548 : gen_unspec_gotdi (high, lo_sum_symbol));
2551 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2552 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2553 constant in that context and can be split into high and low parts.
2554 If so, and if LOW_OUT is nonnull, emit the high part and store the
2555 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2557 TEMP is as for mips_force_temporary and is used to load the high
2558 part into a register.
2560 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2561 a legitimize SET_SRC for an .md pattern, otherwise the low part
2562 is guaranteed to be a legitimate address for mode MODE. */
2565 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2567 enum mips_symbol_context context;
2568 enum mips_symbol_type symbol_type;
2571 context = (mode == MAX_MACHINE_MODE
2572 ? SYMBOL_CONTEXT_LEA
2573 : SYMBOL_CONTEXT_MEM);
2574 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2576 addr = XEXP (addr, 0);
2577 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2578 && mips_symbol_insns (symbol_type, mode) > 0
2579 && mips_split_hi_p[symbol_type])
2582 switch (symbol_type)
2584 case SYMBOL_GOT_PAGE_OFST:
2585 /* The high part of a page/ofst pair is loaded from the GOT. */
2586 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2597 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2598 && mips_symbol_insns (symbol_type, mode) > 0
2599 && mips_split_p[symbol_type])
2602 switch (symbol_type)
2604 case SYMBOL_GOT_DISP:
2605 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2606 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2609 case SYMBOL_GP_RELATIVE:
2610 high = mips_pic_base_register (temp);
2611 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2615 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2616 high = mips_force_temporary (temp, high);
2617 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2626 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2627 mips_force_temporary; it is only needed when OFFSET is not a
2631 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2633 if (!SMALL_OPERAND (offset))
2639 /* Load the full offset into a register so that we can use
2640 an unextended instruction for the address itself. */
2641 high = GEN_INT (offset);
2646 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2647 high = GEN_INT (CONST_HIGH_PART (offset));
2648 offset = CONST_LOW_PART (offset);
2650 high = mips_force_temporary (temp, high);
2651 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2653 return plus_constant (reg, offset);
2656 /* The __tls_get_attr symbol. */
2657 static GTY(()) rtx mips_tls_symbol;
2659 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2660 the TLS symbol we are referencing and TYPE is the symbol type to use
2661 (either global dynamic or local dynamic). V0 is an RTX for the
2662 return value location. */
2665 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2669 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2671 if (!mips_tls_symbol)
2672 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2674 loc = mips_unspec_address (sym, type);
2678 emit_insn (gen_rtx_SET (Pmode, a0,
2679 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2680 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2681 const0_rtx, NULL_RTX, false);
2682 RTL_CONST_CALL_P (insn) = 1;
2683 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2684 insn = get_insns ();
2691 /* Return a pseudo register that contains the current thread pointer. */
2698 tp = gen_reg_rtx (Pmode);
2699 if (Pmode == DImode)
2700 emit_insn (gen_tls_get_tp_di (tp));
2702 emit_insn (gen_tls_get_tp_si (tp));
2706 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2707 its address. The return value will be both a valid address and a valid
2708 SET_SRC (either a REG or a LO_SUM). */
2711 mips_legitimize_tls_address (rtx loc)
2713 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2714 enum tls_model model;
2718 sorry ("MIPS16 TLS");
2719 return gen_reg_rtx (Pmode);
2722 model = SYMBOL_REF_TLS_MODEL (loc);
2723 /* Only TARGET_ABICALLS code can have more than one module; other
2724 code must be be static and should not use a GOT. All TLS models
2725 reduce to local exec in this situation. */
2726 if (!TARGET_ABICALLS)
2727 model = TLS_MODEL_LOCAL_EXEC;
2731 case TLS_MODEL_GLOBAL_DYNAMIC:
2732 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2733 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2734 dest = gen_reg_rtx (Pmode);
2735 emit_libcall_block (insn, dest, v0, loc);
2738 case TLS_MODEL_LOCAL_DYNAMIC:
2739 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2740 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2741 tmp1 = gen_reg_rtx (Pmode);
2743 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2744 share the LDM result with other LD model accesses. */
2745 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2747 emit_libcall_block (insn, tmp1, v0, eqv);
2749 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2750 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2751 mips_unspec_address (loc, SYMBOL_DTPREL));
2754 case TLS_MODEL_INITIAL_EXEC:
2755 tp = mips_get_tp ();
2756 tmp1 = gen_reg_rtx (Pmode);
2757 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2758 if (Pmode == DImode)
2759 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2761 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2762 dest = gen_reg_rtx (Pmode);
2763 emit_insn (gen_add3_insn (dest, tmp1, tp));
2766 case TLS_MODEL_LOCAL_EXEC:
2767 tp = mips_get_tp ();
2768 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2769 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2770 mips_unspec_address (loc, SYMBOL_TPREL));
2779 /* If X is not a valid address for mode MODE, force it into a register. */
2782 mips_force_address (rtx x, enum machine_mode mode)
2784 if (!mips_legitimate_address_p (mode, x, false))
2785 x = force_reg (Pmode, x);
2789 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2790 be legitimized in a way that the generic machinery might not expect,
2791 put the new address in *XLOC and return true. MODE is the mode of
2792 the memory being accessed. */
2795 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2798 HOST_WIDE_INT offset;
2800 if (mips_tls_symbol_p (*xloc))
2802 *xloc = mips_legitimize_tls_address (*xloc);
2806 /* See if the address can split into a high part and a LO_SUM. */
2807 if (mips_split_symbol (NULL, *xloc, mode, &addr))
2809 *xloc = mips_force_address (addr, mode);
2813 /* Handle BASE + OFFSET using mips_add_offset. */
2814 mips_split_plus (*xloc, &base, &offset);
2817 if (!mips_valid_base_register_p (base, mode, false))
2818 base = copy_to_mode_reg (Pmode, base);
2819 addr = mips_add_offset (NULL, base, offset);
2820 *xloc = mips_force_address (addr, mode);
2826 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2829 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2831 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2832 enum machine_mode mode;
2833 unsigned int i, num_ops;
2836 mode = GET_MODE (dest);
2837 num_ops = mips_build_integer (codes, value);
2839 /* Apply each binary operation to X. Invariant: X is a legitimate
2840 source operand for a SET pattern. */
2841 x = GEN_INT (codes[0].value);
2842 for (i = 1; i < num_ops; i++)
2844 if (!can_create_pseudo_p ())
2846 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2850 x = force_reg (mode, x);
2851 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2854 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2857 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2858 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2862 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2866 /* Split moves of big integers into smaller pieces. */
2867 if (splittable_const_int_operand (src, mode))
2869 mips_move_integer (dest, dest, INTVAL (src));
2873 /* Split moves of symbolic constants into high/low pairs. */
2874 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2876 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2880 /* Generate the appropriate access sequences for TLS symbols. */
2881 if (mips_tls_symbol_p (src))
2883 mips_emit_move (dest, mips_legitimize_tls_address (src));
2887 /* If we have (const (plus symbol offset)), and that expression cannot
2888 be forced into memory, load the symbol first and add in the offset.
2889 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2890 forced into memory, as it usually produces better code. */
2891 split_const (src, &base, &offset);
2892 if (offset != const0_rtx
2893 && (targetm.cannot_force_const_mem (src)
2894 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2896 base = mips_force_temporary (dest, base);
2897 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2901 src = force_const_mem (mode, src);
2903 /* When using explicit relocs, constant pool references are sometimes
2904 not legitimate addresses. */
2905 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2906 mips_emit_move (dest, src);
2909 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2910 sequence that is valid. */
2913 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2915 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2917 mips_emit_move (dest, force_reg (mode, src));
2921 /* We need to deal with constants that would be legitimate
2922 immediate_operands but aren't legitimate move_operands. */
2923 if (CONSTANT_P (src) && !move_operand (src, mode))
2925 mips_legitimize_const_move (mode, dest, src);
2926 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2932 /* Return true if value X in context CONTEXT is a small-data address
2933 that can be rewritten as a LO_SUM. */
2936 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2938 enum mips_symbol_type symbol_type;
2940 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
2941 && !mips_split_p[SYMBOL_GP_RELATIVE]
2942 && mips_symbolic_constant_p (x, context, &symbol_type)
2943 && symbol_type == SYMBOL_GP_RELATIVE);
2946 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2947 containing MEM, or null if none. */
2950 mips_small_data_pattern_1 (rtx *loc, void *data)
2952 enum mips_symbol_context context;
2954 if (GET_CODE (*loc) == LO_SUM)
2959 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
2964 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2965 return mips_rewrite_small_data_p (*loc, context);
2968 /* Return true if OP refers to small data symbols directly, not through
2972 mips_small_data_pattern_p (rtx op)
2974 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
2977 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2978 DATA is the containing MEM, or null if none. */
2981 mips_rewrite_small_data_1 (rtx *loc, void *data)
2983 enum mips_symbol_context context;
2987 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
2991 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2992 if (mips_rewrite_small_data_p (*loc, context))
2993 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
2995 if (GET_CODE (*loc) == LO_SUM)
3001 /* Rewrite instruction pattern PATTERN so that it refers to small data
3002 using explicit relocations. */
3005 mips_rewrite_small_data (rtx pattern)
3007 pattern = copy_insn (pattern);
3008 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3012 /* We need a lot of little routines to check the range of MIPS16 immediate
3016 m16_check_op (rtx op, int low, int high, int mask)
3018 return (GET_CODE (op) == CONST_INT
3019 && IN_RANGE (INTVAL (op), low, high)
3020 && (INTVAL (op) & mask) == 0);
3024 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3026 return m16_check_op (op, 0x1, 0x8, 0);
3030 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3032 return m16_check_op (op, -0x8, 0x7, 0);
3036 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3038 return m16_check_op (op, -0x7, 0x8, 0);
3042 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3044 return m16_check_op (op, -0x10, 0xf, 0);
3048 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3050 return m16_check_op (op, -0xf, 0x10, 0);
3054 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3056 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3060 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3062 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3066 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3068 return m16_check_op (op, -0x80, 0x7f, 0);
3072 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3074 return m16_check_op (op, -0x7f, 0x80, 0);
3078 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3080 return m16_check_op (op, 0x0, 0xff, 0);
3084 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3086 return m16_check_op (op, -0xff, 0x0, 0);
3090 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3092 return m16_check_op (op, -0x1, 0xfe, 0);
3096 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3098 return m16_check_op (op, 0x0, 0xff << 2, 3);
3102 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3104 return m16_check_op (op, -0xff << 2, 0x0, 3);
3108 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3110 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3114 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3116 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3119 /* The cost of loading values from the constant pool. It should be
3120 larger than the cost of any constant we want to synthesize inline. */
3121 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3123 /* Return the cost of X when used as an operand to the MIPS16 instruction
3124 that implements CODE. Return -1 if there is no such instruction, or if
3125 X is not a valid immediate operand for it. */
3128 mips16_constant_cost (int code, HOST_WIDE_INT x)
3135 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3136 other shifts are extended. The shift patterns truncate the shift
3137 count to the right size, so there are no out-of-range values. */
3138 if (IN_RANGE (x, 1, 8))
3140 return COSTS_N_INSNS (1);
3143 if (IN_RANGE (x, -128, 127))
3145 if (SMALL_OPERAND (x))
3146 return COSTS_N_INSNS (1);
3150 /* Like LE, but reject the always-true case. */
3154 /* We add 1 to the immediate and use SLT. */
3157 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3160 if (IN_RANGE (x, 0, 255))
3162 if (SMALL_OPERAND_UNSIGNED (x))
3163 return COSTS_N_INSNS (1);
3168 /* Equality comparisons with 0 are cheap. */
3178 /* Return true if there is a non-MIPS16 instruction that implements CODE
3179 and if that instruction accepts X as an immediate operand. */
3182 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3189 /* All shift counts are truncated to a valid constant. */
3194 /* Likewise rotates, if the target supports rotates at all. */
3200 /* These instructions take 16-bit unsigned immediates. */
3201 return SMALL_OPERAND_UNSIGNED (x);
3206 /* These instructions take 16-bit signed immediates. */
3207 return SMALL_OPERAND (x);
3213 /* The "immediate" forms of these instructions are really
3214 implemented as comparisons with register 0. */
3219 /* Likewise, meaning that the only valid immediate operand is 1. */
3223 /* We add 1 to the immediate and use SLT. */
3224 return SMALL_OPERAND (x + 1);
3227 /* Likewise SLTU, but reject the always-true case. */
3228 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3232 /* The bit position and size are immediate operands. */
3233 return ISA_HAS_EXT_INS;
3236 /* By default assume that $0 can be used for 0. */
3241 /* Return the cost of binary operation X, given that the instruction
3242 sequence for a word-sized or smaller operation has cost SINGLE_COST
3243 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3246 mips_binary_cost (rtx x, int single_cost, int double_cost)
3250 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3255 + rtx_cost (XEXP (x, 0), 0, !optimize_size)
3256 + rtx_cost (XEXP (x, 1), GET_CODE (x), !optimize_size));
3259 /* Return the cost of floating-point multiplications of mode MODE. */
3262 mips_fp_mult_cost (enum machine_mode mode)
3264 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3267 /* Return the cost of floating-point divisions of mode MODE. */
3270 mips_fp_div_cost (enum machine_mode mode)
3272 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3275 /* Return the cost of sign-extending OP to mode MODE, not including the
3276 cost of OP itself. */
3279 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3282 /* Extended loads are as cheap as unextended ones. */
3285 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3286 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3289 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3290 /* We can use SEB or SEH. */
3291 return COSTS_N_INSNS (1);
3293 /* We need to use a shift left and a shift right. */
3294 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3297 /* Return the cost of zero-extending OP to mode MODE, not including the
3298 cost of OP itself. */
3301 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3304 /* Extended loads are as cheap as unextended ones. */
3307 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3308 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3309 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3311 if (GENERATE_MIPS16E)
3312 /* We can use ZEB or ZEH. */
3313 return COSTS_N_INSNS (1);
3316 /* We need to load 0xff or 0xffff into a register and use AND. */
3317 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3319 /* We can use ANDI. */
3320 return COSTS_N_INSNS (1);
3323 /* Implement TARGET_RTX_COSTS. */
3326 mips_rtx_costs (rtx x, int code, int outer_code, int *total,
3329 enum machine_mode mode = GET_MODE (x);
3330 bool float_mode_p = FLOAT_MODE_P (mode);
3334 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3335 appear in the instruction stream, and the cost of a comparison is
3336 really the cost of the branch or scc condition. At the time of
3337 writing, GCC only uses an explicit outer COMPARE code when optabs
3338 is testing whether a constant is expensive enough to force into a
3339 register. We want optabs to pass such constants through the MIPS
3340 expanders instead, so make all constants very cheap here. */
3341 if (outer_code == COMPARE)
3343 gcc_assert (CONSTANT_P (x));
3351 /* Treat *clear_upper32-style ANDs as having zero cost in the
3352 second operand. The cost is entirely in the first operand.
3354 ??? This is needed because we would otherwise try to CSE
3355 the constant operand. Although that's the right thing for
3356 instructions that continue to be a register operation throughout
3357 compilation, it is disastrous for instructions that could
3358 later be converted into a memory operation. */
3360 && outer_code == AND
3361 && UINTVAL (x) == 0xffffffff)
3369 cost = mips16_constant_cost (outer_code, INTVAL (x));
3378 /* When not optimizing for size, we care more about the cost
3379 of hot code, and hot code is often in a loop. If a constant
3380 operand needs to be forced into a register, we will often be
3381 able to hoist the constant load out of the loop, so the load
3382 should not contribute to the cost. */
3384 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3396 if (force_to_mem_operand (x, VOIDmode))
3398 *total = COSTS_N_INSNS (1);
3401 cost = mips_const_insns (x);
3404 /* If the constant is likely to be stored in a GPR, SETs of
3405 single-insn constants are as cheap as register sets; we
3406 never want to CSE them.
3408 Don't reduce the cost of storing a floating-point zero in
3409 FPRs. If we have a zero in an FPR for other reasons, we
3410 can get better cfg-cleanup and delayed-branch results by
3411 using it consistently, rather than using $0 sometimes and
3412 an FPR at other times. Also, moves between floating-point
3413 registers are sometimes cheaper than (D)MTC1 $0. */
3415 && outer_code == SET
3416 && !(float_mode_p && TARGET_HARD_FLOAT))
3418 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3419 want to CSE the constant itself. It is usually better to
3420 have N copies of the last operation in the sequence and one
3421 shared copy of the other operations. (Note that this is
3422 not true for MIPS16 code, where the final operation in the
3423 sequence is often an extended instruction.)
3425 Also, if we have a CONST_INT, we don't know whether it is
3426 for a word or doubleword operation, so we cannot rely on
3427 the result of mips_build_integer. */
3428 else if (!TARGET_MIPS16
3429 && (outer_code == SET || mode == VOIDmode))
3431 *total = COSTS_N_INSNS (cost);
3434 /* The value will need to be fetched from the constant pool. */
3435 *total = CONSTANT_POOL_COST;
3439 /* If the address is legitimate, return the number of
3440 instructions it needs. */
3442 cost = mips_address_insns (addr, mode, true);
3445 *total = COSTS_N_INSNS (cost + 1);
3448 /* Check for a scaled indexed address. */
3449 if (mips_lwxs_address_p (addr))
3451 *total = COSTS_N_INSNS (2);
3454 /* Otherwise use the default handling. */
3458 *total = COSTS_N_INSNS (6);
3462 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3466 /* Check for a *clear_upper32 pattern and treat it like a zero
3467 extension. See the pattern's comment for details. */
3470 && CONST_INT_P (XEXP (x, 1))
3471 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3473 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3474 + rtx_cost (XEXP (x, 0), 0, speed));
3481 /* Double-word operations use two single-word operations. */
3482 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3490 if (CONSTANT_P (XEXP (x, 1)))
3491 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3493 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3498 *total = mips_cost->fp_add;
3500 *total = COSTS_N_INSNS (4);
3504 /* Low-part immediates need an extended MIPS16 instruction. */
3505 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3506 + rtx_cost (XEXP (x, 0), 0, speed));
3521 /* Branch comparisons have VOIDmode, so use the first operand's
3523 mode = GET_MODE (XEXP (x, 0));
3524 if (FLOAT_MODE_P (mode))
3526 *total = mips_cost->fp_add;
3529 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3534 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3535 && TARGET_FUSED_MADD
3536 && !HONOR_NANS (mode)
3537 && !HONOR_SIGNED_ZEROS (mode))
3539 /* See if we can use NMADD or NMSUB. See mips.md for the
3540 associated patterns. */
3541 rtx op0 = XEXP (x, 0);
3542 rtx op1 = XEXP (x, 1);
3543 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3545 *total = (mips_fp_mult_cost (mode)
3546 + rtx_cost (XEXP (XEXP (op0, 0), 0), 0, speed)
3547 + rtx_cost (XEXP (op0, 1), 0, speed)
3548 + rtx_cost (op1, 0, speed));
3551 if (GET_CODE (op1) == MULT)
3553 *total = (mips_fp_mult_cost (mode)
3554 + rtx_cost (op0, 0, speed)
3555 + rtx_cost (XEXP (op1, 0), 0, speed)
3556 + rtx_cost (XEXP (op1, 1), 0, speed));
3565 /* If this is part of a MADD or MSUB, treat the PLUS as
3568 && TARGET_FUSED_MADD
3569 && GET_CODE (XEXP (x, 0)) == MULT)
3572 *total = mips_cost->fp_add;
3576 /* Double-word operations require three single-word operations and
3577 an SLTU. The MIPS16 version then needs to move the result of
3578 the SLTU from $24 to a MIPS16 register. */
3579 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3580 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3585 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3586 && TARGET_FUSED_MADD
3587 && !HONOR_NANS (mode)
3588 && HONOR_SIGNED_ZEROS (mode))
3590 /* See if we can use NMADD or NMSUB. See mips.md for the
3591 associated patterns. */
3592 rtx op = XEXP (x, 0);
3593 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3594 && GET_CODE (XEXP (op, 0)) == MULT)
3596 *total = (mips_fp_mult_cost (mode)
3597 + rtx_cost (XEXP (XEXP (op, 0), 0), 0, speed)
3598 + rtx_cost (XEXP (XEXP (op, 0), 1), 0, speed)
3599 + rtx_cost (XEXP (op, 1), 0, speed));
3605 *total = mips_cost->fp_add;
3607 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3612 *total = mips_fp_mult_cost (mode);
3613 else if (mode == DImode && !TARGET_64BIT)
3614 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3615 where the mulsidi3 always includes an MFHI and an MFLO. */
3616 *total = (optimize_size
3617 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3618 : mips_cost->int_mult_si * 3 + 6);
3619 else if (optimize_size)
3620 *total = (ISA_HAS_MUL3 ? 1 : 2);
3621 else if (mode == DImode)
3622 *total = mips_cost->int_mult_di;
3624 *total = mips_cost->int_mult_si;
3628 /* Check for a reciprocal. */
3631 && flag_unsafe_math_optimizations
3632 && XEXP (x, 0) == CONST1_RTX (mode))
3634 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3635 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3636 division as being free. */
3637 *total = rtx_cost (XEXP (x, 1), 0, speed);
3639 *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0, speed);
3648 *total = mips_fp_div_cost (mode);
3657 /* It is our responsibility to make division by a power of 2
3658 as cheap as 2 register additions if we want the division
3659 expanders to be used for such operations; see the setting
3660 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3661 should always produce shorter code than using
3662 expand_sdiv2_pow2. */
3664 && CONST_INT_P (XEXP (x, 1))
3665 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3667 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0, speed);
3670 *total = COSTS_N_INSNS (mips_idiv_insns ());
3672 else if (mode == DImode)
3673 *total = mips_cost->int_div_di;
3675 *total = mips_cost->int_div_si;
3679 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3683 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3687 case UNSIGNED_FLOAT:
3690 case FLOAT_TRUNCATE:
3691 *total = mips_cost->fp_add;
3699 /* Implement TARGET_ADDRESS_COST. */
3702 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3704 return mips_address_insns (addr, SImode, false);
3707 /* Return one word of double-word value OP, taking into account the fixed
3708 endianness of certain registers. HIGH_P is true to select the high part,
3709 false to select the low part. */
3712 mips_subword (rtx op, bool high_p)
3714 unsigned int byte, offset;
3715 enum machine_mode mode;
3717 mode = GET_MODE (op);
3718 if (mode == VOIDmode)
3719 mode = TARGET_64BIT ? TImode : DImode;
3721 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3722 byte = UNITS_PER_WORD;
3726 if (FP_REG_RTX_P (op))
3728 /* Paired FPRs are always ordered little-endian. */
3729 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3730 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3734 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3736 return simplify_gen_subreg (word_mode, op, mode, byte);
3739 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3742 mips_split_64bit_move_p (rtx dest, rtx src)
3747 /* FPR-to-FPR moves can be done in a single instruction, if they're
3749 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3752 /* Check for floating-point loads and stores. */
3753 if (ISA_HAS_LDC1_SDC1)
3755 if (FP_REG_RTX_P (dest) && MEM_P (src))
3757 if (FP_REG_RTX_P (src) && MEM_P (dest))
3763 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3764 this function handles 64-bit moves for which mips_split_64bit_move_p
3765 holds. For 64-bit targets, this function handles 128-bit moves. */
3768 mips_split_doubleword_move (rtx dest, rtx src)
3772 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3774 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3775 emit_insn (gen_move_doubleword_fprdi (dest, src));
3776 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3777 emit_insn (gen_move_doubleword_fprdf (dest, src));
3778 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3779 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3780 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
3781 emit_insn (gen_move_doubleword_fprv2si (dest, src));
3782 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
3783 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
3784 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
3785 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
3786 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3787 emit_insn (gen_move_doubleword_fprtf (dest, src));
3791 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
3793 low_dest = mips_subword (dest, false);
3794 mips_emit_move (low_dest, mips_subword (src, false));
3796 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
3798 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
3800 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
3802 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
3804 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
3806 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
3810 /* The operation can be split into two normal moves. Decide in
3811 which order to do them. */
3812 low_dest = mips_subword (dest, false);
3813 if (REG_P (low_dest)
3814 && reg_overlap_mentioned_p (low_dest, src))
3816 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3817 mips_emit_move (low_dest, mips_subword (src, false));
3821 mips_emit_move (low_dest, mips_subword (src, false));
3822 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3827 /* Return the appropriate instructions to move SRC into DEST. Assume
3828 that SRC is operand 1 and DEST is operand 0. */
3831 mips_output_move (rtx dest, rtx src)
3833 enum rtx_code dest_code, src_code;
3834 enum machine_mode mode;
3835 enum mips_symbol_type symbol_type;
3838 dest_code = GET_CODE (dest);
3839 src_code = GET_CODE (src);
3840 mode = GET_MODE (dest);
3841 dbl_p = (GET_MODE_SIZE (mode) == 8);
3843 if (dbl_p && mips_split_64bit_move_p (dest, src))
3846 if ((src_code == REG && GP_REG_P (REGNO (src)))
3847 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
3849 if (dest_code == REG)
3851 if (GP_REG_P (REGNO (dest)))
3852 return "move\t%0,%z1";
3854 /* Moves to HI are handled by special .md insns. */
3855 if (REGNO (dest) == LO_REGNUM)
3858 if (DSP_ACC_REG_P (REGNO (dest)))
3860 static char retval[] = "mt__\t%z1,%q0";
3862 retval[2] = reg_names[REGNO (dest)][4];
3863 retval[3] = reg_names[REGNO (dest)][5];
3867 if (FP_REG_P (REGNO (dest)))
3868 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3870 if (ALL_COP_REG_P (REGNO (dest)))
3872 static char retval[] = "dmtc_\t%z1,%0";
3874 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3875 return dbl_p ? retval : retval + 1;
3878 if (dest_code == MEM)
3879 switch (GET_MODE_SIZE (mode))
3881 case 1: return "sb\t%z1,%0";
3882 case 2: return "sh\t%z1,%0";
3883 case 4: return "sw\t%z1,%0";
3884 case 8: return "sd\t%z1,%0";
3887 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3889 if (src_code == REG)
3891 /* Moves from HI are handled by special .md insns. */
3892 if (REGNO (src) == LO_REGNUM)
3894 /* When generating VR4120 or VR4130 code, we use MACC and
3895 DMACC instead of MFLO. This avoids both the normal
3896 MIPS III HI/LO hazards and the errata related to
3899 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
3903 if (DSP_ACC_REG_P (REGNO (src)))
3905 static char retval[] = "mf__\t%0,%q1";
3907 retval[2] = reg_names[REGNO (src)][4];
3908 retval[3] = reg_names[REGNO (src)][5];
3912 if (FP_REG_P (REGNO (src)))
3913 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3915 if (ALL_COP_REG_P (REGNO (src)))
3917 static char retval[] = "dmfc_\t%0,%1";
3919 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3920 return dbl_p ? retval : retval + 1;
3923 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3924 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3927 if (src_code == MEM)
3928 switch (GET_MODE_SIZE (mode))
3930 case 1: return "lbu\t%0,%1";
3931 case 2: return "lhu\t%0,%1";
3932 case 4: return "lw\t%0,%1";
3933 case 8: return "ld\t%0,%1";
3936 if (src_code == CONST_INT)
3938 /* Don't use the X format for the operand itself, because that
3939 will give out-of-range numbers for 64-bit hosts and 32-bit
3942 return "li\t%0,%1\t\t\t# %X1";
3944 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
3947 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
3951 if (src_code == HIGH)
3952 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
3954 if (CONST_GP_P (src))
3955 return "move\t%0,%1";
3957 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
3958 && mips_lo_relocs[symbol_type] != 0)
3960 /* A signed 16-bit constant formed by applying a relocation
3961 operator to a symbolic address. */
3962 gcc_assert (!mips_split_p[symbol_type]);
3963 return "li\t%0,%R1";
3966 if (symbolic_operand (src, VOIDmode))
3968 gcc_assert (TARGET_MIPS16
3969 ? TARGET_MIPS16_TEXT_LOADS
3970 : !TARGET_EXPLICIT_RELOCS);
3971 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
3974 if (src_code == REG && FP_REG_P (REGNO (src)))
3976 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3978 if (GET_MODE (dest) == V2SFmode)
3979 return "mov.ps\t%0,%1";
3981 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
3984 if (dest_code == MEM)
3985 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
3987 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3989 if (src_code == MEM)
3990 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
3992 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3994 static char retval[] = "l_c_\t%0,%1";
3996 retval[1] = (dbl_p ? 'd' : 'w');
3997 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4000 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4002 static char retval[] = "s_c_\t%1,%0";
4004 retval[1] = (dbl_p ? 'd' : 'w');
4005 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4011 /* Return true if CMP1 is a suitable second operand for integer ordering
4012 test CODE. See also the *sCC patterns in mips.md. */
4015 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4021 return reg_or_0_operand (cmp1, VOIDmode);
4025 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4029 return arith_operand (cmp1, VOIDmode);
4032 return sle_operand (cmp1, VOIDmode);
4035 return sleu_operand (cmp1, VOIDmode);
4042 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4043 integer ordering test *CODE, or if an equivalent combination can
4044 be formed by adjusting *CODE and *CMP1. When returning true, update
4045 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4049 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4050 enum machine_mode mode)
4052 HOST_WIDE_INT plus_one;
4054 if (mips_int_order_operand_ok_p (*code, *cmp1))
4057 if (GET_CODE (*cmp1) == CONST_INT)
4061 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4062 if (INTVAL (*cmp1) < plus_one)
4065 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4071 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4075 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4086 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4087 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4088 is nonnull, it's OK to set TARGET to the inverse of the result and
4089 flip *INVERT_PTR instead. */
4092 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4093 rtx target, rtx cmp0, rtx cmp1)
4095 enum machine_mode mode;
4097 /* First see if there is a MIPS instruction that can do this operation.
4098 If not, try doing the same for the inverse operation. If that also
4099 fails, force CMP1 into a register and try again. */
4100 mode = GET_MODE (cmp0);
4101 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4102 mips_emit_binary (code, target, cmp0, cmp1);
4105 enum rtx_code inv_code = reverse_condition (code);
4106 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4108 cmp1 = force_reg (mode, cmp1);
4109 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4111 else if (invert_ptr == 0)
4115 inv_target = mips_force_binary (GET_MODE (target),
4116 inv_code, cmp0, cmp1);
4117 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4121 *invert_ptr = !*invert_ptr;
4122 mips_emit_binary (inv_code, target, cmp0, cmp1);
4127 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4128 The register will have the same mode as CMP0. */
4131 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4133 if (cmp1 == const0_rtx)
4136 if (uns_arith_operand (cmp1, VOIDmode))
4137 return expand_binop (GET_MODE (cmp0), xor_optab,
4138 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4140 return expand_binop (GET_MODE (cmp0), sub_optab,
4141 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4144 /* Convert *CODE into a code that can be used in a floating-point
4145 scc instruction (C.cond.fmt). Return true if the values of
4146 the condition code registers will be inverted, with 0 indicating
4147 that the condition holds. */
4150 mips_reversed_fp_cond (enum rtx_code *code)
4157 *code = reverse_condition_maybe_unordered (*code);
4165 /* Convert a comparison into something that can be used in a branch or
4166 conditional move. cmp_operands[0] and cmp_operands[1] are the values
4167 being compared and *CODE is the code used to compare them.
4169 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4170 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4171 otherwise any standard branch condition can be used. The standard branch
4174 - EQ or NE between two registers.
4175 - any comparison between a register and zero. */
4178 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4180 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
4182 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
4184 *op0 = cmp_operands[0];
4185 *op1 = cmp_operands[1];
4187 else if (*code == EQ || *code == NE)
4191 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
4196 *op0 = cmp_operands[0];
4197 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
4202 /* The comparison needs a separate scc instruction. Store the
4203 result of the scc in *OP0 and compare it against zero. */
4204 bool invert = false;
4205 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
4206 mips_emit_int_order_test (*code, &invert, *op0,
4207 cmp_operands[0], cmp_operands[1]);
4208 *code = (invert ? EQ : NE);
4212 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
4214 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4215 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
4221 enum rtx_code cmp_code;
4223 /* Floating-point tests use a separate C.cond.fmt comparison to
4224 set a condition code register. The branch or conditional move
4225 will then compare that register against zero.
4227 Set CMP_CODE to the code of the comparison instruction and
4228 *CODE to the code that the branch or move should use. */
4230 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4232 ? gen_reg_rtx (CCmode)
4233 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4235 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
4239 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
4240 Store the result in TARGET and return true if successful.
4242 On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */
4245 mips_expand_scc (enum rtx_code code, rtx target)
4247 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
4250 if (code == EQ || code == NE)
4253 && reg_imm10_operand (cmp_operands[1], GET_MODE (cmp_operands[1])))
4254 mips_emit_binary (code, target, cmp_operands[0], cmp_operands[1]);
4257 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
4258 mips_emit_binary (code, target, zie, const0_rtx);
4262 mips_emit_int_order_test (code, 0, target,
4263 cmp_operands[0], cmp_operands[1]);
4267 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
4268 CODE and jump to OPERANDS[0] if the condition holds. */
4271 mips_expand_conditional_branch (rtx *operands, enum rtx_code code)
4273 rtx op0, op1, condition;
4275 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4276 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4277 emit_jump_insn (gen_condjump (condition, operands[0]));
4282 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4283 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4286 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4287 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4292 reversed_p = mips_reversed_fp_cond (&cond);
4293 cmp_result = gen_reg_rtx (CCV2mode);
4294 emit_insn (gen_scc_ps (cmp_result,
4295 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4297 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4300 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4304 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
4305 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
4306 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4309 mips_expand_conditional_move (rtx *operands)
4314 code = GET_CODE (operands[1]);
4315 mips_emit_compare (&code, &op0, &op1, true);
4316 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1),
4317 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4318 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4319 operands[2], operands[3])));
4322 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
4323 then trap if the condition holds. */
4326 mips_expand_conditional_trap (enum rtx_code code)
4329 enum machine_mode mode;
4331 /* MIPS conditional trap instructions don't have GT or LE flavors,
4332 so we must swap the operands and convert to LT and GE respectively. */
4339 code = swap_condition (code);
4340 op0 = cmp_operands[1];
4341 op1 = cmp_operands[0];
4345 op0 = cmp_operands[0];
4346 op1 = cmp_operands[1];
4350 mode = GET_MODE (cmp_operands[0]);
4351 op0 = force_reg (mode, op0);
4352 if (!arith_operand (op1, mode))
4353 op1 = force_reg (mode, op1);
4355 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4356 gen_rtx_fmt_ee (code, mode, op0, op1),
4360 /* Initialize *CUM for a call to a function of type FNTYPE. */
4363 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4365 memset (cum, 0, sizeof (*cum));
4366 cum->prototype = (fntype && prototype_p (fntype));
4367 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4370 /* Fill INFO with information about a single argument. CUM is the
4371 cumulative state for earlier arguments. MODE is the mode of this
4372 argument and TYPE is its type (if known). NAMED is true if this
4373 is a named (fixed) argument rather than a variable one. */
4376 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4377 enum machine_mode mode, tree type, int named)
4379 bool doubleword_aligned_p;
4380 unsigned int num_bytes, num_words, max_regs;
4382 /* Work out the size of the argument. */
4383 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4384 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4386 /* Decide whether it should go in a floating-point register, assuming
4387 one is free. Later code checks for availability.
4389 The checks against UNITS_PER_FPVALUE handle the soft-float and
4390 single-float cases. */
4394 /* The EABI conventions have traditionally been defined in terms
4395 of TYPE_MODE, regardless of the actual type. */
4396 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4397 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4398 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4403 /* Only leading floating-point scalars are passed in
4404 floating-point registers. We also handle vector floats the same
4405 say, which is OK because they are not covered by the standard ABI. */
4406 info->fpr_p = (!cum->gp_reg_found
4407 && cum->arg_number < 2
4409 || SCALAR_FLOAT_TYPE_P (type)
4410 || VECTOR_FLOAT_TYPE_P (type))
4411 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4412 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4413 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4418 /* Scalar, complex and vector floating-point types are passed in
4419 floating-point registers, as long as this is a named rather
4420 than a variable argument. */
4421 info->fpr_p = (named
4422 && (type == 0 || FLOAT_TYPE_P (type))
4423 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4424 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4425 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4426 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4428 /* ??? According to the ABI documentation, the real and imaginary
4429 parts of complex floats should be passed in individual registers.
4430 The real and imaginary parts of stack arguments are supposed
4431 to be contiguous and there should be an extra word of padding
4434 This has two problems. First, it makes it impossible to use a
4435 single "void *" va_list type, since register and stack arguments
4436 are passed differently. (At the time of writing, MIPSpro cannot
4437 handle complex float varargs correctly.) Second, it's unclear
4438 what should happen when there is only one register free.
4440 For now, we assume that named complex floats should go into FPRs
4441 if there are two FPRs free, otherwise they should be passed in the
4442 same way as a struct containing two floats. */
4444 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4445 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4447 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4448 info->fpr_p = false;
4458 /* See whether the argument has doubleword alignment. */
4459 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4461 /* Set REG_OFFSET to the register count we're interested in.
4462 The EABI allocates the floating-point registers separately,
4463 but the other ABIs allocate them like integer registers. */
4464 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4468 /* Advance to an even register if the argument is doubleword-aligned. */
4469 if (doubleword_aligned_p)
4470 info->reg_offset += info->reg_offset & 1;
4472 /* Work out the offset of a stack argument. */
4473 info->stack_offset = cum->stack_words;
4474 if (doubleword_aligned_p)
4475 info->stack_offset += info->stack_offset & 1;
4477 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4479 /* Partition the argument between registers and stack. */
4480 info->reg_words = MIN (num_words, max_regs);
4481 info->stack_words = num_words - info->reg_words;
4484 /* INFO describes a register argument that has the normal format for the
4485 argument's mode. Return the register it uses, assuming that FPRs are
4486 available if HARD_FLOAT_P. */
4489 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4491 if (!info->fpr_p || !hard_float_p)
4492 return GP_ARG_FIRST + info->reg_offset;
4493 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4494 /* In o32, the second argument is always passed in $f14
4495 for TARGET_DOUBLE_FLOAT, regardless of whether the
4496 first argument was a word or doubleword. */
4497 return FP_ARG_FIRST + 2;
4499 return FP_ARG_FIRST + info->reg_offset;
4502 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4505 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4507 return !TARGET_OLDABI;
4510 /* Implement FUNCTION_ARG. */
4513 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4514 tree type, int named)
4516 struct mips_arg_info info;
4518 /* We will be called with a mode of VOIDmode after the last argument
4519 has been seen. Whatever we return will be passed to the call expander.
4520 If we need a MIPS16 fp_code, return a REG with the code stored as
4522 if (mode == VOIDmode)
4524 if (TARGET_MIPS16 && cum->fp_code != 0)
4525 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4530 mips_get_arg_info (&info, cum, mode, type, named);
4532 /* Return straight away if the whole argument is passed on the stack. */
4533 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4536 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4537 contains a double in its entirety, then that 64-bit chunk is passed
4538 in a floating-point register. */
4540 && TARGET_HARD_FLOAT
4543 && TREE_CODE (type) == RECORD_TYPE
4544 && TYPE_SIZE_UNIT (type)
4545 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4549 /* First check to see if there is any such field. */
4550 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4551 if (TREE_CODE (field) == FIELD_DECL
4552 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4553 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4554 && host_integerp (bit_position (field), 0)
4555 && int_bit_position (field) % BITS_PER_WORD == 0)
4560 /* Now handle the special case by returning a PARALLEL
4561 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4562 chunks are passed in registers. */
4564 HOST_WIDE_INT bitpos;
4567 /* assign_parms checks the mode of ENTRY_PARM, so we must
4568 use the actual mode here. */
4569 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4572 field = TYPE_FIELDS (type);
4573 for (i = 0; i < info.reg_words; i++)
4577 for (; field; field = TREE_CHAIN (field))
4578 if (TREE_CODE (field) == FIELD_DECL
4579 && int_bit_position (field) >= bitpos)
4583 && int_bit_position (field) == bitpos
4584 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4585 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4586 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4588 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4591 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4592 GEN_INT (bitpos / BITS_PER_UNIT));
4594 bitpos += BITS_PER_WORD;
4600 /* Handle the n32/n64 conventions for passing complex floating-point
4601 arguments in FPR pairs. The real part goes in the lower register
4602 and the imaginary part goes in the upper register. */
4605 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4608 enum machine_mode inner;
4611 inner = GET_MODE_INNER (mode);
4612 regno = FP_ARG_FIRST + info.reg_offset;
4613 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4615 /* Real part in registers, imaginary part on stack. */
4616 gcc_assert (info.stack_words == info.reg_words);
4617 return gen_rtx_REG (inner, regno);
4621 gcc_assert (info.stack_words == 0);
4622 real = gen_rtx_EXPR_LIST (VOIDmode,
4623 gen_rtx_REG (inner, regno),
4625 imag = gen_rtx_EXPR_LIST (VOIDmode,
4627 regno + info.reg_words / 2),
4628 GEN_INT (GET_MODE_SIZE (inner)));
4629 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4633 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4636 /* Implement FUNCTION_ARG_ADVANCE. */
4639 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4640 tree type, int named)
4642 struct mips_arg_info info;
4644 mips_get_arg_info (&info, cum, mode, type, named);
4647 cum->gp_reg_found = true;
4649 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4650 an explanation of what this code does. It assumes that we're using
4651 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4653 if (cum->arg_number < 2 && info.fpr_p)
4654 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4656 /* Advance the register count. This has the effect of setting
4657 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4658 argument required us to skip the final GPR and pass the whole
4659 argument on the stack. */
4660 if (mips_abi != ABI_EABI || !info.fpr_p)
4661 cum->num_gprs = info.reg_offset + info.reg_words;
4662 else if (info.reg_words > 0)
4663 cum->num_fprs += MAX_FPRS_PER_FMT;
4665 /* Advance the stack word count. */
4666 if (info.stack_words > 0)
4667 cum->stack_words = info.stack_offset + info.stack_words;
4672 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4675 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4676 enum machine_mode mode, tree type, bool named)
4678 struct mips_arg_info info;
4680 mips_get_arg_info (&info, cum, mode, type, named);
4681 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4684 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4685 PARM_BOUNDARY bits of alignment, but will be given anything up
4686 to STACK_BOUNDARY bits if the type requires it. */
4689 mips_function_arg_boundary (enum machine_mode mode, tree type)
4691 unsigned int alignment;
4693 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4694 if (alignment < PARM_BOUNDARY)
4695 alignment = PARM_BOUNDARY;
4696 if (alignment > STACK_BOUNDARY)
4697 alignment = STACK_BOUNDARY;
4701 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4702 upward rather than downward. In other words, return true if the
4703 first byte of the stack slot has useful data, false if the last
4707 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4709 /* On little-endian targets, the first byte of every stack argument
4710 is passed in the first byte of the stack slot. */
4711 if (!BYTES_BIG_ENDIAN)
4714 /* Otherwise, integral types are padded downward: the last byte of a
4715 stack argument is passed in the last byte of the stack slot. */
4717 ? (INTEGRAL_TYPE_P (type)
4718 || POINTER_TYPE_P (type)
4719 || FIXED_POINT_TYPE_P (type))
4720 : (SCALAR_INT_MODE_P (mode)
4721 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4724 /* Big-endian o64 pads floating-point arguments downward. */
4725 if (mips_abi == ABI_O64)
4726 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4729 /* Other types are padded upward for o32, o64, n32 and n64. */
4730 if (mips_abi != ABI_EABI)
4733 /* Arguments smaller than a stack slot are padded downward. */
4734 if (mode != BLKmode)
4735 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4737 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4740 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4741 if the least significant byte of the register has useful data. Return
4742 the opposite if the most significant byte does. */
4745 mips_pad_reg_upward (enum machine_mode mode, tree type)
4747 /* No shifting is required for floating-point arguments. */
4748 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4749 return !BYTES_BIG_ENDIAN;
4751 /* Otherwise, apply the same padding to register arguments as we do
4752 to stack arguments. */
4753 return mips_pad_arg_upward (mode, type);
4756 /* Return nonzero when an argument must be passed by reference. */
4759 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4760 enum machine_mode mode, const_tree type,
4761 bool named ATTRIBUTE_UNUSED)
4763 if (mips_abi == ABI_EABI)
4767 /* ??? How should SCmode be handled? */
4768 if (mode == DImode || mode == DFmode
4769 || mode == DQmode || mode == UDQmode
4770 || mode == DAmode || mode == UDAmode)
4773 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4774 return size == -1 || size > UNITS_PER_WORD;
4778 /* If we have a variable-sized parameter, we have no choice. */
4779 return targetm.calls.must_pass_in_stack (mode, type);
4783 /* Implement TARGET_CALLEE_COPIES. */
4786 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4787 enum machine_mode mode ATTRIBUTE_UNUSED,
4788 const_tree type ATTRIBUTE_UNUSED, bool named)
4790 return mips_abi == ABI_EABI && named;
4793 /* See whether VALTYPE is a record whose fields should be returned in
4794 floating-point registers. If so, return the number of fields and
4795 list them in FIELDS (which should have two elements). Return 0
4798 For n32 & n64, a structure with one or two fields is returned in
4799 floating-point registers as long as every field has a floating-point
4803 mips_fpr_return_fields (const_tree valtype, tree *fields)
4811 if (TREE_CODE (valtype) != RECORD_TYPE)
4815 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4817 if (TREE_CODE (field) != FIELD_DECL)
4820 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
4826 fields[i++] = field;
4831 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4832 a value in the most significant part of $2/$3 if:
4834 - the target is big-endian;
4836 - the value has a structure or union type (we generalize this to
4837 cover aggregates from other languages too); and
4839 - the structure is not returned in floating-point registers. */
4842 mips_return_in_msb (const_tree valtype)
4846 return (TARGET_NEWABI
4847 && TARGET_BIG_ENDIAN
4848 && AGGREGATE_TYPE_P (valtype)
4849 && mips_fpr_return_fields (valtype, fields) == 0);
4852 /* Return true if the function return value MODE will get returned in a
4853 floating-point register. */
4856 mips_return_mode_in_fpr_p (enum machine_mode mode)
4858 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4859 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4860 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4861 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4864 /* Return the representation of an FPR return register when the
4865 value being returned in FP_RETURN has mode VALUE_MODE and the
4866 return type itself has mode TYPE_MODE. On NewABI targets,
4867 the two modes may be different for structures like:
4869 struct __attribute__((packed)) foo { float f; }
4871 where we return the SFmode value of "f" in FP_RETURN, but where
4872 the structure itself has mode BLKmode. */
4875 mips_return_fpr_single (enum machine_mode type_mode,
4876 enum machine_mode value_mode)
4880 x = gen_rtx_REG (value_mode, FP_RETURN);
4881 if (type_mode != value_mode)
4883 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
4884 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
4889 /* Return a composite value in a pair of floating-point registers.
4890 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4891 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4894 For n32 & n64, $f0 always holds the first value and $f2 the second.
4895 Otherwise the values are packed together as closely as possible. */
4898 mips_return_fpr_pair (enum machine_mode mode,
4899 enum machine_mode mode1, HOST_WIDE_INT offset1,
4900 enum machine_mode mode2, HOST_WIDE_INT offset2)
4904 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4905 return gen_rtx_PARALLEL
4908 gen_rtx_EXPR_LIST (VOIDmode,
4909 gen_rtx_REG (mode1, FP_RETURN),
4911 gen_rtx_EXPR_LIST (VOIDmode,
4912 gen_rtx_REG (mode2, FP_RETURN + inc),
4913 GEN_INT (offset2))));
4917 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4918 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4919 VALTYPE is null and MODE is the mode of the return value. */
4922 mips_function_value (const_tree valtype, enum machine_mode mode)
4929 mode = TYPE_MODE (valtype);
4930 unsigned_p = TYPE_UNSIGNED (valtype);
4932 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4933 we must promote the mode just as PROMOTE_MODE does. */
4934 mode = promote_mode (valtype, mode, &unsigned_p, 1);
4936 /* Handle structures whose fields are returned in $f0/$f2. */
4937 switch (mips_fpr_return_fields (valtype, fields))
4940 return mips_return_fpr_single (mode,
4941 TYPE_MODE (TREE_TYPE (fields[0])));
4944 return mips_return_fpr_pair (mode,
4945 TYPE_MODE (TREE_TYPE (fields[0])),
4946 int_byte_position (fields[0]),
4947 TYPE_MODE (TREE_TYPE (fields[1])),
4948 int_byte_position (fields[1]));
4951 /* If a value is passed in the most significant part of a register, see
4952 whether we have to round the mode up to a whole number of words. */
4953 if (mips_return_in_msb (valtype))
4955 HOST_WIDE_INT size = int_size_in_bytes (valtype);
4956 if (size % UNITS_PER_WORD != 0)
4958 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4959 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4963 /* For EABI, the class of return register depends entirely on MODE.
4964 For example, "struct { some_type x; }" and "union { some_type x; }"
4965 are returned in the same way as a bare "some_type" would be.
4966 Other ABIs only use FPRs for scalar, complex or vector types. */
4967 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
4968 return gen_rtx_REG (mode, GP_RETURN);
4973 /* Handle long doubles for n32 & n64. */
4975 return mips_return_fpr_pair (mode,
4977 DImode, GET_MODE_SIZE (mode) / 2);
4979 if (mips_return_mode_in_fpr_p (mode))
4981 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4982 return mips_return_fpr_pair (mode,
4983 GET_MODE_INNER (mode), 0,
4984 GET_MODE_INNER (mode),
4985 GET_MODE_SIZE (mode) / 2);
4987 return gen_rtx_REG (mode, FP_RETURN);
4991 return gen_rtx_REG (mode, GP_RETURN);
4994 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
4995 all BLKmode objects are returned in memory. Under the n32, n64
4996 and embedded ABIs, small structures are returned in a register.
4997 Objects with varying size must still be returned in memory, of
5001 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5003 return (TARGET_OLDABI
5004 ? TYPE_MODE (type) == BLKmode
5005 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5008 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5011 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5012 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5015 CUMULATIVE_ARGS local_cum;
5016 int gp_saved, fp_saved;
5018 /* The caller has advanced CUM up to, but not beyond, the last named
5019 argument. Advance a local copy of CUM past the last "real" named
5020 argument, to find out how many registers are left over. */
5022 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5024 /* Found out how many registers we need to save. */
5025 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5026 fp_saved = (EABI_FLOAT_VARARGS_P
5027 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5036 ptr = plus_constant (virtual_incoming_args_rtx,
5037 REG_PARM_STACK_SPACE (cfun->decl)
5038 - gp_saved * UNITS_PER_WORD);
5039 mem = gen_frame_mem (BLKmode, ptr);
5040 set_mem_alias_set (mem, get_varargs_alias_set ());
5042 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5047 /* We can't use move_block_from_reg, because it will use
5049 enum machine_mode mode;
5052 /* Set OFF to the offset from virtual_incoming_args_rtx of
5053 the first float register. The FP save area lies below
5054 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5055 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5056 off -= fp_saved * UNITS_PER_FPREG;
5058 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5060 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5061 i += MAX_FPRS_PER_FMT)
5065 ptr = plus_constant (virtual_incoming_args_rtx, off);
5066 mem = gen_frame_mem (mode, ptr);
5067 set_mem_alias_set (mem, get_varargs_alias_set ());
5068 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5069 off += UNITS_PER_HWFPVALUE;
5073 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5074 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5075 + fp_saved * UNITS_PER_FPREG);
5078 /* Implement TARGET_BUILTIN_VA_LIST. */
5081 mips_build_builtin_va_list (void)
5083 if (EABI_FLOAT_VARARGS_P)
5085 /* We keep 3 pointers, and two offsets.
5087 Two pointers are to the overflow area, which starts at the CFA.
5088 One of these is constant, for addressing into the GPR save area
5089 below it. The other is advanced up the stack through the
5092 The third pointer is to the bottom of the GPR save area.
5093 Since the FPR save area is just below it, we can address
5094 FPR slots off this pointer.
5096 We also keep two one-byte offsets, which are to be subtracted
5097 from the constant pointers to yield addresses in the GPR and
5098 FPR save areas. These are downcounted as float or non-float
5099 arguments are used, and when they get to zero, the argument
5100 must be obtained from the overflow region. */
5101 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5104 record = lang_hooks.types.make_type (RECORD_TYPE);
5106 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
5108 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
5110 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
5112 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
5113 unsigned_char_type_node);
5114 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
5115 unsigned_char_type_node);
5116 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5117 warn on every user file. */
5118 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5119 array = build_array_type (unsigned_char_type_node,
5120 build_index_type (index));
5121 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
5123 DECL_FIELD_CONTEXT (f_ovfl) = record;
5124 DECL_FIELD_CONTEXT (f_gtop) = record;
5125 DECL_FIELD_CONTEXT (f_ftop) = record;
5126 DECL_FIELD_CONTEXT (f_goff) = record;
5127 DECL_FIELD_CONTEXT (f_foff) = record;
5128 DECL_FIELD_CONTEXT (f_res) = record;
5130 TYPE_FIELDS (record) = f_ovfl;
5131 TREE_CHAIN (f_ovfl) = f_gtop;
5132 TREE_CHAIN (f_gtop) = f_ftop;
5133 TREE_CHAIN (f_ftop) = f_goff;
5134 TREE_CHAIN (f_goff) = f_foff;
5135 TREE_CHAIN (f_foff) = f_res;
5137 layout_type (record);
5140 else if (TARGET_IRIX && TARGET_IRIX6)
5141 /* On IRIX 6, this type is 'char *'. */
5142 return build_pointer_type (char_type_node);
5144 /* Otherwise, we use 'void *'. */
5145 return ptr_type_node;
5148 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5151 mips_va_start (tree valist, rtx nextarg)
5153 if (EABI_FLOAT_VARARGS_P)
5155 const CUMULATIVE_ARGS *cum;
5156 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5157 tree ovfl, gtop, ftop, goff, foff;
5159 int gpr_save_area_size;
5160 int fpr_save_area_size;
5163 cum = &crtl->args.info;
5165 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5167 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5169 f_ovfl = TYPE_FIELDS (va_list_type_node);
5170 f_gtop = TREE_CHAIN (f_ovfl);
5171 f_ftop = TREE_CHAIN (f_gtop);
5172 f_goff = TREE_CHAIN (f_ftop);
5173 f_foff = TREE_CHAIN (f_goff);
5175 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5177 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5179 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5181 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5183 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5186 /* Emit code to initialize OVFL, which points to the next varargs
5187 stack argument. CUM->STACK_WORDS gives the number of stack
5188 words used by named arguments. */
5189 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5190 if (cum->stack_words > 0)
5191 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5192 size_int (cum->stack_words * UNITS_PER_WORD));
5193 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5194 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5196 /* Emit code to initialize GTOP, the top of the GPR save area. */
5197 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5198 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5199 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5201 /* Emit code to initialize FTOP, the top of the FPR save area.
5202 This address is gpr_save_area_bytes below GTOP, rounded
5203 down to the next fp-aligned boundary. */
5204 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5205 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5206 fpr_offset &= -UNITS_PER_FPVALUE;
5208 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5209 size_int (-fpr_offset));
5210 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5211 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5213 /* Emit code to initialize GOFF, the offset from GTOP of the
5214 next GPR argument. */
5215 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5216 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5217 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5219 /* Likewise emit code to initialize FOFF, the offset from FTOP
5220 of the next FPR argument. */
5221 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5222 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5223 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5227 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5228 std_expand_builtin_va_start (valist, nextarg);
5232 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5235 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5241 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5243 type = build_pointer_type (type);
5245 if (!EABI_FLOAT_VARARGS_P)
5246 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5249 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5250 tree ovfl, top, off, align;
5251 HOST_WIDE_INT size, rsize, osize;
5254 f_ovfl = TYPE_FIELDS (va_list_type_node);
5255 f_gtop = TREE_CHAIN (f_ovfl);
5256 f_ftop = TREE_CHAIN (f_gtop);
5257 f_goff = TREE_CHAIN (f_ftop);
5258 f_foff = TREE_CHAIN (f_goff);
5262 TOP be the top of the GPR or FPR save area;
5263 OFF be the offset from TOP of the next register;
5264 ADDR_RTX be the address of the argument;
5265 SIZE be the number of bytes in the argument type;
5266 RSIZE be the number of bytes used to store the argument
5267 when it's in the register save area; and
5268 OSIZE be the number of bytes used to store it when it's
5269 in the stack overflow area.
5271 The code we want is:
5273 1: off &= -rsize; // round down
5276 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5281 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5282 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5286 [1] and [9] can sometimes be optimized away. */
5288 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5290 size = int_size_in_bytes (type);
5292 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5293 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5295 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5296 unshare_expr (valist), f_ftop, NULL_TREE);
5297 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5298 unshare_expr (valist), f_foff, NULL_TREE);
5300 /* When va_start saves FPR arguments to the stack, each slot
5301 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5302 argument's precision. */
5303 rsize = UNITS_PER_HWFPVALUE;
5305 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5306 (= PARM_BOUNDARY bits). This can be different from RSIZE
5309 (1) On 32-bit targets when TYPE is a structure such as:
5311 struct s { float f; };
5313 Such structures are passed in paired FPRs, so RSIZE
5314 will be 8 bytes. However, the structure only takes
5315 up 4 bytes of memory, so OSIZE will only be 4.
5317 (2) In combinations such as -mgp64 -msingle-float
5318 -fshort-double. Doubles passed in registers will then take
5319 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5320 stack take up UNITS_PER_WORD bytes. */
5321 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5325 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5326 unshare_expr (valist), f_gtop, NULL_TREE);
5327 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5328 unshare_expr (valist), f_goff, NULL_TREE);
5329 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5330 if (rsize > UNITS_PER_WORD)
5332 /* [1] Emit code for: off &= -rsize. */
5333 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5334 build_int_cst (TREE_TYPE (off), -rsize));
5335 gimplify_assign (unshare_expr (off), t, pre_p);
5340 /* [2] Emit code to branch if off == 0. */
5341 t = build2 (NE_EXPR, boolean_type_node, off,
5342 build_int_cst (TREE_TYPE (off), 0));
5343 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5345 /* [5] Emit code for: off -= rsize. We do this as a form of
5346 post-decrement not available to C. */
5347 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5348 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5350 /* [4] Emit code for:
5351 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5352 t = fold_convert (sizetype, t);
5353 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5354 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5355 if (BYTES_BIG_ENDIAN && rsize > size)
5357 u = size_int (rsize - size);
5358 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5360 COND_EXPR_THEN (addr) = t;
5362 if (osize > UNITS_PER_WORD)
5364 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5365 u = size_int (osize - 1);
5366 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5367 unshare_expr (ovfl), u);
5368 t = fold_convert (sizetype, t);
5369 u = size_int (-osize);
5370 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5371 t = fold_convert (TREE_TYPE (ovfl), t);
5372 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5373 unshare_expr (ovfl), t);
5378 /* [10, 11] Emit code for:
5379 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5381 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5382 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5383 if (BYTES_BIG_ENDIAN && osize > size)
5385 u = size_int (osize - size);
5386 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5389 /* String [9] and [10, 11] together. */
5391 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5392 COND_EXPR_ELSE (addr) = t;
5394 addr = fold_convert (build_pointer_type (type), addr);
5395 addr = build_va_arg_indirect_ref (addr);
5399 addr = build_va_arg_indirect_ref (addr);
5404 /* Start a definition of function NAME. MIPS16_P indicates whether the
5405 function contains MIPS16 code. */
5408 mips_start_function_definition (const char *name, bool mips16_p)
5411 fprintf (asm_out_file, "\t.set\tmips16\n");
5413 fprintf (asm_out_file, "\t.set\tnomips16\n");
5415 if (!flag_inhibit_size_directive)
5417 fputs ("\t.ent\t", asm_out_file);
5418 assemble_name (asm_out_file, name);
5419 fputs ("\n", asm_out_file);
5422 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5424 /* Start the definition proper. */
5425 assemble_name (asm_out_file, name);
5426 fputs (":\n", asm_out_file);
5429 /* End a function definition started by mips_start_function_definition. */
5432 mips_end_function_definition (const char *name)
5434 if (!flag_inhibit_size_directive)
5436 fputs ("\t.end\t", asm_out_file);
5437 assemble_name (asm_out_file, name);
5438 fputs ("\n", asm_out_file);
5442 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5445 mips_ok_for_lazy_binding_p (rtx x)
5447 return (TARGET_USE_GOT
5448 && GET_CODE (x) == SYMBOL_REF
5449 && !SYMBOL_REF_BIND_NOW_P (x)
5450 && !mips_symbol_binds_local_p (x));
5453 /* Load function address ADDR into register DEST. TYPE is as for
5454 mips_expand_call. Return true if we used an explicit lazy-binding
5458 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5460 /* If we're generating PIC, and this call is to a global function,
5461 try to allow its address to be resolved lazily. This isn't
5462 possible for sibcalls when $gp is call-saved because the value
5463 of $gp on entry to the stub would be our caller's gp, not ours. */
5464 if (TARGET_EXPLICIT_RELOCS
5465 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5466 && mips_ok_for_lazy_binding_p (addr))
5468 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5469 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5474 mips_emit_move (dest, addr);
5479 /* Each locally-defined hard-float MIPS16 function has a local symbol
5480 associated with it. This hash table maps the function symbol (FUNC)
5481 to the local symbol (LOCAL). */
5482 struct mips16_local_alias GTY(()) {
5486 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5488 /* Hash table callbacks for mips16_local_aliases. */
5491 mips16_local_aliases_hash (const void *entry)
5493 const struct mips16_local_alias *alias;
5495 alias = (const struct mips16_local_alias *) entry;
5496 return htab_hash_string (XSTR (alias->func, 0));
5500 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5502 const struct mips16_local_alias *alias1, *alias2;
5504 alias1 = (const struct mips16_local_alias *) entry1;
5505 alias2 = (const struct mips16_local_alias *) entry2;
5506 return rtx_equal_p (alias1->func, alias2->func);
5509 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5510 Return a local alias for it, creating a new one if necessary. */
5513 mips16_local_alias (rtx func)
5515 struct mips16_local_alias *alias, tmp_alias;
5518 /* Create the hash table if this is the first call. */
5519 if (mips16_local_aliases == NULL)
5520 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5521 mips16_local_aliases_eq, NULL);
5523 /* Look up the function symbol, creating a new entry if need be. */
5524 tmp_alias.func = func;
5525 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5526 gcc_assert (slot != NULL);
5528 alias = (struct mips16_local_alias *) *slot;
5531 const char *func_name, *local_name;
5534 /* Create a new SYMBOL_REF for the local symbol. The choice of
5535 __fn_local_* is based on the __fn_stub_* names that we've
5536 traditionally used for the non-MIPS16 stub. */
5537 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5538 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5539 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5540 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5542 /* Create a new structure to represent the mapping. */
5543 alias = GGC_NEW (struct mips16_local_alias);
5545 alias->local = local;
5548 return alias->local;
5551 /* A chained list of functions for which mips16_build_call_stub has already
5552 generated a stub. NAME is the name of the function and FP_RET_P is true
5553 if the function returns a value in floating-point registers. */
5554 struct mips16_stub {
5555 struct mips16_stub *next;
5559 static struct mips16_stub *mips16_stubs;
5561 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5564 mips16_stub_function (const char *name)
5568 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5569 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5573 /* Return the two-character string that identifies floating-point
5574 return mode MODE in the name of a MIPS16 function stub. */
5577 mips16_call_stub_mode_suffix (enum machine_mode mode)
5581 else if (mode == DFmode)
5583 else if (mode == SCmode)
5585 else if (mode == DCmode)
5587 else if (mode == V2SFmode)
5593 /* Write instructions to move a 32-bit value between general register
5594 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5595 from GPREG to FPREG and 'f' to move in the opposite direction. */
5598 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5600 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5601 reg_names[gpreg], reg_names[fpreg]);
5604 /* Likewise for 64-bit values. */
5607 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5610 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5611 reg_names[gpreg], reg_names[fpreg]);
5612 else if (TARGET_FLOAT64)
5614 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5615 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5616 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5617 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5621 /* Move the least-significant word. */
5622 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5623 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5624 /* ...then the most significant word. */
5625 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5626 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5630 /* Write out code to move floating-point arguments into or out of
5631 general registers. FP_CODE is the code describing which arguments
5632 are present (see the comment above the definition of CUMULATIVE_ARGS
5633 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5636 mips_output_args_xfer (int fp_code, char direction)
5638 unsigned int gparg, fparg, f;
5639 CUMULATIVE_ARGS cum;
5641 /* This code only works for o32 and o64. */
5642 gcc_assert (TARGET_OLDABI);
5644 mips_init_cumulative_args (&cum, NULL);
5646 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5648 enum machine_mode mode;
5649 struct mips_arg_info info;
5653 else if ((f & 3) == 2)
5658 mips_get_arg_info (&info, &cum, mode, NULL, true);
5659 gparg = mips_arg_regno (&info, false);
5660 fparg = mips_arg_regno (&info, true);
5663 mips_output_32bit_xfer (direction, gparg, fparg);
5665 mips_output_64bit_xfer (direction, gparg, fparg);
5667 mips_function_arg_advance (&cum, mode, NULL, true);
5671 /* Write a MIPS16 stub for the current function. This stub is used
5672 for functions which take arguments in the floating-point registers.
5673 It is normal-mode code that moves the floating-point arguments
5674 into the general registers and then jumps to the MIPS16 code. */
5677 mips16_build_function_stub (void)
5679 const char *fnname, *alias_name, *separator;
5680 char *secname, *stubname;
5685 /* Create the name of the stub, and its unique section. */
5686 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5687 alias = mips16_local_alias (symbol);
5689 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5690 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5691 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5692 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5694 /* Build a decl for the stub. */
5695 stubdecl = build_decl (FUNCTION_DECL, get_identifier (stubname),
5696 build_function_type (void_type_node, NULL_TREE));
5697 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5698 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5700 /* Output a comment. */
5701 fprintf (asm_out_file, "\t# Stub function for %s (",
5702 current_function_name ());
5704 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5706 fprintf (asm_out_file, "%s%s", separator,
5707 (f & 3) == 1 ? "float" : "double");
5710 fprintf (asm_out_file, ")\n");
5712 /* Start the function definition. */
5713 assemble_start_function (stubdecl, stubname);
5714 mips_start_function_definition (stubname, false);
5716 /* If generating pic2 code, either set up the global pointer or
5718 if (TARGET_ABICALLS_PIC2)
5720 if (TARGET_ABSOLUTE_ABICALLS)
5721 fprintf (asm_out_file, "\t.option\tpic0\n");
5724 output_asm_insn ("%(.cpload\t%^%)", NULL);
5725 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5726 target function is. Use a local GOT access when loading the
5727 symbol, to cut down on the number of unnecessary GOT entries
5728 for stubs that aren't needed. */
5729 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
5734 /* Load the address of the MIPS16 function into $25. Do this first so
5735 that targets with coprocessor interlocks can use an MFC1 to fill the
5737 output_asm_insn ("la\t%^,%0", &symbol);
5739 /* Move the arguments from floating-point registers to general registers. */
5740 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5742 /* Jump to the MIPS16 function. */
5743 output_asm_insn ("jr\t%^", NULL);
5745 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
5746 fprintf (asm_out_file, "\t.option\tpic2\n");
5748 mips_end_function_definition (stubname);
5750 /* If the linker needs to create a dynamic symbol for the target
5751 function, it will associate the symbol with the stub (which,
5752 unlike the target function, follows the proper calling conventions).
5753 It is therefore useful to have a local alias for the target function,
5754 so that it can still be identified as MIPS16 code. As an optimization,
5755 this symbol can also be used for indirect MIPS16 references from
5756 within this file. */
5757 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
5759 switch_to_section (function_section (current_function_decl));
5762 /* The current function is a MIPS16 function that returns a value in an FPR.
5763 Copy the return value from its soft-float to its hard-float location.
5764 libgcc2 has special non-MIPS16 helper functions for each case. */
5767 mips16_copy_fpr_return_value (void)
5769 rtx fn, insn, retval;
5771 enum machine_mode return_mode;
5774 return_type = DECL_RESULT (current_function_decl);
5775 return_mode = DECL_MODE (return_type);
5777 name = ACONCAT (("__mips16_ret_",
5778 mips16_call_stub_mode_suffix (return_mode),
5780 fn = mips16_stub_function (name);
5782 /* The function takes arguments in $2 (and possibly $3), so calls
5783 to it cannot be lazily bound. */
5784 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
5786 /* Model the call as something that takes the GPR return value as
5787 argument and returns an "updated" value. */
5788 retval = gen_rtx_REG (return_mode, GP_RETURN);
5789 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
5790 const0_rtx, NULL_RTX, false);
5791 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
5794 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
5795 RETVAL is the location of the return value, or null if this is
5796 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5797 arguments and FP_CODE is the code built by mips_function_arg;
5798 see the comment above CUMULATIVE_ARGS for details.
5800 There are three alternatives:
5802 - If a stub was needed, emit the call and return the call insn itself.
5804 - If we can avoid using a stub by redirecting the call, set *FN_PTR
5805 to the new target and return null.
5807 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
5810 A stub is needed for calls to functions that, in normal mode,
5811 receive arguments in FPRs or return values in FPRs. The stub
5812 copies the arguments from their soft-float positions to their
5813 hard-float positions, calls the real function, then copies the
5814 return value from its hard-float position to its soft-float
5817 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
5818 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
5819 automatically redirects the JAL to the stub, otherwise the JAL
5820 continues to call FN directly. */
5823 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
5827 struct mips16_stub *l;
5830 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5831 we were invoked with the -msoft-float option. */
5832 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5835 /* Figure out whether the value might come back in a floating-point
5837 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
5839 /* We don't need to do anything if there were no floating-point
5840 arguments and the value will not be returned in a floating-point
5842 if (fp_code == 0 && !fp_ret_p)
5845 /* We don't need to do anything if this is a call to a special
5846 MIPS16 support function. */
5848 if (mips16_stub_function_p (fn))
5851 /* This code will only work for o32 and o64 abis. The other ABI's
5852 require more sophisticated support. */
5853 gcc_assert (TARGET_OLDABI);
5855 /* If we're calling via a function pointer, use one of the magic
5856 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5857 Each stub expects the function address to arrive in register $2. */
5858 if (GET_CODE (fn) != SYMBOL_REF
5859 || !call_insn_operand (fn, VOIDmode))
5862 rtx stub_fn, insn, addr;
5865 /* If this is a locally-defined and locally-binding function,
5866 avoid the stub by calling the local alias directly. */
5867 if (mips16_local_function_p (fn))
5869 *fn_ptr = mips16_local_alias (fn);
5873 /* Create a SYMBOL_REF for the libgcc.a function. */
5875 sprintf (buf, "__mips16_call_stub_%s_%d",
5876 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5879 sprintf (buf, "__mips16_call_stub_%d", fp_code);
5880 stub_fn = mips16_stub_function (buf);
5882 /* The function uses $2 as an argument, so calls to it
5883 cannot be lazily bound. */
5884 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
5886 /* Load the target function into $2. */
5887 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
5888 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
5890 /* Emit the call. */
5891 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
5892 args_size, NULL_RTX, lazy_p);
5894 /* Tell GCC that this call does indeed use the value of $2. */
5895 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
5897 /* If we are handling a floating-point return value, we need to
5898 save $18 in the function prologue. Putting a note on the
5899 call will mean that df_regs_ever_live_p ($18) will be true if the
5900 call is not eliminated, and we can check that in the prologue
5903 CALL_INSN_FUNCTION_USAGE (insn) =
5904 gen_rtx_EXPR_LIST (VOIDmode,
5905 gen_rtx_CLOBBER (VOIDmode,
5906 gen_rtx_REG (word_mode, 18)),
5907 CALL_INSN_FUNCTION_USAGE (insn));
5912 /* We know the function we are going to call. If we have already
5913 built a stub, we don't need to do anything further. */
5914 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5915 for (l = mips16_stubs; l != NULL; l = l->next)
5916 if (strcmp (l->name, fnname) == 0)
5921 const char *separator;
5922 char *secname, *stubname;
5923 tree stubid, stubdecl;
5926 /* If the function does not return in FPRs, the special stub
5930 If the function does return in FPRs, the stub section is named
5931 .mips16.call.fp.FNNAME
5933 Build a decl for the stub. */
5934 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
5936 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
5938 stubid = get_identifier (stubname);
5939 stubdecl = build_decl (FUNCTION_DECL, stubid,
5940 build_function_type (void_type_node, NULL_TREE));
5941 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5942 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE,
5945 /* Output a comment. */
5946 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
5948 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
5952 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5954 fprintf (asm_out_file, "%s%s", separator,
5955 (f & 3) == 1 ? "float" : "double");
5958 fprintf (asm_out_file, ")\n");
5960 /* Start the function definition. */
5961 assemble_start_function (stubdecl, stubname);
5962 mips_start_function_definition (stubname, false);
5966 /* Load the address of the MIPS16 function into $25. Do this
5967 first so that targets with coprocessor interlocks can use
5968 an MFC1 to fill the delay slot. */
5969 if (TARGET_EXPLICIT_RELOCS)
5971 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
5972 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
5975 output_asm_insn ("la\t%^,%0", &fn);
5978 /* Move the arguments from general registers to floating-point
5980 mips_output_args_xfer (fp_code, 't');
5984 /* Jump to the previously-loaded address. */
5985 output_asm_insn ("jr\t%^", NULL);
5989 /* Save the return address in $18 and call the non-MIPS16 function.
5990 The stub's caller knows that $18 might be clobbered, even though
5991 $18 is usually a call-saved register. */
5992 fprintf (asm_out_file, "\tmove\t%s,%s\n",
5993 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
5994 output_asm_insn (MIPS_CALL ("jal", &fn, 0), &fn);
5996 /* Move the result from floating-point registers to
5997 general registers. */
5998 switch (GET_MODE (retval))
6001 mips_output_32bit_xfer ('f', GP_RETURN + 1,
6002 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6005 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6006 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6008 /* On 64-bit targets, complex floats are returned in
6009 a single GPR, such that "sd" on a suitably-aligned
6010 target would store the value correctly. */
6011 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6012 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6013 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6014 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6015 reg_names[GP_RETURN],
6016 reg_names[GP_RETURN],
6017 reg_names[GP_RETURN + 1]);
6022 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6023 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6027 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6033 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6036 #ifdef ASM_DECLARE_FUNCTION_SIZE
6037 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6040 mips_end_function_definition (stubname);
6042 /* Record this stub. */
6043 l = XNEW (struct mips16_stub);
6044 l->name = xstrdup (fnname);
6045 l->fp_ret_p = fp_ret_p;
6046 l->next = mips16_stubs;
6050 /* If we expect a floating-point return value, but we've built a
6051 stub which does not expect one, then we're in trouble. We can't
6052 use the existing stub, because it won't handle the floating-point
6053 value. We can't build a new stub, because the linker won't know
6054 which stub to use for the various calls in this object file.
6055 Fortunately, this case is illegal, since it means that a function
6056 was declared in two different ways in a single compilation. */
6057 if (fp_ret_p && !l->fp_ret_p)
6058 error ("cannot handle inconsistent calls to %qs", fnname);
6060 if (retval == NULL_RTX)
6061 insn = gen_call_internal_direct (fn, args_size);
6063 insn = gen_call_value_internal_direct (retval, fn, args_size);
6064 insn = mips_emit_call_insn (insn, fn, fn, false);
6066 /* If we are calling a stub which handles a floating-point return
6067 value, we need to arrange to save $18 in the prologue. We do this
6068 by marking the function call as using the register. The prologue
6069 will later see that it is used, and emit code to save it. */
6071 CALL_INSN_FUNCTION_USAGE (insn) =
6072 gen_rtx_EXPR_LIST (VOIDmode,
6073 gen_rtx_CLOBBER (VOIDmode,
6074 gen_rtx_REG (word_mode, 18)),
6075 CALL_INSN_FUNCTION_USAGE (insn));
6080 /* Expand a call of type TYPE. RESULT is where the result will go (null
6081 for "call"s and "sibcall"s), ADDR is the address of the function,
6082 ARGS_SIZE is the size of the arguments and AUX is the value passed
6083 to us by mips_function_arg. LAZY_P is true if this call already
6084 involves a lazily-bound function address (such as when calling
6085 functions through a MIPS16 hard-float stub).
6087 Return the call itself. */
6090 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6091 rtx args_size, rtx aux, bool lazy_p)
6093 rtx orig_addr, pattern, insn;
6096 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6097 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6100 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6105 if (!call_insn_operand (addr, VOIDmode))
6107 if (type == MIPS_CALL_EPILOGUE)
6108 addr = MIPS_EPILOGUE_TEMP (Pmode);
6110 addr = gen_reg_rtx (Pmode);
6111 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6116 rtx (*fn) (rtx, rtx);
6118 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6119 fn = gen_call_split;
6120 else if (type == MIPS_CALL_SIBCALL)
6121 fn = gen_sibcall_internal;
6123 fn = gen_call_internal;
6125 pattern = fn (addr, args_size);
6127 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6129 /* Handle return values created by mips_return_fpr_pair. */
6130 rtx (*fn) (rtx, rtx, rtx, rtx);
6133 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6134 fn = gen_call_value_multiple_split;
6135 else if (type == MIPS_CALL_SIBCALL)
6136 fn = gen_sibcall_value_multiple_internal;
6138 fn = gen_call_value_multiple_internal;
6140 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6141 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6142 pattern = fn (reg1, addr, args_size, reg2);
6146 rtx (*fn) (rtx, rtx, rtx);
6148 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6149 fn = gen_call_value_split;
6150 else if (type == MIPS_CALL_SIBCALL)
6151 fn = gen_sibcall_value_internal;
6153 fn = gen_call_value_internal;
6155 /* Handle return values created by mips_return_fpr_single. */
6156 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6157 result = XEXP (XVECEXP (result, 0, 0), 0);
6158 pattern = fn (result, addr, args_size);
6161 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6164 /* Split call instruction INSN into a $gp-clobbering call and
6165 (where necessary) an instruction to restore $gp from its save slot.
6166 CALL_PATTERN is the pattern of the new call. */
6169 mips_split_call (rtx insn, rtx call_pattern)
6173 new_insn = emit_call_insn (call_pattern);
6174 CALL_INSN_FUNCTION_USAGE (new_insn)
6175 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6176 if (!find_reg_note (insn, REG_NORETURN, 0))
6177 /* Pick a temporary register that is suitable for both MIPS16 and
6178 non-MIPS16 code. $4 and $5 are used for returning complex double
6179 values in soft-float code, so $6 is the first suitable candidate. */
6180 mips_restore_gp (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6183 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6186 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6188 if (!TARGET_SIBCALLS)
6191 /* We can't do a sibcall if the called function is a MIPS16 function
6192 because there is no direct "jx" instruction equivalent to "jalx" to
6193 switch the ISA mode. We only care about cases where the sibling
6194 and normal calls would both be direct. */
6196 && mips_use_mips16_mode_p (decl)
6197 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6200 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6201 functions could be MIPS16 ones unless an attribute explicitly tells
6203 if (TARGET_INTERLINK_MIPS16
6205 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6206 && !mips_nomips16_decl_p (decl)
6207 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6214 /* Emit code to move general operand SRC into condition-code
6215 register DEST given that SCRATCH is a scratch TFmode FPR.
6222 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6225 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6229 /* Change the source to SFmode. */
6231 src = adjust_address (src, SFmode, 0);
6232 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6233 src = gen_rtx_REG (SFmode, true_regnum (src));
6235 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6236 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6238 mips_emit_move (copy_rtx (fp1), src);
6239 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6240 emit_insn (gen_slt_sf (dest, fp2, fp1));
6243 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6244 Assume that the areas do not overlap. */
6247 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6249 HOST_WIDE_INT offset, delta;
6250 unsigned HOST_WIDE_INT bits;
6252 enum machine_mode mode;
6255 /* Work out how many bits to move at a time. If both operands have
6256 half-word alignment, it is usually better to move in half words.
6257 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6258 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6259 Otherwise move word-sized chunks. */
6260 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6261 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6262 bits = BITS_PER_WORD / 2;
6264 bits = BITS_PER_WORD;
6266 mode = mode_for_size (bits, MODE_INT, 0);
6267 delta = bits / BITS_PER_UNIT;
6269 /* Allocate a buffer for the temporary registers. */
6270 regs = XALLOCAVEC (rtx, length / delta);
6272 /* Load as many BITS-sized chunks as possible. Use a normal load if
6273 the source has enough alignment, otherwise use left/right pairs. */
6274 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6276 regs[i] = gen_reg_rtx (mode);
6277 if (MEM_ALIGN (src) >= bits)
6278 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6281 rtx part = adjust_address (src, BLKmode, offset);
6282 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6287 /* Copy the chunks to the destination. */
6288 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6289 if (MEM_ALIGN (dest) >= bits)
6290 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6293 rtx part = adjust_address (dest, BLKmode, offset);
6294 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6298 /* Mop up any left-over bytes. */
6299 if (offset < length)
6301 src = adjust_address (src, BLKmode, offset);
6302 dest = adjust_address (dest, BLKmode, offset);
6303 move_by_pieces (dest, src, length - offset,
6304 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6308 /* Helper function for doing a loop-based block operation on memory
6309 reference MEM. Each iteration of the loop will operate on LENGTH
6312 Create a new base register for use within the loop and point it to
6313 the start of MEM. Create a new memory reference that uses this
6314 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6317 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6318 rtx *loop_reg, rtx *loop_mem)
6320 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6322 /* Although the new mem does not refer to a known location,
6323 it does keep up to LENGTH bytes of alignment. */
6324 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6325 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6328 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6329 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6330 the memory regions do not overlap. */
6333 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6334 HOST_WIDE_INT bytes_per_iter)
6336 rtx label, src_reg, dest_reg, final_src;
6337 HOST_WIDE_INT leftover;
6339 leftover = length % bytes_per_iter;
6342 /* Create registers and memory references for use within the loop. */
6343 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6344 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6346 /* Calculate the value that SRC_REG should have after the last iteration
6348 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6351 /* Emit the start of the loop. */
6352 label = gen_label_rtx ();
6355 /* Emit the loop body. */
6356 mips_block_move_straight (dest, src, bytes_per_iter);
6358 /* Move on to the next block. */
6359 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6360 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6362 /* Emit the loop condition. */
6363 if (Pmode == DImode)
6364 emit_insn (gen_cmpdi (src_reg, final_src));
6366 emit_insn (gen_cmpsi (src_reg, final_src));
6367 emit_jump_insn (gen_bne (label));
6369 /* Mop up any left-over bytes. */
6371 mips_block_move_straight (dest, src, leftover);
6374 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6375 memory reference SRC to memory reference DEST. */
6378 mips_expand_block_move (rtx dest, rtx src, rtx length)
6380 if (GET_CODE (length) == CONST_INT)
6382 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6384 mips_block_move_straight (dest, src, INTVAL (length));
6389 mips_block_move_loop (dest, src, INTVAL (length),
6390 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6397 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6400 mips_expand_synci_loop (rtx begin, rtx end)
6402 rtx inc, label, cmp, cmp_result;
6404 /* Load INC with the cache line size (rdhwr INC,$1). */
6405 inc = gen_reg_rtx (Pmode);
6406 emit_insn (Pmode == SImode
6407 ? gen_rdhwr_synci_step_si (inc)
6408 : gen_rdhwr_synci_step_di (inc));
6410 /* Loop back to here. */
6411 label = gen_label_rtx ();
6414 emit_insn (gen_synci (begin));
6416 cmp = mips_force_binary (Pmode, GTU, begin, end);
6418 mips_emit_binary (PLUS, begin, begin, inc);
6420 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6421 emit_jump_insn (gen_condjump (cmp_result, label));
6424 /* Expand a QI or HI mode atomic memory operation.
6426 GENERATOR contains a pointer to the gen_* function that generates
6427 the SI mode underlying atomic operation using masks that we
6430 RESULT is the return register for the operation. Its value is NULL
6433 MEM is the location of the atomic access.
6435 OLDVAL is the first operand for the operation.
6437 NEWVAL is the optional second operand for the operation. Its value
6438 is NULL if unused. */
6441 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6442 rtx result, rtx mem, rtx oldval, rtx newval)
6444 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6445 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6447 enum machine_mode mode;
6449 mode = GET_MODE (mem);
6451 /* Compute the address of the containing SImode value. */
6452 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6453 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6454 force_reg (Pmode, GEN_INT (-4)));
6456 /* Create a memory reference for it. */
6457 memsi = gen_rtx_MEM (SImode, memsi_addr);
6458 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6459 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6461 /* Work out the byte offset of the QImode or HImode value,
6462 counting from the least significant byte. */
6463 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6464 if (TARGET_BIG_ENDIAN)
6465 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6467 /* Multiply by eight to convert the shift value from bytes to bits. */
6468 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6470 /* Make the final shift an SImode value, so that it can be used in
6471 SImode operations. */
6472 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6474 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6475 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6476 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6477 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6479 /* Compute the equivalent exclusive mask. */
6480 inverted_mask = gen_reg_rtx (SImode);
6481 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6482 gen_rtx_NOT (SImode, mask)));
6484 /* Shift the old value into place. */
6485 if (oldval != const0_rtx)
6487 oldval = convert_modes (SImode, mode, oldval, true);
6488 oldval = force_reg (SImode, oldval);
6489 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6492 /* Do the same for the new value. */
6493 if (newval && newval != const0_rtx)
6495 newval = convert_modes (SImode, mode, newval, true);
6496 newval = force_reg (SImode, newval);
6497 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6500 /* Do the SImode atomic access. */
6502 res = gen_reg_rtx (SImode);
6504 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6506 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6508 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6514 /* Shift and convert the result. */
6515 mips_emit_binary (AND, res, res, mask);
6516 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6517 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6521 /* Return true if it is possible to use left/right accesses for a
6522 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6523 returning true, update *OP, *LEFT and *RIGHT as follows:
6525 *OP is a BLKmode reference to the whole field.
6527 *LEFT is a QImode reference to the first byte if big endian or
6528 the last byte if little endian. This address can be used in the
6529 left-side instructions (LWL, SWL, LDL, SDL).
6531 *RIGHT is a QImode reference to the opposite end of the field and
6532 can be used in the patterning right-side instruction. */
6535 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6536 rtx *left, rtx *right)
6540 /* Check that the operand really is a MEM. Not all the extv and
6541 extzv predicates are checked. */
6545 /* Check that the size is valid. */
6546 if (width != 32 && (!TARGET_64BIT || width != 64))
6549 /* We can only access byte-aligned values. Since we are always passed
6550 a reference to the first byte of the field, it is not necessary to
6551 do anything with BITPOS after this check. */
6552 if (bitpos % BITS_PER_UNIT != 0)
6555 /* Reject aligned bitfields: we want to use a normal load or store
6556 instead of a left/right pair. */
6557 if (MEM_ALIGN (*op) >= width)
6560 /* Adjust *OP to refer to the whole field. This also has the effect
6561 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6562 *op = adjust_address (*op, BLKmode, 0);
6563 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6565 /* Get references to both ends of the field. We deliberately don't
6566 use the original QImode *OP for FIRST since the new BLKmode one
6567 might have a simpler address. */
6568 first = adjust_address (*op, QImode, 0);
6569 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6571 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6572 correspond to the MSB and RIGHT to the LSB. */
6573 if (TARGET_BIG_ENDIAN)
6574 *left = first, *right = last;
6576 *left = last, *right = first;
6581 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6582 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6583 the operation is the equivalent of:
6585 (set DEST (*_extract SRC WIDTH BITPOS))
6587 Return true on success. */
6590 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6591 HOST_WIDE_INT bitpos)
6593 rtx left, right, temp;
6595 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6596 be a paradoxical word_mode subreg. This is the only case in which
6597 we allow the destination to be larger than the source. */
6598 if (GET_CODE (dest) == SUBREG
6599 && GET_MODE (dest) == DImode
6600 && GET_MODE (SUBREG_REG (dest)) == SImode)
6601 dest = SUBREG_REG (dest);
6603 /* After the above adjustment, the destination must be the same
6604 width as the source. */
6605 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6608 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6611 temp = gen_reg_rtx (GET_MODE (dest));
6612 if (GET_MODE (dest) == DImode)
6614 emit_insn (gen_mov_ldl (temp, src, left));
6615 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6619 emit_insn (gen_mov_lwl (temp, src, left));
6620 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6625 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6626 BITPOS and SRC are the operands passed to the expander; the operation
6627 is the equivalent of:
6629 (set (zero_extract DEST WIDTH BITPOS) SRC)
6631 Return true on success. */
6634 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6635 HOST_WIDE_INT bitpos)
6638 enum machine_mode mode;
6640 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6643 mode = mode_for_size (width, MODE_INT, 0);
6644 src = gen_lowpart (mode, src);
6647 emit_insn (gen_mov_sdl (dest, src, left));
6648 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6652 emit_insn (gen_mov_swl (dest, src, left));
6653 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6658 /* Return true if X is a MEM with the same size as MODE. */
6661 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6668 size = MEM_SIZE (x);
6669 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6672 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6673 source of an "ext" instruction or the destination of an "ins"
6674 instruction. OP must be a register operand and the following
6675 conditions must hold:
6677 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6678 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6679 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6681 Also reject lengths equal to a word as they are better handled
6682 by the move patterns. */
6685 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6687 if (!ISA_HAS_EXT_INS
6688 || !register_operand (op, VOIDmode)
6689 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6692 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6695 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6701 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6702 operation if MAXLEN is the maxium length of consecutive bits that
6703 can make up MASK. MODE is the mode of the operation. See
6704 mask_low_and_shift_len for the actual definition. */
6707 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
6709 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
6712 /* The canonical form of a mask-low-and-shift-left operation is
6713 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
6714 cleared. Thus we need to shift MASK to the right before checking if it
6715 is a valid mask value. MODE is the mode of the operation. If true
6716 return the length of the mask, otherwise return -1. */
6719 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
6721 HOST_WIDE_INT shval;
6723 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
6724 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
6727 /* Return true if -msplit-addresses is selected and should be honored.
6729 -msplit-addresses is a half-way house between explicit relocations
6730 and the traditional assembler macros. It can split absolute 32-bit
6731 symbolic constants into a high/lo_sum pair but uses macros for other
6734 Like explicit relocation support for REL targets, it relies
6735 on GNU extensions in the assembler and the linker.
6737 Although this code should work for -O0, it has traditionally
6738 been treated as an optimization. */
6741 mips_split_addresses_p (void)
6743 return (TARGET_SPLIT_ADDRESSES
6747 && !ABI_HAS_64BIT_SYMBOLS);
6750 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6753 mips_init_relocs (void)
6755 memset (mips_split_p, '\0', sizeof (mips_split_p));
6756 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
6757 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6758 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6760 if (ABI_HAS_64BIT_SYMBOLS)
6762 if (TARGET_EXPLICIT_RELOCS)
6764 mips_split_p[SYMBOL_64_HIGH] = true;
6765 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6766 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6768 mips_split_p[SYMBOL_64_MID] = true;
6769 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6770 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6772 mips_split_p[SYMBOL_64_LOW] = true;
6773 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6774 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6776 mips_split_p[SYMBOL_ABSOLUTE] = true;
6777 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6782 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6784 mips_split_p[SYMBOL_ABSOLUTE] = true;
6785 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6786 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6788 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6794 /* The high part is provided by a pseudo copy of $gp. */
6795 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6796 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6798 else if (TARGET_EXPLICIT_RELOCS)
6799 /* Small data constants are kept whole until after reload,
6800 then lowered by mips_rewrite_small_data. */
6801 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6803 if (TARGET_EXPLICIT_RELOCS)
6805 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6808 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6809 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6813 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6814 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6817 /* Expose the use of $28 as soon as possible. */
6818 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
6822 /* The HIGH and LO_SUM are matched by special .md patterns. */
6823 mips_split_p[SYMBOL_GOT_DISP] = true;
6825 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6826 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6827 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6829 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6830 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6831 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6836 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6838 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6839 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6841 /* Expose the use of $28 as soon as possible. */
6842 mips_split_p[SYMBOL_GOT_DISP] = true;
6848 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6849 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6850 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6853 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6854 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6856 mips_split_p[SYMBOL_DTPREL] = true;
6857 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6858 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6860 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6862 mips_split_p[SYMBOL_TPREL] = true;
6863 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6864 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6866 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6869 /* If OP is an UNSPEC address, return the address to which it refers,
6870 otherwise return OP itself. */
6873 mips_strip_unspec_address (rtx op)
6877 split_const (op, &base, &offset);
6878 if (UNSPEC_ADDRESS_P (base))
6879 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6883 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6884 in context CONTEXT. RELOCS is the array of relocations to use. */
6887 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6888 const char **relocs)
6890 enum mips_symbol_type symbol_type;
6893 symbol_type = mips_classify_symbolic_expression (op, context);
6894 gcc_assert (relocs[symbol_type]);
6896 fputs (relocs[symbol_type], file);
6897 output_addr_const (file, mips_strip_unspec_address (op));
6898 for (p = relocs[symbol_type]; *p != 0; p++)
6903 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6904 The punctuation characters are:
6906 '(' Start a nested ".set noreorder" block.
6907 ')' End a nested ".set noreorder" block.
6908 '[' Start a nested ".set noat" block.
6909 ']' End a nested ".set noat" block.
6910 '<' Start a nested ".set nomacro" block.
6911 '>' End a nested ".set nomacro" block.
6912 '*' Behave like %(%< if generating a delayed-branch sequence.
6913 '#' Print a nop if in a ".set noreorder" block.
6914 '/' Like '#', but do nothing within a delayed-branch sequence.
6915 '?' Print "l" if mips_branch_likely is true
6916 '~' Print a nop if mips_branch_likely is true
6917 '.' Print the name of the register with a hard-wired zero (zero or $0).
6918 '@' Print the name of the assembler temporary register (at or $1).
6919 '^' Print the name of the pic call-through register (t9 or $25).
6920 '+' Print the name of the gp register (usually gp or $28).
6921 '$' Print the name of the stack pointer register (sp or $29).
6922 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6923 '-' Print ".set pop" under the same conditions for '|'.
6925 See also mips_init_print_operand_pucnt. */
6928 mips_print_operand_punctuation (FILE *file, int ch)
6933 if (set_noreorder++ == 0)
6934 fputs (".set\tnoreorder\n\t", file);
6938 gcc_assert (set_noreorder > 0);
6939 if (--set_noreorder == 0)
6940 fputs ("\n\t.set\treorder", file);
6944 if (set_noat++ == 0)
6945 fputs (".set\tnoat\n\t", file);
6949 gcc_assert (set_noat > 0);
6950 if (--set_noat == 0)
6951 fputs ("\n\t.set\tat", file);
6955 if (set_nomacro++ == 0)
6956 fputs (".set\tnomacro\n\t", file);
6960 gcc_assert (set_nomacro > 0);
6961 if (--set_nomacro == 0)
6962 fputs ("\n\t.set\tmacro", file);
6966 if (final_sequence != 0)
6968 mips_print_operand_punctuation (file, '(');
6969 mips_print_operand_punctuation (file, '<');
6974 if (set_noreorder != 0)
6975 fputs ("\n\tnop", file);
6979 /* Print an extra newline so that the delayed insn is separated
6980 from the following ones. This looks neater and is consistent
6981 with non-nop delayed sequences. */
6982 if (set_noreorder != 0 && final_sequence == 0)
6983 fputs ("\n\tnop\n", file);
6987 if (mips_branch_likely)
6992 if (mips_branch_likely)
6993 fputs ("\n\tnop", file);
6997 fputs (reg_names[GP_REG_FIRST + 0], file);
7001 fputs (reg_names[GP_REG_FIRST + 1], file);
7005 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7009 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7013 fputs (reg_names[STACK_POINTER_REGNUM], file);
7018 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
7023 fputs ("\n\t.set\tpop", file);
7032 /* Initialize mips_print_operand_punct. */
7035 mips_init_print_operand_punct (void)
7039 for (p = "()[]<>*#/?~.@^+$|-"; *p; p++)
7040 mips_print_operand_punct[(unsigned char) *p] = true;
7043 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7044 associated with condition CODE. Print the condition part of the
7048 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7062 /* Conveniently, the MIPS names for these conditions are the same
7063 as their RTL equivalents. */
7064 fputs (GET_RTX_NAME (code), file);
7068 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7073 /* Likewise floating-point branches. */
7076 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7081 fputs ("c1f", file);
7085 fputs ("c1t", file);
7089 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7094 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7096 'X' Print CONST_INT OP in hexadecimal format.
7097 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7098 'd' Print CONST_INT OP in decimal.
7099 'm' Print one less than CONST_INT OP in decimal.
7100 'h' Print the high-part relocation associated with OP, after stripping
7102 'R' Print the low-part relocation associated with OP.
7103 'C' Print the integer branch condition for comparison OP.
7104 'N' Print the inverse of the integer branch condition for comparison OP.
7105 'F' Print the FPU branch condition for comparison OP.
7106 'W' Print the inverse of the FPU branch condition for comparison OP.
7107 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7108 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7109 't' Like 'T', but with the EQ/NE cases reversed
7110 'Y' Print mips_fp_conditions[INTVAL (OP)]
7111 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7112 'q' Print a DSP accumulator register.
7113 'D' Print the second part of a double-word register or memory operand.
7114 'L' Print the low-order register in a double-word register operand.
7115 'M' Print high-order register in a double-word register operand.
7116 'z' Print $0 if OP is zero, otherwise print OP normally. */
7119 mips_print_operand (FILE *file, rtx op, int letter)
7123 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7125 mips_print_operand_punctuation (file, letter);
7130 code = GET_CODE (op);
7135 if (GET_CODE (op) == CONST_INT)
7136 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7138 output_operand_lossage ("invalid use of '%%%c'", letter);
7142 if (GET_CODE (op) == CONST_INT)
7143 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7145 output_operand_lossage ("invalid use of '%%%c'", letter);
7149 if (GET_CODE (op) == CONST_INT)
7150 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7152 output_operand_lossage ("invalid use of '%%%c'", letter);
7156 if (GET_CODE (op) == CONST_INT)
7157 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7159 output_operand_lossage ("invalid use of '%%%c'", letter);
7165 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7169 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7173 mips_print_int_branch_condition (file, code, letter);
7177 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7181 mips_print_float_branch_condition (file, code, letter);
7185 mips_print_float_branch_condition (file, reverse_condition (code),
7192 int truth = (code == NE) == (letter == 'T');
7193 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7198 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7199 fputs (mips_fp_conditions[UINTVAL (op)], file);
7201 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7208 mips_print_operand (file, op, 0);
7214 if (code == REG && MD_REG_P (REGNO (op)))
7215 fprintf (file, "$ac0");
7216 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7217 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7219 output_operand_lossage ("invalid use of '%%%c'", letter);
7227 unsigned int regno = REGNO (op);
7228 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7229 || (letter == 'L' && TARGET_BIG_ENDIAN)
7232 fprintf (file, "%s", reg_names[regno]);
7238 output_address (plus_constant (XEXP (op, 0), 4));
7240 output_address (XEXP (op, 0));
7244 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7245 fputs (reg_names[GP_REG_FIRST], file);
7246 else if (CONST_GP_P (op))
7247 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7249 output_addr_const (file, mips_strip_unspec_address (op));
7255 /* Output address operand X to FILE. */
7258 mips_print_operand_address (FILE *file, rtx x)
7260 struct mips_address_info addr;
7262 if (mips_classify_address (&addr, x, word_mode, true))
7266 mips_print_operand (file, addr.offset, 0);
7267 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7270 case ADDRESS_LO_SUM:
7271 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7273 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7276 case ADDRESS_CONST_INT:
7277 output_addr_const (file, x);
7278 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7281 case ADDRESS_SYMBOLIC:
7282 output_addr_const (file, mips_strip_unspec_address (x));
7288 /* Implement TARGET_ENCODE_SECTION_INFO. */
7291 mips_encode_section_info (tree decl, rtx rtl, int first)
7293 default_encode_section_info (decl, rtl, first);
7295 if (TREE_CODE (decl) == FUNCTION_DECL)
7297 rtx symbol = XEXP (rtl, 0);
7298 tree type = TREE_TYPE (decl);
7300 /* Encode whether the symbol is short or long. */
7301 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7302 || mips_far_type_p (type))
7303 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7307 /* Implement TARGET_SELECT_RTX_SECTION. */
7310 mips_select_rtx_section (enum machine_mode mode, rtx x,
7311 unsigned HOST_WIDE_INT align)
7313 /* ??? Consider using mergeable small data sections. */
7314 if (mips_rtx_constant_in_small_data_p (mode))
7315 return get_named_section (NULL, ".sdata", 0);
7317 return default_elf_select_rtx_section (mode, x, align);
7320 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7322 The complication here is that, with the combination TARGET_ABICALLS
7323 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7324 absolute addresses, and should therefore not be included in the
7325 read-only part of a DSO. Handle such cases by selecting a normal
7326 data section instead of a read-only one. The logic apes that in
7327 default_function_rodata_section. */
7330 mips_function_rodata_section (tree decl)
7332 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7333 return default_function_rodata_section (decl);
7335 if (decl && DECL_SECTION_NAME (decl))
7337 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7338 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7340 char *rname = ASTRDUP (name);
7342 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7344 else if (flag_function_sections
7345 && flag_data_sections
7346 && strncmp (name, ".text.", 6) == 0)
7348 char *rname = ASTRDUP (name);
7349 memcpy (rname + 1, "data", 4);
7350 return get_section (rname, SECTION_WRITE, decl);
7353 return data_section;
7356 /* Implement TARGET_IN_SMALL_DATA_P. */
7359 mips_in_small_data_p (const_tree decl)
7361 unsigned HOST_WIDE_INT size;
7363 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7366 /* We don't yet generate small-data references for -mabicalls
7367 or VxWorks RTP code. See the related -G handling in
7368 mips_override_options. */
7369 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7372 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7376 /* Reject anything that isn't in a known small-data section. */
7377 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7378 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7381 /* If a symbol is defined externally, the assembler will use the
7382 usual -G rules when deciding how to implement macros. */
7383 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7386 else if (TARGET_EMBEDDED_DATA)
7388 /* Don't put constants into the small data section: we want them
7389 to be in ROM rather than RAM. */
7390 if (TREE_CODE (decl) != VAR_DECL)
7393 if (TREE_READONLY (decl)
7394 && !TREE_SIDE_EFFECTS (decl)
7395 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7399 /* Enforce -mlocal-sdata. */
7400 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7403 /* Enforce -mextern-sdata. */
7404 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7406 if (DECL_EXTERNAL (decl))
7408 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7412 /* We have traditionally not treated zero-sized objects as small data,
7413 so this is now effectively part of the ABI. */
7414 size = int_size_in_bytes (TREE_TYPE (decl));
7415 return size > 0 && size <= mips_small_data_threshold;
7418 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7419 anchors for small data: the GP register acts as an anchor in that
7420 case. We also don't want to use them for PC-relative accesses,
7421 where the PC acts as an anchor. */
7424 mips_use_anchors_for_symbol_p (const_rtx symbol)
7426 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7428 case SYMBOL_PC_RELATIVE:
7429 case SYMBOL_GP_RELATIVE:
7433 return default_use_anchors_for_symbol_p (symbol);
7437 /* The MIPS debug format wants all automatic variables and arguments
7438 to be in terms of the virtual frame pointer (stack pointer before
7439 any adjustment in the function), while the MIPS 3.0 linker wants
7440 the frame pointer to be the stack pointer after the initial
7441 adjustment. So, we do the adjustment here. The arg pointer (which
7442 is eliminated) points to the virtual frame pointer, while the frame
7443 pointer (which may be eliminated) points to the stack pointer after
7444 the initial adjustments. */
7447 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7449 rtx offset2 = const0_rtx;
7450 rtx reg = eliminate_constant_term (addr, &offset2);
7453 offset = INTVAL (offset2);
7455 if (reg == stack_pointer_rtx
7456 || reg == frame_pointer_rtx
7457 || reg == hard_frame_pointer_rtx)
7459 offset -= cfun->machine->frame.total_size;
7460 if (reg == hard_frame_pointer_rtx)
7461 offset += cfun->machine->frame.hard_frame_pointer_offset;
7464 /* sdbout_parms does not want this to crash for unrecognized cases. */
7466 else if (reg != arg_pointer_rtx)
7467 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7474 /* Implement ASM_OUTPUT_EXTERNAL. */
7477 mips_output_external (FILE *file, tree decl, const char *name)
7479 default_elf_asm_output_external (file, decl, name);
7481 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7482 set in order to avoid putting out names that are never really
7484 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7486 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7488 /* When using assembler macros, emit .extern directives for
7489 all small-data externs so that the assembler knows how
7492 In most cases it would be safe (though pointless) to emit
7493 .externs for other symbols too. One exception is when an
7494 object is within the -G limit but declared by the user to
7495 be in a section other than .sbss or .sdata. */
7496 fputs ("\t.extern\t", file);
7497 assemble_name (file, name);
7498 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7499 int_size_in_bytes (TREE_TYPE (decl)));
7501 else if (TARGET_IRIX
7502 && mips_abi == ABI_32
7503 && TREE_CODE (decl) == FUNCTION_DECL)
7505 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7506 `.global name .text' directive for every used but
7507 undefined function. If we don't, the linker may perform
7508 an optimization (skipping over the insns that set $gp)
7509 when it is unsafe. */
7510 fputs ("\t.globl ", file);
7511 assemble_name (file, name);
7512 fputs (" .text\n", file);
7517 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7520 mips_output_filename (FILE *stream, const char *name)
7522 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7524 if (write_symbols == DWARF2_DEBUG)
7526 else if (mips_output_filename_first_time)
7528 mips_output_filename_first_time = 0;
7529 num_source_filenames += 1;
7530 current_function_file = name;
7531 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7532 output_quoted_string (stream, name);
7533 putc ('\n', stream);
7535 /* If we are emitting stabs, let dbxout.c handle this (except for
7536 the mips_output_filename_first_time case). */
7537 else if (write_symbols == DBX_DEBUG)
7539 else if (name != current_function_file
7540 && strcmp (name, current_function_file) != 0)
7542 num_source_filenames += 1;
7543 current_function_file = name;
7544 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7545 output_quoted_string (stream, name);
7546 putc ('\n', stream);
7550 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7552 static void ATTRIBUTE_UNUSED
7553 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7558 fputs ("\t.dtprelword\t", file);
7562 fputs ("\t.dtpreldword\t", file);
7568 output_addr_const (file, x);
7569 fputs ("+0x8000", file);
7572 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7575 mips_dwarf_register_span (rtx reg)
7578 enum machine_mode mode;
7580 /* By default, GCC maps increasing register numbers to increasing
7581 memory locations, but paired FPRs are always little-endian,
7582 regardless of the prevailing endianness. */
7583 mode = GET_MODE (reg);
7584 if (FP_REG_P (REGNO (reg))
7585 && TARGET_BIG_ENDIAN
7586 && MAX_FPRS_PER_FMT > 1
7587 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7589 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7590 high = mips_subword (reg, true);
7591 low = mips_subword (reg, false);
7592 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7598 /* Implement ASM_OUTPUT_ASCII. */
7601 mips_output_ascii (FILE *stream, const char *string, size_t len)
7607 fprintf (stream, "\t.ascii\t\"");
7608 for (i = 0; i < len; i++)
7612 c = (unsigned char) string[i];
7615 if (c == '\\' || c == '\"')
7617 putc ('\\', stream);
7625 fprintf (stream, "\\%03o", c);
7629 if (cur_pos > 72 && i+1 < len)
7632 fprintf (stream, "\"\n\t.ascii\t\"");
7635 fprintf (stream, "\"\n");
7638 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7639 macros, mark the symbol as written so that mips_asm_output_external
7640 won't emit an .extern for it. STREAM is the output file, NAME is the
7641 name of the symbol, INIT_STRING is the string that should be written
7642 before the symbol and FINAL_STRING is the string that should be
7643 written after it. FINAL_STRING is a printf format that consumes the
7644 remaining arguments. */
7647 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7648 const char *final_string, ...)
7652 fputs (init_string, stream);
7653 assemble_name (stream, name);
7654 va_start (ap, final_string);
7655 vfprintf (stream, final_string, ap);
7658 if (!TARGET_EXPLICIT_RELOCS)
7660 tree name_tree = get_identifier (name);
7661 TREE_ASM_WRITTEN (name_tree) = 1;
7665 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7666 NAME is the name of the object and ALIGN is the required alignment
7667 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7668 alignment argument. */
7671 mips_declare_common_object (FILE *stream, const char *name,
7672 const char *init_string,
7673 unsigned HOST_WIDE_INT size,
7674 unsigned int align, bool takes_alignment_p)
7676 if (!takes_alignment_p)
7678 size += (align / BITS_PER_UNIT) - 1;
7679 size -= size % (align / BITS_PER_UNIT);
7680 mips_declare_object (stream, name, init_string,
7681 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7684 mips_declare_object (stream, name, init_string,
7685 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7686 size, align / BITS_PER_UNIT);
7689 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7690 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7693 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7694 unsigned HOST_WIDE_INT size,
7697 /* If the target wants uninitialized const declarations in
7698 .rdata then don't put them in .comm. */
7699 if (TARGET_EMBEDDED_DATA
7700 && TARGET_UNINIT_CONST_IN_RODATA
7701 && TREE_CODE (decl) == VAR_DECL
7702 && TREE_READONLY (decl)
7703 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7705 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7706 targetm.asm_out.globalize_label (stream, name);
7708 switch_to_section (readonly_data_section);
7709 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7710 mips_declare_object (stream, name, "",
7711 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7715 mips_declare_common_object (stream, name, "\n\t.comm\t",
7719 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7720 extern int size_directive_output;
7722 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7723 definitions except that it uses mips_declare_object to emit the label. */
7726 mips_declare_object_name (FILE *stream, const char *name,
7727 tree decl ATTRIBUTE_UNUSED)
7729 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7730 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7733 size_directive_output = 0;
7734 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7738 size_directive_output = 1;
7739 size = int_size_in_bytes (TREE_TYPE (decl));
7740 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7743 mips_declare_object (stream, name, "", ":\n");
7746 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7749 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7753 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7754 if (!flag_inhibit_size_directive
7755 && DECL_SIZE (decl) != 0
7758 && DECL_INITIAL (decl) == error_mark_node
7759 && !size_directive_output)
7763 size_directive_output = 1;
7764 size = int_size_in_bytes (TREE_TYPE (decl));
7765 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7770 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7771 with the current ABI. */
7774 mips_mdebug_abi_name (void)
7787 return TARGET_64BIT ? "eabi64" : "eabi32";
7793 /* Implement TARGET_ASM_FILE_START. */
7796 mips_file_start (void)
7798 default_file_start ();
7800 /* Generate a special section to describe the ABI switches used to
7801 produce the resultant binary. This is unnecessary on IRIX and
7802 causes unwanted warnings from the native linker. */
7805 /* Record the ABI itself. Modern versions of binutils encode
7806 this information in the ELF header flags, but GDB needs the
7807 information in order to correctly debug binaries produced by
7808 older binutils. See the function mips_gdbarch_init in
7810 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7811 mips_mdebug_abi_name ());
7813 /* There is no ELF header flag to distinguish long32 forms of the
7814 EABI from long64 forms. Emit a special section to help tools
7815 such as GDB. Do the same for o64, which is sometimes used with
7817 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7818 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7819 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7821 #ifdef HAVE_AS_GNU_ATTRIBUTE
7822 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7823 (TARGET_HARD_FLOAT_ABI
7824 ? (TARGET_DOUBLE_FLOAT
7825 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
7829 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7830 if (TARGET_ABICALLS)
7832 fprintf (asm_out_file, "\t.abicalls\n");
7833 if (TARGET_ABICALLS_PIC0)
7834 fprintf (asm_out_file, "\t.option\tpic0\n");
7837 if (flag_verbose_asm)
7838 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7840 mips_small_data_threshold, mips_arch_info->name, mips_isa);
7843 /* Make the last instruction frame-related and note that it performs
7844 the operation described by FRAME_PATTERN. */
7847 mips_set_frame_expr (rtx frame_pattern)
7851 insn = get_last_insn ();
7852 RTX_FRAME_RELATED_P (insn) = 1;
7853 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7858 /* Return a frame-related rtx that stores REG at MEM.
7859 REG must be a single register. */
7862 mips_frame_set (rtx mem, rtx reg)
7866 /* If we're saving the return address register and the DWARF return
7867 address column differs from the hard register number, adjust the
7868 note reg to refer to the former. */
7869 if (REGNO (reg) == GP_REG_FIRST + 31
7870 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7871 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7873 set = gen_rtx_SET (VOIDmode, mem, reg);
7874 RTX_FRAME_RELATED_P (set) = 1;
7879 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7880 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7881 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7882 static const unsigned char mips16e_s2_s8_regs[] = {
7883 30, 23, 22, 21, 20, 19, 18
7885 static const unsigned char mips16e_a0_a3_regs[] = {
7889 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7890 ordered from the uppermost in memory to the lowest in memory. */
7891 static const unsigned char mips16e_save_restore_regs[] = {
7892 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7895 /* Return the index of the lowest X in the range [0, SIZE) for which
7896 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7899 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7904 for (i = 0; i < size; i++)
7905 if (BITSET_P (mask, regs[i]))
7911 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7912 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7913 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7914 is true for all indexes (X, SIZE). */
7917 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7918 unsigned int size, unsigned int *num_regs_ptr)
7922 i = mips16e_find_first_register (*mask_ptr, regs, size);
7923 for (i++; i < size; i++)
7924 if (!BITSET_P (*mask_ptr, regs[i]))
7927 *mask_ptr |= 1 << regs[i];
7931 /* Return a simplified form of X using the register values in REG_VALUES.
7932 REG_VALUES[R] is the last value assigned to hard register R, or null
7933 if R has not been modified.
7935 This function is rather limited, but is good enough for our purposes. */
7938 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7940 x = avoid_constant_pool_reference (x);
7944 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7945 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7946 x0, GET_MODE (XEXP (x, 0)));
7949 if (ARITHMETIC_P (x))
7951 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7952 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7953 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7957 && reg_values[REGNO (x)]
7958 && !rtx_unstable_p (reg_values[REGNO (x)]))
7959 return reg_values[REGNO (x)];
7964 /* Return true if (set DEST SRC) stores an argument register into its
7965 caller-allocated save slot, storing the number of that argument
7966 register in *REGNO_PTR if so. REG_VALUES is as for
7967 mips16e_collect_propagate_value. */
7970 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7971 unsigned int *regno_ptr)
7973 unsigned int argno, regno;
7974 HOST_WIDE_INT offset, required_offset;
7977 /* Check that this is a word-mode store. */
7978 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7981 /* Check that the register being saved is an unmodified argument
7983 regno = REGNO (src);
7984 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
7986 argno = regno - GP_ARG_FIRST;
7988 /* Check whether the address is an appropriate stack-pointer or
7989 frame-pointer access. */
7990 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7991 mips_split_plus (addr, &base, &offset);
7992 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7993 if (base == hard_frame_pointer_rtx)
7994 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
7995 else if (base != stack_pointer_rtx)
7997 if (offset != required_offset)
8004 /* A subroutine of mips_expand_prologue, called only when generating
8005 MIPS16e SAVE instructions. Search the start of the function for any
8006 instructions that save argument registers into their caller-allocated
8007 save slots. Delete such instructions and return a value N such that
8008 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8009 instructions redundant. */
8012 mips16e_collect_argument_saves (void)
8014 rtx reg_values[FIRST_PSEUDO_REGISTER];
8015 rtx insn, next, set, dest, src;
8016 unsigned int nargs, regno;
8018 push_topmost_sequence ();
8020 memset (reg_values, 0, sizeof (reg_values));
8021 for (insn = get_insns (); insn; insn = next)
8023 next = NEXT_INSN (insn);
8030 set = PATTERN (insn);
8031 if (GET_CODE (set) != SET)
8034 dest = SET_DEST (set);
8035 src = SET_SRC (set);
8036 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8038 if (!BITSET_P (cfun->machine->frame.mask, regno))
8041 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8044 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8045 reg_values[REGNO (dest)]
8046 = mips16e_collect_propagate_value (src, reg_values);
8050 pop_topmost_sequence ();
8055 /* Return a move between register REGNO and memory location SP + OFFSET.
8056 Make the move a load if RESTORE_P, otherwise make it a frame-related
8060 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8065 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8066 reg = gen_rtx_REG (SImode, regno);
8068 ? gen_rtx_SET (VOIDmode, reg, mem)
8069 : mips_frame_set (mem, reg));
8072 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8073 The instruction must:
8075 - Allocate or deallocate SIZE bytes in total; SIZE is known
8078 - Save or restore as many registers in *MASK_PTR as possible.
8079 The instruction saves the first registers at the top of the
8080 allocated area, with the other registers below it.
8082 - Save NARGS argument registers above the allocated area.
8084 (NARGS is always zero if RESTORE_P.)
8086 The SAVE and RESTORE instructions cannot save and restore all general
8087 registers, so there may be some registers left over for the caller to
8088 handle. Destructively modify *MASK_PTR so that it contains the registers
8089 that still need to be saved or restored. The caller can save these
8090 registers in the memory immediately below *OFFSET_PTR, which is a
8091 byte offset from the bottom of the allocated stack area. */
8094 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8095 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8099 HOST_WIDE_INT offset, top_offset;
8100 unsigned int i, regno;
8103 gcc_assert (cfun->machine->frame.num_fp == 0);
8105 /* Calculate the number of elements in the PARALLEL. We need one element
8106 for the stack adjustment, one for each argument register save, and one
8107 for each additional register move. */
8109 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8110 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8113 /* Create the final PARALLEL. */
8114 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8117 /* Add the stack pointer adjustment. */
8118 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8119 plus_constant (stack_pointer_rtx,
8120 restore_p ? size : -size));
8121 RTX_FRAME_RELATED_P (set) = 1;
8122 XVECEXP (pattern, 0, n++) = set;
8124 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8125 top_offset = restore_p ? size : 0;
8127 /* Save the arguments. */
8128 for (i = 0; i < nargs; i++)
8130 offset = top_offset + i * UNITS_PER_WORD;
8131 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8132 XVECEXP (pattern, 0, n++) = set;
8135 /* Then fill in the other register moves. */
8136 offset = top_offset;
8137 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8139 regno = mips16e_save_restore_regs[i];
8140 if (BITSET_P (*mask_ptr, regno))
8142 offset -= UNITS_PER_WORD;
8143 set = mips16e_save_restore_reg (restore_p, offset, regno);
8144 XVECEXP (pattern, 0, n++) = set;
8145 *mask_ptr &= ~(1 << regno);
8149 /* Tell the caller what offset it should use for the remaining registers. */
8150 *offset_ptr = size + (offset - top_offset);
8152 gcc_assert (n == XVECLEN (pattern, 0));
8157 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8158 pointer. Return true if PATTERN matches the kind of instruction
8159 generated by mips16e_build_save_restore. If INFO is nonnull,
8160 initialize it when returning true. */
8163 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8164 struct mips16e_save_restore_info *info)
8166 unsigned int i, nargs, mask, extra;
8167 HOST_WIDE_INT top_offset, save_offset, offset;
8168 rtx set, reg, mem, base;
8171 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8174 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8175 top_offset = adjust > 0 ? adjust : 0;
8177 /* Interpret all other members of the PARALLEL. */
8178 save_offset = top_offset - UNITS_PER_WORD;
8182 for (n = 1; n < XVECLEN (pattern, 0); n++)
8184 /* Check that we have a SET. */
8185 set = XVECEXP (pattern, 0, n);
8186 if (GET_CODE (set) != SET)
8189 /* Check that the SET is a load (if restoring) or a store
8191 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8195 /* Check that the address is the sum of the stack pointer and a
8196 possibly-zero constant offset. */
8197 mips_split_plus (XEXP (mem, 0), &base, &offset);
8198 if (base != stack_pointer_rtx)
8201 /* Check that SET's other operand is a register. */
8202 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8206 /* Check for argument saves. */
8207 if (offset == top_offset + nargs * UNITS_PER_WORD
8208 && REGNO (reg) == GP_ARG_FIRST + nargs)
8210 else if (offset == save_offset)
8212 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8213 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8216 mask |= 1 << REGNO (reg);
8217 save_offset -= UNITS_PER_WORD;
8223 /* Check that the restrictions on register ranges are met. */
8225 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8226 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8227 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8228 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8232 /* Make sure that the topmost argument register is not saved twice.
8233 The checks above ensure that the same is then true for the other
8234 argument registers. */
8235 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8238 /* Pass back information, if requested. */
8241 info->nargs = nargs;
8243 info->size = (adjust > 0 ? adjust : -adjust);
8249 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8250 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8251 the null terminator. */
8254 mips16e_add_register_range (char *s, unsigned int min_reg,
8255 unsigned int max_reg)
8257 if (min_reg != max_reg)
8258 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8260 s += sprintf (s, ",%s", reg_names[min_reg]);
8264 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8265 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8268 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8270 static char buffer[300];
8272 struct mips16e_save_restore_info info;
8273 unsigned int i, end;
8276 /* Parse the pattern. */
8277 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8280 /* Add the mnemonic. */
8281 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8284 /* Save the arguments. */
8286 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8287 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8288 else if (info.nargs == 1)
8289 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8291 /* Emit the amount of stack space to allocate or deallocate. */
8292 s += sprintf (s, "%d", (int) info.size);
8294 /* Save or restore $16. */
8295 if (BITSET_P (info.mask, 16))
8296 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8298 /* Save or restore $17. */
8299 if (BITSET_P (info.mask, 17))
8300 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8302 /* Save or restore registers in the range $s2...$s8, which
8303 mips16e_s2_s8_regs lists in decreasing order. Note that this
8304 is a software register range; the hardware registers are not
8305 numbered consecutively. */
8306 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8307 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8309 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8310 mips16e_s2_s8_regs[i]);
8312 /* Save or restore registers in the range $a0...$a3. */
8313 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8314 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8316 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8317 mips16e_a0_a3_regs[end - 1]);
8319 /* Save or restore $31. */
8320 if (BITSET_P (info.mask, 31))
8321 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
8326 /* Return true if the current function has an insn that implicitly
8330 mips_function_has_gp_insn (void)
8332 /* Don't bother rechecking if we found one last time. */
8333 if (!cfun->machine->has_gp_insn_p)
8337 push_topmost_sequence ();
8338 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8339 if (USEFUL_INSN_P (insn)
8340 && (get_attr_got (insn) != GOT_UNSET
8341 || mips_small_data_pattern_p (PATTERN (insn))))
8343 cfun->machine->has_gp_insn_p = true;
8346 pop_topmost_sequence ();
8348 return cfun->machine->has_gp_insn_p;
8351 /* Return true if the current function returns its value in a floating-point
8352 register in MIPS16 mode. */
8355 mips16_cfun_returns_in_fpr_p (void)
8357 tree return_type = DECL_RESULT (current_function_decl);
8358 return (TARGET_MIPS16
8359 && TARGET_HARD_FLOAT_ABI
8360 && !aggregate_value_p (return_type, current_function_decl)
8361 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8364 /* Return the register that should be used as the global pointer
8365 within this function. Return INVALID_REGNUM if the function
8366 doesn't need a global pointer. */
8369 mips_global_pointer (void)
8373 /* $gp is always available unless we're using a GOT. */
8374 if (!TARGET_USE_GOT)
8375 return GLOBAL_POINTER_REGNUM;
8377 /* We must always provide $gp when it is used implicitly. */
8378 if (!TARGET_EXPLICIT_RELOCS)
8379 return GLOBAL_POINTER_REGNUM;
8381 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
8384 return GLOBAL_POINTER_REGNUM;
8386 /* If the function has a nonlocal goto, $gp must hold the correct
8387 global pointer for the target function. */
8388 if (crtl->has_nonlocal_goto)
8389 return GLOBAL_POINTER_REGNUM;
8391 /* There's no need to initialize $gp if it isn't referenced now,
8392 and if we can be sure that no new references will be added during
8394 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
8395 && !mips_function_has_gp_insn ())
8397 /* The function doesn't use $gp at the moment. If we're generating
8398 -call_nonpic code, no new uses will be introduced during or after
8400 if (TARGET_ABICALLS_PIC0)
8401 return INVALID_REGNUM;
8403 /* We need to handle the following implicit gp references:
8405 - Reload can sometimes introduce constant pool references
8406 into a function that otherwise didn't need them. For example,
8407 suppose we have an instruction like:
8409 (set (reg:DF R1) (float:DF (reg:SI R2)))
8411 If R2 turns out to be constant such as 1, the instruction may
8412 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8413 the option of using this constant if R2 doesn't get allocated
8416 In cases like these, reload will have added the constant to the
8417 pool but no instruction will yet refer to it.
8419 - MIPS16 functions that return in FPRs need to call an
8420 external libgcc routine. */
8421 if (!crtl->uses_const_pool
8422 && !mips16_cfun_returns_in_fpr_p ())
8423 return INVALID_REGNUM;
8426 /* We need a global pointer, but perhaps we can use a call-clobbered
8427 register instead of $gp. */
8428 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8429 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8430 if (!df_regs_ever_live_p (regno)
8431 && call_really_used_regs[regno]
8432 && !fixed_regs[regno]
8433 && regno != PIC_FUNCTION_ADDR_REGNUM)
8436 return GLOBAL_POINTER_REGNUM;
8439 /* Return true if the current function should treat register REGNO
8443 mips_cfun_call_saved_reg_p (unsigned int regno)
8445 /* call_insns preserve $28 unless they explicitly say otherwise,
8446 so call_really_used_regs[] treats $28 as call-saved. However,
8447 we want the ABI property rather than the default call_insn
8449 return (regno == GLOBAL_POINTER_REGNUM
8450 ? TARGET_CALL_SAVED_GP
8451 : !call_really_used_regs[regno]);
8454 /* Return true if the function body might clobber register REGNO.
8455 We know that REGNO is call-saved. */
8458 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
8460 /* Some functions should be treated as clobbering all call-saved
8462 if (crtl->saves_all_registers)
8465 /* DF handles cases where a register is explicitly referenced in
8466 the rtl. Incoming values are passed in call-clobbered registers,
8467 so we can assume that any live call-saved register is set within
8469 if (df_regs_ever_live_p (regno))
8472 /* Check for registers that are clobbered by FUNCTION_PROFILER.
8473 These clobbers are not explicit in the rtl. */
8474 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
8477 /* If we're using a call-saved global pointer, the function's
8478 prologue will need to set it up. */
8479 if (cfun->machine->global_pointer == regno)
8482 /* The function's prologue will need to set the frame pointer if
8483 frame_pointer_needed. */
8484 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
8487 /* If a MIPS16 function returns a value in FPRs, its epilogue
8488 will need to call an external libgcc routine. This yet-to-be
8489 generated call_insn will clobber $31. */
8490 if (regno == GP_REG_FIRST + 31 && mips16_cfun_returns_in_fpr_p ())
8496 /* Return true if the current function must save register REGNO. */
8499 mips_save_reg_p (unsigned int regno)
8501 if (mips_cfun_call_saved_reg_p (regno))
8503 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
8506 /* Save both registers in an FPR pair if either one is used. This is
8507 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
8508 register to be used without the even register. */
8509 if (FP_REG_P (regno)
8510 && MAX_FPRS_PER_FMT == 2
8511 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
8515 /* We need to save the incoming return address if __builtin_eh_return
8516 is being used to set a different return address. */
8517 if (regno == GP_REG_FIRST + 31 && crtl->calls_eh_return)
8523 /* Populate the current function's mips_frame_info structure.
8525 MIPS stack frames look like:
8527 +-------------------------------+
8529 | incoming stack arguments |
8531 +-------------------------------+
8533 | caller-allocated save area |
8534 A | for register arguments |
8536 +-------------------------------+ <-- incoming stack pointer
8538 | callee-allocated save area |
8539 B | for arguments that are |
8540 | split between registers and |
8543 +-------------------------------+ <-- arg_pointer_rtx
8545 C | callee-allocated save area |
8546 | for register varargs |
8548 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
8549 | | + UNITS_PER_HWFPVALUE
8552 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
8553 | | + UNITS_PER_WORD
8556 +-------------------------------+
8558 | local variables | | var_size
8560 +-------------------------------+
8562 | $gp save area | | cprestore_size
8564 P +-------------------------------+ <-- hard_frame_pointer_rtx for
8566 | outgoing stack arguments |
8568 +-------------------------------+
8570 | caller-allocated save area |
8571 | for register arguments |
8573 +-------------------------------+ <-- stack_pointer_rtx
8575 hard_frame_pointer_rtx for
8578 At least two of A, B and C will be empty.
8580 Dynamic stack allocations such as alloca insert data at point P.
8581 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
8582 hard_frame_pointer_rtx unchanged. */
8585 mips_compute_frame_info (void)
8587 struct mips_frame_info *frame;
8588 HOST_WIDE_INT offset, size;
8589 unsigned int regno, i;
8591 frame = &cfun->machine->frame;
8592 memset (frame, 0, sizeof (*frame));
8593 size = get_frame_size ();
8595 cfun->machine->global_pointer = mips_global_pointer ();
8597 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
8598 area and the $gp save slot. This area isn't needed in leaf functions,
8599 but if the target-independent frame size is nonzero, we're committed
8600 to allocating it anyway. */
8601 if (size == 0 && current_function_is_leaf)
8603 /* The MIPS 3.0 linker does not like functions that dynamically
8604 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8605 looks like we are trying to create a second frame pointer to the
8606 function, so allocate some stack space to make it happy. */
8607 if (cfun->calls_alloca)
8608 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
8610 frame->args_size = 0;
8611 frame->cprestore_size = 0;
8615 frame->args_size = crtl->outgoing_args_size;
8616 frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
8618 offset = frame->args_size + frame->cprestore_size;
8620 /* Move above the local variables. */
8621 frame->var_size = MIPS_STACK_ALIGN (size);
8622 offset += frame->var_size;
8624 /* Find out which GPRs we need to save. */
8625 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8626 if (mips_save_reg_p (regno))
8629 frame->mask |= 1 << (regno - GP_REG_FIRST);
8632 /* If this function calls eh_return, we must also save and restore the
8633 EH data registers. */
8634 if (crtl->calls_eh_return)
8635 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
8638 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
8641 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8642 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8643 save all later registers too. */
8644 if (GENERATE_MIPS16E_SAVE_RESTORE)
8646 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
8647 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
8648 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
8649 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
8652 /* Move above the GPR save area. */
8653 if (frame->num_gp > 0)
8655 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
8656 frame->gp_sp_offset = offset - UNITS_PER_WORD;
8659 /* Find out which FPRs we need to save. This loop must iterate over
8660 the same space as its companion in mips_for_each_saved_reg. */
8661 if (TARGET_HARD_FLOAT)
8662 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
8663 if (mips_save_reg_p (regno))
8665 frame->num_fp += MAX_FPRS_PER_FMT;
8666 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
8669 /* Move above the FPR save area. */
8670 if (frame->num_fp > 0)
8672 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
8673 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
8676 /* Move above the callee-allocated varargs save area. */
8677 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
8678 frame->arg_pointer_offset = offset;
8680 /* Move above the callee-allocated area for pretend stack arguments. */
8681 offset += crtl->args.pretend_args_size;
8682 frame->total_size = offset;
8684 /* Work out the offsets of the save areas from the top of the frame. */
8685 if (frame->gp_sp_offset > 0)
8686 frame->gp_save_offset = frame->gp_sp_offset - offset;
8687 if (frame->fp_sp_offset > 0)
8688 frame->fp_save_offset = frame->fp_sp_offset - offset;
8690 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8691 arguments. This tends to increase the chances of using unextended
8692 instructions for local variables and incoming arguments. */
8694 frame->hard_frame_pointer_offset = frame->args_size;
8697 /* Return the style of GP load sequence that is being used for the
8698 current function. */
8700 enum mips_loadgp_style
8701 mips_current_loadgp_style (void)
8703 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
8709 if (TARGET_ABSOLUTE_ABICALLS)
8710 return LOADGP_ABSOLUTE;
8712 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
8715 /* Implement FRAME_POINTER_REQUIRED. */
8718 mips_frame_pointer_required (void)
8720 /* If the function contains dynamic stack allocations, we need to
8721 use the frame pointer to access the static parts of the frame. */
8722 if (cfun->calls_alloca)
8725 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8726 reload may be unable to compute the address of a local variable,
8727 since there is no way to add a large constant to the stack pointer
8728 without using a second temporary register. */
8731 mips_compute_frame_info ();
8732 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8739 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8740 or argument pointer. TO is either the stack pointer or hard frame
8744 mips_initial_elimination_offset (int from, int to)
8746 HOST_WIDE_INT offset;
8748 mips_compute_frame_info ();
8750 /* Set OFFSET to the offset from the soft frame pointer, which is also
8751 the offset from the end-of-prologue stack pointer. */
8754 case FRAME_POINTER_REGNUM:
8758 case ARG_POINTER_REGNUM:
8759 offset = cfun->machine->frame.arg_pointer_offset;
8766 if (to == HARD_FRAME_POINTER_REGNUM)
8767 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8772 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8775 mips_extra_live_on_entry (bitmap regs)
8779 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8780 the global pointer. */
8781 if (!TARGET_ABSOLUTE_ABICALLS)
8782 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8784 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
8785 the global pointer. */
8787 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
8789 /* See the comment above load_call<mode> for details. */
8790 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
8794 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8798 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
8803 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
8806 /* Emit code to change the current function's return address to
8807 ADDRESS. SCRATCH is available as a scratch register, if needed.
8808 ADDRESS and SCRATCH are both word-mode GPRs. */
8811 mips_set_return_address (rtx address, rtx scratch)
8815 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
8816 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
8817 cfun->machine->frame.gp_sp_offset);
8818 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
8821 /* Return a MEM rtx for the cprestore slot, using TEMP as a temporary base
8822 register if need be. */
8825 mips_cprestore_slot (rtx temp)
8827 const struct mips_frame_info *frame;
8829 HOST_WIDE_INT offset;
8831 frame = &cfun->machine->frame;
8832 if (frame_pointer_needed)
8834 base = hard_frame_pointer_rtx;
8835 offset = frame->args_size - frame->hard_frame_pointer_offset;
8839 base = stack_pointer_rtx;
8840 offset = frame->args_size;
8842 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
8845 /* Restore $gp from its save slot, using TEMP as a temporary base register
8846 if need be. This function is for o32 and o64 abicalls only. */
8849 mips_restore_gp (rtx temp)
8851 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
8853 if (cfun->machine->global_pointer == INVALID_REGNUM)
8858 mips_emit_move (temp, mips_cprestore_slot (temp));
8859 mips_emit_move (pic_offset_table_rtx, temp);
8862 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp));
8863 if (!TARGET_EXPLICIT_RELOCS)
8864 emit_insn (gen_blockage ());
8867 /* A function to save or store a register. The first argument is the
8868 register and the second is the stack slot. */
8869 typedef void (*mips_save_restore_fn) (rtx, rtx);
8871 /* Use FN to save or restore register REGNO. MODE is the register's
8872 mode and OFFSET is the offset of its save slot from the current
8876 mips_save_restore_reg (enum machine_mode mode, int regno,
8877 HOST_WIDE_INT offset, mips_save_restore_fn fn)
8881 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
8882 fn (gen_rtx_REG (mode, regno), mem);
8885 /* Call FN for each register that is saved by the current function.
8886 SP_OFFSET is the offset of the current stack pointer from the start
8890 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
8892 enum machine_mode fpr_mode;
8893 HOST_WIDE_INT offset;
8896 /* Save registers starting from high to low. The debuggers prefer at least
8897 the return register be stored at func+4, and also it allows us not to
8898 need a nop in the epilogue if at least one register is reloaded in
8899 addition to return address. */
8900 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
8901 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
8902 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
8904 mips_save_restore_reg (word_mode, regno, offset, fn);
8905 offset -= UNITS_PER_WORD;
8908 /* This loop must iterate over the same space as its companion in
8909 mips_compute_frame_info. */
8910 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
8911 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
8912 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
8913 regno >= FP_REG_FIRST;
8914 regno -= MAX_FPRS_PER_FMT)
8915 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
8917 mips_save_restore_reg (fpr_mode, regno, offset, fn);
8918 offset -= GET_MODE_SIZE (fpr_mode);
8922 /* If we're generating n32 or n64 abicalls, and the current function
8923 does not use $28 as its global pointer, emit a cplocal directive.
8924 Use pic_offset_table_rtx as the argument to the directive. */
8927 mips_output_cplocal (void)
8929 if (!TARGET_EXPLICIT_RELOCS
8930 && cfun->machine->global_pointer != INVALID_REGNUM
8931 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
8932 output_asm_insn (".cplocal %+", 0);
8935 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
8938 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8942 #ifdef SDB_DEBUGGING_INFO
8943 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8944 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8947 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
8948 floating-point arguments. */
8950 && TARGET_HARD_FLOAT_ABI
8951 && crtl->args.info.fp_code != 0)
8952 mips16_build_function_stub ();
8954 /* Get the function name the same way that toplev.c does before calling
8955 assemble_start_function. This is needed so that the name used here
8956 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8957 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8958 mips_start_function_definition (fnname, TARGET_MIPS16);
8960 /* Stop mips_file_end from treating this function as external. */
8961 if (TARGET_IRIX && mips_abi == ABI_32)
8962 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
8964 /* Output MIPS-specific frame information. */
8965 if (!flag_inhibit_size_directive)
8967 const struct mips_frame_info *frame;
8969 frame = &cfun->machine->frame;
8971 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
8973 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
8974 "# vars= " HOST_WIDE_INT_PRINT_DEC
8976 ", args= " HOST_WIDE_INT_PRINT_DEC
8977 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
8978 reg_names[frame_pointer_needed
8979 ? HARD_FRAME_POINTER_REGNUM
8980 : STACK_POINTER_REGNUM],
8981 (frame_pointer_needed
8982 ? frame->total_size - frame->hard_frame_pointer_offset
8983 : frame->total_size),
8984 reg_names[GP_REG_FIRST + 31],
8986 frame->num_gp, frame->num_fp,
8988 frame->cprestore_size);
8990 /* .mask MASK, OFFSET. */
8991 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8992 frame->mask, frame->gp_save_offset);
8994 /* .fmask MASK, OFFSET. */
8995 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8996 frame->fmask, frame->fp_save_offset);
8999 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9000 Also emit the ".set noreorder; .set nomacro" sequence for functions
9002 if (mips_current_loadgp_style () == LOADGP_OLDABI)
9006 /* This is a fixed-form sequence. The position of the
9007 first two instructions is important because of the
9008 way _gp_disp is defined. */
9009 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9010 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9011 output_asm_insn ("sll\t$2,16", 0);
9012 output_asm_insn ("addu\t$2,$3", 0);
9014 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
9015 else if (!cfun->machine->all_noreorder_p)
9016 output_asm_insn ("%(.cpload\t%^%)", 0);
9018 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
9020 else if (cfun->machine->all_noreorder_p)
9021 output_asm_insn ("%(%<", 0);
9023 /* Tell the assembler which register we're using as the global
9024 pointer. This is needed for thunks, since they can use either
9025 explicit relocs or assembler macros. */
9026 mips_output_cplocal ();
9029 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9032 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9033 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9037 /* Reinstate the normal $gp. */
9038 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9039 mips_output_cplocal ();
9041 if (cfun->machine->all_noreorder_p)
9043 /* Avoid using %>%) since it adds excess whitespace. */
9044 output_asm_insn (".set\tmacro", 0);
9045 output_asm_insn (".set\treorder", 0);
9046 set_noreorder = set_nomacro = 0;
9049 /* Get the function name the same way that toplev.c does before calling
9050 assemble_start_function. This is needed so that the name used here
9051 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9052 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9053 mips_end_function_definition (fnname);
9056 /* Save register REG to MEM. Make the instruction frame-related. */
9059 mips_save_reg (rtx reg, rtx mem)
9061 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9065 if (mips_split_64bit_move_p (mem, reg))
9066 mips_split_doubleword_move (mem, reg);
9068 mips_emit_move (mem, reg);
9070 x1 = mips_frame_set (mips_subword (mem, false),
9071 mips_subword (reg, false));
9072 x2 = mips_frame_set (mips_subword (mem, true),
9073 mips_subword (reg, true));
9074 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9079 && REGNO (reg) != GP_REG_FIRST + 31
9080 && !M16_REG_P (REGNO (reg)))
9082 /* Save a non-MIPS16 register by moving it through a temporary.
9083 We don't need to do this for $31 since there's a special
9084 instruction for it. */
9085 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
9086 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9089 mips_emit_move (mem, reg);
9091 mips_set_frame_expr (mips_frame_set (mem, reg));
9095 /* The __gnu_local_gp symbol. */
9097 static GTY(()) rtx mips_gnu_local_gp;
9099 /* If we're generating n32 or n64 abicalls, emit instructions
9100 to set up the global pointer. */
9103 mips_emit_loadgp (void)
9105 rtx addr, offset, incoming_address, base, index, pic_reg;
9107 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9108 switch (mips_current_loadgp_style ())
9110 case LOADGP_ABSOLUTE:
9111 if (mips_gnu_local_gp == NULL)
9113 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9114 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9116 emit_insn (Pmode == SImode
9117 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9118 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9122 /* Added by mips_output_function_prologue. */
9126 addr = XEXP (DECL_RTL (current_function_decl), 0);
9127 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9128 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9129 emit_insn (Pmode == SImode
9130 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9131 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9135 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9136 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9137 emit_insn (Pmode == SImode
9138 ? gen_loadgp_rtp_si (pic_reg, base, index)
9139 : gen_loadgp_rtp_di (pic_reg, base, index));
9147 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9149 /* Emit a blockage if there are implicit uses of the GP register.
9150 This includes profiled functions, because FUNCTION_PROFILE uses
9152 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9153 emit_insn (gen_loadgp_blockage ());
9156 /* Expand the "prologue" pattern. */
9159 mips_expand_prologue (void)
9161 const struct mips_frame_info *frame;
9166 if (cfun->machine->global_pointer != INVALID_REGNUM)
9167 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
9169 frame = &cfun->machine->frame;
9170 size = frame->total_size;
9172 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9173 bytes beforehand; this is enough to cover the register save area
9174 without going out of range. */
9175 if ((frame->mask | frame->fmask) != 0)
9177 HOST_WIDE_INT step1;
9179 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
9180 if (GENERATE_MIPS16E_SAVE_RESTORE)
9182 HOST_WIDE_INT offset;
9183 unsigned int mask, regno;
9185 /* Try to merge argument stores into the save instruction. */
9186 nargs = mips16e_collect_argument_saves ();
9188 /* Build the save instruction. */
9190 insn = mips16e_build_save_restore (false, &mask, &offset,
9192 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9195 /* Check if we need to save other registers. */
9196 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9197 if (BITSET_P (mask, regno - GP_REG_FIRST))
9199 offset -= UNITS_PER_WORD;
9200 mips_save_restore_reg (word_mode, regno,
9201 offset, mips_save_reg);
9206 insn = gen_add3_insn (stack_pointer_rtx,
9209 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9211 mips_for_each_saved_reg (size, mips_save_reg);
9215 /* Allocate the rest of the frame. */
9218 if (SMALL_OPERAND (-size))
9219 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
9221 GEN_INT (-size)))) = 1;
9224 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
9227 /* There are no instructions to add or subtract registers
9228 from the stack pointer, so use the frame pointer as a
9229 temporary. We should always be using a frame pointer
9230 in this case anyway. */
9231 gcc_assert (frame_pointer_needed);
9232 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9233 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
9234 hard_frame_pointer_rtx,
9235 MIPS_PROLOGUE_TEMP (Pmode)));
9236 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
9239 emit_insn (gen_sub3_insn (stack_pointer_rtx,
9241 MIPS_PROLOGUE_TEMP (Pmode)));
9243 /* Describe the combined effect of the previous instructions. */
9245 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9246 plus_constant (stack_pointer_rtx, -size)));
9250 /* Set up the frame pointer, if we're using one. */
9251 if (frame_pointer_needed)
9253 HOST_WIDE_INT offset;
9255 offset = frame->hard_frame_pointer_offset;
9258 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9259 RTX_FRAME_RELATED_P (insn) = 1;
9261 else if (SMALL_OPERAND (offset))
9263 insn = gen_add3_insn (hard_frame_pointer_rtx,
9264 stack_pointer_rtx, GEN_INT (offset));
9265 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9269 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
9270 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9271 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
9272 hard_frame_pointer_rtx,
9273 MIPS_PROLOGUE_TEMP (Pmode)));
9275 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
9276 plus_constant (stack_pointer_rtx, offset)));
9280 mips_emit_loadgp ();
9282 /* Initialize the $gp save slot. */
9283 if (frame->cprestore_size > 0
9284 && cfun->machine->global_pointer != INVALID_REGNUM)
9287 mips_emit_move (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9289 else if (TARGET_ABICALLS_PIC2)
9290 emit_insn (gen_cprestore (GEN_INT (frame->args_size)));
9292 emit_move_insn (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9293 pic_offset_table_rtx);
9296 /* If we are profiling, make sure no instructions are scheduled before
9297 the call to mcount. */
9299 emit_insn (gen_blockage ());
9302 /* Emit instructions to restore register REG from slot MEM. */
9305 mips_restore_reg (rtx reg, rtx mem)
9307 /* There's no MIPS16 instruction to load $31 directly. Load into
9308 $7 instead and adjust the return insn appropriately. */
9309 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
9310 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
9312 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
9314 /* Can't restore directly; move through a temporary. */
9315 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
9316 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
9319 mips_emit_move (reg, mem);
9322 /* Emit any instructions needed before a return. */
9325 mips_expand_before_return (void)
9327 /* When using a call-clobbered gp, we start out with unified call
9328 insns that include instructions to restore the gp. We then split
9329 these unified calls after reload. These split calls explicitly
9330 clobber gp, so there is no need to define
9331 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
9333 For consistency, we should also insert an explicit clobber of $28
9334 before return insns, so that the post-reload optimizers know that
9335 the register is not live on exit. */
9336 if (TARGET_CALL_CLOBBERED_GP)
9337 emit_clobber (pic_offset_table_rtx);
9340 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
9344 mips_expand_epilogue (bool sibcall_p)
9346 const struct mips_frame_info *frame;
9347 HOST_WIDE_INT step1, step2;
9350 if (!sibcall_p && mips_can_use_return_insn ())
9352 emit_jump_insn (gen_return ());
9356 /* In MIPS16 mode, if the return value should go into a floating-point
9357 register, we need to call a helper routine to copy it over. */
9358 if (mips16_cfun_returns_in_fpr_p ())
9359 mips16_copy_fpr_return_value ();
9361 /* Split the frame into two. STEP1 is the amount of stack we should
9362 deallocate before restoring the registers. STEP2 is the amount we
9363 should deallocate afterwards.
9365 Start off by assuming that no registers need to be restored. */
9366 frame = &cfun->machine->frame;
9367 step1 = frame->total_size;
9370 /* Work out which register holds the frame address. */
9371 if (!frame_pointer_needed)
9372 base = stack_pointer_rtx;
9375 base = hard_frame_pointer_rtx;
9376 step1 -= frame->hard_frame_pointer_offset;
9379 /* If we need to restore registers, deallocate as much stack as
9380 possible in the second step without going out of range. */
9381 if ((frame->mask | frame->fmask) != 0)
9383 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
9387 /* Set TARGET to BASE + STEP1. */
9393 /* Get an rtx for STEP1 that we can add to BASE. */
9394 adjust = GEN_INT (step1);
9395 if (!SMALL_OPERAND (step1))
9397 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
9398 adjust = MIPS_EPILOGUE_TEMP (Pmode);
9401 /* Normal mode code can copy the result straight into $sp. */
9403 target = stack_pointer_rtx;
9405 emit_insn (gen_add3_insn (target, base, adjust));
9408 /* Copy TARGET into the stack pointer. */
9409 if (target != stack_pointer_rtx)
9410 mips_emit_move (stack_pointer_rtx, target);
9412 /* If we're using addressing macros, $gp is implicitly used by all
9413 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
9415 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
9416 emit_insn (gen_blockage ());
9418 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
9420 unsigned int regno, mask;
9421 HOST_WIDE_INT offset;
9424 /* Generate the restore instruction. */
9426 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
9428 /* Restore any other registers manually. */
9429 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9430 if (BITSET_P (mask, regno - GP_REG_FIRST))
9432 offset -= UNITS_PER_WORD;
9433 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
9436 /* Restore the remaining registers and deallocate the final bit
9438 emit_insn (restore);
9442 /* Restore the registers. */
9443 mips_for_each_saved_reg (frame->total_size - step2, mips_restore_reg);
9445 /* Deallocate the final bit of the frame. */
9447 emit_insn (gen_add3_insn (stack_pointer_rtx,
9452 /* Add in the __builtin_eh_return stack adjustment. We need to
9453 use a temporary in MIPS16 code. */
9454 if (crtl->calls_eh_return)
9458 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
9459 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
9460 MIPS_EPILOGUE_TEMP (Pmode),
9461 EH_RETURN_STACKADJ_RTX));
9462 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
9465 emit_insn (gen_add3_insn (stack_pointer_rtx,
9467 EH_RETURN_STACKADJ_RTX));
9474 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
9475 path will restore the return address into $7 rather than $31. */
9477 && !GENERATE_MIPS16E_SAVE_RESTORE
9478 && BITSET_P (frame->mask, 31))
9479 regno = GP_REG_FIRST + 7;
9481 regno = GP_REG_FIRST + 31;
9482 mips_expand_before_return ();
9483 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
9487 /* Return nonzero if this function is known to have a null epilogue.
9488 This allows the optimizer to omit jumps to jumps if no stack
9492 mips_can_use_return_insn (void)
9494 if (!reload_completed)
9500 /* In MIPS16 mode, a function that returns a floating-point value
9501 needs to arrange to copy the return value into the floating-point
9503 if (mips16_cfun_returns_in_fpr_p ())
9506 return cfun->machine->frame.total_size == 0;
9509 /* Return true if register REGNO can store a value of mode MODE.
9510 The result of this function is cached in mips_hard_regno_mode_ok. */
9513 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
9516 enum mode_class mclass;
9518 if (mode == CCV2mode)
9521 && (regno - ST_REG_FIRST) % 2 == 0);
9523 if (mode == CCV4mode)
9526 && (regno - ST_REG_FIRST) % 4 == 0);
9531 return regno == FPSW_REGNUM;
9533 return (ST_REG_P (regno)
9535 || FP_REG_P (regno));
9538 size = GET_MODE_SIZE (mode);
9539 mclass = GET_MODE_CLASS (mode);
9541 if (GP_REG_P (regno))
9542 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
9544 if (FP_REG_P (regno)
9545 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
9546 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
9548 /* Allow TFmode for CCmode reloads. */
9549 if (mode == TFmode && ISA_HAS_8CC)
9552 /* Allow 64-bit vector modes for Loongson-2E/2F. */
9553 if (TARGET_LOONGSON_VECTORS
9554 && (mode == V2SImode
9560 if (mclass == MODE_FLOAT
9561 || mclass == MODE_COMPLEX_FLOAT
9562 || mclass == MODE_VECTOR_FLOAT)
9563 return size <= UNITS_PER_FPVALUE;
9565 /* Allow integer modes that fit into a single register. We need
9566 to put integers into FPRs when using instructions like CVT
9567 and TRUNC. There's no point allowing sizes smaller than a word,
9568 because the FPU has no appropriate load/store instructions. */
9569 if (mclass == MODE_INT)
9570 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
9573 if (ACC_REG_P (regno)
9574 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
9576 if (MD_REG_P (regno))
9578 /* After a multiplication or division, clobbering HI makes
9579 the value of LO unpredictable, and vice versa. This means
9580 that, for all interesting cases, HI and LO are effectively
9583 We model this by requiring that any value that uses HI
9585 if (size <= UNITS_PER_WORD * 2)
9586 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
9590 /* DSP accumulators do not have the same restrictions as
9591 HI and LO, so we can treat them as normal doubleword
9593 if (size <= UNITS_PER_WORD)
9596 if (size <= UNITS_PER_WORD * 2
9597 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
9602 if (ALL_COP_REG_P (regno))
9603 return mclass == MODE_INT && size <= UNITS_PER_WORD;
9605 if (regno == GOT_VERSION_REGNUM)
9606 return mode == SImode;
9611 /* Implement HARD_REGNO_NREGS. */
9614 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9616 if (ST_REG_P (regno))
9617 /* The size of FP status registers is always 4, because they only hold
9618 CCmode values, and CCmode is always considered to be 4 bytes wide. */
9619 return (GET_MODE_SIZE (mode) + 3) / 4;
9621 if (FP_REG_P (regno))
9622 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
9624 /* All other registers are word-sized. */
9625 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
9628 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
9629 in mips_hard_regno_nregs. */
9632 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
9638 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
9639 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
9641 size = MIN (size, 4);
9642 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
9644 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
9646 size = MIN (size, UNITS_PER_FPREG);
9647 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
9649 if (!hard_reg_set_empty_p (left))
9650 size = MIN (size, UNITS_PER_WORD);
9651 return (GET_MODE_SIZE (mode) + size - 1) / size;
9654 /* Implement CANNOT_CHANGE_MODE_CLASS. */
9657 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
9658 enum machine_mode to ATTRIBUTE_UNUSED,
9659 enum reg_class rclass)
9661 /* There are several problems with changing the modes of values
9662 in floating-point registers:
9664 - When a multi-word value is stored in paired floating-point
9665 registers, the first register always holds the low word.
9666 We therefore can't allow FPRs to change between single-word
9667 and multi-word modes on big-endian targets.
9669 - GCC assumes that each word of a multiword register can be accessed
9670 individually using SUBREGs. This is not true for floating-point
9671 registers if they are bigger than a word.
9673 - Loading a 32-bit value into a 64-bit floating-point register
9674 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
9675 We can't allow FPRs to change from SImode to to a wider mode on
9678 - If the FPU has already interpreted a value in one format, we must
9679 not ask it to treat the value as having a different format.
9681 We therefore disallow all mode changes involving FPRs. */
9682 return reg_classes_intersect_p (FP_REGS, rclass);
9685 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
9688 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
9693 return TARGET_HARD_FLOAT;
9696 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
9699 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
9706 /* Implement MODES_TIEABLE_P. */
9709 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9711 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
9712 prefer to put one of them in FPRs. */
9713 return (mode1 == mode2
9714 || (!mips_mode_ok_for_mov_fmt_p (mode1)
9715 && !mips_mode_ok_for_mov_fmt_p (mode2)));
9718 /* Implement PREFERRED_RELOAD_CLASS. */
9721 mips_preferred_reload_class (rtx x, enum reg_class rclass)
9723 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
9726 if (reg_class_subset_p (FP_REGS, rclass)
9727 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
9730 if (reg_class_subset_p (GR_REGS, rclass))
9733 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
9739 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
9740 Return a "canonical" class to represent it in later calculations. */
9742 static enum reg_class
9743 mips_canonicalize_move_class (enum reg_class rclass)
9745 /* All moves involving accumulator registers have the same cost. */
9746 if (reg_class_subset_p (rclass, ACC_REGS))
9749 /* Likewise promote subclasses of general registers to the most
9750 interesting containing class. */
9751 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
9753 else if (reg_class_subset_p (rclass, GENERAL_REGS))
9754 rclass = GENERAL_REGS;
9759 /* Return the cost of moving a value of mode MODE from a register of
9760 class FROM to a GPR. Return 0 for classes that are unions of other
9761 classes handled by this function. */
9764 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9765 enum reg_class from)
9770 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
9774 /* MFLO and MFHI. */
9782 /* LUI followed by MOVF. */
9788 /* This choice of value is historical. */
9796 /* Return the cost of moving a value of mode MODE from a GPR to a
9797 register of class TO. Return 0 for classes that are unions of
9798 other classes handled by this function. */
9801 mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to)
9806 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
9810 /* MTLO and MTHI. */
9818 /* A secondary reload through an FPR scratch. */
9819 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
9820 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
9825 /* This choice of value is historical. */
9833 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
9834 maximum of the move costs for subclasses; regclass will work out
9835 the maximum for us. */
9838 mips_register_move_cost (enum machine_mode mode,
9839 enum reg_class from, enum reg_class to)
9841 enum reg_class dregs;
9844 from = mips_canonicalize_move_class (from);
9845 to = mips_canonicalize_move_class (to);
9847 /* Handle moves that can be done without using general-purpose registers. */
9848 if (from == FP_REGS)
9850 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
9854 /* The sequence generated by mips_expand_fcc_reload. */
9858 /* Handle cases in which only one class deviates from the ideal. */
9859 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
9861 return mips_move_from_gpr_cost (mode, to);
9863 return mips_move_to_gpr_cost (mode, from);
9865 /* Handles cases that require a GPR temporary. */
9866 cost1 = mips_move_to_gpr_cost (mode, from);
9869 cost2 = mips_move_from_gpr_cost (mode, to);
9871 return cost1 + cost2;
9877 /* Implement TARGET_IRA_COVER_CLASSES. */
9879 static const enum reg_class *
9880 mips_ira_cover_classes (void)
9882 static const enum reg_class acc_classes[] = {
9883 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
9884 ST_REGS, LIM_REG_CLASSES
9886 static const enum reg_class no_acc_classes[] = {
9887 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
9888 ST_REGS, LIM_REG_CLASSES
9891 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
9892 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
9893 as a cover class only works well when we keep per-register costs.
9894 Using it when not optimizing can cause us to think accumulators
9895 have the same cost as GPRs in cases where GPRs are actually much
9897 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
9900 /* Return the register class required for a secondary register when
9901 copying between one of the registers in RCLASS and value X, which
9902 has mode MODE. X is the source of the move if IN_P, otherwise it
9903 is the destination. Return NO_REGS if no secondary register is
9907 mips_secondary_reload_class (enum reg_class rclass,
9908 enum machine_mode mode, rtx x, bool in_p)
9912 /* If X is a constant that cannot be loaded into $25, it must be loaded
9913 into some other GPR. No other register class allows a direct move. */
9914 if (mips_dangerous_for_la25_p (x))
9915 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
9917 regno = true_regnum (x);
9920 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9921 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
9927 /* Copying from accumulator registers to anywhere other than a general
9928 register requires a temporary general register. */
9929 if (reg_class_subset_p (rclass, ACC_REGS))
9930 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9931 if (ACC_REG_P (regno))
9932 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9934 /* We can only copy a value to a condition code register from a
9935 floating-point register, and even then we require a scratch
9936 floating-point register. We can only copy a value out of a
9937 condition-code register into a general register. */
9938 if (reg_class_subset_p (rclass, ST_REGS))
9942 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9944 if (ST_REG_P (regno))
9948 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9951 if (reg_class_subset_p (rclass, FP_REGS))
9954 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
9955 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9956 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9959 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
9960 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9963 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
9964 /* We can force the constant to memory and use lwc1
9965 and ldc1. As above, we will use pairs of lwc1s if
9966 ldc1 is not supported. */
9969 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
9970 /* In this case we can use mov.fmt. */
9973 /* Otherwise, we need to reload through an integer register. */
9976 if (FP_REG_P (regno))
9977 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9982 /* Implement TARGET_MODE_REP_EXTENDED. */
9985 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
9987 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
9988 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
9994 /* Implement TARGET_VALID_POINTER_MODE. */
9997 mips_valid_pointer_mode (enum machine_mode mode)
9999 return mode == SImode || (TARGET_64BIT && mode == DImode);
10002 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10005 mips_vector_mode_supported_p (enum machine_mode mode)
10010 return TARGET_PAIRED_SINGLE_FLOAT;
10025 return TARGET_LOONGSON_VECTORS;
10032 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
10035 mips_scalar_mode_supported_p (enum machine_mode mode)
10037 if (ALL_FIXED_POINT_MODE_P (mode)
10038 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
10041 return default_scalar_mode_supported_p (mode);
10044 /* Implement TARGET_INIT_LIBFUNCS. */
10046 #include "config/gofast.h"
10049 mips_init_libfuncs (void)
10051 if (TARGET_FIX_VR4120)
10053 /* Register the special divsi3 and modsi3 functions needed to work
10054 around VR4120 division errata. */
10055 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10056 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
10059 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
10061 /* Register the MIPS16 -mhard-float stubs. */
10062 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
10063 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
10064 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
10065 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
10067 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
10068 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
10069 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
10070 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
10071 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
10072 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
10073 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
10075 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
10076 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
10077 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
10079 if (TARGET_DOUBLE_FLOAT)
10081 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
10082 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
10083 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
10084 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
10086 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
10087 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
10088 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
10089 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
10090 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
10091 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
10092 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
10094 set_conv_libfunc (sext_optab, DFmode, SFmode,
10095 "__mips16_extendsfdf2");
10096 set_conv_libfunc (trunc_optab, SFmode, DFmode,
10097 "__mips16_truncdfsf2");
10098 set_conv_libfunc (sfix_optab, SImode, DFmode,
10099 "__mips16_fix_truncdfsi");
10100 set_conv_libfunc (sfloat_optab, DFmode, SImode,
10101 "__mips16_floatsidf");
10102 set_conv_libfunc (ufloat_optab, DFmode, SImode,
10103 "__mips16_floatunsidf");
10107 /* Register the gofast functions if selected using --enable-gofast. */
10108 gofast_maybe_init_libfuncs ();
10110 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
10111 on an external non-MIPS16 routine to implement __sync_synchronize. */
10113 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
10116 /* Return the length of INSN. LENGTH is the initial length computed by
10117 attributes in the machine-description file. */
10120 mips_adjust_insn_length (rtx insn, int length)
10122 /* A unconditional jump has an unfilled delay slot if it is not part
10123 of a sequence. A conditional jump normally has a delay slot, but
10124 does not on MIPS16. */
10125 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
10128 /* See how many nops might be needed to avoid hardware hazards. */
10129 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
10130 switch (get_attr_hazard (insn))
10144 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
10145 the .md file length attributes are 4-based for both modes.
10146 Adjust the MIPS16 ones here. */
10153 /* Return an asm sequence to start a noat block and load the address
10154 of a label into $1. */
10157 mips_output_load_label (void)
10159 if (TARGET_EXPLICIT_RELOCS)
10163 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10166 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10169 if (ISA_HAS_LOAD_DELAY)
10170 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10171 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10175 if (Pmode == DImode)
10176 return "%[dla\t%@,%0";
10178 return "%[la\t%@,%0";
10182 /* Return the assembly code for INSN, which has the operands given by
10183 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10184 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10185 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10186 version of BRANCH_IF_TRUE. */
10189 mips_output_conditional_branch (rtx insn, rtx *operands,
10190 const char *branch_if_true,
10191 const char *branch_if_false)
10193 unsigned int length;
10194 rtx taken, not_taken;
10196 gcc_assert (LABEL_P (operands[1]));
10198 length = get_attr_length (insn);
10201 /* Just a simple conditional branch. */
10202 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10203 return branch_if_true;
10206 /* Generate a reversed branch around a direct jump. This fallback does
10207 not use branch-likely instructions. */
10208 mips_branch_likely = false;
10209 not_taken = gen_label_rtx ();
10210 taken = operands[1];
10212 /* Generate the reversed branch to NOT_TAKEN. */
10213 operands[1] = not_taken;
10214 output_asm_insn (branch_if_false, operands);
10216 /* If INSN has a delay slot, we must provide delay slots for both the
10217 branch to NOT_TAKEN and the conditional jump. We must also ensure
10218 that INSN's delay slot is executed in the appropriate cases. */
10219 if (final_sequence)
10221 /* This first delay slot will always be executed, so use INSN's
10222 delay slot if is not annulled. */
10223 if (!INSN_ANNULLED_BRANCH_P (insn))
10225 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10226 asm_out_file, optimize, 1, NULL);
10227 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10230 output_asm_insn ("nop", 0);
10231 fprintf (asm_out_file, "\n");
10234 /* Output the unconditional branch to TAKEN. */
10236 output_asm_insn ("j\t%0%/", &taken);
10239 output_asm_insn (mips_output_load_label (), &taken);
10240 output_asm_insn ("jr\t%@%]%/", 0);
10243 /* Now deal with its delay slot; see above. */
10244 if (final_sequence)
10246 /* This delay slot will only be executed if the branch is taken.
10247 Use INSN's delay slot if is annulled. */
10248 if (INSN_ANNULLED_BRANCH_P (insn))
10250 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10251 asm_out_file, optimize, 1, NULL);
10252 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10255 output_asm_insn ("nop", 0);
10256 fprintf (asm_out_file, "\n");
10259 /* Output NOT_TAKEN. */
10260 targetm.asm_out.internal_label (asm_out_file, "L",
10261 CODE_LABEL_NUMBER (not_taken));
10265 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10266 if some ordering condition is true. The condition is given by
10267 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10268 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10269 its second is always zero. */
10272 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10274 const char *branch[2];
10276 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10277 Make BRANCH[0] branch on the inverse condition. */
10278 switch (GET_CODE (operands[0]))
10280 /* These cases are equivalent to comparisons against zero. */
10282 inverted_p = !inverted_p;
10283 /* Fall through. */
10285 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10286 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10289 /* These cases are always true or always false. */
10291 inverted_p = !inverted_p;
10292 /* Fall through. */
10294 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10295 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10299 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10300 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10303 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10306 /* Return the assembly code for __sync_*() loop LOOP. The loop should support
10307 both normal and likely branches, using %? and %~ where appropriate. */
10310 mips_output_sync_loop (const char *loop)
10312 /* Use branch-likely instructions to work around the LL/SC R10000 errata. */
10313 mips_branch_likely = TARGET_FIX_R10000;
10317 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
10318 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
10320 When working around R4000 and R4400 errata, we need to make sure that
10321 the division is not immediately followed by a shift[1][2]. We also
10322 need to stop the division from being put into a branch delay slot[3].
10323 The easiest way to avoid both problems is to add a nop after the
10324 division. When a divide-by-zero check is needed, this nop can be
10325 used to fill the branch delay slot.
10327 [1] If a double-word or a variable shift executes immediately
10328 after starting an integer division, the shift may give an
10329 incorrect result. See quotations of errata #16 and #28 from
10330 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10331 in mips.md for details.
10333 [2] A similar bug to [1] exists for all revisions of the
10334 R4000 and the R4400 when run in an MC configuration.
10335 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10337 "19. In this following sequence:
10339 ddiv (or ddivu or div or divu)
10340 dsll32 (or dsrl32, dsra32)
10342 if an MPT stall occurs, while the divide is slipping the cpu
10343 pipeline, then the following double shift would end up with an
10346 Workaround: The compiler needs to avoid generating any
10347 sequence with divide followed by extended double shift."
10349 This erratum is also present in "MIPS R4400MC Errata, Processor
10350 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10351 & 3.0" as errata #10 and #4, respectively.
10353 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10354 (also valid for MIPS R4000MC processors):
10356 "52. R4000SC: This bug does not apply for the R4000PC.
10358 There are two flavors of this bug:
10360 1) If the instruction just after divide takes an RF exception
10361 (tlb-refill, tlb-invalid) and gets an instruction cache
10362 miss (both primary and secondary) and the line which is
10363 currently in secondary cache at this index had the first
10364 data word, where the bits 5..2 are set, then R4000 would
10365 get a wrong result for the div.
10370 ------------------- # end-of page. -tlb-refill
10375 ------------------- # end-of page. -tlb-invalid
10378 2) If the divide is in the taken branch delay slot, where the
10379 target takes RF exception and gets an I-cache miss for the
10380 exception vector or where I-cache miss occurs for the
10381 target address, under the above mentioned scenarios, the
10382 div would get wrong results.
10385 j r2 # to next page mapped or unmapped
10386 div r8,r9 # this bug would be there as long
10387 # as there is an ICache miss and
10388 nop # the "data pattern" is present
10391 beq r0, r0, NextPage # to Next page
10395 This bug is present for div, divu, ddiv, and ddivu
10398 Workaround: For item 1), OS could make sure that the next page
10399 after the divide instruction is also mapped. For item 2), the
10400 compiler could make sure that the divide instruction is not in
10401 the branch delay slot."
10403 These processors have PRId values of 0x00004220 and 0x00004300 for
10404 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10407 mips_output_division (const char *division, rtx *operands)
10412 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
10414 output_asm_insn (s, operands);
10417 if (TARGET_CHECK_ZERO_DIV)
10421 output_asm_insn (s, operands);
10422 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
10424 else if (GENERATE_DIVIDE_TRAPS)
10426 output_asm_insn (s, operands);
10427 s = "teq\t%2,%.,7";
10431 output_asm_insn ("%(bne\t%2,%.,1f", operands);
10432 output_asm_insn (s, operands);
10433 s = "break\t7%)\n1:";
10439 /* Return true if IN_INSN is a multiply-add or multiply-subtract
10440 instruction and if OUT_INSN assigns to the accumulator operand. */
10443 mips_linked_madd_p (rtx out_insn, rtx in_insn)
10447 x = single_set (in_insn);
10453 if (GET_CODE (x) == PLUS
10454 && GET_CODE (XEXP (x, 0)) == MULT
10455 && reg_set_p (XEXP (x, 1), out_insn))
10458 if (GET_CODE (x) == MINUS
10459 && GET_CODE (XEXP (x, 1)) == MULT
10460 && reg_set_p (XEXP (x, 0), out_insn))
10466 /* True if the dependency between OUT_INSN and IN_INSN is on the store
10467 data rather than the address. We need this because the cprestore
10468 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
10469 which causes the default routine to abort. We just return false
10473 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10475 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10478 return !store_data_bypass_p (out_insn, in_insn);
10482 /* Variables and flags used in scheduler hooks when tuning for
10486 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
10489 /* If true, then next ALU1/2 instruction will go to ALU1. */
10492 /* If true, then next FALU1/2 unstruction will go to FALU1. */
10495 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
10496 int alu1_core_unit_code;
10497 int alu2_core_unit_code;
10498 int falu1_core_unit_code;
10499 int falu2_core_unit_code;
10501 /* True if current cycle has a multi instruction.
10502 This flag is used in mips_ls2_dfa_post_advance_cycle. */
10503 bool cycle_has_multi_p;
10505 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
10506 These are used in mips_ls2_dfa_post_advance_cycle to initialize
10508 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
10509 instruction to go ALU1. */
10510 rtx alu1_turn_enabled_insn;
10511 rtx alu2_turn_enabled_insn;
10512 rtx falu1_turn_enabled_insn;
10513 rtx falu2_turn_enabled_insn;
10516 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10517 dependencies have no cost, except on the 20Kc where output-dependence
10518 is treated like input-dependence. */
10521 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10522 rtx dep ATTRIBUTE_UNUSED, int cost)
10524 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
10527 if (REG_NOTE_KIND (link) != 0)
10532 /* Return the number of instructions that can be issued per cycle. */
10535 mips_issue_rate (void)
10539 case PROCESSOR_74KC:
10540 case PROCESSOR_74KF2_1:
10541 case PROCESSOR_74KF1_1:
10542 case PROCESSOR_74KF3_2:
10543 /* The 74k is not strictly quad-issue cpu, but can be seen as one
10544 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
10545 but in reality only a maximum of 3 insns can be issued as
10546 floating-point loads and stores also require a slot in the
10548 case PROCESSOR_R10000:
10549 /* All R10K Processors are quad-issue (being the first MIPS
10550 processors to support this feature). */
10553 case PROCESSOR_20KC:
10554 case PROCESSOR_R4130:
10555 case PROCESSOR_R5400:
10556 case PROCESSOR_R5500:
10557 case PROCESSOR_R7000:
10558 case PROCESSOR_R9000:
10559 case PROCESSOR_OCTEON:
10562 case PROCESSOR_SB1:
10563 case PROCESSOR_SB1A:
10564 /* This is actually 4, but we get better performance if we claim 3.
10565 This is partly because of unwanted speculative code motion with the
10566 larger number, and partly because in most common cases we can't
10567 reach the theoretical max of 4. */
10570 case PROCESSOR_LOONGSON_2E:
10571 case PROCESSOR_LOONGSON_2F:
10579 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
10582 mips_ls2_init_dfa_post_cycle_insn (void)
10585 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
10586 mips_ls2.alu1_turn_enabled_insn = get_insns ();
10590 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
10591 mips_ls2.alu2_turn_enabled_insn = get_insns ();
10595 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
10596 mips_ls2.falu1_turn_enabled_insn = get_insns ();
10600 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
10601 mips_ls2.falu2_turn_enabled_insn = get_insns ();
10604 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
10605 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
10606 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
10607 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
10610 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
10611 Init data used in mips_dfa_post_advance_cycle. */
10614 mips_init_dfa_post_cycle_insn (void)
10616 if (TUNE_LOONGSON_2EF)
10617 mips_ls2_init_dfa_post_cycle_insn ();
10620 /* Initialize STATE when scheduling for Loongson 2E/2F.
10621 Support round-robin dispatch scheme by enabling only one of
10622 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
10626 mips_ls2_dfa_post_advance_cycle (state_t state)
10628 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
10630 /* Though there are no non-pipelined ALU1 insns,
10631 we can get an instruction of type 'multi' before reload. */
10632 gcc_assert (mips_ls2.cycle_has_multi_p);
10633 mips_ls2.alu1_turn_p = false;
10636 mips_ls2.cycle_has_multi_p = false;
10638 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
10639 /* We have a non-pipelined alu instruction in the core,
10640 adjust round-robin counter. */
10641 mips_ls2.alu1_turn_p = true;
10643 if (mips_ls2.alu1_turn_p)
10645 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
10646 gcc_unreachable ();
10650 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
10651 gcc_unreachable ();
10654 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
10656 /* There are no non-pipelined FALU1 insns. */
10657 gcc_unreachable ();
10658 mips_ls2.falu1_turn_p = false;
10661 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
10662 /* We have a non-pipelined falu instruction in the core,
10663 adjust round-robin counter. */
10664 mips_ls2.falu1_turn_p = true;
10666 if (mips_ls2.falu1_turn_p)
10668 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
10669 gcc_unreachable ();
10673 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
10674 gcc_unreachable ();
10678 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
10679 This hook is being called at the start of each cycle. */
10682 mips_dfa_post_advance_cycle (void)
10684 if (TUNE_LOONGSON_2EF)
10685 mips_ls2_dfa_post_advance_cycle (curr_state);
10688 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
10689 be as wide as the scheduling freedom in the DFA. */
10692 mips_multipass_dfa_lookahead (void)
10694 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10698 if (TUNE_LOONGSON_2EF)
10707 /* Remove the instruction at index LOWER from ready queue READY and
10708 reinsert it in front of the instruction at index HIGHER. LOWER must
10712 mips_promote_ready (rtx *ready, int lower, int higher)
10717 new_head = ready[lower];
10718 for (i = lower; i < higher; i++)
10719 ready[i] = ready[i + 1];
10720 ready[i] = new_head;
10723 /* If the priority of the instruction at POS2 in the ready queue READY
10724 is within LIMIT units of that of the instruction at POS1, swap the
10725 instructions if POS2 is not already less than POS1. */
10728 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
10731 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
10735 temp = ready[pos1];
10736 ready[pos1] = ready[pos2];
10737 ready[pos2] = temp;
10741 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
10742 that may clobber hi or lo. */
10743 static rtx mips_macc_chains_last_hilo;
10745 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10746 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10749 mips_macc_chains_record (rtx insn)
10751 if (get_attr_may_clobber_hilo (insn))
10752 mips_macc_chains_last_hilo = insn;
10755 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10756 has NREADY elements, looking for a multiply-add or multiply-subtract
10757 instruction that is cumulative with mips_macc_chains_last_hilo.
10758 If there is one, promote it ahead of anything else that might
10759 clobber hi or lo. */
10762 mips_macc_chains_reorder (rtx *ready, int nready)
10766 if (mips_macc_chains_last_hilo != 0)
10767 for (i = nready - 1; i >= 0; i--)
10768 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10770 for (j = nready - 1; j > i; j--)
10771 if (recog_memoized (ready[j]) >= 0
10772 && get_attr_may_clobber_hilo (ready[j]))
10774 mips_promote_ready (ready, i, j);
10781 /* The last instruction to be scheduled. */
10782 static rtx vr4130_last_insn;
10784 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10785 points to an rtx that is initially an instruction. Nullify the rtx
10786 if the instruction uses the value of register X. */
10789 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
10794 insn_ptr = (rtx *) data;
10797 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10801 /* Return true if there is true register dependence between vr4130_last_insn
10805 vr4130_true_reg_dependence_p (rtx insn)
10807 note_stores (PATTERN (vr4130_last_insn),
10808 vr4130_true_reg_dependence_p_1, &insn);
10812 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10813 the ready queue and that INSN2 is the instruction after it, return
10814 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10815 in which INSN1 and INSN2 can probably issue in parallel, but for
10816 which (INSN2, INSN1) should be less sensitive to instruction
10817 alignment than (INSN1, INSN2). See 4130.md for more details. */
10820 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10822 sd_iterator_def sd_it;
10825 /* Check for the following case:
10827 1) there is some other instruction X with an anti dependence on INSN1;
10828 2) X has a higher priority than INSN2; and
10829 3) X is an arithmetic instruction (and thus has no unit restrictions).
10831 If INSN1 is the last instruction blocking X, it would better to
10832 choose (INSN1, X) over (INSN2, INSN1). */
10833 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
10834 if (DEP_TYPE (dep) == REG_DEP_ANTI
10835 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
10836 && recog_memoized (DEP_CON (dep)) >= 0
10837 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
10840 if (vr4130_last_insn != 0
10841 && recog_memoized (insn1) >= 0
10842 && recog_memoized (insn2) >= 0)
10844 /* See whether INSN1 and INSN2 use different execution units,
10845 or if they are both ALU-type instructions. If so, they can
10846 probably execute in parallel. */
10847 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10848 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10849 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10851 /* If only one of the instructions has a dependence on
10852 vr4130_last_insn, prefer to schedule the other one first. */
10853 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
10854 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
10855 if (dep1_p != dep2_p)
10858 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10859 is not an ALU-type instruction and if INSN1 uses the same
10860 execution unit. (Note that if this condition holds, we already
10861 know that INSN2 uses a different execution unit.) */
10862 if (class1 != VR4130_CLASS_ALU
10863 && recog_memoized (vr4130_last_insn) >= 0
10864 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10871 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10872 queue with at least two instructions. Swap the first two if
10873 vr4130_swap_insns_p says that it could be worthwhile. */
10876 vr4130_reorder (rtx *ready, int nready)
10878 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10879 mips_promote_ready (ready, nready - 2, nready - 1);
10882 /* Record whether last 74k AGEN instruction was a load or store. */
10883 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
10885 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
10886 resets to TYPE_UNKNOWN state. */
10889 mips_74k_agen_init (rtx insn)
10891 if (!insn || !NONJUMP_INSN_P (insn))
10892 mips_last_74k_agen_insn = TYPE_UNKNOWN;
10895 enum attr_type type = get_attr_type (insn);
10896 if (type == TYPE_LOAD || type == TYPE_STORE)
10897 mips_last_74k_agen_insn = type;
10901 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
10902 loads to be grouped together, and multiple stores to be grouped
10903 together. Swap things around in the ready queue to make this happen. */
10906 mips_74k_agen_reorder (rtx *ready, int nready)
10909 int store_pos, load_pos;
10914 for (i = nready - 1; i >= 0; i--)
10916 rtx insn = ready[i];
10917 if (USEFUL_INSN_P (insn))
10918 switch (get_attr_type (insn))
10921 if (store_pos == -1)
10926 if (load_pos == -1)
10935 if (load_pos == -1 || store_pos == -1)
10938 switch (mips_last_74k_agen_insn)
10941 /* Prefer to schedule loads since they have a higher latency. */
10943 /* Swap loads to the front of the queue. */
10944 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
10947 /* Swap stores to the front of the queue. */
10948 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
10955 /* Implement TARGET_SCHED_INIT. */
10958 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10959 int max_ready ATTRIBUTE_UNUSED)
10961 mips_macc_chains_last_hilo = 0;
10962 vr4130_last_insn = 0;
10963 mips_74k_agen_init (NULL_RTX);
10965 /* When scheduling for Loongson2, branch instructions go to ALU1,
10966 therefore basic block is most likely to start with round-robin counter
10967 pointed to ALU2. */
10968 mips_ls2.alu1_turn_p = false;
10969 mips_ls2.falu1_turn_p = true;
10972 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
10975 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10976 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
10978 if (!reload_completed
10979 && TUNE_MACC_CHAINS
10981 mips_macc_chains_reorder (ready, *nreadyp);
10983 if (reload_completed
10985 && !TARGET_VR4130_ALIGN
10987 vr4130_reorder (ready, *nreadyp);
10990 mips_74k_agen_reorder (ready, *nreadyp);
10992 return mips_issue_rate ();
10995 /* Update round-robin counters for ALU1/2 and FALU1/2. */
10998 mips_ls2_variable_issue (rtx insn)
11000 if (mips_ls2.alu1_turn_p)
11002 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
11003 mips_ls2.alu1_turn_p = false;
11007 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
11008 mips_ls2.alu1_turn_p = true;
11011 if (mips_ls2.falu1_turn_p)
11013 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
11014 mips_ls2.falu1_turn_p = false;
11018 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
11019 mips_ls2.falu1_turn_p = true;
11022 if (recog_memoized (insn) >= 0)
11023 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
11026 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
11029 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11030 rtx insn, int more)
11032 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
11033 if (USEFUL_INSN_P (insn))
11036 if (!reload_completed && TUNE_MACC_CHAINS)
11037 mips_macc_chains_record (insn);
11038 vr4130_last_insn = insn;
11040 mips_74k_agen_init (insn);
11041 else if (TUNE_LOONGSON_2EF)
11042 mips_ls2_variable_issue (insn);
11045 /* Instructions of type 'multi' should all be split before
11046 the second scheduling pass. */
11047 gcc_assert (!reload_completed
11048 || recog_memoized (insn) < 0
11049 || get_attr_type (insn) != TYPE_MULTI);
11054 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
11055 return the first operand of the associated PREF or PREFX insn. */
11058 mips_prefetch_cookie (rtx write, rtx locality)
11060 /* store_streamed / load_streamed. */
11061 if (INTVAL (locality) <= 0)
11062 return GEN_INT (INTVAL (write) + 4);
11064 /* store / load. */
11065 if (INTVAL (locality) <= 2)
11068 /* store_retained / load_retained. */
11069 return GEN_INT (INTVAL (write) + 6);
11072 /* Flags that indicate when a built-in function is available.
11074 BUILTIN_AVAIL_NON_MIPS16
11075 The function is available on the current target, but only
11076 in non-MIPS16 mode. */
11077 #define BUILTIN_AVAIL_NON_MIPS16 1
11079 /* Declare an availability predicate for built-in functions that
11080 require non-MIPS16 mode and also require COND to be true.
11081 NAME is the main part of the predicate's name. */
11082 #define AVAIL_NON_MIPS16(NAME, COND) \
11083 static unsigned int \
11084 mips_builtin_avail_##NAME (void) \
11086 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
11089 /* This structure describes a single built-in function. */
11090 struct mips_builtin_description {
11091 /* The code of the main .md file instruction. See mips_builtin_type
11092 for more information. */
11093 enum insn_code icode;
11095 /* The floating-point comparison code to use with ICODE, if any. */
11096 enum mips_fp_condition cond;
11098 /* The name of the built-in function. */
11101 /* Specifies how the function should be expanded. */
11102 enum mips_builtin_type builtin_type;
11104 /* The function's prototype. */
11105 enum mips_function_type function_type;
11107 /* Whether the function is available. */
11108 unsigned int (*avail) (void);
11111 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
11112 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
11113 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
11114 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
11115 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
11116 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
11117 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
11118 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
11119 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
11121 /* Construct a mips_builtin_description from the given arguments.
11123 INSN is the name of the associated instruction pattern, without the
11124 leading CODE_FOR_mips_.
11126 CODE is the floating-point condition code associated with the
11127 function. It can be 'f' if the field is not applicable.
11129 NAME is the name of the function itself, without the leading
11132 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
11134 AVAIL is the name of the availability predicate, without the leading
11135 mips_builtin_avail_. */
11136 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
11137 FUNCTION_TYPE, AVAIL) \
11138 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
11139 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
11140 mips_builtin_avail_ ## AVAIL }
11142 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
11143 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
11144 are as for MIPS_BUILTIN. */
11145 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11146 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
11148 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
11149 are subject to mips_builtin_avail_<AVAIL>. */
11150 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
11151 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
11152 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
11153 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
11154 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
11156 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
11157 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
11158 while the any and all forms are subject to mips_builtin_avail_mips3d. */
11159 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
11160 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
11161 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
11163 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
11164 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
11166 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
11167 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
11169 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
11170 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
11173 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
11174 are subject to mips_builtin_avail_mips3d. */
11175 #define CMP_4S_BUILTINS(INSN, COND) \
11176 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
11177 MIPS_BUILTIN_CMP_ANY, \
11178 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
11179 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
11180 MIPS_BUILTIN_CMP_ALL, \
11181 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
11183 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11184 instruction requires mips_builtin_avail_<AVAIL>. */
11185 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
11186 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
11187 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11189 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
11190 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11193 /* Define all the built-in functions related to C.cond.fmt condition COND. */
11194 #define CMP_BUILTINS(COND) \
11195 MOVTF_BUILTINS (c, COND, paired_single), \
11196 MOVTF_BUILTINS (cabs, COND, mips3d), \
11197 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
11198 CMP_PS_BUILTINS (c, COND, paired_single), \
11199 CMP_PS_BUILTINS (cabs, COND, mips3d), \
11200 CMP_4S_BUILTINS (c, COND), \
11201 CMP_4S_BUILTINS (cabs, COND)
11203 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
11204 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
11205 and AVAIL are as for MIPS_BUILTIN. */
11206 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11207 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
11208 FUNCTION_TYPE, AVAIL)
11210 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11211 branch instruction. AVAIL is as for MIPS_BUILTIN. */
11212 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
11213 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
11214 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
11216 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
11217 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11218 builtin_description field. */
11219 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
11220 { CODE_FOR_loongson_ ## INSN, 0, "__builtin_loongson_" #FN_NAME, \
11221 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_loongson }
11223 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
11224 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11225 builtin_description field. */
11226 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
11227 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
11229 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
11230 We use functions of this form when the same insn can be usefully applied
11231 to more than one datatype. */
11232 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
11233 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
11235 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11236 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11237 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11238 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11239 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11240 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11242 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
11243 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
11244 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
11245 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
11246 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
11247 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
11248 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
11249 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
11250 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
11251 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
11252 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
11253 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
11254 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
11255 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
11256 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
11257 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
11258 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
11259 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
11260 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
11261 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
11262 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
11263 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
11264 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
11265 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
11266 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
11267 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
11268 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
11269 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
11270 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
11272 static const struct mips_builtin_description mips_builtins[] = {
11273 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11274 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11275 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11276 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11277 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
11278 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
11279 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
11280 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
11282 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
11283 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11284 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11285 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11286 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
11288 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
11289 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
11290 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11291 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
11292 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
11293 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11295 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
11296 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
11297 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11298 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
11299 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
11300 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11302 MIPS_FP_CONDITIONS (CMP_BUILTINS),
11304 /* Built-in functions for the SB-1 processor. */
11305 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
11307 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
11308 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11309 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11310 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11311 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11312 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11313 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11314 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11315 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11316 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11317 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11318 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
11319 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
11320 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
11321 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
11322 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
11323 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
11324 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
11325 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
11326 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
11327 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
11328 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
11329 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
11330 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
11331 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
11332 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
11333 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
11334 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
11335 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
11336 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
11337 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
11338 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
11339 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11340 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11341 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11342 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
11343 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11344 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11345 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
11346 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
11347 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
11348 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11349 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
11350 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
11351 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
11352 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
11353 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
11354 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
11355 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11356 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11357 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11358 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11359 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11360 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11361 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11362 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11363 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11364 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11365 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11366 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11367 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
11368 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
11369 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
11370 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
11371 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
11372 BPOSGE_BUILTIN (32, dsp),
11374 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
11375 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
11376 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11377 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11378 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11379 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11380 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11381 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11382 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11383 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11384 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11385 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11386 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11387 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11388 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11389 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11390 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
11391 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
11392 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
11393 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11394 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
11395 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
11396 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
11397 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11398 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11399 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11400 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11401 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11402 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11403 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11404 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11405 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11406 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11407 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11408 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11410 /* Built-in functions for the DSP ASE (32-bit only). */
11411 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11412 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11413 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11414 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11415 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11416 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11417 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11418 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
11419 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
11420 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11421 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11422 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11423 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11424 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11425 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11426 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11427 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
11428 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
11429 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
11430 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
11431 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
11433 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
11434 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11435 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11436 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
11437 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
11438 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
11439 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
11440 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11441 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
11442 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
11443 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11444 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11445 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11446 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11447 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11448 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11450 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
11451 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
11452 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
11453 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
11454 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11455 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11456 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11457 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11458 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11459 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11460 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
11461 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
11462 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11463 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11464 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11465 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11466 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
11467 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11468 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11469 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11470 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
11471 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
11472 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11473 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11474 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11475 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11476 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11477 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11478 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11479 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11480 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11481 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11482 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11483 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11484 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11485 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11486 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11487 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11488 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
11489 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
11490 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11491 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11492 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11493 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11494 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11495 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11496 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11497 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11498 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
11499 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11500 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11501 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11502 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11503 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
11504 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
11505 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11506 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11507 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11508 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
11509 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11510 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
11511 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
11512 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
11513 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
11514 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11515 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11516 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11517 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11518 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11519 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11520 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11521 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11522 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11523 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11524 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11525 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11526 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11527 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11528 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11529 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11530 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11531 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11532 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
11533 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
11534 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11535 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11536 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11537 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11538 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11539 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11540 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11541 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11542 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11543 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11544 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11545 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11546 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11547 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11548 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11549 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11551 /* Sundry other built-in functions. */
11552 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
11555 /* MODE is a vector mode whose elements have type TYPE. Return the type
11556 of the vector itself. */
11559 mips_builtin_vector_type (tree type, enum machine_mode mode)
11561 static tree types[2 * (int) MAX_MACHINE_MODE];
11564 mode_index = (int) mode;
11566 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
11567 mode_index += MAX_MACHINE_MODE;
11569 if (types[mode_index] == NULL_TREE)
11570 types[mode_index] = build_vector_type_for_mode (type, mode);
11571 return types[mode_index];
11574 /* Return a type for 'const volatile void *'. */
11577 mips_build_cvpointer_type (void)
11581 if (cache == NULL_TREE)
11582 cache = build_pointer_type (build_qualified_type
11584 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
11588 /* Source-level argument types. */
11589 #define MIPS_ATYPE_VOID void_type_node
11590 #define MIPS_ATYPE_INT integer_type_node
11591 #define MIPS_ATYPE_POINTER ptr_type_node
11592 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
11594 /* Standard mode-based argument types. */
11595 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
11596 #define MIPS_ATYPE_SI intSI_type_node
11597 #define MIPS_ATYPE_USI unsigned_intSI_type_node
11598 #define MIPS_ATYPE_DI intDI_type_node
11599 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
11600 #define MIPS_ATYPE_SF float_type_node
11601 #define MIPS_ATYPE_DF double_type_node
11603 /* Vector argument types. */
11604 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
11605 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
11606 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
11607 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
11608 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
11609 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
11610 #define MIPS_ATYPE_UV2SI \
11611 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
11612 #define MIPS_ATYPE_UV4HI \
11613 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
11614 #define MIPS_ATYPE_UV8QI \
11615 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
11617 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
11618 their associated MIPS_ATYPEs. */
11619 #define MIPS_FTYPE_ATYPES1(A, B) \
11620 MIPS_ATYPE_##A, MIPS_ATYPE_##B
11622 #define MIPS_FTYPE_ATYPES2(A, B, C) \
11623 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
11625 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
11626 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
11628 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
11629 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
11632 /* Return the function type associated with function prototype TYPE. */
11635 mips_build_function_type (enum mips_function_type type)
11637 static tree types[(int) MIPS_MAX_FTYPE_MAX];
11639 if (types[(int) type] == NULL_TREE)
11642 #define DEF_MIPS_FTYPE(NUM, ARGS) \
11643 case MIPS_FTYPE_NAME##NUM ARGS: \
11644 types[(int) type] \
11645 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
11648 #include "config/mips/mips-ftypes.def"
11649 #undef DEF_MIPS_FTYPE
11651 gcc_unreachable ();
11654 return types[(int) type];
11657 /* Implement TARGET_INIT_BUILTINS. */
11660 mips_init_builtins (void)
11662 const struct mips_builtin_description *d;
11665 /* Iterate through all of the bdesc arrays, initializing all of the
11666 builtin functions. */
11667 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
11669 d = &mips_builtins[i];
11671 add_builtin_function (d->name,
11672 mips_build_function_type (d->function_type),
11673 i, BUILT_IN_MD, NULL, NULL);
11677 /* Take argument ARGNO from EXP's argument list and convert it into a
11678 form suitable for input operand OPNO of instruction ICODE. Return the
11682 mips_prepare_builtin_arg (enum insn_code icode,
11683 unsigned int opno, tree exp, unsigned int argno)
11687 enum machine_mode mode;
11689 arg = CALL_EXPR_ARG (exp, argno);
11690 value = expand_normal (arg);
11691 mode = insn_data[icode].operand[opno].mode;
11692 if (!insn_data[icode].operand[opno].predicate (value, mode))
11694 /* We need to get the mode from ARG for two reasons:
11696 - to cope with address operands, where MODE is the mode of the
11697 memory, rather than of VALUE itself.
11699 - to cope with special predicates like pmode_register_operand,
11700 where MODE is VOIDmode. */
11701 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
11703 /* Check the predicate again. */
11704 if (!insn_data[icode].operand[opno].predicate (value, mode))
11706 error ("invalid argument to built-in function");
11714 /* Return an rtx suitable for output operand OP of instruction ICODE.
11715 If TARGET is non-null, try to use it where possible. */
11718 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
11720 enum machine_mode mode;
11722 mode = insn_data[icode].operand[op].mode;
11723 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
11724 target = gen_reg_rtx (mode);
11729 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
11730 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
11731 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
11732 suggests a good place to put the result. */
11735 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
11738 rtx ops[MAX_RECOG_OPERANDS];
11741 /* Map any target to operand 0. */
11745 target = mips_prepare_builtin_target (icode, opno, target);
11746 ops[opno] = target;
11750 /* Map the arguments to the other operands. The n_operands value
11751 for an expander includes match_dups and match_scratches as well as
11752 match_operands, so n_operands is only an upper bound on the number
11753 of arguments to the expander function. */
11754 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
11755 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
11756 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
11761 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11765 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11769 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11773 gcc_unreachable ();
11778 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
11779 function; TYPE says which. EXP is the CALL_EXPR that calls the
11780 function, ICODE is the instruction that should be used to compare
11781 the first two arguments, and COND is the condition it should test.
11782 TARGET, if nonnull, suggests a good place to put the result. */
11785 mips_expand_builtin_movtf (enum mips_builtin_type type,
11786 enum insn_code icode, enum mips_fp_condition cond,
11787 rtx target, tree exp)
11789 rtx cmp_result, op0, op1;
11791 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11792 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11793 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11794 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11796 icode = CODE_FOR_mips_cond_move_tf_ps;
11797 target = mips_prepare_builtin_target (icode, 0, target);
11798 if (type == MIPS_BUILTIN_MOVT)
11800 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11801 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11805 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11806 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11808 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11812 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11813 into TARGET otherwise. Return TARGET. */
11816 mips_builtin_branch_and_move (rtx condition, rtx target,
11817 rtx value_if_true, rtx value_if_false)
11819 rtx true_label, done_label;
11821 true_label = gen_label_rtx ();
11822 done_label = gen_label_rtx ();
11824 /* First assume that CONDITION is false. */
11825 mips_emit_move (target, value_if_false);
11827 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11828 emit_jump_insn (gen_condjump (condition, true_label));
11829 emit_jump_insn (gen_jump (done_label));
11832 /* Fix TARGET if CONDITION is true. */
11833 emit_label (true_label);
11834 mips_emit_move (target, value_if_true);
11836 emit_label (done_label);
11840 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
11841 the CALL_EXPR that calls the function, ICODE is the code of the
11842 comparison instruction, and COND is the condition it should test.
11843 TARGET, if nonnull, suggests a good place to put the boolean result. */
11846 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11847 enum insn_code icode, enum mips_fp_condition cond,
11848 rtx target, tree exp)
11850 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
11853 if (target == 0 || GET_MODE (target) != SImode)
11854 target = gen_reg_rtx (SImode);
11856 /* The instruction should have a target operand, an operand for each
11857 argument, and an operand for COND. */
11858 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
11860 /* Prepare the operands to the comparison. */
11861 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11862 for (argno = 0; argno < call_expr_nargs (exp); argno++)
11863 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
11865 switch (insn_data[icode].n_operands)
11868 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
11873 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
11874 args[2], args[3], GEN_INT (cond)));
11878 gcc_unreachable ();
11881 /* If the comparison sets more than one register, we define the result
11882 to be 0 if all registers are false and -1 if all registers are true.
11883 The value of the complete result is indeterminate otherwise. */
11884 switch (builtin_type)
11886 case MIPS_BUILTIN_CMP_ALL:
11887 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11888 return mips_builtin_branch_and_move (condition, target,
11889 const0_rtx, const1_rtx);
11891 case MIPS_BUILTIN_CMP_UPPER:
11892 case MIPS_BUILTIN_CMP_LOWER:
11893 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11894 condition = gen_single_cc (cmp_result, offset);
11895 return mips_builtin_branch_and_move (condition, target,
11896 const1_rtx, const0_rtx);
11899 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11900 return mips_builtin_branch_and_move (condition, target,
11901 const1_rtx, const0_rtx);
11905 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
11906 if nonnull, suggests a good place to put the boolean result. */
11909 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11911 rtx condition, cmp_result;
11914 if (target == 0 || GET_MODE (target) != SImode)
11915 target = gen_reg_rtx (SImode);
11917 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11919 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11924 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11925 return mips_builtin_branch_and_move (condition, target,
11926 const1_rtx, const0_rtx);
11929 /* Implement TARGET_EXPAND_BUILTIN. */
11932 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11933 enum machine_mode mode, int ignore)
11936 unsigned int fcode, avail;
11937 const struct mips_builtin_description *d;
11939 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11940 fcode = DECL_FUNCTION_CODE (fndecl);
11941 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
11942 d = &mips_builtins[fcode];
11943 avail = d->avail ();
11944 gcc_assert (avail != 0);
11947 error ("built-in function %qs not supported for MIPS16",
11948 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
11949 return ignore ? const0_rtx : CONST0_RTX (mode);
11951 switch (d->builtin_type)
11953 case MIPS_BUILTIN_DIRECT:
11954 return mips_expand_builtin_direct (d->icode, target, exp, true);
11956 case MIPS_BUILTIN_DIRECT_NO_TARGET:
11957 return mips_expand_builtin_direct (d->icode, target, exp, false);
11959 case MIPS_BUILTIN_MOVT:
11960 case MIPS_BUILTIN_MOVF:
11961 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
11962 d->cond, target, exp);
11964 case MIPS_BUILTIN_CMP_ANY:
11965 case MIPS_BUILTIN_CMP_ALL:
11966 case MIPS_BUILTIN_CMP_UPPER:
11967 case MIPS_BUILTIN_CMP_LOWER:
11968 case MIPS_BUILTIN_CMP_SINGLE:
11969 return mips_expand_builtin_compare (d->builtin_type, d->icode,
11970 d->cond, target, exp);
11972 case MIPS_BUILTIN_BPOSGE32:
11973 return mips_expand_builtin_bposge (d->builtin_type, target);
11975 gcc_unreachable ();
11978 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
11979 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
11980 struct mips16_constant {
11981 struct mips16_constant *next;
11984 enum machine_mode mode;
11987 /* Information about an incomplete MIPS16 constant pool. FIRST is the
11988 first constant, HIGHEST_ADDRESS is the highest address that the first
11989 byte of the pool can have, and INSN_ADDRESS is the current instruction
11991 struct mips16_constant_pool {
11992 struct mips16_constant *first;
11993 int highest_address;
11997 /* Add constant VALUE to POOL and return its label. MODE is the
11998 value's mode (used for CONST_INTs, etc.). */
12001 mips16_add_constant (struct mips16_constant_pool *pool,
12002 rtx value, enum machine_mode mode)
12004 struct mips16_constant **p, *c;
12005 bool first_of_size_p;
12007 /* See whether the constant is already in the pool. If so, return the
12008 existing label, otherwise leave P pointing to the place where the
12009 constant should be added.
12011 Keep the pool sorted in increasing order of mode size so that we can
12012 reduce the number of alignments needed. */
12013 first_of_size_p = true;
12014 for (p = &pool->first; *p != 0; p = &(*p)->next)
12016 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
12017 return (*p)->label;
12018 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
12020 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
12021 first_of_size_p = false;
12024 /* In the worst case, the constant needed by the earliest instruction
12025 will end up at the end of the pool. The entire pool must then be
12026 accessible from that instruction.
12028 When adding the first constant, set the pool's highest address to
12029 the address of the first out-of-range byte. Adjust this address
12030 downwards each time a new constant is added. */
12031 if (pool->first == 0)
12032 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
12033 of the instruction with the lowest two bits clear. The base PC
12034 value for LDPC has the lowest three bits clear. Assume the worst
12035 case here; namely that the PC-relative instruction occupies the
12036 last 2 bytes in an aligned word. */
12037 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
12038 pool->highest_address -= GET_MODE_SIZE (mode);
12039 if (first_of_size_p)
12040 /* Take into account the worst possible padding due to alignment. */
12041 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
12043 /* Create a new entry. */
12044 c = XNEW (struct mips16_constant);
12047 c->label = gen_label_rtx ();
12054 /* Output constant VALUE after instruction INSN and return the last
12055 instruction emitted. MODE is the mode of the constant. */
12058 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
12060 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
12062 rtx size = GEN_INT (GET_MODE_SIZE (mode));
12063 return emit_insn_after (gen_consttable_int (value, size), insn);
12066 if (SCALAR_FLOAT_MODE_P (mode))
12067 return emit_insn_after (gen_consttable_float (value), insn);
12069 if (VECTOR_MODE_P (mode))
12073 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
12074 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
12075 CONST_VECTOR_ELT (value, i), insn);
12079 gcc_unreachable ();
12082 /* Dump out the constants in CONSTANTS after INSN. */
12085 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
12087 struct mips16_constant *c, *next;
12091 for (c = constants; c != NULL; c = next)
12093 /* If necessary, increase the alignment of PC. */
12094 if (align < GET_MODE_SIZE (c->mode))
12096 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
12097 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
12099 align = GET_MODE_SIZE (c->mode);
12101 insn = emit_label_after (c->label, insn);
12102 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
12108 emit_barrier_after (insn);
12111 /* Return the length of instruction INSN. */
12114 mips16_insn_length (rtx insn)
12118 rtx body = PATTERN (insn);
12119 if (GET_CODE (body) == ADDR_VEC)
12120 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
12121 if (GET_CODE (body) == ADDR_DIFF_VEC)
12122 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
12124 return get_attr_length (insn);
12127 /* If *X is a symbolic constant that refers to the constant pool, add
12128 the constant to POOL and rewrite *X to use the constant's label. */
12131 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
12133 rtx base, offset, label;
12135 split_const (*x, &base, &offset);
12136 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
12138 label = mips16_add_constant (pool, get_pool_constant (base),
12139 get_pool_mode (base));
12140 base = gen_rtx_LABEL_REF (Pmode, label);
12141 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
12145 /* This structure is used to communicate with mips16_rewrite_pool_refs.
12146 INSN is the instruction we're rewriting and POOL points to the current
12148 struct mips16_rewrite_pool_refs_info {
12150 struct mips16_constant_pool *pool;
12153 /* Rewrite *X so that constant pool references refer to the constant's
12154 label instead. DATA points to a mips16_rewrite_pool_refs_info
12158 mips16_rewrite_pool_refs (rtx *x, void *data)
12160 struct mips16_rewrite_pool_refs_info *info =
12161 (struct mips16_rewrite_pool_refs_info *) data;
12163 if (force_to_mem_operand (*x, Pmode))
12165 rtx mem = force_const_mem (GET_MODE (*x), *x);
12166 validate_change (info->insn, x, mem, false);
12171 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
12175 if (TARGET_MIPS16_TEXT_LOADS)
12176 mips16_rewrite_pool_constant (info->pool, x);
12178 return GET_CODE (*x) == CONST ? -1 : 0;
12181 /* Build MIPS16 constant pools. */
12184 mips16_lay_out_constants (void)
12186 struct mips16_constant_pool pool;
12187 struct mips16_rewrite_pool_refs_info info;
12190 if (!TARGET_MIPS16_PCREL_LOADS)
12193 split_all_insns_noflow ();
12195 memset (&pool, 0, sizeof (pool));
12196 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12198 /* Rewrite constant pool references in INSN. */
12203 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
12206 pool.insn_address += mips16_insn_length (insn);
12208 if (pool.first != NULL)
12210 /* If there are no natural barriers between the first user of
12211 the pool and the highest acceptable address, we'll need to
12212 create a new instruction to jump around the constant pool.
12213 In the worst case, this instruction will be 4 bytes long.
12215 If it's too late to do this transformation after INSN,
12216 do it immediately before INSN. */
12217 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
12221 label = gen_label_rtx ();
12223 jump = emit_jump_insn_before (gen_jump (label), insn);
12224 JUMP_LABEL (jump) = label;
12225 LABEL_NUSES (label) = 1;
12226 barrier = emit_barrier_after (jump);
12228 emit_label_after (label, barrier);
12229 pool.insn_address += 4;
12232 /* See whether the constant pool is now out of range of the first
12233 user. If so, output the constants after the previous barrier.
12234 Note that any instructions between BARRIER and INSN (inclusive)
12235 will use negative offsets to refer to the pool. */
12236 if (pool.insn_address > pool.highest_address)
12238 mips16_emit_constants (pool.first, barrier);
12242 else if (BARRIER_P (insn))
12246 mips16_emit_constants (pool.first, get_last_insn ());
12249 /* Return true if it is worth r10k_simplify_address's while replacing
12250 an address with X. We are looking for constants, and for addresses
12251 at a known offset from the incoming stack pointer. */
12254 r10k_simplified_address_p (rtx x)
12256 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
12258 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
12261 /* X is an expression that appears in INSN. Try to use the UD chains
12262 to simplify it, returning the simplified form on success and the
12263 original form otherwise. Replace the incoming value of $sp with
12264 virtual_incoming_args_rtx (which should never occur in X otherwise). */
12267 r10k_simplify_address (rtx x, rtx insn)
12269 rtx newx, op0, op1, set, def_insn, note;
12271 struct df_link *defs;
12276 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12277 if (op0 != XEXP (x, 0))
12278 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
12279 op0, GET_MODE (XEXP (x, 0)));
12281 else if (BINARY_P (x))
12283 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12284 op1 = r10k_simplify_address (XEXP (x, 1), insn);
12285 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
12286 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
12288 else if (GET_CODE (x) == LO_SUM)
12290 /* LO_SUMs can be offset from HIGHs, if we know they won't
12291 overflow. See mips_classify_address for the rationale behind
12293 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12294 if (GET_CODE (op0) == HIGH)
12295 newx = XEXP (x, 1);
12297 else if (REG_P (x))
12299 /* Uses are recorded by regno_reg_rtx, not X itself. */
12300 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
12302 defs = DF_REF_CHAIN (use);
12304 /* Require a single definition. */
12305 if (defs && defs->next == NULL)
12308 if (DF_REF_IS_ARTIFICIAL (def))
12310 /* Replace the incoming value of $sp with
12311 virtual_incoming_args_rtx. */
12312 if (x == stack_pointer_rtx
12313 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
12314 newx = virtual_incoming_args_rtx;
12316 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
12319 /* Make sure that DEF_INSN is a single set of REG. */
12320 def_insn = DF_REF_INSN (def);
12321 if (NONJUMP_INSN_P (def_insn))
12323 set = single_set (def_insn);
12324 if (set && rtx_equal_p (SET_DEST (set), x))
12326 /* Prefer to use notes, since the def-use chains
12327 are often shorter. */
12328 note = find_reg_equal_equiv_note (def_insn);
12330 newx = XEXP (note, 0);
12332 newx = SET_SRC (set);
12333 newx = r10k_simplify_address (newx, def_insn);
12339 if (newx && r10k_simplified_address_p (newx))
12344 /* Return true if ADDRESS is known to be an uncached address
12345 on R10K systems. */
12348 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
12350 unsigned HOST_WIDE_INT upper;
12352 /* Check for KSEG1. */
12353 if (address + 0x60000000 < 0x20000000)
12356 /* Check for uncached XKPHYS addresses. */
12357 if (Pmode == DImode)
12359 upper = (address >> 40) & 0xf9ffff;
12360 if (upper == 0x900000 || upper == 0xb80000)
12366 /* Return true if we can prove that an access to address X in instruction
12367 INSN would be safe from R10K speculation. This X is a general
12368 expression; it might not be a legitimate address. */
12371 r10k_safe_address_p (rtx x, rtx insn)
12374 HOST_WIDE_INT offset_val;
12376 x = r10k_simplify_address (x, insn);
12378 /* Check for references to the stack frame. It doesn't really matter
12379 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
12380 allows us to assume that accesses to any part of the eventual frame
12381 is safe from speculation at any point in the function. */
12382 mips_split_plus (x, &base, &offset_val);
12383 if (base == virtual_incoming_args_rtx
12384 && offset_val >= -cfun->machine->frame.total_size
12385 && offset_val < cfun->machine->frame.args_size)
12388 /* Check for uncached addresses. */
12389 if (CONST_INT_P (x))
12390 return r10k_uncached_address_p (INTVAL (x));
12392 /* Check for accesses to a static object. */
12393 split_const (x, &base, &offset);
12394 return offset_within_block_p (base, INTVAL (offset));
12397 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
12398 an in-range access to an automatic variable, or to an object with
12399 a link-time-constant address. */
12402 r10k_safe_mem_expr_p (tree expr, rtx offset)
12404 if (expr == NULL_TREE
12405 || offset == NULL_RTX
12406 || !CONST_INT_P (offset)
12407 || INTVAL (offset) < 0
12408 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
12411 while (TREE_CODE (expr) == COMPONENT_REF)
12413 expr = TREE_OPERAND (expr, 0);
12414 if (expr == NULL_TREE)
12418 return DECL_P (expr);
12421 /* A for_each_rtx callback for which DATA points to the instruction
12422 containing *X. Stop the search if we find a MEM that is not safe
12423 from R10K speculation. */
12426 r10k_needs_protection_p_1 (rtx *loc, void *data)
12434 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
12437 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
12443 /* A note_stores callback for which DATA points to an instruction pointer.
12444 If *DATA is nonnull, make it null if it X contains a MEM that is not
12445 safe from R10K speculation. */
12448 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12453 insn_ptr = (rtx *) data;
12454 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
12455 *insn_ptr = NULL_RTX;
12458 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
12459 Return nonzero if the call is not to a declared function. */
12462 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
12471 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
12477 /* Return true if instruction INSN needs to be protected by an R10K
12481 r10k_needs_protection_p (rtx insn)
12484 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
12486 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
12488 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
12489 return insn == NULL_RTX;
12492 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
12495 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
12496 edge is unconditional. */
12499 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
12504 FOR_EACH_EDGE (e, ei, bb->preds)
12505 if (!single_succ_p (e->src)
12506 || !TEST_BIT (protected_bbs, e->src->index)
12507 || (e->flags & EDGE_COMPLEX) != 0)
12512 /* Implement -mr10k-cache-barrier= for the current function. */
12515 r10k_insert_cache_barriers (void)
12517 int *rev_post_order;
12520 sbitmap protected_bbs;
12521 rtx insn, end, unprotected_region;
12525 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
12529 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. */
12530 compute_bb_for_insn ();
12532 /* Create def-use chains. */
12533 df_set_flags (DF_EQ_NOTES);
12534 df_chain_add_problem (DF_UD_CHAIN);
12537 /* Calculate dominators. */
12538 calculate_dominance_info (CDI_DOMINATORS);
12540 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
12541 X is protected by a cache barrier. */
12542 protected_bbs = sbitmap_alloc (last_basic_block);
12543 sbitmap_zero (protected_bbs);
12545 /* Iterate over the basic blocks in reverse post-order. */
12546 rev_post_order = XNEWVEC (int, last_basic_block);
12547 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
12548 for (i = 0; i < n; i++)
12550 bb = BASIC_BLOCK (rev_post_order[i]);
12552 /* If this block is only reached by unconditional edges, and if the
12553 source of every edge is protected, the beginning of the block is
12555 if (r10k_protected_bb_p (bb, protected_bbs))
12556 unprotected_region = NULL_RTX;
12558 unprotected_region = pc_rtx;
12559 end = NEXT_INSN (BB_END (bb));
12561 /* UNPROTECTED_REGION is:
12563 - null if we are processing a protected region,
12564 - pc_rtx if we are processing an unprotected region but have
12565 not yet found the first instruction in it
12566 - the first instruction in an unprotected region otherwise. */
12567 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
12569 if (unprotected_region && INSN_P (insn))
12571 if (recog_memoized (insn) == CODE_FOR_mips_cache)
12572 /* This CACHE instruction protects the following code. */
12573 unprotected_region = NULL_RTX;
12576 /* See if INSN is the first instruction in this
12577 unprotected region. */
12578 if (unprotected_region == pc_rtx)
12579 unprotected_region = insn;
12581 /* See if INSN needs to be protected. If so,
12582 we must insert a cache barrier somewhere between
12583 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
12584 clear which position is better performance-wise,
12585 but as a tie-breaker, we assume that it is better
12586 to allow delay slots to be back-filled where
12587 possible, and that it is better not to insert
12588 barriers in the middle of already-scheduled code.
12589 We therefore insert the barrier at the beginning
12591 if (r10k_needs_protection_p (insn))
12593 emit_insn_before (gen_r10k_cache_barrier (),
12594 unprotected_region);
12595 unprotected_region = NULL_RTX;
12601 /* The called function is not required to protect the exit path.
12602 The code that follows a call is therefore unprotected. */
12603 unprotected_region = pc_rtx;
12606 /* Record whether the end of this block is protected. */
12607 if (unprotected_region == NULL_RTX)
12608 SET_BIT (protected_bbs, bb->index);
12610 XDELETEVEC (rev_post_order);
12612 sbitmap_free (protected_bbs);
12614 free_dominance_info (CDI_DOMINATORS);
12616 df_finish_pass (false);
12618 free_bb_for_insn ();
12621 /* A temporary variable used by for_each_rtx callbacks, etc. */
12622 static rtx mips_sim_insn;
12624 /* A structure representing the state of the processor pipeline.
12625 Used by the mips_sim_* family of functions. */
12627 /* The maximum number of instructions that can be issued in a cycle.
12628 (Caches mips_issue_rate.) */
12629 unsigned int issue_rate;
12631 /* The current simulation time. */
12634 /* How many more instructions can be issued in the current cycle. */
12635 unsigned int insns_left;
12637 /* LAST_SET[X].INSN is the last instruction to set register X.
12638 LAST_SET[X].TIME is the time at which that instruction was issued.
12639 INSN is null if no instruction has yet set register X. */
12643 } last_set[FIRST_PSEUDO_REGISTER];
12645 /* The pipeline's current DFA state. */
12649 /* Reset STATE to the initial simulation state. */
12652 mips_sim_reset (struct mips_sim *state)
12655 state->insns_left = state->issue_rate;
12656 memset (&state->last_set, 0, sizeof (state->last_set));
12657 state_reset (state->dfa_state);
12660 /* Initialize STATE before its first use. DFA_STATE points to an
12661 allocated but uninitialized DFA state. */
12664 mips_sim_init (struct mips_sim *state, state_t dfa_state)
12666 state->issue_rate = mips_issue_rate ();
12667 state->dfa_state = dfa_state;
12668 mips_sim_reset (state);
12671 /* Advance STATE by one clock cycle. */
12674 mips_sim_next_cycle (struct mips_sim *state)
12677 state->insns_left = state->issue_rate;
12678 state_transition (state->dfa_state, 0);
12681 /* Advance simulation state STATE until instruction INSN can read
12685 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
12687 unsigned int regno, end_regno;
12689 end_regno = END_REGNO (reg);
12690 for (regno = REGNO (reg); regno < end_regno; regno++)
12691 if (state->last_set[regno].insn != 0)
12695 t = (state->last_set[regno].time
12696 + insn_latency (state->last_set[regno].insn, insn));
12697 while (state->time < t)
12698 mips_sim_next_cycle (state);
12702 /* A for_each_rtx callback. If *X is a register, advance simulation state
12703 DATA until mips_sim_insn can read the register's value. */
12706 mips_sim_wait_regs_2 (rtx *x, void *data)
12709 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
12713 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
12716 mips_sim_wait_regs_1 (rtx *x, void *data)
12718 for_each_rtx (x, mips_sim_wait_regs_2, data);
12721 /* Advance simulation state STATE until all of INSN's register
12722 dependencies are satisfied. */
12725 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
12727 mips_sim_insn = insn;
12728 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
12731 /* Advance simulation state STATE until the units required by
12732 instruction INSN are available. */
12735 mips_sim_wait_units (struct mips_sim *state, rtx insn)
12739 tmp_state = alloca (state_size ());
12740 while (state->insns_left == 0
12741 || (memcpy (tmp_state, state->dfa_state, state_size ()),
12742 state_transition (tmp_state, insn) >= 0))
12743 mips_sim_next_cycle (state);
12746 /* Advance simulation state STATE until INSN is ready to issue. */
12749 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
12751 mips_sim_wait_regs (state, insn);
12752 mips_sim_wait_units (state, insn);
12755 /* mips_sim_insn has just set X. Update the LAST_SET array
12756 in simulation state DATA. */
12759 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
12761 struct mips_sim *state;
12763 state = (struct mips_sim *) data;
12766 unsigned int regno, end_regno;
12768 end_regno = END_REGNO (x);
12769 for (regno = REGNO (x); regno < end_regno; regno++)
12771 state->last_set[regno].insn = mips_sim_insn;
12772 state->last_set[regno].time = state->time;
12777 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
12778 can issue immediately (i.e., that mips_sim_wait_insn has already
12782 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
12784 state_transition (state->dfa_state, insn);
12785 state->insns_left--;
12787 mips_sim_insn = insn;
12788 note_stores (PATTERN (insn), mips_sim_record_set, state);
12791 /* Simulate issuing a NOP in state STATE. */
12794 mips_sim_issue_nop (struct mips_sim *state)
12796 if (state->insns_left == 0)
12797 mips_sim_next_cycle (state);
12798 state->insns_left--;
12801 /* Update simulation state STATE so that it's ready to accept the instruction
12802 after INSN. INSN should be part of the main rtl chain, not a member of a
12806 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
12808 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
12810 mips_sim_issue_nop (state);
12812 switch (GET_CODE (SEQ_BEGIN (insn)))
12816 /* We can't predict the processor state after a call or label. */
12817 mips_sim_reset (state);
12821 /* The delay slots of branch likely instructions are only executed
12822 when the branch is taken. Therefore, if the caller has simulated
12823 the delay slot instruction, STATE does not really reflect the state
12824 of the pipeline for the instruction after the delay slot. Also,
12825 branch likely instructions tend to incur a penalty when not taken,
12826 so there will probably be an extra delay between the branch and
12827 the instruction after the delay slot. */
12828 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
12829 mips_sim_reset (state);
12837 /* The VR4130 pipeline issues aligned pairs of instructions together,
12838 but it stalls the second instruction if it depends on the first.
12839 In order to cut down the amount of logic required, this dependence
12840 check is not based on a full instruction decode. Instead, any non-SPECIAL
12841 instruction is assumed to modify the register specified by bits 20-16
12842 (which is usually the "rt" field).
12844 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
12845 input, so we can end up with a false dependence between the branch
12846 and its delay slot. If this situation occurs in instruction INSN,
12847 try to avoid it by swapping rs and rt. */
12850 vr4130_avoid_branch_rt_conflict (rtx insn)
12854 first = SEQ_BEGIN (insn);
12855 second = SEQ_END (insn);
12857 && NONJUMP_INSN_P (second)
12858 && GET_CODE (PATTERN (first)) == SET
12859 && GET_CODE (SET_DEST (PATTERN (first))) == PC
12860 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
12862 /* Check for the right kind of condition. */
12863 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
12864 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
12865 && REG_P (XEXP (cond, 0))
12866 && REG_P (XEXP (cond, 1))
12867 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
12868 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
12870 /* SECOND mentions the rt register but not the rs register. */
12871 rtx tmp = XEXP (cond, 0);
12872 XEXP (cond, 0) = XEXP (cond, 1);
12873 XEXP (cond, 1) = tmp;
12878 /* Implement -mvr4130-align. Go through each basic block and simulate the
12879 processor pipeline. If we find that a pair of instructions could execute
12880 in parallel, and the first of those instructions is not 8-byte aligned,
12881 insert a nop to make it aligned. */
12884 vr4130_align_insns (void)
12886 struct mips_sim state;
12887 rtx insn, subinsn, last, last2, next;
12892 /* LAST is the last instruction before INSN to have a nonzero length.
12893 LAST2 is the last such instruction before LAST. */
12897 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
12900 mips_sim_init (&state, alloca (state_size ()));
12901 for (insn = get_insns (); insn != 0; insn = next)
12903 unsigned int length;
12905 next = NEXT_INSN (insn);
12907 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
12908 This isn't really related to the alignment pass, but we do it on
12909 the fly to avoid a separate instruction walk. */
12910 vr4130_avoid_branch_rt_conflict (insn);
12912 if (USEFUL_INSN_P (insn))
12913 FOR_EACH_SUBINSN (subinsn, insn)
12915 mips_sim_wait_insn (&state, subinsn);
12917 /* If we want this instruction to issue in parallel with the
12918 previous one, make sure that the previous instruction is
12919 aligned. There are several reasons why this isn't worthwhile
12920 when the second instruction is a call:
12922 - Calls are less likely to be performance critical,
12923 - There's a good chance that the delay slot can execute
12924 in parallel with the call.
12925 - The return address would then be unaligned.
12927 In general, if we're going to insert a nop between instructions
12928 X and Y, it's better to insert it immediately after X. That
12929 way, if the nop makes Y aligned, it will also align any labels
12930 between X and Y. */
12931 if (state.insns_left != state.issue_rate
12932 && !CALL_P (subinsn))
12934 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
12936 /* SUBINSN is the first instruction in INSN and INSN is
12937 aligned. We want to align the previous instruction
12938 instead, so insert a nop between LAST2 and LAST.
12940 Note that LAST could be either a single instruction
12941 or a branch with a delay slot. In the latter case,
12942 LAST, like INSN, is already aligned, but the delay
12943 slot must have some extra delay that stops it from
12944 issuing at the same time as the branch. We therefore
12945 insert a nop before the branch in order to align its
12947 emit_insn_after (gen_nop (), last2);
12950 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
12952 /* SUBINSN is the delay slot of INSN, but INSN is
12953 currently unaligned. Insert a nop between
12954 LAST and INSN to align it. */
12955 emit_insn_after (gen_nop (), last);
12959 mips_sim_issue_insn (&state, subinsn);
12961 mips_sim_finish_insn (&state, insn);
12963 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
12964 length = get_attr_length (insn);
12967 /* If the instruction is an asm statement or multi-instruction
12968 mips.md patern, the length is only an estimate. Insert an
12969 8 byte alignment after it so that the following instructions
12970 can be handled correctly. */
12971 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
12972 && (recog_memoized (insn) < 0 || length >= 8))
12974 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
12975 next = NEXT_INSN (next);
12976 mips_sim_next_cycle (&state);
12979 else if (length & 4)
12980 aligned_p = !aligned_p;
12985 /* See whether INSN is an aligned label. */
12986 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
12992 /* This structure records that the current function has a LO_SUM
12993 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
12994 the largest offset applied to BASE by all such LO_SUMs. */
12995 struct mips_lo_sum_offset {
12997 HOST_WIDE_INT offset;
13000 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
13003 mips_hash_base (rtx base)
13005 int do_not_record_p;
13007 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
13010 /* Hash-table callbacks for mips_lo_sum_offsets. */
13013 mips_lo_sum_offset_hash (const void *entry)
13015 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
13019 mips_lo_sum_offset_eq (const void *entry, const void *value)
13021 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
13022 (const_rtx) value);
13025 /* Look up symbolic constant X in HTAB, which is a hash table of
13026 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
13027 paired with a recorded LO_SUM, otherwise record X in the table. */
13030 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
13034 struct mips_lo_sum_offset *entry;
13036 /* Split X into a base and offset. */
13037 split_const (x, &base, &offset);
13038 if (UNSPEC_ADDRESS_P (base))
13039 base = UNSPEC_ADDRESS (base);
13041 /* Look up the base in the hash table. */
13042 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
13046 entry = (struct mips_lo_sum_offset *) *slot;
13047 if (option == INSERT)
13051 entry = XNEW (struct mips_lo_sum_offset);
13052 entry->base = base;
13053 entry->offset = INTVAL (offset);
13058 if (INTVAL (offset) > entry->offset)
13059 entry->offset = INTVAL (offset);
13062 return INTVAL (offset) <= entry->offset;
13065 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
13066 Record every LO_SUM in *LOC. */
13069 mips_record_lo_sum (rtx *loc, void *data)
13071 if (GET_CODE (*loc) == LO_SUM)
13072 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
13076 /* Return true if INSN is a SET of an orphaned high-part relocation.
13077 HTAB is a hash table of mips_lo_sum_offsets that describes all the
13078 LO_SUMs in the current function. */
13081 mips_orphaned_high_part_p (htab_t htab, rtx insn)
13083 enum mips_symbol_type type;
13086 set = single_set (insn);
13089 /* Check for %his. */
13091 if (GET_CODE (x) == HIGH
13092 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
13093 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
13095 /* Check for local %gots (and %got_pages, which is redundant but OK). */
13096 if (GET_CODE (x) == UNSPEC
13097 && XINT (x, 1) == UNSPEC_LOAD_GOT
13098 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
13099 SYMBOL_CONTEXT_LEA, &type)
13100 && type == SYMBOL_GOTOFF_PAGE)
13101 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
13106 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
13107 INSN and a previous instruction, avoid it by inserting nops after
13110 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
13111 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
13112 before using the value of that register. *HILO_DELAY counts the
13113 number of instructions since the last hilo hazard (that is,
13114 the number of instructions since the last MFLO or MFHI).
13116 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
13117 for the next instruction.
13119 LO_REG is an rtx for the LO register, used in dependence checking. */
13122 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
13123 rtx *delayed_reg, rtx lo_reg)
13128 pattern = PATTERN (insn);
13130 /* Do not put the whole function in .set noreorder if it contains
13131 an asm statement. We don't know whether there will be hazards
13132 between the asm statement and the gcc-generated code. */
13133 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
13134 cfun->machine->all_noreorder_p = false;
13136 /* Ignore zero-length instructions (barriers and the like). */
13137 ninsns = get_attr_length (insn) / 4;
13141 /* Work out how many nops are needed. Note that we only care about
13142 registers that are explicitly mentioned in the instruction's pattern.
13143 It doesn't matter that calls use the argument registers or that they
13144 clobber hi and lo. */
13145 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
13146 nops = 2 - *hilo_delay;
13147 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
13152 /* Insert the nops between this instruction and the previous one.
13153 Each new nop takes us further from the last hilo hazard. */
13154 *hilo_delay += nops;
13156 emit_insn_after (gen_hazard_nop (), after);
13158 /* Set up the state for the next instruction. */
13159 *hilo_delay += ninsns;
13161 if (INSN_CODE (insn) >= 0)
13162 switch (get_attr_hazard (insn))
13172 set = single_set (insn);
13174 *delayed_reg = SET_DEST (set);
13179 /* Go through the instruction stream and insert nops where necessary.
13180 Also delete any high-part relocations whose partnering low parts
13181 are now all dead. See if the whole function can then be put into
13182 .set noreorder and .set nomacro. */
13185 mips_reorg_process_insns (void)
13187 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
13191 /* Force all instructions to be split into their final form. */
13192 split_all_insns_noflow ();
13194 /* Recalculate instruction lengths without taking nops into account. */
13195 cfun->machine->ignore_hazard_length_p = true;
13196 shorten_branches (get_insns ());
13198 cfun->machine->all_noreorder_p = true;
13200 /* We don't track MIPS16 PC-relative offsets closely enough to make
13201 a good job of "set .noreorder" code in MIPS16 mode. */
13203 cfun->machine->all_noreorder_p = false;
13205 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
13206 if (!TARGET_EXPLICIT_RELOCS)
13207 cfun->machine->all_noreorder_p = false;
13209 /* Profiled functions can't be all noreorder because the profiler
13210 support uses assembler macros. */
13212 cfun->machine->all_noreorder_p = false;
13214 /* Code compiled with -mfix-vr4120 can't be all noreorder because
13215 we rely on the assembler to work around some errata. */
13216 if (TARGET_FIX_VR4120)
13217 cfun->machine->all_noreorder_p = false;
13219 /* The same is true for -mfix-vr4130 if we might generate MFLO or
13220 MFHI instructions. Note that we avoid using MFLO and MFHI if
13221 the VR4130 MACC and DMACC instructions are available instead;
13222 see the *mfhilo_{si,di}_macc patterns. */
13223 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
13224 cfun->machine->all_noreorder_p = false;
13226 htab = htab_create (37, mips_lo_sum_offset_hash,
13227 mips_lo_sum_offset_eq, free);
13229 /* Make a first pass over the instructions, recording all the LO_SUMs. */
13230 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13231 FOR_EACH_SUBINSN (subinsn, insn)
13232 if (INSN_P (subinsn))
13233 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
13238 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
13240 /* Make a second pass over the instructions. Delete orphaned
13241 high-part relocations or turn them into NOPs. Avoid hazards
13242 by inserting NOPs. */
13243 for (insn = get_insns (); insn != 0; insn = next_insn)
13245 next_insn = NEXT_INSN (insn);
13248 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
13250 /* If we find an orphaned high-part relocation in a delay
13251 slot, it's easier to turn that instruction into a NOP than
13252 to delete it. The delay slot will be a NOP either way. */
13253 FOR_EACH_SUBINSN (subinsn, insn)
13254 if (INSN_P (subinsn))
13256 if (mips_orphaned_high_part_p (htab, subinsn))
13258 PATTERN (subinsn) = gen_nop ();
13259 INSN_CODE (subinsn) = CODE_FOR_nop;
13261 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
13262 &delayed_reg, lo_reg);
13268 /* INSN is a single instruction. Delete it if it's an
13269 orphaned high-part relocation. */
13270 if (mips_orphaned_high_part_p (htab, insn))
13271 delete_insn (insn);
13272 /* Also delete cache barriers if the last instruction
13273 was an annulled branch. INSN will not be speculatively
13275 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
13277 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
13278 delete_insn (insn);
13281 mips_avoid_hazard (last_insn, insn, &hilo_delay,
13282 &delayed_reg, lo_reg);
13289 htab_delete (htab);
13292 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
13297 mips16_lay_out_constants ();
13298 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
13299 r10k_insert_cache_barriers ();
13300 if (optimize > 0 && flag_delayed_branch)
13301 dbr_schedule (get_insns ());
13302 mips_reorg_process_insns ();
13304 && TARGET_EXPLICIT_RELOCS
13306 && TARGET_VR4130_ALIGN)
13307 vr4130_align_insns ();
13310 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
13311 in order to avoid duplicating too much logic from elsewhere. */
13314 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13315 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13318 rtx this_rtx, temp1, temp2, insn, fnaddr;
13319 bool use_sibcall_p;
13321 /* Pretend to be a post-reload pass while generating rtl. */
13322 reload_completed = 1;
13324 /* Mark the end of the (empty) prologue. */
13325 emit_note (NOTE_INSN_PROLOGUE_END);
13327 /* Determine if we can use a sibcall to call FUNCTION directly. */
13328 fnaddr = XEXP (DECL_RTL (function), 0);
13329 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
13330 && const_call_insn_operand (fnaddr, Pmode));
13332 /* Determine if we need to load FNADDR from the GOT. */
13334 && (mips_got_symbol_type_p
13335 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
13337 /* Pick a global pointer. Use a call-clobbered register if
13338 TARGET_CALL_SAVED_GP. */
13339 cfun->machine->global_pointer
13340 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
13341 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
13343 /* Set up the global pointer for n32 or n64 abicalls. */
13344 mips_emit_loadgp ();
13347 /* We need two temporary registers in some cases. */
13348 temp1 = gen_rtx_REG (Pmode, 2);
13349 temp2 = gen_rtx_REG (Pmode, 3);
13351 /* Find out which register contains the "this" pointer. */
13352 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13353 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
13355 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
13357 /* Add DELTA to THIS_RTX. */
13360 rtx offset = GEN_INT (delta);
13361 if (!SMALL_OPERAND (delta))
13363 mips_emit_move (temp1, offset);
13366 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
13369 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
13370 if (vcall_offset != 0)
13374 /* Set TEMP1 to *THIS_RTX. */
13375 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
13377 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
13378 addr = mips_add_offset (temp2, temp1, vcall_offset);
13380 /* Load the offset and add it to THIS_RTX. */
13381 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
13382 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
13385 /* Jump to the target function. Use a sibcall if direct jumps are
13386 allowed, otherwise load the address into a register first. */
13389 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
13390 SIBLING_CALL_P (insn) = 1;
13394 /* This is messy. GAS treats "la $25,foo" as part of a call
13395 sequence and may allow a global "foo" to be lazily bound.
13396 The general move patterns therefore reject this combination.
13398 In this context, lazy binding would actually be OK
13399 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
13400 TARGET_CALL_SAVED_GP; see mips_load_call_address.
13401 We must therefore load the address via a temporary
13402 register if mips_dangerous_for_la25_p.
13404 If we jump to the temporary register rather than $25,
13405 the assembler can use the move insn to fill the jump's
13408 We can use the same technique for MIPS16 code, where $25
13409 is not a valid JR register. */
13410 if (TARGET_USE_PIC_FN_ADDR_REG
13412 && !mips_dangerous_for_la25_p (fnaddr))
13413 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
13414 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
13416 if (TARGET_USE_PIC_FN_ADDR_REG
13417 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
13418 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
13419 emit_jump_insn (gen_indirect_jump (temp1));
13422 /* Run just enough of rest_of_compilation. This sequence was
13423 "borrowed" from alpha.c. */
13424 insn = get_insns ();
13425 insn_locators_alloc ();
13426 split_all_insns_noflow ();
13427 mips16_lay_out_constants ();
13428 shorten_branches (insn);
13429 final_start_function (insn, file, 1);
13430 final (insn, file, 1);
13431 final_end_function ();
13432 free_after_compilation (cfun);
13434 /* Clean up the vars set above. Note that final_end_function resets
13435 the global pointer for us. */
13436 reload_completed = 0;
13439 /* The last argument passed to mips_set_mips16_mode, or negative if the
13440 function hasn't been called yet.
13442 There are two copies of this information. One is saved and restored
13443 by the PCH process while the other is specific to this compiler
13444 invocation. The information calculated by mips_set_mips16_mode
13445 is invalid unless the two variables are the same. */
13446 static int was_mips16_p = -1;
13447 static GTY(()) int was_mips16_pch_p = -1;
13449 /* Set up the target-dependent global state so that it matches the
13450 current function's ISA mode. */
13453 mips_set_mips16_mode (int mips16_p)
13455 if (mips16_p == was_mips16_p
13456 && mips16_p == was_mips16_pch_p)
13459 /* Restore base settings of various flags. */
13460 target_flags = mips_base_target_flags;
13461 flag_schedule_insns = mips_base_schedule_insns;
13462 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
13463 flag_move_loop_invariants = mips_base_move_loop_invariants;
13464 align_loops = mips_base_align_loops;
13465 align_jumps = mips_base_align_jumps;
13466 align_functions = mips_base_align_functions;
13470 /* Switch to MIPS16 mode. */
13471 target_flags |= MASK_MIPS16;
13473 /* Don't run the scheduler before reload, since it tends to
13474 increase register pressure. */
13475 flag_schedule_insns = 0;
13477 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
13478 the whole function to be in a single section. */
13479 flag_reorder_blocks_and_partition = 0;
13481 /* Don't move loop invariants, because it tends to increase
13482 register pressure. It also introduces an extra move in cases
13483 where the constant is the first operand in a two-operand binary
13484 instruction, or when it forms a register argument to a functon
13486 flag_move_loop_invariants = 0;
13488 target_flags |= MASK_EXPLICIT_RELOCS;
13490 /* Experiments suggest we get the best overall section-anchor
13491 results from using the range of an unextended LW or SW. Code
13492 that makes heavy use of byte or short accesses can do better
13493 with ranges of 0...31 and 0...63 respectively, but most code is
13494 sensitive to the range of LW and SW instead. */
13495 targetm.min_anchor_offset = 0;
13496 targetm.max_anchor_offset = 127;
13498 if (flag_pic && !TARGET_OLDABI)
13499 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
13502 sorry ("MIPS16 -mxgot code");
13504 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
13505 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
13509 /* Switch to normal (non-MIPS16) mode. */
13510 target_flags &= ~MASK_MIPS16;
13512 /* Provide default values for align_* for 64-bit targets. */
13515 if (align_loops == 0)
13517 if (align_jumps == 0)
13519 if (align_functions == 0)
13520 align_functions = 8;
13523 targetm.min_anchor_offset = -32768;
13524 targetm.max_anchor_offset = 32767;
13527 /* (Re)initialize MIPS target internals for new ISA. */
13528 mips_init_relocs ();
13530 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
13531 /* Reinitialize target-dependent state. */
13534 was_mips16_p = mips16_p;
13535 was_mips16_pch_p = mips16_p;
13538 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
13539 function should use the MIPS16 ISA and switch modes accordingly. */
13542 mips_set_current_function (tree fndecl)
13544 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
13547 /* Allocate a chunk of memory for per-function machine-dependent data. */
13549 static struct machine_function *
13550 mips_init_machine_status (void)
13552 return ((struct machine_function *)
13553 ggc_alloc_cleared (sizeof (struct machine_function)));
13556 /* Return the processor associated with the given ISA level, or null
13557 if the ISA isn't valid. */
13559 static const struct mips_cpu_info *
13560 mips_cpu_info_from_isa (int isa)
13564 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
13565 if (mips_cpu_info_table[i].isa == isa)
13566 return mips_cpu_info_table + i;
13571 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13572 with a final "000" replaced by "k". Ignore case.
13574 Note: this function is shared between GCC and GAS. */
13577 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
13579 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13580 given++, canonical++;
13582 return ((*given == 0 && *canonical == 0)
13583 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13586 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13587 CPU name. We've traditionally allowed a lot of variation here.
13589 Note: this function is shared between GCC and GAS. */
13592 mips_matching_cpu_name_p (const char *canonical, const char *given)
13594 /* First see if the name matches exactly, or with a final "000"
13595 turned into "k". */
13596 if (mips_strict_matching_cpu_name_p (canonical, given))
13599 /* If not, try comparing based on numerical designation alone.
13600 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13601 if (TOLOWER (*given) == 'r')
13603 if (!ISDIGIT (*given))
13606 /* Skip over some well-known prefixes in the canonical name,
13607 hoping to find a number there too. */
13608 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13610 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13612 else if (TOLOWER (canonical[0]) == 'r')
13615 return mips_strict_matching_cpu_name_p (canonical, given);
13618 /* Return the mips_cpu_info entry for the processor or ISA given
13619 by CPU_STRING. Return null if the string isn't recognized.
13621 A similar function exists in GAS. */
13623 static const struct mips_cpu_info *
13624 mips_parse_cpu (const char *cpu_string)
13629 /* In the past, we allowed upper-case CPU names, but it doesn't
13630 work well with the multilib machinery. */
13631 for (s = cpu_string; *s != 0; s++)
13634 warning (0, "CPU names must be lower case");
13638 /* 'from-abi' selects the most compatible architecture for the given
13639 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13640 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13642 if (strcasecmp (cpu_string, "from-abi") == 0)
13643 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
13644 : ABI_NEEDS_64BIT_REGS ? 3
13645 : (TARGET_64BIT ? 3 : 1));
13647 /* 'default' has traditionally been a no-op. Probably not very useful. */
13648 if (strcasecmp (cpu_string, "default") == 0)
13651 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
13652 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
13653 return mips_cpu_info_table + i;
13658 /* Set up globals to generate code for the ISA or processor
13659 described by INFO. */
13662 mips_set_architecture (const struct mips_cpu_info *info)
13666 mips_arch_info = info;
13667 mips_arch = info->cpu;
13668 mips_isa = info->isa;
13672 /* Likewise for tuning. */
13675 mips_set_tune (const struct mips_cpu_info *info)
13679 mips_tune_info = info;
13680 mips_tune = info->cpu;
13684 /* Implement TARGET_HANDLE_OPTION. */
13687 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
13692 if (strcmp (arg, "32") == 0)
13694 else if (strcmp (arg, "o64") == 0)
13695 mips_abi = ABI_O64;
13696 else if (strcmp (arg, "n32") == 0)
13697 mips_abi = ABI_N32;
13698 else if (strcmp (arg, "64") == 0)
13700 else if (strcmp (arg, "eabi") == 0)
13701 mips_abi = ABI_EABI;
13708 return mips_parse_cpu (arg) != 0;
13711 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
13712 return mips_isa_option_info != 0;
13714 case OPT_mno_flush_func:
13715 mips_cache_flush_func = NULL;
13718 case OPT_mcode_readable_:
13719 if (strcmp (arg, "yes") == 0)
13720 mips_code_readable = CODE_READABLE_YES;
13721 else if (strcmp (arg, "pcrel") == 0)
13722 mips_code_readable = CODE_READABLE_PCREL;
13723 else if (strcmp (arg, "no") == 0)
13724 mips_code_readable = CODE_READABLE_NO;
13729 case OPT_mr10k_cache_barrier_:
13730 if (strcmp (arg, "load-store") == 0)
13731 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
13732 else if (strcmp (arg, "store") == 0)
13733 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
13734 else if (strcmp (arg, "none") == 0)
13735 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
13745 /* Implement OVERRIDE_OPTIONS. */
13748 mips_override_options (void)
13750 int i, start, regno, mode;
13752 /* Process flags as though we were generating non-MIPS16 code. */
13753 mips_base_mips16 = TARGET_MIPS16;
13754 target_flags &= ~MASK_MIPS16;
13756 #ifdef SUBTARGET_OVERRIDE_OPTIONS
13757 SUBTARGET_OVERRIDE_OPTIONS;
13760 /* Set the small data limit. */
13761 mips_small_data_threshold = (g_switch_set
13763 : MIPS_DEFAULT_GVALUE);
13765 /* The following code determines the architecture and register size.
13766 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
13767 The GAS and GCC code should be kept in sync as much as possible. */
13769 if (mips_arch_string != 0)
13770 mips_set_architecture (mips_parse_cpu (mips_arch_string));
13772 if (mips_isa_option_info != 0)
13774 if (mips_arch_info == 0)
13775 mips_set_architecture (mips_isa_option_info);
13776 else if (mips_arch_info->isa != mips_isa_option_info->isa)
13777 error ("%<-%s%> conflicts with the other architecture options, "
13778 "which specify a %s processor",
13779 mips_isa_option_info->name,
13780 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
13783 if (mips_arch_info == 0)
13785 #ifdef MIPS_CPU_STRING_DEFAULT
13786 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
13788 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
13792 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
13793 error ("%<-march=%s%> is not compatible with the selected ABI",
13794 mips_arch_info->name);
13796 /* Optimize for mips_arch, unless -mtune selects a different processor. */
13797 if (mips_tune_string != 0)
13798 mips_set_tune (mips_parse_cpu (mips_tune_string));
13800 if (mips_tune_info == 0)
13801 mips_set_tune (mips_arch_info);
13803 if ((target_flags_explicit & MASK_64BIT) != 0)
13805 /* The user specified the size of the integer registers. Make sure
13806 it agrees with the ABI and ISA. */
13807 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
13808 error ("%<-mgp64%> used with a 32-bit processor");
13809 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
13810 error ("%<-mgp32%> used with a 64-bit ABI");
13811 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
13812 error ("%<-mgp64%> used with a 32-bit ABI");
13816 /* Infer the integer register size from the ABI and processor.
13817 Restrict ourselves to 32-bit registers if that's all the
13818 processor has, or if the ABI cannot handle 64-bit registers. */
13819 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
13820 target_flags &= ~MASK_64BIT;
13822 target_flags |= MASK_64BIT;
13825 if ((target_flags_explicit & MASK_FLOAT64) != 0)
13827 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
13828 error ("unsupported combination: %s", "-mfp64 -msingle-float");
13829 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
13830 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
13831 else if (!TARGET_64BIT && TARGET_FLOAT64)
13833 if (!ISA_HAS_MXHC1)
13834 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
13835 " the target supports the mfhc1 and mthc1 instructions");
13836 else if (mips_abi != ABI_32)
13837 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
13843 /* -msingle-float selects 32-bit float registers. Otherwise the
13844 float registers should be the same size as the integer ones. */
13845 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
13846 target_flags |= MASK_FLOAT64;
13848 target_flags &= ~MASK_FLOAT64;
13851 /* End of code shared with GAS. */
13853 /* If no -mlong* option was given, infer it from the other options. */
13854 if ((target_flags_explicit & MASK_LONG64) == 0)
13856 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
13857 target_flags |= MASK_LONG64;
13859 target_flags &= ~MASK_LONG64;
13862 if (!TARGET_OLDABI)
13863 flag_pcc_struct_return = 0;
13865 /* Decide which rtx_costs structure to use. */
13867 mips_cost = &mips_rtx_cost_optimize_size;
13869 mips_cost = &mips_rtx_cost_data[mips_tune];
13871 /* If the user hasn't specified a branch cost, use the processor's
13873 if (mips_branch_cost == 0)
13874 mips_branch_cost = mips_cost->branch_cost;
13876 /* If neither -mbranch-likely nor -mno-branch-likely was given
13877 on the command line, set MASK_BRANCHLIKELY based on the target
13878 architecture and tuning flags. Annulled delay slots are a
13879 size win, so we only consider the processor-specific tuning
13880 for !optimize_size. */
13881 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
13883 if (ISA_HAS_BRANCHLIKELY
13885 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
13886 target_flags |= MASK_BRANCHLIKELY;
13888 target_flags &= ~MASK_BRANCHLIKELY;
13890 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
13891 warning (0, "the %qs architecture does not support branch-likely"
13892 " instructions", mips_arch_info->name);
13894 /* The effect of -mabicalls isn't defined for the EABI. */
13895 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
13897 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
13898 target_flags &= ~MASK_ABICALLS;
13901 if (TARGET_ABICALLS_PIC2)
13902 /* We need to set flag_pic for executables as well as DSOs
13903 because we may reference symbols that are not defined in
13904 the final executable. (MIPS does not use things like
13905 copy relocs, for example.)
13907 There is a body of code that uses __PIC__ to distinguish
13908 between -mabicalls and -mno-abicalls code. The non-__PIC__
13909 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
13910 long as any indirect jumps use $25. */
13913 /* -mvr4130-align is a "speed over size" optimization: it usually produces
13914 faster code, but at the expense of more nops. Enable it at -O3 and
13916 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
13917 target_flags |= MASK_VR4130_ALIGN;
13919 /* Prefer a call to memcpy over inline code when optimizing for size,
13920 though see MOVE_RATIO in mips.h. */
13921 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
13922 target_flags |= MASK_MEMCPY;
13924 /* If we have a nonzero small-data limit, check that the -mgpopt
13925 setting is consistent with the other target flags. */
13926 if (mips_small_data_threshold > 0)
13930 if (!TARGET_EXPLICIT_RELOCS)
13931 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
13933 TARGET_LOCAL_SDATA = false;
13934 TARGET_EXTERN_SDATA = false;
13938 if (TARGET_VXWORKS_RTP)
13939 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
13941 if (TARGET_ABICALLS)
13942 warning (0, "cannot use small-data accesses for %qs",
13947 #ifdef MIPS_TFMODE_FORMAT
13948 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
13951 /* Make sure that the user didn't turn off paired single support when
13952 MIPS-3D support is requested. */
13954 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
13955 && !TARGET_PAIRED_SINGLE_FLOAT)
13956 error ("%<-mips3d%> requires %<-mpaired-single%>");
13958 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
13960 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
13962 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
13963 and TARGET_HARD_FLOAT_ABI are both true. */
13964 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
13965 error ("%qs must be used with %qs",
13966 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
13967 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
13969 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
13971 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
13972 warning (0, "the %qs architecture does not support paired-single"
13973 " instructions", mips_arch_info->name);
13975 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13976 && !TARGET_CACHE_BUILTIN)
13978 error ("%qs requires a target that provides the %qs instruction",
13979 "-mr10k-cache-barrier", "cache");
13980 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
13983 /* If TARGET_DSPR2, enable MASK_DSP. */
13985 target_flags |= MASK_DSP;
13987 /* .eh_frame addresses should be the same width as a C pointer.
13988 Most MIPS ABIs support only one pointer size, so the assembler
13989 will usually know exactly how big an .eh_frame address is.
13991 Unfortunately, this is not true of the 64-bit EABI. The ABI was
13992 originally defined to use 64-bit pointers (i.e. it is LP64), and
13993 this is still the default mode. However, we also support an n32-like
13994 ILP32 mode, which is selected by -mlong32. The problem is that the
13995 assembler has traditionally not had an -mlong option, so it has
13996 traditionally not known whether we're using the ILP32 or LP64 form.
13998 As it happens, gas versions up to and including 2.19 use _32-bit_
13999 addresses for EABI64 .cfi_* directives. This is wrong for the
14000 default LP64 mode, so we can't use the directives by default.
14001 Moreover, since gas's current behavior is at odds with gcc's
14002 default behavior, it seems unwise to rely on future versions
14003 of gas behaving the same way. We therefore avoid using .cfi
14004 directives for -mlong32 as well. */
14005 if (mips_abi == ABI_EABI && TARGET_64BIT)
14006 flag_dwarf2_cfi_asm = 0;
14008 mips_init_print_operand_punct ();
14010 /* Set up array to map GCC register number to debug register number.
14011 Ignore the special purpose register numbers. */
14013 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
14015 mips_dbx_regno[i] = INVALID_REGNUM;
14016 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
14017 mips_dwarf_regno[i] = i;
14019 mips_dwarf_regno[i] = INVALID_REGNUM;
14022 start = GP_DBX_FIRST - GP_REG_FIRST;
14023 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
14024 mips_dbx_regno[i] = i + start;
14026 start = FP_DBX_FIRST - FP_REG_FIRST;
14027 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
14028 mips_dbx_regno[i] = i + start;
14030 /* Accumulator debug registers use big-endian ordering. */
14031 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
14032 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
14033 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
14034 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
14035 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
14037 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
14038 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
14041 /* Set up mips_hard_regno_mode_ok. */
14042 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
14043 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
14044 mips_hard_regno_mode_ok[(int)mode][regno]
14045 = mips_hard_regno_mode_ok_p (regno, mode);
14047 /* Function to allocate machine-dependent function status. */
14048 init_machine_status = &mips_init_machine_status;
14050 /* Default to working around R4000 errata only if the processor
14051 was selected explicitly. */
14052 if ((target_flags_explicit & MASK_FIX_R4000) == 0
14053 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
14054 target_flags |= MASK_FIX_R4000;
14056 /* Default to working around R4400 errata only if the processor
14057 was selected explicitly. */
14058 if ((target_flags_explicit & MASK_FIX_R4400) == 0
14059 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
14060 target_flags |= MASK_FIX_R4400;
14062 /* Default to working around R10000 errata only if the processor
14063 was selected explicitly. */
14064 if ((target_flags_explicit & MASK_FIX_R10000) == 0
14065 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
14066 target_flags |= MASK_FIX_R10000;
14068 /* Make sure that branch-likely instructions available when using
14069 -mfix-r10000. The instructions are not available if either:
14071 1. -mno-branch-likely was passed.
14072 2. The selected ISA does not support branch-likely and
14073 the command line does not include -mbranch-likely. */
14074 if (TARGET_FIX_R10000
14075 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
14076 ? !ISA_HAS_BRANCHLIKELY
14077 : !TARGET_BRANCHLIKELY))
14078 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
14080 /* Save base state of options. */
14081 mips_base_target_flags = target_flags;
14082 mips_base_schedule_insns = flag_schedule_insns;
14083 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
14084 mips_base_move_loop_invariants = flag_move_loop_invariants;
14085 mips_base_align_loops = align_loops;
14086 mips_base_align_jumps = align_jumps;
14087 mips_base_align_functions = align_functions;
14089 /* Now select the ISA mode.
14091 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
14092 MIPS16 mode afterwards if need be. */
14093 mips_set_mips16_mode (false);
14096 /* Swap the register information for registers I and I + 1, which
14097 currently have the wrong endianness. Note that the registers'
14098 fixedness and call-clobberedness might have been set on the
14102 mips_swap_registers (unsigned int i)
14107 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
14108 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
14110 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
14111 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
14112 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
14113 SWAP_STRING (reg_names[i], reg_names[i + 1]);
14119 /* Implement CONDITIONAL_REGISTER_USAGE. */
14122 mips_conditional_register_usage (void)
14127 /* These DSP control register fields are global. */
14128 global_regs[CCDSP_PO_REGNUM] = 1;
14129 global_regs[CCDSP_SC_REGNUM] = 1;
14135 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
14136 fixed_regs[regno] = call_used_regs[regno] = 1;
14138 if (!TARGET_HARD_FLOAT)
14142 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
14143 fixed_regs[regno] = call_used_regs[regno] = 1;
14144 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
14145 fixed_regs[regno] = call_used_regs[regno] = 1;
14147 else if (! ISA_HAS_8CC)
14151 /* We only have a single condition-code register. We implement
14152 this by fixing all the condition-code registers and generating
14153 RTL that refers directly to ST_REG_FIRST. */
14154 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
14155 fixed_regs[regno] = call_used_regs[regno] = 1;
14157 /* In MIPS16 mode, we permit the $t temporary registers to be used
14158 for reload. We prohibit the unused $s registers, since they
14159 are call-saved, and saving them via a MIPS16 register would
14160 probably waste more time than just reloading the value. */
14163 fixed_regs[18] = call_used_regs[18] = 1;
14164 fixed_regs[19] = call_used_regs[19] = 1;
14165 fixed_regs[20] = call_used_regs[20] = 1;
14166 fixed_regs[21] = call_used_regs[21] = 1;
14167 fixed_regs[22] = call_used_regs[22] = 1;
14168 fixed_regs[23] = call_used_regs[23] = 1;
14169 fixed_regs[26] = call_used_regs[26] = 1;
14170 fixed_regs[27] = call_used_regs[27] = 1;
14171 fixed_regs[30] = call_used_regs[30] = 1;
14173 /* $f20-$f23 are call-clobbered for n64. */
14174 if (mips_abi == ABI_64)
14177 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
14178 call_really_used_regs[regno] = call_used_regs[regno] = 1;
14180 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
14182 if (mips_abi == ABI_N32)
14185 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
14186 call_really_used_regs[regno] = call_used_regs[regno] = 1;
14188 /* Make sure that double-register accumulator values are correctly
14189 ordered for the current endianness. */
14190 if (TARGET_LITTLE_ENDIAN)
14192 unsigned int regno;
14194 mips_swap_registers (MD_REG_FIRST);
14195 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
14196 mips_swap_registers (regno);
14200 /* Initialize vector TARGET to VALS. */
14203 mips_expand_vector_init (rtx target, rtx vals)
14205 enum machine_mode mode;
14206 enum machine_mode inner;
14207 unsigned int i, n_elts;
14210 mode = GET_MODE (target);
14211 inner = GET_MODE_INNER (mode);
14212 n_elts = GET_MODE_NUNITS (mode);
14214 gcc_assert (VECTOR_MODE_P (mode));
14216 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
14217 for (i = 0; i < n_elts; i++)
14218 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
14219 XVECEXP (vals, 0, i));
14221 emit_move_insn (target, mem);
14224 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
14225 other registers for instructions for which it is possible. This
14226 encourages the compiler to use CMP in cases where an XOR would
14227 require some register shuffling. */
14230 mips_order_regs_for_local_alloc (void)
14234 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
14235 reg_alloc_order[i] = i;
14239 /* It really doesn't matter where we put register 0, since it is
14240 a fixed register anyhow. */
14241 reg_alloc_order[0] = 24;
14242 reg_alloc_order[24] = 0;
14246 /* Initialize the GCC target structure. */
14247 #undef TARGET_ASM_ALIGNED_HI_OP
14248 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
14249 #undef TARGET_ASM_ALIGNED_SI_OP
14250 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
14251 #undef TARGET_ASM_ALIGNED_DI_OP
14252 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
14254 #undef TARGET_ASM_FUNCTION_PROLOGUE
14255 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
14256 #undef TARGET_ASM_FUNCTION_EPILOGUE
14257 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
14258 #undef TARGET_ASM_SELECT_RTX_SECTION
14259 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
14260 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
14261 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
14263 #undef TARGET_SCHED_INIT
14264 #define TARGET_SCHED_INIT mips_sched_init
14265 #undef TARGET_SCHED_REORDER
14266 #define TARGET_SCHED_REORDER mips_sched_reorder
14267 #undef TARGET_SCHED_REORDER2
14268 #define TARGET_SCHED_REORDER2 mips_sched_reorder
14269 #undef TARGET_SCHED_VARIABLE_ISSUE
14270 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
14271 #undef TARGET_SCHED_ADJUST_COST
14272 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
14273 #undef TARGET_SCHED_ISSUE_RATE
14274 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
14275 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
14276 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
14277 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
14278 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
14279 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14280 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14281 mips_multipass_dfa_lookahead
14283 #undef TARGET_DEFAULT_TARGET_FLAGS
14284 #define TARGET_DEFAULT_TARGET_FLAGS \
14286 | TARGET_CPU_DEFAULT \
14287 | TARGET_ENDIAN_DEFAULT \
14288 | TARGET_FP_EXCEPTIONS_DEFAULT \
14289 | MASK_CHECK_ZERO_DIV \
14291 #undef TARGET_HANDLE_OPTION
14292 #define TARGET_HANDLE_OPTION mips_handle_option
14294 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14295 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
14297 #undef TARGET_INSERT_ATTRIBUTES
14298 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
14299 #undef TARGET_MERGE_DECL_ATTRIBUTES
14300 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
14301 #undef TARGET_SET_CURRENT_FUNCTION
14302 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
14304 #undef TARGET_VALID_POINTER_MODE
14305 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
14306 #undef TARGET_RTX_COSTS
14307 #define TARGET_RTX_COSTS mips_rtx_costs
14308 #undef TARGET_ADDRESS_COST
14309 #define TARGET_ADDRESS_COST mips_address_cost
14311 #undef TARGET_IN_SMALL_DATA_P
14312 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
14314 #undef TARGET_MACHINE_DEPENDENT_REORG
14315 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
14317 #undef TARGET_ASM_FILE_START
14318 #define TARGET_ASM_FILE_START mips_file_start
14319 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
14320 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
14322 #undef TARGET_INIT_LIBFUNCS
14323 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
14325 #undef TARGET_BUILD_BUILTIN_VA_LIST
14326 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
14327 #undef TARGET_EXPAND_BUILTIN_VA_START
14328 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
14329 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14330 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
14332 #undef TARGET_PROMOTE_FUNCTION_ARGS
14333 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
14334 #undef TARGET_PROMOTE_FUNCTION_RETURN
14335 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
14336 #undef TARGET_PROMOTE_PROTOTYPES
14337 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
14339 #undef TARGET_RETURN_IN_MEMORY
14340 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
14341 #undef TARGET_RETURN_IN_MSB
14342 #define TARGET_RETURN_IN_MSB mips_return_in_msb
14344 #undef TARGET_ASM_OUTPUT_MI_THUNK
14345 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
14346 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14347 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
14349 #undef TARGET_SETUP_INCOMING_VARARGS
14350 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
14351 #undef TARGET_STRICT_ARGUMENT_NAMING
14352 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
14353 #undef TARGET_MUST_PASS_IN_STACK
14354 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14355 #undef TARGET_PASS_BY_REFERENCE
14356 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
14357 #undef TARGET_CALLEE_COPIES
14358 #define TARGET_CALLEE_COPIES mips_callee_copies
14359 #undef TARGET_ARG_PARTIAL_BYTES
14360 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
14362 #undef TARGET_MODE_REP_EXTENDED
14363 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
14365 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14366 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
14368 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14369 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
14371 #undef TARGET_INIT_BUILTINS
14372 #define TARGET_INIT_BUILTINS mips_init_builtins
14373 #undef TARGET_EXPAND_BUILTIN
14374 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
14376 #undef TARGET_HAVE_TLS
14377 #define TARGET_HAVE_TLS HAVE_AS_TLS
14379 #undef TARGET_CANNOT_FORCE_CONST_MEM
14380 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
14382 #undef TARGET_ENCODE_SECTION_INFO
14383 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
14385 #undef TARGET_ATTRIBUTE_TABLE
14386 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
14387 /* All our function attributes are related to how out-of-line copies should
14388 be compiled or called. They don't in themselves prevent inlining. */
14389 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
14390 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
14392 #undef TARGET_EXTRA_LIVE_ON_ENTRY
14393 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
14395 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14396 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
14397 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
14398 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
14400 #undef TARGET_COMP_TYPE_ATTRIBUTES
14401 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
14403 #ifdef HAVE_AS_DTPRELWORD
14404 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
14405 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
14407 #undef TARGET_DWARF_REGISTER_SPAN
14408 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
14410 #undef TARGET_IRA_COVER_CLASSES
14411 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
14413 struct gcc_target targetm = TARGET_INITIALIZER;
14415 #include "gt-mips.h"