1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
140 A signed 16-bit constant address.
143 A constant symbolic address. */
144 enum mips_address_type {
151 /* Enumerates the setting of the -mr10k-cache-barrier option. */
152 enum mips_r10k_cache_barrier_setting {
153 R10K_CACHE_BARRIER_NONE,
154 R10K_CACHE_BARRIER_STORE,
155 R10K_CACHE_BARRIER_LOAD_STORE
158 /* Macros to create an enumeration identifier for a function prototype. */
159 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
160 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
161 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
162 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
164 /* Classifies the prototype of a built-in function. */
165 enum mips_function_type {
166 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
167 #include "config/mips/mips-ftypes.def"
168 #undef DEF_MIPS_FTYPE
172 /* Specifies how a built-in function should be converted into rtl. */
173 enum mips_builtin_type {
174 /* The function corresponds directly to an .md pattern. The return
175 value is mapped to operand 0 and the arguments are mapped to
176 operands 1 and above. */
179 /* The function corresponds directly to an .md pattern. There is no return
180 value and the arguments are mapped to operands 0 and above. */
181 MIPS_BUILTIN_DIRECT_NO_TARGET,
183 /* The function corresponds to a comparison instruction followed by
184 a mips_cond_move_tf_ps pattern. The first two arguments are the
185 values to compare and the second two arguments are the vector
186 operands for the movt.ps or movf.ps instruction (in assembly order). */
190 /* The function corresponds to a V2SF comparison instruction. Operand 0
191 of this instruction is the result of the comparison, which has mode
192 CCV2 or CCV4. The function arguments are mapped to operands 1 and
193 above. The function's return value is an SImode boolean that is
194 true under the following conditions:
196 MIPS_BUILTIN_CMP_ANY: one of the registers is true
197 MIPS_BUILTIN_CMP_ALL: all of the registers are true
198 MIPS_BUILTIN_CMP_LOWER: the first register is true
199 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
200 MIPS_BUILTIN_CMP_ANY,
201 MIPS_BUILTIN_CMP_ALL,
202 MIPS_BUILTIN_CMP_UPPER,
203 MIPS_BUILTIN_CMP_LOWER,
205 /* As above, but the instruction only sets a single $fcc register. */
206 MIPS_BUILTIN_CMP_SINGLE,
208 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
209 MIPS_BUILTIN_BPOSGE32
212 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
213 #define MIPS_FP_CONDITIONS(MACRO) \
231 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
232 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
233 enum mips_fp_condition {
234 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
237 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
238 #define STRINGIFY(X) #X
239 static const char *const mips_fp_conditions[] = {
240 MIPS_FP_CONDITIONS (STRINGIFY)
243 /* Information about a function's frame layout. */
244 struct mips_frame_info GTY(()) {
245 /* The size of the frame in bytes. */
246 HOST_WIDE_INT total_size;
248 /* The number of bytes allocated to variables. */
249 HOST_WIDE_INT var_size;
251 /* The number of bytes allocated to outgoing function arguments. */
252 HOST_WIDE_INT args_size;
254 /* The number of bytes allocated to the .cprestore slot, or 0 if there
256 HOST_WIDE_INT cprestore_size;
258 /* Bit X is set if the function saves or restores GPR X. */
261 /* Likewise FPR X. */
264 /* The number of GPRs and FPRs saved. */
268 /* The offset of the topmost GPR and FPR save slots from the top of
269 the frame, or zero if no such slots are needed. */
270 HOST_WIDE_INT gp_save_offset;
271 HOST_WIDE_INT fp_save_offset;
273 /* Likewise, but giving offsets from the bottom of the frame. */
274 HOST_WIDE_INT gp_sp_offset;
275 HOST_WIDE_INT fp_sp_offset;
277 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
278 HOST_WIDE_INT arg_pointer_offset;
280 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
281 HOST_WIDE_INT hard_frame_pointer_offset;
284 struct machine_function GTY(()) {
285 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
286 rtx mips16_gp_pseudo_rtx;
288 /* The number of extra stack bytes taken up by register varargs.
289 This area is allocated by the callee at the very top of the frame. */
292 /* The current frame information, calculated by mips_compute_frame_info. */
293 struct mips_frame_info frame;
295 /* The register to use as the function's global pointer. */
296 unsigned int global_pointer;
298 /* True if mips_adjust_insn_length should ignore an instruction's
300 bool ignore_hazard_length_p;
302 /* True if the whole function is suitable for .set noreorder and
304 bool all_noreorder_p;
306 /* True if the function is known to have an instruction that needs $gp. */
309 /* True if we have emitted an instruction to initialize
310 mips16_gp_pseudo_rtx. */
311 bool initialized_mips16_gp_pseudo_p;
314 /* Information about a single argument. */
315 struct mips_arg_info {
316 /* True if the argument is passed in a floating-point register, or
317 would have been if we hadn't run out of registers. */
320 /* The number of words passed in registers, rounded up. */
321 unsigned int reg_words;
323 /* For EABI, the offset of the first register from GP_ARG_FIRST or
324 FP_ARG_FIRST. For other ABIs, the offset of the first register from
325 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
326 comment for details).
328 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
330 unsigned int reg_offset;
332 /* The number of words that must be passed on the stack, rounded up. */
333 unsigned int stack_words;
335 /* The offset from the start of the stack overflow area of the argument's
336 first stack word. Only meaningful when STACK_WORDS is nonzero. */
337 unsigned int stack_offset;
340 /* Information about an address described by mips_address_type.
346 REG is the base register and OFFSET is the constant offset.
349 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
350 is the type of symbol it references.
353 SYMBOL_TYPE is the type of symbol that the address references. */
354 struct mips_address_info {
355 enum mips_address_type type;
358 enum mips_symbol_type symbol_type;
361 /* One stage in a constant building sequence. These sequences have
365 A = A CODE[1] VALUE[1]
366 A = A CODE[2] VALUE[2]
369 where A is an accumulator, each CODE[i] is a binary rtl operation
370 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
371 struct mips_integer_op {
373 unsigned HOST_WIDE_INT value;
376 /* The largest number of operations needed to load an integer constant.
377 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
378 When the lowest bit is clear, we can try, but reject a sequence with
379 an extra SLL at the end. */
380 #define MIPS_MAX_INTEGER_OPS 7
382 /* Information about a MIPS16e SAVE or RESTORE instruction. */
383 struct mips16e_save_restore_info {
384 /* The number of argument registers saved by a SAVE instruction.
385 0 for RESTORE instructions. */
388 /* Bit X is set if the instruction saves or restores GPR X. */
391 /* The total number of bytes to allocate. */
395 /* Global variables for machine-dependent things. */
397 /* The -G setting, or the configuration's default small-data limit if
398 no -G option is given. */
399 static unsigned int mips_small_data_threshold;
401 /* The number of file directives written by mips_output_filename. */
402 int num_source_filenames;
404 /* The name that appeared in the last .file directive written by
405 mips_output_filename, or "" if mips_output_filename hasn't
406 written anything yet. */
407 const char *current_function_file = "";
409 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
412 /* Arrays that map GCC register numbers to debugger register numbers. */
413 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
414 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
416 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
421 /* True if we're writing out a branch-likely instruction rather than a
423 static bool mips_branch_likely;
425 /* The operands passed to the last cmpMM expander. */
428 /* The current instruction-set architecture. */
429 enum processor_type mips_arch;
430 const struct mips_cpu_info *mips_arch_info;
432 /* The processor that we should tune the code for. */
433 enum processor_type mips_tune;
434 const struct mips_cpu_info *mips_tune_info;
436 /* The ISA level associated with mips_arch. */
439 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
440 static const struct mips_cpu_info *mips_isa_option_info;
442 /* Which ABI to use. */
443 int mips_abi = MIPS_ABI_DEFAULT;
445 /* Which cost information to use. */
446 const struct mips_rtx_cost_data *mips_cost;
448 /* The ambient target flags, excluding MASK_MIPS16. */
449 static int mips_base_target_flags;
451 /* True if MIPS16 is the default mode. */
452 bool mips_base_mips16;
454 /* The ambient values of other global variables. */
455 static int mips_base_delayed_branch; /* flag_delayed_branch */
456 static int mips_base_schedule_insns; /* flag_schedule_insns */
457 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
458 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
459 static int mips_base_align_loops; /* align_loops */
460 static int mips_base_align_jumps; /* align_jumps */
461 static int mips_base_align_functions; /* align_functions */
463 /* The -mcode-readable setting. */
464 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
466 /* The -mr10k-cache-barrier setting. */
467 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
469 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
470 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
472 /* Index C is true if character C is a valid PRINT_OPERAND punctation
474 bool mips_print_operand_punct[256];
476 static GTY (()) int mips_output_filename_first_time = 1;
478 /* mips_split_p[X] is true if symbols of type X can be split by
479 mips_split_symbol. */
480 bool mips_split_p[NUM_SYMBOL_TYPES];
482 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
483 can be split by mips_split_symbol. */
484 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
486 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
487 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
488 if they are matched by a special .md file pattern. */
489 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
491 /* Likewise for HIGHs. */
492 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
494 /* Index R is the smallest register class that contains register R. */
495 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
496 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
497 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
498 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
499 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
500 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
501 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
502 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
503 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
504 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
505 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
506 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
507 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
508 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
509 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
510 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
511 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
512 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
513 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
514 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
515 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
516 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
517 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
518 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
519 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
520 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
521 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
522 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
523 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
524 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
525 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
526 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
527 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
528 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
529 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
530 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
531 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
532 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
533 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
534 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
535 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
536 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
537 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
538 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
539 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
540 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
541 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
542 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
545 /* The value of TARGET_ATTRIBUTE_TABLE. */
546 const struct attribute_spec mips_attribute_table[] = {
547 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
548 { "long_call", 0, 0, false, true, true, NULL },
549 { "far", 0, 0, false, true, true, NULL },
550 { "near", 0, 0, false, true, true, NULL },
551 /* We would really like to treat "mips16" and "nomips16" as type
552 attributes, but GCC doesn't provide the hooks we need to support
553 the right conversion rules. As declaration attributes, they affect
554 code generation but don't carry other semantics. */
555 { "mips16", 0, 0, true, false, false, NULL },
556 { "nomips16", 0, 0, true, false, false, NULL },
557 { NULL, 0, 0, false, false, false, NULL }
560 /* A table describing all the processors GCC knows about. Names are
561 matched in the order listed. The first mention of an ISA level is
562 taken as the canonical name for that ISA.
564 To ease comparison, please keep this table in the same order
565 as GAS's mips_cpu_info_table. Please also make sure that
566 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
567 options correctly. */
568 static const struct mips_cpu_info mips_cpu_info_table[] = {
569 /* Entries for generic ISAs. */
570 { "mips1", PROCESSOR_R3000, 1, 0 },
571 { "mips2", PROCESSOR_R6000, 2, 0 },
572 { "mips3", PROCESSOR_R4000, 3, 0 },
573 { "mips4", PROCESSOR_R8000, 4, 0 },
574 /* Prefer not to use branch-likely instructions for generic MIPS32rX
575 and MIPS64rX code. The instructions were officially deprecated
576 in revisions 2 and earlier, but revision 3 is likely to downgrade
577 that to a recommendation to avoid the instructions in code that
578 isn't tuned to a specific processor. */
579 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
580 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
581 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
582 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
583 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
585 /* MIPS I processors. */
586 { "r3000", PROCESSOR_R3000, 1, 0 },
587 { "r2000", PROCESSOR_R3000, 1, 0 },
588 { "r3900", PROCESSOR_R3900, 1, 0 },
590 /* MIPS II processors. */
591 { "r6000", PROCESSOR_R6000, 2, 0 },
593 /* MIPS III processors. */
594 { "r4000", PROCESSOR_R4000, 3, 0 },
595 { "vr4100", PROCESSOR_R4100, 3, 0 },
596 { "vr4111", PROCESSOR_R4111, 3, 0 },
597 { "vr4120", PROCESSOR_R4120, 3, 0 },
598 { "vr4130", PROCESSOR_R4130, 3, 0 },
599 { "vr4300", PROCESSOR_R4300, 3, 0 },
600 { "r4400", PROCESSOR_R4000, 3, 0 },
601 { "r4600", PROCESSOR_R4600, 3, 0 },
602 { "orion", PROCESSOR_R4600, 3, 0 },
603 { "r4650", PROCESSOR_R4650, 3, 0 },
604 /* ST Loongson 2E/2F processors. */
605 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
606 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
608 /* MIPS IV processors. */
609 { "r8000", PROCESSOR_R8000, 4, 0 },
610 { "vr5000", PROCESSOR_R5000, 4, 0 },
611 { "vr5400", PROCESSOR_R5400, 4, 0 },
612 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
613 { "rm7000", PROCESSOR_R7000, 4, 0 },
614 { "rm9000", PROCESSOR_R9000, 4, 0 },
616 /* MIPS32 processors. */
617 { "4kc", PROCESSOR_4KC, 32, 0 },
618 { "4km", PROCESSOR_4KC, 32, 0 },
619 { "4kp", PROCESSOR_4KP, 32, 0 },
620 { "4ksc", PROCESSOR_4KC, 32, 0 },
622 /* MIPS32 Release 2 processors. */
623 { "m4k", PROCESSOR_M4K, 33, 0 },
624 { "4kec", PROCESSOR_4KC, 33, 0 },
625 { "4kem", PROCESSOR_4KC, 33, 0 },
626 { "4kep", PROCESSOR_4KP, 33, 0 },
627 { "4ksd", PROCESSOR_4KC, 33, 0 },
629 { "24kc", PROCESSOR_24KC, 33, 0 },
630 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
631 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
632 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
633 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
634 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
636 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
637 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
638 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
639 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
640 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
641 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
643 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
644 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
645 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
646 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
647 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
648 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
650 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
651 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
652 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
653 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
654 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
655 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
656 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
658 /* MIPS64 processors. */
659 { "5kc", PROCESSOR_5KC, 64, 0 },
660 { "5kf", PROCESSOR_5KF, 64, 0 },
661 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
662 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
663 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
664 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
665 { "xlr", PROCESSOR_XLR, 64, 0 },
667 /* MIPS64 Release 2 processors. */
668 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
671 /* Default costs. If these are used for a processor we should look
672 up the actual costs. */
673 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
674 COSTS_N_INSNS (7), /* fp_mult_sf */ \
675 COSTS_N_INSNS (8), /* fp_mult_df */ \
676 COSTS_N_INSNS (23), /* fp_div_sf */ \
677 COSTS_N_INSNS (36), /* fp_div_df */ \
678 COSTS_N_INSNS (10), /* int_mult_si */ \
679 COSTS_N_INSNS (10), /* int_mult_di */ \
680 COSTS_N_INSNS (69), /* int_div_si */ \
681 COSTS_N_INSNS (69), /* int_div_di */ \
682 2, /* branch_cost */ \
683 4 /* memory_latency */
685 /* Floating-point costs for processors without an FPU. Just assume that
686 all floating-point libcalls are very expensive. */
687 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
688 COSTS_N_INSNS (256), /* fp_mult_sf */ \
689 COSTS_N_INSNS (256), /* fp_mult_df */ \
690 COSTS_N_INSNS (256), /* fp_div_sf */ \
691 COSTS_N_INSNS (256) /* fp_div_df */
693 /* Costs to use when optimizing for size. */
694 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
695 COSTS_N_INSNS (1), /* fp_add */
696 COSTS_N_INSNS (1), /* fp_mult_sf */
697 COSTS_N_INSNS (1), /* fp_mult_df */
698 COSTS_N_INSNS (1), /* fp_div_sf */
699 COSTS_N_INSNS (1), /* fp_div_df */
700 COSTS_N_INSNS (1), /* int_mult_si */
701 COSTS_N_INSNS (1), /* int_mult_di */
702 COSTS_N_INSNS (1), /* int_div_si */
703 COSTS_N_INSNS (1), /* int_div_di */
705 4 /* memory_latency */
708 /* Costs to use when optimizing for speed, indexed by processor. */
709 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
711 COSTS_N_INSNS (2), /* fp_add */
712 COSTS_N_INSNS (4), /* fp_mult_sf */
713 COSTS_N_INSNS (5), /* fp_mult_df */
714 COSTS_N_INSNS (12), /* fp_div_sf */
715 COSTS_N_INSNS (19), /* fp_div_df */
716 COSTS_N_INSNS (12), /* int_mult_si */
717 COSTS_N_INSNS (12), /* int_mult_di */
718 COSTS_N_INSNS (35), /* int_div_si */
719 COSTS_N_INSNS (35), /* int_div_di */
721 4 /* memory_latency */
725 COSTS_N_INSNS (6), /* int_mult_si */
726 COSTS_N_INSNS (6), /* int_mult_di */
727 COSTS_N_INSNS (36), /* int_div_si */
728 COSTS_N_INSNS (36), /* int_div_di */
730 4 /* memory_latency */
734 COSTS_N_INSNS (36), /* int_mult_si */
735 COSTS_N_INSNS (36), /* int_mult_di */
736 COSTS_N_INSNS (37), /* int_div_si */
737 COSTS_N_INSNS (37), /* int_div_di */
739 4 /* memory_latency */
743 COSTS_N_INSNS (4), /* int_mult_si */
744 COSTS_N_INSNS (11), /* int_mult_di */
745 COSTS_N_INSNS (36), /* int_div_si */
746 COSTS_N_INSNS (68), /* int_div_di */
748 4 /* memory_latency */
751 COSTS_N_INSNS (4), /* fp_add */
752 COSTS_N_INSNS (4), /* fp_mult_sf */
753 COSTS_N_INSNS (5), /* fp_mult_df */
754 COSTS_N_INSNS (17), /* fp_div_sf */
755 COSTS_N_INSNS (32), /* fp_div_df */
756 COSTS_N_INSNS (4), /* int_mult_si */
757 COSTS_N_INSNS (11), /* int_mult_di */
758 COSTS_N_INSNS (36), /* int_div_si */
759 COSTS_N_INSNS (68), /* int_div_di */
761 4 /* memory_latency */
764 COSTS_N_INSNS (4), /* fp_add */
765 COSTS_N_INSNS (4), /* fp_mult_sf */
766 COSTS_N_INSNS (5), /* fp_mult_df */
767 COSTS_N_INSNS (17), /* fp_div_sf */
768 COSTS_N_INSNS (32), /* fp_div_df */
769 COSTS_N_INSNS (4), /* int_mult_si */
770 COSTS_N_INSNS (7), /* int_mult_di */
771 COSTS_N_INSNS (42), /* int_div_si */
772 COSTS_N_INSNS (72), /* int_div_di */
774 4 /* memory_latency */
778 COSTS_N_INSNS (5), /* int_mult_si */
779 COSTS_N_INSNS (5), /* int_mult_di */
780 COSTS_N_INSNS (41), /* int_div_si */
781 COSTS_N_INSNS (41), /* int_div_di */
783 4 /* memory_latency */
786 COSTS_N_INSNS (8), /* fp_add */
787 COSTS_N_INSNS (8), /* fp_mult_sf */
788 COSTS_N_INSNS (10), /* fp_mult_df */
789 COSTS_N_INSNS (34), /* fp_div_sf */
790 COSTS_N_INSNS (64), /* fp_div_df */
791 COSTS_N_INSNS (5), /* int_mult_si */
792 COSTS_N_INSNS (5), /* int_mult_di */
793 COSTS_N_INSNS (41), /* int_div_si */
794 COSTS_N_INSNS (41), /* int_div_di */
796 4 /* memory_latency */
799 COSTS_N_INSNS (4), /* fp_add */
800 COSTS_N_INSNS (4), /* fp_mult_sf */
801 COSTS_N_INSNS (5), /* fp_mult_df */
802 COSTS_N_INSNS (17), /* fp_div_sf */
803 COSTS_N_INSNS (32), /* fp_div_df */
804 COSTS_N_INSNS (5), /* int_mult_si */
805 COSTS_N_INSNS (5), /* int_mult_di */
806 COSTS_N_INSNS (41), /* int_div_si */
807 COSTS_N_INSNS (41), /* int_div_di */
809 4 /* memory_latency */
813 COSTS_N_INSNS (5), /* int_mult_si */
814 COSTS_N_INSNS (5), /* int_mult_di */
815 COSTS_N_INSNS (41), /* int_div_si */
816 COSTS_N_INSNS (41), /* int_div_di */
818 4 /* memory_latency */
821 COSTS_N_INSNS (8), /* fp_add */
822 COSTS_N_INSNS (8), /* fp_mult_sf */
823 COSTS_N_INSNS (10), /* fp_mult_df */
824 COSTS_N_INSNS (34), /* fp_div_sf */
825 COSTS_N_INSNS (64), /* fp_div_df */
826 COSTS_N_INSNS (5), /* int_mult_si */
827 COSTS_N_INSNS (5), /* int_mult_di */
828 COSTS_N_INSNS (41), /* int_div_si */
829 COSTS_N_INSNS (41), /* int_div_di */
831 4 /* memory_latency */
834 COSTS_N_INSNS (4), /* fp_add */
835 COSTS_N_INSNS (4), /* fp_mult_sf */
836 COSTS_N_INSNS (5), /* fp_mult_df */
837 COSTS_N_INSNS (17), /* fp_div_sf */
838 COSTS_N_INSNS (32), /* fp_div_df */
839 COSTS_N_INSNS (5), /* int_mult_si */
840 COSTS_N_INSNS (5), /* int_mult_di */
841 COSTS_N_INSNS (41), /* int_div_si */
842 COSTS_N_INSNS (41), /* int_div_di */
844 4 /* memory_latency */
847 COSTS_N_INSNS (6), /* fp_add */
848 COSTS_N_INSNS (6), /* fp_mult_sf */
849 COSTS_N_INSNS (7), /* fp_mult_df */
850 COSTS_N_INSNS (25), /* fp_div_sf */
851 COSTS_N_INSNS (48), /* fp_div_df */
852 COSTS_N_INSNS (5), /* int_mult_si */
853 COSTS_N_INSNS (5), /* int_mult_di */
854 COSTS_N_INSNS (41), /* int_div_si */
855 COSTS_N_INSNS (41), /* int_div_di */
857 4 /* memory_latency */
871 COSTS_N_INSNS (5), /* int_mult_si */
872 COSTS_N_INSNS (5), /* int_mult_di */
873 COSTS_N_INSNS (72), /* int_div_si */
874 COSTS_N_INSNS (72), /* int_div_di */
876 4 /* memory_latency */
879 COSTS_N_INSNS (2), /* fp_add */
880 COSTS_N_INSNS (4), /* fp_mult_sf */
881 COSTS_N_INSNS (5), /* fp_mult_df */
882 COSTS_N_INSNS (12), /* fp_div_sf */
883 COSTS_N_INSNS (19), /* fp_div_df */
884 COSTS_N_INSNS (2), /* int_mult_si */
885 COSTS_N_INSNS (2), /* int_mult_di */
886 COSTS_N_INSNS (35), /* int_div_si */
887 COSTS_N_INSNS (35), /* int_div_di */
889 4 /* memory_latency */
892 COSTS_N_INSNS (3), /* fp_add */
893 COSTS_N_INSNS (5), /* fp_mult_sf */
894 COSTS_N_INSNS (6), /* fp_mult_df */
895 COSTS_N_INSNS (15), /* fp_div_sf */
896 COSTS_N_INSNS (16), /* fp_div_df */
897 COSTS_N_INSNS (17), /* int_mult_si */
898 COSTS_N_INSNS (17), /* int_mult_di */
899 COSTS_N_INSNS (38), /* int_div_si */
900 COSTS_N_INSNS (38), /* int_div_di */
902 6 /* memory_latency */
905 COSTS_N_INSNS (6), /* fp_add */
906 COSTS_N_INSNS (7), /* fp_mult_sf */
907 COSTS_N_INSNS (8), /* fp_mult_df */
908 COSTS_N_INSNS (23), /* fp_div_sf */
909 COSTS_N_INSNS (36), /* fp_div_df */
910 COSTS_N_INSNS (10), /* int_mult_si */
911 COSTS_N_INSNS (10), /* int_mult_di */
912 COSTS_N_INSNS (69), /* int_div_si */
913 COSTS_N_INSNS (69), /* int_div_di */
915 6 /* memory_latency */
927 /* The only costs that appear to be updated here are
928 integer multiplication. */
930 COSTS_N_INSNS (4), /* int_mult_si */
931 COSTS_N_INSNS (6), /* int_mult_di */
932 COSTS_N_INSNS (69), /* int_div_si */
933 COSTS_N_INSNS (69), /* int_div_di */
935 4 /* memory_latency */
947 COSTS_N_INSNS (6), /* fp_add */
948 COSTS_N_INSNS (4), /* fp_mult_sf */
949 COSTS_N_INSNS (5), /* fp_mult_df */
950 COSTS_N_INSNS (23), /* fp_div_sf */
951 COSTS_N_INSNS (36), /* fp_div_df */
952 COSTS_N_INSNS (5), /* int_mult_si */
953 COSTS_N_INSNS (5), /* int_mult_di */
954 COSTS_N_INSNS (36), /* int_div_si */
955 COSTS_N_INSNS (36), /* int_div_di */
957 4 /* memory_latency */
960 COSTS_N_INSNS (6), /* fp_add */
961 COSTS_N_INSNS (5), /* fp_mult_sf */
962 COSTS_N_INSNS (6), /* fp_mult_df */
963 COSTS_N_INSNS (30), /* fp_div_sf */
964 COSTS_N_INSNS (59), /* fp_div_df */
965 COSTS_N_INSNS (3), /* int_mult_si */
966 COSTS_N_INSNS (4), /* int_mult_di */
967 COSTS_N_INSNS (42), /* int_div_si */
968 COSTS_N_INSNS (74), /* int_div_di */
970 4 /* memory_latency */
973 COSTS_N_INSNS (6), /* fp_add */
974 COSTS_N_INSNS (5), /* fp_mult_sf */
975 COSTS_N_INSNS (6), /* fp_mult_df */
976 COSTS_N_INSNS (30), /* fp_div_sf */
977 COSTS_N_INSNS (59), /* fp_div_df */
978 COSTS_N_INSNS (5), /* int_mult_si */
979 COSTS_N_INSNS (9), /* int_mult_di */
980 COSTS_N_INSNS (42), /* int_div_si */
981 COSTS_N_INSNS (74), /* int_div_di */
983 4 /* memory_latency */
986 /* The only costs that are changed here are
987 integer multiplication. */
988 COSTS_N_INSNS (6), /* fp_add */
989 COSTS_N_INSNS (7), /* fp_mult_sf */
990 COSTS_N_INSNS (8), /* fp_mult_df */
991 COSTS_N_INSNS (23), /* fp_div_sf */
992 COSTS_N_INSNS (36), /* fp_div_df */
993 COSTS_N_INSNS (5), /* int_mult_si */
994 COSTS_N_INSNS (9), /* int_mult_di */
995 COSTS_N_INSNS (69), /* int_div_si */
996 COSTS_N_INSNS (69), /* int_div_di */
998 4 /* memory_latency */
1004 /* The only costs that are changed here are
1005 integer multiplication. */
1006 COSTS_N_INSNS (6), /* fp_add */
1007 COSTS_N_INSNS (7), /* fp_mult_sf */
1008 COSTS_N_INSNS (8), /* fp_mult_df */
1009 COSTS_N_INSNS (23), /* fp_div_sf */
1010 COSTS_N_INSNS (36), /* fp_div_df */
1011 COSTS_N_INSNS (3), /* int_mult_si */
1012 COSTS_N_INSNS (8), /* int_mult_di */
1013 COSTS_N_INSNS (69), /* int_div_si */
1014 COSTS_N_INSNS (69), /* int_div_di */
1015 1, /* branch_cost */
1016 4 /* memory_latency */
1019 /* These costs are the same as the SB-1A below. */
1020 COSTS_N_INSNS (4), /* fp_add */
1021 COSTS_N_INSNS (4), /* fp_mult_sf */
1022 COSTS_N_INSNS (4), /* fp_mult_df */
1023 COSTS_N_INSNS (24), /* fp_div_sf */
1024 COSTS_N_INSNS (32), /* fp_div_df */
1025 COSTS_N_INSNS (3), /* int_mult_si */
1026 COSTS_N_INSNS (4), /* int_mult_di */
1027 COSTS_N_INSNS (36), /* int_div_si */
1028 COSTS_N_INSNS (68), /* int_div_di */
1029 1, /* branch_cost */
1030 4 /* memory_latency */
1033 /* These costs are the same as the SB-1 above. */
1034 COSTS_N_INSNS (4), /* fp_add */
1035 COSTS_N_INSNS (4), /* fp_mult_sf */
1036 COSTS_N_INSNS (4), /* fp_mult_df */
1037 COSTS_N_INSNS (24), /* fp_div_sf */
1038 COSTS_N_INSNS (32), /* fp_div_df */
1039 COSTS_N_INSNS (3), /* int_mult_si */
1040 COSTS_N_INSNS (4), /* int_mult_di */
1041 COSTS_N_INSNS (36), /* int_div_si */
1042 COSTS_N_INSNS (68), /* int_div_di */
1043 1, /* branch_cost */
1044 4 /* memory_latency */
1050 /* Need to replace first five with the costs of calling the appropriate
1052 COSTS_N_INSNS (256), /* fp_add */
1053 COSTS_N_INSNS (256), /* fp_mult_sf */
1054 COSTS_N_INSNS (256), /* fp_mult_df */
1055 COSTS_N_INSNS (256), /* fp_div_sf */
1056 COSTS_N_INSNS (256), /* fp_div_df */
1057 COSTS_N_INSNS (8), /* int_mult_si */
1058 COSTS_N_INSNS (8), /* int_mult_di */
1059 COSTS_N_INSNS (72), /* int_div_si */
1060 COSTS_N_INSNS (72), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1066 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1067 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1068 struct mflip_mips16_entry GTY (()) {
1072 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1074 /* Hash table callbacks for mflip_mips16_htab. */
1077 mflip_mips16_htab_hash (const void *entry)
1079 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1083 mflip_mips16_htab_eq (const void *entry, const void *name)
1085 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1086 (const char *) name) == 0;
1089 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1090 mode, false if it should next add an attribute for the opposite mode. */
1091 static GTY(()) bool mips16_flipper;
1093 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1094 for -mflip-mips16. Return true if it should use "mips16" and false if
1095 it should use "nomips16". */
1098 mflip_mips16_use_mips16_p (tree decl)
1100 struct mflip_mips16_entry *entry;
1105 /* Use the opposite of the command-line setting for anonymous decls. */
1106 if (!DECL_NAME (decl))
1107 return !mips_base_mips16;
1109 if (!mflip_mips16_htab)
1110 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1111 mflip_mips16_htab_eq, NULL);
1113 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1114 hash = htab_hash_string (name);
1115 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1116 entry = (struct mflip_mips16_entry *) *slot;
1119 mips16_flipper = !mips16_flipper;
1120 entry = GGC_NEW (struct mflip_mips16_entry);
1122 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1125 return entry->mips16_p;
1128 /* Predicates to test for presence of "near" and "far"/"long_call"
1129 attributes on the given TYPE. */
1132 mips_near_type_p (const_tree type)
1134 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1138 mips_far_type_p (const_tree type)
1140 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1141 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1144 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1147 mips_mips16_decl_p (const_tree decl)
1149 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1153 mips_nomips16_decl_p (const_tree decl)
1155 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1158 /* Return true if function DECL is a MIPS16 function. Return the ambient
1159 setting if DECL is null. */
1162 mips_use_mips16_mode_p (tree decl)
1166 /* Nested functions must use the same frame pointer as their
1167 parent and must therefore use the same ISA mode. */
1168 tree parent = decl_function_context (decl);
1171 if (mips_mips16_decl_p (decl))
1173 if (mips_nomips16_decl_p (decl))
1176 return mips_base_mips16;
1179 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1182 mips_comp_type_attributes (const_tree type1, const_tree type2)
1184 /* Disallow mixed near/far attributes. */
1185 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1187 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1192 /* Implement TARGET_INSERT_ATTRIBUTES. */
1195 mips_insert_attributes (tree decl, tree *attributes)
1198 bool mips16_p, nomips16_p;
1200 /* Check for "mips16" and "nomips16" attributes. */
1201 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1202 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1203 if (TREE_CODE (decl) != FUNCTION_DECL)
1206 error ("%qs attribute only applies to functions", "mips16");
1208 error ("%qs attribute only applies to functions", "nomips16");
1212 mips16_p |= mips_mips16_decl_p (decl);
1213 nomips16_p |= mips_nomips16_decl_p (decl);
1214 if (mips16_p || nomips16_p)
1216 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1217 if (mips16_p && nomips16_p)
1218 error ("%qs cannot have both %<mips16%> and "
1219 "%<nomips16%> attributes",
1220 IDENTIFIER_POINTER (DECL_NAME (decl)));
1222 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1224 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1225 "mips16" attribute, arbitrarily pick one. We must pick the same
1226 setting for duplicate declarations of a function. */
1227 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1228 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1233 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1236 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1238 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1239 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1240 error ("%qs redeclared with conflicting %qs attributes",
1241 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1242 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1243 error ("%qs redeclared with conflicting %qs attributes",
1244 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1246 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1247 DECL_ATTRIBUTES (newdecl));
1250 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1251 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1254 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1256 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1258 *base_ptr = XEXP (x, 0);
1259 *offset_ptr = INTVAL (XEXP (x, 1));
1268 static unsigned int mips_build_integer (struct mips_integer_op *,
1269 unsigned HOST_WIDE_INT);
1271 /* A subroutine of mips_build_integer, with the same interface.
1272 Assume that the final action in the sequence should be a left shift. */
1275 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1277 unsigned int i, shift;
1279 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1280 since signed numbers are easier to load than unsigned ones. */
1282 while ((value & 1) == 0)
1283 value /= 2, shift++;
1285 i = mips_build_integer (codes, value);
1286 codes[i].code = ASHIFT;
1287 codes[i].value = shift;
1291 /* As for mips_build_shift, but assume that the final action will be
1292 an IOR or PLUS operation. */
1295 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1297 unsigned HOST_WIDE_INT high;
1300 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1301 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1303 /* The constant is too complex to load with a simple LUI/ORI pair,
1304 so we want to give the recursive call as many trailing zeros as
1305 possible. In this case, we know bit 16 is set and that the
1306 low 16 bits form a negative number. If we subtract that number
1307 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1308 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1309 codes[i].code = PLUS;
1310 codes[i].value = CONST_LOW_PART (value);
1314 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1315 bits gives a value with at least 17 trailing zeros. */
1316 i = mips_build_integer (codes, high);
1317 codes[i].code = IOR;
1318 codes[i].value = value & 0xffff;
1323 /* Fill CODES with a sequence of rtl operations to load VALUE.
1324 Return the number of operations needed. */
1327 mips_build_integer (struct mips_integer_op *codes,
1328 unsigned HOST_WIDE_INT value)
1330 if (SMALL_OPERAND (value)
1331 || SMALL_OPERAND_UNSIGNED (value)
1332 || LUI_OPERAND (value))
1334 /* The value can be loaded with a single instruction. */
1335 codes[0].code = UNKNOWN;
1336 codes[0].value = value;
1339 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1341 /* Either the constant is a simple LUI/ORI combination or its
1342 lowest bit is set. We don't want to shift in this case. */
1343 return mips_build_lower (codes, value);
1345 else if ((value & 0xffff) == 0)
1347 /* The constant will need at least three actions. The lowest
1348 16 bits are clear, so the final action will be a shift. */
1349 return mips_build_shift (codes, value);
1353 /* The final action could be a shift, add or inclusive OR.
1354 Rather than use a complex condition to select the best
1355 approach, try both mips_build_shift and mips_build_lower
1356 and pick the one that gives the shortest sequence.
1357 Note that this case is only used once per constant. */
1358 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1359 unsigned int cost, alt_cost;
1361 cost = mips_build_shift (codes, value);
1362 alt_cost = mips_build_lower (alt_codes, value);
1363 if (alt_cost < cost)
1365 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1372 /* Return true if symbols of type TYPE require a GOT access. */
1375 mips_got_symbol_type_p (enum mips_symbol_type type)
1379 case SYMBOL_GOT_PAGE_OFST:
1380 case SYMBOL_GOT_DISP:
1388 /* Return true if X is a thread-local symbol. */
1391 mips_tls_symbol_p (rtx x)
1393 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1396 /* Return true if SYMBOL_REF X is associated with a global symbol
1397 (in the STB_GLOBAL sense). */
1400 mips_global_symbol_p (const_rtx x)
1402 const_tree decl = SYMBOL_REF_DECL (x);
1405 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1407 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1408 or weak symbols. Relocations in the object file will be against
1409 the target symbol, so it's that symbol's binding that matters here. */
1410 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1413 /* Return true if function X is a libgcc MIPS16 stub function. */
1416 mips16_stub_function_p (const_rtx x)
1418 return (GET_CODE (x) == SYMBOL_REF
1419 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1422 /* Return true if function X is a locally-defined and locally-binding
1426 mips16_local_function_p (const_rtx x)
1428 return (GET_CODE (x) == SYMBOL_REF
1429 && SYMBOL_REF_LOCAL_P (x)
1430 && !SYMBOL_REF_EXTERNAL_P (x)
1431 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1434 /* Return true if SYMBOL_REF X binds locally. */
1437 mips_symbol_binds_local_p (const_rtx x)
1439 return (SYMBOL_REF_DECL (x)
1440 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1441 : SYMBOL_REF_LOCAL_P (x));
1444 /* Return true if rtx constants of mode MODE should be put into a small
1448 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1450 return (!TARGET_EMBEDDED_DATA
1451 && TARGET_LOCAL_SDATA
1452 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1455 /* Return true if X should not be moved directly into register $25.
1456 We need this because many versions of GAS will treat "la $25,foo" as
1457 part of a call sequence and so allow a global "foo" to be lazily bound. */
1460 mips_dangerous_for_la25_p (rtx x)
1462 return (!TARGET_EXPLICIT_RELOCS
1464 && GET_CODE (x) == SYMBOL_REF
1465 && mips_global_symbol_p (x));
1468 /* Return true if calls to X might need $25 to be valid on entry. */
1471 mips_use_pic_fn_addr_reg_p (const_rtx x)
1473 if (!TARGET_USE_PIC_FN_ADDR_REG)
1476 /* MIPS16 stub functions are guaranteed not to use $25. */
1477 if (mips16_stub_function_p (x))
1480 if (GET_CODE (x) == SYMBOL_REF)
1482 /* If PLTs and copy relocations are available, the static linker
1483 will make sure that $25 is valid on entry to the target function. */
1484 if (TARGET_ABICALLS_PIC0)
1487 /* Locally-defined functions use absolute accesses to set up
1488 the global pointer. */
1489 if (TARGET_ABSOLUTE_ABICALLS
1490 && mips_symbol_binds_local_p (x)
1491 && !SYMBOL_REF_EXTERNAL_P (x))
1498 /* Return the method that should be used to access SYMBOL_REF or
1499 LABEL_REF X in context CONTEXT. */
1501 static enum mips_symbol_type
1502 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1505 return SYMBOL_GOT_DISP;
1507 if (GET_CODE (x) == LABEL_REF)
1509 /* LABEL_REFs are used for jump tables as well as text labels.
1510 Only return SYMBOL_PC_RELATIVE if we know the label is in
1511 the text section. */
1512 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1513 return SYMBOL_PC_RELATIVE;
1515 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1516 return SYMBOL_GOT_PAGE_OFST;
1518 return SYMBOL_ABSOLUTE;
1521 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1523 if (SYMBOL_REF_TLS_MODEL (x))
1526 if (CONSTANT_POOL_ADDRESS_P (x))
1528 if (TARGET_MIPS16_TEXT_LOADS)
1529 return SYMBOL_PC_RELATIVE;
1531 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1532 return SYMBOL_PC_RELATIVE;
1534 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1535 return SYMBOL_GP_RELATIVE;
1538 /* Do not use small-data accesses for weak symbols; they may end up
1540 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1541 return SYMBOL_GP_RELATIVE;
1543 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1545 if (TARGET_ABICALLS_PIC2
1546 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1548 /* There are three cases to consider:
1550 - o32 PIC (either with or without explicit relocs)
1551 - n32/n64 PIC without explicit relocs
1552 - n32/n64 PIC with explicit relocs
1554 In the first case, both local and global accesses will use an
1555 R_MIPS_GOT16 relocation. We must correctly predict which of
1556 the two semantics (local or global) the assembler and linker
1557 will apply. The choice depends on the symbol's binding rather
1558 than its visibility.
1560 In the second case, the assembler will not use R_MIPS_GOT16
1561 relocations, but it chooses between local and global accesses
1562 in the same way as for o32 PIC.
1564 In the third case we have more freedom since both forms of
1565 access will work for any kind of symbol. However, there seems
1566 little point in doing things differently. */
1567 if (mips_global_symbol_p (x))
1568 return SYMBOL_GOT_DISP;
1570 return SYMBOL_GOT_PAGE_OFST;
1573 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1574 return SYMBOL_FORCE_TO_MEM;
1576 return SYMBOL_ABSOLUTE;
1579 /* Classify the base of symbolic expression X, given that X appears in
1582 static enum mips_symbol_type
1583 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1587 split_const (x, &x, &offset);
1588 if (UNSPEC_ADDRESS_P (x))
1589 return UNSPEC_ADDRESS_TYPE (x);
1591 return mips_classify_symbol (x, context);
1594 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1595 is the alignment in bytes of SYMBOL_REF X. */
1598 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1600 HOST_WIDE_INT align;
1602 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1603 return IN_RANGE (offset, 0, align - 1);
1606 /* Return true if X is a symbolic constant that can be used in context
1607 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1610 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1611 enum mips_symbol_type *symbol_type)
1615 split_const (x, &x, &offset);
1616 if (UNSPEC_ADDRESS_P (x))
1618 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1619 x = UNSPEC_ADDRESS (x);
1621 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1623 *symbol_type = mips_classify_symbol (x, context);
1624 if (*symbol_type == SYMBOL_TLS)
1630 if (offset == const0_rtx)
1633 /* Check whether a nonzero offset is valid for the underlying
1635 switch (*symbol_type)
1637 case SYMBOL_ABSOLUTE:
1638 case SYMBOL_FORCE_TO_MEM:
1639 case SYMBOL_32_HIGH:
1640 case SYMBOL_64_HIGH:
1643 /* If the target has 64-bit pointers and the object file only
1644 supports 32-bit symbols, the values of those symbols will be
1645 sign-extended. In this case we can't allow an arbitrary offset
1646 in case the 32-bit value X + OFFSET has a different sign from X. */
1647 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1648 return offset_within_block_p (x, INTVAL (offset));
1650 /* In other cases the relocations can handle any offset. */
1653 case SYMBOL_PC_RELATIVE:
1654 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1655 In this case, we no longer have access to the underlying constant,
1656 but the original symbol-based access was known to be valid. */
1657 if (GET_CODE (x) == LABEL_REF)
1662 case SYMBOL_GP_RELATIVE:
1663 /* Make sure that the offset refers to something within the
1664 same object block. This should guarantee that the final
1665 PC- or GP-relative offset is within the 16-bit limit. */
1666 return offset_within_block_p (x, INTVAL (offset));
1668 case SYMBOL_GOT_PAGE_OFST:
1669 case SYMBOL_GOTOFF_PAGE:
1670 /* If the symbol is global, the GOT entry will contain the symbol's
1671 address, and we will apply a 16-bit offset after loading it.
1672 If the symbol is local, the linker should provide enough local
1673 GOT entries for a 16-bit offset, but larger offsets may lead
1675 return SMALL_INT (offset);
1679 /* There is no carry between the HI and LO REL relocations, so the
1680 offset is only valid if we know it won't lead to such a carry. */
1681 return mips_offset_within_alignment_p (x, INTVAL (offset));
1683 case SYMBOL_GOT_DISP:
1684 case SYMBOL_GOTOFF_DISP:
1685 case SYMBOL_GOTOFF_CALL:
1686 case SYMBOL_GOTOFF_LOADGP:
1689 case SYMBOL_GOTTPREL:
1697 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1698 single instruction. We rely on the fact that, in the worst case,
1699 all instructions involved in a MIPS16 address calculation are usually
1703 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1707 case SYMBOL_ABSOLUTE:
1708 /* When using 64-bit symbols, we need 5 preparatory instructions,
1711 lui $at,%highest(symbol)
1712 daddiu $at,$at,%higher(symbol)
1714 daddiu $at,$at,%hi(symbol)
1717 The final address is then $at + %lo(symbol). With 32-bit
1718 symbols we just need a preparatory LUI for normal mode and
1719 a preparatory LI and SLL for MIPS16. */
1720 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1722 case SYMBOL_GP_RELATIVE:
1723 /* Treat GP-relative accesses as taking a single instruction on
1724 MIPS16 too; the copy of $gp can often be shared. */
1727 case SYMBOL_PC_RELATIVE:
1728 /* PC-relative constants can be only be used with ADDIUPC,
1729 DADDIUPC, LWPC and LDPC. */
1730 if (mode == MAX_MACHINE_MODE
1731 || GET_MODE_SIZE (mode) == 4
1732 || GET_MODE_SIZE (mode) == 8)
1735 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1738 case SYMBOL_FORCE_TO_MEM:
1739 /* LEAs will be converted into constant-pool references by
1741 if (mode == MAX_MACHINE_MODE)
1744 /* The constant must be loaded and then dereferenced. */
1747 case SYMBOL_GOT_DISP:
1748 /* The constant will have to be loaded from the GOT before it
1749 is used in an address. */
1750 if (mode != MAX_MACHINE_MODE)
1755 case SYMBOL_GOT_PAGE_OFST:
1756 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1757 local/global classification is accurate. The worst cases are:
1759 (1) For local symbols when generating o32 or o64 code. The assembler
1765 ...and the final address will be $at + %lo(symbol).
1767 (2) For global symbols when -mxgot. The assembler will use:
1769 lui $at,%got_hi(symbol)
1772 ...and the final address will be $at + %got_lo(symbol). */
1775 case SYMBOL_GOTOFF_PAGE:
1776 case SYMBOL_GOTOFF_DISP:
1777 case SYMBOL_GOTOFF_CALL:
1778 case SYMBOL_GOTOFF_LOADGP:
1779 case SYMBOL_32_HIGH:
1780 case SYMBOL_64_HIGH:
1786 case SYMBOL_GOTTPREL:
1789 /* A 16-bit constant formed by a single relocation, or a 32-bit
1790 constant formed from a high 16-bit relocation and a low 16-bit
1791 relocation. Use mips_split_p to determine which. 32-bit
1792 constants need an "lui; addiu" sequence for normal mode and
1793 an "li; sll; addiu" sequence for MIPS16 mode. */
1794 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1797 /* We don't treat a bare TLS symbol as a constant. */
1803 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1804 to load symbols of type TYPE into a register. Return 0 if the given
1805 type of symbol cannot be used as an immediate operand.
1807 Otherwise, return the number of instructions needed to load or store
1808 values of mode MODE to or from addresses of type TYPE. Return 0 if
1809 the given type of symbol is not valid in addresses.
1811 In both cases, treat extended MIPS16 instructions as two instructions. */
1814 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1816 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1819 /* A for_each_rtx callback. Stop the search if *X references a
1820 thread-local symbol. */
1823 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1825 return mips_tls_symbol_p (*x);
1828 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1831 mips_cannot_force_const_mem (rtx x)
1833 enum mips_symbol_type type;
1836 /* There is no assembler syntax for expressing an address-sized
1838 if (GET_CODE (x) == HIGH)
1841 /* As an optimization, reject constants that mips_legitimize_move
1844 Suppose we have a multi-instruction sequence that loads constant C
1845 into register R. If R does not get allocated a hard register, and
1846 R is used in an operand that allows both registers and memory
1847 references, reload will consider forcing C into memory and using
1848 one of the instruction's memory alternatives. Returning false
1849 here will force it to use an input reload instead. */
1850 if (GET_CODE (x) == CONST_INT && LEGITIMATE_CONSTANT_P (x))
1853 split_const (x, &base, &offset);
1854 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1855 && type != SYMBOL_FORCE_TO_MEM)
1857 /* The same optimization as for CONST_INT. */
1858 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1861 /* If MIPS16 constant pools live in the text section, they should
1862 not refer to anything that might need run-time relocation. */
1863 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1867 /* TLS symbols must be computed by mips_legitimize_move. */
1868 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1874 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1875 constants when we're using a per-function constant pool. */
1878 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1879 const_rtx x ATTRIBUTE_UNUSED)
1881 return !TARGET_MIPS16_PCREL_LOADS;
1884 /* Return true if register REGNO is a valid base register for mode MODE.
1885 STRICT_P is true if REG_OK_STRICT is in effect. */
1888 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1891 if (!HARD_REGISTER_NUM_P (regno))
1895 regno = reg_renumber[regno];
1898 /* These fake registers will be eliminated to either the stack or
1899 hard frame pointer, both of which are usually valid base registers.
1900 Reload deals with the cases where the eliminated form isn't valid. */
1901 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1904 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1905 values, nothing smaller. There are two problems here:
1907 (a) Instantiating virtual registers can introduce new uses of the
1908 stack pointer. If these virtual registers are valid addresses,
1909 the stack pointer should be too.
1911 (b) Most uses of the stack pointer are not made explicit until
1912 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1913 We don't know until that stage whether we'll be eliminating to the
1914 stack pointer (which needs the restriction) or the hard frame
1915 pointer (which doesn't).
1917 All in all, it seems more consistent to only enforce this restriction
1918 during and after reload. */
1919 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1920 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1922 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1925 /* Return true if X is a valid base register for mode MODE.
1926 STRICT_P is true if REG_OK_STRICT is in effect. */
1929 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1931 if (!strict_p && GET_CODE (x) == SUBREG)
1935 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
1938 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1939 can address a value of mode MODE. */
1942 mips_valid_offset_p (rtx x, enum machine_mode mode)
1944 /* Check that X is a signed 16-bit number. */
1945 if (!const_arith_operand (x, Pmode))
1948 /* We may need to split multiword moves, so make sure that every word
1950 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1951 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
1957 /* Return true if a LO_SUM can address a value of mode MODE when the
1958 LO_SUM symbol has type SYMBOL_TYPE. */
1961 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
1963 /* Check that symbols of type SYMBOL_TYPE can be used to access values
1965 if (mips_symbol_insns (symbol_type, mode) == 0)
1968 /* Check that there is a known low-part relocation. */
1969 if (mips_lo_relocs[symbol_type] == NULL)
1972 /* We may need to split multiword moves, so make sure that each word
1973 can be accessed without inducing a carry. This is mainly needed
1974 for o64, which has historically only guaranteed 64-bit alignment
1975 for 128-bit types. */
1976 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1977 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
1983 /* Return true if X is a valid address for machine mode MODE. If it is,
1984 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
1988 mips_classify_address (struct mips_address_info *info, rtx x,
1989 enum machine_mode mode, bool strict_p)
1991 switch (GET_CODE (x))
1995 info->type = ADDRESS_REG;
1997 info->offset = const0_rtx;
1998 return mips_valid_base_register_p (info->reg, mode, strict_p);
2001 info->type = ADDRESS_REG;
2002 info->reg = XEXP (x, 0);
2003 info->offset = XEXP (x, 1);
2004 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2005 && mips_valid_offset_p (info->offset, mode));
2008 info->type = ADDRESS_LO_SUM;
2009 info->reg = XEXP (x, 0);
2010 info->offset = XEXP (x, 1);
2011 /* We have to trust the creator of the LO_SUM to do something vaguely
2012 sane. Target-independent code that creates a LO_SUM should also
2013 create and verify the matching HIGH. Target-independent code that
2014 adds an offset to a LO_SUM must prove that the offset will not
2015 induce a carry. Failure to do either of these things would be
2016 a bug, and we are not required to check for it here. The MIPS
2017 backend itself should only create LO_SUMs for valid symbolic
2018 constants, with the high part being either a HIGH or a copy
2021 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2022 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2023 && mips_valid_lo_sum_p (info->symbol_type, mode));
2026 /* Small-integer addresses don't occur very often, but they
2027 are legitimate if $0 is a valid base register. */
2028 info->type = ADDRESS_CONST_INT;
2029 return !TARGET_MIPS16 && SMALL_INT (x);
2034 info->type = ADDRESS_SYMBOLIC;
2035 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2037 && mips_symbol_insns (info->symbol_type, mode) > 0
2038 && !mips_split_p[info->symbol_type]);
2045 /* Return true if X is a legitimate address for a memory operand of mode
2046 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
2049 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2051 struct mips_address_info addr;
2053 return mips_classify_address (&addr, x, mode, strict_p);
2056 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2059 mips_stack_address_p (rtx x, enum machine_mode mode)
2061 struct mips_address_info addr;
2063 return (mips_classify_address (&addr, x, mode, false)
2064 && addr.type == ADDRESS_REG
2065 && addr.reg == stack_pointer_rtx);
2068 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2069 address instruction. Note that such addresses are not considered
2070 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
2071 is so restricted. */
2074 mips_lwxs_address_p (rtx addr)
2077 && GET_CODE (addr) == PLUS
2078 && REG_P (XEXP (addr, 1)))
2080 rtx offset = XEXP (addr, 0);
2081 if (GET_CODE (offset) == MULT
2082 && REG_P (XEXP (offset, 0))
2083 && GET_CODE (XEXP (offset, 1)) == CONST_INT
2084 && INTVAL (XEXP (offset, 1)) == 4)
2090 /* Return true if a value at OFFSET bytes from base register BASE can be
2091 accessed using an unextended MIPS16 instruction. MODE is the mode of
2094 Usually the offset in an unextended instruction is a 5-bit field.
2095 The offset is unsigned and shifted left once for LH and SH, twice
2096 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2097 an 8-bit immediate field that's shifted left twice. */
2100 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2101 unsigned HOST_WIDE_INT offset)
2103 if (offset % GET_MODE_SIZE (mode) == 0)
2105 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2106 return offset < 256U * GET_MODE_SIZE (mode);
2107 return offset < 32U * GET_MODE_SIZE (mode);
2112 /* Return the number of instructions needed to load or store a value
2113 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2114 Assume that multiword moves may need to be split into word moves
2115 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2118 For MIPS16 code, count extended instructions as two instructions. */
2121 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2123 struct mips_address_info addr;
2126 /* BLKmode is used for single unaligned loads and stores and should
2127 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2128 meaningless, so we have to single it out as a special case one way
2130 if (mode != BLKmode && might_split_p)
2131 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2135 if (mips_classify_address (&addr, x, mode, false))
2140 && !mips16_unextended_reference_p (mode, addr.reg,
2141 UINTVAL (addr.offset)))
2145 case ADDRESS_LO_SUM:
2146 return TARGET_MIPS16 ? factor * 2 : factor;
2148 case ADDRESS_CONST_INT:
2151 case ADDRESS_SYMBOLIC:
2152 return factor * mips_symbol_insns (addr.symbol_type, mode);
2157 /* Return the number of instructions needed to load constant X.
2158 Return 0 if X isn't a valid constant. */
2161 mips_const_insns (rtx x)
2163 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2164 enum mips_symbol_type symbol_type;
2167 switch (GET_CODE (x))
2170 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2172 || !mips_split_p[symbol_type])
2175 /* This is simply an LUI for normal mode. It is an extended
2176 LI followed by an extended SLL for MIPS16. */
2177 return TARGET_MIPS16 ? 4 : 1;
2181 /* Unsigned 8-bit constants can be loaded using an unextended
2182 LI instruction. Unsigned 16-bit constants can be loaded
2183 using an extended LI. Negative constants must be loaded
2184 using LI and then negated. */
2185 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2186 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2187 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2188 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2191 return mips_build_integer (codes, INTVAL (x));
2195 /* Allow zeros for normal mode, where we can use $0. */
2196 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2202 /* See if we can refer to X directly. */
2203 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2204 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2206 /* Otherwise try splitting the constant into a base and offset.
2207 If the offset is a 16-bit value, we can load the base address
2208 into a register and then use (D)ADDIU to add in the offset.
2209 If the offset is larger, we can load the base and offset
2210 into separate registers and add them together with (D)ADDU.
2211 However, the latter is only possible before reload; during
2212 and after reload, we must have the option of forcing the
2213 constant into the pool instead. */
2214 split_const (x, &x, &offset);
2217 int n = mips_const_insns (x);
2220 if (SMALL_INT (offset))
2222 else if (!targetm.cannot_force_const_mem (x))
2223 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2230 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2238 /* X is a doubleword constant that can be handled by splitting it into
2239 two words and loading each word separately. Return the number of
2240 instructions required to do this. */
2243 mips_split_const_insns (rtx x)
2245 unsigned int low, high;
2247 low = mips_const_insns (mips_subword (x, false));
2248 high = mips_const_insns (mips_subword (x, true));
2249 gcc_assert (low > 0 && high > 0);
2253 /* Return the number of instructions needed to implement INSN,
2254 given that it loads from or stores to MEM. Count extended
2255 MIPS16 instructions as two instructions. */
2258 mips_load_store_insns (rtx mem, rtx insn)
2260 enum machine_mode mode;
2264 gcc_assert (MEM_P (mem));
2265 mode = GET_MODE (mem);
2267 /* Try to prove that INSN does not need to be split. */
2268 might_split_p = true;
2269 if (GET_MODE_BITSIZE (mode) == 64)
2271 set = single_set (insn);
2272 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2273 might_split_p = false;
2276 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2279 /* Return the number of instructions needed for an integer division. */
2282 mips_idiv_insns (void)
2287 if (TARGET_CHECK_ZERO_DIV)
2289 if (GENERATE_DIVIDE_TRAPS)
2295 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2300 /* Emit a move from SRC to DEST. Assume that the move expanders can
2301 handle all moves if !can_create_pseudo_p (). The distinction is
2302 important because, unlike emit_move_insn, the move expanders know
2303 how to force Pmode objects into the constant pool even when the
2304 constant pool address is not itself legitimate. */
2307 mips_emit_move (rtx dest, rtx src)
2309 return (can_create_pseudo_p ()
2310 ? emit_move_insn (dest, src)
2311 : emit_move_insn_1 (dest, src));
2314 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2317 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2319 emit_insn (gen_rtx_SET (VOIDmode, target,
2320 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2323 /* Compute (CODE OP0 OP1) and store the result in a new register
2324 of mode MODE. Return that new register. */
2327 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2331 reg = gen_reg_rtx (mode);
2332 mips_emit_binary (code, reg, op0, op1);
2336 /* Copy VALUE to a register and return that register. If new pseudos
2337 are allowed, copy it into a new register, otherwise use DEST. */
2340 mips_force_temporary (rtx dest, rtx value)
2342 if (can_create_pseudo_p ())
2343 return force_reg (Pmode, value);
2346 mips_emit_move (dest, value);
2351 /* Emit a call sequence with call pattern PATTERN and return the call
2352 instruction itself (which is not necessarily the last instruction
2353 emitted). ORIG_ADDR is the original, unlegitimized address,
2354 ADDR is the legitimized form, and LAZY_P is true if the call
2355 address is lazily-bound. */
2358 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2362 insn = emit_call_insn (pattern);
2364 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2366 /* MIPS16 JALRs only take MIPS16 registers. If the target
2367 function requires $25 to be valid on entry, we must copy it
2368 there separately. The move instruction can be put in the
2369 call's delay slot. */
2370 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2371 emit_insn_before (gen_move_insn (reg, addr), insn);
2372 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2376 /* Lazy-binding stubs require $gp to be valid on entry. */
2377 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2381 /* See the comment above load_call<mode> for details. */
2382 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2383 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2384 emit_insn (gen_update_got_version ());
2389 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2390 then add CONST_INT OFFSET to the result. */
2393 mips_unspec_address_offset (rtx base, rtx offset,
2394 enum mips_symbol_type symbol_type)
2396 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2397 UNSPEC_ADDRESS_FIRST + symbol_type);
2398 if (offset != const0_rtx)
2399 base = gen_rtx_PLUS (Pmode, base, offset);
2400 return gen_rtx_CONST (Pmode, base);
2403 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2404 type SYMBOL_TYPE. */
2407 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2411 split_const (address, &base, &offset);
2412 return mips_unspec_address_offset (base, offset, symbol_type);
2415 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2416 high part to BASE and return the result. Just return BASE otherwise.
2417 TEMP is as for mips_force_temporary.
2419 The returned expression can be used as the first operand to a LO_SUM. */
2422 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2423 enum mips_symbol_type symbol_type)
2425 if (mips_split_p[symbol_type])
2427 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2428 addr = mips_force_temporary (temp, addr);
2429 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2434 /* Return an instruction that copies $gp into register REG. We want
2435 GCC to treat the register's value as constant, so that its value
2436 can be rematerialized on demand. */
2439 gen_load_const_gp (rtx reg)
2441 return (Pmode == SImode
2442 ? gen_load_const_gp_si (reg)
2443 : gen_load_const_gp_di (reg));
2446 /* Return a pseudo register that contains the value of $gp throughout
2447 the current function. Such registers are needed by MIPS16 functions,
2448 for which $gp itself is not a valid base register or addition operand. */
2451 mips16_gp_pseudo_reg (void)
2453 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2454 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2456 /* Don't emit an instruction to initialize the pseudo register if
2457 we are being called from the tree optimizers' cost-calculation
2459 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2460 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2464 push_topmost_sequence ();
2466 scan = get_insns ();
2467 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2468 scan = NEXT_INSN (scan);
2470 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2471 emit_insn_after (insn, scan);
2473 pop_topmost_sequence ();
2475 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2478 return cfun->machine->mips16_gp_pseudo_rtx;
2481 /* Return a base register that holds pic_offset_table_rtx.
2482 TEMP, if nonnull, is a scratch Pmode base register. */
2485 mips_pic_base_register (rtx temp)
2488 return pic_offset_table_rtx;
2490 if (can_create_pseudo_p ())
2491 return mips16_gp_pseudo_reg ();
2494 /* The first post-reload split exposes all references to $gp
2495 (both uses and definitions). All references must remain
2496 explicit after that point.
2498 It is safe to introduce uses of $gp at any time, so for
2499 simplicity, we do that before the split too. */
2500 mips_emit_move (temp, pic_offset_table_rtx);
2502 emit_insn (gen_load_const_gp (temp));
2506 /* Create and return a GOT reference of type TYPE for address ADDR.
2507 TEMP, if nonnull, is a scratch Pmode base register. */
2510 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2512 rtx base, high, lo_sum_symbol;
2514 base = mips_pic_base_register (temp);
2516 /* If we used the temporary register to load $gp, we can't use
2517 it for the high part as well. */
2518 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2521 high = mips_unspec_offset_high (temp, base, addr, type);
2522 lo_sum_symbol = mips_unspec_address (addr, type);
2524 if (type == SYMBOL_GOTOFF_CALL)
2525 return (Pmode == SImode
2526 ? gen_unspec_callsi (high, lo_sum_symbol)
2527 : gen_unspec_calldi (high, lo_sum_symbol));
2529 return (Pmode == SImode
2530 ? gen_unspec_gotsi (high, lo_sum_symbol)
2531 : gen_unspec_gotdi (high, lo_sum_symbol));
2534 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2535 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2536 constant in that context and can be split into high and low parts.
2537 If so, and if LOW_OUT is nonnull, emit the high part and store the
2538 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2540 TEMP is as for mips_force_temporary and is used to load the high
2541 part into a register.
2543 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2544 a legitimize SET_SRC for an .md pattern, otherwise the low part
2545 is guaranteed to be a legitimate address for mode MODE. */
2548 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2550 enum mips_symbol_context context;
2551 enum mips_symbol_type symbol_type;
2554 context = (mode == MAX_MACHINE_MODE
2555 ? SYMBOL_CONTEXT_LEA
2556 : SYMBOL_CONTEXT_MEM);
2557 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2559 addr = XEXP (addr, 0);
2560 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2561 && mips_symbol_insns (symbol_type, mode) > 0
2562 && mips_split_hi_p[symbol_type])
2565 switch (symbol_type)
2567 case SYMBOL_GOT_PAGE_OFST:
2568 /* The high part of a page/ofst pair is loaded from the GOT. */
2569 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2580 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2581 && mips_symbol_insns (symbol_type, mode) > 0
2582 && mips_split_p[symbol_type])
2585 switch (symbol_type)
2587 case SYMBOL_GOT_DISP:
2588 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2589 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2592 case SYMBOL_GP_RELATIVE:
2593 high = mips_pic_base_register (temp);
2594 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2598 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2599 high = mips_force_temporary (temp, high);
2600 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2609 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2610 mips_force_temporary; it is only needed when OFFSET is not a
2614 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2616 if (!SMALL_OPERAND (offset))
2622 /* Load the full offset into a register so that we can use
2623 an unextended instruction for the address itself. */
2624 high = GEN_INT (offset);
2629 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2630 high = GEN_INT (CONST_HIGH_PART (offset));
2631 offset = CONST_LOW_PART (offset);
2633 high = mips_force_temporary (temp, high);
2634 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2636 return plus_constant (reg, offset);
2639 /* The __tls_get_attr symbol. */
2640 static GTY(()) rtx mips_tls_symbol;
2642 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2643 the TLS symbol we are referencing and TYPE is the symbol type to use
2644 (either global dynamic or local dynamic). V0 is an RTX for the
2645 return value location. */
2648 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2652 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2654 if (!mips_tls_symbol)
2655 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2657 loc = mips_unspec_address (sym, type);
2661 emit_insn (gen_rtx_SET (Pmode, a0,
2662 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2663 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2664 const0_rtx, NULL_RTX, false);
2665 RTL_CONST_CALL_P (insn) = 1;
2666 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2667 insn = get_insns ();
2674 /* Return a pseudo register that contains the current thread pointer. */
2681 tp = gen_reg_rtx (Pmode);
2682 if (Pmode == DImode)
2683 emit_insn (gen_tls_get_tp_di (tp));
2685 emit_insn (gen_tls_get_tp_si (tp));
2689 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2690 its address. The return value will be both a valid address and a valid
2691 SET_SRC (either a REG or a LO_SUM). */
2694 mips_legitimize_tls_address (rtx loc)
2696 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2697 enum tls_model model;
2701 sorry ("MIPS16 TLS");
2702 return gen_reg_rtx (Pmode);
2705 model = SYMBOL_REF_TLS_MODEL (loc);
2706 /* Only TARGET_ABICALLS code can have more than one module; other
2707 code must be be static and should not use a GOT. All TLS models
2708 reduce to local exec in this situation. */
2709 if (!TARGET_ABICALLS)
2710 model = TLS_MODEL_LOCAL_EXEC;
2714 case TLS_MODEL_GLOBAL_DYNAMIC:
2715 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2716 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2717 dest = gen_reg_rtx (Pmode);
2718 emit_libcall_block (insn, dest, v0, loc);
2721 case TLS_MODEL_LOCAL_DYNAMIC:
2722 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2723 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2724 tmp1 = gen_reg_rtx (Pmode);
2726 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2727 share the LDM result with other LD model accesses. */
2728 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2730 emit_libcall_block (insn, tmp1, v0, eqv);
2732 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2733 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2734 mips_unspec_address (loc, SYMBOL_DTPREL));
2737 case TLS_MODEL_INITIAL_EXEC:
2738 tp = mips_get_tp ();
2739 tmp1 = gen_reg_rtx (Pmode);
2740 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2741 if (Pmode == DImode)
2742 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2744 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2745 dest = gen_reg_rtx (Pmode);
2746 emit_insn (gen_add3_insn (dest, tmp1, tp));
2749 case TLS_MODEL_LOCAL_EXEC:
2750 tp = mips_get_tp ();
2751 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2752 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2753 mips_unspec_address (loc, SYMBOL_TPREL));
2762 /* If X is not a valid address for mode MODE, force it into a register. */
2765 mips_force_address (rtx x, enum machine_mode mode)
2767 if (!mips_legitimate_address_p (mode, x, false))
2768 x = force_reg (Pmode, x);
2772 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2773 be legitimized in a way that the generic machinery might not expect,
2774 put the new address in *XLOC and return true. MODE is the mode of
2775 the memory being accessed. */
2778 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2781 HOST_WIDE_INT offset;
2783 if (mips_tls_symbol_p (*xloc))
2785 *xloc = mips_legitimize_tls_address (*xloc);
2789 /* See if the address can split into a high part and a LO_SUM. */
2790 if (mips_split_symbol (NULL, *xloc, mode, &addr))
2792 *xloc = mips_force_address (addr, mode);
2796 /* Handle BASE + OFFSET using mips_add_offset. */
2797 mips_split_plus (*xloc, &base, &offset);
2800 if (!mips_valid_base_register_p (base, mode, false))
2801 base = copy_to_mode_reg (Pmode, base);
2802 addr = mips_add_offset (NULL, base, offset);
2803 *xloc = mips_force_address (addr, mode);
2809 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2812 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2814 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2815 enum machine_mode mode;
2816 unsigned int i, num_ops;
2819 mode = GET_MODE (dest);
2820 num_ops = mips_build_integer (codes, value);
2822 /* Apply each binary operation to X. Invariant: X is a legitimate
2823 source operand for a SET pattern. */
2824 x = GEN_INT (codes[0].value);
2825 for (i = 1; i < num_ops; i++)
2827 if (!can_create_pseudo_p ())
2829 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2833 x = force_reg (mode, x);
2834 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2837 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2840 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2841 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2845 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2849 /* Split moves of big integers into smaller pieces. */
2850 if (splittable_const_int_operand (src, mode))
2852 mips_move_integer (dest, dest, INTVAL (src));
2856 /* Split moves of symbolic constants into high/low pairs. */
2857 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2859 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2863 /* Generate the appropriate access sequences for TLS symbols. */
2864 if (mips_tls_symbol_p (src))
2866 mips_emit_move (dest, mips_legitimize_tls_address (src));
2870 /* If we have (const (plus symbol offset)), and that expression cannot
2871 be forced into memory, load the symbol first and add in the offset.
2872 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2873 forced into memory, as it usually produces better code. */
2874 split_const (src, &base, &offset);
2875 if (offset != const0_rtx
2876 && (targetm.cannot_force_const_mem (src)
2877 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2879 base = mips_force_temporary (dest, base);
2880 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2884 src = force_const_mem (mode, src);
2886 /* When using explicit relocs, constant pool references are sometimes
2887 not legitimate addresses. */
2888 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2889 mips_emit_move (dest, src);
2892 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2893 sequence that is valid. */
2896 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2898 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2900 mips_emit_move (dest, force_reg (mode, src));
2904 /* We need to deal with constants that would be legitimate
2905 immediate_operands but aren't legitimate move_operands. */
2906 if (CONSTANT_P (src) && !move_operand (src, mode))
2908 mips_legitimize_const_move (mode, dest, src);
2909 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2915 /* Return true if value X in context CONTEXT is a small-data address
2916 that can be rewritten as a LO_SUM. */
2919 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2921 enum mips_symbol_type symbol_type;
2923 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
2924 && !mips_split_p[SYMBOL_GP_RELATIVE]
2925 && mips_symbolic_constant_p (x, context, &symbol_type)
2926 && symbol_type == SYMBOL_GP_RELATIVE);
2929 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2930 containing MEM, or null if none. */
2933 mips_small_data_pattern_1 (rtx *loc, void *data)
2935 enum mips_symbol_context context;
2937 if (GET_CODE (*loc) == LO_SUM)
2942 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
2947 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2948 return mips_rewrite_small_data_p (*loc, context);
2951 /* Return true if OP refers to small data symbols directly, not through
2955 mips_small_data_pattern_p (rtx op)
2957 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
2960 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2961 DATA is the containing MEM, or null if none. */
2964 mips_rewrite_small_data_1 (rtx *loc, void *data)
2966 enum mips_symbol_context context;
2970 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
2974 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2975 if (mips_rewrite_small_data_p (*loc, context))
2976 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
2978 if (GET_CODE (*loc) == LO_SUM)
2984 /* Rewrite instruction pattern PATTERN so that it refers to small data
2985 using explicit relocations. */
2988 mips_rewrite_small_data (rtx pattern)
2990 pattern = copy_insn (pattern);
2991 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
2995 /* We need a lot of little routines to check the range of MIPS16 immediate
2999 m16_check_op (rtx op, int low, int high, int mask)
3001 return (GET_CODE (op) == CONST_INT
3002 && IN_RANGE (INTVAL (op), low, high)
3003 && (INTVAL (op) & mask) == 0);
3007 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3009 return m16_check_op (op, 0x1, 0x8, 0);
3013 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3015 return m16_check_op (op, -0x8, 0x7, 0);
3019 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3021 return m16_check_op (op, -0x7, 0x8, 0);
3025 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3027 return m16_check_op (op, -0x10, 0xf, 0);
3031 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3033 return m16_check_op (op, -0xf, 0x10, 0);
3037 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3039 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3043 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3045 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3049 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3051 return m16_check_op (op, -0x80, 0x7f, 0);
3055 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3057 return m16_check_op (op, -0x7f, 0x80, 0);
3061 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3063 return m16_check_op (op, 0x0, 0xff, 0);
3067 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3069 return m16_check_op (op, -0xff, 0x0, 0);
3073 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3075 return m16_check_op (op, -0x1, 0xfe, 0);
3079 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3081 return m16_check_op (op, 0x0, 0xff << 2, 3);
3085 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3087 return m16_check_op (op, -0xff << 2, 0x0, 3);
3091 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3093 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3097 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3099 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3102 /* The cost of loading values from the constant pool. It should be
3103 larger than the cost of any constant we want to synthesize inline. */
3104 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3106 /* Return the cost of X when used as an operand to the MIPS16 instruction
3107 that implements CODE. Return -1 if there is no such instruction, or if
3108 X is not a valid immediate operand for it. */
3111 mips16_constant_cost (int code, HOST_WIDE_INT x)
3118 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3119 other shifts are extended. The shift patterns truncate the shift
3120 count to the right size, so there are no out-of-range values. */
3121 if (IN_RANGE (x, 1, 8))
3123 return COSTS_N_INSNS (1);
3126 if (IN_RANGE (x, -128, 127))
3128 if (SMALL_OPERAND (x))
3129 return COSTS_N_INSNS (1);
3133 /* Like LE, but reject the always-true case. */
3137 /* We add 1 to the immediate and use SLT. */
3140 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3143 if (IN_RANGE (x, 0, 255))
3145 if (SMALL_OPERAND_UNSIGNED (x))
3146 return COSTS_N_INSNS (1);
3151 /* Equality comparisons with 0 are cheap. */
3161 /* Return true if there is a non-MIPS16 instruction that implements CODE
3162 and if that instruction accepts X as an immediate operand. */
3165 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3172 /* All shift counts are truncated to a valid constant. */
3177 /* Likewise rotates, if the target supports rotates at all. */
3183 /* These instructions take 16-bit unsigned immediates. */
3184 return SMALL_OPERAND_UNSIGNED (x);
3189 /* These instructions take 16-bit signed immediates. */
3190 return SMALL_OPERAND (x);
3196 /* The "immediate" forms of these instructions are really
3197 implemented as comparisons with register 0. */
3202 /* Likewise, meaning that the only valid immediate operand is 1. */
3206 /* We add 1 to the immediate and use SLT. */
3207 return SMALL_OPERAND (x + 1);
3210 /* Likewise SLTU, but reject the always-true case. */
3211 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3215 /* The bit position and size are immediate operands. */
3216 return ISA_HAS_EXT_INS;
3219 /* By default assume that $0 can be used for 0. */
3224 /* Return the cost of binary operation X, given that the instruction
3225 sequence for a word-sized or smaller operation has cost SINGLE_COST
3226 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3229 mips_binary_cost (rtx x, int single_cost, int double_cost)
3233 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3238 + rtx_cost (XEXP (x, 0), 0, !optimize_size)
3239 + rtx_cost (XEXP (x, 1), GET_CODE (x), !optimize_size));
3242 /* Return the cost of floating-point multiplications of mode MODE. */
3245 mips_fp_mult_cost (enum machine_mode mode)
3247 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3250 /* Return the cost of floating-point divisions of mode MODE. */
3253 mips_fp_div_cost (enum machine_mode mode)
3255 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3258 /* Return the cost of sign-extending OP to mode MODE, not including the
3259 cost of OP itself. */
3262 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3265 /* Extended loads are as cheap as unextended ones. */
3268 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3269 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3272 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3273 /* We can use SEB or SEH. */
3274 return COSTS_N_INSNS (1);
3276 /* We need to use a shift left and a shift right. */
3277 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3280 /* Return the cost of zero-extending OP to mode MODE, not including the
3281 cost of OP itself. */
3284 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3287 /* Extended loads are as cheap as unextended ones. */
3290 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3291 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3292 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3294 if (GENERATE_MIPS16E)
3295 /* We can use ZEB or ZEH. */
3296 return COSTS_N_INSNS (1);
3299 /* We need to load 0xff or 0xffff into a register and use AND. */
3300 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3302 /* We can use ANDI. */
3303 return COSTS_N_INSNS (1);
3306 /* Implement TARGET_RTX_COSTS. */
3309 mips_rtx_costs (rtx x, int code, int outer_code, int *total,
3312 enum machine_mode mode = GET_MODE (x);
3313 bool float_mode_p = FLOAT_MODE_P (mode);
3317 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3318 appear in the instruction stream, and the cost of a comparison is
3319 really the cost of the branch or scc condition. At the time of
3320 writing, GCC only uses an explicit outer COMPARE code when optabs
3321 is testing whether a constant is expensive enough to force into a
3322 register. We want optabs to pass such constants through the MIPS
3323 expanders instead, so make all constants very cheap here. */
3324 if (outer_code == COMPARE)
3326 gcc_assert (CONSTANT_P (x));
3334 /* Treat *clear_upper32-style ANDs as having zero cost in the
3335 second operand. The cost is entirely in the first operand.
3337 ??? This is needed because we would otherwise try to CSE
3338 the constant operand. Although that's the right thing for
3339 instructions that continue to be a register operation throughout
3340 compilation, it is disastrous for instructions that could
3341 later be converted into a memory operation. */
3343 && outer_code == AND
3344 && UINTVAL (x) == 0xffffffff)
3352 cost = mips16_constant_cost (outer_code, INTVAL (x));
3361 /* When not optimizing for size, we care more about the cost
3362 of hot code, and hot code is often in a loop. If a constant
3363 operand needs to be forced into a register, we will often be
3364 able to hoist the constant load out of the loop, so the load
3365 should not contribute to the cost. */
3367 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3379 if (force_to_mem_operand (x, VOIDmode))
3381 *total = COSTS_N_INSNS (1);
3384 cost = mips_const_insns (x);
3387 /* If the constant is likely to be stored in a GPR, SETs of
3388 single-insn constants are as cheap as register sets; we
3389 never want to CSE them.
3391 Don't reduce the cost of storing a floating-point zero in
3392 FPRs. If we have a zero in an FPR for other reasons, we
3393 can get better cfg-cleanup and delayed-branch results by
3394 using it consistently, rather than using $0 sometimes and
3395 an FPR at other times. Also, moves between floating-point
3396 registers are sometimes cheaper than (D)MTC1 $0. */
3398 && outer_code == SET
3399 && !(float_mode_p && TARGET_HARD_FLOAT))
3401 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3402 want to CSE the constant itself. It is usually better to
3403 have N copies of the last operation in the sequence and one
3404 shared copy of the other operations. (Note that this is
3405 not true for MIPS16 code, where the final operation in the
3406 sequence is often an extended instruction.)
3408 Also, if we have a CONST_INT, we don't know whether it is
3409 for a word or doubleword operation, so we cannot rely on
3410 the result of mips_build_integer. */
3411 else if (!TARGET_MIPS16
3412 && (outer_code == SET || mode == VOIDmode))
3414 *total = COSTS_N_INSNS (cost);
3417 /* The value will need to be fetched from the constant pool. */
3418 *total = CONSTANT_POOL_COST;
3422 /* If the address is legitimate, return the number of
3423 instructions it needs. */
3425 cost = mips_address_insns (addr, mode, true);
3428 *total = COSTS_N_INSNS (cost + 1);
3431 /* Check for a scaled indexed address. */
3432 if (mips_lwxs_address_p (addr))
3434 *total = COSTS_N_INSNS (2);
3437 /* Otherwise use the default handling. */
3441 *total = COSTS_N_INSNS (6);
3445 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3449 /* Check for a *clear_upper32 pattern and treat it like a zero
3450 extension. See the pattern's comment for details. */
3453 && CONST_INT_P (XEXP (x, 1))
3454 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3456 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3457 + rtx_cost (XEXP (x, 0), 0, speed));
3464 /* Double-word operations use two single-word operations. */
3465 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3473 if (CONSTANT_P (XEXP (x, 1)))
3474 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3476 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3481 *total = mips_cost->fp_add;
3483 *total = COSTS_N_INSNS (4);
3487 /* Low-part immediates need an extended MIPS16 instruction. */
3488 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3489 + rtx_cost (XEXP (x, 0), 0, speed));
3504 /* Branch comparisons have VOIDmode, so use the first operand's
3506 mode = GET_MODE (XEXP (x, 0));
3507 if (FLOAT_MODE_P (mode))
3509 *total = mips_cost->fp_add;
3512 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3517 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3518 && TARGET_FUSED_MADD
3519 && !HONOR_NANS (mode)
3520 && !HONOR_SIGNED_ZEROS (mode))
3522 /* See if we can use NMADD or NMSUB. See mips.md for the
3523 associated patterns. */
3524 rtx op0 = XEXP (x, 0);
3525 rtx op1 = XEXP (x, 1);
3526 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3528 *total = (mips_fp_mult_cost (mode)
3529 + rtx_cost (XEXP (XEXP (op0, 0), 0), 0, speed)
3530 + rtx_cost (XEXP (op0, 1), 0, speed)
3531 + rtx_cost (op1, 0, speed));
3534 if (GET_CODE (op1) == MULT)
3536 *total = (mips_fp_mult_cost (mode)
3537 + rtx_cost (op0, 0, speed)
3538 + rtx_cost (XEXP (op1, 0), 0, speed)
3539 + rtx_cost (XEXP (op1, 1), 0, speed));
3548 /* If this is part of a MADD or MSUB, treat the PLUS as
3551 && TARGET_FUSED_MADD
3552 && GET_CODE (XEXP (x, 0)) == MULT)
3555 *total = mips_cost->fp_add;
3559 /* Double-word operations require three single-word operations and
3560 an SLTU. The MIPS16 version then needs to move the result of
3561 the SLTU from $24 to a MIPS16 register. */
3562 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3563 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3568 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3569 && TARGET_FUSED_MADD
3570 && !HONOR_NANS (mode)
3571 && HONOR_SIGNED_ZEROS (mode))
3573 /* See if we can use NMADD or NMSUB. See mips.md for the
3574 associated patterns. */
3575 rtx op = XEXP (x, 0);
3576 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3577 && GET_CODE (XEXP (op, 0)) == MULT)
3579 *total = (mips_fp_mult_cost (mode)
3580 + rtx_cost (XEXP (XEXP (op, 0), 0), 0, speed)
3581 + rtx_cost (XEXP (XEXP (op, 0), 1), 0, speed)
3582 + rtx_cost (XEXP (op, 1), 0, speed));
3588 *total = mips_cost->fp_add;
3590 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3595 *total = mips_fp_mult_cost (mode);
3596 else if (mode == DImode && !TARGET_64BIT)
3597 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3598 where the mulsidi3 always includes an MFHI and an MFLO. */
3599 *total = (optimize_size
3600 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3601 : mips_cost->int_mult_si * 3 + 6);
3602 else if (optimize_size)
3603 *total = (ISA_HAS_MUL3 ? 1 : 2);
3604 else if (mode == DImode)
3605 *total = mips_cost->int_mult_di;
3607 *total = mips_cost->int_mult_si;
3611 /* Check for a reciprocal. */
3614 && flag_unsafe_math_optimizations
3615 && XEXP (x, 0) == CONST1_RTX (mode))
3617 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3618 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3619 division as being free. */
3620 *total = rtx_cost (XEXP (x, 1), 0, speed);
3622 *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0, speed);
3631 *total = mips_fp_div_cost (mode);
3640 /* It is our responsibility to make division by a power of 2
3641 as cheap as 2 register additions if we want the division
3642 expanders to be used for such operations; see the setting
3643 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3644 should always produce shorter code than using
3645 expand_sdiv2_pow2. */
3647 && CONST_INT_P (XEXP (x, 1))
3648 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3650 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0, speed);
3653 *total = COSTS_N_INSNS (mips_idiv_insns ());
3655 else if (mode == DImode)
3656 *total = mips_cost->int_div_di;
3658 *total = mips_cost->int_div_si;
3662 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3666 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3670 case UNSIGNED_FLOAT:
3673 case FLOAT_TRUNCATE:
3674 *total = mips_cost->fp_add;
3682 /* Implement TARGET_ADDRESS_COST. */
3685 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3687 return mips_address_insns (addr, SImode, false);
3690 /* Return one word of double-word value OP, taking into account the fixed
3691 endianness of certain registers. HIGH_P is true to select the high part,
3692 false to select the low part. */
3695 mips_subword (rtx op, bool high_p)
3697 unsigned int byte, offset;
3698 enum machine_mode mode;
3700 mode = GET_MODE (op);
3701 if (mode == VOIDmode)
3702 mode = TARGET_64BIT ? TImode : DImode;
3704 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3705 byte = UNITS_PER_WORD;
3709 if (FP_REG_RTX_P (op))
3711 /* Paired FPRs are always ordered little-endian. */
3712 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3713 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3717 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3719 return simplify_gen_subreg (word_mode, op, mode, byte);
3722 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3725 mips_split_64bit_move_p (rtx dest, rtx src)
3730 /* FPR-to-FPR moves can be done in a single instruction, if they're
3732 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3735 /* Check for floating-point loads and stores. */
3736 if (ISA_HAS_LDC1_SDC1)
3738 if (FP_REG_RTX_P (dest) && MEM_P (src))
3740 if (FP_REG_RTX_P (src) && MEM_P (dest))
3746 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3747 this function handles 64-bit moves for which mips_split_64bit_move_p
3748 holds. For 64-bit targets, this function handles 128-bit moves. */
3751 mips_split_doubleword_move (rtx dest, rtx src)
3755 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3757 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3758 emit_insn (gen_move_doubleword_fprdi (dest, src));
3759 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3760 emit_insn (gen_move_doubleword_fprdf (dest, src));
3761 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3762 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3763 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
3764 emit_insn (gen_move_doubleword_fprv2si (dest, src));
3765 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
3766 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
3767 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
3768 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
3769 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3770 emit_insn (gen_move_doubleword_fprtf (dest, src));
3774 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
3776 low_dest = mips_subword (dest, false);
3777 mips_emit_move (low_dest, mips_subword (src, false));
3779 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
3781 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
3783 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
3785 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
3787 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
3789 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
3793 /* The operation can be split into two normal moves. Decide in
3794 which order to do them. */
3795 low_dest = mips_subword (dest, false);
3796 if (REG_P (low_dest)
3797 && reg_overlap_mentioned_p (low_dest, src))
3799 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3800 mips_emit_move (low_dest, mips_subword (src, false));
3804 mips_emit_move (low_dest, mips_subword (src, false));
3805 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3810 /* Return the appropriate instructions to move SRC into DEST. Assume
3811 that SRC is operand 1 and DEST is operand 0. */
3814 mips_output_move (rtx dest, rtx src)
3816 enum rtx_code dest_code, src_code;
3817 enum machine_mode mode;
3818 enum mips_symbol_type symbol_type;
3821 dest_code = GET_CODE (dest);
3822 src_code = GET_CODE (src);
3823 mode = GET_MODE (dest);
3824 dbl_p = (GET_MODE_SIZE (mode) == 8);
3826 if (dbl_p && mips_split_64bit_move_p (dest, src))
3829 if ((src_code == REG && GP_REG_P (REGNO (src)))
3830 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
3832 if (dest_code == REG)
3834 if (GP_REG_P (REGNO (dest)))
3835 return "move\t%0,%z1";
3837 /* Moves to HI are handled by special .md insns. */
3838 if (REGNO (dest) == LO_REGNUM)
3841 if (DSP_ACC_REG_P (REGNO (dest)))
3843 static char retval[] = "mt__\t%z1,%q0";
3845 retval[2] = reg_names[REGNO (dest)][4];
3846 retval[3] = reg_names[REGNO (dest)][5];
3850 if (FP_REG_P (REGNO (dest)))
3851 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3853 if (ALL_COP_REG_P (REGNO (dest)))
3855 static char retval[] = "dmtc_\t%z1,%0";
3857 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3858 return dbl_p ? retval : retval + 1;
3861 if (dest_code == MEM)
3862 switch (GET_MODE_SIZE (mode))
3864 case 1: return "sb\t%z1,%0";
3865 case 2: return "sh\t%z1,%0";
3866 case 4: return "sw\t%z1,%0";
3867 case 8: return "sd\t%z1,%0";
3870 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3872 if (src_code == REG)
3874 /* Moves from HI are handled by special .md insns. */
3875 if (REGNO (src) == LO_REGNUM)
3877 /* When generating VR4120 or VR4130 code, we use MACC and
3878 DMACC instead of MFLO. This avoids both the normal
3879 MIPS III HI/LO hazards and the errata related to
3882 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
3886 if (DSP_ACC_REG_P (REGNO (src)))
3888 static char retval[] = "mf__\t%0,%q1";
3890 retval[2] = reg_names[REGNO (src)][4];
3891 retval[3] = reg_names[REGNO (src)][5];
3895 if (FP_REG_P (REGNO (src)))
3896 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3898 if (ALL_COP_REG_P (REGNO (src)))
3900 static char retval[] = "dmfc_\t%0,%1";
3902 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3903 return dbl_p ? retval : retval + 1;
3906 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3907 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3910 if (src_code == MEM)
3911 switch (GET_MODE_SIZE (mode))
3913 case 1: return "lbu\t%0,%1";
3914 case 2: return "lhu\t%0,%1";
3915 case 4: return "lw\t%0,%1";
3916 case 8: return "ld\t%0,%1";
3919 if (src_code == CONST_INT)
3921 /* Don't use the X format for the operand itself, because that
3922 will give out-of-range numbers for 64-bit hosts and 32-bit
3925 return "li\t%0,%1\t\t\t# %X1";
3927 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
3930 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
3934 if (src_code == HIGH)
3935 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
3937 if (CONST_GP_P (src))
3938 return "move\t%0,%1";
3940 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
3941 && mips_lo_relocs[symbol_type] != 0)
3943 /* A signed 16-bit constant formed by applying a relocation
3944 operator to a symbolic address. */
3945 gcc_assert (!mips_split_p[symbol_type]);
3946 return "li\t%0,%R1";
3949 if (symbolic_operand (src, VOIDmode))
3951 gcc_assert (TARGET_MIPS16
3952 ? TARGET_MIPS16_TEXT_LOADS
3953 : !TARGET_EXPLICIT_RELOCS);
3954 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
3957 if (src_code == REG && FP_REG_P (REGNO (src)))
3959 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3961 if (GET_MODE (dest) == V2SFmode)
3962 return "mov.ps\t%0,%1";
3964 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
3967 if (dest_code == MEM)
3968 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
3970 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3972 if (src_code == MEM)
3973 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
3975 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3977 static char retval[] = "l_c_\t%0,%1";
3979 retval[1] = (dbl_p ? 'd' : 'w');
3980 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3983 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3985 static char retval[] = "s_c_\t%1,%0";
3987 retval[1] = (dbl_p ? 'd' : 'w');
3988 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3994 /* Return true if CMP1 is a suitable second operand for integer ordering
3995 test CODE. See also the *sCC patterns in mips.md. */
3998 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4004 return reg_or_0_operand (cmp1, VOIDmode);
4008 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4012 return arith_operand (cmp1, VOIDmode);
4015 return sle_operand (cmp1, VOIDmode);
4018 return sleu_operand (cmp1, VOIDmode);
4025 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4026 integer ordering test *CODE, or if an equivalent combination can
4027 be formed by adjusting *CODE and *CMP1. When returning true, update
4028 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4032 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4033 enum machine_mode mode)
4035 HOST_WIDE_INT plus_one;
4037 if (mips_int_order_operand_ok_p (*code, *cmp1))
4040 if (GET_CODE (*cmp1) == CONST_INT)
4044 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4045 if (INTVAL (*cmp1) < plus_one)
4048 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4054 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4058 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4069 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4070 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4071 is nonnull, it's OK to set TARGET to the inverse of the result and
4072 flip *INVERT_PTR instead. */
4075 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4076 rtx target, rtx cmp0, rtx cmp1)
4078 enum machine_mode mode;
4080 /* First see if there is a MIPS instruction that can do this operation.
4081 If not, try doing the same for the inverse operation. If that also
4082 fails, force CMP1 into a register and try again. */
4083 mode = GET_MODE (cmp0);
4084 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4085 mips_emit_binary (code, target, cmp0, cmp1);
4088 enum rtx_code inv_code = reverse_condition (code);
4089 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4091 cmp1 = force_reg (mode, cmp1);
4092 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4094 else if (invert_ptr == 0)
4098 inv_target = mips_force_binary (GET_MODE (target),
4099 inv_code, cmp0, cmp1);
4100 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4104 *invert_ptr = !*invert_ptr;
4105 mips_emit_binary (inv_code, target, cmp0, cmp1);
4110 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4111 The register will have the same mode as CMP0. */
4114 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4116 if (cmp1 == const0_rtx)
4119 if (uns_arith_operand (cmp1, VOIDmode))
4120 return expand_binop (GET_MODE (cmp0), xor_optab,
4121 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4123 return expand_binop (GET_MODE (cmp0), sub_optab,
4124 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4127 /* Convert *CODE into a code that can be used in a floating-point
4128 scc instruction (C.cond.fmt). Return true if the values of
4129 the condition code registers will be inverted, with 0 indicating
4130 that the condition holds. */
4133 mips_reversed_fp_cond (enum rtx_code *code)
4140 *code = reverse_condition_maybe_unordered (*code);
4148 /* Convert a comparison into something that can be used in a branch or
4149 conditional move. cmp_operands[0] and cmp_operands[1] are the values
4150 being compared and *CODE is the code used to compare them.
4152 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4153 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4154 otherwise any standard branch condition can be used. The standard branch
4157 - EQ or NE between two registers.
4158 - any comparison between a register and zero. */
4161 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4163 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
4165 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
4167 *op0 = cmp_operands[0];
4168 *op1 = cmp_operands[1];
4170 else if (*code == EQ || *code == NE)
4174 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
4179 *op0 = cmp_operands[0];
4180 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
4185 /* The comparison needs a separate scc instruction. Store the
4186 result of the scc in *OP0 and compare it against zero. */
4187 bool invert = false;
4188 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
4189 mips_emit_int_order_test (*code, &invert, *op0,
4190 cmp_operands[0], cmp_operands[1]);
4191 *code = (invert ? EQ : NE);
4195 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
4197 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4198 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
4204 enum rtx_code cmp_code;
4206 /* Floating-point tests use a separate C.cond.fmt comparison to
4207 set a condition code register. The branch or conditional move
4208 will then compare that register against zero.
4210 Set CMP_CODE to the code of the comparison instruction and
4211 *CODE to the code that the branch or move should use. */
4213 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4215 ? gen_reg_rtx (CCmode)
4216 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4218 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
4222 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
4223 Store the result in TARGET and return true if successful.
4225 On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */
4228 mips_expand_scc (enum rtx_code code, rtx target)
4230 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
4233 if (code == EQ || code == NE)
4236 && reg_imm10_operand (cmp_operands[1], GET_MODE (cmp_operands[1])))
4237 mips_emit_binary (code, target, cmp_operands[0], cmp_operands[1]);
4240 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
4241 mips_emit_binary (code, target, zie, const0_rtx);
4245 mips_emit_int_order_test (code, 0, target,
4246 cmp_operands[0], cmp_operands[1]);
4250 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
4251 CODE and jump to OPERANDS[0] if the condition holds. */
4254 mips_expand_conditional_branch (rtx *operands, enum rtx_code code)
4256 rtx op0, op1, condition;
4258 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4259 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4260 emit_jump_insn (gen_condjump (condition, operands[0]));
4265 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4266 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4269 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4270 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4275 reversed_p = mips_reversed_fp_cond (&cond);
4276 cmp_result = gen_reg_rtx (CCV2mode);
4277 emit_insn (gen_scc_ps (cmp_result,
4278 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4280 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4283 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4287 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
4288 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
4289 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4292 mips_expand_conditional_move (rtx *operands)
4297 code = GET_CODE (operands[1]);
4298 mips_emit_compare (&code, &op0, &op1, true);
4299 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1),
4300 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4301 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4302 operands[2], operands[3])));
4305 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
4306 then trap if the condition holds. */
4309 mips_expand_conditional_trap (enum rtx_code code)
4312 enum machine_mode mode;
4314 /* MIPS conditional trap instructions don't have GT or LE flavors,
4315 so we must swap the operands and convert to LT and GE respectively. */
4322 code = swap_condition (code);
4323 op0 = cmp_operands[1];
4324 op1 = cmp_operands[0];
4328 op0 = cmp_operands[0];
4329 op1 = cmp_operands[1];
4333 mode = GET_MODE (cmp_operands[0]);
4334 op0 = force_reg (mode, op0);
4335 if (!arith_operand (op1, mode))
4336 op1 = force_reg (mode, op1);
4338 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4339 gen_rtx_fmt_ee (code, mode, op0, op1),
4343 /* Initialize *CUM for a call to a function of type FNTYPE. */
4346 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4348 memset (cum, 0, sizeof (*cum));
4349 cum->prototype = (fntype && prototype_p (fntype));
4350 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4353 /* Fill INFO with information about a single argument. CUM is the
4354 cumulative state for earlier arguments. MODE is the mode of this
4355 argument and TYPE is its type (if known). NAMED is true if this
4356 is a named (fixed) argument rather than a variable one. */
4359 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4360 enum machine_mode mode, tree type, int named)
4362 bool doubleword_aligned_p;
4363 unsigned int num_bytes, num_words, max_regs;
4365 /* Work out the size of the argument. */
4366 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4367 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4369 /* Decide whether it should go in a floating-point register, assuming
4370 one is free. Later code checks for availability.
4372 The checks against UNITS_PER_FPVALUE handle the soft-float and
4373 single-float cases. */
4377 /* The EABI conventions have traditionally been defined in terms
4378 of TYPE_MODE, regardless of the actual type. */
4379 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4380 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4381 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4386 /* Only leading floating-point scalars are passed in
4387 floating-point registers. We also handle vector floats the same
4388 say, which is OK because they are not covered by the standard ABI. */
4389 info->fpr_p = (!cum->gp_reg_found
4390 && cum->arg_number < 2
4392 || SCALAR_FLOAT_TYPE_P (type)
4393 || VECTOR_FLOAT_TYPE_P (type))
4394 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4395 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4396 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4401 /* Scalar, complex and vector floating-point types are passed in
4402 floating-point registers, as long as this is a named rather
4403 than a variable argument. */
4404 info->fpr_p = (named
4405 && (type == 0 || FLOAT_TYPE_P (type))
4406 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4407 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4408 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4409 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4411 /* ??? According to the ABI documentation, the real and imaginary
4412 parts of complex floats should be passed in individual registers.
4413 The real and imaginary parts of stack arguments are supposed
4414 to be contiguous and there should be an extra word of padding
4417 This has two problems. First, it makes it impossible to use a
4418 single "void *" va_list type, since register and stack arguments
4419 are passed differently. (At the time of writing, MIPSpro cannot
4420 handle complex float varargs correctly.) Second, it's unclear
4421 what should happen when there is only one register free.
4423 For now, we assume that named complex floats should go into FPRs
4424 if there are two FPRs free, otherwise they should be passed in the
4425 same way as a struct containing two floats. */
4427 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4428 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4430 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4431 info->fpr_p = false;
4441 /* See whether the argument has doubleword alignment. */
4442 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4444 /* Set REG_OFFSET to the register count we're interested in.
4445 The EABI allocates the floating-point registers separately,
4446 but the other ABIs allocate them like integer registers. */
4447 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4451 /* Advance to an even register if the argument is doubleword-aligned. */
4452 if (doubleword_aligned_p)
4453 info->reg_offset += info->reg_offset & 1;
4455 /* Work out the offset of a stack argument. */
4456 info->stack_offset = cum->stack_words;
4457 if (doubleword_aligned_p)
4458 info->stack_offset += info->stack_offset & 1;
4460 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4462 /* Partition the argument between registers and stack. */
4463 info->reg_words = MIN (num_words, max_regs);
4464 info->stack_words = num_words - info->reg_words;
4467 /* INFO describes a register argument that has the normal format for the
4468 argument's mode. Return the register it uses, assuming that FPRs are
4469 available if HARD_FLOAT_P. */
4472 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4474 if (!info->fpr_p || !hard_float_p)
4475 return GP_ARG_FIRST + info->reg_offset;
4476 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4477 /* In o32, the second argument is always passed in $f14
4478 for TARGET_DOUBLE_FLOAT, regardless of whether the
4479 first argument was a word or doubleword. */
4480 return FP_ARG_FIRST + 2;
4482 return FP_ARG_FIRST + info->reg_offset;
4485 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4488 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4490 return !TARGET_OLDABI;
4493 /* Implement FUNCTION_ARG. */
4496 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4497 tree type, int named)
4499 struct mips_arg_info info;
4501 /* We will be called with a mode of VOIDmode after the last argument
4502 has been seen. Whatever we return will be passed to the call expander.
4503 If we need a MIPS16 fp_code, return a REG with the code stored as
4505 if (mode == VOIDmode)
4507 if (TARGET_MIPS16 && cum->fp_code != 0)
4508 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4513 mips_get_arg_info (&info, cum, mode, type, named);
4515 /* Return straight away if the whole argument is passed on the stack. */
4516 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4519 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4520 contains a double in its entirety, then that 64-bit chunk is passed
4521 in a floating-point register. */
4523 && TARGET_HARD_FLOAT
4526 && TREE_CODE (type) == RECORD_TYPE
4527 && TYPE_SIZE_UNIT (type)
4528 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4532 /* First check to see if there is any such field. */
4533 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4534 if (TREE_CODE (field) == FIELD_DECL
4535 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4536 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4537 && host_integerp (bit_position (field), 0)
4538 && int_bit_position (field) % BITS_PER_WORD == 0)
4543 /* Now handle the special case by returning a PARALLEL
4544 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4545 chunks are passed in registers. */
4547 HOST_WIDE_INT bitpos;
4550 /* assign_parms checks the mode of ENTRY_PARM, so we must
4551 use the actual mode here. */
4552 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4555 field = TYPE_FIELDS (type);
4556 for (i = 0; i < info.reg_words; i++)
4560 for (; field; field = TREE_CHAIN (field))
4561 if (TREE_CODE (field) == FIELD_DECL
4562 && int_bit_position (field) >= bitpos)
4566 && int_bit_position (field) == bitpos
4567 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4568 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4569 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4571 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4574 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4575 GEN_INT (bitpos / BITS_PER_UNIT));
4577 bitpos += BITS_PER_WORD;
4583 /* Handle the n32/n64 conventions for passing complex floating-point
4584 arguments in FPR pairs. The real part goes in the lower register
4585 and the imaginary part goes in the upper register. */
4588 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4591 enum machine_mode inner;
4594 inner = GET_MODE_INNER (mode);
4595 regno = FP_ARG_FIRST + info.reg_offset;
4596 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4598 /* Real part in registers, imaginary part on stack. */
4599 gcc_assert (info.stack_words == info.reg_words);
4600 return gen_rtx_REG (inner, regno);
4604 gcc_assert (info.stack_words == 0);
4605 real = gen_rtx_EXPR_LIST (VOIDmode,
4606 gen_rtx_REG (inner, regno),
4608 imag = gen_rtx_EXPR_LIST (VOIDmode,
4610 regno + info.reg_words / 2),
4611 GEN_INT (GET_MODE_SIZE (inner)));
4612 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4616 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4619 /* Implement FUNCTION_ARG_ADVANCE. */
4622 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4623 tree type, int named)
4625 struct mips_arg_info info;
4627 mips_get_arg_info (&info, cum, mode, type, named);
4630 cum->gp_reg_found = true;
4632 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4633 an explanation of what this code does. It assumes that we're using
4634 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4636 if (cum->arg_number < 2 && info.fpr_p)
4637 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4639 /* Advance the register count. This has the effect of setting
4640 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4641 argument required us to skip the final GPR and pass the whole
4642 argument on the stack. */
4643 if (mips_abi != ABI_EABI || !info.fpr_p)
4644 cum->num_gprs = info.reg_offset + info.reg_words;
4645 else if (info.reg_words > 0)
4646 cum->num_fprs += MAX_FPRS_PER_FMT;
4648 /* Advance the stack word count. */
4649 if (info.stack_words > 0)
4650 cum->stack_words = info.stack_offset + info.stack_words;
4655 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4658 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4659 enum machine_mode mode, tree type, bool named)
4661 struct mips_arg_info info;
4663 mips_get_arg_info (&info, cum, mode, type, named);
4664 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4667 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4668 PARM_BOUNDARY bits of alignment, but will be given anything up
4669 to STACK_BOUNDARY bits if the type requires it. */
4672 mips_function_arg_boundary (enum machine_mode mode, tree type)
4674 unsigned int alignment;
4676 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4677 if (alignment < PARM_BOUNDARY)
4678 alignment = PARM_BOUNDARY;
4679 if (alignment > STACK_BOUNDARY)
4680 alignment = STACK_BOUNDARY;
4684 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4685 upward rather than downward. In other words, return true if the
4686 first byte of the stack slot has useful data, false if the last
4690 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4692 /* On little-endian targets, the first byte of every stack argument
4693 is passed in the first byte of the stack slot. */
4694 if (!BYTES_BIG_ENDIAN)
4697 /* Otherwise, integral types are padded downward: the last byte of a
4698 stack argument is passed in the last byte of the stack slot. */
4700 ? (INTEGRAL_TYPE_P (type)
4701 || POINTER_TYPE_P (type)
4702 || FIXED_POINT_TYPE_P (type))
4703 : (SCALAR_INT_MODE_P (mode)
4704 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4707 /* Big-endian o64 pads floating-point arguments downward. */
4708 if (mips_abi == ABI_O64)
4709 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4712 /* Other types are padded upward for o32, o64, n32 and n64. */
4713 if (mips_abi != ABI_EABI)
4716 /* Arguments smaller than a stack slot are padded downward. */
4717 if (mode != BLKmode)
4718 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4720 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4723 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4724 if the least significant byte of the register has useful data. Return
4725 the opposite if the most significant byte does. */
4728 mips_pad_reg_upward (enum machine_mode mode, tree type)
4730 /* No shifting is required for floating-point arguments. */
4731 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4732 return !BYTES_BIG_ENDIAN;
4734 /* Otherwise, apply the same padding to register arguments as we do
4735 to stack arguments. */
4736 return mips_pad_arg_upward (mode, type);
4739 /* Return nonzero when an argument must be passed by reference. */
4742 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4743 enum machine_mode mode, const_tree type,
4744 bool named ATTRIBUTE_UNUSED)
4746 if (mips_abi == ABI_EABI)
4750 /* ??? How should SCmode be handled? */
4751 if (mode == DImode || mode == DFmode
4752 || mode == DQmode || mode == UDQmode
4753 || mode == DAmode || mode == UDAmode)
4756 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4757 return size == -1 || size > UNITS_PER_WORD;
4761 /* If we have a variable-sized parameter, we have no choice. */
4762 return targetm.calls.must_pass_in_stack (mode, type);
4766 /* Implement TARGET_CALLEE_COPIES. */
4769 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4770 enum machine_mode mode ATTRIBUTE_UNUSED,
4771 const_tree type ATTRIBUTE_UNUSED, bool named)
4773 return mips_abi == ABI_EABI && named;
4776 /* See whether VALTYPE is a record whose fields should be returned in
4777 floating-point registers. If so, return the number of fields and
4778 list them in FIELDS (which should have two elements). Return 0
4781 For n32 & n64, a structure with one or two fields is returned in
4782 floating-point registers as long as every field has a floating-point
4786 mips_fpr_return_fields (const_tree valtype, tree *fields)
4794 if (TREE_CODE (valtype) != RECORD_TYPE)
4798 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4800 if (TREE_CODE (field) != FIELD_DECL)
4803 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
4809 fields[i++] = field;
4814 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4815 a value in the most significant part of $2/$3 if:
4817 - the target is big-endian;
4819 - the value has a structure or union type (we generalize this to
4820 cover aggregates from other languages too); and
4822 - the structure is not returned in floating-point registers. */
4825 mips_return_in_msb (const_tree valtype)
4829 return (TARGET_NEWABI
4830 && TARGET_BIG_ENDIAN
4831 && AGGREGATE_TYPE_P (valtype)
4832 && mips_fpr_return_fields (valtype, fields) == 0);
4835 /* Return true if the function return value MODE will get returned in a
4836 floating-point register. */
4839 mips_return_mode_in_fpr_p (enum machine_mode mode)
4841 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4842 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4843 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4844 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4847 /* Return the representation of an FPR return register when the
4848 value being returned in FP_RETURN has mode VALUE_MODE and the
4849 return type itself has mode TYPE_MODE. On NewABI targets,
4850 the two modes may be different for structures like:
4852 struct __attribute__((packed)) foo { float f; }
4854 where we return the SFmode value of "f" in FP_RETURN, but where
4855 the structure itself has mode BLKmode. */
4858 mips_return_fpr_single (enum machine_mode type_mode,
4859 enum machine_mode value_mode)
4863 x = gen_rtx_REG (value_mode, FP_RETURN);
4864 if (type_mode != value_mode)
4866 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
4867 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
4872 /* Return a composite value in a pair of floating-point registers.
4873 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4874 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4877 For n32 & n64, $f0 always holds the first value and $f2 the second.
4878 Otherwise the values are packed together as closely as possible. */
4881 mips_return_fpr_pair (enum machine_mode mode,
4882 enum machine_mode mode1, HOST_WIDE_INT offset1,
4883 enum machine_mode mode2, HOST_WIDE_INT offset2)
4887 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4888 return gen_rtx_PARALLEL
4891 gen_rtx_EXPR_LIST (VOIDmode,
4892 gen_rtx_REG (mode1, FP_RETURN),
4894 gen_rtx_EXPR_LIST (VOIDmode,
4895 gen_rtx_REG (mode2, FP_RETURN + inc),
4896 GEN_INT (offset2))));
4900 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4901 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4902 VALTYPE is null and MODE is the mode of the return value. */
4905 mips_function_value (const_tree valtype, enum machine_mode mode)
4912 mode = TYPE_MODE (valtype);
4913 unsigned_p = TYPE_UNSIGNED (valtype);
4915 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4916 we must promote the mode just as PROMOTE_MODE does. */
4917 mode = promote_mode (valtype, mode, &unsigned_p, 1);
4919 /* Handle structures whose fields are returned in $f0/$f2. */
4920 switch (mips_fpr_return_fields (valtype, fields))
4923 return mips_return_fpr_single (mode,
4924 TYPE_MODE (TREE_TYPE (fields[0])));
4927 return mips_return_fpr_pair (mode,
4928 TYPE_MODE (TREE_TYPE (fields[0])),
4929 int_byte_position (fields[0]),
4930 TYPE_MODE (TREE_TYPE (fields[1])),
4931 int_byte_position (fields[1]));
4934 /* If a value is passed in the most significant part of a register, see
4935 whether we have to round the mode up to a whole number of words. */
4936 if (mips_return_in_msb (valtype))
4938 HOST_WIDE_INT size = int_size_in_bytes (valtype);
4939 if (size % UNITS_PER_WORD != 0)
4941 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4942 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4946 /* For EABI, the class of return register depends entirely on MODE.
4947 For example, "struct { some_type x; }" and "union { some_type x; }"
4948 are returned in the same way as a bare "some_type" would be.
4949 Other ABIs only use FPRs for scalar, complex or vector types. */
4950 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
4951 return gen_rtx_REG (mode, GP_RETURN);
4956 /* Handle long doubles for n32 & n64. */
4958 return mips_return_fpr_pair (mode,
4960 DImode, GET_MODE_SIZE (mode) / 2);
4962 if (mips_return_mode_in_fpr_p (mode))
4964 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4965 return mips_return_fpr_pair (mode,
4966 GET_MODE_INNER (mode), 0,
4967 GET_MODE_INNER (mode),
4968 GET_MODE_SIZE (mode) / 2);
4970 return gen_rtx_REG (mode, FP_RETURN);
4974 return gen_rtx_REG (mode, GP_RETURN);
4977 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
4978 all BLKmode objects are returned in memory. Under the n32, n64
4979 and embedded ABIs, small structures are returned in a register.
4980 Objects with varying size must still be returned in memory, of
4984 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
4986 return (TARGET_OLDABI
4987 ? TYPE_MODE (type) == BLKmode
4988 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
4991 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
4994 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4995 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4998 CUMULATIVE_ARGS local_cum;
4999 int gp_saved, fp_saved;
5001 /* The caller has advanced CUM up to, but not beyond, the last named
5002 argument. Advance a local copy of CUM past the last "real" named
5003 argument, to find out how many registers are left over. */
5005 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5007 /* Found out how many registers we need to save. */
5008 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5009 fp_saved = (EABI_FLOAT_VARARGS_P
5010 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5019 ptr = plus_constant (virtual_incoming_args_rtx,
5020 REG_PARM_STACK_SPACE (cfun->decl)
5021 - gp_saved * UNITS_PER_WORD);
5022 mem = gen_frame_mem (BLKmode, ptr);
5023 set_mem_alias_set (mem, get_varargs_alias_set ());
5025 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5030 /* We can't use move_block_from_reg, because it will use
5032 enum machine_mode mode;
5035 /* Set OFF to the offset from virtual_incoming_args_rtx of
5036 the first float register. The FP save area lies below
5037 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5038 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5039 off -= fp_saved * UNITS_PER_FPREG;
5041 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5043 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5044 i += MAX_FPRS_PER_FMT)
5048 ptr = plus_constant (virtual_incoming_args_rtx, off);
5049 mem = gen_frame_mem (mode, ptr);
5050 set_mem_alias_set (mem, get_varargs_alias_set ());
5051 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5052 off += UNITS_PER_HWFPVALUE;
5056 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5057 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5058 + fp_saved * UNITS_PER_FPREG);
5061 /* Implement TARGET_BUILTIN_VA_LIST. */
5064 mips_build_builtin_va_list (void)
5066 if (EABI_FLOAT_VARARGS_P)
5068 /* We keep 3 pointers, and two offsets.
5070 Two pointers are to the overflow area, which starts at the CFA.
5071 One of these is constant, for addressing into the GPR save area
5072 below it. The other is advanced up the stack through the
5075 The third pointer is to the bottom of the GPR save area.
5076 Since the FPR save area is just below it, we can address
5077 FPR slots off this pointer.
5079 We also keep two one-byte offsets, which are to be subtracted
5080 from the constant pointers to yield addresses in the GPR and
5081 FPR save areas. These are downcounted as float or non-float
5082 arguments are used, and when they get to zero, the argument
5083 must be obtained from the overflow region. */
5084 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5087 record = lang_hooks.types.make_type (RECORD_TYPE);
5089 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
5091 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
5093 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
5095 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
5096 unsigned_char_type_node);
5097 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
5098 unsigned_char_type_node);
5099 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5100 warn on every user file. */
5101 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5102 array = build_array_type (unsigned_char_type_node,
5103 build_index_type (index));
5104 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
5106 DECL_FIELD_CONTEXT (f_ovfl) = record;
5107 DECL_FIELD_CONTEXT (f_gtop) = record;
5108 DECL_FIELD_CONTEXT (f_ftop) = record;
5109 DECL_FIELD_CONTEXT (f_goff) = record;
5110 DECL_FIELD_CONTEXT (f_foff) = record;
5111 DECL_FIELD_CONTEXT (f_res) = record;
5113 TYPE_FIELDS (record) = f_ovfl;
5114 TREE_CHAIN (f_ovfl) = f_gtop;
5115 TREE_CHAIN (f_gtop) = f_ftop;
5116 TREE_CHAIN (f_ftop) = f_goff;
5117 TREE_CHAIN (f_goff) = f_foff;
5118 TREE_CHAIN (f_foff) = f_res;
5120 layout_type (record);
5123 else if (TARGET_IRIX && TARGET_IRIX6)
5124 /* On IRIX 6, this type is 'char *'. */
5125 return build_pointer_type (char_type_node);
5127 /* Otherwise, we use 'void *'. */
5128 return ptr_type_node;
5131 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5134 mips_va_start (tree valist, rtx nextarg)
5136 if (EABI_FLOAT_VARARGS_P)
5138 const CUMULATIVE_ARGS *cum;
5139 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5140 tree ovfl, gtop, ftop, goff, foff;
5142 int gpr_save_area_size;
5143 int fpr_save_area_size;
5146 cum = &crtl->args.info;
5148 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5150 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5152 f_ovfl = TYPE_FIELDS (va_list_type_node);
5153 f_gtop = TREE_CHAIN (f_ovfl);
5154 f_ftop = TREE_CHAIN (f_gtop);
5155 f_goff = TREE_CHAIN (f_ftop);
5156 f_foff = TREE_CHAIN (f_goff);
5158 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5160 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5162 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5164 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5166 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5169 /* Emit code to initialize OVFL, which points to the next varargs
5170 stack argument. CUM->STACK_WORDS gives the number of stack
5171 words used by named arguments. */
5172 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5173 if (cum->stack_words > 0)
5174 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5175 size_int (cum->stack_words * UNITS_PER_WORD));
5176 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5177 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5179 /* Emit code to initialize GTOP, the top of the GPR save area. */
5180 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5181 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5182 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5184 /* Emit code to initialize FTOP, the top of the FPR save area.
5185 This address is gpr_save_area_bytes below GTOP, rounded
5186 down to the next fp-aligned boundary. */
5187 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5188 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5189 fpr_offset &= -UNITS_PER_FPVALUE;
5191 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5192 size_int (-fpr_offset));
5193 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5194 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5196 /* Emit code to initialize GOFF, the offset from GTOP of the
5197 next GPR argument. */
5198 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5199 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5200 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5202 /* Likewise emit code to initialize FOFF, the offset from FTOP
5203 of the next FPR argument. */
5204 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5205 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5206 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5210 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5211 std_expand_builtin_va_start (valist, nextarg);
5215 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5218 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5224 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5226 type = build_pointer_type (type);
5228 if (!EABI_FLOAT_VARARGS_P)
5229 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5232 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5233 tree ovfl, top, off, align;
5234 HOST_WIDE_INT size, rsize, osize;
5237 f_ovfl = TYPE_FIELDS (va_list_type_node);
5238 f_gtop = TREE_CHAIN (f_ovfl);
5239 f_ftop = TREE_CHAIN (f_gtop);
5240 f_goff = TREE_CHAIN (f_ftop);
5241 f_foff = TREE_CHAIN (f_goff);
5245 TOP be the top of the GPR or FPR save area;
5246 OFF be the offset from TOP of the next register;
5247 ADDR_RTX be the address of the argument;
5248 SIZE be the number of bytes in the argument type;
5249 RSIZE be the number of bytes used to store the argument
5250 when it's in the register save area; and
5251 OSIZE be the number of bytes used to store it when it's
5252 in the stack overflow area.
5254 The code we want is:
5256 1: off &= -rsize; // round down
5259 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5264 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5265 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5269 [1] and [9] can sometimes be optimized away. */
5271 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5273 size = int_size_in_bytes (type);
5275 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5276 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5278 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5280 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5283 /* When va_start saves FPR arguments to the stack, each slot
5284 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5285 argument's precision. */
5286 rsize = UNITS_PER_HWFPVALUE;
5288 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5289 (= PARM_BOUNDARY bits). This can be different from RSIZE
5292 (1) On 32-bit targets when TYPE is a structure such as:
5294 struct s { float f; };
5296 Such structures are passed in paired FPRs, so RSIZE
5297 will be 8 bytes. However, the structure only takes
5298 up 4 bytes of memory, so OSIZE will only be 4.
5300 (2) In combinations such as -mgp64 -msingle-float
5301 -fshort-double. Doubles passed in registers will then take
5302 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5303 stack take up UNITS_PER_WORD bytes. */
5304 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5308 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5310 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5312 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5313 if (rsize > UNITS_PER_WORD)
5315 /* [1] Emit code for: off &= -rsize. */
5316 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
5317 build_int_cst (NULL_TREE, -rsize));
5318 gimplify_assign (off, t, pre_p);
5323 /* [2] Emit code to branch if off == 0. */
5324 t = build2 (NE_EXPR, boolean_type_node, off,
5325 build_int_cst (TREE_TYPE (off), 0));
5326 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5328 /* [5] Emit code for: off -= rsize. We do this as a form of
5329 post-decrement not available to C. */
5330 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5331 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5333 /* [4] Emit code for:
5334 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5335 t = fold_convert (sizetype, t);
5336 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5337 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5338 if (BYTES_BIG_ENDIAN && rsize > size)
5340 u = size_int (rsize - size);
5341 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5343 COND_EXPR_THEN (addr) = t;
5345 if (osize > UNITS_PER_WORD)
5347 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5348 u = size_int (osize - 1);
5349 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
5350 t = fold_convert (sizetype, t);
5351 u = size_int (-osize);
5352 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5353 t = fold_convert (TREE_TYPE (ovfl), t);
5354 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5359 /* [10, 11] Emit code for:
5360 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5362 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5363 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5364 if (BYTES_BIG_ENDIAN && osize > size)
5366 u = size_int (osize - size);
5367 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5370 /* String [9] and [10, 11] together. */
5372 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5373 COND_EXPR_ELSE (addr) = t;
5375 addr = fold_convert (build_pointer_type (type), addr);
5376 addr = build_va_arg_indirect_ref (addr);
5380 addr = build_va_arg_indirect_ref (addr);
5385 /* Start a definition of function NAME. MIPS16_P indicates whether the
5386 function contains MIPS16 code. */
5389 mips_start_function_definition (const char *name, bool mips16_p)
5392 fprintf (asm_out_file, "\t.set\tmips16\n");
5394 fprintf (asm_out_file, "\t.set\tnomips16\n");
5396 if (!flag_inhibit_size_directive)
5398 fputs ("\t.ent\t", asm_out_file);
5399 assemble_name (asm_out_file, name);
5400 fputs ("\n", asm_out_file);
5403 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5405 /* Start the definition proper. */
5406 assemble_name (asm_out_file, name);
5407 fputs (":\n", asm_out_file);
5410 /* End a function definition started by mips_start_function_definition. */
5413 mips_end_function_definition (const char *name)
5415 if (!flag_inhibit_size_directive)
5417 fputs ("\t.end\t", asm_out_file);
5418 assemble_name (asm_out_file, name);
5419 fputs ("\n", asm_out_file);
5423 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5426 mips_ok_for_lazy_binding_p (rtx x)
5428 return (TARGET_USE_GOT
5429 && GET_CODE (x) == SYMBOL_REF
5430 && !SYMBOL_REF_BIND_NOW_P (x)
5431 && !mips_symbol_binds_local_p (x));
5434 /* Load function address ADDR into register DEST. TYPE is as for
5435 mips_expand_call. Return true if we used an explicit lazy-binding
5439 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5441 /* If we're generating PIC, and this call is to a global function,
5442 try to allow its address to be resolved lazily. This isn't
5443 possible for sibcalls when $gp is call-saved because the value
5444 of $gp on entry to the stub would be our caller's gp, not ours. */
5445 if (TARGET_EXPLICIT_RELOCS
5446 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5447 && mips_ok_for_lazy_binding_p (addr))
5449 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5450 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5455 mips_emit_move (dest, addr);
5460 /* Each locally-defined hard-float MIPS16 function has a local symbol
5461 associated with it. This hash table maps the function symbol (FUNC)
5462 to the local symbol (LOCAL). */
5463 struct mips16_local_alias GTY(()) {
5467 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5469 /* Hash table callbacks for mips16_local_aliases. */
5472 mips16_local_aliases_hash (const void *entry)
5474 const struct mips16_local_alias *alias;
5476 alias = (const struct mips16_local_alias *) entry;
5477 return htab_hash_string (XSTR (alias->func, 0));
5481 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5483 const struct mips16_local_alias *alias1, *alias2;
5485 alias1 = (const struct mips16_local_alias *) entry1;
5486 alias2 = (const struct mips16_local_alias *) entry2;
5487 return rtx_equal_p (alias1->func, alias2->func);
5490 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5491 Return a local alias for it, creating a new one if necessary. */
5494 mips16_local_alias (rtx func)
5496 struct mips16_local_alias *alias, tmp_alias;
5499 /* Create the hash table if this is the first call. */
5500 if (mips16_local_aliases == NULL)
5501 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5502 mips16_local_aliases_eq, NULL);
5504 /* Look up the function symbol, creating a new entry if need be. */
5505 tmp_alias.func = func;
5506 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5507 gcc_assert (slot != NULL);
5509 alias = (struct mips16_local_alias *) *slot;
5512 const char *func_name, *local_name;
5515 /* Create a new SYMBOL_REF for the local symbol. The choice of
5516 __fn_local_* is based on the __fn_stub_* names that we've
5517 traditionally used for the non-MIPS16 stub. */
5518 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5519 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5520 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5521 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5523 /* Create a new structure to represent the mapping. */
5524 alias = GGC_NEW (struct mips16_local_alias);
5526 alias->local = local;
5529 return alias->local;
5532 /* A chained list of functions for which mips16_build_call_stub has already
5533 generated a stub. NAME is the name of the function and FP_RET_P is true
5534 if the function returns a value in floating-point registers. */
5535 struct mips16_stub {
5536 struct mips16_stub *next;
5540 static struct mips16_stub *mips16_stubs;
5542 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5545 mips16_stub_function (const char *name)
5549 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5550 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5554 /* Return the two-character string that identifies floating-point
5555 return mode MODE in the name of a MIPS16 function stub. */
5558 mips16_call_stub_mode_suffix (enum machine_mode mode)
5562 else if (mode == DFmode)
5564 else if (mode == SCmode)
5566 else if (mode == DCmode)
5568 else if (mode == V2SFmode)
5574 /* Write instructions to move a 32-bit value between general register
5575 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5576 from GPREG to FPREG and 'f' to move in the opposite direction. */
5579 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5581 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5582 reg_names[gpreg], reg_names[fpreg]);
5585 /* Likewise for 64-bit values. */
5588 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5591 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5592 reg_names[gpreg], reg_names[fpreg]);
5593 else if (TARGET_FLOAT64)
5595 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5596 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5597 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5598 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5602 /* Move the least-significant word. */
5603 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5604 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5605 /* ...then the most significant word. */
5606 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5607 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5611 /* Write out code to move floating-point arguments into or out of
5612 general registers. FP_CODE is the code describing which arguments
5613 are present (see the comment above the definition of CUMULATIVE_ARGS
5614 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5617 mips_output_args_xfer (int fp_code, char direction)
5619 unsigned int gparg, fparg, f;
5620 CUMULATIVE_ARGS cum;
5622 /* This code only works for o32 and o64. */
5623 gcc_assert (TARGET_OLDABI);
5625 mips_init_cumulative_args (&cum, NULL);
5627 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5629 enum machine_mode mode;
5630 struct mips_arg_info info;
5634 else if ((f & 3) == 2)
5639 mips_get_arg_info (&info, &cum, mode, NULL, true);
5640 gparg = mips_arg_regno (&info, false);
5641 fparg = mips_arg_regno (&info, true);
5644 mips_output_32bit_xfer (direction, gparg, fparg);
5646 mips_output_64bit_xfer (direction, gparg, fparg);
5648 mips_function_arg_advance (&cum, mode, NULL, true);
5652 /* Write a MIPS16 stub for the current function. This stub is used
5653 for functions which take arguments in the floating-point registers.
5654 It is normal-mode code that moves the floating-point arguments
5655 into the general registers and then jumps to the MIPS16 code. */
5658 mips16_build_function_stub (void)
5660 const char *fnname, *alias_name, *separator;
5661 char *secname, *stubname;
5666 /* Create the name of the stub, and its unique section. */
5667 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5668 alias = mips16_local_alias (symbol);
5670 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5671 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5672 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5673 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5675 /* Build a decl for the stub. */
5676 stubdecl = build_decl (FUNCTION_DECL, get_identifier (stubname),
5677 build_function_type (void_type_node, NULL_TREE));
5678 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5679 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5681 /* Output a comment. */
5682 fprintf (asm_out_file, "\t# Stub function for %s (",
5683 current_function_name ());
5685 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5687 fprintf (asm_out_file, "%s%s", separator,
5688 (f & 3) == 1 ? "float" : "double");
5691 fprintf (asm_out_file, ")\n");
5693 /* Start the function definition. */
5694 assemble_start_function (stubdecl, stubname);
5695 mips_start_function_definition (stubname, false);
5697 /* If generating pic2 code, either set up the global pointer or
5699 if (TARGET_ABICALLS_PIC2)
5701 if (TARGET_ABSOLUTE_ABICALLS)
5702 fprintf (asm_out_file, "\t.option\tpic0\n");
5705 output_asm_insn ("%(.cpload\t%^%)", NULL);
5706 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5707 target function is. Use a local GOT access when loading the
5708 symbol, to cut down on the number of unnecessary GOT entries
5709 for stubs that aren't needed. */
5710 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
5715 /* Load the address of the MIPS16 function into $25. Do this first so
5716 that targets with coprocessor interlocks can use an MFC1 to fill the
5718 output_asm_insn ("la\t%^,%0", &symbol);
5720 /* Move the arguments from floating-point registers to general registers. */
5721 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5723 /* Jump to the MIPS16 function. */
5724 output_asm_insn ("jr\t%^", NULL);
5726 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
5727 fprintf (asm_out_file, "\t.option\tpic2\n");
5729 mips_end_function_definition (stubname);
5731 /* If the linker needs to create a dynamic symbol for the target
5732 function, it will associate the symbol with the stub (which,
5733 unlike the target function, follows the proper calling conventions).
5734 It is therefore useful to have a local alias for the target function,
5735 so that it can still be identified as MIPS16 code. As an optimization,
5736 this symbol can also be used for indirect MIPS16 references from
5737 within this file. */
5738 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
5740 switch_to_section (function_section (current_function_decl));
5743 /* The current function is a MIPS16 function that returns a value in an FPR.
5744 Copy the return value from its soft-float to its hard-float location.
5745 libgcc2 has special non-MIPS16 helper functions for each case. */
5748 mips16_copy_fpr_return_value (void)
5750 rtx fn, insn, retval;
5752 enum machine_mode return_mode;
5755 return_type = DECL_RESULT (current_function_decl);
5756 return_mode = DECL_MODE (return_type);
5758 name = ACONCAT (("__mips16_ret_",
5759 mips16_call_stub_mode_suffix (return_mode),
5761 fn = mips16_stub_function (name);
5763 /* The function takes arguments in $2 (and possibly $3), so calls
5764 to it cannot be lazily bound. */
5765 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
5767 /* Model the call as something that takes the GPR return value as
5768 argument and returns an "updated" value. */
5769 retval = gen_rtx_REG (return_mode, GP_RETURN);
5770 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
5771 const0_rtx, NULL_RTX, false);
5772 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
5775 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
5776 RETVAL is the location of the return value, or null if this is
5777 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5778 arguments and FP_CODE is the code built by mips_function_arg;
5779 see the comment above CUMULATIVE_ARGS for details.
5781 There are three alternatives:
5783 - If a stub was needed, emit the call and return the call insn itself.
5785 - If we can avoid using a stub by redirecting the call, set *FN_PTR
5786 to the new target and return null.
5788 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
5791 A stub is needed for calls to functions that, in normal mode,
5792 receive arguments in FPRs or return values in FPRs. The stub
5793 copies the arguments from their soft-float positions to their
5794 hard-float positions, calls the real function, then copies the
5795 return value from its hard-float position to its soft-float
5798 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
5799 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
5800 automatically redirects the JAL to the stub, otherwise the JAL
5801 continues to call FN directly. */
5804 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
5808 struct mips16_stub *l;
5811 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5812 we were invoked with the -msoft-float option. */
5813 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5816 /* Figure out whether the value might come back in a floating-point
5818 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
5820 /* We don't need to do anything if there were no floating-point
5821 arguments and the value will not be returned in a floating-point
5823 if (fp_code == 0 && !fp_ret_p)
5826 /* We don't need to do anything if this is a call to a special
5827 MIPS16 support function. */
5829 if (mips16_stub_function_p (fn))
5832 /* This code will only work for o32 and o64 abis. The other ABI's
5833 require more sophisticated support. */
5834 gcc_assert (TARGET_OLDABI);
5836 /* If we're calling via a function pointer, use one of the magic
5837 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5838 Each stub expects the function address to arrive in register $2. */
5839 if (GET_CODE (fn) != SYMBOL_REF
5840 || !call_insn_operand (fn, VOIDmode))
5843 rtx stub_fn, insn, addr;
5846 /* If this is a locally-defined and locally-binding function,
5847 avoid the stub by calling the local alias directly. */
5848 if (mips16_local_function_p (fn))
5850 *fn_ptr = mips16_local_alias (fn);
5854 /* Create a SYMBOL_REF for the libgcc.a function. */
5856 sprintf (buf, "__mips16_call_stub_%s_%d",
5857 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5860 sprintf (buf, "__mips16_call_stub_%d", fp_code);
5861 stub_fn = mips16_stub_function (buf);
5863 /* The function uses $2 as an argument, so calls to it
5864 cannot be lazily bound. */
5865 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
5867 /* Load the target function into $2. */
5868 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
5869 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
5871 /* Emit the call. */
5872 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
5873 args_size, NULL_RTX, lazy_p);
5875 /* Tell GCC that this call does indeed use the value of $2. */
5876 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
5878 /* If we are handling a floating-point return value, we need to
5879 save $18 in the function prologue. Putting a note on the
5880 call will mean that df_regs_ever_live_p ($18) will be true if the
5881 call is not eliminated, and we can check that in the prologue
5884 CALL_INSN_FUNCTION_USAGE (insn) =
5885 gen_rtx_EXPR_LIST (VOIDmode,
5886 gen_rtx_CLOBBER (VOIDmode,
5887 gen_rtx_REG (word_mode, 18)),
5888 CALL_INSN_FUNCTION_USAGE (insn));
5893 /* We know the function we are going to call. If we have already
5894 built a stub, we don't need to do anything further. */
5895 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5896 for (l = mips16_stubs; l != NULL; l = l->next)
5897 if (strcmp (l->name, fnname) == 0)
5902 const char *separator;
5903 char *secname, *stubname;
5904 tree stubid, stubdecl;
5907 /* If the function does not return in FPRs, the special stub
5911 If the function does return in FPRs, the stub section is named
5912 .mips16.call.fp.FNNAME
5914 Build a decl for the stub. */
5915 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
5917 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
5919 stubid = get_identifier (stubname);
5920 stubdecl = build_decl (FUNCTION_DECL, stubid,
5921 build_function_type (void_type_node, NULL_TREE));
5922 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5923 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE,
5926 /* Output a comment. */
5927 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
5929 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
5933 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5935 fprintf (asm_out_file, "%s%s", separator,
5936 (f & 3) == 1 ? "float" : "double");
5939 fprintf (asm_out_file, ")\n");
5941 /* Start the function definition. */
5942 assemble_start_function (stubdecl, stubname);
5943 mips_start_function_definition (stubname, false);
5947 /* Load the address of the MIPS16 function into $25. Do this
5948 first so that targets with coprocessor interlocks can use
5949 an MFC1 to fill the delay slot. */
5950 if (TARGET_EXPLICIT_RELOCS)
5952 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
5953 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
5956 output_asm_insn ("la\t%^,%0", &fn);
5959 /* Move the arguments from general registers to floating-point
5961 mips_output_args_xfer (fp_code, 't');
5965 /* Jump to the previously-loaded address. */
5966 output_asm_insn ("jr\t%^", NULL);
5970 /* Save the return address in $18 and call the non-MIPS16 function.
5971 The stub's caller knows that $18 might be clobbered, even though
5972 $18 is usually a call-saved register. */
5973 fprintf (asm_out_file, "\tmove\t%s,%s\n",
5974 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
5975 output_asm_insn (MIPS_CALL ("jal", &fn, 0), &fn);
5977 /* Move the result from floating-point registers to
5978 general registers. */
5979 switch (GET_MODE (retval))
5982 mips_output_32bit_xfer ('f', GP_RETURN + 1,
5983 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5986 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5987 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
5989 /* On 64-bit targets, complex floats are returned in
5990 a single GPR, such that "sd" on a suitably-aligned
5991 target would store the value correctly. */
5992 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
5993 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
5994 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
5995 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
5996 reg_names[GP_RETURN],
5997 reg_names[GP_RETURN],
5998 reg_names[GP_RETURN + 1]);
6003 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6004 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6008 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6014 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6017 #ifdef ASM_DECLARE_FUNCTION_SIZE
6018 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6021 mips_end_function_definition (stubname);
6023 /* Record this stub. */
6024 l = XNEW (struct mips16_stub);
6025 l->name = xstrdup (fnname);
6026 l->fp_ret_p = fp_ret_p;
6027 l->next = mips16_stubs;
6031 /* If we expect a floating-point return value, but we've built a
6032 stub which does not expect one, then we're in trouble. We can't
6033 use the existing stub, because it won't handle the floating-point
6034 value. We can't build a new stub, because the linker won't know
6035 which stub to use for the various calls in this object file.
6036 Fortunately, this case is illegal, since it means that a function
6037 was declared in two different ways in a single compilation. */
6038 if (fp_ret_p && !l->fp_ret_p)
6039 error ("cannot handle inconsistent calls to %qs", fnname);
6041 if (retval == NULL_RTX)
6042 insn = gen_call_internal_direct (fn, args_size);
6044 insn = gen_call_value_internal_direct (retval, fn, args_size);
6045 insn = mips_emit_call_insn (insn, fn, fn, false);
6047 /* If we are calling a stub which handles a floating-point return
6048 value, we need to arrange to save $18 in the prologue. We do this
6049 by marking the function call as using the register. The prologue
6050 will later see that it is used, and emit code to save it. */
6052 CALL_INSN_FUNCTION_USAGE (insn) =
6053 gen_rtx_EXPR_LIST (VOIDmode,
6054 gen_rtx_CLOBBER (VOIDmode,
6055 gen_rtx_REG (word_mode, 18)),
6056 CALL_INSN_FUNCTION_USAGE (insn));
6061 /* Expand a call of type TYPE. RESULT is where the result will go (null
6062 for "call"s and "sibcall"s), ADDR is the address of the function,
6063 ARGS_SIZE is the size of the arguments and AUX is the value passed
6064 to us by mips_function_arg. LAZY_P is true if this call already
6065 involves a lazily-bound function address (such as when calling
6066 functions through a MIPS16 hard-float stub).
6068 Return the call itself. */
6071 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6072 rtx args_size, rtx aux, bool lazy_p)
6074 rtx orig_addr, pattern, insn;
6077 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6078 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6081 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6086 if (!call_insn_operand (addr, VOIDmode))
6088 if (type == MIPS_CALL_EPILOGUE)
6089 addr = MIPS_EPILOGUE_TEMP (Pmode);
6091 addr = gen_reg_rtx (Pmode);
6092 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6097 rtx (*fn) (rtx, rtx);
6099 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6100 fn = gen_call_split;
6101 else if (type == MIPS_CALL_SIBCALL)
6102 fn = gen_sibcall_internal;
6104 fn = gen_call_internal;
6106 pattern = fn (addr, args_size);
6108 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6110 /* Handle return values created by mips_return_fpr_pair. */
6111 rtx (*fn) (rtx, rtx, rtx, rtx);
6114 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6115 fn = gen_call_value_multiple_split;
6116 else if (type == MIPS_CALL_SIBCALL)
6117 fn = gen_sibcall_value_multiple_internal;
6119 fn = gen_call_value_multiple_internal;
6121 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6122 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6123 pattern = fn (reg1, addr, args_size, reg2);
6127 rtx (*fn) (rtx, rtx, rtx);
6129 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6130 fn = gen_call_value_split;
6131 else if (type == MIPS_CALL_SIBCALL)
6132 fn = gen_sibcall_value_internal;
6134 fn = gen_call_value_internal;
6136 /* Handle return values created by mips_return_fpr_single. */
6137 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6138 result = XEXP (XVECEXP (result, 0, 0), 0);
6139 pattern = fn (result, addr, args_size);
6142 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6145 /* Split call instruction INSN into a $gp-clobbering call and
6146 (where necessary) an instruction to restore $gp from its save slot.
6147 CALL_PATTERN is the pattern of the new call. */
6150 mips_split_call (rtx insn, rtx call_pattern)
6154 new_insn = emit_call_insn (call_pattern);
6155 CALL_INSN_FUNCTION_USAGE (new_insn)
6156 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6157 if (!find_reg_note (insn, REG_NORETURN, 0))
6158 /* Pick a temporary register that is suitable for both MIPS16 and
6159 non-MIPS16 code. $4 and $5 are used for returning complex double
6160 values in soft-float code, so $6 is the first suitable candidate. */
6161 mips_restore_gp (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6164 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6167 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6169 if (!TARGET_SIBCALLS)
6172 /* We can't do a sibcall if the called function is a MIPS16 function
6173 because there is no direct "jx" instruction equivalent to "jalx" to
6174 switch the ISA mode. We only care about cases where the sibling
6175 and normal calls would both be direct. */
6177 && mips_use_mips16_mode_p (decl)
6178 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6181 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6182 functions could be MIPS16 ones unless an attribute explicitly tells
6184 if (TARGET_INTERLINK_MIPS16
6186 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6187 && !mips_nomips16_decl_p (decl)
6188 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6195 /* Emit code to move general operand SRC into condition-code
6196 register DEST given that SCRATCH is a scratch TFmode FPR.
6203 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6206 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6210 /* Change the source to SFmode. */
6212 src = adjust_address (src, SFmode, 0);
6213 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6214 src = gen_rtx_REG (SFmode, true_regnum (src));
6216 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6217 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6219 mips_emit_move (copy_rtx (fp1), src);
6220 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6221 emit_insn (gen_slt_sf (dest, fp2, fp1));
6224 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6225 Assume that the areas do not overlap. */
6228 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6230 HOST_WIDE_INT offset, delta;
6231 unsigned HOST_WIDE_INT bits;
6233 enum machine_mode mode;
6236 /* Work out how many bits to move at a time. If both operands have
6237 half-word alignment, it is usually better to move in half words.
6238 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6239 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6240 Otherwise move word-sized chunks. */
6241 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6242 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6243 bits = BITS_PER_WORD / 2;
6245 bits = BITS_PER_WORD;
6247 mode = mode_for_size (bits, MODE_INT, 0);
6248 delta = bits / BITS_PER_UNIT;
6250 /* Allocate a buffer for the temporary registers. */
6251 regs = XALLOCAVEC (rtx, length / delta);
6253 /* Load as many BITS-sized chunks as possible. Use a normal load if
6254 the source has enough alignment, otherwise use left/right pairs. */
6255 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6257 regs[i] = gen_reg_rtx (mode);
6258 if (MEM_ALIGN (src) >= bits)
6259 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6262 rtx part = adjust_address (src, BLKmode, offset);
6263 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6268 /* Copy the chunks to the destination. */
6269 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6270 if (MEM_ALIGN (dest) >= bits)
6271 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6274 rtx part = adjust_address (dest, BLKmode, offset);
6275 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6279 /* Mop up any left-over bytes. */
6280 if (offset < length)
6282 src = adjust_address (src, BLKmode, offset);
6283 dest = adjust_address (dest, BLKmode, offset);
6284 move_by_pieces (dest, src, length - offset,
6285 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6289 /* Helper function for doing a loop-based block operation on memory
6290 reference MEM. Each iteration of the loop will operate on LENGTH
6293 Create a new base register for use within the loop and point it to
6294 the start of MEM. Create a new memory reference that uses this
6295 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6298 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6299 rtx *loop_reg, rtx *loop_mem)
6301 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6303 /* Although the new mem does not refer to a known location,
6304 it does keep up to LENGTH bytes of alignment. */
6305 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6306 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6309 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6310 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6311 the memory regions do not overlap. */
6314 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6315 HOST_WIDE_INT bytes_per_iter)
6317 rtx label, src_reg, dest_reg, final_src;
6318 HOST_WIDE_INT leftover;
6320 leftover = length % bytes_per_iter;
6323 /* Create registers and memory references for use within the loop. */
6324 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6325 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6327 /* Calculate the value that SRC_REG should have after the last iteration
6329 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6332 /* Emit the start of the loop. */
6333 label = gen_label_rtx ();
6336 /* Emit the loop body. */
6337 mips_block_move_straight (dest, src, bytes_per_iter);
6339 /* Move on to the next block. */
6340 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6341 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6343 /* Emit the loop condition. */
6344 if (Pmode == DImode)
6345 emit_insn (gen_cmpdi (src_reg, final_src));
6347 emit_insn (gen_cmpsi (src_reg, final_src));
6348 emit_jump_insn (gen_bne (label));
6350 /* Mop up any left-over bytes. */
6352 mips_block_move_straight (dest, src, leftover);
6355 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6356 memory reference SRC to memory reference DEST. */
6359 mips_expand_block_move (rtx dest, rtx src, rtx length)
6361 if (GET_CODE (length) == CONST_INT)
6363 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6365 mips_block_move_straight (dest, src, INTVAL (length));
6370 mips_block_move_loop (dest, src, INTVAL (length),
6371 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6378 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6381 mips_expand_synci_loop (rtx begin, rtx end)
6383 rtx inc, label, cmp, cmp_result;
6385 /* Load INC with the cache line size (rdhwr INC,$1). */
6386 inc = gen_reg_rtx (SImode);
6387 emit_insn (gen_rdhwr (inc, const1_rtx));
6389 /* Loop back to here. */
6390 label = gen_label_rtx ();
6393 emit_insn (gen_synci (begin));
6395 cmp = mips_force_binary (Pmode, GTU, begin, end);
6397 mips_emit_binary (PLUS, begin, begin, inc);
6399 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6400 emit_jump_insn (gen_condjump (cmp_result, label));
6403 /* Expand a QI or HI mode atomic memory operation.
6405 GENERATOR contains a pointer to the gen_* function that generates
6406 the SI mode underlying atomic operation using masks that we
6409 RESULT is the return register for the operation. Its value is NULL
6412 MEM is the location of the atomic access.
6414 OLDVAL is the first operand for the operation.
6416 NEWVAL is the optional second operand for the operation. Its value
6417 is NULL if unused. */
6420 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6421 rtx result, rtx mem, rtx oldval, rtx newval)
6423 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6424 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6426 enum machine_mode mode;
6428 mode = GET_MODE (mem);
6430 /* Compute the address of the containing SImode value. */
6431 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6432 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6433 force_reg (Pmode, GEN_INT (-4)));
6435 /* Create a memory reference for it. */
6436 memsi = gen_rtx_MEM (SImode, memsi_addr);
6437 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6438 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6440 /* Work out the byte offset of the QImode or HImode value,
6441 counting from the least significant byte. */
6442 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6443 if (TARGET_BIG_ENDIAN)
6444 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6446 /* Multiply by eight to convert the shift value from bytes to bits. */
6447 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6449 /* Make the final shift an SImode value, so that it can be used in
6450 SImode operations. */
6451 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6453 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6454 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6455 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6456 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6458 /* Compute the equivalent exclusive mask. */
6459 inverted_mask = gen_reg_rtx (SImode);
6460 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6461 gen_rtx_NOT (SImode, mask)));
6463 /* Shift the old value into place. */
6464 if (oldval != const0_rtx)
6466 oldval = convert_modes (SImode, mode, oldval, true);
6467 oldval = force_reg (SImode, oldval);
6468 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6471 /* Do the same for the new value. */
6472 if (newval && newval != const0_rtx)
6474 newval = convert_modes (SImode, mode, newval, true);
6475 newval = force_reg (SImode, newval);
6476 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6479 /* Do the SImode atomic access. */
6481 res = gen_reg_rtx (SImode);
6483 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6485 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6487 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6493 /* Shift and convert the result. */
6494 mips_emit_binary (AND, res, res, mask);
6495 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6496 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6500 /* Return true if it is possible to use left/right accesses for a
6501 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6502 returning true, update *OP, *LEFT and *RIGHT as follows:
6504 *OP is a BLKmode reference to the whole field.
6506 *LEFT is a QImode reference to the first byte if big endian or
6507 the last byte if little endian. This address can be used in the
6508 left-side instructions (LWL, SWL, LDL, SDL).
6510 *RIGHT is a QImode reference to the opposite end of the field and
6511 can be used in the patterning right-side instruction. */
6514 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6515 rtx *left, rtx *right)
6519 /* Check that the operand really is a MEM. Not all the extv and
6520 extzv predicates are checked. */
6524 /* Check that the size is valid. */
6525 if (width != 32 && (!TARGET_64BIT || width != 64))
6528 /* We can only access byte-aligned values. Since we are always passed
6529 a reference to the first byte of the field, it is not necessary to
6530 do anything with BITPOS after this check. */
6531 if (bitpos % BITS_PER_UNIT != 0)
6534 /* Reject aligned bitfields: we want to use a normal load or store
6535 instead of a left/right pair. */
6536 if (MEM_ALIGN (*op) >= width)
6539 /* Adjust *OP to refer to the whole field. This also has the effect
6540 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6541 *op = adjust_address (*op, BLKmode, 0);
6542 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6544 /* Get references to both ends of the field. We deliberately don't
6545 use the original QImode *OP for FIRST since the new BLKmode one
6546 might have a simpler address. */
6547 first = adjust_address (*op, QImode, 0);
6548 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6550 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6551 correspond to the MSB and RIGHT to the LSB. */
6552 if (TARGET_BIG_ENDIAN)
6553 *left = first, *right = last;
6555 *left = last, *right = first;
6560 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6561 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6562 the operation is the equivalent of:
6564 (set DEST (*_extract SRC WIDTH BITPOS))
6566 Return true on success. */
6569 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6570 HOST_WIDE_INT bitpos)
6572 rtx left, right, temp;
6574 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6575 be a paradoxical word_mode subreg. This is the only case in which
6576 we allow the destination to be larger than the source. */
6577 if (GET_CODE (dest) == SUBREG
6578 && GET_MODE (dest) == DImode
6579 && GET_MODE (SUBREG_REG (dest)) == SImode)
6580 dest = SUBREG_REG (dest);
6582 /* After the above adjustment, the destination must be the same
6583 width as the source. */
6584 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6587 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6590 temp = gen_reg_rtx (GET_MODE (dest));
6591 if (GET_MODE (dest) == DImode)
6593 emit_insn (gen_mov_ldl (temp, src, left));
6594 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6598 emit_insn (gen_mov_lwl (temp, src, left));
6599 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6604 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6605 BITPOS and SRC are the operands passed to the expander; the operation
6606 is the equivalent of:
6608 (set (zero_extract DEST WIDTH BITPOS) SRC)
6610 Return true on success. */
6613 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6614 HOST_WIDE_INT bitpos)
6617 enum machine_mode mode;
6619 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6622 mode = mode_for_size (width, MODE_INT, 0);
6623 src = gen_lowpart (mode, src);
6626 emit_insn (gen_mov_sdl (dest, src, left));
6627 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6631 emit_insn (gen_mov_swl (dest, src, left));
6632 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6637 /* Return true if X is a MEM with the same size as MODE. */
6640 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6647 size = MEM_SIZE (x);
6648 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6651 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6652 source of an "ext" instruction or the destination of an "ins"
6653 instruction. OP must be a register operand and the following
6654 conditions must hold:
6656 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6657 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6658 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6660 Also reject lengths equal to a word as they are better handled
6661 by the move patterns. */
6664 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6666 if (!ISA_HAS_EXT_INS
6667 || !register_operand (op, VOIDmode)
6668 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6671 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6674 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6680 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6681 operation if MAXLEN is the maxium length of consecutive bits that
6682 can make up MASK. MODE is the mode of the operation. See
6683 mask_low_and_shift_len for the actual definition. */
6686 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
6688 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
6691 /* The canonical form of a mask-low-and-shift-left operation is
6692 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
6693 cleared. Thus we need to shift MASK to the right before checking if it
6694 is a valid mask value. MODE is the mode of the operation. If true
6695 return the length of the mask, otherwise return -1. */
6698 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
6700 HOST_WIDE_INT shval;
6702 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
6703 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
6706 /* Return true if -msplit-addresses is selected and should be honored.
6708 -msplit-addresses is a half-way house between explicit relocations
6709 and the traditional assembler macros. It can split absolute 32-bit
6710 symbolic constants into a high/lo_sum pair but uses macros for other
6713 Like explicit relocation support for REL targets, it relies
6714 on GNU extensions in the assembler and the linker.
6716 Although this code should work for -O0, it has traditionally
6717 been treated as an optimization. */
6720 mips_split_addresses_p (void)
6722 return (TARGET_SPLIT_ADDRESSES
6726 && !ABI_HAS_64BIT_SYMBOLS);
6729 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6732 mips_init_relocs (void)
6734 memset (mips_split_p, '\0', sizeof (mips_split_p));
6735 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
6736 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6737 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6739 if (ABI_HAS_64BIT_SYMBOLS)
6741 if (TARGET_EXPLICIT_RELOCS)
6743 mips_split_p[SYMBOL_64_HIGH] = true;
6744 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6745 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6747 mips_split_p[SYMBOL_64_MID] = true;
6748 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6749 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6751 mips_split_p[SYMBOL_64_LOW] = true;
6752 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6753 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6755 mips_split_p[SYMBOL_ABSOLUTE] = true;
6756 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6761 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6763 mips_split_p[SYMBOL_ABSOLUTE] = true;
6764 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6765 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6767 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6773 /* The high part is provided by a pseudo copy of $gp. */
6774 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6775 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6777 else if (TARGET_EXPLICIT_RELOCS)
6778 /* Small data constants are kept whole until after reload,
6779 then lowered by mips_rewrite_small_data. */
6780 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6782 if (TARGET_EXPLICIT_RELOCS)
6784 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6787 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6788 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6792 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6793 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6796 /* Expose the use of $28 as soon as possible. */
6797 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
6801 /* The HIGH and LO_SUM are matched by special .md patterns. */
6802 mips_split_p[SYMBOL_GOT_DISP] = true;
6804 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6805 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6806 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6808 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6809 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6810 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6815 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6817 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6818 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6820 /* Expose the use of $28 as soon as possible. */
6821 mips_split_p[SYMBOL_GOT_DISP] = true;
6827 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6828 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6829 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6832 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6833 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6835 mips_split_p[SYMBOL_DTPREL] = true;
6836 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6837 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6839 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6841 mips_split_p[SYMBOL_TPREL] = true;
6842 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6843 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6845 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6848 /* If OP is an UNSPEC address, return the address to which it refers,
6849 otherwise return OP itself. */
6852 mips_strip_unspec_address (rtx op)
6856 split_const (op, &base, &offset);
6857 if (UNSPEC_ADDRESS_P (base))
6858 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6862 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6863 in context CONTEXT. RELOCS is the array of relocations to use. */
6866 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6867 const char **relocs)
6869 enum mips_symbol_type symbol_type;
6872 symbol_type = mips_classify_symbolic_expression (op, context);
6873 gcc_assert (relocs[symbol_type]);
6875 fputs (relocs[symbol_type], file);
6876 output_addr_const (file, mips_strip_unspec_address (op));
6877 for (p = relocs[symbol_type]; *p != 0; p++)
6882 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6883 The punctuation characters are:
6885 '(' Start a nested ".set noreorder" block.
6886 ')' End a nested ".set noreorder" block.
6887 '[' Start a nested ".set noat" block.
6888 ']' End a nested ".set noat" block.
6889 '<' Start a nested ".set nomacro" block.
6890 '>' End a nested ".set nomacro" block.
6891 '*' Behave like %(%< if generating a delayed-branch sequence.
6892 '#' Print a nop if in a ".set noreorder" block.
6893 '/' Like '#', but do nothing within a delayed-branch sequence.
6894 '?' Print "l" if mips_branch_likely is true
6895 '.' Print the name of the register with a hard-wired zero (zero or $0).
6896 '@' Print the name of the assembler temporary register (at or $1).
6897 '^' Print the name of the pic call-through register (t9 or $25).
6898 '+' Print the name of the gp register (usually gp or $28).
6899 '$' Print the name of the stack pointer register (sp or $29).
6900 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6901 '-' Print ".set pop" under the same conditions for '|'.
6903 See also mips_init_print_operand_pucnt. */
6906 mips_print_operand_punctuation (FILE *file, int ch)
6911 if (set_noreorder++ == 0)
6912 fputs (".set\tnoreorder\n\t", file);
6916 gcc_assert (set_noreorder > 0);
6917 if (--set_noreorder == 0)
6918 fputs ("\n\t.set\treorder", file);
6922 if (set_noat++ == 0)
6923 fputs (".set\tnoat\n\t", file);
6927 gcc_assert (set_noat > 0);
6928 if (--set_noat == 0)
6929 fputs ("\n\t.set\tat", file);
6933 if (set_nomacro++ == 0)
6934 fputs (".set\tnomacro\n\t", file);
6938 gcc_assert (set_nomacro > 0);
6939 if (--set_nomacro == 0)
6940 fputs ("\n\t.set\tmacro", file);
6944 if (final_sequence != 0)
6946 mips_print_operand_punctuation (file, '(');
6947 mips_print_operand_punctuation (file, '<');
6952 if (set_noreorder != 0)
6953 fputs ("\n\tnop", file);
6957 /* Print an extra newline so that the delayed insn is separated
6958 from the following ones. This looks neater and is consistent
6959 with non-nop delayed sequences. */
6960 if (set_noreorder != 0 && final_sequence == 0)
6961 fputs ("\n\tnop\n", file);
6965 if (mips_branch_likely)
6970 fputs (reg_names[GP_REG_FIRST + 0], file);
6974 fputs (reg_names[GP_REG_FIRST + 1], file);
6978 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
6982 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
6986 fputs (reg_names[STACK_POINTER_REGNUM], file);
6991 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
6996 fputs ("\n\t.set\tpop", file);
7005 /* Initialize mips_print_operand_punct. */
7008 mips_init_print_operand_punct (void)
7012 for (p = "()[]<>*#/?.@^+$|-"; *p; p++)
7013 mips_print_operand_punct[(unsigned char) *p] = true;
7016 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7017 associated with condition CODE. Print the condition part of the
7021 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7035 /* Conveniently, the MIPS names for these conditions are the same
7036 as their RTL equivalents. */
7037 fputs (GET_RTX_NAME (code), file);
7041 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7046 /* Likewise floating-point branches. */
7049 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7054 fputs ("c1f", file);
7058 fputs ("c1t", file);
7062 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7067 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7069 'X' Print CONST_INT OP in hexadecimal format.
7070 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7071 'd' Print CONST_INT OP in decimal.
7072 'm' Print one less than CONST_INT OP in decimal.
7073 'h' Print the high-part relocation associated with OP, after stripping
7075 'R' Print the low-part relocation associated with OP.
7076 'C' Print the integer branch condition for comparison OP.
7077 'N' Print the inverse of the integer branch condition for comparison OP.
7078 'F' Print the FPU branch condition for comparison OP.
7079 'W' Print the inverse of the FPU branch condition for comparison OP.
7080 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7081 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7082 't' Like 'T', but with the EQ/NE cases reversed
7083 'Y' Print mips_fp_conditions[INTVAL (OP)]
7084 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7085 'q' Print a DSP accumulator register.
7086 'D' Print the second part of a double-word register or memory operand.
7087 'L' Print the low-order register in a double-word register operand.
7088 'M' Print high-order register in a double-word register operand.
7089 'z' Print $0 if OP is zero, otherwise print OP normally. */
7092 mips_print_operand (FILE *file, rtx op, int letter)
7096 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7098 mips_print_operand_punctuation (file, letter);
7103 code = GET_CODE (op);
7108 if (GET_CODE (op) == CONST_INT)
7109 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7111 output_operand_lossage ("invalid use of '%%%c'", letter);
7115 if (GET_CODE (op) == CONST_INT)
7116 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7118 output_operand_lossage ("invalid use of '%%%c'", letter);
7122 if (GET_CODE (op) == CONST_INT)
7123 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7125 output_operand_lossage ("invalid use of '%%%c'", letter);
7129 if (GET_CODE (op) == CONST_INT)
7130 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7132 output_operand_lossage ("invalid use of '%%%c'", letter);
7138 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7142 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7146 mips_print_int_branch_condition (file, code, letter);
7150 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7154 mips_print_float_branch_condition (file, code, letter);
7158 mips_print_float_branch_condition (file, reverse_condition (code),
7165 int truth = (code == NE) == (letter == 'T');
7166 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7171 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7172 fputs (mips_fp_conditions[UINTVAL (op)], file);
7174 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7181 mips_print_operand (file, op, 0);
7187 if (code == REG && MD_REG_P (REGNO (op)))
7188 fprintf (file, "$ac0");
7189 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7190 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7192 output_operand_lossage ("invalid use of '%%%c'", letter);
7200 unsigned int regno = REGNO (op);
7201 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7202 || (letter == 'L' && TARGET_BIG_ENDIAN)
7205 fprintf (file, "%s", reg_names[regno]);
7211 output_address (plus_constant (XEXP (op, 0), 4));
7213 output_address (XEXP (op, 0));
7217 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7218 fputs (reg_names[GP_REG_FIRST], file);
7219 else if (CONST_GP_P (op))
7220 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7222 output_addr_const (file, mips_strip_unspec_address (op));
7228 /* Output address operand X to FILE. */
7231 mips_print_operand_address (FILE *file, rtx x)
7233 struct mips_address_info addr;
7235 if (mips_classify_address (&addr, x, word_mode, true))
7239 mips_print_operand (file, addr.offset, 0);
7240 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7243 case ADDRESS_LO_SUM:
7244 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7246 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7249 case ADDRESS_CONST_INT:
7250 output_addr_const (file, x);
7251 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7254 case ADDRESS_SYMBOLIC:
7255 output_addr_const (file, mips_strip_unspec_address (x));
7261 /* Implement TARGET_ENCODE_SECTION_INFO. */
7264 mips_encode_section_info (tree decl, rtx rtl, int first)
7266 default_encode_section_info (decl, rtl, first);
7268 if (TREE_CODE (decl) == FUNCTION_DECL)
7270 rtx symbol = XEXP (rtl, 0);
7271 tree type = TREE_TYPE (decl);
7273 /* Encode whether the symbol is short or long. */
7274 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7275 || mips_far_type_p (type))
7276 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7280 /* Implement TARGET_SELECT_RTX_SECTION. */
7283 mips_select_rtx_section (enum machine_mode mode, rtx x,
7284 unsigned HOST_WIDE_INT align)
7286 /* ??? Consider using mergeable small data sections. */
7287 if (mips_rtx_constant_in_small_data_p (mode))
7288 return get_named_section (NULL, ".sdata", 0);
7290 return default_elf_select_rtx_section (mode, x, align);
7293 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7295 The complication here is that, with the combination TARGET_ABICALLS
7296 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7297 absolute addresses, and should therefore not be included in the
7298 read-only part of a DSO. Handle such cases by selecting a normal
7299 data section instead of a read-only one. The logic apes that in
7300 default_function_rodata_section. */
7303 mips_function_rodata_section (tree decl)
7305 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7306 return default_function_rodata_section (decl);
7308 if (decl && DECL_SECTION_NAME (decl))
7310 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7311 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7313 char *rname = ASTRDUP (name);
7315 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7317 else if (flag_function_sections
7318 && flag_data_sections
7319 && strncmp (name, ".text.", 6) == 0)
7321 char *rname = ASTRDUP (name);
7322 memcpy (rname + 1, "data", 4);
7323 return get_section (rname, SECTION_WRITE, decl);
7326 return data_section;
7329 /* Implement TARGET_IN_SMALL_DATA_P. */
7332 mips_in_small_data_p (const_tree decl)
7334 unsigned HOST_WIDE_INT size;
7336 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7339 /* We don't yet generate small-data references for -mabicalls
7340 or VxWorks RTP code. See the related -G handling in
7341 mips_override_options. */
7342 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7345 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7349 /* Reject anything that isn't in a known small-data section. */
7350 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7351 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7354 /* If a symbol is defined externally, the assembler will use the
7355 usual -G rules when deciding how to implement macros. */
7356 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7359 else if (TARGET_EMBEDDED_DATA)
7361 /* Don't put constants into the small data section: we want them
7362 to be in ROM rather than RAM. */
7363 if (TREE_CODE (decl) != VAR_DECL)
7366 if (TREE_READONLY (decl)
7367 && !TREE_SIDE_EFFECTS (decl)
7368 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7372 /* Enforce -mlocal-sdata. */
7373 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7376 /* Enforce -mextern-sdata. */
7377 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7379 if (DECL_EXTERNAL (decl))
7381 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7385 /* We have traditionally not treated zero-sized objects as small data,
7386 so this is now effectively part of the ABI. */
7387 size = int_size_in_bytes (TREE_TYPE (decl));
7388 return size > 0 && size <= mips_small_data_threshold;
7391 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7392 anchors for small data: the GP register acts as an anchor in that
7393 case. We also don't want to use them for PC-relative accesses,
7394 where the PC acts as an anchor. */
7397 mips_use_anchors_for_symbol_p (const_rtx symbol)
7399 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7401 case SYMBOL_PC_RELATIVE:
7402 case SYMBOL_GP_RELATIVE:
7406 return default_use_anchors_for_symbol_p (symbol);
7410 /* The MIPS debug format wants all automatic variables and arguments
7411 to be in terms of the virtual frame pointer (stack pointer before
7412 any adjustment in the function), while the MIPS 3.0 linker wants
7413 the frame pointer to be the stack pointer after the initial
7414 adjustment. So, we do the adjustment here. The arg pointer (which
7415 is eliminated) points to the virtual frame pointer, while the frame
7416 pointer (which may be eliminated) points to the stack pointer after
7417 the initial adjustments. */
7420 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7422 rtx offset2 = const0_rtx;
7423 rtx reg = eliminate_constant_term (addr, &offset2);
7426 offset = INTVAL (offset2);
7428 if (reg == stack_pointer_rtx
7429 || reg == frame_pointer_rtx
7430 || reg == hard_frame_pointer_rtx)
7432 offset -= cfun->machine->frame.total_size;
7433 if (reg == hard_frame_pointer_rtx)
7434 offset += cfun->machine->frame.hard_frame_pointer_offset;
7437 /* sdbout_parms does not want this to crash for unrecognized cases. */
7439 else if (reg != arg_pointer_rtx)
7440 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7447 /* Implement ASM_OUTPUT_EXTERNAL. */
7450 mips_output_external (FILE *file, tree decl, const char *name)
7452 default_elf_asm_output_external (file, decl, name);
7454 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7455 set in order to avoid putting out names that are never really
7457 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7459 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7461 /* When using assembler macros, emit .extern directives for
7462 all small-data externs so that the assembler knows how
7465 In most cases it would be safe (though pointless) to emit
7466 .externs for other symbols too. One exception is when an
7467 object is within the -G limit but declared by the user to
7468 be in a section other than .sbss or .sdata. */
7469 fputs ("\t.extern\t", file);
7470 assemble_name (file, name);
7471 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7472 int_size_in_bytes (TREE_TYPE (decl)));
7474 else if (TARGET_IRIX
7475 && mips_abi == ABI_32
7476 && TREE_CODE (decl) == FUNCTION_DECL)
7478 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7479 `.global name .text' directive for every used but
7480 undefined function. If we don't, the linker may perform
7481 an optimization (skipping over the insns that set $gp)
7482 when it is unsafe. */
7483 fputs ("\t.globl ", file);
7484 assemble_name (file, name);
7485 fputs (" .text\n", file);
7490 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7493 mips_output_filename (FILE *stream, const char *name)
7495 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7497 if (write_symbols == DWARF2_DEBUG)
7499 else if (mips_output_filename_first_time)
7501 mips_output_filename_first_time = 0;
7502 num_source_filenames += 1;
7503 current_function_file = name;
7504 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7505 output_quoted_string (stream, name);
7506 putc ('\n', stream);
7508 /* If we are emitting stabs, let dbxout.c handle this (except for
7509 the mips_output_filename_first_time case). */
7510 else if (write_symbols == DBX_DEBUG)
7512 else if (name != current_function_file
7513 && strcmp (name, current_function_file) != 0)
7515 num_source_filenames += 1;
7516 current_function_file = name;
7517 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7518 output_quoted_string (stream, name);
7519 putc ('\n', stream);
7523 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7525 static void ATTRIBUTE_UNUSED
7526 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7531 fputs ("\t.dtprelword\t", file);
7535 fputs ("\t.dtpreldword\t", file);
7541 output_addr_const (file, x);
7542 fputs ("+0x8000", file);
7545 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7548 mips_dwarf_register_span (rtx reg)
7551 enum machine_mode mode;
7553 /* By default, GCC maps increasing register numbers to increasing
7554 memory locations, but paired FPRs are always little-endian,
7555 regardless of the prevailing endianness. */
7556 mode = GET_MODE (reg);
7557 if (FP_REG_P (REGNO (reg))
7558 && TARGET_BIG_ENDIAN
7559 && MAX_FPRS_PER_FMT > 1
7560 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7562 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7563 high = mips_subword (reg, true);
7564 low = mips_subword (reg, false);
7565 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7571 /* Implement ASM_OUTPUT_ASCII. */
7574 mips_output_ascii (FILE *stream, const char *string, size_t len)
7580 fprintf (stream, "\t.ascii\t\"");
7581 for (i = 0; i < len; i++)
7585 c = (unsigned char) string[i];
7588 if (c == '\\' || c == '\"')
7590 putc ('\\', stream);
7598 fprintf (stream, "\\%03o", c);
7602 if (cur_pos > 72 && i+1 < len)
7605 fprintf (stream, "\"\n\t.ascii\t\"");
7608 fprintf (stream, "\"\n");
7611 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7612 macros, mark the symbol as written so that mips_asm_output_external
7613 won't emit an .extern for it. STREAM is the output file, NAME is the
7614 name of the symbol, INIT_STRING is the string that should be written
7615 before the symbol and FINAL_STRING is the string that should be
7616 written after it. FINAL_STRING is a printf format that consumes the
7617 remaining arguments. */
7620 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7621 const char *final_string, ...)
7625 fputs (init_string, stream);
7626 assemble_name (stream, name);
7627 va_start (ap, final_string);
7628 vfprintf (stream, final_string, ap);
7631 if (!TARGET_EXPLICIT_RELOCS)
7633 tree name_tree = get_identifier (name);
7634 TREE_ASM_WRITTEN (name_tree) = 1;
7638 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7639 NAME is the name of the object and ALIGN is the required alignment
7640 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7641 alignment argument. */
7644 mips_declare_common_object (FILE *stream, const char *name,
7645 const char *init_string,
7646 unsigned HOST_WIDE_INT size,
7647 unsigned int align, bool takes_alignment_p)
7649 if (!takes_alignment_p)
7651 size += (align / BITS_PER_UNIT) - 1;
7652 size -= size % (align / BITS_PER_UNIT);
7653 mips_declare_object (stream, name, init_string,
7654 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7657 mips_declare_object (stream, name, init_string,
7658 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7659 size, align / BITS_PER_UNIT);
7662 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7663 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7666 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7667 unsigned HOST_WIDE_INT size,
7670 /* If the target wants uninitialized const declarations in
7671 .rdata then don't put them in .comm. */
7672 if (TARGET_EMBEDDED_DATA
7673 && TARGET_UNINIT_CONST_IN_RODATA
7674 && TREE_CODE (decl) == VAR_DECL
7675 && TREE_READONLY (decl)
7676 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7678 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7679 targetm.asm_out.globalize_label (stream, name);
7681 switch_to_section (readonly_data_section);
7682 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7683 mips_declare_object (stream, name, "",
7684 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7688 mips_declare_common_object (stream, name, "\n\t.comm\t",
7692 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7693 extern int size_directive_output;
7695 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7696 definitions except that it uses mips_declare_object to emit the label. */
7699 mips_declare_object_name (FILE *stream, const char *name,
7700 tree decl ATTRIBUTE_UNUSED)
7702 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7703 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7706 size_directive_output = 0;
7707 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7711 size_directive_output = 1;
7712 size = int_size_in_bytes (TREE_TYPE (decl));
7713 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7716 mips_declare_object (stream, name, "", ":\n");
7719 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7722 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7726 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7727 if (!flag_inhibit_size_directive
7728 && DECL_SIZE (decl) != 0
7731 && DECL_INITIAL (decl) == error_mark_node
7732 && !size_directive_output)
7736 size_directive_output = 1;
7737 size = int_size_in_bytes (TREE_TYPE (decl));
7738 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7743 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7744 with the current ABI. */
7747 mips_mdebug_abi_name (void)
7760 return TARGET_64BIT ? "eabi64" : "eabi32";
7766 /* Implement TARGET_ASM_FILE_START. */
7769 mips_file_start (void)
7771 default_file_start ();
7773 /* Generate a special section to describe the ABI switches used to
7774 produce the resultant binary. This is unnecessary on IRIX and
7775 causes unwanted warnings from the native linker. */
7778 /* Record the ABI itself. Modern versions of binutils encode
7779 this information in the ELF header flags, but GDB needs the
7780 information in order to correctly debug binaries produced by
7781 older binutils. See the function mips_gdbarch_init in
7783 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7784 mips_mdebug_abi_name ());
7786 /* There is no ELF header flag to distinguish long32 forms of the
7787 EABI from long64 forms. Emit a special section to help tools
7788 such as GDB. Do the same for o64, which is sometimes used with
7790 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7791 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7792 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7794 #ifdef HAVE_AS_GNU_ATTRIBUTE
7795 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7796 (TARGET_HARD_FLOAT_ABI
7797 ? (TARGET_DOUBLE_FLOAT
7798 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
7802 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7803 if (TARGET_ABICALLS)
7805 fprintf (asm_out_file, "\t.abicalls\n");
7806 if (TARGET_ABICALLS_PIC0)
7807 fprintf (asm_out_file, "\t.option\tpic0\n");
7810 if (flag_verbose_asm)
7811 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7813 mips_small_data_threshold, mips_arch_info->name, mips_isa);
7816 /* Make the last instruction frame-related and note that it performs
7817 the operation described by FRAME_PATTERN. */
7820 mips_set_frame_expr (rtx frame_pattern)
7824 insn = get_last_insn ();
7825 RTX_FRAME_RELATED_P (insn) = 1;
7826 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7831 /* Return a frame-related rtx that stores REG at MEM.
7832 REG must be a single register. */
7835 mips_frame_set (rtx mem, rtx reg)
7839 /* If we're saving the return address register and the DWARF return
7840 address column differs from the hard register number, adjust the
7841 note reg to refer to the former. */
7842 if (REGNO (reg) == GP_REG_FIRST + 31
7843 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7844 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7846 set = gen_rtx_SET (VOIDmode, mem, reg);
7847 RTX_FRAME_RELATED_P (set) = 1;
7852 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7853 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7854 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7855 static const unsigned char mips16e_s2_s8_regs[] = {
7856 30, 23, 22, 21, 20, 19, 18
7858 static const unsigned char mips16e_a0_a3_regs[] = {
7862 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7863 ordered from the uppermost in memory to the lowest in memory. */
7864 static const unsigned char mips16e_save_restore_regs[] = {
7865 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7868 /* Return the index of the lowest X in the range [0, SIZE) for which
7869 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7872 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7877 for (i = 0; i < size; i++)
7878 if (BITSET_P (mask, regs[i]))
7884 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7885 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7886 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7887 is true for all indexes (X, SIZE). */
7890 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7891 unsigned int size, unsigned int *num_regs_ptr)
7895 i = mips16e_find_first_register (*mask_ptr, regs, size);
7896 for (i++; i < size; i++)
7897 if (!BITSET_P (*mask_ptr, regs[i]))
7900 *mask_ptr |= 1 << regs[i];
7904 /* Return a simplified form of X using the register values in REG_VALUES.
7905 REG_VALUES[R] is the last value assigned to hard register R, or null
7906 if R has not been modified.
7908 This function is rather limited, but is good enough for our purposes. */
7911 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7913 x = avoid_constant_pool_reference (x);
7917 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7918 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7919 x0, GET_MODE (XEXP (x, 0)));
7922 if (ARITHMETIC_P (x))
7924 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7925 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7926 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7930 && reg_values[REGNO (x)]
7931 && !rtx_unstable_p (reg_values[REGNO (x)]))
7932 return reg_values[REGNO (x)];
7937 /* Return true if (set DEST SRC) stores an argument register into its
7938 caller-allocated save slot, storing the number of that argument
7939 register in *REGNO_PTR if so. REG_VALUES is as for
7940 mips16e_collect_propagate_value. */
7943 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7944 unsigned int *regno_ptr)
7946 unsigned int argno, regno;
7947 HOST_WIDE_INT offset, required_offset;
7950 /* Check that this is a word-mode store. */
7951 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7954 /* Check that the register being saved is an unmodified argument
7956 regno = REGNO (src);
7957 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
7959 argno = regno - GP_ARG_FIRST;
7961 /* Check whether the address is an appropriate stack-pointer or
7962 frame-pointer access. */
7963 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7964 mips_split_plus (addr, &base, &offset);
7965 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7966 if (base == hard_frame_pointer_rtx)
7967 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
7968 else if (base != stack_pointer_rtx)
7970 if (offset != required_offset)
7977 /* A subroutine of mips_expand_prologue, called only when generating
7978 MIPS16e SAVE instructions. Search the start of the function for any
7979 instructions that save argument registers into their caller-allocated
7980 save slots. Delete such instructions and return a value N such that
7981 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7982 instructions redundant. */
7985 mips16e_collect_argument_saves (void)
7987 rtx reg_values[FIRST_PSEUDO_REGISTER];
7988 rtx insn, next, set, dest, src;
7989 unsigned int nargs, regno;
7991 push_topmost_sequence ();
7993 memset (reg_values, 0, sizeof (reg_values));
7994 for (insn = get_insns (); insn; insn = next)
7996 next = NEXT_INSN (insn);
8003 set = PATTERN (insn);
8004 if (GET_CODE (set) != SET)
8007 dest = SET_DEST (set);
8008 src = SET_SRC (set);
8009 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8011 if (!BITSET_P (cfun->machine->frame.mask, regno))
8014 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8017 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8018 reg_values[REGNO (dest)]
8019 = mips16e_collect_propagate_value (src, reg_values);
8023 pop_topmost_sequence ();
8028 /* Return a move between register REGNO and memory location SP + OFFSET.
8029 Make the move a load if RESTORE_P, otherwise make it a frame-related
8033 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8038 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8039 reg = gen_rtx_REG (SImode, regno);
8041 ? gen_rtx_SET (VOIDmode, reg, mem)
8042 : mips_frame_set (mem, reg));
8045 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8046 The instruction must:
8048 - Allocate or deallocate SIZE bytes in total; SIZE is known
8051 - Save or restore as many registers in *MASK_PTR as possible.
8052 The instruction saves the first registers at the top of the
8053 allocated area, with the other registers below it.
8055 - Save NARGS argument registers above the allocated area.
8057 (NARGS is always zero if RESTORE_P.)
8059 The SAVE and RESTORE instructions cannot save and restore all general
8060 registers, so there may be some registers left over for the caller to
8061 handle. Destructively modify *MASK_PTR so that it contains the registers
8062 that still need to be saved or restored. The caller can save these
8063 registers in the memory immediately below *OFFSET_PTR, which is a
8064 byte offset from the bottom of the allocated stack area. */
8067 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8068 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8072 HOST_WIDE_INT offset, top_offset;
8073 unsigned int i, regno;
8076 gcc_assert (cfun->machine->frame.num_fp == 0);
8078 /* Calculate the number of elements in the PARALLEL. We need one element
8079 for the stack adjustment, one for each argument register save, and one
8080 for each additional register move. */
8082 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8083 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8086 /* Create the final PARALLEL. */
8087 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8090 /* Add the stack pointer adjustment. */
8091 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8092 plus_constant (stack_pointer_rtx,
8093 restore_p ? size : -size));
8094 RTX_FRAME_RELATED_P (set) = 1;
8095 XVECEXP (pattern, 0, n++) = set;
8097 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8098 top_offset = restore_p ? size : 0;
8100 /* Save the arguments. */
8101 for (i = 0; i < nargs; i++)
8103 offset = top_offset + i * UNITS_PER_WORD;
8104 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8105 XVECEXP (pattern, 0, n++) = set;
8108 /* Then fill in the other register moves. */
8109 offset = top_offset;
8110 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8112 regno = mips16e_save_restore_regs[i];
8113 if (BITSET_P (*mask_ptr, regno))
8115 offset -= UNITS_PER_WORD;
8116 set = mips16e_save_restore_reg (restore_p, offset, regno);
8117 XVECEXP (pattern, 0, n++) = set;
8118 *mask_ptr &= ~(1 << regno);
8122 /* Tell the caller what offset it should use for the remaining registers. */
8123 *offset_ptr = size + (offset - top_offset);
8125 gcc_assert (n == XVECLEN (pattern, 0));
8130 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8131 pointer. Return true if PATTERN matches the kind of instruction
8132 generated by mips16e_build_save_restore. If INFO is nonnull,
8133 initialize it when returning true. */
8136 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8137 struct mips16e_save_restore_info *info)
8139 unsigned int i, nargs, mask, extra;
8140 HOST_WIDE_INT top_offset, save_offset, offset;
8141 rtx set, reg, mem, base;
8144 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8147 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8148 top_offset = adjust > 0 ? adjust : 0;
8150 /* Interpret all other members of the PARALLEL. */
8151 save_offset = top_offset - UNITS_PER_WORD;
8155 for (n = 1; n < XVECLEN (pattern, 0); n++)
8157 /* Check that we have a SET. */
8158 set = XVECEXP (pattern, 0, n);
8159 if (GET_CODE (set) != SET)
8162 /* Check that the SET is a load (if restoring) or a store
8164 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8168 /* Check that the address is the sum of the stack pointer and a
8169 possibly-zero constant offset. */
8170 mips_split_plus (XEXP (mem, 0), &base, &offset);
8171 if (base != stack_pointer_rtx)
8174 /* Check that SET's other operand is a register. */
8175 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8179 /* Check for argument saves. */
8180 if (offset == top_offset + nargs * UNITS_PER_WORD
8181 && REGNO (reg) == GP_ARG_FIRST + nargs)
8183 else if (offset == save_offset)
8185 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8186 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8189 mask |= 1 << REGNO (reg);
8190 save_offset -= UNITS_PER_WORD;
8196 /* Check that the restrictions on register ranges are met. */
8198 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8199 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8200 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8201 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8205 /* Make sure that the topmost argument register is not saved twice.
8206 The checks above ensure that the same is then true for the other
8207 argument registers. */
8208 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8211 /* Pass back information, if requested. */
8214 info->nargs = nargs;
8216 info->size = (adjust > 0 ? adjust : -adjust);
8222 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8223 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8224 the null terminator. */
8227 mips16e_add_register_range (char *s, unsigned int min_reg,
8228 unsigned int max_reg)
8230 if (min_reg != max_reg)
8231 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8233 s += sprintf (s, ",%s", reg_names[min_reg]);
8237 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8238 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8241 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8243 static char buffer[300];
8245 struct mips16e_save_restore_info info;
8246 unsigned int i, end;
8249 /* Parse the pattern. */
8250 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8253 /* Add the mnemonic. */
8254 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8257 /* Save the arguments. */
8259 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8260 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8261 else if (info.nargs == 1)
8262 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8264 /* Emit the amount of stack space to allocate or deallocate. */
8265 s += sprintf (s, "%d", (int) info.size);
8267 /* Save or restore $16. */
8268 if (BITSET_P (info.mask, 16))
8269 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8271 /* Save or restore $17. */
8272 if (BITSET_P (info.mask, 17))
8273 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8275 /* Save or restore registers in the range $s2...$s8, which
8276 mips16e_s2_s8_regs lists in decreasing order. Note that this
8277 is a software register range; the hardware registers are not
8278 numbered consecutively. */
8279 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8280 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8282 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8283 mips16e_s2_s8_regs[i]);
8285 /* Save or restore registers in the range $a0...$a3. */
8286 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8287 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8289 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8290 mips16e_a0_a3_regs[end - 1]);
8292 /* Save or restore $31. */
8293 if (BITSET_P (info.mask, 31))
8294 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
8299 /* Return true if the current function has an insn that implicitly
8303 mips_function_has_gp_insn (void)
8305 /* Don't bother rechecking if we found one last time. */
8306 if (!cfun->machine->has_gp_insn_p)
8310 push_topmost_sequence ();
8311 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8312 if (USEFUL_INSN_P (insn)
8313 && (get_attr_got (insn) != GOT_UNSET
8314 || mips_small_data_pattern_p (PATTERN (insn))))
8316 cfun->machine->has_gp_insn_p = true;
8319 pop_topmost_sequence ();
8321 return cfun->machine->has_gp_insn_p;
8324 /* Return true if the current function returns its value in a floating-point
8325 register in MIPS16 mode. */
8328 mips16_cfun_returns_in_fpr_p (void)
8330 tree return_type = DECL_RESULT (current_function_decl);
8331 return (TARGET_MIPS16
8332 && TARGET_HARD_FLOAT_ABI
8333 && !aggregate_value_p (return_type, current_function_decl)
8334 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8337 /* Return the register that should be used as the global pointer
8338 within this function. Return 0 if the function doesn't need
8339 a global pointer. */
8342 mips_global_pointer (void)
8346 /* $gp is always available unless we're using a GOT. */
8347 if (!TARGET_USE_GOT)
8348 return GLOBAL_POINTER_REGNUM;
8350 /* We must always provide $gp when it is used implicitly. */
8351 if (!TARGET_EXPLICIT_RELOCS)
8352 return GLOBAL_POINTER_REGNUM;
8354 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
8357 return GLOBAL_POINTER_REGNUM;
8359 /* If the function has a nonlocal goto, $gp must hold the correct
8360 global pointer for the target function. */
8361 if (crtl->has_nonlocal_goto)
8362 return GLOBAL_POINTER_REGNUM;
8364 /* There's no need to initialize $gp if it isn't referenced now,
8365 and if we can be sure that no new references will be added during
8367 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
8368 && !mips_function_has_gp_insn ())
8370 /* The function doesn't use $gp at the moment. If we're generating
8371 -call_nonpic code, no new uses will be introduced during or after
8373 if (TARGET_ABICALLS_PIC0)
8376 /* We need to handle the following implicit gp references:
8378 - Reload can sometimes introduce constant pool references
8379 into a function that otherwise didn't need them. For example,
8380 suppose we have an instruction like:
8382 (set (reg:DF R1) (float:DF (reg:SI R2)))
8384 If R2 turns out to be constant such as 1, the instruction may
8385 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8386 the option of using this constant if R2 doesn't get allocated
8389 In cases like these, reload will have added the constant to the
8390 pool but no instruction will yet refer to it.
8392 - MIPS16 functions that return in FPRs need to call an
8393 external libgcc routine. */
8394 if (!crtl->uses_const_pool
8395 && !mips16_cfun_returns_in_fpr_p ())
8399 /* We need a global pointer, but perhaps we can use a call-clobbered
8400 register instead of $gp. */
8401 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8402 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8403 if (!df_regs_ever_live_p (regno)
8404 && call_really_used_regs[regno]
8405 && !fixed_regs[regno]
8406 && regno != PIC_FUNCTION_ADDR_REGNUM)
8409 return GLOBAL_POINTER_REGNUM;
8412 /* Return true if the current function must save register REGNO. */
8415 mips_save_reg_p (unsigned int regno)
8417 /* We need to save $gp if TARGET_CALL_SAVED_GP and if we have not
8418 chosen a call-clobbered substitute. */
8419 if (TARGET_CALL_SAVED_GP
8420 && regno == GLOBAL_POINTER_REGNUM
8421 && cfun->machine->global_pointer == regno)
8424 /* Check call-saved registers. */
8425 if ((crtl->saves_all_registers || df_regs_ever_live_p (regno))
8426 && !call_really_used_regs[regno])
8429 /* Save both registers in an FPR pair if either one is used. This is
8430 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
8431 register to be used without the even register. */
8432 if (FP_REG_P (regno)
8433 && MAX_FPRS_PER_FMT == 2
8434 && df_regs_ever_live_p (regno + 1)
8435 && !call_really_used_regs[regno + 1])
8438 /* We need to save the old frame pointer before setting up a new one. */
8439 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
8442 /* Check for registers that must be saved for FUNCTION_PROFILER. */
8443 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
8446 /* We need to save the incoming return address if it is ever clobbered
8447 within the function, if __builtin_eh_return is being used to set a
8448 different return address, or if a stub is being used to return a
8450 if (regno == GP_REG_FIRST + 31
8451 && (df_regs_ever_live_p (regno)
8452 || crtl->calls_eh_return
8453 || mips16_cfun_returns_in_fpr_p ()))
8459 /* Populate the current function's mips_frame_info structure.
8461 MIPS stack frames look like:
8463 +-------------------------------+
8465 | incoming stack arguments |
8467 +-------------------------------+
8469 | caller-allocated save area |
8470 A | for register arguments |
8472 +-------------------------------+ <-- incoming stack pointer
8474 | callee-allocated save area |
8475 B | for arguments that are |
8476 | split between registers and |
8479 +-------------------------------+ <-- arg_pointer_rtx
8481 C | callee-allocated save area |
8482 | for register varargs |
8484 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
8485 | | + UNITS_PER_HWFPVALUE
8488 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
8489 | | + UNITS_PER_WORD
8492 +-------------------------------+
8494 | local variables | | var_size
8496 +-------------------------------+
8498 | $gp save area | | cprestore_size
8500 P +-------------------------------+ <-- hard_frame_pointer_rtx for
8502 | outgoing stack arguments |
8504 +-------------------------------+
8506 | caller-allocated save area |
8507 | for register arguments |
8509 +-------------------------------+ <-- stack_pointer_rtx
8511 hard_frame_pointer_rtx for
8514 At least two of A, B and C will be empty.
8516 Dynamic stack allocations such as alloca insert data at point P.
8517 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
8518 hard_frame_pointer_rtx unchanged. */
8521 mips_compute_frame_info (void)
8523 struct mips_frame_info *frame;
8524 HOST_WIDE_INT offset, size;
8525 unsigned int regno, i;
8527 frame = &cfun->machine->frame;
8528 memset (frame, 0, sizeof (*frame));
8529 size = get_frame_size ();
8531 cfun->machine->global_pointer = mips_global_pointer ();
8533 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
8534 area and the $gp save slot. This area isn't needed in leaf functions,
8535 but if the target-independent frame size is nonzero, we're committed
8536 to allocating it anyway. */
8537 if (size == 0 && current_function_is_leaf)
8539 /* The MIPS 3.0 linker does not like functions that dynamically
8540 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8541 looks like we are trying to create a second frame pointer to the
8542 function, so allocate some stack space to make it happy. */
8543 if (cfun->calls_alloca)
8544 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
8546 frame->args_size = 0;
8547 frame->cprestore_size = 0;
8551 frame->args_size = crtl->outgoing_args_size;
8552 frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
8554 offset = frame->args_size + frame->cprestore_size;
8556 /* Move above the local variables. */
8557 frame->var_size = MIPS_STACK_ALIGN (size);
8558 offset += frame->var_size;
8560 /* Find out which GPRs we need to save. */
8561 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8562 if (mips_save_reg_p (regno))
8565 frame->mask |= 1 << (regno - GP_REG_FIRST);
8568 /* If this function calls eh_return, we must also save and restore the
8569 EH data registers. */
8570 if (crtl->calls_eh_return)
8571 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
8574 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
8577 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8578 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8579 save all later registers too. */
8580 if (GENERATE_MIPS16E_SAVE_RESTORE)
8582 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
8583 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
8584 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
8585 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
8588 /* Move above the GPR save area. */
8589 if (frame->num_gp > 0)
8591 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
8592 frame->gp_sp_offset = offset - UNITS_PER_WORD;
8595 /* Find out which FPRs we need to save. This loop must iterate over
8596 the same space as its companion in mips_for_each_saved_reg. */
8597 if (TARGET_HARD_FLOAT)
8598 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
8599 if (mips_save_reg_p (regno))
8601 frame->num_fp += MAX_FPRS_PER_FMT;
8602 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
8605 /* Move above the FPR save area. */
8606 if (frame->num_fp > 0)
8608 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
8609 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
8612 /* Move above the callee-allocated varargs save area. */
8613 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
8614 frame->arg_pointer_offset = offset;
8616 /* Move above the callee-allocated area for pretend stack arguments. */
8617 offset += crtl->args.pretend_args_size;
8618 frame->total_size = offset;
8620 /* Work out the offsets of the save areas from the top of the frame. */
8621 if (frame->gp_sp_offset > 0)
8622 frame->gp_save_offset = frame->gp_sp_offset - offset;
8623 if (frame->fp_sp_offset > 0)
8624 frame->fp_save_offset = frame->fp_sp_offset - offset;
8626 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8627 arguments. This tends to increase the chances of using unextended
8628 instructions for local variables and incoming arguments. */
8630 frame->hard_frame_pointer_offset = frame->args_size;
8633 /* Return the style of GP load sequence that is being used for the
8634 current function. */
8636 enum mips_loadgp_style
8637 mips_current_loadgp_style (void)
8639 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
8645 if (TARGET_ABSOLUTE_ABICALLS)
8646 return LOADGP_ABSOLUTE;
8648 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
8651 /* Implement FRAME_POINTER_REQUIRED. */
8654 mips_frame_pointer_required (void)
8656 /* If the function contains dynamic stack allocations, we need to
8657 use the frame pointer to access the static parts of the frame. */
8658 if (cfun->calls_alloca)
8661 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8662 reload may be unable to compute the address of a local variable,
8663 since there is no way to add a large constant to the stack pointer
8664 without using a second temporary register. */
8667 mips_compute_frame_info ();
8668 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8675 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8676 or argument pointer. TO is either the stack pointer or hard frame
8680 mips_initial_elimination_offset (int from, int to)
8682 HOST_WIDE_INT offset;
8684 mips_compute_frame_info ();
8686 /* Set OFFSET to the offset from the soft frame pointer, which is also
8687 the offset from the end-of-prologue stack pointer. */
8690 case FRAME_POINTER_REGNUM:
8694 case ARG_POINTER_REGNUM:
8695 offset = cfun->machine->frame.arg_pointer_offset;
8702 if (to == HARD_FRAME_POINTER_REGNUM)
8703 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8708 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8711 mips_extra_live_on_entry (bitmap regs)
8715 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8716 the global pointer. */
8717 if (!TARGET_ABSOLUTE_ABICALLS)
8718 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8720 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
8721 the global pointer. */
8723 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
8725 /* See the comment above load_call<mode> for details. */
8726 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
8730 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8734 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
8739 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
8742 /* Emit code to change the current function's return address to
8743 ADDRESS. SCRATCH is available as a scratch register, if needed.
8744 ADDRESS and SCRATCH are both word-mode GPRs. */
8747 mips_set_return_address (rtx address, rtx scratch)
8751 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
8752 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
8753 cfun->machine->frame.gp_sp_offset);
8754 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
8757 /* Return a MEM rtx for the cprestore slot, using TEMP as a temporary base
8758 register if need be. */
8761 mips_cprestore_slot (rtx temp)
8763 const struct mips_frame_info *frame;
8765 HOST_WIDE_INT offset;
8767 frame = &cfun->machine->frame;
8768 if (frame_pointer_needed)
8770 base = hard_frame_pointer_rtx;
8771 offset = frame->args_size - frame->hard_frame_pointer_offset;
8775 base = stack_pointer_rtx;
8776 offset = frame->args_size;
8778 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
8781 /* Restore $gp from its save slot, using TEMP as a temporary base register
8782 if need be. This function is for o32 and o64 abicalls only. */
8785 mips_restore_gp (rtx temp)
8787 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
8789 if (cfun->machine->global_pointer == 0)
8794 mips_emit_move (temp, mips_cprestore_slot (temp));
8795 mips_emit_move (pic_offset_table_rtx, temp);
8798 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp));
8799 if (!TARGET_EXPLICIT_RELOCS)
8800 emit_insn (gen_blockage ());
8803 /* A function to save or store a register. The first argument is the
8804 register and the second is the stack slot. */
8805 typedef void (*mips_save_restore_fn) (rtx, rtx);
8807 /* Use FN to save or restore register REGNO. MODE is the register's
8808 mode and OFFSET is the offset of its save slot from the current
8812 mips_save_restore_reg (enum machine_mode mode, int regno,
8813 HOST_WIDE_INT offset, mips_save_restore_fn fn)
8817 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
8818 fn (gen_rtx_REG (mode, regno), mem);
8821 /* Call FN for each register that is saved by the current function.
8822 SP_OFFSET is the offset of the current stack pointer from the start
8826 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
8828 enum machine_mode fpr_mode;
8829 HOST_WIDE_INT offset;
8832 /* Save registers starting from high to low. The debuggers prefer at least
8833 the return register be stored at func+4, and also it allows us not to
8834 need a nop in the epilogue if at least one register is reloaded in
8835 addition to return address. */
8836 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
8837 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
8838 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
8840 mips_save_restore_reg (word_mode, regno, offset, fn);
8841 offset -= UNITS_PER_WORD;
8844 /* This loop must iterate over the same space as its companion in
8845 mips_compute_frame_info. */
8846 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
8847 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
8848 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
8849 regno >= FP_REG_FIRST;
8850 regno -= MAX_FPRS_PER_FMT)
8851 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
8853 mips_save_restore_reg (fpr_mode, regno, offset, fn);
8854 offset -= GET_MODE_SIZE (fpr_mode);
8858 /* If we're generating n32 or n64 abicalls, and the current function
8859 does not use $28 as its global pointer, emit a cplocal directive.
8860 Use pic_offset_table_rtx as the argument to the directive. */
8863 mips_output_cplocal (void)
8865 if (!TARGET_EXPLICIT_RELOCS
8866 && cfun->machine->global_pointer > 0
8867 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
8868 output_asm_insn (".cplocal %+", 0);
8871 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
8874 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8878 #ifdef SDB_DEBUGGING_INFO
8879 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8880 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8883 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
8884 floating-point arguments. */
8886 && TARGET_HARD_FLOAT_ABI
8887 && crtl->args.info.fp_code != 0)
8888 mips16_build_function_stub ();
8890 /* Get the function name the same way that toplev.c does before calling
8891 assemble_start_function. This is needed so that the name used here
8892 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8893 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8894 mips_start_function_definition (fnname, TARGET_MIPS16);
8896 /* Stop mips_file_end from treating this function as external. */
8897 if (TARGET_IRIX && mips_abi == ABI_32)
8898 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
8900 /* Output MIPS-specific frame information. */
8901 if (!flag_inhibit_size_directive)
8903 const struct mips_frame_info *frame;
8905 frame = &cfun->machine->frame;
8907 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
8909 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
8910 "# vars= " HOST_WIDE_INT_PRINT_DEC
8912 ", args= " HOST_WIDE_INT_PRINT_DEC
8913 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
8914 reg_names[frame_pointer_needed
8915 ? HARD_FRAME_POINTER_REGNUM
8916 : STACK_POINTER_REGNUM],
8917 (frame_pointer_needed
8918 ? frame->total_size - frame->hard_frame_pointer_offset
8919 : frame->total_size),
8920 reg_names[GP_REG_FIRST + 31],
8922 frame->num_gp, frame->num_fp,
8924 frame->cprestore_size);
8926 /* .mask MASK, OFFSET. */
8927 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8928 frame->mask, frame->gp_save_offset);
8930 /* .fmask MASK, OFFSET. */
8931 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8932 frame->fmask, frame->fp_save_offset);
8935 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
8936 Also emit the ".set noreorder; .set nomacro" sequence for functions
8938 if (mips_current_loadgp_style () == LOADGP_OLDABI)
8942 /* This is a fixed-form sequence. The position of the
8943 first two instructions is important because of the
8944 way _gp_disp is defined. */
8945 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
8946 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
8947 output_asm_insn ("sll\t$2,16", 0);
8948 output_asm_insn ("addu\t$2,$3", 0);
8950 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
8951 else if (!cfun->machine->all_noreorder_p)
8952 output_asm_insn ("%(.cpload\t%^%)", 0);
8954 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8956 else if (cfun->machine->all_noreorder_p)
8957 output_asm_insn ("%(%<", 0);
8959 /* Tell the assembler which register we're using as the global
8960 pointer. This is needed for thunks, since they can use either
8961 explicit relocs or assembler macros. */
8962 mips_output_cplocal ();
8965 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
8968 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8969 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8973 /* Reinstate the normal $gp. */
8974 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
8975 mips_output_cplocal ();
8977 if (cfun->machine->all_noreorder_p)
8979 /* Avoid using %>%) since it adds excess whitespace. */
8980 output_asm_insn (".set\tmacro", 0);
8981 output_asm_insn (".set\treorder", 0);
8982 set_noreorder = set_nomacro = 0;
8985 /* Get the function name the same way that toplev.c does before calling
8986 assemble_start_function. This is needed so that the name used here
8987 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8988 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8989 mips_end_function_definition (fnname);
8992 /* Save register REG to MEM. Make the instruction frame-related. */
8995 mips_save_reg (rtx reg, rtx mem)
8997 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9001 if (mips_split_64bit_move_p (mem, reg))
9002 mips_split_doubleword_move (mem, reg);
9004 mips_emit_move (mem, reg);
9006 x1 = mips_frame_set (mips_subword (mem, false),
9007 mips_subword (reg, false));
9008 x2 = mips_frame_set (mips_subword (mem, true),
9009 mips_subword (reg, true));
9010 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9015 && REGNO (reg) != GP_REG_FIRST + 31
9016 && !M16_REG_P (REGNO (reg)))
9018 /* Save a non-MIPS16 register by moving it through a temporary.
9019 We don't need to do this for $31 since there's a special
9020 instruction for it. */
9021 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
9022 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9025 mips_emit_move (mem, reg);
9027 mips_set_frame_expr (mips_frame_set (mem, reg));
9031 /* The __gnu_local_gp symbol. */
9033 static GTY(()) rtx mips_gnu_local_gp;
9035 /* If we're generating n32 or n64 abicalls, emit instructions
9036 to set up the global pointer. */
9039 mips_emit_loadgp (void)
9041 rtx addr, offset, incoming_address, base, index, pic_reg;
9043 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9044 switch (mips_current_loadgp_style ())
9046 case LOADGP_ABSOLUTE:
9047 if (mips_gnu_local_gp == NULL)
9049 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9050 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9052 emit_insn (Pmode == SImode
9053 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9054 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9058 /* Added by mips_output_function_prologue. */
9062 addr = XEXP (DECL_RTL (current_function_decl), 0);
9063 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9064 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9065 emit_insn (Pmode == SImode
9066 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9067 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9071 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9072 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9073 emit_insn (Pmode == SImode
9074 ? gen_loadgp_rtp_si (pic_reg, base, index)
9075 : gen_loadgp_rtp_di (pic_reg, base, index));
9083 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9085 /* Emit a blockage if there are implicit uses of the GP register.
9086 This includes profiled functions, because FUNCTION_PROFILE uses
9088 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9089 emit_insn (gen_loadgp_blockage ());
9092 /* Expand the "prologue" pattern. */
9095 mips_expand_prologue (void)
9097 const struct mips_frame_info *frame;
9102 if (cfun->machine->global_pointer > 0)
9103 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
9105 frame = &cfun->machine->frame;
9106 size = frame->total_size;
9108 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9109 bytes beforehand; this is enough to cover the register save area
9110 without going out of range. */
9111 if ((frame->mask | frame->fmask) != 0)
9113 HOST_WIDE_INT step1;
9115 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
9116 if (GENERATE_MIPS16E_SAVE_RESTORE)
9118 HOST_WIDE_INT offset;
9119 unsigned int mask, regno;
9121 /* Try to merge argument stores into the save instruction. */
9122 nargs = mips16e_collect_argument_saves ();
9124 /* Build the save instruction. */
9126 insn = mips16e_build_save_restore (false, &mask, &offset,
9128 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9131 /* Check if we need to save other registers. */
9132 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9133 if (BITSET_P (mask, regno - GP_REG_FIRST))
9135 offset -= UNITS_PER_WORD;
9136 mips_save_restore_reg (word_mode, regno,
9137 offset, mips_save_reg);
9142 insn = gen_add3_insn (stack_pointer_rtx,
9145 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9147 mips_for_each_saved_reg (size, mips_save_reg);
9151 /* Allocate the rest of the frame. */
9154 if (SMALL_OPERAND (-size))
9155 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
9157 GEN_INT (-size)))) = 1;
9160 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
9163 /* There are no instructions to add or subtract registers
9164 from the stack pointer, so use the frame pointer as a
9165 temporary. We should always be using a frame pointer
9166 in this case anyway. */
9167 gcc_assert (frame_pointer_needed);
9168 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9169 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
9170 hard_frame_pointer_rtx,
9171 MIPS_PROLOGUE_TEMP (Pmode)));
9172 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
9175 emit_insn (gen_sub3_insn (stack_pointer_rtx,
9177 MIPS_PROLOGUE_TEMP (Pmode)));
9179 /* Describe the combined effect of the previous instructions. */
9181 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9182 plus_constant (stack_pointer_rtx, -size)));
9186 /* Set up the frame pointer, if we're using one. */
9187 if (frame_pointer_needed)
9189 HOST_WIDE_INT offset;
9191 offset = frame->hard_frame_pointer_offset;
9194 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9195 RTX_FRAME_RELATED_P (insn) = 1;
9197 else if (SMALL_OPERAND (offset))
9199 insn = gen_add3_insn (hard_frame_pointer_rtx,
9200 stack_pointer_rtx, GEN_INT (offset));
9201 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9205 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
9206 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9207 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
9208 hard_frame_pointer_rtx,
9209 MIPS_PROLOGUE_TEMP (Pmode)));
9211 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
9212 plus_constant (stack_pointer_rtx, offset)));
9216 mips_emit_loadgp ();
9218 /* Initialize the $gp save slot. */
9219 if (frame->cprestore_size > 0
9220 && cfun->machine->global_pointer != 0)
9223 mips_emit_move (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9225 else if (TARGET_ABICALLS_PIC2)
9226 emit_insn (gen_cprestore (GEN_INT (frame->args_size)));
9228 emit_move_insn (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9229 pic_offset_table_rtx);
9232 /* If we are profiling, make sure no instructions are scheduled before
9233 the call to mcount. */
9235 emit_insn (gen_blockage ());
9238 /* Emit instructions to restore register REG from slot MEM. */
9241 mips_restore_reg (rtx reg, rtx mem)
9243 /* There's no MIPS16 instruction to load $31 directly. Load into
9244 $7 instead and adjust the return insn appropriately. */
9245 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
9246 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
9248 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
9250 /* Can't restore directly; move through a temporary. */
9251 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
9252 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
9255 mips_emit_move (reg, mem);
9258 /* Emit any instructions needed before a return. */
9261 mips_expand_before_return (void)
9263 /* When using a call-clobbered gp, we start out with unified call
9264 insns that include instructions to restore the gp. We then split
9265 these unified calls after reload. These split calls explicitly
9266 clobber gp, so there is no need to define
9267 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
9269 For consistency, we should also insert an explicit clobber of $28
9270 before return insns, so that the post-reload optimizers know that
9271 the register is not live on exit. */
9272 if (TARGET_CALL_CLOBBERED_GP)
9273 emit_clobber (pic_offset_table_rtx);
9276 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
9280 mips_expand_epilogue (bool sibcall_p)
9282 const struct mips_frame_info *frame;
9283 HOST_WIDE_INT step1, step2;
9286 if (!sibcall_p && mips_can_use_return_insn ())
9288 emit_jump_insn (gen_return ());
9292 /* In MIPS16 mode, if the return value should go into a floating-point
9293 register, we need to call a helper routine to copy it over. */
9294 if (mips16_cfun_returns_in_fpr_p ())
9295 mips16_copy_fpr_return_value ();
9297 /* Split the frame into two. STEP1 is the amount of stack we should
9298 deallocate before restoring the registers. STEP2 is the amount we
9299 should deallocate afterwards.
9301 Start off by assuming that no registers need to be restored. */
9302 frame = &cfun->machine->frame;
9303 step1 = frame->total_size;
9306 /* Work out which register holds the frame address. */
9307 if (!frame_pointer_needed)
9308 base = stack_pointer_rtx;
9311 base = hard_frame_pointer_rtx;
9312 step1 -= frame->hard_frame_pointer_offset;
9315 /* If we need to restore registers, deallocate as much stack as
9316 possible in the second step without going out of range. */
9317 if ((frame->mask | frame->fmask) != 0)
9319 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
9323 /* Set TARGET to BASE + STEP1. */
9329 /* Get an rtx for STEP1 that we can add to BASE. */
9330 adjust = GEN_INT (step1);
9331 if (!SMALL_OPERAND (step1))
9333 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
9334 adjust = MIPS_EPILOGUE_TEMP (Pmode);
9337 /* Normal mode code can copy the result straight into $sp. */
9339 target = stack_pointer_rtx;
9341 emit_insn (gen_add3_insn (target, base, adjust));
9344 /* Copy TARGET into the stack pointer. */
9345 if (target != stack_pointer_rtx)
9346 mips_emit_move (stack_pointer_rtx, target);
9348 /* If we're using addressing macros, $gp is implicitly used by all
9349 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
9351 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
9352 emit_insn (gen_blockage ());
9354 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
9356 unsigned int regno, mask;
9357 HOST_WIDE_INT offset;
9360 /* Generate the restore instruction. */
9362 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
9364 /* Restore any other registers manually. */
9365 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9366 if (BITSET_P (mask, regno - GP_REG_FIRST))
9368 offset -= UNITS_PER_WORD;
9369 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
9372 /* Restore the remaining registers and deallocate the final bit
9374 emit_insn (restore);
9378 /* Restore the registers. */
9379 mips_for_each_saved_reg (frame->total_size - step2, mips_restore_reg);
9381 /* Deallocate the final bit of the frame. */
9383 emit_insn (gen_add3_insn (stack_pointer_rtx,
9388 /* Add in the __builtin_eh_return stack adjustment. We need to
9389 use a temporary in MIPS16 code. */
9390 if (crtl->calls_eh_return)
9394 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
9395 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
9396 MIPS_EPILOGUE_TEMP (Pmode),
9397 EH_RETURN_STACKADJ_RTX));
9398 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
9401 emit_insn (gen_add3_insn (stack_pointer_rtx,
9403 EH_RETURN_STACKADJ_RTX));
9410 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
9411 path will restore the return address into $7 rather than $31. */
9413 && !GENERATE_MIPS16E_SAVE_RESTORE
9414 && BITSET_P (frame->mask, 31))
9415 regno = GP_REG_FIRST + 7;
9417 regno = GP_REG_FIRST + 31;
9418 mips_expand_before_return ();
9419 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
9423 /* Return nonzero if this function is known to have a null epilogue.
9424 This allows the optimizer to omit jumps to jumps if no stack
9428 mips_can_use_return_insn (void)
9430 if (!reload_completed)
9436 /* In MIPS16 mode, a function that returns a floating-point value
9437 needs to arrange to copy the return value into the floating-point
9439 if (mips16_cfun_returns_in_fpr_p ())
9442 return cfun->machine->frame.total_size == 0;
9445 /* Return true if register REGNO can store a value of mode MODE.
9446 The result of this function is cached in mips_hard_regno_mode_ok. */
9449 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
9452 enum mode_class mclass;
9454 if (mode == CCV2mode)
9457 && (regno - ST_REG_FIRST) % 2 == 0);
9459 if (mode == CCV4mode)
9462 && (regno - ST_REG_FIRST) % 4 == 0);
9467 return regno == FPSW_REGNUM;
9469 return (ST_REG_P (regno)
9471 || FP_REG_P (regno));
9474 size = GET_MODE_SIZE (mode);
9475 mclass = GET_MODE_CLASS (mode);
9477 if (GP_REG_P (regno))
9478 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
9480 if (FP_REG_P (regno)
9481 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
9482 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
9484 /* Allow TFmode for CCmode reloads. */
9485 if (mode == TFmode && ISA_HAS_8CC)
9488 /* Allow 64-bit vector modes for Loongson-2E/2F. */
9489 if (TARGET_LOONGSON_VECTORS
9490 && (mode == V2SImode
9496 if (mclass == MODE_FLOAT
9497 || mclass == MODE_COMPLEX_FLOAT
9498 || mclass == MODE_VECTOR_FLOAT)
9499 return size <= UNITS_PER_FPVALUE;
9501 /* Allow integer modes that fit into a single register. We need
9502 to put integers into FPRs when using instructions like CVT
9503 and TRUNC. There's no point allowing sizes smaller than a word,
9504 because the FPU has no appropriate load/store instructions. */
9505 if (mclass == MODE_INT)
9506 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
9509 if (ACC_REG_P (regno)
9510 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
9512 if (MD_REG_P (regno))
9514 /* After a multiplication or division, clobbering HI makes
9515 the value of LO unpredictable, and vice versa. This means
9516 that, for all interesting cases, HI and LO are effectively
9519 We model this by requiring that any value that uses HI
9521 if (size <= UNITS_PER_WORD * 2)
9522 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
9526 /* DSP accumulators do not have the same restrictions as
9527 HI and LO, so we can treat them as normal doubleword
9529 if (size <= UNITS_PER_WORD)
9532 if (size <= UNITS_PER_WORD * 2
9533 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
9538 if (ALL_COP_REG_P (regno))
9539 return mclass == MODE_INT && size <= UNITS_PER_WORD;
9541 if (regno == GOT_VERSION_REGNUM)
9542 return mode == SImode;
9547 /* Implement HARD_REGNO_NREGS. */
9550 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9552 if (ST_REG_P (regno))
9553 /* The size of FP status registers is always 4, because they only hold
9554 CCmode values, and CCmode is always considered to be 4 bytes wide. */
9555 return (GET_MODE_SIZE (mode) + 3) / 4;
9557 if (FP_REG_P (regno))
9558 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
9560 /* All other registers are word-sized. */
9561 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
9564 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
9565 in mips_hard_regno_nregs. */
9568 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
9574 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
9575 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
9577 size = MIN (size, 4);
9578 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
9580 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
9582 size = MIN (size, UNITS_PER_FPREG);
9583 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
9585 if (!hard_reg_set_empty_p (left))
9586 size = MIN (size, UNITS_PER_WORD);
9587 return (GET_MODE_SIZE (mode) + size - 1) / size;
9590 /* Implement CANNOT_CHANGE_MODE_CLASS. */
9593 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
9594 enum machine_mode to ATTRIBUTE_UNUSED,
9595 enum reg_class rclass)
9597 /* There are several problems with changing the modes of values
9598 in floating-point registers:
9600 - When a multi-word value is stored in paired floating-point
9601 registers, the first register always holds the low word.
9602 We therefore can't allow FPRs to change between single-word
9603 and multi-word modes on big-endian targets.
9605 - GCC assumes that each word of a multiword register can be accessed
9606 individually using SUBREGs. This is not true for floating-point
9607 registers if they are bigger than a word.
9609 - Loading a 32-bit value into a 64-bit floating-point register
9610 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
9611 We can't allow FPRs to change from SImode to to a wider mode on
9614 - If the FPU has already interpreted a value in one format, we must
9615 not ask it to treat the value as having a different format.
9617 We therefore disallow all mode changes involving FPRs. */
9618 return reg_classes_intersect_p (FP_REGS, rclass);
9621 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
9624 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
9629 return TARGET_HARD_FLOAT;
9632 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
9635 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
9642 /* Implement MODES_TIEABLE_P. */
9645 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9647 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
9648 prefer to put one of them in FPRs. */
9649 return (mode1 == mode2
9650 || (!mips_mode_ok_for_mov_fmt_p (mode1)
9651 && !mips_mode_ok_for_mov_fmt_p (mode2)));
9654 /* Implement PREFERRED_RELOAD_CLASS. */
9657 mips_preferred_reload_class (rtx x, enum reg_class rclass)
9659 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
9662 if (reg_class_subset_p (FP_REGS, rclass)
9663 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
9666 if (reg_class_subset_p (GR_REGS, rclass))
9669 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
9675 /* Implement REGISTER_MOVE_COST. */
9678 mips_register_move_cost (enum machine_mode mode,
9679 enum reg_class to, enum reg_class from)
9683 /* ??? We cannot move general registers into HI and LO because
9684 MIPS16 has no MTHI and MTLO instructions. Make the cost of
9685 moves in the opposite direction just as high, which stops the
9686 register allocators from using HI and LO for pseudos. */
9687 if (reg_class_subset_p (from, GENERAL_REGS)
9688 && reg_class_subset_p (to, GENERAL_REGS))
9690 if (reg_class_subset_p (from, M16_REGS)
9691 || reg_class_subset_p (to, M16_REGS))
9697 else if (reg_class_subset_p (from, GENERAL_REGS))
9699 if (reg_class_subset_p (to, GENERAL_REGS))
9701 if (reg_class_subset_p (to, FP_REGS))
9703 if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
9705 if (reg_class_subset_p (to, ACC_REGS))
9708 else if (reg_class_subset_p (to, GENERAL_REGS))
9710 if (reg_class_subset_p (from, FP_REGS))
9712 if (reg_class_subset_p (from, ST_REGS))
9713 /* LUI followed by MOVF. */
9715 if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
9717 if (reg_class_subset_p (from, ACC_REGS))
9720 else if (reg_class_subset_p (from, FP_REGS))
9722 if (reg_class_subset_p (to, FP_REGS)
9723 && mips_mode_ok_for_mov_fmt_p (mode))
9725 if (reg_class_subset_p (to, ST_REGS))
9726 /* An expensive sequence. */
9733 /* Return the register class required for a secondary register when
9734 copying between one of the registers in RCLASS and value X, which
9735 has mode MODE. X is the source of the move if IN_P, otherwise it
9736 is the destination. Return NO_REGS if no secondary register is
9740 mips_secondary_reload_class (enum reg_class rclass,
9741 enum machine_mode mode, rtx x, bool in_p)
9745 /* If X is a constant that cannot be loaded into $25, it must be loaded
9746 into some other GPR. No other register class allows a direct move. */
9747 if (mips_dangerous_for_la25_p (x))
9748 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
9750 regno = true_regnum (x);
9753 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9754 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
9757 /* We can't really copy to HI or LO at all in MIPS16 mode. */
9758 if (in_p ? reg_classes_intersect_p (rclass, ACC_REGS) : ACC_REG_P (regno))
9764 /* Copying from accumulator registers to anywhere other than a general
9765 register requires a temporary general register. */
9766 if (reg_class_subset_p (rclass, ACC_REGS))
9767 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9768 if (ACC_REG_P (regno))
9769 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9771 /* We can only copy a value to a condition code register from a
9772 floating-point register, and even then we require a scratch
9773 floating-point register. We can only copy a value out of a
9774 condition-code register into a general register. */
9775 if (reg_class_subset_p (rclass, ST_REGS))
9779 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9781 if (ST_REG_P (regno))
9785 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9788 if (reg_class_subset_p (rclass, FP_REGS))
9791 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
9792 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9793 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9796 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
9797 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9800 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
9801 /* We can force the constant to memory and use lwc1
9802 and ldc1. As above, we will use pairs of lwc1s if
9803 ldc1 is not supported. */
9806 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
9807 /* In this case we can use mov.fmt. */
9810 /* Otherwise, we need to reload through an integer register. */
9813 if (FP_REG_P (regno))
9814 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
9819 /* Implement TARGET_MODE_REP_EXTENDED. */
9822 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
9824 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
9825 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
9831 /* Implement TARGET_VALID_POINTER_MODE. */
9834 mips_valid_pointer_mode (enum machine_mode mode)
9836 return mode == SImode || (TARGET_64BIT && mode == DImode);
9839 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
9842 mips_vector_mode_supported_p (enum machine_mode mode)
9847 return TARGET_PAIRED_SINGLE_FLOAT;
9862 return TARGET_LOONGSON_VECTORS;
9869 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9872 mips_scalar_mode_supported_p (enum machine_mode mode)
9874 if (ALL_FIXED_POINT_MODE_P (mode)
9875 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
9878 return default_scalar_mode_supported_p (mode);
9881 /* Implement TARGET_INIT_LIBFUNCS. */
9883 #include "config/gofast.h"
9886 mips_init_libfuncs (void)
9888 if (TARGET_FIX_VR4120)
9890 /* Register the special divsi3 and modsi3 functions needed to work
9891 around VR4120 division errata. */
9892 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9893 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9896 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
9898 /* Register the MIPS16 -mhard-float stubs. */
9899 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9900 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9901 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9902 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9904 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9905 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9906 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9907 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9908 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9909 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9910 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
9912 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9913 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9914 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
9916 if (TARGET_DOUBLE_FLOAT)
9918 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9919 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9920 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9921 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9923 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9924 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9925 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9926 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9927 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9928 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9929 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
9931 set_conv_libfunc (sext_optab, DFmode, SFmode,
9932 "__mips16_extendsfdf2");
9933 set_conv_libfunc (trunc_optab, SFmode, DFmode,
9934 "__mips16_truncdfsf2");
9935 set_conv_libfunc (sfix_optab, SImode, DFmode,
9936 "__mips16_fix_truncdfsi");
9937 set_conv_libfunc (sfloat_optab, DFmode, SImode,
9938 "__mips16_floatsidf");
9939 set_conv_libfunc (ufloat_optab, DFmode, SImode,
9940 "__mips16_floatunsidf");
9944 /* Register the gofast functions if selected using --enable-gofast. */
9945 gofast_maybe_init_libfuncs ();
9947 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
9948 on an external non-MIPS16 routine to implement __sync_synchronize. */
9950 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
9953 /* Return the length of INSN. LENGTH is the initial length computed by
9954 attributes in the machine-description file. */
9957 mips_adjust_insn_length (rtx insn, int length)
9959 /* A unconditional jump has an unfilled delay slot if it is not part
9960 of a sequence. A conditional jump normally has a delay slot, but
9961 does not on MIPS16. */
9962 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9965 /* See how many nops might be needed to avoid hardware hazards. */
9966 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9967 switch (get_attr_hazard (insn))
9981 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
9982 the .md file length attributes are 4-based for both modes.
9983 Adjust the MIPS16 ones here. */
9990 /* Return an asm sequence to start a noat block and load the address
9991 of a label into $1. */
9994 mips_output_load_label (void)
9996 if (TARGET_EXPLICIT_RELOCS)
10000 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10003 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10006 if (ISA_HAS_LOAD_DELAY)
10007 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10008 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10012 if (Pmode == DImode)
10013 return "%[dla\t%@,%0";
10015 return "%[la\t%@,%0";
10019 /* Return the assembly code for INSN, which has the operands given by
10020 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10021 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10022 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10023 version of BRANCH_IF_TRUE. */
10026 mips_output_conditional_branch (rtx insn, rtx *operands,
10027 const char *branch_if_true,
10028 const char *branch_if_false)
10030 unsigned int length;
10031 rtx taken, not_taken;
10033 length = get_attr_length (insn);
10036 /* Just a simple conditional branch. */
10037 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10038 return branch_if_true;
10041 /* Generate a reversed branch around a direct jump. This fallback does
10042 not use branch-likely instructions. */
10043 mips_branch_likely = false;
10044 not_taken = gen_label_rtx ();
10045 taken = operands[1];
10047 /* Generate the reversed branch to NOT_TAKEN. */
10048 operands[1] = not_taken;
10049 output_asm_insn (branch_if_false, operands);
10051 /* If INSN has a delay slot, we must provide delay slots for both the
10052 branch to NOT_TAKEN and the conditional jump. We must also ensure
10053 that INSN's delay slot is executed in the appropriate cases. */
10054 if (final_sequence)
10056 /* This first delay slot will always be executed, so use INSN's
10057 delay slot if is not annulled. */
10058 if (!INSN_ANNULLED_BRANCH_P (insn))
10060 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10061 asm_out_file, optimize, 1, NULL);
10062 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10065 output_asm_insn ("nop", 0);
10066 fprintf (asm_out_file, "\n");
10069 /* Output the unconditional branch to TAKEN. */
10071 output_asm_insn ("j\t%0%/", &taken);
10074 output_asm_insn (mips_output_load_label (), &taken);
10075 output_asm_insn ("jr\t%@%]%/", 0);
10078 /* Now deal with its delay slot; see above. */
10079 if (final_sequence)
10081 /* This delay slot will only be executed if the branch is taken.
10082 Use INSN's delay slot if is annulled. */
10083 if (INSN_ANNULLED_BRANCH_P (insn))
10085 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10086 asm_out_file, optimize, 1, NULL);
10087 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10090 output_asm_insn ("nop", 0);
10091 fprintf (asm_out_file, "\n");
10094 /* Output NOT_TAKEN. */
10095 targetm.asm_out.internal_label (asm_out_file, "L",
10096 CODE_LABEL_NUMBER (not_taken));
10100 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10101 if some ordering condition is true. The condition is given by
10102 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10103 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10104 its second is always zero. */
10107 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10109 const char *branch[2];
10111 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10112 Make BRANCH[0] branch on the inverse condition. */
10113 switch (GET_CODE (operands[0]))
10115 /* These cases are equivalent to comparisons against zero. */
10117 inverted_p = !inverted_p;
10118 /* Fall through. */
10120 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10121 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10124 /* These cases are always true or always false. */
10126 inverted_p = !inverted_p;
10127 /* Fall through. */
10129 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10130 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10134 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10135 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10138 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10141 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
10142 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
10144 When working around R4000 and R4400 errata, we need to make sure that
10145 the division is not immediately followed by a shift[1][2]. We also
10146 need to stop the division from being put into a branch delay slot[3].
10147 The easiest way to avoid both problems is to add a nop after the
10148 division. When a divide-by-zero check is needed, this nop can be
10149 used to fill the branch delay slot.
10151 [1] If a double-word or a variable shift executes immediately
10152 after starting an integer division, the shift may give an
10153 incorrect result. See quotations of errata #16 and #28 from
10154 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10155 in mips.md for details.
10157 [2] A similar bug to [1] exists for all revisions of the
10158 R4000 and the R4400 when run in an MC configuration.
10159 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10161 "19. In this following sequence:
10163 ddiv (or ddivu or div or divu)
10164 dsll32 (or dsrl32, dsra32)
10166 if an MPT stall occurs, while the divide is slipping the cpu
10167 pipeline, then the following double shift would end up with an
10170 Workaround: The compiler needs to avoid generating any
10171 sequence with divide followed by extended double shift."
10173 This erratum is also present in "MIPS R4400MC Errata, Processor
10174 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10175 & 3.0" as errata #10 and #4, respectively.
10177 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10178 (also valid for MIPS R4000MC processors):
10180 "52. R4000SC: This bug does not apply for the R4000PC.
10182 There are two flavors of this bug:
10184 1) If the instruction just after divide takes an RF exception
10185 (tlb-refill, tlb-invalid) and gets an instruction cache
10186 miss (both primary and secondary) and the line which is
10187 currently in secondary cache at this index had the first
10188 data word, where the bits 5..2 are set, then R4000 would
10189 get a wrong result for the div.
10194 ------------------- # end-of page. -tlb-refill
10199 ------------------- # end-of page. -tlb-invalid
10202 2) If the divide is in the taken branch delay slot, where the
10203 target takes RF exception and gets an I-cache miss for the
10204 exception vector or where I-cache miss occurs for the
10205 target address, under the above mentioned scenarios, the
10206 div would get wrong results.
10209 j r2 # to next page mapped or unmapped
10210 div r8,r9 # this bug would be there as long
10211 # as there is an ICache miss and
10212 nop # the "data pattern" is present
10215 beq r0, r0, NextPage # to Next page
10219 This bug is present for div, divu, ddiv, and ddivu
10222 Workaround: For item 1), OS could make sure that the next page
10223 after the divide instruction is also mapped. For item 2), the
10224 compiler could make sure that the divide instruction is not in
10225 the branch delay slot."
10227 These processors have PRId values of 0x00004220 and 0x00004300 for
10228 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10231 mips_output_division (const char *division, rtx *operands)
10236 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
10238 output_asm_insn (s, operands);
10241 if (TARGET_CHECK_ZERO_DIV)
10245 output_asm_insn (s, operands);
10246 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
10248 else if (GENERATE_DIVIDE_TRAPS)
10250 output_asm_insn (s, operands);
10251 s = "teq\t%2,%.,7";
10255 output_asm_insn ("%(bne\t%2,%.,1f", operands);
10256 output_asm_insn (s, operands);
10257 s = "break\t7%)\n1:";
10263 /* Return true if IN_INSN is a multiply-add or multiply-subtract
10264 instruction and if OUT_INSN assigns to the accumulator operand. */
10267 mips_linked_madd_p (rtx out_insn, rtx in_insn)
10271 x = single_set (in_insn);
10277 if (GET_CODE (x) == PLUS
10278 && GET_CODE (XEXP (x, 0)) == MULT
10279 && reg_set_p (XEXP (x, 1), out_insn))
10282 if (GET_CODE (x) == MINUS
10283 && GET_CODE (XEXP (x, 1)) == MULT
10284 && reg_set_p (XEXP (x, 0), out_insn))
10290 /* True if the dependency between OUT_INSN and IN_INSN is on the store
10291 data rather than the address. We need this because the cprestore
10292 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
10293 which causes the default routine to abort. We just return false
10297 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10299 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10302 return !store_data_bypass_p (out_insn, in_insn);
10306 /* Variables and flags used in scheduler hooks when tuning for
10310 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
10313 /* If true, then next ALU1/2 instruction will go to ALU1. */
10316 /* If true, then next FALU1/2 unstruction will go to FALU1. */
10319 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
10320 int alu1_core_unit_code;
10321 int alu2_core_unit_code;
10322 int falu1_core_unit_code;
10323 int falu2_core_unit_code;
10325 /* True if current cycle has a multi instruction.
10326 This flag is used in mips_ls2_dfa_post_advance_cycle. */
10327 bool cycle_has_multi_p;
10329 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
10330 These are used in mips_ls2_dfa_post_advance_cycle to initialize
10332 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
10333 instruction to go ALU1. */
10334 rtx alu1_turn_enabled_insn;
10335 rtx alu2_turn_enabled_insn;
10336 rtx falu1_turn_enabled_insn;
10337 rtx falu2_turn_enabled_insn;
10340 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10341 dependencies have no cost, except on the 20Kc where output-dependence
10342 is treated like input-dependence. */
10345 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10346 rtx dep ATTRIBUTE_UNUSED, int cost)
10348 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
10351 if (REG_NOTE_KIND (link) != 0)
10356 /* Return the number of instructions that can be issued per cycle. */
10359 mips_issue_rate (void)
10363 case PROCESSOR_74KC:
10364 case PROCESSOR_74KF2_1:
10365 case PROCESSOR_74KF1_1:
10366 case PROCESSOR_74KF3_2:
10367 /* The 74k is not strictly quad-issue cpu, but can be seen as one
10368 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
10369 but in reality only a maximum of 3 insns can be issued as
10370 floating-point loads and stores also require a slot in the
10374 case PROCESSOR_20KC:
10375 case PROCESSOR_R4130:
10376 case PROCESSOR_R5400:
10377 case PROCESSOR_R5500:
10378 case PROCESSOR_R7000:
10379 case PROCESSOR_R9000:
10382 case PROCESSOR_SB1:
10383 case PROCESSOR_SB1A:
10384 /* This is actually 4, but we get better performance if we claim 3.
10385 This is partly because of unwanted speculative code motion with the
10386 larger number, and partly because in most common cases we can't
10387 reach the theoretical max of 4. */
10390 case PROCESSOR_LOONGSON_2E:
10391 case PROCESSOR_LOONGSON_2F:
10399 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
10402 mips_ls2_init_dfa_post_cycle_insn (void)
10405 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
10406 mips_ls2.alu1_turn_enabled_insn = get_insns ();
10410 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
10411 mips_ls2.alu2_turn_enabled_insn = get_insns ();
10415 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
10416 mips_ls2.falu1_turn_enabled_insn = get_insns ();
10420 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
10421 mips_ls2.falu2_turn_enabled_insn = get_insns ();
10424 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
10425 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
10426 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
10427 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
10430 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
10431 Init data used in mips_dfa_post_advance_cycle. */
10434 mips_init_dfa_post_cycle_insn (void)
10436 if (TUNE_LOONGSON_2EF)
10437 mips_ls2_init_dfa_post_cycle_insn ();
10440 /* Initialize STATE when scheduling for Loongson 2E/2F.
10441 Support round-robin dispatch scheme by enabling only one of
10442 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
10446 mips_ls2_dfa_post_advance_cycle (state_t state)
10448 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
10450 /* Though there are no non-pipelined ALU1 insns,
10451 we can get an instruction of type 'multi' before reload. */
10452 gcc_assert (mips_ls2.cycle_has_multi_p);
10453 mips_ls2.alu1_turn_p = false;
10456 mips_ls2.cycle_has_multi_p = false;
10458 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
10459 /* We have a non-pipelined alu instruction in the core,
10460 adjust round-robin counter. */
10461 mips_ls2.alu1_turn_p = true;
10463 if (mips_ls2.alu1_turn_p)
10465 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
10466 gcc_unreachable ();
10470 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
10471 gcc_unreachable ();
10474 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
10476 /* There are no non-pipelined FALU1 insns. */
10477 gcc_unreachable ();
10478 mips_ls2.falu1_turn_p = false;
10481 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
10482 /* We have a non-pipelined falu instruction in the core,
10483 adjust round-robin counter. */
10484 mips_ls2.falu1_turn_p = true;
10486 if (mips_ls2.falu1_turn_p)
10488 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
10489 gcc_unreachable ();
10493 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
10494 gcc_unreachable ();
10498 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
10499 This hook is being called at the start of each cycle. */
10502 mips_dfa_post_advance_cycle (void)
10504 if (TUNE_LOONGSON_2EF)
10505 mips_ls2_dfa_post_advance_cycle (curr_state);
10508 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
10509 be as wide as the scheduling freedom in the DFA. */
10512 mips_multipass_dfa_lookahead (void)
10514 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10518 if (TUNE_LOONGSON_2EF)
10524 /* Remove the instruction at index LOWER from ready queue READY and
10525 reinsert it in front of the instruction at index HIGHER. LOWER must
10529 mips_promote_ready (rtx *ready, int lower, int higher)
10534 new_head = ready[lower];
10535 for (i = lower; i < higher; i++)
10536 ready[i] = ready[i + 1];
10537 ready[i] = new_head;
10540 /* If the priority of the instruction at POS2 in the ready queue READY
10541 is within LIMIT units of that of the instruction at POS1, swap the
10542 instructions if POS2 is not already less than POS1. */
10545 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
10548 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
10552 temp = ready[pos1];
10553 ready[pos1] = ready[pos2];
10554 ready[pos2] = temp;
10558 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
10559 that may clobber hi or lo. */
10560 static rtx mips_macc_chains_last_hilo;
10562 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10563 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10566 mips_macc_chains_record (rtx insn)
10568 if (get_attr_may_clobber_hilo (insn))
10569 mips_macc_chains_last_hilo = insn;
10572 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10573 has NREADY elements, looking for a multiply-add or multiply-subtract
10574 instruction that is cumulative with mips_macc_chains_last_hilo.
10575 If there is one, promote it ahead of anything else that might
10576 clobber hi or lo. */
10579 mips_macc_chains_reorder (rtx *ready, int nready)
10583 if (mips_macc_chains_last_hilo != 0)
10584 for (i = nready - 1; i >= 0; i--)
10585 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10587 for (j = nready - 1; j > i; j--)
10588 if (recog_memoized (ready[j]) >= 0
10589 && get_attr_may_clobber_hilo (ready[j]))
10591 mips_promote_ready (ready, i, j);
10598 /* The last instruction to be scheduled. */
10599 static rtx vr4130_last_insn;
10601 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10602 points to an rtx that is initially an instruction. Nullify the rtx
10603 if the instruction uses the value of register X. */
10606 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
10611 insn_ptr = (rtx *) data;
10614 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10618 /* Return true if there is true register dependence between vr4130_last_insn
10622 vr4130_true_reg_dependence_p (rtx insn)
10624 note_stores (PATTERN (vr4130_last_insn),
10625 vr4130_true_reg_dependence_p_1, &insn);
10629 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10630 the ready queue and that INSN2 is the instruction after it, return
10631 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10632 in which INSN1 and INSN2 can probably issue in parallel, but for
10633 which (INSN2, INSN1) should be less sensitive to instruction
10634 alignment than (INSN1, INSN2). See 4130.md for more details. */
10637 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10639 sd_iterator_def sd_it;
10642 /* Check for the following case:
10644 1) there is some other instruction X with an anti dependence on INSN1;
10645 2) X has a higher priority than INSN2; and
10646 3) X is an arithmetic instruction (and thus has no unit restrictions).
10648 If INSN1 is the last instruction blocking X, it would better to
10649 choose (INSN1, X) over (INSN2, INSN1). */
10650 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
10651 if (DEP_TYPE (dep) == REG_DEP_ANTI
10652 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
10653 && recog_memoized (DEP_CON (dep)) >= 0
10654 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
10657 if (vr4130_last_insn != 0
10658 && recog_memoized (insn1) >= 0
10659 && recog_memoized (insn2) >= 0)
10661 /* See whether INSN1 and INSN2 use different execution units,
10662 or if they are both ALU-type instructions. If so, they can
10663 probably execute in parallel. */
10664 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10665 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10666 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10668 /* If only one of the instructions has a dependence on
10669 vr4130_last_insn, prefer to schedule the other one first. */
10670 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
10671 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
10672 if (dep1_p != dep2_p)
10675 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10676 is not an ALU-type instruction and if INSN1 uses the same
10677 execution unit. (Note that if this condition holds, we already
10678 know that INSN2 uses a different execution unit.) */
10679 if (class1 != VR4130_CLASS_ALU
10680 && recog_memoized (vr4130_last_insn) >= 0
10681 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10688 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10689 queue with at least two instructions. Swap the first two if
10690 vr4130_swap_insns_p says that it could be worthwhile. */
10693 vr4130_reorder (rtx *ready, int nready)
10695 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10696 mips_promote_ready (ready, nready - 2, nready - 1);
10699 /* Record whether last 74k AGEN instruction was a load or store. */
10700 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
10702 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
10703 resets to TYPE_UNKNOWN state. */
10706 mips_74k_agen_init (rtx insn)
10708 if (!insn || !NONJUMP_INSN_P (insn))
10709 mips_last_74k_agen_insn = TYPE_UNKNOWN;
10712 enum attr_type type = get_attr_type (insn);
10713 if (type == TYPE_LOAD || type == TYPE_STORE)
10714 mips_last_74k_agen_insn = type;
10718 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
10719 loads to be grouped together, and multiple stores to be grouped
10720 together. Swap things around in the ready queue to make this happen. */
10723 mips_74k_agen_reorder (rtx *ready, int nready)
10726 int store_pos, load_pos;
10731 for (i = nready - 1; i >= 0; i--)
10733 rtx insn = ready[i];
10734 if (USEFUL_INSN_P (insn))
10735 switch (get_attr_type (insn))
10738 if (store_pos == -1)
10743 if (load_pos == -1)
10752 if (load_pos == -1 || store_pos == -1)
10755 switch (mips_last_74k_agen_insn)
10758 /* Prefer to schedule loads since they have a higher latency. */
10760 /* Swap loads to the front of the queue. */
10761 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
10764 /* Swap stores to the front of the queue. */
10765 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
10772 /* Implement TARGET_SCHED_INIT. */
10775 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10776 int max_ready ATTRIBUTE_UNUSED)
10778 mips_macc_chains_last_hilo = 0;
10779 vr4130_last_insn = 0;
10780 mips_74k_agen_init (NULL_RTX);
10782 /* When scheduling for Loongson2, branch instructions go to ALU1,
10783 therefore basic block is most likely to start with round-robin counter
10784 pointed to ALU2. */
10785 mips_ls2.alu1_turn_p = false;
10786 mips_ls2.falu1_turn_p = true;
10789 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
10792 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10793 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
10795 if (!reload_completed
10796 && TUNE_MACC_CHAINS
10798 mips_macc_chains_reorder (ready, *nreadyp);
10800 if (reload_completed
10802 && !TARGET_VR4130_ALIGN
10804 vr4130_reorder (ready, *nreadyp);
10807 mips_74k_agen_reorder (ready, *nreadyp);
10809 return mips_issue_rate ();
10812 /* Update round-robin counters for ALU1/2 and FALU1/2. */
10815 mips_ls2_variable_issue (rtx insn)
10817 if (mips_ls2.alu1_turn_p)
10819 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
10820 mips_ls2.alu1_turn_p = false;
10824 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
10825 mips_ls2.alu1_turn_p = true;
10828 if (mips_ls2.falu1_turn_p)
10830 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
10831 mips_ls2.falu1_turn_p = false;
10835 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
10836 mips_ls2.falu1_turn_p = true;
10839 if (recog_memoized (insn) >= 0)
10840 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
10843 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10846 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10847 rtx insn, int more)
10849 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
10850 if (USEFUL_INSN_P (insn))
10853 if (!reload_completed && TUNE_MACC_CHAINS)
10854 mips_macc_chains_record (insn);
10855 vr4130_last_insn = insn;
10857 mips_74k_agen_init (insn);
10858 else if (TUNE_LOONGSON_2EF)
10859 mips_ls2_variable_issue (insn);
10862 /* Instructions of type 'multi' should all be split before
10863 the second scheduling pass. */
10864 gcc_assert (!reload_completed
10865 || recog_memoized (insn) < 0
10866 || get_attr_type (insn) != TYPE_MULTI);
10871 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10872 return the first operand of the associated PREF or PREFX insn. */
10875 mips_prefetch_cookie (rtx write, rtx locality)
10877 /* store_streamed / load_streamed. */
10878 if (INTVAL (locality) <= 0)
10879 return GEN_INT (INTVAL (write) + 4);
10881 /* store / load. */
10882 if (INTVAL (locality) <= 2)
10885 /* store_retained / load_retained. */
10886 return GEN_INT (INTVAL (write) + 6);
10889 /* Flags that indicate when a built-in function is available.
10891 BUILTIN_AVAIL_NON_MIPS16
10892 The function is available on the current target, but only
10893 in non-MIPS16 mode. */
10894 #define BUILTIN_AVAIL_NON_MIPS16 1
10896 /* Declare an availability predicate for built-in functions that
10897 require non-MIPS16 mode and also require COND to be true.
10898 NAME is the main part of the predicate's name. */
10899 #define AVAIL_NON_MIPS16(NAME, COND) \
10900 static unsigned int \
10901 mips_builtin_avail_##NAME (void) \
10903 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
10906 /* This structure describes a single built-in function. */
10907 struct mips_builtin_description {
10908 /* The code of the main .md file instruction. See mips_builtin_type
10909 for more information. */
10910 enum insn_code icode;
10912 /* The floating-point comparison code to use with ICODE, if any. */
10913 enum mips_fp_condition cond;
10915 /* The name of the built-in function. */
10918 /* Specifies how the function should be expanded. */
10919 enum mips_builtin_type builtin_type;
10921 /* The function's prototype. */
10922 enum mips_function_type function_type;
10924 /* Whether the function is available. */
10925 unsigned int (*avail) (void);
10928 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
10929 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
10930 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
10931 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
10932 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
10933 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
10934 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
10935 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
10936 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
10938 /* Construct a mips_builtin_description from the given arguments.
10940 INSN is the name of the associated instruction pattern, without the
10941 leading CODE_FOR_mips_.
10943 CODE is the floating-point condition code associated with the
10944 function. It can be 'f' if the field is not applicable.
10946 NAME is the name of the function itself, without the leading
10949 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
10951 AVAIL is the name of the availability predicate, without the leading
10952 mips_builtin_avail_. */
10953 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
10954 FUNCTION_TYPE, AVAIL) \
10955 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
10956 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
10957 mips_builtin_avail_ ## AVAIL }
10959 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
10960 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
10961 are as for MIPS_BUILTIN. */
10962 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
10963 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
10965 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
10966 are subject to mips_builtin_avail_<AVAIL>. */
10967 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
10968 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
10969 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
10970 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
10971 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
10973 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10974 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
10975 while the any and all forms are subject to mips_builtin_avail_mips3d. */
10976 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
10977 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
10978 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
10980 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
10981 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
10983 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
10984 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
10986 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
10987 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
10990 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10991 are subject to mips_builtin_avail_mips3d. */
10992 #define CMP_4S_BUILTINS(INSN, COND) \
10993 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
10994 MIPS_BUILTIN_CMP_ANY, \
10995 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
10996 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
10997 MIPS_BUILTIN_CMP_ALL, \
10998 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
11000 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11001 instruction requires mips_builtin_avail_<AVAIL>. */
11002 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
11003 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
11004 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11006 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
11007 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11010 /* Define all the built-in functions related to C.cond.fmt condition COND. */
11011 #define CMP_BUILTINS(COND) \
11012 MOVTF_BUILTINS (c, COND, paired_single), \
11013 MOVTF_BUILTINS (cabs, COND, mips3d), \
11014 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
11015 CMP_PS_BUILTINS (c, COND, paired_single), \
11016 CMP_PS_BUILTINS (cabs, COND, mips3d), \
11017 CMP_4S_BUILTINS (c, COND), \
11018 CMP_4S_BUILTINS (cabs, COND)
11020 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
11021 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
11022 and AVAIL are as for MIPS_BUILTIN. */
11023 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11024 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
11025 FUNCTION_TYPE, AVAIL)
11027 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11028 branch instruction. AVAIL is as for MIPS_BUILTIN. */
11029 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
11030 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
11031 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
11033 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
11034 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11035 builtin_description field. */
11036 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
11037 { CODE_FOR_loongson_ ## INSN, 0, "__builtin_loongson_" #FN_NAME, \
11038 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_loongson }
11040 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
11041 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11042 builtin_description field. */
11043 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
11044 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
11046 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
11047 We use functions of this form when the same insn can be usefully applied
11048 to more than one datatype. */
11049 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
11050 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
11052 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11053 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11054 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11055 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11056 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11057 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11059 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
11060 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
11061 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
11062 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
11063 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
11064 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
11065 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
11066 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
11067 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
11068 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
11069 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
11070 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
11071 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
11072 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
11073 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
11074 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
11075 #define CODE_FOR_loongson_biadd CODE_FOR_reduc_uplus_v8qi
11076 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
11077 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
11078 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
11079 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
11080 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
11081 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
11082 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
11083 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
11084 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
11085 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
11086 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
11087 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
11088 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
11090 static const struct mips_builtin_description mips_builtins[] = {
11091 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11092 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11093 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11094 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11095 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
11096 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
11097 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
11098 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
11100 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
11101 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11102 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11103 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11104 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
11106 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
11107 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
11108 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11109 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
11110 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
11111 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11113 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
11114 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
11115 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11116 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
11117 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
11118 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11120 MIPS_FP_CONDITIONS (CMP_BUILTINS),
11122 /* Built-in functions for the SB-1 processor. */
11123 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
11125 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
11126 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11127 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11128 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11129 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11130 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11131 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11132 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11133 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11134 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11135 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11136 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
11137 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
11138 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
11139 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
11140 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
11141 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
11142 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
11143 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
11144 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
11145 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
11146 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
11147 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
11148 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
11149 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
11150 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
11151 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
11152 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
11153 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
11154 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
11155 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
11156 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
11157 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11158 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11159 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11160 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
11161 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11162 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11163 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
11164 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
11165 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
11166 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11167 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
11168 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
11169 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
11170 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
11171 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
11172 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
11173 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11174 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11175 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11176 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11177 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11178 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11179 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11180 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11181 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11182 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11183 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11184 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11185 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
11186 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
11187 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
11188 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
11189 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
11190 BPOSGE_BUILTIN (32, dsp),
11192 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
11193 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
11194 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11195 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11196 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11197 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11198 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11199 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11200 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11201 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11202 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11203 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11204 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11205 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11206 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11207 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11208 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
11209 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
11210 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
11211 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11212 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
11213 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
11214 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
11215 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11216 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11217 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11218 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11219 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11220 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11221 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11222 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11223 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11224 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11225 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11226 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11228 /* Built-in functions for the DSP ASE (32-bit only). */
11229 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11230 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11231 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11232 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11233 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11234 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11235 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11236 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
11237 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
11238 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11239 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11240 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11241 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11242 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11243 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11244 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11245 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
11246 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
11247 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
11248 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
11249 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
11251 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
11252 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11253 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11254 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
11255 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
11256 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
11257 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
11258 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11259 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
11260 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
11261 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11262 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11263 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11264 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11265 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11266 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11268 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
11269 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
11270 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
11271 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
11272 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11273 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11274 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11275 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11276 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11277 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11278 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
11279 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
11280 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11281 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11282 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11283 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11284 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
11285 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11286 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11287 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11288 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
11289 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
11290 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11291 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11292 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11293 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11294 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11295 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11296 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11297 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11298 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11299 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11300 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11301 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11302 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11303 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11304 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11305 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11306 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
11307 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
11308 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11309 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11310 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11311 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11312 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11313 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11314 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11315 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11316 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
11317 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11318 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11319 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11320 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11321 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
11322 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
11323 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11324 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11325 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11326 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
11327 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11328 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
11329 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
11330 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
11331 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
11332 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11333 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11334 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11335 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11336 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11337 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11338 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11339 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11340 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11341 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11342 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11343 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11344 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11345 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11346 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11347 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11348 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11349 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11350 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
11351 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
11352 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11353 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11354 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11355 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11356 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11357 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11358 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11359 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11360 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11361 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11362 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11363 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11364 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11365 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11366 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11367 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11369 /* Sundry other built-in functions. */
11370 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
11373 /* MODE is a vector mode whose elements have type TYPE. Return the type
11374 of the vector itself. */
11377 mips_builtin_vector_type (tree type, enum machine_mode mode)
11379 static tree types[2 * (int) MAX_MACHINE_MODE];
11382 mode_index = (int) mode;
11384 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
11385 mode_index += MAX_MACHINE_MODE;
11387 if (types[mode_index] == NULL_TREE)
11388 types[mode_index] = build_vector_type_for_mode (type, mode);
11389 return types[mode_index];
11392 /* Return a type for 'const volatile void *'. */
11395 mips_build_cvpointer_type (void)
11399 if (cache == NULL_TREE)
11400 cache = build_pointer_type (build_qualified_type
11402 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
11406 /* Source-level argument types. */
11407 #define MIPS_ATYPE_VOID void_type_node
11408 #define MIPS_ATYPE_INT integer_type_node
11409 #define MIPS_ATYPE_POINTER ptr_type_node
11410 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
11412 /* Standard mode-based argument types. */
11413 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
11414 #define MIPS_ATYPE_SI intSI_type_node
11415 #define MIPS_ATYPE_USI unsigned_intSI_type_node
11416 #define MIPS_ATYPE_DI intDI_type_node
11417 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
11418 #define MIPS_ATYPE_SF float_type_node
11419 #define MIPS_ATYPE_DF double_type_node
11421 /* Vector argument types. */
11422 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
11423 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
11424 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
11425 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
11426 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
11427 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
11428 #define MIPS_ATYPE_UV2SI \
11429 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
11430 #define MIPS_ATYPE_UV4HI \
11431 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
11432 #define MIPS_ATYPE_UV8QI \
11433 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
11435 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
11436 their associated MIPS_ATYPEs. */
11437 #define MIPS_FTYPE_ATYPES1(A, B) \
11438 MIPS_ATYPE_##A, MIPS_ATYPE_##B
11440 #define MIPS_FTYPE_ATYPES2(A, B, C) \
11441 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
11443 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
11444 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
11446 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
11447 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
11450 /* Return the function type associated with function prototype TYPE. */
11453 mips_build_function_type (enum mips_function_type type)
11455 static tree types[(int) MIPS_MAX_FTYPE_MAX];
11457 if (types[(int) type] == NULL_TREE)
11460 #define DEF_MIPS_FTYPE(NUM, ARGS) \
11461 case MIPS_FTYPE_NAME##NUM ARGS: \
11462 types[(int) type] \
11463 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
11466 #include "config/mips/mips-ftypes.def"
11467 #undef DEF_MIPS_FTYPE
11469 gcc_unreachable ();
11472 return types[(int) type];
11475 /* Implement TARGET_INIT_BUILTINS. */
11478 mips_init_builtins (void)
11480 const struct mips_builtin_description *d;
11483 /* Iterate through all of the bdesc arrays, initializing all of the
11484 builtin functions. */
11485 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
11487 d = &mips_builtins[i];
11489 add_builtin_function (d->name,
11490 mips_build_function_type (d->function_type),
11491 i, BUILT_IN_MD, NULL, NULL);
11495 /* Take argument ARGNO from EXP's argument list and convert it into a
11496 form suitable for input operand OPNO of instruction ICODE. Return the
11500 mips_prepare_builtin_arg (enum insn_code icode,
11501 unsigned int opno, tree exp, unsigned int argno)
11504 enum machine_mode mode;
11506 value = expand_normal (CALL_EXPR_ARG (exp, argno));
11507 mode = insn_data[icode].operand[opno].mode;
11508 if (!insn_data[icode].operand[opno].predicate (value, mode))
11510 /* Cope with address operands, where MODE is not the mode of
11512 if (GET_MODE (value) == VOIDmode)
11513 value = copy_to_mode_reg (mode, value);
11515 value = copy_to_reg (value);
11517 /* Check the predicate again. */
11518 if (!insn_data[icode].operand[opno].predicate (value, mode))
11520 error ("invalid argument to built-in function");
11528 /* Return an rtx suitable for output operand OP of instruction ICODE.
11529 If TARGET is non-null, try to use it where possible. */
11532 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
11534 enum machine_mode mode;
11536 mode = insn_data[icode].operand[op].mode;
11537 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
11538 target = gen_reg_rtx (mode);
11543 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
11544 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
11545 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
11546 suggests a good place to put the result. */
11549 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
11552 rtx ops[MAX_RECOG_OPERANDS];
11555 /* Map any target to operand 0. */
11559 ops[opno] = mips_prepare_builtin_target (icode, opno, target);
11563 /* Map the arguments to the other operands. The n_operands value
11564 for an expander includes match_dups and match_scratches as well as
11565 match_operands, so n_operands is only an upper bound on the number
11566 of arguments to the expander function. */
11567 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
11568 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
11569 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
11574 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11578 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11582 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11586 gcc_unreachable ();
11591 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
11592 function; TYPE says which. EXP is the CALL_EXPR that calls the
11593 function, ICODE is the instruction that should be used to compare
11594 the first two arguments, and COND is the condition it should test.
11595 TARGET, if nonnull, suggests a good place to put the result. */
11598 mips_expand_builtin_movtf (enum mips_builtin_type type,
11599 enum insn_code icode, enum mips_fp_condition cond,
11600 rtx target, tree exp)
11602 rtx cmp_result, op0, op1;
11604 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11605 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11606 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11607 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11609 icode = CODE_FOR_mips_cond_move_tf_ps;
11610 target = mips_prepare_builtin_target (icode, 0, target);
11611 if (type == MIPS_BUILTIN_MOVT)
11613 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11614 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11618 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11619 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11621 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11625 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11626 into TARGET otherwise. Return TARGET. */
11629 mips_builtin_branch_and_move (rtx condition, rtx target,
11630 rtx value_if_true, rtx value_if_false)
11632 rtx true_label, done_label;
11634 true_label = gen_label_rtx ();
11635 done_label = gen_label_rtx ();
11637 /* First assume that CONDITION is false. */
11638 mips_emit_move (target, value_if_false);
11640 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11641 emit_jump_insn (gen_condjump (condition, true_label));
11642 emit_jump_insn (gen_jump (done_label));
11645 /* Fix TARGET if CONDITION is true. */
11646 emit_label (true_label);
11647 mips_emit_move (target, value_if_true);
11649 emit_label (done_label);
11653 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
11654 the CALL_EXPR that calls the function, ICODE is the code of the
11655 comparison instruction, and COND is the condition it should test.
11656 TARGET, if nonnull, suggests a good place to put the boolean result. */
11659 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11660 enum insn_code icode, enum mips_fp_condition cond,
11661 rtx target, tree exp)
11663 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
11666 if (target == 0 || GET_MODE (target) != SImode)
11667 target = gen_reg_rtx (SImode);
11669 /* The instruction should have a target operand, an operand for each
11670 argument, and an operand for COND. */
11671 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
11673 /* Prepare the operands to the comparison. */
11674 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11675 for (argno = 0; argno < call_expr_nargs (exp); argno++)
11676 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
11678 switch (insn_data[icode].n_operands)
11681 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
11686 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
11687 args[2], args[3], GEN_INT (cond)));
11691 gcc_unreachable ();
11694 /* If the comparison sets more than one register, we define the result
11695 to be 0 if all registers are false and -1 if all registers are true.
11696 The value of the complete result is indeterminate otherwise. */
11697 switch (builtin_type)
11699 case MIPS_BUILTIN_CMP_ALL:
11700 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11701 return mips_builtin_branch_and_move (condition, target,
11702 const0_rtx, const1_rtx);
11704 case MIPS_BUILTIN_CMP_UPPER:
11705 case MIPS_BUILTIN_CMP_LOWER:
11706 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11707 condition = gen_single_cc (cmp_result, offset);
11708 return mips_builtin_branch_and_move (condition, target,
11709 const1_rtx, const0_rtx);
11712 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11713 return mips_builtin_branch_and_move (condition, target,
11714 const1_rtx, const0_rtx);
11718 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
11719 if nonnull, suggests a good place to put the boolean result. */
11722 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11724 rtx condition, cmp_result;
11727 if (target == 0 || GET_MODE (target) != SImode)
11728 target = gen_reg_rtx (SImode);
11730 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11732 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11737 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11738 return mips_builtin_branch_and_move (condition, target,
11739 const1_rtx, const0_rtx);
11742 /* Implement TARGET_EXPAND_BUILTIN. */
11745 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11746 enum machine_mode mode ATTRIBUTE_UNUSED,
11747 int ignore ATTRIBUTE_UNUSED)
11750 unsigned int fcode, avail;
11751 const struct mips_builtin_description *d;
11753 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11754 fcode = DECL_FUNCTION_CODE (fndecl);
11755 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
11756 d = &mips_builtins[fcode];
11757 avail = d->avail ();
11758 gcc_assert (avail != 0);
11761 error ("built-in function %qs not supported for MIPS16",
11762 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
11765 switch (d->builtin_type)
11767 case MIPS_BUILTIN_DIRECT:
11768 return mips_expand_builtin_direct (d->icode, target, exp, true);
11770 case MIPS_BUILTIN_DIRECT_NO_TARGET:
11771 return mips_expand_builtin_direct (d->icode, target, exp, false);
11773 case MIPS_BUILTIN_MOVT:
11774 case MIPS_BUILTIN_MOVF:
11775 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
11776 d->cond, target, exp);
11778 case MIPS_BUILTIN_CMP_ANY:
11779 case MIPS_BUILTIN_CMP_ALL:
11780 case MIPS_BUILTIN_CMP_UPPER:
11781 case MIPS_BUILTIN_CMP_LOWER:
11782 case MIPS_BUILTIN_CMP_SINGLE:
11783 return mips_expand_builtin_compare (d->builtin_type, d->icode,
11784 d->cond, target, exp);
11786 case MIPS_BUILTIN_BPOSGE32:
11787 return mips_expand_builtin_bposge (d->builtin_type, target);
11789 gcc_unreachable ();
11792 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
11793 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
11794 struct mips16_constant {
11795 struct mips16_constant *next;
11798 enum machine_mode mode;
11801 /* Information about an incomplete MIPS16 constant pool. FIRST is the
11802 first constant, HIGHEST_ADDRESS is the highest address that the first
11803 byte of the pool can have, and INSN_ADDRESS is the current instruction
11805 struct mips16_constant_pool {
11806 struct mips16_constant *first;
11807 int highest_address;
11811 /* Add constant VALUE to POOL and return its label. MODE is the
11812 value's mode (used for CONST_INTs, etc.). */
11815 mips16_add_constant (struct mips16_constant_pool *pool,
11816 rtx value, enum machine_mode mode)
11818 struct mips16_constant **p, *c;
11819 bool first_of_size_p;
11821 /* See whether the constant is already in the pool. If so, return the
11822 existing label, otherwise leave P pointing to the place where the
11823 constant should be added.
11825 Keep the pool sorted in increasing order of mode size so that we can
11826 reduce the number of alignments needed. */
11827 first_of_size_p = true;
11828 for (p = &pool->first; *p != 0; p = &(*p)->next)
11830 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
11831 return (*p)->label;
11832 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
11834 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
11835 first_of_size_p = false;
11838 /* In the worst case, the constant needed by the earliest instruction
11839 will end up at the end of the pool. The entire pool must then be
11840 accessible from that instruction.
11842 When adding the first constant, set the pool's highest address to
11843 the address of the first out-of-range byte. Adjust this address
11844 downwards each time a new constant is added. */
11845 if (pool->first == 0)
11846 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
11847 of the instruction with the lowest two bits clear. The base PC
11848 value for LDPC has the lowest three bits clear. Assume the worst
11849 case here; namely that the PC-relative instruction occupies the
11850 last 2 bytes in an aligned word. */
11851 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
11852 pool->highest_address -= GET_MODE_SIZE (mode);
11853 if (first_of_size_p)
11854 /* Take into account the worst possible padding due to alignment. */
11855 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
11857 /* Create a new entry. */
11858 c = XNEW (struct mips16_constant);
11861 c->label = gen_label_rtx ();
11868 /* Output constant VALUE after instruction INSN and return the last
11869 instruction emitted. MODE is the mode of the constant. */
11872 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
11874 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
11876 rtx size = GEN_INT (GET_MODE_SIZE (mode));
11877 return emit_insn_after (gen_consttable_int (value, size), insn);
11880 if (SCALAR_FLOAT_MODE_P (mode))
11881 return emit_insn_after (gen_consttable_float (value), insn);
11883 if (VECTOR_MODE_P (mode))
11887 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
11888 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
11889 CONST_VECTOR_ELT (value, i), insn);
11893 gcc_unreachable ();
11896 /* Dump out the constants in CONSTANTS after INSN. */
11899 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
11901 struct mips16_constant *c, *next;
11905 for (c = constants; c != NULL; c = next)
11907 /* If necessary, increase the alignment of PC. */
11908 if (align < GET_MODE_SIZE (c->mode))
11910 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
11911 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
11913 align = GET_MODE_SIZE (c->mode);
11915 insn = emit_label_after (c->label, insn);
11916 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
11922 emit_barrier_after (insn);
11925 /* Return the length of instruction INSN. */
11928 mips16_insn_length (rtx insn)
11932 rtx body = PATTERN (insn);
11933 if (GET_CODE (body) == ADDR_VEC)
11934 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
11935 if (GET_CODE (body) == ADDR_DIFF_VEC)
11936 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
11938 return get_attr_length (insn);
11941 /* If *X is a symbolic constant that refers to the constant pool, add
11942 the constant to POOL and rewrite *X to use the constant's label. */
11945 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
11947 rtx base, offset, label;
11949 split_const (*x, &base, &offset);
11950 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
11952 label = mips16_add_constant (pool, get_pool_constant (base),
11953 get_pool_mode (base));
11954 base = gen_rtx_LABEL_REF (Pmode, label);
11955 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
11959 /* This structure is used to communicate with mips16_rewrite_pool_refs.
11960 INSN is the instruction we're rewriting and POOL points to the current
11962 struct mips16_rewrite_pool_refs_info {
11964 struct mips16_constant_pool *pool;
11967 /* Rewrite *X so that constant pool references refer to the constant's
11968 label instead. DATA points to a mips16_rewrite_pool_refs_info
11972 mips16_rewrite_pool_refs (rtx *x, void *data)
11974 struct mips16_rewrite_pool_refs_info *info =
11975 (struct mips16_rewrite_pool_refs_info *) data;
11977 if (force_to_mem_operand (*x, Pmode))
11979 rtx mem = force_const_mem (GET_MODE (*x), *x);
11980 validate_change (info->insn, x, mem, false);
11985 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
11989 if (TARGET_MIPS16_TEXT_LOADS)
11990 mips16_rewrite_pool_constant (info->pool, x);
11992 return GET_CODE (*x) == CONST ? -1 : 0;
11995 /* Build MIPS16 constant pools. */
11998 mips16_lay_out_constants (void)
12000 struct mips16_constant_pool pool;
12001 struct mips16_rewrite_pool_refs_info info;
12004 if (!TARGET_MIPS16_PCREL_LOADS)
12007 split_all_insns_noflow ();
12009 memset (&pool, 0, sizeof (pool));
12010 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12012 /* Rewrite constant pool references in INSN. */
12017 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
12020 pool.insn_address += mips16_insn_length (insn);
12022 if (pool.first != NULL)
12024 /* If there are no natural barriers between the first user of
12025 the pool and the highest acceptable address, we'll need to
12026 create a new instruction to jump around the constant pool.
12027 In the worst case, this instruction will be 4 bytes long.
12029 If it's too late to do this transformation after INSN,
12030 do it immediately before INSN. */
12031 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
12035 label = gen_label_rtx ();
12037 jump = emit_jump_insn_before (gen_jump (label), insn);
12038 JUMP_LABEL (jump) = label;
12039 LABEL_NUSES (label) = 1;
12040 barrier = emit_barrier_after (jump);
12042 emit_label_after (label, barrier);
12043 pool.insn_address += 4;
12046 /* See whether the constant pool is now out of range of the first
12047 user. If so, output the constants after the previous barrier.
12048 Note that any instructions between BARRIER and INSN (inclusive)
12049 will use negative offsets to refer to the pool. */
12050 if (pool.insn_address > pool.highest_address)
12052 mips16_emit_constants (pool.first, barrier);
12056 else if (BARRIER_P (insn))
12060 mips16_emit_constants (pool.first, get_last_insn ());
12063 /* Return true if it is worth r10k_simplify_address's while replacing
12064 an address with X. We are looking for constants, and for addresses
12065 at a known offset from the incoming stack pointer. */
12068 r10k_simplified_address_p (rtx x)
12070 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
12072 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
12075 /* X is an expression that appears in INSN. Try to use the UD chains
12076 to simplify it, returning the simplified form on success and the
12077 original form otherwise. Replace the incoming value of $sp with
12078 virtual_incoming_args_rtx (which should never occur in X otherwise). */
12081 r10k_simplify_address (rtx x, rtx insn)
12083 rtx newx, op0, op1, set, def_insn, note;
12084 struct df_ref *use, *def;
12085 struct df_link *defs;
12090 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12091 if (op0 != XEXP (x, 0))
12092 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
12093 op0, GET_MODE (XEXP (x, 0)));
12095 else if (BINARY_P (x))
12097 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12098 op1 = r10k_simplify_address (XEXP (x, 1), insn);
12099 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
12100 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
12102 else if (GET_CODE (x) == LO_SUM)
12104 /* LO_SUMs can be offset from HIGHs, if we know they won't
12105 overflow. See mips_classify_address for the rationale behind
12107 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12108 if (GET_CODE (op0) == HIGH)
12109 newx = XEXP (x, 1);
12111 else if (REG_P (x))
12113 /* Uses are recorded by regno_reg_rtx, not X itself. */
12114 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
12116 defs = DF_REF_CHAIN (use);
12118 /* Require a single definition. */
12119 if (defs && defs->next == NULL)
12122 if (DF_REF_IS_ARTIFICIAL (def))
12124 /* Replace the incoming value of $sp with
12125 virtual_incoming_args_rtx. */
12126 if (x == stack_pointer_rtx
12127 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
12128 newx = virtual_incoming_args_rtx;
12130 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
12133 /* Make sure that DEF_INSN is a single set of REG. */
12134 def_insn = DF_REF_INSN (def);
12135 if (NONJUMP_INSN_P (def_insn))
12137 set = single_set (def_insn);
12138 if (set && rtx_equal_p (SET_DEST (set), x))
12140 /* Prefer to use notes, since the def-use chains
12141 are often shorter. */
12142 note = find_reg_equal_equiv_note (def_insn);
12144 newx = XEXP (note, 0);
12146 newx = SET_SRC (set);
12147 newx = r10k_simplify_address (newx, def_insn);
12153 if (newx && r10k_simplified_address_p (newx))
12158 /* Return true if ADDRESS is known to be an uncached address
12159 on R10K systems. */
12162 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
12164 unsigned HOST_WIDE_INT upper;
12166 /* Check for KSEG1. */
12167 if (address + 0x60000000 < 0x20000000)
12170 /* Check for uncached XKPHYS addresses. */
12171 if (Pmode == DImode)
12173 upper = (address >> 40) & 0xf9ffff;
12174 if (upper == 0x900000 || upper == 0xb80000)
12180 /* Return true if we can prove that an access to address X in instruction
12181 INSN would be safe from R10K speculation. This X is a general
12182 expression; it might not be a legitimate address. */
12185 r10k_safe_address_p (rtx x, rtx insn)
12188 HOST_WIDE_INT offset_val;
12190 x = r10k_simplify_address (x, insn);
12192 /* Check for references to the stack frame. It doesn't really matter
12193 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
12194 allows us to assume that accesses to any part of the eventual frame
12195 is safe from speculation at any point in the function. */
12196 mips_split_plus (x, &base, &offset_val);
12197 if (base == virtual_incoming_args_rtx
12198 && offset_val >= -cfun->machine->frame.total_size
12199 && offset_val < cfun->machine->frame.args_size)
12202 /* Check for uncached addresses. */
12203 if (CONST_INT_P (x))
12204 return r10k_uncached_address_p (INTVAL (x));
12206 /* Check for accesses to a static object. */
12207 split_const (x, &base, &offset);
12208 return offset_within_block_p (base, INTVAL (offset));
12211 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
12212 an in-range access to an automatic variable, or to an object with
12213 a link-time-constant address. */
12216 r10k_safe_mem_expr_p (tree expr, rtx offset)
12218 if (expr == NULL_TREE
12219 || offset == NULL_RTX
12220 || !CONST_INT_P (offset)
12221 || INTVAL (offset) < 0
12222 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
12225 while (TREE_CODE (expr) == COMPONENT_REF)
12227 expr = TREE_OPERAND (expr, 0);
12228 if (expr == NULL_TREE)
12232 return DECL_P (expr);
12235 /* A for_each_rtx callback for which DATA points to the instruction
12236 containing *X. Stop the search if we find a MEM that is not safe
12237 from R10K speculation. */
12240 r10k_needs_protection_p_1 (rtx *loc, void *data)
12248 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
12251 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
12257 /* A note_stores callback for which DATA points to an instruction pointer.
12258 If *DATA is nonnull, make it null if it X contains a MEM that is not
12259 safe from R10K speculation. */
12262 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12267 insn_ptr = (rtx *) data;
12268 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
12269 *insn_ptr = NULL_RTX;
12272 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
12273 Return nonzero if the call is not to a declared function. */
12276 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
12285 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
12291 /* Return true if instruction INSN needs to be protected by an R10K
12295 r10k_needs_protection_p (rtx insn)
12298 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
12300 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
12302 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
12303 return insn == NULL_RTX;
12306 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
12309 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
12310 edge is unconditional. */
12313 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
12318 FOR_EACH_EDGE (e, ei, bb->preds)
12319 if (!single_succ_p (e->src)
12320 || !TEST_BIT (protected_bbs, e->src->index)
12321 || (e->flags & EDGE_COMPLEX) != 0)
12326 /* Implement -mr10k-cache-barrier= for the current function. */
12329 r10k_insert_cache_barriers (void)
12331 int *rev_post_order;
12334 sbitmap protected_bbs;
12335 rtx insn, end, unprotected_region;
12339 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
12343 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. */
12344 compute_bb_for_insn ();
12346 /* Create def-use chains. */
12347 df_set_flags (DF_EQ_NOTES);
12348 df_chain_add_problem (DF_UD_CHAIN);
12351 /* Calculate dominators. */
12352 calculate_dominance_info (CDI_DOMINATORS);
12354 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
12355 X is protected by a cache barrier. */
12356 protected_bbs = sbitmap_alloc (last_basic_block);
12357 sbitmap_zero (protected_bbs);
12359 /* Iterate over the basic blocks in reverse post-order. */
12360 rev_post_order = XNEWVEC (int, last_basic_block);
12361 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
12362 for (i = 0; i < n; i++)
12364 bb = BASIC_BLOCK (rev_post_order[i]);
12366 /* If this block is only reached by unconditional edges, and if the
12367 source of every edge is protected, the beginning of the block is
12369 if (r10k_protected_bb_p (bb, protected_bbs))
12370 unprotected_region = NULL_RTX;
12372 unprotected_region = pc_rtx;
12373 end = NEXT_INSN (BB_END (bb));
12375 /* UNPROTECTED_REGION is:
12377 - null if we are processing a protected region,
12378 - pc_rtx if we are processing an unprotected region but have
12379 not yet found the first instruction in it
12380 - the first instruction in an unprotected region otherwise. */
12381 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
12383 if (unprotected_region && INSN_P (insn))
12385 if (recog_memoized (insn) == CODE_FOR_mips_cache)
12386 /* This CACHE instruction protects the following code. */
12387 unprotected_region = NULL_RTX;
12390 /* See if INSN is the first instruction in this
12391 unprotected region. */
12392 if (unprotected_region == pc_rtx)
12393 unprotected_region = insn;
12395 /* See if INSN needs to be protected. If so,
12396 we must insert a cache barrier somewhere between
12397 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
12398 clear which position is better performance-wise,
12399 but as a tie-breaker, we assume that it is better
12400 to allow delay slots to be back-filled where
12401 possible, and that it is better not to insert
12402 barriers in the middle of already-scheduled code.
12403 We therefore insert the barrier at the beginning
12405 if (r10k_needs_protection_p (insn))
12407 emit_insn_before (gen_r10k_cache_barrier (),
12408 unprotected_region);
12409 unprotected_region = NULL_RTX;
12415 /* The called function is not required to protect the exit path.
12416 The code that follows a call is therefore unprotected. */
12417 unprotected_region = pc_rtx;
12420 /* Record whether the end of this block is protected. */
12421 if (unprotected_region == NULL_RTX)
12422 SET_BIT (protected_bbs, bb->index);
12424 XDELETEVEC (rev_post_order);
12426 sbitmap_free (protected_bbs);
12428 free_dominance_info (CDI_DOMINATORS);
12430 df_finish_pass (false);
12432 free_bb_for_insn ();
12435 /* A temporary variable used by for_each_rtx callbacks, etc. */
12436 static rtx mips_sim_insn;
12438 /* A structure representing the state of the processor pipeline.
12439 Used by the mips_sim_* family of functions. */
12441 /* The maximum number of instructions that can be issued in a cycle.
12442 (Caches mips_issue_rate.) */
12443 unsigned int issue_rate;
12445 /* The current simulation time. */
12448 /* How many more instructions can be issued in the current cycle. */
12449 unsigned int insns_left;
12451 /* LAST_SET[X].INSN is the last instruction to set register X.
12452 LAST_SET[X].TIME is the time at which that instruction was issued.
12453 INSN is null if no instruction has yet set register X. */
12457 } last_set[FIRST_PSEUDO_REGISTER];
12459 /* The pipeline's current DFA state. */
12463 /* Reset STATE to the initial simulation state. */
12466 mips_sim_reset (struct mips_sim *state)
12469 state->insns_left = state->issue_rate;
12470 memset (&state->last_set, 0, sizeof (state->last_set));
12471 state_reset (state->dfa_state);
12474 /* Initialize STATE before its first use. DFA_STATE points to an
12475 allocated but uninitialized DFA state. */
12478 mips_sim_init (struct mips_sim *state, state_t dfa_state)
12480 state->issue_rate = mips_issue_rate ();
12481 state->dfa_state = dfa_state;
12482 mips_sim_reset (state);
12485 /* Advance STATE by one clock cycle. */
12488 mips_sim_next_cycle (struct mips_sim *state)
12491 state->insns_left = state->issue_rate;
12492 state_transition (state->dfa_state, 0);
12495 /* Advance simulation state STATE until instruction INSN can read
12499 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
12501 unsigned int regno, end_regno;
12503 end_regno = END_REGNO (reg);
12504 for (regno = REGNO (reg); regno < end_regno; regno++)
12505 if (state->last_set[regno].insn != 0)
12509 t = (state->last_set[regno].time
12510 + insn_latency (state->last_set[regno].insn, insn));
12511 while (state->time < t)
12512 mips_sim_next_cycle (state);
12516 /* A for_each_rtx callback. If *X is a register, advance simulation state
12517 DATA until mips_sim_insn can read the register's value. */
12520 mips_sim_wait_regs_2 (rtx *x, void *data)
12523 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
12527 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
12530 mips_sim_wait_regs_1 (rtx *x, void *data)
12532 for_each_rtx (x, mips_sim_wait_regs_2, data);
12535 /* Advance simulation state STATE until all of INSN's register
12536 dependencies are satisfied. */
12539 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
12541 mips_sim_insn = insn;
12542 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
12545 /* Advance simulation state STATE until the units required by
12546 instruction INSN are available. */
12549 mips_sim_wait_units (struct mips_sim *state, rtx insn)
12553 tmp_state = alloca (state_size ());
12554 while (state->insns_left == 0
12555 || (memcpy (tmp_state, state->dfa_state, state_size ()),
12556 state_transition (tmp_state, insn) >= 0))
12557 mips_sim_next_cycle (state);
12560 /* Advance simulation state STATE until INSN is ready to issue. */
12563 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
12565 mips_sim_wait_regs (state, insn);
12566 mips_sim_wait_units (state, insn);
12569 /* mips_sim_insn has just set X. Update the LAST_SET array
12570 in simulation state DATA. */
12573 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
12575 struct mips_sim *state;
12577 state = (struct mips_sim *) data;
12580 unsigned int regno, end_regno;
12582 end_regno = END_REGNO (x);
12583 for (regno = REGNO (x); regno < end_regno; regno++)
12585 state->last_set[regno].insn = mips_sim_insn;
12586 state->last_set[regno].time = state->time;
12591 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
12592 can issue immediately (i.e., that mips_sim_wait_insn has already
12596 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
12598 state_transition (state->dfa_state, insn);
12599 state->insns_left--;
12601 mips_sim_insn = insn;
12602 note_stores (PATTERN (insn), mips_sim_record_set, state);
12605 /* Simulate issuing a NOP in state STATE. */
12608 mips_sim_issue_nop (struct mips_sim *state)
12610 if (state->insns_left == 0)
12611 mips_sim_next_cycle (state);
12612 state->insns_left--;
12615 /* Update simulation state STATE so that it's ready to accept the instruction
12616 after INSN. INSN should be part of the main rtl chain, not a member of a
12620 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
12622 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
12624 mips_sim_issue_nop (state);
12626 switch (GET_CODE (SEQ_BEGIN (insn)))
12630 /* We can't predict the processor state after a call or label. */
12631 mips_sim_reset (state);
12635 /* The delay slots of branch likely instructions are only executed
12636 when the branch is taken. Therefore, if the caller has simulated
12637 the delay slot instruction, STATE does not really reflect the state
12638 of the pipeline for the instruction after the delay slot. Also,
12639 branch likely instructions tend to incur a penalty when not taken,
12640 so there will probably be an extra delay between the branch and
12641 the instruction after the delay slot. */
12642 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
12643 mips_sim_reset (state);
12651 /* The VR4130 pipeline issues aligned pairs of instructions together,
12652 but it stalls the second instruction if it depends on the first.
12653 In order to cut down the amount of logic required, this dependence
12654 check is not based on a full instruction decode. Instead, any non-SPECIAL
12655 instruction is assumed to modify the register specified by bits 20-16
12656 (which is usually the "rt" field).
12658 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
12659 input, so we can end up with a false dependence between the branch
12660 and its delay slot. If this situation occurs in instruction INSN,
12661 try to avoid it by swapping rs and rt. */
12664 vr4130_avoid_branch_rt_conflict (rtx insn)
12668 first = SEQ_BEGIN (insn);
12669 second = SEQ_END (insn);
12671 && NONJUMP_INSN_P (second)
12672 && GET_CODE (PATTERN (first)) == SET
12673 && GET_CODE (SET_DEST (PATTERN (first))) == PC
12674 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
12676 /* Check for the right kind of condition. */
12677 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
12678 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
12679 && REG_P (XEXP (cond, 0))
12680 && REG_P (XEXP (cond, 1))
12681 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
12682 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
12684 /* SECOND mentions the rt register but not the rs register. */
12685 rtx tmp = XEXP (cond, 0);
12686 XEXP (cond, 0) = XEXP (cond, 1);
12687 XEXP (cond, 1) = tmp;
12692 /* Implement -mvr4130-align. Go through each basic block and simulate the
12693 processor pipeline. If we find that a pair of instructions could execute
12694 in parallel, and the first of those instructions is not 8-byte aligned,
12695 insert a nop to make it aligned. */
12698 vr4130_align_insns (void)
12700 struct mips_sim state;
12701 rtx insn, subinsn, last, last2, next;
12706 /* LAST is the last instruction before INSN to have a nonzero length.
12707 LAST2 is the last such instruction before LAST. */
12711 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
12714 mips_sim_init (&state, alloca (state_size ()));
12715 for (insn = get_insns (); insn != 0; insn = next)
12717 unsigned int length;
12719 next = NEXT_INSN (insn);
12721 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
12722 This isn't really related to the alignment pass, but we do it on
12723 the fly to avoid a separate instruction walk. */
12724 vr4130_avoid_branch_rt_conflict (insn);
12726 if (USEFUL_INSN_P (insn))
12727 FOR_EACH_SUBINSN (subinsn, insn)
12729 mips_sim_wait_insn (&state, subinsn);
12731 /* If we want this instruction to issue in parallel with the
12732 previous one, make sure that the previous instruction is
12733 aligned. There are several reasons why this isn't worthwhile
12734 when the second instruction is a call:
12736 - Calls are less likely to be performance critical,
12737 - There's a good chance that the delay slot can execute
12738 in parallel with the call.
12739 - The return address would then be unaligned.
12741 In general, if we're going to insert a nop between instructions
12742 X and Y, it's better to insert it immediately after X. That
12743 way, if the nop makes Y aligned, it will also align any labels
12744 between X and Y. */
12745 if (state.insns_left != state.issue_rate
12746 && !CALL_P (subinsn))
12748 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
12750 /* SUBINSN is the first instruction in INSN and INSN is
12751 aligned. We want to align the previous instruction
12752 instead, so insert a nop between LAST2 and LAST.
12754 Note that LAST could be either a single instruction
12755 or a branch with a delay slot. In the latter case,
12756 LAST, like INSN, is already aligned, but the delay
12757 slot must have some extra delay that stops it from
12758 issuing at the same time as the branch. We therefore
12759 insert a nop before the branch in order to align its
12761 emit_insn_after (gen_nop (), last2);
12764 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
12766 /* SUBINSN is the delay slot of INSN, but INSN is
12767 currently unaligned. Insert a nop between
12768 LAST and INSN to align it. */
12769 emit_insn_after (gen_nop (), last);
12773 mips_sim_issue_insn (&state, subinsn);
12775 mips_sim_finish_insn (&state, insn);
12777 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
12778 length = get_attr_length (insn);
12781 /* If the instruction is an asm statement or multi-instruction
12782 mips.md patern, the length is only an estimate. Insert an
12783 8 byte alignment after it so that the following instructions
12784 can be handled correctly. */
12785 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
12786 && (recog_memoized (insn) < 0 || length >= 8))
12788 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
12789 next = NEXT_INSN (next);
12790 mips_sim_next_cycle (&state);
12793 else if (length & 4)
12794 aligned_p = !aligned_p;
12799 /* See whether INSN is an aligned label. */
12800 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
12806 /* This structure records that the current function has a LO_SUM
12807 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
12808 the largest offset applied to BASE by all such LO_SUMs. */
12809 struct mips_lo_sum_offset {
12811 HOST_WIDE_INT offset;
12814 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
12817 mips_hash_base (rtx base)
12819 int do_not_record_p;
12821 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
12824 /* Hash-table callbacks for mips_lo_sum_offsets. */
12827 mips_lo_sum_offset_hash (const void *entry)
12829 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
12833 mips_lo_sum_offset_eq (const void *entry, const void *value)
12835 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
12836 (const_rtx) value);
12839 /* Look up symbolic constant X in HTAB, which is a hash table of
12840 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
12841 paired with a recorded LO_SUM, otherwise record X in the table. */
12844 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
12848 struct mips_lo_sum_offset *entry;
12850 /* Split X into a base and offset. */
12851 split_const (x, &base, &offset);
12852 if (UNSPEC_ADDRESS_P (base))
12853 base = UNSPEC_ADDRESS (base);
12855 /* Look up the base in the hash table. */
12856 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
12860 entry = (struct mips_lo_sum_offset *) *slot;
12861 if (option == INSERT)
12865 entry = XNEW (struct mips_lo_sum_offset);
12866 entry->base = base;
12867 entry->offset = INTVAL (offset);
12872 if (INTVAL (offset) > entry->offset)
12873 entry->offset = INTVAL (offset);
12876 return INTVAL (offset) <= entry->offset;
12879 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
12880 Record every LO_SUM in *LOC. */
12883 mips_record_lo_sum (rtx *loc, void *data)
12885 if (GET_CODE (*loc) == LO_SUM)
12886 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
12890 /* Return true if INSN is a SET of an orphaned high-part relocation.
12891 HTAB is a hash table of mips_lo_sum_offsets that describes all the
12892 LO_SUMs in the current function. */
12895 mips_orphaned_high_part_p (htab_t htab, rtx insn)
12897 enum mips_symbol_type type;
12900 set = single_set (insn);
12903 /* Check for %his. */
12905 if (GET_CODE (x) == HIGH
12906 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
12907 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
12909 /* Check for local %gots (and %got_pages, which is redundant but OK). */
12910 if (GET_CODE (x) == UNSPEC
12911 && XINT (x, 1) == UNSPEC_LOAD_GOT
12912 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
12913 SYMBOL_CONTEXT_LEA, &type)
12914 && type == SYMBOL_GOTOFF_PAGE)
12915 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
12920 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
12921 INSN and a previous instruction, avoid it by inserting nops after
12924 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
12925 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
12926 before using the value of that register. *HILO_DELAY counts the
12927 number of instructions since the last hilo hazard (that is,
12928 the number of instructions since the last MFLO or MFHI).
12930 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
12931 for the next instruction.
12933 LO_REG is an rtx for the LO register, used in dependence checking. */
12936 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
12937 rtx *delayed_reg, rtx lo_reg)
12942 pattern = PATTERN (insn);
12944 /* Do not put the whole function in .set noreorder if it contains
12945 an asm statement. We don't know whether there will be hazards
12946 between the asm statement and the gcc-generated code. */
12947 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
12948 cfun->machine->all_noreorder_p = false;
12950 /* Ignore zero-length instructions (barriers and the like). */
12951 ninsns = get_attr_length (insn) / 4;
12955 /* Work out how many nops are needed. Note that we only care about
12956 registers that are explicitly mentioned in the instruction's pattern.
12957 It doesn't matter that calls use the argument registers or that they
12958 clobber hi and lo. */
12959 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
12960 nops = 2 - *hilo_delay;
12961 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
12966 /* Insert the nops between this instruction and the previous one.
12967 Each new nop takes us further from the last hilo hazard. */
12968 *hilo_delay += nops;
12970 emit_insn_after (gen_hazard_nop (), after);
12972 /* Set up the state for the next instruction. */
12973 *hilo_delay += ninsns;
12975 if (INSN_CODE (insn) >= 0)
12976 switch (get_attr_hazard (insn))
12986 set = single_set (insn);
12988 *delayed_reg = SET_DEST (set);
12993 /* Go through the instruction stream and insert nops where necessary.
12994 Also delete any high-part relocations whose partnering low parts
12995 are now all dead. See if the whole function can then be put into
12996 .set noreorder and .set nomacro. */
12999 mips_reorg_process_insns (void)
13001 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
13005 /* Force all instructions to be split into their final form. */
13006 split_all_insns_noflow ();
13008 /* Recalculate instruction lengths without taking nops into account. */
13009 cfun->machine->ignore_hazard_length_p = true;
13010 shorten_branches (get_insns ());
13012 cfun->machine->all_noreorder_p = true;
13014 /* We don't track MIPS16 PC-relative offsets closely enough to make
13015 a good job of "set .noreorder" code in MIPS16 mode. */
13017 cfun->machine->all_noreorder_p = false;
13019 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
13020 if (!TARGET_EXPLICIT_RELOCS)
13021 cfun->machine->all_noreorder_p = false;
13023 /* Profiled functions can't be all noreorder because the profiler
13024 support uses assembler macros. */
13026 cfun->machine->all_noreorder_p = false;
13028 /* Code compiled with -mfix-vr4120 can't be all noreorder because
13029 we rely on the assembler to work around some errata. */
13030 if (TARGET_FIX_VR4120)
13031 cfun->machine->all_noreorder_p = false;
13033 /* The same is true for -mfix-vr4130 if we might generate MFLO or
13034 MFHI instructions. Note that we avoid using MFLO and MFHI if
13035 the VR4130 MACC and DMACC instructions are available instead;
13036 see the *mfhilo_{si,di}_macc patterns. */
13037 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
13038 cfun->machine->all_noreorder_p = false;
13040 htab = htab_create (37, mips_lo_sum_offset_hash,
13041 mips_lo_sum_offset_eq, free);
13043 /* Make a first pass over the instructions, recording all the LO_SUMs. */
13044 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13045 FOR_EACH_SUBINSN (subinsn, insn)
13046 if (INSN_P (subinsn))
13047 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
13052 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
13054 /* Make a second pass over the instructions. Delete orphaned
13055 high-part relocations or turn them into NOPs. Avoid hazards
13056 by inserting NOPs. */
13057 for (insn = get_insns (); insn != 0; insn = next_insn)
13059 next_insn = NEXT_INSN (insn);
13062 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
13064 /* If we find an orphaned high-part relocation in a delay
13065 slot, it's easier to turn that instruction into a NOP than
13066 to delete it. The delay slot will be a NOP either way. */
13067 FOR_EACH_SUBINSN (subinsn, insn)
13068 if (INSN_P (subinsn))
13070 if (mips_orphaned_high_part_p (htab, subinsn))
13072 PATTERN (subinsn) = gen_nop ();
13073 INSN_CODE (subinsn) = CODE_FOR_nop;
13075 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
13076 &delayed_reg, lo_reg);
13082 /* INSN is a single instruction. Delete it if it's an
13083 orphaned high-part relocation. */
13084 if (mips_orphaned_high_part_p (htab, insn))
13085 delete_insn (insn);
13086 /* Also delete cache barriers if the last instruction
13087 was an annulled branch. INSN will not be speculatively
13089 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
13091 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
13092 delete_insn (insn);
13095 mips_avoid_hazard (last_insn, insn, &hilo_delay,
13096 &delayed_reg, lo_reg);
13103 htab_delete (htab);
13106 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
13111 mips16_lay_out_constants ();
13112 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
13113 r10k_insert_cache_barriers ();
13114 if (mips_base_delayed_branch)
13115 dbr_schedule (get_insns ());
13116 mips_reorg_process_insns ();
13118 && TARGET_EXPLICIT_RELOCS
13120 && TARGET_VR4130_ALIGN)
13121 vr4130_align_insns ();
13124 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
13125 in order to avoid duplicating too much logic from elsewhere. */
13128 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13129 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13132 rtx this_rtx, temp1, temp2, insn, fnaddr;
13133 bool use_sibcall_p;
13135 /* Pretend to be a post-reload pass while generating rtl. */
13136 reload_completed = 1;
13138 /* Mark the end of the (empty) prologue. */
13139 emit_note (NOTE_INSN_PROLOGUE_END);
13141 /* Determine if we can use a sibcall to call FUNCTION directly. */
13142 fnaddr = XEXP (DECL_RTL (function), 0);
13143 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
13144 && const_call_insn_operand (fnaddr, Pmode));
13146 /* Determine if we need to load FNADDR from the GOT. */
13148 && (mips_got_symbol_type_p
13149 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
13151 /* Pick a global pointer. Use a call-clobbered register if
13152 TARGET_CALL_SAVED_GP. */
13153 cfun->machine->global_pointer
13154 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
13155 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
13157 /* Set up the global pointer for n32 or n64 abicalls. */
13158 mips_emit_loadgp ();
13161 /* We need two temporary registers in some cases. */
13162 temp1 = gen_rtx_REG (Pmode, 2);
13163 temp2 = gen_rtx_REG (Pmode, 3);
13165 /* Find out which register contains the "this" pointer. */
13166 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13167 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
13169 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
13171 /* Add DELTA to THIS_RTX. */
13174 rtx offset = GEN_INT (delta);
13175 if (!SMALL_OPERAND (delta))
13177 mips_emit_move (temp1, offset);
13180 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
13183 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
13184 if (vcall_offset != 0)
13188 /* Set TEMP1 to *THIS_RTX. */
13189 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
13191 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
13192 addr = mips_add_offset (temp2, temp1, vcall_offset);
13194 /* Load the offset and add it to THIS_RTX. */
13195 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
13196 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
13199 /* Jump to the target function. Use a sibcall if direct jumps are
13200 allowed, otherwise load the address into a register first. */
13203 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
13204 SIBLING_CALL_P (insn) = 1;
13208 /* This is messy. GAS treats "la $25,foo" as part of a call
13209 sequence and may allow a global "foo" to be lazily bound.
13210 The general move patterns therefore reject this combination.
13212 In this context, lazy binding would actually be OK
13213 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
13214 TARGET_CALL_SAVED_GP; see mips_load_call_address.
13215 We must therefore load the address via a temporary
13216 register if mips_dangerous_for_la25_p.
13218 If we jump to the temporary register rather than $25,
13219 the assembler can use the move insn to fill the jump's
13222 We can use the same technique for MIPS16 code, where $25
13223 is not a valid JR register. */
13224 if (TARGET_USE_PIC_FN_ADDR_REG
13226 && !mips_dangerous_for_la25_p (fnaddr))
13227 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
13228 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
13230 if (TARGET_USE_PIC_FN_ADDR_REG
13231 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
13232 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
13233 emit_jump_insn (gen_indirect_jump (temp1));
13236 /* Run just enough of rest_of_compilation. This sequence was
13237 "borrowed" from alpha.c. */
13238 insn = get_insns ();
13239 insn_locators_alloc ();
13240 split_all_insns_noflow ();
13241 mips16_lay_out_constants ();
13242 shorten_branches (insn);
13243 final_start_function (insn, file, 1);
13244 final (insn, file, 1);
13245 final_end_function ();
13246 free_after_compilation (cfun);
13248 /* Clean up the vars set above. Note that final_end_function resets
13249 the global pointer for us. */
13250 reload_completed = 0;
13253 /* The last argument passed to mips_set_mips16_mode, or negative if the
13254 function hasn't been called yet.
13256 There are two copies of this information. One is saved and restored
13257 by the PCH process while the other is specific to this compiler
13258 invocation. The information calculated by mips_set_mips16_mode
13259 is invalid unless the two variables are the same. */
13260 static int was_mips16_p = -1;
13261 static GTY(()) int was_mips16_pch_p = -1;
13263 /* Set up the target-dependent global state so that it matches the
13264 current function's ISA mode. */
13267 mips_set_mips16_mode (int mips16_p)
13269 if (mips16_p == was_mips16_p
13270 && mips16_p == was_mips16_pch_p)
13273 /* Restore base settings of various flags. */
13274 target_flags = mips_base_target_flags;
13275 flag_schedule_insns = mips_base_schedule_insns;
13276 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
13277 flag_move_loop_invariants = mips_base_move_loop_invariants;
13278 align_loops = mips_base_align_loops;
13279 align_jumps = mips_base_align_jumps;
13280 align_functions = mips_base_align_functions;
13284 /* Switch to MIPS16 mode. */
13285 target_flags |= MASK_MIPS16;
13287 /* Don't run the scheduler before reload, since it tends to
13288 increase register pressure. */
13289 flag_schedule_insns = 0;
13291 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
13292 the whole function to be in a single section. */
13293 flag_reorder_blocks_and_partition = 0;
13295 /* Don't move loop invariants, because it tends to increase
13296 register pressure. It also introduces an extra move in cases
13297 where the constant is the first operand in a two-operand binary
13298 instruction, or when it forms a register argument to a functon
13300 flag_move_loop_invariants = 0;
13302 target_flags |= MASK_EXPLICIT_RELOCS;
13304 /* Experiments suggest we get the best overall section-anchor
13305 results from using the range of an unextended LW or SW. Code
13306 that makes heavy use of byte or short accesses can do better
13307 with ranges of 0...31 and 0...63 respectively, but most code is
13308 sensitive to the range of LW and SW instead. */
13309 targetm.min_anchor_offset = 0;
13310 targetm.max_anchor_offset = 127;
13312 if (flag_pic && !TARGET_OLDABI)
13313 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
13316 sorry ("MIPS16 -mxgot code");
13318 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
13319 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
13323 /* Switch to normal (non-MIPS16) mode. */
13324 target_flags &= ~MASK_MIPS16;
13326 /* Provide default values for align_* for 64-bit targets. */
13329 if (align_loops == 0)
13331 if (align_jumps == 0)
13333 if (align_functions == 0)
13334 align_functions = 8;
13337 targetm.min_anchor_offset = -32768;
13338 targetm.max_anchor_offset = 32767;
13341 /* (Re)initialize MIPS target internals for new ISA. */
13342 mips_init_relocs ();
13344 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
13345 /* Reinitialize target-dependent state. */
13348 was_mips16_p = mips16_p;
13349 was_mips16_pch_p = mips16_p;
13352 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
13353 function should use the MIPS16 ISA and switch modes accordingly. */
13356 mips_set_current_function (tree fndecl)
13358 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
13361 /* Allocate a chunk of memory for per-function machine-dependent data. */
13363 static struct machine_function *
13364 mips_init_machine_status (void)
13366 return ((struct machine_function *)
13367 ggc_alloc_cleared (sizeof (struct machine_function)));
13370 /* Return the processor associated with the given ISA level, or null
13371 if the ISA isn't valid. */
13373 static const struct mips_cpu_info *
13374 mips_cpu_info_from_isa (int isa)
13378 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
13379 if (mips_cpu_info_table[i].isa == isa)
13380 return mips_cpu_info_table + i;
13385 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13386 with a final "000" replaced by "k". Ignore case.
13388 Note: this function is shared between GCC and GAS. */
13391 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
13393 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13394 given++, canonical++;
13396 return ((*given == 0 && *canonical == 0)
13397 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13400 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13401 CPU name. We've traditionally allowed a lot of variation here.
13403 Note: this function is shared between GCC and GAS. */
13406 mips_matching_cpu_name_p (const char *canonical, const char *given)
13408 /* First see if the name matches exactly, or with a final "000"
13409 turned into "k". */
13410 if (mips_strict_matching_cpu_name_p (canonical, given))
13413 /* If not, try comparing based on numerical designation alone.
13414 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13415 if (TOLOWER (*given) == 'r')
13417 if (!ISDIGIT (*given))
13420 /* Skip over some well-known prefixes in the canonical name,
13421 hoping to find a number there too. */
13422 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13424 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13426 else if (TOLOWER (canonical[0]) == 'r')
13429 return mips_strict_matching_cpu_name_p (canonical, given);
13432 /* Return the mips_cpu_info entry for the processor or ISA given
13433 by CPU_STRING. Return null if the string isn't recognized.
13435 A similar function exists in GAS. */
13437 static const struct mips_cpu_info *
13438 mips_parse_cpu (const char *cpu_string)
13443 /* In the past, we allowed upper-case CPU names, but it doesn't
13444 work well with the multilib machinery. */
13445 for (s = cpu_string; *s != 0; s++)
13448 warning (0, "CPU names must be lower case");
13452 /* 'from-abi' selects the most compatible architecture for the given
13453 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13454 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13456 if (strcasecmp (cpu_string, "from-abi") == 0)
13457 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
13458 : ABI_NEEDS_64BIT_REGS ? 3
13459 : (TARGET_64BIT ? 3 : 1));
13461 /* 'default' has traditionally been a no-op. Probably not very useful. */
13462 if (strcasecmp (cpu_string, "default") == 0)
13465 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
13466 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
13467 return mips_cpu_info_table + i;
13472 /* Set up globals to generate code for the ISA or processor
13473 described by INFO. */
13476 mips_set_architecture (const struct mips_cpu_info *info)
13480 mips_arch_info = info;
13481 mips_arch = info->cpu;
13482 mips_isa = info->isa;
13486 /* Likewise for tuning. */
13489 mips_set_tune (const struct mips_cpu_info *info)
13493 mips_tune_info = info;
13494 mips_tune = info->cpu;
13498 /* Implement TARGET_HANDLE_OPTION. */
13501 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
13506 if (strcmp (arg, "32") == 0)
13508 else if (strcmp (arg, "o64") == 0)
13509 mips_abi = ABI_O64;
13510 else if (strcmp (arg, "n32") == 0)
13511 mips_abi = ABI_N32;
13512 else if (strcmp (arg, "64") == 0)
13514 else if (strcmp (arg, "eabi") == 0)
13515 mips_abi = ABI_EABI;
13522 return mips_parse_cpu (arg) != 0;
13525 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
13526 return mips_isa_option_info != 0;
13528 case OPT_mno_flush_func:
13529 mips_cache_flush_func = NULL;
13532 case OPT_mcode_readable_:
13533 if (strcmp (arg, "yes") == 0)
13534 mips_code_readable = CODE_READABLE_YES;
13535 else if (strcmp (arg, "pcrel") == 0)
13536 mips_code_readable = CODE_READABLE_PCREL;
13537 else if (strcmp (arg, "no") == 0)
13538 mips_code_readable = CODE_READABLE_NO;
13543 case OPT_mr10k_cache_barrier_:
13544 if (strcmp (arg, "load-store") == 0)
13545 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
13546 else if (strcmp (arg, "store") == 0)
13547 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
13548 else if (strcmp (arg, "none") == 0)
13549 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
13559 /* Implement OVERRIDE_OPTIONS. */
13562 mips_override_options (void)
13564 int i, start, regno, mode;
13566 /* Process flags as though we were generating non-MIPS16 code. */
13567 mips_base_mips16 = TARGET_MIPS16;
13568 target_flags &= ~MASK_MIPS16;
13570 #ifdef SUBTARGET_OVERRIDE_OPTIONS
13571 SUBTARGET_OVERRIDE_OPTIONS;
13574 /* Set the small data limit. */
13575 mips_small_data_threshold = (g_switch_set
13577 : MIPS_DEFAULT_GVALUE);
13579 /* The following code determines the architecture and register size.
13580 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
13581 The GAS and GCC code should be kept in sync as much as possible. */
13583 if (mips_arch_string != 0)
13584 mips_set_architecture (mips_parse_cpu (mips_arch_string));
13586 if (mips_isa_option_info != 0)
13588 if (mips_arch_info == 0)
13589 mips_set_architecture (mips_isa_option_info);
13590 else if (mips_arch_info->isa != mips_isa_option_info->isa)
13591 error ("%<-%s%> conflicts with the other architecture options, "
13592 "which specify a %s processor",
13593 mips_isa_option_info->name,
13594 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
13597 if (mips_arch_info == 0)
13599 #ifdef MIPS_CPU_STRING_DEFAULT
13600 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
13602 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
13606 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
13607 error ("%<-march=%s%> is not compatible with the selected ABI",
13608 mips_arch_info->name);
13610 /* Optimize for mips_arch, unless -mtune selects a different processor. */
13611 if (mips_tune_string != 0)
13612 mips_set_tune (mips_parse_cpu (mips_tune_string));
13614 if (mips_tune_info == 0)
13615 mips_set_tune (mips_arch_info);
13617 if ((target_flags_explicit & MASK_64BIT) != 0)
13619 /* The user specified the size of the integer registers. Make sure
13620 it agrees with the ABI and ISA. */
13621 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
13622 error ("%<-mgp64%> used with a 32-bit processor");
13623 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
13624 error ("%<-mgp32%> used with a 64-bit ABI");
13625 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
13626 error ("%<-mgp64%> used with a 32-bit ABI");
13630 /* Infer the integer register size from the ABI and processor.
13631 Restrict ourselves to 32-bit registers if that's all the
13632 processor has, or if the ABI cannot handle 64-bit registers. */
13633 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
13634 target_flags &= ~MASK_64BIT;
13636 target_flags |= MASK_64BIT;
13639 if ((target_flags_explicit & MASK_FLOAT64) != 0)
13641 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
13642 error ("unsupported combination: %s", "-mfp64 -msingle-float");
13643 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
13644 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
13645 else if (!TARGET_64BIT && TARGET_FLOAT64)
13647 if (!ISA_HAS_MXHC1)
13648 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
13649 " the target supports the mfhc1 and mthc1 instructions");
13650 else if (mips_abi != ABI_32)
13651 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
13657 /* -msingle-float selects 32-bit float registers. Otherwise the
13658 float registers should be the same size as the integer ones. */
13659 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
13660 target_flags |= MASK_FLOAT64;
13662 target_flags &= ~MASK_FLOAT64;
13665 /* End of code shared with GAS. */
13667 /* If no -mlong* option was given, infer it from the other options. */
13668 if ((target_flags_explicit & MASK_LONG64) == 0)
13670 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
13671 target_flags |= MASK_LONG64;
13673 target_flags &= ~MASK_LONG64;
13676 if (!TARGET_OLDABI)
13677 flag_pcc_struct_return = 0;
13679 /* Decide which rtx_costs structure to use. */
13681 mips_cost = &mips_rtx_cost_optimize_size;
13683 mips_cost = &mips_rtx_cost_data[mips_tune];
13685 /* If the user hasn't specified a branch cost, use the processor's
13687 if (mips_branch_cost == 0)
13688 mips_branch_cost = mips_cost->branch_cost;
13690 /* If neither -mbranch-likely nor -mno-branch-likely was given
13691 on the command line, set MASK_BRANCHLIKELY based on the target
13692 architecture and tuning flags. Annulled delay slots are a
13693 size win, so we only consider the processor-specific tuning
13694 for !optimize_size. */
13695 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
13697 if (ISA_HAS_BRANCHLIKELY
13699 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
13700 target_flags |= MASK_BRANCHLIKELY;
13702 target_flags &= ~MASK_BRANCHLIKELY;
13704 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
13705 warning (0, "the %qs architecture does not support branch-likely"
13706 " instructions", mips_arch_info->name);
13708 /* The effect of -mabicalls isn't defined for the EABI. */
13709 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
13711 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
13712 target_flags &= ~MASK_ABICALLS;
13715 if (TARGET_ABICALLS_PIC2)
13716 /* We need to set flag_pic for executables as well as DSOs
13717 because we may reference symbols that are not defined in
13718 the final executable. (MIPS does not use things like
13719 copy relocs, for example.)
13721 There is a body of code that uses __PIC__ to distinguish
13722 between -mabicalls and -mno-abicalls code. The non-__PIC__
13723 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
13724 long as any indirect jumps use $25. */
13727 /* -mvr4130-align is a "speed over size" optimization: it usually produces
13728 faster code, but at the expense of more nops. Enable it at -O3 and
13730 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
13731 target_flags |= MASK_VR4130_ALIGN;
13733 /* Prefer a call to memcpy over inline code when optimizing for size,
13734 though see MOVE_RATIO in mips.h. */
13735 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
13736 target_flags |= MASK_MEMCPY;
13738 /* If we have a nonzero small-data limit, check that the -mgpopt
13739 setting is consistent with the other target flags. */
13740 if (mips_small_data_threshold > 0)
13744 if (!TARGET_EXPLICIT_RELOCS)
13745 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
13747 TARGET_LOCAL_SDATA = false;
13748 TARGET_EXTERN_SDATA = false;
13752 if (TARGET_VXWORKS_RTP)
13753 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
13755 if (TARGET_ABICALLS)
13756 warning (0, "cannot use small-data accesses for %qs",
13761 #ifdef MIPS_TFMODE_FORMAT
13762 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
13765 /* Make sure that the user didn't turn off paired single support when
13766 MIPS-3D support is requested. */
13768 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
13769 && !TARGET_PAIRED_SINGLE_FLOAT)
13770 error ("%<-mips3d%> requires %<-mpaired-single%>");
13772 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
13774 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
13776 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
13777 and TARGET_HARD_FLOAT_ABI are both true. */
13778 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
13779 error ("%qs must be used with %qs",
13780 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
13781 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
13783 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
13785 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
13786 warning (0, "the %qs architecture does not support paired-single"
13787 " instructions", mips_arch_info->name);
13789 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13790 && !TARGET_CACHE_BUILTIN)
13792 error ("%qs requires a target that provides the %qs instruction",
13793 "-mr10k-cache-barrier", "cache");
13794 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
13797 /* If TARGET_DSPR2, enable MASK_DSP. */
13799 target_flags |= MASK_DSP;
13801 mips_init_print_operand_punct ();
13803 /* Set up array to map GCC register number to debug register number.
13804 Ignore the special purpose register numbers. */
13806 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
13808 mips_dbx_regno[i] = INVALID_REGNUM;
13809 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
13810 mips_dwarf_regno[i] = i;
13812 mips_dwarf_regno[i] = INVALID_REGNUM;
13815 start = GP_DBX_FIRST - GP_REG_FIRST;
13816 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
13817 mips_dbx_regno[i] = i + start;
13819 start = FP_DBX_FIRST - FP_REG_FIRST;
13820 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
13821 mips_dbx_regno[i] = i + start;
13823 /* Accumulator debug registers use big-endian ordering. */
13824 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
13825 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
13826 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
13827 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
13828 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
13830 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
13831 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
13834 /* Set up mips_hard_regno_mode_ok. */
13835 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
13836 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
13837 mips_hard_regno_mode_ok[(int)mode][regno]
13838 = mips_hard_regno_mode_ok_p (regno, mode);
13840 /* Function to allocate machine-dependent function status. */
13841 init_machine_status = &mips_init_machine_status;
13843 /* Default to working around R4000 errata only if the processor
13844 was selected explicitly. */
13845 if ((target_flags_explicit & MASK_FIX_R4000) == 0
13846 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
13847 target_flags |= MASK_FIX_R4000;
13849 /* Default to working around R4400 errata only if the processor
13850 was selected explicitly. */
13851 if ((target_flags_explicit & MASK_FIX_R4400) == 0
13852 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
13853 target_flags |= MASK_FIX_R4400;
13855 /* Save base state of options. */
13856 mips_base_target_flags = target_flags;
13857 mips_base_delayed_branch = flag_delayed_branch;
13858 mips_base_schedule_insns = flag_schedule_insns;
13859 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
13860 mips_base_move_loop_invariants = flag_move_loop_invariants;
13861 mips_base_align_loops = align_loops;
13862 mips_base_align_jumps = align_jumps;
13863 mips_base_align_functions = align_functions;
13865 /* Now select the ISA mode.
13867 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
13868 MIPS16 mode afterwards if need be. */
13869 mips_set_mips16_mode (false);
13871 /* We call dbr_schedule from within mips_reorg. */
13872 flag_delayed_branch = 0;
13875 /* Swap the register information for registers I and I + 1, which
13876 currently have the wrong endianness. Note that the registers'
13877 fixedness and call-clobberedness might have been set on the
13881 mips_swap_registers (unsigned int i)
13886 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
13887 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
13889 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
13890 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
13891 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
13892 SWAP_STRING (reg_names[i], reg_names[i + 1]);
13898 /* Implement CONDITIONAL_REGISTER_USAGE. */
13901 mips_conditional_register_usage (void)
13907 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
13908 fixed_regs[regno] = call_used_regs[regno] = 1;
13910 if (!TARGET_HARD_FLOAT)
13914 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
13915 fixed_regs[regno] = call_used_regs[regno] = 1;
13916 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
13917 fixed_regs[regno] = call_used_regs[regno] = 1;
13919 else if (! ISA_HAS_8CC)
13923 /* We only have a single condition-code register. We implement
13924 this by fixing all the condition-code registers and generating
13925 RTL that refers directly to ST_REG_FIRST. */
13926 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
13927 fixed_regs[regno] = call_used_regs[regno] = 1;
13929 /* In MIPS16 mode, we permit the $t temporary registers to be used
13930 for reload. We prohibit the unused $s registers, since they
13931 are call-saved, and saving them via a MIPS16 register would
13932 probably waste more time than just reloading the value. */
13935 fixed_regs[18] = call_used_regs[18] = 1;
13936 fixed_regs[19] = call_used_regs[19] = 1;
13937 fixed_regs[20] = call_used_regs[20] = 1;
13938 fixed_regs[21] = call_used_regs[21] = 1;
13939 fixed_regs[22] = call_used_regs[22] = 1;
13940 fixed_regs[23] = call_used_regs[23] = 1;
13941 fixed_regs[26] = call_used_regs[26] = 1;
13942 fixed_regs[27] = call_used_regs[27] = 1;
13943 fixed_regs[30] = call_used_regs[30] = 1;
13945 /* $f20-$f23 are call-clobbered for n64. */
13946 if (mips_abi == ABI_64)
13949 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
13950 call_really_used_regs[regno] = call_used_regs[regno] = 1;
13952 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
13954 if (mips_abi == ABI_N32)
13957 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
13958 call_really_used_regs[regno] = call_used_regs[regno] = 1;
13960 /* Make sure that double-register accumulator values are correctly
13961 ordered for the current endianness. */
13962 if (TARGET_LITTLE_ENDIAN)
13964 unsigned int regno;
13966 mips_swap_registers (MD_REG_FIRST);
13967 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
13968 mips_swap_registers (regno);
13972 /* Initialize vector TARGET to VALS. */
13975 mips_expand_vector_init (rtx target, rtx vals)
13977 enum machine_mode mode;
13978 enum machine_mode inner;
13979 unsigned int i, n_elts;
13982 mode = GET_MODE (target);
13983 inner = GET_MODE_INNER (mode);
13984 n_elts = GET_MODE_NUNITS (mode);
13986 gcc_assert (VECTOR_MODE_P (mode));
13988 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
13989 for (i = 0; i < n_elts; i++)
13990 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
13991 XVECEXP (vals, 0, i));
13993 emit_move_insn (target, mem);
13996 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
13997 other registers for instructions for which it is possible. This
13998 encourages the compiler to use CMP in cases where an XOR would
13999 require some register shuffling. */
14002 mips_order_regs_for_local_alloc (void)
14006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
14007 reg_alloc_order[i] = i;
14011 /* It really doesn't matter where we put register 0, since it is
14012 a fixed register anyhow. */
14013 reg_alloc_order[0] = 24;
14014 reg_alloc_order[24] = 0;
14018 /* Initialize the GCC target structure. */
14019 #undef TARGET_ASM_ALIGNED_HI_OP
14020 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
14021 #undef TARGET_ASM_ALIGNED_SI_OP
14022 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
14023 #undef TARGET_ASM_ALIGNED_DI_OP
14024 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
14026 #undef TARGET_ASM_FUNCTION_PROLOGUE
14027 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
14028 #undef TARGET_ASM_FUNCTION_EPILOGUE
14029 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
14030 #undef TARGET_ASM_SELECT_RTX_SECTION
14031 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
14032 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
14033 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
14035 #undef TARGET_SCHED_INIT
14036 #define TARGET_SCHED_INIT mips_sched_init
14037 #undef TARGET_SCHED_REORDER
14038 #define TARGET_SCHED_REORDER mips_sched_reorder
14039 #undef TARGET_SCHED_REORDER2
14040 #define TARGET_SCHED_REORDER2 mips_sched_reorder
14041 #undef TARGET_SCHED_VARIABLE_ISSUE
14042 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
14043 #undef TARGET_SCHED_ADJUST_COST
14044 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
14045 #undef TARGET_SCHED_ISSUE_RATE
14046 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
14047 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
14048 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
14049 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
14050 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
14051 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14052 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14053 mips_multipass_dfa_lookahead
14055 #undef TARGET_DEFAULT_TARGET_FLAGS
14056 #define TARGET_DEFAULT_TARGET_FLAGS \
14058 | TARGET_CPU_DEFAULT \
14059 | TARGET_ENDIAN_DEFAULT \
14060 | TARGET_FP_EXCEPTIONS_DEFAULT \
14061 | MASK_CHECK_ZERO_DIV \
14063 #undef TARGET_HANDLE_OPTION
14064 #define TARGET_HANDLE_OPTION mips_handle_option
14066 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14067 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
14069 #undef TARGET_INSERT_ATTRIBUTES
14070 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
14071 #undef TARGET_MERGE_DECL_ATTRIBUTES
14072 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
14073 #undef TARGET_SET_CURRENT_FUNCTION
14074 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
14076 #undef TARGET_VALID_POINTER_MODE
14077 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
14078 #undef TARGET_RTX_COSTS
14079 #define TARGET_RTX_COSTS mips_rtx_costs
14080 #undef TARGET_ADDRESS_COST
14081 #define TARGET_ADDRESS_COST mips_address_cost
14083 #undef TARGET_IN_SMALL_DATA_P
14084 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
14086 #undef TARGET_MACHINE_DEPENDENT_REORG
14087 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
14089 #undef TARGET_ASM_FILE_START
14090 #define TARGET_ASM_FILE_START mips_file_start
14091 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
14092 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
14094 #undef TARGET_INIT_LIBFUNCS
14095 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
14097 #undef TARGET_BUILD_BUILTIN_VA_LIST
14098 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
14099 #undef TARGET_EXPAND_BUILTIN_VA_START
14100 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
14101 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14102 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
14104 #undef TARGET_PROMOTE_FUNCTION_ARGS
14105 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
14106 #undef TARGET_PROMOTE_FUNCTION_RETURN
14107 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
14108 #undef TARGET_PROMOTE_PROTOTYPES
14109 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
14111 #undef TARGET_RETURN_IN_MEMORY
14112 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
14113 #undef TARGET_RETURN_IN_MSB
14114 #define TARGET_RETURN_IN_MSB mips_return_in_msb
14116 #undef TARGET_ASM_OUTPUT_MI_THUNK
14117 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
14118 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14119 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
14121 #undef TARGET_SETUP_INCOMING_VARARGS
14122 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
14123 #undef TARGET_STRICT_ARGUMENT_NAMING
14124 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
14125 #undef TARGET_MUST_PASS_IN_STACK
14126 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14127 #undef TARGET_PASS_BY_REFERENCE
14128 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
14129 #undef TARGET_CALLEE_COPIES
14130 #define TARGET_CALLEE_COPIES mips_callee_copies
14131 #undef TARGET_ARG_PARTIAL_BYTES
14132 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
14134 #undef TARGET_MODE_REP_EXTENDED
14135 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
14137 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14138 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
14140 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14141 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
14143 #undef TARGET_INIT_BUILTINS
14144 #define TARGET_INIT_BUILTINS mips_init_builtins
14145 #undef TARGET_EXPAND_BUILTIN
14146 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
14148 #undef TARGET_HAVE_TLS
14149 #define TARGET_HAVE_TLS HAVE_AS_TLS
14151 #undef TARGET_CANNOT_FORCE_CONST_MEM
14152 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
14154 #undef TARGET_ENCODE_SECTION_INFO
14155 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
14157 #undef TARGET_ATTRIBUTE_TABLE
14158 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
14159 /* All our function attributes are related to how out-of-line copies should
14160 be compiled or called. They don't in themselves prevent inlining. */
14161 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
14162 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
14164 #undef TARGET_EXTRA_LIVE_ON_ENTRY
14165 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
14167 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14168 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
14169 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
14170 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
14172 #undef TARGET_COMP_TYPE_ATTRIBUTES
14173 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
14175 #ifdef HAVE_AS_DTPRELWORD
14176 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
14177 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
14179 #undef TARGET_DWARF_REGISTER_SPAN
14180 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
14182 struct gcc_target targetm = TARGET_INITIALIZER;
14184 #include "gt-mips.h"