1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
58 #define STAB_CODE_TYPE enum __stab_debug_code
60 #define STAB_CODE_TYPE int
63 extern tree lookup_name PARAMS ((tree));
65 /* Enumeration for all of the relational tests, so that we can build
66 arrays indexed by the test type, and not worry about the order
85 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
86 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
88 static int m16_check_op PARAMS ((rtx, int, int, int));
89 static void block_move_loop PARAMS ((rtx, rtx,
93 static void block_move_call PARAMS ((rtx, rtx, rtx));
94 static rtx mips_add_large_offset_to_sp PARAMS ((HOST_WIDE_INT,
96 static void mips_annotate_frame_insn PARAMS ((rtx, rtx));
97 static rtx mips_frame_set PARAMS ((enum machine_mode,
99 static void mips_emit_frame_related_store PARAMS ((rtx, rtx,
101 static void save_restore_insns PARAMS ((int, rtx,
103 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
104 static void mips16_fp_args PARAMS ((FILE *, int, int));
105 static void build_mips16_function_stub PARAMS ((FILE *));
106 static void mips16_optimize_gp PARAMS ((rtx));
107 static rtx add_constant PARAMS ((struct constant **,
110 static void dump_constants PARAMS ((struct constant *,
112 static rtx mips_find_symbol PARAMS ((rtx));
113 static void abort_with_insn PARAMS ((rtx, const char *))
115 static int symbolic_expression_p PARAMS ((rtx));
116 static void mips_add_gc_roots PARAMS ((void));
117 static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
118 static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
119 static enum processor_type mips_parse_cpu PARAMS ((const char *));
120 static void copy_file_data PARAMS ((FILE *, FILE *));
122 static void iris6_asm_named_section_1 PARAMS ((const char *,
125 static void iris6_asm_named_section PARAMS ((const char *,
127 static int iris_section_align_entry_eq PARAMS ((const PTR, const PTR));
128 static hashval_t iris_section_align_entry_hash PARAMS ((const PTR));
129 static int iris6_section_align_1 PARAMS ((void **, void *));
131 static int mips_adjust_cost PARAMS ((rtx, rtx, rtx, int));
133 /* Global variables for machine-dependent things. */
135 /* Threshold for data being put into the small data/bss area, instead
136 of the normal data area (references to the small data/bss area take
137 1 instruction, and use the global pointer, references to the normal
138 data area takes 2 instructions). */
139 int mips_section_threshold = -1;
141 /* Count the number of .file directives, so that .loc is up to date. */
142 int num_source_filenames = 0;
144 /* Count the number of sdb related labels are generated (to find block
145 start and end boundaries). */
146 int sdb_label_count = 0;
148 /* Next label # for each statement for Silicon Graphics IRIS systems. */
151 /* Non-zero if inside of a function, because the stupid MIPS asm can't
152 handle .files inside of functions. */
153 int inside_function = 0;
155 /* Files to separate the text and the data output, so that all of the data
156 can be emitted before the text, which will mean that the assembler will
157 generate smaller code, based on the global pointer. */
158 FILE *asm_out_data_file;
159 FILE *asm_out_text_file;
161 /* Linked list of all externals that are to be emitted when optimizing
162 for the global pointer if they haven't been declared by the end of
163 the program with an appropriate .comm or initialization. */
167 struct extern_list *next; /* next external */
168 const char *name; /* name of the external */
169 int size; /* size in bytes */
172 /* Name of the file containing the current function. */
173 const char *current_function_file = "";
175 /* Warning given that Mips ECOFF can't support changing files
176 within a function. */
177 int file_in_function_warning = FALSE;
179 /* Whether to suppress issuing .loc's because the user attempted
180 to change the filename within a function. */
181 int ignore_line_number = FALSE;
183 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
189 /* The next branch instruction is a branch likely, not branch normal. */
190 int mips_branch_likely;
192 /* Count of delay slots and how many are filled. */
193 int dslots_load_total;
194 int dslots_load_filled;
195 int dslots_jump_total;
196 int dslots_jump_filled;
198 /* # of nops needed by previous insn */
199 int dslots_number_nops;
201 /* Number of 1/2/3 word references to data items (ie, not jal's). */
204 /* registers to check for load delay */
205 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
207 /* Cached operands, and operator to compare for use in set/branch/trap
208 on condition codes. */
211 /* what type of branch to use */
212 enum cmp_type branch_type;
214 /* Number of previously seen half-pic pointers and references. */
215 static int prev_half_pic_ptrs = 0;
216 static int prev_half_pic_refs = 0;
218 /* The target cpu for code generation. */
219 enum processor_type mips_arch;
221 /* The target cpu for optimization and scheduling. */
222 enum processor_type mips_tune;
224 /* which instruction set architecture to use. */
227 #ifdef MIPS_ABI_DEFAULT
228 /* Which ABI to use. This is defined to a constant in mips.h if the target
229 doesn't support multiple ABIs. */
233 /* Strings to hold which cpu and instruction set architecture to use. */
234 const char *mips_cpu_string; /* for -mcpu=<xxx> */
235 const char *mips_arch_string; /* for -march=<xxx> */
236 const char *mips_tune_string; /* for -mtune=<xxx> */
237 const char *mips_isa_string; /* for -mips{1,2,3,4} */
238 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
240 /* Whether we are generating mips16 code. This is a synonym for
241 TARGET_MIPS16, and exists for use as an attribute. */
244 /* This variable is set by -mno-mips16. We only care whether
245 -mno-mips16 appears or not, and using a string in this fashion is
246 just a way to avoid using up another bit in target_flags. */
247 const char *mips_no_mips16_string;
249 /* This is only used to determine if an type size setting option was
250 explicitly specified (-mlong64, -mint64, -mlong32). The specs
251 set this option if such an option is used. */
252 const char *mips_explicit_type_size_string;
254 /* Whether we are generating mips16 hard float code. In mips16 mode
255 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
256 -msoft-float was not specified by the user, which means that we
257 should arrange to call mips32 hard floating point code. */
258 int mips16_hard_float;
260 /* This variable is set by -mentry. We only care whether -mentry
261 appears or not, and using a string in this fashion is just a way to
262 avoid using up another bit in target_flags. */
263 const char *mips_entry_string;
265 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
268 /* If TRUE, we split addresses into their high and low parts in the RTL. */
269 int mips_split_addresses;
271 /* Generating calls to position independent functions? */
272 enum mips_abicalls_type mips_abicalls;
274 /* High and low marks for floating point values which we will accept
275 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
276 initialized in override_options. */
277 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
279 /* Mode used for saving/restoring general purpose registers. */
280 static enum machine_mode gpr_mode;
282 /* Array giving truth value on whether or not a given hard register
283 can support a given mode. */
284 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
286 /* Current frame information calculated by compute_frame_size. */
287 struct mips_frame_info current_frame_info;
289 /* Zero structure to initialize current_frame_info. */
290 struct mips_frame_info zero_frame_info;
292 /* Pseudo-reg holding the address of the current function when
293 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
294 by mips_finalize_pic if it was created. */
295 rtx embedded_pic_fnaddr_rtx;
297 /* The length of all strings seen when compiling for the mips16. This
298 is used to tell how many strings are in the constant pool, so that
299 we can see if we may have an overflow. This is reset each time the
300 constant pool is output. */
301 int mips_string_length;
303 /* Pseudo-reg holding the value of $28 in a mips16 function which
304 refers to GP relative global variables. */
305 rtx mips16_gp_pseudo_rtx;
307 /* In mips16 mode, we build a list of all the string constants we see
308 in a particular function. */
310 struct string_constant
312 struct string_constant *next;
316 static struct string_constant *string_constants;
318 /* List of all MIPS punctuation characters used by print_operand. */
319 char mips_print_operand_punct[256];
321 /* Map GCC register number to debugger register number. */
322 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
324 /* Buffer to use to enclose a load/store operation with %{ %} to
325 turn on .set volatile. */
326 static char volatile_buffer[60];
328 /* Hardware names for the registers. If -mrnames is used, this
329 will be overwritten with mips_sw_reg_names. */
331 char mips_reg_names[][8] =
333 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
334 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
335 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
336 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
337 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
338 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
339 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
340 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
341 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
342 "$fcc5","$fcc6","$fcc7","$rap"
345 /* Mips software names for the registers, used to overwrite the
346 mips_reg_names array. */
348 char mips_sw_reg_names[][8] =
350 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
351 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
352 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
353 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
354 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
355 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
356 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
357 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
358 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
359 "$fcc5","$fcc6","$fcc7","$rap"
362 /* Map hard register number to register class */
363 enum reg_class mips_regno_to_class[] =
365 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
366 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
367 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
368 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
369 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
370 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
371 T_REG, GR_REGS, GR_REGS, GR_REGS,
372 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
373 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
374 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
375 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
376 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
377 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
378 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
379 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
380 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
381 HI_REG, LO_REG, HILO_REG, ST_REGS,
382 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
383 ST_REGS, ST_REGS, ST_REGS, GR_REGS
386 /* Map register constraint character to register class. */
387 enum reg_class mips_char_to_class[256] =
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
431 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
432 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
433 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
434 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
435 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
436 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
437 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
438 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
439 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
440 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
441 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
442 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
443 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
444 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
445 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
446 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
447 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
448 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
449 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
450 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
451 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
452 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
455 /* Initialize the GCC target structure. */
456 #undef TARGET_ASM_FUNCTION_PROLOGUE
457 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
458 #undef TARGET_ASM_FUNCTION_EPILOGUE
459 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
461 #undef TARGET_SCHED_ADJUST_COST
462 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
464 struct gcc_target targetm = TARGET_INITIALIZER;
466 /* Return truth value of whether OP can be used as an operands
467 where a register or 16 bit unsigned integer is needed. */
470 uns_arith_operand (op, mode)
472 enum machine_mode mode;
474 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
477 return register_operand (op, mode);
480 /* Return truth value of whether OP can be used as an operands
481 where a 16 bit integer is needed */
484 arith_operand (op, mode)
486 enum machine_mode mode;
488 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
491 /* On the mips16, a GP relative value is a signed 16 bit offset. */
492 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
495 return register_operand (op, mode);
498 /* Return truth value of whether OP can be used as an operand in a two
499 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
502 arith32_operand (op, mode)
504 enum machine_mode mode;
506 if (GET_CODE (op) == CONST_INT)
509 return register_operand (op, mode);
512 /* Return truth value of whether OP is a integer which fits in 16 bits */
517 enum machine_mode mode ATTRIBUTE_UNUSED;
519 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
522 /* Return truth value of whether OP is a 32 bit integer which is too big to
523 be loaded with one instruction. */
528 enum machine_mode mode ATTRIBUTE_UNUSED;
532 if (GET_CODE (op) != CONST_INT)
537 /* ior reg,$r0,value */
538 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
541 /* subu reg,$r0,value */
542 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
545 /* lui reg,value>>16 */
546 if ((value & 0x0000ffff) == 0)
552 /* Return truth value of whether OP is a register or the constant 0.
553 In mips16 mode, we only accept a register, since the mips16 does
557 reg_or_0_operand (op, mode)
559 enum machine_mode mode;
561 switch (GET_CODE (op))
566 return INTVAL (op) == 0;
571 return op == CONST0_RTX (mode);
575 return register_operand (op, mode);
584 /* Return truth value of whether OP is a register or the constant 0,
585 even in mips16 mode. */
588 true_reg_or_0_operand (op, mode)
590 enum machine_mode mode;
592 switch (GET_CODE (op))
595 return INTVAL (op) == 0;
598 return op == CONST0_RTX (mode);
602 return register_operand (op, mode);
611 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
614 mips_const_double_ok (op, mode)
616 enum machine_mode mode;
620 if (GET_CODE (op) != CONST_DOUBLE)
623 if (mode == VOIDmode)
626 if (mode != SFmode && mode != DFmode)
629 if (op == CONST0_RTX (mode))
632 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
633 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
636 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
638 if (REAL_VALUE_ISNAN (d))
641 if (REAL_VALUE_NEGATIVE (d))
642 d = REAL_VALUE_NEGATE (d);
646 if (REAL_VALUES_LESS (d, dfhigh)
647 && REAL_VALUES_LESS (dflow, d))
652 if (REAL_VALUES_LESS (d, sfhigh)
653 && REAL_VALUES_LESS (sflow, d))
660 /* Accept the floating point constant 1 in the appropriate mode. */
663 const_float_1_operand (op, mode)
665 enum machine_mode mode;
668 static REAL_VALUE_TYPE onedf;
669 static REAL_VALUE_TYPE onesf;
670 static int one_initialized;
672 if (GET_CODE (op) != CONST_DOUBLE
673 || mode != GET_MODE (op)
674 || (mode != DFmode && mode != SFmode))
677 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
679 /* We only initialize these values if we need them, since we will
680 never get called unless mips_isa >= 4. */
681 if (! one_initialized)
683 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
684 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
689 return REAL_VALUES_EQUAL (d, onedf);
691 return REAL_VALUES_EQUAL (d, onesf);
694 /* Return true if a memory load or store of REG plus OFFSET in MODE
695 can be represented in a single word on the mips16. */
698 mips16_simple_memory_operand (reg, offset, mode)
701 enum machine_mode mode;
708 /* We can't tell, because we don't know how the value will
709 eventually be accessed. Returning 0 here does no great
710 harm; it just prevents some possible instruction scheduling. */
714 size = GET_MODE_SIZE (mode);
716 if (INTVAL (offset) % size != 0)
718 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
722 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
727 /* Return truth value if a memory operand fits in a single instruction
728 (ie, register + small offset). */
731 simple_memory_operand (op, mode)
733 enum machine_mode mode;
735 rtx addr, plus0, plus1;
737 /* Eliminate non-memory operations */
738 if (GET_CODE (op) != MEM)
741 /* dword operations really put out 2 instructions, so eliminate them. */
742 /* ??? This isn't strictly correct. It is OK to accept multiword modes
743 here, since the length attributes are being set correctly, but only
744 if the address is offsettable. LO_SUM is not offsettable. */
745 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
748 /* Decode the address now. */
750 switch (GET_CODE (addr))
759 return SMALL_INT (addr);
762 plus0 = XEXP (addr, 0);
763 plus1 = XEXP (addr, 1);
764 if (GET_CODE (plus0) == REG
765 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
767 || mips16_simple_memory_operand (plus0, plus1, mode)))
770 else if (GET_CODE (plus1) == REG
771 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
773 || mips16_simple_memory_operand (plus1, plus0, mode)))
780 /* We used to allow small symbol refs here (ie, stuff in .sdata
781 or .sbss), but this causes some bugs in G++. Also, it won't
782 interfere if the MIPS linker rewrites the store instruction
783 because the function is PIC. */
785 case LABEL_REF: /* never gp relative */
789 /* If -G 0, we can never have a GP relative memory operation.
790 Also, save some time if not optimizing. */
795 rtx offset = const0_rtx;
796 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
797 if (GET_CODE (op) != SYMBOL_REF)
800 /* let's be paranoid.... */
801 if (! SMALL_INT (offset))
808 return SYMBOL_REF_FLAG (addr);
811 /* This SYMBOL_REF case is for the mips16. If the above case is
812 reenabled, this one should be merged in. */
814 /* References to the constant pool on the mips16 use a small
815 offset if the function is small. The only time we care about
816 getting this right is during delayed branch scheduling, so
817 don't need to check until then. The machine_dependent_reorg
818 function will set the total length of the instructions used
819 in the function in current_frame_info. If that is small
820 enough, we know for sure that this is a small offset. It
821 would be better if we could take into account the location of
822 the instruction within the function, but we can't, because we
823 don't know where we are. */
825 && CONSTANT_POOL_ADDRESS_P (addr)
826 && current_frame_info.insns_len > 0)
830 size = current_frame_info.insns_len + get_pool_size ();
831 if (GET_MODE_SIZE (mode) == 4)
832 return size < 4 * 0x100;
833 else if (GET_MODE_SIZE (mode) == 8)
834 return size < 8 * 0x20;
848 /* Return nonzero for a memory address that can be used to load or store
852 double_memory_operand (op, mode)
854 enum machine_mode mode;
856 if (GET_CODE (op) != MEM
857 || ! memory_operand (op, mode))
859 /* During reload, we accept a pseudo register if it has an
860 appropriate memory address. If we don't do this, we will
861 wind up reloading into a register, and then reloading that
862 register from memory, when we could just reload directly from
864 if (reload_in_progress
865 && GET_CODE (op) == REG
866 && REGNO (op) >= FIRST_PSEUDO_REGISTER
867 && reg_renumber[REGNO (op)] < 0
868 && reg_equiv_mem[REGNO (op)] != 0
869 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
872 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
873 the same test performed for 'm' in find_reloads. */
875 if (reload_in_progress
877 && (GET_CODE (op) == MEM
878 || (GET_CODE (op) == REG
879 && REGNO (op) >= FIRST_PSEUDO_REGISTER
880 && reg_renumber[REGNO (op)] < 0)))
883 if (reload_in_progress
885 && GET_CODE (op) == MEM)
891 /* During reload on the mips16, we accept a large offset
892 from the frame pointer or the stack pointer. This large
893 address will get reloaded anyhow. */
894 if (GET_CODE (addr) == PLUS
895 && GET_CODE (XEXP (addr, 0)) == REG
896 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
897 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
898 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
899 && ! SMALL_INT (XEXP (addr, 1)))
900 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
901 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
904 /* Similarly, we accept a case where the memory address is
905 itself on the stack, and will be reloaded. */
906 if (GET_CODE (addr) == MEM)
910 maddr = XEXP (addr, 0);
911 if (GET_CODE (maddr) == PLUS
912 && GET_CODE (XEXP (maddr, 0)) == REG
913 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
914 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
915 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
916 && ! SMALL_INT (XEXP (maddr, 1)))
917 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
918 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
922 /* We also accept the same case when we have a 16 bit signed
923 offset mixed in as well. The large address will get
924 reloaded, and the 16 bit offset will be OK. */
925 if (GET_CODE (addr) == PLUS
926 && GET_CODE (XEXP (addr, 0)) == MEM
927 && GET_CODE (XEXP (addr, 1)) == CONST_INT
928 && SMALL_INT (XEXP (addr, 1)))
930 addr = XEXP (XEXP (addr, 0), 0);
931 if (GET_CODE (addr) == PLUS
932 && GET_CODE (XEXP (addr, 0)) == REG
933 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
934 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
935 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
936 && ! SMALL_INT (XEXP (addr, 1)))
937 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
938 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
948 /* In this case we can use an instruction like sd. */
952 /* Make sure that 4 added to the address is a valid memory address.
953 This essentially just checks for overflow in an added constant. */
955 if (CONSTANT_ADDRESS_P (XEXP (op, 0)))
958 op = adjust_address_nv (op, GET_MODE_CLASS (mode) == MODE_INT
959 ? SImode : SFmode, 4);
960 return memory_address_p (GET_MODE (op), XEXP (op, 0));
963 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
966 equality_op (op, mode)
968 enum machine_mode mode;
970 if (mode != GET_MODE (op))
973 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
976 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
981 enum machine_mode mode;
983 if (mode != GET_MODE (op))
986 return GET_RTX_CLASS (GET_CODE (op)) == '<';
989 /* Return nonzero if the code is a relational operation suitable for a
990 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
991 We need this in the insn that expands `trap_if' in order to prevent
992 combine from erroneously altering the condition. */
995 trap_cmp_op (op, mode)
997 enum machine_mode mode;
999 if (mode != GET_MODE (op))
1002 switch (GET_CODE (op))
1017 /* Return nonzero if the operand is either the PC or a label_ref. */
1020 pc_or_label_operand (op, mode)
1022 enum machine_mode mode ATTRIBUTE_UNUSED;
1027 if (GET_CODE (op) == LABEL_REF)
1033 /* Test for a valid operand for a call instruction.
1034 Don't allow the arg pointer register or virtual regs
1035 since they may change into reg + const, which the patterns
1036 can't handle yet. */
1039 call_insn_operand (op, mode)
1041 enum machine_mode mode ATTRIBUTE_UNUSED;
1043 return (CONSTANT_ADDRESS_P (op)
1044 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1045 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1046 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1049 /* Return nonzero if OPERAND is valid as a source operand for a move
1053 move_operand (op, mode)
1055 enum machine_mode mode;
1057 /* Accept any general operand after reload has started; doing so
1058 avoids losing if reload does an in-place replacement of a register
1059 with a SYMBOL_REF or CONST. */
1060 return (general_operand (op, mode)
1061 && (! (mips_split_addresses && mips_check_split (op, mode))
1062 || reload_in_progress || reload_completed)
1064 && GET_CODE (op) == SYMBOL_REF
1065 && ! mips16_constant (op, mode, 1, 0)));
1068 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1069 This accepts not only general_operand, but also sign extended
1070 constants and registers. We need to accept sign extended constants
1071 in case a sign extended register which is used in an expression,
1072 and is equivalent to a constant, is spilled. */
1075 movdi_operand (op, mode)
1077 enum machine_mode mode;
1081 && GET_CODE (op) == SIGN_EXTEND
1082 && GET_MODE (op) == DImode
1083 && (GET_MODE (XEXP (op, 0)) == SImode
1084 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1085 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1086 && (register_operand (XEXP (op, 0), SImode)
1087 || immediate_operand (XEXP (op, 0), SImode)))
1090 return (general_operand (op, mode)
1092 && GET_CODE (op) == SYMBOL_REF
1093 && ! mips16_constant (op, mode, 1, 0)));
1096 /* Like register_operand, but when in 64 bit mode also accept a sign
1097 extend of a 32 bit register, since the value is known to be already
1101 se_register_operand (op, mode)
1103 enum machine_mode mode;
1107 && GET_CODE (op) == SIGN_EXTEND
1108 && GET_MODE (op) == DImode
1109 && GET_MODE (XEXP (op, 0)) == SImode
1110 && register_operand (XEXP (op, 0), SImode))
1113 return register_operand (op, mode);
1116 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1117 extend of a 32 bit register, since the value is known to be already
1121 se_reg_or_0_operand (op, mode)
1123 enum machine_mode mode;
1127 && GET_CODE (op) == SIGN_EXTEND
1128 && GET_MODE (op) == DImode
1129 && GET_MODE (XEXP (op, 0)) == SImode
1130 && register_operand (XEXP (op, 0), SImode))
1133 return reg_or_0_operand (op, mode);
1136 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1137 extend of a 32 bit register, since the value is known to be already
1141 se_uns_arith_operand (op, mode)
1143 enum machine_mode mode;
1147 && GET_CODE (op) == SIGN_EXTEND
1148 && GET_MODE (op) == DImode
1149 && GET_MODE (XEXP (op, 0)) == SImode
1150 && register_operand (XEXP (op, 0), SImode))
1153 return uns_arith_operand (op, mode);
1156 /* Like arith_operand, but when in 64 bit mode also accept a sign
1157 extend of a 32 bit register, since the value is known to be already
1161 se_arith_operand (op, mode)
1163 enum machine_mode mode;
1167 && GET_CODE (op) == SIGN_EXTEND
1168 && GET_MODE (op) == DImode
1169 && GET_MODE (XEXP (op, 0)) == SImode
1170 && register_operand (XEXP (op, 0), SImode))
1173 return arith_operand (op, mode);
1176 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1177 extend of a 32 bit register, since the value is known to be already
1181 se_nonmemory_operand (op, mode)
1183 enum machine_mode mode;
1187 && GET_CODE (op) == SIGN_EXTEND
1188 && GET_MODE (op) == DImode
1189 && GET_MODE (XEXP (op, 0)) == SImode
1190 && register_operand (XEXP (op, 0), SImode))
1193 return nonmemory_operand (op, mode);
1196 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1197 sign extend of a 32 bit register, since the value is known to be
1198 already sign extended. */
1201 se_nonimmediate_operand (op, mode)
1203 enum machine_mode mode;
1207 && GET_CODE (op) == SIGN_EXTEND
1208 && GET_MODE (op) == DImode
1209 && GET_MODE (XEXP (op, 0)) == SImode
1210 && register_operand (XEXP (op, 0), SImode))
1213 return nonimmediate_operand (op, mode);
1216 /* Accept any operand that can appear in a mips16 constant table
1217 instruction. We can't use any of the standard operand functions
1218 because for these instructions we accept values that are not
1219 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1222 consttable_operand (op, mode)
1224 enum machine_mode mode ATTRIBUTE_UNUSED;
1226 return CONSTANT_P (op);
1229 /* Return nonzero if we split the address into high and low parts. */
1231 /* ??? We should also handle reg+array somewhere. We get four
1232 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1233 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1234 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1235 out of the address, then we have 4 instructions to combine. Perhaps
1236 add a 3->2 define_split for combine. */
1238 /* ??? We could also split a CONST_INT here if it is a large_int().
1239 However, it doesn't seem to be very useful to have %hi(constant).
1240 We would be better off by doing the masking ourselves and then putting
1241 the explicit high part of the constant in the RTL. This will give better
1242 optimization. Also, %hi(constant) needs assembler changes to work.
1243 There is already a define_split that does this. */
1246 mips_check_split (address, mode)
1248 enum machine_mode mode;
1250 /* ??? This is the same check used in simple_memory_operand.
1251 We use it here because LO_SUM is not offsettable. */
1252 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1255 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1256 || (GET_CODE (address) == CONST
1257 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1258 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1259 || GET_CODE (address) == LABEL_REF)
1265 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1268 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1270 enum machine_mode mode;
1274 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1275 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1278 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1279 returns a nonzero value if XINSN is a legitimate address for a
1280 memory operand of the indicated MODE. STRICT is non-zero if this
1281 function is called during reload. */
1284 mips_legitimate_address_p (mode, xinsn, strict)
1285 enum machine_mode mode;
1289 if (TARGET_DEBUG_B_MODE)
1291 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1292 strict ? "" : "not ");
1293 GO_DEBUG_RTX (xinsn);
1296 /* Check for constant before stripping off SUBREG, so that we don't
1297 accept (subreg (const_int)) which will fail to reload. */
1298 if (CONSTANT_ADDRESS_P (xinsn)
1299 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1300 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1303 while (GET_CODE (xinsn) == SUBREG)
1304 xinsn = SUBREG_REG (xinsn);
1306 /* The mips16 can only use the stack pointer as a base register when
1307 loading SImode or DImode values. */
1308 if (GET_CODE (xinsn) == REG
1309 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1312 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1314 register rtx xlow0 = XEXP (xinsn, 0);
1315 register rtx xlow1 = XEXP (xinsn, 1);
1317 while (GET_CODE (xlow0) == SUBREG)
1318 xlow0 = SUBREG_REG (xlow0);
1319 if (GET_CODE (xlow0) == REG
1320 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1321 && mips_check_split (xlow1, mode))
1325 if (GET_CODE (xinsn) == PLUS)
1327 register rtx xplus0 = XEXP (xinsn, 0);
1328 register rtx xplus1 = XEXP (xinsn, 1);
1329 register enum rtx_code code0;
1330 register enum rtx_code code1;
1332 while (GET_CODE (xplus0) == SUBREG)
1333 xplus0 = SUBREG_REG (xplus0);
1334 code0 = GET_CODE (xplus0);
1336 while (GET_CODE (xplus1) == SUBREG)
1337 xplus1 = SUBREG_REG (xplus1);
1338 code1 = GET_CODE (xplus1);
1340 /* The mips16 can only use the stack pointer as a base register
1341 when loading SImode or DImode values. */
1343 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1345 if (code1 == CONST_INT && SMALL_INT (xplus1))
1348 /* On the mips16, we represent GP relative offsets in RTL.
1349 These are 16 bit signed values, and can serve as register
1352 && mips16_gp_offset_p (xplus1))
1355 /* For some code sequences, you actually get better code by
1356 pretending that the MIPS supports an address mode of a
1357 constant address + a register, even though the real
1358 machine doesn't support it. This is because the
1359 assembler can use $r1 to load just the high 16 bits, add
1360 in the register, and fold the low 16 bits into the memory
1361 reference, whereas the compiler generates a 4 instruction
1362 sequence. On the other hand, CSE is not as effective.
1363 It would be a win to generate the lui directly, but the
1364 MIPS assembler does not have syntax to generate the
1365 appropriate relocation. */
1367 /* Also accept CONST_INT addresses here, so no else. */
1368 /* Reject combining an embedded PIC text segment reference
1369 with a register. That requires an additional
1371 /* ??? Reject combining an address with a register for the MIPS
1372 64 bit ABI, because the SGI assembler can not handle this. */
1373 if (!TARGET_DEBUG_A_MODE
1374 && (mips_abi == ABI_32
1375 || mips_abi == ABI_O64
1376 || mips_abi == ABI_EABI)
1377 && CONSTANT_ADDRESS_P (xplus1)
1378 && ! mips_split_addresses
1379 && (!TARGET_EMBEDDED_PIC
1381 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1382 /* When assembling for machines with 64 bit registers,
1383 the assembler will sign-extend the constant "foo"
1384 in "la x, foo(x)" yielding the wrong result for:
1385 (set (blah:DI) (plus x y)). */
1387 || (code1 == CONST_INT
1388 && trunc_int_for_mode (INTVAL (xplus1),
1389 SImode) == INTVAL (xplus1)))
1395 if (TARGET_DEBUG_B_MODE)
1396 GO_PRINTF ("Not a legitimate address\n");
1398 /* The address was not legitimate. */
1403 /* We need a lot of little routines to check constant values on the
1404 mips16. These are used to figure out how long the instruction will
1405 be. It would be much better to do this using constraints, but
1406 there aren't nearly enough letters available. */
1409 m16_check_op (op, low, high, mask)
1415 return (GET_CODE (op) == CONST_INT
1416 && INTVAL (op) >= low
1417 && INTVAL (op) <= high
1418 && (INTVAL (op) & mask) == 0);
1422 m16_uimm3_b (op, mode)
1424 enum machine_mode mode ATTRIBUTE_UNUSED;
1426 return m16_check_op (op, 0x1, 0x8, 0);
1430 m16_simm4_1 (op, mode)
1432 enum machine_mode mode ATTRIBUTE_UNUSED;
1434 return m16_check_op (op, - 0x8, 0x7, 0);
1438 m16_nsimm4_1 (op, mode)
1440 enum machine_mode mode ATTRIBUTE_UNUSED;
1442 return m16_check_op (op, - 0x7, 0x8, 0);
1446 m16_simm5_1 (op, mode)
1448 enum machine_mode mode ATTRIBUTE_UNUSED;
1450 return m16_check_op (op, - 0x10, 0xf, 0);
1454 m16_nsimm5_1 (op, mode)
1456 enum machine_mode mode ATTRIBUTE_UNUSED;
1458 return m16_check_op (op, - 0xf, 0x10, 0);
1462 m16_uimm5_4 (op, mode)
1464 enum machine_mode mode ATTRIBUTE_UNUSED;
1466 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1470 m16_nuimm5_4 (op, mode)
1472 enum machine_mode mode ATTRIBUTE_UNUSED;
1474 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1478 m16_simm8_1 (op, mode)
1480 enum machine_mode mode ATTRIBUTE_UNUSED;
1482 return m16_check_op (op, - 0x80, 0x7f, 0);
1486 m16_nsimm8_1 (op, mode)
1488 enum machine_mode mode ATTRIBUTE_UNUSED;
1490 return m16_check_op (op, - 0x7f, 0x80, 0);
1494 m16_uimm8_1 (op, mode)
1496 enum machine_mode mode ATTRIBUTE_UNUSED;
1498 return m16_check_op (op, 0x0, 0xff, 0);
1502 m16_nuimm8_1 (op, mode)
1504 enum machine_mode mode ATTRIBUTE_UNUSED;
1506 return m16_check_op (op, - 0xff, 0x0, 0);
1510 m16_uimm8_m1_1 (op, mode)
1512 enum machine_mode mode ATTRIBUTE_UNUSED;
1514 return m16_check_op (op, - 0x1, 0xfe, 0);
1518 m16_uimm8_4 (op, mode)
1520 enum machine_mode mode ATTRIBUTE_UNUSED;
1522 return m16_check_op (op, 0x0, 0xff << 2, 3);
1526 m16_nuimm8_4 (op, mode)
1528 enum machine_mode mode ATTRIBUTE_UNUSED;
1530 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1534 m16_simm8_8 (op, mode)
1536 enum machine_mode mode ATTRIBUTE_UNUSED;
1538 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1542 m16_nsimm8_8 (op, mode)
1544 enum machine_mode mode ATTRIBUTE_UNUSED;
1546 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1549 /* References to the string table on the mips16 only use a small
1550 offset if the function is small. See the comment in the SYMBOL_REF
1551 case in simple_memory_operand. We can't check for LABEL_REF here,
1552 because the offset is always large if the label is before the
1553 referencing instruction. */
1556 m16_usym8_4 (op, mode)
1558 enum machine_mode mode ATTRIBUTE_UNUSED;
1560 if (GET_CODE (op) == SYMBOL_REF
1561 && SYMBOL_REF_FLAG (op)
1562 && current_frame_info.insns_len > 0
1563 && XSTR (op, 0)[0] == '*'
1564 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1565 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1566 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1569 struct string_constant *l;
1571 /* Make sure this symbol is on thelist of string constants to be
1572 output for this function. It is possible that it has already
1573 been output, in which case this requires a large offset. */
1574 for (l = string_constants; l != NULL; l = l->next)
1575 if (strcmp (l->label, XSTR (op, 0)) == 0)
1583 m16_usym5_4 (op, mode)
1585 enum machine_mode mode ATTRIBUTE_UNUSED;
1587 if (GET_CODE (op) == SYMBOL_REF
1588 && SYMBOL_REF_FLAG (op)
1589 && current_frame_info.insns_len > 0
1590 && XSTR (op, 0)[0] == '*'
1591 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1592 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1593 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1596 struct string_constant *l;
1598 /* Make sure this symbol is on thelist of string constants to be
1599 output for this function. It is possible that it has already
1600 been output, in which case this requires a large offset. */
1601 for (l = string_constants; l != NULL; l = l->next)
1602 if (strcmp (l->label, XSTR (op, 0)) == 0)
1609 /* Returns an operand string for the given instruction's delay slot,
1610 after updating filled delay slot statistics.
1612 We assume that operands[0] is the target register that is set.
1614 In order to check the next insn, most of this functionality is moved
1615 to FINAL_PRESCAN_INSN, and we just set the global variables that
1618 /* ??? This function no longer does anything useful, because final_prescan_insn
1619 now will never emit a nop. */
1622 mips_fill_delay_slot (ret, type, operands, cur_insn)
1623 const char *ret; /* normal string to return */
1624 enum delay_type type; /* type of delay */
1625 rtx operands[]; /* operands to use */
1626 rtx cur_insn; /* current insn */
1628 register rtx set_reg;
1629 register enum machine_mode mode;
1630 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1631 register int num_nops;
1633 if (type == DELAY_LOAD || type == DELAY_FCMP)
1636 else if (type == DELAY_HILO)
1642 /* Make sure that we don't put nop's after labels. */
1643 next_insn = NEXT_INSN (cur_insn);
1644 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1645 next_insn = NEXT_INSN (next_insn);
1647 dslots_load_total += num_nops;
1648 if (TARGET_DEBUG_F_MODE
1650 || type == DELAY_NONE
1654 || GET_CODE (next_insn) == CODE_LABEL
1655 || (set_reg = operands[0]) == 0)
1657 dslots_number_nops = 0;
1665 set_reg = operands[0];
1669 while (GET_CODE (set_reg) == SUBREG)
1670 set_reg = SUBREG_REG (set_reg);
1672 mode = GET_MODE (set_reg);
1673 dslots_number_nops = num_nops;
1674 mips_load_reg = set_reg;
1675 if (GET_MODE_SIZE (mode)
1676 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1677 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1681 if (type == DELAY_HILO)
1683 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1684 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1696 /* Determine whether a memory reference takes one (based off of the GP
1697 pointer), two (normal), or three (label + reg) instructions, and bump the
1698 appropriate counter for -mstats. */
1701 mips_count_memory_refs (op, num)
1707 rtx addr, plus0, plus1;
1708 enum rtx_code code0, code1;
1711 if (TARGET_DEBUG_B_MODE)
1713 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1717 /* Skip MEM if passed, otherwise handle movsi of address. */
1718 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1720 /* Loop, going through the address RTL. */
1724 switch (GET_CODE (addr))
1732 plus0 = XEXP (addr, 0);
1733 plus1 = XEXP (addr, 1);
1734 code0 = GET_CODE (plus0);
1735 code1 = GET_CODE (plus1);
1745 if (code0 == CONST_INT)
1760 if (code1 == CONST_INT)
1767 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1774 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1784 n_words = 2; /* always 2 words */
1788 addr = XEXP (addr, 0);
1793 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1805 n_words += additional;
1809 num_refs[n_words-1] += num;
1813 /* Return RTL for the offset from the current function to the argument.
1815 ??? Which argument is this? */
1818 embedded_pic_offset (x)
1821 if (embedded_pic_fnaddr_rtx == NULL)
1825 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1827 /* Output code at function start to initialize the pseudo-reg. */
1828 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1829 inline functions, because it is called after RTL for the function
1830 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1831 does not get copied, and ends up not matching the rest of the RTL.
1832 This solution works, but means that we get unnecessary code to
1833 initialize this value every time a function is inlined into another
1836 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1837 XEXP (DECL_RTL (current_function_decl), 0)));
1838 seq = gen_sequence ();
1840 push_topmost_sequence ();
1841 emit_insn_after (seq, get_insns ());
1842 pop_topmost_sequence ();
1846 gen_rtx_CONST (Pmode,
1847 gen_rtx_MINUS (Pmode, x,
1848 XEXP (DECL_RTL (current_function_decl), 0)));
1851 /* Return the appropriate instructions to move one operand to another. */
1854 mips_move_1word (operands, insn, unsignedp)
1859 const char *ret = 0;
1860 rtx op0 = operands[0];
1861 rtx op1 = operands[1];
1862 enum rtx_code code0 = GET_CODE (op0);
1863 enum rtx_code code1 = GET_CODE (op1);
1864 enum machine_mode mode = GET_MODE (op0);
1865 int subreg_offset0 = 0;
1866 int subreg_offset1 = 0;
1867 enum delay_type delay = DELAY_NONE;
1869 while (code0 == SUBREG)
1871 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
1872 GET_MODE (SUBREG_REG (op0)),
1875 op0 = SUBREG_REG (op0);
1876 code0 = GET_CODE (op0);
1879 while (code1 == SUBREG)
1881 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
1882 GET_MODE (SUBREG_REG (op1)),
1885 op1 = SUBREG_REG (op1);
1886 code1 = GET_CODE (op1);
1889 /* For our purposes, a condition code mode is the same as SImode. */
1895 int regno0 = REGNO (op0) + subreg_offset0;
1899 int regno1 = REGNO (op1) + subreg_offset1;
1901 /* Just in case, don't do anything for assigning a register
1902 to itself, unless we are filling a delay slot. */
1903 if (regno0 == regno1 && set_nomacro == 0)
1906 else if (GP_REG_P (regno0))
1908 if (GP_REG_P (regno1))
1909 ret = "move\t%0,%1";
1911 else if (MD_REG_P (regno1))
1914 if (regno1 != HILO_REGNUM)
1920 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
1921 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1926 if (FP_REG_P (regno1))
1927 ret = "mfc1\t%0,%1";
1929 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
1930 ret = "cfc1\t%0,$31";
1934 else if (FP_REG_P (regno0))
1936 if (GP_REG_P (regno1))
1939 ret = "mtc1\t%1,%0";
1942 if (FP_REG_P (regno1))
1943 ret = "mov.s\t%0,%1";
1946 else if (MD_REG_P (regno0))
1948 if (GP_REG_P (regno1))
1951 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1956 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
1958 if (GP_REG_P (regno1))
1961 ret = "ctc1\t%0,$31";
1966 else if (code1 == MEM)
1971 mips_count_memory_refs (op1, 1);
1973 if (GP_REG_P (regno0))
1975 /* For loads, use the mode of the memory item, instead of the
1976 target, so zero/sign extend can use this code as well. */
1977 switch (GET_MODE (op1))
1986 ret = ((unsignedp && TARGET_64BIT)
1991 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1994 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1999 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
2002 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
2004 size_t i = strlen (ret);
2005 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2008 sprintf (volatile_buffer, "%%{%s%%}", ret);
2009 ret = volatile_buffer;
2013 else if (code1 == CONST_INT
2014 || (code1 == CONST_DOUBLE
2015 && GET_MODE (op1) == VOIDmode))
2017 if (code1 == CONST_DOUBLE)
2019 /* This can happen when storing constants into long long
2020 bitfields. Just store the least significant word of
2022 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2025 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
2027 if (GP_REG_P (regno0))
2028 ret = "move\t%0,%z1";
2030 else if (FP_REG_P (regno0))
2033 ret = "mtc1\t%z1,%0";
2036 else if (MD_REG_P (regno0))
2043 else if (GP_REG_P (regno0))
2045 /* Don't use X format, because that will give out of
2046 range numbers for 64 bit host and 32 bit target. */
2047 if (! TARGET_MIPS16)
2048 ret = "li\t%0,%1\t\t\t# %X1";
2051 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2053 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2054 ret = "li\t%0,%n1\n\tneg\t%0";
2059 else if (code1 == CONST_DOUBLE && mode == SFmode)
2061 if (op1 == CONST0_RTX (SFmode))
2063 if (GP_REG_P (regno0))
2064 ret = "move\t%0,%.";
2066 else if (FP_REG_P (regno0))
2069 ret = "mtc1\t%.,%0";
2076 ret = "li.s\t%0,%1";
2080 else if (code1 == LABEL_REF)
2083 mips_count_memory_refs (op1, 1);
2088 else if (code1 == SYMBOL_REF || code1 == CONST)
2090 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
2092 rtx offset = const0_rtx;
2094 if (GET_CODE (op1) == CONST)
2095 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2097 if (GET_CODE (op1) == SYMBOL_REF)
2099 operands[2] = HALF_PIC_PTR (op1);
2102 mips_count_memory_refs (operands[2], 1);
2104 if (INTVAL (offset) == 0)
2107 ret = (unsignedp && TARGET_64BIT
2113 dslots_load_total++;
2114 operands[3] = offset;
2115 if (unsignedp && TARGET_64BIT)
2116 ret = (SMALL_INT (offset)
2117 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2118 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2120 ret = (SMALL_INT (offset)
2121 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2122 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2126 else if (TARGET_MIPS16
2128 && GET_CODE (XEXP (op1, 0)) == REG
2129 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2131 /* This case arises on the mips16; see
2132 mips16_gp_pseudo_reg. */
2133 ret = "move\t%0,%+";
2135 else if (TARGET_MIPS16
2136 && code1 == SYMBOL_REF
2137 && SYMBOL_REF_FLAG (op1)
2138 && (XSTR (op1, 0)[0] != '*'
2139 || strncmp (XSTR (op1, 0) + 1,
2141 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2143 /* This can occur when reloading the address of a GP
2144 relative symbol on the mips16. */
2145 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2150 mips_count_memory_refs (op1, 1);
2156 else if (code1 == PLUS)
2158 rtx add_op0 = XEXP (op1, 0);
2159 rtx add_op1 = XEXP (op1, 1);
2161 if (GET_CODE (XEXP (op1, 1)) == REG
2162 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2163 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2165 operands[2] = add_op0;
2166 operands[3] = add_op1;
2167 ret = "add%:\t%0,%2,%3";
2170 else if (code1 == HIGH)
2172 operands[1] = XEXP (op1, 0);
2173 ret = "lui\t%0,%%hi(%1)";
2177 else if (code0 == MEM)
2180 mips_count_memory_refs (op0, 1);
2184 int regno1 = REGNO (op1) + subreg_offset1;
2186 if (GP_REG_P (regno1))
2190 case SFmode: ret = "sw\t%1,%0"; break;
2191 case SImode: ret = "sw\t%1,%0"; break;
2192 case HImode: ret = "sh\t%1,%0"; break;
2193 case QImode: ret = "sb\t%1,%0"; break;
2198 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2202 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2206 case SFmode: ret = "sw\t%z1,%0"; break;
2207 case SImode: ret = "sw\t%z1,%0"; break;
2208 case HImode: ret = "sh\t%z1,%0"; break;
2209 case QImode: ret = "sb\t%z1,%0"; break;
2214 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2218 case SFmode: ret = "sw\t%.,%0"; break;
2219 case SImode: ret = "sw\t%.,%0"; break;
2220 case HImode: ret = "sh\t%.,%0"; break;
2221 case QImode: ret = "sb\t%.,%0"; break;
2226 if (ret != 0 && MEM_VOLATILE_P (op0))
2228 size_t i = strlen (ret);
2230 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2233 sprintf (volatile_buffer, "%%{%s%%}", ret);
2234 ret = volatile_buffer;
2240 abort_with_insn (insn, "Bad move");
2244 if (delay != DELAY_NONE)
2245 return mips_fill_delay_slot (ret, delay, operands, insn);
2251 /* Return the appropriate instructions to move 2 words */
2254 mips_move_2words (operands, insn)
2258 const char *ret = 0;
2259 rtx op0 = operands[0];
2260 rtx op1 = operands[1];
2261 enum rtx_code code0 = GET_CODE (operands[0]);
2262 enum rtx_code code1 = GET_CODE (operands[1]);
2263 int subreg_offset0 = 0;
2264 int subreg_offset1 = 0;
2265 enum delay_type delay = DELAY_NONE;
2267 while (code0 == SUBREG)
2269 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2270 GET_MODE (SUBREG_REG (op0)),
2273 op0 = SUBREG_REG (op0);
2274 code0 = GET_CODE (op0);
2277 if (code1 == SIGN_EXTEND)
2279 op1 = XEXP (op1, 0);
2280 code1 = GET_CODE (op1);
2283 while (code1 == SUBREG)
2285 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2286 GET_MODE (SUBREG_REG (op1)),
2289 op1 = SUBREG_REG (op1);
2290 code1 = GET_CODE (op1);
2294 if (GET_CODE (operands[1]) == SIGN_EXTEND
2296 && code1 != CONST_INT
2297 /* The following three can happen as the result of a questionable
2299 && code1 != LABEL_REF
2300 && code1 != SYMBOL_REF
2306 int regno0 = REGNO (op0) + subreg_offset0;
2310 int regno1 = REGNO (op1) + subreg_offset1;
2312 /* Just in case, don't do anything for assigning a register
2313 to itself, unless we are filling a delay slot. */
2314 if (regno0 == regno1 && set_nomacro == 0)
2317 else if (FP_REG_P (regno0))
2319 if (FP_REG_P (regno1))
2320 ret = "mov.d\t%0,%1";
2328 abort_with_insn (insn, "Bad move");
2330 #ifdef TARGET_FP_CALL_32
2331 if (FP_CALL_GP_REG_P (regno1))
2332 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2335 ret = "dmtc1\t%1,%0";
2338 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2342 else if (FP_REG_P (regno1))
2348 abort_with_insn (insn, "Bad move");
2350 #ifdef TARGET_FP_CALL_32
2351 if (FP_CALL_GP_REG_P (regno0))
2352 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2355 ret = "dmfc1\t%0,%1";
2358 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2361 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2366 if (regno0 != HILO_REGNUM)
2368 else if (regno1 == 0)
2369 ret = "mtlo\t%.\n\tmthi\t%.";
2372 ret = "mthi\t%M1\n\tmtlo\t%L1";
2375 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2380 if (regno1 != HILO_REGNUM)
2384 ret = "mfhi\t%M0\n\tmflo\t%L0";
2387 else if (TARGET_64BIT)
2388 ret = "move\t%0,%1";
2390 else if (regno0 != (regno1+1))
2391 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2394 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2397 else if (code1 == CONST_DOUBLE)
2399 /* Move zero from $0 unless !TARGET_64BIT and recipient
2400 is 64-bit fp reg, in which case generate a constant. */
2401 if (op1 != CONST0_RTX (GET_MODE (op1))
2402 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2404 if (GET_MODE (op1) == DFmode)
2408 #ifdef TARGET_FP_CALL_32
2409 if (FP_CALL_GP_REG_P (regno0))
2411 if (TARGET_FLOAT64 && !TARGET_64BIT)
2413 split_double (op1, operands + 2, operands + 3);
2414 ret = "li\t%0,%2\n\tli\t%D0,%3";
2417 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2421 /* GNU as emits 64-bit code for li.d if the ISA is 3
2422 or higher. For !TARGET_64BIT && gp registers we
2423 need to avoid this by using two li instructions
2425 if (ISA_HAS_64BIT_REGS
2427 && ! FP_REG_P (regno0))
2429 split_double (op1, operands + 2, operands + 3);
2430 ret = "li\t%0,%2\n\tli\t%D0,%3";
2433 ret = "li.d\t%0,%1";
2436 else if (TARGET_64BIT)
2438 if (! TARGET_MIPS16)
2444 split_double (op1, operands + 2, operands + 3);
2445 ret = "li\t%0,%2\n\tli\t%D0,%3";
2451 if (GP_REG_P (regno0))
2453 #ifdef TARGET_FP_CALL_32
2454 && ! FP_CALL_GP_REG_P (regno0)
2457 : "move\t%0,%.\n\tmove\t%D0,%.");
2459 else if (FP_REG_P (regno0))
2464 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2469 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2471 if (GP_REG_P (regno0))
2474 : "move\t%0,%.\n\tmove\t%D0,%.");
2476 else if (FP_REG_P (regno0))
2483 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2485 else if (MD_REG_P (regno0))
2488 ret = (regno0 == HILO_REGNUM
2489 ? "mtlo\t%.\n\tmthi\t%."
2494 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2495 && GP_REG_P (regno0))
2501 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2503 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2504 ret = "li\t%0,%n1\n\tneg\t%0";
2506 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2507 ret = "li\t%0,%1\t\t# %X1";
2508 else if (HOST_BITS_PER_WIDE_INT < 64)
2509 /* We can't use 'X' for negative numbers, because then we won't
2510 get the right value for the upper 32 bits. */
2511 ret = (INTVAL (op1) < 0
2512 ? "dli\t%0,%1\t\t\t# %X1"
2513 : "dli\t%0,%X1\t\t# %1");
2515 /* We must use 'X', because otherwise LONG_MIN will print as
2516 a number that the assembler won't accept. */
2517 ret = "dli\t%0,%X1\t\t# %1";
2519 else if (HOST_BITS_PER_WIDE_INT < 64)
2521 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2524 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2525 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2526 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2528 operands[2] = GEN_INT (1);
2529 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2533 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2537 /* We use multiple shifts here, to avoid warnings about out
2538 of range shifts on 32 bit hosts. */
2539 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2541 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2542 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2546 else if (code1 == MEM)
2551 mips_count_memory_refs (op1, 2);
2553 if (FP_REG_P (regno0))
2556 else if (TARGET_64BIT)
2559 #ifdef TARGET_FP_CALL_32
2560 if (FP_CALL_GP_REG_P (regno0))
2561 ret = (double_memory_operand (op1, GET_MODE (op1))
2562 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2563 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2569 else if (double_memory_operand (op1, GET_MODE (op1)))
2570 ret = (reg_mentioned_p (op0, op1)
2571 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2572 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2574 if (ret != 0 && MEM_VOLATILE_P (op1))
2576 size_t i = strlen (ret);
2578 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2581 sprintf (volatile_buffer, "%%{%s%%}", ret);
2582 ret = volatile_buffer;
2586 else if (code1 == LABEL_REF)
2589 mips_count_memory_refs (op1, 2);
2591 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2592 /* We deliberately remove the 'a' from '%1', so that we don't
2593 have to add SIGN_EXTEND support to print_operand_address.
2594 print_operand will just call print_operand_address in this
2595 case, so there is no problem. */
2598 ret = "dla\t%0,%a1";
2600 else if (code1 == SYMBOL_REF || code1 == CONST)
2604 && GET_CODE (XEXP (op1, 0)) == REG
2605 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2607 /* This case arises on the mips16; see
2608 mips16_gp_pseudo_reg. */
2609 ret = "move\t%0,%+";
2611 else if (TARGET_MIPS16
2612 && code1 == SYMBOL_REF
2613 && SYMBOL_REF_FLAG (op1)
2614 && (XSTR (op1, 0)[0] != '*'
2615 || strncmp (XSTR (op1, 0) + 1,
2617 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2619 /* This can occur when reloading the address of a GP
2620 relative symbol on the mips16. */
2621 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2626 mips_count_memory_refs (op1, 2);
2628 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2629 /* We deliberately remove the 'a' from '%1', so that we don't
2630 have to add SIGN_EXTEND support to print_operand_address.
2631 print_operand will just call print_operand_address in this
2632 case, so there is no problem. */
2635 ret = "dla\t%0,%a1";
2640 else if (code0 == MEM)
2644 int regno1 = REGNO (op1) + subreg_offset1;
2646 if (FP_REG_P (regno1))
2649 else if (TARGET_64BIT)
2652 #ifdef TARGET_FP_CALL_32
2653 if (FP_CALL_GP_REG_P (regno1))
2654 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2660 else if (double_memory_operand (op0, GET_MODE (op0)))
2661 ret = "sw\t%1,%0\n\tsw\t%D1,%D0";
2664 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2665 || (code1 == CONST_DOUBLE
2666 && op1 == CONST0_RTX (GET_MODE (op1))))
2668 || double_memory_operand (op0, GET_MODE (op0))))
2673 ret = "sw\t%.,%0\n\tsw\t%.,%D0";
2677 mips_count_memory_refs (op0, 2);
2679 if (ret != 0 && MEM_VOLATILE_P (op0))
2681 size_t i = strlen (ret);
2683 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2686 sprintf (volatile_buffer, "%%{%s%%}", ret);
2687 ret = volatile_buffer;
2693 abort_with_insn (insn, "Bad move");
2697 if (delay != DELAY_NONE)
2698 return mips_fill_delay_slot (ret, delay, operands, insn);
2703 /* Provide the costs of an addressing mode that contains ADDR.
2704 If ADDR is not a valid address, its cost is irrelevant. */
2707 mips_address_cost (addr)
2710 switch (GET_CODE (addr))
2720 rtx offset = const0_rtx;
2721 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2722 if (GET_CODE (addr) == LABEL_REF)
2725 if (GET_CODE (addr) != SYMBOL_REF)
2728 if (! SMALL_INT (offset))
2732 /* ... fall through ... */
2735 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2739 register rtx plus0 = XEXP (addr, 0);
2740 register rtx plus1 = XEXP (addr, 1);
2742 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2743 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2745 if (GET_CODE (plus0) != REG)
2748 switch (GET_CODE (plus1))
2751 return SMALL_INT (plus1) ? 1 : 2;
2758 return mips_address_cost (plus1) + 1;
2772 /* Return nonzero if X is an address which needs a temporary register when
2773 reloaded while generating PIC code. */
2776 pic_address_needs_scratch (x)
2779 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2780 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2781 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2782 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2783 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2789 /* Make normal rtx_code into something we can index from an array */
2791 static enum internal_test
2792 map_test_to_internal_test (test_code)
2793 enum rtx_code test_code;
2795 enum internal_test test = ITEST_MAX;
2799 case EQ: test = ITEST_EQ; break;
2800 case NE: test = ITEST_NE; break;
2801 case GT: test = ITEST_GT; break;
2802 case GE: test = ITEST_GE; break;
2803 case LT: test = ITEST_LT; break;
2804 case LE: test = ITEST_LE; break;
2805 case GTU: test = ITEST_GTU; break;
2806 case GEU: test = ITEST_GEU; break;
2807 case LTU: test = ITEST_LTU; break;
2808 case LEU: test = ITEST_LEU; break;
2816 /* Generate the code to compare two integer values. The return value is:
2817 (reg:SI xx) The pseudo register the comparison is in
2818 0 No register, generate a simple branch.
2820 ??? This is called with result nonzero by the Scond patterns in
2821 mips.md. These patterns are called with a target in the mode of
2822 the Scond instruction pattern. Since this must be a constant, we
2823 must use SImode. This means that if RESULT is non-zero, it will
2824 always be an SImode register, even if TARGET_64BIT is true. We
2825 cope with this by calling convert_move rather than emit_move_insn.
2826 This will sometimes lead to an unnecessary extension of the result;
2838 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2839 enum rtx_code test_code; /* relational test (EQ, etc) */
2840 rtx result; /* result to store comp. or 0 if branch */
2841 rtx cmp0; /* first operand to compare */
2842 rtx cmp1; /* second operand to compare */
2843 int *p_invert; /* NULL or ptr to hold whether branch needs */
2844 /* to reverse its test */
2848 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2849 int const_low; /* low bound of constant we can accept */
2850 int const_high; /* high bound of constant we can accept */
2851 int const_add; /* constant to add (convert LE -> LT) */
2852 int reverse_regs; /* reverse registers in test */
2853 int invert_const; /* != 0 if invert value if cmp1 is constant */
2854 int invert_reg; /* != 0 if invert value if cmp1 is register */
2855 int unsignedp; /* != 0 for unsigned comparisons. */
2858 static struct cmp_info info[ (int)ITEST_MAX ] = {
2860 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2861 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2862 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2863 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2864 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2865 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2866 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2867 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2868 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2869 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2872 enum internal_test test;
2873 enum machine_mode mode;
2874 struct cmp_info *p_info;
2881 test = map_test_to_internal_test (test_code);
2882 if (test == ITEST_MAX)
2885 p_info = &info[(int) test];
2886 eqne_p = (p_info->test_code == XOR);
2888 mode = GET_MODE (cmp0);
2889 if (mode == VOIDmode)
2890 mode = GET_MODE (cmp1);
2892 /* Eliminate simple branches */
2893 branch_p = (result == 0);
2896 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2898 /* Comparisons against zero are simple branches */
2899 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2900 && (! TARGET_MIPS16 || eqne_p))
2903 /* Test for beq/bne. */
2904 if (eqne_p && ! TARGET_MIPS16)
2908 /* allocate a pseudo to calculate the value in. */
2909 result = gen_reg_rtx (mode);
2912 /* Make sure we can handle any constants given to us. */
2913 if (GET_CODE (cmp0) == CONST_INT)
2914 cmp0 = force_reg (mode, cmp0);
2916 if (GET_CODE (cmp1) == CONST_INT)
2918 HOST_WIDE_INT value = INTVAL (cmp1);
2920 if (value < p_info->const_low
2921 || value > p_info->const_high
2922 /* ??? Why? And why wasn't the similar code below modified too? */
2924 && HOST_BITS_PER_WIDE_INT < 64
2925 && p_info->const_add != 0
2926 && ((p_info->unsignedp
2927 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2928 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2929 : (value + p_info->const_add) > INTVAL (cmp1))
2930 != (p_info->const_add > 0))))
2931 cmp1 = force_reg (mode, cmp1);
2934 /* See if we need to invert the result. */
2935 invert = (GET_CODE (cmp1) == CONST_INT
2936 ? p_info->invert_const : p_info->invert_reg);
2938 if (p_invert != (int *)0)
2944 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2945 Comparison between two registers, may involve switching operands. */
2946 if (GET_CODE (cmp1) == CONST_INT)
2948 if (p_info->const_add != 0)
2950 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2952 /* If modification of cmp1 caused overflow,
2953 we would get the wrong answer if we follow the usual path;
2954 thus, x > 0xffffffffU would turn into x > 0U. */
2955 if ((p_info->unsignedp
2956 ? (unsigned HOST_WIDE_INT) new >
2957 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2958 : new > INTVAL (cmp1))
2959 != (p_info->const_add > 0))
2961 /* This test is always true, but if INVERT is true then
2962 the result of the test needs to be inverted so 0 should
2963 be returned instead. */
2964 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2968 cmp1 = GEN_INT (new);
2972 else if (p_info->reverse_regs)
2979 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2983 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2984 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2987 if (test == ITEST_NE)
2989 if (! TARGET_MIPS16)
2991 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2992 if (p_invert != NULL)
2998 reg2 = invert ? gen_reg_rtx (mode) : result;
2999 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3004 else if (test == ITEST_EQ)
3006 reg2 = invert ? gen_reg_rtx (mode) : result;
3007 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3015 if (! TARGET_MIPS16)
3019 /* The value is in $24. Copy it to another register, so
3020 that reload doesn't think it needs to store the $24 and
3021 the input to the XOR in the same location. */
3022 reg2 = gen_reg_rtx (mode);
3023 emit_move_insn (reg2, reg);
3025 one = force_reg (mode, const1_rtx);
3027 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3033 /* Emit the common code for doing conditional branches.
3034 operand[0] is the label to jump to.
3035 The comparison operands are saved away by cmp{si,di,sf,df}. */
3038 gen_conditional_branch (operands, test_code)
3040 enum rtx_code test_code;
3042 enum cmp_type type = branch_type;
3043 rtx cmp0 = branch_cmp[0];
3044 rtx cmp1 = branch_cmp[1];
3045 enum machine_mode mode;
3054 mode = type == CMP_SI ? SImode : DImode;
3056 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3064 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3065 /* We don't want to build a comparison against a non-zero
3067 cmp1 = force_reg (mode, cmp1);
3074 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3076 reg = gen_reg_rtx (CCmode);
3078 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3079 0 in the instruction built below. The MIPS FPU handles
3080 inequality testing by testing for equality and looking for a
3082 emit_insn (gen_rtx_SET (VOIDmode, reg,
3083 gen_rtx (test_code == NE ? EQ : test_code,
3084 CCmode, cmp0, cmp1)));
3086 test_code = test_code == NE ? EQ : NE;
3094 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3097 /* Generate the branch. */
3099 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3108 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3109 gen_rtx_IF_THEN_ELSE (VOIDmode,
3110 gen_rtx (test_code, mode,
3115 /* Emit the common code for conditional moves. OPERANDS is the array
3116 of operands passed to the conditional move defined_expand. */
3119 gen_conditional_move (operands)
3122 rtx op0 = branch_cmp[0];
3123 rtx op1 = branch_cmp[1];
3124 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3125 enum rtx_code cmp_code = GET_CODE (operands[1]);
3126 enum rtx_code move_code = NE;
3127 enum machine_mode op_mode = GET_MODE (operands[0]);
3128 enum machine_mode cmp_mode;
3131 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3150 op0 = force_reg (mode, branch_cmp[1]);
3151 op1 = branch_cmp[0];
3155 op0 = force_reg (mode, branch_cmp[1]);
3156 op1 = branch_cmp[0];
3167 op0 = force_reg (mode, branch_cmp[1]);
3168 op1 = branch_cmp[0];
3172 op0 = force_reg (mode, branch_cmp[1]);
3173 op1 = branch_cmp[0];
3180 else if (cmp_code == NE)
3181 cmp_code = EQ, move_code = EQ;
3183 if (mode == SImode || mode == DImode)
3185 else if (mode == SFmode || mode == DFmode)
3190 cmp_reg = gen_reg_rtx (cmp_mode);
3191 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3192 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3194 emit_insn (gen_rtx_SET (op_mode, operands[0],
3195 gen_rtx_IF_THEN_ELSE (op_mode,
3196 gen_rtx (move_code, VOIDmode,
3198 CONST0_RTX (SImode)),
3199 operands[2], operands[3])));
3202 /* Emit the common code for conditional moves. OPERANDS is the array
3203 of operands passed to the conditional move defined_expand. */
3206 mips_gen_conditional_trap (operands)
3210 enum rtx_code cmp_code = GET_CODE (operands[0]);
3211 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3213 /* MIPS conditional trap machine instructions don't have GT or LE
3214 flavors, so we must invert the comparison and convert to LT and
3215 GE, respectively. */
3218 case GT: cmp_code = LT; break;
3219 case LE: cmp_code = GE; break;
3220 case GTU: cmp_code = LTU; break;
3221 case LEU: cmp_code = GEU; break;
3224 if (cmp_code == GET_CODE (operands[0]))
3226 op0 = force_reg (mode, branch_cmp[0]);
3227 op1 = branch_cmp[1];
3231 op0 = force_reg (mode, branch_cmp[1]);
3232 op1 = branch_cmp[0];
3234 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3235 op1 = force_reg (mode, op1);
3237 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3238 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3242 /* Write a loop to move a constant number of bytes.
3243 Generate load/stores as follows:
3249 temp<last> = src[MAX_MOVE_REGS-1];
3253 dest[MAX_MOVE_REGS-1] = temp<last>;
3254 src += MAX_MOVE_REGS;
3255 dest += MAX_MOVE_REGS;
3256 } while (src != final);
3258 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3259 registers are needed.
3261 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3262 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3263 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3265 #define MAX_MOVE_REGS 4
3266 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3269 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3270 rtx dest_reg; /* register holding destination address */
3271 rtx src_reg; /* register holding source address */
3272 unsigned int bytes; /* # bytes to move */
3273 int align; /* alignment */
3274 rtx orig_dest; /* original dest */
3275 rtx orig_src; /* original source for making a reg note */
3277 rtx dest_mem = replace_equiv_address (orig_dest, dest_reg);
3278 rtx src_mem = replace_equiv_address (orig_src, src_reg);
3279 rtx align_rtx = GEN_INT (align);
3285 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3288 leftover = bytes % MAX_MOVE_BYTES;
3291 label = gen_label_rtx ();
3292 final_src = gen_reg_rtx (Pmode);
3293 bytes_rtx = GEN_INT (bytes);
3297 if (Pmode == DImode)
3299 emit_insn (gen_movdi (final_src, bytes_rtx));
3300 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3304 emit_insn (gen_movsi (final_src, bytes_rtx));
3305 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3310 if (Pmode == DImode)
3311 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3313 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3318 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3319 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3321 if (Pmode == DImode)
3323 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3324 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3325 emit_insn (gen_cmpdi (src_reg, final_src));
3329 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3330 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3331 emit_insn (gen_cmpsi (src_reg, final_src));
3334 emit_jump_insn (gen_bne (label));
3337 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3341 /* Use a library function to move some bytes. */
3344 block_move_call (dest_reg, src_reg, bytes_rtx)
3349 /* We want to pass the size as Pmode, which will normally be SImode
3350 but will be DImode if we are using 64 bit longs and pointers. */
3351 if (GET_MODE (bytes_rtx) != VOIDmode
3352 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3353 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3355 #ifdef TARGET_MEM_FUNCTIONS
3356 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3357 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3358 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3359 TREE_UNSIGNED (sizetype)),
3360 TYPE_MODE (sizetype));
3362 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3363 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3364 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3365 TREE_UNSIGNED (integer_type_node)),
3366 TYPE_MODE (integer_type_node));
3370 /* Expand string/block move operations.
3372 operands[0] is the pointer to the destination.
3373 operands[1] is the pointer to the source.
3374 operands[2] is the number of bytes to move.
3375 operands[3] is the alignment. */
3378 expand_block_move (operands)
3381 rtx bytes_rtx = operands[2];
3382 rtx align_rtx = operands[3];
3383 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3384 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3385 unsigned int align = INTVAL (align_rtx);
3386 rtx orig_src = operands[1];
3387 rtx orig_dest = operands[0];
3391 if (constp && bytes == 0)
3394 if (align > (unsigned) UNITS_PER_WORD)
3395 align = UNITS_PER_WORD;
3397 /* Move the address into scratch registers. */
3398 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3399 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3402 block_move_call (dest_reg, src_reg, bytes_rtx);
3404 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3405 && align == (unsigned) UNITS_PER_WORD)
3406 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3408 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3409 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3411 replace_equiv_address (orig_src,
3413 bytes_rtx, align_rtx));
3415 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3416 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3418 else if (constp && optimize)
3420 /* If the alignment is not word aligned, generate a test at
3421 runtime, to see whether things wound up aligned, and we
3422 can use the faster lw/sw instead ulw/usw. */
3424 rtx temp = gen_reg_rtx (Pmode);
3425 rtx aligned_label = gen_label_rtx ();
3426 rtx join_label = gen_label_rtx ();
3427 int leftover = bytes % MAX_MOVE_BYTES;
3431 if (Pmode == DImode)
3433 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3434 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3435 emit_insn (gen_cmpdi (temp, const0_rtx));
3439 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3440 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3441 emit_insn (gen_cmpsi (temp, const0_rtx));
3444 emit_jump_insn (gen_beq (aligned_label));
3446 /* Unaligned loop. */
3447 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3448 emit_jump_insn (gen_jump (join_label));
3452 emit_label (aligned_label);
3453 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3455 emit_label (join_label);
3457 /* Bytes at the end of the loop. */
3459 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3461 replace_equiv_address (orig_src,
3468 block_move_call (dest_reg, src_reg, bytes_rtx);
3471 /* Emit load/stores for a small constant block_move.
3473 operands[0] is the memory address of the destination.
3474 operands[1] is the memory address of the source.
3475 operands[2] is the number of bytes to move.
3476 operands[3] is the alignment.
3477 operands[4] is a temp register.
3478 operands[5] is a temp register.
3480 operands[3+num_regs] is the last temp register.
3482 The block move type can be one of the following:
3483 BLOCK_MOVE_NORMAL Do all of the block move.
3484 BLOCK_MOVE_NOT_LAST Do all but the last store.
3485 BLOCK_MOVE_LAST Do just the last store. */
3488 output_block_move (insn, operands, num_regs, move_type)
3492 enum block_move_type move_type;
3494 rtx dest_reg = XEXP (operands[0], 0);
3495 rtx src_reg = XEXP (operands[1], 0);
3496 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3497 int align = INTVAL (operands[3]);
3500 int use_lwl_lwr = 0;
3501 int last_operand = num_regs + 4;
3507 const char *load; /* load insn without nop */
3508 const char *load_nop; /* load insn with trailing nop */
3509 const char *store; /* store insn */
3510 const char *final; /* if last_store used: NULL or swr */
3511 const char *last_store; /* last store instruction */
3512 int offset; /* current offset */
3513 enum machine_mode mode; /* mode to use on (MEM) */
3516 /* ??? Detect a bug in GCC, where it can give us a register
3517 the same as one of the addressing registers and reduce
3518 the number of registers available. */
3519 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3520 if (! reg_mentioned_p (operands[i], operands[0])
3521 && ! reg_mentioned_p (operands[i], operands[1]))
3522 xoperands[safe_regs++] = operands[i];
3524 if (safe_regs < last_operand)
3526 xoperands[0] = operands[0];
3527 xoperands[1] = operands[1];
3528 xoperands[2] = operands[2];
3529 xoperands[3] = operands[3];
3530 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3533 /* If we are given global or static addresses, and we would be
3534 emitting a few instructions, try to save time by using a
3535 temporary register for the pointer. */
3536 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3537 an ldl/ldr instruction pair. We play it safe, and always move
3538 constant addresses into registers when generating N32/N64 code, just
3539 in case we might emit an unaligned load instruction. */
3540 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3541 || mips_abi == ABI_MEABI
3542 || mips_abi == ABI_N32
3543 || mips_abi == ABI_64))
3545 if (CONSTANT_P (src_reg))
3548 mips_count_memory_refs (operands[1], 1);
3550 src_reg = operands[3 + num_regs--];
3551 if (move_type != BLOCK_MOVE_LAST)
3553 xoperands[1] = operands[1];
3554 xoperands[0] = src_reg;
3555 if (Pmode == DImode)
3556 output_asm_insn ("dla\t%0,%1", xoperands);
3558 output_asm_insn ("la\t%0,%1", xoperands);
3562 if (CONSTANT_P (dest_reg))
3565 mips_count_memory_refs (operands[0], 1);
3567 dest_reg = operands[3 + num_regs--];
3568 if (move_type != BLOCK_MOVE_LAST)
3570 xoperands[1] = operands[0];
3571 xoperands[0] = dest_reg;
3572 if (Pmode == DImode)
3573 output_asm_insn ("dla\t%0,%1", xoperands);
3575 output_asm_insn ("la\t%0,%1", xoperands);
3580 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3581 are not offsettable, however, offsettable_address_p says they are
3582 offsettable. I think this is a bug in offsettable_address_p.
3583 For expediency, we fix this by just loading the address into a register
3584 if we happen to get one. */
3586 if (GET_CODE (src_reg) == LO_SUM)
3588 src_reg = operands[3 + num_regs--];
3589 if (move_type != BLOCK_MOVE_LAST)
3591 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3592 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3593 xoperands[0] = src_reg;
3594 if (Pmode == DImode)
3595 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3597 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3601 if (GET_CODE (dest_reg) == LO_SUM)
3603 dest_reg = operands[3 + num_regs--];
3604 if (move_type != BLOCK_MOVE_LAST)
3606 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3607 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3608 xoperands[0] = dest_reg;
3609 if (Pmode == DImode)
3610 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3612 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3616 if (num_regs > (int) ARRAY_SIZE (load_store))
3617 num_regs = ARRAY_SIZE (load_store);
3619 else if (num_regs < 1)
3620 abort_with_insn (insn,
3621 "Cannot do block move, not enough scratch registers");
3625 load_store[num].offset = offset;
3627 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3629 load_store[num].load = "ld\t%0,%1";
3630 load_store[num].load_nop = "ld\t%0,%1%#";
3631 load_store[num].store = "sd\t%0,%1";
3632 load_store[num].last_store = "sd\t%0,%1";
3633 load_store[num].final = 0;
3634 load_store[num].mode = DImode;
3639 /* ??? Fails because of a MIPS assembler bug? */
3640 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3642 if (BYTES_BIG_ENDIAN)
3644 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3645 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3646 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3647 load_store[num].last_store = "sdr\t%0,%2";
3648 load_store[num].final = "sdl\t%0,%1";
3652 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3653 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3654 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3655 load_store[num].last_store = "sdr\t%0,%1";
3656 load_store[num].final = "sdl\t%0,%2";
3659 load_store[num].mode = DImode;
3665 else if (bytes >= 4 && align >= 4)
3667 load_store[num].load = "lw\t%0,%1";
3668 load_store[num].load_nop = "lw\t%0,%1%#";
3669 load_store[num].store = "sw\t%0,%1";
3670 load_store[num].last_store = "sw\t%0,%1";
3671 load_store[num].final = 0;
3672 load_store[num].mode = SImode;
3677 else if (bytes >= 4 && ! TARGET_MIPS16)
3679 if (BYTES_BIG_ENDIAN)
3681 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3682 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3683 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3684 load_store[num].last_store = "swr\t%0,%2";
3685 load_store[num].final = "swl\t%0,%1";
3689 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3690 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3691 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3692 load_store[num].last_store = "swr\t%0,%1";
3693 load_store[num].final = "swl\t%0,%2";
3696 load_store[num].mode = SImode;
3702 else if (bytes >= 2 && align >= 2)
3704 load_store[num].load = "lh\t%0,%1";
3705 load_store[num].load_nop = "lh\t%0,%1%#";
3706 load_store[num].store = "sh\t%0,%1";
3707 load_store[num].last_store = "sh\t%0,%1";
3708 load_store[num].final = 0;
3709 load_store[num].mode = HImode;
3715 load_store[num].load = "lb\t%0,%1";
3716 load_store[num].load_nop = "lb\t%0,%1%#";
3717 load_store[num].store = "sb\t%0,%1";
3718 load_store[num].last_store = "sb\t%0,%1";
3719 load_store[num].final = 0;
3720 load_store[num].mode = QImode;
3725 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3727 dslots_load_total++;
3728 dslots_load_filled++;
3730 if (CONSTANT_P (src_reg))
3731 mips_count_memory_refs (src_reg, 1);
3733 if (CONSTANT_P (dest_reg))
3734 mips_count_memory_refs (dest_reg, 1);
3737 /* Emit load/stores now if we have run out of registers or are
3738 at the end of the move. */
3740 if (++num == num_regs || bytes == 0)
3742 /* If only load/store, we need a NOP after the load. */
3745 load_store[0].load = load_store[0].load_nop;
3746 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3747 dslots_load_filled--;
3750 if (move_type != BLOCK_MOVE_LAST)
3752 for (i = 0; i < num; i++)
3756 if (!operands[i + 4])
3759 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3760 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3761 REGNO (operands[i + 4]));
3763 offset = load_store[i].offset;
3764 xoperands[0] = operands[i + 4];
3765 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3766 plus_constant (src_reg, offset));
3771 = GET_MODE_SIZE (load_store[i].mode) - 1;
3773 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3774 plus_constant (src_reg,
3779 output_asm_insn (load_store[i].load, xoperands);
3783 for (i = 0; i < num; i++)
3785 int last_p = (i == num-1 && bytes == 0);
3786 int offset = load_store[i].offset;
3788 xoperands[0] = operands[i + 4];
3789 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3790 plus_constant (dest_reg, offset));
3795 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3796 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3797 plus_constant (dest_reg,
3802 if (move_type == BLOCK_MOVE_NORMAL)
3803 output_asm_insn (load_store[i].store, xoperands);
3805 else if (move_type == BLOCK_MOVE_NOT_LAST)
3808 output_asm_insn (load_store[i].store, xoperands);
3810 else if (load_store[i].final != 0)
3811 output_asm_insn (load_store[i].final, xoperands);
3815 output_asm_insn (load_store[i].last_store, xoperands);
3818 num = 0; /* reset load_store */
3826 /* Argument support functions. */
3828 /* Initialize CUMULATIVE_ARGS for a function. */
3831 init_cumulative_args (cum, fntype, libname)
3832 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3833 tree fntype; /* tree ptr for function decl */
3834 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3836 static CUMULATIVE_ARGS zero_cum;
3837 tree param, next_param;
3839 if (TARGET_DEBUG_E_MODE)
3842 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3845 fputc ('\n', stderr);
3849 tree ret_type = TREE_TYPE (fntype);
3850 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3851 tree_code_name[(int)TREE_CODE (fntype)],
3852 tree_code_name[(int)TREE_CODE (ret_type)]);
3858 /* Determine if this function has variable arguments. This is
3859 indicated by the last argument being 'void_type_mode' if there
3860 are no variable arguments. The standard MIPS calling sequence
3861 passes all arguments in the general purpose registers in this case. */
3863 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3864 param != 0; param = next_param)
3866 next_param = TREE_CHAIN (param);
3867 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3868 cum->gp_reg_found = 1;
3872 /* Advance the argument to the next argument position. */
3875 function_arg_advance (cum, mode, type, named)
3876 CUMULATIVE_ARGS *cum; /* current arg information */
3877 enum machine_mode mode; /* current arg mode */
3878 tree type; /* type of the argument or 0 if lib support */
3879 int named; /* whether or not the argument was named */
3881 if (TARGET_DEBUG_E_MODE)
3884 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3885 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3886 GET_MODE_NAME (mode));
3887 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3888 fprintf (stderr, ", %d )\n\n", named);
3898 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3899 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3902 cum->gp_reg_found = 1;
3903 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3908 cum->gp_reg_found = 1;
3909 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3914 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3915 cum->fp_arg_words++;
3918 if (! cum->gp_reg_found && cum->arg_number <= 2)
3919 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3923 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3924 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3926 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3927 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3928 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3932 cum->gp_reg_found = 1;
3933 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3939 cum->gp_reg_found = 1;
3945 /* Return an RTL expression containing the register for the given mode,
3946 or 0 if the argument is to be passed on the stack. */
3949 function_arg (cum, mode, type, named)
3950 CUMULATIVE_ARGS *cum; /* current arg information */
3951 enum machine_mode mode; /* current arg mode */
3952 tree type; /* type of the argument or 0 if lib support */
3953 int named; /* != 0 for normal args, == 0 for ... args */
3958 unsigned int *arg_words = &cum->arg_words;
3959 int struct_p = (type != 0
3960 && (TREE_CODE (type) == RECORD_TYPE
3961 || TREE_CODE (type) == UNION_TYPE
3962 || TREE_CODE (type) == QUAL_UNION_TYPE));
3964 if (TARGET_DEBUG_E_MODE)
3967 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3968 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3969 GET_MODE_NAME (mode));
3970 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3971 fprintf (stderr, ", %d ) = ", named);
3975 cum->last_arg_fp = 0;
3979 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3981 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3982 regbase = GP_ARG_FIRST;
3985 regbase = FP_ARG_FIRST;
3987 /* If the first arg was a float in a floating point register,
3988 then set bias to align this float arg properly. */
3989 if (cum->arg_words == 1)
3993 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3996 cum->fp_arg_words += cum->fp_arg_words & 1;
3997 cum->last_arg_fp = 1;
3998 arg_words = &cum->fp_arg_words;
3999 regbase = FP_ARG_FIRST;
4001 /* The MIPS eabi says only structures containing doubles get passed in a
4002 fp register, so force a structure containing a float to be passed in
4003 the integer registers. */
4004 else if (mips_abi == ABI_MEABI && struct_p)
4005 regbase = GP_ARG_FIRST;
4007 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
4013 if (mips_abi == ABI_EABI
4014 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
4015 cum->fp_arg_words += cum->fp_arg_words & 1;
4017 cum->arg_words += cum->arg_words & 1;
4020 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4021 regbase = ((cum->gp_reg_found
4022 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
4023 || cum->arg_number >= 2)
4024 ? GP_ARG_FIRST : FP_ARG_FIRST);
4025 else if (mips_abi == ABI_EABI
4026 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
4028 cum->last_arg_fp = 1;
4029 arg_words = &cum->fp_arg_words;
4030 regbase = FP_ARG_FIRST;
4033 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
4034 ? GP_ARG_FIRST : FP_ARG_FIRST);
4038 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4039 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4042 /* Drops through. */
4044 if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
4045 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4046 cum->arg_words += (cum->arg_words & 1);
4047 regbase = GP_ARG_FIRST;
4054 regbase = GP_ARG_FIRST;
4059 cum->arg_words += (cum->arg_words & 1);
4060 regbase = GP_ARG_FIRST;
4063 if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
4065 if (TARGET_DEBUG_E_MODE)
4066 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
4075 if (! type || TREE_CODE (type) != RECORD_TYPE
4076 || mips_abi == ABI_32 || mips_abi == ABI_EABI
4077 || mips_abi == ABI_O64 || mips_abi == ABI_MEABI
4079 || ! TYPE_SIZE_UNIT (type)
4080 || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
4083 unsigned int arg_reg = (regbase + *arg_words + bias);
4084 ret = gen_rtx_REG (mode, arg_reg);
4085 if (mips_abi == ABI_MEABI
4086 && regbase == FP_ARG_FIRST
4087 && ! cum->prototype)
4089 /* To make K&R varargs work we need to pass floating
4090 point arguments in both integer and FP registers. */
4091 ret = gen_rtx_PARALLEL (mode,
4093 gen_rtx_EXPR_LIST (VOIDmode,
4095 arg_reg + GP_ARG_FIRST - FP_ARG_FIRST),
4096 const0_rtx), gen_rtx_EXPR_LIST (VOIDmode, ret, const0_rtx)));
4101 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4102 structure contains a double in its entirety, then that 64 bit
4103 chunk is passed in a floating point register. */
4106 /* First check to see if there is any such field. */
4107 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4108 if (TREE_CODE (field) == FIELD_DECL
4109 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4110 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4111 && host_integerp (bit_position (field), 0)
4112 && int_bit_position (field) % BITS_PER_WORD == 0)
4115 /* If the whole struct fits a DFmode register,
4116 we don't need the PARALLEL. */
4117 if (! field || mode == DFmode)
4118 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4121 /* Now handle the special case by returning a PARALLEL
4122 indicating where each 64 bit chunk goes. */
4123 unsigned int chunks;
4124 HOST_WIDE_INT bitpos;
4128 /* ??? If this is a packed structure, then the last hunk won't
4132 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
4133 if (chunks + *arg_words + bias > (unsigned) MAX_ARGS_IN_REGISTERS)
4134 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
4136 /* assign_parms checks the mode of ENTRY_PARM, so we must
4137 use the actual mode here. */
4138 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
4141 regno = regbase + *arg_words + bias;
4142 field = TYPE_FIELDS (type);
4143 for (i = 0; i < chunks; i++)
4147 for (; field; field = TREE_CHAIN (field))
4148 if (TREE_CODE (field) == FIELD_DECL
4149 && int_bit_position (field) >= bitpos)
4153 && int_bit_position (field) == bitpos
4154 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4155 && !TARGET_SOFT_FLOAT
4156 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4157 reg = gen_rtx_REG (DFmode,
4158 regno + FP_ARG_FIRST - GP_ARG_FIRST);
4160 reg = gen_rtx_REG (word_mode, regno);
4163 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4164 GEN_INT (bitpos / BITS_PER_UNIT));
4172 if (TARGET_DEBUG_E_MODE)
4173 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
4174 struct_p ? ", [struct]" : "");
4176 /* The following is a hack in order to pass 1 byte structures
4177 the same way that the MIPS compiler does (namely by passing
4178 the structure in the high byte or half word of the register).
4179 This also makes varargs work. If we have such a structure,
4180 we save the adjustment RTL, and the call define expands will
4181 emit them. For the VOIDmode argument (argument after the
4182 last real argument), pass back a parallel vector holding each
4183 of the adjustments. */
4185 /* ??? function_arg can be called more than once for each argument.
4186 As a result, we compute more adjustments than we need here.
4187 See the CUMULATIVE_ARGS definition in mips.h. */
4189 /* ??? This scheme requires everything smaller than the word size to
4190 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4191 that would mean every int needs to be shifted left, which is very
4192 inefficient. Let's not carry this compatibility to the 64 bit
4193 calling convention for now. */
4195 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
4197 && mips_abi != ABI_EABI
4198 && mips_abi != ABI_MEABI)
4200 rtx amount = GEN_INT (BITS_PER_WORD
4201 - int_size_in_bytes (type) * BITS_PER_UNIT);
4202 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
4205 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
4207 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
4211 /* We will be called with a mode of VOIDmode after the last argument
4212 has been seen. Whatever we return will be passed to the call
4213 insn. If we need any shifts for small structures, return them in
4214 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4215 mode. Otherwise, if we have need a mips16 fp_code, return a REG
4216 with the code stored as the mode. */
4217 if (mode == VOIDmode)
4219 if (cum->num_adjusts > 0)
4220 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
4221 gen_rtvec_v (cum->num_adjusts, cum->adjust));
4222 else if (TARGET_MIPS16 && cum->fp_code != 0)
4223 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
4230 function_arg_partial_nregs (cum, mode, type, named)
4231 CUMULATIVE_ARGS *cum; /* current arg information */
4232 enum machine_mode mode; /* current arg mode */
4233 tree type; /* type of the argument or 0 if lib support */
4234 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
4236 if ((mode == BLKmode
4237 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4238 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4239 && cum->arg_words < (unsigned) MAX_ARGS_IN_REGISTERS
4240 && mips_abi != ABI_EABI)
4243 if (mode == BLKmode)
4244 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
4247 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4249 if (words + cum->arg_words <= (unsigned) MAX_ARGS_IN_REGISTERS)
4250 return 0; /* structure fits in registers */
4252 if (TARGET_DEBUG_E_MODE)
4253 fprintf (stderr, "function_arg_partial_nregs = %d\n",
4254 MAX_ARGS_IN_REGISTERS - cum->arg_words);
4256 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
4259 else if (mode == DImode
4260 && cum->arg_words == MAX_ARGS_IN_REGISTERS - (unsigned)1
4261 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4263 if (TARGET_DEBUG_E_MODE)
4264 fprintf (stderr, "function_arg_partial_nregs = 1\n");
4272 /* Create the va_list data type.
4273 We keep 3 pointers, and two offsets.
4274 Two pointers are to the overflow area, which starts at the CFA.
4275 One of these is constant, for addressing into the GPR save area below it.
4276 The other is advanced up the stack through the overflow region.
4277 The third pointer is to the GPR save area. Since the FPR save area
4278 is just below it, we can address FPR slots off this pointer.
4279 We also keep two one-byte offsets, which are to be subtracted from the
4280 constant pointers to yield addresses in the GPR and FPR save areas.
4281 These are downcounted as float or non-float arguments are used,
4282 and when they get to zero, the argument must be obtained from the
4284 If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
4285 and a single pointer is enough. It's started at the GPR save area,
4286 and is advanced, period.
4287 Note that the GPR save area is not constant size, due to optimization
4288 in the prologue. Hence, we can't use a design with two pointers
4289 and two offsets, although we could have designed this with two pointers
4290 and three offsets. */
4294 mips_build_va_list ()
4296 if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4298 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4300 record = make_node (RECORD_TYPE);
4302 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4304 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4306 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4308 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4309 unsigned_char_type_node);
4310 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4311 unsigned_char_type_node);
4314 DECL_FIELD_CONTEXT (f_ovfl) = record;
4315 DECL_FIELD_CONTEXT (f_gtop) = record;
4316 DECL_FIELD_CONTEXT (f_ftop) = record;
4317 DECL_FIELD_CONTEXT (f_goff) = record;
4318 DECL_FIELD_CONTEXT (f_foff) = record;
4320 TYPE_FIELDS (record) = f_ovfl;
4321 TREE_CHAIN (f_ovfl) = f_gtop;
4322 TREE_CHAIN (f_gtop) = f_ftop;
4323 TREE_CHAIN (f_ftop) = f_goff;
4324 TREE_CHAIN (f_goff) = f_foff;
4326 layout_type (record);
4330 return ptr_type_node;
4333 /* Implement va_start. stdarg_p is 0 if implementing
4334 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4335 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4336 (It doesn't have "...", so it inherits the pointers of its caller.) */
4339 mips_va_start (stdarg_p, valist, nextarg)
4347 /* Find out how many non-float named formals */
4348 int_arg_words = current_function_args_info.arg_words;
4350 if (mips_abi == ABI_EABI)
4352 int gpr_save_area_size;
4353 /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
4354 if (int_arg_words < 8 )
4355 /* Adjust for the prologue's economy measure */
4356 gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
4358 gpr_save_area_size = 0;
4360 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4362 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4363 tree ovfl, gtop, ftop, goff, foff;
4365 int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
4366 int fpr_save_offset;
4368 float_formals = current_function_args_info.fp_arg_words;
4369 /* If mips2, the number of formals is half the reported # of words */
4372 floats_passed_in_regs = (TARGET_64BIT ? 8 : 4);
4374 f_ovfl = TYPE_FIELDS (va_list_type_node);
4375 f_gtop = TREE_CHAIN (f_ovfl);
4376 f_ftop = TREE_CHAIN (f_gtop);
4377 f_goff = TREE_CHAIN (f_ftop);
4378 f_foff = TREE_CHAIN (f_goff);
4380 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4381 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4382 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4383 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4384 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4386 /* Emit code setting a pointer into the overflow (shared-stack) area.
4387 If there were more than 8 non-float formals, or more than 8
4388 float formals, then this pointer isn't to the base of the area.
4389 In that case, it must point to where the first vararg is. */
4391 if (float_formals > floats_passed_in_regs)
4392 size_excess += (float_formals-floats_passed_in_regs) * 8;
4393 if (int_arg_words > 8)
4394 size_excess += (int_arg_words-8) * UNITS_PER_WORD;
4396 /* FIXME: for mips2, the above size_excess can be wrong. Because the
4397 overflow stack holds mixed size items, there can be alignments,
4398 so that an 8 byte double following a 4 byte int will be on an
4399 8 byte boundary. This means that the above calculation should
4400 take into account the exact sequence of floats and non-floats
4401 which make up the excess. That calculation should be rolled
4402 into the code which sets the current_function_args_info struct.
4403 The above then reduces to a fetch from that struct. */
4406 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4408 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4409 build_int_2 (size_excess, 0));
4410 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4411 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4413 /* Emit code setting a ptr to the base of the overflow area. */
4414 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4415 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4416 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4418 /* Emit code setting a pointer to the GPR save area.
4419 More precisely, a pointer to off-the-end of the FPR save area.
4420 If mips4, this is gpr_save_area_size below the overflow area.
4421 If mips2, also round down to an 8-byte boundary, since the FPR
4422 save area is 8-byte aligned, and GPR is 4-byte-aligned.
4423 Therefore there can be a 4-byte gap between the save areas. */
4424 gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4425 fpr_save_offset = gpr_save_area_size;
4428 if (fpr_save_offset & 7)
4429 fpr_save_offset += 4;
4431 if (fpr_save_offset)
4432 gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
4433 build_int_2 (-fpr_save_offset,-1));
4434 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
4435 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4437 /* Emit code initting an offset to the size of the GPR save area */
4438 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4439 build_int_2 (gpr_save_area_size,0));
4440 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4442 /* Emit code initting an offset from ftop to the first float
4443 vararg. This varies in size, since any float
4444 varargs are put in the FPR save area after the formals.
4445 Note it's 8 bytes/formal regardless of TARGET_64BIT.
4446 However, mips2 stores 4 GPRs, mips4 stores 8 GPRs.
4447 If there are 8 or more float formals, init to zero.
4448 (In fact, the formals aren't stored in the bottom of the
4449 FPR save area: they are elsewhere, and the size of the FPR
4450 save area is economized by the prologue. But this code doesn't
4451 care. This design is unaffected by that fact.) */
4452 if (float_formals >= floats_passed_in_regs)
4455 fpr_offset = (floats_passed_in_regs - float_formals) * 8;
4456 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4457 build_int_2 (fpr_offset,0));
4458 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4462 /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
4464 /* Everything is in the GPR save area, or in the overflow
4465 area which is contiguous with it. */
4467 int offset = -gpr_save_area_size;
4468 if (gpr_save_area_size == 0)
4469 offset = (stdarg_p ? 0 : -UNITS_PER_WORD);
4470 nextarg = plus_constant (nextarg, offset);
4471 std_expand_builtin_va_start (1, valist, nextarg);
4483 /* ??? This had been conditional on
4484 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4485 and both iris5.h and iris6.h define _MIPS_SIM. */
4486 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4487 ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
4488 else if (mips_abi == ABI_MEABI)
4489 ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
4491 ofs = -UNITS_PER_WORD;
4494 nextarg = plus_constant (nextarg, ofs);
4495 std_expand_builtin_va_start (1, valist, nextarg);
4499 /* Implement va_arg. */
4502 mips_va_arg (valist, type)
4505 HOST_WIDE_INT size, rsize;
4509 size = int_size_in_bytes (type);
4510 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4512 if (mips_abi == ABI_EABI)
4515 rtx r, lab_over = NULL_RTX, lab_false;
4516 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4517 tree ovfl, gtop, ftop, goff, foff;
4520 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4523 size = POINTER_SIZE / BITS_PER_UNIT;
4524 rsize = UNITS_PER_WORD;
4527 addr_rtx = gen_reg_rtx (Pmode);
4529 if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
4531 /* Case of all args in a merged stack. No need to check bounds,
4532 just advance valist along the stack. */
4537 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4539 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4540 build_int_2 (2*UNITS_PER_WORD - 1, 0));
4541 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4542 build_int_2 (-2*UNITS_PER_WORD, -1));
4543 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4544 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4547 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4549 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4551 emit_move_insn (addr_rtx, r);
4553 /* flush the POSTINCREMENT */
4558 r = gen_rtx_MEM (Pmode, addr_rtx);
4559 set_mem_alias_set (r, get_varargs_alias_set ());
4560 emit_move_insn (addr_rtx, r);
4564 if (BYTES_BIG_ENDIAN && rsize != size)
4565 addr_rtx = plus_constant (addr_rtx, rsize - size);
4570 /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
4572 f_ovfl = TYPE_FIELDS (va_list_type_node);
4573 f_gtop = TREE_CHAIN (f_ovfl);
4574 f_ftop = TREE_CHAIN (f_gtop);
4575 f_goff = TREE_CHAIN (f_ftop);
4576 f_foff = TREE_CHAIN (f_goff);
4578 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4579 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4580 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4581 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4582 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4584 lab_false = gen_label_rtx ();
4585 lab_over = gen_label_rtx ();
4587 if (TREE_CODE (type) == REAL_TYPE)
4590 /* Emit code to branch if foff == 0. */
4591 r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
4593 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4594 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4596 /* Emit code for addr_rtx = ftop - foff */
4597 t = build (MINUS_EXPR, TREE_TYPE (ftop), ftop, foff );
4598 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4600 emit_move_insn (addr_rtx, r);
4602 /* Emit code for foff-=8.
4603 Advances the offset up FPR save area by one double */
4604 t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
4605 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
4606 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4609 emit_jump (lab_over);
4611 emit_label (lab_false);
4615 /* For mips2, the overflow area contains mixed size items.
4616 If a 4-byte int is followed by an 8-byte float, then
4617 natural alignment causes a 4 byte gap.
4618 So, dynamically adjust ovfl up to a multiple of 8. */
4619 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
4620 build_int_2 (7, 0));
4621 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
4622 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4623 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4626 /* Emit code for addr_rtx = the ovfl pointer into overflow area.
4627 Regardless of mips2, postincrement the ovfl pointer by 8. */
4628 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4630 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4632 emit_move_insn (addr_rtx, r);
4635 emit_label (lab_over);
4644 && TREE_CODE (type) == INTEGER_TYPE
4645 && TYPE_PRECISION (type) == 64)
4647 /* In mips2, int takes 32 bits of the GPR save area, but
4648 longlong takes an aligned 64 bits. So, emit code
4649 to zero the low order bits of goff, thus aligning
4650 the later calculation of (gtop-goff) upwards. */
4651 t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
4652 build_int_2 (-8, -1));
4653 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4654 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4657 /* Emit code to branch if goff == 0. */
4658 r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
4660 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4661 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4663 /* Emit code for addr_rtx = gtop - goff. */
4664 t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
4665 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4667 emit_move_insn (addr_rtx, r);
4669 /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
4670 if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
4673 step_size = UNITS_PER_WORD;
4675 /* Emit code for goff = goff - step_size.
4676 Advances the offset up GPR save area over the item. */
4677 t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
4678 build_int_2 (step_size, 0));
4679 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4680 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4683 emit_jump (lab_over);
4685 emit_label (lab_false);
4687 /* Emit code for addr_rtx -> overflow area, postinc by step_size */
4688 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4689 size_int (step_size));
4690 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4692 emit_move_insn (addr_rtx, r);
4695 emit_label (lab_over);
4699 r = gen_rtx_MEM (Pmode, addr_rtx);
4700 set_mem_alias_set (r, get_varargs_alias_set ());
4701 emit_move_insn (addr_rtx, r);
4705 if (BYTES_BIG_ENDIAN && rsize != size)
4706 addr_rtx = plus_constant (addr_rtx, rsize - size);
4716 /* ??? The original va-mips.h did always align, despite the fact
4717 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4718 increment mechanism. */
4722 else if (TYPE_ALIGN (type) > 32)
4727 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4728 build_int_2 (align - 1, 0));
4729 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4730 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4731 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4733 /* Everything past the alignment is standard. */
4734 return std_expand_builtin_va_arg (valist, type);
4738 /* Abort after printing out a specific insn. */
4741 abort_with_insn (insn, reason)
4750 /* Set up the threshold for data to go into the small data area, instead
4751 of the normal data area, and detect any conflicts in the switches. */
4756 register int i, start;
4758 register enum machine_mode mode;
4759 register enum processor_type mips_cpu;
4761 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4763 if (mips_section_threshold <= 0)
4764 target_flags &= ~MASK_GPOPT;
4766 target_flags |= MASK_GPOPT;
4768 /* If both single-float and soft-float are set, then clear the one that
4769 was set by TARGET_DEFAULT, leaving the one that was set by the
4770 user. We assume here that the specs prevent both being set by the
4772 #ifdef TARGET_DEFAULT
4773 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4774 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
4777 /* Get the architectural level. */
4778 if (mips_isa_string == 0)
4779 mips_isa = MIPS_ISA_DEFAULT;
4781 else if (ISDIGIT (*mips_isa_string))
4783 mips_isa = atoi (mips_isa_string);
4786 /* -mno-mips16 overrides -mips16. */
4787 if (mips_no_mips16_string == NULL)
4789 target_flags |= MASK_MIPS16;
4793 mips_isa = MIPS_ISA_DEFAULT;
4797 mips_isa = MIPS_ISA_DEFAULT;
4800 else if (mips_isa < 1
4805 error ("-mips%d not supported", mips_isa);
4812 error ("bad value (%s) for -mips switch", mips_isa_string);
4816 #ifdef MIPS_ABI_DEFAULT
4817 /* Get the ABI to use. */
4818 if (mips_abi_string == (char *) 0)
4819 mips_abi = MIPS_ABI_DEFAULT;
4820 else if (! strcmp (mips_abi_string, "32"))
4822 else if (! strcmp (mips_abi_string, "o64"))
4824 else if (! strcmp (mips_abi_string, "n32"))
4826 else if (! strcmp (mips_abi_string, "64"))
4828 else if (! strcmp (mips_abi_string, "eabi"))
4829 mips_abi = ABI_EABI;
4830 else if (! strcmp (mips_abi_string, "meabi"))
4831 mips_abi = ABI_MEABI;
4833 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4835 /* A specified ISA defaults the ABI if it was not specified. */
4836 if (mips_abi_string == 0 && mips_isa_string
4837 && mips_abi != ABI_EABI
4838 && mips_abi != ABI_O64
4839 && mips_abi != ABI_MEABI)
4845 if (! ISA_HAS_64BIT_REGS)
4852 #ifdef MIPS_CPU_STRING_DEFAULT
4853 /* A specified ABI defaults the ISA if it was not specified. */
4854 else if (mips_isa_string == 0 && mips_abi_string
4855 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4857 if (mips_abi == ABI_32)
4859 else if (mips_abi == ABI_N32)
4866 /* If both ABI and ISA were specified, check for conflicts. */
4867 else if (mips_isa_string && mips_abi_string)
4869 if (! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
4870 || mips_abi == ABI_O64))
4871 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4874 /* Override TARGET_DEFAULT if necessary. */
4875 if (mips_abi == ABI_32)
4876 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4878 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4879 then set the type sizes. In the EABI in 64 bit mode, longs and
4880 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4881 if (mips_explicit_type_size_string == NULL
4882 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4883 || mips_abi == ABI_64))
4884 target_flags |= MASK_LONG64;
4886 /* ??? This doesn't work yet, so don't let people try to use it. */
4887 if (mips_abi == ABI_32)
4888 error ("The -mabi=32 support does not work yet.");
4891 if (mips_abi_string)
4892 error ("This target does not support the -mabi switch.");
4895 #ifdef MIPS_CPU_STRING_DEFAULT
4896 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4897 greater than that supported by the default processor, then the user gets
4898 an error. Normally, the compiler will just default to the base level cpu
4899 for the indicated isa. */
4900 if (mips_arch_string == 0)
4901 mips_arch_string = MIPS_CPU_STRING_DEFAULT;
4902 if (mips_tune_string == 0)
4903 mips_tune_string = MIPS_CPU_STRING_DEFAULT;
4906 /* Identify the processor type. */
4908 if (mips_cpu_string != 0)
4910 mips_cpu = mips_parse_cpu (mips_cpu_string);
4911 if (mips_cpu == PROCESSOR_DEFAULT)
4913 error ("bad value (%s) for -mcpu= switch", mips_arch_string);
4914 mips_cpu_string = "default";
4916 mips_arch = mips_cpu;
4917 mips_tune = mips_cpu;
4920 if (mips_arch_string == 0
4921 || ! strcmp (mips_arch_string, "default")
4922 || ! strcmp (mips_arch_string, "DEFAULT"))
4927 mips_arch_string = "3000";
4928 mips_arch = PROCESSOR_R3000;
4931 mips_arch_string = "6000";
4932 mips_arch = PROCESSOR_R6000;
4935 mips_arch_string = "4000";
4936 mips_arch = PROCESSOR_R4000;
4939 mips_arch_string = "8000";
4940 mips_arch = PROCESSOR_R8000;
4943 mips_arch_string = "4kc";
4944 mips_arch = PROCESSOR_R4KC;
4947 mips_arch_string = "5kc";
4948 mips_arch = PROCESSOR_R5KC;
4954 mips_arch = mips_parse_cpu (mips_arch_string);
4955 if (mips_arch == PROCESSOR_DEFAULT)
4957 error ("bad value (%s) for -march= switch", mips_arch_string);
4958 mips_arch_string = "default";
4961 if (mips_tune_string == 0
4962 || ! strcmp (mips_tune_string, "default")
4963 || ! strcmp (mips_tune_string, "DEFAULT"))
4965 if (mips_arch != PROCESSOR_DEFAULT)
4966 mips_tune = mips_arch;
4971 mips_tune_string = "3000";
4972 mips_tune = PROCESSOR_R3000;
4975 mips_tune_string = "6000";
4976 mips_tune = PROCESSOR_R6000;
4979 mips_tune_string = "4000";
4980 mips_tune = PROCESSOR_R4000;
4983 mips_tune_string = "8000";
4984 mips_tune = PROCESSOR_R8000;
4987 mips_arch_string = "4kc";
4988 mips_arch = PROCESSOR_R4KC;
4991 mips_arch_string = "5kc";
4992 mips_arch = PROCESSOR_R5KC;
4999 mips_tune = mips_parse_cpu (mips_tune_string);
5000 if (mips_tune == PROCESSOR_DEFAULT)
5002 error ("bad value (%s) for -mtune= switch", mips_tune_string);
5003 mips_tune_string = "default";
5007 /* Handle processor configuration based on architecture. */
5012 target_flags |= MASK_SOFT_FLOAT;
5015 if ((mips_arch == PROCESSOR_R3000 && (mips_isa != 1))
5016 || (mips_arch == PROCESSOR_R4KC && mips_isa != 32)
5017 || ((mips_arch == PROCESSOR_R5KC
5018 || mips_arch == PROCESSOR_R20KC) && mips_isa != 64)
5019 || (mips_arch == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
5020 || ((mips_arch == PROCESSOR_R4000
5021 || mips_arch == PROCESSOR_R4100
5022 || mips_arch == PROCESSOR_R4300
5023 || mips_arch == PROCESSOR_R4600
5024 || mips_arch == PROCESSOR_R4650)
5025 && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
5026 error ("-march=%s does not support -mips%d", mips_arch_string, mips_isa);
5028 /* make sure sizes of ints/longs/etc. are ok */
5029 if (! ISA_HAS_64BIT_REGS)
5033 error ("-mips%d does not support 64 bit fp registers", mips_isa);
5034 target_flags &= ~ MASK_FLOAT64;
5037 else if (TARGET_64BIT)
5039 error ("-mips%d does not support 64 bit gp registers", mips_isa);
5040 target_flags &= ~MASK_64BIT;
5044 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
5045 flag_pcc_struct_return = 0;
5047 /* Tell halfpic.c that we have half-pic code if we do. */
5048 if (TARGET_HALF_PIC)
5051 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5052 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5053 /* ??? -non_shared turns off pic code generation, but this is not
5055 if (TARGET_ABICALLS)
5057 mips_abicalls = MIPS_ABICALLS_YES;
5059 if (mips_section_threshold > 0)
5060 warning ("-G is incompatible with PIC code which is the default");
5063 mips_abicalls = MIPS_ABICALLS_NO;
5065 /* -membedded-pic is a form of PIC code suitable for embedded
5066 systems. All calls are made using PC relative addressing, and
5067 all data is addressed using the $gp register. This requires gas,
5068 which does most of the work, and GNU ld, which automatically
5069 expands PC relative calls which are out of range into a longer
5070 instruction sequence. All gcc really does differently is
5071 generate a different sequence for a switch. */
5072 if (TARGET_EMBEDDED_PIC)
5075 if (TARGET_ABICALLS)
5076 warning ("-membedded-pic and -mabicalls are incompatible");
5079 warning ("-G and -membedded-pic are incompatible");
5081 /* Setting mips_section_threshold is not required, because gas
5082 will force everything to be GP addressable anyhow, but
5083 setting it will cause gcc to make better estimates of the
5084 number of instructions required to access a particular data
5086 mips_section_threshold = 0x7fffffff;
5089 /* This optimization requires a linker that can support a R_MIPS_LO16
5090 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5091 GNU ld has this support, but not all other MIPS linkers do, so we enable
5092 this optimization only if the user requests it, or if GNU ld is the
5093 standard linker for this configuration. */
5094 /* ??? This does not work when target addresses are DImode.
5095 This is because we are missing DImode high/lo_sum patterns. */
5096 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5098 mips_split_addresses = 1;
5100 mips_split_addresses = 0;
5102 /* -mrnames says to use the MIPS software convention for register
5103 names instead of the hardware names (ie, $a0 instead of $4).
5104 We do this by switching the names in mips_reg_names, which the
5105 reg_names points into via the REGISTER_NAMES macro. */
5107 if (TARGET_NAME_REGS)
5108 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
5110 /* When compiling for the mips16, we can not use floating point. We
5111 record the original hard float value in mips16_hard_float. */
5114 if (TARGET_SOFT_FLOAT)
5115 mips16_hard_float = 0;
5117 mips16_hard_float = 1;
5118 target_flags |= MASK_SOFT_FLOAT;
5120 /* Don't run the scheduler before reload, since it tends to
5121 increase register pressure. */
5122 flag_schedule_insns = 0;
5125 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5126 to avoid using up another bit in target_flags. */
5127 if (mips_entry_string != NULL)
5129 if (*mips_entry_string != '\0')
5130 error ("Invalid option `entry%s'", mips_entry_string);
5132 if (! TARGET_MIPS16)
5133 warning ("-mentry is only meaningful with -mips-16");
5138 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5139 attributes can access it. */
5145 /* Initialize the high and low values for legitimate floating point
5146 constants. Rather than trying to get the accuracy down to the
5147 last bit, just use approximate ranges. */
5148 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5149 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5150 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5151 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5153 mips_print_operand_punct['?'] = 1;
5154 mips_print_operand_punct['#'] = 1;
5155 mips_print_operand_punct['&'] = 1;
5156 mips_print_operand_punct['!'] = 1;
5157 mips_print_operand_punct['*'] = 1;
5158 mips_print_operand_punct['@'] = 1;
5159 mips_print_operand_punct['.'] = 1;
5160 mips_print_operand_punct['('] = 1;
5161 mips_print_operand_punct[')'] = 1;
5162 mips_print_operand_punct['['] = 1;
5163 mips_print_operand_punct[']'] = 1;
5164 mips_print_operand_punct['<'] = 1;
5165 mips_print_operand_punct['>'] = 1;
5166 mips_print_operand_punct['{'] = 1;
5167 mips_print_operand_punct['}'] = 1;
5168 mips_print_operand_punct['^'] = 1;
5169 mips_print_operand_punct['$'] = 1;
5170 mips_print_operand_punct['+'] = 1;
5171 mips_print_operand_punct['~'] = 1;
5173 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5174 mips_char_to_class['e'] = M16_NA_REGS;
5175 mips_char_to_class['t'] = T_REG;
5176 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5177 mips_char_to_class['h'] = HI_REG;
5178 mips_char_to_class['l'] = LO_REG;
5179 mips_char_to_class['a'] = HILO_REG;
5180 mips_char_to_class['x'] = MD_REGS;
5181 mips_char_to_class['b'] = ALL_REGS;
5182 mips_char_to_class['y'] = GR_REGS;
5183 mips_char_to_class['z'] = ST_REGS;
5185 /* Set up array to map GCC register number to debug register number.
5186 Ignore the special purpose register numbers. */
5188 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5189 mips_dbx_regno[i] = -1;
5191 start = GP_DBX_FIRST - GP_REG_FIRST;
5192 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5193 mips_dbx_regno[i] = i + start;
5195 start = FP_DBX_FIRST - FP_REG_FIRST;
5196 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5197 mips_dbx_regno[i] = i + start;
5199 /* Set up array giving whether a given register can hold a given mode.
5200 At present, restrict ints from being in FP registers, because reload
5201 is a little enthusiastic about storing extra values in FP registers,
5202 and this is not good for things like OS kernels. Also, due to the
5203 mandatory delay, it is as fast to load from cached memory as to move
5204 from the FP register. */
5206 for (mode = VOIDmode;
5207 mode != MAX_MACHINE_MODE;
5208 mode = (enum machine_mode) ((int)mode + 1))
5210 register int size = GET_MODE_SIZE (mode);
5211 register enum mode_class class = GET_MODE_CLASS (mode);
5213 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5220 temp = (regno == FPSW_REGNUM);
5222 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5223 || FP_REG_P (regno));
5226 else if (GP_REG_P (regno))
5227 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5229 else if (FP_REG_P (regno))
5230 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)
5231 /* I think this change is OK regardless of abi, but
5232 I'm being cautions untill I can test this more.
5233 HARD_REGNO_MODE_OK is about whether or not you
5234 can move to and from a register without changing
5235 the value, not about whether math works on the
5237 || (mips_abi == ABI_MEABI && size <= 4))
5238 && (class == MODE_FLOAT
5239 || class == MODE_COMPLEX_FLOAT
5240 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
5241 && (! TARGET_SINGLE_FLOAT || size <= 4));
5243 else if (MD_REG_P (regno))
5244 temp = (class == MODE_INT
5245 && (size <= UNITS_PER_WORD
5246 || (regno == MD_REG_FIRST
5247 && size == 2 * UNITS_PER_WORD)));
5252 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5256 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5257 initialized yet, so we can't use that here. */
5258 gpr_mode = TARGET_64BIT ? DImode : SImode;
5260 /* Provide default values for align_* for 64-bit targets. */
5261 if (TARGET_64BIT && !TARGET_MIPS16)
5263 if (align_loops == 0)
5265 if (align_jumps == 0)
5267 if (align_functions == 0)
5268 align_functions = 8;
5271 /* Register global variables with the garbage collector. */
5272 mips_add_gc_roots ();
5275 /* On the mips16, we want to allocate $24 (T_REG) before other
5276 registers for instructions for which it is possible. This helps
5277 avoid shuffling registers around in order to set up for an xor,
5278 encouraging the compiler to use a cmp instead. */
5281 mips_order_regs_for_local_alloc ()
5285 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5286 reg_alloc_order[i] = i;
5290 /* It really doesn't matter where we put register 0, since it is
5291 a fixed register anyhow. */
5292 reg_alloc_order[0] = 24;
5293 reg_alloc_order[24] = 0;
5298 /* The MIPS debug format wants all automatic variables and arguments
5299 to be in terms of the virtual frame pointer (stack pointer before
5300 any adjustment in the function), while the MIPS 3.0 linker wants
5301 the frame pointer to be the stack pointer after the initial
5302 adjustment. So, we do the adjustment here. The arg pointer (which
5303 is eliminated) points to the virtual frame pointer, while the frame
5304 pointer (which may be eliminated) points to the stack pointer after
5305 the initial adjustments. */
5308 mips_debugger_offset (addr, offset)
5310 HOST_WIDE_INT offset;
5312 rtx offset2 = const0_rtx;
5313 rtx reg = eliminate_constant_term (addr, &offset2);
5316 offset = INTVAL (offset2);
5318 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5319 || reg == hard_frame_pointer_rtx)
5321 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
5322 ? compute_frame_size (get_frame_size ())
5323 : current_frame_info.total_size;
5325 /* MIPS16 frame is smaller */
5326 if (frame_pointer_needed && TARGET_MIPS16)
5327 frame_size -= current_function_outgoing_args_size;
5329 offset = offset - frame_size;
5332 /* sdbout_parms does not want this to crash for unrecognized cases. */
5334 else if (reg != arg_pointer_rtx)
5335 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
5341 /* A C compound statement to output to stdio stream STREAM the
5342 assembler syntax for an instruction operand X. X is an RTL
5345 CODE is a value that can be used to specify one of several ways
5346 of printing the operand. It is used when identical operands
5347 must be printed differently depending on the context. CODE
5348 comes from the `%' specification that was used to request
5349 printing of the operand. If the specification was just `%DIGIT'
5350 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5351 is the ASCII code for LTR.
5353 If X is a register, this macro should print the register's name.
5354 The names can be found in an array `reg_names' whose type is
5355 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5357 When the machine description has a specification `%PUNCT' (a `%'
5358 followed by a punctuation character), this macro is called with
5359 a null pointer for X and the punctuation character for CODE.
5361 The MIPS specific codes are:
5363 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5364 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5365 'd' output integer constant in decimal,
5366 'z' if the operand is 0, use $0 instead of normal operand.
5367 'D' print second part of double-word register or memory operand.
5368 'L' print low-order register of double-word register operand.
5369 'M' print high-order register of double-word register operand.
5370 'C' print part of opcode for a branch condition.
5371 'F' print part of opcode for a floating-point branch condition.
5372 'N' print part of opcode for a branch condition, inverted.
5373 'W' print part of opcode for a floating-point branch condition, inverted.
5374 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5375 'B' print 'z' for EQ, 'n' for NE
5376 'b' print 'n' for EQ, 'z' for NE
5377 'T' print 'f' for EQ, 't' for NE
5378 't' print 't' for EQ, 'f' for NE
5379 'Z' print register and a comma, but print nothing for $fcc0
5380 '(' Turn on .set noreorder
5381 ')' Turn on .set reorder
5382 '[' Turn on .set noat
5384 '<' Turn on .set nomacro
5385 '>' Turn on .set macro
5386 '{' Turn on .set volatile (not GAS)
5387 '}' Turn on .set novolatile (not GAS)
5388 '&' Turn on .set noreorder if filling delay slots
5389 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5390 '!' Turn on .set nomacro if filling delay slots
5391 '#' Print nop if in a .set noreorder section.
5392 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5393 '@' Print the name of the assembler temporary register (at or $1).
5394 '.' Print the name of the register with a hard-wired zero (zero or $0).
5395 '^' Print the name of the pic call-through register (t9 or $25).
5396 '$' Print the name of the stack pointer register (sp or $29).
5397 '+' Print the name of the gp register (gp or $28).
5398 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5401 print_operand (file, op, letter)
5402 FILE *file; /* file to write to */
5403 rtx op; /* operand to print */
5404 int letter; /* %<letter> or 0 */
5406 register enum rtx_code code;
5408 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5413 if (mips_branch_likely)
5418 fputs (reg_names [GP_REG_FIRST + 1], file);
5422 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5426 fputs (reg_names [GP_REG_FIRST + 0], file);
5430 fputs (reg_names[STACK_POINTER_REGNUM], file);
5434 fputs (reg_names[GP_REG_FIRST + 28], file);
5438 if (final_sequence != 0 && set_noreorder++ == 0)
5439 fputs (".set\tnoreorder\n\t", file);
5443 if (final_sequence != 0)
5445 if (set_noreorder++ == 0)
5446 fputs (".set\tnoreorder\n\t", file);
5448 if (set_nomacro++ == 0)
5449 fputs (".set\tnomacro\n\t", file);
5454 if (final_sequence != 0 && set_nomacro++ == 0)
5455 fputs ("\n\t.set\tnomacro", file);
5459 if (set_noreorder != 0)
5460 fputs ("\n\tnop", file);
5461 else if (TARGET_STATS)
5462 fputs ("\n\t#nop", file);
5467 if (set_noreorder++ == 0)
5468 fputs (".set\tnoreorder\n\t", file);
5472 if (set_noreorder == 0)
5473 error ("internal error: %%) found without a %%( in assembler pattern");
5475 else if (--set_noreorder == 0)
5476 fputs ("\n\t.set\treorder", file);
5481 if (set_noat++ == 0)
5482 fputs (".set\tnoat\n\t", file);
5487 error ("internal error: %%] found without a %%[ in assembler pattern");
5488 else if (--set_noat == 0)
5489 fputs ("\n\t.set\tat", file);
5494 if (set_nomacro++ == 0)
5495 fputs (".set\tnomacro\n\t", file);
5499 if (set_nomacro == 0)
5500 error ("internal error: %%> found without a %%< in assembler pattern");
5501 else if (--set_nomacro == 0)
5502 fputs ("\n\t.set\tmacro", file);
5507 if (set_volatile++ == 0)
5508 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5512 if (set_volatile == 0)
5513 error ("internal error: %%} found without a %%{ in assembler pattern");
5514 else if (--set_volatile == 0)
5515 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5521 if (align_labels_log > 0)
5522 ASM_OUTPUT_ALIGN (file, align_labels_log);
5527 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
5536 error ("PRINT_OPERAND null pointer");
5540 code = GET_CODE (op);
5542 if (code == SIGN_EXTEND)
5543 op = XEXP (op, 0), code = GET_CODE (op);
5548 case EQ: fputs ("eq", file); break;
5549 case NE: fputs ("ne", file); break;
5550 case GT: fputs ("gt", file); break;
5551 case GE: fputs ("ge", file); break;
5552 case LT: fputs ("lt", file); break;
5553 case LE: fputs ("le", file); break;
5554 case GTU: fputs ("gtu", file); break;
5555 case GEU: fputs ("geu", file); break;
5556 case LTU: fputs ("ltu", file); break;
5557 case LEU: fputs ("leu", file); break;
5559 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5562 else if (letter == 'N')
5565 case EQ: fputs ("ne", file); break;
5566 case NE: fputs ("eq", file); break;
5567 case GT: fputs ("le", file); break;
5568 case GE: fputs ("lt", file); break;
5569 case LT: fputs ("ge", file); break;
5570 case LE: fputs ("gt", file); break;
5571 case GTU: fputs ("leu", file); break;
5572 case GEU: fputs ("ltu", file); break;
5573 case LTU: fputs ("geu", file); break;
5574 case LEU: fputs ("gtu", file); break;
5576 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5579 else if (letter == 'F')
5582 case EQ: fputs ("c1f", file); break;
5583 case NE: fputs ("c1t", file); break;
5585 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5588 else if (letter == 'W')
5591 case EQ: fputs ("c1t", file); break;
5592 case NE: fputs ("c1f", file); break;
5594 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5597 else if (letter == 'S')
5601 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5602 assemble_name (file, buffer);
5605 else if (letter == 'Z')
5607 register int regnum;
5612 regnum = REGNO (op);
5613 if (! ST_REG_P (regnum))
5616 if (regnum != ST_REG_FIRST)
5617 fprintf (file, "%s,", reg_names[regnum]);
5620 else if (code == REG || code == SUBREG)
5622 register int regnum;
5625 regnum = REGNO (op);
5627 regnum = true_regnum (op);
5629 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5630 || (letter == 'L' && WORDS_BIG_ENDIAN)
5634 fprintf (file, "%s", reg_names[regnum]);
5637 else if (code == MEM)
5640 output_address (plus_constant (XEXP (op, 0), 4));
5642 output_address (XEXP (op, 0));
5645 else if (code == CONST_DOUBLE
5646 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5651 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5652 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5656 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5657 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5659 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5660 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5662 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5663 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5665 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5666 fputs (reg_names[GP_REG_FIRST], file);
5668 else if (letter == 'd' || letter == 'x' || letter == 'X')
5669 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5671 else if (letter == 'B')
5672 fputs (code == EQ ? "z" : "n", file);
5673 else if (letter == 'b')
5674 fputs (code == EQ ? "n" : "z", file);
5675 else if (letter == 'T')
5676 fputs (code == EQ ? "f" : "t", file);
5677 else if (letter == 't')
5678 fputs (code == EQ ? "t" : "f", file);
5680 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5682 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5683 print_operand (file, XEXP (op, 0), letter);
5686 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5688 fputs ("%gprel(", file);
5689 mips16_output_gp_offset (file, op);
5694 output_addr_const (file, op);
5697 /* A C compound statement to output to stdio stream STREAM the
5698 assembler syntax for an instruction operand that is a memory
5699 reference whose address is ADDR. ADDR is an RTL expression.
5701 On some machines, the syntax for a symbolic address depends on
5702 the section that the address refers to. On these machines,
5703 define the macro `ENCODE_SECTION_INFO' to store the information
5704 into the `symbol_ref', and then check for it here. */
5707 print_operand_address (file, addr)
5712 error ("PRINT_OPERAND_ADDRESS, null pointer");
5715 switch (GET_CODE (addr))
5718 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5719 abort_with_insn (addr, "Arg pointer not eliminated.");
5721 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5726 register rtx arg0 = XEXP (addr, 0);
5727 register rtx arg1 = XEXP (addr, 1);
5729 if (! mips_split_addresses)
5730 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5732 if (GET_CODE (arg0) != REG)
5733 abort_with_insn (addr,
5734 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
5736 fprintf (file, "%%lo(");
5737 print_operand_address (file, arg1);
5738 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5744 register rtx reg = 0;
5745 register rtx offset = 0;
5746 register rtx arg0 = XEXP (addr, 0);
5747 register rtx arg1 = XEXP (addr, 1);
5749 if (GET_CODE (arg0) == REG)
5753 if (GET_CODE (offset) == REG)
5754 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5757 else if (GET_CODE (arg1) == REG)
5758 reg = arg1, offset = arg0;
5759 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5761 output_addr_const (file, addr);
5765 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5767 if (! CONSTANT_P (offset))
5768 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5770 if (REGNO (reg) == ARG_POINTER_REGNUM)
5771 abort_with_insn (addr, "Arg pointer not eliminated.");
5774 && GET_CODE (offset) == CONST
5775 && mips16_gp_offset_p (offset))
5777 fputs ("%gprel(", file);
5778 mips16_output_gp_offset (file, offset);
5782 output_addr_const (file, offset);
5783 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5791 output_addr_const (file, addr);
5795 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5801 /* If optimizing for the global pointer, keep track of all of the externs, so
5802 that at the end of the file, we can emit the appropriate .extern
5803 declaration for them, before writing out the text section. We assume all
5804 names passed to us are in the permanent obstack, so they will be valid at
5805 the end of the compilation.
5807 If we have -G 0, or the extern size is unknown, or the object is in a user
5808 specified section that is not .sbss/.sdata, don't bother emitting the
5809 .externs. In the case of user specified sections this behaviour is
5810 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5813 mips_output_external (file, decl, name)
5814 FILE *file ATTRIBUTE_UNUSED;
5818 register struct extern_list *p;
5823 && TREE_CODE (decl) != FUNCTION_DECL
5824 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5825 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5826 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5827 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5829 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5830 p->next = extern_head;
5836 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5837 if (TREE_CODE (decl) == FUNCTION_DECL
5838 /* ??? Don't include alloca, since gcc will always expand it
5839 inline. If we don't do this, the C++ library fails to build. */
5840 && strcmp (name, "alloca")
5841 /* ??? Don't include __builtin_next_arg, because then gcc will not
5842 bootstrap under Irix 5.1. */
5843 && strcmp (name, "__builtin_next_arg"))
5845 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5846 p->next = extern_head;
5856 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5858 mips_output_external_libcall (file, name)
5862 register struct extern_list *p;
5864 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5865 p->next = extern_head;
5874 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5875 for .file's that start within a function. If we are smuggling stabs, try to
5876 put out a MIPS ECOFF file and a stab. */
5879 mips_output_filename (stream, name)
5883 static int first_time = 1;
5884 char ltext_label_name[100];
5890 current_function_file = name;
5891 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5892 /* This tells mips-tfile that stabs will follow. */
5893 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5894 fprintf (stream, "\t#@stabs\n");
5897 else if (write_symbols == DBX_DEBUG)
5899 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5900 fprintf (stream, "%s", ASM_STABS_OP);
5901 output_quoted_string (stream, name);
5902 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5905 else if (name != current_function_file
5906 && strcmp (name, current_function_file) != 0)
5908 if (inside_function && !TARGET_GAS)
5910 if (!file_in_function_warning)
5912 file_in_function_warning = 1;
5913 ignore_line_number = 1;
5914 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5920 current_function_file = name;
5921 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5926 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5927 as well as a .loc, since it is possible that MIPS ECOFF might not be
5928 able to represent the location for inlines that come from a different
5932 mips_output_lineno (stream, line)
5936 if (write_symbols == DBX_DEBUG)
5939 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5940 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5941 LOCAL_LABEL_PREFIX, sym_lineno);
5945 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5946 (ignore_line_number) ? "#" : "",
5947 num_source_filenames, line);
5949 LABEL_AFTER_LOC (stream);
5953 /* Output an ASCII string, in a space-saving way. */
5956 mips_output_ascii (stream, string_param, len)
5958 const char *string_param;
5963 register const unsigned char *string =
5964 (const unsigned char *)string_param;
5966 fprintf (stream, "\t.ascii\t\"");
5967 for (i = 0; i < len; i++)
5969 register int c = string[i];
5975 putc ('\\', stream);
5980 case TARGET_NEWLINE:
5981 fputs ("\\n", stream);
5983 && (((c = string[i+1]) >= '\040' && c <= '~')
5984 || c == TARGET_TAB))
5985 cur_pos = 32767; /* break right here */
5991 fputs ("\\t", stream);
5996 fputs ("\\f", stream);
6001 fputs ("\\b", stream);
6006 fputs ("\\r", stream);
6011 if (c >= ' ' && c < 0177)
6018 fprintf (stream, "\\%03o", c);
6023 if (cur_pos > 72 && i+1 < len)
6026 fprintf (stream, "\"\n\t.ascii\t\"");
6029 fprintf (stream, "\"\n");
6032 /* If defined, a C statement to be executed just prior to the output of
6033 assembler code for INSN, to modify the extracted operands so they will be
6036 Here the argument OPVEC is the vector containing the operands extracted
6037 from INSN, and NOPERANDS is the number of elements of the vector which
6038 contain meaningful data for this insn. The contents of this vector are
6039 what will be used to convert the insn template into assembler code, so you
6040 can change the assembler output by changing the contents of the vector.
6042 We use it to check if the current insn needs a nop in front of it because
6043 of load delays, and also to update the delay slot statistics. */
6045 /* ??? There is no real need for this function, because it never actually
6046 emits a NOP anymore. */
6049 final_prescan_insn (insn, opvec, noperands)
6051 rtx opvec[] ATTRIBUTE_UNUSED;
6052 int noperands ATTRIBUTE_UNUSED;
6054 if (dslots_number_nops > 0)
6056 rtx pattern = PATTERN (insn);
6057 int length = get_attr_length (insn);
6059 /* Do we need to emit a NOP? */
6061 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
6062 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
6063 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
6064 || (mips_load_reg4 != 0
6065 && reg_mentioned_p (mips_load_reg4, pattern)))
6066 fputs ("\t#nop\n", asm_out_file);
6069 dslots_load_filled++;
6071 while (--dslots_number_nops > 0)
6072 fputs ("\t#nop\n", asm_out_file);
6081 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6082 dslots_jump_total++;
6085 /* Output at beginning of assembler file.
6087 If we are optimizing to use the global pointer, create a temporary file to
6088 hold all of the text stuff, and write it out to the end. This is needed
6089 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6090 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6091 processed, it generates a two instruction sequence. */
6094 mips_asm_file_start (stream)
6097 const char * abi_string = NULL;
6099 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6101 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6102 inside of a .set noreorder section jumps to a label outside of the .set
6103 noreorder section. Revision 2.20 just set nobopt silently rather than
6106 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6107 fprintf (stream, "\t.set\tnobopt\n");
6109 #ifdef OBJECT_FORMAT_ELF
6110 /* Generate a special section to describe the ABI switches used to produce
6111 the resultant binary. This used to be done by the assembler setting bits
6112 in the ELF header's flags field, but we have run out of bits. GDB needs
6113 this information in order to be able to correctly debug these binaries.
6114 See the function mips_gdbarch_init() in gdb/mips-tdep.c. */
6117 case ABI_32: abi_string = "abi32"; break;
6118 case ABI_N32: abi_string = "abiN32"; break;
6119 case ABI_64: abi_string = "abi64"; break;
6120 case ABI_O64: abi_string = "abiO64"; break;
6121 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6122 case ABI_MEABI:abi_string = TARGET_64BIT ? "meabi64" : "meabi32"; break;
6126 /* Note - we use fprintf directly rather than called named_section()
6127 because in this way we can avoid creating an allocated section. We
6128 do not want this section to take up any space in the running
6130 fprintf (stream, "\t.section .mdebug.%s\n", abi_string);
6132 /* Restore the default section. */
6133 fprintf (stream, "\t.previous\n");
6138 /* Generate the pseudo ops that System V.4 wants. */
6139 #ifndef ABICALLS_ASM_OP
6140 #define ABICALLS_ASM_OP "\t.abicalls"
6142 if (TARGET_ABICALLS)
6143 /* ??? but do not want this (or want pic0) if -non-shared? */
6144 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
6147 fprintf (stream, "\t.set\tmips16\n");
6149 /* This code exists so that we can put all externs before all symbol
6150 references. This is necessary for the MIPS assembler's global pointer
6151 optimizations to work. */
6152 if (TARGET_FILE_SWITCHING)
6154 asm_out_data_file = stream;
6155 asm_out_text_file = tmpfile ();
6158 asm_out_data_file = asm_out_text_file = stream;
6160 if (flag_verbose_asm)
6161 fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6163 mips_section_threshold, mips_arch_string, mips_isa);
6166 /* If we are optimizing the global pointer, emit the text section now and any
6167 small externs which did not have .comm, etc that are needed. Also, give a
6168 warning if the data area is more than 32K and -pic because 3 instructions
6169 are needed to reference the data pointers. */
6172 mips_asm_file_end (file)
6176 struct extern_list *p;
6180 HALF_PIC_FINISH (file);
6187 for (p = extern_head; p != 0; p = p->next)
6189 name_tree = get_identifier (p->name);
6191 /* Positively ensure only one .extern for any given symbol. */
6192 if (! TREE_ASM_WRITTEN (name_tree))
6194 TREE_ASM_WRITTEN (name_tree) = 1;
6195 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6197 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6201 fputs ("\t.extern\t", file);
6202 assemble_name (file, p->name);
6203 fprintf (file, ", %d\n", p->size);
6209 if (TARGET_FILE_SWITCHING)
6211 fprintf (file, "\n\t.text\n");
6212 copy_file_data (file, asm_out_text_file);
6217 copy_file_data (to, from)
6224 fatal_io_error ("can't rewind temp file");
6226 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
6227 if (fwrite (buffer, 1, len, to) != len)
6228 fatal_io_error ("can't write to output file");
6231 fatal_io_error ("can't read from temp file");
6234 fatal_io_error ("can't close temp file");
6237 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6238 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6241 mips_declare_object (stream, name, init_string, final_string, size)
6244 const char *init_string;
6245 const char *final_string;
6248 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6249 assemble_name (stream, name);
6250 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6254 tree name_tree = get_identifier (name);
6255 TREE_ASM_WRITTEN (name_tree) = 1;
6259 /* Output a double precision value to the assembler. If both the
6260 host and target are IEEE, emit the values in hex. */
6263 mips_output_double (stream, value)
6265 REAL_VALUE_TYPE value;
6267 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
6269 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
6271 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
6272 value_long[0], value, value_long[1]);
6274 fprintf (stream, "\t.double\t%.20g\n", value);
6278 /* Output a single precision value to the assembler. If both the
6279 host and target are IEEE, emit the values in hex. */
6282 mips_output_float (stream, value)
6284 REAL_VALUE_TYPE value;
6286 #ifdef REAL_VALUE_TO_TARGET_SINGLE
6288 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
6290 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
6292 fprintf (stream, "\t.float\t%.12g\n", value);
6296 /* Return the bytes needed to compute the frame pointer from the current
6299 Mips stack frames look like:
6301 Before call After call
6302 +-----------------------+ +-----------------------+
6305 | caller's temps. | | caller's temps. |
6307 +-----------------------+ +-----------------------+
6309 | arguments on stack. | | arguments on stack. |
6311 +-----------------------+ +-----------------------+
6312 | 4 words to save | | 4 words to save |
6313 | arguments passed | | arguments passed |
6314 | in registers, even | | in registers, even |
6315 SP->| if not passed. | VFP->| if not passed. |
6316 +-----------------------+ +-----------------------+
6318 | fp register save |
6320 +-----------------------+
6322 | gp register save |
6324 +-----------------------+
6328 +-----------------------+
6330 | alloca allocations |
6332 +-----------------------+
6334 | GP save for V.4 abi |
6336 +-----------------------+
6338 | arguments on stack |
6340 +-----------------------+
6342 | arguments passed |
6343 | in registers, even |
6344 low SP->| if not passed. |
6345 memory +-----------------------+
6350 compute_frame_size (size)
6351 HOST_WIDE_INT size; /* # of var. bytes allocated */
6354 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6355 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6356 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6357 HOST_WIDE_INT extra_size; /* # extra bytes */
6358 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6359 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6360 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6361 long mask; /* mask of saved gp registers */
6362 long fmask; /* mask of saved fp registers */
6363 int fp_inc; /* 1 or 2 depending on the size of fp regs */
6364 long fp_bits; /* bitmask to use for each fp register */
6370 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6371 var_size = MIPS_STACK_ALIGN (size);
6372 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6374 /* The MIPS 3.0 linker does not like functions that dynamically
6375 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6376 looks like we are trying to create a second frame pointer to the
6377 function, so allocate some stack space to make it happy. */
6379 if (args_size == 0 && current_function_calls_alloca)
6380 args_size = 4 * UNITS_PER_WORD;
6382 total_size = var_size + args_size + extra_size;
6384 /* Calculate space needed for gp registers. */
6385 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6387 /* $18 is a special case on the mips16. It may be used to call
6388 a function which returns a floating point value, but it is
6389 marked in call_used_regs. $31 is also a special case. When
6390 not using -mentry, it will be used to copy a return value
6391 into the floating point registers if the return value is
6393 if (MUST_SAVE_REGISTER (regno)
6395 && regno == GP_REG_FIRST + 18
6396 && regs_ever_live[regno])
6398 && regno == GP_REG_FIRST + 31
6399 && mips16_hard_float
6401 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6402 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6404 && (! TARGET_SINGLE_FLOAT
6405 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6408 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6409 mask |= 1L << (regno - GP_REG_FIRST);
6411 /* The entry and exit pseudo instructions can not save $17
6412 without also saving $16. */
6414 && regno == GP_REG_FIRST + 17
6415 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6417 gp_reg_size += UNITS_PER_WORD;
6423 /* We need to restore these for the handler. */
6424 if (current_function_calls_eh_return)
6429 regno = EH_RETURN_DATA_REGNO (i);
6430 if (regno == INVALID_REGNUM)
6432 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6433 mask |= 1L << (regno - GP_REG_FIRST);
6437 /* Calculate space needed for fp registers. */
6438 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
6449 /* This loop must iterate over the same space as its companion in
6450 save_restore_regs. */
6451 for (regno = (FP_REG_LAST - fp_inc + 1);
6452 regno >= FP_REG_FIRST;
6455 if (regs_ever_live[regno] && !call_used_regs[regno])
6457 fp_reg_size += fp_inc * UNITS_PER_FPREG;
6458 fmask |= fp_bits << (regno - FP_REG_FIRST);
6462 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6463 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6465 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6466 for leaf routines (total_size == extra_size) to save the gp reg.
6467 The gp reg is callee saved in the 64 bit ABI, so all routines must
6468 save the gp reg. This is not a leaf routine if -p, because of the
6470 if (total_size == extra_size
6471 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6473 total_size = extra_size = 0;
6474 else if (TARGET_ABICALLS)
6476 /* Add the context-pointer to the saved registers. */
6477 gp_reg_size += UNITS_PER_WORD;
6478 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6479 total_size -= gp_reg_rounded;
6480 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6481 total_size += gp_reg_rounded;
6484 /* Add in space reserved on the stack by the callee for storing arguments
6485 passed in registers. */
6486 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6487 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6489 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6490 if (mips_entry && total_size > 0 && total_size < 32)
6493 /* Save other computed information. */
6494 current_frame_info.total_size = total_size;
6495 current_frame_info.var_size = var_size;
6496 current_frame_info.args_size = args_size;
6497 current_frame_info.extra_size = extra_size;
6498 current_frame_info.gp_reg_size = gp_reg_size;
6499 current_frame_info.fp_reg_size = fp_reg_size;
6500 current_frame_info.mask = mask;
6501 current_frame_info.fmask = fmask;
6502 current_frame_info.initialized = reload_completed;
6503 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6504 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
6508 unsigned long offset;
6510 /* When using mips_entry, the registers are always saved at the
6511 top of the stack. */
6513 offset = (args_size + extra_size + var_size
6514 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6516 offset = total_size - GET_MODE_SIZE (gpr_mode);
6518 current_frame_info.gp_sp_offset = offset;
6519 current_frame_info.gp_save_offset = offset - total_size;
6523 current_frame_info.gp_sp_offset = 0;
6524 current_frame_info.gp_save_offset = 0;
6529 unsigned long offset = (args_size + extra_size + var_size
6530 + gp_reg_rounded + fp_reg_size
6531 - fp_inc * UNITS_PER_FPREG);
6532 current_frame_info.fp_sp_offset = offset;
6533 current_frame_info.fp_save_offset = offset - total_size;
6537 current_frame_info.fp_sp_offset = 0;
6538 current_frame_info.fp_save_offset = 0;
6541 /* Ok, we're done. */
6545 /* Common code to emit the insns (or to write the instructions to a file)
6546 to save/restore registers.
6548 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6549 is not modified within save_restore_insns. */
6551 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6553 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6554 and return an rtl expression for the register. Write the assembly
6555 instructions directly to FILE if it is not null, otherwise emit them as
6558 This function is a subroutine of save_restore_insns. It is used when
6559 OFFSET is too large to add in a single instruction. */
6562 mips_add_large_offset_to_sp (offset, file)
6563 HOST_WIDE_INT offset;
6566 rtx reg = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6569 rtx offset_rtx = GEN_INT (offset);
6571 emit_move_insn (reg, offset_rtx);
6572 if (Pmode == DImode)
6573 emit_insn (gen_adddi3 (reg, reg, stack_pointer_rtx));
6575 emit_insn (gen_addsi3 (reg, reg, stack_pointer_rtx));
6579 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6580 reg_names[MIPS_TEMP2_REGNUM], (long) offset);
6581 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
6582 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6583 Pmode == DImode ? "daddu" : "addu",
6584 reg_names[MIPS_TEMP2_REGNUM],
6585 reg_names[MIPS_TEMP2_REGNUM],
6586 reg_names[STACK_POINTER_REGNUM]);
6591 /* Make INSN frame related and note that it performs the frame-related
6592 operation DWARF_PATTERN. */
6595 mips_annotate_frame_insn (insn, dwarf_pattern)
6596 rtx insn, dwarf_pattern;
6598 RTX_FRAME_RELATED_P (insn) = 1;
6599 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6604 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6605 The expression should only be used to store single registers. */
6608 mips_frame_set (mode, regno, offset)
6609 enum machine_mode mode;
6613 rtx address = plus_constant (stack_pointer_rtx, offset);
6614 rtx set = gen_rtx_SET (mode,
6615 gen_rtx_MEM (mode, address),
6616 gen_rtx_REG (mode, regno));
6617 RTX_FRAME_RELATED_P (set) = 1;
6622 /* Emit a move instruction that stores REG in MEM. Make the instruction
6623 frame related and note that it stores REG at (SP + OFFSET). This
6624 function may be asked to store an FPR pair. */
6627 mips_emit_frame_related_store (mem, reg, offset)
6630 HOST_WIDE_INT offset;
6634 if (GET_MODE (reg) == DFmode && ! TARGET_FLOAT64)
6636 /* Two registers are being stored, so the frame-related expression
6637 must be a PARALLEL rtx with one SET for each register. The
6638 higher numbered register is stored in the lower address on
6639 big-endian targets. */
6640 int regno1 = TARGET_BIG_ENDIAN ? REGNO (reg) + 1 : REGNO (reg);
6641 int regno2 = TARGET_BIG_ENDIAN ? REGNO (reg) : REGNO (reg) + 1;
6642 rtx set1 = mips_frame_set (SFmode, regno1, offset);
6643 rtx set2 = mips_frame_set (SFmode, regno2, offset + UNITS_PER_FPREG);
6644 dwarf_expr = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2));
6647 dwarf_expr = mips_frame_set (GET_MODE (reg), REGNO (reg), offset);
6649 mips_annotate_frame_insn (emit_move_insn (mem, reg), dwarf_expr);
6653 save_restore_insns (store_p, large_reg, large_offset, file)
6654 int store_p; /* true if this is prologue */
6655 rtx large_reg; /* register holding large offset constant or NULL */
6656 long large_offset; /* large constant offset value */
6657 FILE *file; /* file to write instructions instead of making RTL */
6659 long mask = current_frame_info.mask;
6660 long fmask = current_frame_info.fmask;
6663 HOST_WIDE_INT base_offset;
6664 HOST_WIDE_INT gp_offset;
6665 HOST_WIDE_INT fp_offset;
6666 HOST_WIDE_INT end_offset;
6669 if (frame_pointer_needed
6670 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6673 if (mask == 0 && fmask == 0)
6676 /* Save registers starting from high to low. The debuggers prefer at least
6677 the return register be stored at func+4, and also it allows us not to
6678 need a nop in the epilog if at least one register is reloaded in
6679 addition to return address. */
6681 /* Save GP registers if needed. */
6684 /* Pick which pointer to use as a base register. For small frames, just
6685 use the stack pointer. Otherwise, use a temporary register. Save 2
6686 cycles if the save area is near the end of a large frame, by reusing
6687 the constant created in the prologue/epilogue to adjust the stack
6690 gp_offset = current_frame_info.gp_sp_offset;
6692 = gp_offset - (current_frame_info.gp_reg_size
6693 - GET_MODE_SIZE (gpr_mode));
6695 if (gp_offset < 0 || end_offset < 0)
6697 ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6698 (long) gp_offset, (long) end_offset);
6700 /* If we see a large frame in mips16 mode, we save the registers
6701 before adjusting the stack pointer, and load them afterward. */
6702 else if (TARGET_MIPS16 && large_offset > 32767)
6703 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6705 else if (gp_offset < 32768)
6706 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6708 else if (large_reg != 0
6709 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6710 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6712 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6713 base_offset = large_offset;
6716 if (Pmode == DImode)
6717 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6718 stack_pointer_rtx));
6720 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6721 stack_pointer_rtx));
6724 fprintf (file, "\t%s\t%s,%s,%s\n",
6725 Pmode == DImode ? "daddu" : "addu",
6726 reg_names[MIPS_TEMP2_REGNUM],
6727 reg_names[REGNO (large_reg)],
6728 reg_names[STACK_POINTER_REGNUM]);
6732 base_offset = gp_offset;
6733 base_reg_rtx = mips_add_large_offset_to_sp (base_offset, file);
6736 /* When we restore the registers in MIPS16 mode, then if we are
6737 using a frame pointer, and this is not a large frame, the
6738 current stack pointer will be offset by
6739 current_function_outgoing_args_size. Doing it this way lets
6740 us avoid offsetting the frame pointer before copying it into
6741 the stack pointer; there is no instruction to set the stack
6742 pointer to the sum of a register and a constant. */
6745 && frame_pointer_needed
6746 && large_offset <= 32767)
6747 base_offset += current_function_outgoing_args_size;
6749 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6750 if (BITSET_P (mask, regno - GP_REG_FIRST))
6756 = gen_rtx (MEM, gpr_mode,
6757 gen_rtx (PLUS, Pmode, base_reg_rtx,
6758 GEN_INT (gp_offset - base_offset)));
6760 if (! current_function_calls_eh_return)
6761 RTX_UNCHANGING_P (mem_rtx) = 1;
6763 /* The mips16 does not have an instruction to load
6764 $31, so we load $7 instead, and work things out
6766 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6767 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6768 /* The mips16 sometimes needs to save $18. */
6769 else if (TARGET_MIPS16
6770 && regno != GP_REG_FIRST + 31
6771 && ! M16_REG_P (regno))
6774 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6777 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6778 emit_move_insn (reg_rtx,
6779 gen_rtx (REG, gpr_mode, regno));
6783 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6786 mips_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
6787 else if (!TARGET_ABICALLS
6788 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6789 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6791 emit_move_insn (reg_rtx, mem_rtx);
6793 && regno != GP_REG_FIRST + 31
6794 && ! M16_REG_P (regno))
6795 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6801 if (store_p || !TARGET_ABICALLS
6802 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6803 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6807 /* The mips16 does not have an instruction to
6808 load $31, so we load $7 instead, and work
6809 things out in the caller. */
6810 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6811 r = GP_REG_FIRST + 7;
6812 /* The mips16 sometimes needs to save $18. */
6814 && regno != GP_REG_FIRST + 31
6815 && ! M16_REG_P (regno))
6818 r = GP_REG_FIRST + 6;
6821 r = GP_REG_FIRST + 3;
6822 fprintf (file, "\tmove\t%s,%s\n",
6823 reg_names[r], reg_names[regno]);
6826 fprintf (file, "\t%s\t%s,",
6828 ? (store_p) ? "sd" : "ld"
6829 : (store_p) ? "sw" : "lw"),
6831 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6832 gp_offset - base_offset);
6833 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6836 && regno != GP_REG_FIRST + 31
6837 && ! M16_REG_P (regno))
6838 fprintf (file, "\tmove\t%s,%s\n",
6839 reg_names[regno], reg_names[r]);
6843 gp_offset -= GET_MODE_SIZE (gpr_mode);
6847 base_reg_rtx = 0, base_offset = 0;
6849 /* Save floating point registers if needed. */
6852 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
6853 int fp_size = fp_inc * UNITS_PER_FPREG;
6855 /* Pick which pointer to use as a base register. */
6856 fp_offset = current_frame_info.fp_sp_offset;
6857 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
6859 if (fp_offset < 0 || end_offset < 0)
6861 ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6862 (long) fp_offset, (long) end_offset);
6864 else if (fp_offset < 32768)
6865 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6867 else if (base_reg_rtx != 0
6868 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6869 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6870 ; /* already set up for gp registers above */
6872 else if (large_reg != 0
6873 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6874 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6876 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6877 base_offset = large_offset;
6880 if (Pmode == DImode)
6881 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6882 stack_pointer_rtx));
6884 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6885 stack_pointer_rtx));
6889 fprintf (file, "\t%s\t%s,%s,%s\n",
6890 Pmode == DImode ? "daddu" : "addu",
6891 reg_names[MIPS_TEMP2_REGNUM],
6892 reg_names[REGNO (large_reg)],
6893 reg_names[STACK_POINTER_REGNUM]);
6897 base_offset = fp_offset;
6898 base_reg_rtx = mips_add_large_offset_to_sp (fp_offset, file);
6901 /* This loop must iterate over the same space as its companion in
6902 compute_frame_size. */
6903 for (regno = (FP_REG_LAST - fp_inc + 1);
6904 regno >= FP_REG_FIRST;
6906 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6910 enum machine_mode sz
6911 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6912 rtx reg_rtx = gen_rtx (REG, sz, regno);
6913 rtx mem_rtx = gen_rtx (MEM, sz,
6914 gen_rtx (PLUS, Pmode, base_reg_rtx,
6917 if (! current_function_calls_eh_return)
6918 RTX_UNCHANGING_P (mem_rtx) = 1;
6921 mips_emit_frame_related_store (mem_rtx, reg_rtx, fp_offset);
6923 emit_move_insn (reg_rtx, mem_rtx);
6927 fprintf (file, "\t%s\t%s,",
6928 (TARGET_SINGLE_FLOAT
6929 ? (store_p ? "s.s" : "l.s")
6930 : (store_p ? "s.d" : "l.d")),
6932 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6933 fp_offset - base_offset);
6934 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6937 fp_offset -= fp_size;
6942 /* Set up the stack and frame (if desired) for the function. */
6945 mips_output_function_prologue (file, size)
6947 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6949 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6952 long tsize = current_frame_info.total_size;
6954 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6956 #ifdef SDB_DEBUGGING_INFO
6957 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6958 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6961 /* In mips16 mode, we may need to generate a 32 bit to handle
6962 floating point arguments. The linker will arrange for any 32 bit
6963 functions to call this stub, which will then jump to the 16 bit
6965 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6966 && current_function_args_info.fp_code != 0)
6967 build_mips16_function_stub (file);
6969 inside_function = 1;
6971 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6972 /* Get the function name the same way that toplev.c does before calling
6973 assemble_start_function. This is needed so that the name used here
6974 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6975 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6977 if (!flag_inhibit_size_directive)
6979 fputs ("\t.ent\t", file);
6980 assemble_name (file, fnname);
6984 assemble_name (file, fnname);
6985 fputs (":\n", file);
6988 if (!flag_inhibit_size_directive)
6990 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6992 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6993 (reg_names[(frame_pointer_needed)
6994 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6995 ((frame_pointer_needed && TARGET_MIPS16)
6996 ? (tsize - current_function_outgoing_args_size)
6998 reg_names[31 + GP_REG_FIRST],
6999 current_frame_info.var_size,
7000 current_frame_info.num_gp,
7001 current_frame_info.num_fp,
7002 current_function_outgoing_args_size,
7003 current_frame_info.extra_size);
7005 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7006 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7007 current_frame_info.mask,
7008 current_frame_info.gp_save_offset,
7009 current_frame_info.fmask,
7010 current_frame_info.fp_save_offset);
7013 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7014 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7017 if (mips_entry && ! mips_can_use_return_insn ())
7019 int save16 = BITSET_P (current_frame_info.mask, 16);
7020 int save17 = BITSET_P (current_frame_info.mask, 17);
7021 int save31 = BITSET_P (current_frame_info.mask, 31);
7025 /* Look through the initial insns to see if any of them store
7026 the function parameters into the incoming parameter storage
7027 area. If they do, we delete the insn, and save the register
7028 using the entry pseudo-instruction instead. We don't try to
7029 look past a label, jump, or call. */
7030 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
7032 rtx note, set, src, dest, base, offset;
7035 if (GET_CODE (insn) == CODE_LABEL
7036 || GET_CODE (insn) == JUMP_INSN
7037 || GET_CODE (insn) == CALL_INSN)
7039 if (GET_CODE (insn) != INSN)
7041 set = PATTERN (insn);
7042 if (GET_CODE (set) != SET)
7045 /* An insn storing a function parameter will still have a
7046 REG_EQUIV note on it mentioning the argument pointer. */
7047 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
7048 if (note == NULL_RTX)
7050 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
7053 src = SET_SRC (set);
7054 if (GET_CODE (src) != REG
7055 || REGNO (src) < GP_REG_FIRST + 4
7056 || REGNO (src) > GP_REG_FIRST + 7)
7059 dest = SET_DEST (set);
7060 if (GET_CODE (dest) != MEM)
7062 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
7064 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
7065 && REGNO (src) < GP_REG_FIRST + 7)
7069 offset = const0_rtx;
7070 base = eliminate_constant_term (XEXP (dest, 0), &offset);
7071 if (GET_CODE (base) != REG
7072 || GET_CODE (offset) != CONST_INT)
7074 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
7075 && (unsigned HOST_WIDE_INT) INTVAL (offset)
7076 == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
7078 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
7079 && ((unsigned HOST_WIDE_INT) INTVAL (offset)
7081 + (REGNO (src) - 4) * UNITS_PER_WORD
7082 - current_function_outgoing_args_size)))
7087 /* This insn stores a parameter onto the stack, in the same
7088 location where the entry pseudo-instruction will put it.
7089 Delete the insn, and arrange to tell the entry
7090 instruction to save the register. */
7091 PUT_CODE (insn, NOTE);
7092 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7093 NOTE_SOURCE_FILE (insn) = 0;
7095 hireg = (REGNO (src)
7096 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
7098 if (hireg > savearg)
7102 /* If this is a varargs function, we need to save all the
7103 registers onto the stack anyhow. */
7104 if (current_function_stdarg || current_function_varargs)
7105 savearg = GP_REG_FIRST + 7;
7107 fprintf (file, "\tentry\t");
7110 if (savearg == GP_REG_FIRST + 4)
7111 fprintf (file, "%s", reg_names[savearg]);
7113 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
7114 reg_names[savearg]);
7116 if (save16 || save17)
7119 fprintf (file, ",");
7120 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
7122 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
7126 if (savearg > 0 || save16 || save17)
7127 fprintf (file, ",");
7128 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
7130 fprintf (file, "\n");
7133 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
7135 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7137 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7138 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7141 fprintf (file, "\t%s\t%s,%s,%ld\n",
7142 (Pmode == DImode ? "dsubu" : "subu"),
7143 sp_str, sp_str, tsize);
7144 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
7147 if (dwarf2out_do_frame ())
7148 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
7152 /* Expand the prologue into a bunch of separate insns. */
7155 mips_expand_prologue ()
7158 HOST_WIDE_INT tsize;
7160 int last_arg_is_vararg_marker = 0;
7161 tree fndecl = current_function_decl;
7162 tree fntype = TREE_TYPE (fndecl);
7163 tree fnargs = DECL_ARGUMENTS (fndecl);
7168 CUMULATIVE_ARGS args_so_far;
7169 rtx reg_18_save = NULL_RTX;
7170 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7171 && (! mips_entry || mips_can_use_return_insn ());
7173 /* If struct value address is treated as the first argument, make it so. */
7174 if (aggregate_value_p (DECL_RESULT (fndecl))
7175 && ! current_function_returns_pcc_struct
7176 && struct_value_incoming_rtx == 0)
7178 tree type = build_pointer_type (fntype);
7179 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7181 DECL_ARG_TYPE (function_result_decl) = type;
7182 TREE_CHAIN (function_result_decl) = fnargs;
7183 fnargs = function_result_decl;
7186 /* For arguments passed in registers, find the register number
7187 of the first argument in the variable part of the argument list,
7188 otherwise GP_ARG_LAST+1. Note also if the last argument is
7189 the varargs special argument, and treat it as part of the
7192 This is only needed if store_args_on_stack is true. */
7194 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7195 regno = GP_ARG_FIRST;
7197 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7199 tree passed_type = DECL_ARG_TYPE (cur_arg);
7200 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7203 if (TREE_ADDRESSABLE (passed_type))
7205 passed_type = build_pointer_type (passed_type);
7206 passed_mode = Pmode;
7209 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7211 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7212 next_arg = TREE_CHAIN (cur_arg);
7214 if (entry_parm && store_args_on_stack)
7217 && DECL_NAME (cur_arg)
7218 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7219 "__builtin_va_alist"))
7220 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7223 last_arg_is_vararg_marker = 1;
7230 if (GET_CODE (entry_parm) != REG)
7233 /* passed in a register, so will get homed automatically */
7234 if (GET_MODE (entry_parm) == BLKmode)
7235 words = (int_size_in_bytes (passed_type) + 3) / 4;
7237 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
7239 regno = REGNO (entry_parm) + words - 1;
7244 regno = GP_ARG_LAST+1;
7249 /* In order to pass small structures by value in registers compatibly with
7250 the MIPS compiler, we need to shift the value into the high part of the
7251 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7252 adjustments to be made as the next_arg_reg variable, so we split up the
7253 insns, and emit them separately. */
7255 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7256 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7258 rtvec adjust = XVEC (next_arg_reg, 0);
7259 int num = GET_NUM_ELEM (adjust);
7261 for (i = 0; i < num; i++)
7265 pattern = RTVEC_ELT (adjust, i);
7266 if (GET_CODE (pattern) != SET
7267 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7268 abort_with_insn (pattern, "Insn is not a shift");
7269 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7271 insn = emit_insn (pattern);
7273 /* Global life information isn't valid at this point, so we
7274 can't check whether these shifts are actually used. Mark
7275 them MAYBE_DEAD so that flow2 will remove them, and not
7276 complain about dead code in the prologue. */
7277 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7282 tsize = compute_frame_size (get_frame_size ());
7284 /* If this function is a varargs function, store any registers that
7285 would normally hold arguments ($4 - $7) on the stack. */
7286 if (store_args_on_stack
7287 && ((TYPE_ARG_TYPES (fntype) != 0
7288 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7290 || last_arg_is_vararg_marker))
7292 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7293 rtx ptr = stack_pointer_rtx;
7295 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7296 if (TARGET_ABICALLS)
7299 for (; regno <= GP_ARG_LAST; regno++)
7302 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7303 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7304 gen_rtx (REG, gpr_mode, regno));
7306 offset += GET_MODE_SIZE (gpr_mode);
7310 /* If we are using the entry pseudo instruction, it will
7311 automatically subtract 32 from the stack pointer, so we don't
7312 need to. The entry pseudo instruction is emitted by
7313 function_prologue. */
7314 if (mips_entry && ! mips_can_use_return_insn ())
7316 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7320 /* If we are using a frame pointer with a small stack frame,
7321 we need to initialize it here since it won't be done
7323 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7325 rtx incr = GEN_INT (current_function_outgoing_args_size);
7326 if (Pmode == DImode)
7327 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7331 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7335 else if (Pmode == DImode)
7336 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7337 stack_pointer_rtx));
7339 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7340 stack_pointer_rtx));
7342 RTX_FRAME_RELATED_P (insn) = 1;
7345 /* We may need to save $18, if it is used to call a function
7346 which may return a floating point value. Set up a sequence
7347 of instructions to do so. Later on we emit them at the right
7349 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
7351 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7352 long gp_offset, base_offset;
7354 gp_offset = current_frame_info.gp_sp_offset;
7355 if (BITSET_P (current_frame_info.mask, 16))
7356 gp_offset -= UNITS_PER_WORD;
7357 if (BITSET_P (current_frame_info.mask, 17))
7358 gp_offset -= UNITS_PER_WORD;
7359 if (BITSET_P (current_frame_info.mask, 31))
7360 gp_offset -= UNITS_PER_WORD;
7362 base_offset = tsize;
7366 emit_move_insn (reg_rtx,
7367 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7368 emit_move_insn (gen_rtx (MEM, gpr_mode,
7369 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7373 reg_18_save = gen_sequence ();
7382 if (reg_18_save != NULL_RTX)
7383 emit_insn (reg_18_save);
7389 rtx tsize_rtx = GEN_INT (tsize);
7391 /* If we are doing svr4-abi, sp move is done by
7392 function_prologue. In mips16 mode with a large frame, we
7393 save the registers before adjusting the stack. */
7394 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7395 && (!TARGET_MIPS16 || tsize <= 32767))
7397 rtx adjustment_rtx, insn, dwarf_pattern;
7401 adjustment_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7402 emit_move_insn (adjustment_rtx, tsize_rtx);
7405 adjustment_rtx = tsize_rtx;
7407 if (Pmode == DImode)
7408 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7411 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7414 dwarf_pattern = gen_rtx_SET (Pmode, stack_pointer_rtx,
7415 plus_constant (stack_pointer_rtx,
7418 mips_annotate_frame_insn (insn, dwarf_pattern);
7422 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
7423 else if (reg_18_save != NULL_RTX)
7424 emit_insn (reg_18_save);
7426 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7432 if (!frame_pointer_needed)
7435 reg_rtx = gen_rtx (REG, Pmode, 3);
7436 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7437 emit_move_insn (reg_rtx, tsize_rtx);
7438 if (Pmode == DImode)
7439 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7440 hard_frame_pointer_rtx,
7443 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7444 hard_frame_pointer_rtx,
7446 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7449 if (frame_pointer_needed)
7453 /* On the mips16, we encourage the use of unextended
7454 instructions when using the frame pointer by pointing the
7455 frame pointer ahead of the argument space allocated on
7457 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7461 /* In this case, we have already copied the stack
7462 pointer into the frame pointer, above. We need only
7463 adjust for the outgoing argument size. */
7464 if (current_function_outgoing_args_size != 0)
7466 rtx incr = GEN_INT (current_function_outgoing_args_size);
7467 if (Pmode == DImode)
7468 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7469 hard_frame_pointer_rtx,
7472 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7473 hard_frame_pointer_rtx,
7477 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7479 rtx incr = GEN_INT (current_function_outgoing_args_size);
7480 if (Pmode == DImode)
7481 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7485 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7489 else if (Pmode == DImode)
7490 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7491 stack_pointer_rtx));
7493 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7494 stack_pointer_rtx));
7497 RTX_FRAME_RELATED_P (insn) = 1;
7500 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7501 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7502 gen_rtx_REG (DImode, 25)));
7505 /* If we are profiling, make sure no instructions are scheduled before
7506 the call to mcount. */
7508 if (profile_flag || profile_block_flag)
7509 emit_insn (gen_blockage ());
7512 /* Do any necessary cleanup after a function to restore stack, frame,
7515 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7516 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7519 mips_output_function_epilogue (file, size)
7520 FILE *file ATTRIBUTE_UNUSED;
7521 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7523 const char *fnname = ""; /* FIXME: Correct initialisation? */
7525 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7526 /* Get the function name the same way that toplev.c does before calling
7527 assemble_start_function. This is needed so that the name used here
7528 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7529 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7531 if (!flag_inhibit_size_directive)
7533 fputs ("\t.end\t", file);
7534 assemble_name (file, fnname);
7541 int num_gp_regs = current_frame_info.gp_reg_size / 4;
7542 int num_fp_regs = current_frame_info.fp_reg_size / 8;
7543 int num_regs = num_gp_regs + num_fp_regs;
7544 const char *name = fnname;
7549 dslots_load_total += num_regs;
7552 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7553 name, frame_pointer_needed ? 'y' : 'n',
7554 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7555 current_function_calls_alloca ? 'y' : 'n',
7556 current_function_calls_setjmp ? 'y' : 'n',
7557 current_frame_info.total_size,
7558 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7559 dslots_load_total, dslots_load_filled,
7560 dslots_jump_total, dslots_jump_filled,
7561 num_refs[0], num_refs[1], num_refs[2]);
7563 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7566 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7567 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7570 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7573 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7574 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7577 fputc ('\n', stderr);
7580 /* Reset state info for each function. */
7581 inside_function = 0;
7582 ignore_line_number = 0;
7583 dslots_load_total = 0;
7584 dslots_jump_total = 0;
7585 dslots_load_filled = 0;
7586 dslots_jump_filled = 0;
7592 current_frame_info = zero_frame_info;
7594 while (string_constants != NULL)
7596 struct string_constant *next;
7598 next = string_constants->next;
7599 free (string_constants);
7600 string_constants = next;
7603 /* Restore the output file if optimizing the GP (optimizing the GP causes
7604 the text to be diverted to a tempfile, so that data decls come before
7605 references to the data). */
7606 if (TARGET_FILE_SWITCHING)
7608 asm_out_file = asm_out_data_file;
7613 /* Expand the epilogue into a bunch of separate insns. */
7616 mips_expand_epilogue ()
7618 HOST_WIDE_INT tsize = current_frame_info.total_size;
7619 rtx tsize_rtx = GEN_INT (tsize);
7620 rtx tmp_rtx = (rtx)0;
7622 if (mips_can_use_return_insn ())
7624 emit_insn (gen_return ());
7628 if (mips_entry && ! mips_can_use_return_insn ())
7631 if (tsize > 32767 && ! TARGET_MIPS16)
7633 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7634 emit_move_insn (tmp_rtx, tsize_rtx);
7635 tsize_rtx = tmp_rtx;
7640 long orig_tsize = tsize;
7642 if (frame_pointer_needed)
7644 emit_insn (gen_blockage ());
7646 /* On the mips16, the frame pointer is offset from the stack
7647 pointer by current_function_outgoing_args_size. We
7648 account for that by changing tsize. Note that this can
7649 actually make tsize negative. */
7652 tsize -= current_function_outgoing_args_size;
7654 /* If we have a large frame, it's easier to add to $17
7655 than to $sp, since the mips16 has no instruction to
7656 add a register to $sp. */
7657 if (orig_tsize > 32767)
7659 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7661 emit_move_insn (g6_rtx, GEN_INT (tsize));
7662 if (Pmode == DImode)
7663 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7664 hard_frame_pointer_rtx,
7667 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7668 hard_frame_pointer_rtx,
7673 if (tsize && tsize != orig_tsize)
7674 tsize_rtx = GEN_INT (tsize);
7677 if (Pmode == DImode)
7678 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7680 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7683 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7684 are going to restore it, then we must emit a blockage insn to
7685 prevent the scheduler from moving the restore out of the epilogue. */
7686 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7687 && (current_frame_info.mask
7688 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7689 emit_insn (gen_blockage ());
7691 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
7693 /* In mips16 mode with a large frame, we adjust the stack
7694 pointer before restoring the registers. In this case, we
7695 should always be using a frame pointer, so everything should
7696 have been handled above. */
7697 if (tsize > 32767 && TARGET_MIPS16)
7700 if (current_function_calls_eh_return)
7702 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
7703 if (Pmode == DImode)
7704 emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
7706 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
7710 emit_insn (gen_blockage ());
7712 if (tsize != 0 || current_function_calls_eh_return)
7714 if (Pmode == DImode)
7715 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7718 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7723 /* The mips16 loads the return address into $7, not $31. */
7724 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7725 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7726 GP_REG_FIRST + 7)));
7728 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7729 GP_REG_FIRST + 31)));
7732 /* Return nonzero if this function is known to have a null epilogue.
7733 This allows the optimizer to omit jumps to jumps if no stack
7737 mips_can_use_return_insn ()
7739 if (! reload_completed)
7742 if (regs_ever_live[31] || profile_flag)
7745 /* In mips16 mode, a function which returns a floating point value
7746 needs to arrange to copy the return value into the floating point
7749 && mips16_hard_float
7750 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7751 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7753 && (! TARGET_SINGLE_FLOAT
7754 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7758 if (current_frame_info.initialized)
7759 return current_frame_info.total_size == 0;
7761 return compute_frame_size (get_frame_size ()) == 0;
7764 /* Returns non-zero if X contains a SYMBOL_REF. */
7767 symbolic_expression_p (x)
7770 if (GET_CODE (x) == SYMBOL_REF)
7773 if (GET_CODE (x) == CONST)
7774 return symbolic_expression_p (XEXP (x, 0));
7776 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7777 return symbolic_expression_p (XEXP (x, 0));
7779 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7780 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7781 return (symbolic_expression_p (XEXP (x, 0))
7782 || symbolic_expression_p (XEXP (x, 1)));
7787 /* Choose the section to use for the constant rtx expression X that has
7791 mips_select_rtx_section (mode, x)
7792 enum machine_mode mode;
7793 rtx x ATTRIBUTE_UNUSED;
7797 /* In mips16 mode, the constant table always goes in the same section
7798 as the function, so that constants can be loaded using PC relative
7800 function_section (current_function_decl);
7802 else if (TARGET_EMBEDDED_DATA)
7804 /* For embedded applications, always put constants in read-only data,
7805 in order to reduce RAM usage. */
7806 READONLY_DATA_SECTION ();
7810 /* For hosted applications, always put constants in small data if
7811 possible, as this gives the best performance. */
7813 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7814 && mips_section_threshold > 0)
7815 SMALL_DATA_SECTION ();
7816 else if (flag_pic && symbolic_expression_p (x))
7817 /* Any expression involving a SYMBOL_REF might need a run-time
7818 relocation. (The symbol might be defined in a shared
7819 library loaded at an unexpected base address.) So, we must
7820 put such expressions in the data segment (which is
7821 writable), rather than the text segment (which is
7825 READONLY_DATA_SECTION ();
7829 /* Choose the section to use for DECL. RELOC is true if its value contains
7830 any relocatable expression.
7832 Some of the logic used here needs to be replicated in
7833 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7834 are done correctly. Specifically, at least all symbols assigned
7835 here to rom (.text and/or .rodata) must not be referenced via
7836 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7838 If you need to make a change here, you probably should check
7839 ENCODE_SECTION_INFO to see if it needs a similar change. */
7842 mips_select_section (decl, reloc)
7846 int size = int_size_in_bytes (TREE_TYPE (decl));
7848 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7849 && TREE_CODE (decl) == STRING_CST
7850 && !flag_writable_strings)
7851 /* For embedded position independent code, put constant strings in the
7852 text section, because the data section is limited to 64K in size.
7853 For mips16 code, put strings in the text section so that a PC
7854 relative load instruction can be used to get their address. */
7856 else if (TARGET_EMBEDDED_DATA)
7858 /* For embedded applications, always put an object in read-only data
7859 if possible, in order to reduce RAM usage. */
7861 if (((TREE_CODE (decl) == VAR_DECL
7862 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7863 && DECL_INITIAL (decl)
7864 && (DECL_INITIAL (decl) == error_mark_node
7865 || TREE_CONSTANT (DECL_INITIAL (decl))))
7866 /* Deal with calls from output_constant_def_contents. */
7867 || (TREE_CODE (decl) != VAR_DECL
7868 && (TREE_CODE (decl) != STRING_CST
7869 || !flag_writable_strings)))
7870 && ! (flag_pic && reloc))
7871 READONLY_DATA_SECTION ();
7872 else if (size > 0 && size <= mips_section_threshold)
7873 SMALL_DATA_SECTION ();
7879 /* For hosted applications, always put an object in small data if
7880 possible, as this gives the best performance. */
7882 if (size > 0 && size <= mips_section_threshold)
7883 SMALL_DATA_SECTION ();
7884 else if (((TREE_CODE (decl) == VAR_DECL
7885 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7886 && DECL_INITIAL (decl)
7887 && (DECL_INITIAL (decl) == error_mark_node
7888 || TREE_CONSTANT (DECL_INITIAL (decl))))
7889 /* Deal with calls from output_constant_def_contents. */
7890 || (TREE_CODE (decl) != VAR_DECL
7891 && (TREE_CODE (decl) != STRING_CST
7892 || !flag_writable_strings)))
7893 && ! (flag_pic && reloc))
7894 READONLY_DATA_SECTION ();
7900 #ifdef MIPS_ABI_DEFAULT
7902 /* Support functions for the 64 bit ABI. */
7904 /* Return register to use for a function return value with VALTYPE for function
7908 mips_function_value (valtype, func)
7910 tree func ATTRIBUTE_UNUSED;
7912 int reg = GP_RETURN;
7913 enum machine_mode mode = TYPE_MODE (valtype);
7914 enum mode_class mclass = GET_MODE_CLASS (mode);
7915 int unsignedp = TREE_UNSIGNED (valtype);
7917 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7918 just as PROMOTE_MODE does. */
7919 mode = promote_mode (valtype, mode, &unsignedp, 1);
7921 if (mclass == MODE_FLOAT)
7923 if (TARGET_SINGLE_FLOAT
7924 && (mclass == MODE_FLOAT
7925 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7931 else if (mclass == MODE_COMPLEX_FLOAT)
7935 else if (mode == SCmode)
7937 /* When FP registers are 32 bits, we can't directly reference
7938 the odd numbered ones, so let's make a pair of evens. */
7940 enum machine_mode cmode = TYPE_MODE (TREE_TYPE (valtype));
7942 return gen_rtx_PARALLEL
7945 gen_rtx_EXPR_LIST (VOIDmode,
7949 gen_rtx_EXPR_LIST (VOIDmode,
7958 else if (TREE_CODE (valtype) == RECORD_TYPE
7959 && mips_abi != ABI_32
7960 && mips_abi != ABI_O64
7961 && mips_abi != ABI_EABI)
7963 /* A struct with only one or two floating point fields is returned in
7964 the floating point registers. */
7965 tree field, fields[2];
7968 for (i = 0, field = TYPE_FIELDS (valtype); field;
7969 field = TREE_CHAIN (field))
7971 if (TREE_CODE (field) != FIELD_DECL)
7974 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7977 fields[i++] = field;
7980 /* Must check i, so that we reject structures with no elements. */
7985 /* The structure has DImode, but we don't allow DImode values
7986 in FP registers, so we use a PARALLEL even though it isn't
7987 strictly necessary. */
7988 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7990 return gen_rtx_PARALLEL
7993 gen_rtx_EXPR_LIST (VOIDmode,
7994 gen_rtx_REG (field_mode,
8001 enum machine_mode first_mode
8002 = TYPE_MODE (TREE_TYPE (fields[0]));
8003 enum machine_mode second_mode
8004 = TYPE_MODE (TREE_TYPE (fields[1]));
8005 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
8006 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
8008 return gen_rtx_PARALLEL
8011 gen_rtx_EXPR_LIST (VOIDmode,
8012 gen_rtx_REG (first_mode,
8014 GEN_INT (first_offset)),
8015 gen_rtx_EXPR_LIST (VOIDmode,
8016 gen_rtx_REG (second_mode,
8018 GEN_INT (second_offset))));
8023 return gen_rtx_REG (mode, reg);
8027 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8028 nonzero when an argument must be passed by reference. */
8031 function_arg_pass_by_reference (cum, mode, type, named)
8032 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
8033 enum machine_mode mode;
8035 int named ATTRIBUTE_UNUSED;
8039 /* We must pass by reference if we would be both passing in registers
8040 and the stack. This is because any subsequent partial arg would be
8041 handled incorrectly in this case.
8043 ??? This is really a kludge. We should either fix GCC so that such
8044 a situation causes an abort and then do something in the MIPS port
8045 to prevent it, or add code to function.c to properly handle the case. */
8046 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8047 here hopefully is not relevant to mips_va_arg. */
8048 if (cum && MUST_PASS_IN_STACK (mode, type)
8049 && mips_abi != ABI_MEABI)
8051 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
8052 get double copies of any offsets generated for small structs
8053 passed in registers. */
8054 CUMULATIVE_ARGS temp;
8056 if (FUNCTION_ARG (temp, mode, type, named) != 0)
8060 /* Otherwise, we only do this if EABI is selected. */
8061 if (mips_abi != ABI_EABI)
8064 /* ??? How should SCmode be handled? */
8065 if (type == NULL_TREE || mode == DImode || mode == DFmode)
8068 size = int_size_in_bytes (type);
8069 return size == -1 || size > UNITS_PER_WORD;
8072 /* This function returns the register class required for a secondary
8073 register when copying between one of the registers in CLASS, and X,
8074 using MODE. If IN_P is nonzero, the copy is going from X to the
8075 register, otherwise the register is the source. A return value of
8076 NO_REGS means that no secondary register is required. */
8079 mips_secondary_reload_class (class, mode, x, in_p)
8080 enum reg_class class;
8081 enum machine_mode mode;
8085 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8089 if (GET_CODE (x) == SIGN_EXTEND)
8095 /* We may be called with reg_renumber NULL from regclass.
8096 ??? This is probably a bug. */
8098 regno = true_regnum (x);
8101 while (GET_CODE (x) == SUBREG)
8103 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
8104 GET_MODE (SUBREG_REG (x)),
8110 if (GET_CODE (x) == REG)
8111 regno = REGNO (x) + off;
8115 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
8116 regno = true_regnum (x);
8118 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8120 /* We always require a general register when copying anything to
8121 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8122 to a general register, or when copying from register 0. */
8123 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
8126 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8127 ? NO_REGS : gr_regs);
8128 else if (regno == HILO_REGNUM)
8131 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8132 ? NO_REGS : gr_regs);
8134 /* Copying from HI or LO to anywhere other than a general register
8135 requires a general register. */
8136 if (class == HI_REG || class == LO_REG || class == MD_REGS)
8138 if (TARGET_MIPS16 && in_p)
8140 /* We can't really copy to HI or LO at all in mips16 mode. */
8143 return gp_reg_p ? NO_REGS : gr_regs;
8145 if (MD_REG_P (regno))
8147 if (TARGET_MIPS16 && ! in_p)
8149 /* We can't really copy to HI or LO at all in mips16 mode. */
8152 return class == gr_regs ? NO_REGS : gr_regs;
8155 /* We can only copy a value to a condition code register from a
8156 floating point register, and even then we require a scratch
8157 floating point register. We can only copy a value out of a
8158 condition code register into a general register. */
8159 if (class == ST_REGS)
8163 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8165 if (ST_REG_P (regno))
8169 return class == GR_REGS ? NO_REGS : GR_REGS;
8172 /* In mips16 mode, going between memory and anything but M16_REGS
8173 requires an M16_REG. */
8176 if (class != M16_REGS && class != M16_NA_REGS)
8184 /* The stack pointer isn't a valid operand to an add instruction,
8185 so we need to load it into M16_REGS first. This can happen as
8186 a result of register elimination and form_sum converting
8187 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8188 need an extra register if the dest is the same as the other
8189 register. In that case, we can't fix the problem by loading SP
8190 into the dest first. */
8191 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8192 && GET_CODE (XEXP (x, 1)) == REG
8193 && (XEXP (x, 0) == stack_pointer_rtx
8194 || XEXP (x, 1) == stack_pointer_rtx))
8195 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8197 if (class == M16_REGS || class == M16_NA_REGS)
8206 /* For each mips16 function which refers to GP relative symbols, we
8207 use a pseudo register, initialized at the start of the function, to
8208 hold the $gp value. */
8211 mips16_gp_pseudo_reg ()
8213 if (mips16_gp_pseudo_rtx == NULL_RTX)
8218 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8219 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
8221 /* We want to initialize this to a value which gcc will believe
8223 const_gp = gen_rtx (CONST, Pmode,
8224 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8227 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
8228 insn = gen_sequence ();
8231 push_topmost_sequence ();
8232 /* We need to emit the initialization after the FUNCTION_BEG
8233 note, so that it will be integrated. */
8234 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8235 if (GET_CODE (scan) == NOTE
8236 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8238 if (scan == NULL_RTX)
8239 scan = get_insns ();
8240 insn = emit_insn_after (insn, scan);
8241 pop_topmost_sequence ();
8244 return mips16_gp_pseudo_rtx;
8247 /* Return an RTX which represents the signed 16 bit offset from the
8248 $gp register for the given symbol. This is only used on the
8252 mips16_gp_offset (sym)
8257 if (GET_CODE (sym) != SYMBOL_REF
8258 || ! SYMBOL_REF_FLAG (sym))
8261 /* We use a special identifier to represent the value of the gp
8263 gp = get_identifier ("__mips16_gp_value");
8265 return gen_rtx (CONST, Pmode,
8266 gen_rtx (MINUS, Pmode, sym,
8267 gen_rtx (SYMBOL_REF, Pmode,
8268 IDENTIFIER_POINTER (gp))));
8271 /* Return nonzero if the given RTX represents a signed 16 bit offset
8272 from the $gp register. */
8275 mips16_gp_offset_p (x)
8278 if (GET_CODE (x) == CONST)
8281 /* It's OK to add a small integer value to a gp offset. */
8282 if (GET_CODE (x) == PLUS)
8284 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8285 && SMALL_INT (XEXP (x, 1)))
8286 return mips16_gp_offset_p (XEXP (x, 0));
8287 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8288 && SMALL_INT (XEXP (x, 0)))
8289 return mips16_gp_offset_p (XEXP (x, 1));
8293 /* Make sure it is in the form SYM - __mips16_gp_value. */
8294 return (GET_CODE (x) == MINUS
8295 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8296 && SYMBOL_REF_FLAG (XEXP (x, 0))
8297 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8298 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8301 /* Output a GP offset. We don't want to print the subtraction of
8302 __mips16_gp_value; it is implicitly represented by the %gprel which
8303 should have been printed by the caller. */
8306 mips16_output_gp_offset (file, x)
8310 if (GET_CODE (x) == CONST)
8313 if (GET_CODE (x) == PLUS)
8315 mips16_output_gp_offset (file, XEXP (x, 0));
8317 mips16_output_gp_offset (file, XEXP (x, 1));
8321 if (GET_CODE (x) == MINUS
8322 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8323 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8325 mips16_output_gp_offset (file, XEXP (x, 0));
8329 output_addr_const (file, x);
8332 /* Return nonzero if a constant should not be output until after the
8333 function. This is true of most string constants, so that we can
8334 use a more efficient PC relative reference. However, a static
8335 inline function may never call assemble_function_end to write out
8336 the constant pool, so don't try to postpone the constant in that
8339 ??? It's really a bug that a static inline function can put stuff
8340 in the constant pool even if the function itself is not output.
8342 We record which string constants we've seen, so that we know which
8343 ones might use the more efficient reference. */
8346 mips16_constant_after_function_p (x)
8349 if (TREE_CODE (x) == STRING_CST
8350 && ! flag_writable_strings
8351 && current_function_decl != 0
8352 && ! DECL_DEFER_OUTPUT (current_function_decl)
8353 && ! (DECL_INLINE (current_function_decl)
8354 && ((! TREE_PUBLIC (current_function_decl)
8355 && ! TREE_ADDRESSABLE (current_function_decl)
8356 && ! flag_keep_inline_functions)
8357 || DECL_EXTERNAL (current_function_decl))))
8359 struct string_constant *n;
8361 n = (struct string_constant *) xmalloc (sizeof *n);
8362 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8363 n->next = string_constants;
8364 string_constants = n;
8372 /* Validate a constant for the mips16. This rejects general symbolic
8373 addresses, which must be loaded from memory. If ADDR is nonzero,
8374 this should reject anything which is not a legal address. If
8375 ADDEND is nonzero, this is being added to something else. */
8378 mips16_constant (x, mode, addr, addend)
8380 enum machine_mode mode;
8384 while (GET_CODE (x) == CONST)
8387 switch (GET_CODE (x))
8393 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8394 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8397 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8399 if (CONSTANT_POOL_ADDRESS_P (x))
8402 /* If we aren't looking for a memory address, we can accept a GP
8403 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8404 knows how to handle this. We can always accept a string
8405 constant, which is the other case in which SYMBOL_REF_FLAG
8409 && SYMBOL_REF_FLAG (x)
8410 && mode == (enum machine_mode) Pmode)
8413 /* We can accept a string constant, which will have
8414 SYMBOL_REF_FLAG set but must be recognized by name to
8415 distinguish from a GP accessible symbol. The name of a
8416 string constant will have been generated by
8417 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8418 if (SYMBOL_REF_FLAG (x))
8420 const char *name = XSTR (x, 0);
8422 return (name[0] == '*'
8423 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8424 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8430 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8435 if (addr && ! addend)
8437 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8440 /* We need to treat $gp as a legitimate constant, because
8441 mips16_gp_pseudo_reg assumes that. */
8442 return REGNO (x) == GP_REG_FIRST + 28;
8446 /* Write out code to move floating point arguments in or out of
8447 general registers. Output the instructions to FILE. FP_CODE is
8448 the code describing which arguments are present (see the comment at
8449 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8450 we are copying from the floating point registers. */
8453 mips16_fp_args (file, fp_code, from_fp_p)
8462 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8463 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8470 gparg = GP_ARG_FIRST;
8471 fparg = FP_ARG_FIRST;
8472 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8476 if ((fparg & 1) != 0)
8478 fprintf (file, "\t%s\t%s,%s\n", s,
8479 reg_names[gparg], reg_names[fparg]);
8481 else if ((f & 3) == 2)
8484 fprintf (file, "\td%s\t%s,%s\n", s,
8485 reg_names[gparg], reg_names[fparg]);
8488 if ((fparg & 1) != 0)
8490 if (TARGET_BIG_ENDIAN)
8491 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8492 reg_names[gparg], reg_names[fparg + 1], s,
8493 reg_names[gparg + 1], reg_names[fparg]);
8495 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8496 reg_names[gparg], reg_names[fparg], s,
8497 reg_names[gparg + 1], reg_names[fparg + 1]);
8510 /* Build a mips16 function stub. This is used for functions which
8511 take aruments in the floating point registers. It is 32 bit code
8512 that moves the floating point args into the general registers, and
8513 then jumps to the 16 bit code. */
8516 build_mips16_function_stub (file)
8520 char *secname, *stubname;
8521 tree stubid, stubdecl;
8525 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8526 secname = (char *) alloca (strlen (fnname) + 20);
8527 sprintf (secname, ".mips16.fn.%s", fnname);
8528 stubname = (char *) alloca (strlen (fnname) + 20);
8529 sprintf (stubname, "__fn_stub_%s", fnname);
8530 stubid = get_identifier (stubname);
8531 stubdecl = build_decl (FUNCTION_DECL, stubid,
8532 build_function_type (void_type_node, NULL_TREE));
8533 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8535 fprintf (file, "\t# Stub function for %s (", current_function_name);
8537 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8539 fprintf (file, "%s%s",
8540 need_comma ? ", " : "",
8541 (f & 3) == 1 ? "float" : "double");
8544 fprintf (file, ")\n");
8546 fprintf (file, "\t.set\tnomips16\n");
8547 function_section (stubdecl);
8548 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8550 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8551 within a .ent, and we can not emit another .ent. */
8552 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8553 fputs ("\t.ent\t", file);
8554 assemble_name (file, stubname);
8558 assemble_name (file, stubname);
8559 fputs (":\n", file);
8561 /* We don't want the assembler to insert any nops here. */
8562 fprintf (file, "\t.set\tnoreorder\n");
8564 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8566 fprintf (asm_out_file, "\t.set\tnoat\n");
8567 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8568 assemble_name (file, fnname);
8569 fprintf (file, "\n");
8570 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8571 fprintf (asm_out_file, "\t.set\tat\n");
8573 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8574 with one of the mfc1 instructions, because the result is not
8575 available for one instruction, so if the very first instruction
8576 in the function refers to the register, it will see the wrong
8578 fprintf (file, "\tnop\n");
8580 fprintf (file, "\t.set\treorder\n");
8582 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8583 fputs ("\t.end\t", file);
8584 assemble_name (file, stubname);
8588 fprintf (file, "\t.set\tmips16\n");
8590 function_section (current_function_decl);
8593 /* We keep a list of functions for which we have already built stubs
8594 in build_mips16_call_stub. */
8598 struct mips16_stub *next;
8603 static struct mips16_stub *mips16_stubs;
8605 /* Build a call stub for a mips16 call. A stub is needed if we are
8606 passing any floating point values which should go into the floating
8607 point registers. If we are, and the call turns out to be to a 32
8608 bit function, the stub will be used to move the values into the
8609 floating point registers before calling the 32 bit function. The
8610 linker will magically adjust the function call to either the 16 bit
8611 function or the 32 bit stub, depending upon where the function call
8612 is actually defined.
8614 Similarly, we need a stub if the return value might come back in a
8615 floating point register.
8617 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8618 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8619 is the code built by function_arg. This function returns a nonzero
8620 value if it builds the call instruction itself. */
8623 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8632 char *secname, *stubname;
8633 struct mips16_stub *l;
8634 tree stubid, stubdecl;
8638 /* We don't need to do anything if we aren't in mips16 mode, or if
8639 we were invoked with the -msoft-float option. */
8640 if (! TARGET_MIPS16 || ! mips16_hard_float)
8643 /* Figure out whether the value might come back in a floating point
8645 fpret = (retval != 0
8646 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8647 && (! TARGET_SINGLE_FLOAT
8648 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8650 /* We don't need to do anything if there were no floating point
8651 arguments and the value will not be returned in a floating point
8653 if (fp_code == 0 && ! fpret)
8656 if (GET_CODE (fnmem) != MEM)
8658 fn = XEXP (fnmem, 0);
8660 /* We don't need to do anything if this is a call to a special
8661 mips16 support function. */
8662 if (GET_CODE (fn) == SYMBOL_REF
8663 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8666 /* This code will only work for o32 and o64 abis. The other ABI's
8667 require more sophisticated support. */
8668 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8671 /* We can only handle SFmode and DFmode floating point return
8673 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8676 /* If we're calling via a function pointer, then we must always call
8677 via a stub. There are magic stubs provided in libgcc.a for each
8678 of the required cases. Each of them expects the function address
8679 to arrive in register $2. */
8681 if (GET_CODE (fn) != SYMBOL_REF)
8685 rtx stub_fn, stub_mem, insn;
8687 /* ??? If this code is modified to support other ABI's, we need
8688 to handle PARALLEL return values here. */
8690 sprintf (buf, "__mips16_call_stub_%s%d",
8692 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8695 id = get_identifier (buf);
8696 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8697 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8699 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8701 if (retval == NULL_RTX)
8702 insn = gen_call_internal0 (stub_mem, arg_size,
8703 gen_rtx (REG, SImode,
8704 GP_REG_FIRST + 31));
8706 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8707 gen_rtx (REG, SImode,
8708 GP_REG_FIRST + 31));
8709 insn = emit_call_insn (insn);
8711 /* Put the register usage information on the CALL. */
8712 if (GET_CODE (insn) != CALL_INSN)
8714 CALL_INSN_FUNCTION_USAGE (insn) =
8715 gen_rtx (EXPR_LIST, VOIDmode,
8716 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8717 CALL_INSN_FUNCTION_USAGE (insn));
8719 /* If we are handling a floating point return value, we need to
8720 save $18 in the function prologue. Putting a note on the
8721 call will mean that regs_ever_live[$18] will be true if the
8722 call is not eliminated, and we can check that in the prologue
8725 CALL_INSN_FUNCTION_USAGE (insn) =
8726 gen_rtx (EXPR_LIST, VOIDmode,
8727 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8728 CALL_INSN_FUNCTION_USAGE (insn));
8730 /* Return 1 to tell the caller that we've generated the call
8735 /* We know the function we are going to call. If we have already
8736 built a stub, we don't need to do anything further. */
8738 fnname = XSTR (fn, 0);
8739 for (l = mips16_stubs; l != NULL; l = l->next)
8740 if (strcmp (l->name, fnname) == 0)
8745 /* Build a special purpose stub. When the linker sees a
8746 function call in mips16 code, it will check where the target
8747 is defined. If the target is a 32 bit call, the linker will
8748 search for the section defined here. It can tell which
8749 symbol this section is associated with by looking at the
8750 relocation information (the name is unreliable, since this
8751 might be a static function). If such a section is found, the
8752 linker will redirect the call to the start of the magic
8755 If the function does not return a floating point value, the
8756 special stub section is named
8759 If the function does return a floating point value, the stub
8761 .mips16.call.fp.FNNAME
8764 secname = (char *) alloca (strlen (fnname) + 40);
8765 sprintf (secname, ".mips16.call.%s%s",
8768 stubname = (char *) alloca (strlen (fnname) + 20);
8769 sprintf (stubname, "__call_stub_%s%s",
8772 stubid = get_identifier (stubname);
8773 stubdecl = build_decl (FUNCTION_DECL, stubid,
8774 build_function_type (void_type_node, NULL_TREE));
8775 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8777 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8779 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8783 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8785 fprintf (asm_out_file, "%s%s",
8786 need_comma ? ", " : "",
8787 (f & 3) == 1 ? "float" : "double");
8790 fprintf (asm_out_file, ")\n");
8792 fprintf (asm_out_file, "\t.set\tnomips16\n");
8793 assemble_start_function (stubdecl, stubname);
8795 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8796 fputs ("\t.ent\t", asm_out_file);
8797 assemble_name (asm_out_file, stubname);
8798 fputs ("\n", asm_out_file);
8800 assemble_name (asm_out_file, stubname);
8801 fputs (":\n", asm_out_file);
8804 /* We build the stub code by hand. That's the only way we can
8805 do it, since we can't generate 32 bit code during a 16 bit
8808 /* We don't want the assembler to insert any nops here. */
8809 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8811 mips16_fp_args (asm_out_file, fp_code, 0);
8815 fprintf (asm_out_file, "\t.set\tnoat\n");
8816 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8818 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8819 fprintf (asm_out_file, "\t.set\tat\n");
8820 /* Unfortunately, we can't fill the jump delay slot. We
8821 can't fill with one of the mtc1 instructions, because the
8822 result is not available for one instruction, so if the
8823 very first instruction in the function refers to the
8824 register, it will see the wrong value. */
8825 fprintf (asm_out_file, "\tnop\n");
8829 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8830 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8831 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8832 /* As above, we can't fill the delay slot. */
8833 fprintf (asm_out_file, "\tnop\n");
8834 if (GET_MODE (retval) == SFmode)
8835 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8836 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8839 if (TARGET_BIG_ENDIAN)
8841 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8842 reg_names[GP_REG_FIRST + 2],
8843 reg_names[FP_REG_FIRST + 1]);
8844 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8845 reg_names[GP_REG_FIRST + 3],
8846 reg_names[FP_REG_FIRST + 0]);
8850 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8851 reg_names[GP_REG_FIRST + 2],
8852 reg_names[FP_REG_FIRST + 0]);
8853 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8854 reg_names[GP_REG_FIRST + 3],
8855 reg_names[FP_REG_FIRST + 1]);
8858 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8859 /* As above, we can't fill the delay slot. */
8860 fprintf (asm_out_file, "\tnop\n");
8863 fprintf (asm_out_file, "\t.set\treorder\n");
8865 #ifdef ASM_DECLARE_FUNCTION_SIZE
8866 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8869 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8870 fputs ("\t.end\t", asm_out_file);
8871 assemble_name (asm_out_file, stubname);
8872 fputs ("\n", asm_out_file);
8875 fprintf (asm_out_file, "\t.set\tmips16\n");
8877 /* Record this stub. */
8878 l = (struct mips16_stub *) xmalloc (sizeof *l);
8879 l->name = xstrdup (fnname);
8881 l->next = mips16_stubs;
8885 /* If we expect a floating point return value, but we've built a
8886 stub which does not expect one, then we're in trouble. We can't
8887 use the existing stub, because it won't handle the floating point
8888 value. We can't build a new stub, because the linker won't know
8889 which stub to use for the various calls in this object file.
8890 Fortunately, this case is illegal, since it means that a function
8891 was declared in two different ways in a single compilation. */
8892 if (fpret && ! l->fpret)
8893 error ("can not handle inconsistent calls to `%s'", fnname);
8895 /* If we are calling a stub which handles a floating point return
8896 value, we need to arrange to save $18 in the prologue. We do
8897 this by marking the function call as using the register. The
8898 prologue will later see that it is used, and emit code to save
8905 if (retval == NULL_RTX)
8906 insn = gen_call_internal0 (fnmem, arg_size,
8907 gen_rtx (REG, SImode,
8908 GP_REG_FIRST + 31));
8910 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8911 gen_rtx (REG, SImode,
8912 GP_REG_FIRST + 31));
8913 insn = emit_call_insn (insn);
8915 if (GET_CODE (insn) != CALL_INSN)
8918 CALL_INSN_FUNCTION_USAGE (insn) =
8919 gen_rtx (EXPR_LIST, VOIDmode,
8920 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8921 CALL_INSN_FUNCTION_USAGE (insn));
8923 /* Return 1 to tell the caller that we've generated the call
8928 /* Return 0 to let the caller generate the call insn. */
8932 /* This function looks through the code for a function, and tries to
8933 optimize the usage of the $gp register. We arrange to copy $gp
8934 into a pseudo-register, and then let gcc's normal reload handling
8935 deal with the pseudo-register. Unfortunately, if reload choose to
8936 put the pseudo-register into a call-clobbered register, it will
8937 emit saves and restores for that register around any function
8938 calls. We don't need the saves, and it's faster to copy $gp than
8939 to do an actual restore. ??? This still means that we waste a
8942 This is an optimization, and the code which gcc has actually
8943 generated is correct, so we do not need to catch all cases. */
8946 mips16_optimize_gp (first)
8949 rtx gpcopy, slot, insn;
8951 /* Look through the instructions. Set GPCOPY to the register which
8952 holds a copy of $gp. Set SLOT to the stack slot where it is
8953 saved. If we find an instruction which sets GPCOPY to anything
8954 other than $gp or SLOT, then we can't use it. If we find an
8955 instruction which sets SLOT to anything other than GPCOPY, we
8960 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8964 if (! INSN_P (insn))
8967 set = PATTERN (insn);
8969 /* We know that all references to memory will be inside a SET,
8970 because there is no other way to access memory on the mips16.
8971 We don't have to worry about a PARALLEL here, because the
8972 mips.md file will never generate them for memory references. */
8973 if (GET_CODE (set) != SET)
8976 if (gpcopy == NULL_RTX
8977 && GET_CODE (SET_SRC (set)) == CONST
8978 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8979 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8980 && GET_CODE (SET_DEST (set)) == REG
8981 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8982 gpcopy = SET_DEST (set);
8983 else if (slot == NULL_RTX
8984 && gpcopy != NULL_RTX
8985 && GET_CODE (SET_DEST (set)) == MEM
8986 && GET_CODE (SET_SRC (set)) == REG
8987 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8988 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8992 offset = const0_rtx;
8993 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8994 if (GET_CODE (base) == REG
8995 && (REGNO (base) == STACK_POINTER_REGNUM
8996 || REGNO (base) == FRAME_POINTER_REGNUM))
8997 slot = SET_DEST (set);
8999 else if (gpcopy != NULL_RTX
9000 && (GET_CODE (SET_DEST (set)) == REG
9001 || GET_CODE (SET_DEST (set)) == SUBREG)
9002 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
9003 && (GET_CODE (SET_DEST (set)) != REG
9004 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
9005 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
9006 || ((GET_CODE (SET_SRC (set)) != CONST
9007 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
9008 || (REGNO (XEXP (SET_SRC (set), 0))
9009 != GP_REG_FIRST + 28))
9010 && ! rtx_equal_p (SET_SRC (set), slot))))
9012 else if (slot != NULL_RTX
9013 && GET_CODE (SET_DEST (set)) == MEM
9014 && rtx_equal_p (SET_DEST (set), slot)
9015 && (GET_CODE (SET_SRC (set)) != REG
9016 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
9020 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9021 different optimization. Any time we find a copy of $28 into a
9022 register, followed by an add of a symbol_ref to that register, we
9023 convert it to load the value from the constant table instead.
9024 The copy and add will take six bytes, just as the load and
9025 constant table entry will take six bytes. However, it is
9026 possible that the constant table entry will be shared.
9028 This could be a peephole optimization, but I don't know if the
9029 peephole code can call force_const_mem.
9031 Using the same register for the copy of $28 and the add of the
9032 symbol_ref is actually pretty likely, since the add instruction
9033 requires the destination and the first addend to be the same
9036 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
9040 /* This optimization is only reasonable if the constant table
9041 entries are only 4 bytes. */
9042 if (Pmode != SImode)
9045 for (insn = first; insn != NULL_RTX; insn = next)
9052 next = NEXT_INSN (next);
9054 while (next != NULL_RTX
9055 && (GET_CODE (next) == NOTE
9056 || (GET_CODE (next) == INSN
9057 && (GET_CODE (PATTERN (next)) == USE
9058 || GET_CODE (PATTERN (next)) == CLOBBER))));
9060 if (next == NULL_RTX)
9063 if (! INSN_P (insn))
9066 if (! INSN_P (next))
9069 set1 = PATTERN (insn);
9070 if (GET_CODE (set1) != SET)
9072 set2 = PATTERN (next);
9073 if (GET_CODE (set2) != SET)
9076 if (GET_CODE (SET_DEST (set1)) == REG
9077 && GET_CODE (SET_SRC (set1)) == CONST
9078 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
9079 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
9080 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
9081 && GET_CODE (SET_SRC (set2)) == PLUS
9082 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
9083 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
9084 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
9088 /* We've found a case we can change to load from the
9091 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
9092 if (GET_CODE (sym) != SYMBOL_REF)
9094 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
9095 force_const_mem (Pmode, sym)),
9098 PUT_CODE (insn, NOTE);
9099 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9100 NOTE_SOURCE_FILE (insn) = 0;
9102 PUT_CODE (next, NOTE);
9103 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
9104 NOTE_SOURCE_FILE (next) = 0;
9111 /* We can safely remove all assignments to SLOT from GPCOPY, and
9112 replace all assignments from SLOT to GPCOPY with assignments from
9115 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9119 if (! INSN_P (insn))
9122 set = PATTERN (insn);
9123 if (GET_CODE (set) != SET
9124 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
9127 if (GET_CODE (SET_DEST (set)) == MEM
9128 && rtx_equal_p (SET_DEST (set), slot)
9129 && GET_CODE (SET_SRC (set)) == REG
9130 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
9132 PUT_CODE (insn, NOTE);
9133 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9134 NOTE_SOURCE_FILE (insn) = 0;
9136 else if (GET_CODE (SET_DEST (set)) == REG
9137 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9138 && GET_CODE (SET_SRC (set)) == MEM
9139 && rtx_equal_p (SET_SRC (set), slot))
9141 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
9142 gen_rtx (CONST, Pmode,
9143 gen_rtx (REG, Pmode,
9144 GP_REG_FIRST + 28))),
9146 PUT_CODE (insn, NOTE);
9147 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9148 NOTE_SOURCE_FILE (insn) = 0;
9153 /* We keep a list of constants we which we have to add to internal
9154 constant tables in the middle of large functions. */
9158 struct constant *next;
9161 enum machine_mode mode;
9164 /* Add a constant to the list in *PCONSTANTS. */
9167 add_constant (pconstants, val, mode)
9168 struct constant **pconstants;
9170 enum machine_mode mode;
9174 for (c = *pconstants; c != NULL; c = c->next)
9175 if (mode == c->mode && rtx_equal_p (val, c->value))
9178 c = (struct constant *) xmalloc (sizeof *c);
9181 c->label = gen_label_rtx ();
9182 c->next = *pconstants;
9187 /* Dump out the constants in CONSTANTS after INSN. */
9190 dump_constants (constants, insn)
9191 struct constant *constants;
9202 struct constant *next;
9204 switch (GET_MODE_SIZE (c->mode))
9211 insn = emit_insn_after (gen_align_2 (), insn);
9216 insn = emit_insn_after (gen_align_4 (), insn);
9221 insn = emit_insn_after (gen_align_8 (), insn);
9226 insn = emit_label_after (c->label, insn);
9231 r = gen_consttable_qi (c->value);
9234 r = gen_consttable_hi (c->value);
9237 r = gen_consttable_si (c->value);
9240 r = gen_consttable_sf (c->value);
9243 r = gen_consttable_di (c->value);
9246 r = gen_consttable_df (c->value);
9252 insn = emit_insn_after (r, insn);
9259 emit_barrier_after (insn);
9262 /* Find the symbol in an address expression. */
9265 mips_find_symbol (addr)
9268 if (GET_CODE (addr) == MEM)
9269 addr = XEXP (addr, 0);
9270 while (GET_CODE (addr) == CONST)
9271 addr = XEXP (addr, 0);
9272 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9274 if (GET_CODE (addr) == PLUS)
9278 l1 = mips_find_symbol (XEXP (addr, 0));
9279 l2 = mips_find_symbol (XEXP (addr, 1));
9280 if (l1 != NULL_RTX && l2 == NULL_RTX)
9282 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9288 /* Exported to toplev.c.
9290 Do a final pass over the function, just before delayed branch
9294 machine_dependent_reorg (first)
9297 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9299 struct constant *constants;
9301 if (! TARGET_MIPS16)
9304 /* If $gp is used, try to remove stores, and replace loads with
9307 mips16_optimize_gp (first);
9309 /* Scan the function looking for PC relative loads which may be out
9310 of range. All such loads will either be from the constant table,
9311 or be getting the address of a constant string. If the size of
9312 the function plus the size of the constant table is less than
9313 0x8000, then all loads are in range. */
9316 for (insn = first; insn; insn = NEXT_INSN (insn))
9318 insns_len += get_attr_length (insn);
9320 /* ??? We put switch tables in .text, but we don't define
9321 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9322 compute their lengths correctly. */
9323 if (GET_CODE (insn) == JUMP_INSN)
9327 body = PATTERN (insn);
9328 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9329 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9330 * GET_MODE_SIZE (GET_MODE (body)));
9331 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9335 /* Store the original value of insns_len in current_frame_info, so
9336 that simple_memory_operand can look at it. */
9337 current_frame_info.insns_len = insns_len;
9339 pool_size = get_pool_size ();
9340 if (insns_len + pool_size + mips_string_length < 0x8000)
9343 /* Loop over the insns and figure out what the maximum internal pool
9345 max_internal_pool_size = 0;
9346 for (insn = first; insn; insn = NEXT_INSN (insn))
9348 if (GET_CODE (insn) == INSN
9349 && GET_CODE (PATTERN (insn)) == SET)
9353 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9354 if (src == NULL_RTX)
9356 if (CONSTANT_POOL_ADDRESS_P (src))
9357 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9358 else if (SYMBOL_REF_FLAG (src))
9359 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9365 first_constant_ref = -1;
9367 for (insn = first; insn; insn = NEXT_INSN (insn))
9369 if (GET_CODE (insn) == INSN
9370 && GET_CODE (PATTERN (insn)) == SET)
9373 enum machine_mode mode = VOIDmode;
9376 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9377 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9379 /* ??? This is very conservative, which means that we
9380 will generate too many copies of the constant table.
9381 The only solution would seem to be some form of
9383 if (((insns_len - addr)
9384 + max_internal_pool_size
9385 + get_pool_offset (src))
9388 val = get_pool_constant (src);
9389 mode = get_pool_mode (src);
9391 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9393 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9395 /* Including all of mips_string_length is conservative,
9396 and so is including all of max_internal_pool_size. */
9397 if (((insns_len - addr)
9398 + max_internal_pool_size
9400 + mips_string_length)
9406 max_internal_pool_size -= Pmode;
9409 if (val != NULL_RTX)
9413 /* This PC relative load is out of range. ??? In the
9414 case of a string constant, we are only guessing that
9415 it is range, since we don't know the offset of a
9416 particular string constant. */
9418 lab = add_constant (&constants, val, mode);
9419 newsrc = gen_rtx (MEM, mode,
9420 gen_rtx (LABEL_REF, VOIDmode, lab));
9421 RTX_UNCHANGING_P (newsrc) = 1;
9422 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9423 SET_DEST (PATTERN (insn)),
9425 INSN_CODE (insn) = -1;
9427 if (first_constant_ref < 0)
9428 first_constant_ref = addr;
9432 addr += get_attr_length (insn);
9434 /* ??? We put switch tables in .text, but we don't define
9435 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9436 compute their lengths correctly. */
9437 if (GET_CODE (insn) == JUMP_INSN)
9441 body = PATTERN (insn);
9442 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9443 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9444 * GET_MODE_SIZE (GET_MODE (body)));
9445 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9448 if (GET_CODE (insn) == BARRIER)
9450 /* Output any constants we have accumulated. Note that we
9451 don't need to change ADDR, since its only use is
9452 subtraction from INSNS_LEN, and both would be changed by
9454 ??? If the instructions up to the next barrier reuse a
9455 constant, it would often be better to continue
9457 if (constants != NULL)
9458 dump_constants (constants, insn);
9460 first_constant_ref = -1;
9463 if (constants != NULL
9464 && (NEXT_INSN (insn) == NULL
9465 || (first_constant_ref >= 0
9466 && (((addr - first_constant_ref)
9467 + 2 /* for alignment */
9468 + 2 /* for a short jump insn */
9472 /* If we haven't had a barrier within 0x8000 bytes of a
9473 constant reference or we are at the end of the function,
9474 emit a barrier now. */
9476 rtx label, jump, barrier;
9478 label = gen_label_rtx ();
9479 jump = emit_jump_insn_after (gen_jump (label), insn);
9480 JUMP_LABEL (jump) = label;
9481 LABEL_NUSES (label) = 1;
9482 barrier = emit_barrier_after (jump);
9483 emit_label_after (label, barrier);
9484 first_constant_ref = -1;
9488 /* ??? If we output all references to a constant in internal
9489 constants table, we don't need to output the constant in the real
9490 constant table, but we have no way to prevent that. */
9493 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9495 extend_operator (x, mode)
9497 enum machine_mode mode ATTRIBUTE_UNUSED;
9499 enum rtx_code code = GET_CODE (x);
9500 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9503 /* Accept any operator that can be used to shift the high half of the
9504 input value to the lower half, suitable for truncation. The
9505 remainder (the lower half of the input, and the upper half of the
9506 output) will be discarded. */
9508 highpart_shift_operator (x, mode)
9510 enum machine_mode mode ATTRIBUTE_UNUSED;
9512 enum rtx_code code = GET_CODE (x);
9513 return (code == LSHIFTRT
9519 /* Return the length of INSN. LENGTH is the initial length computed by
9520 attributes in the machine-description file. */
9523 mips_adjust_insn_length (insn, length)
9527 /* A unconditional jump has an unfilled delay slot if it is not part
9528 of a sequence. A conditional jump normally has a delay slot, but
9529 does not on MIPS16. */
9530 if (simplejump_p (insn)
9531 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9532 || GET_CODE (insn) == CALL_INSN)))
9535 /* All MIPS16 instructions are a measly two bytes. */
9542 /* Output assembly instructions to peform a conditional branch.
9544 INSN is the branch instruction. OPERANDS[0] is the condition.
9545 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9546 of the first operand to the condition. If TWO_OPERANDS_P is
9547 non-zero the comparison takes two operands; OPERANDS[3] will be the
9550 If INVERTED_P is non-zero we are to branch if the condition does
9551 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9553 LENGTH is the length (in bytes) of the sequence we are to generate.
9554 That tells us whether to generate a simple conditional branch, or a
9555 reversed conditional branch around a `jr' instruction. */
9557 mips_output_conditional_branch (insn,
9570 static char buffer[200];
9571 /* The kind of comparison we are doing. */
9572 enum rtx_code code = GET_CODE (operands[0]);
9573 /* Non-zero if the opcode for the comparison needs a `z' indicating
9574 that it is a comparision against zero. */
9576 /* A string to use in the assembly output to represent the first
9578 const char *op1 = "%z2";
9579 /* A string to use in the assembly output to represent the second
9580 operand. Use the hard-wired zero register if there's no second
9582 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9583 /* The operand-printing string for the comparison. */
9584 const char *const comp = (float_p ? "%F0" : "%C0");
9585 /* The operand-printing string for the inverted comparison. */
9586 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9588 /* The MIPS processors (for levels of the ISA at least two), have
9589 "likely" variants of each branch instruction. These instructions
9590 annul the instruction in the delay slot if the branch is not
9592 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9594 if (!two_operands_p)
9596 /* To compute whether than A > B, for example, we normally
9597 subtract B from A and then look at the sign bit. But, if we
9598 are doing an unsigned comparison, and B is zero, we don't
9599 have to do the subtraction. Instead, we can just check to
9600 see if A is non-zero. Thus, we change the CODE here to
9601 reflect the simpler comparison operation. */
9613 /* A condition which will always be true. */
9619 /* A condition which will always be false. */
9625 /* Not a special case. */
9630 /* Relative comparisons are always done against zero. But
9631 equality comparisons are done between two operands, and therefore
9632 do not require a `z' in the assembly language output. */
9633 need_z_p = (!float_p && code != EQ && code != NE);
9634 /* For comparisons against zero, the zero is not provided
9639 /* Begin by terminating the buffer. That way we can always use
9640 strcat to add to it. */
9647 /* Just a simple conditional branch. */
9649 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9650 inverted_p ? inverted_comp : comp);
9652 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9653 inverted_p ? inverted_comp : comp,
9654 need_z_p ? "z" : "",
9662 /* Generate a reversed conditional branch around ` j'
9674 Because we have to jump four bytes *past* the following
9675 instruction if this branch was annulled, we can't just use
9676 a label, as in the picture above; there's no way to put the
9677 label after the next instruction, as the assembler does not
9678 accept `.L+4' as the target of a branch. (We can't just
9679 wait until the next instruction is output; it might be a
9680 macro and take up more than four bytes. Once again, we see
9681 why we want to eliminate macros.)
9683 If the branch is annulled, we jump four more bytes that we
9684 would otherwise; that way we skip the annulled instruction
9685 in the delay slot. */
9687 const char *const target
9688 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
9691 strcpy (buffer, "%(%<");
9692 c = strchr (buffer, '\0');
9693 /* Generate the reversed comparision. This takes four
9696 sprintf (c, "%%*b%s\t%%Z2%s",
9697 inverted_p ? comp : inverted_comp,
9700 sprintf (c, "%%*b%s%s\t%s%s,%s",
9701 inverted_p ? comp : inverted_comp,
9702 need_z_p ? "z" : "",
9706 strcat (c, "\n\tnop\n\tj\t%1");
9708 /* The delay slot was unfilled. Since we're inside
9709 .noreorder, the assembler will not fill in the NOP for
9710 us, so we must do it ourselves. */
9711 strcat (buffer, "\n\tnop");
9712 strcat (buffer, "%>%)");
9716 /* We do not currently use this code. It handles jumps to
9717 arbitrary locations, using `jr', even across a 256MB boundary.
9718 We could add a -mhuge switch, and then use this code instead of
9719 the `j' alternative above when -mhuge was used. */
9724 /* Generate a reversed conditional branch around a `jr'
9738 Not pretty, but allows a conditional branch anywhere in the
9739 32-bit address space. If the original branch is annulled,
9740 then the instruction in the delay slot should be executed
9741 only if the branch is taken. The la instruction is really
9742 a macro which will usually take eight bytes, but sometimes
9743 takes only four, if the instruction to which we're jumping
9744 gets its own entry in the global pointer table, which will
9745 happen if its a case label. The assembler will then
9746 generate only a four-byte sequence, rather than eight, and
9747 there seems to be no way to tell it not to. Thus, we can't
9748 just use a `.+x' addressing form; we don't know what value
9751 So, we resort to using the explicit relocation syntax
9752 available in the assembler and do:
9754 lw $at,%got_page(target)($gp)
9755 daddiu $at,$at,%got_ofst(target)
9757 That way, this always takes up eight bytes, and we can use
9758 the `.+x' form. Of course, these explicit machinations
9759 with relocation will not work with old assemblers. Then
9760 again, neither do out-of-range branches, so we haven't lost
9763 /* The target of the reversed branch. */
9764 const char *const target
9765 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9766 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9767 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9770 strcpy (buffer, "%(%<%[");
9771 c = strchr (buffer, '\0');
9772 /* Generate the reversed comparision. This takes four
9775 sprintf (c, "%%*b%s\t%%Z2%s",
9776 inverted_p ? comp : inverted_comp,
9779 sprintf (c, "%%*b%s%s\t%s%s,%s",
9780 inverted_p ? comp : inverted_comp,
9781 need_z_p ? "z" : "",
9785 c = strchr (buffer, '\0');
9786 /* Generate the load-address, and jump. This takes twelve
9787 bytes, for a total of 16. */
9789 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9796 /* The delay slot was unfilled. Since we're inside
9797 .noreorder, the assembler will not fill in the NOP for
9798 us, so we must do it ourselves. */
9799 strcat (buffer, "\n\tnop");
9800 strcat (buffer, "%]%>%)");
9813 /* Called to register all of our global variables with the garbage
9817 mips_add_gc_roots ()
9819 ggc_add_rtx_root (&mips_load_reg, 1);
9820 ggc_add_rtx_root (&mips_load_reg2, 1);
9821 ggc_add_rtx_root (&mips_load_reg3, 1);
9822 ggc_add_rtx_root (&mips_load_reg4, 1);
9823 ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9824 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9825 ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);
9828 static enum processor_type
9829 mips_parse_cpu (cpu_string)
9830 const char *cpu_string;
9832 const char *p = cpu_string;
9834 enum processor_type cpu;
9836 /* We need to cope with the various "vr" prefixes for the NEC 4300
9837 and 4100 processors. */
9838 if (*p == 'v' || *p == 'V')
9841 if (*p == 'r' || *p == 'R')
9844 /* Since there is no difference between a R2000 and R3000 in
9845 terms of the scheduler, we collapse them into just an R3000. */
9847 cpu = PROCESSOR_DEFAULT;
9851 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
9852 cpu = PROCESSOR_R3000;
9853 else if (!strcmp (p, "20kc") || !strcmp (p, "20Kc") )
9854 cpu = PROCESSOR_R20KC;
9858 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
9859 cpu = PROCESSOR_R3000;
9860 else if (!strcmp (p, "3900"))
9861 cpu = PROCESSOR_R3900;
9865 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
9866 cpu = PROCESSOR_R4000;
9867 /* The vr4100 is a non-FP ISA III processor with some extra
9869 else if (!strcmp (p, "4100"))
9870 cpu = PROCESSOR_R4100;
9871 /* The vr4300 is a standard ISA III processor, but with a different
9873 else if (!strcmp (p, "4300"))
9874 cpu = PROCESSOR_R4300;
9875 /* The r4400 is exactly the same as the r4000 from the compiler's
9877 else if (!strcmp (p, "4400"))
9878 cpu = PROCESSOR_R4000;
9879 else if (!strcmp (p, "4600"))
9880 cpu = PROCESSOR_R4600;
9881 else if (!strcmp (p, "4650"))
9882 cpu = PROCESSOR_R4650;
9883 /* The 4kc and 4kp processor cores are the same for
9884 scheduling purposes; they both implement the MIPS32
9885 ISA and only differ in their memory management
9887 else if (!strcmp (p, "4kc") || !strcmp (p, "4Kc")
9888 || !strcmp (p, "4kp") || !strcmp (p, "4Kp") )
9889 cpu = PROCESSOR_R4KC;
9893 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
9894 cpu = PROCESSOR_R5000;
9895 else if (!strcmp (p, "5kc") || !strcmp (p, "5Kc") )
9896 cpu = PROCESSOR_R5KC;
9900 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
9901 cpu = PROCESSOR_R6000;
9905 if (!strcmp (p, "8000"))
9906 cpu = PROCESSOR_R8000;
9910 if (!strcmp (p, "orion"))
9911 cpu = PROCESSOR_R4600;
9916 && cpu != PROCESSOR_R4300
9917 && cpu != PROCESSOR_R4100
9918 && cpu != PROCESSOR_R5000)
9919 cpu = PROCESSOR_DEFAULT;
9924 /* Adjust the cost of INSN based on the relationship between INSN that
9925 is dependent on DEP_INSN through the dependence LINK. The default
9926 is to make no adjustment to COST.
9928 On the MIPS, ignore the cost of anti- and output-dependencies. */
9930 mips_adjust_cost (insn, link, dep, cost)
9931 rtx insn ATTRIBUTE_UNUSED;
9933 rtx dep ATTRIBUTE_UNUSED;
9936 if (REG_NOTE_KIND (link) != 0)
9937 return 0; /* Anti or output dependence. */
9941 /* Cover function for UNIQUE_SECTION. */
9944 mips_unique_section (decl, reloc)
9949 const char *name, *prefix;
9951 static const char *const prefixes[4][2] = {
9952 { ".text.", ".gnu.linkonce.t." },
9953 { ".rodata.", ".gnu.linkonce.r." },
9954 { ".data.", ".gnu.linkonce.d." },
9955 { ".sdata.", ".gnu.linkonce.s." }
9958 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9959 size = int_size_in_bytes (TREE_TYPE (decl));
9961 /* Determine the base section we are interested in:
9962 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
9963 if (TREE_CODE (decl) == FUNCTION_DECL)
9965 else if (DECL_INITIAL (decl) == 0
9966 || DECL_INITIAL (decl) == error_mark_node)
9968 else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
9969 && TREE_CODE (decl) == STRING_CST
9970 && !flag_writable_strings)
9972 /* For embedded position independent code, put constant
9973 strings in the text section, because the data section
9974 is limited to 64K in size. For mips16 code, put
9975 strings in the text section so that a PC relative load
9976 instruction can be used to get their address. */
9979 else if (TARGET_EMBEDDED_DATA)
9981 /* For embedded applications, always put an object in
9982 read-only data if possible, in order to reduce RAM
9985 if (DECL_READONLY_SECTION (decl, reloc))
9987 else if (size > 0 && size <= mips_section_threshold)
9994 /* For hosted applications, always put an object in
9995 small data if possible, as this gives the best
9998 if (size > 0 && size <= mips_section_threshold)
10000 else if (DECL_READONLY_SECTION (decl, reloc))
10006 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
10007 len = strlen (name) + strlen (prefix);
10008 string = alloca (len + 1);
10009 sprintf (string, "%s%s", prefix, name);
10011 DECL_SECTION_NAME (decl) = build_string (len, string);
10015 mips_hard_regno_nregs (regno, mode)
10017 enum machine_mode mode;
10019 if (! FP_REG_P (regno))
10020 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10022 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10026 #ifdef TARGET_IRIX6
10027 /* Output assembly to switch to section NAME with attribute FLAGS. */
10030 iris6_asm_named_section_1 (name, flags, align)
10032 unsigned int flags;
10033 unsigned int align;
10035 unsigned int sh_type, sh_flags, sh_entsize;
10038 if (!(flags & SECTION_DEBUG))
10039 sh_flags |= 2; /* SHF_ALLOC */
10040 if (flags & SECTION_WRITE)
10041 sh_flags |= 1; /* SHF_WRITE */
10042 if (flags & SECTION_CODE)
10043 sh_flags |= 4; /* SHF_EXECINSTR */
10044 if (flags & SECTION_SMALL)
10045 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
10046 if (strcmp (name, ".debug_frame") == 0)
10047 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
10048 if (flags & SECTION_DEBUG)
10049 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
10050 else if (flags & SECTION_BSS)
10051 sh_type = 8; /* SHT_NOBITS */
10053 sh_type = 1; /* SHT_PROGBITS */
10055 if (flags & SECTION_CODE)
10060 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
10061 name, sh_type, sh_flags, sh_entsize, align);
10065 iris6_asm_named_section (name, flags)
10067 unsigned int flags;
10069 if (TARGET_FILE_SWITCHING && (flags & SECTION_CODE))
10070 asm_out_file = asm_out_text_file;
10071 iris6_asm_named_section_1 (name, flags, 0);
10074 /* In addition to emitting a .align directive, record the maximum
10075 alignment requested for the current section. */
10077 struct iris_section_align_entry
10081 unsigned int flags;
10084 static htab_t iris_section_align_htab;
10085 static FILE *iris_orig_asm_out_file;
10088 iris_section_align_entry_eq (p1, p2)
10092 const struct iris_section_align_entry *old = p1;
10093 const char *new = p2;
10095 return strcmp (old->name, new) == 0;
10099 iris_section_align_entry_hash (p)
10102 const struct iris_section_align_entry *old = p;
10103 return htab_hash_string (old->name);
10107 iris6_asm_output_align (file, log)
10111 const char *section = current_section_name ();
10112 struct iris_section_align_entry **slot, *entry;
10117 slot = (struct iris_section_align_entry **)
10118 htab_find_slot_with_hash (iris_section_align_htab, section,
10119 htab_hash_string (section), INSERT);
10123 entry = (struct iris_section_align_entry *)
10124 xmalloc (sizeof (struct iris_section_align_entry));
10126 entry->name = section;
10128 entry->flags = current_section_flags ();
10130 else if (entry->log < log)
10133 fprintf (file, "\t.align\t%u\n", log);
10136 /* The Iris assembler does not record alignment from .align directives,
10137 but takes it from the first .section directive seen. Play yet more
10138 file switching games so that we can emit a .section directive at the
10139 beginning of the file with the proper alignment attached. */
10142 iris6_asm_file_start (stream)
10145 mips_asm_file_start (stream);
10147 iris_orig_asm_out_file = asm_out_file;
10148 stream = tmpfile ();
10149 asm_out_file = stream;
10150 asm_out_data_file = stream;
10151 if (! TARGET_FILE_SWITCHING)
10152 asm_out_text_file = stream;
10154 iris_section_align_htab = htab_create (31, iris_section_align_entry_hash,
10155 iris_section_align_entry_eq, NULL);
10159 iris6_section_align_1 (slot, data)
10161 void *data ATTRIBUTE_UNUSED;
10163 const struct iris_section_align_entry *entry
10164 = *(const struct iris_section_align_entry **) slot;
10166 iris6_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
10171 iris6_asm_file_end (stream)
10174 /* Emit section directives with the proper alignment at the top of the
10175 real output file. */
10176 asm_out_file = iris_orig_asm_out_file;
10177 htab_traverse (iris_section_align_htab, iris6_section_align_1, NULL);
10179 /* Copy the data emitted to the temp file to the real output file. */
10180 copy_file_data (asm_out_file, stream);
10182 mips_asm_file_end (stream);
10184 #endif /* TARGET_IRIX6 */