1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
140 A signed 16-bit constant address.
143 A constant symbolic address. */
144 enum mips_address_type {
151 /* Enumerates the setting of the -mr10k-cache-barrier option. */
152 enum mips_r10k_cache_barrier_setting {
153 R10K_CACHE_BARRIER_NONE,
154 R10K_CACHE_BARRIER_STORE,
155 R10K_CACHE_BARRIER_LOAD_STORE
158 /* Macros to create an enumeration identifier for a function prototype. */
159 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
160 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
161 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
162 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
164 /* Classifies the prototype of a built-in function. */
165 enum mips_function_type {
166 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
167 #include "config/mips/mips-ftypes.def"
168 #undef DEF_MIPS_FTYPE
172 /* Specifies how a built-in function should be converted into rtl. */
173 enum mips_builtin_type {
174 /* The function corresponds directly to an .md pattern. The return
175 value is mapped to operand 0 and the arguments are mapped to
176 operands 1 and above. */
179 /* The function corresponds directly to an .md pattern. There is no return
180 value and the arguments are mapped to operands 0 and above. */
181 MIPS_BUILTIN_DIRECT_NO_TARGET,
183 /* The function corresponds to a comparison instruction followed by
184 a mips_cond_move_tf_ps pattern. The first two arguments are the
185 values to compare and the second two arguments are the vector
186 operands for the movt.ps or movf.ps instruction (in assembly order). */
190 /* The function corresponds to a V2SF comparison instruction. Operand 0
191 of this instruction is the result of the comparison, which has mode
192 CCV2 or CCV4. The function arguments are mapped to operands 1 and
193 above. The function's return value is an SImode boolean that is
194 true under the following conditions:
196 MIPS_BUILTIN_CMP_ANY: one of the registers is true
197 MIPS_BUILTIN_CMP_ALL: all of the registers are true
198 MIPS_BUILTIN_CMP_LOWER: the first register is true
199 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
200 MIPS_BUILTIN_CMP_ANY,
201 MIPS_BUILTIN_CMP_ALL,
202 MIPS_BUILTIN_CMP_UPPER,
203 MIPS_BUILTIN_CMP_LOWER,
205 /* As above, but the instruction only sets a single $fcc register. */
206 MIPS_BUILTIN_CMP_SINGLE,
208 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
209 MIPS_BUILTIN_BPOSGE32
212 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
213 #define MIPS_FP_CONDITIONS(MACRO) \
231 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
232 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
233 enum mips_fp_condition {
234 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
237 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
238 #define STRINGIFY(X) #X
239 static const char *const mips_fp_conditions[] = {
240 MIPS_FP_CONDITIONS (STRINGIFY)
243 /* Information about a function's frame layout. */
244 struct GTY(()) mips_frame_info {
245 /* The size of the frame in bytes. */
246 HOST_WIDE_INT total_size;
248 /* The number of bytes allocated to variables. */
249 HOST_WIDE_INT var_size;
251 /* The number of bytes allocated to outgoing function arguments. */
252 HOST_WIDE_INT args_size;
254 /* The number of bytes allocated to the .cprestore slot, or 0 if there
256 HOST_WIDE_INT cprestore_size;
258 /* Bit X is set if the function saves or restores GPR X. */
261 /* Likewise FPR X. */
264 /* Likewise doubleword accumulator X ($acX). */
265 unsigned int acc_mask;
267 /* The number of GPRs, FPRs, doubleword accumulators and COP0
271 unsigned int num_acc;
272 unsigned int num_cop0_regs;
274 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
275 save slots from the top of the frame, or zero if no such slots are
277 HOST_WIDE_INT gp_save_offset;
278 HOST_WIDE_INT fp_save_offset;
279 HOST_WIDE_INT acc_save_offset;
280 HOST_WIDE_INT cop0_save_offset;
282 /* Likewise, but giving offsets from the bottom of the frame. */
283 HOST_WIDE_INT gp_sp_offset;
284 HOST_WIDE_INT fp_sp_offset;
285 HOST_WIDE_INT acc_sp_offset;
286 HOST_WIDE_INT cop0_sp_offset;
288 /* The offset of arg_pointer_rtx from the bottom of the frame. */
289 HOST_WIDE_INT arg_pointer_offset;
291 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
292 HOST_WIDE_INT hard_frame_pointer_offset;
295 struct GTY(()) machine_function {
296 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
297 rtx mips16_gp_pseudo_rtx;
299 /* The number of extra stack bytes taken up by register varargs.
300 This area is allocated by the callee at the very top of the frame. */
303 /* The current frame information, calculated by mips_compute_frame_info. */
304 struct mips_frame_info frame;
306 /* The register to use as the function's global pointer, or INVALID_REGNUM
307 if the function doesn't need one. */
308 unsigned int global_pointer;
310 /* True if mips_adjust_insn_length should ignore an instruction's
312 bool ignore_hazard_length_p;
314 /* True if the whole function is suitable for .set noreorder and
316 bool all_noreorder_p;
318 /* True if the function is known to have an instruction that needs $gp. */
321 /* True if we have emitted an instruction to initialize
322 mips16_gp_pseudo_rtx. */
323 bool initialized_mips16_gp_pseudo_p;
325 /* True if this is an interrupt handler. */
326 bool interrupt_handler_p;
328 /* True if this is an interrupt handler that uses shadow registers. */
329 bool use_shadow_register_set_p;
331 /* True if this is an interrupt handler that should keep interrupts
333 bool keep_interrupts_masked_p;
335 /* True if this is an interrupt handler that should use DERET
337 bool use_debug_exception_return_p;
340 /* Information about a single argument. */
341 struct mips_arg_info {
342 /* True if the argument is passed in a floating-point register, or
343 would have been if we hadn't run out of registers. */
346 /* The number of words passed in registers, rounded up. */
347 unsigned int reg_words;
349 /* For EABI, the offset of the first register from GP_ARG_FIRST or
350 FP_ARG_FIRST. For other ABIs, the offset of the first register from
351 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
352 comment for details).
354 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
356 unsigned int reg_offset;
358 /* The number of words that must be passed on the stack, rounded up. */
359 unsigned int stack_words;
361 /* The offset from the start of the stack overflow area of the argument's
362 first stack word. Only meaningful when STACK_WORDS is nonzero. */
363 unsigned int stack_offset;
366 /* Information about an address described by mips_address_type.
372 REG is the base register and OFFSET is the constant offset.
375 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
376 is the type of symbol it references.
379 SYMBOL_TYPE is the type of symbol that the address references. */
380 struct mips_address_info {
381 enum mips_address_type type;
384 enum mips_symbol_type symbol_type;
387 /* One stage in a constant building sequence. These sequences have
391 A = A CODE[1] VALUE[1]
392 A = A CODE[2] VALUE[2]
395 where A is an accumulator, each CODE[i] is a binary rtl operation
396 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
397 struct mips_integer_op {
399 unsigned HOST_WIDE_INT value;
402 /* The largest number of operations needed to load an integer constant.
403 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
404 When the lowest bit is clear, we can try, but reject a sequence with
405 an extra SLL at the end. */
406 #define MIPS_MAX_INTEGER_OPS 7
408 /* Information about a MIPS16e SAVE or RESTORE instruction. */
409 struct mips16e_save_restore_info {
410 /* The number of argument registers saved by a SAVE instruction.
411 0 for RESTORE instructions. */
414 /* Bit X is set if the instruction saves or restores GPR X. */
417 /* The total number of bytes to allocate. */
421 /* Global variables for machine-dependent things. */
423 /* The -G setting, or the configuration's default small-data limit if
424 no -G option is given. */
425 static unsigned int mips_small_data_threshold;
427 /* The number of file directives written by mips_output_filename. */
428 int num_source_filenames;
430 /* The name that appeared in the last .file directive written by
431 mips_output_filename, or "" if mips_output_filename hasn't
432 written anything yet. */
433 const char *current_function_file = "";
435 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
438 /* Arrays that map GCC register numbers to debugger register numbers. */
439 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
440 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
442 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
447 /* True if we're writing out a branch-likely instruction rather than a
449 static bool mips_branch_likely;
451 /* The operands passed to the last cmpMM expander. */
454 /* The current instruction-set architecture. */
455 enum processor_type mips_arch;
456 const struct mips_cpu_info *mips_arch_info;
458 /* The processor that we should tune the code for. */
459 enum processor_type mips_tune;
460 const struct mips_cpu_info *mips_tune_info;
462 /* The ISA level associated with mips_arch. */
465 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
466 static const struct mips_cpu_info *mips_isa_option_info;
468 /* Which ABI to use. */
469 int mips_abi = MIPS_ABI_DEFAULT;
471 /* Which cost information to use. */
472 const struct mips_rtx_cost_data *mips_cost;
474 /* The ambient target flags, excluding MASK_MIPS16. */
475 static int mips_base_target_flags;
477 /* True if MIPS16 is the default mode. */
478 bool mips_base_mips16;
480 /* The ambient values of other global variables. */
481 static int mips_base_schedule_insns; /* flag_schedule_insns */
482 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
483 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
484 static int mips_base_align_loops; /* align_loops */
485 static int mips_base_align_jumps; /* align_jumps */
486 static int mips_base_align_functions; /* align_functions */
488 /* The -mcode-readable setting. */
489 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
491 /* The -mr10k-cache-barrier setting. */
492 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
494 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
495 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
497 /* Index C is true if character C is a valid PRINT_OPERAND punctation
499 bool mips_print_operand_punct[256];
501 static GTY (()) int mips_output_filename_first_time = 1;
503 /* mips_split_p[X] is true if symbols of type X can be split by
504 mips_split_symbol. */
505 bool mips_split_p[NUM_SYMBOL_TYPES];
507 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
508 can be split by mips_split_symbol. */
509 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
511 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
512 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
513 if they are matched by a special .md file pattern. */
514 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
516 /* Likewise for HIGHs. */
517 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
519 /* Index R is the smallest register class that contains register R. */
520 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
521 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
522 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
523 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
524 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
525 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
526 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
527 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
528 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
529 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
530 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
531 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
532 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
533 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
534 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
535 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
536 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
537 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
538 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
539 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
540 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
541 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
542 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
543 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
544 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
545 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
546 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
547 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
548 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
549 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
550 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
551 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
552 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
553 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
554 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
555 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
556 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
557 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
558 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
559 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
560 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
561 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
562 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
563 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
564 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
565 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
566 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
567 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
570 /* The value of TARGET_ATTRIBUTE_TABLE. */
571 const struct attribute_spec mips_attribute_table[] = {
572 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
573 { "long_call", 0, 0, false, true, true, NULL },
574 { "far", 0, 0, false, true, true, NULL },
575 { "near", 0, 0, false, true, true, NULL },
576 /* We would really like to treat "mips16" and "nomips16" as type
577 attributes, but GCC doesn't provide the hooks we need to support
578 the right conversion rules. As declaration attributes, they affect
579 code generation but don't carry other semantics. */
580 { "mips16", 0, 0, true, false, false, NULL },
581 { "nomips16", 0, 0, true, false, false, NULL },
582 /* Allow functions to be specified as interrupt handlers */
583 { "interrupt", 0, 0, false, true, true, NULL },
584 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
585 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
586 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
587 { NULL, 0, 0, false, false, false, NULL }
590 /* A table describing all the processors GCC knows about. Names are
591 matched in the order listed. The first mention of an ISA level is
592 taken as the canonical name for that ISA.
594 To ease comparison, please keep this table in the same order
595 as GAS's mips_cpu_info_table. Please also make sure that
596 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
597 options correctly. */
598 static const struct mips_cpu_info mips_cpu_info_table[] = {
599 /* Entries for generic ISAs. */
600 { "mips1", PROCESSOR_R3000, 1, 0 },
601 { "mips2", PROCESSOR_R6000, 2, 0 },
602 { "mips3", PROCESSOR_R4000, 3, 0 },
603 { "mips4", PROCESSOR_R8000, 4, 0 },
604 /* Prefer not to use branch-likely instructions for generic MIPS32rX
605 and MIPS64rX code. The instructions were officially deprecated
606 in revisions 2 and earlier, but revision 3 is likely to downgrade
607 that to a recommendation to avoid the instructions in code that
608 isn't tuned to a specific processor. */
609 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
610 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
611 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
612 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
613 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
615 /* MIPS I processors. */
616 { "r3000", PROCESSOR_R3000, 1, 0 },
617 { "r2000", PROCESSOR_R3000, 1, 0 },
618 { "r3900", PROCESSOR_R3900, 1, 0 },
620 /* MIPS II processors. */
621 { "r6000", PROCESSOR_R6000, 2, 0 },
623 /* MIPS III processors. */
624 { "r4000", PROCESSOR_R4000, 3, 0 },
625 { "vr4100", PROCESSOR_R4100, 3, 0 },
626 { "vr4111", PROCESSOR_R4111, 3, 0 },
627 { "vr4120", PROCESSOR_R4120, 3, 0 },
628 { "vr4130", PROCESSOR_R4130, 3, 0 },
629 { "vr4300", PROCESSOR_R4300, 3, 0 },
630 { "r4400", PROCESSOR_R4000, 3, 0 },
631 { "r4600", PROCESSOR_R4600, 3, 0 },
632 { "orion", PROCESSOR_R4600, 3, 0 },
633 { "r4650", PROCESSOR_R4650, 3, 0 },
634 /* ST Loongson 2E/2F processors. */
635 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
636 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
638 /* MIPS IV processors. */
639 { "r8000", PROCESSOR_R8000, 4, 0 },
640 { "r10000", PROCESSOR_R10000, 4, 0 },
641 { "r12000", PROCESSOR_R10000, 4, 0 },
642 { "r14000", PROCESSOR_R10000, 4, 0 },
643 { "r16000", PROCESSOR_R10000, 4, 0 },
644 { "vr5000", PROCESSOR_R5000, 4, 0 },
645 { "vr5400", PROCESSOR_R5400, 4, 0 },
646 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
647 { "rm7000", PROCESSOR_R7000, 4, 0 },
648 { "rm9000", PROCESSOR_R9000, 4, 0 },
650 /* MIPS32 processors. */
651 { "4kc", PROCESSOR_4KC, 32, 0 },
652 { "4km", PROCESSOR_4KC, 32, 0 },
653 { "4kp", PROCESSOR_4KP, 32, 0 },
654 { "4ksc", PROCESSOR_4KC, 32, 0 },
656 /* MIPS32 Release 2 processors. */
657 { "m4k", PROCESSOR_M4K, 33, 0 },
658 { "4kec", PROCESSOR_4KC, 33, 0 },
659 { "4kem", PROCESSOR_4KC, 33, 0 },
660 { "4kep", PROCESSOR_4KP, 33, 0 },
661 { "4ksd", PROCESSOR_4KC, 33, 0 },
663 { "24kc", PROCESSOR_24KC, 33, 0 },
664 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
665 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
666 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
667 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
668 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
670 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
671 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
672 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
673 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
674 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
675 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
677 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
678 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
679 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
680 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
681 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
682 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
684 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
685 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
686 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
687 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
688 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
689 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
690 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
692 /* MIPS64 processors. */
693 { "5kc", PROCESSOR_5KC, 64, 0 },
694 { "5kf", PROCESSOR_5KF, 64, 0 },
695 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
696 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
697 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
698 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
699 { "xlr", PROCESSOR_XLR, 64, 0 },
701 /* MIPS64 Release 2 processors. */
702 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
705 /* Default costs. If these are used for a processor we should look
706 up the actual costs. */
707 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
708 COSTS_N_INSNS (7), /* fp_mult_sf */ \
709 COSTS_N_INSNS (8), /* fp_mult_df */ \
710 COSTS_N_INSNS (23), /* fp_div_sf */ \
711 COSTS_N_INSNS (36), /* fp_div_df */ \
712 COSTS_N_INSNS (10), /* int_mult_si */ \
713 COSTS_N_INSNS (10), /* int_mult_di */ \
714 COSTS_N_INSNS (69), /* int_div_si */ \
715 COSTS_N_INSNS (69), /* int_div_di */ \
716 2, /* branch_cost */ \
717 4 /* memory_latency */
719 /* Floating-point costs for processors without an FPU. Just assume that
720 all floating-point libcalls are very expensive. */
721 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
722 COSTS_N_INSNS (256), /* fp_mult_sf */ \
723 COSTS_N_INSNS (256), /* fp_mult_df */ \
724 COSTS_N_INSNS (256), /* fp_div_sf */ \
725 COSTS_N_INSNS (256) /* fp_div_df */
727 /* Costs to use when optimizing for size. */
728 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
729 COSTS_N_INSNS (1), /* fp_add */
730 COSTS_N_INSNS (1), /* fp_mult_sf */
731 COSTS_N_INSNS (1), /* fp_mult_df */
732 COSTS_N_INSNS (1), /* fp_div_sf */
733 COSTS_N_INSNS (1), /* fp_div_df */
734 COSTS_N_INSNS (1), /* int_mult_si */
735 COSTS_N_INSNS (1), /* int_mult_di */
736 COSTS_N_INSNS (1), /* int_div_si */
737 COSTS_N_INSNS (1), /* int_div_di */
739 4 /* memory_latency */
742 /* Costs to use when optimizing for speed, indexed by processor. */
743 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
745 COSTS_N_INSNS (2), /* fp_add */
746 COSTS_N_INSNS (4), /* fp_mult_sf */
747 COSTS_N_INSNS (5), /* fp_mult_df */
748 COSTS_N_INSNS (12), /* fp_div_sf */
749 COSTS_N_INSNS (19), /* fp_div_df */
750 COSTS_N_INSNS (12), /* int_mult_si */
751 COSTS_N_INSNS (12), /* int_mult_di */
752 COSTS_N_INSNS (35), /* int_div_si */
753 COSTS_N_INSNS (35), /* int_div_di */
755 4 /* memory_latency */
759 COSTS_N_INSNS (6), /* int_mult_si */
760 COSTS_N_INSNS (6), /* int_mult_di */
761 COSTS_N_INSNS (36), /* int_div_si */
762 COSTS_N_INSNS (36), /* int_div_di */
764 4 /* memory_latency */
768 COSTS_N_INSNS (36), /* int_mult_si */
769 COSTS_N_INSNS (36), /* int_mult_di */
770 COSTS_N_INSNS (37), /* int_div_si */
771 COSTS_N_INSNS (37), /* int_div_di */
773 4 /* memory_latency */
777 COSTS_N_INSNS (4), /* int_mult_si */
778 COSTS_N_INSNS (11), /* int_mult_di */
779 COSTS_N_INSNS (36), /* int_div_si */
780 COSTS_N_INSNS (68), /* int_div_di */
782 4 /* memory_latency */
785 COSTS_N_INSNS (4), /* fp_add */
786 COSTS_N_INSNS (4), /* fp_mult_sf */
787 COSTS_N_INSNS (5), /* fp_mult_df */
788 COSTS_N_INSNS (17), /* fp_div_sf */
789 COSTS_N_INSNS (32), /* fp_div_df */
790 COSTS_N_INSNS (4), /* int_mult_si */
791 COSTS_N_INSNS (11), /* int_mult_di */
792 COSTS_N_INSNS (36), /* int_div_si */
793 COSTS_N_INSNS (68), /* int_div_di */
795 4 /* memory_latency */
798 COSTS_N_INSNS (4), /* fp_add */
799 COSTS_N_INSNS (4), /* fp_mult_sf */
800 COSTS_N_INSNS (5), /* fp_mult_df */
801 COSTS_N_INSNS (17), /* fp_div_sf */
802 COSTS_N_INSNS (32), /* fp_div_df */
803 COSTS_N_INSNS (4), /* int_mult_si */
804 COSTS_N_INSNS (7), /* int_mult_di */
805 COSTS_N_INSNS (42), /* int_div_si */
806 COSTS_N_INSNS (72), /* int_div_di */
808 4 /* memory_latency */
812 COSTS_N_INSNS (5), /* int_mult_si */
813 COSTS_N_INSNS (5), /* int_mult_di */
814 COSTS_N_INSNS (41), /* int_div_si */
815 COSTS_N_INSNS (41), /* int_div_di */
817 4 /* memory_latency */
820 COSTS_N_INSNS (8), /* fp_add */
821 COSTS_N_INSNS (8), /* fp_mult_sf */
822 COSTS_N_INSNS (10), /* fp_mult_df */
823 COSTS_N_INSNS (34), /* fp_div_sf */
824 COSTS_N_INSNS (64), /* fp_div_df */
825 COSTS_N_INSNS (5), /* int_mult_si */
826 COSTS_N_INSNS (5), /* int_mult_di */
827 COSTS_N_INSNS (41), /* int_div_si */
828 COSTS_N_INSNS (41), /* int_div_di */
830 4 /* memory_latency */
833 COSTS_N_INSNS (4), /* fp_add */
834 COSTS_N_INSNS (4), /* fp_mult_sf */
835 COSTS_N_INSNS (5), /* fp_mult_df */
836 COSTS_N_INSNS (17), /* fp_div_sf */
837 COSTS_N_INSNS (32), /* fp_div_df */
838 COSTS_N_INSNS (5), /* int_mult_si */
839 COSTS_N_INSNS (5), /* int_mult_di */
840 COSTS_N_INSNS (41), /* int_div_si */
841 COSTS_N_INSNS (41), /* int_div_di */
843 4 /* memory_latency */
847 COSTS_N_INSNS (5), /* int_mult_si */
848 COSTS_N_INSNS (5), /* int_mult_di */
849 COSTS_N_INSNS (41), /* int_div_si */
850 COSTS_N_INSNS (41), /* int_div_di */
852 4 /* memory_latency */
855 COSTS_N_INSNS (8), /* fp_add */
856 COSTS_N_INSNS (8), /* fp_mult_sf */
857 COSTS_N_INSNS (10), /* fp_mult_df */
858 COSTS_N_INSNS (34), /* fp_div_sf */
859 COSTS_N_INSNS (64), /* fp_div_df */
860 COSTS_N_INSNS (5), /* int_mult_si */
861 COSTS_N_INSNS (5), /* int_mult_di */
862 COSTS_N_INSNS (41), /* int_div_si */
863 COSTS_N_INSNS (41), /* int_div_di */
865 4 /* memory_latency */
868 COSTS_N_INSNS (4), /* fp_add */
869 COSTS_N_INSNS (4), /* fp_mult_sf */
870 COSTS_N_INSNS (5), /* fp_mult_df */
871 COSTS_N_INSNS (17), /* fp_div_sf */
872 COSTS_N_INSNS (32), /* fp_div_df */
873 COSTS_N_INSNS (5), /* int_mult_si */
874 COSTS_N_INSNS (5), /* int_mult_di */
875 COSTS_N_INSNS (41), /* int_div_si */
876 COSTS_N_INSNS (41), /* int_div_di */
878 4 /* memory_latency */
881 COSTS_N_INSNS (6), /* fp_add */
882 COSTS_N_INSNS (6), /* fp_mult_sf */
883 COSTS_N_INSNS (7), /* fp_mult_df */
884 COSTS_N_INSNS (25), /* fp_div_sf */
885 COSTS_N_INSNS (48), /* fp_div_df */
886 COSTS_N_INSNS (5), /* int_mult_si */
887 COSTS_N_INSNS (5), /* int_mult_di */
888 COSTS_N_INSNS (41), /* int_div_si */
889 COSTS_N_INSNS (41), /* int_div_di */
891 4 /* memory_latency */
905 COSTS_N_INSNS (5), /* int_mult_si */
906 COSTS_N_INSNS (5), /* int_mult_di */
907 COSTS_N_INSNS (72), /* int_div_si */
908 COSTS_N_INSNS (72), /* int_div_di */
910 4 /* memory_latency */
913 COSTS_N_INSNS (2), /* fp_add */
914 COSTS_N_INSNS (4), /* fp_mult_sf */
915 COSTS_N_INSNS (5), /* fp_mult_df */
916 COSTS_N_INSNS (12), /* fp_div_sf */
917 COSTS_N_INSNS (19), /* fp_div_df */
918 COSTS_N_INSNS (2), /* int_mult_si */
919 COSTS_N_INSNS (2), /* int_mult_di */
920 COSTS_N_INSNS (35), /* int_div_si */
921 COSTS_N_INSNS (35), /* int_div_di */
923 4 /* memory_latency */
926 COSTS_N_INSNS (3), /* fp_add */
927 COSTS_N_INSNS (5), /* fp_mult_sf */
928 COSTS_N_INSNS (6), /* fp_mult_df */
929 COSTS_N_INSNS (15), /* fp_div_sf */
930 COSTS_N_INSNS (16), /* fp_div_df */
931 COSTS_N_INSNS (17), /* int_mult_si */
932 COSTS_N_INSNS (17), /* int_mult_di */
933 COSTS_N_INSNS (38), /* int_div_si */
934 COSTS_N_INSNS (38), /* int_div_di */
936 6 /* memory_latency */
939 COSTS_N_INSNS (6), /* fp_add */
940 COSTS_N_INSNS (7), /* fp_mult_sf */
941 COSTS_N_INSNS (8), /* fp_mult_df */
942 COSTS_N_INSNS (23), /* fp_div_sf */
943 COSTS_N_INSNS (36), /* fp_div_df */
944 COSTS_N_INSNS (10), /* int_mult_si */
945 COSTS_N_INSNS (10), /* int_mult_di */
946 COSTS_N_INSNS (69), /* int_div_si */
947 COSTS_N_INSNS (69), /* int_div_di */
949 6 /* memory_latency */
961 /* The only costs that appear to be updated here are
962 integer multiplication. */
964 COSTS_N_INSNS (4), /* int_mult_si */
965 COSTS_N_INSNS (6), /* int_mult_di */
966 COSTS_N_INSNS (69), /* int_div_si */
967 COSTS_N_INSNS (69), /* int_div_di */
969 4 /* memory_latency */
981 COSTS_N_INSNS (6), /* fp_add */
982 COSTS_N_INSNS (4), /* fp_mult_sf */
983 COSTS_N_INSNS (5), /* fp_mult_df */
984 COSTS_N_INSNS (23), /* fp_div_sf */
985 COSTS_N_INSNS (36), /* fp_div_df */
986 COSTS_N_INSNS (5), /* int_mult_si */
987 COSTS_N_INSNS (5), /* int_mult_di */
988 COSTS_N_INSNS (36), /* int_div_si */
989 COSTS_N_INSNS (36), /* int_div_di */
991 4 /* memory_latency */
994 COSTS_N_INSNS (6), /* fp_add */
995 COSTS_N_INSNS (5), /* fp_mult_sf */
996 COSTS_N_INSNS (6), /* fp_mult_df */
997 COSTS_N_INSNS (30), /* fp_div_sf */
998 COSTS_N_INSNS (59), /* fp_div_df */
999 COSTS_N_INSNS (3), /* int_mult_si */
1000 COSTS_N_INSNS (4), /* int_mult_di */
1001 COSTS_N_INSNS (42), /* int_div_si */
1002 COSTS_N_INSNS (74), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (5), /* fp_mult_sf */
1009 COSTS_N_INSNS (6), /* fp_mult_df */
1010 COSTS_N_INSNS (30), /* fp_div_sf */
1011 COSTS_N_INSNS (59), /* fp_div_df */
1012 COSTS_N_INSNS (5), /* int_mult_si */
1013 COSTS_N_INSNS (9), /* int_mult_di */
1014 COSTS_N_INSNS (42), /* int_div_si */
1015 COSTS_N_INSNS (74), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1020 /* The only costs that are changed here are
1021 integer multiplication. */
1022 COSTS_N_INSNS (6), /* fp_add */
1023 COSTS_N_INSNS (7), /* fp_mult_sf */
1024 COSTS_N_INSNS (8), /* fp_mult_df */
1025 COSTS_N_INSNS (23), /* fp_div_sf */
1026 COSTS_N_INSNS (36), /* fp_div_df */
1027 COSTS_N_INSNS (5), /* int_mult_si */
1028 COSTS_N_INSNS (9), /* int_mult_di */
1029 COSTS_N_INSNS (69), /* int_div_si */
1030 COSTS_N_INSNS (69), /* int_div_di */
1031 1, /* branch_cost */
1032 4 /* memory_latency */
1038 /* The only costs that are changed here are
1039 integer multiplication. */
1040 COSTS_N_INSNS (6), /* fp_add */
1041 COSTS_N_INSNS (7), /* fp_mult_sf */
1042 COSTS_N_INSNS (8), /* fp_mult_df */
1043 COSTS_N_INSNS (23), /* fp_div_sf */
1044 COSTS_N_INSNS (36), /* fp_div_df */
1045 COSTS_N_INSNS (3), /* int_mult_si */
1046 COSTS_N_INSNS (8), /* int_mult_di */
1047 COSTS_N_INSNS (69), /* int_div_si */
1048 COSTS_N_INSNS (69), /* int_div_di */
1049 1, /* branch_cost */
1050 4 /* memory_latency */
1053 COSTS_N_INSNS (2), /* fp_add */
1054 COSTS_N_INSNS (2), /* fp_mult_sf */
1055 COSTS_N_INSNS (2), /* fp_mult_df */
1056 COSTS_N_INSNS (12), /* fp_div_sf */
1057 COSTS_N_INSNS (19), /* fp_div_df */
1058 COSTS_N_INSNS (5), /* int_mult_si */
1059 COSTS_N_INSNS (9), /* int_mult_di */
1060 COSTS_N_INSNS (34), /* int_div_si */
1061 COSTS_N_INSNS (66), /* int_div_di */
1062 1, /* branch_cost */
1063 4 /* memory_latency */
1066 /* These costs are the same as the SB-1A below. */
1067 COSTS_N_INSNS (4), /* fp_add */
1068 COSTS_N_INSNS (4), /* fp_mult_sf */
1069 COSTS_N_INSNS (4), /* fp_mult_df */
1070 COSTS_N_INSNS (24), /* fp_div_sf */
1071 COSTS_N_INSNS (32), /* fp_div_df */
1072 COSTS_N_INSNS (3), /* int_mult_si */
1073 COSTS_N_INSNS (4), /* int_mult_di */
1074 COSTS_N_INSNS (36), /* int_div_si */
1075 COSTS_N_INSNS (68), /* int_div_di */
1076 1, /* branch_cost */
1077 4 /* memory_latency */
1080 /* These costs are the same as the SB-1 above. */
1081 COSTS_N_INSNS (4), /* fp_add */
1082 COSTS_N_INSNS (4), /* fp_mult_sf */
1083 COSTS_N_INSNS (4), /* fp_mult_df */
1084 COSTS_N_INSNS (24), /* fp_div_sf */
1085 COSTS_N_INSNS (32), /* fp_div_df */
1086 COSTS_N_INSNS (3), /* int_mult_si */
1087 COSTS_N_INSNS (4), /* int_mult_di */
1088 COSTS_N_INSNS (36), /* int_div_si */
1089 COSTS_N_INSNS (68), /* int_div_di */
1090 1, /* branch_cost */
1091 4 /* memory_latency */
1098 COSTS_N_INSNS (8), /* int_mult_si */
1099 COSTS_N_INSNS (8), /* int_mult_di */
1100 COSTS_N_INSNS (72), /* int_div_si */
1101 COSTS_N_INSNS (72), /* int_div_di */
1102 1, /* branch_cost */
1103 4 /* memory_latency */
1107 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1108 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1109 struct GTY (()) mflip_mips16_entry {
1113 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1115 /* Hash table callbacks for mflip_mips16_htab. */
1118 mflip_mips16_htab_hash (const void *entry)
1120 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1124 mflip_mips16_htab_eq (const void *entry, const void *name)
1126 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1127 (const char *) name) == 0;
1130 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1131 mode, false if it should next add an attribute for the opposite mode. */
1132 static GTY(()) bool mips16_flipper;
1134 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1135 for -mflip-mips16. Return true if it should use "mips16" and false if
1136 it should use "nomips16". */
1139 mflip_mips16_use_mips16_p (tree decl)
1141 struct mflip_mips16_entry *entry;
1146 /* Use the opposite of the command-line setting for anonymous decls. */
1147 if (!DECL_NAME (decl))
1148 return !mips_base_mips16;
1150 if (!mflip_mips16_htab)
1151 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1152 mflip_mips16_htab_eq, NULL);
1154 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1155 hash = htab_hash_string (name);
1156 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1157 entry = (struct mflip_mips16_entry *) *slot;
1160 mips16_flipper = !mips16_flipper;
1161 entry = GGC_NEW (struct mflip_mips16_entry);
1163 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1166 return entry->mips16_p;
1169 /* Predicates to test for presence of "near" and "far"/"long_call"
1170 attributes on the given TYPE. */
1173 mips_near_type_p (const_tree type)
1175 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1179 mips_far_type_p (const_tree type)
1181 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1182 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1185 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1188 mips_mips16_decl_p (const_tree decl)
1190 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1194 mips_nomips16_decl_p (const_tree decl)
1196 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1199 /* Check if the interrupt attribute is set for a function. */
1202 mips_interrupt_type_p (tree type)
1204 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1207 /* Check if the attribute to use shadow register set is set for a function. */
1210 mips_use_shadow_register_set_p (tree type)
1212 return lookup_attribute ("use_shadow_register_set",
1213 TYPE_ATTRIBUTES (type)) != NULL;
1216 /* Check if the attribute to keep interrupts masked is set for a function. */
1219 mips_keep_interrupts_masked_p (tree type)
1221 return lookup_attribute ("keep_interrupts_masked",
1222 TYPE_ATTRIBUTES (type)) != NULL;
1225 /* Check if the attribute to use debug exception return is set for
1229 mips_use_debug_exception_return_p (tree type)
1231 return lookup_attribute ("use_debug_exception_return",
1232 TYPE_ATTRIBUTES (type)) != NULL;
1235 /* Return true if function DECL is a MIPS16 function. Return the ambient
1236 setting if DECL is null. */
1239 mips_use_mips16_mode_p (tree decl)
1243 /* Nested functions must use the same frame pointer as their
1244 parent and must therefore use the same ISA mode. */
1245 tree parent = decl_function_context (decl);
1248 if (mips_mips16_decl_p (decl))
1250 if (mips_nomips16_decl_p (decl))
1253 return mips_base_mips16;
1256 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1259 mips_comp_type_attributes (const_tree type1, const_tree type2)
1261 /* Disallow mixed near/far attributes. */
1262 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1264 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1269 /* Implement TARGET_INSERT_ATTRIBUTES. */
1272 mips_insert_attributes (tree decl, tree *attributes)
1275 bool mips16_p, nomips16_p;
1277 /* Check for "mips16" and "nomips16" attributes. */
1278 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1279 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1280 if (TREE_CODE (decl) != FUNCTION_DECL)
1283 error ("%qs attribute only applies to functions", "mips16");
1285 error ("%qs attribute only applies to functions", "nomips16");
1289 mips16_p |= mips_mips16_decl_p (decl);
1290 nomips16_p |= mips_nomips16_decl_p (decl);
1291 if (mips16_p || nomips16_p)
1293 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1294 if (mips16_p && nomips16_p)
1295 error ("%qs cannot have both %<mips16%> and "
1296 "%<nomips16%> attributes",
1297 IDENTIFIER_POINTER (DECL_NAME (decl)));
1299 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1301 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1302 "mips16" attribute, arbitrarily pick one. We must pick the same
1303 setting for duplicate declarations of a function. */
1304 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1305 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1310 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1313 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1315 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1316 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1317 error ("%qs redeclared with conflicting %qs attributes",
1318 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1319 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1320 error ("%qs redeclared with conflicting %qs attributes",
1321 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1323 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1324 DECL_ATTRIBUTES (newdecl));
1327 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1328 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1331 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1333 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1335 *base_ptr = XEXP (x, 0);
1336 *offset_ptr = INTVAL (XEXP (x, 1));
1345 static unsigned int mips_build_integer (struct mips_integer_op *,
1346 unsigned HOST_WIDE_INT);
1348 /* A subroutine of mips_build_integer, with the same interface.
1349 Assume that the final action in the sequence should be a left shift. */
1352 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1354 unsigned int i, shift;
1356 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1357 since signed numbers are easier to load than unsigned ones. */
1359 while ((value & 1) == 0)
1360 value /= 2, shift++;
1362 i = mips_build_integer (codes, value);
1363 codes[i].code = ASHIFT;
1364 codes[i].value = shift;
1368 /* As for mips_build_shift, but assume that the final action will be
1369 an IOR or PLUS operation. */
1372 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1374 unsigned HOST_WIDE_INT high;
1377 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1378 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1380 /* The constant is too complex to load with a simple LUI/ORI pair,
1381 so we want to give the recursive call as many trailing zeros as
1382 possible. In this case, we know bit 16 is set and that the
1383 low 16 bits form a negative number. If we subtract that number
1384 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1385 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1386 codes[i].code = PLUS;
1387 codes[i].value = CONST_LOW_PART (value);
1391 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1392 bits gives a value with at least 17 trailing zeros. */
1393 i = mips_build_integer (codes, high);
1394 codes[i].code = IOR;
1395 codes[i].value = value & 0xffff;
1400 /* Fill CODES with a sequence of rtl operations to load VALUE.
1401 Return the number of operations needed. */
1404 mips_build_integer (struct mips_integer_op *codes,
1405 unsigned HOST_WIDE_INT value)
1407 if (SMALL_OPERAND (value)
1408 || SMALL_OPERAND_UNSIGNED (value)
1409 || LUI_OPERAND (value))
1411 /* The value can be loaded with a single instruction. */
1412 codes[0].code = UNKNOWN;
1413 codes[0].value = value;
1416 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1418 /* Either the constant is a simple LUI/ORI combination or its
1419 lowest bit is set. We don't want to shift in this case. */
1420 return mips_build_lower (codes, value);
1422 else if ((value & 0xffff) == 0)
1424 /* The constant will need at least three actions. The lowest
1425 16 bits are clear, so the final action will be a shift. */
1426 return mips_build_shift (codes, value);
1430 /* The final action could be a shift, add or inclusive OR.
1431 Rather than use a complex condition to select the best
1432 approach, try both mips_build_shift and mips_build_lower
1433 and pick the one that gives the shortest sequence.
1434 Note that this case is only used once per constant. */
1435 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1436 unsigned int cost, alt_cost;
1438 cost = mips_build_shift (codes, value);
1439 alt_cost = mips_build_lower (alt_codes, value);
1440 if (alt_cost < cost)
1442 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1449 /* Return true if symbols of type TYPE require a GOT access. */
1452 mips_got_symbol_type_p (enum mips_symbol_type type)
1456 case SYMBOL_GOT_PAGE_OFST:
1457 case SYMBOL_GOT_DISP:
1465 /* Return true if X is a thread-local symbol. */
1468 mips_tls_symbol_p (rtx x)
1470 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1473 /* Return true if SYMBOL_REF X is associated with a global symbol
1474 (in the STB_GLOBAL sense). */
1477 mips_global_symbol_p (const_rtx x)
1479 const_tree decl = SYMBOL_REF_DECL (x);
1482 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1484 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1485 or weak symbols. Relocations in the object file will be against
1486 the target symbol, so it's that symbol's binding that matters here. */
1487 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1490 /* Return true if function X is a libgcc MIPS16 stub function. */
1493 mips16_stub_function_p (const_rtx x)
1495 return (GET_CODE (x) == SYMBOL_REF
1496 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1499 /* Return true if function X is a locally-defined and locally-binding
1503 mips16_local_function_p (const_rtx x)
1505 return (GET_CODE (x) == SYMBOL_REF
1506 && SYMBOL_REF_LOCAL_P (x)
1507 && !SYMBOL_REF_EXTERNAL_P (x)
1508 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1511 /* Return true if SYMBOL_REF X binds locally. */
1514 mips_symbol_binds_local_p (const_rtx x)
1516 return (SYMBOL_REF_DECL (x)
1517 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1518 : SYMBOL_REF_LOCAL_P (x));
1521 /* Return true if rtx constants of mode MODE should be put into a small
1525 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1527 return (!TARGET_EMBEDDED_DATA
1528 && TARGET_LOCAL_SDATA
1529 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1532 /* Return true if X should not be moved directly into register $25.
1533 We need this because many versions of GAS will treat "la $25,foo" as
1534 part of a call sequence and so allow a global "foo" to be lazily bound. */
1537 mips_dangerous_for_la25_p (rtx x)
1539 return (!TARGET_EXPLICIT_RELOCS
1541 && GET_CODE (x) == SYMBOL_REF
1542 && mips_global_symbol_p (x));
1545 /* Return true if calls to X might need $25 to be valid on entry. */
1548 mips_use_pic_fn_addr_reg_p (const_rtx x)
1550 if (!TARGET_USE_PIC_FN_ADDR_REG)
1553 /* MIPS16 stub functions are guaranteed not to use $25. */
1554 if (mips16_stub_function_p (x))
1557 if (GET_CODE (x) == SYMBOL_REF)
1559 /* If PLTs and copy relocations are available, the static linker
1560 will make sure that $25 is valid on entry to the target function. */
1561 if (TARGET_ABICALLS_PIC0)
1564 /* Locally-defined functions use absolute accesses to set up
1565 the global pointer. */
1566 if (TARGET_ABSOLUTE_ABICALLS
1567 && mips_symbol_binds_local_p (x)
1568 && !SYMBOL_REF_EXTERNAL_P (x))
1575 /* Return the method that should be used to access SYMBOL_REF or
1576 LABEL_REF X in context CONTEXT. */
1578 static enum mips_symbol_type
1579 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1582 return SYMBOL_GOT_DISP;
1584 if (GET_CODE (x) == LABEL_REF)
1586 /* LABEL_REFs are used for jump tables as well as text labels.
1587 Only return SYMBOL_PC_RELATIVE if we know the label is in
1588 the text section. */
1589 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1590 return SYMBOL_PC_RELATIVE;
1592 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1593 return SYMBOL_GOT_PAGE_OFST;
1595 return SYMBOL_ABSOLUTE;
1598 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1600 if (SYMBOL_REF_TLS_MODEL (x))
1603 if (CONSTANT_POOL_ADDRESS_P (x))
1605 if (TARGET_MIPS16_TEXT_LOADS)
1606 return SYMBOL_PC_RELATIVE;
1608 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1609 return SYMBOL_PC_RELATIVE;
1611 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1612 return SYMBOL_GP_RELATIVE;
1615 /* Do not use small-data accesses for weak symbols; they may end up
1617 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1618 return SYMBOL_GP_RELATIVE;
1620 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1622 if (TARGET_ABICALLS_PIC2
1623 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1625 /* There are three cases to consider:
1627 - o32 PIC (either with or without explicit relocs)
1628 - n32/n64 PIC without explicit relocs
1629 - n32/n64 PIC with explicit relocs
1631 In the first case, both local and global accesses will use an
1632 R_MIPS_GOT16 relocation. We must correctly predict which of
1633 the two semantics (local or global) the assembler and linker
1634 will apply. The choice depends on the symbol's binding rather
1635 than its visibility.
1637 In the second case, the assembler will not use R_MIPS_GOT16
1638 relocations, but it chooses between local and global accesses
1639 in the same way as for o32 PIC.
1641 In the third case we have more freedom since both forms of
1642 access will work for any kind of symbol. However, there seems
1643 little point in doing things differently. */
1644 if (mips_global_symbol_p (x))
1645 return SYMBOL_GOT_DISP;
1647 return SYMBOL_GOT_PAGE_OFST;
1650 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1651 return SYMBOL_FORCE_TO_MEM;
1653 return SYMBOL_ABSOLUTE;
1656 /* Classify the base of symbolic expression X, given that X appears in
1659 static enum mips_symbol_type
1660 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1664 split_const (x, &x, &offset);
1665 if (UNSPEC_ADDRESS_P (x))
1666 return UNSPEC_ADDRESS_TYPE (x);
1668 return mips_classify_symbol (x, context);
1671 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1672 is the alignment in bytes of SYMBOL_REF X. */
1675 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1677 HOST_WIDE_INT align;
1679 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1680 return IN_RANGE (offset, 0, align - 1);
1683 /* Return true if X is a symbolic constant that can be used in context
1684 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1687 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1688 enum mips_symbol_type *symbol_type)
1692 split_const (x, &x, &offset);
1693 if (UNSPEC_ADDRESS_P (x))
1695 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1696 x = UNSPEC_ADDRESS (x);
1698 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1700 *symbol_type = mips_classify_symbol (x, context);
1701 if (*symbol_type == SYMBOL_TLS)
1707 if (offset == const0_rtx)
1710 /* Check whether a nonzero offset is valid for the underlying
1712 switch (*symbol_type)
1714 case SYMBOL_ABSOLUTE:
1715 case SYMBOL_FORCE_TO_MEM:
1716 case SYMBOL_32_HIGH:
1717 case SYMBOL_64_HIGH:
1720 /* If the target has 64-bit pointers and the object file only
1721 supports 32-bit symbols, the values of those symbols will be
1722 sign-extended. In this case we can't allow an arbitrary offset
1723 in case the 32-bit value X + OFFSET has a different sign from X. */
1724 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1725 return offset_within_block_p (x, INTVAL (offset));
1727 /* In other cases the relocations can handle any offset. */
1730 case SYMBOL_PC_RELATIVE:
1731 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1732 In this case, we no longer have access to the underlying constant,
1733 but the original symbol-based access was known to be valid. */
1734 if (GET_CODE (x) == LABEL_REF)
1739 case SYMBOL_GP_RELATIVE:
1740 /* Make sure that the offset refers to something within the
1741 same object block. This should guarantee that the final
1742 PC- or GP-relative offset is within the 16-bit limit. */
1743 return offset_within_block_p (x, INTVAL (offset));
1745 case SYMBOL_GOT_PAGE_OFST:
1746 case SYMBOL_GOTOFF_PAGE:
1747 /* If the symbol is global, the GOT entry will contain the symbol's
1748 address, and we will apply a 16-bit offset after loading it.
1749 If the symbol is local, the linker should provide enough local
1750 GOT entries for a 16-bit offset, but larger offsets may lead
1752 return SMALL_INT (offset);
1756 /* There is no carry between the HI and LO REL relocations, so the
1757 offset is only valid if we know it won't lead to such a carry. */
1758 return mips_offset_within_alignment_p (x, INTVAL (offset));
1760 case SYMBOL_GOT_DISP:
1761 case SYMBOL_GOTOFF_DISP:
1762 case SYMBOL_GOTOFF_CALL:
1763 case SYMBOL_GOTOFF_LOADGP:
1766 case SYMBOL_GOTTPREL:
1774 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1775 single instruction. We rely on the fact that, in the worst case,
1776 all instructions involved in a MIPS16 address calculation are usually
1780 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1784 case SYMBOL_ABSOLUTE:
1785 /* When using 64-bit symbols, we need 5 preparatory instructions,
1788 lui $at,%highest(symbol)
1789 daddiu $at,$at,%higher(symbol)
1791 daddiu $at,$at,%hi(symbol)
1794 The final address is then $at + %lo(symbol). With 32-bit
1795 symbols we just need a preparatory LUI for normal mode and
1796 a preparatory LI and SLL for MIPS16. */
1797 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1799 case SYMBOL_GP_RELATIVE:
1800 /* Treat GP-relative accesses as taking a single instruction on
1801 MIPS16 too; the copy of $gp can often be shared. */
1804 case SYMBOL_PC_RELATIVE:
1805 /* PC-relative constants can be only be used with ADDIUPC,
1806 DADDIUPC, LWPC and LDPC. */
1807 if (mode == MAX_MACHINE_MODE
1808 || GET_MODE_SIZE (mode) == 4
1809 || GET_MODE_SIZE (mode) == 8)
1812 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1815 case SYMBOL_FORCE_TO_MEM:
1816 /* LEAs will be converted into constant-pool references by
1818 if (mode == MAX_MACHINE_MODE)
1821 /* The constant must be loaded and then dereferenced. */
1824 case SYMBOL_GOT_DISP:
1825 /* The constant will have to be loaded from the GOT before it
1826 is used in an address. */
1827 if (mode != MAX_MACHINE_MODE)
1832 case SYMBOL_GOT_PAGE_OFST:
1833 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1834 local/global classification is accurate. The worst cases are:
1836 (1) For local symbols when generating o32 or o64 code. The assembler
1842 ...and the final address will be $at + %lo(symbol).
1844 (2) For global symbols when -mxgot. The assembler will use:
1846 lui $at,%got_hi(symbol)
1849 ...and the final address will be $at + %got_lo(symbol). */
1852 case SYMBOL_GOTOFF_PAGE:
1853 case SYMBOL_GOTOFF_DISP:
1854 case SYMBOL_GOTOFF_CALL:
1855 case SYMBOL_GOTOFF_LOADGP:
1856 case SYMBOL_32_HIGH:
1857 case SYMBOL_64_HIGH:
1863 case SYMBOL_GOTTPREL:
1866 /* A 16-bit constant formed by a single relocation, or a 32-bit
1867 constant formed from a high 16-bit relocation and a low 16-bit
1868 relocation. Use mips_split_p to determine which. 32-bit
1869 constants need an "lui; addiu" sequence for normal mode and
1870 an "li; sll; addiu" sequence for MIPS16 mode. */
1871 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1874 /* We don't treat a bare TLS symbol as a constant. */
1880 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1881 to load symbols of type TYPE into a register. Return 0 if the given
1882 type of symbol cannot be used as an immediate operand.
1884 Otherwise, return the number of instructions needed to load or store
1885 values of mode MODE to or from addresses of type TYPE. Return 0 if
1886 the given type of symbol is not valid in addresses.
1888 In both cases, treat extended MIPS16 instructions as two instructions. */
1891 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1893 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1896 /* A for_each_rtx callback. Stop the search if *X references a
1897 thread-local symbol. */
1900 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1902 return mips_tls_symbol_p (*x);
1905 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1908 mips_cannot_force_const_mem (rtx x)
1910 enum mips_symbol_type type;
1913 /* There is no assembler syntax for expressing an address-sized
1915 if (GET_CODE (x) == HIGH)
1918 /* As an optimization, reject constants that mips_legitimize_move
1921 Suppose we have a multi-instruction sequence that loads constant C
1922 into register R. If R does not get allocated a hard register, and
1923 R is used in an operand that allows both registers and memory
1924 references, reload will consider forcing C into memory and using
1925 one of the instruction's memory alternatives. Returning false
1926 here will force it to use an input reload instead. */
1927 if (GET_CODE (x) == CONST_INT && LEGITIMATE_CONSTANT_P (x))
1930 split_const (x, &base, &offset);
1931 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1932 && type != SYMBOL_FORCE_TO_MEM)
1934 /* The same optimization as for CONST_INT. */
1935 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1938 /* If MIPS16 constant pools live in the text section, they should
1939 not refer to anything that might need run-time relocation. */
1940 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1944 /* TLS symbols must be computed by mips_legitimize_move. */
1945 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1951 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1952 constants when we're using a per-function constant pool. */
1955 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1956 const_rtx x ATTRIBUTE_UNUSED)
1958 return !TARGET_MIPS16_PCREL_LOADS;
1961 /* Return true if register REGNO is a valid base register for mode MODE.
1962 STRICT_P is true if REG_OK_STRICT is in effect. */
1965 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1968 if (!HARD_REGISTER_NUM_P (regno))
1972 regno = reg_renumber[regno];
1975 /* These fake registers will be eliminated to either the stack or
1976 hard frame pointer, both of which are usually valid base registers.
1977 Reload deals with the cases where the eliminated form isn't valid. */
1978 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1981 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1982 values, nothing smaller. There are two problems here:
1984 (a) Instantiating virtual registers can introduce new uses of the
1985 stack pointer. If these virtual registers are valid addresses,
1986 the stack pointer should be too.
1988 (b) Most uses of the stack pointer are not made explicit until
1989 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1990 We don't know until that stage whether we'll be eliminating to the
1991 stack pointer (which needs the restriction) or the hard frame
1992 pointer (which doesn't).
1994 All in all, it seems more consistent to only enforce this restriction
1995 during and after reload. */
1996 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1997 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1999 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2002 /* Return true if X is a valid base register for mode MODE.
2003 STRICT_P is true if REG_OK_STRICT is in effect. */
2006 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2008 if (!strict_p && GET_CODE (x) == SUBREG)
2012 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2015 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2016 can address a value of mode MODE. */
2019 mips_valid_offset_p (rtx x, enum machine_mode mode)
2021 /* Check that X is a signed 16-bit number. */
2022 if (!const_arith_operand (x, Pmode))
2025 /* We may need to split multiword moves, so make sure that every word
2027 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2028 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2034 /* Return true if a LO_SUM can address a value of mode MODE when the
2035 LO_SUM symbol has type SYMBOL_TYPE. */
2038 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2040 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2042 if (mips_symbol_insns (symbol_type, mode) == 0)
2045 /* Check that there is a known low-part relocation. */
2046 if (mips_lo_relocs[symbol_type] == NULL)
2049 /* We may need to split multiword moves, so make sure that each word
2050 can be accessed without inducing a carry. This is mainly needed
2051 for o64, which has historically only guaranteed 64-bit alignment
2052 for 128-bit types. */
2053 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2054 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2060 /* Return true if X is a valid address for machine mode MODE. If it is,
2061 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2065 mips_classify_address (struct mips_address_info *info, rtx x,
2066 enum machine_mode mode, bool strict_p)
2068 switch (GET_CODE (x))
2072 info->type = ADDRESS_REG;
2074 info->offset = const0_rtx;
2075 return mips_valid_base_register_p (info->reg, mode, strict_p);
2078 info->type = ADDRESS_REG;
2079 info->reg = XEXP (x, 0);
2080 info->offset = XEXP (x, 1);
2081 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2082 && mips_valid_offset_p (info->offset, mode));
2085 info->type = ADDRESS_LO_SUM;
2086 info->reg = XEXP (x, 0);
2087 info->offset = XEXP (x, 1);
2088 /* We have to trust the creator of the LO_SUM to do something vaguely
2089 sane. Target-independent code that creates a LO_SUM should also
2090 create and verify the matching HIGH. Target-independent code that
2091 adds an offset to a LO_SUM must prove that the offset will not
2092 induce a carry. Failure to do either of these things would be
2093 a bug, and we are not required to check for it here. The MIPS
2094 backend itself should only create LO_SUMs for valid symbolic
2095 constants, with the high part being either a HIGH or a copy
2098 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2099 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2100 && mips_valid_lo_sum_p (info->symbol_type, mode));
2103 /* Small-integer addresses don't occur very often, but they
2104 are legitimate if $0 is a valid base register. */
2105 info->type = ADDRESS_CONST_INT;
2106 return !TARGET_MIPS16 && SMALL_INT (x);
2111 info->type = ADDRESS_SYMBOLIC;
2112 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2114 && mips_symbol_insns (info->symbol_type, mode) > 0
2115 && !mips_split_p[info->symbol_type]);
2122 /* Return true if X is a legitimate address for a memory operand of mode
2123 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
2126 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2128 struct mips_address_info addr;
2130 return mips_classify_address (&addr, x, mode, strict_p);
2133 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2136 mips_stack_address_p (rtx x, enum machine_mode mode)
2138 struct mips_address_info addr;
2140 return (mips_classify_address (&addr, x, mode, false)
2141 && addr.type == ADDRESS_REG
2142 && addr.reg == stack_pointer_rtx);
2145 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2146 address instruction. Note that such addresses are not considered
2147 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
2148 is so restricted. */
2151 mips_lwxs_address_p (rtx addr)
2154 && GET_CODE (addr) == PLUS
2155 && REG_P (XEXP (addr, 1)))
2157 rtx offset = XEXP (addr, 0);
2158 if (GET_CODE (offset) == MULT
2159 && REG_P (XEXP (offset, 0))
2160 && GET_CODE (XEXP (offset, 1)) == CONST_INT
2161 && INTVAL (XEXP (offset, 1)) == 4)
2167 /* Return true if a value at OFFSET bytes from base register BASE can be
2168 accessed using an unextended MIPS16 instruction. MODE is the mode of
2171 Usually the offset in an unextended instruction is a 5-bit field.
2172 The offset is unsigned and shifted left once for LH and SH, twice
2173 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2174 an 8-bit immediate field that's shifted left twice. */
2177 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2178 unsigned HOST_WIDE_INT offset)
2180 if (offset % GET_MODE_SIZE (mode) == 0)
2182 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2183 return offset < 256U * GET_MODE_SIZE (mode);
2184 return offset < 32U * GET_MODE_SIZE (mode);
2189 /* Return the number of instructions needed to load or store a value
2190 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2191 Assume that multiword moves may need to be split into word moves
2192 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2195 For MIPS16 code, count extended instructions as two instructions. */
2198 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2200 struct mips_address_info addr;
2203 /* BLKmode is used for single unaligned loads and stores and should
2204 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2205 meaningless, so we have to single it out as a special case one way
2207 if (mode != BLKmode && might_split_p)
2208 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2212 if (mips_classify_address (&addr, x, mode, false))
2217 && !mips16_unextended_reference_p (mode, addr.reg,
2218 UINTVAL (addr.offset)))
2222 case ADDRESS_LO_SUM:
2223 return TARGET_MIPS16 ? factor * 2 : factor;
2225 case ADDRESS_CONST_INT:
2228 case ADDRESS_SYMBOLIC:
2229 return factor * mips_symbol_insns (addr.symbol_type, mode);
2234 /* Return the number of instructions needed to load constant X.
2235 Return 0 if X isn't a valid constant. */
2238 mips_const_insns (rtx x)
2240 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2241 enum mips_symbol_type symbol_type;
2244 switch (GET_CODE (x))
2247 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2249 || !mips_split_p[symbol_type])
2252 /* This is simply an LUI for normal mode. It is an extended
2253 LI followed by an extended SLL for MIPS16. */
2254 return TARGET_MIPS16 ? 4 : 1;
2258 /* Unsigned 8-bit constants can be loaded using an unextended
2259 LI instruction. Unsigned 16-bit constants can be loaded
2260 using an extended LI. Negative constants must be loaded
2261 using LI and then negated. */
2262 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2263 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2264 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2265 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2268 return mips_build_integer (codes, INTVAL (x));
2272 /* Allow zeros for normal mode, where we can use $0. */
2273 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2279 /* See if we can refer to X directly. */
2280 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2281 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2283 /* Otherwise try splitting the constant into a base and offset.
2284 If the offset is a 16-bit value, we can load the base address
2285 into a register and then use (D)ADDIU to add in the offset.
2286 If the offset is larger, we can load the base and offset
2287 into separate registers and add them together with (D)ADDU.
2288 However, the latter is only possible before reload; during
2289 and after reload, we must have the option of forcing the
2290 constant into the pool instead. */
2291 split_const (x, &x, &offset);
2294 int n = mips_const_insns (x);
2297 if (SMALL_INT (offset))
2299 else if (!targetm.cannot_force_const_mem (x))
2300 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2307 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2315 /* X is a doubleword constant that can be handled by splitting it into
2316 two words and loading each word separately. Return the number of
2317 instructions required to do this. */
2320 mips_split_const_insns (rtx x)
2322 unsigned int low, high;
2324 low = mips_const_insns (mips_subword (x, false));
2325 high = mips_const_insns (mips_subword (x, true));
2326 gcc_assert (low > 0 && high > 0);
2330 /* Return the number of instructions needed to implement INSN,
2331 given that it loads from or stores to MEM. Count extended
2332 MIPS16 instructions as two instructions. */
2335 mips_load_store_insns (rtx mem, rtx insn)
2337 enum machine_mode mode;
2341 gcc_assert (MEM_P (mem));
2342 mode = GET_MODE (mem);
2344 /* Try to prove that INSN does not need to be split. */
2345 might_split_p = true;
2346 if (GET_MODE_BITSIZE (mode) == 64)
2348 set = single_set (insn);
2349 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2350 might_split_p = false;
2353 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2356 /* Return the number of instructions needed for an integer division. */
2359 mips_idiv_insns (void)
2364 if (TARGET_CHECK_ZERO_DIV)
2366 if (GENERATE_DIVIDE_TRAPS)
2372 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2377 /* Emit a move from SRC to DEST. Assume that the move expanders can
2378 handle all moves if !can_create_pseudo_p (). The distinction is
2379 important because, unlike emit_move_insn, the move expanders know
2380 how to force Pmode objects into the constant pool even when the
2381 constant pool address is not itself legitimate. */
2384 mips_emit_move (rtx dest, rtx src)
2386 return (can_create_pseudo_p ()
2387 ? emit_move_insn (dest, src)
2388 : emit_move_insn_1 (dest, src));
2391 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2394 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2396 emit_insn (gen_rtx_SET (VOIDmode, target,
2397 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2400 /* Compute (CODE OP0 OP1) and store the result in a new register
2401 of mode MODE. Return that new register. */
2404 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2408 reg = gen_reg_rtx (mode);
2409 mips_emit_binary (code, reg, op0, op1);
2413 /* Copy VALUE to a register and return that register. If new pseudos
2414 are allowed, copy it into a new register, otherwise use DEST. */
2417 mips_force_temporary (rtx dest, rtx value)
2419 if (can_create_pseudo_p ())
2420 return force_reg (Pmode, value);
2423 mips_emit_move (dest, value);
2428 /* Emit a call sequence with call pattern PATTERN and return the call
2429 instruction itself (which is not necessarily the last instruction
2430 emitted). ORIG_ADDR is the original, unlegitimized address,
2431 ADDR is the legitimized form, and LAZY_P is true if the call
2432 address is lazily-bound. */
2435 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2439 insn = emit_call_insn (pattern);
2441 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2443 /* MIPS16 JALRs only take MIPS16 registers. If the target
2444 function requires $25 to be valid on entry, we must copy it
2445 there separately. The move instruction can be put in the
2446 call's delay slot. */
2447 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2448 emit_insn_before (gen_move_insn (reg, addr), insn);
2449 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2453 /* Lazy-binding stubs require $gp to be valid on entry. */
2454 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2458 /* See the comment above load_call<mode> for details. */
2459 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2460 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2461 emit_insn (gen_update_got_version ());
2466 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2467 then add CONST_INT OFFSET to the result. */
2470 mips_unspec_address_offset (rtx base, rtx offset,
2471 enum mips_symbol_type symbol_type)
2473 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2474 UNSPEC_ADDRESS_FIRST + symbol_type);
2475 if (offset != const0_rtx)
2476 base = gen_rtx_PLUS (Pmode, base, offset);
2477 return gen_rtx_CONST (Pmode, base);
2480 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2481 type SYMBOL_TYPE. */
2484 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2488 split_const (address, &base, &offset);
2489 return mips_unspec_address_offset (base, offset, symbol_type);
2492 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2493 high part to BASE and return the result. Just return BASE otherwise.
2494 TEMP is as for mips_force_temporary.
2496 The returned expression can be used as the first operand to a LO_SUM. */
2499 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2500 enum mips_symbol_type symbol_type)
2502 if (mips_split_p[symbol_type])
2504 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2505 addr = mips_force_temporary (temp, addr);
2506 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2511 /* Return an instruction that copies $gp into register REG. We want
2512 GCC to treat the register's value as constant, so that its value
2513 can be rematerialized on demand. */
2516 gen_load_const_gp (rtx reg)
2518 return (Pmode == SImode
2519 ? gen_load_const_gp_si (reg)
2520 : gen_load_const_gp_di (reg));
2523 /* Return a pseudo register that contains the value of $gp throughout
2524 the current function. Such registers are needed by MIPS16 functions,
2525 for which $gp itself is not a valid base register or addition operand. */
2528 mips16_gp_pseudo_reg (void)
2530 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2531 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2533 /* Don't emit an instruction to initialize the pseudo register if
2534 we are being called from the tree optimizers' cost-calculation
2536 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2537 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2541 push_topmost_sequence ();
2543 scan = get_insns ();
2544 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2545 scan = NEXT_INSN (scan);
2547 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2548 emit_insn_after (insn, scan);
2550 pop_topmost_sequence ();
2552 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2555 return cfun->machine->mips16_gp_pseudo_rtx;
2558 /* Return a base register that holds pic_offset_table_rtx.
2559 TEMP, if nonnull, is a scratch Pmode base register. */
2562 mips_pic_base_register (rtx temp)
2565 return pic_offset_table_rtx;
2567 if (can_create_pseudo_p ())
2568 return mips16_gp_pseudo_reg ();
2571 /* The first post-reload split exposes all references to $gp
2572 (both uses and definitions). All references must remain
2573 explicit after that point.
2575 It is safe to introduce uses of $gp at any time, so for
2576 simplicity, we do that before the split too. */
2577 mips_emit_move (temp, pic_offset_table_rtx);
2579 emit_insn (gen_load_const_gp (temp));
2583 /* Create and return a GOT reference of type TYPE for address ADDR.
2584 TEMP, if nonnull, is a scratch Pmode base register. */
2587 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2589 rtx base, high, lo_sum_symbol;
2591 base = mips_pic_base_register (temp);
2593 /* If we used the temporary register to load $gp, we can't use
2594 it for the high part as well. */
2595 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2598 high = mips_unspec_offset_high (temp, base, addr, type);
2599 lo_sum_symbol = mips_unspec_address (addr, type);
2601 if (type == SYMBOL_GOTOFF_CALL)
2602 return (Pmode == SImode
2603 ? gen_unspec_callsi (high, lo_sum_symbol)
2604 : gen_unspec_calldi (high, lo_sum_symbol));
2606 return (Pmode == SImode
2607 ? gen_unspec_gotsi (high, lo_sum_symbol)
2608 : gen_unspec_gotdi (high, lo_sum_symbol));
2611 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2612 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2613 constant in that context and can be split into high and low parts.
2614 If so, and if LOW_OUT is nonnull, emit the high part and store the
2615 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2617 TEMP is as for mips_force_temporary and is used to load the high
2618 part into a register.
2620 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2621 a legitimize SET_SRC for an .md pattern, otherwise the low part
2622 is guaranteed to be a legitimate address for mode MODE. */
2625 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2627 enum mips_symbol_context context;
2628 enum mips_symbol_type symbol_type;
2631 context = (mode == MAX_MACHINE_MODE
2632 ? SYMBOL_CONTEXT_LEA
2633 : SYMBOL_CONTEXT_MEM);
2634 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2636 addr = XEXP (addr, 0);
2637 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2638 && mips_symbol_insns (symbol_type, mode) > 0
2639 && mips_split_hi_p[symbol_type])
2642 switch (symbol_type)
2644 case SYMBOL_GOT_PAGE_OFST:
2645 /* The high part of a page/ofst pair is loaded from the GOT. */
2646 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2657 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2658 && mips_symbol_insns (symbol_type, mode) > 0
2659 && mips_split_p[symbol_type])
2662 switch (symbol_type)
2664 case SYMBOL_GOT_DISP:
2665 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2666 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2669 case SYMBOL_GP_RELATIVE:
2670 high = mips_pic_base_register (temp);
2671 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2675 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2676 high = mips_force_temporary (temp, high);
2677 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2686 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2687 mips_force_temporary; it is only needed when OFFSET is not a
2691 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2693 if (!SMALL_OPERAND (offset))
2699 /* Load the full offset into a register so that we can use
2700 an unextended instruction for the address itself. */
2701 high = GEN_INT (offset);
2706 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2707 The addition inside the macro CONST_HIGH_PART may cause an
2708 overflow, so we need to force a sign-extension check. */
2709 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2710 offset = CONST_LOW_PART (offset);
2712 high = mips_force_temporary (temp, high);
2713 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2715 return plus_constant (reg, offset);
2718 /* The __tls_get_attr symbol. */
2719 static GTY(()) rtx mips_tls_symbol;
2721 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2722 the TLS symbol we are referencing and TYPE is the symbol type to use
2723 (either global dynamic or local dynamic). V0 is an RTX for the
2724 return value location. */
2727 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2731 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2733 if (!mips_tls_symbol)
2734 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2736 loc = mips_unspec_address (sym, type);
2740 emit_insn (gen_rtx_SET (Pmode, a0,
2741 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2742 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2743 const0_rtx, NULL_RTX, false);
2744 RTL_CONST_CALL_P (insn) = 1;
2745 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2746 insn = get_insns ();
2753 /* Return a pseudo register that contains the current thread pointer. */
2760 tp = gen_reg_rtx (Pmode);
2761 if (Pmode == DImode)
2762 emit_insn (gen_tls_get_tp_di (tp));
2764 emit_insn (gen_tls_get_tp_si (tp));
2768 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2769 its address. The return value will be both a valid address and a valid
2770 SET_SRC (either a REG or a LO_SUM). */
2773 mips_legitimize_tls_address (rtx loc)
2775 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2776 enum tls_model model;
2780 sorry ("MIPS16 TLS");
2781 return gen_reg_rtx (Pmode);
2784 model = SYMBOL_REF_TLS_MODEL (loc);
2785 /* Only TARGET_ABICALLS code can have more than one module; other
2786 code must be be static and should not use a GOT. All TLS models
2787 reduce to local exec in this situation. */
2788 if (!TARGET_ABICALLS)
2789 model = TLS_MODEL_LOCAL_EXEC;
2793 case TLS_MODEL_GLOBAL_DYNAMIC:
2794 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2795 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2796 dest = gen_reg_rtx (Pmode);
2797 emit_libcall_block (insn, dest, v0, loc);
2800 case TLS_MODEL_LOCAL_DYNAMIC:
2801 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2802 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2803 tmp1 = gen_reg_rtx (Pmode);
2805 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2806 share the LDM result with other LD model accesses. */
2807 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2809 emit_libcall_block (insn, tmp1, v0, eqv);
2811 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2812 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2813 mips_unspec_address (loc, SYMBOL_DTPREL));
2816 case TLS_MODEL_INITIAL_EXEC:
2817 tp = mips_get_tp ();
2818 tmp1 = gen_reg_rtx (Pmode);
2819 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2820 if (Pmode == DImode)
2821 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2823 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2824 dest = gen_reg_rtx (Pmode);
2825 emit_insn (gen_add3_insn (dest, tmp1, tp));
2828 case TLS_MODEL_LOCAL_EXEC:
2829 tp = mips_get_tp ();
2830 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2831 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2832 mips_unspec_address (loc, SYMBOL_TPREL));
2841 /* If X is not a valid address for mode MODE, force it into a register. */
2844 mips_force_address (rtx x, enum machine_mode mode)
2846 if (!mips_legitimate_address_p (mode, x, false))
2847 x = force_reg (Pmode, x);
2851 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2852 be legitimized in a way that the generic machinery might not expect,
2853 return a new address, otherwise return NULL. MODE is the mode of
2854 the memory being accessed. */
2857 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2858 enum machine_mode mode)
2861 HOST_WIDE_INT offset;
2863 if (mips_tls_symbol_p (x))
2864 return mips_legitimize_tls_address (x);
2866 /* See if the address can split into a high part and a LO_SUM. */
2867 if (mips_split_symbol (NULL, x, mode, &addr))
2868 return mips_force_address (addr, mode);
2870 /* Handle BASE + OFFSET using mips_add_offset. */
2871 mips_split_plus (x, &base, &offset);
2874 if (!mips_valid_base_register_p (base, mode, false))
2875 base = copy_to_mode_reg (Pmode, base);
2876 addr = mips_add_offset (NULL, base, offset);
2877 return mips_force_address (addr, mode);
2883 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2886 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2888 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2889 enum machine_mode mode;
2890 unsigned int i, num_ops;
2893 mode = GET_MODE (dest);
2894 num_ops = mips_build_integer (codes, value);
2896 /* Apply each binary operation to X. Invariant: X is a legitimate
2897 source operand for a SET pattern. */
2898 x = GEN_INT (codes[0].value);
2899 for (i = 1; i < num_ops; i++)
2901 if (!can_create_pseudo_p ())
2903 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2907 x = force_reg (mode, x);
2908 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2911 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2914 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2915 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2919 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2923 /* Split moves of big integers into smaller pieces. */
2924 if (splittable_const_int_operand (src, mode))
2926 mips_move_integer (dest, dest, INTVAL (src));
2930 /* Split moves of symbolic constants into high/low pairs. */
2931 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2933 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2937 /* Generate the appropriate access sequences for TLS symbols. */
2938 if (mips_tls_symbol_p (src))
2940 mips_emit_move (dest, mips_legitimize_tls_address (src));
2944 /* If we have (const (plus symbol offset)), and that expression cannot
2945 be forced into memory, load the symbol first and add in the offset.
2946 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2947 forced into memory, as it usually produces better code. */
2948 split_const (src, &base, &offset);
2949 if (offset != const0_rtx
2950 && (targetm.cannot_force_const_mem (src)
2951 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2953 base = mips_force_temporary (dest, base);
2954 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2958 src = force_const_mem (mode, src);
2960 /* When using explicit relocs, constant pool references are sometimes
2961 not legitimate addresses. */
2962 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2963 mips_emit_move (dest, src);
2966 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2967 sequence that is valid. */
2970 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2972 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2974 mips_emit_move (dest, force_reg (mode, src));
2978 /* We need to deal with constants that would be legitimate
2979 immediate_operands but aren't legitimate move_operands. */
2980 if (CONSTANT_P (src) && !move_operand (src, mode))
2982 mips_legitimize_const_move (mode, dest, src);
2983 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2989 /* Return true if value X in context CONTEXT is a small-data address
2990 that can be rewritten as a LO_SUM. */
2993 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2995 enum mips_symbol_type symbol_type;
2997 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
2998 && !mips_split_p[SYMBOL_GP_RELATIVE]
2999 && mips_symbolic_constant_p (x, context, &symbol_type)
3000 && symbol_type == SYMBOL_GP_RELATIVE);
3003 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3004 containing MEM, or null if none. */
3007 mips_small_data_pattern_1 (rtx *loc, void *data)
3009 enum mips_symbol_context context;
3011 if (GET_CODE (*loc) == LO_SUM)
3016 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3021 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3022 return mips_rewrite_small_data_p (*loc, context);
3025 /* Return true if OP refers to small data symbols directly, not through
3029 mips_small_data_pattern_p (rtx op)
3031 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3034 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3035 DATA is the containing MEM, or null if none. */
3038 mips_rewrite_small_data_1 (rtx *loc, void *data)
3040 enum mips_symbol_context context;
3044 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3048 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3049 if (mips_rewrite_small_data_p (*loc, context))
3050 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3052 if (GET_CODE (*loc) == LO_SUM)
3058 /* Rewrite instruction pattern PATTERN so that it refers to small data
3059 using explicit relocations. */
3062 mips_rewrite_small_data (rtx pattern)
3064 pattern = copy_insn (pattern);
3065 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3069 /* We need a lot of little routines to check the range of MIPS16 immediate
3073 m16_check_op (rtx op, int low, int high, int mask)
3075 return (GET_CODE (op) == CONST_INT
3076 && IN_RANGE (INTVAL (op), low, high)
3077 && (INTVAL (op) & mask) == 0);
3081 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3083 return m16_check_op (op, 0x1, 0x8, 0);
3087 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3089 return m16_check_op (op, -0x8, 0x7, 0);
3093 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3095 return m16_check_op (op, -0x7, 0x8, 0);
3099 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3101 return m16_check_op (op, -0x10, 0xf, 0);
3105 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3107 return m16_check_op (op, -0xf, 0x10, 0);
3111 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3113 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3117 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3119 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3123 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3125 return m16_check_op (op, -0x80, 0x7f, 0);
3129 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3131 return m16_check_op (op, -0x7f, 0x80, 0);
3135 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3137 return m16_check_op (op, 0x0, 0xff, 0);
3141 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3143 return m16_check_op (op, -0xff, 0x0, 0);
3147 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3149 return m16_check_op (op, -0x1, 0xfe, 0);
3153 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3155 return m16_check_op (op, 0x0, 0xff << 2, 3);
3159 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3161 return m16_check_op (op, -0xff << 2, 0x0, 3);
3165 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3167 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3171 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3173 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3176 /* The cost of loading values from the constant pool. It should be
3177 larger than the cost of any constant we want to synthesize inline. */
3178 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3180 /* Return the cost of X when used as an operand to the MIPS16 instruction
3181 that implements CODE. Return -1 if there is no such instruction, or if
3182 X is not a valid immediate operand for it. */
3185 mips16_constant_cost (int code, HOST_WIDE_INT x)
3192 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3193 other shifts are extended. The shift patterns truncate the shift
3194 count to the right size, so there are no out-of-range values. */
3195 if (IN_RANGE (x, 1, 8))
3197 return COSTS_N_INSNS (1);
3200 if (IN_RANGE (x, -128, 127))
3202 if (SMALL_OPERAND (x))
3203 return COSTS_N_INSNS (1);
3207 /* Like LE, but reject the always-true case. */
3211 /* We add 1 to the immediate and use SLT. */
3214 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3217 if (IN_RANGE (x, 0, 255))
3219 if (SMALL_OPERAND_UNSIGNED (x))
3220 return COSTS_N_INSNS (1);
3225 /* Equality comparisons with 0 are cheap. */
3235 /* Return true if there is a non-MIPS16 instruction that implements CODE
3236 and if that instruction accepts X as an immediate operand. */
3239 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3246 /* All shift counts are truncated to a valid constant. */
3251 /* Likewise rotates, if the target supports rotates at all. */
3257 /* These instructions take 16-bit unsigned immediates. */
3258 return SMALL_OPERAND_UNSIGNED (x);
3263 /* These instructions take 16-bit signed immediates. */
3264 return SMALL_OPERAND (x);
3270 /* The "immediate" forms of these instructions are really
3271 implemented as comparisons with register 0. */
3276 /* Likewise, meaning that the only valid immediate operand is 1. */
3280 /* We add 1 to the immediate and use SLT. */
3281 return SMALL_OPERAND (x + 1);
3284 /* Likewise SLTU, but reject the always-true case. */
3285 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3289 /* The bit position and size are immediate operands. */
3290 return ISA_HAS_EXT_INS;
3293 /* By default assume that $0 can be used for 0. */
3298 /* Return the cost of binary operation X, given that the instruction
3299 sequence for a word-sized or smaller operation has cost SINGLE_COST
3300 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3303 mips_binary_cost (rtx x, int single_cost, int double_cost)
3307 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3312 + rtx_cost (XEXP (x, 0), SET, !optimize_size)
3313 + rtx_cost (XEXP (x, 1), GET_CODE (x), !optimize_size));
3316 /* Return the cost of floating-point multiplications of mode MODE. */
3319 mips_fp_mult_cost (enum machine_mode mode)
3321 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3324 /* Return the cost of floating-point divisions of mode MODE. */
3327 mips_fp_div_cost (enum machine_mode mode)
3329 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3332 /* Return the cost of sign-extending OP to mode MODE, not including the
3333 cost of OP itself. */
3336 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3339 /* Extended loads are as cheap as unextended ones. */
3342 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3343 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3346 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3347 /* We can use SEB or SEH. */
3348 return COSTS_N_INSNS (1);
3350 /* We need to use a shift left and a shift right. */
3351 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3354 /* Return the cost of zero-extending OP to mode MODE, not including the
3355 cost of OP itself. */
3358 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3361 /* Extended loads are as cheap as unextended ones. */
3364 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3365 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3366 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3368 if (GENERATE_MIPS16E)
3369 /* We can use ZEB or ZEH. */
3370 return COSTS_N_INSNS (1);
3373 /* We need to load 0xff or 0xffff into a register and use AND. */
3374 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3376 /* We can use ANDI. */
3377 return COSTS_N_INSNS (1);
3380 /* Implement TARGET_RTX_COSTS. */
3383 mips_rtx_costs (rtx x, int code, int outer_code, int *total,
3386 enum machine_mode mode = GET_MODE (x);
3387 bool float_mode_p = FLOAT_MODE_P (mode);
3391 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3392 appear in the instruction stream, and the cost of a comparison is
3393 really the cost of the branch or scc condition. At the time of
3394 writing, GCC only uses an explicit outer COMPARE code when optabs
3395 is testing whether a constant is expensive enough to force into a
3396 register. We want optabs to pass such constants through the MIPS
3397 expanders instead, so make all constants very cheap here. */
3398 if (outer_code == COMPARE)
3400 gcc_assert (CONSTANT_P (x));
3408 /* Treat *clear_upper32-style ANDs as having zero cost in the
3409 second operand. The cost is entirely in the first operand.
3411 ??? This is needed because we would otherwise try to CSE
3412 the constant operand. Although that's the right thing for
3413 instructions that continue to be a register operation throughout
3414 compilation, it is disastrous for instructions that could
3415 later be converted into a memory operation. */
3417 && outer_code == AND
3418 && UINTVAL (x) == 0xffffffff)
3426 cost = mips16_constant_cost (outer_code, INTVAL (x));
3435 /* When not optimizing for size, we care more about the cost
3436 of hot code, and hot code is often in a loop. If a constant
3437 operand needs to be forced into a register, we will often be
3438 able to hoist the constant load out of the loop, so the load
3439 should not contribute to the cost. */
3441 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3453 if (force_to_mem_operand (x, VOIDmode))
3455 *total = COSTS_N_INSNS (1);
3458 cost = mips_const_insns (x);
3461 /* If the constant is likely to be stored in a GPR, SETs of
3462 single-insn constants are as cheap as register sets; we
3463 never want to CSE them.
3465 Don't reduce the cost of storing a floating-point zero in
3466 FPRs. If we have a zero in an FPR for other reasons, we
3467 can get better cfg-cleanup and delayed-branch results by
3468 using it consistently, rather than using $0 sometimes and
3469 an FPR at other times. Also, moves between floating-point
3470 registers are sometimes cheaper than (D)MTC1 $0. */
3472 && outer_code == SET
3473 && !(float_mode_p && TARGET_HARD_FLOAT))
3475 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3476 want to CSE the constant itself. It is usually better to
3477 have N copies of the last operation in the sequence and one
3478 shared copy of the other operations. (Note that this is
3479 not true for MIPS16 code, where the final operation in the
3480 sequence is often an extended instruction.)
3482 Also, if we have a CONST_INT, we don't know whether it is
3483 for a word or doubleword operation, so we cannot rely on
3484 the result of mips_build_integer. */
3485 else if (!TARGET_MIPS16
3486 && (outer_code == SET || mode == VOIDmode))
3488 *total = COSTS_N_INSNS (cost);
3491 /* The value will need to be fetched from the constant pool. */
3492 *total = CONSTANT_POOL_COST;
3496 /* If the address is legitimate, return the number of
3497 instructions it needs. */
3499 cost = mips_address_insns (addr, mode, true);
3502 *total = COSTS_N_INSNS (cost + 1);
3505 /* Check for a scaled indexed address. */
3506 if (mips_lwxs_address_p (addr))
3508 *total = COSTS_N_INSNS (2);
3511 /* Otherwise use the default handling. */
3515 *total = COSTS_N_INSNS (6);
3519 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3523 /* Check for a *clear_upper32 pattern and treat it like a zero
3524 extension. See the pattern's comment for details. */
3527 && CONST_INT_P (XEXP (x, 1))
3528 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3530 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3531 + rtx_cost (XEXP (x, 0), SET, speed));
3538 /* Double-word operations use two single-word operations. */
3539 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3547 if (CONSTANT_P (XEXP (x, 1)))
3548 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3550 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3555 *total = mips_cost->fp_add;
3557 *total = COSTS_N_INSNS (4);
3561 /* Low-part immediates need an extended MIPS16 instruction. */
3562 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3563 + rtx_cost (XEXP (x, 0), SET, speed));
3578 /* Branch comparisons have VOIDmode, so use the first operand's
3580 mode = GET_MODE (XEXP (x, 0));
3581 if (FLOAT_MODE_P (mode))
3583 *total = mips_cost->fp_add;
3586 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3591 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3592 && TARGET_FUSED_MADD
3593 && !HONOR_NANS (mode)
3594 && !HONOR_SIGNED_ZEROS (mode))
3596 /* See if we can use NMADD or NMSUB. See mips.md for the
3597 associated patterns. */
3598 rtx op0 = XEXP (x, 0);
3599 rtx op1 = XEXP (x, 1);
3600 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3602 *total = (mips_fp_mult_cost (mode)
3603 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3604 + rtx_cost (XEXP (op0, 1), SET, speed)
3605 + rtx_cost (op1, SET, speed));
3608 if (GET_CODE (op1) == MULT)
3610 *total = (mips_fp_mult_cost (mode)
3611 + rtx_cost (op0, SET, speed)
3612 + rtx_cost (XEXP (op1, 0), SET, speed)
3613 + rtx_cost (XEXP (op1, 1), SET, speed));
3622 /* If this is part of a MADD or MSUB, treat the PLUS as
3625 && TARGET_FUSED_MADD
3626 && GET_CODE (XEXP (x, 0)) == MULT)
3629 *total = mips_cost->fp_add;
3633 /* Double-word operations require three single-word operations and
3634 an SLTU. The MIPS16 version then needs to move the result of
3635 the SLTU from $24 to a MIPS16 register. */
3636 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3637 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3642 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3643 && TARGET_FUSED_MADD
3644 && !HONOR_NANS (mode)
3645 && HONOR_SIGNED_ZEROS (mode))
3647 /* See if we can use NMADD or NMSUB. See mips.md for the
3648 associated patterns. */
3649 rtx op = XEXP (x, 0);
3650 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3651 && GET_CODE (XEXP (op, 0)) == MULT)
3653 *total = (mips_fp_mult_cost (mode)
3654 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3655 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3656 + rtx_cost (XEXP (op, 1), SET, speed));
3662 *total = mips_cost->fp_add;
3664 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3669 *total = mips_fp_mult_cost (mode);
3670 else if (mode == DImode && !TARGET_64BIT)
3671 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3672 where the mulsidi3 always includes an MFHI and an MFLO. */
3673 *total = (optimize_size
3674 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3675 : mips_cost->int_mult_si * 3 + 6);
3676 else if (optimize_size)
3677 *total = (ISA_HAS_MUL3 ? 1 : 2);
3678 else if (mode == DImode)
3679 *total = mips_cost->int_mult_di;
3681 *total = mips_cost->int_mult_si;
3685 /* Check for a reciprocal. */
3688 && flag_unsafe_math_optimizations
3689 && XEXP (x, 0) == CONST1_RTX (mode))
3691 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3692 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3693 division as being free. */
3694 *total = rtx_cost (XEXP (x, 1), SET, speed);
3696 *total = (mips_fp_div_cost (mode)
3697 + rtx_cost (XEXP (x, 1), SET, speed));
3706 *total = mips_fp_div_cost (mode);
3715 /* It is our responsibility to make division by a power of 2
3716 as cheap as 2 register additions if we want the division
3717 expanders to be used for such operations; see the setting
3718 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3719 should always produce shorter code than using
3720 expand_sdiv2_pow2. */
3722 && CONST_INT_P (XEXP (x, 1))
3723 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3725 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3728 *total = COSTS_N_INSNS (mips_idiv_insns ());
3730 else if (mode == DImode)
3731 *total = mips_cost->int_div_di;
3733 *total = mips_cost->int_div_si;
3737 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3741 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3745 case UNSIGNED_FLOAT:
3748 case FLOAT_TRUNCATE:
3749 *total = mips_cost->fp_add;
3757 /* Implement TARGET_ADDRESS_COST. */
3760 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3762 return mips_address_insns (addr, SImode, false);
3765 /* Return one word of double-word value OP, taking into account the fixed
3766 endianness of certain registers. HIGH_P is true to select the high part,
3767 false to select the low part. */
3770 mips_subword (rtx op, bool high_p)
3772 unsigned int byte, offset;
3773 enum machine_mode mode;
3775 mode = GET_MODE (op);
3776 if (mode == VOIDmode)
3777 mode = TARGET_64BIT ? TImode : DImode;
3779 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3780 byte = UNITS_PER_WORD;
3784 if (FP_REG_RTX_P (op))
3786 /* Paired FPRs are always ordered little-endian. */
3787 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3788 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3792 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3794 return simplify_gen_subreg (word_mode, op, mode, byte);
3797 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3800 mips_split_64bit_move_p (rtx dest, rtx src)
3805 /* FPR-to-FPR moves can be done in a single instruction, if they're
3807 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3810 /* Check for floating-point loads and stores. */
3811 if (ISA_HAS_LDC1_SDC1)
3813 if (FP_REG_RTX_P (dest) && MEM_P (src))
3815 if (FP_REG_RTX_P (src) && MEM_P (dest))
3821 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3822 this function handles 64-bit moves for which mips_split_64bit_move_p
3823 holds. For 64-bit targets, this function handles 128-bit moves. */
3826 mips_split_doubleword_move (rtx dest, rtx src)
3830 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3832 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3833 emit_insn (gen_move_doubleword_fprdi (dest, src));
3834 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3835 emit_insn (gen_move_doubleword_fprdf (dest, src));
3836 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3837 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3838 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
3839 emit_insn (gen_move_doubleword_fprv2si (dest, src));
3840 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
3841 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
3842 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
3843 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
3844 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3845 emit_insn (gen_move_doubleword_fprtf (dest, src));
3849 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
3851 low_dest = mips_subword (dest, false);
3852 mips_emit_move (low_dest, mips_subword (src, false));
3854 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
3856 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
3858 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
3860 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
3862 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
3864 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
3868 /* The operation can be split into two normal moves. Decide in
3869 which order to do them. */
3870 low_dest = mips_subword (dest, false);
3871 if (REG_P (low_dest)
3872 && reg_overlap_mentioned_p (low_dest, src))
3874 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3875 mips_emit_move (low_dest, mips_subword (src, false));
3879 mips_emit_move (low_dest, mips_subword (src, false));
3880 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3885 /* Return the appropriate instructions to move SRC into DEST. Assume
3886 that SRC is operand 1 and DEST is operand 0. */
3889 mips_output_move (rtx dest, rtx src)
3891 enum rtx_code dest_code, src_code;
3892 enum machine_mode mode;
3893 enum mips_symbol_type symbol_type;
3896 dest_code = GET_CODE (dest);
3897 src_code = GET_CODE (src);
3898 mode = GET_MODE (dest);
3899 dbl_p = (GET_MODE_SIZE (mode) == 8);
3901 if (dbl_p && mips_split_64bit_move_p (dest, src))
3904 if ((src_code == REG && GP_REG_P (REGNO (src)))
3905 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
3907 if (dest_code == REG)
3909 if (GP_REG_P (REGNO (dest)))
3910 return "move\t%0,%z1";
3912 /* Moves to HI are handled by special .md insns. */
3913 if (REGNO (dest) == LO_REGNUM)
3916 if (DSP_ACC_REG_P (REGNO (dest)))
3918 static char retval[] = "mt__\t%z1,%q0";
3920 retval[2] = reg_names[REGNO (dest)][4];
3921 retval[3] = reg_names[REGNO (dest)][5];
3925 if (FP_REG_P (REGNO (dest)))
3926 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3928 if (ALL_COP_REG_P (REGNO (dest)))
3930 static char retval[] = "dmtc_\t%z1,%0";
3932 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3933 return dbl_p ? retval : retval + 1;
3936 if (dest_code == MEM)
3937 switch (GET_MODE_SIZE (mode))
3939 case 1: return "sb\t%z1,%0";
3940 case 2: return "sh\t%z1,%0";
3941 case 4: return "sw\t%z1,%0";
3942 case 8: return "sd\t%z1,%0";
3945 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3947 if (src_code == REG)
3949 /* Moves from HI are handled by special .md insns. */
3950 if (REGNO (src) == LO_REGNUM)
3952 /* When generating VR4120 or VR4130 code, we use MACC and
3953 DMACC instead of MFLO. This avoids both the normal
3954 MIPS III HI/LO hazards and the errata related to
3957 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
3961 if (DSP_ACC_REG_P (REGNO (src)))
3963 static char retval[] = "mf__\t%0,%q1";
3965 retval[2] = reg_names[REGNO (src)][4];
3966 retval[3] = reg_names[REGNO (src)][5];
3970 if (FP_REG_P (REGNO (src)))
3971 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3973 if (ALL_COP_REG_P (REGNO (src)))
3975 static char retval[] = "dmfc_\t%0,%1";
3977 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3978 return dbl_p ? retval : retval + 1;
3981 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3982 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3985 if (src_code == MEM)
3986 switch (GET_MODE_SIZE (mode))
3988 case 1: return "lbu\t%0,%1";
3989 case 2: return "lhu\t%0,%1";
3990 case 4: return "lw\t%0,%1";
3991 case 8: return "ld\t%0,%1";
3994 if (src_code == CONST_INT)
3996 /* Don't use the X format for the operand itself, because that
3997 will give out-of-range numbers for 64-bit hosts and 32-bit
4000 return "li\t%0,%1\t\t\t# %X1";
4002 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4005 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4009 if (src_code == HIGH)
4010 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4012 if (CONST_GP_P (src))
4013 return "move\t%0,%1";
4015 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4016 && mips_lo_relocs[symbol_type] != 0)
4018 /* A signed 16-bit constant formed by applying a relocation
4019 operator to a symbolic address. */
4020 gcc_assert (!mips_split_p[symbol_type]);
4021 return "li\t%0,%R1";
4024 if (symbolic_operand (src, VOIDmode))
4026 gcc_assert (TARGET_MIPS16
4027 ? TARGET_MIPS16_TEXT_LOADS
4028 : !TARGET_EXPLICIT_RELOCS);
4029 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4032 if (src_code == REG && FP_REG_P (REGNO (src)))
4034 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4036 if (GET_MODE (dest) == V2SFmode)
4037 return "mov.ps\t%0,%1";
4039 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4042 if (dest_code == MEM)
4043 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4045 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4047 if (src_code == MEM)
4048 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4050 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4052 static char retval[] = "l_c_\t%0,%1";
4054 retval[1] = (dbl_p ? 'd' : 'w');
4055 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4058 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4060 static char retval[] = "s_c_\t%1,%0";
4062 retval[1] = (dbl_p ? 'd' : 'w');
4063 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4069 /* Return true if CMP1 is a suitable second operand for integer ordering
4070 test CODE. See also the *sCC patterns in mips.md. */
4073 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4079 return reg_or_0_operand (cmp1, VOIDmode);
4083 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4087 return arith_operand (cmp1, VOIDmode);
4090 return sle_operand (cmp1, VOIDmode);
4093 return sleu_operand (cmp1, VOIDmode);
4100 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4101 integer ordering test *CODE, or if an equivalent combination can
4102 be formed by adjusting *CODE and *CMP1. When returning true, update
4103 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4107 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4108 enum machine_mode mode)
4110 HOST_WIDE_INT plus_one;
4112 if (mips_int_order_operand_ok_p (*code, *cmp1))
4115 if (GET_CODE (*cmp1) == CONST_INT)
4119 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4120 if (INTVAL (*cmp1) < plus_one)
4123 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4129 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4133 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4144 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4145 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4146 is nonnull, it's OK to set TARGET to the inverse of the result and
4147 flip *INVERT_PTR instead. */
4150 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4151 rtx target, rtx cmp0, rtx cmp1)
4153 enum machine_mode mode;
4155 /* First see if there is a MIPS instruction that can do this operation.
4156 If not, try doing the same for the inverse operation. If that also
4157 fails, force CMP1 into a register and try again. */
4158 mode = GET_MODE (cmp0);
4159 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4160 mips_emit_binary (code, target, cmp0, cmp1);
4163 enum rtx_code inv_code = reverse_condition (code);
4164 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4166 cmp1 = force_reg (mode, cmp1);
4167 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4169 else if (invert_ptr == 0)
4173 inv_target = mips_force_binary (GET_MODE (target),
4174 inv_code, cmp0, cmp1);
4175 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4179 *invert_ptr = !*invert_ptr;
4180 mips_emit_binary (inv_code, target, cmp0, cmp1);
4185 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4186 The register will have the same mode as CMP0. */
4189 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4191 if (cmp1 == const0_rtx)
4194 if (uns_arith_operand (cmp1, VOIDmode))
4195 return expand_binop (GET_MODE (cmp0), xor_optab,
4196 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4198 return expand_binop (GET_MODE (cmp0), sub_optab,
4199 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4202 /* Convert *CODE into a code that can be used in a floating-point
4203 scc instruction (C.cond.fmt). Return true if the values of
4204 the condition code registers will be inverted, with 0 indicating
4205 that the condition holds. */
4208 mips_reversed_fp_cond (enum rtx_code *code)
4215 *code = reverse_condition_maybe_unordered (*code);
4223 /* Convert a comparison into something that can be used in a branch or
4224 conditional move. cmp_operands[0] and cmp_operands[1] are the values
4225 being compared and *CODE is the code used to compare them.
4227 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4228 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4229 otherwise any standard branch condition can be used. The standard branch
4232 - EQ or NE between two registers.
4233 - any comparison between a register and zero. */
4236 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4238 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
4240 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
4242 *op0 = cmp_operands[0];
4243 *op1 = cmp_operands[1];
4245 else if (*code == EQ || *code == NE)
4249 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
4254 *op0 = cmp_operands[0];
4255 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
4260 /* The comparison needs a separate scc instruction. Store the
4261 result of the scc in *OP0 and compare it against zero. */
4262 bool invert = false;
4263 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
4264 mips_emit_int_order_test (*code, &invert, *op0,
4265 cmp_operands[0], cmp_operands[1]);
4266 *code = (invert ? EQ : NE);
4270 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
4272 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4273 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
4279 enum rtx_code cmp_code;
4281 /* Floating-point tests use a separate C.cond.fmt comparison to
4282 set a condition code register. The branch or conditional move
4283 will then compare that register against zero.
4285 Set CMP_CODE to the code of the comparison instruction and
4286 *CODE to the code that the branch or move should use. */
4288 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4290 ? gen_reg_rtx (CCmode)
4291 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4293 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
4297 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
4298 Store the result in TARGET and return true if successful.
4300 On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */
4303 mips_expand_scc (enum rtx_code code, rtx target)
4305 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
4308 if (code == EQ || code == NE)
4311 && reg_imm10_operand (cmp_operands[1], GET_MODE (cmp_operands[1])))
4312 mips_emit_binary (code, target, cmp_operands[0], cmp_operands[1]);
4315 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
4316 mips_emit_binary (code, target, zie, const0_rtx);
4320 mips_emit_int_order_test (code, 0, target,
4321 cmp_operands[0], cmp_operands[1]);
4325 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
4326 CODE and jump to OPERANDS[0] if the condition holds. */
4329 mips_expand_conditional_branch (rtx *operands, enum rtx_code code)
4331 rtx op0, op1, condition;
4333 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4334 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4335 emit_jump_insn (gen_condjump (condition, operands[0]));
4340 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4341 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4344 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4345 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4350 reversed_p = mips_reversed_fp_cond (&cond);
4351 cmp_result = gen_reg_rtx (CCV2mode);
4352 emit_insn (gen_scc_ps (cmp_result,
4353 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4355 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4358 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4362 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
4363 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
4364 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4367 mips_expand_conditional_move (rtx *operands)
4372 code = GET_CODE (operands[1]);
4373 mips_emit_compare (&code, &op0, &op1, true);
4374 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1),
4375 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4376 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4377 operands[2], operands[3])));
4380 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
4381 then trap if the condition holds. */
4384 mips_expand_conditional_trap (enum rtx_code code)
4387 enum machine_mode mode;
4389 /* MIPS conditional trap instructions don't have GT or LE flavors,
4390 so we must swap the operands and convert to LT and GE respectively. */
4397 code = swap_condition (code);
4398 op0 = cmp_operands[1];
4399 op1 = cmp_operands[0];
4403 op0 = cmp_operands[0];
4404 op1 = cmp_operands[1];
4408 mode = GET_MODE (cmp_operands[0]);
4409 op0 = force_reg (mode, op0);
4410 if (!arith_operand (op1, mode))
4411 op1 = force_reg (mode, op1);
4413 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4414 gen_rtx_fmt_ee (code, mode, op0, op1),
4418 /* Initialize *CUM for a call to a function of type FNTYPE. */
4421 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4423 memset (cum, 0, sizeof (*cum));
4424 cum->prototype = (fntype && prototype_p (fntype));
4425 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4428 /* Fill INFO with information about a single argument. CUM is the
4429 cumulative state for earlier arguments. MODE is the mode of this
4430 argument and TYPE is its type (if known). NAMED is true if this
4431 is a named (fixed) argument rather than a variable one. */
4434 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4435 enum machine_mode mode, tree type, int named)
4437 bool doubleword_aligned_p;
4438 unsigned int num_bytes, num_words, max_regs;
4440 /* Work out the size of the argument. */
4441 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4442 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4444 /* Decide whether it should go in a floating-point register, assuming
4445 one is free. Later code checks for availability.
4447 The checks against UNITS_PER_FPVALUE handle the soft-float and
4448 single-float cases. */
4452 /* The EABI conventions have traditionally been defined in terms
4453 of TYPE_MODE, regardless of the actual type. */
4454 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4455 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4456 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4461 /* Only leading floating-point scalars are passed in
4462 floating-point registers. We also handle vector floats the same
4463 say, which is OK because they are not covered by the standard ABI. */
4464 info->fpr_p = (!cum->gp_reg_found
4465 && cum->arg_number < 2
4467 || SCALAR_FLOAT_TYPE_P (type)
4468 || VECTOR_FLOAT_TYPE_P (type))
4469 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4470 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4471 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4476 /* Scalar, complex and vector floating-point types are passed in
4477 floating-point registers, as long as this is a named rather
4478 than a variable argument. */
4479 info->fpr_p = (named
4480 && (type == 0 || FLOAT_TYPE_P (type))
4481 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4482 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4483 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4484 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4486 /* ??? According to the ABI documentation, the real and imaginary
4487 parts of complex floats should be passed in individual registers.
4488 The real and imaginary parts of stack arguments are supposed
4489 to be contiguous and there should be an extra word of padding
4492 This has two problems. First, it makes it impossible to use a
4493 single "void *" va_list type, since register and stack arguments
4494 are passed differently. (At the time of writing, MIPSpro cannot
4495 handle complex float varargs correctly.) Second, it's unclear
4496 what should happen when there is only one register free.
4498 For now, we assume that named complex floats should go into FPRs
4499 if there are two FPRs free, otherwise they should be passed in the
4500 same way as a struct containing two floats. */
4502 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4503 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4505 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4506 info->fpr_p = false;
4516 /* See whether the argument has doubleword alignment. */
4517 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4519 /* Set REG_OFFSET to the register count we're interested in.
4520 The EABI allocates the floating-point registers separately,
4521 but the other ABIs allocate them like integer registers. */
4522 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4526 /* Advance to an even register if the argument is doubleword-aligned. */
4527 if (doubleword_aligned_p)
4528 info->reg_offset += info->reg_offset & 1;
4530 /* Work out the offset of a stack argument. */
4531 info->stack_offset = cum->stack_words;
4532 if (doubleword_aligned_p)
4533 info->stack_offset += info->stack_offset & 1;
4535 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4537 /* Partition the argument between registers and stack. */
4538 info->reg_words = MIN (num_words, max_regs);
4539 info->stack_words = num_words - info->reg_words;
4542 /* INFO describes a register argument that has the normal format for the
4543 argument's mode. Return the register it uses, assuming that FPRs are
4544 available if HARD_FLOAT_P. */
4547 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4549 if (!info->fpr_p || !hard_float_p)
4550 return GP_ARG_FIRST + info->reg_offset;
4551 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4552 /* In o32, the second argument is always passed in $f14
4553 for TARGET_DOUBLE_FLOAT, regardless of whether the
4554 first argument was a word or doubleword. */
4555 return FP_ARG_FIRST + 2;
4557 return FP_ARG_FIRST + info->reg_offset;
4560 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4563 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4565 return !TARGET_OLDABI;
4568 /* Implement FUNCTION_ARG. */
4571 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4572 tree type, int named)
4574 struct mips_arg_info info;
4576 /* We will be called with a mode of VOIDmode after the last argument
4577 has been seen. Whatever we return will be passed to the call expander.
4578 If we need a MIPS16 fp_code, return a REG with the code stored as
4580 if (mode == VOIDmode)
4582 if (TARGET_MIPS16 && cum->fp_code != 0)
4583 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4588 mips_get_arg_info (&info, cum, mode, type, named);
4590 /* Return straight away if the whole argument is passed on the stack. */
4591 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4594 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4595 contains a double in its entirety, then that 64-bit chunk is passed
4596 in a floating-point register. */
4598 && TARGET_HARD_FLOAT
4601 && TREE_CODE (type) == RECORD_TYPE
4602 && TYPE_SIZE_UNIT (type)
4603 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4607 /* First check to see if there is any such field. */
4608 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4609 if (TREE_CODE (field) == FIELD_DECL
4610 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4611 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4612 && host_integerp (bit_position (field), 0)
4613 && int_bit_position (field) % BITS_PER_WORD == 0)
4618 /* Now handle the special case by returning a PARALLEL
4619 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4620 chunks are passed in registers. */
4622 HOST_WIDE_INT bitpos;
4625 /* assign_parms checks the mode of ENTRY_PARM, so we must
4626 use the actual mode here. */
4627 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4630 field = TYPE_FIELDS (type);
4631 for (i = 0; i < info.reg_words; i++)
4635 for (; field; field = TREE_CHAIN (field))
4636 if (TREE_CODE (field) == FIELD_DECL
4637 && int_bit_position (field) >= bitpos)
4641 && int_bit_position (field) == bitpos
4642 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4643 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4644 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4646 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4649 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4650 GEN_INT (bitpos / BITS_PER_UNIT));
4652 bitpos += BITS_PER_WORD;
4658 /* Handle the n32/n64 conventions for passing complex floating-point
4659 arguments in FPR pairs. The real part goes in the lower register
4660 and the imaginary part goes in the upper register. */
4663 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4666 enum machine_mode inner;
4669 inner = GET_MODE_INNER (mode);
4670 regno = FP_ARG_FIRST + info.reg_offset;
4671 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4673 /* Real part in registers, imaginary part on stack. */
4674 gcc_assert (info.stack_words == info.reg_words);
4675 return gen_rtx_REG (inner, regno);
4679 gcc_assert (info.stack_words == 0);
4680 real = gen_rtx_EXPR_LIST (VOIDmode,
4681 gen_rtx_REG (inner, regno),
4683 imag = gen_rtx_EXPR_LIST (VOIDmode,
4685 regno + info.reg_words / 2),
4686 GEN_INT (GET_MODE_SIZE (inner)));
4687 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4691 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4694 /* Implement FUNCTION_ARG_ADVANCE. */
4697 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4698 tree type, int named)
4700 struct mips_arg_info info;
4702 mips_get_arg_info (&info, cum, mode, type, named);
4705 cum->gp_reg_found = true;
4707 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4708 an explanation of what this code does. It assumes that we're using
4709 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4711 if (cum->arg_number < 2 && info.fpr_p)
4712 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4714 /* Advance the register count. This has the effect of setting
4715 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4716 argument required us to skip the final GPR and pass the whole
4717 argument on the stack. */
4718 if (mips_abi != ABI_EABI || !info.fpr_p)
4719 cum->num_gprs = info.reg_offset + info.reg_words;
4720 else if (info.reg_words > 0)
4721 cum->num_fprs += MAX_FPRS_PER_FMT;
4723 /* Advance the stack word count. */
4724 if (info.stack_words > 0)
4725 cum->stack_words = info.stack_offset + info.stack_words;
4730 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4733 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4734 enum machine_mode mode, tree type, bool named)
4736 struct mips_arg_info info;
4738 mips_get_arg_info (&info, cum, mode, type, named);
4739 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4742 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4743 PARM_BOUNDARY bits of alignment, but will be given anything up
4744 to STACK_BOUNDARY bits if the type requires it. */
4747 mips_function_arg_boundary (enum machine_mode mode, tree type)
4749 unsigned int alignment;
4751 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4752 if (alignment < PARM_BOUNDARY)
4753 alignment = PARM_BOUNDARY;
4754 if (alignment > STACK_BOUNDARY)
4755 alignment = STACK_BOUNDARY;
4759 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4760 upward rather than downward. In other words, return true if the
4761 first byte of the stack slot has useful data, false if the last
4765 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4767 /* On little-endian targets, the first byte of every stack argument
4768 is passed in the first byte of the stack slot. */
4769 if (!BYTES_BIG_ENDIAN)
4772 /* Otherwise, integral types are padded downward: the last byte of a
4773 stack argument is passed in the last byte of the stack slot. */
4775 ? (INTEGRAL_TYPE_P (type)
4776 || POINTER_TYPE_P (type)
4777 || FIXED_POINT_TYPE_P (type))
4778 : (SCALAR_INT_MODE_P (mode)
4779 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4782 /* Big-endian o64 pads floating-point arguments downward. */
4783 if (mips_abi == ABI_O64)
4784 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4787 /* Other types are padded upward for o32, o64, n32 and n64. */
4788 if (mips_abi != ABI_EABI)
4791 /* Arguments smaller than a stack slot are padded downward. */
4792 if (mode != BLKmode)
4793 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4795 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4798 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4799 if the least significant byte of the register has useful data. Return
4800 the opposite if the most significant byte does. */
4803 mips_pad_reg_upward (enum machine_mode mode, tree type)
4805 /* No shifting is required for floating-point arguments. */
4806 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4807 return !BYTES_BIG_ENDIAN;
4809 /* Otherwise, apply the same padding to register arguments as we do
4810 to stack arguments. */
4811 return mips_pad_arg_upward (mode, type);
4814 /* Return nonzero when an argument must be passed by reference. */
4817 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4818 enum machine_mode mode, const_tree type,
4819 bool named ATTRIBUTE_UNUSED)
4821 if (mips_abi == ABI_EABI)
4825 /* ??? How should SCmode be handled? */
4826 if (mode == DImode || mode == DFmode
4827 || mode == DQmode || mode == UDQmode
4828 || mode == DAmode || mode == UDAmode)
4831 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4832 return size == -1 || size > UNITS_PER_WORD;
4836 /* If we have a variable-sized parameter, we have no choice. */
4837 return targetm.calls.must_pass_in_stack (mode, type);
4841 /* Implement TARGET_CALLEE_COPIES. */
4844 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4845 enum machine_mode mode ATTRIBUTE_UNUSED,
4846 const_tree type ATTRIBUTE_UNUSED, bool named)
4848 return mips_abi == ABI_EABI && named;
4851 /* See whether VALTYPE is a record whose fields should be returned in
4852 floating-point registers. If so, return the number of fields and
4853 list them in FIELDS (which should have two elements). Return 0
4856 For n32 & n64, a structure with one or two fields is returned in
4857 floating-point registers as long as every field has a floating-point
4861 mips_fpr_return_fields (const_tree valtype, tree *fields)
4869 if (TREE_CODE (valtype) != RECORD_TYPE)
4873 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4875 if (TREE_CODE (field) != FIELD_DECL)
4878 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
4884 fields[i++] = field;
4889 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4890 a value in the most significant part of $2/$3 if:
4892 - the target is big-endian;
4894 - the value has a structure or union type (we generalize this to
4895 cover aggregates from other languages too); and
4897 - the structure is not returned in floating-point registers. */
4900 mips_return_in_msb (const_tree valtype)
4904 return (TARGET_NEWABI
4905 && TARGET_BIG_ENDIAN
4906 && AGGREGATE_TYPE_P (valtype)
4907 && mips_fpr_return_fields (valtype, fields) == 0);
4910 /* Return true if the function return value MODE will get returned in a
4911 floating-point register. */
4914 mips_return_mode_in_fpr_p (enum machine_mode mode)
4916 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4917 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4918 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4919 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4922 /* Return the representation of an FPR return register when the
4923 value being returned in FP_RETURN has mode VALUE_MODE and the
4924 return type itself has mode TYPE_MODE. On NewABI targets,
4925 the two modes may be different for structures like:
4927 struct __attribute__((packed)) foo { float f; }
4929 where we return the SFmode value of "f" in FP_RETURN, but where
4930 the structure itself has mode BLKmode. */
4933 mips_return_fpr_single (enum machine_mode type_mode,
4934 enum machine_mode value_mode)
4938 x = gen_rtx_REG (value_mode, FP_RETURN);
4939 if (type_mode != value_mode)
4941 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
4942 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
4947 /* Return a composite value in a pair of floating-point registers.
4948 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4949 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4952 For n32 & n64, $f0 always holds the first value and $f2 the second.
4953 Otherwise the values are packed together as closely as possible. */
4956 mips_return_fpr_pair (enum machine_mode mode,
4957 enum machine_mode mode1, HOST_WIDE_INT offset1,
4958 enum machine_mode mode2, HOST_WIDE_INT offset2)
4962 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4963 return gen_rtx_PARALLEL
4966 gen_rtx_EXPR_LIST (VOIDmode,
4967 gen_rtx_REG (mode1, FP_RETURN),
4969 gen_rtx_EXPR_LIST (VOIDmode,
4970 gen_rtx_REG (mode2, FP_RETURN + inc),
4971 GEN_INT (offset2))));
4975 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4976 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4977 VALTYPE is null and MODE is the mode of the return value. */
4980 mips_function_value (const_tree valtype, enum machine_mode mode)
4987 mode = TYPE_MODE (valtype);
4988 unsigned_p = TYPE_UNSIGNED (valtype);
4990 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4991 we must promote the mode just as PROMOTE_MODE does. */
4992 mode = promote_mode (valtype, mode, &unsigned_p, 1);
4994 /* Handle structures whose fields are returned in $f0/$f2. */
4995 switch (mips_fpr_return_fields (valtype, fields))
4998 return mips_return_fpr_single (mode,
4999 TYPE_MODE (TREE_TYPE (fields[0])));
5002 return mips_return_fpr_pair (mode,
5003 TYPE_MODE (TREE_TYPE (fields[0])),
5004 int_byte_position (fields[0]),
5005 TYPE_MODE (TREE_TYPE (fields[1])),
5006 int_byte_position (fields[1]));
5009 /* If a value is passed in the most significant part of a register, see
5010 whether we have to round the mode up to a whole number of words. */
5011 if (mips_return_in_msb (valtype))
5013 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5014 if (size % UNITS_PER_WORD != 0)
5016 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5017 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5021 /* For EABI, the class of return register depends entirely on MODE.
5022 For example, "struct { some_type x; }" and "union { some_type x; }"
5023 are returned in the same way as a bare "some_type" would be.
5024 Other ABIs only use FPRs for scalar, complex or vector types. */
5025 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5026 return gen_rtx_REG (mode, GP_RETURN);
5031 /* Handle long doubles for n32 & n64. */
5033 return mips_return_fpr_pair (mode,
5035 DImode, GET_MODE_SIZE (mode) / 2);
5037 if (mips_return_mode_in_fpr_p (mode))
5039 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5040 return mips_return_fpr_pair (mode,
5041 GET_MODE_INNER (mode), 0,
5042 GET_MODE_INNER (mode),
5043 GET_MODE_SIZE (mode) / 2);
5045 return gen_rtx_REG (mode, FP_RETURN);
5049 return gen_rtx_REG (mode, GP_RETURN);
5052 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5053 all BLKmode objects are returned in memory. Under the n32, n64
5054 and embedded ABIs, small structures are returned in a register.
5055 Objects with varying size must still be returned in memory, of
5059 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5061 return (TARGET_OLDABI
5062 ? TYPE_MODE (type) == BLKmode
5063 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5066 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5069 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5070 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5073 CUMULATIVE_ARGS local_cum;
5074 int gp_saved, fp_saved;
5076 /* The caller has advanced CUM up to, but not beyond, the last named
5077 argument. Advance a local copy of CUM past the last "real" named
5078 argument, to find out how many registers are left over. */
5080 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5082 /* Found out how many registers we need to save. */
5083 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5084 fp_saved = (EABI_FLOAT_VARARGS_P
5085 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5094 ptr = plus_constant (virtual_incoming_args_rtx,
5095 REG_PARM_STACK_SPACE (cfun->decl)
5096 - gp_saved * UNITS_PER_WORD);
5097 mem = gen_frame_mem (BLKmode, ptr);
5098 set_mem_alias_set (mem, get_varargs_alias_set ());
5100 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5105 /* We can't use move_block_from_reg, because it will use
5107 enum machine_mode mode;
5110 /* Set OFF to the offset from virtual_incoming_args_rtx of
5111 the first float register. The FP save area lies below
5112 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5113 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5114 off -= fp_saved * UNITS_PER_FPREG;
5116 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5118 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5119 i += MAX_FPRS_PER_FMT)
5123 ptr = plus_constant (virtual_incoming_args_rtx, off);
5124 mem = gen_frame_mem (mode, ptr);
5125 set_mem_alias_set (mem, get_varargs_alias_set ());
5126 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5127 off += UNITS_PER_HWFPVALUE;
5131 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5132 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5133 + fp_saved * UNITS_PER_FPREG);
5136 /* Implement TARGET_BUILTIN_VA_LIST. */
5139 mips_build_builtin_va_list (void)
5141 if (EABI_FLOAT_VARARGS_P)
5143 /* We keep 3 pointers, and two offsets.
5145 Two pointers are to the overflow area, which starts at the CFA.
5146 One of these is constant, for addressing into the GPR save area
5147 below it. The other is advanced up the stack through the
5150 The third pointer is to the bottom of the GPR save area.
5151 Since the FPR save area is just below it, we can address
5152 FPR slots off this pointer.
5154 We also keep two one-byte offsets, which are to be subtracted
5155 from the constant pointers to yield addresses in the GPR and
5156 FPR save areas. These are downcounted as float or non-float
5157 arguments are used, and when they get to zero, the argument
5158 must be obtained from the overflow region. */
5159 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5162 record = lang_hooks.types.make_type (RECORD_TYPE);
5164 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
5166 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
5168 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
5170 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
5171 unsigned_char_type_node);
5172 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
5173 unsigned_char_type_node);
5174 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5175 warn on every user file. */
5176 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5177 array = build_array_type (unsigned_char_type_node,
5178 build_index_type (index));
5179 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
5181 DECL_FIELD_CONTEXT (f_ovfl) = record;
5182 DECL_FIELD_CONTEXT (f_gtop) = record;
5183 DECL_FIELD_CONTEXT (f_ftop) = record;
5184 DECL_FIELD_CONTEXT (f_goff) = record;
5185 DECL_FIELD_CONTEXT (f_foff) = record;
5186 DECL_FIELD_CONTEXT (f_res) = record;
5188 TYPE_FIELDS (record) = f_ovfl;
5189 TREE_CHAIN (f_ovfl) = f_gtop;
5190 TREE_CHAIN (f_gtop) = f_ftop;
5191 TREE_CHAIN (f_ftop) = f_goff;
5192 TREE_CHAIN (f_goff) = f_foff;
5193 TREE_CHAIN (f_foff) = f_res;
5195 layout_type (record);
5198 else if (TARGET_IRIX && TARGET_IRIX6)
5199 /* On IRIX 6, this type is 'char *'. */
5200 return build_pointer_type (char_type_node);
5202 /* Otherwise, we use 'void *'. */
5203 return ptr_type_node;
5206 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5209 mips_va_start (tree valist, rtx nextarg)
5211 if (EABI_FLOAT_VARARGS_P)
5213 const CUMULATIVE_ARGS *cum;
5214 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5215 tree ovfl, gtop, ftop, goff, foff;
5217 int gpr_save_area_size;
5218 int fpr_save_area_size;
5221 cum = &crtl->args.info;
5223 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5225 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5227 f_ovfl = TYPE_FIELDS (va_list_type_node);
5228 f_gtop = TREE_CHAIN (f_ovfl);
5229 f_ftop = TREE_CHAIN (f_gtop);
5230 f_goff = TREE_CHAIN (f_ftop);
5231 f_foff = TREE_CHAIN (f_goff);
5233 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5235 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5237 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5239 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5241 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5244 /* Emit code to initialize OVFL, which points to the next varargs
5245 stack argument. CUM->STACK_WORDS gives the number of stack
5246 words used by named arguments. */
5247 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5248 if (cum->stack_words > 0)
5249 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5250 size_int (cum->stack_words * UNITS_PER_WORD));
5251 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5252 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5254 /* Emit code to initialize GTOP, the top of the GPR save area. */
5255 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5256 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5257 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5259 /* Emit code to initialize FTOP, the top of the FPR save area.
5260 This address is gpr_save_area_bytes below GTOP, rounded
5261 down to the next fp-aligned boundary. */
5262 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5263 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5264 fpr_offset &= -UNITS_PER_FPVALUE;
5266 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5267 size_int (-fpr_offset));
5268 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5269 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5271 /* Emit code to initialize GOFF, the offset from GTOP of the
5272 next GPR argument. */
5273 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5274 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5275 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5277 /* Likewise emit code to initialize FOFF, the offset from FTOP
5278 of the next FPR argument. */
5279 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5280 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5281 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5285 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5286 std_expand_builtin_va_start (valist, nextarg);
5290 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5293 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5299 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5301 type = build_pointer_type (type);
5303 if (!EABI_FLOAT_VARARGS_P)
5304 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5307 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5308 tree ovfl, top, off, align;
5309 HOST_WIDE_INT size, rsize, osize;
5312 f_ovfl = TYPE_FIELDS (va_list_type_node);
5313 f_gtop = TREE_CHAIN (f_ovfl);
5314 f_ftop = TREE_CHAIN (f_gtop);
5315 f_goff = TREE_CHAIN (f_ftop);
5316 f_foff = TREE_CHAIN (f_goff);
5320 TOP be the top of the GPR or FPR save area;
5321 OFF be the offset from TOP of the next register;
5322 ADDR_RTX be the address of the argument;
5323 SIZE be the number of bytes in the argument type;
5324 RSIZE be the number of bytes used to store the argument
5325 when it's in the register save area; and
5326 OSIZE be the number of bytes used to store it when it's
5327 in the stack overflow area.
5329 The code we want is:
5331 1: off &= -rsize; // round down
5334 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5339 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5340 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5344 [1] and [9] can sometimes be optimized away. */
5346 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5348 size = int_size_in_bytes (type);
5350 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5351 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5353 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5354 unshare_expr (valist), f_ftop, NULL_TREE);
5355 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5356 unshare_expr (valist), f_foff, NULL_TREE);
5358 /* When va_start saves FPR arguments to the stack, each slot
5359 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5360 argument's precision. */
5361 rsize = UNITS_PER_HWFPVALUE;
5363 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5364 (= PARM_BOUNDARY bits). This can be different from RSIZE
5367 (1) On 32-bit targets when TYPE is a structure such as:
5369 struct s { float f; };
5371 Such structures are passed in paired FPRs, so RSIZE
5372 will be 8 bytes. However, the structure only takes
5373 up 4 bytes of memory, so OSIZE will only be 4.
5375 (2) In combinations such as -mgp64 -msingle-float
5376 -fshort-double. Doubles passed in registers will then take
5377 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5378 stack take up UNITS_PER_WORD bytes. */
5379 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5383 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5384 unshare_expr (valist), f_gtop, NULL_TREE);
5385 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5386 unshare_expr (valist), f_goff, NULL_TREE);
5387 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5388 if (rsize > UNITS_PER_WORD)
5390 /* [1] Emit code for: off &= -rsize. */
5391 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5392 build_int_cst (TREE_TYPE (off), -rsize));
5393 gimplify_assign (unshare_expr (off), t, pre_p);
5398 /* [2] Emit code to branch if off == 0. */
5399 t = build2 (NE_EXPR, boolean_type_node, off,
5400 build_int_cst (TREE_TYPE (off), 0));
5401 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5403 /* [5] Emit code for: off -= rsize. We do this as a form of
5404 post-decrement not available to C. */
5405 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5406 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5408 /* [4] Emit code for:
5409 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5410 t = fold_convert (sizetype, t);
5411 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5412 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5413 if (BYTES_BIG_ENDIAN && rsize > size)
5415 u = size_int (rsize - size);
5416 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5418 COND_EXPR_THEN (addr) = t;
5420 if (osize > UNITS_PER_WORD)
5422 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5423 u = size_int (osize - 1);
5424 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5425 unshare_expr (ovfl), u);
5426 t = fold_convert (sizetype, t);
5427 u = size_int (-osize);
5428 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5429 t = fold_convert (TREE_TYPE (ovfl), t);
5430 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5431 unshare_expr (ovfl), t);
5436 /* [10, 11] Emit code for:
5437 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5439 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5440 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5441 if (BYTES_BIG_ENDIAN && osize > size)
5443 u = size_int (osize - size);
5444 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5447 /* String [9] and [10, 11] together. */
5449 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5450 COND_EXPR_ELSE (addr) = t;
5452 addr = fold_convert (build_pointer_type (type), addr);
5453 addr = build_va_arg_indirect_ref (addr);
5457 addr = build_va_arg_indirect_ref (addr);
5462 /* Start a definition of function NAME. MIPS16_P indicates whether the
5463 function contains MIPS16 code. */
5466 mips_start_function_definition (const char *name, bool mips16_p)
5469 fprintf (asm_out_file, "\t.set\tmips16\n");
5471 fprintf (asm_out_file, "\t.set\tnomips16\n");
5473 if (!flag_inhibit_size_directive)
5475 fputs ("\t.ent\t", asm_out_file);
5476 assemble_name (asm_out_file, name);
5477 fputs ("\n", asm_out_file);
5480 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5482 /* Start the definition proper. */
5483 assemble_name (asm_out_file, name);
5484 fputs (":\n", asm_out_file);
5487 /* End a function definition started by mips_start_function_definition. */
5490 mips_end_function_definition (const char *name)
5492 if (!flag_inhibit_size_directive)
5494 fputs ("\t.end\t", asm_out_file);
5495 assemble_name (asm_out_file, name);
5496 fputs ("\n", asm_out_file);
5500 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5503 mips_ok_for_lazy_binding_p (rtx x)
5505 return (TARGET_USE_GOT
5506 && GET_CODE (x) == SYMBOL_REF
5507 && !SYMBOL_REF_BIND_NOW_P (x)
5508 && !mips_symbol_binds_local_p (x));
5511 /* Load function address ADDR into register DEST. TYPE is as for
5512 mips_expand_call. Return true if we used an explicit lazy-binding
5516 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5518 /* If we're generating PIC, and this call is to a global function,
5519 try to allow its address to be resolved lazily. This isn't
5520 possible for sibcalls when $gp is call-saved because the value
5521 of $gp on entry to the stub would be our caller's gp, not ours. */
5522 if (TARGET_EXPLICIT_RELOCS
5523 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5524 && mips_ok_for_lazy_binding_p (addr))
5526 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5527 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5532 mips_emit_move (dest, addr);
5537 /* Each locally-defined hard-float MIPS16 function has a local symbol
5538 associated with it. This hash table maps the function symbol (FUNC)
5539 to the local symbol (LOCAL). */
5540 struct GTY(()) mips16_local_alias {
5544 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5546 /* Hash table callbacks for mips16_local_aliases. */
5549 mips16_local_aliases_hash (const void *entry)
5551 const struct mips16_local_alias *alias;
5553 alias = (const struct mips16_local_alias *) entry;
5554 return htab_hash_string (XSTR (alias->func, 0));
5558 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5560 const struct mips16_local_alias *alias1, *alias2;
5562 alias1 = (const struct mips16_local_alias *) entry1;
5563 alias2 = (const struct mips16_local_alias *) entry2;
5564 return rtx_equal_p (alias1->func, alias2->func);
5567 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5568 Return a local alias for it, creating a new one if necessary. */
5571 mips16_local_alias (rtx func)
5573 struct mips16_local_alias *alias, tmp_alias;
5576 /* Create the hash table if this is the first call. */
5577 if (mips16_local_aliases == NULL)
5578 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5579 mips16_local_aliases_eq, NULL);
5581 /* Look up the function symbol, creating a new entry if need be. */
5582 tmp_alias.func = func;
5583 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5584 gcc_assert (slot != NULL);
5586 alias = (struct mips16_local_alias *) *slot;
5589 const char *func_name, *local_name;
5592 /* Create a new SYMBOL_REF for the local symbol. The choice of
5593 __fn_local_* is based on the __fn_stub_* names that we've
5594 traditionally used for the non-MIPS16 stub. */
5595 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5596 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5597 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5598 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5600 /* Create a new structure to represent the mapping. */
5601 alias = GGC_NEW (struct mips16_local_alias);
5603 alias->local = local;
5606 return alias->local;
5609 /* A chained list of functions for which mips16_build_call_stub has already
5610 generated a stub. NAME is the name of the function and FP_RET_P is true
5611 if the function returns a value in floating-point registers. */
5612 struct mips16_stub {
5613 struct mips16_stub *next;
5617 static struct mips16_stub *mips16_stubs;
5619 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5622 mips16_stub_function (const char *name)
5626 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5627 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5631 /* Return the two-character string that identifies floating-point
5632 return mode MODE in the name of a MIPS16 function stub. */
5635 mips16_call_stub_mode_suffix (enum machine_mode mode)
5639 else if (mode == DFmode)
5641 else if (mode == SCmode)
5643 else if (mode == DCmode)
5645 else if (mode == V2SFmode)
5651 /* Write instructions to move a 32-bit value between general register
5652 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5653 from GPREG to FPREG and 'f' to move in the opposite direction. */
5656 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5658 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5659 reg_names[gpreg], reg_names[fpreg]);
5662 /* Likewise for 64-bit values. */
5665 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5668 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5669 reg_names[gpreg], reg_names[fpreg]);
5670 else if (TARGET_FLOAT64)
5672 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5673 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5674 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5675 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5679 /* Move the least-significant word. */
5680 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5681 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5682 /* ...then the most significant word. */
5683 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5684 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5688 /* Write out code to move floating-point arguments into or out of
5689 general registers. FP_CODE is the code describing which arguments
5690 are present (see the comment above the definition of CUMULATIVE_ARGS
5691 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5694 mips_output_args_xfer (int fp_code, char direction)
5696 unsigned int gparg, fparg, f;
5697 CUMULATIVE_ARGS cum;
5699 /* This code only works for o32 and o64. */
5700 gcc_assert (TARGET_OLDABI);
5702 mips_init_cumulative_args (&cum, NULL);
5704 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5706 enum machine_mode mode;
5707 struct mips_arg_info info;
5711 else if ((f & 3) == 2)
5716 mips_get_arg_info (&info, &cum, mode, NULL, true);
5717 gparg = mips_arg_regno (&info, false);
5718 fparg = mips_arg_regno (&info, true);
5721 mips_output_32bit_xfer (direction, gparg, fparg);
5723 mips_output_64bit_xfer (direction, gparg, fparg);
5725 mips_function_arg_advance (&cum, mode, NULL, true);
5729 /* Write a MIPS16 stub for the current function. This stub is used
5730 for functions which take arguments in the floating-point registers.
5731 It is normal-mode code that moves the floating-point arguments
5732 into the general registers and then jumps to the MIPS16 code. */
5735 mips16_build_function_stub (void)
5737 const char *fnname, *alias_name, *separator;
5738 char *secname, *stubname;
5743 /* Create the name of the stub, and its unique section. */
5744 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5745 alias = mips16_local_alias (symbol);
5747 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5748 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5749 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5750 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5752 /* Build a decl for the stub. */
5753 stubdecl = build_decl (FUNCTION_DECL, get_identifier (stubname),
5754 build_function_type (void_type_node, NULL_TREE));
5755 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5756 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5758 /* Output a comment. */
5759 fprintf (asm_out_file, "\t# Stub function for %s (",
5760 current_function_name ());
5762 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5764 fprintf (asm_out_file, "%s%s", separator,
5765 (f & 3) == 1 ? "float" : "double");
5768 fprintf (asm_out_file, ")\n");
5770 /* Start the function definition. */
5771 assemble_start_function (stubdecl, stubname);
5772 mips_start_function_definition (stubname, false);
5774 /* If generating pic2 code, either set up the global pointer or
5776 if (TARGET_ABICALLS_PIC2)
5778 if (TARGET_ABSOLUTE_ABICALLS)
5779 fprintf (asm_out_file, "\t.option\tpic0\n");
5782 output_asm_insn ("%(.cpload\t%^%)", NULL);
5783 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5784 target function is. Use a local GOT access when loading the
5785 symbol, to cut down on the number of unnecessary GOT entries
5786 for stubs that aren't needed. */
5787 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
5792 /* Load the address of the MIPS16 function into $25. Do this first so
5793 that targets with coprocessor interlocks can use an MFC1 to fill the
5795 output_asm_insn ("la\t%^,%0", &symbol);
5797 /* Move the arguments from floating-point registers to general registers. */
5798 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5800 /* Jump to the MIPS16 function. */
5801 output_asm_insn ("jr\t%^", NULL);
5803 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
5804 fprintf (asm_out_file, "\t.option\tpic2\n");
5806 mips_end_function_definition (stubname);
5808 /* If the linker needs to create a dynamic symbol for the target
5809 function, it will associate the symbol with the stub (which,
5810 unlike the target function, follows the proper calling conventions).
5811 It is therefore useful to have a local alias for the target function,
5812 so that it can still be identified as MIPS16 code. As an optimization,
5813 this symbol can also be used for indirect MIPS16 references from
5814 within this file. */
5815 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
5817 switch_to_section (function_section (current_function_decl));
5820 /* The current function is a MIPS16 function that returns a value in an FPR.
5821 Copy the return value from its soft-float to its hard-float location.
5822 libgcc2 has special non-MIPS16 helper functions for each case. */
5825 mips16_copy_fpr_return_value (void)
5827 rtx fn, insn, retval;
5829 enum machine_mode return_mode;
5832 return_type = DECL_RESULT (current_function_decl);
5833 return_mode = DECL_MODE (return_type);
5835 name = ACONCAT (("__mips16_ret_",
5836 mips16_call_stub_mode_suffix (return_mode),
5838 fn = mips16_stub_function (name);
5840 /* The function takes arguments in $2 (and possibly $3), so calls
5841 to it cannot be lazily bound. */
5842 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
5844 /* Model the call as something that takes the GPR return value as
5845 argument and returns an "updated" value. */
5846 retval = gen_rtx_REG (return_mode, GP_RETURN);
5847 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
5848 const0_rtx, NULL_RTX, false);
5849 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
5852 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
5853 RETVAL is the location of the return value, or null if this is
5854 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5855 arguments and FP_CODE is the code built by mips_function_arg;
5856 see the comment above CUMULATIVE_ARGS for details.
5858 There are three alternatives:
5860 - If a stub was needed, emit the call and return the call insn itself.
5862 - If we can avoid using a stub by redirecting the call, set *FN_PTR
5863 to the new target and return null.
5865 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
5868 A stub is needed for calls to functions that, in normal mode,
5869 receive arguments in FPRs or return values in FPRs. The stub
5870 copies the arguments from their soft-float positions to their
5871 hard-float positions, calls the real function, then copies the
5872 return value from its hard-float position to its soft-float
5875 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
5876 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
5877 automatically redirects the JAL to the stub, otherwise the JAL
5878 continues to call FN directly. */
5881 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
5885 struct mips16_stub *l;
5888 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5889 we were invoked with the -msoft-float option. */
5890 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5893 /* Figure out whether the value might come back in a floating-point
5895 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
5897 /* We don't need to do anything if there were no floating-point
5898 arguments and the value will not be returned in a floating-point
5900 if (fp_code == 0 && !fp_ret_p)
5903 /* We don't need to do anything if this is a call to a special
5904 MIPS16 support function. */
5906 if (mips16_stub_function_p (fn))
5909 /* This code will only work for o32 and o64 abis. The other ABI's
5910 require more sophisticated support. */
5911 gcc_assert (TARGET_OLDABI);
5913 /* If we're calling via a function pointer, use one of the magic
5914 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5915 Each stub expects the function address to arrive in register $2. */
5916 if (GET_CODE (fn) != SYMBOL_REF
5917 || !call_insn_operand (fn, VOIDmode))
5920 rtx stub_fn, insn, addr;
5923 /* If this is a locally-defined and locally-binding function,
5924 avoid the stub by calling the local alias directly. */
5925 if (mips16_local_function_p (fn))
5927 *fn_ptr = mips16_local_alias (fn);
5931 /* Create a SYMBOL_REF for the libgcc.a function. */
5933 sprintf (buf, "__mips16_call_stub_%s_%d",
5934 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5937 sprintf (buf, "__mips16_call_stub_%d", fp_code);
5938 stub_fn = mips16_stub_function (buf);
5940 /* The function uses $2 as an argument, so calls to it
5941 cannot be lazily bound. */
5942 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
5944 /* Load the target function into $2. */
5945 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
5946 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
5948 /* Emit the call. */
5949 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
5950 args_size, NULL_RTX, lazy_p);
5952 /* Tell GCC that this call does indeed use the value of $2. */
5953 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
5955 /* If we are handling a floating-point return value, we need to
5956 save $18 in the function prologue. Putting a note on the
5957 call will mean that df_regs_ever_live_p ($18) will be true if the
5958 call is not eliminated, and we can check that in the prologue
5961 CALL_INSN_FUNCTION_USAGE (insn) =
5962 gen_rtx_EXPR_LIST (VOIDmode,
5963 gen_rtx_CLOBBER (VOIDmode,
5964 gen_rtx_REG (word_mode, 18)),
5965 CALL_INSN_FUNCTION_USAGE (insn));
5970 /* We know the function we are going to call. If we have already
5971 built a stub, we don't need to do anything further. */
5972 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5973 for (l = mips16_stubs; l != NULL; l = l->next)
5974 if (strcmp (l->name, fnname) == 0)
5979 const char *separator;
5980 char *secname, *stubname;
5981 tree stubid, stubdecl;
5984 /* If the function does not return in FPRs, the special stub
5988 If the function does return in FPRs, the stub section is named
5989 .mips16.call.fp.FNNAME
5991 Build a decl for the stub. */
5992 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
5994 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
5996 stubid = get_identifier (stubname);
5997 stubdecl = build_decl (FUNCTION_DECL, stubid,
5998 build_function_type (void_type_node, NULL_TREE));
5999 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6000 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE,
6003 /* Output a comment. */
6004 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6006 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6010 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6012 fprintf (asm_out_file, "%s%s", separator,
6013 (f & 3) == 1 ? "float" : "double");
6016 fprintf (asm_out_file, ")\n");
6018 /* Start the function definition. */
6019 assemble_start_function (stubdecl, stubname);
6020 mips_start_function_definition (stubname, false);
6024 /* Load the address of the MIPS16 function into $25. Do this
6025 first so that targets with coprocessor interlocks can use
6026 an MFC1 to fill the delay slot. */
6027 if (TARGET_EXPLICIT_RELOCS)
6029 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6030 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6033 output_asm_insn ("la\t%^,%0", &fn);
6036 /* Move the arguments from general registers to floating-point
6038 mips_output_args_xfer (fp_code, 't');
6042 /* Jump to the previously-loaded address. */
6043 output_asm_insn ("jr\t%^", NULL);
6047 /* Save the return address in $18 and call the non-MIPS16 function.
6048 The stub's caller knows that $18 might be clobbered, even though
6049 $18 is usually a call-saved register. */
6050 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6051 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
6052 output_asm_insn (MIPS_CALL ("jal", &fn, 0), &fn);
6054 /* Move the result from floating-point registers to
6055 general registers. */
6056 switch (GET_MODE (retval))
6059 mips_output_32bit_xfer ('f', GP_RETURN + 1,
6060 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6063 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6064 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6066 /* On 64-bit targets, complex floats are returned in
6067 a single GPR, such that "sd" on a suitably-aligned
6068 target would store the value correctly. */
6069 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6070 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6071 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6072 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6073 reg_names[GP_RETURN],
6074 reg_names[GP_RETURN],
6075 reg_names[GP_RETURN + 1]);
6080 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6081 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6085 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6091 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6094 #ifdef ASM_DECLARE_FUNCTION_SIZE
6095 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6098 mips_end_function_definition (stubname);
6100 /* Record this stub. */
6101 l = XNEW (struct mips16_stub);
6102 l->name = xstrdup (fnname);
6103 l->fp_ret_p = fp_ret_p;
6104 l->next = mips16_stubs;
6108 /* If we expect a floating-point return value, but we've built a
6109 stub which does not expect one, then we're in trouble. We can't
6110 use the existing stub, because it won't handle the floating-point
6111 value. We can't build a new stub, because the linker won't know
6112 which stub to use for the various calls in this object file.
6113 Fortunately, this case is illegal, since it means that a function
6114 was declared in two different ways in a single compilation. */
6115 if (fp_ret_p && !l->fp_ret_p)
6116 error ("cannot handle inconsistent calls to %qs", fnname);
6118 if (retval == NULL_RTX)
6119 insn = gen_call_internal_direct (fn, args_size);
6121 insn = gen_call_value_internal_direct (retval, fn, args_size);
6122 insn = mips_emit_call_insn (insn, fn, fn, false);
6124 /* If we are calling a stub which handles a floating-point return
6125 value, we need to arrange to save $18 in the prologue. We do this
6126 by marking the function call as using the register. The prologue
6127 will later see that it is used, and emit code to save it. */
6129 CALL_INSN_FUNCTION_USAGE (insn) =
6130 gen_rtx_EXPR_LIST (VOIDmode,
6131 gen_rtx_CLOBBER (VOIDmode,
6132 gen_rtx_REG (word_mode, 18)),
6133 CALL_INSN_FUNCTION_USAGE (insn));
6138 /* Expand a call of type TYPE. RESULT is where the result will go (null
6139 for "call"s and "sibcall"s), ADDR is the address of the function,
6140 ARGS_SIZE is the size of the arguments and AUX is the value passed
6141 to us by mips_function_arg. LAZY_P is true if this call already
6142 involves a lazily-bound function address (such as when calling
6143 functions through a MIPS16 hard-float stub).
6145 Return the call itself. */
6148 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6149 rtx args_size, rtx aux, bool lazy_p)
6151 rtx orig_addr, pattern, insn;
6154 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6155 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6158 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6163 if (!call_insn_operand (addr, VOIDmode))
6165 if (type == MIPS_CALL_EPILOGUE)
6166 addr = MIPS_EPILOGUE_TEMP (Pmode);
6168 addr = gen_reg_rtx (Pmode);
6169 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6174 rtx (*fn) (rtx, rtx);
6176 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6177 fn = gen_call_split;
6178 else if (type == MIPS_CALL_SIBCALL)
6179 fn = gen_sibcall_internal;
6181 fn = gen_call_internal;
6183 pattern = fn (addr, args_size);
6185 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6187 /* Handle return values created by mips_return_fpr_pair. */
6188 rtx (*fn) (rtx, rtx, rtx, rtx);
6191 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6192 fn = gen_call_value_multiple_split;
6193 else if (type == MIPS_CALL_SIBCALL)
6194 fn = gen_sibcall_value_multiple_internal;
6196 fn = gen_call_value_multiple_internal;
6198 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6199 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6200 pattern = fn (reg1, addr, args_size, reg2);
6204 rtx (*fn) (rtx, rtx, rtx);
6206 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6207 fn = gen_call_value_split;
6208 else if (type == MIPS_CALL_SIBCALL)
6209 fn = gen_sibcall_value_internal;
6211 fn = gen_call_value_internal;
6213 /* Handle return values created by mips_return_fpr_single. */
6214 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6215 result = XEXP (XVECEXP (result, 0, 0), 0);
6216 pattern = fn (result, addr, args_size);
6219 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6222 /* Split call instruction INSN into a $gp-clobbering call and
6223 (where necessary) an instruction to restore $gp from its save slot.
6224 CALL_PATTERN is the pattern of the new call. */
6227 mips_split_call (rtx insn, rtx call_pattern)
6231 new_insn = emit_call_insn (call_pattern);
6232 CALL_INSN_FUNCTION_USAGE (new_insn)
6233 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6234 if (!find_reg_note (insn, REG_NORETURN, 0))
6235 /* Pick a temporary register that is suitable for both MIPS16 and
6236 non-MIPS16 code. $4 and $5 are used for returning complex double
6237 values in soft-float code, so $6 is the first suitable candidate. */
6238 mips_restore_gp (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6241 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6244 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6246 if (!TARGET_SIBCALLS)
6249 /* Interrupt handlers need special epilogue code and therefore can't
6251 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6254 /* We can't do a sibcall if the called function is a MIPS16 function
6255 because there is no direct "jx" instruction equivalent to "jalx" to
6256 switch the ISA mode. We only care about cases where the sibling
6257 and normal calls would both be direct. */
6259 && mips_use_mips16_mode_p (decl)
6260 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6263 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6264 functions could be MIPS16 ones unless an attribute explicitly tells
6266 if (TARGET_INTERLINK_MIPS16
6268 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6269 && !mips_nomips16_decl_p (decl)
6270 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6277 /* Emit code to move general operand SRC into condition-code
6278 register DEST given that SCRATCH is a scratch TFmode FPR.
6285 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6288 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6292 /* Change the source to SFmode. */
6294 src = adjust_address (src, SFmode, 0);
6295 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6296 src = gen_rtx_REG (SFmode, true_regnum (src));
6298 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6299 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6301 mips_emit_move (copy_rtx (fp1), src);
6302 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6303 emit_insn (gen_slt_sf (dest, fp2, fp1));
6306 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6307 Assume that the areas do not overlap. */
6310 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6312 HOST_WIDE_INT offset, delta;
6313 unsigned HOST_WIDE_INT bits;
6315 enum machine_mode mode;
6318 /* Work out how many bits to move at a time. If both operands have
6319 half-word alignment, it is usually better to move in half words.
6320 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6321 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6322 Otherwise move word-sized chunks. */
6323 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6324 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6325 bits = BITS_PER_WORD / 2;
6327 bits = BITS_PER_WORD;
6329 mode = mode_for_size (bits, MODE_INT, 0);
6330 delta = bits / BITS_PER_UNIT;
6332 /* Allocate a buffer for the temporary registers. */
6333 regs = XALLOCAVEC (rtx, length / delta);
6335 /* Load as many BITS-sized chunks as possible. Use a normal load if
6336 the source has enough alignment, otherwise use left/right pairs. */
6337 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6339 regs[i] = gen_reg_rtx (mode);
6340 if (MEM_ALIGN (src) >= bits)
6341 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6344 rtx part = adjust_address (src, BLKmode, offset);
6345 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6350 /* Copy the chunks to the destination. */
6351 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6352 if (MEM_ALIGN (dest) >= bits)
6353 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6356 rtx part = adjust_address (dest, BLKmode, offset);
6357 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6361 /* Mop up any left-over bytes. */
6362 if (offset < length)
6364 src = adjust_address (src, BLKmode, offset);
6365 dest = adjust_address (dest, BLKmode, offset);
6366 move_by_pieces (dest, src, length - offset,
6367 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6371 /* Helper function for doing a loop-based block operation on memory
6372 reference MEM. Each iteration of the loop will operate on LENGTH
6375 Create a new base register for use within the loop and point it to
6376 the start of MEM. Create a new memory reference that uses this
6377 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6380 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6381 rtx *loop_reg, rtx *loop_mem)
6383 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6385 /* Although the new mem does not refer to a known location,
6386 it does keep up to LENGTH bytes of alignment. */
6387 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6388 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6391 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6392 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6393 the memory regions do not overlap. */
6396 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6397 HOST_WIDE_INT bytes_per_iter)
6399 rtx label, src_reg, dest_reg, final_src;
6400 HOST_WIDE_INT leftover;
6402 leftover = length % bytes_per_iter;
6405 /* Create registers and memory references for use within the loop. */
6406 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6407 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6409 /* Calculate the value that SRC_REG should have after the last iteration
6411 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6414 /* Emit the start of the loop. */
6415 label = gen_label_rtx ();
6418 /* Emit the loop body. */
6419 mips_block_move_straight (dest, src, bytes_per_iter);
6421 /* Move on to the next block. */
6422 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6423 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6425 /* Emit the loop condition. */
6426 if (Pmode == DImode)
6427 emit_insn (gen_cmpdi (src_reg, final_src));
6429 emit_insn (gen_cmpsi (src_reg, final_src));
6430 emit_jump_insn (gen_bne (label));
6432 /* Mop up any left-over bytes. */
6434 mips_block_move_straight (dest, src, leftover);
6437 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6438 memory reference SRC to memory reference DEST. */
6441 mips_expand_block_move (rtx dest, rtx src, rtx length)
6443 if (GET_CODE (length) == CONST_INT)
6445 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6447 mips_block_move_straight (dest, src, INTVAL (length));
6452 mips_block_move_loop (dest, src, INTVAL (length),
6453 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6460 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6463 mips_expand_synci_loop (rtx begin, rtx end)
6465 rtx inc, label, cmp, cmp_result;
6467 /* Load INC with the cache line size (rdhwr INC,$1). */
6468 inc = gen_reg_rtx (Pmode);
6469 emit_insn (Pmode == SImode
6470 ? gen_rdhwr_synci_step_si (inc)
6471 : gen_rdhwr_synci_step_di (inc));
6473 /* Loop back to here. */
6474 label = gen_label_rtx ();
6477 emit_insn (gen_synci (begin));
6479 cmp = mips_force_binary (Pmode, GTU, begin, end);
6481 mips_emit_binary (PLUS, begin, begin, inc);
6483 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6484 emit_jump_insn (gen_condjump (cmp_result, label));
6487 /* Expand a QI or HI mode atomic memory operation.
6489 GENERATOR contains a pointer to the gen_* function that generates
6490 the SI mode underlying atomic operation using masks that we
6493 RESULT is the return register for the operation. Its value is NULL
6496 MEM is the location of the atomic access.
6498 OLDVAL is the first operand for the operation.
6500 NEWVAL is the optional second operand for the operation. Its value
6501 is NULL if unused. */
6504 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6505 rtx result, rtx mem, rtx oldval, rtx newval)
6507 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6508 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6510 enum machine_mode mode;
6512 mode = GET_MODE (mem);
6514 /* Compute the address of the containing SImode value. */
6515 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6516 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6517 force_reg (Pmode, GEN_INT (-4)));
6519 /* Create a memory reference for it. */
6520 memsi = gen_rtx_MEM (SImode, memsi_addr);
6521 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6522 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6524 /* Work out the byte offset of the QImode or HImode value,
6525 counting from the least significant byte. */
6526 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6527 if (TARGET_BIG_ENDIAN)
6528 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6530 /* Multiply by eight to convert the shift value from bytes to bits. */
6531 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6533 /* Make the final shift an SImode value, so that it can be used in
6534 SImode operations. */
6535 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6537 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6538 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6539 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6540 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6542 /* Compute the equivalent exclusive mask. */
6543 inverted_mask = gen_reg_rtx (SImode);
6544 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6545 gen_rtx_NOT (SImode, mask)));
6547 /* Shift the old value into place. */
6548 if (oldval != const0_rtx)
6550 oldval = convert_modes (SImode, mode, oldval, true);
6551 oldval = force_reg (SImode, oldval);
6552 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6555 /* Do the same for the new value. */
6556 if (newval && newval != const0_rtx)
6558 newval = convert_modes (SImode, mode, newval, true);
6559 newval = force_reg (SImode, newval);
6560 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6563 /* Do the SImode atomic access. */
6565 res = gen_reg_rtx (SImode);
6567 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6569 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6571 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6577 /* Shift and convert the result. */
6578 mips_emit_binary (AND, res, res, mask);
6579 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6580 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6584 /* Return true if it is possible to use left/right accesses for a
6585 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6586 returning true, update *OP, *LEFT and *RIGHT as follows:
6588 *OP is a BLKmode reference to the whole field.
6590 *LEFT is a QImode reference to the first byte if big endian or
6591 the last byte if little endian. This address can be used in the
6592 left-side instructions (LWL, SWL, LDL, SDL).
6594 *RIGHT is a QImode reference to the opposite end of the field and
6595 can be used in the patterning right-side instruction. */
6598 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6599 rtx *left, rtx *right)
6603 /* Check that the operand really is a MEM. Not all the extv and
6604 extzv predicates are checked. */
6608 /* Check that the size is valid. */
6609 if (width != 32 && (!TARGET_64BIT || width != 64))
6612 /* We can only access byte-aligned values. Since we are always passed
6613 a reference to the first byte of the field, it is not necessary to
6614 do anything with BITPOS after this check. */
6615 if (bitpos % BITS_PER_UNIT != 0)
6618 /* Reject aligned bitfields: we want to use a normal load or store
6619 instead of a left/right pair. */
6620 if (MEM_ALIGN (*op) >= width)
6623 /* Adjust *OP to refer to the whole field. This also has the effect
6624 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6625 *op = adjust_address (*op, BLKmode, 0);
6626 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6628 /* Get references to both ends of the field. We deliberately don't
6629 use the original QImode *OP for FIRST since the new BLKmode one
6630 might have a simpler address. */
6631 first = adjust_address (*op, QImode, 0);
6632 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6634 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6635 correspond to the MSB and RIGHT to the LSB. */
6636 if (TARGET_BIG_ENDIAN)
6637 *left = first, *right = last;
6639 *left = last, *right = first;
6644 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6645 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6646 the operation is the equivalent of:
6648 (set DEST (*_extract SRC WIDTH BITPOS))
6650 Return true on success. */
6653 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6654 HOST_WIDE_INT bitpos)
6656 rtx left, right, temp;
6658 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6659 be a paradoxical word_mode subreg. This is the only case in which
6660 we allow the destination to be larger than the source. */
6661 if (GET_CODE (dest) == SUBREG
6662 && GET_MODE (dest) == DImode
6663 && GET_MODE (SUBREG_REG (dest)) == SImode)
6664 dest = SUBREG_REG (dest);
6666 /* After the above adjustment, the destination must be the same
6667 width as the source. */
6668 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6671 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6674 temp = gen_reg_rtx (GET_MODE (dest));
6675 if (GET_MODE (dest) == DImode)
6677 emit_insn (gen_mov_ldl (temp, src, left));
6678 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6682 emit_insn (gen_mov_lwl (temp, src, left));
6683 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6688 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6689 BITPOS and SRC are the operands passed to the expander; the operation
6690 is the equivalent of:
6692 (set (zero_extract DEST WIDTH BITPOS) SRC)
6694 Return true on success. */
6697 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6698 HOST_WIDE_INT bitpos)
6701 enum machine_mode mode;
6703 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6706 mode = mode_for_size (width, MODE_INT, 0);
6707 src = gen_lowpart (mode, src);
6710 emit_insn (gen_mov_sdl (dest, src, left));
6711 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6715 emit_insn (gen_mov_swl (dest, src, left));
6716 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6721 /* Return true if X is a MEM with the same size as MODE. */
6724 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6731 size = MEM_SIZE (x);
6732 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6735 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6736 source of an "ext" instruction or the destination of an "ins"
6737 instruction. OP must be a register operand and the following
6738 conditions must hold:
6740 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6741 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6742 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6744 Also reject lengths equal to a word as they are better handled
6745 by the move patterns. */
6748 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6750 if (!ISA_HAS_EXT_INS
6751 || !register_operand (op, VOIDmode)
6752 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6755 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6758 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6764 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6765 operation if MAXLEN is the maxium length of consecutive bits that
6766 can make up MASK. MODE is the mode of the operation. See
6767 mask_low_and_shift_len for the actual definition. */
6770 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
6772 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
6775 /* The canonical form of a mask-low-and-shift-left operation is
6776 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
6777 cleared. Thus we need to shift MASK to the right before checking if it
6778 is a valid mask value. MODE is the mode of the operation. If true
6779 return the length of the mask, otherwise return -1. */
6782 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
6784 HOST_WIDE_INT shval;
6786 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
6787 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
6790 /* Return true if -msplit-addresses is selected and should be honored.
6792 -msplit-addresses is a half-way house between explicit relocations
6793 and the traditional assembler macros. It can split absolute 32-bit
6794 symbolic constants into a high/lo_sum pair but uses macros for other
6797 Like explicit relocation support for REL targets, it relies
6798 on GNU extensions in the assembler and the linker.
6800 Although this code should work for -O0, it has traditionally
6801 been treated as an optimization. */
6804 mips_split_addresses_p (void)
6806 return (TARGET_SPLIT_ADDRESSES
6810 && !ABI_HAS_64BIT_SYMBOLS);
6813 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6816 mips_init_relocs (void)
6818 memset (mips_split_p, '\0', sizeof (mips_split_p));
6819 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
6820 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6821 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6823 if (ABI_HAS_64BIT_SYMBOLS)
6825 if (TARGET_EXPLICIT_RELOCS)
6827 mips_split_p[SYMBOL_64_HIGH] = true;
6828 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6829 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6831 mips_split_p[SYMBOL_64_MID] = true;
6832 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6833 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6835 mips_split_p[SYMBOL_64_LOW] = true;
6836 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6837 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6839 mips_split_p[SYMBOL_ABSOLUTE] = true;
6840 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6845 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6847 mips_split_p[SYMBOL_ABSOLUTE] = true;
6848 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6849 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6851 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6857 /* The high part is provided by a pseudo copy of $gp. */
6858 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6859 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6861 else if (TARGET_EXPLICIT_RELOCS)
6862 /* Small data constants are kept whole until after reload,
6863 then lowered by mips_rewrite_small_data. */
6864 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6866 if (TARGET_EXPLICIT_RELOCS)
6868 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6871 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6872 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6876 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6877 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6880 /* Expose the use of $28 as soon as possible. */
6881 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
6885 /* The HIGH and LO_SUM are matched by special .md patterns. */
6886 mips_split_p[SYMBOL_GOT_DISP] = true;
6888 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6889 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6890 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6892 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6893 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6894 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6899 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6901 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6902 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6904 /* Expose the use of $28 as soon as possible. */
6905 mips_split_p[SYMBOL_GOT_DISP] = true;
6911 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6912 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6913 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6916 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6917 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6919 mips_split_p[SYMBOL_DTPREL] = true;
6920 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6921 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6923 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6925 mips_split_p[SYMBOL_TPREL] = true;
6926 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6927 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6929 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6932 /* If OP is an UNSPEC address, return the address to which it refers,
6933 otherwise return OP itself. */
6936 mips_strip_unspec_address (rtx op)
6940 split_const (op, &base, &offset);
6941 if (UNSPEC_ADDRESS_P (base))
6942 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6946 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6947 in context CONTEXT. RELOCS is the array of relocations to use. */
6950 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6951 const char **relocs)
6953 enum mips_symbol_type symbol_type;
6956 symbol_type = mips_classify_symbolic_expression (op, context);
6957 gcc_assert (relocs[symbol_type]);
6959 fputs (relocs[symbol_type], file);
6960 output_addr_const (file, mips_strip_unspec_address (op));
6961 for (p = relocs[symbol_type]; *p != 0; p++)
6966 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6967 The punctuation characters are:
6969 '(' Start a nested ".set noreorder" block.
6970 ')' End a nested ".set noreorder" block.
6971 '[' Start a nested ".set noat" block.
6972 ']' End a nested ".set noat" block.
6973 '<' Start a nested ".set nomacro" block.
6974 '>' End a nested ".set nomacro" block.
6975 '*' Behave like %(%< if generating a delayed-branch sequence.
6976 '#' Print a nop if in a ".set noreorder" block.
6977 '/' Like '#', but do nothing within a delayed-branch sequence.
6978 '?' Print "l" if mips_branch_likely is true
6979 '~' Print a nop if mips_branch_likely is true
6980 '.' Print the name of the register with a hard-wired zero (zero or $0).
6981 '@' Print the name of the assembler temporary register (at or $1).
6982 '^' Print the name of the pic call-through register (t9 or $25).
6983 '+' Print the name of the gp register (usually gp or $28).
6984 '$' Print the name of the stack pointer register (sp or $29).
6985 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6986 '-' Print ".set pop" under the same conditions for '|'.
6988 See also mips_init_print_operand_pucnt. */
6991 mips_print_operand_punctuation (FILE *file, int ch)
6996 if (set_noreorder++ == 0)
6997 fputs (".set\tnoreorder\n\t", file);
7001 gcc_assert (set_noreorder > 0);
7002 if (--set_noreorder == 0)
7003 fputs ("\n\t.set\treorder", file);
7007 if (set_noat++ == 0)
7008 fputs (".set\tnoat\n\t", file);
7012 gcc_assert (set_noat > 0);
7013 if (--set_noat == 0)
7014 fputs ("\n\t.set\tat", file);
7018 if (set_nomacro++ == 0)
7019 fputs (".set\tnomacro\n\t", file);
7023 gcc_assert (set_nomacro > 0);
7024 if (--set_nomacro == 0)
7025 fputs ("\n\t.set\tmacro", file);
7029 if (final_sequence != 0)
7031 mips_print_operand_punctuation (file, '(');
7032 mips_print_operand_punctuation (file, '<');
7037 if (set_noreorder != 0)
7038 fputs ("\n\tnop", file);
7042 /* Print an extra newline so that the delayed insn is separated
7043 from the following ones. This looks neater and is consistent
7044 with non-nop delayed sequences. */
7045 if (set_noreorder != 0 && final_sequence == 0)
7046 fputs ("\n\tnop\n", file);
7050 if (mips_branch_likely)
7055 if (mips_branch_likely)
7056 fputs ("\n\tnop", file);
7060 fputs (reg_names[GP_REG_FIRST + 0], file);
7064 fputs (reg_names[GP_REG_FIRST + 1], file);
7068 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7072 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7076 fputs (reg_names[STACK_POINTER_REGNUM], file);
7081 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
7086 fputs ("\n\t.set\tpop", file);
7095 /* Initialize mips_print_operand_punct. */
7098 mips_init_print_operand_punct (void)
7102 for (p = "()[]<>*#/?~.@^+$|-"; *p; p++)
7103 mips_print_operand_punct[(unsigned char) *p] = true;
7106 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7107 associated with condition CODE. Print the condition part of the
7111 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7125 /* Conveniently, the MIPS names for these conditions are the same
7126 as their RTL equivalents. */
7127 fputs (GET_RTX_NAME (code), file);
7131 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7136 /* Likewise floating-point branches. */
7139 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7144 fputs ("c1f", file);
7148 fputs ("c1t", file);
7152 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7157 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7159 'X' Print CONST_INT OP in hexadecimal format.
7160 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7161 'd' Print CONST_INT OP in decimal.
7162 'm' Print one less than CONST_INT OP in decimal.
7163 'h' Print the high-part relocation associated with OP, after stripping
7165 'R' Print the low-part relocation associated with OP.
7166 'C' Print the integer branch condition for comparison OP.
7167 'N' Print the inverse of the integer branch condition for comparison OP.
7168 'F' Print the FPU branch condition for comparison OP.
7169 'W' Print the inverse of the FPU branch condition for comparison OP.
7170 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7171 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7172 't' Like 'T', but with the EQ/NE cases reversed
7173 'Y' Print mips_fp_conditions[INTVAL (OP)]
7174 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7175 'q' Print a DSP accumulator register.
7176 'D' Print the second part of a double-word register or memory operand.
7177 'L' Print the low-order register in a double-word register operand.
7178 'M' Print high-order register in a double-word register operand.
7179 'z' Print $0 if OP is zero, otherwise print OP normally. */
7182 mips_print_operand (FILE *file, rtx op, int letter)
7186 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7188 mips_print_operand_punctuation (file, letter);
7193 code = GET_CODE (op);
7198 if (GET_CODE (op) == CONST_INT)
7199 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7201 output_operand_lossage ("invalid use of '%%%c'", letter);
7205 if (GET_CODE (op) == CONST_INT)
7206 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7208 output_operand_lossage ("invalid use of '%%%c'", letter);
7212 if (GET_CODE (op) == CONST_INT)
7213 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7215 output_operand_lossage ("invalid use of '%%%c'", letter);
7219 if (GET_CODE (op) == CONST_INT)
7220 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7222 output_operand_lossage ("invalid use of '%%%c'", letter);
7228 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7232 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7236 mips_print_int_branch_condition (file, code, letter);
7240 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7244 mips_print_float_branch_condition (file, code, letter);
7248 mips_print_float_branch_condition (file, reverse_condition (code),
7255 int truth = (code == NE) == (letter == 'T');
7256 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7261 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7262 fputs (mips_fp_conditions[UINTVAL (op)], file);
7264 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7271 mips_print_operand (file, op, 0);
7277 if (code == REG && MD_REG_P (REGNO (op)))
7278 fprintf (file, "$ac0");
7279 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7280 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7282 output_operand_lossage ("invalid use of '%%%c'", letter);
7290 unsigned int regno = REGNO (op);
7291 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7292 || (letter == 'L' && TARGET_BIG_ENDIAN)
7295 /* We need to print $0 .. $31 for COP0 registers. */
7296 if (COP0_REG_P (regno))
7297 fprintf (file, "$%s", ®_names[regno][4]);
7299 fprintf (file, "%s", reg_names[regno]);
7305 output_address (plus_constant (XEXP (op, 0), 4));
7307 output_address (XEXP (op, 0));
7311 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7312 fputs (reg_names[GP_REG_FIRST], file);
7313 else if (CONST_GP_P (op))
7314 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7316 output_addr_const (file, mips_strip_unspec_address (op));
7322 /* Output address operand X to FILE. */
7325 mips_print_operand_address (FILE *file, rtx x)
7327 struct mips_address_info addr;
7329 if (mips_classify_address (&addr, x, word_mode, true))
7333 mips_print_operand (file, addr.offset, 0);
7334 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7337 case ADDRESS_LO_SUM:
7338 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7340 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7343 case ADDRESS_CONST_INT:
7344 output_addr_const (file, x);
7345 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7348 case ADDRESS_SYMBOLIC:
7349 output_addr_const (file, mips_strip_unspec_address (x));
7355 /* Implement TARGET_ENCODE_SECTION_INFO. */
7358 mips_encode_section_info (tree decl, rtx rtl, int first)
7360 default_encode_section_info (decl, rtl, first);
7362 if (TREE_CODE (decl) == FUNCTION_DECL)
7364 rtx symbol = XEXP (rtl, 0);
7365 tree type = TREE_TYPE (decl);
7367 /* Encode whether the symbol is short or long. */
7368 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7369 || mips_far_type_p (type))
7370 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7374 /* Implement TARGET_SELECT_RTX_SECTION. */
7377 mips_select_rtx_section (enum machine_mode mode, rtx x,
7378 unsigned HOST_WIDE_INT align)
7380 /* ??? Consider using mergeable small data sections. */
7381 if (mips_rtx_constant_in_small_data_p (mode))
7382 return get_named_section (NULL, ".sdata", 0);
7384 return default_elf_select_rtx_section (mode, x, align);
7387 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7389 The complication here is that, with the combination TARGET_ABICALLS
7390 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7391 absolute addresses, and should therefore not be included in the
7392 read-only part of a DSO. Handle such cases by selecting a normal
7393 data section instead of a read-only one. The logic apes that in
7394 default_function_rodata_section. */
7397 mips_function_rodata_section (tree decl)
7399 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7400 return default_function_rodata_section (decl);
7402 if (decl && DECL_SECTION_NAME (decl))
7404 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7405 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7407 char *rname = ASTRDUP (name);
7409 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7411 else if (flag_function_sections
7412 && flag_data_sections
7413 && strncmp (name, ".text.", 6) == 0)
7415 char *rname = ASTRDUP (name);
7416 memcpy (rname + 1, "data", 4);
7417 return get_section (rname, SECTION_WRITE, decl);
7420 return data_section;
7423 /* Implement TARGET_IN_SMALL_DATA_P. */
7426 mips_in_small_data_p (const_tree decl)
7428 unsigned HOST_WIDE_INT size;
7430 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7433 /* We don't yet generate small-data references for -mabicalls
7434 or VxWorks RTP code. See the related -G handling in
7435 mips_override_options. */
7436 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7439 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7443 /* Reject anything that isn't in a known small-data section. */
7444 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7445 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7448 /* If a symbol is defined externally, the assembler will use the
7449 usual -G rules when deciding how to implement macros. */
7450 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7453 else if (TARGET_EMBEDDED_DATA)
7455 /* Don't put constants into the small data section: we want them
7456 to be in ROM rather than RAM. */
7457 if (TREE_CODE (decl) != VAR_DECL)
7460 if (TREE_READONLY (decl)
7461 && !TREE_SIDE_EFFECTS (decl)
7462 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7466 /* Enforce -mlocal-sdata. */
7467 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7470 /* Enforce -mextern-sdata. */
7471 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7473 if (DECL_EXTERNAL (decl))
7475 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7479 /* We have traditionally not treated zero-sized objects as small data,
7480 so this is now effectively part of the ABI. */
7481 size = int_size_in_bytes (TREE_TYPE (decl));
7482 return size > 0 && size <= mips_small_data_threshold;
7485 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7486 anchors for small data: the GP register acts as an anchor in that
7487 case. We also don't want to use them for PC-relative accesses,
7488 where the PC acts as an anchor. */
7491 mips_use_anchors_for_symbol_p (const_rtx symbol)
7493 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7495 case SYMBOL_PC_RELATIVE:
7496 case SYMBOL_GP_RELATIVE:
7500 return default_use_anchors_for_symbol_p (symbol);
7504 /* The MIPS debug format wants all automatic variables and arguments
7505 to be in terms of the virtual frame pointer (stack pointer before
7506 any adjustment in the function), while the MIPS 3.0 linker wants
7507 the frame pointer to be the stack pointer after the initial
7508 adjustment. So, we do the adjustment here. The arg pointer (which
7509 is eliminated) points to the virtual frame pointer, while the frame
7510 pointer (which may be eliminated) points to the stack pointer after
7511 the initial adjustments. */
7514 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7516 rtx offset2 = const0_rtx;
7517 rtx reg = eliminate_constant_term (addr, &offset2);
7520 offset = INTVAL (offset2);
7522 if (reg == stack_pointer_rtx
7523 || reg == frame_pointer_rtx
7524 || reg == hard_frame_pointer_rtx)
7526 offset -= cfun->machine->frame.total_size;
7527 if (reg == hard_frame_pointer_rtx)
7528 offset += cfun->machine->frame.hard_frame_pointer_offset;
7531 /* sdbout_parms does not want this to crash for unrecognized cases. */
7533 else if (reg != arg_pointer_rtx)
7534 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7541 /* Implement ASM_OUTPUT_EXTERNAL. */
7544 mips_output_external (FILE *file, tree decl, const char *name)
7546 default_elf_asm_output_external (file, decl, name);
7548 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7549 set in order to avoid putting out names that are never really
7551 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7553 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7555 /* When using assembler macros, emit .extern directives for
7556 all small-data externs so that the assembler knows how
7559 In most cases it would be safe (though pointless) to emit
7560 .externs for other symbols too. One exception is when an
7561 object is within the -G limit but declared by the user to
7562 be in a section other than .sbss or .sdata. */
7563 fputs ("\t.extern\t", file);
7564 assemble_name (file, name);
7565 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7566 int_size_in_bytes (TREE_TYPE (decl)));
7568 else if (TARGET_IRIX
7569 && mips_abi == ABI_32
7570 && TREE_CODE (decl) == FUNCTION_DECL)
7572 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7573 `.global name .text' directive for every used but
7574 undefined function. If we don't, the linker may perform
7575 an optimization (skipping over the insns that set $gp)
7576 when it is unsafe. */
7577 fputs ("\t.globl ", file);
7578 assemble_name (file, name);
7579 fputs (" .text\n", file);
7584 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7587 mips_output_filename (FILE *stream, const char *name)
7589 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7591 if (write_symbols == DWARF2_DEBUG)
7593 else if (mips_output_filename_first_time)
7595 mips_output_filename_first_time = 0;
7596 num_source_filenames += 1;
7597 current_function_file = name;
7598 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7599 output_quoted_string (stream, name);
7600 putc ('\n', stream);
7602 /* If we are emitting stabs, let dbxout.c handle this (except for
7603 the mips_output_filename_first_time case). */
7604 else if (write_symbols == DBX_DEBUG)
7606 else if (name != current_function_file
7607 && strcmp (name, current_function_file) != 0)
7609 num_source_filenames += 1;
7610 current_function_file = name;
7611 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7612 output_quoted_string (stream, name);
7613 putc ('\n', stream);
7617 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7619 static void ATTRIBUTE_UNUSED
7620 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7625 fputs ("\t.dtprelword\t", file);
7629 fputs ("\t.dtpreldword\t", file);
7635 output_addr_const (file, x);
7636 fputs ("+0x8000", file);
7639 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7642 mips_dwarf_register_span (rtx reg)
7645 enum machine_mode mode;
7647 /* By default, GCC maps increasing register numbers to increasing
7648 memory locations, but paired FPRs are always little-endian,
7649 regardless of the prevailing endianness. */
7650 mode = GET_MODE (reg);
7651 if (FP_REG_P (REGNO (reg))
7652 && TARGET_BIG_ENDIAN
7653 && MAX_FPRS_PER_FMT > 1
7654 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7656 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7657 high = mips_subword (reg, true);
7658 low = mips_subword (reg, false);
7659 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7665 /* Implement ASM_OUTPUT_ASCII. */
7668 mips_output_ascii (FILE *stream, const char *string, size_t len)
7674 fprintf (stream, "\t.ascii\t\"");
7675 for (i = 0; i < len; i++)
7679 c = (unsigned char) string[i];
7682 if (c == '\\' || c == '\"')
7684 putc ('\\', stream);
7692 fprintf (stream, "\\%03o", c);
7696 if (cur_pos > 72 && i+1 < len)
7699 fprintf (stream, "\"\n\t.ascii\t\"");
7702 fprintf (stream, "\"\n");
7705 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7706 macros, mark the symbol as written so that mips_asm_output_external
7707 won't emit an .extern for it. STREAM is the output file, NAME is the
7708 name of the symbol, INIT_STRING is the string that should be written
7709 before the symbol and FINAL_STRING is the string that should be
7710 written after it. FINAL_STRING is a printf format that consumes the
7711 remaining arguments. */
7714 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7715 const char *final_string, ...)
7719 fputs (init_string, stream);
7720 assemble_name (stream, name);
7721 va_start (ap, final_string);
7722 vfprintf (stream, final_string, ap);
7725 if (!TARGET_EXPLICIT_RELOCS)
7727 tree name_tree = get_identifier (name);
7728 TREE_ASM_WRITTEN (name_tree) = 1;
7732 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7733 NAME is the name of the object and ALIGN is the required alignment
7734 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7735 alignment argument. */
7738 mips_declare_common_object (FILE *stream, const char *name,
7739 const char *init_string,
7740 unsigned HOST_WIDE_INT size,
7741 unsigned int align, bool takes_alignment_p)
7743 if (!takes_alignment_p)
7745 size += (align / BITS_PER_UNIT) - 1;
7746 size -= size % (align / BITS_PER_UNIT);
7747 mips_declare_object (stream, name, init_string,
7748 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7751 mips_declare_object (stream, name, init_string,
7752 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7753 size, align / BITS_PER_UNIT);
7756 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7757 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7760 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7761 unsigned HOST_WIDE_INT size,
7764 /* If the target wants uninitialized const declarations in
7765 .rdata then don't put them in .comm. */
7766 if (TARGET_EMBEDDED_DATA
7767 && TARGET_UNINIT_CONST_IN_RODATA
7768 && TREE_CODE (decl) == VAR_DECL
7769 && TREE_READONLY (decl)
7770 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7772 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7773 targetm.asm_out.globalize_label (stream, name);
7775 switch_to_section (readonly_data_section);
7776 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7777 mips_declare_object (stream, name, "",
7778 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7782 mips_declare_common_object (stream, name, "\n\t.comm\t",
7786 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7787 extern int size_directive_output;
7789 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7790 definitions except that it uses mips_declare_object to emit the label. */
7793 mips_declare_object_name (FILE *stream, const char *name,
7794 tree decl ATTRIBUTE_UNUSED)
7796 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7797 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7800 size_directive_output = 0;
7801 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7805 size_directive_output = 1;
7806 size = int_size_in_bytes (TREE_TYPE (decl));
7807 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7810 mips_declare_object (stream, name, "", ":\n");
7813 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7816 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7820 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7821 if (!flag_inhibit_size_directive
7822 && DECL_SIZE (decl) != 0
7825 && DECL_INITIAL (decl) == error_mark_node
7826 && !size_directive_output)
7830 size_directive_output = 1;
7831 size = int_size_in_bytes (TREE_TYPE (decl));
7832 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7837 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7838 with the current ABI. */
7841 mips_mdebug_abi_name (void)
7854 return TARGET_64BIT ? "eabi64" : "eabi32";
7860 /* Implement TARGET_ASM_FILE_START. */
7863 mips_file_start (void)
7865 default_file_start ();
7867 /* Generate a special section to describe the ABI switches used to
7868 produce the resultant binary. This is unnecessary on IRIX and
7869 causes unwanted warnings from the native linker. */
7872 /* Record the ABI itself. Modern versions of binutils encode
7873 this information in the ELF header flags, but GDB needs the
7874 information in order to correctly debug binaries produced by
7875 older binutils. See the function mips_gdbarch_init in
7877 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7878 mips_mdebug_abi_name ());
7880 /* There is no ELF header flag to distinguish long32 forms of the
7881 EABI from long64 forms. Emit a special section to help tools
7882 such as GDB. Do the same for o64, which is sometimes used with
7884 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7885 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7886 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7888 #ifdef HAVE_AS_GNU_ATTRIBUTE
7889 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7890 (TARGET_HARD_FLOAT_ABI
7891 ? (TARGET_DOUBLE_FLOAT
7892 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
7896 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7897 if (TARGET_ABICALLS)
7899 fprintf (asm_out_file, "\t.abicalls\n");
7900 if (TARGET_ABICALLS_PIC0)
7901 fprintf (asm_out_file, "\t.option\tpic0\n");
7904 if (flag_verbose_asm)
7905 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7907 mips_small_data_threshold, mips_arch_info->name, mips_isa);
7910 /* Make the last instruction frame-related and note that it performs
7911 the operation described by FRAME_PATTERN. */
7914 mips_set_frame_expr (rtx frame_pattern)
7918 insn = get_last_insn ();
7919 RTX_FRAME_RELATED_P (insn) = 1;
7920 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7925 /* Return a frame-related rtx that stores REG at MEM.
7926 REG must be a single register. */
7929 mips_frame_set (rtx mem, rtx reg)
7933 /* If we're saving the return address register and the DWARF return
7934 address column differs from the hard register number, adjust the
7935 note reg to refer to the former. */
7936 if (REGNO (reg) == GP_REG_FIRST + 31
7937 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7938 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7940 set = gen_rtx_SET (VOIDmode, mem, reg);
7941 RTX_FRAME_RELATED_P (set) = 1;
7946 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7947 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7948 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7949 static const unsigned char mips16e_s2_s8_regs[] = {
7950 30, 23, 22, 21, 20, 19, 18
7952 static const unsigned char mips16e_a0_a3_regs[] = {
7956 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7957 ordered from the uppermost in memory to the lowest in memory. */
7958 static const unsigned char mips16e_save_restore_regs[] = {
7959 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7962 /* Return the index of the lowest X in the range [0, SIZE) for which
7963 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7966 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7971 for (i = 0; i < size; i++)
7972 if (BITSET_P (mask, regs[i]))
7978 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7979 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7980 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7981 is true for all indexes (X, SIZE). */
7984 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7985 unsigned int size, unsigned int *num_regs_ptr)
7989 i = mips16e_find_first_register (*mask_ptr, regs, size);
7990 for (i++; i < size; i++)
7991 if (!BITSET_P (*mask_ptr, regs[i]))
7994 *mask_ptr |= 1 << regs[i];
7998 /* Return a simplified form of X using the register values in REG_VALUES.
7999 REG_VALUES[R] is the last value assigned to hard register R, or null
8000 if R has not been modified.
8002 This function is rather limited, but is good enough for our purposes. */
8005 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8007 x = avoid_constant_pool_reference (x);
8011 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8012 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8013 x0, GET_MODE (XEXP (x, 0)));
8016 if (ARITHMETIC_P (x))
8018 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8019 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8020 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8024 && reg_values[REGNO (x)]
8025 && !rtx_unstable_p (reg_values[REGNO (x)]))
8026 return reg_values[REGNO (x)];
8031 /* Return true if (set DEST SRC) stores an argument register into its
8032 caller-allocated save slot, storing the number of that argument
8033 register in *REGNO_PTR if so. REG_VALUES is as for
8034 mips16e_collect_propagate_value. */
8037 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8038 unsigned int *regno_ptr)
8040 unsigned int argno, regno;
8041 HOST_WIDE_INT offset, required_offset;
8044 /* Check that this is a word-mode store. */
8045 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8048 /* Check that the register being saved is an unmodified argument
8050 regno = REGNO (src);
8051 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8053 argno = regno - GP_ARG_FIRST;
8055 /* Check whether the address is an appropriate stack-pointer or
8056 frame-pointer access. */
8057 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8058 mips_split_plus (addr, &base, &offset);
8059 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8060 if (base == hard_frame_pointer_rtx)
8061 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8062 else if (base != stack_pointer_rtx)
8064 if (offset != required_offset)
8071 /* A subroutine of mips_expand_prologue, called only when generating
8072 MIPS16e SAVE instructions. Search the start of the function for any
8073 instructions that save argument registers into their caller-allocated
8074 save slots. Delete such instructions and return a value N such that
8075 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8076 instructions redundant. */
8079 mips16e_collect_argument_saves (void)
8081 rtx reg_values[FIRST_PSEUDO_REGISTER];
8082 rtx insn, next, set, dest, src;
8083 unsigned int nargs, regno;
8085 push_topmost_sequence ();
8087 memset (reg_values, 0, sizeof (reg_values));
8088 for (insn = get_insns (); insn; insn = next)
8090 next = NEXT_INSN (insn);
8097 set = PATTERN (insn);
8098 if (GET_CODE (set) != SET)
8101 dest = SET_DEST (set);
8102 src = SET_SRC (set);
8103 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8105 if (!BITSET_P (cfun->machine->frame.mask, regno))
8108 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8111 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8112 reg_values[REGNO (dest)]
8113 = mips16e_collect_propagate_value (src, reg_values);
8117 pop_topmost_sequence ();
8122 /* Return a move between register REGNO and memory location SP + OFFSET.
8123 Make the move a load if RESTORE_P, otherwise make it a frame-related
8127 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8132 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8133 reg = gen_rtx_REG (SImode, regno);
8135 ? gen_rtx_SET (VOIDmode, reg, mem)
8136 : mips_frame_set (mem, reg));
8139 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8140 The instruction must:
8142 - Allocate or deallocate SIZE bytes in total; SIZE is known
8145 - Save or restore as many registers in *MASK_PTR as possible.
8146 The instruction saves the first registers at the top of the
8147 allocated area, with the other registers below it.
8149 - Save NARGS argument registers above the allocated area.
8151 (NARGS is always zero if RESTORE_P.)
8153 The SAVE and RESTORE instructions cannot save and restore all general
8154 registers, so there may be some registers left over for the caller to
8155 handle. Destructively modify *MASK_PTR so that it contains the registers
8156 that still need to be saved or restored. The caller can save these
8157 registers in the memory immediately below *OFFSET_PTR, which is a
8158 byte offset from the bottom of the allocated stack area. */
8161 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8162 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8166 HOST_WIDE_INT offset, top_offset;
8167 unsigned int i, regno;
8170 gcc_assert (cfun->machine->frame.num_fp == 0);
8172 /* Calculate the number of elements in the PARALLEL. We need one element
8173 for the stack adjustment, one for each argument register save, and one
8174 for each additional register move. */
8176 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8177 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8180 /* Create the final PARALLEL. */
8181 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8184 /* Add the stack pointer adjustment. */
8185 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8186 plus_constant (stack_pointer_rtx,
8187 restore_p ? size : -size));
8188 RTX_FRAME_RELATED_P (set) = 1;
8189 XVECEXP (pattern, 0, n++) = set;
8191 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8192 top_offset = restore_p ? size : 0;
8194 /* Save the arguments. */
8195 for (i = 0; i < nargs; i++)
8197 offset = top_offset + i * UNITS_PER_WORD;
8198 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8199 XVECEXP (pattern, 0, n++) = set;
8202 /* Then fill in the other register moves. */
8203 offset = top_offset;
8204 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8206 regno = mips16e_save_restore_regs[i];
8207 if (BITSET_P (*mask_ptr, regno))
8209 offset -= UNITS_PER_WORD;
8210 set = mips16e_save_restore_reg (restore_p, offset, regno);
8211 XVECEXP (pattern, 0, n++) = set;
8212 *mask_ptr &= ~(1 << regno);
8216 /* Tell the caller what offset it should use for the remaining registers. */
8217 *offset_ptr = size + (offset - top_offset);
8219 gcc_assert (n == XVECLEN (pattern, 0));
8224 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8225 pointer. Return true if PATTERN matches the kind of instruction
8226 generated by mips16e_build_save_restore. If INFO is nonnull,
8227 initialize it when returning true. */
8230 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8231 struct mips16e_save_restore_info *info)
8233 unsigned int i, nargs, mask, extra;
8234 HOST_WIDE_INT top_offset, save_offset, offset;
8235 rtx set, reg, mem, base;
8238 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8241 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8242 top_offset = adjust > 0 ? adjust : 0;
8244 /* Interpret all other members of the PARALLEL. */
8245 save_offset = top_offset - UNITS_PER_WORD;
8249 for (n = 1; n < XVECLEN (pattern, 0); n++)
8251 /* Check that we have a SET. */
8252 set = XVECEXP (pattern, 0, n);
8253 if (GET_CODE (set) != SET)
8256 /* Check that the SET is a load (if restoring) or a store
8258 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8262 /* Check that the address is the sum of the stack pointer and a
8263 possibly-zero constant offset. */
8264 mips_split_plus (XEXP (mem, 0), &base, &offset);
8265 if (base != stack_pointer_rtx)
8268 /* Check that SET's other operand is a register. */
8269 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8273 /* Check for argument saves. */
8274 if (offset == top_offset + nargs * UNITS_PER_WORD
8275 && REGNO (reg) == GP_ARG_FIRST + nargs)
8277 else if (offset == save_offset)
8279 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8280 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8283 mask |= 1 << REGNO (reg);
8284 save_offset -= UNITS_PER_WORD;
8290 /* Check that the restrictions on register ranges are met. */
8292 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8293 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8294 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8295 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8299 /* Make sure that the topmost argument register is not saved twice.
8300 The checks above ensure that the same is then true for the other
8301 argument registers. */
8302 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8305 /* Pass back information, if requested. */
8308 info->nargs = nargs;
8310 info->size = (adjust > 0 ? adjust : -adjust);
8316 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8317 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8318 the null terminator. */
8321 mips16e_add_register_range (char *s, unsigned int min_reg,
8322 unsigned int max_reg)
8324 if (min_reg != max_reg)
8325 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8327 s += sprintf (s, ",%s", reg_names[min_reg]);
8331 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8332 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8335 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8337 static char buffer[300];
8339 struct mips16e_save_restore_info info;
8340 unsigned int i, end;
8343 /* Parse the pattern. */
8344 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8347 /* Add the mnemonic. */
8348 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8351 /* Save the arguments. */
8353 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8354 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8355 else if (info.nargs == 1)
8356 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8358 /* Emit the amount of stack space to allocate or deallocate. */
8359 s += sprintf (s, "%d", (int) info.size);
8361 /* Save or restore $16. */
8362 if (BITSET_P (info.mask, 16))
8363 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8365 /* Save or restore $17. */
8366 if (BITSET_P (info.mask, 17))
8367 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8369 /* Save or restore registers in the range $s2...$s8, which
8370 mips16e_s2_s8_regs lists in decreasing order. Note that this
8371 is a software register range; the hardware registers are not
8372 numbered consecutively. */
8373 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8374 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8376 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8377 mips16e_s2_s8_regs[i]);
8379 /* Save or restore registers in the range $a0...$a3. */
8380 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8381 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8383 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8384 mips16e_a0_a3_regs[end - 1]);
8386 /* Save or restore $31. */
8387 if (BITSET_P (info.mask, 31))
8388 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
8393 /* Return true if the current function has an insn that implicitly
8397 mips_function_has_gp_insn (void)
8399 /* Don't bother rechecking if we found one last time. */
8400 if (!cfun->machine->has_gp_insn_p)
8404 push_topmost_sequence ();
8405 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8406 if (USEFUL_INSN_P (insn)
8407 && (get_attr_got (insn) != GOT_UNSET
8408 || mips_small_data_pattern_p (PATTERN (insn))))
8410 cfun->machine->has_gp_insn_p = true;
8413 pop_topmost_sequence ();
8415 return cfun->machine->has_gp_insn_p;
8418 /* Return true if the current function returns its value in a floating-point
8419 register in MIPS16 mode. */
8422 mips16_cfun_returns_in_fpr_p (void)
8424 tree return_type = DECL_RESULT (current_function_decl);
8425 return (TARGET_MIPS16
8426 && TARGET_HARD_FLOAT_ABI
8427 && !aggregate_value_p (return_type, current_function_decl)
8428 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8431 /* Return the register that should be used as the global pointer
8432 within this function. Return INVALID_REGNUM if the function
8433 doesn't need a global pointer. */
8436 mips_global_pointer (void)
8440 /* $gp is always available unless we're using a GOT. */
8441 if (!TARGET_USE_GOT)
8442 return GLOBAL_POINTER_REGNUM;
8444 /* We must always provide $gp when it is used implicitly. */
8445 if (!TARGET_EXPLICIT_RELOCS)
8446 return GLOBAL_POINTER_REGNUM;
8448 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
8451 return GLOBAL_POINTER_REGNUM;
8453 /* If the function has a nonlocal goto, $gp must hold the correct
8454 global pointer for the target function. */
8455 if (crtl->has_nonlocal_goto)
8456 return GLOBAL_POINTER_REGNUM;
8458 /* There's no need to initialize $gp if it isn't referenced now,
8459 and if we can be sure that no new references will be added during
8461 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
8462 && !mips_function_has_gp_insn ())
8464 /* The function doesn't use $gp at the moment. If we're generating
8465 -call_nonpic code, no new uses will be introduced during or after
8467 if (TARGET_ABICALLS_PIC0)
8468 return INVALID_REGNUM;
8470 /* We need to handle the following implicit gp references:
8472 - Reload can sometimes introduce constant pool references
8473 into a function that otherwise didn't need them. For example,
8474 suppose we have an instruction like:
8476 (set (reg:DF R1) (float:DF (reg:SI R2)))
8478 If R2 turns out to be constant such as 1, the instruction may
8479 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8480 the option of using this constant if R2 doesn't get allocated
8483 In cases like these, reload will have added the constant to the
8484 pool but no instruction will yet refer to it.
8486 - MIPS16 functions that return in FPRs need to call an
8487 external libgcc routine. */
8488 if (!crtl->uses_const_pool
8489 && !mips16_cfun_returns_in_fpr_p ())
8490 return INVALID_REGNUM;
8493 /* We need a global pointer, but perhaps we can use a call-clobbered
8494 register instead of $gp. */
8495 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8496 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8497 if (!df_regs_ever_live_p (regno)
8498 && call_really_used_regs[regno]
8499 && !fixed_regs[regno]
8500 && regno != PIC_FUNCTION_ADDR_REGNUM)
8503 return GLOBAL_POINTER_REGNUM;
8506 /* Return true if REGNO is a register that is ordinarily call-clobbered
8507 but must nevertheless be preserved by an interrupt handler. */
8510 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8512 if (MD_REG_P (regno))
8515 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8518 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8520 /* $0 is hard-wired. */
8521 if (regno == GP_REG_FIRST)
8524 /* The interrupt handler can treat kernel registers as
8525 scratch registers. */
8526 if (KERNEL_REG_P (regno))
8529 /* The function will return the stack pointer to its original value
8531 if (regno == STACK_POINTER_REGNUM)
8534 /* Otherwise, return true for registers that aren't ordinarily
8536 return call_really_used_regs[regno];
8542 /* Return true if the current function should treat register REGNO
8546 mips_cfun_call_saved_reg_p (unsigned int regno)
8548 /* Interrupt handlers need to save extra registers. */
8549 if (cfun->machine->interrupt_handler_p
8550 && mips_interrupt_extra_call_saved_reg_p (regno))
8553 /* call_insns preserve $28 unless they explicitly say otherwise,
8554 so call_really_used_regs[] treats $28 as call-saved. However,
8555 we want the ABI property rather than the default call_insn
8557 return (regno == GLOBAL_POINTER_REGNUM
8558 ? TARGET_CALL_SAVED_GP
8559 : !call_really_used_regs[regno]);
8562 /* Return true if the function body might clobber register REGNO.
8563 We know that REGNO is call-saved. */
8566 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
8568 /* Some functions should be treated as clobbering all call-saved
8570 if (crtl->saves_all_registers)
8573 /* DF handles cases where a register is explicitly referenced in
8574 the rtl. Incoming values are passed in call-clobbered registers,
8575 so we can assume that any live call-saved register is set within
8577 if (df_regs_ever_live_p (regno))
8580 /* Check for registers that are clobbered by FUNCTION_PROFILER.
8581 These clobbers are not explicit in the rtl. */
8582 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
8585 /* If we're using a call-saved global pointer, the function's
8586 prologue will need to set it up. */
8587 if (cfun->machine->global_pointer == regno)
8590 /* The function's prologue will need to set the frame pointer if
8591 frame_pointer_needed. */
8592 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
8595 /* If a MIPS16 function returns a value in FPRs, its epilogue
8596 will need to call an external libgcc routine. This yet-to-be
8597 generated call_insn will clobber $31. */
8598 if (regno == GP_REG_FIRST + 31 && mips16_cfun_returns_in_fpr_p ())
8601 /* If REGNO is ordinarily call-clobbered, we must assume that any
8602 called function could modify it. */
8603 if (cfun->machine->interrupt_handler_p
8604 && !current_function_is_leaf
8605 && mips_interrupt_extra_call_saved_reg_p (regno))
8611 /* Return true if the current function must save register REGNO. */
8614 mips_save_reg_p (unsigned int regno)
8616 if (mips_cfun_call_saved_reg_p (regno))
8618 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
8621 /* Save both registers in an FPR pair if either one is used. This is
8622 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
8623 register to be used without the even register. */
8624 if (FP_REG_P (regno)
8625 && MAX_FPRS_PER_FMT == 2
8626 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
8630 /* We need to save the incoming return address if __builtin_eh_return
8631 is being used to set a different return address. */
8632 if (regno == GP_REG_FIRST + 31 && crtl->calls_eh_return)
8638 /* Populate the current function's mips_frame_info structure.
8640 MIPS stack frames look like:
8642 +-------------------------------+
8644 | incoming stack arguments |
8646 +-------------------------------+
8648 | caller-allocated save area |
8649 A | for register arguments |
8651 +-------------------------------+ <-- incoming stack pointer
8653 | callee-allocated save area |
8654 B | for arguments that are |
8655 | split between registers and |
8658 +-------------------------------+ <-- arg_pointer_rtx
8660 C | callee-allocated save area |
8661 | for register varargs |
8663 +-------------------------------+ <-- frame_pointer_rtx
8664 | | + cop0_sp_offset
8665 | COP0 reg save area | + UNITS_PER_WORD
8667 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
8668 | | + UNITS_PER_WORD
8669 | accumulator save area |
8671 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
8672 | | + UNITS_PER_HWFPVALUE
8675 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
8676 | | + UNITS_PER_WORD
8679 +-------------------------------+ <-- frame_pointer_rtx with
8680 | | \ -fstack-protector
8681 | local variables | | var_size
8683 +-------------------------------+
8685 | $gp save area | | cprestore_size
8687 P +-------------------------------+ <-- hard_frame_pointer_rtx for
8689 | outgoing stack arguments | |
8691 +-------------------------------+ | args_size
8693 | caller-allocated save area | |
8694 | for register arguments | |
8696 +-------------------------------+ <-- stack_pointer_rtx
8697 frame_pointer_rtx without
8699 hard_frame_pointer_rtx for
8702 At least two of A, B and C will be empty.
8704 Dynamic stack allocations such as alloca insert data at point P.
8705 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
8706 hard_frame_pointer_rtx unchanged. */
8709 mips_compute_frame_info (void)
8711 struct mips_frame_info *frame;
8712 HOST_WIDE_INT offset, size;
8713 unsigned int regno, i;
8715 /* Set this function's interrupt properties. */
8716 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
8719 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
8720 else if (TARGET_HARD_FLOAT)
8721 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
8722 else if (TARGET_MIPS16)
8723 error ("interrupt handlers cannot be MIPS16 functions");
8726 cfun->machine->interrupt_handler_p = true;
8727 cfun->machine->use_shadow_register_set_p =
8728 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
8729 cfun->machine->keep_interrupts_masked_p =
8730 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
8731 cfun->machine->use_debug_exception_return_p =
8732 mips_use_debug_exception_return_p (TREE_TYPE
8733 (current_function_decl));
8737 frame = &cfun->machine->frame;
8738 memset (frame, 0, sizeof (*frame));
8739 size = get_frame_size ();
8741 cfun->machine->global_pointer = mips_global_pointer ();
8743 /* The first two blocks contain the outgoing argument area and the $gp save
8744 slot. This area isn't needed in leaf functions, but if the
8745 target-independent frame size is nonzero, we have already committed to
8746 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
8747 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
8749 /* The MIPS 3.0 linker does not like functions that dynamically
8750 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8751 looks like we are trying to create a second frame pointer to the
8752 function, so allocate some stack space to make it happy. */
8753 if (cfun->calls_alloca)
8754 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
8756 frame->args_size = 0;
8757 frame->cprestore_size = 0;
8761 frame->args_size = crtl->outgoing_args_size;
8762 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
8764 offset = frame->args_size + frame->cprestore_size;
8766 /* Move above the local variables. */
8767 frame->var_size = MIPS_STACK_ALIGN (size);
8768 offset += frame->var_size;
8770 /* Find out which GPRs we need to save. */
8771 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8772 if (mips_save_reg_p (regno))
8775 frame->mask |= 1 << (regno - GP_REG_FIRST);
8778 /* If this function calls eh_return, we must also save and restore the
8779 EH data registers. */
8780 if (crtl->calls_eh_return)
8781 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
8784 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
8787 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8788 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8789 save all later registers too. */
8790 if (GENERATE_MIPS16E_SAVE_RESTORE)
8792 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
8793 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
8794 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
8795 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
8798 /* Move above the GPR save area. */
8799 if (frame->num_gp > 0)
8801 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
8802 frame->gp_sp_offset = offset - UNITS_PER_WORD;
8805 /* Find out which FPRs we need to save. This loop must iterate over
8806 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
8807 if (TARGET_HARD_FLOAT)
8808 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
8809 if (mips_save_reg_p (regno))
8811 frame->num_fp += MAX_FPRS_PER_FMT;
8812 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
8815 /* Move above the FPR save area. */
8816 if (frame->num_fp > 0)
8818 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
8819 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
8822 /* Add in space for the interrupt context information. */
8823 if (cfun->machine->interrupt_handler_p)
8826 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
8829 frame->acc_mask |= (1 << 0);
8832 /* Check accumulators 1, 2, 3. */
8833 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
8834 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
8837 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
8840 /* All interrupt context functions need space to preserve STATUS. */
8841 frame->num_cop0_regs++;
8843 /* If we don't keep interrupts masked, we need to save EPC. */
8844 if (!cfun->machine->keep_interrupts_masked_p)
8845 frame->num_cop0_regs++;
8848 /* Move above the accumulator save area. */
8849 if (frame->num_acc > 0)
8851 /* Each accumulator needs 2 words. */
8852 offset += frame->num_acc * 2 * UNITS_PER_WORD;
8853 frame->acc_sp_offset = offset - UNITS_PER_WORD;
8856 /* Move above the COP0 register save area. */
8857 if (frame->num_cop0_regs > 0)
8859 offset += frame->num_cop0_regs * UNITS_PER_WORD;
8860 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
8863 /* Move above the callee-allocated varargs save area. */
8864 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
8865 frame->arg_pointer_offset = offset;
8867 /* Move above the callee-allocated area for pretend stack arguments. */
8868 offset += crtl->args.pretend_args_size;
8869 frame->total_size = offset;
8871 /* Work out the offsets of the save areas from the top of the frame. */
8872 if (frame->gp_sp_offset > 0)
8873 frame->gp_save_offset = frame->gp_sp_offset - offset;
8874 if (frame->fp_sp_offset > 0)
8875 frame->fp_save_offset = frame->fp_sp_offset - offset;
8876 if (frame->acc_sp_offset > 0)
8877 frame->acc_save_offset = frame->acc_sp_offset - offset;
8878 if (frame->num_cop0_regs > 0)
8879 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
8881 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8882 arguments. This tends to increase the chances of using unextended
8883 instructions for local variables and incoming arguments. */
8885 frame->hard_frame_pointer_offset = frame->args_size;
8888 /* Return the style of GP load sequence that is being used for the
8889 current function. */
8891 enum mips_loadgp_style
8892 mips_current_loadgp_style (void)
8894 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
8900 if (TARGET_ABSOLUTE_ABICALLS)
8901 return LOADGP_ABSOLUTE;
8903 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
8906 /* Implement FRAME_POINTER_REQUIRED. */
8909 mips_frame_pointer_required (void)
8911 /* If the function contains dynamic stack allocations, we need to
8912 use the frame pointer to access the static parts of the frame. */
8913 if (cfun->calls_alloca)
8916 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8917 reload may be unable to compute the address of a local variable,
8918 since there is no way to add a large constant to the stack pointer
8919 without using a second temporary register. */
8922 mips_compute_frame_info ();
8923 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8930 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8931 or argument pointer. TO is either the stack pointer or hard frame
8935 mips_initial_elimination_offset (int from, int to)
8937 HOST_WIDE_INT offset;
8939 mips_compute_frame_info ();
8941 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
8944 case FRAME_POINTER_REGNUM:
8945 if (FRAME_GROWS_DOWNWARD)
8946 offset = (cfun->machine->frame.args_size
8947 + cfun->machine->frame.cprestore_size
8948 + cfun->machine->frame.var_size);
8953 case ARG_POINTER_REGNUM:
8954 offset = cfun->machine->frame.arg_pointer_offset;
8961 if (to == HARD_FRAME_POINTER_REGNUM)
8962 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8967 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8970 mips_extra_live_on_entry (bitmap regs)
8974 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8975 the global pointer. */
8976 if (!TARGET_ABSOLUTE_ABICALLS)
8977 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8979 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
8980 the global pointer. */
8982 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
8984 /* See the comment above load_call<mode> for details. */
8985 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
8989 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8993 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
8998 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
9001 /* Emit code to change the current function's return address to
9002 ADDRESS. SCRATCH is available as a scratch register, if needed.
9003 ADDRESS and SCRATCH are both word-mode GPRs. */
9006 mips_set_return_address (rtx address, rtx scratch)
9010 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
9011 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9012 cfun->machine->frame.gp_sp_offset);
9013 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9016 /* Return a MEM rtx for the cprestore slot, using TEMP as a temporary base
9017 register if need be. */
9020 mips_cprestore_slot (rtx temp)
9022 const struct mips_frame_info *frame;
9024 HOST_WIDE_INT offset;
9026 frame = &cfun->machine->frame;
9027 if (frame_pointer_needed)
9029 base = hard_frame_pointer_rtx;
9030 offset = frame->args_size - frame->hard_frame_pointer_offset;
9034 base = stack_pointer_rtx;
9035 offset = frame->args_size;
9037 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9040 /* Restore $gp from its save slot, using TEMP as a temporary base register
9041 if need be. This function is for o32 and o64 abicalls only. */
9044 mips_restore_gp (rtx temp)
9046 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
9048 if (cfun->machine->global_pointer == INVALID_REGNUM)
9053 mips_emit_move (temp, mips_cprestore_slot (temp));
9054 mips_emit_move (pic_offset_table_rtx, temp);
9057 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp));
9058 if (!TARGET_EXPLICIT_RELOCS)
9059 emit_insn (gen_blockage ());
9062 /* A function to save or store a register. The first argument is the
9063 register and the second is the stack slot. */
9064 typedef void (*mips_save_restore_fn) (rtx, rtx);
9066 /* Use FN to save or restore register REGNO. MODE is the register's
9067 mode and OFFSET is the offset of its save slot from the current
9071 mips_save_restore_reg (enum machine_mode mode, int regno,
9072 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9076 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9077 fn (gen_rtx_REG (mode, regno), mem);
9080 /* Call FN for each accumlator that is saved by the current function.
9081 SP_OFFSET is the offset of the current stack pointer from the start
9085 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9087 HOST_WIDE_INT offset;
9090 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9091 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9093 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9094 offset -= UNITS_PER_WORD;
9095 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9096 offset -= UNITS_PER_WORD;
9099 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9100 if (BITSET_P (cfun->machine->frame.acc_mask,
9101 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9103 mips_save_restore_reg (word_mode, regno, offset, fn);
9104 offset -= UNITS_PER_WORD;
9108 /* Call FN for each register that is saved by the current function.
9109 SP_OFFSET is the offset of the current stack pointer from the start
9113 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9114 mips_save_restore_fn fn)
9116 enum machine_mode fpr_mode;
9117 HOST_WIDE_INT offset;
9120 /* Save registers starting from high to low. The debuggers prefer at least
9121 the return register be stored at func+4, and also it allows us not to
9122 need a nop in the epilogue if at least one register is reloaded in
9123 addition to return address. */
9124 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9125 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9126 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9128 mips_save_restore_reg (word_mode, regno, offset, fn);
9129 offset -= UNITS_PER_WORD;
9132 /* This loop must iterate over the same space as its companion in
9133 mips_compute_frame_info. */
9134 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9135 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9136 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9137 regno >= FP_REG_FIRST;
9138 regno -= MAX_FPRS_PER_FMT)
9139 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9141 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9142 offset -= GET_MODE_SIZE (fpr_mode);
9146 /* If we're generating n32 or n64 abicalls, and the current function
9147 does not use $28 as its global pointer, emit a cplocal directive.
9148 Use pic_offset_table_rtx as the argument to the directive. */
9151 mips_output_cplocal (void)
9153 if (!TARGET_EXPLICIT_RELOCS
9154 && cfun->machine->global_pointer != INVALID_REGNUM
9155 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9156 output_asm_insn (".cplocal %+", 0);
9159 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9162 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9166 #ifdef SDB_DEBUGGING_INFO
9167 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9168 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9171 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9172 floating-point arguments. */
9174 && TARGET_HARD_FLOAT_ABI
9175 && crtl->args.info.fp_code != 0)
9176 mips16_build_function_stub ();
9178 /* Get the function name the same way that toplev.c does before calling
9179 assemble_start_function. This is needed so that the name used here
9180 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9181 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9182 mips_start_function_definition (fnname, TARGET_MIPS16);
9184 /* Stop mips_file_end from treating this function as external. */
9185 if (TARGET_IRIX && mips_abi == ABI_32)
9186 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
9188 /* Output MIPS-specific frame information. */
9189 if (!flag_inhibit_size_directive)
9191 const struct mips_frame_info *frame;
9193 frame = &cfun->machine->frame;
9195 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9197 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9198 "# vars= " HOST_WIDE_INT_PRINT_DEC
9200 ", args= " HOST_WIDE_INT_PRINT_DEC
9201 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9202 reg_names[frame_pointer_needed
9203 ? HARD_FRAME_POINTER_REGNUM
9204 : STACK_POINTER_REGNUM],
9205 (frame_pointer_needed
9206 ? frame->total_size - frame->hard_frame_pointer_offset
9207 : frame->total_size),
9208 reg_names[GP_REG_FIRST + 31],
9210 frame->num_gp, frame->num_fp,
9212 frame->cprestore_size);
9214 /* .mask MASK, OFFSET. */
9215 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9216 frame->mask, frame->gp_save_offset);
9218 /* .fmask MASK, OFFSET. */
9219 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9220 frame->fmask, frame->fp_save_offset);
9223 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9224 Also emit the ".set noreorder; .set nomacro" sequence for functions
9226 if (mips_current_loadgp_style () == LOADGP_OLDABI)
9230 /* This is a fixed-form sequence. The position of the
9231 first two instructions is important because of the
9232 way _gp_disp is defined. */
9233 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9234 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9235 output_asm_insn ("sll\t$2,16", 0);
9236 output_asm_insn ("addu\t$2,$3", 0);
9238 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
9239 else if (!cfun->machine->all_noreorder_p)
9240 output_asm_insn ("%(.cpload\t%^%)", 0);
9242 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
9244 else if (cfun->machine->all_noreorder_p)
9245 output_asm_insn ("%(%<", 0);
9247 /* Tell the assembler which register we're using as the global
9248 pointer. This is needed for thunks, since they can use either
9249 explicit relocs or assembler macros. */
9250 mips_output_cplocal ();
9253 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9256 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9257 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9261 /* Reinstate the normal $gp. */
9262 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9263 mips_output_cplocal ();
9265 if (cfun->machine->all_noreorder_p)
9267 /* Avoid using %>%) since it adds excess whitespace. */
9268 output_asm_insn (".set\tmacro", 0);
9269 output_asm_insn (".set\treorder", 0);
9270 set_noreorder = set_nomacro = 0;
9273 /* Get the function name the same way that toplev.c does before calling
9274 assemble_start_function. This is needed so that the name used here
9275 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9276 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9277 mips_end_function_definition (fnname);
9280 /* Save register REG to MEM. Make the instruction frame-related. */
9283 mips_save_reg (rtx reg, rtx mem)
9285 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9289 if (mips_split_64bit_move_p (mem, reg))
9290 mips_split_doubleword_move (mem, reg);
9292 mips_emit_move (mem, reg);
9294 x1 = mips_frame_set (mips_subword (mem, false),
9295 mips_subword (reg, false));
9296 x2 = mips_frame_set (mips_subword (mem, true),
9297 mips_subword (reg, true));
9298 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9302 if (REGNO (reg) == HI_REGNUM)
9305 emit_insn (gen_mfhidi_ti (MIPS_PROLOGUE_TEMP (DImode),
9306 gen_rtx_REG (TImode, MD_REG_FIRST)));
9308 emit_insn (gen_mfhisi_di (MIPS_PROLOGUE_TEMP (SImode),
9309 gen_rtx_REG (DImode, MD_REG_FIRST)));
9310 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9312 else if ((TARGET_MIPS16
9313 && REGNO (reg) != GP_REG_FIRST + 31
9314 && !M16_REG_P (REGNO (reg)))
9315 || ACC_REG_P (REGNO (reg)))
9317 /* If the register has no direct store instruction, move it
9318 through a temporary. Note that there's a special MIPS16
9319 instruction to save $31. */
9320 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
9321 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9324 mips_emit_move (mem, reg);
9326 mips_set_frame_expr (mips_frame_set (mem, reg));
9330 /* The __gnu_local_gp symbol. */
9332 static GTY(()) rtx mips_gnu_local_gp;
9334 /* If we're generating n32 or n64 abicalls, emit instructions
9335 to set up the global pointer. */
9338 mips_emit_loadgp (void)
9340 rtx addr, offset, incoming_address, base, index, pic_reg;
9342 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9343 switch (mips_current_loadgp_style ())
9345 case LOADGP_ABSOLUTE:
9346 if (mips_gnu_local_gp == NULL)
9348 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9349 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9351 emit_insn (Pmode == SImode
9352 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9353 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9357 /* Added by mips_output_function_prologue. */
9361 addr = XEXP (DECL_RTL (current_function_decl), 0);
9362 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9363 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9364 emit_insn (Pmode == SImode
9365 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9366 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9370 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9371 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9372 emit_insn (Pmode == SImode
9373 ? gen_loadgp_rtp_si (pic_reg, base, index)
9374 : gen_loadgp_rtp_di (pic_reg, base, index));
9382 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9384 /* Emit a blockage if there are implicit uses of the GP register.
9385 This includes profiled functions, because FUNCTION_PROFILE uses
9387 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9388 emit_insn (gen_loadgp_blockage ());
9391 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9394 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
9396 return GET_CODE (*x) == REG && KERNEL_REG_P (REGNO (*x));
9399 /* Expand the "prologue" pattern. */
9402 mips_expand_prologue (void)
9404 const struct mips_frame_info *frame;
9409 if (cfun->machine->global_pointer != INVALID_REGNUM)
9410 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
9412 frame = &cfun->machine->frame;
9413 size = frame->total_size;
9415 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9416 bytes beforehand; this is enough to cover the register save area
9417 without going out of range. */
9418 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
9419 || frame->num_cop0_regs > 0)
9421 HOST_WIDE_INT step1;
9423 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
9424 if (GENERATE_MIPS16E_SAVE_RESTORE)
9426 HOST_WIDE_INT offset;
9427 unsigned int mask, regno;
9429 /* Try to merge argument stores into the save instruction. */
9430 nargs = mips16e_collect_argument_saves ();
9432 /* Build the save instruction. */
9434 insn = mips16e_build_save_restore (false, &mask, &offset,
9436 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9439 /* Check if we need to save other registers. */
9440 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9441 if (BITSET_P (mask, regno - GP_REG_FIRST))
9443 offset -= UNITS_PER_WORD;
9444 mips_save_restore_reg (word_mode, regno,
9445 offset, mips_save_reg);
9450 if (cfun->machine->interrupt_handler_p)
9452 HOST_WIDE_INT offset;
9455 /* If this interrupt is using a shadow register set, we need to
9456 get the stack pointer from the previous register set. */
9457 if (cfun->machine->use_shadow_register_set_p)
9458 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
9459 stack_pointer_rtx));
9461 if (!cfun->machine->keep_interrupts_masked_p)
9463 /* Move from COP0 Cause to K0. */
9464 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
9465 gen_rtx_REG (SImode,
9466 COP0_CAUSE_REG_NUM)));
9467 /* Move from COP0 EPC to K1. */
9468 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
9469 gen_rtx_REG (SImode,
9470 COP0_EPC_REG_NUM)));
9473 /* Allocate the first part of the frame. */
9474 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
9476 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9479 /* Start at the uppermost location for saving. */
9480 offset = frame->cop0_sp_offset - size;
9481 if (!cfun->machine->keep_interrupts_masked_p)
9483 /* Push EPC into its stack slot. */
9484 mem = gen_frame_mem (word_mode,
9485 plus_constant (stack_pointer_rtx,
9487 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
9488 offset -= UNITS_PER_WORD;
9491 /* Move from COP0 Status to K1. */
9492 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
9493 gen_rtx_REG (SImode,
9494 COP0_STATUS_REG_NUM)));
9496 /* Right justify the RIPL in k0. */
9497 if (!cfun->machine->keep_interrupts_masked_p)
9498 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
9499 gen_rtx_REG (SImode, K0_REG_NUM),
9500 GEN_INT (CAUSE_IPL)));
9502 /* Push Status into its stack slot. */
9503 mem = gen_frame_mem (word_mode,
9504 plus_constant (stack_pointer_rtx, offset));
9505 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
9506 offset -= UNITS_PER_WORD;
9508 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
9509 if (!cfun->machine->keep_interrupts_masked_p)
9510 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9513 gen_rtx_REG (SImode, K0_REG_NUM)));
9515 if (!cfun->machine->keep_interrupts_masked_p)
9516 /* Enable interrupts by clearing the KSU ERL and EXL bits.
9517 IE is already the correct value, so we don't have to do
9518 anything explicit. */
9519 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9522 gen_rtx_REG (SImode, GP_REG_FIRST)));
9524 /* Disable interrupts by clearing the KSU, ERL, EXL,
9526 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9529 gen_rtx_REG (SImode, GP_REG_FIRST)));
9533 insn = gen_add3_insn (stack_pointer_rtx,
9536 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9539 mips_for_each_saved_acc (size, mips_save_reg);
9540 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
9544 /* Allocate the rest of the frame. */
9547 if (SMALL_OPERAND (-size))
9548 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
9550 GEN_INT (-size)))) = 1;
9553 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
9556 /* There are no instructions to add or subtract registers
9557 from the stack pointer, so use the frame pointer as a
9558 temporary. We should always be using a frame pointer
9559 in this case anyway. */
9560 gcc_assert (frame_pointer_needed);
9561 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9562 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
9563 hard_frame_pointer_rtx,
9564 MIPS_PROLOGUE_TEMP (Pmode)));
9565 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
9568 emit_insn (gen_sub3_insn (stack_pointer_rtx,
9570 MIPS_PROLOGUE_TEMP (Pmode)));
9572 /* Describe the combined effect of the previous instructions. */
9574 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9575 plus_constant (stack_pointer_rtx, -size)));
9579 /* Set up the frame pointer, if we're using one. */
9580 if (frame_pointer_needed)
9582 HOST_WIDE_INT offset;
9584 offset = frame->hard_frame_pointer_offset;
9587 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9588 RTX_FRAME_RELATED_P (insn) = 1;
9590 else if (SMALL_OPERAND (offset))
9592 insn = gen_add3_insn (hard_frame_pointer_rtx,
9593 stack_pointer_rtx, GEN_INT (offset));
9594 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9598 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
9599 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9600 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
9601 hard_frame_pointer_rtx,
9602 MIPS_PROLOGUE_TEMP (Pmode)));
9604 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
9605 plus_constant (stack_pointer_rtx, offset)));
9609 mips_emit_loadgp ();
9611 /* Initialize the $gp save slot. */
9612 if (frame->cprestore_size > 0
9613 && cfun->machine->global_pointer != INVALID_REGNUM)
9616 mips_emit_move (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9618 else if (TARGET_ABICALLS_PIC2)
9619 emit_insn (gen_cprestore (GEN_INT (frame->args_size)));
9621 emit_move_insn (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9622 pic_offset_table_rtx);
9625 /* We need to search back to the last use of K0 or K1. */
9626 if (cfun->machine->interrupt_handler_p)
9628 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
9630 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
9632 /* Emit a move from K1 to COP0 Status after insn. */
9633 gcc_assert (insn != NULL_RTX);
9634 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
9635 gen_rtx_REG (SImode, K1_REG_NUM)),
9639 /* If we are profiling, make sure no instructions are scheduled before
9640 the call to mcount. */
9642 emit_insn (gen_blockage ());
9645 /* Emit instructions to restore register REG from slot MEM. */
9648 mips_restore_reg (rtx reg, rtx mem)
9650 /* There's no MIPS16 instruction to load $31 directly. Load into
9651 $7 instead and adjust the return insn appropriately. */
9652 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
9653 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
9655 if (REGNO (reg) == HI_REGNUM)
9657 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
9659 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9660 MIPS_EPILOGUE_TEMP (DImode),
9661 gen_rtx_REG (DImode, LO_REGNUM)));
9663 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9664 MIPS_EPILOGUE_TEMP (SImode),
9665 gen_rtx_REG (SImode, LO_REGNUM)));
9667 else if ((TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
9668 || ACC_REG_P (REGNO (reg)))
9670 /* Can't restore directly; move through a temporary. */
9671 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
9672 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
9675 mips_emit_move (reg, mem);
9678 /* Emit any instructions needed before a return. */
9681 mips_expand_before_return (void)
9683 /* When using a call-clobbered gp, we start out with unified call
9684 insns that include instructions to restore the gp. We then split
9685 these unified calls after reload. These split calls explicitly
9686 clobber gp, so there is no need to define
9687 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
9689 For consistency, we should also insert an explicit clobber of $28
9690 before return insns, so that the post-reload optimizers know that
9691 the register is not live on exit. */
9692 if (TARGET_CALL_CLOBBERED_GP)
9693 emit_clobber (pic_offset_table_rtx);
9696 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
9700 mips_expand_epilogue (bool sibcall_p)
9702 const struct mips_frame_info *frame;
9703 HOST_WIDE_INT step1, step2;
9704 rtx base, target, insn;
9706 if (!sibcall_p && mips_can_use_return_insn ())
9708 emit_jump_insn (gen_return ());
9712 /* In MIPS16 mode, if the return value should go into a floating-point
9713 register, we need to call a helper routine to copy it over. */
9714 if (mips16_cfun_returns_in_fpr_p ())
9715 mips16_copy_fpr_return_value ();
9717 /* Split the frame into two. STEP1 is the amount of stack we should
9718 deallocate before restoring the registers. STEP2 is the amount we
9719 should deallocate afterwards.
9721 Start off by assuming that no registers need to be restored. */
9722 frame = &cfun->machine->frame;
9723 step1 = frame->total_size;
9726 /* Work out which register holds the frame address. */
9727 if (!frame_pointer_needed)
9728 base = stack_pointer_rtx;
9731 base = hard_frame_pointer_rtx;
9732 step1 -= frame->hard_frame_pointer_offset;
9735 /* If we need to restore registers, deallocate as much stack as
9736 possible in the second step without going out of range. */
9737 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
9738 || frame->num_cop0_regs > 0)
9740 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
9744 /* Set TARGET to BASE + STEP1. */
9750 /* Get an rtx for STEP1 that we can add to BASE. */
9751 adjust = GEN_INT (step1);
9752 if (!SMALL_OPERAND (step1))
9754 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
9755 adjust = MIPS_EPILOGUE_TEMP (Pmode);
9758 /* Normal mode code can copy the result straight into $sp. */
9760 target = stack_pointer_rtx;
9762 emit_insn (gen_add3_insn (target, base, adjust));
9765 /* Copy TARGET into the stack pointer. */
9766 if (target != stack_pointer_rtx)
9767 mips_emit_move (stack_pointer_rtx, target);
9769 /* If we're using addressing macros, $gp is implicitly used by all
9770 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
9772 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
9773 emit_insn (gen_blockage ());
9775 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
9777 unsigned int regno, mask;
9778 HOST_WIDE_INT offset;
9781 /* Generate the restore instruction. */
9783 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
9785 /* Restore any other registers manually. */
9786 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9787 if (BITSET_P (mask, regno - GP_REG_FIRST))
9789 offset -= UNITS_PER_WORD;
9790 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
9793 /* Restore the remaining registers and deallocate the final bit
9795 emit_insn (restore);
9799 /* Restore the registers. */
9800 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
9801 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
9804 if (cfun->machine->interrupt_handler_p)
9806 HOST_WIDE_INT offset;
9809 offset = frame->cop0_sp_offset - (frame->total_size - step2);
9810 if (!cfun->machine->keep_interrupts_masked_p)
9812 /* Restore the original EPC. */
9813 mem = gen_frame_mem (word_mode,
9814 plus_constant (stack_pointer_rtx, offset));
9815 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
9816 offset -= UNITS_PER_WORD;
9818 /* Move to COP0 EPC. */
9819 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
9820 gen_rtx_REG (SImode, K0_REG_NUM)));
9823 /* Restore the original Status. */
9824 mem = gen_frame_mem (word_mode,
9825 plus_constant (stack_pointer_rtx, offset));
9826 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
9827 offset -= UNITS_PER_WORD;
9829 /* If we don't use shoadow register set, we need to update SP. */
9830 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
9831 emit_insn (gen_add3_insn (stack_pointer_rtx,
9835 /* Move to COP0 Status. */
9836 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
9837 gen_rtx_REG (SImode, K0_REG_NUM)));
9841 /* Deallocate the final bit of the frame. */
9843 emit_insn (gen_add3_insn (stack_pointer_rtx,
9849 /* Add in the __builtin_eh_return stack adjustment. We need to
9850 use a temporary in MIPS16 code. */
9851 if (crtl->calls_eh_return)
9855 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
9856 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
9857 MIPS_EPILOGUE_TEMP (Pmode),
9858 EH_RETURN_STACKADJ_RTX));
9859 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
9862 emit_insn (gen_add3_insn (stack_pointer_rtx,
9864 EH_RETURN_STACKADJ_RTX));
9869 mips_expand_before_return ();
9870 if (cfun->machine->interrupt_handler_p)
9872 /* Interrupt handlers generate eret or deret. */
9873 if (cfun->machine->use_debug_exception_return_p)
9874 emit_jump_insn (gen_mips_deret ());
9876 emit_jump_insn (gen_mips_eret ());
9882 /* When generating MIPS16 code, the normal
9883 mips_for_each_saved_gpr_and_fpr path will restore the return
9884 address into $7 rather than $31. */
9886 && !GENERATE_MIPS16E_SAVE_RESTORE
9887 && BITSET_P (frame->mask, 31))
9888 regno = GP_REG_FIRST + 7;
9890 regno = GP_REG_FIRST + 31;
9891 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
9895 /* Search from the beginning to the first use of K0 or K1. */
9896 if (cfun->machine->interrupt_handler_p
9897 && !cfun->machine->keep_interrupts_masked_p)
9899 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
9901 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
9903 gcc_assert (insn != NULL_RTX);
9904 /* Insert disable interrupts before the first use of K0 or K1. */
9905 emit_insn_before (gen_mips_di (), insn);
9906 emit_insn_before (gen_mips_ehb (), insn);
9910 /* Return nonzero if this function is known to have a null epilogue.
9911 This allows the optimizer to omit jumps to jumps if no stack
9915 mips_can_use_return_insn (void)
9917 /* Interrupt handlers need to go through the epilogue. */
9918 if (cfun->machine->interrupt_handler_p)
9921 if (!reload_completed)
9927 /* In MIPS16 mode, a function that returns a floating-point value
9928 needs to arrange to copy the return value into the floating-point
9930 if (mips16_cfun_returns_in_fpr_p ())
9933 return cfun->machine->frame.total_size == 0;
9936 /* Return true if register REGNO can store a value of mode MODE.
9937 The result of this function is cached in mips_hard_regno_mode_ok. */
9940 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
9943 enum mode_class mclass;
9945 if (mode == CCV2mode)
9948 && (regno - ST_REG_FIRST) % 2 == 0);
9950 if (mode == CCV4mode)
9953 && (regno - ST_REG_FIRST) % 4 == 0);
9958 return regno == FPSW_REGNUM;
9960 return (ST_REG_P (regno)
9962 || FP_REG_P (regno));
9965 size = GET_MODE_SIZE (mode);
9966 mclass = GET_MODE_CLASS (mode);
9968 if (GP_REG_P (regno))
9969 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
9971 if (FP_REG_P (regno)
9972 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
9973 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
9975 /* Allow TFmode for CCmode reloads. */
9976 if (mode == TFmode && ISA_HAS_8CC)
9979 /* Allow 64-bit vector modes for Loongson-2E/2F. */
9980 if (TARGET_LOONGSON_VECTORS
9981 && (mode == V2SImode
9987 if (mclass == MODE_FLOAT
9988 || mclass == MODE_COMPLEX_FLOAT
9989 || mclass == MODE_VECTOR_FLOAT)
9990 return size <= UNITS_PER_FPVALUE;
9992 /* Allow integer modes that fit into a single register. We need
9993 to put integers into FPRs when using instructions like CVT
9994 and TRUNC. There's no point allowing sizes smaller than a word,
9995 because the FPU has no appropriate load/store instructions. */
9996 if (mclass == MODE_INT)
9997 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10000 if (ACC_REG_P (regno)
10001 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10003 if (MD_REG_P (regno))
10005 /* After a multiplication or division, clobbering HI makes
10006 the value of LO unpredictable, and vice versa. This means
10007 that, for all interesting cases, HI and LO are effectively
10010 We model this by requiring that any value that uses HI
10012 if (size <= UNITS_PER_WORD * 2)
10013 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10017 /* DSP accumulators do not have the same restrictions as
10018 HI and LO, so we can treat them as normal doubleword
10020 if (size <= UNITS_PER_WORD)
10023 if (size <= UNITS_PER_WORD * 2
10024 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10029 if (ALL_COP_REG_P (regno))
10030 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10032 if (regno == GOT_VERSION_REGNUM)
10033 return mode == SImode;
10038 /* Implement HARD_REGNO_NREGS. */
10041 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10043 if (ST_REG_P (regno))
10044 /* The size of FP status registers is always 4, because they only hold
10045 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10046 return (GET_MODE_SIZE (mode) + 3) / 4;
10048 if (FP_REG_P (regno))
10049 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10051 /* All other registers are word-sized. */
10052 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10055 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10056 in mips_hard_regno_nregs. */
10059 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10065 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10066 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10068 size = MIN (size, 4);
10069 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10071 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10073 size = MIN (size, UNITS_PER_FPREG);
10074 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10076 if (!hard_reg_set_empty_p (left))
10077 size = MIN (size, UNITS_PER_WORD);
10078 return (GET_MODE_SIZE (mode) + size - 1) / size;
10081 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10084 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10085 enum machine_mode to ATTRIBUTE_UNUSED,
10086 enum reg_class rclass)
10088 /* There are several problems with changing the modes of values
10089 in floating-point registers:
10091 - When a multi-word value is stored in paired floating-point
10092 registers, the first register always holds the low word.
10093 We therefore can't allow FPRs to change between single-word
10094 and multi-word modes on big-endian targets.
10096 - GCC assumes that each word of a multiword register can be accessed
10097 individually using SUBREGs. This is not true for floating-point
10098 registers if they are bigger than a word.
10100 - Loading a 32-bit value into a 64-bit floating-point register
10101 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10102 We can't allow FPRs to change from SImode to to a wider mode on
10105 - If the FPU has already interpreted a value in one format, we must
10106 not ask it to treat the value as having a different format.
10108 We therefore disallow all mode changes involving FPRs. */
10109 return reg_classes_intersect_p (FP_REGS, rclass);
10112 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10115 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10120 return TARGET_HARD_FLOAT;
10123 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10126 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10133 /* Implement MODES_TIEABLE_P. */
10136 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10138 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10139 prefer to put one of them in FPRs. */
10140 return (mode1 == mode2
10141 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10142 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10145 /* Implement PREFERRED_RELOAD_CLASS. */
10148 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10150 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10153 if (reg_class_subset_p (FP_REGS, rclass)
10154 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10157 if (reg_class_subset_p (GR_REGS, rclass))
10160 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10166 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10167 Return a "canonical" class to represent it in later calculations. */
10169 static enum reg_class
10170 mips_canonicalize_move_class (enum reg_class rclass)
10172 /* All moves involving accumulator registers have the same cost. */
10173 if (reg_class_subset_p (rclass, ACC_REGS))
10176 /* Likewise promote subclasses of general registers to the most
10177 interesting containing class. */
10178 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10180 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10181 rclass = GENERAL_REGS;
10186 /* Return the cost of moving a value of mode MODE from a register of
10187 class FROM to a GPR. Return 0 for classes that are unions of other
10188 classes handled by this function. */
10191 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10192 enum reg_class from)
10197 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10201 /* MFLO and MFHI. */
10209 /* LUI followed by MOVF. */
10215 /* This choice of value is historical. */
10223 /* Return the cost of moving a value of mode MODE from a GPR to a
10224 register of class TO. Return 0 for classes that are unions of
10225 other classes handled by this function. */
10228 mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to)
10233 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10237 /* MTLO and MTHI. */
10245 /* A secondary reload through an FPR scratch. */
10246 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10247 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10252 /* This choice of value is historical. */
10260 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
10261 maximum of the move costs for subclasses; regclass will work out
10262 the maximum for us. */
10265 mips_register_move_cost (enum machine_mode mode,
10266 enum reg_class from, enum reg_class to)
10268 enum reg_class dregs;
10271 from = mips_canonicalize_move_class (from);
10272 to = mips_canonicalize_move_class (to);
10274 /* Handle moves that can be done without using general-purpose registers. */
10275 if (from == FP_REGS)
10277 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10281 /* The sequence generated by mips_expand_fcc_reload. */
10285 /* Handle cases in which only one class deviates from the ideal. */
10286 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10288 return mips_move_from_gpr_cost (mode, to);
10290 return mips_move_to_gpr_cost (mode, from);
10292 /* Handles cases that require a GPR temporary. */
10293 cost1 = mips_move_to_gpr_cost (mode, from);
10296 cost2 = mips_move_from_gpr_cost (mode, to);
10298 return cost1 + cost2;
10304 /* Implement TARGET_IRA_COVER_CLASSES. */
10306 static const enum reg_class *
10307 mips_ira_cover_classes (void)
10309 static const enum reg_class acc_classes[] = {
10310 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10311 ST_REGS, LIM_REG_CLASSES
10313 static const enum reg_class no_acc_classes[] = {
10314 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10315 ST_REGS, LIM_REG_CLASSES
10318 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10319 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10320 as a cover class only works well when we keep per-register costs.
10321 Using it when not optimizing can cause us to think accumulators
10322 have the same cost as GPRs in cases where GPRs are actually much
10324 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10327 /* Return the register class required for a secondary register when
10328 copying between one of the registers in RCLASS and value X, which
10329 has mode MODE. X is the source of the move if IN_P, otherwise it
10330 is the destination. Return NO_REGS if no secondary register is
10334 mips_secondary_reload_class (enum reg_class rclass,
10335 enum machine_mode mode, rtx x, bool in_p)
10339 /* If X is a constant that cannot be loaded into $25, it must be loaded
10340 into some other GPR. No other register class allows a direct move. */
10341 if (mips_dangerous_for_la25_p (x))
10342 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
10344 regno = true_regnum (x);
10347 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10348 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
10354 /* Copying from accumulator registers to anywhere other than a general
10355 register requires a temporary general register. */
10356 if (reg_class_subset_p (rclass, ACC_REGS))
10357 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10358 if (ACC_REG_P (regno))
10359 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10361 /* We can only copy a value to a condition code register from a
10362 floating-point register, and even then we require a scratch
10363 floating-point register. We can only copy a value out of a
10364 condition-code register into a general register. */
10365 if (reg_class_subset_p (rclass, ST_REGS))
10369 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10371 if (ST_REG_P (regno))
10375 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10378 if (reg_class_subset_p (rclass, FP_REGS))
10381 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
10382 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10383 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10386 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
10387 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10390 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
10391 /* We can force the constant to memory and use lwc1
10392 and ldc1. As above, we will use pairs of lwc1s if
10393 ldc1 is not supported. */
10396 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
10397 /* In this case we can use mov.fmt. */
10400 /* Otherwise, we need to reload through an integer register. */
10403 if (FP_REG_P (regno))
10404 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10409 /* Implement TARGET_MODE_REP_EXTENDED. */
10412 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10414 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
10415 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10416 return SIGN_EXTEND;
10421 /* Implement TARGET_VALID_POINTER_MODE. */
10424 mips_valid_pointer_mode (enum machine_mode mode)
10426 return mode == SImode || (TARGET_64BIT && mode == DImode);
10429 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10432 mips_vector_mode_supported_p (enum machine_mode mode)
10437 return TARGET_PAIRED_SINGLE_FLOAT;
10452 return TARGET_LOONGSON_VECTORS;
10459 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
10462 mips_scalar_mode_supported_p (enum machine_mode mode)
10464 if (ALL_FIXED_POINT_MODE_P (mode)
10465 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
10468 return default_scalar_mode_supported_p (mode);
10471 /* Implement TARGET_INIT_LIBFUNCS. */
10473 #include "config/gofast.h"
10476 mips_init_libfuncs (void)
10478 if (TARGET_FIX_VR4120)
10480 /* Register the special divsi3 and modsi3 functions needed to work
10481 around VR4120 division errata. */
10482 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10483 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
10486 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
10488 /* Register the MIPS16 -mhard-float stubs. */
10489 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
10490 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
10491 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
10492 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
10494 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
10495 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
10496 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
10497 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
10498 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
10499 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
10500 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
10502 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
10503 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
10504 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
10506 if (TARGET_DOUBLE_FLOAT)
10508 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
10509 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
10510 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
10511 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
10513 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
10514 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
10515 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
10516 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
10517 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
10518 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
10519 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
10521 set_conv_libfunc (sext_optab, DFmode, SFmode,
10522 "__mips16_extendsfdf2");
10523 set_conv_libfunc (trunc_optab, SFmode, DFmode,
10524 "__mips16_truncdfsf2");
10525 set_conv_libfunc (sfix_optab, SImode, DFmode,
10526 "__mips16_fix_truncdfsi");
10527 set_conv_libfunc (sfloat_optab, DFmode, SImode,
10528 "__mips16_floatsidf");
10529 set_conv_libfunc (ufloat_optab, DFmode, SImode,
10530 "__mips16_floatunsidf");
10534 /* Register the gofast functions if selected using --enable-gofast. */
10535 gofast_maybe_init_libfuncs ();
10537 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
10538 on an external non-MIPS16 routine to implement __sync_synchronize. */
10540 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
10543 /* Return the length of INSN. LENGTH is the initial length computed by
10544 attributes in the machine-description file. */
10547 mips_adjust_insn_length (rtx insn, int length)
10549 /* A unconditional jump has an unfilled delay slot if it is not part
10550 of a sequence. A conditional jump normally has a delay slot, but
10551 does not on MIPS16. */
10552 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
10555 /* See how many nops might be needed to avoid hardware hazards. */
10556 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
10557 switch (get_attr_hazard (insn))
10571 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
10572 the .md file length attributes are 4-based for both modes.
10573 Adjust the MIPS16 ones here. */
10580 /* Return an asm sequence to start a noat block and load the address
10581 of a label into $1. */
10584 mips_output_load_label (void)
10586 if (TARGET_EXPLICIT_RELOCS)
10590 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10593 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10596 if (ISA_HAS_LOAD_DELAY)
10597 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10598 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10602 if (Pmode == DImode)
10603 return "%[dla\t%@,%0";
10605 return "%[la\t%@,%0";
10609 /* Return the assembly code for INSN, which has the operands given by
10610 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10611 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10612 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10613 version of BRANCH_IF_TRUE. */
10616 mips_output_conditional_branch (rtx insn, rtx *operands,
10617 const char *branch_if_true,
10618 const char *branch_if_false)
10620 unsigned int length;
10621 rtx taken, not_taken;
10623 gcc_assert (LABEL_P (operands[1]));
10625 length = get_attr_length (insn);
10628 /* Just a simple conditional branch. */
10629 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10630 return branch_if_true;
10633 /* Generate a reversed branch around a direct jump. This fallback does
10634 not use branch-likely instructions. */
10635 mips_branch_likely = false;
10636 not_taken = gen_label_rtx ();
10637 taken = operands[1];
10639 /* Generate the reversed branch to NOT_TAKEN. */
10640 operands[1] = not_taken;
10641 output_asm_insn (branch_if_false, operands);
10643 /* If INSN has a delay slot, we must provide delay slots for both the
10644 branch to NOT_TAKEN and the conditional jump. We must also ensure
10645 that INSN's delay slot is executed in the appropriate cases. */
10646 if (final_sequence)
10648 /* This first delay slot will always be executed, so use INSN's
10649 delay slot if is not annulled. */
10650 if (!INSN_ANNULLED_BRANCH_P (insn))
10652 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10653 asm_out_file, optimize, 1, NULL);
10654 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10657 output_asm_insn ("nop", 0);
10658 fprintf (asm_out_file, "\n");
10661 /* Output the unconditional branch to TAKEN. */
10663 output_asm_insn ("j\t%0%/", &taken);
10666 output_asm_insn (mips_output_load_label (), &taken);
10667 output_asm_insn ("jr\t%@%]%/", 0);
10670 /* Now deal with its delay slot; see above. */
10671 if (final_sequence)
10673 /* This delay slot will only be executed if the branch is taken.
10674 Use INSN's delay slot if is annulled. */
10675 if (INSN_ANNULLED_BRANCH_P (insn))
10677 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10678 asm_out_file, optimize, 1, NULL);
10679 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10682 output_asm_insn ("nop", 0);
10683 fprintf (asm_out_file, "\n");
10686 /* Output NOT_TAKEN. */
10687 targetm.asm_out.internal_label (asm_out_file, "L",
10688 CODE_LABEL_NUMBER (not_taken));
10692 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10693 if some ordering condition is true. The condition is given by
10694 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10695 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10696 its second is always zero. */
10699 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10701 const char *branch[2];
10703 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10704 Make BRANCH[0] branch on the inverse condition. */
10705 switch (GET_CODE (operands[0]))
10707 /* These cases are equivalent to comparisons against zero. */
10709 inverted_p = !inverted_p;
10710 /* Fall through. */
10712 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10713 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10716 /* These cases are always true or always false. */
10718 inverted_p = !inverted_p;
10719 /* Fall through. */
10721 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10722 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10726 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10727 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10730 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10733 /* Return the assembly code for __sync_*() loop LOOP. The loop should support
10734 both normal and likely branches, using %? and %~ where appropriate. */
10737 mips_output_sync_loop (const char *loop)
10739 /* Use branch-likely instructions to work around the LL/SC R10000 errata. */
10740 mips_branch_likely = TARGET_FIX_R10000;
10744 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
10745 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
10747 When working around R4000 and R4400 errata, we need to make sure that
10748 the division is not immediately followed by a shift[1][2]. We also
10749 need to stop the division from being put into a branch delay slot[3].
10750 The easiest way to avoid both problems is to add a nop after the
10751 division. When a divide-by-zero check is needed, this nop can be
10752 used to fill the branch delay slot.
10754 [1] If a double-word or a variable shift executes immediately
10755 after starting an integer division, the shift may give an
10756 incorrect result. See quotations of errata #16 and #28 from
10757 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10758 in mips.md for details.
10760 [2] A similar bug to [1] exists for all revisions of the
10761 R4000 and the R4400 when run in an MC configuration.
10762 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10764 "19. In this following sequence:
10766 ddiv (or ddivu or div or divu)
10767 dsll32 (or dsrl32, dsra32)
10769 if an MPT stall occurs, while the divide is slipping the cpu
10770 pipeline, then the following double shift would end up with an
10773 Workaround: The compiler needs to avoid generating any
10774 sequence with divide followed by extended double shift."
10776 This erratum is also present in "MIPS R4400MC Errata, Processor
10777 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10778 & 3.0" as errata #10 and #4, respectively.
10780 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10781 (also valid for MIPS R4000MC processors):
10783 "52. R4000SC: This bug does not apply for the R4000PC.
10785 There are two flavors of this bug:
10787 1) If the instruction just after divide takes an RF exception
10788 (tlb-refill, tlb-invalid) and gets an instruction cache
10789 miss (both primary and secondary) and the line which is
10790 currently in secondary cache at this index had the first
10791 data word, where the bits 5..2 are set, then R4000 would
10792 get a wrong result for the div.
10797 ------------------- # end-of page. -tlb-refill
10802 ------------------- # end-of page. -tlb-invalid
10805 2) If the divide is in the taken branch delay slot, where the
10806 target takes RF exception and gets an I-cache miss for the
10807 exception vector or where I-cache miss occurs for the
10808 target address, under the above mentioned scenarios, the
10809 div would get wrong results.
10812 j r2 # to next page mapped or unmapped
10813 div r8,r9 # this bug would be there as long
10814 # as there is an ICache miss and
10815 nop # the "data pattern" is present
10818 beq r0, r0, NextPage # to Next page
10822 This bug is present for div, divu, ddiv, and ddivu
10825 Workaround: For item 1), OS could make sure that the next page
10826 after the divide instruction is also mapped. For item 2), the
10827 compiler could make sure that the divide instruction is not in
10828 the branch delay slot."
10830 These processors have PRId values of 0x00004220 and 0x00004300 for
10831 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10834 mips_output_division (const char *division, rtx *operands)
10839 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
10841 output_asm_insn (s, operands);
10844 if (TARGET_CHECK_ZERO_DIV)
10848 output_asm_insn (s, operands);
10849 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
10851 else if (GENERATE_DIVIDE_TRAPS)
10853 output_asm_insn (s, operands);
10854 s = "teq\t%2,%.,7";
10858 output_asm_insn ("%(bne\t%2,%.,1f", operands);
10859 output_asm_insn (s, operands);
10860 s = "break\t7%)\n1:";
10866 /* Return true if IN_INSN is a multiply-add or multiply-subtract
10867 instruction and if OUT_INSN assigns to the accumulator operand. */
10870 mips_linked_madd_p (rtx out_insn, rtx in_insn)
10874 x = single_set (in_insn);
10880 if (GET_CODE (x) == PLUS
10881 && GET_CODE (XEXP (x, 0)) == MULT
10882 && reg_set_p (XEXP (x, 1), out_insn))
10885 if (GET_CODE (x) == MINUS
10886 && GET_CODE (XEXP (x, 1)) == MULT
10887 && reg_set_p (XEXP (x, 0), out_insn))
10893 /* True if the dependency between OUT_INSN and IN_INSN is on the store
10894 data rather than the address. We need this because the cprestore
10895 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
10896 which causes the default routine to abort. We just return false
10900 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10902 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10905 return !store_data_bypass_p (out_insn, in_insn);
10909 /* Variables and flags used in scheduler hooks when tuning for
10913 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
10916 /* If true, then next ALU1/2 instruction will go to ALU1. */
10919 /* If true, then next FALU1/2 unstruction will go to FALU1. */
10922 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
10923 int alu1_core_unit_code;
10924 int alu2_core_unit_code;
10925 int falu1_core_unit_code;
10926 int falu2_core_unit_code;
10928 /* True if current cycle has a multi instruction.
10929 This flag is used in mips_ls2_dfa_post_advance_cycle. */
10930 bool cycle_has_multi_p;
10932 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
10933 These are used in mips_ls2_dfa_post_advance_cycle to initialize
10935 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
10936 instruction to go ALU1. */
10937 rtx alu1_turn_enabled_insn;
10938 rtx alu2_turn_enabled_insn;
10939 rtx falu1_turn_enabled_insn;
10940 rtx falu2_turn_enabled_insn;
10943 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10944 dependencies have no cost, except on the 20Kc where output-dependence
10945 is treated like input-dependence. */
10948 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10949 rtx dep ATTRIBUTE_UNUSED, int cost)
10951 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
10954 if (REG_NOTE_KIND (link) != 0)
10959 /* Return the number of instructions that can be issued per cycle. */
10962 mips_issue_rate (void)
10966 case PROCESSOR_74KC:
10967 case PROCESSOR_74KF2_1:
10968 case PROCESSOR_74KF1_1:
10969 case PROCESSOR_74KF3_2:
10970 /* The 74k is not strictly quad-issue cpu, but can be seen as one
10971 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
10972 but in reality only a maximum of 3 insns can be issued as
10973 floating-point loads and stores also require a slot in the
10975 case PROCESSOR_R10000:
10976 /* All R10K Processors are quad-issue (being the first MIPS
10977 processors to support this feature). */
10980 case PROCESSOR_20KC:
10981 case PROCESSOR_R4130:
10982 case PROCESSOR_R5400:
10983 case PROCESSOR_R5500:
10984 case PROCESSOR_R7000:
10985 case PROCESSOR_R9000:
10986 case PROCESSOR_OCTEON:
10989 case PROCESSOR_SB1:
10990 case PROCESSOR_SB1A:
10991 /* This is actually 4, but we get better performance if we claim 3.
10992 This is partly because of unwanted speculative code motion with the
10993 larger number, and partly because in most common cases we can't
10994 reach the theoretical max of 4. */
10997 case PROCESSOR_LOONGSON_2E:
10998 case PROCESSOR_LOONGSON_2F:
11006 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11009 mips_ls2_init_dfa_post_cycle_insn (void)
11012 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11013 mips_ls2.alu1_turn_enabled_insn = get_insns ();
11017 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11018 mips_ls2.alu2_turn_enabled_insn = get_insns ();
11022 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11023 mips_ls2.falu1_turn_enabled_insn = get_insns ();
11027 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11028 mips_ls2.falu2_turn_enabled_insn = get_insns ();
11031 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
11032 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
11033 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
11034 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
11037 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11038 Init data used in mips_dfa_post_advance_cycle. */
11041 mips_init_dfa_post_cycle_insn (void)
11043 if (TUNE_LOONGSON_2EF)
11044 mips_ls2_init_dfa_post_cycle_insn ();
11047 /* Initialize STATE when scheduling for Loongson 2E/2F.
11048 Support round-robin dispatch scheme by enabling only one of
11049 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
11053 mips_ls2_dfa_post_advance_cycle (state_t state)
11055 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
11057 /* Though there are no non-pipelined ALU1 insns,
11058 we can get an instruction of type 'multi' before reload. */
11059 gcc_assert (mips_ls2.cycle_has_multi_p);
11060 mips_ls2.alu1_turn_p = false;
11063 mips_ls2.cycle_has_multi_p = false;
11065 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
11066 /* We have a non-pipelined alu instruction in the core,
11067 adjust round-robin counter. */
11068 mips_ls2.alu1_turn_p = true;
11070 if (mips_ls2.alu1_turn_p)
11072 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
11073 gcc_unreachable ();
11077 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
11078 gcc_unreachable ();
11081 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
11083 /* There are no non-pipelined FALU1 insns. */
11084 gcc_unreachable ();
11085 mips_ls2.falu1_turn_p = false;
11088 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
11089 /* We have a non-pipelined falu instruction in the core,
11090 adjust round-robin counter. */
11091 mips_ls2.falu1_turn_p = true;
11093 if (mips_ls2.falu1_turn_p)
11095 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
11096 gcc_unreachable ();
11100 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
11101 gcc_unreachable ();
11105 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
11106 This hook is being called at the start of each cycle. */
11109 mips_dfa_post_advance_cycle (void)
11111 if (TUNE_LOONGSON_2EF)
11112 mips_ls2_dfa_post_advance_cycle (curr_state);
11115 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
11116 be as wide as the scheduling freedom in the DFA. */
11119 mips_multipass_dfa_lookahead (void)
11121 /* Can schedule up to 4 of the 6 function units in any one cycle. */
11125 if (TUNE_LOONGSON_2EF)
11134 /* Remove the instruction at index LOWER from ready queue READY and
11135 reinsert it in front of the instruction at index HIGHER. LOWER must
11139 mips_promote_ready (rtx *ready, int lower, int higher)
11144 new_head = ready[lower];
11145 for (i = lower; i < higher; i++)
11146 ready[i] = ready[i + 1];
11147 ready[i] = new_head;
11150 /* If the priority of the instruction at POS2 in the ready queue READY
11151 is within LIMIT units of that of the instruction at POS1, swap the
11152 instructions if POS2 is not already less than POS1. */
11155 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
11158 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
11162 temp = ready[pos1];
11163 ready[pos1] = ready[pos2];
11164 ready[pos2] = temp;
11168 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
11169 that may clobber hi or lo. */
11170 static rtx mips_macc_chains_last_hilo;
11172 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
11173 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
11176 mips_macc_chains_record (rtx insn)
11178 if (get_attr_may_clobber_hilo (insn))
11179 mips_macc_chains_last_hilo = insn;
11182 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
11183 has NREADY elements, looking for a multiply-add or multiply-subtract
11184 instruction that is cumulative with mips_macc_chains_last_hilo.
11185 If there is one, promote it ahead of anything else that might
11186 clobber hi or lo. */
11189 mips_macc_chains_reorder (rtx *ready, int nready)
11193 if (mips_macc_chains_last_hilo != 0)
11194 for (i = nready - 1; i >= 0; i--)
11195 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
11197 for (j = nready - 1; j > i; j--)
11198 if (recog_memoized (ready[j]) >= 0
11199 && get_attr_may_clobber_hilo (ready[j]))
11201 mips_promote_ready (ready, i, j);
11208 /* The last instruction to be scheduled. */
11209 static rtx vr4130_last_insn;
11211 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
11212 points to an rtx that is initially an instruction. Nullify the rtx
11213 if the instruction uses the value of register X. */
11216 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
11221 insn_ptr = (rtx *) data;
11224 && reg_referenced_p (x, PATTERN (*insn_ptr)))
11228 /* Return true if there is true register dependence between vr4130_last_insn
11232 vr4130_true_reg_dependence_p (rtx insn)
11234 note_stores (PATTERN (vr4130_last_insn),
11235 vr4130_true_reg_dependence_p_1, &insn);
11239 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
11240 the ready queue and that INSN2 is the instruction after it, return
11241 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
11242 in which INSN1 and INSN2 can probably issue in parallel, but for
11243 which (INSN2, INSN1) should be less sensitive to instruction
11244 alignment than (INSN1, INSN2). See 4130.md for more details. */
11247 vr4130_swap_insns_p (rtx insn1, rtx insn2)
11249 sd_iterator_def sd_it;
11252 /* Check for the following case:
11254 1) there is some other instruction X with an anti dependence on INSN1;
11255 2) X has a higher priority than INSN2; and
11256 3) X is an arithmetic instruction (and thus has no unit restrictions).
11258 If INSN1 is the last instruction blocking X, it would better to
11259 choose (INSN1, X) over (INSN2, INSN1). */
11260 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
11261 if (DEP_TYPE (dep) == REG_DEP_ANTI
11262 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
11263 && recog_memoized (DEP_CON (dep)) >= 0
11264 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
11267 if (vr4130_last_insn != 0
11268 && recog_memoized (insn1) >= 0
11269 && recog_memoized (insn2) >= 0)
11271 /* See whether INSN1 and INSN2 use different execution units,
11272 or if they are both ALU-type instructions. If so, they can
11273 probably execute in parallel. */
11274 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
11275 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
11276 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
11278 /* If only one of the instructions has a dependence on
11279 vr4130_last_insn, prefer to schedule the other one first. */
11280 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
11281 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
11282 if (dep1_p != dep2_p)
11285 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
11286 is not an ALU-type instruction and if INSN1 uses the same
11287 execution unit. (Note that if this condition holds, we already
11288 know that INSN2 uses a different execution unit.) */
11289 if (class1 != VR4130_CLASS_ALU
11290 && recog_memoized (vr4130_last_insn) >= 0
11291 && class1 == get_attr_vr4130_class (vr4130_last_insn))
11298 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
11299 queue with at least two instructions. Swap the first two if
11300 vr4130_swap_insns_p says that it could be worthwhile. */
11303 vr4130_reorder (rtx *ready, int nready)
11305 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
11306 mips_promote_ready (ready, nready - 2, nready - 1);
11309 /* Record whether last 74k AGEN instruction was a load or store. */
11310 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
11312 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
11313 resets to TYPE_UNKNOWN state. */
11316 mips_74k_agen_init (rtx insn)
11318 if (!insn || !NONJUMP_INSN_P (insn))
11319 mips_last_74k_agen_insn = TYPE_UNKNOWN;
11322 enum attr_type type = get_attr_type (insn);
11323 if (type == TYPE_LOAD || type == TYPE_STORE)
11324 mips_last_74k_agen_insn = type;
11328 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
11329 loads to be grouped together, and multiple stores to be grouped
11330 together. Swap things around in the ready queue to make this happen. */
11333 mips_74k_agen_reorder (rtx *ready, int nready)
11336 int store_pos, load_pos;
11341 for (i = nready - 1; i >= 0; i--)
11343 rtx insn = ready[i];
11344 if (USEFUL_INSN_P (insn))
11345 switch (get_attr_type (insn))
11348 if (store_pos == -1)
11353 if (load_pos == -1)
11362 if (load_pos == -1 || store_pos == -1)
11365 switch (mips_last_74k_agen_insn)
11368 /* Prefer to schedule loads since they have a higher latency. */
11370 /* Swap loads to the front of the queue. */
11371 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
11374 /* Swap stores to the front of the queue. */
11375 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
11382 /* Implement TARGET_SCHED_INIT. */
11385 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11386 int max_ready ATTRIBUTE_UNUSED)
11388 mips_macc_chains_last_hilo = 0;
11389 vr4130_last_insn = 0;
11390 mips_74k_agen_init (NULL_RTX);
11392 /* When scheduling for Loongson2, branch instructions go to ALU1,
11393 therefore basic block is most likely to start with round-robin counter
11394 pointed to ALU2. */
11395 mips_ls2.alu1_turn_p = false;
11396 mips_ls2.falu1_turn_p = true;
11399 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
11402 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11403 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
11405 if (!reload_completed
11406 && TUNE_MACC_CHAINS
11408 mips_macc_chains_reorder (ready, *nreadyp);
11410 if (reload_completed
11412 && !TARGET_VR4130_ALIGN
11414 vr4130_reorder (ready, *nreadyp);
11417 mips_74k_agen_reorder (ready, *nreadyp);
11419 return mips_issue_rate ();
11422 /* Update round-robin counters for ALU1/2 and FALU1/2. */
11425 mips_ls2_variable_issue (rtx insn)
11427 if (mips_ls2.alu1_turn_p)
11429 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
11430 mips_ls2.alu1_turn_p = false;
11434 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
11435 mips_ls2.alu1_turn_p = true;
11438 if (mips_ls2.falu1_turn_p)
11440 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
11441 mips_ls2.falu1_turn_p = false;
11445 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
11446 mips_ls2.falu1_turn_p = true;
11449 if (recog_memoized (insn) >= 0)
11450 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
11453 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
11456 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11457 rtx insn, int more)
11459 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
11460 if (USEFUL_INSN_P (insn))
11463 if (!reload_completed && TUNE_MACC_CHAINS)
11464 mips_macc_chains_record (insn);
11465 vr4130_last_insn = insn;
11467 mips_74k_agen_init (insn);
11468 else if (TUNE_LOONGSON_2EF)
11469 mips_ls2_variable_issue (insn);
11472 /* Instructions of type 'multi' should all be split before
11473 the second scheduling pass. */
11474 gcc_assert (!reload_completed
11475 || recog_memoized (insn) < 0
11476 || get_attr_type (insn) != TYPE_MULTI);
11481 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
11482 return the first operand of the associated PREF or PREFX insn. */
11485 mips_prefetch_cookie (rtx write, rtx locality)
11487 /* store_streamed / load_streamed. */
11488 if (INTVAL (locality) <= 0)
11489 return GEN_INT (INTVAL (write) + 4);
11491 /* store / load. */
11492 if (INTVAL (locality) <= 2)
11495 /* store_retained / load_retained. */
11496 return GEN_INT (INTVAL (write) + 6);
11499 /* Flags that indicate when a built-in function is available.
11501 BUILTIN_AVAIL_NON_MIPS16
11502 The function is available on the current target, but only
11503 in non-MIPS16 mode. */
11504 #define BUILTIN_AVAIL_NON_MIPS16 1
11506 /* Declare an availability predicate for built-in functions that
11507 require non-MIPS16 mode and also require COND to be true.
11508 NAME is the main part of the predicate's name. */
11509 #define AVAIL_NON_MIPS16(NAME, COND) \
11510 static unsigned int \
11511 mips_builtin_avail_##NAME (void) \
11513 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
11516 /* This structure describes a single built-in function. */
11517 struct mips_builtin_description {
11518 /* The code of the main .md file instruction. See mips_builtin_type
11519 for more information. */
11520 enum insn_code icode;
11522 /* The floating-point comparison code to use with ICODE, if any. */
11523 enum mips_fp_condition cond;
11525 /* The name of the built-in function. */
11528 /* Specifies how the function should be expanded. */
11529 enum mips_builtin_type builtin_type;
11531 /* The function's prototype. */
11532 enum mips_function_type function_type;
11534 /* Whether the function is available. */
11535 unsigned int (*avail) (void);
11538 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
11539 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
11540 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
11541 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
11542 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
11543 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
11544 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
11545 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
11546 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
11548 /* Construct a mips_builtin_description from the given arguments.
11550 INSN is the name of the associated instruction pattern, without the
11551 leading CODE_FOR_mips_.
11553 CODE is the floating-point condition code associated with the
11554 function. It can be 'f' if the field is not applicable.
11556 NAME is the name of the function itself, without the leading
11559 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
11561 AVAIL is the name of the availability predicate, without the leading
11562 mips_builtin_avail_. */
11563 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
11564 FUNCTION_TYPE, AVAIL) \
11565 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
11566 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
11567 mips_builtin_avail_ ## AVAIL }
11569 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
11570 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
11571 are as for MIPS_BUILTIN. */
11572 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11573 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
11575 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
11576 are subject to mips_builtin_avail_<AVAIL>. */
11577 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
11578 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
11579 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
11580 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
11581 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
11583 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
11584 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
11585 while the any and all forms are subject to mips_builtin_avail_mips3d. */
11586 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
11587 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
11588 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
11590 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
11591 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
11593 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
11594 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
11596 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
11597 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
11600 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
11601 are subject to mips_builtin_avail_mips3d. */
11602 #define CMP_4S_BUILTINS(INSN, COND) \
11603 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
11604 MIPS_BUILTIN_CMP_ANY, \
11605 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
11606 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
11607 MIPS_BUILTIN_CMP_ALL, \
11608 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
11610 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11611 instruction requires mips_builtin_avail_<AVAIL>. */
11612 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
11613 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
11614 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11616 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
11617 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11620 /* Define all the built-in functions related to C.cond.fmt condition COND. */
11621 #define CMP_BUILTINS(COND) \
11622 MOVTF_BUILTINS (c, COND, paired_single), \
11623 MOVTF_BUILTINS (cabs, COND, mips3d), \
11624 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
11625 CMP_PS_BUILTINS (c, COND, paired_single), \
11626 CMP_PS_BUILTINS (cabs, COND, mips3d), \
11627 CMP_4S_BUILTINS (c, COND), \
11628 CMP_4S_BUILTINS (cabs, COND)
11630 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
11631 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
11632 and AVAIL are as for MIPS_BUILTIN. */
11633 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11634 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
11635 FUNCTION_TYPE, AVAIL)
11637 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11638 branch instruction. AVAIL is as for MIPS_BUILTIN. */
11639 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
11640 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
11641 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
11643 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
11644 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11645 builtin_description field. */
11646 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
11647 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
11648 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
11649 FUNCTION_TYPE, mips_builtin_avail_loongson }
11651 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
11652 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11653 builtin_description field. */
11654 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
11655 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
11657 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
11658 We use functions of this form when the same insn can be usefully applied
11659 to more than one datatype. */
11660 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
11661 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
11663 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11664 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11665 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11666 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11667 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11668 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11670 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
11671 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
11672 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
11673 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
11674 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
11675 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
11676 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
11677 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
11678 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
11679 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
11680 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
11681 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
11682 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
11683 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
11684 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
11685 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
11686 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
11687 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
11688 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
11689 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
11690 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
11691 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
11692 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
11693 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
11694 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
11695 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
11696 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
11697 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
11698 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
11700 static const struct mips_builtin_description mips_builtins[] = {
11701 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11702 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11703 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11704 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11705 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
11706 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
11707 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
11708 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
11710 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
11711 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11712 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11713 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11714 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
11716 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
11717 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
11718 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11719 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
11720 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
11721 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11723 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
11724 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
11725 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11726 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
11727 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
11728 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11730 MIPS_FP_CONDITIONS (CMP_BUILTINS),
11732 /* Built-in functions for the SB-1 processor. */
11733 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
11735 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
11736 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11737 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11738 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11739 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11740 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11741 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11742 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11743 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11744 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11745 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11746 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
11747 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
11748 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
11749 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
11750 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
11751 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
11752 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
11753 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
11754 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
11755 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
11756 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
11757 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
11758 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
11759 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
11760 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
11761 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
11762 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
11763 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
11764 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
11765 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
11766 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
11767 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11768 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11769 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11770 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
11771 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11772 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11773 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
11774 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
11775 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
11776 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11777 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
11778 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
11779 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
11780 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
11781 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
11782 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
11783 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11784 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11785 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11786 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11787 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11788 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11789 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11790 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11791 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11792 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11793 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11794 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11795 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
11796 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
11797 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
11798 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
11799 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
11800 BPOSGE_BUILTIN (32, dsp),
11802 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
11803 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
11804 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11805 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11806 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11807 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11808 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11809 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11810 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11811 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11812 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11813 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11814 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11815 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11816 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11817 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11818 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
11819 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
11820 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
11821 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11822 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
11823 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
11824 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
11825 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11826 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11827 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11828 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11829 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11830 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11831 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11832 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11833 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11834 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11835 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11836 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11838 /* Built-in functions for the DSP ASE (32-bit only). */
11839 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11840 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11841 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11842 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11843 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11844 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11845 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11846 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
11847 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
11848 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11849 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11850 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11851 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11852 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11853 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11854 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11855 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
11856 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
11857 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
11858 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
11859 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
11861 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
11862 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11863 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11864 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
11865 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
11866 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
11867 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
11868 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11869 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
11870 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
11871 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11872 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11873 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11874 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11875 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11876 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11878 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
11879 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
11880 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
11881 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
11882 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11883 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11884 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11885 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11886 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11887 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11888 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
11889 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
11890 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11891 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11892 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11893 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11894 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
11895 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11896 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11897 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11898 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
11899 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
11900 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11901 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11902 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11903 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11904 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11905 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11906 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11907 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11908 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11909 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11910 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11911 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11912 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11913 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11914 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11915 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11916 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
11917 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
11918 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11919 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11920 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11921 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11922 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11923 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11924 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11925 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11926 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
11927 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11928 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11929 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11930 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11931 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
11932 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
11933 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11934 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11935 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11936 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
11937 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11938 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
11939 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
11940 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
11941 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
11942 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11943 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11944 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11945 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11946 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11947 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11948 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11949 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11950 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11951 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11952 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11953 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11954 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11955 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11956 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11957 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11958 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11959 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11960 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
11961 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
11962 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11963 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11964 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11965 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11966 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11967 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11968 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11969 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11970 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11971 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11972 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11973 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11974 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11975 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11976 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11977 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11979 /* Sundry other built-in functions. */
11980 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
11983 /* MODE is a vector mode whose elements have type TYPE. Return the type
11984 of the vector itself. */
11987 mips_builtin_vector_type (tree type, enum machine_mode mode)
11989 static tree types[2 * (int) MAX_MACHINE_MODE];
11992 mode_index = (int) mode;
11994 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
11995 mode_index += MAX_MACHINE_MODE;
11997 if (types[mode_index] == NULL_TREE)
11998 types[mode_index] = build_vector_type_for_mode (type, mode);
11999 return types[mode_index];
12002 /* Return a type for 'const volatile void *'. */
12005 mips_build_cvpointer_type (void)
12009 if (cache == NULL_TREE)
12010 cache = build_pointer_type (build_qualified_type
12012 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
12016 /* Source-level argument types. */
12017 #define MIPS_ATYPE_VOID void_type_node
12018 #define MIPS_ATYPE_INT integer_type_node
12019 #define MIPS_ATYPE_POINTER ptr_type_node
12020 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12022 /* Standard mode-based argument types. */
12023 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12024 #define MIPS_ATYPE_SI intSI_type_node
12025 #define MIPS_ATYPE_USI unsigned_intSI_type_node
12026 #define MIPS_ATYPE_DI intDI_type_node
12027 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
12028 #define MIPS_ATYPE_SF float_type_node
12029 #define MIPS_ATYPE_DF double_type_node
12031 /* Vector argument types. */
12032 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
12033 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
12034 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
12035 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
12036 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
12037 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
12038 #define MIPS_ATYPE_UV2SI \
12039 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
12040 #define MIPS_ATYPE_UV4HI \
12041 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
12042 #define MIPS_ATYPE_UV8QI \
12043 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
12045 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
12046 their associated MIPS_ATYPEs. */
12047 #define MIPS_FTYPE_ATYPES1(A, B) \
12048 MIPS_ATYPE_##A, MIPS_ATYPE_##B
12050 #define MIPS_FTYPE_ATYPES2(A, B, C) \
12051 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
12053 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
12054 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
12056 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
12057 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
12060 /* Return the function type associated with function prototype TYPE. */
12063 mips_build_function_type (enum mips_function_type type)
12065 static tree types[(int) MIPS_MAX_FTYPE_MAX];
12067 if (types[(int) type] == NULL_TREE)
12070 #define DEF_MIPS_FTYPE(NUM, ARGS) \
12071 case MIPS_FTYPE_NAME##NUM ARGS: \
12072 types[(int) type] \
12073 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
12076 #include "config/mips/mips-ftypes.def"
12077 #undef DEF_MIPS_FTYPE
12079 gcc_unreachable ();
12082 return types[(int) type];
12085 /* Implement TARGET_INIT_BUILTINS. */
12088 mips_init_builtins (void)
12090 const struct mips_builtin_description *d;
12093 /* Iterate through all of the bdesc arrays, initializing all of the
12094 builtin functions. */
12095 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
12097 d = &mips_builtins[i];
12099 add_builtin_function (d->name,
12100 mips_build_function_type (d->function_type),
12101 i, BUILT_IN_MD, NULL, NULL);
12105 /* Take argument ARGNO from EXP's argument list and convert it into a
12106 form suitable for input operand OPNO of instruction ICODE. Return the
12110 mips_prepare_builtin_arg (enum insn_code icode,
12111 unsigned int opno, tree exp, unsigned int argno)
12115 enum machine_mode mode;
12117 arg = CALL_EXPR_ARG (exp, argno);
12118 value = expand_normal (arg);
12119 mode = insn_data[icode].operand[opno].mode;
12120 if (!insn_data[icode].operand[opno].predicate (value, mode))
12122 /* We need to get the mode from ARG for two reasons:
12124 - to cope with address operands, where MODE is the mode of the
12125 memory, rather than of VALUE itself.
12127 - to cope with special predicates like pmode_register_operand,
12128 where MODE is VOIDmode. */
12129 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
12131 /* Check the predicate again. */
12132 if (!insn_data[icode].operand[opno].predicate (value, mode))
12134 error ("invalid argument to built-in function");
12142 /* Return an rtx suitable for output operand OP of instruction ICODE.
12143 If TARGET is non-null, try to use it where possible. */
12146 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
12148 enum machine_mode mode;
12150 mode = insn_data[icode].operand[op].mode;
12151 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
12152 target = gen_reg_rtx (mode);
12157 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
12158 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
12159 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
12160 suggests a good place to put the result. */
12163 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
12166 rtx ops[MAX_RECOG_OPERANDS];
12169 /* Map any target to operand 0. */
12173 target = mips_prepare_builtin_target (icode, opno, target);
12174 ops[opno] = target;
12178 /* Map the arguments to the other operands. The n_operands value
12179 for an expander includes match_dups and match_scratches as well as
12180 match_operands, so n_operands is only an upper bound on the number
12181 of arguments to the expander function. */
12182 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
12183 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
12184 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
12189 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
12193 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
12197 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
12201 gcc_unreachable ();
12206 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
12207 function; TYPE says which. EXP is the CALL_EXPR that calls the
12208 function, ICODE is the instruction that should be used to compare
12209 the first two arguments, and COND is the condition it should test.
12210 TARGET, if nonnull, suggests a good place to put the result. */
12213 mips_expand_builtin_movtf (enum mips_builtin_type type,
12214 enum insn_code icode, enum mips_fp_condition cond,
12215 rtx target, tree exp)
12217 rtx cmp_result, op0, op1;
12219 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
12220 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
12221 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
12222 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
12224 icode = CODE_FOR_mips_cond_move_tf_ps;
12225 target = mips_prepare_builtin_target (icode, 0, target);
12226 if (type == MIPS_BUILTIN_MOVT)
12228 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
12229 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
12233 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
12234 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
12236 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
12240 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
12241 into TARGET otherwise. Return TARGET. */
12244 mips_builtin_branch_and_move (rtx condition, rtx target,
12245 rtx value_if_true, rtx value_if_false)
12247 rtx true_label, done_label;
12249 true_label = gen_label_rtx ();
12250 done_label = gen_label_rtx ();
12252 /* First assume that CONDITION is false. */
12253 mips_emit_move (target, value_if_false);
12255 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
12256 emit_jump_insn (gen_condjump (condition, true_label));
12257 emit_jump_insn (gen_jump (done_label));
12260 /* Fix TARGET if CONDITION is true. */
12261 emit_label (true_label);
12262 mips_emit_move (target, value_if_true);
12264 emit_label (done_label);
12268 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
12269 the CALL_EXPR that calls the function, ICODE is the code of the
12270 comparison instruction, and COND is the condition it should test.
12271 TARGET, if nonnull, suggests a good place to put the boolean result. */
12274 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
12275 enum insn_code icode, enum mips_fp_condition cond,
12276 rtx target, tree exp)
12278 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
12281 if (target == 0 || GET_MODE (target) != SImode)
12282 target = gen_reg_rtx (SImode);
12284 /* The instruction should have a target operand, an operand for each
12285 argument, and an operand for COND. */
12286 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
12288 /* Prepare the operands to the comparison. */
12289 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
12290 for (argno = 0; argno < call_expr_nargs (exp); argno++)
12291 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
12293 switch (insn_data[icode].n_operands)
12296 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
12301 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
12302 args[2], args[3], GEN_INT (cond)));
12306 gcc_unreachable ();
12309 /* If the comparison sets more than one register, we define the result
12310 to be 0 if all registers are false and -1 if all registers are true.
12311 The value of the complete result is indeterminate otherwise. */
12312 switch (builtin_type)
12314 case MIPS_BUILTIN_CMP_ALL:
12315 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
12316 return mips_builtin_branch_and_move (condition, target,
12317 const0_rtx, const1_rtx);
12319 case MIPS_BUILTIN_CMP_UPPER:
12320 case MIPS_BUILTIN_CMP_LOWER:
12321 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
12322 condition = gen_single_cc (cmp_result, offset);
12323 return mips_builtin_branch_and_move (condition, target,
12324 const1_rtx, const0_rtx);
12327 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
12328 return mips_builtin_branch_and_move (condition, target,
12329 const1_rtx, const0_rtx);
12333 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
12334 if nonnull, suggests a good place to put the boolean result. */
12337 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
12339 rtx condition, cmp_result;
12342 if (target == 0 || GET_MODE (target) != SImode)
12343 target = gen_reg_rtx (SImode);
12345 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
12347 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
12352 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
12353 return mips_builtin_branch_and_move (condition, target,
12354 const1_rtx, const0_rtx);
12357 /* Implement TARGET_EXPAND_BUILTIN. */
12360 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
12361 enum machine_mode mode, int ignore)
12364 unsigned int fcode, avail;
12365 const struct mips_builtin_description *d;
12367 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12368 fcode = DECL_FUNCTION_CODE (fndecl);
12369 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
12370 d = &mips_builtins[fcode];
12371 avail = d->avail ();
12372 gcc_assert (avail != 0);
12375 error ("built-in function %qs not supported for MIPS16",
12376 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
12377 return ignore ? const0_rtx : CONST0_RTX (mode);
12379 switch (d->builtin_type)
12381 case MIPS_BUILTIN_DIRECT:
12382 return mips_expand_builtin_direct (d->icode, target, exp, true);
12384 case MIPS_BUILTIN_DIRECT_NO_TARGET:
12385 return mips_expand_builtin_direct (d->icode, target, exp, false);
12387 case MIPS_BUILTIN_MOVT:
12388 case MIPS_BUILTIN_MOVF:
12389 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
12390 d->cond, target, exp);
12392 case MIPS_BUILTIN_CMP_ANY:
12393 case MIPS_BUILTIN_CMP_ALL:
12394 case MIPS_BUILTIN_CMP_UPPER:
12395 case MIPS_BUILTIN_CMP_LOWER:
12396 case MIPS_BUILTIN_CMP_SINGLE:
12397 return mips_expand_builtin_compare (d->builtin_type, d->icode,
12398 d->cond, target, exp);
12400 case MIPS_BUILTIN_BPOSGE32:
12401 return mips_expand_builtin_bposge (d->builtin_type, target);
12403 gcc_unreachable ();
12406 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
12407 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
12408 struct mips16_constant {
12409 struct mips16_constant *next;
12412 enum machine_mode mode;
12415 /* Information about an incomplete MIPS16 constant pool. FIRST is the
12416 first constant, HIGHEST_ADDRESS is the highest address that the first
12417 byte of the pool can have, and INSN_ADDRESS is the current instruction
12419 struct mips16_constant_pool {
12420 struct mips16_constant *first;
12421 int highest_address;
12425 /* Add constant VALUE to POOL and return its label. MODE is the
12426 value's mode (used for CONST_INTs, etc.). */
12429 mips16_add_constant (struct mips16_constant_pool *pool,
12430 rtx value, enum machine_mode mode)
12432 struct mips16_constant **p, *c;
12433 bool first_of_size_p;
12435 /* See whether the constant is already in the pool. If so, return the
12436 existing label, otherwise leave P pointing to the place where the
12437 constant should be added.
12439 Keep the pool sorted in increasing order of mode size so that we can
12440 reduce the number of alignments needed. */
12441 first_of_size_p = true;
12442 for (p = &pool->first; *p != 0; p = &(*p)->next)
12444 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
12445 return (*p)->label;
12446 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
12448 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
12449 first_of_size_p = false;
12452 /* In the worst case, the constant needed by the earliest instruction
12453 will end up at the end of the pool. The entire pool must then be
12454 accessible from that instruction.
12456 When adding the first constant, set the pool's highest address to
12457 the address of the first out-of-range byte. Adjust this address
12458 downwards each time a new constant is added. */
12459 if (pool->first == 0)
12460 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
12461 of the instruction with the lowest two bits clear. The base PC
12462 value for LDPC has the lowest three bits clear. Assume the worst
12463 case here; namely that the PC-relative instruction occupies the
12464 last 2 bytes in an aligned word. */
12465 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
12466 pool->highest_address -= GET_MODE_SIZE (mode);
12467 if (first_of_size_p)
12468 /* Take into account the worst possible padding due to alignment. */
12469 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
12471 /* Create a new entry. */
12472 c = XNEW (struct mips16_constant);
12475 c->label = gen_label_rtx ();
12482 /* Output constant VALUE after instruction INSN and return the last
12483 instruction emitted. MODE is the mode of the constant. */
12486 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
12488 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
12490 rtx size = GEN_INT (GET_MODE_SIZE (mode));
12491 return emit_insn_after (gen_consttable_int (value, size), insn);
12494 if (SCALAR_FLOAT_MODE_P (mode))
12495 return emit_insn_after (gen_consttable_float (value), insn);
12497 if (VECTOR_MODE_P (mode))
12501 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
12502 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
12503 CONST_VECTOR_ELT (value, i), insn);
12507 gcc_unreachable ();
12510 /* Dump out the constants in CONSTANTS after INSN. */
12513 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
12515 struct mips16_constant *c, *next;
12519 for (c = constants; c != NULL; c = next)
12521 /* If necessary, increase the alignment of PC. */
12522 if (align < GET_MODE_SIZE (c->mode))
12524 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
12525 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
12527 align = GET_MODE_SIZE (c->mode);
12529 insn = emit_label_after (c->label, insn);
12530 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
12536 emit_barrier_after (insn);
12539 /* Return the length of instruction INSN. */
12542 mips16_insn_length (rtx insn)
12546 rtx body = PATTERN (insn);
12547 if (GET_CODE (body) == ADDR_VEC)
12548 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
12549 if (GET_CODE (body) == ADDR_DIFF_VEC)
12550 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
12552 return get_attr_length (insn);
12555 /* If *X is a symbolic constant that refers to the constant pool, add
12556 the constant to POOL and rewrite *X to use the constant's label. */
12559 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
12561 rtx base, offset, label;
12563 split_const (*x, &base, &offset);
12564 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
12566 label = mips16_add_constant (pool, get_pool_constant (base),
12567 get_pool_mode (base));
12568 base = gen_rtx_LABEL_REF (Pmode, label);
12569 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
12573 /* This structure is used to communicate with mips16_rewrite_pool_refs.
12574 INSN is the instruction we're rewriting and POOL points to the current
12576 struct mips16_rewrite_pool_refs_info {
12578 struct mips16_constant_pool *pool;
12581 /* Rewrite *X so that constant pool references refer to the constant's
12582 label instead. DATA points to a mips16_rewrite_pool_refs_info
12586 mips16_rewrite_pool_refs (rtx *x, void *data)
12588 struct mips16_rewrite_pool_refs_info *info =
12589 (struct mips16_rewrite_pool_refs_info *) data;
12591 if (force_to_mem_operand (*x, Pmode))
12593 rtx mem = force_const_mem (GET_MODE (*x), *x);
12594 validate_change (info->insn, x, mem, false);
12599 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
12603 if (TARGET_MIPS16_TEXT_LOADS)
12604 mips16_rewrite_pool_constant (info->pool, x);
12606 return GET_CODE (*x) == CONST ? -1 : 0;
12609 /* Build MIPS16 constant pools. */
12612 mips16_lay_out_constants (void)
12614 struct mips16_constant_pool pool;
12615 struct mips16_rewrite_pool_refs_info info;
12618 if (!TARGET_MIPS16_PCREL_LOADS)
12621 split_all_insns_noflow ();
12623 memset (&pool, 0, sizeof (pool));
12624 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12626 /* Rewrite constant pool references in INSN. */
12631 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
12634 pool.insn_address += mips16_insn_length (insn);
12636 if (pool.first != NULL)
12638 /* If there are no natural barriers between the first user of
12639 the pool and the highest acceptable address, we'll need to
12640 create a new instruction to jump around the constant pool.
12641 In the worst case, this instruction will be 4 bytes long.
12643 If it's too late to do this transformation after INSN,
12644 do it immediately before INSN. */
12645 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
12649 label = gen_label_rtx ();
12651 jump = emit_jump_insn_before (gen_jump (label), insn);
12652 JUMP_LABEL (jump) = label;
12653 LABEL_NUSES (label) = 1;
12654 barrier = emit_barrier_after (jump);
12656 emit_label_after (label, barrier);
12657 pool.insn_address += 4;
12660 /* See whether the constant pool is now out of range of the first
12661 user. If so, output the constants after the previous barrier.
12662 Note that any instructions between BARRIER and INSN (inclusive)
12663 will use negative offsets to refer to the pool. */
12664 if (pool.insn_address > pool.highest_address)
12666 mips16_emit_constants (pool.first, barrier);
12670 else if (BARRIER_P (insn))
12674 mips16_emit_constants (pool.first, get_last_insn ());
12677 /* Return true if it is worth r10k_simplify_address's while replacing
12678 an address with X. We are looking for constants, and for addresses
12679 at a known offset from the incoming stack pointer. */
12682 r10k_simplified_address_p (rtx x)
12684 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
12686 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
12689 /* X is an expression that appears in INSN. Try to use the UD chains
12690 to simplify it, returning the simplified form on success and the
12691 original form otherwise. Replace the incoming value of $sp with
12692 virtual_incoming_args_rtx (which should never occur in X otherwise). */
12695 r10k_simplify_address (rtx x, rtx insn)
12697 rtx newx, op0, op1, set, def_insn, note;
12699 struct df_link *defs;
12704 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12705 if (op0 != XEXP (x, 0))
12706 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
12707 op0, GET_MODE (XEXP (x, 0)));
12709 else if (BINARY_P (x))
12711 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12712 op1 = r10k_simplify_address (XEXP (x, 1), insn);
12713 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
12714 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
12716 else if (GET_CODE (x) == LO_SUM)
12718 /* LO_SUMs can be offset from HIGHs, if we know they won't
12719 overflow. See mips_classify_address for the rationale behind
12721 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12722 if (GET_CODE (op0) == HIGH)
12723 newx = XEXP (x, 1);
12725 else if (REG_P (x))
12727 /* Uses are recorded by regno_reg_rtx, not X itself. */
12728 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
12730 defs = DF_REF_CHAIN (use);
12732 /* Require a single definition. */
12733 if (defs && defs->next == NULL)
12736 if (DF_REF_IS_ARTIFICIAL (def))
12738 /* Replace the incoming value of $sp with
12739 virtual_incoming_args_rtx. */
12740 if (x == stack_pointer_rtx
12741 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
12742 newx = virtual_incoming_args_rtx;
12744 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
12747 /* Make sure that DEF_INSN is a single set of REG. */
12748 def_insn = DF_REF_INSN (def);
12749 if (NONJUMP_INSN_P (def_insn))
12751 set = single_set (def_insn);
12752 if (set && rtx_equal_p (SET_DEST (set), x))
12754 /* Prefer to use notes, since the def-use chains
12755 are often shorter. */
12756 note = find_reg_equal_equiv_note (def_insn);
12758 newx = XEXP (note, 0);
12760 newx = SET_SRC (set);
12761 newx = r10k_simplify_address (newx, def_insn);
12767 if (newx && r10k_simplified_address_p (newx))
12772 /* Return true if ADDRESS is known to be an uncached address
12773 on R10K systems. */
12776 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
12778 unsigned HOST_WIDE_INT upper;
12780 /* Check for KSEG1. */
12781 if (address + 0x60000000 < 0x20000000)
12784 /* Check for uncached XKPHYS addresses. */
12785 if (Pmode == DImode)
12787 upper = (address >> 40) & 0xf9ffff;
12788 if (upper == 0x900000 || upper == 0xb80000)
12794 /* Return true if we can prove that an access to address X in instruction
12795 INSN would be safe from R10K speculation. This X is a general
12796 expression; it might not be a legitimate address. */
12799 r10k_safe_address_p (rtx x, rtx insn)
12802 HOST_WIDE_INT offset_val;
12804 x = r10k_simplify_address (x, insn);
12806 /* Check for references to the stack frame. It doesn't really matter
12807 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
12808 allows us to assume that accesses to any part of the eventual frame
12809 is safe from speculation at any point in the function. */
12810 mips_split_plus (x, &base, &offset_val);
12811 if (base == virtual_incoming_args_rtx
12812 && offset_val >= -cfun->machine->frame.total_size
12813 && offset_val < cfun->machine->frame.args_size)
12816 /* Check for uncached addresses. */
12817 if (CONST_INT_P (x))
12818 return r10k_uncached_address_p (INTVAL (x));
12820 /* Check for accesses to a static object. */
12821 split_const (x, &base, &offset);
12822 return offset_within_block_p (base, INTVAL (offset));
12825 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
12826 an in-range access to an automatic variable, or to an object with
12827 a link-time-constant address. */
12830 r10k_safe_mem_expr_p (tree expr, rtx offset)
12832 if (expr == NULL_TREE
12833 || offset == NULL_RTX
12834 || !CONST_INT_P (offset)
12835 || INTVAL (offset) < 0
12836 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
12839 while (TREE_CODE (expr) == COMPONENT_REF)
12841 expr = TREE_OPERAND (expr, 0);
12842 if (expr == NULL_TREE)
12846 return DECL_P (expr);
12849 /* A for_each_rtx callback for which DATA points to the instruction
12850 containing *X. Stop the search if we find a MEM that is not safe
12851 from R10K speculation. */
12854 r10k_needs_protection_p_1 (rtx *loc, void *data)
12862 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
12865 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
12871 /* A note_stores callback for which DATA points to an instruction pointer.
12872 If *DATA is nonnull, make it null if it X contains a MEM that is not
12873 safe from R10K speculation. */
12876 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12881 insn_ptr = (rtx *) data;
12882 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
12883 *insn_ptr = NULL_RTX;
12886 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
12887 Return nonzero if the call is not to a declared function. */
12890 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
12899 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
12905 /* Return true if instruction INSN needs to be protected by an R10K
12909 r10k_needs_protection_p (rtx insn)
12912 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
12914 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
12916 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
12917 return insn == NULL_RTX;
12920 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
12923 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
12924 edge is unconditional. */
12927 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
12932 FOR_EACH_EDGE (e, ei, bb->preds)
12933 if (!single_succ_p (e->src)
12934 || !TEST_BIT (protected_bbs, e->src->index)
12935 || (e->flags & EDGE_COMPLEX) != 0)
12940 /* Implement -mr10k-cache-barrier= for the current function. */
12943 r10k_insert_cache_barriers (void)
12945 int *rev_post_order;
12948 sbitmap protected_bbs;
12949 rtx insn, end, unprotected_region;
12953 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
12957 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. */
12958 compute_bb_for_insn ();
12960 /* Create def-use chains. */
12961 df_set_flags (DF_EQ_NOTES);
12962 df_chain_add_problem (DF_UD_CHAIN);
12965 /* Calculate dominators. */
12966 calculate_dominance_info (CDI_DOMINATORS);
12968 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
12969 X is protected by a cache barrier. */
12970 protected_bbs = sbitmap_alloc (last_basic_block);
12971 sbitmap_zero (protected_bbs);
12973 /* Iterate over the basic blocks in reverse post-order. */
12974 rev_post_order = XNEWVEC (int, last_basic_block);
12975 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
12976 for (i = 0; i < n; i++)
12978 bb = BASIC_BLOCK (rev_post_order[i]);
12980 /* If this block is only reached by unconditional edges, and if the
12981 source of every edge is protected, the beginning of the block is
12983 if (r10k_protected_bb_p (bb, protected_bbs))
12984 unprotected_region = NULL_RTX;
12986 unprotected_region = pc_rtx;
12987 end = NEXT_INSN (BB_END (bb));
12989 /* UNPROTECTED_REGION is:
12991 - null if we are processing a protected region,
12992 - pc_rtx if we are processing an unprotected region but have
12993 not yet found the first instruction in it
12994 - the first instruction in an unprotected region otherwise. */
12995 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
12997 if (unprotected_region && INSN_P (insn))
12999 if (recog_memoized (insn) == CODE_FOR_mips_cache)
13000 /* This CACHE instruction protects the following code. */
13001 unprotected_region = NULL_RTX;
13004 /* See if INSN is the first instruction in this
13005 unprotected region. */
13006 if (unprotected_region == pc_rtx)
13007 unprotected_region = insn;
13009 /* See if INSN needs to be protected. If so,
13010 we must insert a cache barrier somewhere between
13011 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13012 clear which position is better performance-wise,
13013 but as a tie-breaker, we assume that it is better
13014 to allow delay slots to be back-filled where
13015 possible, and that it is better not to insert
13016 barriers in the middle of already-scheduled code.
13017 We therefore insert the barrier at the beginning
13019 if (r10k_needs_protection_p (insn))
13021 emit_insn_before (gen_r10k_cache_barrier (),
13022 unprotected_region);
13023 unprotected_region = NULL_RTX;
13029 /* The called function is not required to protect the exit path.
13030 The code that follows a call is therefore unprotected. */
13031 unprotected_region = pc_rtx;
13034 /* Record whether the end of this block is protected. */
13035 if (unprotected_region == NULL_RTX)
13036 SET_BIT (protected_bbs, bb->index);
13038 XDELETEVEC (rev_post_order);
13040 sbitmap_free (protected_bbs);
13042 free_dominance_info (CDI_DOMINATORS);
13044 df_finish_pass (false);
13046 free_bb_for_insn ();
13049 /* A temporary variable used by for_each_rtx callbacks, etc. */
13050 static rtx mips_sim_insn;
13052 /* A structure representing the state of the processor pipeline.
13053 Used by the mips_sim_* family of functions. */
13055 /* The maximum number of instructions that can be issued in a cycle.
13056 (Caches mips_issue_rate.) */
13057 unsigned int issue_rate;
13059 /* The current simulation time. */
13062 /* How many more instructions can be issued in the current cycle. */
13063 unsigned int insns_left;
13065 /* LAST_SET[X].INSN is the last instruction to set register X.
13066 LAST_SET[X].TIME is the time at which that instruction was issued.
13067 INSN is null if no instruction has yet set register X. */
13071 } last_set[FIRST_PSEUDO_REGISTER];
13073 /* The pipeline's current DFA state. */
13077 /* Reset STATE to the initial simulation state. */
13080 mips_sim_reset (struct mips_sim *state)
13083 state->insns_left = state->issue_rate;
13084 memset (&state->last_set, 0, sizeof (state->last_set));
13085 state_reset (state->dfa_state);
13088 /* Initialize STATE before its first use. DFA_STATE points to an
13089 allocated but uninitialized DFA state. */
13092 mips_sim_init (struct mips_sim *state, state_t dfa_state)
13094 state->issue_rate = mips_issue_rate ();
13095 state->dfa_state = dfa_state;
13096 mips_sim_reset (state);
13099 /* Advance STATE by one clock cycle. */
13102 mips_sim_next_cycle (struct mips_sim *state)
13105 state->insns_left = state->issue_rate;
13106 state_transition (state->dfa_state, 0);
13109 /* Advance simulation state STATE until instruction INSN can read
13113 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
13115 unsigned int regno, end_regno;
13117 end_regno = END_REGNO (reg);
13118 for (regno = REGNO (reg); regno < end_regno; regno++)
13119 if (state->last_set[regno].insn != 0)
13123 t = (state->last_set[regno].time
13124 + insn_latency (state->last_set[regno].insn, insn));
13125 while (state->time < t)
13126 mips_sim_next_cycle (state);
13130 /* A for_each_rtx callback. If *X is a register, advance simulation state
13131 DATA until mips_sim_insn can read the register's value. */
13134 mips_sim_wait_regs_2 (rtx *x, void *data)
13137 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
13141 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
13144 mips_sim_wait_regs_1 (rtx *x, void *data)
13146 for_each_rtx (x, mips_sim_wait_regs_2, data);
13149 /* Advance simulation state STATE until all of INSN's register
13150 dependencies are satisfied. */
13153 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
13155 mips_sim_insn = insn;
13156 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
13159 /* Advance simulation state STATE until the units required by
13160 instruction INSN are available. */
13163 mips_sim_wait_units (struct mips_sim *state, rtx insn)
13167 tmp_state = alloca (state_size ());
13168 while (state->insns_left == 0
13169 || (memcpy (tmp_state, state->dfa_state, state_size ()),
13170 state_transition (tmp_state, insn) >= 0))
13171 mips_sim_next_cycle (state);
13174 /* Advance simulation state STATE until INSN is ready to issue. */
13177 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
13179 mips_sim_wait_regs (state, insn);
13180 mips_sim_wait_units (state, insn);
13183 /* mips_sim_insn has just set X. Update the LAST_SET array
13184 in simulation state DATA. */
13187 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
13189 struct mips_sim *state;
13191 state = (struct mips_sim *) data;
13194 unsigned int regno, end_regno;
13196 end_regno = END_REGNO (x);
13197 for (regno = REGNO (x); regno < end_regno; regno++)
13199 state->last_set[regno].insn = mips_sim_insn;
13200 state->last_set[regno].time = state->time;
13205 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
13206 can issue immediately (i.e., that mips_sim_wait_insn has already
13210 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
13212 state_transition (state->dfa_state, insn);
13213 state->insns_left--;
13215 mips_sim_insn = insn;
13216 note_stores (PATTERN (insn), mips_sim_record_set, state);
13219 /* Simulate issuing a NOP in state STATE. */
13222 mips_sim_issue_nop (struct mips_sim *state)
13224 if (state->insns_left == 0)
13225 mips_sim_next_cycle (state);
13226 state->insns_left--;
13229 /* Update simulation state STATE so that it's ready to accept the instruction
13230 after INSN. INSN should be part of the main rtl chain, not a member of a
13234 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
13236 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
13238 mips_sim_issue_nop (state);
13240 switch (GET_CODE (SEQ_BEGIN (insn)))
13244 /* We can't predict the processor state after a call or label. */
13245 mips_sim_reset (state);
13249 /* The delay slots of branch likely instructions are only executed
13250 when the branch is taken. Therefore, if the caller has simulated
13251 the delay slot instruction, STATE does not really reflect the state
13252 of the pipeline for the instruction after the delay slot. Also,
13253 branch likely instructions tend to incur a penalty when not taken,
13254 so there will probably be an extra delay between the branch and
13255 the instruction after the delay slot. */
13256 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
13257 mips_sim_reset (state);
13265 /* The VR4130 pipeline issues aligned pairs of instructions together,
13266 but it stalls the second instruction if it depends on the first.
13267 In order to cut down the amount of logic required, this dependence
13268 check is not based on a full instruction decode. Instead, any non-SPECIAL
13269 instruction is assumed to modify the register specified by bits 20-16
13270 (which is usually the "rt" field).
13272 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
13273 input, so we can end up with a false dependence between the branch
13274 and its delay slot. If this situation occurs in instruction INSN,
13275 try to avoid it by swapping rs and rt. */
13278 vr4130_avoid_branch_rt_conflict (rtx insn)
13282 first = SEQ_BEGIN (insn);
13283 second = SEQ_END (insn);
13285 && NONJUMP_INSN_P (second)
13286 && GET_CODE (PATTERN (first)) == SET
13287 && GET_CODE (SET_DEST (PATTERN (first))) == PC
13288 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
13290 /* Check for the right kind of condition. */
13291 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
13292 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
13293 && REG_P (XEXP (cond, 0))
13294 && REG_P (XEXP (cond, 1))
13295 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
13296 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
13298 /* SECOND mentions the rt register but not the rs register. */
13299 rtx tmp = XEXP (cond, 0);
13300 XEXP (cond, 0) = XEXP (cond, 1);
13301 XEXP (cond, 1) = tmp;
13306 /* Implement -mvr4130-align. Go through each basic block and simulate the
13307 processor pipeline. If we find that a pair of instructions could execute
13308 in parallel, and the first of those instructions is not 8-byte aligned,
13309 insert a nop to make it aligned. */
13312 vr4130_align_insns (void)
13314 struct mips_sim state;
13315 rtx insn, subinsn, last, last2, next;
13320 /* LAST is the last instruction before INSN to have a nonzero length.
13321 LAST2 is the last such instruction before LAST. */
13325 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
13328 mips_sim_init (&state, alloca (state_size ()));
13329 for (insn = get_insns (); insn != 0; insn = next)
13331 unsigned int length;
13333 next = NEXT_INSN (insn);
13335 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
13336 This isn't really related to the alignment pass, but we do it on
13337 the fly to avoid a separate instruction walk. */
13338 vr4130_avoid_branch_rt_conflict (insn);
13340 if (USEFUL_INSN_P (insn))
13341 FOR_EACH_SUBINSN (subinsn, insn)
13343 mips_sim_wait_insn (&state, subinsn);
13345 /* If we want this instruction to issue in parallel with the
13346 previous one, make sure that the previous instruction is
13347 aligned. There are several reasons why this isn't worthwhile
13348 when the second instruction is a call:
13350 - Calls are less likely to be performance critical,
13351 - There's a good chance that the delay slot can execute
13352 in parallel with the call.
13353 - The return address would then be unaligned.
13355 In general, if we're going to insert a nop between instructions
13356 X and Y, it's better to insert it immediately after X. That
13357 way, if the nop makes Y aligned, it will also align any labels
13358 between X and Y. */
13359 if (state.insns_left != state.issue_rate
13360 && !CALL_P (subinsn))
13362 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
13364 /* SUBINSN is the first instruction in INSN and INSN is
13365 aligned. We want to align the previous instruction
13366 instead, so insert a nop between LAST2 and LAST.
13368 Note that LAST could be either a single instruction
13369 or a branch with a delay slot. In the latter case,
13370 LAST, like INSN, is already aligned, but the delay
13371 slot must have some extra delay that stops it from
13372 issuing at the same time as the branch. We therefore
13373 insert a nop before the branch in order to align its
13375 emit_insn_after (gen_nop (), last2);
13378 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
13380 /* SUBINSN is the delay slot of INSN, but INSN is
13381 currently unaligned. Insert a nop between
13382 LAST and INSN to align it. */
13383 emit_insn_after (gen_nop (), last);
13387 mips_sim_issue_insn (&state, subinsn);
13389 mips_sim_finish_insn (&state, insn);
13391 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
13392 length = get_attr_length (insn);
13395 /* If the instruction is an asm statement or multi-instruction
13396 mips.md patern, the length is only an estimate. Insert an
13397 8 byte alignment after it so that the following instructions
13398 can be handled correctly. */
13399 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
13400 && (recog_memoized (insn) < 0 || length >= 8))
13402 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
13403 next = NEXT_INSN (next);
13404 mips_sim_next_cycle (&state);
13407 else if (length & 4)
13408 aligned_p = !aligned_p;
13413 /* See whether INSN is an aligned label. */
13414 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
13420 /* This structure records that the current function has a LO_SUM
13421 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
13422 the largest offset applied to BASE by all such LO_SUMs. */
13423 struct mips_lo_sum_offset {
13425 HOST_WIDE_INT offset;
13428 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
13431 mips_hash_base (rtx base)
13433 int do_not_record_p;
13435 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
13438 /* Hash-table callbacks for mips_lo_sum_offsets. */
13441 mips_lo_sum_offset_hash (const void *entry)
13443 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
13447 mips_lo_sum_offset_eq (const void *entry, const void *value)
13449 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
13450 (const_rtx) value);
13453 /* Look up symbolic constant X in HTAB, which is a hash table of
13454 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
13455 paired with a recorded LO_SUM, otherwise record X in the table. */
13458 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
13462 struct mips_lo_sum_offset *entry;
13464 /* Split X into a base and offset. */
13465 split_const (x, &base, &offset);
13466 if (UNSPEC_ADDRESS_P (base))
13467 base = UNSPEC_ADDRESS (base);
13469 /* Look up the base in the hash table. */
13470 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
13474 entry = (struct mips_lo_sum_offset *) *slot;
13475 if (option == INSERT)
13479 entry = XNEW (struct mips_lo_sum_offset);
13480 entry->base = base;
13481 entry->offset = INTVAL (offset);
13486 if (INTVAL (offset) > entry->offset)
13487 entry->offset = INTVAL (offset);
13490 return INTVAL (offset) <= entry->offset;
13493 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
13494 Record every LO_SUM in *LOC. */
13497 mips_record_lo_sum (rtx *loc, void *data)
13499 if (GET_CODE (*loc) == LO_SUM)
13500 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
13504 /* Return true if INSN is a SET of an orphaned high-part relocation.
13505 HTAB is a hash table of mips_lo_sum_offsets that describes all the
13506 LO_SUMs in the current function. */
13509 mips_orphaned_high_part_p (htab_t htab, rtx insn)
13511 enum mips_symbol_type type;
13514 set = single_set (insn);
13517 /* Check for %his. */
13519 if (GET_CODE (x) == HIGH
13520 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
13521 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
13523 /* Check for local %gots (and %got_pages, which is redundant but OK). */
13524 if (GET_CODE (x) == UNSPEC
13525 && XINT (x, 1) == UNSPEC_LOAD_GOT
13526 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
13527 SYMBOL_CONTEXT_LEA, &type)
13528 && type == SYMBOL_GOTOFF_PAGE)
13529 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
13534 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
13535 INSN and a previous instruction, avoid it by inserting nops after
13538 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
13539 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
13540 before using the value of that register. *HILO_DELAY counts the
13541 number of instructions since the last hilo hazard (that is,
13542 the number of instructions since the last MFLO or MFHI).
13544 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
13545 for the next instruction.
13547 LO_REG is an rtx for the LO register, used in dependence checking. */
13550 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
13551 rtx *delayed_reg, rtx lo_reg)
13556 pattern = PATTERN (insn);
13558 /* Do not put the whole function in .set noreorder if it contains
13559 an asm statement. We don't know whether there will be hazards
13560 between the asm statement and the gcc-generated code. */
13561 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
13562 cfun->machine->all_noreorder_p = false;
13564 /* Ignore zero-length instructions (barriers and the like). */
13565 ninsns = get_attr_length (insn) / 4;
13569 /* Work out how many nops are needed. Note that we only care about
13570 registers that are explicitly mentioned in the instruction's pattern.
13571 It doesn't matter that calls use the argument registers or that they
13572 clobber hi and lo. */
13573 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
13574 nops = 2 - *hilo_delay;
13575 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
13580 /* Insert the nops between this instruction and the previous one.
13581 Each new nop takes us further from the last hilo hazard. */
13582 *hilo_delay += nops;
13584 emit_insn_after (gen_hazard_nop (), after);
13586 /* Set up the state for the next instruction. */
13587 *hilo_delay += ninsns;
13589 if (INSN_CODE (insn) >= 0)
13590 switch (get_attr_hazard (insn))
13600 set = single_set (insn);
13602 *delayed_reg = SET_DEST (set);
13607 /* Go through the instruction stream and insert nops where necessary.
13608 Also delete any high-part relocations whose partnering low parts
13609 are now all dead. See if the whole function can then be put into
13610 .set noreorder and .set nomacro. */
13613 mips_reorg_process_insns (void)
13615 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
13619 /* Force all instructions to be split into their final form. */
13620 split_all_insns_noflow ();
13622 /* Recalculate instruction lengths without taking nops into account. */
13623 cfun->machine->ignore_hazard_length_p = true;
13624 shorten_branches (get_insns ());
13626 cfun->machine->all_noreorder_p = true;
13628 /* We don't track MIPS16 PC-relative offsets closely enough to make
13629 a good job of "set .noreorder" code in MIPS16 mode. */
13631 cfun->machine->all_noreorder_p = false;
13633 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
13634 if (!TARGET_EXPLICIT_RELOCS)
13635 cfun->machine->all_noreorder_p = false;
13637 /* Profiled functions can't be all noreorder because the profiler
13638 support uses assembler macros. */
13640 cfun->machine->all_noreorder_p = false;
13642 /* Code compiled with -mfix-vr4120 can't be all noreorder because
13643 we rely on the assembler to work around some errata. */
13644 if (TARGET_FIX_VR4120)
13645 cfun->machine->all_noreorder_p = false;
13647 /* The same is true for -mfix-vr4130 if we might generate MFLO or
13648 MFHI instructions. Note that we avoid using MFLO and MFHI if
13649 the VR4130 MACC and DMACC instructions are available instead;
13650 see the *mfhilo_{si,di}_macc patterns. */
13651 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
13652 cfun->machine->all_noreorder_p = false;
13654 htab = htab_create (37, mips_lo_sum_offset_hash,
13655 mips_lo_sum_offset_eq, free);
13657 /* Make a first pass over the instructions, recording all the LO_SUMs. */
13658 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13659 FOR_EACH_SUBINSN (subinsn, insn)
13660 if (INSN_P (subinsn))
13661 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
13666 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
13668 /* Make a second pass over the instructions. Delete orphaned
13669 high-part relocations or turn them into NOPs. Avoid hazards
13670 by inserting NOPs. */
13671 for (insn = get_insns (); insn != 0; insn = next_insn)
13673 next_insn = NEXT_INSN (insn);
13676 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
13678 /* If we find an orphaned high-part relocation in a delay
13679 slot, it's easier to turn that instruction into a NOP than
13680 to delete it. The delay slot will be a NOP either way. */
13681 FOR_EACH_SUBINSN (subinsn, insn)
13682 if (INSN_P (subinsn))
13684 if (mips_orphaned_high_part_p (htab, subinsn))
13686 PATTERN (subinsn) = gen_nop ();
13687 INSN_CODE (subinsn) = CODE_FOR_nop;
13689 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
13690 &delayed_reg, lo_reg);
13696 /* INSN is a single instruction. Delete it if it's an
13697 orphaned high-part relocation. */
13698 if (mips_orphaned_high_part_p (htab, insn))
13699 delete_insn (insn);
13700 /* Also delete cache barriers if the last instruction
13701 was an annulled branch. INSN will not be speculatively
13703 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
13705 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
13706 delete_insn (insn);
13709 mips_avoid_hazard (last_insn, insn, &hilo_delay,
13710 &delayed_reg, lo_reg);
13717 htab_delete (htab);
13720 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
13725 mips16_lay_out_constants ();
13726 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
13727 r10k_insert_cache_barriers ();
13728 if (optimize > 0 && flag_delayed_branch)
13729 dbr_schedule (get_insns ());
13730 mips_reorg_process_insns ();
13732 && TARGET_EXPLICIT_RELOCS
13734 && TARGET_VR4130_ALIGN)
13735 vr4130_align_insns ();
13738 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
13739 in order to avoid duplicating too much logic from elsewhere. */
13742 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13743 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13746 rtx this_rtx, temp1, temp2, insn, fnaddr;
13747 bool use_sibcall_p;
13749 /* Pretend to be a post-reload pass while generating rtl. */
13750 reload_completed = 1;
13752 /* Mark the end of the (empty) prologue. */
13753 emit_note (NOTE_INSN_PROLOGUE_END);
13755 /* Determine if we can use a sibcall to call FUNCTION directly. */
13756 fnaddr = XEXP (DECL_RTL (function), 0);
13757 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
13758 && const_call_insn_operand (fnaddr, Pmode));
13760 /* Determine if we need to load FNADDR from the GOT. */
13762 && (mips_got_symbol_type_p
13763 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
13765 /* Pick a global pointer. Use a call-clobbered register if
13766 TARGET_CALL_SAVED_GP. */
13767 cfun->machine->global_pointer
13768 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
13769 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
13771 /* Set up the global pointer for n32 or n64 abicalls. */
13772 mips_emit_loadgp ();
13775 /* We need two temporary registers in some cases. */
13776 temp1 = gen_rtx_REG (Pmode, 2);
13777 temp2 = gen_rtx_REG (Pmode, 3);
13779 /* Find out which register contains the "this" pointer. */
13780 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13781 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
13783 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
13785 /* Add DELTA to THIS_RTX. */
13788 rtx offset = GEN_INT (delta);
13789 if (!SMALL_OPERAND (delta))
13791 mips_emit_move (temp1, offset);
13794 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
13797 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
13798 if (vcall_offset != 0)
13802 /* Set TEMP1 to *THIS_RTX. */
13803 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
13805 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
13806 addr = mips_add_offset (temp2, temp1, vcall_offset);
13808 /* Load the offset and add it to THIS_RTX. */
13809 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
13810 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
13813 /* Jump to the target function. Use a sibcall if direct jumps are
13814 allowed, otherwise load the address into a register first. */
13817 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
13818 SIBLING_CALL_P (insn) = 1;
13822 /* This is messy. GAS treats "la $25,foo" as part of a call
13823 sequence and may allow a global "foo" to be lazily bound.
13824 The general move patterns therefore reject this combination.
13826 In this context, lazy binding would actually be OK
13827 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
13828 TARGET_CALL_SAVED_GP; see mips_load_call_address.
13829 We must therefore load the address via a temporary
13830 register if mips_dangerous_for_la25_p.
13832 If we jump to the temporary register rather than $25,
13833 the assembler can use the move insn to fill the jump's
13836 We can use the same technique for MIPS16 code, where $25
13837 is not a valid JR register. */
13838 if (TARGET_USE_PIC_FN_ADDR_REG
13840 && !mips_dangerous_for_la25_p (fnaddr))
13841 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
13842 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
13844 if (TARGET_USE_PIC_FN_ADDR_REG
13845 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
13846 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
13847 emit_jump_insn (gen_indirect_jump (temp1));
13850 /* Run just enough of rest_of_compilation. This sequence was
13851 "borrowed" from alpha.c. */
13852 insn = get_insns ();
13853 insn_locators_alloc ();
13854 split_all_insns_noflow ();
13855 mips16_lay_out_constants ();
13856 shorten_branches (insn);
13857 final_start_function (insn, file, 1);
13858 final (insn, file, 1);
13859 final_end_function ();
13860 free_after_compilation (cfun);
13862 /* Clean up the vars set above. Note that final_end_function resets
13863 the global pointer for us. */
13864 reload_completed = 0;
13867 /* The last argument passed to mips_set_mips16_mode, or negative if the
13868 function hasn't been called yet.
13870 There are two copies of this information. One is saved and restored
13871 by the PCH process while the other is specific to this compiler
13872 invocation. The information calculated by mips_set_mips16_mode
13873 is invalid unless the two variables are the same. */
13874 static int was_mips16_p = -1;
13875 static GTY(()) int was_mips16_pch_p = -1;
13877 /* Set up the target-dependent global state so that it matches the
13878 current function's ISA mode. */
13881 mips_set_mips16_mode (int mips16_p)
13883 if (mips16_p == was_mips16_p
13884 && mips16_p == was_mips16_pch_p)
13887 /* Restore base settings of various flags. */
13888 target_flags = mips_base_target_flags;
13889 flag_schedule_insns = mips_base_schedule_insns;
13890 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
13891 flag_move_loop_invariants = mips_base_move_loop_invariants;
13892 align_loops = mips_base_align_loops;
13893 align_jumps = mips_base_align_jumps;
13894 align_functions = mips_base_align_functions;
13898 /* Switch to MIPS16 mode. */
13899 target_flags |= MASK_MIPS16;
13901 /* Don't run the scheduler before reload, since it tends to
13902 increase register pressure. */
13903 flag_schedule_insns = 0;
13905 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
13906 the whole function to be in a single section. */
13907 flag_reorder_blocks_and_partition = 0;
13909 /* Don't move loop invariants, because it tends to increase
13910 register pressure. It also introduces an extra move in cases
13911 where the constant is the first operand in a two-operand binary
13912 instruction, or when it forms a register argument to a functon
13914 flag_move_loop_invariants = 0;
13916 target_flags |= MASK_EXPLICIT_RELOCS;
13918 /* Experiments suggest we get the best overall section-anchor
13919 results from using the range of an unextended LW or SW. Code
13920 that makes heavy use of byte or short accesses can do better
13921 with ranges of 0...31 and 0...63 respectively, but most code is
13922 sensitive to the range of LW and SW instead. */
13923 targetm.min_anchor_offset = 0;
13924 targetm.max_anchor_offset = 127;
13926 if (flag_pic && !TARGET_OLDABI)
13927 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
13930 sorry ("MIPS16 -mxgot code");
13932 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
13933 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
13937 /* Switch to normal (non-MIPS16) mode. */
13938 target_flags &= ~MASK_MIPS16;
13940 /* Provide default values for align_* for 64-bit targets. */
13943 if (align_loops == 0)
13945 if (align_jumps == 0)
13947 if (align_functions == 0)
13948 align_functions = 8;
13951 targetm.min_anchor_offset = -32768;
13952 targetm.max_anchor_offset = 32767;
13955 /* (Re)initialize MIPS target internals for new ISA. */
13956 mips_init_relocs ();
13958 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
13959 /* Reinitialize target-dependent state. */
13962 was_mips16_p = mips16_p;
13963 was_mips16_pch_p = mips16_p;
13966 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
13967 function should use the MIPS16 ISA and switch modes accordingly. */
13970 mips_set_current_function (tree fndecl)
13972 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
13975 /* Allocate a chunk of memory for per-function machine-dependent data. */
13977 static struct machine_function *
13978 mips_init_machine_status (void)
13980 return ((struct machine_function *)
13981 ggc_alloc_cleared (sizeof (struct machine_function)));
13984 /* Return the processor associated with the given ISA level, or null
13985 if the ISA isn't valid. */
13987 static const struct mips_cpu_info *
13988 mips_cpu_info_from_isa (int isa)
13992 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
13993 if (mips_cpu_info_table[i].isa == isa)
13994 return mips_cpu_info_table + i;
13999 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14000 with a final "000" replaced by "k". Ignore case.
14002 Note: this function is shared between GCC and GAS. */
14005 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14007 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14008 given++, canonical++;
14010 return ((*given == 0 && *canonical == 0)
14011 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14014 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14015 CPU name. We've traditionally allowed a lot of variation here.
14017 Note: this function is shared between GCC and GAS. */
14020 mips_matching_cpu_name_p (const char *canonical, const char *given)
14022 /* First see if the name matches exactly, or with a final "000"
14023 turned into "k". */
14024 if (mips_strict_matching_cpu_name_p (canonical, given))
14027 /* If not, try comparing based on numerical designation alone.
14028 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14029 if (TOLOWER (*given) == 'r')
14031 if (!ISDIGIT (*given))
14034 /* Skip over some well-known prefixes in the canonical name,
14035 hoping to find a number there too. */
14036 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14038 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14040 else if (TOLOWER (canonical[0]) == 'r')
14043 return mips_strict_matching_cpu_name_p (canonical, given);
14046 /* Return the mips_cpu_info entry for the processor or ISA given
14047 by CPU_STRING. Return null if the string isn't recognized.
14049 A similar function exists in GAS. */
14051 static const struct mips_cpu_info *
14052 mips_parse_cpu (const char *cpu_string)
14057 /* In the past, we allowed upper-case CPU names, but it doesn't
14058 work well with the multilib machinery. */
14059 for (s = cpu_string; *s != 0; s++)
14062 warning (0, "CPU names must be lower case");
14066 /* 'from-abi' selects the most compatible architecture for the given
14067 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14068 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14070 if (strcasecmp (cpu_string, "from-abi") == 0)
14071 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
14072 : ABI_NEEDS_64BIT_REGS ? 3
14073 : (TARGET_64BIT ? 3 : 1));
14075 /* 'default' has traditionally been a no-op. Probably not very useful. */
14076 if (strcasecmp (cpu_string, "default") == 0)
14079 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
14080 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
14081 return mips_cpu_info_table + i;
14086 /* Set up globals to generate code for the ISA or processor
14087 described by INFO. */
14090 mips_set_architecture (const struct mips_cpu_info *info)
14094 mips_arch_info = info;
14095 mips_arch = info->cpu;
14096 mips_isa = info->isa;
14100 /* Likewise for tuning. */
14103 mips_set_tune (const struct mips_cpu_info *info)
14107 mips_tune_info = info;
14108 mips_tune = info->cpu;
14112 /* Implement TARGET_HANDLE_OPTION. */
14115 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
14120 if (strcmp (arg, "32") == 0)
14122 else if (strcmp (arg, "o64") == 0)
14123 mips_abi = ABI_O64;
14124 else if (strcmp (arg, "n32") == 0)
14125 mips_abi = ABI_N32;
14126 else if (strcmp (arg, "64") == 0)
14128 else if (strcmp (arg, "eabi") == 0)
14129 mips_abi = ABI_EABI;
14136 return mips_parse_cpu (arg) != 0;
14139 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
14140 return mips_isa_option_info != 0;
14142 case OPT_mno_flush_func:
14143 mips_cache_flush_func = NULL;
14146 case OPT_mcode_readable_:
14147 if (strcmp (arg, "yes") == 0)
14148 mips_code_readable = CODE_READABLE_YES;
14149 else if (strcmp (arg, "pcrel") == 0)
14150 mips_code_readable = CODE_READABLE_PCREL;
14151 else if (strcmp (arg, "no") == 0)
14152 mips_code_readable = CODE_READABLE_NO;
14157 case OPT_mr10k_cache_barrier_:
14158 if (strcmp (arg, "load-store") == 0)
14159 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
14160 else if (strcmp (arg, "store") == 0)
14161 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
14162 else if (strcmp (arg, "none") == 0)
14163 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
14173 /* Implement OVERRIDE_OPTIONS. */
14176 mips_override_options (void)
14178 int i, start, regno, mode;
14180 /* Process flags as though we were generating non-MIPS16 code. */
14181 mips_base_mips16 = TARGET_MIPS16;
14182 target_flags &= ~MASK_MIPS16;
14184 #ifdef SUBTARGET_OVERRIDE_OPTIONS
14185 SUBTARGET_OVERRIDE_OPTIONS;
14188 /* Set the small data limit. */
14189 mips_small_data_threshold = (g_switch_set
14191 : MIPS_DEFAULT_GVALUE);
14193 /* The following code determines the architecture and register size.
14194 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
14195 The GAS and GCC code should be kept in sync as much as possible. */
14197 if (mips_arch_string != 0)
14198 mips_set_architecture (mips_parse_cpu (mips_arch_string));
14200 if (mips_isa_option_info != 0)
14202 if (mips_arch_info == 0)
14203 mips_set_architecture (mips_isa_option_info);
14204 else if (mips_arch_info->isa != mips_isa_option_info->isa)
14205 error ("%<-%s%> conflicts with the other architecture options, "
14206 "which specify a %s processor",
14207 mips_isa_option_info->name,
14208 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
14211 if (mips_arch_info == 0)
14213 #ifdef MIPS_CPU_STRING_DEFAULT
14214 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
14216 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
14220 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
14221 error ("%<-march=%s%> is not compatible with the selected ABI",
14222 mips_arch_info->name);
14224 /* Optimize for mips_arch, unless -mtune selects a different processor. */
14225 if (mips_tune_string != 0)
14226 mips_set_tune (mips_parse_cpu (mips_tune_string));
14228 if (mips_tune_info == 0)
14229 mips_set_tune (mips_arch_info);
14231 if ((target_flags_explicit & MASK_64BIT) != 0)
14233 /* The user specified the size of the integer registers. Make sure
14234 it agrees with the ABI and ISA. */
14235 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
14236 error ("%<-mgp64%> used with a 32-bit processor");
14237 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
14238 error ("%<-mgp32%> used with a 64-bit ABI");
14239 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
14240 error ("%<-mgp64%> used with a 32-bit ABI");
14244 /* Infer the integer register size from the ABI and processor.
14245 Restrict ourselves to 32-bit registers if that's all the
14246 processor has, or if the ABI cannot handle 64-bit registers. */
14247 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
14248 target_flags &= ~MASK_64BIT;
14250 target_flags |= MASK_64BIT;
14253 if ((target_flags_explicit & MASK_FLOAT64) != 0)
14255 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
14256 error ("unsupported combination: %s", "-mfp64 -msingle-float");
14257 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
14258 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
14259 else if (!TARGET_64BIT && TARGET_FLOAT64)
14261 if (!ISA_HAS_MXHC1)
14262 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
14263 " the target supports the mfhc1 and mthc1 instructions");
14264 else if (mips_abi != ABI_32)
14265 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
14271 /* -msingle-float selects 32-bit float registers. Otherwise the
14272 float registers should be the same size as the integer ones. */
14273 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
14274 target_flags |= MASK_FLOAT64;
14276 target_flags &= ~MASK_FLOAT64;
14279 /* End of code shared with GAS. */
14281 /* If no -mlong* option was given, infer it from the other options. */
14282 if ((target_flags_explicit & MASK_LONG64) == 0)
14284 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
14285 target_flags |= MASK_LONG64;
14287 target_flags &= ~MASK_LONG64;
14290 if (!TARGET_OLDABI)
14291 flag_pcc_struct_return = 0;
14293 /* Decide which rtx_costs structure to use. */
14295 mips_cost = &mips_rtx_cost_optimize_size;
14297 mips_cost = &mips_rtx_cost_data[mips_tune];
14299 /* If the user hasn't specified a branch cost, use the processor's
14301 if (mips_branch_cost == 0)
14302 mips_branch_cost = mips_cost->branch_cost;
14304 /* If neither -mbranch-likely nor -mno-branch-likely was given
14305 on the command line, set MASK_BRANCHLIKELY based on the target
14306 architecture and tuning flags. Annulled delay slots are a
14307 size win, so we only consider the processor-specific tuning
14308 for !optimize_size. */
14309 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
14311 if (ISA_HAS_BRANCHLIKELY
14313 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
14314 target_flags |= MASK_BRANCHLIKELY;
14316 target_flags &= ~MASK_BRANCHLIKELY;
14318 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
14319 warning (0, "the %qs architecture does not support branch-likely"
14320 " instructions", mips_arch_info->name);
14322 /* The effect of -mabicalls isn't defined for the EABI. */
14323 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
14325 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
14326 target_flags &= ~MASK_ABICALLS;
14329 if (TARGET_ABICALLS_PIC2)
14330 /* We need to set flag_pic for executables as well as DSOs
14331 because we may reference symbols that are not defined in
14332 the final executable. (MIPS does not use things like
14333 copy relocs, for example.)
14335 There is a body of code that uses __PIC__ to distinguish
14336 between -mabicalls and -mno-abicalls code. The non-__PIC__
14337 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
14338 long as any indirect jumps use $25. */
14341 /* -mvr4130-align is a "speed over size" optimization: it usually produces
14342 faster code, but at the expense of more nops. Enable it at -O3 and
14344 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
14345 target_flags |= MASK_VR4130_ALIGN;
14347 /* Prefer a call to memcpy over inline code when optimizing for size,
14348 though see MOVE_RATIO in mips.h. */
14349 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
14350 target_flags |= MASK_MEMCPY;
14352 /* If we have a nonzero small-data limit, check that the -mgpopt
14353 setting is consistent with the other target flags. */
14354 if (mips_small_data_threshold > 0)
14358 if (!TARGET_EXPLICIT_RELOCS)
14359 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
14361 TARGET_LOCAL_SDATA = false;
14362 TARGET_EXTERN_SDATA = false;
14366 if (TARGET_VXWORKS_RTP)
14367 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
14369 if (TARGET_ABICALLS)
14370 warning (0, "cannot use small-data accesses for %qs",
14375 #ifdef MIPS_TFMODE_FORMAT
14376 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
14379 /* Make sure that the user didn't turn off paired single support when
14380 MIPS-3D support is requested. */
14382 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
14383 && !TARGET_PAIRED_SINGLE_FLOAT)
14384 error ("%<-mips3d%> requires %<-mpaired-single%>");
14386 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
14388 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
14390 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
14391 and TARGET_HARD_FLOAT_ABI are both true. */
14392 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
14393 error ("%qs must be used with %qs",
14394 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
14395 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
14397 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
14399 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
14400 warning (0, "the %qs architecture does not support paired-single"
14401 " instructions", mips_arch_info->name);
14403 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14404 && !TARGET_CACHE_BUILTIN)
14406 error ("%qs requires a target that provides the %qs instruction",
14407 "-mr10k-cache-barrier", "cache");
14408 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
14411 /* If TARGET_DSPR2, enable MASK_DSP. */
14413 target_flags |= MASK_DSP;
14415 /* .eh_frame addresses should be the same width as a C pointer.
14416 Most MIPS ABIs support only one pointer size, so the assembler
14417 will usually know exactly how big an .eh_frame address is.
14419 Unfortunately, this is not true of the 64-bit EABI. The ABI was
14420 originally defined to use 64-bit pointers (i.e. it is LP64), and
14421 this is still the default mode. However, we also support an n32-like
14422 ILP32 mode, which is selected by -mlong32. The problem is that the
14423 assembler has traditionally not had an -mlong option, so it has
14424 traditionally not known whether we're using the ILP32 or LP64 form.
14426 As it happens, gas versions up to and including 2.19 use _32-bit_
14427 addresses for EABI64 .cfi_* directives. This is wrong for the
14428 default LP64 mode, so we can't use the directives by default.
14429 Moreover, since gas's current behavior is at odds with gcc's
14430 default behavior, it seems unwise to rely on future versions
14431 of gas behaving the same way. We therefore avoid using .cfi
14432 directives for -mlong32 as well. */
14433 if (mips_abi == ABI_EABI && TARGET_64BIT)
14434 flag_dwarf2_cfi_asm = 0;
14436 mips_init_print_operand_punct ();
14438 /* Set up array to map GCC register number to debug register number.
14439 Ignore the special purpose register numbers. */
14441 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
14443 mips_dbx_regno[i] = INVALID_REGNUM;
14444 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
14445 mips_dwarf_regno[i] = i;
14447 mips_dwarf_regno[i] = INVALID_REGNUM;
14450 start = GP_DBX_FIRST - GP_REG_FIRST;
14451 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
14452 mips_dbx_regno[i] = i + start;
14454 start = FP_DBX_FIRST - FP_REG_FIRST;
14455 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
14456 mips_dbx_regno[i] = i + start;
14458 /* Accumulator debug registers use big-endian ordering. */
14459 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
14460 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
14461 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
14462 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
14463 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
14465 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
14466 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
14469 /* Set up mips_hard_regno_mode_ok. */
14470 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
14471 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
14472 mips_hard_regno_mode_ok[mode][regno]
14473 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
14475 /* Function to allocate machine-dependent function status. */
14476 init_machine_status = &mips_init_machine_status;
14478 /* Default to working around R4000 errata only if the processor
14479 was selected explicitly. */
14480 if ((target_flags_explicit & MASK_FIX_R4000) == 0
14481 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
14482 target_flags |= MASK_FIX_R4000;
14484 /* Default to working around R4400 errata only if the processor
14485 was selected explicitly. */
14486 if ((target_flags_explicit & MASK_FIX_R4400) == 0
14487 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
14488 target_flags |= MASK_FIX_R4400;
14490 /* Default to working around R10000 errata only if the processor
14491 was selected explicitly. */
14492 if ((target_flags_explicit & MASK_FIX_R10000) == 0
14493 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
14494 target_flags |= MASK_FIX_R10000;
14496 /* Make sure that branch-likely instructions available when using
14497 -mfix-r10000. The instructions are not available if either:
14499 1. -mno-branch-likely was passed.
14500 2. The selected ISA does not support branch-likely and
14501 the command line does not include -mbranch-likely. */
14502 if (TARGET_FIX_R10000
14503 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
14504 ? !ISA_HAS_BRANCHLIKELY
14505 : !TARGET_BRANCHLIKELY))
14506 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
14508 /* Save base state of options. */
14509 mips_base_target_flags = target_flags;
14510 mips_base_schedule_insns = flag_schedule_insns;
14511 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
14512 mips_base_move_loop_invariants = flag_move_loop_invariants;
14513 mips_base_align_loops = align_loops;
14514 mips_base_align_jumps = align_jumps;
14515 mips_base_align_functions = align_functions;
14517 /* Now select the ISA mode.
14519 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
14520 MIPS16 mode afterwards if need be. */
14521 mips_set_mips16_mode (false);
14524 /* Swap the register information for registers I and I + 1, which
14525 currently have the wrong endianness. Note that the registers'
14526 fixedness and call-clobberedness might have been set on the
14530 mips_swap_registers (unsigned int i)
14535 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
14536 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
14538 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
14539 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
14540 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
14541 SWAP_STRING (reg_names[i], reg_names[i + 1]);
14547 /* Implement CONDITIONAL_REGISTER_USAGE. */
14550 mips_conditional_register_usage (void)
14555 /* These DSP control register fields are global. */
14556 global_regs[CCDSP_PO_REGNUM] = 1;
14557 global_regs[CCDSP_SC_REGNUM] = 1;
14563 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
14564 fixed_regs[regno] = call_used_regs[regno] = 1;
14566 if (!TARGET_HARD_FLOAT)
14570 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
14571 fixed_regs[regno] = call_used_regs[regno] = 1;
14572 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
14573 fixed_regs[regno] = call_used_regs[regno] = 1;
14575 else if (! ISA_HAS_8CC)
14579 /* We only have a single condition-code register. We implement
14580 this by fixing all the condition-code registers and generating
14581 RTL that refers directly to ST_REG_FIRST. */
14582 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
14583 fixed_regs[regno] = call_used_regs[regno] = 1;
14585 /* In MIPS16 mode, we permit the $t temporary registers to be used
14586 for reload. We prohibit the unused $s registers, since they
14587 are call-saved, and saving them via a MIPS16 register would
14588 probably waste more time than just reloading the value. */
14591 fixed_regs[18] = call_used_regs[18] = 1;
14592 fixed_regs[19] = call_used_regs[19] = 1;
14593 fixed_regs[20] = call_used_regs[20] = 1;
14594 fixed_regs[21] = call_used_regs[21] = 1;
14595 fixed_regs[22] = call_used_regs[22] = 1;
14596 fixed_regs[23] = call_used_regs[23] = 1;
14597 fixed_regs[26] = call_used_regs[26] = 1;
14598 fixed_regs[27] = call_used_regs[27] = 1;
14599 fixed_regs[30] = call_used_regs[30] = 1;
14601 /* $f20-$f23 are call-clobbered for n64. */
14602 if (mips_abi == ABI_64)
14605 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
14606 call_really_used_regs[regno] = call_used_regs[regno] = 1;
14608 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
14610 if (mips_abi == ABI_N32)
14613 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
14614 call_really_used_regs[regno] = call_used_regs[regno] = 1;
14616 /* Make sure that double-register accumulator values are correctly
14617 ordered for the current endianness. */
14618 if (TARGET_LITTLE_ENDIAN)
14620 unsigned int regno;
14622 mips_swap_registers (MD_REG_FIRST);
14623 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
14624 mips_swap_registers (regno);
14628 /* Initialize vector TARGET to VALS. */
14631 mips_expand_vector_init (rtx target, rtx vals)
14633 enum machine_mode mode;
14634 enum machine_mode inner;
14635 unsigned int i, n_elts;
14638 mode = GET_MODE (target);
14639 inner = GET_MODE_INNER (mode);
14640 n_elts = GET_MODE_NUNITS (mode);
14642 gcc_assert (VECTOR_MODE_P (mode));
14644 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
14645 for (i = 0; i < n_elts; i++)
14646 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
14647 XVECEXP (vals, 0, i));
14649 emit_move_insn (target, mem);
14652 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
14653 other registers for instructions for which it is possible. This
14654 encourages the compiler to use CMP in cases where an XOR would
14655 require some register shuffling. */
14658 mips_order_regs_for_local_alloc (void)
14662 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
14663 reg_alloc_order[i] = i;
14667 /* It really doesn't matter where we put register 0, since it is
14668 a fixed register anyhow. */
14669 reg_alloc_order[0] = 24;
14670 reg_alloc_order[24] = 0;
14674 /* Implement EPILOGUE_USES. */
14677 mips_epilogue_uses (unsigned int regno)
14679 /* Say that the epilogue uses the return address register. Note that
14680 in the case of sibcalls, the values "used by the epilogue" are
14681 considered live at the start of the called function. */
14685 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
14686 See the comment above load_call<mode> for details. */
14687 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
14690 /* An interrupt handler must preserve some registers that are
14691 ordinarily call-clobbered. */
14692 if (cfun->machine->interrupt_handler_p
14693 && mips_interrupt_extra_call_saved_reg_p (regno))
14699 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
14702 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
14704 return GET_CODE (*x) == REG && REGNO (*x) == AT_REGNUM;
14708 /* Implement FINAL_PRESCAN_INSN. */
14711 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
14715 /* We need to emit ".set noat" before an instruction that accesses
14717 if (recog_memoized (insn) >= 0)
14718 for (i = 0; i < noperands; i++)
14719 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
14720 if (set_noat++ == 0)
14721 fprintf (asm_out_file, "\t.set\tnoat\n");
14724 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
14727 mips_final_postscan_insn (FILE *file, rtx insn, rtx *opvec, int noperands)
14731 /* Close any ".set noat" block opened by mips_final_prescan_insn. */
14732 if (recog_memoized (insn) >= 0)
14733 for (i = 0; i < noperands; i++)
14734 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
14735 if (--set_noat == 0)
14736 fprintf (file, "\t.set\tat\n");
14739 /* Initialize the GCC target structure. */
14740 #undef TARGET_ASM_ALIGNED_HI_OP
14741 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
14742 #undef TARGET_ASM_ALIGNED_SI_OP
14743 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
14744 #undef TARGET_ASM_ALIGNED_DI_OP
14745 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
14747 #undef TARGET_LEGITIMIZE_ADDRESS
14748 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
14750 #undef TARGET_ASM_FUNCTION_PROLOGUE
14751 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
14752 #undef TARGET_ASM_FUNCTION_EPILOGUE
14753 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
14754 #undef TARGET_ASM_SELECT_RTX_SECTION
14755 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
14756 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
14757 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
14759 #undef TARGET_SCHED_INIT
14760 #define TARGET_SCHED_INIT mips_sched_init
14761 #undef TARGET_SCHED_REORDER
14762 #define TARGET_SCHED_REORDER mips_sched_reorder
14763 #undef TARGET_SCHED_REORDER2
14764 #define TARGET_SCHED_REORDER2 mips_sched_reorder
14765 #undef TARGET_SCHED_VARIABLE_ISSUE
14766 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
14767 #undef TARGET_SCHED_ADJUST_COST
14768 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
14769 #undef TARGET_SCHED_ISSUE_RATE
14770 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
14771 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
14772 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
14773 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
14774 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
14775 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14776 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14777 mips_multipass_dfa_lookahead
14779 #undef TARGET_DEFAULT_TARGET_FLAGS
14780 #define TARGET_DEFAULT_TARGET_FLAGS \
14782 | TARGET_CPU_DEFAULT \
14783 | TARGET_ENDIAN_DEFAULT \
14784 | TARGET_FP_EXCEPTIONS_DEFAULT \
14785 | MASK_CHECK_ZERO_DIV \
14787 #undef TARGET_HANDLE_OPTION
14788 #define TARGET_HANDLE_OPTION mips_handle_option
14790 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14791 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
14793 #undef TARGET_INSERT_ATTRIBUTES
14794 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
14795 #undef TARGET_MERGE_DECL_ATTRIBUTES
14796 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
14797 #undef TARGET_SET_CURRENT_FUNCTION
14798 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
14800 #undef TARGET_VALID_POINTER_MODE
14801 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
14802 #undef TARGET_RTX_COSTS
14803 #define TARGET_RTX_COSTS mips_rtx_costs
14804 #undef TARGET_ADDRESS_COST
14805 #define TARGET_ADDRESS_COST mips_address_cost
14807 #undef TARGET_IN_SMALL_DATA_P
14808 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
14810 #undef TARGET_MACHINE_DEPENDENT_REORG
14811 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
14813 #undef TARGET_ASM_FILE_START
14814 #define TARGET_ASM_FILE_START mips_file_start
14815 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
14816 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
14818 #undef TARGET_INIT_LIBFUNCS
14819 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
14821 #undef TARGET_BUILD_BUILTIN_VA_LIST
14822 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
14823 #undef TARGET_EXPAND_BUILTIN_VA_START
14824 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
14825 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14826 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
14828 #undef TARGET_PROMOTE_FUNCTION_ARGS
14829 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
14830 #undef TARGET_PROMOTE_FUNCTION_RETURN
14831 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
14832 #undef TARGET_PROMOTE_PROTOTYPES
14833 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
14835 #undef TARGET_RETURN_IN_MEMORY
14836 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
14837 #undef TARGET_RETURN_IN_MSB
14838 #define TARGET_RETURN_IN_MSB mips_return_in_msb
14840 #undef TARGET_ASM_OUTPUT_MI_THUNK
14841 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
14842 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14843 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
14845 #undef TARGET_SETUP_INCOMING_VARARGS
14846 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
14847 #undef TARGET_STRICT_ARGUMENT_NAMING
14848 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
14849 #undef TARGET_MUST_PASS_IN_STACK
14850 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14851 #undef TARGET_PASS_BY_REFERENCE
14852 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
14853 #undef TARGET_CALLEE_COPIES
14854 #define TARGET_CALLEE_COPIES mips_callee_copies
14855 #undef TARGET_ARG_PARTIAL_BYTES
14856 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
14858 #undef TARGET_MODE_REP_EXTENDED
14859 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
14861 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14862 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
14864 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14865 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
14867 #undef TARGET_INIT_BUILTINS
14868 #define TARGET_INIT_BUILTINS mips_init_builtins
14869 #undef TARGET_EXPAND_BUILTIN
14870 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
14872 #undef TARGET_HAVE_TLS
14873 #define TARGET_HAVE_TLS HAVE_AS_TLS
14875 #undef TARGET_CANNOT_FORCE_CONST_MEM
14876 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
14878 #undef TARGET_ENCODE_SECTION_INFO
14879 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
14881 #undef TARGET_ATTRIBUTE_TABLE
14882 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
14883 /* All our function attributes are related to how out-of-line copies should
14884 be compiled or called. They don't in themselves prevent inlining. */
14885 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
14886 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
14888 #undef TARGET_EXTRA_LIVE_ON_ENTRY
14889 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
14891 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14892 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
14893 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
14894 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
14896 #undef TARGET_COMP_TYPE_ATTRIBUTES
14897 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
14899 #ifdef HAVE_AS_DTPRELWORD
14900 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
14901 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
14903 #undef TARGET_DWARF_REGISTER_SPAN
14904 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
14906 #undef TARGET_IRA_COVER_CLASSES
14907 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
14909 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
14910 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
14912 struct gcc_target targetm = TARGET_INITIALIZER;
14914 #include "gt-mips.h"