1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
160 MIPS_SI_FTYPE_PTR_SI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY,
217 MIPS_BUILTIN_CMP_ALL,
218 MIPS_BUILTIN_CMP_UPPER,
219 MIPS_BUILTIN_CMP_LOWER,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition {
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn) (rtx, rtx);
263 struct mips16_constant;
264 struct mips_arg_info;
265 struct mips_address_info;
266 struct mips_integer_op;
269 static enum mips_symbol_type mips_classify_symbol (rtx);
270 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
271 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
272 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
273 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
274 static bool mips_classify_address (struct mips_address_info *, rtx,
275 enum machine_mode, int);
276 static bool mips_cannot_force_const_mem (rtx);
277 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
278 static int mips_symbol_insns (enum mips_symbol_type);
279 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
280 static rtx mips_force_temporary (rtx, rtx);
281 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
282 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
283 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
284 static unsigned int mips_build_lower (struct mips_integer_op *,
285 unsigned HOST_WIDE_INT);
286 static unsigned int mips_build_integer (struct mips_integer_op *,
287 unsigned HOST_WIDE_INT);
288 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
289 static int m16_check_op (rtx, int, int, int);
290 static bool mips_rtx_costs (rtx, int, int, int *);
291 static int mips_address_cost (rtx);
292 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
293 static void mips_load_call_address (rtx, rtx, int);
294 static bool mips_function_ok_for_sibcall (tree, tree);
295 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
296 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
297 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
298 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
299 tree, int, struct mips_arg_info *);
300 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
301 static void mips_set_architecture (const struct mips_cpu_info *);
302 static void mips_set_tune (const struct mips_cpu_info *);
303 static bool mips_handle_option (size_t, const char *, int);
304 static struct machine_function *mips_init_machine_status (void);
305 static void print_operand_reloc (FILE *, rtx, const char **);
307 static void irix_output_external_libcall (rtx);
309 static void mips_file_start (void);
310 static void mips_file_end (void);
311 static bool mips_rewrite_small_data_p (rtx);
312 static int mips_small_data_pattern_1 (rtx *, void *);
313 static int mips_rewrite_small_data_1 (rtx *, void *);
314 static bool mips_function_has_gp_insn (void);
315 static unsigned int mips_global_pointer (void);
316 static bool mips_save_reg_p (unsigned int);
317 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
318 mips_save_restore_fn);
319 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
320 static void mips_output_cplocal (void);
321 static void mips_emit_loadgp (void);
322 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
323 static void mips_set_frame_expr (rtx);
324 static rtx mips_frame_set (rtx, rtx);
325 static void mips_save_reg (rtx, rtx);
326 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
327 static void mips_restore_reg (rtx, rtx);
328 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
329 HOST_WIDE_INT, tree);
330 static int symbolic_expression_p (rtx);
331 static section *mips_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static section *mips_function_rodata_section (tree);
334 static bool mips_in_small_data_p (tree);
335 static bool mips_use_anchors_for_symbol_p (rtx);
336 static int mips_fpr_return_fields (tree, tree *);
337 static bool mips_return_in_msb (tree);
338 static rtx mips_return_fpr_pair (enum machine_mode mode,
339 enum machine_mode mode1, HOST_WIDE_INT,
340 enum machine_mode mode2, HOST_WIDE_INT);
341 static rtx mips16_gp_pseudo_reg (void);
342 static void mips16_fp_args (FILE *, int, int);
343 static void build_mips16_function_stub (FILE *);
344 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
345 static void dump_constants (struct mips16_constant *, rtx);
346 static int mips16_insn_length (rtx);
347 static int mips16_rewrite_pool_refs (rtx *, void *);
348 static void mips16_lay_out_constants (void);
349 static void mips_sim_reset (struct mips_sim *);
350 static void mips_sim_init (struct mips_sim *, state_t);
351 static void mips_sim_next_cycle (struct mips_sim *);
352 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
353 static int mips_sim_wait_regs_2 (rtx *, void *);
354 static void mips_sim_wait_regs_1 (rtx *, void *);
355 static void mips_sim_wait_regs (struct mips_sim *, rtx);
356 static void mips_sim_wait_units (struct mips_sim *, rtx);
357 static void mips_sim_wait_insn (struct mips_sim *, rtx);
358 static void mips_sim_record_set (rtx, rtx, void *);
359 static void mips_sim_issue_insn (struct mips_sim *, rtx);
360 static void mips_sim_issue_nop (struct mips_sim *);
361 static void mips_sim_finish_insn (struct mips_sim *, rtx);
362 static void vr4130_avoid_branch_rt_conflict (rtx);
363 static void vr4130_align_insns (void);
364 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
365 static void mips_avoid_hazards (void);
366 static void mips_reorg (void);
367 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
368 static bool mips_matching_cpu_name_p (const char *, const char *);
369 static const struct mips_cpu_info *mips_parse_cpu (const char *);
370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
371 static bool mips_return_in_memory (tree, tree);
372 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
373 static void mips_macc_chains_record (rtx);
374 static void mips_macc_chains_reorder (rtx *, int);
375 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
376 static bool vr4130_true_reg_dependence_p (rtx);
377 static bool vr4130_swap_insns_p (rtx, rtx);
378 static void vr4130_reorder (rtx *, int);
379 static void mips_promote_ready (rtx *, int, int);
380 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
381 static int mips_variable_issue (FILE *, int, rtx, int);
382 static int mips_adjust_cost (rtx, rtx, rtx, int);
383 static int mips_issue_rate (void);
384 static int mips_multipass_dfa_lookahead (void);
385 static void mips_init_libfuncs (void);
386 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
388 static tree mips_build_builtin_va_list (void);
389 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
390 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
392 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
394 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
396 static bool mips_valid_pointer_mode (enum machine_mode);
397 static bool mips_vector_mode_supported_p (enum machine_mode);
398 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
399 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
400 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
401 static void mips_init_builtins (void);
402 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
403 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
404 enum insn_code, enum mips_fp_condition,
406 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
407 enum insn_code, enum mips_fp_condition,
409 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
410 static void mips_encode_section_info (tree, rtx, int);
411 static void mips_extra_live_on_entry (bitmap);
412 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
414 /* Structure to be filled in by compute_frame_size with register
415 save masks, and offsets for the current function. */
417 struct mips_frame_info GTY(())
419 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
420 HOST_WIDE_INT var_size; /* # bytes that variables take up */
421 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
422 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
423 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
424 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
425 unsigned int mask; /* mask of saved gp registers */
426 unsigned int fmask; /* mask of saved fp registers */
427 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
428 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
429 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
430 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
431 bool initialized; /* true if frame size already calculated */
432 int num_gp; /* number of gp registers saved */
433 int num_fp; /* number of fp registers saved */
436 struct machine_function GTY(()) {
437 /* Pseudo-reg holding the value of $28 in a mips16 function which
438 refers to GP relative global variables. */
439 rtx mips16_gp_pseudo_rtx;
441 /* The number of extra stack bytes taken up by register varargs.
442 This area is allocated by the callee at the very top of the frame. */
445 /* Current frame information, calculated by compute_frame_size. */
446 struct mips_frame_info frame;
448 /* The register to use as the global pointer within this function. */
449 unsigned int global_pointer;
451 /* True if mips_adjust_insn_length should ignore an instruction's
453 bool ignore_hazard_length_p;
455 /* True if the whole function is suitable for .set noreorder and
457 bool all_noreorder_p;
459 /* True if the function is known to have an instruction that needs $gp. */
463 /* Information about a single argument. */
466 /* True if the argument is passed in a floating-point register, or
467 would have been if we hadn't run out of registers. */
470 /* The number of words passed in registers, rounded up. */
471 unsigned int reg_words;
473 /* For EABI, the offset of the first register from GP_ARG_FIRST or
474 FP_ARG_FIRST. For other ABIs, the offset of the first register from
475 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
476 comment for details).
478 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
480 unsigned int reg_offset;
482 /* The number of words that must be passed on the stack, rounded up. */
483 unsigned int stack_words;
485 /* The offset from the start of the stack overflow area of the argument's
486 first stack word. Only meaningful when STACK_WORDS is nonzero. */
487 unsigned int stack_offset;
491 /* Information about an address described by mips_address_type.
497 REG is the base register and OFFSET is the constant offset.
500 REG is the register that contains the high part of the address,
501 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
502 is the type of OFFSET's symbol.
505 SYMBOL_TYPE is the type of symbol being referenced. */
507 struct mips_address_info
509 enum mips_address_type type;
512 enum mips_symbol_type symbol_type;
516 /* One stage in a constant building sequence. These sequences have
520 A = A CODE[1] VALUE[1]
521 A = A CODE[2] VALUE[2]
524 where A is an accumulator, each CODE[i] is a binary rtl operation
525 and each VALUE[i] is a constant integer. */
526 struct mips_integer_op {
528 unsigned HOST_WIDE_INT value;
532 /* The largest number of operations needed to load an integer constant.
533 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
534 When the lowest bit is clear, we can try, but reject a sequence with
535 an extra SLL at the end. */
536 #define MIPS_MAX_INTEGER_OPS 7
539 /* Global variables for machine-dependent things. */
541 /* Threshold for data being put into the small data/bss area, instead
542 of the normal data area. */
543 int mips_section_threshold = -1;
545 /* Count the number of .file directives, so that .loc is up to date. */
546 int num_source_filenames = 0;
548 /* Count the number of sdb related labels are generated (to find block
549 start and end boundaries). */
550 int sdb_label_count = 0;
552 /* Next label # for each statement for Silicon Graphics IRIS systems. */
555 /* Linked list of all externals that are to be emitted when optimizing
556 for the global pointer if they haven't been declared by the end of
557 the program with an appropriate .comm or initialization. */
559 struct extern_list GTY (())
561 struct extern_list *next; /* next external */
562 const char *name; /* name of the external */
563 int size; /* size in bytes */
566 static GTY (()) struct extern_list *extern_head = 0;
568 /* Name of the file containing the current function. */
569 const char *current_function_file = "";
571 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
577 /* The next branch instruction is a branch likely, not branch normal. */
578 int mips_branch_likely;
580 /* The operands passed to the last cmpMM expander. */
583 /* The target cpu for code generation. */
584 enum processor_type mips_arch;
585 const struct mips_cpu_info *mips_arch_info;
587 /* The target cpu for optimization and scheduling. */
588 enum processor_type mips_tune;
589 const struct mips_cpu_info *mips_tune_info;
591 /* Which instruction set architecture to use. */
594 /* Which ABI to use. */
595 int mips_abi = MIPS_ABI_DEFAULT;
597 /* Cost information to use. */
598 const struct mips_rtx_cost_data *mips_cost;
600 /* Whether we are generating mips16 hard float code. In mips16 mode
601 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
602 -msoft-float was not specified by the user, which means that we
603 should arrange to call mips32 hard floating point code. */
604 int mips16_hard_float;
606 /* The architecture selected by -mipsN. */
607 static const struct mips_cpu_info *mips_isa_info;
609 /* If TRUE, we split addresses into their high and low parts in the RTL. */
610 int mips_split_addresses;
612 /* Mode used for saving/restoring general purpose registers. */
613 static enum machine_mode gpr_mode;
615 /* Array giving truth value on whether or not a given hard register
616 can support a given mode. */
617 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
619 /* List of all MIPS punctuation characters used by print_operand. */
620 char mips_print_operand_punct[256];
622 /* Map GCC register number to debugger register number. */
623 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
625 /* A copy of the original flag_delayed_branch: see override_options. */
626 static int mips_flag_delayed_branch;
628 static GTY (()) int mips_output_filename_first_time = 1;
630 /* mips_split_p[X] is true if symbols of type X can be split by
631 mips_split_symbol(). */
632 bool mips_split_p[NUM_SYMBOL_TYPES];
634 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
635 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
636 if they are matched by a special .md file pattern. */
637 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
639 /* Likewise for HIGHs. */
640 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
642 /* Map hard register number to register class */
643 const enum reg_class mips_regno_to_class[] =
645 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
646 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
649 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
650 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
651 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
652 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
659 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
660 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
661 HI_REG, LO_REG, NO_REGS, ST_REGS,
662 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
663 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
664 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
671 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
672 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
679 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
680 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
687 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
688 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
689 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
690 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
691 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
694 /* Table of machine dependent attributes. */
695 const struct attribute_spec mips_attribute_table[] =
697 { "long_call", 0, 0, false, true, true, NULL },
698 { NULL, 0, 0, false, false, false, NULL }
701 /* A table describing all the processors gcc knows about. Names are
702 matched in the order listed. The first mention of an ISA level is
703 taken as the canonical name for that ISA.
705 To ease comparison, please keep this table in the same order as
706 gas's mips_cpu_info_table[]. */
707 const struct mips_cpu_info mips_cpu_info_table[] = {
708 /* Entries for generic ISAs */
709 { "mips1", PROCESSOR_R3000, 1 },
710 { "mips2", PROCESSOR_R6000, 2 },
711 { "mips3", PROCESSOR_R4000, 3 },
712 { "mips4", PROCESSOR_R8000, 4 },
713 { "mips32", PROCESSOR_4KC, 32 },
714 { "mips32r2", PROCESSOR_M4K, 33 },
715 { "mips64", PROCESSOR_5KC, 64 },
718 { "r3000", PROCESSOR_R3000, 1 },
719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
720 { "r3900", PROCESSOR_R3900, 1 },
723 { "r6000", PROCESSOR_R6000, 2 },
726 { "r4000", PROCESSOR_R4000, 3 },
727 { "vr4100", PROCESSOR_R4100, 3 },
728 { "vr4111", PROCESSOR_R4111, 3 },
729 { "vr4120", PROCESSOR_R4120, 3 },
730 { "vr4130", PROCESSOR_R4130, 3 },
731 { "vr4300", PROCESSOR_R4300, 3 },
732 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
733 { "r4600", PROCESSOR_R4600, 3 },
734 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
735 { "r4650", PROCESSOR_R4650, 3 },
738 { "r8000", PROCESSOR_R8000, 4 },
739 { "vr5000", PROCESSOR_R5000, 4 },
740 { "vr5400", PROCESSOR_R5400, 4 },
741 { "vr5500", PROCESSOR_R5500, 4 },
742 { "rm7000", PROCESSOR_R7000, 4 },
743 { "rm9000", PROCESSOR_R9000, 4 },
746 { "4kc", PROCESSOR_4KC, 32 },
747 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
748 { "4kp", PROCESSOR_4KP, 32 },
750 /* MIPS32 Release 2 */
751 { "m4k", PROCESSOR_M4K, 33 },
752 { "24k", PROCESSOR_24K, 33 },
753 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
754 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
755 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
758 { "5kc", PROCESSOR_5KC, 64 },
759 { "5kf", PROCESSOR_5KF, 64 },
760 { "20kc", PROCESSOR_20KC, 64 },
761 { "sb1", PROCESSOR_SB1, 64 },
762 { "sb1a", PROCESSOR_SB1A, 64 },
763 { "sr71000", PROCESSOR_SR71000, 64 },
769 /* Default costs. If these are used for a processor we should look
770 up the actual costs. */
771 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
772 COSTS_N_INSNS (7), /* fp_mult_sf */ \
773 COSTS_N_INSNS (8), /* fp_mult_df */ \
774 COSTS_N_INSNS (23), /* fp_div_sf */ \
775 COSTS_N_INSNS (36), /* fp_div_df */ \
776 COSTS_N_INSNS (10), /* int_mult_si */ \
777 COSTS_N_INSNS (10), /* int_mult_di */ \
778 COSTS_N_INSNS (69), /* int_div_si */ \
779 COSTS_N_INSNS (69), /* int_div_di */ \
780 2, /* branch_cost */ \
781 4 /* memory_latency */
783 /* Need to replace these with the costs of calling the appropriate
785 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
786 COSTS_N_INSNS (256), /* fp_mult_sf */ \
787 COSTS_N_INSNS (256), /* fp_mult_df */ \
788 COSTS_N_INSNS (256), /* fp_div_sf */ \
789 COSTS_N_INSNS (256) /* fp_div_df */
791 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
794 COSTS_N_INSNS (2), /* fp_add */
795 COSTS_N_INSNS (4), /* fp_mult_sf */
796 COSTS_N_INSNS (5), /* fp_mult_df */
797 COSTS_N_INSNS (12), /* fp_div_sf */
798 COSTS_N_INSNS (19), /* fp_div_df */
799 COSTS_N_INSNS (12), /* int_mult_si */
800 COSTS_N_INSNS (12), /* int_mult_di */
801 COSTS_N_INSNS (35), /* int_div_si */
802 COSTS_N_INSNS (35), /* int_div_di */
804 4 /* memory_latency */
809 COSTS_N_INSNS (6), /* int_mult_si */
810 COSTS_N_INSNS (6), /* int_mult_di */
811 COSTS_N_INSNS (36), /* int_div_si */
812 COSTS_N_INSNS (36), /* int_div_di */
814 4 /* memory_latency */
818 COSTS_N_INSNS (36), /* int_mult_si */
819 COSTS_N_INSNS (36), /* int_mult_di */
820 COSTS_N_INSNS (37), /* int_div_si */
821 COSTS_N_INSNS (37), /* int_div_di */
823 4 /* memory_latency */
827 COSTS_N_INSNS (4), /* int_mult_si */
828 COSTS_N_INSNS (11), /* int_mult_di */
829 COSTS_N_INSNS (36), /* int_div_si */
830 COSTS_N_INSNS (68), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (4), /* int_mult_si */
841 COSTS_N_INSNS (11), /* int_mult_di */
842 COSTS_N_INSNS (36), /* int_div_si */
843 COSTS_N_INSNS (68), /* int_div_di */
845 4 /* memory_latency */
851 COSTS_N_INSNS (8), /* fp_add */
852 COSTS_N_INSNS (8), /* fp_mult_sf */
853 COSTS_N_INSNS (10), /* fp_mult_df */
854 COSTS_N_INSNS (34), /* fp_div_sf */
855 COSTS_N_INSNS (64), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
864 COSTS_N_INSNS (4), /* fp_add */
865 COSTS_N_INSNS (4), /* fp_mult_sf */
866 COSTS_N_INSNS (5), /* fp_mult_df */
867 COSTS_N_INSNS (17), /* fp_div_sf */
868 COSTS_N_INSNS (32), /* fp_div_df */
869 COSTS_N_INSNS (5), /* int_mult_si */
870 COSTS_N_INSNS (5), /* int_mult_di */
871 COSTS_N_INSNS (41), /* int_div_si */
872 COSTS_N_INSNS (41), /* int_div_di */
874 4 /* memory_latency */
880 COSTS_N_INSNS (2), /* fp_add */
881 COSTS_N_INSNS (4), /* fp_mult_sf */
882 COSTS_N_INSNS (5), /* fp_mult_df */
883 COSTS_N_INSNS (12), /* fp_div_sf */
884 COSTS_N_INSNS (19), /* fp_div_df */
885 COSTS_N_INSNS (2), /* int_mult_si */
886 COSTS_N_INSNS (2), /* int_mult_di */
887 COSTS_N_INSNS (35), /* int_div_si */
888 COSTS_N_INSNS (35), /* int_div_di */
890 4 /* memory_latency */
893 COSTS_N_INSNS (3), /* fp_add */
894 COSTS_N_INSNS (5), /* fp_mult_sf */
895 COSTS_N_INSNS (6), /* fp_mult_df */
896 COSTS_N_INSNS (15), /* fp_div_sf */
897 COSTS_N_INSNS (16), /* fp_div_df */
898 COSTS_N_INSNS (17), /* int_mult_si */
899 COSTS_N_INSNS (17), /* int_mult_di */
900 COSTS_N_INSNS (38), /* int_div_si */
901 COSTS_N_INSNS (38), /* int_div_di */
903 6 /* memory_latency */
906 COSTS_N_INSNS (6), /* fp_add */
907 COSTS_N_INSNS (7), /* fp_mult_sf */
908 COSTS_N_INSNS (8), /* fp_mult_df */
909 COSTS_N_INSNS (23), /* fp_div_sf */
910 COSTS_N_INSNS (36), /* fp_div_df */
911 COSTS_N_INSNS (10), /* int_mult_si */
912 COSTS_N_INSNS (10), /* int_mult_di */
913 COSTS_N_INSNS (69), /* int_div_si */
914 COSTS_N_INSNS (69), /* int_div_di */
916 6 /* memory_latency */
928 /* The only costs that appear to be updated here are
929 integer multiplication. */
931 COSTS_N_INSNS (4), /* int_mult_si */
932 COSTS_N_INSNS (6), /* int_mult_di */
933 COSTS_N_INSNS (69), /* int_div_si */
934 COSTS_N_INSNS (69), /* int_div_di */
936 4 /* memory_latency */
948 COSTS_N_INSNS (6), /* fp_add */
949 COSTS_N_INSNS (4), /* fp_mult_sf */
950 COSTS_N_INSNS (5), /* fp_mult_df */
951 COSTS_N_INSNS (23), /* fp_div_sf */
952 COSTS_N_INSNS (36), /* fp_div_df */
953 COSTS_N_INSNS (5), /* int_mult_si */
954 COSTS_N_INSNS (5), /* int_mult_di */
955 COSTS_N_INSNS (36), /* int_div_si */
956 COSTS_N_INSNS (36), /* int_div_di */
958 4 /* memory_latency */
961 COSTS_N_INSNS (6), /* fp_add */
962 COSTS_N_INSNS (5), /* fp_mult_sf */
963 COSTS_N_INSNS (6), /* fp_mult_df */
964 COSTS_N_INSNS (30), /* fp_div_sf */
965 COSTS_N_INSNS (59), /* fp_div_df */
966 COSTS_N_INSNS (3), /* int_mult_si */
967 COSTS_N_INSNS (4), /* int_mult_di */
968 COSTS_N_INSNS (42), /* int_div_si */
969 COSTS_N_INSNS (74), /* int_div_di */
971 4 /* memory_latency */
974 COSTS_N_INSNS (6), /* fp_add */
975 COSTS_N_INSNS (5), /* fp_mult_sf */
976 COSTS_N_INSNS (6), /* fp_mult_df */
977 COSTS_N_INSNS (30), /* fp_div_sf */
978 COSTS_N_INSNS (59), /* fp_div_df */
979 COSTS_N_INSNS (5), /* int_mult_si */
980 COSTS_N_INSNS (9), /* int_mult_di */
981 COSTS_N_INSNS (42), /* int_div_si */
982 COSTS_N_INSNS (74), /* int_div_di */
984 4 /* memory_latency */
987 /* The only costs that are changed here are
988 integer multiplication. */
989 COSTS_N_INSNS (6), /* fp_add */
990 COSTS_N_INSNS (7), /* fp_mult_sf */
991 COSTS_N_INSNS (8), /* fp_mult_df */
992 COSTS_N_INSNS (23), /* fp_div_sf */
993 COSTS_N_INSNS (36), /* fp_div_df */
994 COSTS_N_INSNS (5), /* int_mult_si */
995 COSTS_N_INSNS (9), /* int_mult_di */
996 COSTS_N_INSNS (69), /* int_div_si */
997 COSTS_N_INSNS (69), /* int_div_di */
999 4 /* memory_latency */
1005 /* The only costs that are changed here are
1006 integer multiplication. */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (7), /* fp_mult_sf */
1009 COSTS_N_INSNS (8), /* fp_mult_df */
1010 COSTS_N_INSNS (23), /* fp_div_sf */
1011 COSTS_N_INSNS (36), /* fp_div_df */
1012 COSTS_N_INSNS (3), /* int_mult_si */
1013 COSTS_N_INSNS (8), /* int_mult_di */
1014 COSTS_N_INSNS (69), /* int_div_si */
1015 COSTS_N_INSNS (69), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1020 /* These costs are the same as the SB-1A below. */
1021 COSTS_N_INSNS (4), /* fp_add */
1022 COSTS_N_INSNS (4), /* fp_mult_sf */
1023 COSTS_N_INSNS (4), /* fp_mult_df */
1024 COSTS_N_INSNS (24), /* fp_div_sf */
1025 COSTS_N_INSNS (32), /* fp_div_df */
1026 COSTS_N_INSNS (3), /* int_mult_si */
1027 COSTS_N_INSNS (4), /* int_mult_di */
1028 COSTS_N_INSNS (36), /* int_div_si */
1029 COSTS_N_INSNS (68), /* int_div_di */
1030 1, /* branch_cost */
1031 4 /* memory_latency */
1034 /* These costs are the same as the SB-1 above. */
1035 COSTS_N_INSNS (4), /* fp_add */
1036 COSTS_N_INSNS (4), /* fp_mult_sf */
1037 COSTS_N_INSNS (4), /* fp_mult_df */
1038 COSTS_N_INSNS (24), /* fp_div_sf */
1039 COSTS_N_INSNS (32), /* fp_div_df */
1040 COSTS_N_INSNS (3), /* int_mult_si */
1041 COSTS_N_INSNS (4), /* int_mult_di */
1042 COSTS_N_INSNS (36), /* int_div_si */
1043 COSTS_N_INSNS (68), /* int_div_di */
1044 1, /* branch_cost */
1045 4 /* memory_latency */
1053 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1054 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1055 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1058 /* Initialize the GCC target structure. */
1059 #undef TARGET_ASM_ALIGNED_HI_OP
1060 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1061 #undef TARGET_ASM_ALIGNED_SI_OP
1062 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1063 #undef TARGET_ASM_ALIGNED_DI_OP
1064 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1066 #undef TARGET_ASM_FUNCTION_PROLOGUE
1067 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1068 #undef TARGET_ASM_FUNCTION_EPILOGUE
1069 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1070 #undef TARGET_ASM_SELECT_RTX_SECTION
1071 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1072 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1073 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1075 #undef TARGET_SCHED_REORDER
1076 #define TARGET_SCHED_REORDER mips_sched_reorder
1077 #undef TARGET_SCHED_VARIABLE_ISSUE
1078 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1079 #undef TARGET_SCHED_ADJUST_COST
1080 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1081 #undef TARGET_SCHED_ISSUE_RATE
1082 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1083 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1084 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1085 mips_multipass_dfa_lookahead
1087 #undef TARGET_DEFAULT_TARGET_FLAGS
1088 #define TARGET_DEFAULT_TARGET_FLAGS \
1090 | TARGET_CPU_DEFAULT \
1091 | TARGET_ENDIAN_DEFAULT \
1092 | TARGET_FP_EXCEPTIONS_DEFAULT \
1093 | MASK_CHECK_ZERO_DIV \
1095 #undef TARGET_HANDLE_OPTION
1096 #define TARGET_HANDLE_OPTION mips_handle_option
1098 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1099 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1101 #undef TARGET_VALID_POINTER_MODE
1102 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1103 #undef TARGET_RTX_COSTS
1104 #define TARGET_RTX_COSTS mips_rtx_costs
1105 #undef TARGET_ADDRESS_COST
1106 #define TARGET_ADDRESS_COST mips_address_cost
1108 #undef TARGET_IN_SMALL_DATA_P
1109 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1111 #undef TARGET_MACHINE_DEPENDENT_REORG
1112 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1114 #undef TARGET_ASM_FILE_START
1115 #undef TARGET_ASM_FILE_END
1116 #define TARGET_ASM_FILE_START mips_file_start
1117 #define TARGET_ASM_FILE_END mips_file_end
1118 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1119 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1121 #undef TARGET_INIT_LIBFUNCS
1122 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1124 #undef TARGET_BUILD_BUILTIN_VA_LIST
1125 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1126 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1127 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1129 #undef TARGET_PROMOTE_FUNCTION_ARGS
1130 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1131 #undef TARGET_PROMOTE_FUNCTION_RETURN
1132 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1133 #undef TARGET_PROMOTE_PROTOTYPES
1134 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1136 #undef TARGET_RETURN_IN_MEMORY
1137 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1138 #undef TARGET_RETURN_IN_MSB
1139 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1141 #undef TARGET_ASM_OUTPUT_MI_THUNK
1142 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1143 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1144 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1146 #undef TARGET_SETUP_INCOMING_VARARGS
1147 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1148 #undef TARGET_STRICT_ARGUMENT_NAMING
1149 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1150 #undef TARGET_MUST_PASS_IN_STACK
1151 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1152 #undef TARGET_PASS_BY_REFERENCE
1153 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1154 #undef TARGET_CALLEE_COPIES
1155 #define TARGET_CALLEE_COPIES mips_callee_copies
1156 #undef TARGET_ARG_PARTIAL_BYTES
1157 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1159 #undef TARGET_MODE_REP_EXTENDED
1160 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1162 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1163 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1165 #undef TARGET_INIT_BUILTINS
1166 #define TARGET_INIT_BUILTINS mips_init_builtins
1167 #undef TARGET_EXPAND_BUILTIN
1168 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1170 #undef TARGET_HAVE_TLS
1171 #define TARGET_HAVE_TLS HAVE_AS_TLS
1173 #undef TARGET_CANNOT_FORCE_CONST_MEM
1174 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1176 #undef TARGET_ENCODE_SECTION_INFO
1177 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1179 #undef TARGET_ATTRIBUTE_TABLE
1180 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1182 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1183 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1185 #undef TARGET_MIN_ANCHOR_OFFSET
1186 #define TARGET_MIN_ANCHOR_OFFSET -32768
1187 #undef TARGET_MAX_ANCHOR_OFFSET
1188 #define TARGET_MAX_ANCHOR_OFFSET 32767
1189 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1190 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1191 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1192 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1194 struct gcc_target targetm = TARGET_INITIALIZER;
1196 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1198 static enum mips_symbol_type
1199 mips_classify_symbol (rtx x)
1201 if (GET_CODE (x) == LABEL_REF)
1204 return SYMBOL_CONSTANT_POOL;
1205 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1206 return SYMBOL_GOT_LOCAL;
1207 return SYMBOL_GENERAL;
1210 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1212 if (SYMBOL_REF_TLS_MODEL (x))
1215 if (CONSTANT_POOL_ADDRESS_P (x))
1218 return SYMBOL_CONSTANT_POOL;
1220 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1221 return SYMBOL_SMALL_DATA;
1224 /* Do not use small-data accesses for weak symbols; they may end up
1226 if (SYMBOL_REF_SMALL_P (x)
1227 && !SYMBOL_REF_WEAK (x))
1228 return SYMBOL_SMALL_DATA;
1230 if (TARGET_ABICALLS)
1232 if (SYMBOL_REF_DECL (x) == 0)
1234 if (!SYMBOL_REF_LOCAL_P (x))
1235 return SYMBOL_GOT_GLOBAL;
1239 /* Don't use GOT accesses for locally-binding symbols if
1240 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three
1243 - o32 PIC (either with or without explicit relocs)
1244 - n32/n64 PIC without explicit relocs
1245 - n32/n64 PIC with explicit relocs
1247 In the first case, both local and global accesses will use an
1248 R_MIPS_GOT16 relocation. We must correctly predict which of
1249 the two semantics (local or global) the assembler and linker
1250 will apply. The choice doesn't depend on the symbol's
1251 visibility, so we deliberately ignore decl_visibility and
1254 In the second case, the assembler will not use R_MIPS_GOT16
1255 relocations, but it chooses between local and global accesses
1256 in the same way as for o32 PIC.
1258 In the third case we have more freedom since both forms of
1259 access will work for any kind of symbol. However, there seems
1260 little point in doing things differently. */
1261 if (DECL_P (SYMBOL_REF_DECL (x))
1262 && TREE_PUBLIC (SYMBOL_REF_DECL (x))
1263 && !(TARGET_ABSOLUTE_ABICALLS
1264 && targetm.binds_local_p (SYMBOL_REF_DECL (x))))
1265 return SYMBOL_GOT_GLOBAL;
1268 if (!TARGET_ABSOLUTE_ABICALLS)
1269 return SYMBOL_GOT_LOCAL;
1272 return SYMBOL_GENERAL;
1276 /* Split X into a base and a constant offset, storing them in *BASE
1277 and *OFFSET respectively. */
1280 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1284 if (GET_CODE (x) == CONST)
1287 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1289 *offset += INTVAL (XEXP (x, 1));
1296 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1297 to the same object as SYMBOL, or to the same object_block. */
1300 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1302 if (GET_CODE (symbol) != SYMBOL_REF)
1305 if (CONSTANT_POOL_ADDRESS_P (symbol)
1307 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1310 if (SYMBOL_REF_DECL (symbol) != 0
1312 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1315 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
1316 && SYMBOL_REF_BLOCK (symbol)
1317 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
1318 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
1319 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
1326 /* Return true if X is a symbolic constant that can be calculated in
1327 the same way as a bare symbol. If it is, store the type of the
1328 symbol in *SYMBOL_TYPE. */
1331 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1333 HOST_WIDE_INT offset;
1335 mips_split_const (x, &x, &offset);
1336 if (UNSPEC_ADDRESS_P (x))
1337 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1338 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1340 *symbol_type = mips_classify_symbol (x);
1341 if (*symbol_type == SYMBOL_TLS)
1350 /* Check whether a nonzero offset is valid for the underlying
1352 switch (*symbol_type)
1354 case SYMBOL_GENERAL:
1355 case SYMBOL_64_HIGH:
1358 /* If the target has 64-bit pointers and the object file only
1359 supports 32-bit symbols, the values of those symbols will be
1360 sign-extended. In this case we can't allow an arbitrary offset
1361 in case the 32-bit value X + OFFSET has a different sign from X. */
1362 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1363 return mips_offset_within_object_p (x, offset);
1365 /* In other cases the relocations can handle any offset. */
1368 case SYMBOL_CONSTANT_POOL:
1369 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1370 In this case, we no longer have access to the underlying constant,
1371 but the original symbol-based access was known to be valid. */
1372 if (GET_CODE (x) == LABEL_REF)
1377 case SYMBOL_SMALL_DATA:
1378 /* Make sure that the offset refers to something within the
1379 underlying object. This should guarantee that the final
1380 PC- or GP-relative offset is within the 16-bit limit. */
1381 return mips_offset_within_object_p (x, offset);
1383 case SYMBOL_GOT_LOCAL:
1384 case SYMBOL_GOTOFF_PAGE:
1385 /* The linker should provide enough local GOT entries for a
1386 16-bit offset. Larger offsets may lead to GOT overflow. */
1387 return SMALL_OPERAND (offset);
1389 case SYMBOL_GOT_GLOBAL:
1390 case SYMBOL_GOTOFF_GLOBAL:
1391 case SYMBOL_GOTOFF_CALL:
1392 case SYMBOL_GOTOFF_LOADGP:
1397 case SYMBOL_GOTTPREL:
1405 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1408 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1410 if (regno >= FIRST_PSEUDO_REGISTER)
1414 regno = reg_renumber[regno];
1417 /* These fake registers will be eliminated to either the stack or
1418 hard frame pointer, both of which are usually valid base registers.
1419 Reload deals with the cases where the eliminated form isn't valid. */
1420 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1423 /* In mips16 mode, the stack pointer can only address word and doubleword
1424 values, nothing smaller. There are two problems here:
1426 (a) Instantiating virtual registers can introduce new uses of the
1427 stack pointer. If these virtual registers are valid addresses,
1428 the stack pointer should be too.
1430 (b) Most uses of the stack pointer are not made explicit until
1431 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1432 We don't know until that stage whether we'll be eliminating to the
1433 stack pointer (which needs the restriction) or the hard frame
1434 pointer (which doesn't).
1436 All in all, it seems more consistent to only enforce this restriction
1437 during and after reload. */
1438 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1439 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1441 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1445 /* Return true if X is a valid base register for the given mode.
1446 Allow only hard registers if STRICT. */
1449 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1451 if (!strict && GET_CODE (x) == SUBREG)
1455 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1459 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1460 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1463 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1464 enum machine_mode mode)
1466 switch (symbol_type)
1468 case SYMBOL_GENERAL:
1469 return !TARGET_MIPS16;
1471 case SYMBOL_SMALL_DATA:
1474 case SYMBOL_CONSTANT_POOL:
1475 /* PC-relative addressing is only available for lw and ld. */
1476 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1478 case SYMBOL_GOT_LOCAL:
1481 case SYMBOL_GOT_GLOBAL:
1482 /* The address will have to be loaded from the GOT first. */
1485 case SYMBOL_GOTOFF_PAGE:
1486 case SYMBOL_GOTOFF_GLOBAL:
1487 case SYMBOL_GOTOFF_CALL:
1488 case SYMBOL_GOTOFF_LOADGP:
1493 case SYMBOL_GOTTPREL:
1495 case SYMBOL_64_HIGH:
1504 /* Return true if X is a valid address for machine mode MODE. If it is,
1505 fill in INFO appropriately. STRICT is true if we should only accept
1506 hard base registers. */
1509 mips_classify_address (struct mips_address_info *info, rtx x,
1510 enum machine_mode mode, int strict)
1512 switch (GET_CODE (x))
1516 info->type = ADDRESS_REG;
1518 info->offset = const0_rtx;
1519 return mips_valid_base_register_p (info->reg, mode, strict);
1522 info->type = ADDRESS_REG;
1523 info->reg = XEXP (x, 0);
1524 info->offset = XEXP (x, 1);
1525 return (mips_valid_base_register_p (info->reg, mode, strict)
1526 && const_arith_operand (info->offset, VOIDmode));
1529 info->type = ADDRESS_LO_SUM;
1530 info->reg = XEXP (x, 0);
1531 info->offset = XEXP (x, 1);
1532 return (mips_valid_base_register_p (info->reg, mode, strict)
1533 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1534 && mips_symbolic_address_p (info->symbol_type, mode)
1535 && mips_lo_relocs[info->symbol_type] != 0);
1538 /* Small-integer addresses don't occur very often, but they
1539 are legitimate if $0 is a valid base register. */
1540 info->type = ADDRESS_CONST_INT;
1541 return !TARGET_MIPS16 && SMALL_INT (x);
1546 info->type = ADDRESS_SYMBOLIC;
1547 return (mips_symbolic_constant_p (x, &info->symbol_type)
1548 && mips_symbolic_address_p (info->symbol_type, mode)
1549 && !mips_split_p[info->symbol_type]);
1556 /* Return true if X is a thread-local symbol. */
1559 mips_tls_operand_p (rtx x)
1561 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1564 /* Return true if X can not be forced into a constant pool. */
1567 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1569 return mips_tls_operand_p (*x);
1572 /* Return true if X can not be forced into a constant pool. */
1575 mips_cannot_force_const_mem (rtx x)
1578 HOST_WIDE_INT offset;
1582 /* As an optimization, reject constants that mips_legitimize_move
1585 Suppose we have a multi-instruction sequence that loads constant C
1586 into register R. If R does not get allocated a hard register, and
1587 R is used in an operand that allows both registers and memory
1588 references, reload will consider forcing C into memory and using
1589 one of the instruction's memory alternatives. Returning false
1590 here will force it to use an input reload instead. */
1591 if (GET_CODE (x) == CONST_INT)
1594 mips_split_const (x, &base, &offset);
1595 if (symbolic_operand (base, VOIDmode) && SMALL_OPERAND (offset))
1599 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1605 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1606 constant pools, but normal-mode code doesn't need to. */
1609 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1610 rtx x ATTRIBUTE_UNUSED)
1612 return !TARGET_MIPS16;
1615 /* Return the number of instructions needed to load a symbol of the
1616 given type into a register. If valid in an address, the same number
1617 of instructions are needed for loads and stores. Treat extended
1618 mips16 instructions as two instructions. */
1621 mips_symbol_insns (enum mips_symbol_type type)
1625 case SYMBOL_GENERAL:
1626 /* In mips16 code, general symbols must be fetched from the
1631 /* When using 64-bit symbols, we need 5 preparatory instructions,
1634 lui $at,%highest(symbol)
1635 daddiu $at,$at,%higher(symbol)
1637 daddiu $at,$at,%hi(symbol)
1640 The final address is then $at + %lo(symbol). With 32-bit
1641 symbols we just need a preparatory lui. */
1642 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1644 case SYMBOL_SMALL_DATA:
1647 case SYMBOL_CONSTANT_POOL:
1648 /* This case is for mips16 only. Assume we'll need an
1649 extended instruction. */
1652 case SYMBOL_GOT_LOCAL:
1653 case SYMBOL_GOT_GLOBAL:
1654 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1655 the local/global classification is accurate. See override_options
1658 The worst cases are:
1660 (1) For local symbols when generating o32 or o64 code. The assembler
1666 ...and the final address will be $at + %lo(symbol).
1668 (2) For global symbols when -mxgot. The assembler will use:
1670 lui $at,%got_hi(symbol)
1673 ...and the final address will be $at + %got_lo(symbol). */
1676 case SYMBOL_GOTOFF_PAGE:
1677 case SYMBOL_GOTOFF_GLOBAL:
1678 case SYMBOL_GOTOFF_CALL:
1679 case SYMBOL_GOTOFF_LOADGP:
1680 case SYMBOL_64_HIGH:
1686 case SYMBOL_GOTTPREL:
1688 /* Check whether the offset is a 16- or 32-bit value. */
1689 return mips_split_p[type] ? 2 : 1;
1692 /* We don't treat a bare TLS symbol as a constant. */
1698 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1701 mips_stack_address_p (rtx x, enum machine_mode mode)
1703 struct mips_address_info addr;
1705 return (mips_classify_address (&addr, x, mode, false)
1706 && addr.type == ADDRESS_REG
1707 && addr.reg == stack_pointer_rtx);
1710 /* Return true if a value at OFFSET bytes from BASE can be accessed
1711 using an unextended mips16 instruction. MODE is the mode of the
1714 Usually the offset in an unextended instruction is a 5-bit field.
1715 The offset is unsigned and shifted left once for HIs, twice
1716 for SIs, and so on. An exception is SImode accesses off the
1717 stack pointer, which have an 8-bit immediate field. */
1720 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1723 && GET_CODE (offset) == CONST_INT
1724 && INTVAL (offset) >= 0
1725 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1727 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1728 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1729 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1735 /* Return the number of instructions needed to load or store a value
1736 of mode MODE at X. Return 0 if X isn't valid for MODE.
1738 For mips16 code, count extended instructions as two instructions. */
1741 mips_address_insns (rtx x, enum machine_mode mode)
1743 struct mips_address_info addr;
1746 if (mode == BLKmode)
1747 /* BLKmode is used for single unaligned loads and stores. */
1750 /* Each word of a multi-word value will be accessed individually. */
1751 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1753 if (mips_classify_address (&addr, x, mode, false))
1758 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1762 case ADDRESS_LO_SUM:
1763 return (TARGET_MIPS16 ? factor * 2 : factor);
1765 case ADDRESS_CONST_INT:
1768 case ADDRESS_SYMBOLIC:
1769 return factor * mips_symbol_insns (addr.symbol_type);
1775 /* Likewise for constant X. */
1778 mips_const_insns (rtx x)
1780 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1781 enum mips_symbol_type symbol_type;
1782 HOST_WIDE_INT offset;
1784 switch (GET_CODE (x))
1788 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1789 || !mips_split_p[symbol_type])
1796 /* Unsigned 8-bit constants can be loaded using an unextended
1797 LI instruction. Unsigned 16-bit constants can be loaded
1798 using an extended LI. Negative constants must be loaded
1799 using LI and then negated. */
1800 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1801 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1802 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1803 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1806 return mips_build_integer (codes, INTVAL (x));
1810 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1816 /* See if we can refer to X directly. */
1817 if (mips_symbolic_constant_p (x, &symbol_type))
1818 return mips_symbol_insns (symbol_type);
1820 /* Otherwise try splitting the constant into a base and offset.
1821 16-bit offsets can be added using an extra addiu. Larger offsets
1822 must be calculated separately and then added to the base. */
1823 mips_split_const (x, &x, &offset);
1826 int n = mips_const_insns (x);
1829 if (SMALL_OPERAND (offset))
1832 return n + 1 + mips_build_integer (codes, offset);
1839 return mips_symbol_insns (mips_classify_symbol (x));
1847 /* Return the number of instructions needed for memory reference X.
1848 Count extended mips16 instructions as two instructions. */
1851 mips_fetch_insns (rtx x)
1853 gcc_assert (MEM_P (x));
1854 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1858 /* Return the number of instructions needed for an integer division. */
1861 mips_idiv_insns (void)
1866 if (TARGET_CHECK_ZERO_DIV)
1868 if (GENERATE_DIVIDE_TRAPS)
1874 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1879 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1880 returns a nonzero value if X is a legitimate address for a memory
1881 operand of the indicated MODE. STRICT is nonzero if this function
1882 is called during reload. */
1885 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1887 struct mips_address_info addr;
1889 return mips_classify_address (&addr, x, mode, strict);
1893 /* Copy VALUE to a register and return that register. If new psuedos
1894 are allowed, copy it into a new register, otherwise use DEST. */
1897 mips_force_temporary (rtx dest, rtx value)
1899 if (!no_new_pseudos)
1900 return force_reg (Pmode, value);
1903 emit_move_insn (copy_rtx (dest), value);
1909 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1910 and is used to load the high part into a register. */
1913 mips_split_symbol (rtx temp, rtx addr)
1918 high = mips16_gp_pseudo_reg ();
1920 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1921 return gen_rtx_LO_SUM (Pmode, high, addr);
1925 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1926 type SYMBOL_TYPE. */
1929 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1932 HOST_WIDE_INT offset;
1934 mips_split_const (address, &base, &offset);
1935 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1936 UNSPEC_ADDRESS_FIRST + symbol_type);
1937 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1941 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1942 high part to BASE and return the result. Just return BASE otherwise.
1943 TEMP is available as a temporary register if needed.
1945 The returned expression can be used as the first operand to a LO_SUM. */
1948 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1949 enum mips_symbol_type symbol_type)
1951 if (mips_split_p[symbol_type])
1953 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1954 addr = mips_force_temporary (temp, addr);
1955 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1961 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1962 mips_force_temporary; it is only needed when OFFSET is not a
1966 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1968 if (!SMALL_OPERAND (offset))
1973 /* Load the full offset into a register so that we can use
1974 an unextended instruction for the address itself. */
1975 high = GEN_INT (offset);
1980 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1981 high = GEN_INT (CONST_HIGH_PART (offset));
1982 offset = CONST_LOW_PART (offset);
1984 high = mips_force_temporary (temp, high);
1985 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1987 return plus_constant (reg, offset);
1990 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1991 referencing, and TYPE is the symbol type to use (either global
1992 dynamic or local dynamic). V0 is an RTX for the return value
1993 location. The entire insn sequence is returned. */
1995 static GTY(()) rtx mips_tls_symbol;
1998 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2000 rtx insn, loc, tga, a0;
2002 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2004 if (!mips_tls_symbol)
2005 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2007 loc = mips_unspec_address (sym, type);
2011 emit_insn (gen_rtx_SET (Pmode, a0,
2012 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2013 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2014 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2015 CONST_OR_PURE_CALL_P (insn) = 1;
2016 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2017 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2018 insn = get_insns ();
2025 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2026 return value will be a valid address and move_operand (either a REG
2030 mips_legitimize_tls_address (rtx loc)
2032 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2033 enum tls_model model;
2035 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2036 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2038 model = SYMBOL_REF_TLS_MODEL (loc);
2042 case TLS_MODEL_GLOBAL_DYNAMIC:
2043 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2044 dest = gen_reg_rtx (Pmode);
2045 emit_libcall_block (insn, dest, v0, loc);
2048 case TLS_MODEL_LOCAL_DYNAMIC:
2049 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2050 tmp1 = gen_reg_rtx (Pmode);
2052 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2053 share the LDM result with other LD model accesses. */
2054 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2056 emit_libcall_block (insn, tmp1, v0, eqv);
2058 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2059 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2060 mips_unspec_address (loc, SYMBOL_DTPREL));
2063 case TLS_MODEL_INITIAL_EXEC:
2064 tmp1 = gen_reg_rtx (Pmode);
2065 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2066 if (Pmode == DImode)
2068 emit_insn (gen_tls_get_tp_di (v1));
2069 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2073 emit_insn (gen_tls_get_tp_si (v1));
2074 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2076 dest = gen_reg_rtx (Pmode);
2077 emit_insn (gen_add3_insn (dest, tmp1, v1));
2080 case TLS_MODEL_LOCAL_EXEC:
2082 if (Pmode == DImode)
2083 emit_insn (gen_tls_get_tp_di (v1));
2085 emit_insn (gen_tls_get_tp_si (v1));
2087 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2088 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2089 mips_unspec_address (loc, SYMBOL_TPREL));
2099 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2100 be legitimized in a way that the generic machinery might not expect,
2101 put the new address in *XLOC and return true. MODE is the mode of
2102 the memory being accessed. */
2105 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2107 enum mips_symbol_type symbol_type;
2109 if (mips_tls_operand_p (*xloc))
2111 *xloc = mips_legitimize_tls_address (*xloc);
2115 /* See if the address can split into a high part and a LO_SUM. */
2116 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2117 && mips_symbolic_address_p (symbol_type, mode)
2118 && mips_split_p[symbol_type])
2120 *xloc = mips_split_symbol (0, *xloc);
2124 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2126 /* Handle REG + CONSTANT using mips_add_offset. */
2129 reg = XEXP (*xloc, 0);
2130 if (!mips_valid_base_register_p (reg, mode, 0))
2131 reg = copy_to_mode_reg (Pmode, reg);
2132 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2140 /* Subroutine of mips_build_integer (with the same interface).
2141 Assume that the final action in the sequence should be a left shift. */
2144 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2146 unsigned int i, shift;
2148 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2149 since signed numbers are easier to load than unsigned ones. */
2151 while ((value & 1) == 0)
2152 value /= 2, shift++;
2154 i = mips_build_integer (codes, value);
2155 codes[i].code = ASHIFT;
2156 codes[i].value = shift;
2161 /* As for mips_build_shift, but assume that the final action will be
2162 an IOR or PLUS operation. */
2165 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2167 unsigned HOST_WIDE_INT high;
2170 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2171 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2173 /* The constant is too complex to load with a simple lui/ori pair
2174 so our goal is to clear as many trailing zeros as possible.
2175 In this case, we know bit 16 is set and that the low 16 bits
2176 form a negative number. If we subtract that number from VALUE,
2177 we will clear at least the lowest 17 bits, maybe more. */
2178 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2179 codes[i].code = PLUS;
2180 codes[i].value = CONST_LOW_PART (value);
2184 i = mips_build_integer (codes, high);
2185 codes[i].code = IOR;
2186 codes[i].value = value & 0xffff;
2192 /* Fill CODES with a sequence of rtl operations to load VALUE.
2193 Return the number of operations needed. */
2196 mips_build_integer (struct mips_integer_op *codes,
2197 unsigned HOST_WIDE_INT value)
2199 if (SMALL_OPERAND (value)
2200 || SMALL_OPERAND_UNSIGNED (value)
2201 || LUI_OPERAND (value))
2203 /* The value can be loaded with a single instruction. */
2204 codes[0].code = UNKNOWN;
2205 codes[0].value = value;
2208 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2210 /* Either the constant is a simple LUI/ORI combination or its
2211 lowest bit is set. We don't want to shift in this case. */
2212 return mips_build_lower (codes, value);
2214 else if ((value & 0xffff) == 0)
2216 /* The constant will need at least three actions. The lowest
2217 16 bits are clear, so the final action will be a shift. */
2218 return mips_build_shift (codes, value);
2222 /* The final action could be a shift, add or inclusive OR.
2223 Rather than use a complex condition to select the best
2224 approach, try both mips_build_shift and mips_build_lower
2225 and pick the one that gives the shortest sequence.
2226 Note that this case is only used once per constant. */
2227 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2228 unsigned int cost, alt_cost;
2230 cost = mips_build_shift (codes, value);
2231 alt_cost = mips_build_lower (alt_codes, value);
2232 if (alt_cost < cost)
2234 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2242 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2245 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2247 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2248 enum machine_mode mode;
2249 unsigned int i, cost;
2252 mode = GET_MODE (dest);
2253 cost = mips_build_integer (codes, value);
2255 /* Apply each binary operation to X. Invariant: X is a legitimate
2256 source operand for a SET pattern. */
2257 x = GEN_INT (codes[0].value);
2258 for (i = 1; i < cost; i++)
2262 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2266 x = force_reg (mode, x);
2267 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2270 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2274 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2275 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2279 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2282 HOST_WIDE_INT offset;
2284 /* Split moves of big integers into smaller pieces. */
2285 if (splittable_const_int_operand (src, mode))
2287 mips_move_integer (dest, dest, INTVAL (src));
2291 /* Split moves of symbolic constants into high/low pairs. */
2292 if (splittable_symbolic_operand (src, mode))
2294 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2298 if (mips_tls_operand_p (src))
2300 emit_move_insn (dest, mips_legitimize_tls_address (src));
2304 /* If we have (const (plus symbol offset)), load the symbol first
2305 and then add in the offset. This is usually better than forcing
2306 the constant into memory, at least in non-mips16 code. */
2307 mips_split_const (src, &base, &offset);
2310 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2312 base = mips_force_temporary (dest, base);
2313 emit_move_insn (dest, mips_add_offset (0, base, offset));
2317 src = force_const_mem (mode, src);
2319 /* When using explicit relocs, constant pool references are sometimes
2320 not legitimate addresses. */
2321 if (!memory_operand (src, VOIDmode))
2322 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2323 emit_move_insn (dest, src);
2327 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2328 sequence that is valid. */
2331 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2333 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2335 emit_move_insn (dest, force_reg (mode, src));
2339 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2340 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2341 && REG_P (src) && MD_REG_P (REGNO (src))
2342 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2344 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2345 if (GET_MODE_SIZE (mode) <= 4)
2346 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2347 gen_rtx_REG (SImode, REGNO (src)),
2348 gen_rtx_REG (SImode, other_regno)));
2350 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2351 gen_rtx_REG (DImode, REGNO (src)),
2352 gen_rtx_REG (DImode, other_regno)));
2356 /* We need to deal with constants that would be legitimate
2357 immediate_operands but not legitimate move_operands. */
2358 if (CONSTANT_P (src) && !move_operand (src, mode))
2360 mips_legitimize_const_move (mode, dest, src);
2361 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2367 /* We need a lot of little routines to check constant values on the
2368 mips16. These are used to figure out how long the instruction will
2369 be. It would be much better to do this using constraints, but
2370 there aren't nearly enough letters available. */
2373 m16_check_op (rtx op, int low, int high, int mask)
2375 return (GET_CODE (op) == CONST_INT
2376 && INTVAL (op) >= low
2377 && INTVAL (op) <= high
2378 && (INTVAL (op) & mask) == 0);
2382 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2384 return m16_check_op (op, 0x1, 0x8, 0);
2388 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2390 return m16_check_op (op, - 0x8, 0x7, 0);
2394 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2396 return m16_check_op (op, - 0x7, 0x8, 0);
2400 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2402 return m16_check_op (op, - 0x10, 0xf, 0);
2406 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2408 return m16_check_op (op, - 0xf, 0x10, 0);
2412 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2414 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2418 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2420 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2424 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2426 return m16_check_op (op, - 0x80, 0x7f, 0);
2430 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2432 return m16_check_op (op, - 0x7f, 0x80, 0);
2436 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2438 return m16_check_op (op, 0x0, 0xff, 0);
2442 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2444 return m16_check_op (op, - 0xff, 0x0, 0);
2448 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2450 return m16_check_op (op, - 0x1, 0xfe, 0);
2454 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2456 return m16_check_op (op, 0x0, 0xff << 2, 3);
2460 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2462 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2466 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2468 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2472 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2474 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2478 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2480 enum machine_mode mode = GET_MODE (x);
2481 bool float_mode_p = FLOAT_MODE_P (mode);
2488 /* A number between 1 and 8 inclusive is efficient for a shift.
2489 Otherwise, we will need an extended instruction. */
2490 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2491 || (outer_code) == LSHIFTRT)
2493 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2496 *total = COSTS_N_INSNS (1);
2500 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2501 if ((outer_code) == XOR
2502 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2508 /* We may be able to use slt or sltu for a comparison with a
2509 signed 16 bit value. (The boundary conditions aren't quite
2510 right, but this is just a heuristic anyhow.) */
2511 if (((outer_code) == LT || (outer_code) == LE
2512 || (outer_code) == GE || (outer_code) == GT
2513 || (outer_code) == LTU || (outer_code) == LEU
2514 || (outer_code) == GEU || (outer_code) == GTU)
2515 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2521 /* Equality comparisons with 0 are cheap. */
2522 if (((outer_code) == EQ || (outer_code) == NE)
2529 /* Constants in the range 0...255 can be loaded with an unextended
2530 instruction. They are therefore as cheap as a register move.
2532 Given the choice between "li R1,0...255" and "move R1,R2"
2533 (where R2 is a known constant), it is usually better to use "li",
2534 since we do not want to unnecessarily extend the lifetime
2536 if (outer_code == SET
2538 && INTVAL (x) < 256)
2546 /* These can be used anywhere. */
2551 /* Otherwise fall through to the handling below because
2552 we'll need to construct the constant. */
2558 if (LEGITIMATE_CONSTANT_P (x))
2560 *total = COSTS_N_INSNS (1);
2565 /* The value will need to be fetched from the constant pool. */
2566 *total = CONSTANT_POOL_COST;
2572 /* If the address is legitimate, return the number of
2573 instructions it needs, otherwise use the default handling. */
2574 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2577 *total = COSTS_N_INSNS (n + 1);
2584 *total = COSTS_N_INSNS (6);
2588 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2594 if (mode == DImode && !TARGET_64BIT)
2596 *total = COSTS_N_INSNS (2);
2604 if (mode == DImode && !TARGET_64BIT)
2606 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2614 *total = COSTS_N_INSNS (1);
2616 *total = COSTS_N_INSNS (4);
2620 *total = COSTS_N_INSNS (1);
2627 *total = mips_cost->fp_add;
2631 else if (mode == DImode && !TARGET_64BIT)
2633 *total = COSTS_N_INSNS (4);
2639 if (mode == DImode && !TARGET_64BIT)
2641 *total = COSTS_N_INSNS (4);
2648 *total = mips_cost->fp_mult_sf;
2650 else if (mode == DFmode)
2651 *total = mips_cost->fp_mult_df;
2653 else if (mode == SImode)
2654 *total = mips_cost->int_mult_si;
2657 *total = mips_cost->int_mult_di;
2666 *total = mips_cost->fp_div_sf;
2668 *total = mips_cost->fp_div_df;
2677 *total = mips_cost->int_div_di;
2679 *total = mips_cost->int_div_si;
2684 /* A sign extend from SImode to DImode in 64 bit mode is often
2685 zero instructions, because the result can often be used
2686 directly by another instruction; we'll call it one. */
2687 if (TARGET_64BIT && mode == DImode
2688 && GET_MODE (XEXP (x, 0)) == SImode)
2689 *total = COSTS_N_INSNS (1);
2691 *total = COSTS_N_INSNS (2);
2695 if (TARGET_64BIT && mode == DImode
2696 && GET_MODE (XEXP (x, 0)) == SImode)
2697 *total = COSTS_N_INSNS (2);
2699 *total = COSTS_N_INSNS (1);
2703 case UNSIGNED_FLOAT:
2706 case FLOAT_TRUNCATE:
2708 *total = mips_cost->fp_add;
2716 /* Provide the costs of an addressing mode that contains ADDR.
2717 If ADDR is not a valid address, its cost is irrelevant. */
2720 mips_address_cost (rtx addr)
2722 return mips_address_insns (addr, SImode);
2725 /* Return one word of double-word value OP, taking into account the fixed
2726 endianness of certain registers. HIGH_P is true to select the high part,
2727 false to select the low part. */
2730 mips_subword (rtx op, int high_p)
2733 enum machine_mode mode;
2735 mode = GET_MODE (op);
2736 if (mode == VOIDmode)
2739 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2740 byte = UNITS_PER_WORD;
2746 if (FP_REG_P (REGNO (op)))
2747 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2748 if (ACC_HI_REG_P (REGNO (op)))
2749 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2753 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2755 return simplify_gen_subreg (word_mode, op, mode, byte);
2759 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2762 mips_split_64bit_move_p (rtx dest, rtx src)
2767 /* FP->FP moves can be done in a single instruction. */
2768 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2771 /* Check for floating-point loads and stores. They can be done using
2772 ldc1 and sdc1 on MIPS II and above. */
2775 if (FP_REG_RTX_P (dest) && MEM_P (src))
2777 if (FP_REG_RTX_P (src) && MEM_P (dest))
2784 /* Split a 64-bit move from SRC to DEST assuming that
2785 mips_split_64bit_move_p holds.
2787 Moves into and out of FPRs cause some difficulty here. Such moves
2788 will always be DFmode, since paired FPRs are not allowed to store
2789 DImode values. The most natural representation would be two separate
2790 32-bit moves, such as:
2792 (set (reg:SI $f0) (mem:SI ...))
2793 (set (reg:SI $f1) (mem:SI ...))
2795 However, the second insn is invalid because odd-numbered FPRs are
2796 not allowed to store independent values. Use the patterns load_df_low,
2797 load_df_high and store_df_high instead. */
2800 mips_split_64bit_move (rtx dest, rtx src)
2802 if (FP_REG_RTX_P (dest))
2804 /* Loading an FPR from memory or from GPRs. */
2805 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2806 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2809 else if (FP_REG_RTX_P (src))
2811 /* Storing an FPR into memory or GPRs. */
2812 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2813 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2817 /* The operation can be split into two normal moves. Decide in
2818 which order to do them. */
2821 low_dest = mips_subword (dest, 0);
2822 if (REG_P (low_dest)
2823 && reg_overlap_mentioned_p (low_dest, src))
2825 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2826 emit_move_insn (low_dest, mips_subword (src, 0));
2830 emit_move_insn (low_dest, mips_subword (src, 0));
2831 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2836 /* Return the appropriate instructions to move SRC into DEST. Assume
2837 that SRC is operand 1 and DEST is operand 0. */
2840 mips_output_move (rtx dest, rtx src)
2842 enum rtx_code dest_code, src_code;
2845 dest_code = GET_CODE (dest);
2846 src_code = GET_CODE (src);
2847 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2849 if (dbl_p && mips_split_64bit_move_p (dest, src))
2852 if ((src_code == REG && GP_REG_P (REGNO (src)))
2853 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2855 if (dest_code == REG)
2857 if (GP_REG_P (REGNO (dest)))
2858 return "move\t%0,%z1";
2860 if (MD_REG_P (REGNO (dest)))
2863 if (DSP_ACC_REG_P (REGNO (dest)))
2865 static char retval[] = "mt__\t%z1,%q0";
2866 retval[2] = reg_names[REGNO (dest)][4];
2867 retval[3] = reg_names[REGNO (dest)][5];
2871 if (FP_REG_P (REGNO (dest)))
2872 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2874 if (ALL_COP_REG_P (REGNO (dest)))
2876 static char retval[] = "dmtc_\t%z1,%0";
2878 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2879 return (dbl_p ? retval : retval + 1);
2882 if (dest_code == MEM)
2883 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2885 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2887 if (src_code == REG)
2889 if (DSP_ACC_REG_P (REGNO (src)))
2891 static char retval[] = "mf__\t%0,%q1";
2892 retval[2] = reg_names[REGNO (src)][4];
2893 retval[3] = reg_names[REGNO (src)][5];
2897 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2898 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2900 if (FP_REG_P (REGNO (src)))
2901 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2903 if (ALL_COP_REG_P (REGNO (src)))
2905 static char retval[] = "dmfc_\t%0,%1";
2907 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2908 return (dbl_p ? retval : retval + 1);
2912 if (src_code == MEM)
2913 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2915 if (src_code == CONST_INT)
2917 /* Don't use the X format, because that will give out of
2918 range numbers for 64 bit hosts and 32 bit targets. */
2920 return "li\t%0,%1\t\t\t# %X1";
2922 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2925 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2929 if (src_code == HIGH)
2930 return "lui\t%0,%h1";
2932 if (CONST_GP_P (src))
2933 return "move\t%0,%1";
2935 if (symbolic_operand (src, VOIDmode))
2936 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2938 if (src_code == REG && FP_REG_P (REGNO (src)))
2940 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2942 if (GET_MODE (dest) == V2SFmode)
2943 return "mov.ps\t%0,%1";
2945 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2948 if (dest_code == MEM)
2949 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2951 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2953 if (src_code == MEM)
2954 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2956 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2958 static char retval[] = "l_c_\t%0,%1";
2960 retval[1] = (dbl_p ? 'd' : 'w');
2961 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2964 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2966 static char retval[] = "s_c_\t%1,%0";
2968 retval[1] = (dbl_p ? 'd' : 'w');
2969 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2975 /* Restore $gp from its save slot. Valid only when using o32 or
2979 mips_restore_gp (void)
2983 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2985 address = mips_add_offset (pic_offset_table_rtx,
2986 frame_pointer_needed
2987 ? hard_frame_pointer_rtx
2988 : stack_pointer_rtx,
2989 current_function_outgoing_args_size);
2990 slot = gen_rtx_MEM (Pmode, address);
2992 emit_move_insn (pic_offset_table_rtx, slot);
2993 if (!TARGET_EXPLICIT_RELOCS)
2994 emit_insn (gen_blockage ());
2997 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3000 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3002 emit_insn (gen_rtx_SET (VOIDmode, target,
3003 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3006 /* Return true if CMP1 is a suitable second operand for relational
3007 operator CODE. See also the *sCC patterns in mips.md. */
3010 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3016 return reg_or_0_operand (cmp1, VOIDmode);
3020 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3024 return arith_operand (cmp1, VOIDmode);
3027 return sle_operand (cmp1, VOIDmode);
3030 return sleu_operand (cmp1, VOIDmode);
3037 /* Canonicalize LE or LEU comparisons into LT comparisons when
3038 possible to avoid extra instructions or inverting the
3042 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3043 enum machine_mode mode)
3045 HOST_WIDE_INT original, plus_one;
3047 if (GET_CODE (*cmp1) != CONST_INT)
3050 original = INTVAL (*cmp1);
3051 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3056 if (original < plus_one)
3059 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3068 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3081 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3082 result in TARGET. CMP0 and TARGET are register_operands that have
3083 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3084 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3087 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3088 rtx target, rtx cmp0, rtx cmp1)
3090 /* First see if there is a MIPS instruction that can do this operation
3091 with CMP1 in its current form. If not, try to canonicalize the
3092 comparison to LT. If that fails, try doing the same for the
3093 inverse operation. If that also fails, force CMP1 into a register
3095 if (mips_relational_operand_ok_p (code, cmp1))
3096 mips_emit_binary (code, target, cmp0, cmp1);
3097 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3098 mips_emit_binary (code, target, cmp0, cmp1);
3101 enum rtx_code inv_code = reverse_condition (code);
3102 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3104 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3105 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3107 else if (invert_ptr == 0)
3109 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3110 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3111 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3115 *invert_ptr = !*invert_ptr;
3116 mips_emit_binary (inv_code, target, cmp0, cmp1);
3121 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3122 The register will have the same mode as CMP0. */
3125 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3127 if (cmp1 == const0_rtx)
3130 if (uns_arith_operand (cmp1, VOIDmode))
3131 return expand_binop (GET_MODE (cmp0), xor_optab,
3132 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3134 return expand_binop (GET_MODE (cmp0), sub_optab,
3135 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3138 /* Convert *CODE into a code that can be used in a floating-point
3139 scc instruction (c.<cond>.<fmt>). Return true if the values of
3140 the condition code registers will be inverted, with 0 indicating
3141 that the condition holds. */
3144 mips_reverse_fp_cond_p (enum rtx_code *code)
3151 *code = reverse_condition_maybe_unordered (*code);
3159 /* Convert a comparison into something that can be used in a branch or
3160 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3161 being compared and *CODE is the code used to compare them.
3163 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3164 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3165 otherwise any standard branch condition can be used. The standard branch
3168 - EQ/NE between two registers.
3169 - any comparison between a register and zero. */
3172 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3174 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3176 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3178 *op0 = cmp_operands[0];
3179 *op1 = cmp_operands[1];
3181 else if (*code == EQ || *code == NE)
3185 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3190 *op0 = cmp_operands[0];
3191 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3196 /* The comparison needs a separate scc instruction. Store the
3197 result of the scc in *OP0 and compare it against zero. */
3198 bool invert = false;
3199 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3201 mips_emit_int_relational (*code, &invert, *op0,
3202 cmp_operands[0], cmp_operands[1]);
3203 *code = (invert ? EQ : NE);
3208 enum rtx_code cmp_code;
3210 /* Floating-point tests use a separate c.cond.fmt comparison to
3211 set a condition code register. The branch or conditional move
3212 will then compare that register against zero.
3214 Set CMP_CODE to the code of the comparison instruction and
3215 *CODE to the code that the branch or move should use. */
3217 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3219 ? gen_reg_rtx (CCmode)
3220 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3222 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3226 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3227 Store the result in TARGET and return true if successful.
3229 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3232 mips_emit_scc (enum rtx_code code, rtx target)
3234 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3237 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3238 if (code == EQ || code == NE)
3240 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3241 mips_emit_binary (code, target, zie, const0_rtx);
3244 mips_emit_int_relational (code, 0, target,
3245 cmp_operands[0], cmp_operands[1]);
3249 /* Emit the common code for doing conditional branches.
3250 operand[0] is the label to jump to.
3251 The comparison operands are saved away by cmp{si,di,sf,df}. */
3254 gen_conditional_branch (rtx *operands, enum rtx_code code)
3256 rtx op0, op1, condition;
3258 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3259 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3260 emit_jump_insn (gen_condjump (condition, operands[0]));
3265 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3266 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3269 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3270 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3275 reversed_p = mips_reverse_fp_cond_p (&cond);
3276 cmp_result = gen_reg_rtx (CCV2mode);
3277 emit_insn (gen_scc_ps (cmp_result,
3278 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3280 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3283 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3287 /* Emit the common code for conditional moves. OPERANDS is the array
3288 of operands passed to the conditional move define_expand. */
3291 gen_conditional_move (rtx *operands)
3296 code = GET_CODE (operands[1]);
3297 mips_emit_compare (&code, &op0, &op1, true);
3298 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3299 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3300 gen_rtx_fmt_ee (code,
3303 operands[2], operands[3])));
3306 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3307 the conditional_trap expander. */
3310 mips_gen_conditional_trap (rtx *operands)
3313 enum rtx_code cmp_code = GET_CODE (operands[0]);
3314 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3316 /* MIPS conditional trap machine instructions don't have GT or LE
3317 flavors, so we must invert the comparison and convert to LT and
3318 GE, respectively. */
3321 case GT: cmp_code = LT; break;
3322 case LE: cmp_code = GE; break;
3323 case GTU: cmp_code = LTU; break;
3324 case LEU: cmp_code = GEU; break;
3327 if (cmp_code == GET_CODE (operands[0]))
3329 op0 = cmp_operands[0];
3330 op1 = cmp_operands[1];
3334 op0 = cmp_operands[1];
3335 op1 = cmp_operands[0];
3337 op0 = force_reg (mode, op0);
3338 if (!arith_operand (op1, mode))
3339 op1 = force_reg (mode, op1);
3341 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3342 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3346 /* Load function address ADDR into register DEST. SIBCALL_P is true
3347 if the address is needed for a sibling call. */
3350 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3352 /* If we're generating PIC, and this call is to a global function,
3353 try to allow its address to be resolved lazily. This isn't
3354 possible for NewABI sibcalls since the value of $gp on entry
3355 to the stub would be our caller's gp, not ours. */
3356 if (TARGET_EXPLICIT_RELOCS
3357 && !(sibcall_p && TARGET_NEWABI)
3358 && global_got_operand (addr, VOIDmode))
3360 rtx high, lo_sum_symbol;
3362 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3363 addr, SYMBOL_GOTOFF_CALL);
3364 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3365 if (Pmode == SImode)
3366 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3368 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3371 emit_move_insn (dest, addr);
3375 /* Expand a call or call_value instruction. RESULT is where the
3376 result will go (null for calls), ADDR is the address of the
3377 function, ARGS_SIZE is the size of the arguments and AUX is
3378 the value passed to us by mips_function_arg. SIBCALL_P is true
3379 if we are expanding a sibling call, false if we're expanding
3383 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3385 rtx orig_addr, pattern, insn;
3388 if (!call_insn_operand (addr, VOIDmode))
3390 addr = gen_reg_rtx (Pmode);
3391 mips_load_call_address (addr, orig_addr, sibcall_p);
3395 && mips16_hard_float
3396 && build_mips16_call_stub (result, addr, args_size,
3397 aux == 0 ? 0 : (int) GET_MODE (aux)))
3401 pattern = (sibcall_p
3402 ? gen_sibcall_internal (addr, args_size)
3403 : gen_call_internal (addr, args_size));
3404 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3408 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3409 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3412 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3413 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3416 pattern = (sibcall_p
3417 ? gen_sibcall_value_internal (result, addr, args_size)
3418 : gen_call_value_internal (result, addr, args_size));
3420 insn = emit_call_insn (pattern);
3422 /* Lazy-binding stubs require $gp to be valid on entry. */
3423 if (global_got_operand (orig_addr, VOIDmode))
3424 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3428 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3431 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3432 tree exp ATTRIBUTE_UNUSED)
3434 return TARGET_SIBCALLS;
3437 /* Emit code to move general operand SRC into condition-code
3438 register DEST. SCRATCH is a scratch TFmode float register.
3445 where FP1 and FP2 are single-precision float registers
3446 taken from SCRATCH. */
3449 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3453 /* Change the source to SFmode. */
3455 src = adjust_address (src, SFmode, 0);
3456 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3457 src = gen_rtx_REG (SFmode, true_regnum (src));
3459 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3460 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3462 emit_move_insn (copy_rtx (fp1), src);
3463 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3464 emit_insn (gen_slt_sf (dest, fp2, fp1));
3467 /* Emit code to change the current function's return address to
3468 ADDRESS. SCRATCH is available as a scratch register, if needed.
3469 ADDRESS and SCRATCH are both word-mode GPRs. */
3472 mips_set_return_address (rtx address, rtx scratch)
3476 compute_frame_size (get_frame_size ());
3477 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3478 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3479 cfun->machine->frame.gp_sp_offset);
3481 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3484 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3485 Assume that the areas do not overlap. */
3488 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3490 HOST_WIDE_INT offset, delta;
3491 unsigned HOST_WIDE_INT bits;
3493 enum machine_mode mode;
3496 /* Work out how many bits to move at a time. If both operands have
3497 half-word alignment, it is usually better to move in half words.
3498 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3499 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3500 Otherwise move word-sized chunks. */
3501 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3502 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3503 bits = BITS_PER_WORD / 2;
3505 bits = BITS_PER_WORD;
3507 mode = mode_for_size (bits, MODE_INT, 0);
3508 delta = bits / BITS_PER_UNIT;
3510 /* Allocate a buffer for the temporary registers. */
3511 regs = alloca (sizeof (rtx) * length / delta);
3513 /* Load as many BITS-sized chunks as possible. Use a normal load if
3514 the source has enough alignment, otherwise use left/right pairs. */
3515 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3517 regs[i] = gen_reg_rtx (mode);
3518 if (MEM_ALIGN (src) >= bits)
3519 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3522 rtx part = adjust_address (src, BLKmode, offset);
3523 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3528 /* Copy the chunks to the destination. */
3529 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3530 if (MEM_ALIGN (dest) >= bits)
3531 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3534 rtx part = adjust_address (dest, BLKmode, offset);
3535 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3539 /* Mop up any left-over bytes. */
3540 if (offset < length)
3542 src = adjust_address (src, BLKmode, offset);
3543 dest = adjust_address (dest, BLKmode, offset);
3544 move_by_pieces (dest, src, length - offset,
3545 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3549 #define MAX_MOVE_REGS 4
3550 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3553 /* Helper function for doing a loop-based block operation on memory
3554 reference MEM. Each iteration of the loop will operate on LENGTH
3557 Create a new base register for use within the loop and point it to
3558 the start of MEM. Create a new memory reference that uses this
3559 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3562 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3563 rtx *loop_reg, rtx *loop_mem)
3565 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3567 /* Although the new mem does not refer to a known location,
3568 it does keep up to LENGTH bytes of alignment. */
3569 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3570 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3574 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3575 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3576 memory regions do not overlap. */
3579 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3581 rtx label, src_reg, dest_reg, final_src;
3582 HOST_WIDE_INT leftover;
3584 leftover = length % MAX_MOVE_BYTES;
3587 /* Create registers and memory references for use within the loop. */
3588 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3589 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3591 /* Calculate the value that SRC_REG should have after the last iteration
3593 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3596 /* Emit the start of the loop. */
3597 label = gen_label_rtx ();
3600 /* Emit the loop body. */
3601 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3603 /* Move on to the next block. */
3604 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3605 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3607 /* Emit the loop condition. */
3608 if (Pmode == DImode)
3609 emit_insn (gen_cmpdi (src_reg, final_src));
3611 emit_insn (gen_cmpsi (src_reg, final_src));
3612 emit_jump_insn (gen_bne (label));
3614 /* Mop up any left-over bytes. */
3616 mips_block_move_straight (dest, src, leftover);
3619 /* Expand a movmemsi instruction. */
3622 mips_expand_block_move (rtx dest, rtx src, rtx length)
3624 if (GET_CODE (length) == CONST_INT)
3626 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3628 mips_block_move_straight (dest, src, INTVAL (length));
3633 mips_block_move_loop (dest, src, INTVAL (length));
3640 /* Argument support functions. */
3642 /* Initialize CUMULATIVE_ARGS for a function. */
3645 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3646 rtx libname ATTRIBUTE_UNUSED)
3648 static CUMULATIVE_ARGS zero_cum;
3649 tree param, next_param;
3652 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3654 /* Determine if this function has variable arguments. This is
3655 indicated by the last argument being 'void_type_mode' if there
3656 are no variable arguments. The standard MIPS calling sequence
3657 passes all arguments in the general purpose registers in this case. */
3659 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3660 param != 0; param = next_param)
3662 next_param = TREE_CHAIN (param);
3663 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3664 cum->gp_reg_found = 1;
3669 /* Fill INFO with information about a single argument. CUM is the
3670 cumulative state for earlier arguments. MODE is the mode of this
3671 argument and TYPE is its type (if known). NAMED is true if this
3672 is a named (fixed) argument rather than a variable one. */
3675 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3676 tree type, int named, struct mips_arg_info *info)
3678 bool doubleword_aligned_p;
3679 unsigned int num_bytes, num_words, max_regs;
3681 /* Work out the size of the argument. */
3682 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3683 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3685 /* Decide whether it should go in a floating-point register, assuming
3686 one is free. Later code checks for availability.
3688 The checks against UNITS_PER_FPVALUE handle the soft-float and
3689 single-float cases. */
3693 /* The EABI conventions have traditionally been defined in terms
3694 of TYPE_MODE, regardless of the actual type. */
3695 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3696 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3697 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3702 /* Only leading floating-point scalars are passed in
3703 floating-point registers. We also handle vector floats the same
3704 say, which is OK because they are not covered by the standard ABI. */
3705 info->fpr_p = (!cum->gp_reg_found
3706 && cum->arg_number < 2
3707 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3708 || VECTOR_FLOAT_TYPE_P (type))
3709 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3710 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3711 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3716 /* Scalar and complex floating-point types are passed in
3717 floating-point registers. */
3718 info->fpr_p = (named
3719 && (type == 0 || FLOAT_TYPE_P (type))
3720 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3721 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3722 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3723 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3725 /* ??? According to the ABI documentation, the real and imaginary
3726 parts of complex floats should be passed in individual registers.
3727 The real and imaginary parts of stack arguments are supposed
3728 to be contiguous and there should be an extra word of padding
3731 This has two problems. First, it makes it impossible to use a
3732 single "void *" va_list type, since register and stack arguments
3733 are passed differently. (At the time of writing, MIPSpro cannot
3734 handle complex float varargs correctly.) Second, it's unclear
3735 what should happen when there is only one register free.
3737 For now, we assume that named complex floats should go into FPRs
3738 if there are two FPRs free, otherwise they should be passed in the
3739 same way as a struct containing two floats. */
3741 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3742 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3744 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3745 info->fpr_p = false;
3755 /* See whether the argument has doubleword alignment. */
3756 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3758 /* Set REG_OFFSET to the register count we're interested in.
3759 The EABI allocates the floating-point registers separately,
3760 but the other ABIs allocate them like integer registers. */
3761 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3765 /* Advance to an even register if the argument is doubleword-aligned. */
3766 if (doubleword_aligned_p)
3767 info->reg_offset += info->reg_offset & 1;
3769 /* Work out the offset of a stack argument. */
3770 info->stack_offset = cum->stack_words;
3771 if (doubleword_aligned_p)
3772 info->stack_offset += info->stack_offset & 1;
3774 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3776 /* Partition the argument between registers and stack. */
3777 info->reg_words = MIN (num_words, max_regs);
3778 info->stack_words = num_words - info->reg_words;
3782 /* Implement FUNCTION_ARG_ADVANCE. */
3785 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3786 tree type, int named)
3788 struct mips_arg_info info;
3790 mips_arg_info (cum, mode, type, named, &info);
3793 cum->gp_reg_found = true;
3795 /* See the comment above the cumulative args structure in mips.h
3796 for an explanation of what this code does. It assumes the O32
3797 ABI, which passes at most 2 arguments in float registers. */
3798 if (cum->arg_number < 2 && info.fpr_p)
3799 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3801 if (mips_abi != ABI_EABI || !info.fpr_p)
3802 cum->num_gprs = info.reg_offset + info.reg_words;
3803 else if (info.reg_words > 0)
3804 cum->num_fprs += FP_INC;
3806 if (info.stack_words > 0)
3807 cum->stack_words = info.stack_offset + info.stack_words;
3812 /* Implement FUNCTION_ARG. */
3815 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3816 tree type, int named)
3818 struct mips_arg_info info;
3820 /* We will be called with a mode of VOIDmode after the last argument
3821 has been seen. Whatever we return will be passed to the call
3822 insn. If we need a mips16 fp_code, return a REG with the code
3823 stored as the mode. */
3824 if (mode == VOIDmode)
3826 if (TARGET_MIPS16 && cum->fp_code != 0)
3827 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3833 mips_arg_info (cum, mode, type, named, &info);
3835 /* Return straight away if the whole argument is passed on the stack. */
3836 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3840 && TREE_CODE (type) == RECORD_TYPE
3842 && TYPE_SIZE_UNIT (type)
3843 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3846 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3847 structure contains a double in its entirety, then that 64 bit
3848 chunk is passed in a floating point register. */
3851 /* First check to see if there is any such field. */
3852 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3853 if (TREE_CODE (field) == FIELD_DECL
3854 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3855 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3856 && host_integerp (bit_position (field), 0)
3857 && int_bit_position (field) % BITS_PER_WORD == 0)
3862 /* Now handle the special case by returning a PARALLEL
3863 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3864 chunks are passed in registers. */
3866 HOST_WIDE_INT bitpos;
3869 /* assign_parms checks the mode of ENTRY_PARM, so we must
3870 use the actual mode here. */
3871 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3874 field = TYPE_FIELDS (type);
3875 for (i = 0; i < info.reg_words; i++)
3879 for (; field; field = TREE_CHAIN (field))
3880 if (TREE_CODE (field) == FIELD_DECL
3881 && int_bit_position (field) >= bitpos)
3885 && int_bit_position (field) == bitpos
3886 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3887 && !TARGET_SOFT_FLOAT
3888 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3889 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3891 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3894 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3895 GEN_INT (bitpos / BITS_PER_UNIT));
3897 bitpos += BITS_PER_WORD;
3903 /* Handle the n32/n64 conventions for passing complex floating-point
3904 arguments in FPR pairs. The real part goes in the lower register
3905 and the imaginary part goes in the upper register. */
3908 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3911 enum machine_mode inner;
3914 inner = GET_MODE_INNER (mode);
3915 reg = FP_ARG_FIRST + info.reg_offset;
3916 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
3918 /* Real part in registers, imaginary part on stack. */
3919 gcc_assert (info.stack_words == info.reg_words);
3920 return gen_rtx_REG (inner, reg);
3924 gcc_assert (info.stack_words == 0);
3925 real = gen_rtx_EXPR_LIST (VOIDmode,
3926 gen_rtx_REG (inner, reg),
3928 imag = gen_rtx_EXPR_LIST (VOIDmode,
3930 reg + info.reg_words / 2),
3931 GEN_INT (GET_MODE_SIZE (inner)));
3932 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3937 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3938 else if (info.reg_offset == 1)
3939 /* This code handles the special o32 case in which the second word
3940 of the argument structure is passed in floating-point registers. */
3941 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3943 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3947 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3950 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3951 enum machine_mode mode, tree type, bool named)
3953 struct mips_arg_info info;
3955 mips_arg_info (cum, mode, type, named, &info);
3956 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3960 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3961 PARM_BOUNDARY bits of alignment, but will be given anything up
3962 to STACK_BOUNDARY bits if the type requires it. */
3965 function_arg_boundary (enum machine_mode mode, tree type)
3967 unsigned int alignment;
3969 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3970 if (alignment < PARM_BOUNDARY)
3971 alignment = PARM_BOUNDARY;
3972 if (alignment > STACK_BOUNDARY)
3973 alignment = STACK_BOUNDARY;
3977 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3978 upward rather than downward. In other words, return true if the
3979 first byte of the stack slot has useful data, false if the last
3983 mips_pad_arg_upward (enum machine_mode mode, tree type)
3985 /* On little-endian targets, the first byte of every stack argument
3986 is passed in the first byte of the stack slot. */
3987 if (!BYTES_BIG_ENDIAN)
3990 /* Otherwise, integral types are padded downward: the last byte of a
3991 stack argument is passed in the last byte of the stack slot. */
3993 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3994 : GET_MODE_CLASS (mode) == MODE_INT)
3997 /* Big-endian o64 pads floating-point arguments downward. */
3998 if (mips_abi == ABI_O64)
3999 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4002 /* Other types are padded upward for o32, o64, n32 and n64. */
4003 if (mips_abi != ABI_EABI)
4006 /* Arguments smaller than a stack slot are padded downward. */
4007 if (mode != BLKmode)
4008 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4010 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4014 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4015 if the least significant byte of the register has useful data. Return
4016 the opposite if the most significant byte does. */
4019 mips_pad_reg_upward (enum machine_mode mode, tree type)
4021 /* No shifting is required for floating-point arguments. */
4022 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4023 return !BYTES_BIG_ENDIAN;
4025 /* Otherwise, apply the same padding to register arguments as we do
4026 to stack arguments. */
4027 return mips_pad_arg_upward (mode, type);
4031 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4032 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4035 CUMULATIVE_ARGS local_cum;
4036 int gp_saved, fp_saved;
4038 /* The caller has advanced CUM up to, but not beyond, the last named
4039 argument. Advance a local copy of CUM past the last "real" named
4040 argument, to find out how many registers are left over. */
4043 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4045 /* Found out how many registers we need to save. */
4046 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4047 fp_saved = (EABI_FLOAT_VARARGS_P
4048 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4057 ptr = plus_constant (virtual_incoming_args_rtx,
4058 REG_PARM_STACK_SPACE (cfun->decl)
4059 - gp_saved * UNITS_PER_WORD);
4060 mem = gen_rtx_MEM (BLKmode, ptr);
4061 set_mem_alias_set (mem, get_varargs_alias_set ());
4063 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4068 /* We can't use move_block_from_reg, because it will use
4070 enum machine_mode mode;
4073 /* Set OFF to the offset from virtual_incoming_args_rtx of
4074 the first float register. The FP save area lies below
4075 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4076 off = -gp_saved * UNITS_PER_WORD;
4077 off &= ~(UNITS_PER_FPVALUE - 1);
4078 off -= fp_saved * UNITS_PER_FPREG;
4080 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4082 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4086 ptr = plus_constant (virtual_incoming_args_rtx, off);
4087 mem = gen_rtx_MEM (mode, ptr);
4088 set_mem_alias_set (mem, get_varargs_alias_set ());
4089 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4090 off += UNITS_PER_HWFPVALUE;
4094 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4095 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4096 + fp_saved * UNITS_PER_FPREG);
4099 /* Create the va_list data type.
4100 We keep 3 pointers, and two offsets.
4101 Two pointers are to the overflow area, which starts at the CFA.
4102 One of these is constant, for addressing into the GPR save area below it.
4103 The other is advanced up the stack through the overflow region.
4104 The third pointer is to the GPR save area. Since the FPR save area
4105 is just below it, we can address FPR slots off this pointer.
4106 We also keep two one-byte offsets, which are to be subtracted from the
4107 constant pointers to yield addresses in the GPR and FPR save areas.
4108 These are downcounted as float or non-float arguments are used,
4109 and when they get to zero, the argument must be obtained from the
4111 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4112 pointer is enough. It's started at the GPR save area, and is
4114 Note that the GPR save area is not constant size, due to optimization
4115 in the prologue. Hence, we can't use a design with two pointers
4116 and two offsets, although we could have designed this with two pointers
4117 and three offsets. */
4120 mips_build_builtin_va_list (void)
4122 if (EABI_FLOAT_VARARGS_P)
4124 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4127 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4129 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4131 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4133 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4135 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4136 unsigned_char_type_node);
4137 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4138 unsigned_char_type_node);
4139 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4140 warn on every user file. */
4141 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4142 array = build_array_type (unsigned_char_type_node,
4143 build_index_type (index));
4144 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4146 DECL_FIELD_CONTEXT (f_ovfl) = record;
4147 DECL_FIELD_CONTEXT (f_gtop) = record;
4148 DECL_FIELD_CONTEXT (f_ftop) = record;
4149 DECL_FIELD_CONTEXT (f_goff) = record;
4150 DECL_FIELD_CONTEXT (f_foff) = record;
4151 DECL_FIELD_CONTEXT (f_res) = record;
4153 TYPE_FIELDS (record) = f_ovfl;
4154 TREE_CHAIN (f_ovfl) = f_gtop;
4155 TREE_CHAIN (f_gtop) = f_ftop;
4156 TREE_CHAIN (f_ftop) = f_goff;
4157 TREE_CHAIN (f_goff) = f_foff;
4158 TREE_CHAIN (f_foff) = f_res;
4160 layout_type (record);
4163 else if (TARGET_IRIX && TARGET_IRIX6)
4164 /* On IRIX 6, this type is 'char *'. */
4165 return build_pointer_type (char_type_node);
4167 /* Otherwise, we use 'void *'. */
4168 return ptr_type_node;
4171 /* Implement va_start. */
4174 mips_va_start (tree valist, rtx nextarg)
4176 if (EABI_FLOAT_VARARGS_P)
4178 const CUMULATIVE_ARGS *cum;
4179 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4180 tree ovfl, gtop, ftop, goff, foff;
4182 int gpr_save_area_size;
4183 int fpr_save_area_size;
4186 cum = ¤t_function_args_info;
4188 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4190 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4192 f_ovfl = TYPE_FIELDS (va_list_type_node);
4193 f_gtop = TREE_CHAIN (f_ovfl);
4194 f_ftop = TREE_CHAIN (f_gtop);
4195 f_goff = TREE_CHAIN (f_ftop);
4196 f_foff = TREE_CHAIN (f_goff);
4198 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4200 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4202 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4204 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4206 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4209 /* Emit code to initialize OVFL, which points to the next varargs
4210 stack argument. CUM->STACK_WORDS gives the number of stack
4211 words used by named arguments. */
4212 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4213 if (cum->stack_words > 0)
4214 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4215 build_int_cst (NULL_TREE,
4216 cum->stack_words * UNITS_PER_WORD));
4217 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4218 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4220 /* Emit code to initialize GTOP, the top of the GPR save area. */
4221 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4222 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4223 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4225 /* Emit code to initialize FTOP, the top of the FPR save area.
4226 This address is gpr_save_area_bytes below GTOP, rounded
4227 down to the next fp-aligned boundary. */
4228 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4229 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4230 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4232 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4233 build_int_cst (NULL_TREE, -fpr_offset));
4234 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4235 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4237 /* Emit code to initialize GOFF, the offset from GTOP of the
4238 next GPR argument. */
4239 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4240 build_int_cst (NULL_TREE, gpr_save_area_size));
4241 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4243 /* Likewise emit code to initialize FOFF, the offset from FTOP
4244 of the next FPR argument. */
4245 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4246 build_int_cst (NULL_TREE, fpr_save_area_size));
4247 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4251 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4252 std_expand_builtin_va_start (valist, nextarg);
4256 /* Implement va_arg. */
4259 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4261 HOST_WIDE_INT size, rsize;
4265 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4268 type = build_pointer_type (type);
4270 size = int_size_in_bytes (type);
4271 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4273 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4274 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4277 /* Not a simple merged stack. */
4279 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4280 tree ovfl, top, off, align;
4281 HOST_WIDE_INT osize;
4284 f_ovfl = TYPE_FIELDS (va_list_type_node);
4285 f_gtop = TREE_CHAIN (f_ovfl);
4286 f_ftop = TREE_CHAIN (f_gtop);
4287 f_goff = TREE_CHAIN (f_ftop);
4288 f_foff = TREE_CHAIN (f_goff);
4290 /* We maintain separate pointers and offsets for floating-point
4291 and integer arguments, but we need similar code in both cases.
4294 TOP be the top of the register save area;
4295 OFF be the offset from TOP of the next register;
4296 ADDR_RTX be the address of the argument;
4297 RSIZE be the number of bytes used to store the argument
4298 when it's in the register save area;
4299 OSIZE be the number of bytes used to store it when it's
4300 in the stack overflow area; and
4301 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4303 The code we want is:
4305 1: off &= -rsize; // round down
4308 4: addr_rtx = top - off;
4313 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4314 10: addr_rtx = ovfl + PADDING;
4318 [1] and [9] can sometimes be optimized away. */
4320 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4323 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4324 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4326 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4328 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4331 /* When floating-point registers are saved to the stack,
4332 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4333 of the float's precision. */
4334 rsize = UNITS_PER_HWFPVALUE;
4336 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4337 (= PARM_BOUNDARY bits). This can be different from RSIZE
4340 (1) On 32-bit targets when TYPE is a structure such as:
4342 struct s { float f; };
4344 Such structures are passed in paired FPRs, so RSIZE
4345 will be 8 bytes. However, the structure only takes
4346 up 4 bytes of memory, so OSIZE will only be 4.
4348 (2) In combinations such as -mgp64 -msingle-float
4349 -fshort-double. Doubles passed in registers
4350 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4351 but those passed on the stack take up
4352 UNITS_PER_WORD bytes. */
4353 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4357 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4359 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4361 if (rsize > UNITS_PER_WORD)
4363 /* [1] Emit code for: off &= -rsize. */
4364 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4365 build_int_cst (NULL_TREE, -rsize));
4366 t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
4367 gimplify_and_add (t, pre_p);
4372 /* [2] Emit code to branch if off == 0. */
4373 t = build2 (NE_EXPR, boolean_type_node, off,
4374 build_int_cst (TREE_TYPE (off), 0));
4375 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4377 /* [5] Emit code for: off -= rsize. We do this as a form of
4378 post-increment not available to C. Also widen for the
4379 coming pointer arithmetic. */
4380 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4381 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4382 t = fold_convert (sizetype, t);
4383 t = fold_convert (TREE_TYPE (top), t);
4385 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4386 the argument has RSIZE - SIZE bytes of leading padding. */
4387 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4388 if (BYTES_BIG_ENDIAN && rsize > size)
4390 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4392 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4394 COND_EXPR_THEN (addr) = t;
4396 if (osize > UNITS_PER_WORD)
4398 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4399 u = fold_convert (TREE_TYPE (ovfl),
4400 build_int_cst (NULL_TREE, osize - 1));
4401 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4402 u = fold_convert (TREE_TYPE (ovfl),
4403 build_int_cst (NULL_TREE, -osize));
4404 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4405 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4410 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4411 post-increment ovfl by osize. On big-endian machines,
4412 the argument has OSIZE - SIZE bytes of leading padding. */
4413 u = fold_convert (TREE_TYPE (ovfl),
4414 build_int_cst (NULL_TREE, osize));
4415 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4416 if (BYTES_BIG_ENDIAN && osize > size)
4418 u = fold_convert (TREE_TYPE (t),
4419 build_int_cst (NULL_TREE, osize - size));
4420 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4423 /* String [9] and [10,11] together. */
4425 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4426 COND_EXPR_ELSE (addr) = t;
4428 addr = fold_convert (build_pointer_type (type), addr);
4429 addr = build_va_arg_indirect_ref (addr);
4433 addr = build_va_arg_indirect_ref (addr);
4438 /* Return true if it is possible to use left/right accesses for a
4439 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4440 returning true, update *OP, *LEFT and *RIGHT as follows:
4442 *OP is a BLKmode reference to the whole field.
4444 *LEFT is a QImode reference to the first byte if big endian or
4445 the last byte if little endian. This address can be used in the
4446 left-side instructions (lwl, swl, ldl, sdl).
4448 *RIGHT is a QImode reference to the opposite end of the field and
4449 can be used in the patterning right-side instruction. */
4452 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4453 rtx *left, rtx *right)
4457 /* Check that the operand really is a MEM. Not all the extv and
4458 extzv predicates are checked. */
4462 /* Check that the size is valid. */
4463 if (width != 32 && (!TARGET_64BIT || width != 64))
4466 /* We can only access byte-aligned values. Since we are always passed
4467 a reference to the first byte of the field, it is not necessary to
4468 do anything with BITPOS after this check. */
4469 if (bitpos % BITS_PER_UNIT != 0)
4472 /* Reject aligned bitfields: we want to use a normal load or store
4473 instead of a left/right pair. */
4474 if (MEM_ALIGN (*op) >= width)
4477 /* Adjust *OP to refer to the whole field. This also has the effect
4478 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4479 *op = adjust_address (*op, BLKmode, 0);
4480 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4482 /* Get references to both ends of the field. We deliberately don't
4483 use the original QImode *OP for FIRST since the new BLKmode one
4484 might have a simpler address. */
4485 first = adjust_address (*op, QImode, 0);
4486 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4488 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4489 be the upper word and RIGHT the lower word. */
4490 if (TARGET_BIG_ENDIAN)
4491 *left = first, *right = last;
4493 *left = last, *right = first;
4499 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4500 Return true on success. We only handle cases where zero_extract is
4501 equivalent to sign_extract. */
4504 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4506 rtx left, right, temp;
4508 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4509 paradoxical word_mode subreg. This is the only case in which
4510 we allow the destination to be larger than the source. */
4511 if (GET_CODE (dest) == SUBREG
4512 && GET_MODE (dest) == DImode
4513 && SUBREG_BYTE (dest) == 0
4514 && GET_MODE (SUBREG_REG (dest)) == SImode)
4515 dest = SUBREG_REG (dest);
4517 /* After the above adjustment, the destination must be the same
4518 width as the source. */
4519 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4522 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4525 temp = gen_reg_rtx (GET_MODE (dest));
4526 if (GET_MODE (dest) == DImode)
4528 emit_insn (gen_mov_ldl (temp, src, left));
4529 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4533 emit_insn (gen_mov_lwl (temp, src, left));
4534 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4540 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4544 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4547 enum machine_mode mode;
4549 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4552 mode = mode_for_size (width, MODE_INT, 0);
4553 src = gen_lowpart (mode, src);
4557 emit_insn (gen_mov_sdl (dest, src, left));
4558 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4562 emit_insn (gen_mov_swl (dest, src, left));
4563 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4568 /* Return true if X is a MEM with the same size as MODE. */
4571 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4578 size = MEM_SIZE (x);
4579 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4582 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4583 source of an "ext" instruction or the destination of an "ins"
4584 instruction. OP must be a register operand and the following
4585 conditions must hold:
4587 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4588 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4589 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4591 Also reject lengths equal to a word as they are better handled
4592 by the move patterns. */
4595 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4597 HOST_WIDE_INT len, pos;
4599 if (!ISA_HAS_EXT_INS
4600 || !register_operand (op, VOIDmode)
4601 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4604 len = INTVAL (size);
4605 pos = INTVAL (position);
4607 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4608 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4614 /* Set up globals to generate code for the ISA or processor
4615 described by INFO. */
4618 mips_set_architecture (const struct mips_cpu_info *info)
4622 mips_arch_info = info;
4623 mips_arch = info->cpu;
4624 mips_isa = info->isa;
4629 /* Likewise for tuning. */
4632 mips_set_tune (const struct mips_cpu_info *info)
4636 mips_tune_info = info;
4637 mips_tune = info->cpu;
4641 /* Implement TARGET_HANDLE_OPTION. */
4644 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4649 if (strcmp (arg, "32") == 0)
4651 else if (strcmp (arg, "o64") == 0)
4653 else if (strcmp (arg, "n32") == 0)
4655 else if (strcmp (arg, "64") == 0)
4657 else if (strcmp (arg, "eabi") == 0)
4658 mips_abi = ABI_EABI;
4665 return mips_parse_cpu (arg) != 0;
4668 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4669 return mips_isa_info != 0;
4671 case OPT_mno_flush_func:
4672 mips_cache_flush_func = NULL;
4680 /* Set up the threshold for data to go into the small data area, instead
4681 of the normal data area, and detect any conflicts in the switches. */
4684 override_options (void)
4686 int i, start, regno;
4687 enum machine_mode mode;
4689 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4691 /* The following code determines the architecture and register size.
4692 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4693 The GAS and GCC code should be kept in sync as much as possible. */
4695 if (mips_arch_string != 0)
4696 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4698 if (mips_isa_info != 0)
4700 if (mips_arch_info == 0)
4701 mips_set_architecture (mips_isa_info);
4702 else if (mips_arch_info->isa != mips_isa_info->isa)
4703 error ("-%s conflicts with the other architecture options, "
4704 "which specify a %s processor",
4705 mips_isa_info->name,
4706 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4709 if (mips_arch_info == 0)
4711 #ifdef MIPS_CPU_STRING_DEFAULT
4712 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4714 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4718 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4719 error ("-march=%s is not compatible with the selected ABI",
4720 mips_arch_info->name);
4722 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4723 if (mips_tune_string != 0)
4724 mips_set_tune (mips_parse_cpu (mips_tune_string));
4726 if (mips_tune_info == 0)
4727 mips_set_tune (mips_arch_info);
4729 /* Set cost structure for the processor. */
4730 mips_cost = &mips_rtx_cost_data[mips_tune];
4732 if ((target_flags_explicit & MASK_64BIT) != 0)
4734 /* The user specified the size of the integer registers. Make sure
4735 it agrees with the ABI and ISA. */
4736 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4737 error ("-mgp64 used with a 32-bit processor");
4738 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4739 error ("-mgp32 used with a 64-bit ABI");
4740 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4741 error ("-mgp64 used with a 32-bit ABI");
4745 /* Infer the integer register size from the ABI and processor.
4746 Restrict ourselves to 32-bit registers if that's all the
4747 processor has, or if the ABI cannot handle 64-bit registers. */
4748 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4749 target_flags &= ~MASK_64BIT;
4751 target_flags |= MASK_64BIT;
4754 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4756 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4757 only one right answer here. */
4758 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4759 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4760 else if (!TARGET_64BIT && TARGET_FLOAT64)
4761 error ("unsupported combination: %s", "-mgp32 -mfp64");
4762 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4763 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4767 /* -msingle-float selects 32-bit float registers. Otherwise the
4768 float registers should be the same size as the integer ones. */
4769 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4770 target_flags |= MASK_FLOAT64;
4772 target_flags &= ~MASK_FLOAT64;
4775 /* End of code shared with GAS. */
4777 if ((target_flags_explicit & MASK_LONG64) == 0)
4779 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4780 target_flags |= MASK_LONG64;
4782 target_flags &= ~MASK_LONG64;
4785 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4786 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4788 /* For some configurations, it is useful to have -march control
4789 the default setting of MASK_SOFT_FLOAT. */
4790 switch ((int) mips_arch)
4792 case PROCESSOR_R4100:
4793 case PROCESSOR_R4111:
4794 case PROCESSOR_R4120:
4795 case PROCESSOR_R4130:
4796 target_flags |= MASK_SOFT_FLOAT;
4800 target_flags &= ~MASK_SOFT_FLOAT;
4806 flag_pcc_struct_return = 0;
4808 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4810 /* If neither -mbranch-likely nor -mno-branch-likely was given
4811 on the command line, set MASK_BRANCHLIKELY based on the target
4814 By default, we enable use of Branch Likely instructions on
4815 all architectures which support them with the following
4816 exceptions: when creating MIPS32 or MIPS64 code, and when
4817 tuning for architectures where their use tends to hurt
4820 The MIPS32 and MIPS64 architecture specifications say "Software
4821 is strongly encouraged to avoid use of Branch Likely
4822 instructions, as they will be removed from a future revision
4823 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4824 issue those instructions unless instructed to do so by
4826 if (ISA_HAS_BRANCHLIKELY
4827 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4828 && !(TUNE_MIPS5500 || TUNE_SB1))
4829 target_flags |= MASK_BRANCHLIKELY;
4831 target_flags &= ~MASK_BRANCHLIKELY;
4833 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4834 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4836 /* The effect of -mabicalls isn't defined for the EABI. */
4837 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4839 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4840 target_flags &= ~MASK_ABICALLS;
4843 if (TARGET_ABICALLS)
4845 /* We need to set flag_pic for executables as well as DSOs
4846 because we may reference symbols that are not defined in
4847 the final executable. (MIPS does not use things like
4848 copy relocs, for example.)
4850 Also, there is a body of code that uses __PIC__ to distinguish
4851 between -mabicalls and -mno-abicalls code. */
4853 if (mips_section_threshold > 0)
4854 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4857 /* mips_split_addresses is a half-way house between explicit
4858 relocations and the traditional assembler macros. It can
4859 split absolute 32-bit symbolic constants into a high/lo_sum
4860 pair but uses macros for other sorts of access.
4862 Like explicit relocation support for REL targets, it relies
4863 on GNU extensions in the assembler and the linker.
4865 Although this code should work for -O0, it has traditionally
4866 been treated as an optimization. */
4867 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4868 && optimize && !flag_pic
4869 && !ABI_HAS_64BIT_SYMBOLS)
4870 mips_split_addresses = 1;
4872 mips_split_addresses = 0;
4874 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4875 faster code, but at the expense of more nops. Enable it at -O3 and
4877 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4878 target_flags |= MASK_VR4130_ALIGN;
4880 /* When compiling for the mips16, we cannot use floating point. We
4881 record the original hard float value in mips16_hard_float. */
4884 if (TARGET_SOFT_FLOAT)
4885 mips16_hard_float = 0;
4887 mips16_hard_float = 1;
4888 target_flags |= MASK_SOFT_FLOAT;
4890 /* Don't run the scheduler before reload, since it tends to
4891 increase register pressure. */
4892 flag_schedule_insns = 0;
4894 /* Don't do hot/cold partitioning. The constant layout code expects
4895 the whole function to be in a single section. */
4896 flag_reorder_blocks_and_partition = 0;
4898 /* Silently disable -mexplicit-relocs since it doesn't apply
4899 to mips16 code. Even so, it would overly pedantic to warn
4900 about "-mips16 -mexplicit-relocs", especially given that
4901 we use a %gprel() operator. */
4902 target_flags &= ~MASK_EXPLICIT_RELOCS;
4905 /* When using explicit relocs, we call dbr_schedule from within
4907 if (TARGET_EXPLICIT_RELOCS)
4909 mips_flag_delayed_branch = flag_delayed_branch;
4910 flag_delayed_branch = 0;
4913 #ifdef MIPS_TFMODE_FORMAT
4914 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4917 /* Make sure that the user didn't turn off paired single support when
4918 MIPS-3D support is requested. */
4919 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4920 && !TARGET_PAIRED_SINGLE_FLOAT)
4921 error ("-mips3d requires -mpaired-single");
4923 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4925 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4927 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4928 and TARGET_HARD_FLOAT are both true. */
4929 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4930 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4932 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4934 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4935 error ("-mips3d/-mpaired-single must be used with -mips64");
4937 if (TARGET_MIPS16 && TARGET_DSP)
4938 error ("-mips16 and -mdsp cannot be used together");
4940 mips_print_operand_punct['?'] = 1;
4941 mips_print_operand_punct['#'] = 1;
4942 mips_print_operand_punct['/'] = 1;
4943 mips_print_operand_punct['&'] = 1;
4944 mips_print_operand_punct['!'] = 1;
4945 mips_print_operand_punct['*'] = 1;
4946 mips_print_operand_punct['@'] = 1;
4947 mips_print_operand_punct['.'] = 1;
4948 mips_print_operand_punct['('] = 1;
4949 mips_print_operand_punct[')'] = 1;
4950 mips_print_operand_punct['['] = 1;
4951 mips_print_operand_punct[']'] = 1;
4952 mips_print_operand_punct['<'] = 1;
4953 mips_print_operand_punct['>'] = 1;
4954 mips_print_operand_punct['{'] = 1;
4955 mips_print_operand_punct['}'] = 1;
4956 mips_print_operand_punct['^'] = 1;
4957 mips_print_operand_punct['$'] = 1;
4958 mips_print_operand_punct['+'] = 1;
4959 mips_print_operand_punct['~'] = 1;
4961 /* Set up array to map GCC register number to debug register number.
4962 Ignore the special purpose register numbers. */
4964 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4965 mips_dbx_regno[i] = -1;
4967 start = GP_DBX_FIRST - GP_REG_FIRST;
4968 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4969 mips_dbx_regno[i] = i + start;
4971 start = FP_DBX_FIRST - FP_REG_FIRST;
4972 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4973 mips_dbx_regno[i] = i + start;
4975 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4976 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4978 /* Set up array giving whether a given register can hold a given mode. */
4980 for (mode = VOIDmode;
4981 mode != MAX_MACHINE_MODE;
4982 mode = (enum machine_mode) ((int)mode + 1))
4984 register int size = GET_MODE_SIZE (mode);
4985 register enum mode_class class = GET_MODE_CLASS (mode);
4987 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4991 if (mode == CCV2mode)
4994 && (regno - ST_REG_FIRST) % 2 == 0);
4996 else if (mode == CCV4mode)
4999 && (regno - ST_REG_FIRST) % 4 == 0);
5001 else if (mode == CCmode)
5004 temp = (regno == FPSW_REGNUM);
5006 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5007 || FP_REG_P (regno));
5010 else if (GP_REG_P (regno))
5011 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5013 else if (FP_REG_P (regno))
5014 temp = ((regno % FP_INC) == 0)
5015 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5016 || class == MODE_VECTOR_FLOAT)
5017 && size <= UNITS_PER_FPVALUE)
5018 /* Allow integer modes that fit into a single
5019 register. We need to put integers into FPRs
5020 when using instructions like cvt and trunc.
5021 We can't allow sizes smaller than a word,
5022 the FPU has no appropriate load/store
5023 instructions for those. */
5024 || (class == MODE_INT
5025 && size >= MIN_UNITS_PER_WORD
5026 && size <= UNITS_PER_FPREG)
5027 /* Allow TFmode for CCmode reloads. */
5028 || (ISA_HAS_8CC && mode == TFmode));
5030 else if (ACC_REG_P (regno))
5031 temp = (INTEGRAL_MODE_P (mode)
5032 && (size <= UNITS_PER_WORD
5033 || (ACC_HI_REG_P (regno)
5034 && size == 2 * UNITS_PER_WORD)));
5036 else if (ALL_COP_REG_P (regno))
5037 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5041 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5045 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5046 initialized yet, so we can't use that here. */
5047 gpr_mode = TARGET_64BIT ? DImode : SImode;
5049 /* Provide default values for align_* for 64-bit targets. */
5050 if (TARGET_64BIT && !TARGET_MIPS16)
5052 if (align_loops == 0)
5054 if (align_jumps == 0)
5056 if (align_functions == 0)
5057 align_functions = 8;
5060 /* Function to allocate machine-dependent function status. */
5061 init_machine_status = &mips_init_machine_status;
5063 if (ABI_HAS_64BIT_SYMBOLS)
5065 if (TARGET_EXPLICIT_RELOCS)
5067 mips_split_p[SYMBOL_64_HIGH] = true;
5068 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5069 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5071 mips_split_p[SYMBOL_64_MID] = true;
5072 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5073 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5075 mips_split_p[SYMBOL_64_LOW] = true;
5076 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5077 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5079 mips_split_p[SYMBOL_GENERAL] = true;
5080 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5085 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5087 mips_split_p[SYMBOL_GENERAL] = true;
5088 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5089 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5095 /* The high part is provided by a pseudo copy of $gp. */
5096 mips_split_p[SYMBOL_SMALL_DATA] = true;
5097 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5100 if (TARGET_EXPLICIT_RELOCS)
5102 /* Small data constants are kept whole until after reload,
5103 then lowered by mips_rewrite_small_data. */
5104 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5106 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5109 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5110 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5114 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5115 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5120 /* The HIGH and LO_SUM are matched by special .md patterns. */
5121 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5123 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5124 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5125 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5127 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5128 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5129 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5134 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5136 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5137 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5143 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5144 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5145 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5148 /* Thread-local relocation operators. */
5149 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5150 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5151 mips_split_p[SYMBOL_DTPREL] = 1;
5152 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5153 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5154 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5155 mips_split_p[SYMBOL_TPREL] = 1;
5156 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5157 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5159 /* We don't have a thread pointer access instruction on MIPS16, or
5160 appropriate TLS relocations. */
5162 targetm.have_tls = false;
5164 /* Default to working around R4000 errata only if the processor
5165 was selected explicitly. */
5166 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5167 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5168 target_flags |= MASK_FIX_R4000;
5170 /* Default to working around R4400 errata only if the processor
5171 was selected explicitly. */
5172 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5173 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5174 target_flags |= MASK_FIX_R4400;
5177 /* Implement CONDITIONAL_REGISTER_USAGE. */
5180 mips_conditional_register_usage (void)
5186 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5187 fixed_regs[regno] = call_used_regs[regno] = 1;
5189 if (!TARGET_HARD_FLOAT)
5193 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5194 fixed_regs[regno] = call_used_regs[regno] = 1;
5195 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5196 fixed_regs[regno] = call_used_regs[regno] = 1;
5198 else if (! ISA_HAS_8CC)
5202 /* We only have a single condition code register. We
5203 implement this by hiding all the condition code registers,
5204 and generating RTL that refers directly to ST_REG_FIRST. */
5205 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5206 fixed_regs[regno] = call_used_regs[regno] = 1;
5208 /* In mips16 mode, we permit the $t temporary registers to be used
5209 for reload. We prohibit the unused $s registers, since they
5210 are caller saved, and saving them via a mips16 register would
5211 probably waste more time than just reloading the value. */
5214 fixed_regs[18] = call_used_regs[18] = 1;
5215 fixed_regs[19] = call_used_regs[19] = 1;
5216 fixed_regs[20] = call_used_regs[20] = 1;
5217 fixed_regs[21] = call_used_regs[21] = 1;
5218 fixed_regs[22] = call_used_regs[22] = 1;
5219 fixed_regs[23] = call_used_regs[23] = 1;
5220 fixed_regs[26] = call_used_regs[26] = 1;
5221 fixed_regs[27] = call_used_regs[27] = 1;
5222 fixed_regs[30] = call_used_regs[30] = 1;
5224 /* fp20-23 are now caller saved. */
5225 if (mips_abi == ABI_64)
5228 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5229 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5231 /* Odd registers from fp21 to fp31 are now caller saved. */
5232 if (mips_abi == ABI_N32)
5235 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5236 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5240 /* Allocate a chunk of memory for per-function machine-dependent data. */
5241 static struct machine_function *
5242 mips_init_machine_status (void)
5244 return ((struct machine_function *)
5245 ggc_alloc_cleared (sizeof (struct machine_function)));
5248 /* On the mips16, we want to allocate $24 (T_REG) before other
5249 registers for instructions for which it is possible. This helps
5250 avoid shuffling registers around in order to set up for an xor,
5251 encouraging the compiler to use a cmp instead. */
5254 mips_order_regs_for_local_alloc (void)
5258 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5259 reg_alloc_order[i] = i;
5263 /* It really doesn't matter where we put register 0, since it is
5264 a fixed register anyhow. */
5265 reg_alloc_order[0] = 24;
5266 reg_alloc_order[24] = 0;
5271 /* The MIPS debug format wants all automatic variables and arguments
5272 to be in terms of the virtual frame pointer (stack pointer before
5273 any adjustment in the function), while the MIPS 3.0 linker wants
5274 the frame pointer to be the stack pointer after the initial
5275 adjustment. So, we do the adjustment here. The arg pointer (which
5276 is eliminated) points to the virtual frame pointer, while the frame
5277 pointer (which may be eliminated) points to the stack pointer after
5278 the initial adjustments. */
5281 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5283 rtx offset2 = const0_rtx;
5284 rtx reg = eliminate_constant_term (addr, &offset2);
5287 offset = INTVAL (offset2);
5289 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5290 || reg == hard_frame_pointer_rtx)
5292 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5293 ? compute_frame_size (get_frame_size ())
5294 : cfun->machine->frame.total_size;
5296 /* MIPS16 frame is smaller */
5297 if (frame_pointer_needed && TARGET_MIPS16)
5298 frame_size -= cfun->machine->frame.args_size;
5300 offset = offset - frame_size;
5303 /* sdbout_parms does not want this to crash for unrecognized cases. */
5305 else if (reg != arg_pointer_rtx)
5306 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5313 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5315 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5316 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5317 'h' OP is HIGH, prints %hi(X),
5318 'd' output integer constant in decimal,
5319 'z' if the operand is 0, use $0 instead of normal operand.
5320 'D' print second part of double-word register or memory operand.
5321 'L' print low-order register of double-word register operand.
5322 'M' print high-order register of double-word register operand.
5323 'C' print part of opcode for a branch condition.
5324 'F' print part of opcode for a floating-point branch condition.
5325 'N' print part of opcode for a branch condition, inverted.
5326 'W' print part of opcode for a floating-point branch condition, inverted.
5327 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5328 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5329 't' like 'T', but with the EQ/NE cases reversed
5330 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5331 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5332 'R' print the reloc associated with LO_SUM
5333 'q' print DSP accumulator registers
5335 The punctuation characters are:
5337 '(' Turn on .set noreorder
5338 ')' Turn on .set reorder
5339 '[' Turn on .set noat
5341 '<' Turn on .set nomacro
5342 '>' Turn on .set macro
5343 '{' Turn on .set volatile (not GAS)
5344 '}' Turn on .set novolatile (not GAS)
5345 '&' Turn on .set noreorder if filling delay slots
5346 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5347 '!' Turn on .set nomacro if filling delay slots
5348 '#' Print nop if in a .set noreorder section.
5349 '/' Like '#', but does nothing within a delayed branch sequence
5350 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5351 '@' Print the name of the assembler temporary register (at or $1).
5352 '.' Print the name of the register with a hard-wired zero (zero or $0).
5353 '^' Print the name of the pic call-through register (t9 or $25).
5354 '$' Print the name of the stack pointer register (sp or $29).
5355 '+' Print the name of the gp register (usually gp or $28).
5356 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5359 print_operand (FILE *file, rtx op, int letter)
5361 register enum rtx_code code;
5363 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5368 if (mips_branch_likely)
5373 fputs (reg_names [GP_REG_FIRST + 1], file);
5377 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5381 fputs (reg_names [GP_REG_FIRST + 0], file);
5385 fputs (reg_names[STACK_POINTER_REGNUM], file);
5389 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5393 if (final_sequence != 0 && set_noreorder++ == 0)
5394 fputs (".set\tnoreorder\n\t", file);
5398 if (final_sequence != 0)
5400 if (set_noreorder++ == 0)
5401 fputs (".set\tnoreorder\n\t", file);
5403 if (set_nomacro++ == 0)
5404 fputs (".set\tnomacro\n\t", file);
5409 if (final_sequence != 0 && set_nomacro++ == 0)
5410 fputs ("\n\t.set\tnomacro", file);
5414 if (set_noreorder != 0)
5415 fputs ("\n\tnop", file);
5419 /* Print an extra newline so that the delayed insn is separated
5420 from the following ones. This looks neater and is consistent
5421 with non-nop delayed sequences. */
5422 if (set_noreorder != 0 && final_sequence == 0)
5423 fputs ("\n\tnop\n", file);
5427 if (set_noreorder++ == 0)
5428 fputs (".set\tnoreorder\n\t", file);
5432 if (set_noreorder == 0)
5433 error ("internal error: %%) found without a %%( in assembler pattern");
5435 else if (--set_noreorder == 0)
5436 fputs ("\n\t.set\treorder", file);
5441 if (set_noat++ == 0)
5442 fputs (".set\tnoat\n\t", file);
5447 error ("internal error: %%] found without a %%[ in assembler pattern");
5448 else if (--set_noat == 0)
5449 fputs ("\n\t.set\tat", file);
5454 if (set_nomacro++ == 0)
5455 fputs (".set\tnomacro\n\t", file);
5459 if (set_nomacro == 0)
5460 error ("internal error: %%> found without a %%< in assembler pattern");
5461 else if (--set_nomacro == 0)
5462 fputs ("\n\t.set\tmacro", file);
5467 if (set_volatile++ == 0)
5468 fputs ("#.set\tvolatile\n\t", file);
5472 if (set_volatile == 0)
5473 error ("internal error: %%} found without a %%{ in assembler pattern");
5474 else if (--set_volatile == 0)
5475 fputs ("\n\t#.set\tnovolatile", file);
5481 if (align_labels_log > 0)
5482 ASM_OUTPUT_ALIGN (file, align_labels_log);
5487 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5496 error ("PRINT_OPERAND null pointer");
5500 code = GET_CODE (op);
5505 case EQ: fputs ("eq", file); break;
5506 case NE: fputs ("ne", file); break;
5507 case GT: fputs ("gt", file); break;
5508 case GE: fputs ("ge", file); break;
5509 case LT: fputs ("lt", file); break;
5510 case LE: fputs ("le", file); break;
5511 case GTU: fputs ("gtu", file); break;
5512 case GEU: fputs ("geu", file); break;
5513 case LTU: fputs ("ltu", file); break;
5514 case LEU: fputs ("leu", file); break;
5516 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5519 else if (letter == 'N')
5522 case EQ: fputs ("ne", file); break;
5523 case NE: fputs ("eq", file); break;
5524 case GT: fputs ("le", file); break;
5525 case GE: fputs ("lt", file); break;
5526 case LT: fputs ("ge", file); break;
5527 case LE: fputs ("gt", file); break;
5528 case GTU: fputs ("leu", file); break;
5529 case GEU: fputs ("ltu", file); break;
5530 case LTU: fputs ("geu", file); break;
5531 case LEU: fputs ("gtu", file); break;
5533 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5536 else if (letter == 'F')
5539 case EQ: fputs ("c1f", file); break;
5540 case NE: fputs ("c1t", file); break;
5542 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5545 else if (letter == 'W')
5548 case EQ: fputs ("c1t", file); break;
5549 case NE: fputs ("c1f", file); break;
5551 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5554 else if (letter == 'h')
5556 if (GET_CODE (op) == HIGH)
5559 print_operand_reloc (file, op, mips_hi_relocs);
5562 else if (letter == 'R')
5563 print_operand_reloc (file, op, mips_lo_relocs);
5565 else if (letter == 'Y')
5567 if (GET_CODE (op) == CONST_INT
5568 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5569 < ARRAY_SIZE (mips_fp_conditions)))
5570 fputs (mips_fp_conditions[INTVAL (op)], file);
5572 output_operand_lossage ("invalid %%Y value");
5575 else if (letter == 'Z')
5579 print_operand (file, op, 0);
5584 else if (letter == 'q')
5589 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5591 regnum = REGNO (op);
5592 if (MD_REG_P (regnum))
5593 fprintf (file, "$ac0");
5594 else if (DSP_ACC_REG_P (regnum))
5595 fprintf (file, "$ac%c", reg_names[regnum][3]);
5597 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5600 else if (code == REG || code == SUBREG)
5602 register int regnum;
5605 regnum = REGNO (op);
5607 regnum = true_regnum (op);
5609 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5610 || (letter == 'L' && WORDS_BIG_ENDIAN)
5614 fprintf (file, "%s", reg_names[regnum]);
5617 else if (code == MEM)
5620 output_address (plus_constant (XEXP (op, 0), 4));
5622 output_address (XEXP (op, 0));
5625 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5626 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5628 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5629 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5631 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5632 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5634 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5635 fputs (reg_names[GP_REG_FIRST], file);
5637 else if (letter == 'd' || letter == 'x' || letter == 'X')
5638 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5640 else if (letter == 'T' || letter == 't')
5642 int truth = (code == NE) == (letter == 'T');
5643 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5646 else if (CONST_GP_P (op))
5647 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5650 output_addr_const (file, op);
5654 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5655 RELOCS is the array of relocations to use. */
5658 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5660 enum mips_symbol_type symbol_type;
5663 HOST_WIDE_INT offset;
5665 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5666 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5668 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5669 mips_split_const (op, &base, &offset);
5670 if (UNSPEC_ADDRESS_P (base))
5671 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5673 fputs (relocs[symbol_type], file);
5674 output_addr_const (file, op);
5675 for (p = relocs[symbol_type]; *p != 0; p++)
5680 /* Output address operand X to FILE. */
5683 print_operand_address (FILE *file, rtx x)
5685 struct mips_address_info addr;
5687 if (mips_classify_address (&addr, x, word_mode, true))
5691 print_operand (file, addr.offset, 0);
5692 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5695 case ADDRESS_LO_SUM:
5696 print_operand (file, addr.offset, 'R');
5697 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5700 case ADDRESS_CONST_INT:
5701 output_addr_const (file, x);
5702 fprintf (file, "(%s)", reg_names[0]);
5705 case ADDRESS_SYMBOLIC:
5706 output_addr_const (file, x);
5712 /* When using assembler macros, keep track of all of small-data externs
5713 so that mips_file_end can emit the appropriate declarations for them.
5715 In most cases it would be safe (though pointless) to emit .externs
5716 for other symbols too. One exception is when an object is within
5717 the -G limit but declared by the user to be in a section other
5718 than .sbss or .sdata. */
5721 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5723 register struct extern_list *p;
5725 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5727 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5728 p->next = extern_head;
5730 p->size = int_size_in_bytes (TREE_TYPE (decl));
5734 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5736 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5737 p->next = extern_head;
5748 irix_output_external_libcall (rtx fun)
5750 register struct extern_list *p;
5752 if (mips_abi == ABI_32)
5754 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5755 p->next = extern_head;
5756 p->name = XSTR (fun, 0);
5763 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5764 put out a MIPS ECOFF file and a stab. */
5767 mips_output_filename (FILE *stream, const char *name)
5770 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5772 if (write_symbols == DWARF2_DEBUG)
5774 else if (mips_output_filename_first_time)
5776 mips_output_filename_first_time = 0;
5777 num_source_filenames += 1;
5778 current_function_file = name;
5779 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5780 output_quoted_string (stream, name);
5781 putc ('\n', stream);
5784 /* If we are emitting stabs, let dbxout.c handle this (except for
5785 the mips_output_filename_first_time case). */
5786 else if (write_symbols == DBX_DEBUG)
5789 else if (name != current_function_file
5790 && strcmp (name, current_function_file) != 0)
5792 num_source_filenames += 1;
5793 current_function_file = name;
5794 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5795 output_quoted_string (stream, name);
5796 putc ('\n', stream);
5800 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5801 that should be written before the opening quote, such as "\t.ascii\t"
5802 for real string data or "\t# " for a comment. */
5805 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5810 register const unsigned char *string =
5811 (const unsigned char *)string_param;
5813 fprintf (stream, "%s\"", prefix);
5814 for (i = 0; i < len; i++)
5816 register int c = string[i];
5820 if (c == '\\' || c == '\"')
5822 putc ('\\', stream);
5830 fprintf (stream, "\\%03o", c);
5834 if (cur_pos > 72 && i+1 < len)
5837 fprintf (stream, "\"\n%s\"", prefix);
5840 fprintf (stream, "\"\n");
5843 /* Implement TARGET_ASM_FILE_START. */
5846 mips_file_start (void)
5848 default_file_start ();
5852 /* Generate a special section to describe the ABI switches used to
5853 produce the resultant binary. This used to be done by the assembler
5854 setting bits in the ELF header's flags field, but we have run out of
5855 bits. GDB needs this information in order to be able to correctly
5856 debug these binaries. See the function mips_gdbarch_init() in
5857 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5858 causes unnecessary IRIX 6 ld warnings. */
5859 const char * abi_string = NULL;
5863 case ABI_32: abi_string = "abi32"; break;
5864 case ABI_N32: abi_string = "abiN32"; break;
5865 case ABI_64: abi_string = "abi64"; break;
5866 case ABI_O64: abi_string = "abiO64"; break;
5867 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5871 /* Note - we use fprintf directly rather than calling switch_to_section
5872 because in this way we can avoid creating an allocated section. We
5873 do not want this section to take up any space in the running
5875 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5877 /* There is no ELF header flag to distinguish long32 forms of the
5878 EABI from long64 forms. Emit a special section to help tools
5879 such as GDB. Do the same for o64, which is sometimes used with
5881 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
5882 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5883 TARGET_LONG64 ? 64 : 32);
5885 /* Restore the default section. */
5886 fprintf (asm_out_file, "\t.previous\n");
5889 /* Generate the pseudo ops that System V.4 wants. */
5890 if (TARGET_ABICALLS)
5891 fprintf (asm_out_file, "\t.abicalls\n");
5894 fprintf (asm_out_file, "\t.set\tmips16\n");
5896 if (flag_verbose_asm)
5897 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5899 mips_section_threshold, mips_arch_info->name, mips_isa);
5902 #ifdef BSS_SECTION_ASM_OP
5903 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5904 in the use of sbss. */
5907 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5908 unsigned HOST_WIDE_INT size, int align)
5910 extern tree last_assemble_variable_decl;
5912 if (mips_in_small_data_p (decl))
5913 switch_to_section (get_named_section (NULL, ".sbss", 0));
5915 switch_to_section (bss_section);
5916 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5917 last_assemble_variable_decl = decl;
5918 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5919 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5923 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5924 .externs for any small-data variables that turned out to be external. */
5927 mips_file_end (void)
5930 struct extern_list *p;
5934 fputs ("\n", asm_out_file);
5936 for (p = extern_head; p != 0; p = p->next)
5938 name_tree = get_identifier (p->name);
5940 /* Positively ensure only one .extern for any given symbol. */
5941 if (!TREE_ASM_WRITTEN (name_tree)
5942 && TREE_SYMBOL_REFERENCED (name_tree))
5944 TREE_ASM_WRITTEN (name_tree) = 1;
5945 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5946 `.global name .text' directive for every used but
5947 undefined function. If we don't, the linker may perform
5948 an optimization (skipping over the insns that set $gp)
5949 when it is unsafe. */
5950 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5952 fputs ("\t.globl ", asm_out_file);
5953 assemble_name (asm_out_file, p->name);
5954 fputs (" .text\n", asm_out_file);
5958 fputs ("\t.extern\t", asm_out_file);
5959 assemble_name (asm_out_file, p->name);
5960 fprintf (asm_out_file, ", %d\n", p->size);
5967 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5968 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5971 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5972 unsigned HOST_WIDE_INT size,
5975 /* If the target wants uninitialized const declarations in
5976 .rdata then don't put them in .comm. */
5977 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5978 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5979 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5981 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5982 targetm.asm_out.globalize_label (stream, name);
5984 switch_to_section (readonly_data_section);
5985 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5986 mips_declare_object (stream, name, "",
5987 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5991 mips_declare_common_object (stream, name, "\n\t.comm\t",
5995 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5996 NAME is the name of the object and ALIGN is the required alignment
5997 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5998 alignment argument. */
6001 mips_declare_common_object (FILE *stream, const char *name,
6002 const char *init_string,
6003 unsigned HOST_WIDE_INT size,
6004 unsigned int align, bool takes_alignment_p)
6006 if (!takes_alignment_p)
6008 size += (align / BITS_PER_UNIT) - 1;
6009 size -= size % (align / BITS_PER_UNIT);
6010 mips_declare_object (stream, name, init_string,
6011 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6014 mips_declare_object (stream, name, init_string,
6015 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6016 size, align / BITS_PER_UNIT);
6019 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6020 macros, mark the symbol as written so that mips_file_end won't emit an
6021 .extern for it. STREAM is the output file, NAME is the name of the
6022 symbol, INIT_STRING is the string that should be written before the
6023 symbol and FINAL_STRING is the string that should be written after it.
6024 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6027 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6028 const char *final_string, ...)
6032 fputs (init_string, stream);
6033 assemble_name (stream, name);
6034 va_start (ap, final_string);
6035 vfprintf (stream, final_string, ap);
6038 if (!TARGET_EXPLICIT_RELOCS)
6040 tree name_tree = get_identifier (name);
6041 TREE_ASM_WRITTEN (name_tree) = 1;
6045 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6046 extern int size_directive_output;
6048 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6049 definitions except that it uses mips_declare_object() to emit the label. */
6052 mips_declare_object_name (FILE *stream, const char *name,
6053 tree decl ATTRIBUTE_UNUSED)
6055 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6056 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6059 size_directive_output = 0;
6060 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6064 size_directive_output = 1;
6065 size = int_size_in_bytes (TREE_TYPE (decl));
6066 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6069 mips_declare_object (stream, name, "", ":\n");
6072 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6075 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6079 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6080 if (!flag_inhibit_size_directive
6081 && DECL_SIZE (decl) != 0
6082 && !at_end && top_level
6083 && DECL_INITIAL (decl) == error_mark_node
6084 && !size_directive_output)
6088 size_directive_output = 1;
6089 size = int_size_in_bytes (TREE_TYPE (decl));
6090 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6095 /* Return true if X is a small data address that can be rewritten
6099 mips_rewrite_small_data_p (rtx x)
6101 enum mips_symbol_type symbol_type;
6103 return (TARGET_EXPLICIT_RELOCS
6104 && mips_symbolic_constant_p (x, &symbol_type)
6105 && symbol_type == SYMBOL_SMALL_DATA);
6109 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6112 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6114 if (GET_CODE (*loc) == LO_SUM)
6117 return mips_rewrite_small_data_p (*loc);
6120 /* Return true if OP refers to small data symbols directly, not through
6124 mips_small_data_pattern_p (rtx op)
6126 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6129 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6132 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6134 if (mips_rewrite_small_data_p (*loc))
6135 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6137 if (GET_CODE (*loc) == LO_SUM)
6143 /* If possible, rewrite OP so that it refers to small data using
6144 explicit relocations. */
6147 mips_rewrite_small_data (rtx op)
6149 op = copy_insn (op);
6150 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6154 /* Return true if the current function has an insn that implicitly
6158 mips_function_has_gp_insn (void)
6160 /* Don't bother rechecking if we found one last time. */
6161 if (!cfun->machine->has_gp_insn_p)
6165 push_topmost_sequence ();
6166 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6168 && GET_CODE (PATTERN (insn)) != USE
6169 && GET_CODE (PATTERN (insn)) != CLOBBER
6170 && (get_attr_got (insn) != GOT_UNSET
6171 || small_data_pattern (PATTERN (insn), VOIDmode)))
6173 pop_topmost_sequence ();
6175 cfun->machine->has_gp_insn_p = (insn != 0);
6177 return cfun->machine->has_gp_insn_p;
6181 /* Return the register that should be used as the global pointer
6182 within this function. Return 0 if the function doesn't need
6183 a global pointer. */
6186 mips_global_pointer (void)
6190 /* $gp is always available in non-abicalls code. */
6191 if (!TARGET_ABICALLS)
6192 return GLOBAL_POINTER_REGNUM;
6194 /* We must always provide $gp when it is used implicitly. */
6195 if (!TARGET_EXPLICIT_RELOCS)
6196 return GLOBAL_POINTER_REGNUM;
6198 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6200 if (current_function_profile)
6201 return GLOBAL_POINTER_REGNUM;
6203 /* If the function has a nonlocal goto, $gp must hold the correct
6204 global pointer for the target function. */
6205 if (current_function_has_nonlocal_goto)
6206 return GLOBAL_POINTER_REGNUM;
6208 /* If the gp is never referenced, there's no need to initialize it.
6209 Note that reload can sometimes introduce constant pool references
6210 into a function that otherwise didn't need them. For example,
6211 suppose we have an instruction like:
6213 (set (reg:DF R1) (float:DF (reg:SI R2)))
6215 If R2 turns out to be constant such as 1, the instruction may have a
6216 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6217 using this constant if R2 doesn't get allocated to a register.
6219 In cases like these, reload will have added the constant to the pool
6220 but no instruction will yet refer to it. */
6221 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6222 && !current_function_uses_const_pool
6223 && !mips_function_has_gp_insn ())
6226 /* We need a global pointer, but perhaps we can use a call-clobbered
6227 register instead of $gp. */
6228 if (TARGET_NEWABI && current_function_is_leaf)
6229 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6230 if (!regs_ever_live[regno]
6231 && call_used_regs[regno]
6232 && !fixed_regs[regno]
6233 && regno != PIC_FUNCTION_ADDR_REGNUM)
6236 return GLOBAL_POINTER_REGNUM;
6240 /* Return true if the current function must save REGNO. */
6243 mips_save_reg_p (unsigned int regno)
6245 /* We only need to save $gp for NewABI PIC. */
6246 if (regno == GLOBAL_POINTER_REGNUM)
6247 return (TARGET_ABICALLS && TARGET_NEWABI
6248 && cfun->machine->global_pointer == regno);
6250 /* Check call-saved registers. */
6251 if (regs_ever_live[regno] && !call_used_regs[regno])
6254 /* We need to save the old frame pointer before setting up a new one. */
6255 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6258 /* We need to save the incoming return address if it is ever clobbered
6259 within the function. */
6260 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6267 return_type = DECL_RESULT (current_function_decl);
6269 /* $18 is a special case in mips16 code. It may be used to call
6270 a function which returns a floating point value, but it is
6271 marked in call_used_regs. */
6272 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6275 /* $31 is also a special case. It will be used to copy a return
6276 value into the floating point registers if the return value is
6278 if (regno == GP_REG_FIRST + 31
6279 && mips16_hard_float
6280 && !aggregate_value_p (return_type, current_function_decl)
6281 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6282 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6290 /* Return the bytes needed to compute the frame pointer from the current
6291 stack pointer. SIZE is the size (in bytes) of the local variables.
6293 MIPS stack frames look like:
6295 Before call After call
6296 +-----------------------+ +-----------------------+
6299 | caller's temps. | | caller's temps. |
6301 +-----------------------+ +-----------------------+
6303 | arguments on stack. | | arguments on stack. |
6305 +-----------------------+ +-----------------------+
6306 | 4 words to save | | 4 words to save |
6307 | arguments passed | | arguments passed |
6308 | in registers, even | | in registers, even |
6309 SP->| if not passed. | VFP->| if not passed. |
6310 +-----------------------+ +-----------------------+
6312 | fp register save |
6314 +-----------------------+
6316 | gp register save |
6318 +-----------------------+
6322 +-----------------------+
6324 | alloca allocations |
6326 +-----------------------+
6328 | GP save for V.4 abi |
6330 +-----------------------+
6332 | arguments on stack |
6334 +-----------------------+
6336 | arguments passed |
6337 | in registers, even |
6338 low SP->| if not passed. |
6339 memory +-----------------------+
6344 compute_frame_size (HOST_WIDE_INT size)
6347 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6348 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6349 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6350 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6351 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6352 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6353 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6354 unsigned int mask; /* mask of saved gp registers */
6355 unsigned int fmask; /* mask of saved fp registers */
6357 cfun->machine->global_pointer = mips_global_pointer ();
6363 var_size = MIPS_STACK_ALIGN (size);
6364 args_size = current_function_outgoing_args_size;
6365 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6367 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6368 functions. If the function has local variables, we're committed
6369 to allocating it anyway. Otherwise reclaim it here. */
6370 if (var_size == 0 && current_function_is_leaf)
6371 cprestore_size = args_size = 0;
6373 /* The MIPS 3.0 linker does not like functions that dynamically
6374 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6375 looks like we are trying to create a second frame pointer to the
6376 function, so allocate some stack space to make it happy. */
6378 if (args_size == 0 && current_function_calls_alloca)
6379 args_size = 4 * UNITS_PER_WORD;
6381 total_size = var_size + args_size + cprestore_size;
6383 /* Calculate space needed for gp registers. */
6384 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6385 if (mips_save_reg_p (regno))
6387 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6388 mask |= 1 << (regno - GP_REG_FIRST);
6391 /* We need to restore these for the handler. */
6392 if (current_function_calls_eh_return)
6397 regno = EH_RETURN_DATA_REGNO (i);
6398 if (regno == INVALID_REGNUM)
6400 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6401 mask |= 1 << (regno - GP_REG_FIRST);
6405 /* This loop must iterate over the same space as its companion in
6406 save_restore_insns. */
6407 for (regno = (FP_REG_LAST - FP_INC + 1);
6408 regno >= FP_REG_FIRST;
6411 if (mips_save_reg_p (regno))
6413 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6414 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6418 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6419 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6421 /* Add in the space required for saving incoming register arguments. */
6422 total_size += current_function_pretend_args_size;
6423 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6425 /* Save other computed information. */
6426 cfun->machine->frame.total_size = total_size;
6427 cfun->machine->frame.var_size = var_size;
6428 cfun->machine->frame.args_size = args_size;
6429 cfun->machine->frame.cprestore_size = cprestore_size;
6430 cfun->machine->frame.gp_reg_size = gp_reg_size;
6431 cfun->machine->frame.fp_reg_size = fp_reg_size;
6432 cfun->machine->frame.mask = mask;
6433 cfun->machine->frame.fmask = fmask;
6434 cfun->machine->frame.initialized = reload_completed;
6435 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6436 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6440 HOST_WIDE_INT offset;
6442 offset = (args_size + cprestore_size + var_size
6443 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6444 cfun->machine->frame.gp_sp_offset = offset;
6445 cfun->machine->frame.gp_save_offset = offset - total_size;
6449 cfun->machine->frame.gp_sp_offset = 0;
6450 cfun->machine->frame.gp_save_offset = 0;
6455 HOST_WIDE_INT offset;
6457 offset = (args_size + cprestore_size + var_size
6458 + gp_reg_rounded + fp_reg_size
6459 - FP_INC * UNITS_PER_FPREG);
6460 cfun->machine->frame.fp_sp_offset = offset;
6461 cfun->machine->frame.fp_save_offset = offset - total_size;
6465 cfun->machine->frame.fp_sp_offset = 0;
6466 cfun->machine->frame.fp_save_offset = 0;
6469 /* Ok, we're done. */
6473 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6474 pointer or argument pointer. TO is either the stack pointer or
6475 hard frame pointer. */
6478 mips_initial_elimination_offset (int from, int to)
6480 HOST_WIDE_INT offset;
6482 compute_frame_size (get_frame_size ());
6484 /* Set OFFSET to the offset from the stack pointer. */
6487 case FRAME_POINTER_REGNUM:
6491 case ARG_POINTER_REGNUM:
6492 offset = (cfun->machine->frame.total_size
6493 - current_function_pretend_args_size);
6500 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6501 offset -= cfun->machine->frame.args_size;
6506 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6507 back to a previous frame. */
6509 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6514 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6517 /* Use FN to save or restore register REGNO. MODE is the register's
6518 mode and OFFSET is the offset of its save slot from the current
6522 mips_save_restore_reg (enum machine_mode mode, int regno,
6523 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6527 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6529 fn (gen_rtx_REG (mode, regno), mem);
6533 /* Call FN for each register that is saved by the current function.
6534 SP_OFFSET is the offset of the current stack pointer from the start
6538 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6540 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6542 enum machine_mode fpr_mode;
6543 HOST_WIDE_INT offset;
6546 /* Save registers starting from high to low. The debuggers prefer at least
6547 the return register be stored at func+4, and also it allows us not to
6548 need a nop in the epilog if at least one register is reloaded in
6549 addition to return address. */
6550 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6551 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6552 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6554 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6555 offset -= GET_MODE_SIZE (gpr_mode);
6558 /* This loop must iterate over the same space as its companion in
6559 compute_frame_size. */
6560 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6561 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6562 for (regno = (FP_REG_LAST - FP_INC + 1);
6563 regno >= FP_REG_FIRST;
6565 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6567 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6568 offset -= GET_MODE_SIZE (fpr_mode);
6573 /* If we're generating n32 or n64 abicalls, and the current function
6574 does not use $28 as its global pointer, emit a cplocal directive.
6575 Use pic_offset_table_rtx as the argument to the directive. */
6578 mips_output_cplocal (void)
6580 if (!TARGET_EXPLICIT_RELOCS
6581 && cfun->machine->global_pointer > 0
6582 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6583 output_asm_insn (".cplocal %+", 0);
6586 /* Return the style of GP load sequence that is being used for the
6587 current function. */
6589 enum mips_loadgp_style
6590 mips_current_loadgp_style (void)
6592 if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0)
6595 if (TARGET_ABSOLUTE_ABICALLS)
6596 return LOADGP_ABSOLUTE;
6598 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6601 /* The __gnu_local_gp symbol. */
6603 static GTY(()) rtx mips_gnu_local_gp;
6605 /* If we're generating n32 or n64 abicalls, emit instructions
6606 to set up the global pointer. */
6609 mips_emit_loadgp (void)
6611 rtx addr, offset, incoming_address;
6613 switch (mips_current_loadgp_style ())
6615 case LOADGP_ABSOLUTE:
6616 if (mips_gnu_local_gp == NULL)
6618 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6619 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6621 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp));
6625 addr = XEXP (DECL_RTL (current_function_decl), 0);
6626 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6627 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6628 emit_insn (gen_loadgp (offset, incoming_address));
6629 if (!TARGET_EXPLICIT_RELOCS)
6630 emit_insn (gen_loadgp_blockage ());
6638 /* Set up the stack and frame (if desired) for the function. */
6641 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6644 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6646 #ifdef SDB_DEBUGGING_INFO
6647 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6648 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6651 /* In mips16 mode, we may need to generate a 32 bit to handle
6652 floating point arguments. The linker will arrange for any 32 bit
6653 functions to call this stub, which will then jump to the 16 bit
6655 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6656 && current_function_args_info.fp_code != 0)
6657 build_mips16_function_stub (file);
6659 if (!FUNCTION_NAME_ALREADY_DECLARED)
6661 /* Get the function name the same way that toplev.c does before calling
6662 assemble_start_function. This is needed so that the name used here
6663 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6664 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6666 if (!flag_inhibit_size_directive)
6668 fputs ("\t.ent\t", file);
6669 assemble_name (file, fnname);
6673 assemble_name (file, fnname);
6674 fputs (":\n", file);
6677 /* Stop mips_file_end from treating this function as external. */
6678 if (TARGET_IRIX && mips_abi == ABI_32)
6679 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6681 if (!flag_inhibit_size_directive)
6683 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6685 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6686 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6687 ", args= " HOST_WIDE_INT_PRINT_DEC
6688 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6689 (reg_names[(frame_pointer_needed)
6690 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6691 ((frame_pointer_needed && TARGET_MIPS16)
6692 ? tsize - cfun->machine->frame.args_size
6694 reg_names[GP_REG_FIRST + 31],
6695 cfun->machine->frame.var_size,
6696 cfun->machine->frame.num_gp,
6697 cfun->machine->frame.num_fp,
6698 cfun->machine->frame.args_size,
6699 cfun->machine->frame.cprestore_size);
6701 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6702 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6703 cfun->machine->frame.mask,
6704 cfun->machine->frame.gp_save_offset);
6705 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6706 cfun->machine->frame.fmask,
6707 cfun->machine->frame.fp_save_offset);
6710 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6711 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6714 if (mips_current_loadgp_style () == LOADGP_OLDABI)
6716 /* Handle the initialization of $gp for SVR4 PIC. */
6717 if (!cfun->machine->all_noreorder_p)
6718 output_asm_insn ("%(.cpload\t%^%)", 0);
6720 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6722 else if (cfun->machine->all_noreorder_p)
6723 output_asm_insn ("%(%<", 0);
6725 /* Tell the assembler which register we're using as the global
6726 pointer. This is needed for thunks, since they can use either
6727 explicit relocs or assembler macros. */
6728 mips_output_cplocal ();
6731 /* Make the last instruction frame related and note that it performs
6732 the operation described by FRAME_PATTERN. */
6735 mips_set_frame_expr (rtx frame_pattern)
6739 insn = get_last_insn ();
6740 RTX_FRAME_RELATED_P (insn) = 1;
6741 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6747 /* Return a frame-related rtx that stores REG at MEM.
6748 REG must be a single register. */
6751 mips_frame_set (rtx mem, rtx reg)
6755 /* If we're saving the return address register and the dwarf return
6756 address column differs from the hard register number, adjust the
6757 note reg to refer to the former. */
6758 if (REGNO (reg) == GP_REG_FIRST + 31
6759 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6760 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6762 set = gen_rtx_SET (VOIDmode, mem, reg);
6763 RTX_FRAME_RELATED_P (set) = 1;
6769 /* Save register REG to MEM. Make the instruction frame-related. */
6772 mips_save_reg (rtx reg, rtx mem)
6774 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6778 if (mips_split_64bit_move_p (mem, reg))
6779 mips_split_64bit_move (mem, reg);
6781 emit_move_insn (mem, reg);
6783 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6784 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6785 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6790 && REGNO (reg) != GP_REG_FIRST + 31
6791 && !M16_REG_P (REGNO (reg)))
6793 /* Save a non-mips16 register by moving it through a temporary.
6794 We don't need to do this for $31 since there's a special
6795 instruction for it. */
6796 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6797 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6800 emit_move_insn (mem, reg);
6802 mips_set_frame_expr (mips_frame_set (mem, reg));
6807 /* Expand the prologue into a bunch of separate insns. */
6810 mips_expand_prologue (void)
6814 if (cfun->machine->global_pointer > 0)
6815 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6817 size = compute_frame_size (get_frame_size ());
6819 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6820 bytes beforehand; this is enough to cover the register save area
6821 without going out of range. */
6822 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6824 HOST_WIDE_INT step1;
6826 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6827 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6829 GEN_INT (-step1)))) = 1;
6831 mips_for_each_saved_reg (size, mips_save_reg);
6834 /* Allocate the rest of the frame. */
6837 if (SMALL_OPERAND (-size))
6838 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6840 GEN_INT (-size)))) = 1;
6843 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6846 /* There are no instructions to add or subtract registers
6847 from the stack pointer, so use the frame pointer as a
6848 temporary. We should always be using a frame pointer
6849 in this case anyway. */
6850 gcc_assert (frame_pointer_needed);
6851 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6852 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6853 hard_frame_pointer_rtx,
6854 MIPS_PROLOGUE_TEMP (Pmode)));
6855 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6858 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6860 MIPS_PROLOGUE_TEMP (Pmode)));
6862 /* Describe the combined effect of the previous instructions. */
6864 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6865 plus_constant (stack_pointer_rtx, -size)));
6869 /* Set up the frame pointer, if we're using one. In mips16 code,
6870 we point the frame pointer ahead of the outgoing argument area.
6871 This should allow more variables & incoming arguments to be
6872 accessed with unextended instructions. */
6873 if (frame_pointer_needed)
6875 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6877 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6878 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6880 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6885 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6886 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6887 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6888 hard_frame_pointer_rtx,
6889 MIPS_PROLOGUE_TEMP (Pmode)));
6891 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6892 plus_constant (stack_pointer_rtx,
6893 cfun->machine->frame.args_size)));
6897 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6898 stack_pointer_rtx)) = 1;
6901 mips_emit_loadgp ();
6903 /* If generating o32/o64 abicalls, save $gp on the stack. */
6904 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6905 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6907 /* If we are profiling, make sure no instructions are scheduled before
6908 the call to mcount. */
6910 if (current_function_profile)
6911 emit_insn (gen_blockage ());
6914 /* Do any necessary cleanup after a function to restore stack, frame,
6917 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6920 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6921 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6923 /* Reinstate the normal $gp. */
6924 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6925 mips_output_cplocal ();
6927 if (cfun->machine->all_noreorder_p)
6929 /* Avoid using %>%) since it adds excess whitespace. */
6930 output_asm_insn (".set\tmacro", 0);
6931 output_asm_insn (".set\treorder", 0);
6932 set_noreorder = set_nomacro = 0;
6935 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6939 /* Get the function name the same way that toplev.c does before calling
6940 assemble_start_function. This is needed so that the name used here
6941 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6942 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6943 fputs ("\t.end\t", file);
6944 assemble_name (file, fnname);
6949 /* Emit instructions to restore register REG from slot MEM. */
6952 mips_restore_reg (rtx reg, rtx mem)
6954 /* There's no mips16 instruction to load $31 directly. Load into
6955 $7 instead and adjust the return insn appropriately. */
6956 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6957 reg = gen_rtx_REG (GET_MODE (reg), 7);
6959 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6961 /* Can't restore directly; move through a temporary. */
6962 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6963 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6966 emit_move_insn (reg, mem);
6970 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6971 if this epilogue precedes a sibling call, false if it is for a normal
6972 "epilogue" pattern. */
6975 mips_expand_epilogue (int sibcall_p)
6977 HOST_WIDE_INT step1, step2;
6980 if (!sibcall_p && mips_can_use_return_insn ())
6982 emit_jump_insn (gen_return ());
6986 /* Split the frame into two. STEP1 is the amount of stack we should
6987 deallocate before restoring the registers. STEP2 is the amount we
6988 should deallocate afterwards.
6990 Start off by assuming that no registers need to be restored. */
6991 step1 = cfun->machine->frame.total_size;
6994 /* Work out which register holds the frame address. Account for the
6995 frame pointer offset used by mips16 code. */
6996 if (!frame_pointer_needed)
6997 base = stack_pointer_rtx;
7000 base = hard_frame_pointer_rtx;
7002 step1 -= cfun->machine->frame.args_size;
7005 /* If we need to restore registers, deallocate as much stack as
7006 possible in the second step without going out of range. */
7007 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7009 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7013 /* Set TARGET to BASE + STEP1. */
7019 /* Get an rtx for STEP1 that we can add to BASE. */
7020 adjust = GEN_INT (step1);
7021 if (!SMALL_OPERAND (step1))
7023 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7024 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7027 /* Normal mode code can copy the result straight into $sp. */
7029 target = stack_pointer_rtx;
7031 emit_insn (gen_add3_insn (target, base, adjust));
7034 /* Copy TARGET into the stack pointer. */
7035 if (target != stack_pointer_rtx)
7036 emit_move_insn (stack_pointer_rtx, target);
7038 /* If we're using addressing macros for n32/n64 abicalls, $gp is
7039 implicitly used by all SYMBOL_REFs. We must emit a blockage
7040 insn before restoring it. */
7041 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7042 emit_insn (gen_blockage ());
7044 /* Restore the registers. */
7045 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7048 /* Deallocate the final bit of the frame. */
7050 emit_insn (gen_add3_insn (stack_pointer_rtx,
7054 /* Add in the __builtin_eh_return stack adjustment. We need to
7055 use a temporary in mips16 code. */
7056 if (current_function_calls_eh_return)
7060 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7061 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7062 MIPS_EPILOGUE_TEMP (Pmode),
7063 EH_RETURN_STACKADJ_RTX));
7064 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7067 emit_insn (gen_add3_insn (stack_pointer_rtx,
7069 EH_RETURN_STACKADJ_RTX));
7074 /* The mips16 loads the return address into $7, not $31. */
7075 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7076 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7077 GP_REG_FIRST + 7)));
7079 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7080 GP_REG_FIRST + 31)));
7084 /* Return nonzero if this function is known to have a null epilogue.
7085 This allows the optimizer to omit jumps to jumps if no stack
7089 mips_can_use_return_insn (void)
7093 if (! reload_completed)
7096 if (regs_ever_live[31] || current_function_profile)
7099 return_type = DECL_RESULT (current_function_decl);
7101 /* In mips16 mode, a function which returns a floating point value
7102 needs to arrange to copy the return value into the floating point
7105 && mips16_hard_float
7106 && ! aggregate_value_p (return_type, current_function_decl)
7107 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7108 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7111 if (cfun->machine->frame.initialized)
7112 return cfun->machine->frame.total_size == 0;
7114 return compute_frame_size (get_frame_size ()) == 0;
7117 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7118 in order to avoid duplicating too much logic from elsewhere. */
7121 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7122 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7125 rtx this, temp1, temp2, insn, fnaddr;
7127 /* Pretend to be a post-reload pass while generating rtl. */
7129 reload_completed = 1;
7130 reset_block_changes ();
7132 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7133 for TARGET_NEWABI since the latter is a call-saved register. */
7134 if (TARGET_ABICALLS)
7135 cfun->machine->global_pointer
7136 = REGNO (pic_offset_table_rtx)
7137 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7139 /* Set up the global pointer for n32 or n64 abicalls. */
7140 mips_emit_loadgp ();
7142 /* We need two temporary registers in some cases. */
7143 temp1 = gen_rtx_REG (Pmode, 2);
7144 temp2 = gen_rtx_REG (Pmode, 3);
7146 /* Find out which register contains the "this" pointer. */
7147 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7148 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7150 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7152 /* Add DELTA to THIS. */
7155 rtx offset = GEN_INT (delta);
7156 if (!SMALL_OPERAND (delta))
7158 emit_move_insn (temp1, offset);
7161 emit_insn (gen_add3_insn (this, this, offset));
7164 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7165 if (vcall_offset != 0)
7169 /* Set TEMP1 to *THIS. */
7170 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7172 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7173 addr = mips_add_offset (temp2, temp1, vcall_offset);
7175 /* Load the offset and add it to THIS. */
7176 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7177 emit_insn (gen_add3_insn (this, this, temp1));
7180 /* Jump to the target function. Use a sibcall if direct jumps are
7181 allowed, otherwise load the address into a register first. */
7182 fnaddr = XEXP (DECL_RTL (function), 0);
7183 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7185 /* This is messy. gas treats "la $25,foo" as part of a call
7186 sequence and may allow a global "foo" to be lazily bound.
7187 The general move patterns therefore reject this combination.
7189 In this context, lazy binding would actually be OK for o32 and o64,
7190 but it's still wrong for n32 and n64; see mips_load_call_address.
7191 We must therefore load the address via a temporary register if
7192 mips_dangerous_for_la25_p.
7194 If we jump to the temporary register rather than $25, the assembler
7195 can use the move insn to fill the jump's delay slot. */
7196 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7197 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7198 mips_load_call_address (temp1, fnaddr, true);
7200 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7201 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7202 emit_jump_insn (gen_indirect_jump (temp1));
7206 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7207 SIBLING_CALL_P (insn) = 1;
7210 /* Run just enough of rest_of_compilation. This sequence was
7211 "borrowed" from alpha.c. */
7212 insn = get_insns ();
7213 insn_locators_initialize ();
7214 split_all_insns_noflow ();
7216 mips16_lay_out_constants ();
7217 shorten_branches (insn);
7218 final_start_function (insn, file, 1);
7219 final (insn, file, 1);
7220 final_end_function ();
7222 /* Clean up the vars set above. Note that final_end_function resets
7223 the global pointer for us. */
7224 reload_completed = 0;
7228 /* Returns nonzero if X contains a SYMBOL_REF. */
7231 symbolic_expression_p (rtx x)
7233 if (GET_CODE (x) == SYMBOL_REF)
7236 if (GET_CODE (x) == CONST)
7237 return symbolic_expression_p (XEXP (x, 0));
7240 return symbolic_expression_p (XEXP (x, 0));
7242 if (ARITHMETIC_P (x))
7243 return (symbolic_expression_p (XEXP (x, 0))
7244 || symbolic_expression_p (XEXP (x, 1)));
7249 /* Choose the section to use for the constant rtx expression X that has
7253 mips_select_rtx_section (enum machine_mode mode, rtx x,
7254 unsigned HOST_WIDE_INT align)
7258 /* In mips16 mode, the constant table always goes in the same section
7259 as the function, so that constants can be loaded using PC relative
7261 return function_section (current_function_decl);
7263 else if (TARGET_EMBEDDED_DATA)
7265 /* For embedded applications, always put constants in read-only data,
7266 in order to reduce RAM usage. */
7267 return mergeable_constant_section (mode, align, 0);
7271 /* For hosted applications, always put constants in small data if
7272 possible, as this gives the best performance. */
7273 /* ??? Consider using mergeable small data sections. */
7275 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7276 && mips_section_threshold > 0)
7277 return get_named_section (NULL, ".sdata", 0);
7278 else if (flag_pic && symbolic_expression_p (x))
7279 return get_named_section (NULL, ".data.rel.ro", 3);
7281 return mergeable_constant_section (mode, align, 0);
7285 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7287 The complication here is that, with the combination TARGET_ABICALLS
7288 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7289 therefore not be included in the read-only part of a DSO. Handle such
7290 cases by selecting a normal data section instead of a read-only one.
7291 The logic apes that in default_function_rodata_section. */
7294 mips_function_rodata_section (tree decl)
7296 if (!TARGET_ABICALLS || TARGET_GPWORD)
7297 return default_function_rodata_section (decl);
7299 if (decl && DECL_SECTION_NAME (decl))
7301 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7302 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7304 char *rname = ASTRDUP (name);
7306 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7308 else if (flag_function_sections && flag_data_sections
7309 && strncmp (name, ".text.", 6) == 0)
7311 char *rname = ASTRDUP (name);
7312 memcpy (rname + 1, "data", 4);
7313 return get_section (rname, SECTION_WRITE, decl);
7316 return data_section;
7319 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
7320 locally-defined objects go in a small data section. It also controls
7321 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
7322 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
7325 mips_in_small_data_p (tree decl)
7329 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7332 /* We don't yet generate small-data references for -mabicalls. See related
7333 -G handling in override_options. */
7334 if (TARGET_ABICALLS)
7337 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7341 /* Reject anything that isn't in a known small-data section. */
7342 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7343 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7346 /* If a symbol is defined externally, the assembler will use the
7347 usual -G rules when deciding how to implement macros. */
7348 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7351 else if (TARGET_EMBEDDED_DATA)
7353 /* Don't put constants into the small data section: we want them
7354 to be in ROM rather than RAM. */
7355 if (TREE_CODE (decl) != VAR_DECL)
7358 if (TREE_READONLY (decl)
7359 && !TREE_SIDE_EFFECTS (decl)
7360 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7364 size = int_size_in_bytes (TREE_TYPE (decl));
7365 return (size > 0 && size <= mips_section_threshold);
7368 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7369 anchors for small data: the GP register acts as an anchor in that
7370 case. We also don't want to use them for PC-relative accesses,
7371 where the PC acts as an anchor. */
7374 mips_use_anchors_for_symbol_p (rtx symbol)
7376 switch (mips_classify_symbol (symbol))
7378 case SYMBOL_CONSTANT_POOL:
7379 case SYMBOL_SMALL_DATA:
7387 /* See whether VALTYPE is a record whose fields should be returned in
7388 floating-point registers. If so, return the number of fields and
7389 list them in FIELDS (which should have two elements). Return 0
7392 For n32 & n64, a structure with one or two fields is returned in
7393 floating-point registers as long as every field has a floating-point
7397 mips_fpr_return_fields (tree valtype, tree *fields)
7405 if (TREE_CODE (valtype) != RECORD_TYPE)
7409 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7411 if (TREE_CODE (field) != FIELD_DECL)
7414 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7420 fields[i++] = field;
7426 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7427 a value in the most significant part of $2/$3 if:
7429 - the target is big-endian;
7431 - the value has a structure or union type (we generalize this to
7432 cover aggregates from other languages too); and
7434 - the structure is not returned in floating-point registers. */
7437 mips_return_in_msb (tree valtype)
7441 return (TARGET_NEWABI
7442 && TARGET_BIG_ENDIAN
7443 && AGGREGATE_TYPE_P (valtype)
7444 && mips_fpr_return_fields (valtype, fields) == 0);
7448 /* Return a composite value in a pair of floating-point registers.
7449 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7450 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7453 For n32 & n64, $f0 always holds the first value and $f2 the second.
7454 Otherwise the values are packed together as closely as possible. */
7457 mips_return_fpr_pair (enum machine_mode mode,
7458 enum machine_mode mode1, HOST_WIDE_INT offset1,
7459 enum machine_mode mode2, HOST_WIDE_INT offset2)
7463 inc = (TARGET_NEWABI ? 2 : FP_INC);
7464 return gen_rtx_PARALLEL
7467 gen_rtx_EXPR_LIST (VOIDmode,
7468 gen_rtx_REG (mode1, FP_RETURN),
7470 gen_rtx_EXPR_LIST (VOIDmode,
7471 gen_rtx_REG (mode2, FP_RETURN + inc),
7472 GEN_INT (offset2))));
7477 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7478 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7479 VALTYPE is null and MODE is the mode of the return value. */
7482 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7483 enum machine_mode mode)
7490 mode = TYPE_MODE (valtype);
7491 unsignedp = TYPE_UNSIGNED (valtype);
7493 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7494 true, we must promote the mode just as PROMOTE_MODE does. */
7495 mode = promote_mode (valtype, mode, &unsignedp, 1);
7497 /* Handle structures whose fields are returned in $f0/$f2. */
7498 switch (mips_fpr_return_fields (valtype, fields))
7501 return gen_rtx_REG (mode, FP_RETURN);
7504 return mips_return_fpr_pair (mode,
7505 TYPE_MODE (TREE_TYPE (fields[0])),
7506 int_byte_position (fields[0]),
7507 TYPE_MODE (TREE_TYPE (fields[1])),
7508 int_byte_position (fields[1]));
7511 /* If a value is passed in the most significant part of a register, see
7512 whether we have to round the mode up to a whole number of words. */
7513 if (mips_return_in_msb (valtype))
7515 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7516 if (size % UNITS_PER_WORD != 0)
7518 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7519 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7523 /* For EABI, the class of return register depends entirely on MODE.
7524 For example, "struct { some_type x; }" and "union { some_type x; }"
7525 are returned in the same way as a bare "some_type" would be.
7526 Other ABIs only use FPRs for scalar, complex or vector types. */
7527 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7528 return gen_rtx_REG (mode, GP_RETURN);
7531 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7532 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7533 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7534 return gen_rtx_REG (mode, FP_RETURN);
7536 /* Handle long doubles for n32 & n64. */
7538 return mips_return_fpr_pair (mode,
7540 DImode, GET_MODE_SIZE (mode) / 2);
7542 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7543 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7544 return mips_return_fpr_pair (mode,
7545 GET_MODE_INNER (mode), 0,
7546 GET_MODE_INNER (mode),
7547 GET_MODE_SIZE (mode) / 2);
7549 return gen_rtx_REG (mode, GP_RETURN);
7552 /* Return nonzero when an argument must be passed by reference. */
7555 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7556 enum machine_mode mode, tree type,
7557 bool named ATTRIBUTE_UNUSED)
7559 if (mips_abi == ABI_EABI)
7563 /* ??? How should SCmode be handled? */
7564 if (mode == DImode || mode == DFmode)
7567 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
7568 return size == -1 || size > UNITS_PER_WORD;
7572 /* If we have a variable-sized parameter, we have no choice. */
7573 return targetm.calls.must_pass_in_stack (mode, type);
7578 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7579 enum machine_mode mode ATTRIBUTE_UNUSED,
7580 tree type ATTRIBUTE_UNUSED, bool named)
7582 return mips_abi == ABI_EABI && named;
7585 /* Return true if registers of class CLASS cannot change from mode FROM
7589 mips_cannot_change_mode_class (enum machine_mode from,
7590 enum machine_mode to, enum reg_class class)
7592 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7593 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7595 if (TARGET_BIG_ENDIAN)
7597 /* When a multi-word value is stored in paired floating-point
7598 registers, the first register always holds the low word.
7599 We therefore can't allow FPRs to change between single-word
7600 and multi-word modes. */
7601 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7606 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7607 in LO and HI, the high word always comes first. We therefore
7608 can't allow values stored in HI to change between single-word
7609 and multi-word modes.
7610 This rule applies to both the original HI/LO pair and the new
7611 DSP accumulators. */
7612 if (reg_classes_intersect_p (ACC_REGS, class))
7616 /* Loading a 32-bit value into a 64-bit floating-point register
7617 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7618 We can't allow 64-bit float registers to change from SImode to
7622 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7623 && reg_classes_intersect_p (FP_REGS, class))
7628 /* Return true if X should not be moved directly into register $25.
7629 We need this because many versions of GAS will treat "la $25,foo" as
7630 part of a call sequence and so allow a global "foo" to be lazily bound. */
7633 mips_dangerous_for_la25_p (rtx x)
7635 HOST_WIDE_INT offset;
7637 if (TARGET_EXPLICIT_RELOCS)
7640 mips_split_const (x, &x, &offset);
7641 return global_got_operand (x, VOIDmode);
7644 /* Implement PREFERRED_RELOAD_CLASS. */
7647 mips_preferred_reload_class (rtx x, enum reg_class class)
7649 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7652 if (TARGET_HARD_FLOAT
7653 && FLOAT_MODE_P (GET_MODE (x))
7654 && reg_class_subset_p (FP_REGS, class))
7657 if (reg_class_subset_p (GR_REGS, class))
7660 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7666 /* This function returns the register class required for a secondary
7667 register when copying between one of the registers in CLASS, and X,
7668 using MODE. If IN_P is nonzero, the copy is going from X to the
7669 register, otherwise the register is the source. A return value of
7670 NO_REGS means that no secondary register is required. */
7673 mips_secondary_reload_class (enum reg_class class,
7674 enum machine_mode mode, rtx x, int in_p)
7676 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7680 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7681 regno = true_regnum (x);
7683 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7685 if (mips_dangerous_for_la25_p (x))
7688 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7692 /* Copying from HI or LO to anywhere other than a general register
7693 requires a general register.
7694 This rule applies to both the original HI/LO pair and the new
7695 DSP accumulators. */
7696 if (reg_class_subset_p (class, ACC_REGS))
7698 if (TARGET_MIPS16 && in_p)
7700 /* We can't really copy to HI or LO at all in mips16 mode. */
7703 return gp_reg_p ? NO_REGS : gr_regs;
7705 if (ACC_REG_P (regno))
7707 if (TARGET_MIPS16 && ! in_p)
7709 /* We can't really copy to HI or LO at all in mips16 mode. */
7712 return class == gr_regs ? NO_REGS : gr_regs;
7715 /* We can only copy a value to a condition code register from a
7716 floating point register, and even then we require a scratch
7717 floating point register. We can only copy a value out of a
7718 condition code register into a general register. */
7719 if (class == ST_REGS)
7723 return gp_reg_p ? NO_REGS : gr_regs;
7725 if (ST_REG_P (regno))
7729 return class == gr_regs ? NO_REGS : gr_regs;
7732 if (class == FP_REGS)
7736 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7739 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7741 /* We can use the l.s and l.d macros to load floating-point
7742 constants. ??? For l.s, we could probably get better
7743 code by returning GR_REGS here. */
7746 else if (gp_reg_p || x == CONST0_RTX (mode))
7748 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7751 else if (FP_REG_P (regno))
7753 /* In this case we can use mov.s or mov.d. */
7758 /* Otherwise, we need to reload through an integer register. */
7763 /* In mips16 mode, going between memory and anything but M16_REGS
7764 requires an M16_REG. */
7767 if (class != M16_REGS && class != M16_NA_REGS)
7775 if (class == M16_REGS || class == M16_NA_REGS)
7784 /* Implement CLASS_MAX_NREGS.
7786 Usually all registers are word-sized. The only supported exception
7787 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7788 registers. A word-based calculation is correct even in that case,
7789 since -msingle-float disallows multi-FPR values.
7791 The FP status registers are an exception to this rule. They are always
7792 4 bytes wide as they only hold condition code modes, and CCmode is always
7793 considered to be 4 bytes wide. */
7796 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7797 enum machine_mode mode)
7799 if (class == ST_REGS)
7800 return (GET_MODE_SIZE (mode) + 3) / 4;
7802 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7806 mips_valid_pointer_mode (enum machine_mode mode)
7808 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7811 /* Target hook for vector_mode_supported_p. */
7814 mips_vector_mode_supported_p (enum machine_mode mode)
7819 return TARGET_PAIRED_SINGLE_FLOAT;
7830 /* If we can access small data directly (using gp-relative relocation
7831 operators) return the small data pointer, otherwise return null.
7833 For each mips16 function which refers to GP relative symbols, we
7834 use a pseudo register, initialized at the start of the function, to
7835 hold the $gp value. */
7838 mips16_gp_pseudo_reg (void)
7840 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7845 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7847 /* We want to initialize this to a value which gcc will believe
7850 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7851 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7852 gen_rtx_CONST (Pmode, unspec));
7853 insn = get_insns ();
7856 push_topmost_sequence ();
7857 /* We need to emit the initialization after the FUNCTION_BEG
7858 note, so that it will be integrated. */
7859 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7861 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7863 if (scan == NULL_RTX)
7864 scan = get_insns ();
7865 insn = emit_insn_after (insn, scan);
7866 pop_topmost_sequence ();
7869 return cfun->machine->mips16_gp_pseudo_rtx;
7872 /* Write out code to move floating point arguments in or out of
7873 general registers. Output the instructions to FILE. FP_CODE is
7874 the code describing which arguments are present (see the comment at
7875 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7876 we are copying from the floating point registers. */
7879 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7885 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7886 gcc_assert (TARGET_OLDABI);
7892 gparg = GP_ARG_FIRST;
7893 fparg = FP_ARG_FIRST;
7894 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7898 if ((fparg & 1) != 0)
7900 fprintf (file, "\t%s\t%s,%s\n", s,
7901 reg_names[gparg], reg_names[fparg]);
7903 else if ((f & 3) == 2)
7906 fprintf (file, "\td%s\t%s,%s\n", s,
7907 reg_names[gparg], reg_names[fparg]);
7910 if ((fparg & 1) != 0)
7912 if (TARGET_BIG_ENDIAN)
7913 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7914 reg_names[gparg], reg_names[fparg + 1], s,
7915 reg_names[gparg + 1], reg_names[fparg]);
7917 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7918 reg_names[gparg], reg_names[fparg], s,
7919 reg_names[gparg + 1], reg_names[fparg + 1]);
7932 /* Build a mips16 function stub. This is used for functions which
7933 take arguments in the floating point registers. It is 32 bit code
7934 that moves the floating point args into the general registers, and
7935 then jumps to the 16 bit code. */
7938 build_mips16_function_stub (FILE *file)
7941 char *secname, *stubname;
7942 tree stubid, stubdecl;
7946 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7947 secname = (char *) alloca (strlen (fnname) + 20);
7948 sprintf (secname, ".mips16.fn.%s", fnname);
7949 stubname = (char *) alloca (strlen (fnname) + 20);
7950 sprintf (stubname, "__fn_stub_%s", fnname);
7951 stubid = get_identifier (stubname);
7952 stubdecl = build_decl (FUNCTION_DECL, stubid,
7953 build_function_type (void_type_node, NULL_TREE));
7954 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7956 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7958 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7960 fprintf (file, "%s%s",
7961 need_comma ? ", " : "",
7962 (f & 3) == 1 ? "float" : "double");
7965 fprintf (file, ")\n");
7967 fprintf (file, "\t.set\tnomips16\n");
7968 switch_to_section (function_section (stubdecl));
7969 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7971 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7972 within a .ent, and we cannot emit another .ent. */
7973 if (!FUNCTION_NAME_ALREADY_DECLARED)
7975 fputs ("\t.ent\t", file);
7976 assemble_name (file, stubname);
7980 assemble_name (file, stubname);
7981 fputs (":\n", file);
7983 /* We don't want the assembler to insert any nops here. */
7984 fprintf (file, "\t.set\tnoreorder\n");
7986 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7988 fprintf (asm_out_file, "\t.set\tnoat\n");
7989 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7990 assemble_name (file, fnname);
7991 fprintf (file, "\n");
7992 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7993 fprintf (asm_out_file, "\t.set\tat\n");
7995 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7996 with one of the mfc1 instructions, because the result is not
7997 available for one instruction, so if the very first instruction
7998 in the function refers to the register, it will see the wrong
8000 fprintf (file, "\tnop\n");
8002 fprintf (file, "\t.set\treorder\n");
8004 if (!FUNCTION_NAME_ALREADY_DECLARED)
8006 fputs ("\t.end\t", file);
8007 assemble_name (file, stubname);
8011 fprintf (file, "\t.set\tmips16\n");
8013 switch_to_section (function_section (current_function_decl));
8016 /* We keep a list of functions for which we have already built stubs
8017 in build_mips16_call_stub. */
8021 struct mips16_stub *next;
8026 static struct mips16_stub *mips16_stubs;
8028 /* Build a call stub for a mips16 call. A stub is needed if we are
8029 passing any floating point values which should go into the floating
8030 point registers. If we are, and the call turns out to be to a 32
8031 bit function, the stub will be used to move the values into the
8032 floating point registers before calling the 32 bit function. The
8033 linker will magically adjust the function call to either the 16 bit
8034 function or the 32 bit stub, depending upon where the function call
8035 is actually defined.
8037 Similarly, we need a stub if the return value might come back in a
8038 floating point register.
8040 RETVAL is the location of the return value, or null if this is
8041 a call rather than a call_value. FN is the address of the
8042 function and ARG_SIZE is the size of the arguments. FP_CODE
8043 is the code built by function_arg. This function returns a nonzero
8044 value if it builds the call instruction itself. */
8047 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8051 char *secname, *stubname;
8052 struct mips16_stub *l;
8053 tree stubid, stubdecl;
8057 /* We don't need to do anything if we aren't in mips16 mode, or if
8058 we were invoked with the -msoft-float option. */
8059 if (! TARGET_MIPS16 || ! mips16_hard_float)
8062 /* Figure out whether the value might come back in a floating point
8064 fpret = (retval != 0
8065 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8066 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8068 /* We don't need to do anything if there were no floating point
8069 arguments and the value will not be returned in a floating point
8071 if (fp_code == 0 && ! fpret)
8074 /* We don't need to do anything if this is a call to a special
8075 mips16 support function. */
8076 if (GET_CODE (fn) == SYMBOL_REF
8077 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8080 /* This code will only work for o32 and o64 abis. The other ABI's
8081 require more sophisticated support. */
8082 gcc_assert (TARGET_OLDABI);
8084 /* We can only handle SFmode and DFmode floating point return
8087 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
8089 /* If we're calling via a function pointer, then we must always call
8090 via a stub. There are magic stubs provided in libgcc.a for each
8091 of the required cases. Each of them expects the function address
8092 to arrive in register $2. */
8094 if (GET_CODE (fn) != SYMBOL_REF)
8100 /* ??? If this code is modified to support other ABI's, we need
8101 to handle PARALLEL return values here. */
8103 sprintf (buf, "__mips16_call_stub_%s%d",
8105 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8108 id = get_identifier (buf);
8109 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8111 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8113 if (retval == NULL_RTX)
8114 insn = gen_call_internal (stub_fn, arg_size);
8116 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8117 insn = emit_call_insn (insn);
8119 /* Put the register usage information on the CALL. */
8120 CALL_INSN_FUNCTION_USAGE (insn) =
8121 gen_rtx_EXPR_LIST (VOIDmode,
8122 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8123 CALL_INSN_FUNCTION_USAGE (insn));
8125 /* If we are handling a floating point return value, we need to
8126 save $18 in the function prologue. Putting a note on the
8127 call will mean that regs_ever_live[$18] will be true if the
8128 call is not eliminated, and we can check that in the prologue
8131 CALL_INSN_FUNCTION_USAGE (insn) =
8132 gen_rtx_EXPR_LIST (VOIDmode,
8133 gen_rtx_USE (VOIDmode,
8134 gen_rtx_REG (word_mode, 18)),
8135 CALL_INSN_FUNCTION_USAGE (insn));
8137 /* Return 1 to tell the caller that we've generated the call
8142 /* We know the function we are going to call. If we have already
8143 built a stub, we don't need to do anything further. */
8145 fnname = XSTR (fn, 0);
8146 for (l = mips16_stubs; l != NULL; l = l->next)
8147 if (strcmp (l->name, fnname) == 0)
8152 /* Build a special purpose stub. When the linker sees a
8153 function call in mips16 code, it will check where the target
8154 is defined. If the target is a 32 bit call, the linker will
8155 search for the section defined here. It can tell which
8156 symbol this section is associated with by looking at the
8157 relocation information (the name is unreliable, since this
8158 might be a static function). If such a section is found, the
8159 linker will redirect the call to the start of the magic
8162 If the function does not return a floating point value, the
8163 special stub section is named
8166 If the function does return a floating point value, the stub
8168 .mips16.call.fp.FNNAME
8171 secname = (char *) alloca (strlen (fnname) + 40);
8172 sprintf (secname, ".mips16.call.%s%s",
8175 stubname = (char *) alloca (strlen (fnname) + 20);
8176 sprintf (stubname, "__call_stub_%s%s",
8179 stubid = get_identifier (stubname);
8180 stubdecl = build_decl (FUNCTION_DECL, stubid,
8181 build_function_type (void_type_node, NULL_TREE));
8182 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8184 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8186 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8190 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8192 fprintf (asm_out_file, "%s%s",
8193 need_comma ? ", " : "",
8194 (f & 3) == 1 ? "float" : "double");
8197 fprintf (asm_out_file, ")\n");
8199 fprintf (asm_out_file, "\t.set\tnomips16\n");
8200 assemble_start_function (stubdecl, stubname);
8202 if (!FUNCTION_NAME_ALREADY_DECLARED)
8204 fputs ("\t.ent\t", asm_out_file);
8205 assemble_name (asm_out_file, stubname);
8206 fputs ("\n", asm_out_file);
8208 assemble_name (asm_out_file, stubname);
8209 fputs (":\n", asm_out_file);
8212 /* We build the stub code by hand. That's the only way we can
8213 do it, since we can't generate 32 bit code during a 16 bit
8216 /* We don't want the assembler to insert any nops here. */
8217 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8219 mips16_fp_args (asm_out_file, fp_code, 0);
8223 fprintf (asm_out_file, "\t.set\tnoat\n");
8224 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8226 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8227 fprintf (asm_out_file, "\t.set\tat\n");
8228 /* Unfortunately, we can't fill the jump delay slot. We
8229 can't fill with one of the mtc1 instructions, because the
8230 result is not available for one instruction, so if the
8231 very first instruction in the function refers to the
8232 register, it will see the wrong value. */
8233 fprintf (asm_out_file, "\tnop\n");
8237 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8238 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8239 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8240 /* As above, we can't fill the delay slot. */
8241 fprintf (asm_out_file, "\tnop\n");
8242 if (GET_MODE (retval) == SFmode)
8243 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8244 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8247 if (TARGET_BIG_ENDIAN)
8249 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8250 reg_names[GP_REG_FIRST + 2],
8251 reg_names[FP_REG_FIRST + 1]);
8252 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8253 reg_names[GP_REG_FIRST + 3],
8254 reg_names[FP_REG_FIRST + 0]);
8258 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8259 reg_names[GP_REG_FIRST + 2],
8260 reg_names[FP_REG_FIRST + 0]);
8261 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8262 reg_names[GP_REG_FIRST + 3],
8263 reg_names[FP_REG_FIRST + 1]);
8266 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8267 /* As above, we can't fill the delay slot. */
8268 fprintf (asm_out_file, "\tnop\n");
8271 fprintf (asm_out_file, "\t.set\treorder\n");
8273 #ifdef ASM_DECLARE_FUNCTION_SIZE
8274 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8277 if (!FUNCTION_NAME_ALREADY_DECLARED)
8279 fputs ("\t.end\t", asm_out_file);
8280 assemble_name (asm_out_file, stubname);
8281 fputs ("\n", asm_out_file);
8284 fprintf (asm_out_file, "\t.set\tmips16\n");
8286 /* Record this stub. */
8287 l = (struct mips16_stub *) xmalloc (sizeof *l);
8288 l->name = xstrdup (fnname);
8290 l->next = mips16_stubs;
8294 /* If we expect a floating point return value, but we've built a
8295 stub which does not expect one, then we're in trouble. We can't
8296 use the existing stub, because it won't handle the floating point
8297 value. We can't build a new stub, because the linker won't know
8298 which stub to use for the various calls in this object file.
8299 Fortunately, this case is illegal, since it means that a function
8300 was declared in two different ways in a single compilation. */
8301 if (fpret && ! l->fpret)
8302 error ("cannot handle inconsistent calls to %qs", fnname);
8304 /* If we are calling a stub which handles a floating point return
8305 value, we need to arrange to save $18 in the prologue. We do
8306 this by marking the function call as using the register. The
8307 prologue will later see that it is used, and emit code to save
8314 if (retval == NULL_RTX)
8315 insn = gen_call_internal (fn, arg_size);
8317 insn = gen_call_value_internal (retval, fn, arg_size);
8318 insn = emit_call_insn (insn);
8320 CALL_INSN_FUNCTION_USAGE (insn) =
8321 gen_rtx_EXPR_LIST (VOIDmode,
8322 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8323 CALL_INSN_FUNCTION_USAGE (insn));
8325 /* Return 1 to tell the caller that we've generated the call
8330 /* Return 0 to let the caller generate the call insn. */
8334 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8335 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8337 struct mips16_constant {
8338 struct mips16_constant *next;
8341 enum machine_mode mode;
8344 /* Information about an incomplete mips16 constant pool. FIRST is the
8345 first constant, HIGHEST_ADDRESS is the highest address that the first
8346 byte of the pool can have, and INSN_ADDRESS is the current instruction
8349 struct mips16_constant_pool {
8350 struct mips16_constant *first;
8351 int highest_address;
8355 /* Add constant VALUE to POOL and return its label. MODE is the
8356 value's mode (used for CONST_INTs, etc.). */
8359 add_constant (struct mips16_constant_pool *pool,
8360 rtx value, enum machine_mode mode)
8362 struct mips16_constant **p, *c;
8363 bool first_of_size_p;
8365 /* See whether the constant is already in the pool. If so, return the
8366 existing label, otherwise leave P pointing to the place where the
8367 constant should be added.
8369 Keep the pool sorted in increasing order of mode size so that we can
8370 reduce the number of alignments needed. */
8371 first_of_size_p = true;
8372 for (p = &pool->first; *p != 0; p = &(*p)->next)
8374 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8376 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8378 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8379 first_of_size_p = false;
8382 /* In the worst case, the constant needed by the earliest instruction
8383 will end up at the end of the pool. The entire pool must then be
8384 accessible from that instruction.
8386 When adding the first constant, set the pool's highest address to
8387 the address of the first out-of-range byte. Adjust this address
8388 downwards each time a new constant is added. */
8389 if (pool->first == 0)
8390 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8391 is the address of the instruction with the lowest two bits clear.
8392 The base PC value for ld has the lowest three bits clear. Assume
8393 the worst case here. */
8394 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8395 pool->highest_address -= GET_MODE_SIZE (mode);
8396 if (first_of_size_p)
8397 /* Take into account the worst possible padding due to alignment. */
8398 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8400 /* Create a new entry. */
8401 c = (struct mips16_constant *) xmalloc (sizeof *c);
8404 c->label = gen_label_rtx ();
8411 /* Output constant VALUE after instruction INSN and return the last
8412 instruction emitted. MODE is the mode of the constant. */
8415 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8417 switch (GET_MODE_CLASS (mode))
8421 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8422 return emit_insn_after (gen_consttable_int (value, size), insn);
8426 return emit_insn_after (gen_consttable_float (value), insn);
8428 case MODE_VECTOR_FLOAT:
8429 case MODE_VECTOR_INT:
8432 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8433 insn = dump_constants_1 (GET_MODE_INNER (mode),
8434 CONST_VECTOR_ELT (value, i), insn);
8444 /* Dump out the constants in CONSTANTS after INSN. */
8447 dump_constants (struct mips16_constant *constants, rtx insn)
8449 struct mips16_constant *c, *next;
8453 for (c = constants; c != NULL; c = next)
8455 /* If necessary, increase the alignment of PC. */
8456 if (align < GET_MODE_SIZE (c->mode))
8458 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8459 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8461 align = GET_MODE_SIZE (c->mode);
8463 insn = emit_label_after (c->label, insn);
8464 insn = dump_constants_1 (c->mode, c->value, insn);
8470 emit_barrier_after (insn);
8473 /* Return the length of instruction INSN. */
8476 mips16_insn_length (rtx insn)
8480 rtx body = PATTERN (insn);
8481 if (GET_CODE (body) == ADDR_VEC)
8482 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8483 if (GET_CODE (body) == ADDR_DIFF_VEC)
8484 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8486 return get_attr_length (insn);
8489 /* Rewrite *X so that constant pool references refer to the constant's
8490 label instead. DATA points to the constant pool structure. */
8493 mips16_rewrite_pool_refs (rtx *x, void *data)
8495 struct mips16_constant_pool *pool = data;
8496 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8497 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8498 get_pool_constant (*x),
8499 get_pool_mode (*x)));
8503 /* Build MIPS16 constant pools. */
8506 mips16_lay_out_constants (void)
8508 struct mips16_constant_pool pool;
8512 memset (&pool, 0, sizeof (pool));
8513 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8515 /* Rewrite constant pool references in INSN. */
8517 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8519 pool.insn_address += mips16_insn_length (insn);
8521 if (pool.first != NULL)
8523 /* If there are no natural barriers between the first user of
8524 the pool and the highest acceptable address, we'll need to
8525 create a new instruction to jump around the constant pool.
8526 In the worst case, this instruction will be 4 bytes long.
8528 If it's too late to do this transformation after INSN,
8529 do it immediately before INSN. */
8530 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8534 label = gen_label_rtx ();
8536 jump = emit_jump_insn_before (gen_jump (label), insn);
8537 JUMP_LABEL (jump) = label;
8538 LABEL_NUSES (label) = 1;
8539 barrier = emit_barrier_after (jump);
8541 emit_label_after (label, barrier);
8542 pool.insn_address += 4;
8545 /* See whether the constant pool is now out of range of the first
8546 user. If so, output the constants after the previous barrier.
8547 Note that any instructions between BARRIER and INSN (inclusive)
8548 will use negative offsets to refer to the pool. */
8549 if (pool.insn_address > pool.highest_address)
8551 dump_constants (pool.first, barrier);
8555 else if (BARRIER_P (insn))
8559 dump_constants (pool.first, get_last_insn ());
8562 /* A temporary variable used by for_each_rtx callbacks, etc. */
8563 static rtx mips_sim_insn;
8565 /* A structure representing the state of the processor pipeline.
8566 Used by the mips_sim_* family of functions. */
8568 /* The maximum number of instructions that can be issued in a cycle.
8569 (Caches mips_issue_rate.) */
8570 unsigned int issue_rate;
8572 /* The current simulation time. */
8575 /* How many more instructions can be issued in the current cycle. */
8576 unsigned int insns_left;
8578 /* LAST_SET[X].INSN is the last instruction to set register X.
8579 LAST_SET[X].TIME is the time at which that instruction was issued.
8580 INSN is null if no instruction has yet set register X. */
8584 } last_set[FIRST_PSEUDO_REGISTER];
8586 /* The pipeline's current DFA state. */
8590 /* Reset STATE to the initial simulation state. */
8593 mips_sim_reset (struct mips_sim *state)
8596 state->insns_left = state->issue_rate;
8597 memset (&state->last_set, 0, sizeof (state->last_set));
8598 state_reset (state->dfa_state);
8601 /* Initialize STATE before its first use. DFA_STATE points to an
8602 allocated but uninitialized DFA state. */
8605 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8607 state->issue_rate = mips_issue_rate ();
8608 state->dfa_state = dfa_state;
8609 mips_sim_reset (state);
8612 /* Advance STATE by one clock cycle. */
8615 mips_sim_next_cycle (struct mips_sim *state)
8618 state->insns_left = state->issue_rate;
8619 state_transition (state->dfa_state, 0);
8622 /* Advance simulation state STATE until instruction INSN can read
8626 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8630 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8631 if (state->last_set[REGNO (reg) + i].insn != 0)
8635 t = state->last_set[REGNO (reg) + i].time;
8636 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8637 while (state->time < t)
8638 mips_sim_next_cycle (state);
8642 /* A for_each_rtx callback. If *X is a register, advance simulation state
8643 DATA until mips_sim_insn can read the register's value. */
8646 mips_sim_wait_regs_2 (rtx *x, void *data)
8649 mips_sim_wait_reg (data, mips_sim_insn, *x);
8653 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8656 mips_sim_wait_regs_1 (rtx *x, void *data)
8658 for_each_rtx (x, mips_sim_wait_regs_2, data);
8661 /* Advance simulation state STATE until all of INSN's register
8662 dependencies are satisfied. */
8665 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8667 mips_sim_insn = insn;
8668 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8671 /* Advance simulation state STATE until the units required by
8672 instruction INSN are available. */
8675 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8679 tmp_state = alloca (state_size ());
8680 while (state->insns_left == 0
8681 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8682 state_transition (tmp_state, insn) >= 0))
8683 mips_sim_next_cycle (state);
8686 /* Advance simulation state STATE until INSN is ready to issue. */
8689 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8691 mips_sim_wait_regs (state, insn);
8692 mips_sim_wait_units (state, insn);
8695 /* mips_sim_insn has just set X. Update the LAST_SET array
8696 in simulation state DATA. */
8699 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8701 struct mips_sim *state;
8706 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8708 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8709 state->last_set[REGNO (x) + i].time = state->time;
8713 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8714 can issue immediately (i.e., that mips_sim_wait_insn has already
8718 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8720 state_transition (state->dfa_state, insn);
8721 state->insns_left--;
8723 mips_sim_insn = insn;
8724 note_stores (PATTERN (insn), mips_sim_record_set, state);
8727 /* Simulate issuing a NOP in state STATE. */
8730 mips_sim_issue_nop (struct mips_sim *state)
8732 if (state->insns_left == 0)
8733 mips_sim_next_cycle (state);
8734 state->insns_left--;
8737 /* Update simulation state STATE so that it's ready to accept the instruction
8738 after INSN. INSN should be part of the main rtl chain, not a member of a
8742 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8744 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8746 mips_sim_issue_nop (state);
8748 switch (GET_CODE (SEQ_BEGIN (insn)))
8752 /* We can't predict the processor state after a call or label. */
8753 mips_sim_reset (state);
8757 /* The delay slots of branch likely instructions are only executed
8758 when the branch is taken. Therefore, if the caller has simulated
8759 the delay slot instruction, STATE does not really reflect the state
8760 of the pipeline for the instruction after the delay slot. Also,
8761 branch likely instructions tend to incur a penalty when not taken,
8762 so there will probably be an extra delay between the branch and
8763 the instruction after the delay slot. */
8764 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8765 mips_sim_reset (state);
8773 /* The VR4130 pipeline issues aligned pairs of instructions together,
8774 but it stalls the second instruction if it depends on the first.
8775 In order to cut down the amount of logic required, this dependence
8776 check is not based on a full instruction decode. Instead, any non-SPECIAL
8777 instruction is assumed to modify the register specified by bits 20-16
8778 (which is usually the "rt" field).
8780 In beq, beql, bne and bnel instructions, the rt field is actually an
8781 input, so we can end up with a false dependence between the branch
8782 and its delay slot. If this situation occurs in instruction INSN,
8783 try to avoid it by swapping rs and rt. */
8786 vr4130_avoid_branch_rt_conflict (rtx insn)
8790 first = SEQ_BEGIN (insn);
8791 second = SEQ_END (insn);
8793 && NONJUMP_INSN_P (second)
8794 && GET_CODE (PATTERN (first)) == SET
8795 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8796 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8798 /* Check for the right kind of condition. */
8799 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8800 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8801 && REG_P (XEXP (cond, 0))
8802 && REG_P (XEXP (cond, 1))
8803 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8804 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8806 /* SECOND mentions the rt register but not the rs register. */
8807 rtx tmp = XEXP (cond, 0);
8808 XEXP (cond, 0) = XEXP (cond, 1);
8809 XEXP (cond, 1) = tmp;
8814 /* Implement -mvr4130-align. Go through each basic block and simulate the
8815 processor pipeline. If we find that a pair of instructions could execute
8816 in parallel, and the first of those instruction is not 8-byte aligned,
8817 insert a nop to make it aligned. */
8820 vr4130_align_insns (void)
8822 struct mips_sim state;
8823 rtx insn, subinsn, last, last2, next;
8828 /* LAST is the last instruction before INSN to have a nonzero length.
8829 LAST2 is the last such instruction before LAST. */
8833 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8836 mips_sim_init (&state, alloca (state_size ()));
8837 for (insn = get_insns (); insn != 0; insn = next)
8839 unsigned int length;
8841 next = NEXT_INSN (insn);
8843 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8844 This isn't really related to the alignment pass, but we do it on
8845 the fly to avoid a separate instruction walk. */
8846 vr4130_avoid_branch_rt_conflict (insn);
8848 if (USEFUL_INSN_P (insn))
8849 FOR_EACH_SUBINSN (subinsn, insn)
8851 mips_sim_wait_insn (&state, subinsn);
8853 /* If we want this instruction to issue in parallel with the
8854 previous one, make sure that the previous instruction is
8855 aligned. There are several reasons why this isn't worthwhile
8856 when the second instruction is a call:
8858 - Calls are less likely to be performance critical,
8859 - There's a good chance that the delay slot can execute
8860 in parallel with the call.
8861 - The return address would then be unaligned.
8863 In general, if we're going to insert a nop between instructions
8864 X and Y, it's better to insert it immediately after X. That
8865 way, if the nop makes Y aligned, it will also align any labels
8867 if (state.insns_left != state.issue_rate
8868 && !CALL_P (subinsn))
8870 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8872 /* SUBINSN is the first instruction in INSN and INSN is
8873 aligned. We want to align the previous instruction
8874 instead, so insert a nop between LAST2 and LAST.
8876 Note that LAST could be either a single instruction
8877 or a branch with a delay slot. In the latter case,
8878 LAST, like INSN, is already aligned, but the delay
8879 slot must have some extra delay that stops it from
8880 issuing at the same time as the branch. We therefore
8881 insert a nop before the branch in order to align its
8883 emit_insn_after (gen_nop (), last2);
8886 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8888 /* SUBINSN is the delay slot of INSN, but INSN is
8889 currently unaligned. Insert a nop between
8890 LAST and INSN to align it. */
8891 emit_insn_after (gen_nop (), last);
8895 mips_sim_issue_insn (&state, subinsn);
8897 mips_sim_finish_insn (&state, insn);
8899 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8900 length = get_attr_length (insn);
8903 /* If the instruction is an asm statement or multi-instruction
8904 mips.md patern, the length is only an estimate. Insert an
8905 8 byte alignment after it so that the following instructions
8906 can be handled correctly. */
8907 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8908 && (recog_memoized (insn) < 0 || length >= 8))
8910 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8911 next = NEXT_INSN (next);
8912 mips_sim_next_cycle (&state);
8915 else if (length & 4)
8916 aligned_p = !aligned_p;
8921 /* See whether INSN is an aligned label. */
8922 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8928 /* Subroutine of mips_reorg. If there is a hazard between INSN
8929 and a previous instruction, avoid it by inserting nops after
8932 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8933 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8934 before using the value of that register. *HILO_DELAY counts the
8935 number of instructions since the last hilo hazard (that is,
8936 the number of instructions since the last mflo or mfhi).
8938 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8939 for the next instruction.
8941 LO_REG is an rtx for the LO register, used in dependence checking. */
8944 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8945 rtx *delayed_reg, rtx lo_reg)
8953 pattern = PATTERN (insn);
8955 /* Do not put the whole function in .set noreorder if it contains
8956 an asm statement. We don't know whether there will be hazards
8957 between the asm statement and the gcc-generated code. */
8958 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8959 cfun->machine->all_noreorder_p = false;
8961 /* Ignore zero-length instructions (barriers and the like). */
8962 ninsns = get_attr_length (insn) / 4;
8966 /* Work out how many nops are needed. Note that we only care about
8967 registers that are explicitly mentioned in the instruction's pattern.
8968 It doesn't matter that calls use the argument registers or that they
8969 clobber hi and lo. */
8970 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8971 nops = 2 - *hilo_delay;
8972 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8977 /* Insert the nops between this instruction and the previous one.
8978 Each new nop takes us further from the last hilo hazard. */
8979 *hilo_delay += nops;
8981 emit_insn_after (gen_hazard_nop (), after);
8983 /* Set up the state for the next instruction. */
8984 *hilo_delay += ninsns;
8986 if (INSN_CODE (insn) >= 0)
8987 switch (get_attr_hazard (insn))
8997 set = single_set (insn);
8998 gcc_assert (set != 0);
8999 *delayed_reg = SET_DEST (set);
9005 /* Go through the instruction stream and insert nops where necessary.
9006 See if the whole function can then be put into .set noreorder &
9010 mips_avoid_hazards (void)
9012 rtx insn, last_insn, lo_reg, delayed_reg;
9015 /* Force all instructions to be split into their final form. */
9016 split_all_insns_noflow ();
9018 /* Recalculate instruction lengths without taking nops into account. */
9019 cfun->machine->ignore_hazard_length_p = true;
9020 shorten_branches (get_insns ());
9022 cfun->machine->all_noreorder_p = true;
9024 /* Profiled functions can't be all noreorder because the profiler
9025 support uses assembler macros. */
9026 if (current_function_profile)
9027 cfun->machine->all_noreorder_p = false;
9029 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9030 we rely on the assembler to work around some errata. */
9031 if (TARGET_FIX_VR4120)
9032 cfun->machine->all_noreorder_p = false;
9034 /* The same is true for -mfix-vr4130 if we might generate mflo or
9035 mfhi instructions. Note that we avoid using mflo and mfhi if
9036 the VR4130 macc and dmacc instructions are available instead;
9037 see the *mfhilo_{si,di}_macc patterns. */
9038 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9039 cfun->machine->all_noreorder_p = false;
9044 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9046 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9049 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9050 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9051 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9052 &hilo_delay, &delayed_reg, lo_reg);
9054 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9055 &delayed_reg, lo_reg);
9062 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9068 mips16_lay_out_constants ();
9069 else if (TARGET_EXPLICIT_RELOCS)
9071 if (mips_flag_delayed_branch)
9072 dbr_schedule (get_insns ());
9073 mips_avoid_hazards ();
9074 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9075 vr4130_align_insns ();
9079 /* This function does three things:
9081 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9082 - Register the mips16 hardware floating point stubs.
9083 - Register the gofast functions if selected using --enable-gofast. */
9085 #include "config/gofast.h"
9088 mips_init_libfuncs (void)
9090 if (TARGET_FIX_VR4120)
9092 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9093 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9096 if (TARGET_MIPS16 && mips16_hard_float)
9098 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9099 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9100 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9101 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9103 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9104 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9105 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9106 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9107 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9108 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9110 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9111 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9113 if (TARGET_DOUBLE_FLOAT)
9115 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9116 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9117 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9118 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9120 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9121 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9122 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9123 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9124 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9125 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9127 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9128 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9130 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9131 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9135 gofast_maybe_init_libfuncs ();
9138 /* Return a number assessing the cost of moving a register in class
9139 FROM to class TO. The classes are expressed using the enumeration
9140 values such as `GENERAL_REGS'. A value of 2 is the default; other
9141 values are interpreted relative to that.
9143 It is not required that the cost always equal 2 when FROM is the
9144 same as TO; on some machines it is expensive to move between
9145 registers if they are not general registers.
9147 If reload sees an insn consisting of a single `set' between two
9148 hard registers, and if `REGISTER_MOVE_COST' applied to their
9149 classes returns a value of 2, reload does not check to ensure that
9150 the constraints of the insn are met. Setting a cost of other than
9151 2 will allow reload to verify that the constraints are met. You
9152 should do this if the `movM' pattern's constraints do not allow
9155 ??? We make the cost of moving from HI/LO into general
9156 registers the same as for one of moving general registers to
9157 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9158 pseudo to HI/LO. This might hurt optimizations though, it
9159 isn't clear if it is wise. And it might not work in all cases. We
9160 could solve the DImode LO reg problem by using a multiply, just
9161 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9162 problem by using divide instructions. divu puts the remainder in
9163 the HI reg, so doing a divide by -1 will move the value in the HI
9164 reg for all values except -1. We could handle that case by using a
9165 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9166 a compare/branch to test the input value to see which instruction
9167 we need to use. This gets pretty messy, but it is feasible. */
9170 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9171 enum reg_class to, enum reg_class from)
9173 if (from == M16_REGS && GR_REG_CLASS_P (to))
9175 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9177 else if (GR_REG_CLASS_P (from))
9181 else if (to == M16_NA_REGS)
9183 else if (GR_REG_CLASS_P (to))
9190 else if (to == FP_REGS)
9192 else if (reg_class_subset_p (to, ACC_REGS))
9199 else if (COP_REG_CLASS_P (to))
9204 else if (from == FP_REGS)
9206 if (GR_REG_CLASS_P (to))
9208 else if (to == FP_REGS)
9210 else if (to == ST_REGS)
9213 else if (reg_class_subset_p (from, ACC_REGS))
9215 if (GR_REG_CLASS_P (to))
9223 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9225 else if (COP_REG_CLASS_P (from))
9231 ??? What cases are these? Shouldn't we return 2 here? */
9236 /* Return the length of INSN. LENGTH is the initial length computed by
9237 attributes in the machine-description file. */
9240 mips_adjust_insn_length (rtx insn, int length)
9242 /* A unconditional jump has an unfilled delay slot if it is not part
9243 of a sequence. A conditional jump normally has a delay slot, but
9244 does not on MIPS16. */
9245 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9248 /* See how many nops might be needed to avoid hardware hazards. */
9249 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9250 switch (get_attr_hazard (insn))
9264 /* All MIPS16 instructions are a measly two bytes. */
9272 /* Return an asm sequence to start a noat block and load the address
9273 of a label into $1. */
9276 mips_output_load_label (void)
9278 if (TARGET_EXPLICIT_RELOCS)
9282 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9285 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9288 if (ISA_HAS_LOAD_DELAY)
9289 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9290 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9294 if (Pmode == DImode)
9295 return "%[dla\t%@,%0";
9297 return "%[la\t%@,%0";
9301 /* Return the assembly code for INSN, which has the operands given by
9302 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9303 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9304 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9305 version of BRANCH_IF_TRUE. */
9308 mips_output_conditional_branch (rtx insn, rtx *operands,
9309 const char *branch_if_true,
9310 const char *branch_if_false)
9312 unsigned int length;
9313 rtx taken, not_taken;
9315 length = get_attr_length (insn);
9318 /* Just a simple conditional branch. */
9319 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9320 return branch_if_true;
9323 /* Generate a reversed branch around a direct jump. This fallback does
9324 not use branch-likely instructions. */
9325 mips_branch_likely = false;
9326 not_taken = gen_label_rtx ();
9327 taken = operands[1];
9329 /* Generate the reversed branch to NOT_TAKEN. */
9330 operands[1] = not_taken;
9331 output_asm_insn (branch_if_false, operands);
9333 /* If INSN has a delay slot, we must provide delay slots for both the
9334 branch to NOT_TAKEN and the conditional jump. We must also ensure
9335 that INSN's delay slot is executed in the appropriate cases. */
9338 /* This first delay slot will always be executed, so use INSN's
9339 delay slot if is not annulled. */
9340 if (!INSN_ANNULLED_BRANCH_P (insn))
9342 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9343 asm_out_file, optimize, 1, NULL);
9344 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9347 output_asm_insn ("nop", 0);
9348 fprintf (asm_out_file, "\n");
9351 /* Output the unconditional branch to TAKEN. */
9353 output_asm_insn ("j\t%0%/", &taken);
9356 output_asm_insn (mips_output_load_label (), &taken);
9357 output_asm_insn ("jr\t%@%]%/", 0);
9360 /* Now deal with its delay slot; see above. */
9363 /* This delay slot will only be executed if the branch is taken.
9364 Use INSN's delay slot if is annulled. */
9365 if (INSN_ANNULLED_BRANCH_P (insn))
9367 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9368 asm_out_file, optimize, 1, NULL);
9369 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9372 output_asm_insn ("nop", 0);
9373 fprintf (asm_out_file, "\n");
9376 /* Output NOT_TAKEN. */
9377 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9378 CODE_LABEL_NUMBER (not_taken));
9382 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9383 if some ordered condition is true. The condition is given by
9384 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9385 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9386 its second is always zero. */
9389 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9391 const char *branch[2];
9393 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9394 Make BRANCH[0] branch on the inverse condition. */
9395 switch (GET_CODE (operands[0]))
9397 /* These cases are equivalent to comparisons against zero. */
9399 inverted_p = !inverted_p;
9402 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9403 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9406 /* These cases are always true or always false. */
9408 inverted_p = !inverted_p;
9411 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9412 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9416 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9417 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9420 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9423 /* Used to output div or ddiv instruction DIVISION, which has the operands
9424 given by OPERANDS. Add in a divide-by-zero check if needed.
9426 When working around R4000 and R4400 errata, we need to make sure that
9427 the division is not immediately followed by a shift[1][2]. We also
9428 need to stop the division from being put into a branch delay slot[3].
9429 The easiest way to avoid both problems is to add a nop after the
9430 division. When a divide-by-zero check is needed, this nop can be
9431 used to fill the branch delay slot.
9433 [1] If a double-word or a variable shift executes immediately
9434 after starting an integer division, the shift may give an
9435 incorrect result. See quotations of errata #16 and #28 from
9436 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9437 in mips.md for details.
9439 [2] A similar bug to [1] exists for all revisions of the
9440 R4000 and the R4400 when run in an MC configuration.
9441 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9443 "19. In this following sequence:
9445 ddiv (or ddivu or div or divu)
9446 dsll32 (or dsrl32, dsra32)
9448 if an MPT stall occurs, while the divide is slipping the cpu
9449 pipeline, then the following double shift would end up with an
9452 Workaround: The compiler needs to avoid generating any
9453 sequence with divide followed by extended double shift."
9455 This erratum is also present in "MIPS R4400MC Errata, Processor
9456 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9457 & 3.0" as errata #10 and #4, respectively.
9459 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9460 (also valid for MIPS R4000MC processors):
9462 "52. R4000SC: This bug does not apply for the R4000PC.
9464 There are two flavors of this bug:
9466 1) If the instruction just after divide takes an RF exception
9467 (tlb-refill, tlb-invalid) and gets an instruction cache
9468 miss (both primary and secondary) and the line which is
9469 currently in secondary cache at this index had the first
9470 data word, where the bits 5..2 are set, then R4000 would
9471 get a wrong result for the div.
9476 ------------------- # end-of page. -tlb-refill
9481 ------------------- # end-of page. -tlb-invalid
9484 2) If the divide is in the taken branch delay slot, where the
9485 target takes RF exception and gets an I-cache miss for the
9486 exception vector or where I-cache miss occurs for the
9487 target address, under the above mentioned scenarios, the
9488 div would get wrong results.
9491 j r2 # to next page mapped or unmapped
9492 div r8,r9 # this bug would be there as long
9493 # as there is an ICache miss and
9494 nop # the "data pattern" is present
9497 beq r0, r0, NextPage # to Next page
9501 This bug is present for div, divu, ddiv, and ddivu
9504 Workaround: For item 1), OS could make sure that the next page
9505 after the divide instruction is also mapped. For item 2), the
9506 compiler could make sure that the divide instruction is not in
9507 the branch delay slot."
9509 These processors have PRId values of 0x00004220 and 0x00004300 for
9510 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9513 mips_output_division (const char *division, rtx *operands)
9518 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9520 output_asm_insn (s, operands);
9523 if (TARGET_CHECK_ZERO_DIV)
9527 output_asm_insn (s, operands);
9528 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9530 else if (GENERATE_DIVIDE_TRAPS)
9532 output_asm_insn (s, operands);
9537 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9538 output_asm_insn (s, operands);
9539 s = "break\t7%)\n1:";
9545 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9546 with a final "000" replaced by "k". Ignore case.
9548 Note: this function is shared between GCC and GAS. */
9551 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9553 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9554 given++, canonical++;
9556 return ((*given == 0 && *canonical == 0)
9557 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9561 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9562 CPU name. We've traditionally allowed a lot of variation here.
9564 Note: this function is shared between GCC and GAS. */
9567 mips_matching_cpu_name_p (const char *canonical, const char *given)
9569 /* First see if the name matches exactly, or with a final "000"
9571 if (mips_strict_matching_cpu_name_p (canonical, given))
9574 /* If not, try comparing based on numerical designation alone.
9575 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9576 if (TOLOWER (*given) == 'r')
9578 if (!ISDIGIT (*given))
9581 /* Skip over some well-known prefixes in the canonical name,
9582 hoping to find a number there too. */
9583 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9585 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9587 else if (TOLOWER (canonical[0]) == 'r')
9590 return mips_strict_matching_cpu_name_p (canonical, given);
9594 /* Return the mips_cpu_info entry for the processor or ISA given
9595 by CPU_STRING. Return null if the string isn't recognized.
9597 A similar function exists in GAS. */
9599 static const struct mips_cpu_info *
9600 mips_parse_cpu (const char *cpu_string)
9602 const struct mips_cpu_info *p;
9605 /* In the past, we allowed upper-case CPU names, but it doesn't
9606 work well with the multilib machinery. */
9607 for (s = cpu_string; *s != 0; s++)
9610 warning (0, "the cpu name must be lower case");
9614 /* 'from-abi' selects the most compatible architecture for the given
9615 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9616 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9617 version. Look first at the -mgp options, if given, otherwise base
9618 the choice on MASK_64BIT in TARGET_DEFAULT. */
9619 if (strcasecmp (cpu_string, "from-abi") == 0)
9620 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9621 : ABI_NEEDS_64BIT_REGS ? 3
9622 : (TARGET_64BIT ? 3 : 1));
9624 /* 'default' has traditionally been a no-op. Probably not very useful. */
9625 if (strcasecmp (cpu_string, "default") == 0)
9628 for (p = mips_cpu_info_table; p->name != 0; p++)
9629 if (mips_matching_cpu_name_p (p->name, cpu_string))
9636 /* Return the processor associated with the given ISA level, or null
9637 if the ISA isn't valid. */
9639 static const struct mips_cpu_info *
9640 mips_cpu_info_from_isa (int isa)
9642 const struct mips_cpu_info *p;
9644 for (p = mips_cpu_info_table; p->name != 0; p++)
9651 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9652 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9653 they only hold condition code modes, and CCmode is always considered to
9654 be 4 bytes wide. All other registers are word sized. */
9657 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9659 if (ST_REG_P (regno))
9660 return ((GET_MODE_SIZE (mode) + 3) / 4);
9661 else if (! FP_REG_P (regno))
9662 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9664 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9667 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9668 all BLKmode objects are returned in memory. Under the new (N32 and
9669 64-bit MIPS ABIs) small structures are returned in a register.
9670 Objects with varying size must still be returned in memory, of
9674 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9677 return (TYPE_MODE (type) == BLKmode);
9679 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9680 || (int_size_in_bytes (type) == -1));
9684 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9686 return !TARGET_OLDABI;
9689 /* Return true if INSN is a multiply-add or multiply-subtract
9690 instruction and PREV assigns to the accumulator operand. */
9693 mips_linked_madd_p (rtx prev, rtx insn)
9697 x = single_set (insn);
9703 if (GET_CODE (x) == PLUS
9704 && GET_CODE (XEXP (x, 0)) == MULT
9705 && reg_set_p (XEXP (x, 1), prev))
9708 if (GET_CODE (x) == MINUS
9709 && GET_CODE (XEXP (x, 1)) == MULT
9710 && reg_set_p (XEXP (x, 0), prev))
9716 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9717 that may clobber hi or lo. */
9719 static rtx mips_macc_chains_last_hilo;
9721 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9722 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9725 mips_macc_chains_record (rtx insn)
9727 if (get_attr_may_clobber_hilo (insn))
9728 mips_macc_chains_last_hilo = insn;
9731 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9732 has NREADY elements, looking for a multiply-add or multiply-subtract
9733 instruction that is cumulative with mips_macc_chains_last_hilo.
9734 If there is one, promote it ahead of anything else that might
9735 clobber hi or lo. */
9738 mips_macc_chains_reorder (rtx *ready, int nready)
9742 if (mips_macc_chains_last_hilo != 0)
9743 for (i = nready - 1; i >= 0; i--)
9744 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9746 for (j = nready - 1; j > i; j--)
9747 if (recog_memoized (ready[j]) >= 0
9748 && get_attr_may_clobber_hilo (ready[j]))
9750 mips_promote_ready (ready, i, j);
9757 /* The last instruction to be scheduled. */
9759 static rtx vr4130_last_insn;
9761 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9762 points to an rtx that is initially an instruction. Nullify the rtx
9763 if the instruction uses the value of register X. */
9766 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9768 rtx *insn_ptr = data;
9771 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9775 /* Return true if there is true register dependence between vr4130_last_insn
9779 vr4130_true_reg_dependence_p (rtx insn)
9781 note_stores (PATTERN (vr4130_last_insn),
9782 vr4130_true_reg_dependence_p_1, &insn);
9786 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9787 the ready queue and that INSN2 is the instruction after it, return
9788 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9789 in which INSN1 and INSN2 can probably issue in parallel, but for
9790 which (INSN2, INSN1) should be less sensitive to instruction
9791 alignment than (INSN1, INSN2). See 4130.md for more details. */
9794 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9798 /* Check for the following case:
9800 1) there is some other instruction X with an anti dependence on INSN1;
9801 2) X has a higher priority than INSN2; and
9802 3) X is an arithmetic instruction (and thus has no unit restrictions).
9804 If INSN1 is the last instruction blocking X, it would better to
9805 choose (INSN1, X) over (INSN2, INSN1). */
9806 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9807 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9808 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9809 && recog_memoized (XEXP (dep, 0)) >= 0
9810 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9813 if (vr4130_last_insn != 0
9814 && recog_memoized (insn1) >= 0
9815 && recog_memoized (insn2) >= 0)
9817 /* See whether INSN1 and INSN2 use different execution units,
9818 or if they are both ALU-type instructions. If so, they can
9819 probably execute in parallel. */
9820 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9821 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9822 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9824 /* If only one of the instructions has a dependence on
9825 vr4130_last_insn, prefer to schedule the other one first. */
9826 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9827 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9831 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9832 is not an ALU-type instruction and if INSN1 uses the same
9833 execution unit. (Note that if this condition holds, we already
9834 know that INSN2 uses a different execution unit.) */
9835 if (class1 != VR4130_CLASS_ALU
9836 && recog_memoized (vr4130_last_insn) >= 0
9837 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9844 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9845 queue with at least two instructions. Swap the first two if
9846 vr4130_swap_insns_p says that it could be worthwhile. */
9849 vr4130_reorder (rtx *ready, int nready)
9851 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9852 mips_promote_ready (ready, nready - 2, nready - 1);
9855 /* Remove the instruction at index LOWER from ready queue READY and
9856 reinsert it in front of the instruction at index HIGHER. LOWER must
9860 mips_promote_ready (rtx *ready, int lower, int higher)
9865 new_head = ready[lower];
9866 for (i = lower; i < higher; i++)
9867 ready[i] = ready[i + 1];
9868 ready[i] = new_head;
9871 /* Implement TARGET_SCHED_REORDER. */
9874 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9875 rtx *ready, int *nreadyp, int cycle)
9877 if (!reload_completed && TUNE_MACC_CHAINS)
9880 mips_macc_chains_last_hilo = 0;
9882 mips_macc_chains_reorder (ready, *nreadyp);
9884 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9887 vr4130_last_insn = 0;
9889 vr4130_reorder (ready, *nreadyp);
9891 return mips_issue_rate ();
9894 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9897 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9900 switch (GET_CODE (PATTERN (insn)))
9904 /* Don't count USEs and CLOBBERs against the issue rate. */
9909 if (!reload_completed && TUNE_MACC_CHAINS)
9910 mips_macc_chains_record (insn);
9911 vr4130_last_insn = insn;
9917 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9918 dependencies have no cost. */
9921 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9922 rtx dep ATTRIBUTE_UNUSED, int cost)
9924 if (REG_NOTE_KIND (link) != 0)
9929 /* Return the number of instructions that can be issued per cycle. */
9932 mips_issue_rate (void)
9936 case PROCESSOR_R4130:
9937 case PROCESSOR_R5400:
9938 case PROCESSOR_R5500:
9939 case PROCESSOR_R7000:
9940 case PROCESSOR_R9000:
9944 case PROCESSOR_SB1A:
9945 /* This is actually 4, but we get better performance if we claim 3.
9946 This is partly because of unwanted speculative code motion with the
9947 larger number, and partly because in most common cases we can't
9948 reach the theoretical max of 4. */
9956 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9957 be as wide as the scheduling freedom in the DFA. */
9960 mips_multipass_dfa_lookahead (void)
9962 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9969 /* Implements a store data bypass check. We need this because the cprestore
9970 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9971 default routine to abort. We just return false for that case. */
9972 /* ??? Should try to give a better result here than assuming false. */
9975 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9977 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9980 return ! store_data_bypass_p (out_insn, in_insn);
9983 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9984 return the first operand of the associated "pref" or "prefx" insn. */
9987 mips_prefetch_cookie (rtx write, rtx locality)
9989 /* store_streamed / load_streamed. */
9990 if (INTVAL (locality) <= 0)
9991 return GEN_INT (INTVAL (write) + 4);
9994 if (INTVAL (locality) <= 2)
9997 /* store_retained / load_retained. */
9998 return GEN_INT (INTVAL (write) + 6);
10001 /* MIPS builtin function support. */
10003 struct builtin_description
10005 /* The code of the main .md file instruction. See mips_builtin_type
10006 for more information. */
10007 enum insn_code icode;
10009 /* The floating-point comparison code to use with ICODE, if any. */
10010 enum mips_fp_condition cond;
10012 /* The name of the builtin function. */
10015 /* Specifies how the function should be expanded. */
10016 enum mips_builtin_type builtin_type;
10018 /* The function's prototype. */
10019 enum mips_function_type function_type;
10021 /* The target flags required for this function. */
10025 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10026 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
10027 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10028 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10029 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10031 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10033 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10034 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10035 "__builtin_mips_" #INSN "_" #COND "_s", \
10036 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10037 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10038 "__builtin_mips_" #INSN "_" #COND "_d", \
10039 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10041 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10042 The lower and upper forms require TARGET_FLAGS while the any and all
10043 forms require MASK_MIPS3D. */
10044 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10045 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10046 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10047 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10048 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10049 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10050 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10051 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10052 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10053 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10054 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10055 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10056 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10058 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10059 require MASK_MIPS3D. */
10060 #define CMP_4S_BUILTINS(INSN, COND) \
10061 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10062 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10063 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10065 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10066 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10067 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10070 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10071 instruction requires TARGET_FLAGS. */
10072 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10073 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10074 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10075 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10077 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10078 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10079 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10082 /* Define all the builtins related to c.cond.fmt condition COND. */
10083 #define CMP_BUILTINS(COND) \
10084 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10085 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10086 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10087 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10088 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10089 CMP_4S_BUILTINS (c, COND), \
10090 CMP_4S_BUILTINS (cabs, COND)
10092 static const struct builtin_description mips_bdesc[] =
10094 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10095 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10096 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10097 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10098 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10099 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10100 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10101 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10103 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10104 MASK_PAIRED_SINGLE_FLOAT),
10105 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10106 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10107 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10108 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10110 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10111 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10112 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10113 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10114 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10115 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10117 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10118 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10119 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10120 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10121 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10122 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10124 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10127 /* Builtin functions for the SB-1 processor. */
10129 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10131 static const struct builtin_description sb1_bdesc[] =
10133 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10136 /* Builtin functions for DSP ASE. */
10138 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10139 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10140 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10141 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10143 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10144 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10145 builtin_description fields. */
10146 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10147 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10148 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10150 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10151 branch instruction. TARGET_FLAGS is a builtin_description field. */
10152 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10153 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10154 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10156 static const struct builtin_description dsp_bdesc[] =
10158 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10159 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10160 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10161 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10162 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10163 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10164 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10165 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10166 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10167 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10168 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10169 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10170 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10171 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10172 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10173 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10174 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10175 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10176 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10177 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10178 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10179 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10180 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10181 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10182 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10183 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10184 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10185 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10186 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10187 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10188 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10189 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10190 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10191 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10192 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10193 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10194 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10195 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10196 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10197 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10198 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10199 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10200 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10201 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10202 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10203 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10204 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10205 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10206 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10207 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10208 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10209 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10210 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10211 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10212 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10213 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10214 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10215 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10216 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10217 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10218 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10219 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10220 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10221 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10222 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10223 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10224 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10225 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10226 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10227 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10228 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10229 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10230 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10231 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10232 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10233 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10234 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10235 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10236 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10237 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10238 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10239 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10240 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10241 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10242 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10243 BPOSGE_BUILTIN (32, MASK_DSP)
10246 /* This helps provide a mapping from builtin function codes to bdesc
10251 /* The builtin function table that this entry describes. */
10252 const struct builtin_description *bdesc;
10254 /* The number of entries in the builtin function table. */
10257 /* The target processor that supports these builtin functions.
10258 PROCESSOR_MAX means we enable them for all processors. */
10259 enum processor_type proc;
10262 static const struct bdesc_map bdesc_arrays[] =
10264 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10265 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10266 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10269 /* Take the head of argument list *ARGLIST and convert it into a form
10270 suitable for input operand OP of instruction ICODE. Return the value
10271 and point *ARGLIST at the next element of the list. */
10274 mips_prepare_builtin_arg (enum insn_code icode,
10275 unsigned int op, tree *arglist)
10278 enum machine_mode mode;
10280 value = expand_normal (TREE_VALUE (*arglist));
10281 mode = insn_data[icode].operand[op].mode;
10282 if (!insn_data[icode].operand[op].predicate (value, mode))
10284 value = copy_to_mode_reg (mode, value);
10285 /* Check the predicate again. */
10286 if (!insn_data[icode].operand[op].predicate (value, mode))
10288 error ("invalid argument to builtin function");
10293 *arglist = TREE_CHAIN (*arglist);
10297 /* Return an rtx suitable for output operand OP of instruction ICODE.
10298 If TARGET is non-null, try to use it where possible. */
10301 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10303 enum machine_mode mode;
10305 mode = insn_data[icode].operand[op].mode;
10306 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10307 target = gen_reg_rtx (mode);
10312 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10315 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10316 enum machine_mode mode ATTRIBUTE_UNUSED,
10317 int ignore ATTRIBUTE_UNUSED)
10319 enum insn_code icode;
10320 enum mips_builtin_type type;
10321 tree fndecl, arglist;
10322 unsigned int fcode;
10323 const struct builtin_description *bdesc;
10324 const struct bdesc_map *m;
10326 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10327 arglist = TREE_OPERAND (exp, 1);
10328 fcode = DECL_FUNCTION_CODE (fndecl);
10331 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10333 if (fcode < m->size)
10336 icode = bdesc[fcode].icode;
10337 type = bdesc[fcode].builtin_type;
10347 case MIPS_BUILTIN_DIRECT:
10348 return mips_expand_builtin_direct (icode, target, arglist, true);
10350 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10351 return mips_expand_builtin_direct (icode, target, arglist, false);
10353 case MIPS_BUILTIN_MOVT:
10354 case MIPS_BUILTIN_MOVF:
10355 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10358 case MIPS_BUILTIN_CMP_ANY:
10359 case MIPS_BUILTIN_CMP_ALL:
10360 case MIPS_BUILTIN_CMP_UPPER:
10361 case MIPS_BUILTIN_CMP_LOWER:
10362 case MIPS_BUILTIN_CMP_SINGLE:
10363 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10366 case MIPS_BUILTIN_BPOSGE32:
10367 return mips_expand_builtin_bposge (type, target);
10374 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10377 mips_init_builtins (void)
10379 const struct builtin_description *d;
10380 const struct bdesc_map *m;
10381 tree types[(int) MIPS_MAX_FTYPE_MAX];
10382 tree V2SF_type_node;
10383 tree V2HI_type_node;
10384 tree V4QI_type_node;
10385 unsigned int offset;
10387 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10388 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10391 if (TARGET_PAIRED_SINGLE_FLOAT)
10393 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10395 types[MIPS_V2SF_FTYPE_V2SF]
10396 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10398 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10399 = build_function_type_list (V2SF_type_node,
10400 V2SF_type_node, V2SF_type_node, NULL_TREE);
10402 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10403 = build_function_type_list (V2SF_type_node,
10404 V2SF_type_node, V2SF_type_node,
10405 integer_type_node, NULL_TREE);
10407 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10408 = build_function_type_list (V2SF_type_node,
10409 V2SF_type_node, V2SF_type_node,
10410 V2SF_type_node, V2SF_type_node, NULL_TREE);
10412 types[MIPS_V2SF_FTYPE_SF_SF]
10413 = build_function_type_list (V2SF_type_node,
10414 float_type_node, float_type_node, NULL_TREE);
10416 types[MIPS_INT_FTYPE_V2SF_V2SF]
10417 = build_function_type_list (integer_type_node,
10418 V2SF_type_node, V2SF_type_node, NULL_TREE);
10420 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10421 = build_function_type_list (integer_type_node,
10422 V2SF_type_node, V2SF_type_node,
10423 V2SF_type_node, V2SF_type_node, NULL_TREE);
10425 types[MIPS_INT_FTYPE_SF_SF]
10426 = build_function_type_list (integer_type_node,
10427 float_type_node, float_type_node, NULL_TREE);
10429 types[MIPS_INT_FTYPE_DF_DF]
10430 = build_function_type_list (integer_type_node,
10431 double_type_node, double_type_node, NULL_TREE);
10433 types[MIPS_SF_FTYPE_V2SF]
10434 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10436 types[MIPS_SF_FTYPE_SF]
10437 = build_function_type_list (float_type_node,
10438 float_type_node, NULL_TREE);
10440 types[MIPS_SF_FTYPE_SF_SF]
10441 = build_function_type_list (float_type_node,
10442 float_type_node, float_type_node, NULL_TREE);
10444 types[MIPS_DF_FTYPE_DF]
10445 = build_function_type_list (double_type_node,
10446 double_type_node, NULL_TREE);
10448 types[MIPS_DF_FTYPE_DF_DF]
10449 = build_function_type_list (double_type_node,
10450 double_type_node, double_type_node, NULL_TREE);
10455 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10456 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10458 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10459 = build_function_type_list (V2HI_type_node,
10460 V2HI_type_node, V2HI_type_node,
10463 types[MIPS_SI_FTYPE_SI_SI]
10464 = build_function_type_list (intSI_type_node,
10465 intSI_type_node, intSI_type_node,
10468 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10469 = build_function_type_list (V4QI_type_node,
10470 V4QI_type_node, V4QI_type_node,
10473 types[MIPS_SI_FTYPE_V4QI]
10474 = build_function_type_list (intSI_type_node,
10478 types[MIPS_V2HI_FTYPE_V2HI]
10479 = build_function_type_list (V2HI_type_node,
10483 types[MIPS_SI_FTYPE_SI]
10484 = build_function_type_list (intSI_type_node,
10488 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10489 = build_function_type_list (V4QI_type_node,
10490 V2HI_type_node, V2HI_type_node,
10493 types[MIPS_V2HI_FTYPE_SI_SI]
10494 = build_function_type_list (V2HI_type_node,
10495 intSI_type_node, intSI_type_node,
10498 types[MIPS_SI_FTYPE_V2HI]
10499 = build_function_type_list (intSI_type_node,
10503 types[MIPS_V2HI_FTYPE_V4QI]
10504 = build_function_type_list (V2HI_type_node,
10508 types[MIPS_V4QI_FTYPE_V4QI_SI]
10509 = build_function_type_list (V4QI_type_node,
10510 V4QI_type_node, intSI_type_node,
10513 types[MIPS_V2HI_FTYPE_V2HI_SI]
10514 = build_function_type_list (V2HI_type_node,
10515 V2HI_type_node, intSI_type_node,
10518 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10519 = build_function_type_list (V2HI_type_node,
10520 V4QI_type_node, V2HI_type_node,
10523 types[MIPS_SI_FTYPE_V2HI_V2HI]
10524 = build_function_type_list (intSI_type_node,
10525 V2HI_type_node, V2HI_type_node,
10528 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10529 = build_function_type_list (intDI_type_node,
10530 intDI_type_node, V4QI_type_node, V4QI_type_node,
10533 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10534 = build_function_type_list (intDI_type_node,
10535 intDI_type_node, V2HI_type_node, V2HI_type_node,
10538 types[MIPS_DI_FTYPE_DI_SI_SI]
10539 = build_function_type_list (intDI_type_node,
10540 intDI_type_node, intSI_type_node, intSI_type_node,
10543 types[MIPS_V4QI_FTYPE_SI]
10544 = build_function_type_list (V4QI_type_node,
10548 types[MIPS_V2HI_FTYPE_SI]
10549 = build_function_type_list (V2HI_type_node,
10553 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10554 = build_function_type_list (void_type_node,
10555 V4QI_type_node, V4QI_type_node,
10558 types[MIPS_SI_FTYPE_V4QI_V4QI]
10559 = build_function_type_list (intSI_type_node,
10560 V4QI_type_node, V4QI_type_node,
10563 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10564 = build_function_type_list (void_type_node,
10565 V2HI_type_node, V2HI_type_node,
10568 types[MIPS_SI_FTYPE_DI_SI]
10569 = build_function_type_list (intSI_type_node,
10570 intDI_type_node, intSI_type_node,
10573 types[MIPS_DI_FTYPE_DI_SI]
10574 = build_function_type_list (intDI_type_node,
10575 intDI_type_node, intSI_type_node,
10578 types[MIPS_VOID_FTYPE_SI_SI]
10579 = build_function_type_list (void_type_node,
10580 intSI_type_node, intSI_type_node,
10583 types[MIPS_SI_FTYPE_PTR_SI]
10584 = build_function_type_list (intSI_type_node,
10585 ptr_type_node, intSI_type_node,
10588 types[MIPS_SI_FTYPE_VOID]
10589 = build_function_type (intSI_type_node, void_list_node);
10592 /* Iterate through all of the bdesc arrays, initializing all of the
10593 builtin functions. */
10596 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10598 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10599 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10600 if ((d->target_flags & target_flags) == d->target_flags)
10601 lang_hooks.builtin_function (d->name, types[d->function_type],
10602 d - m->bdesc + offset,
10603 BUILT_IN_MD, NULL, NULL);
10608 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10609 .md pattern and ARGLIST is the list of function arguments. TARGET,
10610 if nonnull, suggests a good place to put the result.
10611 HAS_TARGET indicates the function must return something. */
10614 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10617 rtx ops[MAX_RECOG_OPERANDS];
10622 /* We save target to ops[0]. */
10623 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10627 /* We need to test if arglist is not zero. Some instructions have extra
10628 clobber registers. */
10629 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10630 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10635 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10639 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10643 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10647 gcc_unreachable ();
10652 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10653 function (TYPE says which). ARGLIST is the list of arguments to the
10654 function, ICODE is the instruction that should be used to compare
10655 the first two arguments, and COND is the condition it should test.
10656 TARGET, if nonnull, suggests a good place to put the result. */
10659 mips_expand_builtin_movtf (enum mips_builtin_type type,
10660 enum insn_code icode, enum mips_fp_condition cond,
10661 rtx target, tree arglist)
10663 rtx cmp_result, op0, op1;
10665 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10666 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10667 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10668 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10670 icode = CODE_FOR_mips_cond_move_tf_ps;
10671 target = mips_prepare_builtin_target (icode, 0, target);
10672 if (type == MIPS_BUILTIN_MOVT)
10674 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10675 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10679 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10680 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10682 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10686 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10687 into TARGET otherwise. Return TARGET. */
10690 mips_builtin_branch_and_move (rtx condition, rtx target,
10691 rtx value_if_true, rtx value_if_false)
10693 rtx true_label, done_label;
10695 true_label = gen_label_rtx ();
10696 done_label = gen_label_rtx ();
10698 /* First assume that CONDITION is false. */
10699 emit_move_insn (target, value_if_false);
10701 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10702 emit_jump_insn (gen_condjump (condition, true_label));
10703 emit_jump_insn (gen_jump (done_label));
10706 /* Fix TARGET if CONDITION is true. */
10707 emit_label (true_label);
10708 emit_move_insn (target, value_if_true);
10710 emit_label (done_label);
10714 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10715 of the comparison instruction and COND is the condition it should test.
10716 ARGLIST is the list of function arguments and TARGET, if nonnull,
10717 suggests a good place to put the boolean result. */
10720 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10721 enum insn_code icode, enum mips_fp_condition cond,
10722 rtx target, tree arglist)
10724 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10727 if (target == 0 || GET_MODE (target) != SImode)
10728 target = gen_reg_rtx (SImode);
10730 /* Prepare the operands to the comparison. */
10731 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10732 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10733 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10735 switch (insn_data[icode].n_operands)
10738 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10742 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10743 ops[3], ops[4], GEN_INT (cond)));
10747 gcc_unreachable ();
10750 /* If the comparison sets more than one register, we define the result
10751 to be 0 if all registers are false and -1 if all registers are true.
10752 The value of the complete result is indeterminate otherwise. */
10753 switch (builtin_type)
10755 case MIPS_BUILTIN_CMP_ALL:
10756 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10757 return mips_builtin_branch_and_move (condition, target,
10758 const0_rtx, const1_rtx);
10760 case MIPS_BUILTIN_CMP_UPPER:
10761 case MIPS_BUILTIN_CMP_LOWER:
10762 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10763 condition = gen_single_cc (cmp_result, offset);
10764 return mips_builtin_branch_and_move (condition, target,
10765 const1_rtx, const0_rtx);
10768 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10769 return mips_builtin_branch_and_move (condition, target,
10770 const1_rtx, const0_rtx);
10774 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10775 suggests a good place to put the boolean result. */
10778 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10780 rtx condition, cmp_result;
10783 if (target == 0 || GET_MODE (target) != SImode)
10784 target = gen_reg_rtx (SImode);
10786 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10788 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10793 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10794 return mips_builtin_branch_and_move (condition, target,
10795 const1_rtx, const0_rtx);
10798 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10799 FIRST is true if this is the first time handling this decl. */
10802 mips_encode_section_info (tree decl, rtx rtl, int first)
10804 default_encode_section_info (decl, rtl, first);
10806 if (TREE_CODE (decl) == FUNCTION_DECL
10807 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10809 rtx symbol = XEXP (rtl, 0);
10810 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10814 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live
10815 on entry to a function when generating -mshared abicalls code. */
10818 mips_extra_live_on_entry (bitmap regs)
10820 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
10821 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10824 /* SImode values are represented as sign-extended to DImode. */
10827 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10829 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10830 return SIGN_EXTEND;
10835 #include "gt-mips.h"