1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-flags.h"
40 #include "insn-attr.h"
41 #include "insn-codes.h"
45 #undef MAX /* sys/param.h may also define these */
54 #if defined(USG) || !defined(HAVE_STAB_H)
55 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
57 #include <stab.h> /* On BSD, use the system's stab.h. */
61 #define STAB_CODE_TYPE enum __stab_debug_code
63 #define STAB_CODE_TYPE int
66 extern char *mktemp ();
67 extern tree lookup_name ();
69 /* Enumeration for all of the relational tests, so that we can build
70 arrays indexed by the test type, and not worry about the order
89 static enum internal_test map_test_to_internal_test PROTO ((enum rtx_code));
90 static int mips16_simple_memory_operand PROTO ((rtx, rtx,
92 static int m16_check_op PROTO ((rtx, int, int, int));
93 static void block_move_loop PROTO ((rtx, rtx, int, int,
95 static void block_move_call PROTO ((rtx, rtx, rtx));
96 static FILE *make_temp_file PROTO ((void));
97 static void save_restore_insns PROTO ((int, rtx,
99 static void mips16_output_gp_offset PROTO ((FILE *, rtx));
100 static void mips16_fp_args PROTO ((FILE *, int, int));
101 static void build_mips16_function_stub PROTO ((FILE *));
102 static void mips16_optimize_gp PROTO ((rtx));
103 static rtx add_constant PROTO ((struct constant **,
106 static void dump_constants PROTO ((struct constant *,
108 static rtx mips_find_symbol PROTO ((rtx));
109 static void abort_with_insn PROTO ((rtx, const char *))
113 /* Global variables for machine-dependent things. */
115 /* Threshold for data being put into the small data/bss area, instead
116 of the normal data area (references to the small data/bss area take
117 1 instruction, and use the global pointer, references to the normal
118 data area takes 2 instructions). */
119 int mips_section_threshold = -1;
121 /* Count the number of .file directives, so that .loc is up to date. */
122 int num_source_filenames = 0;
124 /* Count the number of sdb related labels are generated (to find block
125 start and end boundaries). */
126 int sdb_label_count = 0;
128 /* Next label # for each statement for Silicon Graphics IRIS systems. */
131 /* Non-zero if inside of a function, because the stupid MIPS asm can't
132 handle .files inside of functions. */
133 int inside_function = 0;
135 /* Files to separate the text and the data output, so that all of the data
136 can be emitted before the text, which will mean that the assembler will
137 generate smaller code, based on the global pointer. */
138 FILE *asm_out_data_file;
139 FILE *asm_out_text_file;
141 /* Linked list of all externals that are to be emitted when optimizing
142 for the global pointer if they haven't been declared by the end of
143 the program with an appropriate .comm or initialization. */
147 struct extern_list *next; /* next external */
148 char *name; /* name of the external */
149 int size; /* size in bytes */
152 /* Name of the file containing the current function. */
153 const char *current_function_file = "";
155 /* Warning given that Mips ECOFF can't support changing files
156 within a function. */
157 int file_in_function_warning = FALSE;
159 /* Whether to suppress issuing .loc's because the user attempted
160 to change the filename within a function. */
161 int ignore_line_number = FALSE;
163 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
169 /* The next branch instruction is a branch likely, not branch normal. */
170 int mips_branch_likely;
172 /* Count of delay slots and how many are filled. */
173 int dslots_load_total;
174 int dslots_load_filled;
175 int dslots_jump_total;
176 int dslots_jump_filled;
178 /* # of nops needed by previous insn */
179 int dslots_number_nops;
181 /* Number of 1/2/3 word references to data items (ie, not jal's). */
184 /* registers to check for load delay */
185 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
187 /* Cached operands, and operator to compare for use in set/branch on
191 /* what type of branch to use */
192 enum cmp_type branch_type;
194 /* Number of previously seen half-pic pointers and references. */
195 static int prev_half_pic_ptrs = 0;
196 static int prev_half_pic_refs = 0;
198 /* which cpu are we scheduling for */
199 enum processor_type mips_cpu;
201 /* which instruction set architecture to use. */
204 #ifdef MIPS_ABI_DEFAULT
205 /* Which ABI to use. This is defined to a constant in mips.h if the target
206 doesn't support multiple ABIs. */
210 /* Strings to hold which cpu and instruction set architecture to use. */
211 const char *mips_cpu_string; /* for -mcpu=<xxx> */
212 const char *mips_isa_string; /* for -mips{1,2,3,4} */
213 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
215 /* Whether we are generating mips16 code. This is a synonym for
216 TARGET_MIPS16, and exists for use as an attribute. */
219 /* This variable is set by -mno-mips16. We only care whether
220 -mno-mips16 appears or not, and using a string in this fashion is
221 just a way to avoid using up another bit in target_flags. */
222 const char *mips_no_mips16_string;
224 /* This is only used to determine if an type size setting option was
225 explicitly specified (-mlong64, -mint64, -mlong32). The specs
226 set this option if such an option is used. */
227 const char *mips_explicit_type_size_string;
229 /* Whether we are generating mips16 hard float code. In mips16 mode
230 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
231 -msoft-float was not specified by the user, which means that we
232 should arrange to call mips32 hard floating point code. */
233 int mips16_hard_float;
235 /* This variable is set by -mentry. We only care whether -mentry
236 appears or not, and using a string in this fashion is just a way to
237 avoid using up another bit in target_flags. */
238 const char *mips_entry_string;
240 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
243 /* If TRUE, we split addresses into their high and low parts in the RTL. */
244 int mips_split_addresses;
246 /* Generating calls to position independent functions? */
247 enum mips_abicalls_type mips_abicalls;
249 /* High and low marks for floating point values which we will accept
250 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
251 initialized in override_options. */
252 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
254 /* Mode used for saving/restoring general purpose registers. */
255 static enum machine_mode gpr_mode;
257 /* Array giving truth value on whether or not a given hard register
258 can support a given mode. */
259 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
261 /* Current frame information calculated by compute_frame_size. */
262 struct mips_frame_info current_frame_info;
264 /* Zero structure to initialize current_frame_info. */
265 struct mips_frame_info zero_frame_info;
267 /* Temporary filename used to buffer .text until end of program
269 static char *temp_filename;
271 /* Pseudo-reg holding the address of the current function when
272 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
273 by mips_finalize_pic if it was created. */
274 rtx embedded_pic_fnaddr_rtx;
276 /* The length of all strings seen when compiling for the mips16. This
277 is used to tell how many strings are in the constant pool, so that
278 we can see if we may have an overflow. This is reset each time the
279 constant pool is output. */
280 int mips_string_length;
282 /* Pseudo-reg holding the value of $28 in a mips16 function which
283 refers to GP relative global variables. */
284 rtx mips16_gp_pseudo_rtx;
286 /* In mips16 mode, we build a list of all the string constants we see
287 in a particular function. */
289 struct string_constant
291 struct string_constant *next;
295 static struct string_constant *string_constants;
297 /* List of all MIPS punctuation characters used by print_operand. */
298 char mips_print_operand_punct[256];
300 /* Map GCC register number to debugger register number. */
301 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
303 /* Buffer to use to enclose a load/store operation with %{ %} to
304 turn on .set volatile. */
305 static char volatile_buffer[60];
307 /* Hardware names for the registers. If -mrnames is used, this
308 will be overwritten with mips_sw_reg_names. */
310 char mips_reg_names[][8] =
312 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
313 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
314 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
315 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
316 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
317 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
318 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
319 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
320 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
321 "$fcc5","$fcc6","$fcc7","$rap"
324 /* Mips software names for the registers, used to overwrite the
325 mips_reg_names array. */
327 char mips_sw_reg_names[][8] =
329 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
330 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
331 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
332 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
333 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
334 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
335 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
336 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
337 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
338 "$fcc5","$fcc6","$fcc7","$rap"
341 /* Map hard register number to register class */
342 enum reg_class mips_regno_to_class[] =
344 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
345 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
346 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
347 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
348 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
349 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
350 T_REG, GR_REGS, GR_REGS, GR_REGS,
351 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
352 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
353 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
354 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
355 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
356 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
357 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
358 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
359 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
360 HI_REG, LO_REG, HILO_REG, ST_REGS,
361 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
362 ST_REGS, ST_REGS, ST_REGS, GR_REGS
365 /* Map register constraint character to register class. */
366 enum reg_class mips_char_to_class[256] =
368 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
369 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
370 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
371 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
431 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
435 /* Return truth value of whether OP can be used as an operands
436 where a register or 16 bit unsigned integer is needed. */
439 uns_arith_operand (op, mode)
441 enum machine_mode mode;
443 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
446 return register_operand (op, mode);
449 /* Return truth value of whether OP can be used as an operands
450 where a 16 bit integer is needed */
453 arith_operand (op, mode)
455 enum machine_mode mode;
457 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
460 /* On the mips16, a GP relative value is a signed 16 bit offset. */
461 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
464 return register_operand (op, mode);
467 /* Return truth value of whether OP can be used as an operand in a two
468 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
471 arith32_operand (op, mode)
473 enum machine_mode mode;
475 if (GET_CODE (op) == CONST_INT)
478 return register_operand (op, mode);
481 /* Return truth value of whether OP is a integer which fits in 16 bits */
486 enum machine_mode mode ATTRIBUTE_UNUSED;
488 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
491 /* Return truth value of whether OP is a 32 bit integer which is too big to
492 be loaded with one instruction. */
497 enum machine_mode mode ATTRIBUTE_UNUSED;
501 if (GET_CODE (op) != CONST_INT)
506 /* ior reg,$r0,value */
507 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
510 /* subu reg,$r0,value */
511 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
514 /* lui reg,value>>16 */
515 if ((value & 0x0000ffff) == 0)
521 /* Return truth value of whether OP is a register or the constant 0.
522 In mips16 mode, we only accept a register, since the mips16 does
526 reg_or_0_operand (op, mode)
528 enum machine_mode mode;
530 switch (GET_CODE (op))
535 return INTVAL (op) == 0;
540 return op == CONST0_RTX (mode);
544 return register_operand (op, mode);
553 /* Return truth value of whether OP is a register or the constant 0,
554 even in mips16 mode. */
557 true_reg_or_0_operand (op, mode)
559 enum machine_mode mode;
561 switch (GET_CODE (op))
564 return INTVAL (op) == 0;
567 return op == CONST0_RTX (mode);
571 return register_operand (op, mode);
580 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
583 mips_const_double_ok (op, mode)
585 enum machine_mode mode;
589 if (GET_CODE (op) != CONST_DOUBLE)
592 if (mode == VOIDmode)
595 if (mode != SFmode && mode != DFmode)
598 if (op == CONST0_RTX (mode))
601 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
602 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
605 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
607 if (REAL_VALUE_ISNAN (d))
610 if (REAL_VALUE_NEGATIVE (d))
611 d = REAL_VALUE_NEGATE (d);
615 if (REAL_VALUES_LESS (d, dfhigh)
616 && REAL_VALUES_LESS (dflow, d))
621 if (REAL_VALUES_LESS (d, sfhigh)
622 && REAL_VALUES_LESS (sflow, d))
629 /* Accept the floating point constant 1 in the appropriate mode. */
632 const_float_1_operand (op, mode)
634 enum machine_mode mode;
637 static REAL_VALUE_TYPE onedf;
638 static REAL_VALUE_TYPE onesf;
639 static int one_initialized;
641 if (GET_CODE (op) != CONST_DOUBLE
642 || mode != GET_MODE (op)
643 || (mode != DFmode && mode != SFmode))
646 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
648 /* We only initialize these values if we need them, since we will
649 never get called unless mips_isa >= 4. */
650 if (! one_initialized)
652 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
653 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
658 return REAL_VALUES_EQUAL (d, onedf);
660 return REAL_VALUES_EQUAL (d, onesf);
663 /* Return true if a memory load or store of REG plus OFFSET in MODE
664 can be represented in a single word on the mips16. */
667 mips16_simple_memory_operand (reg, offset, mode)
670 enum machine_mode mode;
676 /* We can't tell, because we don't know how the value will
677 eventually be accessed. Returning 0 here does no great
678 harm; it just prevents some possible instruction scheduling. */
682 size = GET_MODE_SIZE (mode);
684 if (INTVAL (offset) % size != 0)
686 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
690 if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size)
695 /* Return truth value if a memory operand fits in a single instruction
696 (ie, register + small offset). */
699 simple_memory_operand (op, mode)
701 enum machine_mode mode;
703 rtx addr, plus0, plus1;
705 /* Eliminate non-memory operations */
706 if (GET_CODE (op) != MEM)
709 /* dword operations really put out 2 instructions, so eliminate them. */
710 /* ??? This isn't strictly correct. It is OK to accept multiword modes
711 here, since the length attributes are being set correctly, but only
712 if the address is offsettable. LO_SUM is not offsettable. */
713 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
716 /* Decode the address now. */
718 switch (GET_CODE (addr))
727 return SMALL_INT (op);
730 plus0 = XEXP (addr, 0);
731 plus1 = XEXP (addr, 1);
732 if (GET_CODE (plus0) == REG
733 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
735 || mips16_simple_memory_operand (plus0, plus1, mode)))
738 else if (GET_CODE (plus1) == REG
739 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
741 || mips16_simple_memory_operand (plus1, plus0, mode)))
748 /* We used to allow small symbol refs here (ie, stuff in .sdata
749 or .sbss), but this causes some bugs in G++. Also, it won't
750 interfere if the MIPS linker rewrites the store instruction
751 because the function is PIC. */
753 case LABEL_REF: /* never gp relative */
757 /* If -G 0, we can never have a GP relative memory operation.
758 Also, save some time if not optimizing. */
763 rtx offset = const0_rtx;
764 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
765 if (GET_CODE (op) != SYMBOL_REF)
768 /* let's be paranoid.... */
769 if (! SMALL_INT (offset))
776 return SYMBOL_REF_FLAG (addr);
779 /* This SYMBOL_REF case is for the mips16. If the above case is
780 reenabled, this one should be merged in. */
782 /* References to the constant pool on the mips16 use a small
783 offset if the function is small. The only time we care about
784 getting this right is during delayed branch scheduling, so
785 don't need to check until then. The machine_dependent_reorg
786 function will set the total length of the instructions used
787 in the function in current_frame_info. If that is small
788 enough, we know for sure that this is a small offset. It
789 would be better if we could take into account the location of
790 the instruction within the function, but we can't, because we
791 don't know where we are. */
793 && CONSTANT_POOL_ADDRESS_P (addr)
794 && current_frame_info.insns_len > 0)
798 size = current_frame_info.insns_len + get_pool_size ();
799 if (GET_MODE_SIZE (mode) == 4)
800 return size < 4 * 0x100;
801 else if (GET_MODE_SIZE (mode) == 8)
802 return size < 8 * 0x20;
816 /* Return nonzero for a memory address that can be used to load or store
820 double_memory_operand (op, mode)
822 enum machine_mode mode;
826 if (GET_CODE (op) != MEM
827 || ! memory_operand (op, mode))
829 /* During reload, we accept a pseudo register if it has an
830 appropriate memory address. If we don't do this, we will
831 wind up reloading into a register, and then reloading that
832 register from memory, when we could just reload directly from
834 if (reload_in_progress
835 && GET_CODE (op) == REG
836 && REGNO (op) >= FIRST_PSEUDO_REGISTER
837 && reg_renumber[REGNO (op)] < 0
838 && reg_equiv_mem[REGNO (op)] != 0
839 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
842 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
843 the same test performed for 'm' in find_reloads. */
845 if (reload_in_progress
847 && (GET_CODE (op) == MEM
848 || (GET_CODE (op) == REG
849 && REGNO (op) >= FIRST_PSEUDO_REGISTER
850 && reg_renumber[REGNO (op)] < 0)))
853 if (reload_in_progress
855 && GET_CODE (op) == MEM)
861 /* During reload on the mips16, we accept a large offset
862 from the frame pointer or the stack pointer. This large
863 address will get reloaded anyhow. */
864 if (GET_CODE (addr) == PLUS
865 && GET_CODE (XEXP (addr, 0)) == REG
866 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
867 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
868 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
869 && ! SMALL_INT (XEXP (addr, 1)))
870 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
871 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
874 /* Similarly, we accept a case where the memory address is
875 itself on the stack, and will be reloaded. */
876 if (GET_CODE (addr) == MEM)
880 maddr = XEXP (addr, 0);
881 if (GET_CODE (maddr) == PLUS
882 && GET_CODE (XEXP (maddr, 0)) == REG
883 && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM
884 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
885 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
886 && ! SMALL_INT (XEXP (maddr, 1)))
887 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
888 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
892 /* We also accept the same case when we have a 16 bit signed
893 offset mixed in as well. The large address will get
894 reloaded, and the 16 bit offset will be OK. */
895 if (GET_CODE (addr) == PLUS
896 && GET_CODE (XEXP (addr, 0)) == MEM
897 && GET_CODE (XEXP (addr, 1)) == CONST_INT
898 && SMALL_INT (XEXP (addr, 1)))
900 addr = XEXP (XEXP (addr, 0), 0);
901 if (GET_CODE (addr) == PLUS
902 && GET_CODE (XEXP (addr, 0)) == REG
903 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
904 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
905 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
906 && ! SMALL_INT (XEXP (addr, 1)))
907 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
908 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
918 /* In this case we can use an instruction like sd. */
922 /* Make sure that 4 added to the address is a valid memory address.
923 This essentially just checks for overflow in an added constant. */
927 if (CONSTANT_ADDRESS_P (addr))
930 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
933 plus_constant_for_output (addr, 4));
936 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
939 equality_op (op, mode)
941 enum machine_mode mode;
943 if (mode != GET_MODE (op))
946 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
949 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
954 enum machine_mode mode;
956 if (mode != GET_MODE (op))
959 return GET_RTX_CLASS (GET_CODE (op)) == '<';
962 /* Return nonzero if the operand is either the PC or a label_ref. */
965 pc_or_label_operand (op, mode)
967 enum machine_mode mode ATTRIBUTE_UNUSED;
972 if (GET_CODE (op) == LABEL_REF)
978 /* Test for a valid operand for a call instruction.
979 Don't allow the arg pointer register or virtual regs
980 since they may change into reg + const, which the patterns
984 call_insn_operand (op, mode)
986 enum machine_mode mode ATTRIBUTE_UNUSED;
988 return (CONSTANT_ADDRESS_P (op)
989 || (GET_CODE (op) == REG && op != arg_pointer_rtx
990 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
991 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
994 /* Return nonzero if OPERAND is valid as a source operand for a move
998 move_operand (op, mode)
1000 enum machine_mode mode;
1002 /* Accept any general operand after reload has started; doing so
1003 avoids losing if reload does an in-place replacement of a register
1004 with a SYMBOL_REF or CONST. */
1005 return (general_operand (op, mode)
1006 && (! (mips_split_addresses && mips_check_split (op, mode))
1007 || reload_in_progress || reload_completed)
1009 && GET_CODE (op) == SYMBOL_REF
1010 && ! mips16_constant (op, mode, 1, 0)));
1013 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1014 This accepts not only general_operand, but also sign extended
1015 constants and registers. We need to accept sign extended constants
1016 in case a sign extended register which is used in an expression,
1017 and is equivalent to a constant, is spilled. */
1020 movdi_operand (op, mode)
1022 enum machine_mode mode;
1026 && GET_CODE (op) == SIGN_EXTEND
1027 && GET_MODE (op) == DImode
1028 && (GET_MODE (XEXP (op, 0)) == SImode
1029 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1030 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1031 && (register_operand (XEXP (op, 0), SImode)
1032 || immediate_operand (XEXP (op, 0), SImode)))
1035 return (general_operand (op, mode)
1037 && GET_CODE (op) == SYMBOL_REF
1038 && ! mips16_constant (op, mode, 1, 0)));
1041 /* Like register_operand, but when in 64 bit mode also accept a sign
1042 extend of a 32 bit register, since the value is known to be already
1046 se_register_operand (op, mode)
1048 enum machine_mode mode;
1052 && GET_CODE (op) == SIGN_EXTEND
1053 && GET_MODE (op) == DImode
1054 && GET_MODE (XEXP (op, 0)) == SImode
1055 && register_operand (XEXP (op, 0), SImode))
1058 return register_operand (op, mode);
1061 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1062 extend of a 32 bit register, since the value is known to be already
1066 se_reg_or_0_operand (op, mode)
1068 enum machine_mode mode;
1072 && GET_CODE (op) == SIGN_EXTEND
1073 && GET_MODE (op) == DImode
1074 && GET_MODE (XEXP (op, 0)) == SImode
1075 && register_operand (XEXP (op, 0), SImode))
1078 return reg_or_0_operand (op, mode);
1081 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1082 extend of a 32 bit register, since the value is known to be already
1086 se_uns_arith_operand (op, mode)
1088 enum machine_mode mode;
1092 && GET_CODE (op) == SIGN_EXTEND
1093 && GET_MODE (op) == DImode
1094 && GET_MODE (XEXP (op, 0)) == SImode
1095 && register_operand (XEXP (op, 0), SImode))
1098 return uns_arith_operand (op, mode);
1101 /* Like arith_operand, but when in 64 bit mode also accept a sign
1102 extend of a 32 bit register, since the value is known to be already
1106 se_arith_operand (op, mode)
1108 enum machine_mode mode;
1112 && GET_CODE (op) == SIGN_EXTEND
1113 && GET_MODE (op) == DImode
1114 && GET_MODE (XEXP (op, 0)) == SImode
1115 && register_operand (XEXP (op, 0), SImode))
1118 return arith_operand (op, mode);
1121 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1122 extend of a 32 bit register, since the value is known to be already
1126 se_nonmemory_operand (op, mode)
1128 enum machine_mode mode;
1132 && GET_CODE (op) == SIGN_EXTEND
1133 && GET_MODE (op) == DImode
1134 && GET_MODE (XEXP (op, 0)) == SImode
1135 && register_operand (XEXP (op, 0), SImode))
1138 return nonmemory_operand (op, mode);
1141 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1142 sign extend of a 32 bit register, since the value is known to be
1143 already sign extended. */
1146 se_nonimmediate_operand (op, mode)
1148 enum machine_mode mode;
1152 && GET_CODE (op) == SIGN_EXTEND
1153 && GET_MODE (op) == DImode
1154 && GET_MODE (XEXP (op, 0)) == SImode
1155 && register_operand (XEXP (op, 0), SImode))
1158 return nonimmediate_operand (op, mode);
1161 /* Accept any operand that can appear in a mips16 constant table
1162 instruction. We can't use any of the standard operand functions
1163 because for these instructions we accept values that are not
1164 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1167 consttable_operand (op, mode)
1169 enum machine_mode mode ATTRIBUTE_UNUSED;
1171 return CONSTANT_P (op);
1174 /* Return nonzero if we split the address into high and low parts. */
1176 /* ??? We should also handle reg+array somewhere. We get four
1177 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1178 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1179 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1180 out of the address, then we have 4 instructions to combine. Perhaps
1181 add a 3->2 define_split for combine. */
1183 /* ??? We could also split a CONST_INT here if it is a large_int().
1184 However, it doesn't seem to be very useful to have %hi(constant).
1185 We would be better off by doing the masking ourselves and then putting
1186 the explicit high part of the constant in the RTL. This will give better
1187 optimization. Also, %hi(constant) needs assembler changes to work.
1188 There is already a define_split that does this. */
1191 mips_check_split (address, mode)
1193 enum machine_mode mode;
1195 /* ??? This is the same check used in simple_memory_operand.
1196 We use it here because LO_SUM is not offsettable. */
1197 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1200 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1201 || (GET_CODE (address) == CONST
1202 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1203 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1204 || GET_CODE (address) == LABEL_REF)
1210 /* We need a lot of little routines to check constant values on the
1211 mips16. These are used to figure out how long the instruction will
1212 be. It would be much better to do this using constraints, but
1213 there aren't nearly enough letters available. */
1216 m16_check_op (op, low, high, mask)
1222 return (GET_CODE (op) == CONST_INT
1223 && INTVAL (op) >= low
1224 && INTVAL (op) <= high
1225 && (INTVAL (op) & mask) == 0);
1229 m16_uimm3_b (op, mode)
1231 enum machine_mode mode ATTRIBUTE_UNUSED;
1233 return m16_check_op (op, 0x1, 0x8, 0);
1237 m16_simm4_1 (op, mode)
1239 enum machine_mode mode ATTRIBUTE_UNUSED;
1241 return m16_check_op (op, - 0x8, 0x7, 0);
1245 m16_nsimm4_1 (op, mode)
1247 enum machine_mode mode ATTRIBUTE_UNUSED;
1249 return m16_check_op (op, - 0x7, 0x8, 0);
1253 m16_simm5_1 (op, mode)
1255 enum machine_mode mode ATTRIBUTE_UNUSED;
1257 return m16_check_op (op, - 0x10, 0xf, 0);
1261 m16_nsimm5_1 (op, mode)
1263 enum machine_mode mode ATTRIBUTE_UNUSED;
1265 return m16_check_op (op, - 0xf, 0x10, 0);
1269 m16_uimm5_4 (op, mode)
1271 enum machine_mode mode ATTRIBUTE_UNUSED;
1273 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1277 m16_nuimm5_4 (op, mode)
1279 enum machine_mode mode ATTRIBUTE_UNUSED;
1281 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1285 m16_simm8_1 (op, mode)
1287 enum machine_mode mode ATTRIBUTE_UNUSED;
1289 return m16_check_op (op, - 0x80, 0x7f, 0);
1293 m16_nsimm8_1 (op, mode)
1295 enum machine_mode mode ATTRIBUTE_UNUSED;
1297 return m16_check_op (op, - 0x7f, 0x80, 0);
1301 m16_uimm8_1 (op, mode)
1303 enum machine_mode mode ATTRIBUTE_UNUSED;
1305 return m16_check_op (op, 0x0, 0xff, 0);
1309 m16_nuimm8_1 (op, mode)
1311 enum machine_mode mode ATTRIBUTE_UNUSED;
1313 return m16_check_op (op, - 0xff, 0x0, 0);
1317 m16_uimm8_m1_1 (op, mode)
1319 enum machine_mode mode ATTRIBUTE_UNUSED;
1321 return m16_check_op (op, - 0x1, 0xfe, 0);
1325 m16_uimm8_4 (op, mode)
1327 enum machine_mode mode ATTRIBUTE_UNUSED;
1329 return m16_check_op (op, 0x0, 0xff << 2, 3);
1333 m16_nuimm8_4 (op, mode)
1335 enum machine_mode mode ATTRIBUTE_UNUSED;
1337 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1341 m16_simm8_8 (op, mode)
1343 enum machine_mode mode ATTRIBUTE_UNUSED;
1345 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1349 m16_nsimm8_8 (op, mode)
1351 enum machine_mode mode ATTRIBUTE_UNUSED;
1353 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1356 /* References to the string table on the mips16 only use a small
1357 offset if the function is small. See the comment in the SYMBOL_REF
1358 case in simple_memory_operand. We can't check for LABEL_REF here,
1359 because the offset is always large if the label is before the
1360 referencing instruction. */
1363 m16_usym8_4 (op, mode)
1365 enum machine_mode mode ATTRIBUTE_UNUSED;
1367 if (GET_CODE (op) == SYMBOL_REF
1368 && SYMBOL_REF_FLAG (op)
1369 && current_frame_info.insns_len > 0
1370 && XSTR (op, 0)[0] == '*'
1371 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1372 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1373 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1376 struct string_constant *l;
1378 /* Make sure this symbol is on thelist of string constants to be
1379 output for this function. It is possible that it has already
1380 been output, in which case this requires a large offset. */
1381 for (l = string_constants; l != NULL; l = l->next)
1382 if (strcmp (l->label, XSTR (op, 0)) == 0)
1390 m16_usym5_4 (op, mode)
1392 enum machine_mode mode ATTRIBUTE_UNUSED;
1394 if (GET_CODE (op) == SYMBOL_REF
1395 && SYMBOL_REF_FLAG (op)
1396 && current_frame_info.insns_len > 0
1397 && XSTR (op, 0)[0] == '*'
1398 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1399 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1400 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1403 struct string_constant *l;
1405 /* Make sure this symbol is on thelist of string constants to be
1406 output for this function. It is possible that it has already
1407 been output, in which case this requires a large offset. */
1408 for (l = string_constants; l != NULL; l = l->next)
1409 if (strcmp (l->label, XSTR (op, 0)) == 0)
1416 /* Returns an operand string for the given instruction's delay slot,
1417 after updating filled delay slot statistics.
1419 We assume that operands[0] is the target register that is set.
1421 In order to check the next insn, most of this functionality is moved
1422 to FINAL_PRESCAN_INSN, and we just set the global variables that
1425 /* ??? This function no longer does anything useful, because final_prescan_insn
1426 now will never emit a nop. */
1429 mips_fill_delay_slot (ret, type, operands, cur_insn)
1430 char *ret; /* normal string to return */
1431 enum delay_type type; /* type of delay */
1432 rtx operands[]; /* operands to use */
1433 rtx cur_insn; /* current insn */
1435 register rtx set_reg;
1436 register enum machine_mode mode;
1437 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1438 register int num_nops;
1440 if (type == DELAY_LOAD || type == DELAY_FCMP)
1443 else if (type == DELAY_HILO)
1449 /* Make sure that we don't put nop's after labels. */
1450 next_insn = NEXT_INSN (cur_insn);
1451 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1452 next_insn = NEXT_INSN (next_insn);
1454 dslots_load_total += num_nops;
1455 if (TARGET_DEBUG_F_MODE
1457 || type == DELAY_NONE
1461 || GET_CODE (next_insn) == CODE_LABEL
1462 || (set_reg = operands[0]) == 0)
1464 dslots_number_nops = 0;
1472 set_reg = operands[0];
1476 while (GET_CODE (set_reg) == SUBREG)
1477 set_reg = SUBREG_REG (set_reg);
1479 mode = GET_MODE (set_reg);
1480 dslots_number_nops = num_nops;
1481 mips_load_reg = set_reg;
1482 if (GET_MODE_SIZE (mode)
1483 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1484 mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
1488 if (type == DELAY_HILO)
1490 mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
1491 mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
1503 /* Determine whether a memory reference takes one (based off of the GP
1504 pointer), two (normal), or three (label + reg) instructions, and bump the
1505 appropriate counter for -mstats. */
1508 mips_count_memory_refs (op, num)
1514 rtx addr, plus0, plus1;
1515 enum rtx_code code0, code1;
1518 if (TARGET_DEBUG_B_MODE)
1520 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1524 /* Skip MEM if passed, otherwise handle movsi of address. */
1525 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1527 /* Loop, going through the address RTL. */
1531 switch (GET_CODE (addr))
1539 plus0 = XEXP (addr, 0);
1540 plus1 = XEXP (addr, 1);
1541 code0 = GET_CODE (plus0);
1542 code1 = GET_CODE (plus1);
1552 if (code0 == CONST_INT)
1567 if (code1 == CONST_INT)
1574 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1581 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1591 n_words = 2; /* always 2 words */
1595 addr = XEXP (addr, 0);
1600 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1612 n_words += additional;
1616 num_refs[n_words-1] += num;
1620 /* Return RTL for the offset from the current function to the argument.
1622 ??? Which argument is this? */
1625 embedded_pic_offset (x)
1628 if (embedded_pic_fnaddr_rtx == NULL)
1632 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1634 /* Output code at function start to initialize the pseudo-reg. */
1635 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1636 inline functions, because it is called after RTL for the function
1637 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1638 does not get copied, and ends up not matching the rest of the RTL.
1639 This solution works, but means that we get unnecessary code to
1640 initialize this value every time a function is inlined into another
1643 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1644 XEXP (DECL_RTL (current_function_decl), 0)));
1645 seq = gen_sequence ();
1647 push_topmost_sequence ();
1648 emit_insn_after (seq, get_insns ());
1649 pop_topmost_sequence ();
1652 return gen_rtx (CONST, Pmode,
1653 gen_rtx (MINUS, Pmode, x,
1654 XEXP (DECL_RTL (current_function_decl), 0)));
1657 /* Return the appropriate instructions to move one operand to another. */
1660 mips_move_1word (operands, insn, unsignedp)
1665 const char *ret = 0;
1666 rtx op0 = operands[0];
1667 rtx op1 = operands[1];
1668 enum rtx_code code0 = GET_CODE (op0);
1669 enum rtx_code code1 = GET_CODE (op1);
1670 enum machine_mode mode = GET_MODE (op0);
1671 int subreg_word0 = 0;
1672 int subreg_word1 = 0;
1673 enum delay_type delay = DELAY_NONE;
1675 while (code0 == SUBREG)
1677 subreg_word0 += SUBREG_WORD (op0);
1678 op0 = SUBREG_REG (op0);
1679 code0 = GET_CODE (op0);
1682 while (code1 == SUBREG)
1684 subreg_word1 += SUBREG_WORD (op1);
1685 op1 = SUBREG_REG (op1);
1686 code1 = GET_CODE (op1);
1689 /* For our purposes, a condition code mode is the same as SImode. */
1695 int regno0 = REGNO (op0) + subreg_word0;
1699 int regno1 = REGNO (op1) + subreg_word1;
1701 /* Just in case, don't do anything for assigning a register
1702 to itself, unless we are filling a delay slot. */
1703 if (regno0 == regno1 && set_nomacro == 0)
1706 else if (GP_REG_P (regno0))
1708 if (GP_REG_P (regno1))
1709 ret = "move\t%0,%1";
1711 else if (MD_REG_P (regno1))
1714 if (regno1 != HILO_REGNUM)
1720 else if (ST_REG_P (regno1) && mips_isa >= 4)
1721 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1726 if (FP_REG_P (regno1))
1727 ret = "mfc1\t%0,%1";
1729 else if (regno1 == FPSW_REGNUM && mips_isa < 4)
1730 ret = "cfc1\t%0,$31";
1734 else if (FP_REG_P (regno0))
1736 if (GP_REG_P (regno1))
1739 ret = "mtc1\t%1,%0";
1742 if (FP_REG_P (regno1))
1743 ret = "mov.s\t%0,%1";
1746 else if (MD_REG_P (regno0))
1748 if (GP_REG_P (regno1))
1751 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1756 else if (regno0 == FPSW_REGNUM && mips_isa < 4)
1758 if (GP_REG_P (regno1))
1761 ret = "ctc1\t%0,$31";
1766 else if (code1 == MEM)
1771 mips_count_memory_refs (op1, 1);
1773 if (GP_REG_P (regno0))
1775 /* For loads, use the mode of the memory item, instead of the
1776 target, so zero/sign extend can use this code as well. */
1777 switch (GET_MODE (op1))
1786 ret = ((unsignedp && TARGET_64BIT)
1791 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1794 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1799 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1802 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1804 size_t i = strlen (ret);
1805 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1808 sprintf (volatile_buffer, "%%{%s%%}", ret);
1809 ret = volatile_buffer;
1813 else if (code1 == CONST_INT
1814 || (code1 == CONST_DOUBLE
1815 && GET_MODE (op1) == VOIDmode))
1817 if (code1 == CONST_DOUBLE)
1819 /* This can happen when storing constants into long long
1820 bitfields. Just store the least significant word of
1822 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1825 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
1827 if (GP_REG_P (regno0))
1828 ret = "move\t%0,%z1";
1830 else if (FP_REG_P (regno0))
1833 ret = "mtc1\t%z1,%0";
1836 else if (MD_REG_P (regno0))
1843 else if (GP_REG_P (regno0))
1845 /* Don't use X format, because that will give out of
1846 range numbers for 64 bit host and 32 bit target. */
1847 if (! TARGET_MIPS16)
1848 ret = "li\t%0,%1\t\t\t# %X1";
1851 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
1853 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
1854 ret = "li\t%0,%n1\n\tneg\t%0";
1859 else if (code1 == CONST_DOUBLE && mode == SFmode)
1861 if (op1 == CONST0_RTX (SFmode))
1863 if (GP_REG_P (regno0))
1864 ret = "move\t%0,%.";
1866 else if (FP_REG_P (regno0))
1869 ret = "mtc1\t%.,%0";
1876 ret = "li.s\t%0,%1";
1880 else if (code1 == LABEL_REF)
1883 mips_count_memory_refs (op1, 1);
1888 else if (code1 == SYMBOL_REF || code1 == CONST)
1890 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
1892 rtx offset = const0_rtx;
1894 if (GET_CODE (op1) == CONST)
1895 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1897 if (GET_CODE (op1) == SYMBOL_REF)
1899 operands[2] = HALF_PIC_PTR (op1);
1902 mips_count_memory_refs (operands[2], 1);
1904 if (INTVAL (offset) == 0)
1907 ret = (unsignedp && TARGET_64BIT
1913 dslots_load_total++;
1914 operands[3] = offset;
1915 if (unsignedp && TARGET_64BIT)
1916 ret = (SMALL_INT (offset)
1917 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1918 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1920 ret = (SMALL_INT (offset)
1921 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1922 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1926 else if (TARGET_MIPS16
1928 && GET_CODE (XEXP (op1, 0)) == REG
1929 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
1931 /* This case arises on the mips16; see
1932 mips16_gp_pseudo_reg. */
1933 ret = "move\t%0,%+";
1935 else if (TARGET_MIPS16
1936 && code1 == SYMBOL_REF
1937 && SYMBOL_REF_FLAG (op1)
1938 && (XSTR (op1, 0)[0] != '*'
1939 || strncmp (XSTR (op1, 0) + 1,
1941 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
1943 /* This can occur when reloading the address of a GP
1944 relative symbol on the mips16. */
1945 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
1950 mips_count_memory_refs (op1, 1);
1956 else if (code1 == PLUS)
1958 rtx add_op0 = XEXP (op1, 0);
1959 rtx add_op1 = XEXP (op1, 1);
1961 if (GET_CODE (XEXP (op1, 1)) == REG
1962 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1963 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
1965 operands[2] = add_op0;
1966 operands[3] = add_op1;
1967 ret = "add%:\t%0,%2,%3";
1970 else if (code1 == HIGH)
1972 operands[1] = XEXP (op1, 0);
1973 ret = "lui\t%0,%%hi(%1)";
1977 else if (code0 == MEM)
1980 mips_count_memory_refs (op0, 1);
1984 int regno1 = REGNO (op1) + subreg_word1;
1986 if (GP_REG_P (regno1))
1990 case SFmode: ret = "sw\t%1,%0"; break;
1991 case SImode: ret = "sw\t%1,%0"; break;
1992 case HImode: ret = "sh\t%1,%0"; break;
1993 case QImode: ret = "sb\t%1,%0"; break;
1998 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2002 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2006 case SFmode: ret = "sw\t%z1,%0"; break;
2007 case SImode: ret = "sw\t%z1,%0"; break;
2008 case HImode: ret = "sh\t%z1,%0"; break;
2009 case QImode: ret = "sb\t%z1,%0"; break;
2014 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2018 case SFmode: ret = "sw\t%.,%0"; break;
2019 case SImode: ret = "sw\t%.,%0"; break;
2020 case HImode: ret = "sh\t%.,%0"; break;
2021 case QImode: ret = "sb\t%.,%0"; break;
2026 if (ret != 0 && MEM_VOLATILE_P (op0))
2028 size_t i = strlen (ret);
2030 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2033 sprintf (volatile_buffer, "%%{%s%%}", ret);
2034 ret = volatile_buffer;
2040 abort_with_insn (insn, "Bad move");
2044 if (delay != DELAY_NONE)
2045 return mips_fill_delay_slot (ret, delay, operands, insn);
2051 /* Return the appropriate instructions to move 2 words */
2054 mips_move_2words (operands, insn)
2058 const char *ret = 0;
2059 rtx op0 = operands[0];
2060 rtx op1 = operands[1];
2061 enum rtx_code code0 = GET_CODE (operands[0]);
2062 enum rtx_code code1 = GET_CODE (operands[1]);
2063 int subreg_word0 = 0;
2064 int subreg_word1 = 0;
2065 enum delay_type delay = DELAY_NONE;
2067 while (code0 == SUBREG)
2069 subreg_word0 += SUBREG_WORD (op0);
2070 op0 = SUBREG_REG (op0);
2071 code0 = GET_CODE (op0);
2074 if (code1 == SIGN_EXTEND)
2076 op1 = XEXP (op1, 0);
2077 code1 = GET_CODE (op1);
2080 while (code1 == SUBREG)
2082 subreg_word1 += SUBREG_WORD (op1);
2083 op1 = SUBREG_REG (op1);
2084 code1 = GET_CODE (op1);
2088 if (GET_CODE (operands[1]) == SIGN_EXTEND
2090 && code1 != CONST_INT
2091 /* The following three can happen as the result of a questionable
2093 && code1 != LABEL_REF
2094 && code1 != SYMBOL_REF
2100 int regno0 = REGNO (op0) + subreg_word0;
2104 int regno1 = REGNO (op1) + subreg_word1;
2106 /* Just in case, don't do anything for assigning a register
2107 to itself, unless we are filling a delay slot. */
2108 if (regno0 == regno1 && set_nomacro == 0)
2111 else if (FP_REG_P (regno0))
2113 if (FP_REG_P (regno1))
2114 ret = "mov.d\t%0,%1";
2122 abort_with_insn (insn, "Bad move");
2124 #ifdef TARGET_FP_CALL_32
2125 if (FP_CALL_GP_REG_P (regno1))
2126 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2129 ret = "dmtc1\t%1,%0";
2132 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2136 else if (FP_REG_P (regno1))
2142 abort_with_insn (insn, "Bad move");
2144 #ifdef TARGET_FP_CALL_32
2145 if (FP_CALL_GP_REG_P (regno0))
2146 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2149 ret = "dmfc1\t%0,%1";
2152 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2155 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2160 if (regno0 != HILO_REGNUM)
2162 else if (regno1 == 0)
2163 ret = "mtlo\t%.\n\tmthi\t%.";
2166 ret = "mthi\t%M1\n\tmtlo\t%L1";
2169 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2174 if (regno1 != HILO_REGNUM)
2178 ret = "mfhi\t%M0\n\tmflo\t%L0";
2181 else if (TARGET_64BIT)
2182 ret = "move\t%0,%1";
2184 else if (regno0 != (regno1+1))
2185 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2188 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2191 else if (code1 == CONST_DOUBLE)
2193 /* Move zero from $0 unless !TARGET_64BIT and recipient
2194 is 64-bit fp reg, in which case generate a constant. */
2195 if (op1 != CONST0_RTX (GET_MODE (op1))
2196 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2198 if (GET_MODE (op1) == DFmode)
2202 #ifdef TARGET_FP_CALL_32
2203 if (FP_CALL_GP_REG_P (regno0))
2205 if (TARGET_FLOAT64 && !TARGET_64BIT)
2207 split_double (op1, operands + 2, operands + 3);
2208 ret = "li\t%0,%2\n\tli\t%D0,%3";
2211 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2215 ret = "li.d\t%0,%1";
2218 else if (TARGET_64BIT)
2220 if (! TARGET_MIPS16)
2226 split_double (op1, operands + 2, operands + 3);
2227 ret = "li\t%0,%2\n\tli\t%D0,%3";
2233 if (GP_REG_P (regno0))
2235 #ifdef TARGET_FP_CALL_32
2236 && ! FP_CALL_GP_REG_P (regno0)
2239 : "move\t%0,%.\n\tmove\t%D0,%.");
2241 else if (FP_REG_P (regno0))
2246 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2251 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2253 if (GP_REG_P (regno0))
2256 : "move\t%0,%.\n\tmove\t%D0,%.");
2258 else if (FP_REG_P (regno0))
2265 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2267 else if (MD_REG_P (regno0))
2270 ret = (regno0 == HILO_REGNUM
2271 ? "mtlo\t%.\n\tmthi\t%."
2276 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2277 && GP_REG_P (regno0))
2283 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2285 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2286 ret = "li\t%0,%n1\n\tneg\t%0";
2288 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2289 ret = "li\t%0,%1\t\t# %X1";
2290 else if (HOST_BITS_PER_WIDE_INT < 64)
2291 /* We can't use 'X' for negative numbers, because then we won't
2292 get the right value for the upper 32 bits. */
2293 ret = (INTVAL (op1) < 0
2294 ? "dli\t%0,%1\t\t\t# %X1"
2295 : "dli\t%0,%X1\t\t# %1");
2297 /* We must use 'X', because otherwise LONG_MIN will print as
2298 a number that the assembler won't accept. */
2299 ret = "dli\t%0,%X1\t\t# %1";
2301 else if (HOST_BITS_PER_WIDE_INT < 64)
2303 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2306 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2307 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2308 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2310 operands[2] = GEN_INT (1);
2311 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2315 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2319 /* We use multiple shifts here, to avoid warnings about out
2320 of range shifts on 32 bit hosts. */
2321 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2323 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2324 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2328 else if (code1 == MEM)
2333 mips_count_memory_refs (op1, 2);
2335 if (FP_REG_P (regno0))
2338 else if (TARGET_64BIT)
2341 #ifdef TARGET_FP_CALL_32
2342 if (FP_CALL_GP_REG_P (regno0))
2343 ret = (double_memory_operand (op1, GET_MODE (op1))
2344 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2345 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2351 else if (double_memory_operand (op1, GET_MODE (op1)))
2353 operands[2] = adj_offsettable_operand (op1, 4);
2354 ret = (reg_mentioned_p (op0, op1)
2355 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2356 : "lw\t%0,%1\n\tlw\t%D0,%2");
2359 if (ret != 0 && MEM_VOLATILE_P (op1))
2361 size_t i = strlen (ret);
2363 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2366 sprintf (volatile_buffer, "%%{%s%%}", ret);
2367 ret = volatile_buffer;
2371 else if (code1 == LABEL_REF)
2374 mips_count_memory_refs (op1, 2);
2376 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2377 /* We deliberately remove the 'a' from '%1', so that we don't
2378 have to add SIGN_EXTEND support to print_operand_address.
2379 print_operand will just call print_operand_address in this
2380 case, so there is no problem. */
2383 ret = "dla\t%0,%a1";
2385 else if (code1 == SYMBOL_REF || code1 == CONST)
2389 && GET_CODE (XEXP (op1, 0)) == REG
2390 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2392 /* This case arises on the mips16; see
2393 mips16_gp_pseudo_reg. */
2394 ret = "move\t%0,%+";
2396 else if (TARGET_MIPS16
2397 && code1 == SYMBOL_REF
2398 && SYMBOL_REF_FLAG (op1)
2399 && (XSTR (op1, 0)[0] != '*'
2400 || strncmp (XSTR (op1, 0) + 1,
2402 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2404 /* This can occur when reloading the address of a GP
2405 relative symbol on the mips16. */
2406 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2411 mips_count_memory_refs (op1, 2);
2413 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2414 /* We deliberately remove the 'a' from '%1', so that we don't
2415 have to add SIGN_EXTEND support to print_operand_address.
2416 print_operand will just call print_operand_address in this
2417 case, so there is no problem. */
2420 ret = "dla\t%0,%a1";
2425 else if (code0 == MEM)
2429 int regno1 = REGNO (op1) + subreg_word1;
2431 if (FP_REG_P (regno1))
2434 else if (TARGET_64BIT)
2437 #ifdef TARGET_FP_CALL_32
2438 if (FP_CALL_GP_REG_P (regno1))
2439 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2445 else if (double_memory_operand (op0, GET_MODE (op0)))
2447 operands[2] = adj_offsettable_operand (op0, 4);
2448 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2452 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2453 || (code1 == CONST_DOUBLE
2454 && op1 == CONST0_RTX (GET_MODE (op1))))
2456 || double_memory_operand (op0, GET_MODE (op0))))
2462 operands[2] = adj_offsettable_operand (op0, 4);
2463 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2468 mips_count_memory_refs (op0, 2);
2470 if (ret != 0 && MEM_VOLATILE_P (op0))
2472 size_t i = strlen (ret);
2474 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2477 sprintf (volatile_buffer, "%%{%s%%}", ret);
2478 ret = volatile_buffer;
2484 abort_with_insn (insn, "Bad move");
2488 if (delay != DELAY_NONE)
2489 return mips_fill_delay_slot (ret, delay, operands, insn);
2494 /* Provide the costs of an addressing mode that contains ADDR.
2495 If ADDR is not a valid address, its cost is irrelevant. */
2498 mips_address_cost (addr)
2501 switch (GET_CODE (addr))
2511 rtx offset = const0_rtx;
2512 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2513 if (GET_CODE (addr) == LABEL_REF)
2516 if (GET_CODE (addr) != SYMBOL_REF)
2519 if (! SMALL_INT (offset))
2523 /* ... fall through ... */
2526 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2530 register rtx plus0 = XEXP (addr, 0);
2531 register rtx plus1 = XEXP (addr, 1);
2533 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2534 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2536 if (GET_CODE (plus0) != REG)
2539 switch (GET_CODE (plus1))
2542 return SMALL_INT (plus1) ? 1 : 2;
2549 return mips_address_cost (plus1) + 1;
2563 /* Return nonzero if X is an address which needs a temporary register when
2564 reloaded while generating PIC code. */
2567 pic_address_needs_scratch (x)
2570 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2571 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2572 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2573 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2574 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2580 /* Make normal rtx_code into something we can index from an array */
2582 static enum internal_test
2583 map_test_to_internal_test (test_code)
2584 enum rtx_code test_code;
2586 enum internal_test test = ITEST_MAX;
2590 case EQ: test = ITEST_EQ; break;
2591 case NE: test = ITEST_NE; break;
2592 case GT: test = ITEST_GT; break;
2593 case GE: test = ITEST_GE; break;
2594 case LT: test = ITEST_LT; break;
2595 case LE: test = ITEST_LE; break;
2596 case GTU: test = ITEST_GTU; break;
2597 case GEU: test = ITEST_GEU; break;
2598 case LTU: test = ITEST_LTU; break;
2599 case LEU: test = ITEST_LEU; break;
2607 /* Generate the code to compare two integer values. The return value is:
2608 (reg:SI xx) The pseudo register the comparison is in
2609 0 No register, generate a simple branch.
2611 ??? This is called with result nonzero by the Scond patterns in
2612 mips.md. These patterns are called with a target in the mode of
2613 the Scond instruction pattern. Since this must be a constant, we
2614 must use SImode. This means that if RESULT is non-zero, it will
2615 always be an SImode register, even if TARGET_64BIT is true. We
2616 cope with this by calling convert_move rather than emit_move_insn.
2617 This will sometimes lead to an unnecessary extension of the result;
2629 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2630 enum rtx_code test_code; /* relational test (EQ, etc) */
2631 rtx result; /* result to store comp. or 0 if branch */
2632 rtx cmp0; /* first operand to compare */
2633 rtx cmp1; /* second operand to compare */
2634 int *p_invert; /* NULL or ptr to hold whether branch needs */
2635 /* to reverse its test */
2639 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2640 int const_low; /* low bound of constant we can accept */
2641 int const_high; /* high bound of constant we can accept */
2642 int const_add; /* constant to add (convert LE -> LT) */
2643 int reverse_regs; /* reverse registers in test */
2644 int invert_const; /* != 0 if invert value if cmp1 is constant */
2645 int invert_reg; /* != 0 if invert value if cmp1 is register */
2646 int unsignedp; /* != 0 for unsigned comparisons. */
2649 static struct cmp_info info[ (int)ITEST_MAX ] = {
2651 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2652 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2653 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2654 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2655 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2656 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2657 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2658 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2659 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2660 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2663 enum internal_test test;
2664 enum machine_mode mode;
2665 struct cmp_info *p_info;
2672 test = map_test_to_internal_test (test_code);
2673 if (test == ITEST_MAX)
2676 p_info = &info[(int) test];
2677 eqne_p = (p_info->test_code == XOR);
2679 mode = GET_MODE (cmp0);
2680 if (mode == VOIDmode)
2681 mode = GET_MODE (cmp1);
2683 /* Eliminate simple branches */
2684 branch_p = (result == 0);
2687 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2689 /* Comparisons against zero are simple branches */
2690 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2691 && (! TARGET_MIPS16 || eqne_p))
2694 /* Test for beq/bne. */
2695 if (eqne_p && ! TARGET_MIPS16)
2699 /* allocate a pseudo to calculate the value in. */
2700 result = gen_reg_rtx (mode);
2703 /* Make sure we can handle any constants given to us. */
2704 if (GET_CODE (cmp0) == CONST_INT)
2705 cmp0 = force_reg (mode, cmp0);
2707 if (GET_CODE (cmp1) == CONST_INT)
2709 HOST_WIDE_INT value = INTVAL (cmp1);
2711 if (value < p_info->const_low
2712 || value > p_info->const_high
2713 /* ??? Why? And why wasn't the similar code below modified too? */
2715 && HOST_BITS_PER_WIDE_INT < 64
2716 && p_info->const_add != 0
2717 && ((p_info->unsignedp
2718 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2719 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2720 : (value + p_info->const_add) > INTVAL (cmp1))
2721 != (p_info->const_add > 0))))
2722 cmp1 = force_reg (mode, cmp1);
2725 /* See if we need to invert the result. */
2726 invert = (GET_CODE (cmp1) == CONST_INT
2727 ? p_info->invert_const : p_info->invert_reg);
2729 if (p_invert != (int *)0)
2735 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2736 Comparison between two registers, may involve switching operands. */
2737 if (GET_CODE (cmp1) == CONST_INT)
2739 if (p_info->const_add != 0)
2741 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2743 /* If modification of cmp1 caused overflow,
2744 we would get the wrong answer if we follow the usual path;
2745 thus, x > 0xffffffffU would turn into x > 0U. */
2746 if ((p_info->unsignedp
2747 ? (unsigned HOST_WIDE_INT) new >
2748 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2749 : new > INTVAL (cmp1))
2750 != (p_info->const_add > 0))
2752 /* This test is always true, but if INVERT is true then
2753 the result of the test needs to be inverted so 0 should
2754 be returned instead. */
2755 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2759 cmp1 = GEN_INT (new);
2763 else if (p_info->reverse_regs)
2770 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2774 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2775 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2778 if (test == ITEST_NE)
2780 if (! TARGET_MIPS16)
2782 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2787 reg2 = invert ? gen_reg_rtx (mode) : result;
2788 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2793 else if (test == ITEST_EQ)
2795 reg2 = invert ? gen_reg_rtx (mode) : result;
2796 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2804 if (! TARGET_MIPS16)
2808 /* The value is in $24. Copy it to another register, so
2809 that reload doesn't think it needs to store the $24 and
2810 the input to the XOR in the same location. */
2811 reg2 = gen_reg_rtx (mode);
2812 emit_move_insn (reg2, reg);
2814 one = force_reg (mode, const1_rtx);
2816 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
2822 /* Emit the common code for doing conditional branches.
2823 operand[0] is the label to jump to.
2824 The comparison operands are saved away by cmp{si,di,sf,df}. */
2827 gen_conditional_branch (operands, test_code)
2829 enum rtx_code test_code;
2831 enum cmp_type type = branch_type;
2832 rtx cmp0 = branch_cmp[0];
2833 rtx cmp1 = branch_cmp[1];
2834 enum machine_mode mode;
2843 mode = type == CMP_SI ? SImode : DImode;
2845 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
2853 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
2854 /* We don't want to build a comparison against a non-zero
2856 cmp1 = force_reg (mode, cmp1);
2863 reg = gen_rtx (REG, CCmode, FPSW_REGNUM);
2865 reg = gen_reg_rtx (CCmode);
2867 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2868 0 in the instruction built below. The MIPS FPU handles
2869 inequality testing by testing for equality and looking for a
2871 emit_insn (gen_rtx (SET, VOIDmode, reg,
2872 gen_rtx (test_code == NE ? EQ : test_code,
2873 CCmode, cmp0, cmp1)));
2875 test_code = test_code == NE ? EQ : NE;
2883 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
2886 /* Generate the branch. */
2888 label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
2897 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2898 gen_rtx (IF_THEN_ELSE, VOIDmode,
2899 gen_rtx (test_code, mode, cmp0, cmp1),
2903 /* Emit the common code for conditional moves. OPERANDS is the array
2904 of operands passed to the conditional move defined_expand. */
2907 gen_conditional_move (operands)
2910 rtx op0 = branch_cmp[0];
2911 rtx op1 = branch_cmp[1];
2912 enum machine_mode mode = GET_MODE (branch_cmp[0]);
2913 enum rtx_code cmp_code = GET_CODE (operands[1]);
2914 enum rtx_code move_code = NE;
2915 enum machine_mode op_mode = GET_MODE (operands[0]);
2916 enum machine_mode cmp_mode;
2919 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
2938 op0 = force_reg (mode, branch_cmp[1]);
2939 op1 = branch_cmp[0];
2943 op0 = force_reg (mode, branch_cmp[1]);
2944 op1 = branch_cmp[0];
2955 op0 = force_reg (mode, branch_cmp[1]);
2956 op1 = branch_cmp[0];
2960 op0 = force_reg (mode, branch_cmp[1]);
2961 op1 = branch_cmp[0];
2968 else if (cmp_code == NE)
2969 cmp_code = EQ, move_code = EQ;
2971 if (mode == SImode || mode == DImode)
2973 else if (mode == SFmode || mode == DFmode)
2978 cmp_reg = gen_reg_rtx (cmp_mode);
2979 emit_insn (gen_rtx (SET, cmp_mode, cmp_reg,
2980 gen_rtx (cmp_code, cmp_mode, op0, op1)));
2982 emit_insn (gen_rtx (SET, op_mode, operands[0],
2983 gen_rtx (IF_THEN_ELSE, op_mode,
2984 gen_rtx (move_code, VOIDmode,
2985 cmp_reg, CONST0_RTX (SImode)),
2986 operands[2], operands[3])));
2989 /* Write a loop to move a constant number of bytes.
2990 Generate load/stores as follows:
2996 temp<last> = src[MAX_MOVE_REGS-1];
3000 dest[MAX_MOVE_REGS-1] = temp<last>;
3001 src += MAX_MOVE_REGS;
3002 dest += MAX_MOVE_REGS;
3003 } while (src != final);
3005 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3006 registers are needed.
3008 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3009 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3010 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3012 #define MAX_MOVE_REGS 4
3013 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3016 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3017 rtx dest_reg; /* register holding destination address */
3018 rtx src_reg; /* register holding source address */
3019 int bytes; /* # bytes to move */
3020 int align; /* alignment */
3021 rtx orig_dest; /* original dest for change_address */
3022 rtx orig_src; /* original source for making a reg note */
3024 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
3025 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
3026 rtx align_rtx = GEN_INT (align);
3032 if (bytes < 2 * MAX_MOVE_BYTES)
3035 leftover = bytes % MAX_MOVE_BYTES;
3038 label = gen_label_rtx ();
3039 final_src = gen_reg_rtx (Pmode);
3040 bytes_rtx = GEN_INT (bytes);
3044 if (Pmode == DImode)
3046 emit_insn (gen_movdi (final_src, bytes_rtx));
3047 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3051 emit_insn (gen_movsi (final_src, bytes_rtx));
3052 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3057 if (Pmode == DImode)
3058 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3060 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3065 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3066 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3068 if (Pmode == DImode)
3070 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3071 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3072 emit_insn (gen_cmpdi (src_reg, final_src));
3076 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3077 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3078 emit_insn (gen_cmpsi (src_reg, final_src));
3081 emit_jump_insn (gen_bne (label));
3084 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3088 /* Use a library function to move some bytes. */
3091 block_move_call (dest_reg, src_reg, bytes_rtx)
3096 /* We want to pass the size as Pmode, which will normally be SImode
3097 but will be DImode if we are using 64 bit longs and pointers. */
3098 if (GET_MODE (bytes_rtx) != VOIDmode
3099 && GET_MODE (bytes_rtx) != Pmode)
3100 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3102 #ifdef TARGET_MEM_FUNCTIONS
3103 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
3104 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3105 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3106 TREE_UNSIGNED (sizetype)),
3107 TYPE_MODE (sizetype));
3109 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
3110 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3111 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3112 TREE_UNSIGNED (integer_type_node)),
3113 TYPE_MODE (integer_type_node));
3117 /* Expand string/block move operations.
3119 operands[0] is the pointer to the destination.
3120 operands[1] is the pointer to the source.
3121 operands[2] is the number of bytes to move.
3122 operands[3] is the alignment. */
3125 expand_block_move (operands)
3128 rtx bytes_rtx = operands[2];
3129 rtx align_rtx = operands[3];
3130 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3131 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3132 int align = INTVAL (align_rtx);
3133 rtx orig_src = operands[1];
3134 rtx orig_dest = operands[0];
3138 if (constp && bytes <= 0)
3141 if (align > UNITS_PER_WORD)
3142 align = UNITS_PER_WORD;
3144 /* Move the address into scratch registers. */
3145 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3146 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3149 block_move_call (dest_reg, src_reg, bytes_rtx);
3151 else if (constp && bytes <= 2 * MAX_MOVE_BYTES
3152 && align == UNITS_PER_WORD)
3153 move_by_pieces (orig_dest, orig_src, bytes, align);
3155 else if (constp && bytes <= 2 * MAX_MOVE_BYTES)
3156 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3158 change_address (orig_src, BLKmode,
3160 bytes_rtx, align_rtx));
3162 else if (constp && align >= UNITS_PER_WORD && optimize)
3163 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3165 else if (constp && optimize)
3167 /* If the alignment is not word aligned, generate a test at
3168 runtime, to see whether things wound up aligned, and we
3169 can use the faster lw/sw instead ulw/usw. */
3171 rtx temp = gen_reg_rtx (Pmode);
3172 rtx aligned_label = gen_label_rtx ();
3173 rtx join_label = gen_label_rtx ();
3174 int leftover = bytes % MAX_MOVE_BYTES;
3178 if (Pmode == DImode)
3180 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3181 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3182 emit_insn (gen_cmpdi (temp, const0_rtx));
3186 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3187 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3188 emit_insn (gen_cmpsi (temp, const0_rtx));
3191 emit_jump_insn (gen_beq (aligned_label));
3193 /* Unaligned loop. */
3194 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3195 emit_jump_insn (gen_jump (join_label));
3199 emit_label (aligned_label);
3200 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3202 emit_label (join_label);
3204 /* Bytes at the end of the loop. */
3206 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3208 change_address (orig_src, BLKmode,
3215 block_move_call (dest_reg, src_reg, bytes_rtx);
3218 /* Emit load/stores for a small constant block_move.
3220 operands[0] is the memory address of the destination.
3221 operands[1] is the memory address of the source.
3222 operands[2] is the number of bytes to move.
3223 operands[3] is the alignment.
3224 operands[4] is a temp register.
3225 operands[5] is a temp register.
3227 operands[3+num_regs] is the last temp register.
3229 The block move type can be one of the following:
3230 BLOCK_MOVE_NORMAL Do all of the block move.
3231 BLOCK_MOVE_NOT_LAST Do all but the last store.
3232 BLOCK_MOVE_LAST Do just the last store. */
3235 output_block_move (insn, operands, num_regs, move_type)
3239 enum block_move_type move_type;
3241 rtx dest_reg = XEXP (operands[0], 0);
3242 rtx src_reg = XEXP (operands[1], 0);
3243 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3244 int align = INTVAL (operands[3]);
3247 int use_lwl_lwr = 0;
3248 int last_operand = num_regs + 4;
3254 const char *load; /* load insn without nop */
3255 const char *load_nop; /* load insn with trailing nop */
3256 const char *store; /* store insn */
3257 const char *final; /* if last_store used: NULL or swr */
3258 const char *last_store; /* last store instruction */
3259 int offset; /* current offset */
3260 enum machine_mode mode; /* mode to use on (MEM) */
3263 /* ??? Detect a bug in GCC, where it can give us a register
3264 the same as one of the addressing registers and reduce
3265 the number of registers available. */
3268 && safe_regs < (int)(sizeof(xoperands) / sizeof(xoperands[0]));
3270 if (! reg_mentioned_p (operands[i], operands[0])
3271 && ! reg_mentioned_p (operands[i], operands[1]))
3272 xoperands[safe_regs++] = operands[i];
3274 if (safe_regs < last_operand)
3276 xoperands[0] = operands[0];
3277 xoperands[1] = operands[1];
3278 xoperands[2] = operands[2];
3279 xoperands[3] = operands[3];
3280 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3283 /* If we are given global or static addresses, and we would be
3284 emitting a few instructions, try to save time by using a
3285 temporary register for the pointer. */
3286 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3287 an ldl/ldr instruction pair. We play it safe, and always move
3288 constant addresses into registers when generating N32/N64 code, just
3289 in case we might emit an unaligned load instruction. */
3290 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3291 || mips_abi == ABI_N32 || mips_abi == ABI_64))
3293 if (CONSTANT_P (src_reg))
3296 mips_count_memory_refs (operands[1], 1);
3298 src_reg = operands[3 + num_regs--];
3299 if (move_type != BLOCK_MOVE_LAST)
3301 xoperands[1] = operands[1];
3302 xoperands[0] = src_reg;
3303 if (Pmode == DImode)
3304 output_asm_insn ("dla\t%0,%1", xoperands);
3306 output_asm_insn ("la\t%0,%1", xoperands);
3310 if (CONSTANT_P (dest_reg))
3313 mips_count_memory_refs (operands[0], 1);
3315 dest_reg = operands[3 + num_regs--];
3316 if (move_type != BLOCK_MOVE_LAST)
3318 xoperands[1] = operands[0];
3319 xoperands[0] = dest_reg;
3320 if (Pmode == DImode)
3321 output_asm_insn ("dla\t%0,%1", xoperands);
3323 output_asm_insn ("la\t%0,%1", xoperands);
3328 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3329 are not offsettable, however, offsettable_address_p says they are
3330 offsettable. I think this is a bug in offsettable_address_p.
3331 For expediency, we fix this by just loading the address into a register
3332 if we happen to get one. */
3334 if (GET_CODE (src_reg) == LO_SUM)
3336 src_reg = operands[3 + num_regs--];
3337 if (move_type != BLOCK_MOVE_LAST)
3339 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3340 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3341 xoperands[0] = src_reg;
3342 if (Pmode == DImode)
3343 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3345 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3349 if (GET_CODE (dest_reg) == LO_SUM)
3351 dest_reg = operands[3 + num_regs--];
3352 if (move_type != BLOCK_MOVE_LAST)
3354 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3355 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3356 xoperands[0] = dest_reg;
3357 if (Pmode == DImode)
3358 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3360 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3364 if (num_regs > (int)(sizeof (load_store) / sizeof (load_store[0])))
3365 num_regs = sizeof (load_store) / sizeof (load_store[0]);
3367 else if (num_regs < 1)
3368 abort_with_insn (insn,
3369 "Cannot do block move, not enough scratch registers");
3373 load_store[num].offset = offset;
3375 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3377 load_store[num].load = "ld\t%0,%1";
3378 load_store[num].load_nop = "ld\t%0,%1%#";
3379 load_store[num].store = "sd\t%0,%1";
3380 load_store[num].last_store = "sd\t%0,%1";
3381 load_store[num].final = 0;
3382 load_store[num].mode = DImode;
3387 /* ??? Fails because of a MIPS assembler bug? */
3388 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3390 if (BYTES_BIG_ENDIAN)
3392 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3393 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3394 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3395 load_store[num].last_store = "sdr\t%0,%2";
3396 load_store[num].final = "sdl\t%0,%1";
3400 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3401 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3402 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3403 load_store[num].last_store = "sdr\t%0,%1";
3404 load_store[num].final = "sdl\t%0,%2";
3407 load_store[num].mode = DImode;
3413 else if (bytes >= 4 && align >= 4)
3415 load_store[num].load = "lw\t%0,%1";
3416 load_store[num].load_nop = "lw\t%0,%1%#";
3417 load_store[num].store = "sw\t%0,%1";
3418 load_store[num].last_store = "sw\t%0,%1";
3419 load_store[num].final = 0;
3420 load_store[num].mode = SImode;
3425 else if (bytes >= 4 && ! TARGET_MIPS16)
3427 if (BYTES_BIG_ENDIAN)
3429 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3430 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3431 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3432 load_store[num].last_store = "swr\t%0,%2";
3433 load_store[num].final = "swl\t%0,%1";
3437 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3438 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3439 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3440 load_store[num].last_store = "swr\t%0,%1";
3441 load_store[num].final = "swl\t%0,%2";
3444 load_store[num].mode = SImode;
3450 else if (bytes >= 2 && align >= 2)
3452 load_store[num].load = "lh\t%0,%1";
3453 load_store[num].load_nop = "lh\t%0,%1%#";
3454 load_store[num].store = "sh\t%0,%1";
3455 load_store[num].last_store = "sh\t%0,%1";
3456 load_store[num].final = 0;
3457 load_store[num].mode = HImode;
3463 load_store[num].load = "lb\t%0,%1";
3464 load_store[num].load_nop = "lb\t%0,%1%#";
3465 load_store[num].store = "sb\t%0,%1";
3466 load_store[num].last_store = "sb\t%0,%1";
3467 load_store[num].final = 0;
3468 load_store[num].mode = QImode;
3473 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3475 dslots_load_total++;
3476 dslots_load_filled++;
3478 if (CONSTANT_P (src_reg))
3479 mips_count_memory_refs (src_reg, 1);
3481 if (CONSTANT_P (dest_reg))
3482 mips_count_memory_refs (dest_reg, 1);
3485 /* Emit load/stores now if we have run out of registers or are
3486 at the end of the move. */
3488 if (++num == num_regs || bytes == 0)
3490 /* If only load/store, we need a NOP after the load. */
3493 load_store[0].load = load_store[0].load_nop;
3494 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3495 dslots_load_filled--;
3498 if (move_type != BLOCK_MOVE_LAST)
3500 for (i = 0; i < num; i++)
3504 if (!operands[i + 4])
3507 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3508 operands[i + 4] = gen_rtx (REG, load_store[i].mode,
3509 REGNO (operands[i + 4]));
3511 offset = load_store[i].offset;
3512 xoperands[0] = operands[i + 4];
3513 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
3514 plus_constant (src_reg, offset));
3519 = GET_MODE_SIZE (load_store[i].mode) - 1;
3521 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
3522 plus_constant (src_reg,
3527 output_asm_insn (load_store[i].load, xoperands);
3531 for (i = 0; i < num; i++)
3533 int last_p = (i == num-1 && bytes == 0);
3534 int offset = load_store[i].offset;
3536 xoperands[0] = operands[i + 4];
3537 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
3538 plus_constant (dest_reg, offset));
3543 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3544 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
3545 plus_constant (dest_reg,
3550 if (move_type == BLOCK_MOVE_NORMAL)
3551 output_asm_insn (load_store[i].store, xoperands);
3553 else if (move_type == BLOCK_MOVE_NOT_LAST)
3556 output_asm_insn (load_store[i].store, xoperands);
3558 else if (load_store[i].final != 0)
3559 output_asm_insn (load_store[i].final, xoperands);
3563 output_asm_insn (load_store[i].last_store, xoperands);
3566 num = 0; /* reset load_store */
3574 /* Argument support functions. */
3576 /* Initialize CUMULATIVE_ARGS for a function. */
3579 init_cumulative_args (cum, fntype, libname)
3580 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3581 tree fntype; /* tree ptr for function decl */
3582 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3584 static CUMULATIVE_ARGS zero_cum;
3585 tree param, next_param;
3587 if (TARGET_DEBUG_E_MODE)
3590 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3593 fputc ('\n', stderr);
3597 tree ret_type = TREE_TYPE (fntype);
3598 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3599 tree_code_name[(int)TREE_CODE (fntype)],
3600 tree_code_name[(int)TREE_CODE (ret_type)]);
3606 /* Determine if this function has variable arguments. This is
3607 indicated by the last argument being 'void_type_mode' if there
3608 are no variable arguments. The standard MIPS calling sequence
3609 passes all arguments in the general purpose registers in this case. */
3611 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3612 param != 0; param = next_param)
3614 next_param = TREE_CHAIN (param);
3615 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3616 cum->gp_reg_found = 1;
3620 /* Advance the argument to the next argument position. */
3623 function_arg_advance (cum, mode, type, named)
3624 CUMULATIVE_ARGS *cum; /* current arg information */
3625 enum machine_mode mode; /* current arg mode */
3626 tree type; /* type of the argument or 0 if lib support */
3627 int named; /* whether or not the argument was named */
3629 if (TARGET_DEBUG_E_MODE)
3632 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3633 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3634 GET_MODE_NAME (mode));
3635 fprintf (stderr, HOST_PTR_PRINTF, type);
3636 fprintf (stderr, ", %d )\n\n", named);
3646 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3647 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3650 cum->gp_reg_found = 1;
3651 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3656 cum->gp_reg_found = 1;
3657 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3662 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3663 cum->fp_arg_words++;
3666 if (! cum->gp_reg_found && cum->arg_number <= 2)
3667 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3671 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3672 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3674 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3675 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3676 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3680 cum->gp_reg_found = 1;
3681 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3687 cum->gp_reg_found = 1;
3693 /* Return an RTL expression containing the register for the given mode,
3694 or 0 if the argument is to be passed on the stack. */
3697 function_arg (cum, mode, type, named)
3698 CUMULATIVE_ARGS *cum; /* current arg information */
3699 enum machine_mode mode; /* current arg mode */
3700 tree type; /* type of the argument or 0 if lib support */
3701 int named; /* != 0 for normal args, == 0 for ... args */
3706 int *arg_words = &cum->arg_words;
3707 int struct_p = (type != 0
3708 && (TREE_CODE (type) == RECORD_TYPE
3709 || TREE_CODE (type) == UNION_TYPE
3710 || TREE_CODE (type) == QUAL_UNION_TYPE));
3712 if (TARGET_DEBUG_E_MODE)
3715 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3716 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3717 GET_MODE_NAME (mode));
3718 fprintf (stderr, HOST_PTR_PRINTF, type);
3719 fprintf (stderr, ", %d ) = ", named);
3723 cum->last_arg_fp = 0;
3727 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3729 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3730 regbase = GP_ARG_FIRST;
3733 regbase = FP_ARG_FIRST;
3735 /* If the first arg was a float in a floating point register,
3736 then set bias to align this float arg properly. */
3737 if (cum->arg_words == 1)
3741 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3744 cum->fp_arg_words += cum->fp_arg_words & 1;
3745 cum->last_arg_fp = 1;
3746 arg_words = &cum->fp_arg_words;
3747 regbase = FP_ARG_FIRST;
3750 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3756 if (mips_abi == ABI_EABI
3757 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3758 cum->fp_arg_words += cum->fp_arg_words & 1;
3760 cum->arg_words += cum->arg_words & 1;
3763 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3764 regbase = ((cum->gp_reg_found
3765 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
3766 || cum->arg_number >= 2)
3767 ? GP_ARG_FIRST : FP_ARG_FIRST);
3768 else if (mips_abi == ABI_EABI
3769 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3771 cum->last_arg_fp = 1;
3772 arg_words = &cum->fp_arg_words;
3773 regbase = FP_ARG_FIRST;
3776 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3777 ? GP_ARG_FIRST : FP_ARG_FIRST);
3781 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3782 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3785 /* Drops through. */
3787 if (type != (tree)0 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
3788 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3789 cum->arg_words += (cum->arg_words & 1);
3790 regbase = GP_ARG_FIRST;
3797 regbase = GP_ARG_FIRST;
3802 cum->arg_words += (cum->arg_words & 1);
3803 regbase = GP_ARG_FIRST;
3806 if (*arg_words >= MAX_ARGS_IN_REGISTERS)
3808 if (TARGET_DEBUG_E_MODE)
3809 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
3818 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
3819 || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named)
3820 ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
3823 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3824 structure contains a double in its entirety, then that 64 bit
3825 chunk is passed in a floating point register. */
3828 /* First check to see if there is any such field. */
3829 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3830 if (TREE_CODE (field) == FIELD_DECL
3831 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3832 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3833 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3834 % BITS_PER_WORD == 0))
3837 /* If the whole struct fits a DFmode register,
3838 we don't need the PARALLEL. */
3839 if (! field || mode == DFmode)
3840 ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
3843 /* Now handle the special case by returning a PARALLEL
3844 indicating where each 64 bit chunk goes. */
3850 /* ??? If this is a packed structure, then the last hunk won't
3853 chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
3854 if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
3855 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
3857 /* assign_parms checks the mode of ENTRY_PARM, so we must
3858 use the actual mode here. */
3859 ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks));
3862 regno = regbase + *arg_words + bias;
3863 field = TYPE_FIELDS (type);
3864 for (i = 0; i < chunks; i++)
3868 for (; field; field = TREE_CHAIN (field))
3869 if (TREE_CODE (field) == FIELD_DECL
3870 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3875 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
3876 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3877 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3878 reg = gen_rtx (REG, DFmode,
3879 regno + FP_ARG_FIRST - GP_ARG_FIRST);
3881 reg = gen_rtx (REG, word_mode, regno);
3884 = gen_rtx (EXPR_LIST, VOIDmode, reg,
3885 GEN_INT (bitpos / BITS_PER_UNIT));
3893 if (TARGET_DEBUG_E_MODE)
3894 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
3895 struct_p ? ", [struct]" : "");
3897 /* The following is a hack in order to pass 1 byte structures
3898 the same way that the MIPS compiler does (namely by passing
3899 the structure in the high byte or half word of the register).
3900 This also makes varargs work. If we have such a structure,
3901 we save the adjustment RTL, and the call define expands will
3902 emit them. For the VOIDmode argument (argument after the
3903 last real argument), pass back a parallel vector holding each
3904 of the adjustments. */
3906 /* ??? function_arg can be called more than once for each argument.
3907 As a result, we compute more adjustments than we need here.
3908 See the CUMULATIVE_ARGS definition in mips.h. */
3910 /* ??? This scheme requires everything smaller than the word size to
3911 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3912 that would mean every int needs to be shifted left, which is very
3913 inefficient. Let's not carry this compatibility to the 64 bit
3914 calling convention for now. */
3916 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
3917 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3919 rtx amount = GEN_INT (BITS_PER_WORD
3920 - int_size_in_bytes (type) * BITS_PER_UNIT);
3921 rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias);
3924 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
3926 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
3930 /* We will be called with a mode of VOIDmode after the last argument
3931 has been seen. Whatever we return will be passed to the call
3932 insn. If we need any shifts for small structures, return them in
3933 a PARALLEL; in that case, stuff the mips16 fp_code in as the
3934 mode. Otherwise, if we have need a mips16 fp_code, return a REG
3935 with the code stored as the mode. */
3936 if (mode == VOIDmode)
3938 if (cum->num_adjusts > 0)
3939 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
3940 gen_rtvec_v (cum->num_adjusts, cum->adjust));
3941 else if (TARGET_MIPS16 && cum->fp_code != 0)
3942 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
3949 function_arg_partial_nregs (cum, mode, type, named)
3950 CUMULATIVE_ARGS *cum; /* current arg information */
3951 enum machine_mode mode; /* current arg mode */
3952 tree type; /* type of the argument or 0 if lib support */
3953 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
3955 if ((mode == BLKmode
3956 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3957 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3958 && cum->arg_words < MAX_ARGS_IN_REGISTERS
3959 && mips_abi != ABI_EABI)
3962 if (mode == BLKmode)
3963 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3966 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3968 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
3969 return 0; /* structure fits in registers */
3971 if (TARGET_DEBUG_E_MODE)
3972 fprintf (stderr, "function_arg_partial_nregs = %d\n",
3973 MAX_ARGS_IN_REGISTERS - cum->arg_words);
3975 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
3978 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
3979 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3981 if (TARGET_DEBUG_E_MODE)
3982 fprintf (stderr, "function_arg_partial_nregs = 1\n");
3990 /* Abort after printing out a specific insn. */
3993 abort_with_insn (insn, reason)
4002 /* Write a message to stderr (for use in macros expanded in files that do not
4003 include stdio.h). */
4009 fprintf (stderr, s, s1, s2);
4012 /* Set up the threshold for data to go into the small data area, instead
4013 of the normal data area, and detect any conflicts in the switches. */
4018 register int i, start;
4020 register enum machine_mode mode;
4022 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4024 if (mips_section_threshold <= 0)
4025 target_flags &= ~MASK_GPOPT;
4027 target_flags |= MASK_GPOPT;
4029 #ifndef MIPS_ISA_DEFAULT
4030 #define MIPS_ISA_DEFAULT 1
4033 /* If both single-float and soft-float are set, then clear the one that
4034 was set by TARGET_DEFAULT, leaving the one that was set by the
4035 user. We assume here that the specs prevent both being set by the
4037 #ifdef TARGET_DEFAULT
4038 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4039 target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT));
4042 /* Get the architectural level. */
4043 if (mips_isa_string == 0)
4044 mips_isa = MIPS_ISA_DEFAULT;
4046 else if (ISDIGIT (*mips_isa_string))
4048 mips_isa = atoi (mips_isa_string);
4051 /* -mno-mips16 overrides -mips16. */
4052 if (mips_no_mips16_string == NULL)
4054 target_flags |= MASK_MIPS16;
4058 mips_isa = MIPS_ISA_DEFAULT;
4062 mips_isa = MIPS_ISA_DEFAULT;
4065 else if (mips_isa < 1 || mips_isa > 4)
4067 error ("-mips%d not supported", mips_isa);
4074 error ("bad value (%s) for -mips switch", mips_isa_string);
4078 #ifdef MIPS_ABI_DEFAULT
4079 /* Get the ABI to use. */
4080 if (mips_abi_string == (char *) 0)
4081 mips_abi = MIPS_ABI_DEFAULT;
4082 else if (! strcmp (mips_abi_string, "32"))
4084 else if (! strcmp (mips_abi_string, "o64"))
4086 else if (! strcmp (mips_abi_string, "n32"))
4088 else if (! strcmp (mips_abi_string, "64"))
4090 else if (! strcmp (mips_abi_string, "eabi"))
4091 mips_abi = ABI_EABI;
4093 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4095 /* A specified ISA defaults the ABI if it was not specified. */
4096 if (mips_abi_string == 0 && mips_isa_string
4097 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4105 /* A specified ABI defaults the ISA if it was not specified. */
4106 else if (mips_isa_string == 0 && mips_abi_string
4107 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4109 if (mips_abi == ABI_32)
4111 else if (mips_abi == ABI_N32)
4117 /* If both ABI and ISA were specified, check for conflicts. */
4118 else if (mips_isa_string && mips_abi_string)
4120 if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64
4121 || mips_abi == ABI_O64))
4122 || (mips_isa >= 3 && mips_abi == ABI_32))
4123 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4126 /* Override TARGET_DEFAULT if necessary. */
4127 if (mips_abi == ABI_32)
4128 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4130 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4131 then set the type sizes. In the EABI in 64 bit mode, longs and
4132 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4133 if (mips_explicit_type_size_string == NULL
4134 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4135 || mips_abi == ABI_64))
4136 target_flags |= MASK_LONG64;
4138 /* ??? This doesn't work yet, so don't let people try to use it. */
4139 if (mips_abi == ABI_32)
4140 error ("The -mabi=32 support does not work yet.");
4143 if (mips_abi_string)
4144 error ("This target does not support the -mabi switch.");
4147 #ifdef MIPS_CPU_STRING_DEFAULT
4148 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4149 greater than that supported by the default processor, then the user gets
4150 an error. Normally, the compiler will just default to the base level cpu
4151 for the indicated isa. */
4152 if (mips_cpu_string == 0)
4153 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4156 /* Identify the processor type */
4157 if (mips_cpu_string == 0
4158 || !strcmp (mips_cpu_string, "default")
4159 || !strcmp (mips_cpu_string, "DEFAULT"))
4164 mips_cpu_string = "3000";
4165 mips_cpu = PROCESSOR_R3000;
4168 mips_cpu_string = "6000";
4169 mips_cpu = PROCESSOR_R6000;
4172 mips_cpu_string = "4000";
4173 mips_cpu = PROCESSOR_R4000;
4176 mips_cpu_string = "8000";
4177 mips_cpu = PROCESSOR_R8000;
4184 const char *p = mips_cpu_string;
4187 /* We need to cope with the various "vr" prefixes for the NEC 4300
4188 and 4100 processors. */
4189 if (*p == 'v' || *p == 'V')
4192 if (*p == 'r' || *p == 'R')
4195 /* Since there is no difference between a R2000 and R3000 in
4196 terms of the scheduler, we collapse them into just an R3000. */
4198 mips_cpu = PROCESSOR_DEFAULT;
4202 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4203 mips_cpu = PROCESSOR_R3000;
4207 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4208 mips_cpu = PROCESSOR_R3000;
4209 else if (!strcmp (p, "3900"))
4210 mips_cpu = PROCESSOR_R3900;
4214 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4215 mips_cpu = PROCESSOR_R4000;
4216 /* The vr4100 is a non-FP ISA III processor with some extra
4218 else if (!strcmp (p, "4100"))
4220 mips_cpu = PROCESSOR_R4100;
4221 target_flags |= MASK_SOFT_FLOAT ;
4223 /* The vr4300 is a standard ISA III processor, but with a different
4225 else if (!strcmp (p, "4300"))
4226 mips_cpu = PROCESSOR_R4300;
4227 /* The r4400 is exactly the same as the r4000 from the compiler's
4229 else if (!strcmp (p, "4400"))
4230 mips_cpu = PROCESSOR_R4000;
4231 else if (!strcmp (p, "4600"))
4232 mips_cpu = PROCESSOR_R4600;
4233 else if (!strcmp (p, "4650"))
4234 mips_cpu = PROCESSOR_R4650;
4238 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4239 mips_cpu = PROCESSOR_R5000;
4243 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4244 mips_cpu = PROCESSOR_R6000;
4248 if (!strcmp (p, "8000"))
4249 mips_cpu = PROCESSOR_R8000;
4253 if (!strcmp (p, "orion"))
4254 mips_cpu = PROCESSOR_R4600;
4259 && mips_cpu != PROCESSOR_R4300
4260 && mips_cpu != PROCESSOR_R4100
4261 && mips_cpu != PROCESSOR_R5000)
4262 mips_cpu = PROCESSOR_DEFAULT;
4264 if (mips_cpu == PROCESSOR_DEFAULT)
4266 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4267 mips_cpu_string = "default";
4271 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
4272 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
4273 || ((mips_cpu == PROCESSOR_R4000
4274 || mips_cpu == PROCESSOR_R4100
4275 || mips_cpu == PROCESSOR_R4300
4276 || mips_cpu == PROCESSOR_R4600
4277 || mips_cpu == PROCESSOR_R4650)
4279 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4281 /* make sure sizes of ints/longs/etc. are ok */
4285 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
4287 else if (TARGET_64BIT)
4288 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
4291 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4292 flag_pcc_struct_return = 0;
4294 /* Tell halfpic.c that we have half-pic code if we do. */
4295 if (TARGET_HALF_PIC)
4298 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4299 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4300 /* ??? -non_shared turns off pic code generation, but this is not
4302 if (TARGET_ABICALLS)
4304 mips_abicalls = MIPS_ABICALLS_YES;
4306 if (mips_section_threshold > 0)
4307 warning ("-G is incompatible with PIC code which is the default");
4310 mips_abicalls = MIPS_ABICALLS_NO;
4312 /* -membedded-pic is a form of PIC code suitable for embedded
4313 systems. All calls are made using PC relative addressing, and
4314 all data is addressed using the $gp register. This requires gas,
4315 which does most of the work, and GNU ld, which automatically
4316 expands PC relative calls which are out of range into a longer
4317 instruction sequence. All gcc really does differently is
4318 generate a different sequence for a switch. */
4319 if (TARGET_EMBEDDED_PIC)
4322 if (TARGET_ABICALLS)
4323 warning ("-membedded-pic and -mabicalls are incompatible");
4326 warning ("-G and -membedded-pic are incompatible");
4328 /* Setting mips_section_threshold is not required, because gas
4329 will force everything to be GP addressable anyhow, but
4330 setting it will cause gcc to make better estimates of the
4331 number of instructions required to access a particular data
4333 mips_section_threshold = 0x7fffffff;
4336 /* This optimization requires a linker that can support a R_MIPS_LO16
4337 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
4338 GNU ld has this support, but not all other MIPS linkers do, so we enable
4339 this optimization only if the user requests it, or if GNU ld is the
4340 standard linker for this configuration. */
4341 /* ??? This does not work when target addresses are DImode.
4342 This is because we are missing DImode high/lo_sum patterns. */
4343 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
4345 mips_split_addresses = 1;
4347 mips_split_addresses = 0;
4349 /* -mrnames says to use the MIPS software convention for register
4350 names instead of the hardware names (ie, $a0 instead of $4).
4351 We do this by switching the names in mips_reg_names, which the
4352 reg_names points into via the REGISTER_NAMES macro. */
4354 if (TARGET_NAME_REGS)
4355 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names,
4356 sizeof (mips_reg_names));
4358 /* When compiling for the mips16, we can not use floating point. We
4359 record the original hard float value in mips16_hard_float. */
4362 if (TARGET_SOFT_FLOAT)
4363 mips16_hard_float = 0;
4365 mips16_hard_float = 1;
4366 target_flags |= MASK_SOFT_FLOAT;
4368 /* Don't run the scheduler before reload, since it tends to
4369 increase register pressure. */
4370 flag_schedule_insns = 0;
4373 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
4374 to avoid using up another bit in target_flags. */
4375 if (mips_entry_string != NULL)
4377 if (*mips_entry_string != '\0')
4378 error ("Invalid option `entry%s'", mips_entry_string);
4380 if (! TARGET_MIPS16)
4381 warning ("-mentry is only meaningful with -mips-16");
4386 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
4387 attributes can access it. */
4393 /* Initialize the high and low values for legitimate floating point
4394 constants. Rather than trying to get the accuracy down to the
4395 last bit, just use approximate ranges. */
4396 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
4397 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
4398 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
4399 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
4401 mips_print_operand_punct['?'] = 1;
4402 mips_print_operand_punct['#'] = 1;
4403 mips_print_operand_punct['&'] = 1;
4404 mips_print_operand_punct['!'] = 1;
4405 mips_print_operand_punct['*'] = 1;
4406 mips_print_operand_punct['@'] = 1;
4407 mips_print_operand_punct['.'] = 1;
4408 mips_print_operand_punct['('] = 1;
4409 mips_print_operand_punct[')'] = 1;
4410 mips_print_operand_punct['['] = 1;
4411 mips_print_operand_punct[']'] = 1;
4412 mips_print_operand_punct['<'] = 1;
4413 mips_print_operand_punct['>'] = 1;
4414 mips_print_operand_punct['{'] = 1;
4415 mips_print_operand_punct['}'] = 1;
4416 mips_print_operand_punct['^'] = 1;
4417 mips_print_operand_punct['$'] = 1;
4418 mips_print_operand_punct['+'] = 1;
4420 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4421 mips_char_to_class['e'] = M16_NA_REGS;
4422 mips_char_to_class['t'] = T_REG;
4423 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4424 mips_char_to_class['h'] = HI_REG;
4425 mips_char_to_class['l'] = LO_REG;
4426 mips_char_to_class['a'] = HILO_REG;
4427 mips_char_to_class['x'] = MD_REGS;
4428 mips_char_to_class['b'] = ALL_REGS;
4429 mips_char_to_class['y'] = GR_REGS;
4430 mips_char_to_class['z'] = ST_REGS;
4432 /* Set up array to map GCC register number to debug register number.
4433 Ignore the special purpose register numbers. */
4435 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4436 mips_dbx_regno[i] = -1;
4438 start = GP_DBX_FIRST - GP_REG_FIRST;
4439 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4440 mips_dbx_regno[i] = i + start;
4442 start = FP_DBX_FIRST - FP_REG_FIRST;
4443 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4444 mips_dbx_regno[i] = i + start;
4446 /* Set up array giving whether a given register can hold a given mode.
4447 At present, restrict ints from being in FP registers, because reload
4448 is a little enthusiastic about storing extra values in FP registers,
4449 and this is not good for things like OS kernels. Also, due to the
4450 mandatory delay, it is as fast to load from cached memory as to move
4451 from the FP register. */
4453 for (mode = VOIDmode;
4454 mode != MAX_MACHINE_MODE;
4455 mode = (enum machine_mode) ((int)mode + 1))
4457 register int size = GET_MODE_SIZE (mode);
4458 register enum mode_class class = GET_MODE_CLASS (mode);
4460 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4467 temp = (regno == FPSW_REGNUM);
4469 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4470 || FP_REG_P (regno));
4473 else if (GP_REG_P (regno))
4474 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4476 else if (FP_REG_P (regno))
4477 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
4478 && (class == MODE_FLOAT
4479 || class == MODE_COMPLEX_FLOAT
4480 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
4481 && (! TARGET_SINGLE_FLOAT || size <= 4));
4483 else if (MD_REG_P (regno))
4484 temp = (class == MODE_INT
4485 && (size <= UNITS_PER_WORD
4486 || (regno == MD_REG_FIRST
4487 && size == 2 * UNITS_PER_WORD)));
4492 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4496 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4497 initialized yet, so we can't use that here. */
4498 gpr_mode = TARGET_64BIT ? DImode : SImode;
4501 /* On the mips16, we want to allocate $24 (T_REG) before other
4502 registers for instructions for which it is possible. This helps
4503 avoid shuffling registers around in order to set up for an xor,
4504 encouraging the compiler to use a cmp instead. */
4507 mips_order_regs_for_local_alloc ()
4511 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4512 reg_alloc_order[i] = i;
4516 /* It really doesn't matter where we put register 0, since it is
4517 a fixed register anyhow. */
4518 reg_alloc_order[0] = 24;
4519 reg_alloc_order[24] = 0;
4524 /* The MIPS debug format wants all automatic variables and arguments
4525 to be in terms of the virtual frame pointer (stack pointer before
4526 any adjustment in the function), while the MIPS 3.0 linker wants
4527 the frame pointer to be the stack pointer after the initial
4528 adjustment. So, we do the adjustment here. The arg pointer (which
4529 is eliminated) points to the virtual frame pointer, while the frame
4530 pointer (which may be eliminated) points to the stack pointer after
4531 the initial adjustments. */
4534 mips_debugger_offset (addr, offset)
4536 HOST_WIDE_INT offset;
4538 rtx offset2 = const0_rtx;
4539 rtx reg = eliminate_constant_term (addr, &offset2);
4542 offset = INTVAL (offset2);
4544 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4545 || reg == hard_frame_pointer_rtx)
4547 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
4548 ? compute_frame_size (get_frame_size ())
4549 : current_frame_info.total_size;
4551 /* MIPS16 frame is smaller */
4552 if (frame_pointer_needed && TARGET_MIPS16)
4553 frame_size -= current_function_outgoing_args_size;
4555 offset = offset - frame_size;
4558 /* sdbout_parms does not want this to crash for unrecognized cases. */
4560 else if (reg != arg_pointer_rtx)
4561 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
4567 /* A C compound statement to output to stdio stream STREAM the
4568 assembler syntax for an instruction operand X. X is an RTL
4571 CODE is a value that can be used to specify one of several ways
4572 of printing the operand. It is used when identical operands
4573 must be printed differently depending on the context. CODE
4574 comes from the `%' specification that was used to request
4575 printing of the operand. If the specification was just `%DIGIT'
4576 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4577 is the ASCII code for LTR.
4579 If X is a register, this macro should print the register's name.
4580 The names can be found in an array `reg_names' whose type is
4581 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4583 When the machine description has a specification `%PUNCT' (a `%'
4584 followed by a punctuation character), this macro is called with
4585 a null pointer for X and the punctuation character for CODE.
4587 The MIPS specific codes are:
4589 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4590 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4591 'd' output integer constant in decimal,
4592 'z' if the operand is 0, use $0 instead of normal operand.
4593 'D' print second register of double-word register operand.
4594 'L' print low-order register of double-word register operand.
4595 'M' print high-order register of double-word register operand.
4596 'C' print part of opcode for a branch condition.
4597 'F' print part of opcode for a floating-point branch condition.
4598 'N' print part of opcode for a branch condition, inverted.
4599 'W' print part of opcode for a floating-point branch condition, inverted.
4600 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
4601 'B' print 'z' for EQ, 'n' for NE
4602 'b' print 'n' for EQ, 'z' for NE
4603 'T' print 'f' for EQ, 't' for NE
4604 't' print 't' for EQ, 'f' for NE
4605 'Z' print register and a comma, but print nothing for $fcc0
4606 '(' Turn on .set noreorder
4607 ')' Turn on .set reorder
4608 '[' Turn on .set noat
4610 '<' Turn on .set nomacro
4611 '>' Turn on .set macro
4612 '{' Turn on .set volatile (not GAS)
4613 '}' Turn on .set novolatile (not GAS)
4614 '&' Turn on .set noreorder if filling delay slots
4615 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4616 '!' Turn on .set nomacro if filling delay slots
4617 '#' Print nop if in a .set noreorder section.
4618 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4619 '@' Print the name of the assembler temporary register (at or $1).
4620 '.' Print the name of the register with a hard-wired zero (zero or $0).
4621 '^' Print the name of the pic call-through register (t9 or $25).
4622 '$' Print the name of the stack pointer register (sp or $29).
4623 '+' Print the name of the gp register (gp or $28). */
4626 print_operand (file, op, letter)
4627 FILE *file; /* file to write to */
4628 rtx op; /* operand to print */
4629 int letter; /* %<letter> or 0 */
4631 register enum rtx_code code;
4633 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
4638 if (mips_branch_likely)
4643 fputs (reg_names [GP_REG_FIRST + 1], file);
4647 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
4651 fputs (reg_names [GP_REG_FIRST + 0], file);
4655 fputs (reg_names[STACK_POINTER_REGNUM], file);
4659 fputs (reg_names[GP_REG_FIRST + 28], file);
4663 if (final_sequence != 0 && set_noreorder++ == 0)
4664 fputs (".set\tnoreorder\n\t", file);
4668 if (final_sequence != 0)
4670 if (set_noreorder++ == 0)
4671 fputs (".set\tnoreorder\n\t", file);
4673 if (set_nomacro++ == 0)
4674 fputs (".set\tnomacro\n\t", file);
4679 if (final_sequence != 0 && set_nomacro++ == 0)
4680 fputs ("\n\t.set\tnomacro", file);
4684 if (set_noreorder != 0)
4685 fputs ("\n\tnop", file);
4686 else if (TARGET_STATS)
4687 fputs ("\n\t#nop", file);
4692 if (set_noreorder++ == 0)
4693 fputs (".set\tnoreorder\n\t", file);
4697 if (set_noreorder == 0)
4698 error ("internal error: %%) found without a %%( in assembler pattern");
4700 else if (--set_noreorder == 0)
4701 fputs ("\n\t.set\treorder", file);
4706 if (set_noat++ == 0)
4707 fputs (".set\tnoat\n\t", file);
4712 error ("internal error: %%] found without a %%[ in assembler pattern");
4713 else if (--set_noat == 0)
4714 fputs ("\n\t.set\tat", file);
4719 if (set_nomacro++ == 0)
4720 fputs (".set\tnomacro\n\t", file);
4724 if (set_nomacro == 0)
4725 error ("internal error: %%> found without a %%< in assembler pattern");
4726 else if (--set_nomacro == 0)
4727 fputs ("\n\t.set\tmacro", file);
4732 if (set_volatile++ == 0)
4733 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
4737 if (set_volatile == 0)
4738 error ("internal error: %%} found without a %%{ in assembler pattern");
4739 else if (--set_volatile == 0)
4740 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
4745 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
4754 error ("PRINT_OPERAND null pointer");
4758 code = GET_CODE (op);
4760 if (code == SIGN_EXTEND)
4761 op = XEXP (op, 0), code = GET_CODE (op);
4766 case EQ: fputs ("eq", file); break;
4767 case NE: fputs ("ne", file); break;
4768 case GT: fputs ("gt", file); break;
4769 case GE: fputs ("ge", file); break;
4770 case LT: fputs ("lt", file); break;
4771 case LE: fputs ("le", file); break;
4772 case GTU: fputs ("gtu", file); break;
4773 case GEU: fputs ("geu", file); break;
4774 case LTU: fputs ("ltu", file); break;
4775 case LEU: fputs ("leu", file); break;
4777 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
4780 else if (letter == 'N')
4783 case EQ: fputs ("ne", file); break;
4784 case NE: fputs ("eq", file); break;
4785 case GT: fputs ("le", file); break;
4786 case GE: fputs ("lt", file); break;
4787 case LT: fputs ("ge", file); break;
4788 case LE: fputs ("gt", file); break;
4789 case GTU: fputs ("leu", file); break;
4790 case GEU: fputs ("ltu", file); break;
4791 case LTU: fputs ("geu", file); break;
4792 case LEU: fputs ("gtu", file); break;
4794 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
4797 else if (letter == 'F')
4800 case EQ: fputs ("c1f", file); break;
4801 case NE: fputs ("c1t", file); break;
4803 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
4806 else if (letter == 'W')
4809 case EQ: fputs ("c1t", file); break;
4810 case NE: fputs ("c1f", file); break;
4812 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
4815 else if (letter == 'S')
4819 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
4820 assemble_name (file, buffer);
4823 else if (letter == 'Z')
4825 register int regnum;
4830 regnum = REGNO (op);
4831 if (! ST_REG_P (regnum))
4834 if (regnum != ST_REG_FIRST)
4835 fprintf (file, "%s,", reg_names[regnum]);
4838 else if (code == REG || code == SUBREG)
4840 register int regnum;
4843 regnum = REGNO (op);
4845 regnum = true_regnum (op);
4847 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
4848 || (letter == 'L' && WORDS_BIG_ENDIAN)
4852 fprintf (file, "%s", reg_names[regnum]);
4855 else if (code == MEM)
4856 output_address (XEXP (op, 0));
4858 else if (code == CONST_DOUBLE
4859 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
4864 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
4865 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
4869 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
4870 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
4872 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
4873 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
4875 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
4876 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
4878 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
4879 fputs (reg_names[GP_REG_FIRST], file);
4881 else if (letter == 'd' || letter == 'x' || letter == 'X')
4882 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
4885 else if (letter == 'B')
4886 fputs (code == EQ ? "z" : "n", file);
4887 else if (letter == 'b')
4888 fputs (code == EQ ? "n" : "z", file);
4889 else if (letter == 'T')
4890 fputs (code == EQ ? "f" : "t", file);
4891 else if (letter == 't')
4892 fputs (code == EQ ? "t" : "f", file);
4894 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
4896 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
4897 print_operand (file, XEXP (op, 0), letter);
4900 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
4902 fputs ("%gprel(", file);
4903 mips16_output_gp_offset (file, op);
4908 output_addr_const (file, op);
4911 /* A C compound statement to output to stdio stream STREAM the
4912 assembler syntax for an instruction operand that is a memory
4913 reference whose address is ADDR. ADDR is an RTL expression.
4915 On some machines, the syntax for a symbolic address depends on
4916 the section that the address refers to. On these machines,
4917 define the macro `ENCODE_SECTION_INFO' to store the information
4918 into the `symbol_ref', and then check for it here. */
4921 print_operand_address (file, addr)
4926 error ("PRINT_OPERAND_ADDRESS, null pointer");
4929 switch (GET_CODE (addr))
4932 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
4933 abort_with_insn (addr, "Arg pointer not eliminated.");
4935 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
4940 register rtx arg0 = XEXP (addr, 0);
4941 register rtx arg1 = XEXP (addr, 1);
4943 if (! mips_split_addresses)
4944 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4946 if (GET_CODE (arg0) != REG)
4947 abort_with_insn (addr,
4948 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4950 fprintf (file, "%%lo(");
4951 print_operand_address (file, arg1);
4952 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
4958 register rtx reg = 0;
4959 register rtx offset = 0;
4960 register rtx arg0 = XEXP (addr, 0);
4961 register rtx arg1 = XEXP (addr, 1);
4963 if (GET_CODE (arg0) == REG)
4967 if (GET_CODE (offset) == REG)
4968 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
4971 else if (GET_CODE (arg1) == REG)
4972 reg = arg1, offset = arg0;
4973 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
4975 output_addr_const (file, addr);
4979 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
4981 if (! CONSTANT_P (offset))
4982 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4984 if (REGNO (reg) == ARG_POINTER_REGNUM)
4985 abort_with_insn (addr, "Arg pointer not eliminated.");
4988 && GET_CODE (offset) == CONST
4989 && mips16_gp_offset_p (offset))
4991 fputs ("%gprel(", file);
4992 mips16_output_gp_offset (file, offset);
4996 output_addr_const (file, offset);
4997 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5005 output_addr_const (file, addr);
5009 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5015 /* If optimizing for the global pointer, keep track of all of the externs, so
5016 that at the end of the file, we can emit the appropriate .extern
5017 declaration for them, before writing out the text section. We assume all
5018 names passed to us are in the permanent obstack, so they will be valid at
5019 the end of the compilation.
5021 If we have -G 0, or the extern size is unknown, or the object is in a user
5022 specified section that is not .sbss/.sdata, don't bother emitting the
5023 .externs. In the case of user specified sections this behaviour is
5024 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5027 mips_output_external (file, decl, name)
5028 FILE *file ATTRIBUTE_UNUSED;
5032 register struct extern_list *p;
5037 && TREE_CODE (decl) != FUNCTION_DECL
5038 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5039 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5040 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5041 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5043 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5044 p->next = extern_head;
5050 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5051 if (TREE_CODE (decl) == FUNCTION_DECL
5052 /* ??? Don't include alloca, since gcc will always expand it
5053 inline. If we don't do this, the C++ library fails to build. */
5054 && strcmp (name, "alloca")
5055 /* ??? Don't include __builtin_next_arg, because then gcc will not
5056 bootstrap under Irix 5.1. */
5057 && strcmp (name, "__builtin_next_arg"))
5059 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5060 p->next = extern_head;
5070 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5072 mips_output_external_libcall (file, name)
5076 register struct extern_list *p;
5078 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5079 p->next = extern_head;
5088 /* Compute a string to use as a temporary file name. */
5090 /* On MSDOS, write temp files in current dir
5091 because there's no place else we can expect to use. */
5094 #define P_tmpdir "./"
5102 const char *base = getenv ("TMPDIR");
5108 if (access (P_tmpdir, R_OK | W_OK) == 0)
5112 if (access ("/usr/tmp", R_OK | W_OK) == 0)
5118 len = strlen (base);
5119 /* temp_filename is global, so we must use malloc, not alloca. */
5120 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
5121 strcpy (temp_filename, base);
5122 if (len > 0 && temp_filename[len-1] != '/')
5123 temp_filename[len++] = '/';
5125 strcpy (temp_filename + len, "ctXXXXXX");
5126 mktemp (temp_filename);
5128 stream = fopen (temp_filename, "w+");
5130 pfatal_with_name (temp_filename);
5133 /* In MSDOS, we cannot unlink the temporary file until we are finished using
5134 it. Otherwise, we delete it now, so that it will be gone even if the
5135 compiler happens to crash. */
5136 unlink (temp_filename);
5141 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5142 for .file's that start within a function. If we are smuggling stabs, try to
5143 put out a MIPS ECOFF file and a stab. */
5146 mips_output_filename (stream, name)
5150 static int first_time = 1;
5151 char ltext_label_name[100];
5157 current_function_file = name;
5158 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5159 /* This tells mips-tfile that stabs will follow. */
5160 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5161 fprintf (stream, "\t#@stabs\n");
5164 else if (write_symbols == DBX_DEBUG)
5166 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5167 fprintf (stream, "%s ", ASM_STABS_OP);
5168 output_quoted_string (stream, name);
5169 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5172 else if (name != current_function_file
5173 && strcmp (name, current_function_file) != 0)
5175 if (inside_function && !TARGET_GAS)
5177 if (!file_in_function_warning)
5179 file_in_function_warning = 1;
5180 ignore_line_number = 1;
5181 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5187 current_function_file = name;
5188 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5193 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5194 as well as a .loc, since it is possible that MIPS ECOFF might not be
5195 able to represent the location for inlines that come from a different
5199 mips_output_lineno (stream, line)
5203 if (write_symbols == DBX_DEBUG)
5206 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
5207 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5208 LOCAL_LABEL_PREFIX, sym_lineno);
5213 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5214 (ignore_line_number) ? "#" : "",
5215 num_source_filenames, line);
5217 LABEL_AFTER_LOC (stream);
5221 /* If defined, a C statement to be executed just prior to the output of
5222 assembler code for INSN, to modify the extracted operands so they will be
5225 Here the argument OPVEC is the vector containing the operands extracted
5226 from INSN, and NOPERANDS is the number of elements of the vector which
5227 contain meaningful data for this insn. The contents of this vector are
5228 what will be used to convert the insn template into assembler code, so you
5229 can change the assembler output by changing the contents of the vector.
5231 We use it to check if the current insn needs a nop in front of it because
5232 of load delays, and also to update the delay slot statistics. */
5234 /* ??? There is no real need for this function, because it never actually
5235 emits a NOP anymore. */
5238 final_prescan_insn (insn, opvec, noperands)
5240 rtx opvec[] ATTRIBUTE_UNUSED;
5241 int noperands ATTRIBUTE_UNUSED;
5243 if (dslots_number_nops > 0)
5245 rtx pattern = PATTERN (insn);
5246 int length = get_attr_length (insn);
5248 /* Do we need to emit a NOP? */
5250 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5251 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5252 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5253 || (mips_load_reg4 != 0
5254 && reg_mentioned_p (mips_load_reg4, pattern)))
5255 fputs ("\t#nop\n", asm_out_file);
5258 dslots_load_filled++;
5260 while (--dslots_number_nops > 0)
5261 fputs ("\t#nop\n", asm_out_file);
5270 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
5271 dslots_jump_total++;
5274 /* Output at beginning of assembler file.
5276 If we are optimizing to use the global pointer, create a temporary file to
5277 hold all of the text stuff, and write it out to the end. This is needed
5278 because the MIPS assembler is evidently one pass, and if it hasn't seen the
5279 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
5280 processed, it generates a two instruction sequence. */
5283 mips_asm_file_start (stream)
5286 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
5288 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5289 inside of a .set noreorder section jumps to a label outside of the .set
5290 noreorder section. Revision 2.20 just set nobopt silently rather than
5293 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5294 fprintf (stream, "\t.set\tnobopt\n");
5296 /* Generate the pseudo ops that System V.4 wants. */
5297 #ifndef ABICALLS_ASM_OP
5298 #define ABICALLS_ASM_OP ".abicalls"
5300 if (TARGET_ABICALLS)
5301 /* ??? but do not want this (or want pic0) if -non-shared? */
5302 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
5305 fprintf (stream, "\t.set\tmips16\n");
5307 /* Start a section, so that the first .popsection directive is guaranteed
5308 to have a previously defined section to pop back to. */
5309 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
5310 fprintf (stream, "\t.section\t.text\n");
5312 /* This code exists so that we can put all externs before all symbol
5313 references. This is necessary for the MIPS assembler's global pointer
5314 optimizations to work. */
5315 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5317 asm_out_data_file = stream;
5318 asm_out_text_file = make_temp_file ();
5322 asm_out_data_file = asm_out_text_file = stream;
5324 if (flag_verbose_asm)
5325 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
5327 mips_section_threshold, mips_cpu_string, mips_isa);
5330 /* If we are optimizing the global pointer, emit the text section now and any
5331 small externs which did not have .comm, etc that are needed. Also, give a
5332 warning if the data area is more than 32K and -pic because 3 instructions
5333 are needed to reference the data pointers. */
5336 mips_asm_file_end (file)
5341 struct extern_list *p;
5346 HALF_PIC_FINISH (file);
5353 for (p = extern_head; p != 0; p = p->next)
5355 name_tree = get_identifier (p->name);
5357 /* Positively ensure only one .extern for any given symbol. */
5358 if (! TREE_ASM_WRITTEN (name_tree))
5360 TREE_ASM_WRITTEN (name_tree) = 1;
5361 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5363 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
5367 fputs ("\t.extern\t", file);
5368 assemble_name (file, p->name);
5369 fprintf (file, ", %d\n", p->size);
5375 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5377 fprintf (file, "\n\t.text\n");
5378 rewind (asm_out_text_file);
5379 if (ferror (asm_out_text_file))
5380 fatal_io_error (temp_filename);
5382 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
5383 if ((int) fwrite (buffer, 1, len, file) != len)
5384 pfatal_with_name (asm_file_name);
5387 pfatal_with_name (temp_filename);
5389 if (fclose (asm_out_text_file) != 0)
5390 pfatal_with_name (temp_filename);
5393 unlink (temp_filename);
5398 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
5399 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
5402 mips_declare_object (stream, name, init_string, final_string, size)
5409 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
5410 assemble_name (stream, name);
5411 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
5415 tree name_tree = get_identifier (name);
5416 TREE_ASM_WRITTEN (name_tree) = 1;
5420 /* Output a double precision value to the assembler. If both the
5421 host and target are IEEE, emit the values in hex. */
5424 mips_output_double (stream, value)
5426 REAL_VALUE_TYPE value;
5428 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
5430 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
5432 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
5433 value_long[0], value, value_long[1]);
5435 fprintf (stream, "\t.double\t%.20g\n", value);
5439 /* Output a single precision value to the assembler. If both the
5440 host and target are IEEE, emit the values in hex. */
5443 mips_output_float (stream, value)
5445 REAL_VALUE_TYPE value;
5447 #ifdef REAL_VALUE_TO_TARGET_SINGLE
5449 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
5451 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
5453 fprintf (stream, "\t.float\t%.12g\n", value);
5457 /* Return the bytes needed to compute the frame pointer from the current
5460 Mips stack frames look like:
5462 Before call After call
5463 +-----------------------+ +-----------------------+
5466 | caller's temps. | | caller's temps. |
5468 +-----------------------+ +-----------------------+
5470 | arguments on stack. | | arguments on stack. |
5472 +-----------------------+ +-----------------------+
5473 | 4 words to save | | 4 words to save |
5474 | arguments passed | | arguments passed |
5475 | in registers, even | | in registers, even |
5476 SP->| if not passed. | VFP->| if not passed. |
5477 +-----------------------+ +-----------------------+
5479 | fp register save |
5481 +-----------------------+
5483 | gp register save |
5485 +-----------------------+
5489 +-----------------------+
5491 | alloca allocations |
5493 +-----------------------+
5495 | GP save for V.4 abi |
5497 +-----------------------+
5499 | arguments on stack |
5501 +-----------------------+
5503 | arguments passed |
5504 | in registers, even |
5505 low SP->| if not passed. |
5506 memory +-----------------------+
5511 compute_frame_size (size)
5512 HOST_WIDE_INT size; /* # of var. bytes allocated */
5515 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
5516 HOST_WIDE_INT var_size; /* # bytes that variables take up */
5517 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
5518 HOST_WIDE_INT extra_size; /* # extra bytes */
5519 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
5520 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
5521 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
5522 long mask; /* mask of saved gp registers */
5523 long fmask; /* mask of saved fp registers */
5524 int fp_inc; /* 1 or 2 depending on the size of fp regs */
5525 long fp_bits; /* bitmask to use for each fp register */
5531 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
5532 var_size = MIPS_STACK_ALIGN (size);
5533 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
5535 /* The MIPS 3.0 linker does not like functions that dynamically
5536 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5537 looks like we are trying to create a second frame pointer to the
5538 function, so allocate some stack space to make it happy. */
5540 if (args_size == 0 && current_function_calls_alloca)
5541 args_size = 4 * UNITS_PER_WORD;
5543 total_size = var_size + args_size + extra_size;
5545 /* Calculate space needed for gp registers. */
5546 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5548 /* $18 is a special case on the mips16. It may be used to call
5549 a function which returns a floating point value, but it is
5550 marked in call_used_regs. $31 is also a special case. When
5551 not using -mentry, it will be used to copy a return value
5552 into the floating point registers if the return value is
5554 if (MUST_SAVE_REGISTER (regno)
5556 && regno == GP_REG_FIRST + 18
5557 && regs_ever_live[regno])
5559 && regno == GP_REG_FIRST + 31
5560 && mips16_hard_float
5562 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
5563 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
5565 && (! TARGET_SINGLE_FLOAT
5566 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
5569 gp_reg_size += GET_MODE_SIZE (gpr_mode);
5570 mask |= 1L << (regno - GP_REG_FIRST);
5572 /* The entry and exit pseudo instructions can not save $17
5573 without also saving $16. */
5575 && regno == GP_REG_FIRST + 17
5576 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
5578 gp_reg_size += UNITS_PER_WORD;
5584 /* Calculate space needed for fp registers. */
5585 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
5596 /* This loop must iterate over the same space as its companion in
5597 save_restore_regs. */
5598 for (regno = (FP_REG_LAST - fp_inc + 1);
5599 regno >= FP_REG_FIRST;
5602 if (regs_ever_live[regno] && !call_used_regs[regno])
5604 fp_reg_size += fp_inc * UNITS_PER_FPREG;
5605 fmask |= fp_bits << (regno - FP_REG_FIRST);
5609 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5610 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
5612 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
5613 for leaf routines (total_size == extra_size) to save the gp reg.
5614 The gp reg is callee saved in the 64 bit ABI, so all routines must
5615 save the gp reg. This is not a leaf routine if -p, because of the
5617 if (total_size == extra_size
5618 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
5620 total_size = extra_size = 0;
5621 else if (TARGET_ABICALLS)
5623 /* Add the context-pointer to the saved registers. */
5624 gp_reg_size += UNITS_PER_WORD;
5625 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
5626 total_size -= gp_reg_rounded;
5627 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5628 total_size += gp_reg_rounded;
5631 /* Add in space reserved on the stack by the callee for storing arguments
5632 passed in registers. */
5633 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
5634 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
5636 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
5637 if (mips_entry && total_size > 0 && total_size < 32)
5640 /* Save other computed information. */
5641 current_frame_info.total_size = total_size;
5642 current_frame_info.var_size = var_size;
5643 current_frame_info.args_size = args_size;
5644 current_frame_info.extra_size = extra_size;
5645 current_frame_info.gp_reg_size = gp_reg_size;
5646 current_frame_info.fp_reg_size = fp_reg_size;
5647 current_frame_info.mask = mask;
5648 current_frame_info.fmask = fmask;
5649 current_frame_info.initialized = reload_completed;
5650 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
5651 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
5655 unsigned long offset;
5657 /* When using mips_entry, the registers are always saved at the
5658 top of the stack. */
5660 offset = (args_size + extra_size + var_size
5661 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
5663 offset = total_size - GET_MODE_SIZE (gpr_mode);
5665 current_frame_info.gp_sp_offset = offset;
5666 current_frame_info.gp_save_offset = offset - total_size;
5670 current_frame_info.gp_sp_offset = 0;
5671 current_frame_info.gp_save_offset = 0;
5676 unsigned long offset = (args_size + extra_size + var_size
5677 + gp_reg_rounded + fp_reg_size
5678 - fp_inc * UNITS_PER_FPREG);
5679 current_frame_info.fp_sp_offset = offset;
5680 current_frame_info.fp_save_offset = offset - total_size;
5684 current_frame_info.fp_sp_offset = 0;
5685 current_frame_info.fp_save_offset = 0;
5688 /* Ok, we're done. */
5692 /* Common code to emit the insns (or to write the instructions to a file)
5693 to save/restore registers.
5695 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
5696 is not modified within save_restore_insns. */
5698 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
5701 save_restore_insns (store_p, large_reg, large_offset, file)
5702 int store_p; /* true if this is prologue */
5703 rtx large_reg; /* register holding large offset constant or NULL */
5704 long large_offset; /* large constant offset value */
5705 FILE *file; /* file to write instructions instead of making RTL */
5707 long mask = current_frame_info.mask;
5708 long fmask = current_frame_info.fmask;
5711 HOST_WIDE_INT base_offset;
5712 HOST_WIDE_INT gp_offset;
5713 HOST_WIDE_INT fp_offset;
5714 HOST_WIDE_INT end_offset;
5717 if (frame_pointer_needed
5718 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
5721 if (mask == 0 && fmask == 0)
5724 /* Save registers starting from high to low. The debuggers prefer at least
5725 the return register be stored at func+4, and also it allows us not to
5726 need a nop in the epilog if at least one register is reloaded in
5727 addition to return address. */
5729 /* Save GP registers if needed. */
5732 /* Pick which pointer to use as a base register. For small frames, just
5733 use the stack pointer. Otherwise, use a temporary register. Save 2
5734 cycles if the save area is near the end of a large frame, by reusing
5735 the constant created in the prologue/epilogue to adjust the stack
5738 gp_offset = current_frame_info.gp_sp_offset;
5740 = gp_offset - (current_frame_info.gp_reg_size
5741 - GET_MODE_SIZE (gpr_mode));
5743 if (gp_offset < 0 || end_offset < 0)
5744 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
5745 (long) gp_offset, (long) end_offset);
5747 /* If we see a large frame in mips16 mode, we save the registers
5748 before adjusting the stack pointer, and load them afterward. */
5749 else if (TARGET_MIPS16 && large_offset > 32767)
5750 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
5752 else if (gp_offset < 32768)
5753 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
5755 else if (large_reg != 0
5756 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
5757 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
5759 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5760 base_offset = large_offset;
5763 if (Pmode == DImode)
5764 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
5765 stack_pointer_rtx));
5767 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
5768 stack_pointer_rtx));
5770 RTX_FRAME_RELATED_P (insn) = 1;
5773 fprintf (file, "\t%s\t%s,%s,%s\n",
5774 Pmode == DImode ? "daddu" : "addu",
5775 reg_names[MIPS_TEMP2_REGNUM],
5776 reg_names[REGNO (large_reg)],
5777 reg_names[STACK_POINTER_REGNUM]);
5782 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5783 base_offset = gp_offset;
5786 rtx gp_offset_rtx = GEN_INT (gp_offset);
5788 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5789 bit, so make sure that we don't emit anything that can be
5791 /* ??? There is no DImode ori immediate pattern, so we can only
5792 do this for 32 bit code. */
5793 if (large_int (gp_offset_rtx)
5794 && GET_MODE (base_reg_rtx) == SImode)
5796 insn = emit_move_insn (base_reg_rtx,
5797 GEN_INT (gp_offset & 0xffff0000));
5799 RTX_FRAME_RELATED_P (insn) = 1;
5801 = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
5802 GEN_INT (gp_offset & 0x0000ffff)));
5804 RTX_FRAME_RELATED_P (insn) = 1;
5808 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
5810 RTX_FRAME_RELATED_P (insn) = 1;
5813 if (Pmode == DImode)
5814 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
5815 stack_pointer_rtx));
5817 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
5818 stack_pointer_rtx));
5820 RTX_FRAME_RELATED_P (insn) = 1;
5824 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
5825 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
5826 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
5827 fprintf (file, "\n\t%s\t%s,%s,%s\n",
5828 Pmode == DImode ? "daddu" : "addu",
5829 reg_names[MIPS_TEMP2_REGNUM],
5830 reg_names[MIPS_TEMP2_REGNUM],
5831 reg_names[STACK_POINTER_REGNUM]);
5835 /* When we restore the registers in MIPS16 mode, then if we are
5836 using a frame pointer, and this is not a large frame, the
5837 current stack pointer will be offset by
5838 current_function_outgoing_args_size. Doing it this way lets
5839 us avoid offsetting the frame pointer before copying it into
5840 the stack pointer; there is no instruction to set the stack
5841 pointer to the sum of a register and a constant. */
5844 && frame_pointer_needed
5845 && large_offset <= 32767)
5846 base_offset += current_function_outgoing_args_size;
5848 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
5849 if (BITSET_P (mask, regno - GP_REG_FIRST))
5855 = gen_rtx (MEM, gpr_mode,
5856 gen_rtx (PLUS, Pmode, base_reg_rtx,
5857 GEN_INT (gp_offset - base_offset)));
5859 RTX_UNCHANGING_P (mem_rtx) = 1;
5861 /* The mips16 does not have an instruction to load
5862 $31, so we load $7 instead, and work things out
5864 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
5865 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
5866 /* The mips16 sometimes needs to save $18. */
5867 else if (TARGET_MIPS16
5868 && regno != GP_REG_FIRST + 31
5869 && ! M16_REG_P (regno))
5872 reg_rtx = gen_rtx (REG, gpr_mode, 6);
5875 reg_rtx = gen_rtx (REG, gpr_mode, 3);
5876 emit_move_insn (reg_rtx,
5877 gen_rtx (REG, gpr_mode, regno));
5881 reg_rtx = gen_rtx (REG, gpr_mode, regno);
5885 insn = emit_move_insn (mem_rtx, reg_rtx);
5886 RTX_FRAME_RELATED_P (insn) = 1;
5888 else if (!TARGET_ABICALLS
5889 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
5890 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5892 emit_move_insn (reg_rtx, mem_rtx);
5894 && regno != GP_REG_FIRST + 31
5895 && ! M16_REG_P (regno))
5896 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
5902 if (store_p || !TARGET_ABICALLS
5903 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
5904 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5908 /* The mips16 does not have an instruction to
5909 load $31, so we load $7 instead, and work
5910 things out in the caller. */
5911 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
5912 r = GP_REG_FIRST + 7;
5913 /* The mips16 sometimes needs to save $18. */
5915 && regno != GP_REG_FIRST + 31
5916 && ! M16_REG_P (regno))
5919 r = GP_REG_FIRST + 6;
5922 r = GP_REG_FIRST + 3;
5923 fprintf (file, "\tmove\t%s,%s\n",
5924 reg_names[r], reg_names[regno]);
5927 fprintf (file, "\t%s\t%s,",
5929 ? (store_p) ? "sd" : "ld"
5930 : (store_p) ? "sw" : "lw"),
5932 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5933 gp_offset - base_offset);
5934 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
5937 && regno != GP_REG_FIRST + 31
5938 && ! M16_REG_P (regno))
5939 fprintf (file, "\tmove\t%s,%s\n",
5940 reg_names[regno], reg_names[r]);
5944 gp_offset -= GET_MODE_SIZE (gpr_mode);
5948 base_reg_rtx = 0, base_offset = 0;
5950 /* Save floating point registers if needed. */
5953 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
5954 int fp_size = fp_inc * UNITS_PER_FPREG;
5956 /* Pick which pointer to use as a base register. */
5957 fp_offset = current_frame_info.fp_sp_offset;
5958 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
5960 if (fp_offset < 0 || end_offset < 0)
5961 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5962 (long) fp_offset, (long) end_offset);
5964 else if (fp_offset < 32768)
5965 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
5967 else if (base_reg_rtx != 0
5968 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
5969 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
5970 ; /* already set up for gp registers above */
5972 else if (large_reg != 0
5973 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
5974 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
5976 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5977 base_offset = large_offset;
5980 if (Pmode == DImode)
5981 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
5982 stack_pointer_rtx));
5984 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
5985 stack_pointer_rtx));
5987 RTX_FRAME_RELATED_P (insn) = 1;
5991 fprintf (file, "\t%s\t%s,%s,%s\n",
5992 Pmode == DImode ? "daddu" : "addu",
5993 reg_names[MIPS_TEMP2_REGNUM],
5994 reg_names[REGNO (large_reg)],
5995 reg_names[STACK_POINTER_REGNUM]);
6000 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
6001 base_offset = fp_offset;
6004 rtx fp_offset_rtx = GEN_INT (fp_offset);
6006 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6007 bit, so make sure that we don't emit anything that can be
6009 /* ??? There is no DImode ori immediate pattern, so we can only
6010 do this for 32 bit code. */
6011 if (large_int (fp_offset_rtx)
6012 && GET_MODE (base_reg_rtx) == SImode)
6014 insn = emit_move_insn (base_reg_rtx,
6015 GEN_INT (fp_offset & 0xffff0000));
6017 RTX_FRAME_RELATED_P (insn) = 1;
6018 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6019 GEN_INT (fp_offset & 0x0000ffff)));
6021 RTX_FRAME_RELATED_P (insn) = 1;
6025 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
6027 RTX_FRAME_RELATED_P (insn) = 1;
6031 RTX_FRAME_RELATED_P (insn) = 1;
6032 if (Pmode == DImode)
6033 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6034 stack_pointer_rtx));
6036 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6037 stack_pointer_rtx));
6039 RTX_FRAME_RELATED_P (insn) = 1;
6043 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6044 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6045 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6046 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6047 Pmode == DImode ? "daddu" : "addu",
6048 reg_names[MIPS_TEMP2_REGNUM],
6049 reg_names[MIPS_TEMP2_REGNUM],
6050 reg_names[STACK_POINTER_REGNUM]);
6054 /* This loop must iterate over the same space as its companion in
6055 compute_frame_size. */
6056 for (regno = (FP_REG_LAST - fp_inc + 1);
6057 regno >= FP_REG_FIRST;
6059 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6063 enum machine_mode sz
6064 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6065 rtx reg_rtx = gen_rtx (REG, sz, regno);
6066 rtx mem_rtx = gen_rtx (MEM, sz,
6067 gen_rtx (PLUS, Pmode, base_reg_rtx,
6070 RTX_UNCHANGING_P (mem_rtx) = 1;
6074 insn = emit_move_insn (mem_rtx, reg_rtx);
6075 RTX_FRAME_RELATED_P (insn) = 1;
6078 emit_move_insn (reg_rtx, mem_rtx);
6082 fprintf (file, "\t%s\t%s,",
6083 (TARGET_SINGLE_FLOAT
6084 ? (store_p ? "s.s" : "l.s")
6085 : (store_p ? "s.d" : "l.d")),
6087 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6088 fp_offset - base_offset);
6089 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6092 fp_offset -= fp_size;
6097 /* Set up the stack and frame (if desired) for the function. */
6100 function_prologue (file, size)
6102 int size ATTRIBUTE_UNUSED;
6104 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6107 long tsize = current_frame_info.total_size;
6109 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6111 #ifdef SDB_DEBUGGING_INFO
6112 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6113 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6116 /* In mips16 mode, we may need to generate a 32 bit to handle
6117 floating point arguments. The linker will arrange for any 32 bit
6118 functions to call this stub, which will then jump to the 16 bit
6120 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6121 && current_function_args_info.fp_code != 0)
6122 build_mips16_function_stub (file);
6124 inside_function = 1;
6126 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6127 /* Get the function name the same way that toplev.c does before calling
6128 assemble_start_function. This is needed so that the name used here
6129 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6130 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6132 if (!flag_inhibit_size_directive)
6134 fputs ("\t.ent\t", file);
6135 assemble_name (file, fnname);
6139 assemble_name (file, fnname);
6140 fputs (":\n", file);
6143 if (!flag_inhibit_size_directive)
6145 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6147 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6148 (reg_names[(frame_pointer_needed)
6149 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6150 ((frame_pointer_needed && TARGET_MIPS16)
6151 ? (tsize - current_function_outgoing_args_size)
6153 reg_names[31 + GP_REG_FIRST],
6154 current_frame_info.var_size,
6155 current_frame_info.num_gp,
6156 current_frame_info.num_fp,
6157 current_function_outgoing_args_size,
6158 current_frame_info.extra_size);
6160 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6161 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6162 current_frame_info.mask,
6163 current_frame_info.gp_save_offset,
6164 current_frame_info.fmask,
6165 current_frame_info.fp_save_offset);
6168 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6169 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6172 if (mips_entry && ! mips_can_use_return_insn ())
6174 int save16 = BITSET_P (current_frame_info.mask, 16);
6175 int save17 = BITSET_P (current_frame_info.mask, 17);
6176 int save31 = BITSET_P (current_frame_info.mask, 31);
6180 /* Look through the initial insns to see if any of them store
6181 the function parameters into the incoming parameter storage
6182 area. If they do, we delete the insn, and save the register
6183 using the entry pseudo-instruction instead. We don't try to
6184 look past a label, jump, or call. */
6185 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6187 rtx note, set, src, dest, base, offset;
6190 if (GET_CODE (insn) == CODE_LABEL
6191 || GET_CODE (insn) == JUMP_INSN
6192 || GET_CODE (insn) == CALL_INSN)
6194 if (GET_CODE (insn) != INSN)
6196 set = PATTERN (insn);
6197 if (GET_CODE (set) != SET)
6200 /* An insn storing a function parameter will still have a
6201 REG_EQUIV note on it mentioning the argument pointer. */
6202 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6203 if (note == NULL_RTX)
6205 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6208 src = SET_SRC (set);
6209 if (GET_CODE (src) != REG
6210 || REGNO (src) < GP_REG_FIRST + 4
6211 || REGNO (src) > GP_REG_FIRST + 7)
6214 dest = SET_DEST (set);
6215 if (GET_CODE (dest) != MEM)
6217 if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD)
6219 else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
6220 && REGNO (src) < GP_REG_FIRST + 7)
6224 offset = const0_rtx;
6225 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6226 if (GET_CODE (base) != REG
6227 || GET_CODE (offset) != CONST_INT)
6229 if (REGNO (base) == STACK_POINTER_REGNUM
6230 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6232 else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM
6235 + (REGNO (src) - 4) * UNITS_PER_WORD
6236 - current_function_outgoing_args_size)))
6241 /* This insn stores a parameter onto the stack, in the same
6242 location where the entry pseudo-instruction will put it.
6243 Delete the insn, and arrange to tell the entry
6244 instruction to save the register. */
6245 PUT_CODE (insn, NOTE);
6246 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6247 NOTE_SOURCE_FILE (insn) = 0;
6249 hireg = (REGNO (src)
6250 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6252 if (hireg > savearg)
6256 /* If this is a varargs function, we need to save all the
6257 registers onto the stack anyhow. */
6258 if (current_function_stdarg || current_function_varargs)
6259 savearg = GP_REG_FIRST + 7;
6261 fprintf (file, "\tentry\t");
6264 if (savearg == GP_REG_FIRST + 4)
6265 fprintf (file, "%s", reg_names[savearg]);
6267 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6268 reg_names[savearg]);
6270 if (save16 || save17)
6273 fprintf (file, ",");
6274 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6276 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6280 if (savearg > 0 || save16 || save17)
6281 fprintf (file, ",");
6282 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6284 fprintf (file, "\n");
6287 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
6289 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6291 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6292 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
6295 fprintf (file, "\t%s\t%s,%s,%ld\n",
6296 (Pmode == DImode ? "dsubu" : "subu"),
6297 sp_str, sp_str, tsize);
6298 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
6301 if (dwarf2out_do_frame ())
6302 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
6306 /* Expand the prologue into a bunch of separate insns. */
6309 mips_expand_prologue ()
6312 HOST_WIDE_INT tsize;
6315 tree fndecl = current_function_decl;
6316 tree fntype = TREE_TYPE (fndecl);
6317 tree fnargs = DECL_ARGUMENTS (fndecl);
6322 CUMULATIVE_ARGS args_so_far;
6323 rtx reg_18_save = NULL_RTX;
6325 /* If struct value address is treated as the first argument, make it so. */
6326 if (aggregate_value_p (DECL_RESULT (fndecl))
6327 && ! current_function_returns_pcc_struct
6328 && struct_value_incoming_rtx == 0)
6330 tree type = build_pointer_type (fntype);
6331 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
6333 DECL_ARG_TYPE (function_result_decl) = type;
6334 TREE_CHAIN (function_result_decl) = fnargs;
6335 fnargs = function_result_decl;
6338 /* Determine the last argument, and get its name. */
6340 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
6341 regno = GP_ARG_FIRST;
6343 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
6345 tree passed_type = DECL_ARG_TYPE (cur_arg);
6346 enum machine_mode passed_mode = TYPE_MODE (passed_type);
6349 if (TREE_ADDRESSABLE (passed_type))
6351 passed_type = build_pointer_type (passed_type);
6352 passed_mode = Pmode;
6355 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
6361 /* passed in a register, so will get homed automatically */
6362 if (GET_MODE (entry_parm) == BLKmode)
6363 words = (int_size_in_bytes (passed_type) + 3) / 4;
6365 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
6367 regno = REGNO (entry_parm) + words - 1;
6371 regno = GP_ARG_LAST+1;
6375 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
6377 next_arg = TREE_CHAIN (cur_arg);
6380 if (DECL_NAME (cur_arg))
6381 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
6387 /* In order to pass small structures by value in registers compatibly with
6388 the MIPS compiler, we need to shift the value into the high part of the
6389 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
6390 adjustments to be made as the next_arg_reg variable, so we split up the
6391 insns, and emit them separately. */
6393 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
6394 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
6396 rtvec adjust = XVEC (next_arg_reg, 0);
6397 int num = GET_NUM_ELEM (adjust);
6399 for (i = 0; i < num; i++)
6401 rtx pattern = RTVEC_ELT (adjust, i);
6402 if (GET_CODE (pattern) != SET
6403 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
6404 abort_with_insn (pattern, "Insn is not a shift");
6406 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
6407 emit_insn (pattern);
6411 tsize = compute_frame_size (get_frame_size ());
6413 /* If this function is a varargs function, store any registers that
6414 would normally hold arguments ($4 - $7) on the stack. */
6415 if ((mips_abi == ABI_32 || mips_abi == ABI_O64)
6416 && (! mips_entry || mips_can_use_return_insn ())
6417 && ((TYPE_ARG_TYPES (fntype) != 0
6418 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6421 && ((arg_name[0] == '_'
6422 && strcmp (arg_name, "__builtin_va_alist") == 0)
6423 || (arg_name[0] == 'v'
6424 && strcmp (arg_name, "va_alist") == 0)))))
6426 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
6427 rtx ptr = stack_pointer_rtx;
6429 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
6430 if (TARGET_ABICALLS)
6433 for (; regno <= GP_ARG_LAST; regno++)
6436 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
6437 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
6438 gen_rtx (REG, gpr_mode, regno));
6440 offset += GET_MODE_SIZE (gpr_mode);
6444 /* If we are using the entry pseudo instruction, it will
6445 automatically subtract 32 from the stack pointer, so we don't
6446 need to. The entry pseudo instruction is emitted by
6447 function_prologue. */
6448 if (mips_entry && ! mips_can_use_return_insn ())
6450 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
6454 /* If we are using a frame pointer with a small stack frame,
6455 we need to initialize it here since it won't be done
6457 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6459 rtx incr = GEN_INT (current_function_outgoing_args_size);
6460 if (Pmode == DImode)
6461 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6465 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6469 else if (Pmode == DImode)
6470 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6471 stack_pointer_rtx));
6473 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6474 stack_pointer_rtx));
6476 RTX_FRAME_RELATED_P (insn) = 1;
6479 /* We may need to save $18, if it is used to call a function
6480 which may return a floating point value. Set up a sequence
6481 of instructions to do so. Later on we emit them at the right
6483 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
6485 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
6486 long gp_offset, base_offset;
6488 gp_offset = current_frame_info.gp_sp_offset;
6489 if (BITSET_P (current_frame_info.mask, 16))
6490 gp_offset -= UNITS_PER_WORD;
6491 if (BITSET_P (current_frame_info.mask, 17))
6492 gp_offset -= UNITS_PER_WORD;
6493 if (BITSET_P (current_frame_info.mask, 31))
6494 gp_offset -= UNITS_PER_WORD;
6496 base_offset = tsize;
6500 emit_move_insn (reg_rtx,
6501 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
6502 emit_move_insn (gen_rtx (MEM, gpr_mode,
6503 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
6507 reg_18_save = gen_sequence ();
6516 if (reg_18_save != NULL_RTX)
6517 emit_insn (reg_18_save);
6523 rtx tsize_rtx = GEN_INT (tsize);
6525 /* If we are doing svr4-abi, sp move is done by
6526 function_prologue. In mips16 mode with a large frame, we
6527 save the registers before adjusting the stack. */
6528 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
6529 && (!TARGET_MIPS16 || tsize <= 32767))
6535 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
6537 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6538 bit, so make sure that we don't emit anything that can be
6540 /* ??? There is no DImode ori immediate pattern, so we can only
6541 do this for 32 bit code. */
6542 if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode)
6544 insn = emit_move_insn (tmp_rtx,
6545 GEN_INT (tsize & 0xffff0000));
6546 RTX_FRAME_RELATED_P (insn) = 1;
6547 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
6548 GEN_INT (tsize & 0x0000ffff)));
6549 RTX_FRAME_RELATED_P (insn) = 1;
6553 insn = emit_move_insn (tmp_rtx, tsize_rtx);
6554 RTX_FRAME_RELATED_P (insn) = 1;
6557 tsize_rtx = tmp_rtx;
6560 if (Pmode == DImode)
6561 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
6564 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
6567 RTX_FRAME_RELATED_P (insn) = 1;
6571 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
6572 else if (reg_18_save != NULL_RTX)
6573 emit_insn (reg_18_save);
6575 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
6581 if (!frame_pointer_needed)
6584 reg_rtx = gen_rtx (REG, Pmode, 3);
6585 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6586 emit_move_insn (reg_rtx, tsize_rtx);
6587 if (Pmode == DImode)
6588 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
6589 hard_frame_pointer_rtx,
6592 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
6593 hard_frame_pointer_rtx,
6595 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6598 if (frame_pointer_needed)
6602 /* On the mips16, we encourage the use of unextended
6603 instructions when using the frame pointer by pointing the
6604 frame pointer ahead of the argument space allocated on
6606 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
6610 /* In this case, we have already copied the stack
6611 pointer into the frame pointer, above. We need only
6612 adjust for the outgoing argument size. */
6613 if (current_function_outgoing_args_size != 0)
6615 rtx incr = GEN_INT (current_function_outgoing_args_size);
6616 if (Pmode == DImode)
6617 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6618 hard_frame_pointer_rtx,
6621 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6622 hard_frame_pointer_rtx,
6626 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6628 rtx incr = GEN_INT (current_function_outgoing_args_size);
6629 if (Pmode == DImode)
6630 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6634 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6638 else if (Pmode == DImode)
6639 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6640 stack_pointer_rtx));
6642 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6643 stack_pointer_rtx));
6646 RTX_FRAME_RELATED_P (insn) = 1;
6649 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
6650 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
6651 gen_rtx (REG, DImode, 25)));
6654 /* If we are profiling, make sure no instructions are scheduled before
6655 the call to mcount. */
6657 if (profile_flag || profile_block_flag)
6658 emit_insn (gen_blockage ());
6661 /* Do any necessary cleanup after a function to restore stack, frame,
6664 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
6665 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6668 function_epilogue (file, size)
6669 FILE *file ATTRIBUTE_UNUSED;
6670 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6674 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6675 /* Get the function name the same way that toplev.c does before calling
6676 assemble_start_function. This is needed so that the name used here
6677 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6678 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6680 if (!flag_inhibit_size_directive)
6682 fputs ("\t.end\t", file);
6683 assemble_name (file, fnname);
6690 int num_gp_regs = current_frame_info.gp_reg_size / 4;
6691 int num_fp_regs = current_frame_info.fp_reg_size / 8;
6692 int num_regs = num_gp_regs + num_fp_regs;
6693 char *name = fnname;
6698 dslots_load_total += num_regs;
6701 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
6702 name, frame_pointer_needed ? 'y' : 'n',
6703 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
6704 current_function_calls_alloca ? 'y' : 'n',
6705 current_function_calls_setjmp ? 'y' : 'n',
6706 current_frame_info.total_size,
6707 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
6708 dslots_load_total, dslots_load_filled,
6709 dslots_jump_total, dslots_jump_filled,
6710 num_refs[0], num_refs[1], num_refs[2]);
6712 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
6715 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
6716 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
6719 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
6722 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
6723 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
6726 fputc ('\n', stderr);
6729 /* Reset state info for each function. */
6730 inside_function = 0;
6731 ignore_line_number = 0;
6732 dslots_load_total = 0;
6733 dslots_jump_total = 0;
6734 dslots_load_filled = 0;
6735 dslots_jump_filled = 0;
6741 current_frame_info = zero_frame_info;
6743 while (string_constants != NULL)
6745 struct string_constant *next;
6747 next = string_constants->next;
6748 free (string_constants);
6749 string_constants = next;
6752 /* Restore the output file if optimizing the GP (optimizing the GP causes
6753 the text to be diverted to a tempfile, so that data decls come before
6754 references to the data). */
6756 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
6757 asm_out_file = asm_out_data_file;
6760 /* Expand the epilogue into a bunch of separate insns. */
6763 mips_expand_epilogue ()
6765 HOST_WIDE_INT tsize = current_frame_info.total_size;
6766 rtx tsize_rtx = GEN_INT (tsize);
6767 rtx tmp_rtx = (rtx)0;
6769 if (mips_can_use_return_insn ())
6771 emit_insn (gen_return ());
6775 if (mips_entry && ! mips_can_use_return_insn ())
6778 if (tsize > 32767 && ! TARGET_MIPS16)
6780 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
6781 emit_move_insn (tmp_rtx, tsize_rtx);
6782 tsize_rtx = tmp_rtx;
6787 long orig_tsize = tsize;
6789 if (frame_pointer_needed)
6791 emit_insn (gen_blockage ());
6793 /* On the mips16, the frame pointer is offset from the stack
6794 pointer by current_function_outgoing_args_size. We
6795 account for that by changing tsize. Note that this can
6796 actually make tsize negative. */
6799 tsize -= current_function_outgoing_args_size;
6801 /* If we have a large frame, it's easier to add to $17
6802 than to $sp, since the mips16 has no instruction to
6803 add a register to $sp. */
6804 if (orig_tsize > 32767)
6806 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
6808 emit_move_insn (g6_rtx, GEN_INT (tsize));
6809 if (Pmode == DImode)
6810 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6811 hard_frame_pointer_rtx,
6814 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6815 hard_frame_pointer_rtx,
6820 if (tsize && tsize != orig_tsize)
6821 tsize_rtx = GEN_INT (tsize);
6824 if (Pmode == DImode)
6825 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
6827 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
6830 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
6831 are going to restore it, then we must emit a blockage insn to
6832 prevent the scheduler from moving the restore out of the epilogue. */
6833 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
6834 && (current_frame_info.mask
6835 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
6836 emit_insn (gen_blockage ());
6838 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
6840 /* In mips16 mode with a large frame, we adjust the stack
6841 pointer before restoring the registers. In this case, we
6842 should always be using a frame pointer, so everything should
6843 have been handled above. */
6844 if (tsize > 32767 && TARGET_MIPS16)
6847 emit_insn (gen_blockage ());
6848 if (Pmode == DImode && tsize != 0)
6849 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
6851 else if (tsize != 0)
6852 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6856 /* The mips16 loads the return address into $7, not $31. */
6857 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
6858 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6859 GP_REG_FIRST + 7)));
6861 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6862 GP_REG_FIRST + 31)));
6865 /* Return nonzero if this function is known to have a null epilogue.
6866 This allows the optimizer to omit jumps to jumps if no stack
6870 mips_can_use_return_insn ()
6872 if (! reload_completed)
6875 if (regs_ever_live[31] || profile_flag)
6878 /* In mips16 mode, a function which returns a floating point value
6879 needs to arrange to copy the return value into the floating point
6882 && mips16_hard_float
6883 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6884 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6886 && (! TARGET_SINGLE_FLOAT
6887 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6891 if (current_frame_info.initialized)
6892 return current_frame_info.total_size == 0;
6894 return compute_frame_size (get_frame_size ()) == 0;
6897 /* Choose the section to use for the constant rtx expression X that has
6901 mips_select_rtx_section (mode, x)
6902 enum machine_mode mode;
6903 rtx x ATTRIBUTE_UNUSED;
6907 /* In mips16 mode, the constant table always goes in the same section
6908 as the function, so that constants can be loaded using PC relative
6910 function_section (current_function_decl);
6912 else if (TARGET_EMBEDDED_DATA)
6914 /* For embedded applications, always put constants in read-only data,
6915 in order to reduce RAM usage. */
6916 READONLY_DATA_SECTION ();
6920 /* For hosted applications, always put constants in small data if
6921 possible, as this gives the best performance. */
6923 if (GET_MODE_SIZE (mode) <= mips_section_threshold
6924 && mips_section_threshold > 0)
6925 SMALL_DATA_SECTION ();
6927 READONLY_DATA_SECTION ();
6931 /* Choose the section to use for DECL. RELOC is true if its value contains
6932 any relocatable expression.
6934 Some of the logic used here needs to be replicated in
6935 ENCODE_SECTION_INFO in mips.h so that references to these symbols
6936 are done correctly. Specifically, at least all symbols assigned
6937 here to rom (.text and/or .rodata) must not be referenced via
6938 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
6940 If you need to make a change here, you probably should check
6941 ENCODE_SECTION_INFO to see if it needs a similar change. */
6944 mips_select_section (decl, reloc)
6948 int size = int_size_in_bytes (TREE_TYPE (decl));
6950 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
6951 && TREE_CODE (decl) == STRING_CST
6952 && !flag_writable_strings)
6953 /* For embedded position independent code, put constant strings in the
6954 text section, because the data section is limited to 64K in size.
6955 For mips16 code, put strings in the text section so that a PC
6956 relative load instruction can be used to get their address. */
6958 else if (TARGET_EMBEDDED_DATA)
6960 /* For embedded applications, always put an object in read-only data
6961 if possible, in order to reduce RAM usage. */
6963 if (((TREE_CODE (decl) == VAR_DECL
6964 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
6965 && DECL_INITIAL (decl)
6966 && (DECL_INITIAL (decl) == error_mark_node
6967 || TREE_CONSTANT (DECL_INITIAL (decl))))
6968 /* Deal with calls from output_constant_def_contents. */
6969 || (TREE_CODE (decl) != VAR_DECL
6970 && (TREE_CODE (decl) != STRING_CST
6971 || !flag_writable_strings)))
6972 && ! (flag_pic && reloc))
6973 READONLY_DATA_SECTION ();
6974 else if (size > 0 && size <= mips_section_threshold)
6975 SMALL_DATA_SECTION ();
6981 /* For hosted applications, always put an object in small data if
6982 possible, as this gives the best performance. */
6984 if (size > 0 && size <= mips_section_threshold)
6985 SMALL_DATA_SECTION ();
6986 else if (((TREE_CODE (decl) == VAR_DECL
6987 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
6988 && DECL_INITIAL (decl)
6989 && (DECL_INITIAL (decl) == error_mark_node
6990 || TREE_CONSTANT (DECL_INITIAL (decl))))
6991 /* Deal with calls from output_constant_def_contents. */
6992 || (TREE_CODE (decl) != VAR_DECL
6993 && (TREE_CODE (decl) != STRING_CST
6994 || !flag_writable_strings)))
6995 && ! (flag_pic && reloc))
6996 READONLY_DATA_SECTION ();
7002 #ifdef MIPS_ABI_DEFAULT
7004 /* Support functions for the 64 bit ABI. */
7006 /* Return register to use for a function return value with VALTYPE for function
7010 mips_function_value (valtype, func)
7012 tree func ATTRIBUTE_UNUSED;
7014 int reg = GP_RETURN;
7015 enum machine_mode mode = TYPE_MODE (valtype);
7016 enum mode_class mclass = GET_MODE_CLASS (mode);
7017 int unsignedp = TREE_UNSIGNED (valtype);
7019 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7020 just as PROMOTE_MODE does. */
7021 mode = promote_mode (valtype, mode, &unsignedp, 1);
7023 /* ??? How should we return complex float? */
7024 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
7026 if (TARGET_SINGLE_FLOAT
7027 && (mclass == MODE_FLOAT
7028 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7034 else if (TREE_CODE (valtype) == RECORD_TYPE
7035 && mips_abi != ABI_32
7036 && mips_abi != ABI_O64
7037 && mips_abi != ABI_EABI)
7039 /* A struct with only one or two floating point fields is returned in
7040 the floating point registers. */
7041 tree field, fields[2];
7044 for (i = 0, field = TYPE_FIELDS (valtype); field;
7045 field = TREE_CHAIN (field))
7047 if (TREE_CODE (field) != FIELD_DECL)
7050 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7053 fields[i++] = field;
7056 /* Must check i, so that we reject structures with no elements. */
7061 /* The structure has DImode, but we don't allow DImode values
7062 in FP registers, so we use a PARALLEL even though it isn't
7063 strictly necessary. */
7064 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7066 return gen_rtx (PARALLEL, mode,
7068 gen_rtx (EXPR_LIST, VOIDmode,
7069 gen_rtx (REG, field_mode,
7076 enum machine_mode first_mode
7077 = TYPE_MODE (TREE_TYPE (fields[0]));
7078 enum machine_mode second_mode
7079 = TYPE_MODE (TREE_TYPE (fields[1]));
7081 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
7083 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
7085 return gen_rtx (PARALLEL, mode,
7087 gen_rtx (EXPR_LIST, VOIDmode,
7088 gen_rtx (REG, first_mode,
7090 GEN_INT (first_offset
7092 gen_rtx (EXPR_LIST, VOIDmode,
7093 gen_rtx (REG, second_mode,
7095 GEN_INT (second_offset
7096 / BITS_PER_UNIT))));
7101 return gen_rtx (REG, mode, reg);
7104 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7105 nonzero when an argument must be passed by reference. */
7108 function_arg_pass_by_reference (cum, mode, type, named)
7109 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
7110 enum machine_mode mode;
7112 int named ATTRIBUTE_UNUSED;
7116 if (mips_abi != ABI_EABI)
7119 /* ??? How should SCmode be handled? */
7120 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7123 size = int_size_in_bytes (type);
7124 return size == -1 || size > UNITS_PER_WORD;
7128 /* This function returns the register class required for a secondary
7129 register when copying between one of the registers in CLASS, and X,
7130 using MODE. If IN_P is nonzero, the copy is going from X to the
7131 register, otherwise the register is the source. A return value of
7132 NO_REGS means that no secondary register is required. */
7135 mips_secondary_reload_class (class, mode, x, in_p)
7136 enum reg_class class;
7137 enum machine_mode mode;
7141 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7145 if (GET_CODE (x) == SIGN_EXTEND)
7151 /* We may be called with reg_renumber NULL from regclass.
7152 ??? This is probably a bug. */
7154 regno = true_regnum (x);
7157 while (GET_CODE (x) == SUBREG)
7159 off += SUBREG_WORD (x);
7163 if (GET_CODE (x) == REG)
7164 regno = REGNO (x) + off;
7168 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7169 regno = true_regnum (x);
7171 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7173 /* We always require a general register when copying anything to
7174 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7175 to a general register, or when copying from register 0. */
7176 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
7179 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7180 ? NO_REGS : gr_regs);
7181 else if (regno == HILO_REGNUM)
7184 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7185 ? NO_REGS : gr_regs);
7187 /* Copying from HI or LO to anywhere other than a general register
7188 requires a general register. */
7189 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7191 if (TARGET_MIPS16 && in_p)
7193 /* We can't really copy to HI or LO at all in mips16 mode. */
7196 return gp_reg_p ? NO_REGS : gr_regs;
7198 if (MD_REG_P (regno))
7200 if (TARGET_MIPS16 && ! in_p)
7202 /* We can't really copy to HI or LO at all in mips16 mode. */
7205 return class == gr_regs ? NO_REGS : gr_regs;
7208 /* We can only copy a value to a condition code register from a
7209 floating point register, and even then we require a scratch
7210 floating point register. We can only copy a value out of a
7211 condition code register into a general register. */
7212 if (class == ST_REGS)
7216 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
7218 if (ST_REG_P (regno))
7222 return class == GR_REGS ? NO_REGS : GR_REGS;
7225 /* In mips16 mode, going between memory and anything but M16_REGS
7226 requires an M16_REG. */
7229 if (class != M16_REGS && class != M16_NA_REGS)
7237 /* The stack pointer isn't a valid operand to an add instruction,
7238 so we need to load it into M16_REGS first. This can happen as
7239 a result of register elimination and form_sum converting
7240 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
7241 need an extra register if the dest is the same as the other
7242 register. In that case, we can't fix the problem by loading SP
7243 into the dest first. */
7244 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
7245 && GET_CODE (XEXP (x, 1)) == REG
7246 && (XEXP (x, 0) == stack_pointer_rtx
7247 || XEXP (x, 1) == stack_pointer_rtx))
7248 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
7250 if (class == M16_REGS || class == M16_NA_REGS)
7259 /* For each mips16 function which refers to GP relative symbols, we
7260 use a pseudo register, initialized at the start of the function, to
7261 hold the $gp value. */
7264 mips16_gp_pseudo_reg ()
7266 if (mips16_gp_pseudo_rtx == NULL_RTX)
7271 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7272 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
7274 /* We want to initialize this to a value which gcc will believe
7276 const_gp = gen_rtx (CONST, Pmode,
7277 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
7280 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
7281 insn = gen_sequence ();
7284 push_topmost_sequence ();
7285 /* We need to emit the initialization after the FUNCTION_BEG
7286 note, so that it will be integrated. */
7287 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7288 if (GET_CODE (scan) == NOTE
7289 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7291 if (scan == NULL_RTX)
7292 scan = get_insns ();
7293 insn = emit_insn_after (insn, scan);
7294 pop_topmost_sequence ();
7297 return mips16_gp_pseudo_rtx;
7300 /* Return an RTX which represents the signed 16 bit offset from the
7301 $gp register for the given symbol. This is only used on the
7305 mips16_gp_offset (sym)
7310 if (GET_CODE (sym) != SYMBOL_REF
7311 || ! SYMBOL_REF_FLAG (sym))
7314 /* We use a special identifier to represent the value of the gp
7316 gp = get_identifier ("__mips16_gp_value");
7318 return gen_rtx (CONST, Pmode,
7319 gen_rtx (MINUS, Pmode, sym,
7320 gen_rtx (SYMBOL_REF, Pmode,
7321 IDENTIFIER_POINTER (gp))));
7324 /* Return nonzero if the given RTX represents a signed 16 bit offset
7325 from the $gp register. */
7328 mips16_gp_offset_p (x)
7331 if (GET_CODE (x) == CONST)
7334 /* It's OK to add a small integer value to a gp offset. */
7335 if (GET_CODE (x) == PLUS)
7337 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7338 && SMALL_INT (XEXP (x, 1)))
7339 return mips16_gp_offset_p (XEXP (x, 0));
7340 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7341 && SMALL_INT (XEXP (x, 0)))
7342 return mips16_gp_offset_p (XEXP (x, 1));
7346 /* Make sure it is in the form SYM - __mips16_gp_value. */
7347 return (GET_CODE (x) == MINUS
7348 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
7349 && SYMBOL_REF_FLAG (XEXP (x, 0))
7350 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7351 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
7354 /* Output a GP offset. We don't want to print the subtraction of
7355 __mips16_gp_value; it is implicitly represented by the %gprel which
7356 should have been printed by the caller. */
7359 mips16_output_gp_offset (file, x)
7363 if (GET_CODE (x) == CONST)
7366 if (GET_CODE (x) == PLUS)
7368 mips16_output_gp_offset (file, XEXP (x, 0));
7370 mips16_output_gp_offset (file, XEXP (x, 1));
7374 if (GET_CODE (x) == MINUS
7375 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7376 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
7378 mips16_output_gp_offset (file, XEXP (x, 0));
7382 output_addr_const (file, x);
7385 /* Return nonzero if a constant should not be output until after the
7386 function. This is true of most string constants, so that we can
7387 use a more efficient PC relative reference. However, a static
7388 inline function may never call assemble_function_end to write out
7389 the constant pool, so don't try to postpone the constant in that
7392 ??? It's really a bug that a static inline function can put stuff
7393 in the constant pool even if the function itself is not output.
7395 We record which string constants we've seen, so that we know which
7396 ones might use the more efficient reference. */
7399 mips16_constant_after_function_p (x)
7402 if (TREE_CODE (x) == STRING_CST
7403 && ! flag_writable_strings
7404 && current_function_decl != 0
7405 && ! DECL_DEFER_OUTPUT (current_function_decl)
7406 && ! (DECL_INLINE (current_function_decl)
7407 && ((! TREE_PUBLIC (current_function_decl)
7408 && ! TREE_ADDRESSABLE (current_function_decl)
7409 && ! flag_keep_inline_functions)
7410 || DECL_EXTERNAL (current_function_decl))))
7412 struct string_constant *n;
7414 n = (struct string_constant *) xmalloc (sizeof *n);
7415 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
7416 n->next = string_constants;
7417 string_constants = n;
7425 /* Validate a constant for the mips16. This rejects general symbolic
7426 addresses, which must be loaded from memory. If ADDR is nonzero,
7427 this should reject anything which is not a legal address. If
7428 ADDEND is nonzero, this is being added to something else. */
7431 mips16_constant (x, mode, addr, addend)
7433 enum machine_mode mode;
7437 while (GET_CODE (x) == CONST)
7440 switch (GET_CODE (x))
7446 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
7447 && mips16_constant (XEXP (x, 1), mode, addr, 1));
7450 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7452 if (CONSTANT_POOL_ADDRESS_P (x))
7455 /* If we aren't looking for a memory address, we can accept a GP
7456 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
7457 knows how to handle this. We can always accept a string
7458 constant, which is the other case in which SYMBOL_REF_FLAG
7460 if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode)
7463 /* We can accept a string constant, which will have
7464 SYMBOL_REF_FLAG set but must be recognized by name to
7465 distinguish from a GP accessible symbol. The name of a
7466 string constant will have been generated by
7467 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
7468 if (SYMBOL_REF_FLAG (x))
7470 char *name = XSTR (x, 0);
7472 return (name[0] == '*'
7473 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
7474 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
7480 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7485 if (addr && ! addend)
7487 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
7490 /* We need to treat $gp as a legitimate constant, because
7491 mips16_gp_pseudo_reg assumes that. */
7492 return REGNO (x) == GP_REG_FIRST + 28;
7496 /* Write out code to move floating point arguments in or out of
7497 general registers. Output the instructions to FILE. FP_CODE is
7498 the code describing which arguments are present (see the comment at
7499 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
7500 we are copying from the floating point registers. */
7503 mips16_fp_args (file, fp_code, from_fp_p)
7512 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7513 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
7520 gparg = GP_ARG_FIRST;
7521 fparg = FP_ARG_FIRST;
7522 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7526 if ((fparg & 1) != 0)
7528 fprintf (file, "\t%s\t%s,%s\n", s,
7529 reg_names[gparg], reg_names[fparg]);
7531 else if ((f & 3) == 2)
7534 fprintf (file, "\td%s\t%s,%s\n", s,
7535 reg_names[gparg], reg_names[fparg]);
7538 if ((fparg & 1) != 0)
7540 if (TARGET_BIG_ENDIAN)
7541 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7542 reg_names[gparg], reg_names[fparg + 1], s,
7543 reg_names[gparg + 1], reg_names[fparg]);
7545 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7546 reg_names[gparg], reg_names[fparg], s,
7547 reg_names[gparg + 1], reg_names[fparg + 1]);
7560 /* Build a mips16 function stub. This is used for functions which
7561 take aruments in the floating point registers. It is 32 bit code
7562 that moves the floating point args into the general registers, and
7563 then jumps to the 16 bit code. */
7566 build_mips16_function_stub (file)
7570 char *secname, *stubname;
7571 tree stubid, stubdecl;
7575 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7576 secname = (char *) alloca (strlen (fnname) + 20);
7577 sprintf (secname, ".mips16.fn.%s", fnname);
7578 stubname = (char *) alloca (strlen (fnname) + 20);
7579 sprintf (stubname, "__fn_stub_%s", fnname);
7580 stubid = get_identifier (stubname);
7581 stubdecl = build_decl (FUNCTION_DECL, stubid,
7582 build_function_type (void_type_node, NULL_TREE));
7583 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7585 fprintf (file, "\t# Stub function for %s (", current_function_name);
7587 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7589 fprintf (file, "%s%s",
7590 need_comma ? ", " : "",
7591 (f & 3) == 1 ? "float" : "double");
7594 fprintf (file, ")\n");
7596 fprintf (file, "\t.set\tnomips16\n");
7597 function_section (stubdecl);
7598 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7600 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7601 within a .ent, and we can not emit another .ent. */
7602 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7603 fputs ("\t.ent\t", file);
7604 assemble_name (file, stubname);
7608 assemble_name (file, stubname);
7609 fputs (":\n", file);
7611 /* We don't want the assembler to insert any nops here. */
7612 fprintf (file, "\t.set\tnoreorder\n");
7614 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7616 fprintf (asm_out_file, "\t.set\tnoat\n");
7617 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7618 assemble_name (file, fnname);
7619 fprintf (file, "\n");
7620 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7621 fprintf (asm_out_file, "\t.set\tat\n");
7623 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7624 with one of the mfc1 instructions, because the result is not
7625 available for one instruction, so if the very first instruction
7626 in the function refers to the register, it will see the wrong
7628 fprintf (file, "\tnop\n");
7630 fprintf (file, "\t.set\treorder\n");
7632 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7633 fputs ("\t.end\t", file);
7634 assemble_name (file, stubname);
7638 fprintf (file, "\t.set\tmips16\n");
7640 function_section (current_function_decl);
7643 /* We keep a list of functions for which we have already built stubs
7644 in build_mips16_call_stub. */
7648 struct mips16_stub *next;
7653 static struct mips16_stub *mips16_stubs;
7655 /* Build a call stub for a mips16 call. A stub is needed if we are
7656 passing any floating point values which should go into the floating
7657 point registers. If we are, and the call turns out to be to a 32
7658 bit function, the stub will be used to move the values into the
7659 floating point registers before calling the 32 bit function. The
7660 linker will magically adjust the function call to either the 16 bit
7661 function or the 32 bit stub, depending upon where the function call
7662 is actually defined.
7664 Similarly, we need a stub if the return value might come back in a
7665 floating point register.
7667 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
7668 (RETVAL is NULL if this is call rather than call_value). FP_CODE
7669 is the code built by function_arg. This function returns a nonzero
7670 value if it builds the call instruction itself. */
7673 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
7681 char *fnname, *secname, *stubname;
7682 struct mips16_stub *l;
7683 tree stubid, stubdecl;
7687 /* We don't need to do anything if we aren't in mips16 mode, or if
7688 we were invoked with the -msoft-float option. */
7689 if (! TARGET_MIPS16 || ! mips16_hard_float)
7692 /* Figure out whether the value might come back in a floating point
7694 fpret = (retval != 0
7695 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7696 && (! TARGET_SINGLE_FLOAT
7697 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
7699 /* We don't need to do anything if there were no floating point
7700 arguments and the value will not be returned in a floating point
7702 if (fp_code == 0 && ! fpret)
7705 if (GET_CODE (fnmem) != MEM)
7707 fn = XEXP (fnmem, 0);
7709 /* We don't need to do anything if this is a call to a special
7710 mips16 support function. */
7711 if (GET_CODE (fn) == SYMBOL_REF
7712 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7715 /* This code will only work for o32 and o64 abis. The other ABI's
7716 require more sophisticated support. */
7717 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
7720 /* We can only handle SFmode and DFmode floating point return
7722 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
7725 /* If we're calling via a function pointer, then we must always call
7726 via a stub. There are magic stubs provided in libgcc.a for each
7727 of the required cases. Each of them expects the function address
7728 to arrive in register $2. */
7730 if (GET_CODE (fn) != SYMBOL_REF)
7734 rtx stub_fn, stub_mem, insn;
7736 /* ??? If this code is modified to support other ABI's, we need
7737 to handle PARALLEL return values here. */
7739 sprintf (buf, "__mips16_call_stub_%s%d",
7741 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7744 id = get_identifier (buf);
7745 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
7746 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
7748 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
7750 if (retval == NULL_RTX)
7751 insn = gen_call_internal0 (stub_mem, arg_size,
7752 gen_rtx (REG, SImode,
7753 GP_REG_FIRST + 31));
7755 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
7756 gen_rtx (REG, SImode,
7757 GP_REG_FIRST + 31));
7758 insn = emit_call_insn (insn);
7760 /* Put the register usage information on the CALL. */
7761 if (GET_CODE (insn) != CALL_INSN)
7763 CALL_INSN_FUNCTION_USAGE (insn) =
7764 gen_rtx (EXPR_LIST, VOIDmode,
7765 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
7766 CALL_INSN_FUNCTION_USAGE (insn));
7768 /* If we are handling a floating point return value, we need to
7769 save $18 in the function prologue. Putting a note on the
7770 call will mean that regs_ever_live[$18] will be true if the
7771 call is not eliminated, and we can check that in the prologue
7774 CALL_INSN_FUNCTION_USAGE (insn) =
7775 gen_rtx (EXPR_LIST, VOIDmode,
7776 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7777 CALL_INSN_FUNCTION_USAGE (insn));
7779 /* Return 1 to tell the caller that we've generated the call
7784 /* We know the function we are going to call. If we have already
7785 built a stub, we don't need to do anything further. */
7787 fnname = XSTR (fn, 0);
7788 for (l = mips16_stubs; l != NULL; l = l->next)
7789 if (strcmp (l->name, fnname) == 0)
7794 /* Build a special purpose stub. When the linker sees a
7795 function call in mips16 code, it will check where the target
7796 is defined. If the target is a 32 bit call, the linker will
7797 search for the section defined here. It can tell which
7798 symbol this section is associated with by looking at the
7799 relocation information (the name is unreliable, since this
7800 might be a static function). If such a section is found, the
7801 linker will redirect the call to the start of the magic
7804 If the function does not return a floating point value, the
7805 special stub section is named
7808 If the function does return a floating point value, the stub
7810 .mips16.call.fp.FNNAME
7813 secname = (char *) alloca (strlen (fnname) + 40);
7814 sprintf (secname, ".mips16.call.%s%s",
7817 stubname = (char *) alloca (strlen (fnname) + 20);
7818 sprintf (stubname, "__call_stub_%s%s",
7821 stubid = get_identifier (stubname);
7822 stubdecl = build_decl (FUNCTION_DECL, stubid,
7823 build_function_type (void_type_node, NULL_TREE));
7824 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7826 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7828 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7832 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7834 fprintf (asm_out_file, "%s%s",
7835 need_comma ? ", " : "",
7836 (f & 3) == 1 ? "float" : "double");
7839 fprintf (asm_out_file, ")\n");
7841 fprintf (asm_out_file, "\t.set\tnomips16\n");
7842 assemble_start_function (stubdecl, stubname);
7844 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7845 fputs ("\t.ent\t", asm_out_file);
7846 assemble_name (asm_out_file, stubname);
7847 fputs ("\n", asm_out_file);
7849 assemble_name (asm_out_file, stubname);
7850 fputs (":\n", asm_out_file);
7853 /* We build the stub code by hand. That's the only way we can
7854 do it, since we can't generate 32 bit code during a 16 bit
7857 /* We don't want the assembler to insert any nops here. */
7858 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7860 mips16_fp_args (asm_out_file, fp_code, 0);
7864 fprintf (asm_out_file, "\t.set\tnoat\n");
7865 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7867 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7868 fprintf (asm_out_file, "\t.set\tat\n");
7869 /* Unfortunately, we can't fill the jump delay slot. We
7870 can't fill with one of the mtc1 instructions, because the
7871 result is not available for one instruction, so if the
7872 very first instruction in the function refers to the
7873 register, it will see the wrong value. */
7874 fprintf (asm_out_file, "\tnop\n");
7878 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7879 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7880 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7881 /* As above, we can't fill the delay slot. */
7882 fprintf (asm_out_file, "\tnop\n");
7883 if (GET_MODE (retval) == SFmode)
7884 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7885 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7888 if (TARGET_BIG_ENDIAN)
7890 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7891 reg_names[GP_REG_FIRST + 2],
7892 reg_names[FP_REG_FIRST + 1]);
7893 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7894 reg_names[GP_REG_FIRST + 3],
7895 reg_names[FP_REG_FIRST + 0]);
7899 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7900 reg_names[GP_REG_FIRST + 2],
7901 reg_names[FP_REG_FIRST + 0]);
7902 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7903 reg_names[GP_REG_FIRST + 3],
7904 reg_names[FP_REG_FIRST + 1]);
7907 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7908 /* As above, we can't fill the delay slot. */
7909 fprintf (asm_out_file, "\tnop\n");
7912 fprintf (asm_out_file, "\t.set\treorder\n");
7914 #ifdef ASM_DECLARE_FUNCTION_SIZE
7915 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7918 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7919 fputs ("\t.end\t", asm_out_file);
7920 assemble_name (asm_out_file, stubname);
7921 fputs ("\n", asm_out_file);
7924 fprintf (asm_out_file, "\t.set\tmips16\n");
7926 /* Record this stub. */
7927 l = (struct mips16_stub *) xmalloc (sizeof *l);
7928 l->name = (char *) xmalloc (strlen (fnname) + 1);
7929 strcpy (l->name, fnname);
7931 l->next = mips16_stubs;
7935 /* If we expect a floating point return value, but we've built a
7936 stub which does not expect one, then we're in trouble. We can't
7937 use the existing stub, because it won't handle the floating point
7938 value. We can't build a new stub, because the linker won't know
7939 which stub to use for the various calls in this object file.
7940 Fortunately, this case is illegal, since it means that a function
7941 was declared in two different ways in a single compilation. */
7942 if (fpret && ! l->fpret)
7943 error ("can not handle inconsistent calls to `%s'", fnname);
7945 /* If we are calling a stub which handles a floating point return
7946 value, we need to arrange to save $18 in the prologue. We do
7947 this by marking the function call as using the register. The
7948 prologue will later see that it is used, and emit code to save
7955 if (retval == NULL_RTX)
7956 insn = gen_call_internal0 (fnmem, arg_size,
7957 gen_rtx (REG, SImode,
7958 GP_REG_FIRST + 31));
7960 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
7961 gen_rtx (REG, SImode,
7962 GP_REG_FIRST + 31));
7963 insn = emit_call_insn (insn);
7965 if (GET_CODE (insn) != CALL_INSN)
7968 CALL_INSN_FUNCTION_USAGE (insn) =
7969 gen_rtx (EXPR_LIST, VOIDmode,
7970 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7971 CALL_INSN_FUNCTION_USAGE (insn));
7973 /* Return 1 to tell the caller that we've generated the call
7978 /* Return 0 to let the caller generate the call insn. */
7982 /* This function looks through the code for a function, and tries to
7983 optimize the usage of the $gp register. We arrange to copy $gp
7984 into a pseudo-register, and then let gcc's normal reload handling
7985 deal with the pseudo-register. Unfortunately, if reload choose to
7986 put the pseudo-register into a call-clobbered register, it will
7987 emit saves and restores for that register around any function
7988 calls. We don't need the saves, and it's faster to copy $gp than
7989 to do an actual restore. ??? This still means that we waste a
7992 This is an optimization, and the code which gcc has actually
7993 generated is correct, so we do not need to catch all cases. */
7996 mips16_optimize_gp (first)
7999 rtx gpcopy, slot, insn;
8001 /* Look through the instructions. Set GPCOPY to the register which
8002 holds a copy of $gp. Set SLOT to the stack slot where it is
8003 saved. If we find an instruction which sets GPCOPY to anything
8004 other than $gp or SLOT, then we can't use it. If we find an
8005 instruction which sets SLOT to anything other than GPCOPY, we
8010 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8014 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8017 set = PATTERN (insn);
8019 /* We know that all references to memory will be inside a SET,
8020 because there is no other way to access memory on the mips16.
8021 We don't have to worry about a PARALLEL here, because the
8022 mips.md file will never generate them for memory references. */
8023 if (GET_CODE (set) != SET)
8026 if (gpcopy == NULL_RTX
8027 && GET_CODE (SET_SRC (set)) == CONST
8028 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8029 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8030 && GET_CODE (SET_DEST (set)) == REG
8031 && GET_MODE (SET_DEST (set)) == Pmode)
8032 gpcopy = SET_DEST (set);
8033 else if (slot == NULL_RTX
8034 && gpcopy != NULL_RTX
8035 && GET_CODE (SET_DEST (set)) == MEM
8036 && GET_CODE (SET_SRC (set)) == REG
8037 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8038 && GET_MODE (SET_DEST (set)) == Pmode)
8042 offset = const0_rtx;
8043 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8044 if (GET_CODE (base) == REG
8045 && (REGNO (base) == STACK_POINTER_REGNUM
8046 || REGNO (base) == FRAME_POINTER_REGNUM))
8047 slot = SET_DEST (set);
8049 else if (gpcopy != NULL_RTX
8050 && (GET_CODE (SET_DEST (set)) == REG
8051 || GET_CODE (SET_DEST (set)) == SUBREG)
8052 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8053 && (GET_CODE (SET_DEST (set)) != REG
8054 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8055 || GET_MODE (SET_DEST (set)) != Pmode
8056 || ((GET_CODE (SET_SRC (set)) != CONST
8057 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8058 || (REGNO (XEXP (SET_SRC (set), 0))
8059 != GP_REG_FIRST + 28))
8060 && ! rtx_equal_p (SET_SRC (set), slot))))
8062 else if (slot != NULL_RTX
8063 && GET_CODE (SET_DEST (set)) == MEM
8064 && rtx_equal_p (SET_DEST (set), slot)
8065 && (GET_CODE (SET_SRC (set)) != REG
8066 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8070 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8071 different optimization. Any time we find a copy of $28 into a
8072 register, followed by an add of a symbol_ref to that register, we
8073 convert it to load the value from the constant table instead.
8074 The copy and add will take six bytes, just as the load and
8075 constant table entry will take six bytes. However, it is
8076 possible that the constant table entry will be shared.
8078 This could be a peephole optimization, but I don't know if the
8079 peephole code can call force_const_mem.
8081 Using the same register for the copy of $28 and the add of the
8082 symbol_ref is actually pretty likely, since the add instruction
8083 requires the destination and the first addend to be the same
8086 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8090 /* This optimization is only reasonable if the constant table
8091 entries are only 4 bytes. */
8092 if (Pmode != SImode)
8095 for (insn = first; insn != NULL_RTX; insn = next)
8102 next = NEXT_INSN (next);
8104 while (next != NULL_RTX
8105 && (GET_CODE (next) == NOTE
8106 || (GET_CODE (next) == INSN
8107 && (GET_CODE (PATTERN (next)) == USE
8108 || GET_CODE (PATTERN (next)) == CLOBBER))));
8110 if (next == NULL_RTX)
8113 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8116 if (GET_RTX_CLASS (GET_CODE (next)) != 'i')
8119 set1 = PATTERN (insn);
8120 if (GET_CODE (set1) != SET)
8122 set2 = PATTERN (next);
8123 if (GET_CODE (set2) != SET)
8126 if (GET_CODE (SET_DEST (set1)) == REG
8127 && GET_CODE (SET_SRC (set1)) == CONST
8128 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8129 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8130 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8131 && GET_CODE (SET_SRC (set2)) == PLUS
8132 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8133 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8134 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8138 /* We've found a case we can change to load from the
8141 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8142 if (GET_CODE (sym) != SYMBOL_REF)
8144 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8145 force_const_mem (Pmode, sym)),
8148 PUT_CODE (insn, NOTE);
8149 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8150 NOTE_SOURCE_FILE (insn) = 0;
8152 PUT_CODE (next, NOTE);
8153 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8154 NOTE_SOURCE_FILE (next) = 0;
8161 /* We can safely remove all assignments to SLOT from GPCOPY, and
8162 replace all assignments from SLOT to GPCOPY with assignments from
8165 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8169 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8172 set = PATTERN (insn);
8173 if (GET_CODE (set) != SET
8174 || GET_MODE (SET_DEST (set)) != Pmode)
8177 if (GET_CODE (SET_DEST (set)) == MEM
8178 && rtx_equal_p (SET_DEST (set), slot)
8179 && GET_CODE (SET_SRC (set)) == REG
8180 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8182 PUT_CODE (insn, NOTE);
8183 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8184 NOTE_SOURCE_FILE (insn) = 0;
8186 else if (GET_CODE (SET_DEST (set)) == REG
8187 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8188 && GET_CODE (SET_SRC (set)) == MEM
8189 && rtx_equal_p (SET_SRC (set), slot))
8191 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
8192 gen_rtx (CONST, Pmode,
8193 gen_rtx (REG, Pmode,
8194 GP_REG_FIRST + 28))),
8196 PUT_CODE (insn, NOTE);
8197 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8198 NOTE_SOURCE_FILE (insn) = 0;
8203 /* We keep a list of constants we which we have to add to internal
8204 constant tables in the middle of large functions. */
8208 struct constant *next;
8211 enum machine_mode mode;
8214 /* Add a constant to the list in *PCONSTANTS. */
8217 add_constant (pconstants, val, mode)
8218 struct constant **pconstants;
8220 enum machine_mode mode;
8224 for (c = *pconstants; c != NULL; c = c->next)
8225 if (mode == c->mode && rtx_equal_p (val, c->value))
8228 c = (struct constant *) xmalloc (sizeof *c);
8231 c->label = gen_label_rtx ();
8232 c->next = *pconstants;
8237 /* Dump out the constants in CONSTANTS after INSN. */
8240 dump_constants (constants, insn)
8241 struct constant *constants;
8252 struct constant *next;
8254 switch (GET_MODE_SIZE (c->mode))
8261 insn = emit_insn_after (gen_align_2 (), insn);
8266 insn = emit_insn_after (gen_align_4 (), insn);
8271 insn = emit_insn_after (gen_align_8 (), insn);
8276 insn = emit_label_after (c->label, insn);
8281 r = gen_consttable_qi (c->value);
8284 r = gen_consttable_hi (c->value);
8287 r = gen_consttable_si (c->value);
8290 r = gen_consttable_sf (c->value);
8293 r = gen_consttable_di (c->value);
8296 r = gen_consttable_df (c->value);
8302 insn = emit_insn_after (r, insn);
8309 emit_barrier_after (insn);
8312 /* Find the symbol in an address expression. */
8315 mips_find_symbol (addr)
8318 if (GET_CODE (addr) == MEM)
8319 addr = XEXP (addr, 0);
8320 while (GET_CODE (addr) == CONST)
8321 addr = XEXP (addr, 0);
8322 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8324 if (GET_CODE (addr) == PLUS)
8328 l1 = mips_find_symbol (XEXP (addr, 0));
8329 l2 = mips_find_symbol (XEXP (addr, 1));
8330 if (l1 != NULL_RTX && l2 == NULL_RTX)
8332 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8338 /* Exported to toplev.c.
8340 Do a final pass over the function, just before delayed branch
8344 machine_dependent_reorg (first)
8347 int insns_len, max_internal_pool_size, pool_size, addr;
8349 struct constant *constants;
8351 if (! TARGET_MIPS16)
8354 /* If $gp is used, try to remove stores, and replace loads with
8357 mips16_optimize_gp (first);
8359 /* Scan the function looking for PC relative loads which may be out
8360 of range. All such loads will either be from the constant table,
8361 or be getting the address of a constant string. If the size of
8362 the function plus the size of the constant table is less than
8363 0x8000, then all loads are in range. */
8366 for (insn = first; insn; insn = NEXT_INSN (insn))
8368 insns_len += get_attr_length (insn);
8370 /* ??? We put switch tables in .text, but we don't define
8371 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8372 compute their lengths correctly. */
8373 if (GET_CODE (insn) == JUMP_INSN)
8377 body = PATTERN (insn);
8378 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8379 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8380 * GET_MODE_SIZE (GET_MODE (body)));
8381 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8385 /* Store the original value of insns_len in current_frame_info, so
8386 that simple_memory_operand can look at it. */
8387 current_frame_info.insns_len = insns_len;
8389 pool_size = get_pool_size ();
8390 if (insns_len + pool_size + mips_string_length < 0x8000)
8393 /* Loop over the insns and figure out what the maximum internal pool
8395 max_internal_pool_size = 0;
8396 for (insn = first; insn; insn = NEXT_INSN (insn))
8398 if (GET_CODE (insn) == INSN
8399 && GET_CODE (PATTERN (insn)) == SET)
8403 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8404 if (src == NULL_RTX)
8406 if (CONSTANT_POOL_ADDRESS_P (src))
8407 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8408 else if (SYMBOL_REF_FLAG (src))
8409 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8416 for (insn = first; insn; insn = NEXT_INSN (insn))
8418 if (GET_CODE (insn) == INSN
8419 && GET_CODE (PATTERN (insn)) == SET)
8422 enum machine_mode mode;
8425 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8426 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8428 /* ??? This is very conservative, which means that we
8429 will generate too many copies of the constant table.
8430 The only solution would seem to be some form of
8432 if (((insns_len - addr)
8433 + max_internal_pool_size
8434 + get_pool_offset (src))
8437 val = get_pool_constant (src);
8438 mode = get_pool_mode (src);
8440 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8442 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8444 /* Including all of mips_string_length is conservative,
8445 and so is including all of max_internal_pool_size. */
8446 if (((insns_len - addr)
8447 + max_internal_pool_size
8449 + mips_string_length)
8453 max_internal_pool_size -= Pmode;
8456 if (val != NULL_RTX)
8460 /* This PC relative load is out of range. ??? In the
8461 case of a string constant, we are only guessing that
8462 it is range, since we don't know the offset of a
8463 particular string constant. */
8465 lab = add_constant (&constants, val, mode);
8466 newsrc = gen_rtx (MEM, mode,
8467 gen_rtx (LABEL_REF, VOIDmode, lab));
8468 RTX_UNCHANGING_P (newsrc) = 1;
8469 PATTERN (insn) = gen_rtx (SET, VOIDmode,
8470 SET_DEST (PATTERN (insn)),
8472 INSN_CODE (insn) = -1;
8476 addr += get_attr_length (insn);
8478 /* ??? We put switch tables in .text, but we don't define
8479 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8480 compute their lengths correctly. */
8481 if (GET_CODE (insn) == JUMP_INSN)
8485 body = PATTERN (insn);
8486 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8487 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8488 * GET_MODE_SIZE (GET_MODE (body)));
8489 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8492 if (GET_CODE (insn) == BARRIER)
8494 /* Output any constants we have accumulated. Note that we
8495 don't need to change ADDR, since its only use is
8496 subtraction from INSNS_LEN, and both would be changed by
8498 ??? If the instructions up to the next barrier reuse a
8499 constant, it would often be better to continue
8501 if (constants != NULL)
8502 dump_constants (constants, insn);
8506 /* ??? If we don't find a barrier within 0x8000 bytes of
8507 instructions and constants in CONSTANTS, we need to invent
8508 one. This seems sufficiently unlikely that I am not going to
8512 if (constants != NULL)
8514 rtx label, jump, barrier;
8516 label = gen_label_rtx ();
8517 jump = emit_jump_insn_after (gen_jump (label), get_last_insn ());
8518 JUMP_LABEL (jump) = label;
8519 LABEL_NUSES (label) = 1;
8520 barrier = emit_barrier_after (jump);
8521 emit_label_after (label, barrier);
8522 dump_constants (constants, barrier);
8526 /* ??? If we output all references to a constant in internal
8527 constants table, we don't need to output the constant in the real
8528 constant table, but we have no way to prevent that. */
8531 /* Return nonzero if X is a SIGN or ZERO extend operator. */
8533 extend_operator (x, mode)
8535 enum machine_mode mode ATTRIBUTE_UNUSED;
8537 enum rtx_code code = GET_CODE (x);
8538 return code == SIGN_EXTEND || code == ZERO_EXTEND;
8541 /* Accept any operator that can be used to shift the high half of the
8542 input value to the lower half, suitable for truncation. The
8543 remainder (the lower half of the input, and the upper half of the
8544 output) will be discarded. */
8546 highpart_shift_operator (x, mode)
8548 enum machine_mode mode ATTRIBUTE_UNUSED;
8550 enum rtx_code code = GET_CODE (x);
8551 return (code == LSHIFTRT
8557 /* Return the length of INSN. LENGTH is the initial length computed by
8558 attributes in the machine-description file. */
8561 mips_adjust_insn_length (insn, length)
8565 /* A unconditional jump has an unfilled delay slot if it is not part
8566 of a sequence. A conditional jump normally has a delay slot, but
8567 does not on MIPS16. */
8568 if (simplejump_p (insn)
8569 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8570 || GET_CODE (insn) == CALL_INSN)))
8573 /* All MIPS16 instructions are a measly two bytes. */
8580 /* Output assembly instructions to peform a conditional branch.
8582 INSN is the branch instruction. OPERANDS[0] is the condition.
8583 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8584 of the first operand to the condition. If TWO_OPERANDS_P is
8585 non-zero the comparison takes two operands; OPERANDS[3] will be the
8588 If INVERTED_P is non-zero we are to branch if the condition does
8589 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
8591 LENGTH is the length (in bytes) of the sequence we are to generate.
8592 That tells us whether to generate a simple conditional branch, or a
8593 reversed conditional branch around a `jr' instruction. */
8595 mips_output_conditional_branch (insn,
8608 static char buffer[200];
8609 /* The kind of comparison we are doing. */
8610 enum rtx_code code = GET_CODE (operands[0]);
8611 /* Non-zero if the opcode for the comparison needs a `z' indicating
8612 that it is a comparision against zero. */
8614 /* A string to use in the assembly output to represent the first
8617 /* A string to use in the assembly output to represent the second
8618 operand. Use the hard-wired zero register if there's no second
8620 char *op2 = (two_operands_p ? ",%z3" : ",%.");
8621 /* The operand-printing string for the comparison. */
8622 char *comp = (float_p ? "%F0" : "%C0");
8623 /* The operand-printing string for the inverted comparison. */
8624 char *inverted_comp = (float_p ? "%W0" : "%N0");
8626 /* The MIPS processors (for levels of the ISA at least two), have
8627 "likely" variants of each branch instruction. These instructions
8628 annul the instruction in the delay slot if the branch is not
8630 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8632 if (!two_operands_p)
8634 /* To compute whether than A > B, for example, we normally
8635 subtract B from A and then look at the sign bit. But, if we
8636 are doing an unsigned comparison, and B is zero, we don't
8637 have to do the subtraction. Instead, we can just check to
8638 see if A is non-zero. Thus, we change the CODE here to
8639 reflect the simpler comparison operation. */
8651 /* A condition which will always be true. */
8657 /* A condition which will always be false. */
8663 /* Not a special case. */
8667 /* Relative comparisons are always done against zero. But
8668 equality comparisons are done between two operands, and therefore
8669 do not require a `z' in the assembly language output. */
8670 need_z_p = (!float_p && code != EQ && code != NE);
8671 /* For comparisons against zero, the zero is not provided
8676 /* Begin by terminating the buffer. That way we can always use
8677 strcat to add to it. */
8684 /* Just a simple conditional branch. */
8686 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
8687 inverted_p ? inverted_comp : comp);
8689 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
8690 inverted_p ? inverted_comp : comp,
8691 need_z_p ? "z" : "",
8699 /* Generate a reversed conditional branch around ` j'
8711 Because we have to jump four bytes *past* the following
8712 instruction if this branch was annulled, we can't just use
8713 a label, as in the picture above; there's no way to put the
8714 label after the next instruction, as the assembler does not
8715 accept `.L+4' as the target of a branch. (We can't just
8716 wait until the next instruction is output; it might be a
8717 macro and take up more than four bytes. Once again, we see
8718 why we want to eliminate macros.)
8720 If the branch is annulled, we jump four more bytes that we
8721 would otherwise; that way we skip the annulled instruction
8722 in the delay slot. */
8725 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
8728 strcpy (buffer, "%(%<");
8729 c = strchr (buffer, '\0');
8730 /* Generate the reversed comparision. This takes four
8733 sprintf (c, "%%*b%s\t%%Z2%s",
8734 inverted_p ? comp : inverted_comp,
8737 sprintf (c, "%%*b%s%s\t%s%s,%s",
8738 inverted_p ? comp : inverted_comp,
8739 need_z_p ? "z" : "",
8743 strcat (c, "\n\tnop\n\tj\t%1");
8745 /* The delay slot was unfilled. Since we're inside
8746 .noreorder, the assembler will not fill in the NOP for
8747 us, so we must do it ourselves. */
8748 strcat (buffer, "\n\tnop");
8749 strcat (buffer, "%>%)");
8753 /* We do not currently use this code. It handles jumps to
8754 arbitrary locations, using `jr', even across a 256MB boundary.
8755 We could add a -mhuge switch, and then use this code instead of
8756 the `j' alternative above when -mhuge was used. */
8761 /* Generate a reversed conditional branch around a `jr'
8775 Not pretty, but allows a conditional branch anywhere in the
8776 32-bit address space. If the original branch is annulled,
8777 then the instruction in the delay slot should be executed
8778 only if the branch is taken. The la instruction is really
8779 a macro which will usually take eight bytes, but sometimes
8780 takes only four, if the instruction to which we're jumping
8781 gets its own entry in the global pointer table, which will
8782 happen if its a case label. The assembler will then
8783 generate only a four-byte sequence, rather than eight, and
8784 there seems to be no way to tell it not to. Thus, we can't
8785 just use a `.+x' addressing form; we don't know what value
8788 So, we resort to using the explicit relocation syntax
8789 available in the assembler and do:
8791 lw $at,%got_page(target)($gp)
8792 daddiu $at,$at,%got_ofst(target)
8794 That way, this always takes up eight bytes, and we can use
8795 the `.+x' form. Of course, these explicit machinations
8796 with relocation will not work with old assemblers. Then
8797 again, neither do out-of-range branches, so we haven't lost
8800 /* The target of the reversed branch. */
8802 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
8803 char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
8804 char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
8807 strcpy (buffer, "%(%<%[");
8808 c = strchr (buffer, '\0');
8809 /* Generate the reversed comparision. This takes four
8812 sprintf (c, "%%*b%s\t%%Z2%s",
8813 inverted_p ? comp : inverted_comp,
8816 sprintf (c, "%%*b%s%s\t%s%s,%s",
8817 inverted_p ? comp : inverted_comp,
8818 need_z_p ? "z" : "",
8822 c = strchr (buffer, '\0');
8823 /* Generate the load-address, and jump. This takes twelve
8824 bytes, for a total of 16. */
8826 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
8833 /* The delay slot was unfilled. Since we're inside
8834 .noreorder, the assembler will not fill in the NOP for
8835 us, so we must do it ourselves. */
8836 strcat (buffer, "\n\tnop");
8837 strcat (buffer, "%]%>%)");