1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
34 #include "hard-reg-set.h"
36 #include "insn-config.h"
37 #include "conditions.h"
38 #include "insn-flags.h"
39 #include "insn-attr.h"
40 #include "insn-codes.h"
53 #if defined(USG) || !defined(HAVE_STAB_H)
54 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
56 #include <stab.h> /* On BSD, use the system's stab.h. */
60 #define STAB_CODE_TYPE enum __stab_debug_code
62 #define STAB_CODE_TYPE int
65 extern char *mktemp ();
66 extern tree lookup_name ();
68 /* Enumeration for all of the relational tests, so that we can build
69 arrays indexed by the test type, and not worry about the order
88 static enum internal_test map_test_to_internal_test PROTO ((enum rtx_code));
89 static int mips16_simple_memory_operand PROTO ((rtx, rtx,
91 static int m16_check_op PROTO ((rtx, int, int, int));
92 static void block_move_loop PROTO ((rtx, rtx, int, int,
94 static void block_move_call PROTO ((rtx, rtx, rtx));
95 static FILE *make_temp_file PROTO ((void));
96 static void save_restore_insns PROTO ((int, rtx,
98 static void mips16_output_gp_offset PROTO ((FILE *, rtx));
99 static void mips16_fp_args PROTO ((FILE *, int, int));
100 static void build_mips16_function_stub PROTO ((FILE *));
101 static void mips16_optimize_gp PROTO ((rtx));
102 static rtx add_constant PROTO ((struct constant **,
105 static void dump_constants PROTO ((struct constant *,
107 static rtx mips_find_symbol PROTO ((rtx));
108 static void abort_with_insn PROTO ((rtx, const char *))
110 static int symbolic_expression_p PROTO ((rtx));
111 static void mips_add_gc_roots PROTO ((void));
113 /* Global variables for machine-dependent things. */
115 /* Threshold for data being put into the small data/bss area, instead
116 of the normal data area (references to the small data/bss area take
117 1 instruction, and use the global pointer, references to the normal
118 data area takes 2 instructions). */
119 int mips_section_threshold = -1;
121 /* Count the number of .file directives, so that .loc is up to date. */
122 int num_source_filenames = 0;
124 /* Count the number of sdb related labels are generated (to find block
125 start and end boundaries). */
126 int sdb_label_count = 0;
128 /* Next label # for each statement for Silicon Graphics IRIS systems. */
131 /* Non-zero if inside of a function, because the stupid MIPS asm can't
132 handle .files inside of functions. */
133 int inside_function = 0;
135 /* Files to separate the text and the data output, so that all of the data
136 can be emitted before the text, which will mean that the assembler will
137 generate smaller code, based on the global pointer. */
138 FILE *asm_out_data_file;
139 FILE *asm_out_text_file;
141 /* Linked list of all externals that are to be emitted when optimizing
142 for the global pointer if they haven't been declared by the end of
143 the program with an appropriate .comm or initialization. */
147 struct extern_list *next; /* next external */
148 char *name; /* name of the external */
149 int size; /* size in bytes */
152 /* Name of the file containing the current function. */
153 const char *current_function_file = "";
155 /* Warning given that Mips ECOFF can't support changing files
156 within a function. */
157 int file_in_function_warning = FALSE;
159 /* Whether to suppress issuing .loc's because the user attempted
160 to change the filename within a function. */
161 int ignore_line_number = FALSE;
163 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
169 /* The next branch instruction is a branch likely, not branch normal. */
170 int mips_branch_likely;
172 /* Count of delay slots and how many are filled. */
173 int dslots_load_total;
174 int dslots_load_filled;
175 int dslots_jump_total;
176 int dslots_jump_filled;
178 /* # of nops needed by previous insn */
179 int dslots_number_nops;
181 /* Number of 1/2/3 word references to data items (ie, not jal's). */
184 /* registers to check for load delay */
185 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
187 /* Cached operands, and operator to compare for use in set/branch on
191 /* what type of branch to use */
192 enum cmp_type branch_type;
194 /* Number of previously seen half-pic pointers and references. */
195 static int prev_half_pic_ptrs = 0;
196 static int prev_half_pic_refs = 0;
198 /* which cpu are we scheduling for */
199 enum processor_type mips_cpu;
201 /* which instruction set architecture to use. */
204 #ifdef MIPS_ABI_DEFAULT
205 /* Which ABI to use. This is defined to a constant in mips.h if the target
206 doesn't support multiple ABIs. */
210 /* Strings to hold which cpu and instruction set architecture to use. */
211 const char *mips_cpu_string; /* for -mcpu=<xxx> */
212 const char *mips_isa_string; /* for -mips{1,2,3,4} */
213 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
215 /* Whether we are generating mips16 code. This is a synonym for
216 TARGET_MIPS16, and exists for use as an attribute. */
219 /* This variable is set by -mno-mips16. We only care whether
220 -mno-mips16 appears or not, and using a string in this fashion is
221 just a way to avoid using up another bit in target_flags. */
222 const char *mips_no_mips16_string;
224 /* This is only used to determine if an type size setting option was
225 explicitly specified (-mlong64, -mint64, -mlong32). The specs
226 set this option if such an option is used. */
227 const char *mips_explicit_type_size_string;
229 /* Whether we are generating mips16 hard float code. In mips16 mode
230 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
231 -msoft-float was not specified by the user, which means that we
232 should arrange to call mips32 hard floating point code. */
233 int mips16_hard_float;
235 /* This variable is set by -mentry. We only care whether -mentry
236 appears or not, and using a string in this fashion is just a way to
237 avoid using up another bit in target_flags. */
238 const char *mips_entry_string;
240 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
243 /* If TRUE, we split addresses into their high and low parts in the RTL. */
244 int mips_split_addresses;
246 /* Generating calls to position independent functions? */
247 enum mips_abicalls_type mips_abicalls;
249 /* High and low marks for floating point values which we will accept
250 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
251 initialized in override_options. */
252 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
254 /* Mode used for saving/restoring general purpose registers. */
255 static enum machine_mode gpr_mode;
257 /* Array giving truth value on whether or not a given hard register
258 can support a given mode. */
259 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
261 /* Current frame information calculated by compute_frame_size. */
262 struct mips_frame_info current_frame_info;
264 /* Zero structure to initialize current_frame_info. */
265 struct mips_frame_info zero_frame_info;
267 /* Temporary filename used to buffer .text until end of program
269 static char *temp_filename;
271 /* Pseudo-reg holding the address of the current function when
272 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
273 by mips_finalize_pic if it was created. */
274 rtx embedded_pic_fnaddr_rtx;
276 /* The length of all strings seen when compiling for the mips16. This
277 is used to tell how many strings are in the constant pool, so that
278 we can see if we may have an overflow. This is reset each time the
279 constant pool is output. */
280 int mips_string_length;
282 /* Pseudo-reg holding the value of $28 in a mips16 function which
283 refers to GP relative global variables. */
284 rtx mips16_gp_pseudo_rtx;
286 /* In mips16 mode, we build a list of all the string constants we see
287 in a particular function. */
289 struct string_constant
291 struct string_constant *next;
295 static struct string_constant *string_constants;
297 /* List of all MIPS punctuation characters used by print_operand. */
298 char mips_print_operand_punct[256];
300 /* Map GCC register number to debugger register number. */
301 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
303 /* Buffer to use to enclose a load/store operation with %{ %} to
304 turn on .set volatile. */
305 static char volatile_buffer[60];
307 /* Hardware names for the registers. If -mrnames is used, this
308 will be overwritten with mips_sw_reg_names. */
310 char mips_reg_names[][8] =
312 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
313 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
314 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
315 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
316 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
317 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
318 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
319 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
320 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
321 "$fcc5","$fcc6","$fcc7","$rap"
324 /* Mips software names for the registers, used to overwrite the
325 mips_reg_names array. */
327 char mips_sw_reg_names[][8] =
329 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
330 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
331 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
332 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
333 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
334 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
335 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
336 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
337 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
338 "$fcc5","$fcc6","$fcc7","$rap"
341 /* Map hard register number to register class */
342 enum reg_class mips_regno_to_class[] =
344 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
345 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
346 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
347 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
348 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
349 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
350 T_REG, GR_REGS, GR_REGS, GR_REGS,
351 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
352 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
353 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
354 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
355 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
356 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
357 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
358 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
359 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
360 HI_REG, LO_REG, HILO_REG, ST_REGS,
361 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
362 ST_REGS, ST_REGS, ST_REGS, GR_REGS
365 /* Map register constraint character to register class. */
366 enum reg_class mips_char_to_class[256] =
368 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
369 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
370 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
371 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
431 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
435 /* Return truth value of whether OP can be used as an operands
436 where a register or 16 bit unsigned integer is needed. */
439 uns_arith_operand (op, mode)
441 enum machine_mode mode;
443 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
446 return register_operand (op, mode);
449 /* Return truth value of whether OP can be used as an operands
450 where a 16 bit integer is needed */
453 arith_operand (op, mode)
455 enum machine_mode mode;
457 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
460 /* On the mips16, a GP relative value is a signed 16 bit offset. */
461 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
464 return register_operand (op, mode);
467 /* Return truth value of whether OP can be used as an operand in a two
468 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
471 arith32_operand (op, mode)
473 enum machine_mode mode;
475 if (GET_CODE (op) == CONST_INT)
478 return register_operand (op, mode);
481 /* Return truth value of whether OP is a integer which fits in 16 bits */
486 enum machine_mode mode ATTRIBUTE_UNUSED;
488 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
491 /* Return truth value of whether OP is a 32 bit integer which is too big to
492 be loaded with one instruction. */
497 enum machine_mode mode ATTRIBUTE_UNUSED;
501 if (GET_CODE (op) != CONST_INT)
506 /* ior reg,$r0,value */
507 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
510 /* subu reg,$r0,value */
511 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
514 /* lui reg,value>>16 */
515 if ((value & 0x0000ffff) == 0)
521 /* Return truth value of whether OP is a register or the constant 0.
522 In mips16 mode, we only accept a register, since the mips16 does
526 reg_or_0_operand (op, mode)
528 enum machine_mode mode;
530 switch (GET_CODE (op))
535 return INTVAL (op) == 0;
540 return op == CONST0_RTX (mode);
544 return register_operand (op, mode);
553 /* Return truth value of whether OP is a register or the constant 0,
554 even in mips16 mode. */
557 true_reg_or_0_operand (op, mode)
559 enum machine_mode mode;
561 switch (GET_CODE (op))
564 return INTVAL (op) == 0;
567 return op == CONST0_RTX (mode);
571 return register_operand (op, mode);
580 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
583 mips_const_double_ok (op, mode)
585 enum machine_mode mode;
589 if (GET_CODE (op) != CONST_DOUBLE)
592 if (mode == VOIDmode)
595 if (mode != SFmode && mode != DFmode)
598 if (op == CONST0_RTX (mode))
601 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
602 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
605 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
607 if (REAL_VALUE_ISNAN (d))
610 if (REAL_VALUE_NEGATIVE (d))
611 d = REAL_VALUE_NEGATE (d);
615 if (REAL_VALUES_LESS (d, dfhigh)
616 && REAL_VALUES_LESS (dflow, d))
621 if (REAL_VALUES_LESS (d, sfhigh)
622 && REAL_VALUES_LESS (sflow, d))
629 /* Accept the floating point constant 1 in the appropriate mode. */
632 const_float_1_operand (op, mode)
634 enum machine_mode mode;
637 static REAL_VALUE_TYPE onedf;
638 static REAL_VALUE_TYPE onesf;
639 static int one_initialized;
641 if (GET_CODE (op) != CONST_DOUBLE
642 || mode != GET_MODE (op)
643 || (mode != DFmode && mode != SFmode))
646 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
648 /* We only initialize these values if we need them, since we will
649 never get called unless mips_isa >= 4. */
650 if (! one_initialized)
652 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
653 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
658 return REAL_VALUES_EQUAL (d, onedf);
660 return REAL_VALUES_EQUAL (d, onesf);
663 /* Return true if a memory load or store of REG plus OFFSET in MODE
664 can be represented in a single word on the mips16. */
667 mips16_simple_memory_operand (reg, offset, mode)
670 enum machine_mode mode;
676 /* We can't tell, because we don't know how the value will
677 eventually be accessed. Returning 0 here does no great
678 harm; it just prevents some possible instruction scheduling. */
682 size = GET_MODE_SIZE (mode);
684 if (INTVAL (offset) % size != 0)
686 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
690 if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size)
695 /* Return truth value if a memory operand fits in a single instruction
696 (ie, register + small offset). */
699 simple_memory_operand (op, mode)
701 enum machine_mode mode;
703 rtx addr, plus0, plus1;
705 /* Eliminate non-memory operations */
706 if (GET_CODE (op) != MEM)
709 /* dword operations really put out 2 instructions, so eliminate them. */
710 /* ??? This isn't strictly correct. It is OK to accept multiword modes
711 here, since the length attributes are being set correctly, but only
712 if the address is offsettable. LO_SUM is not offsettable. */
713 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
716 /* Decode the address now. */
718 switch (GET_CODE (addr))
727 return SMALL_INT (op);
730 plus0 = XEXP (addr, 0);
731 plus1 = XEXP (addr, 1);
732 if (GET_CODE (plus0) == REG
733 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
735 || mips16_simple_memory_operand (plus0, plus1, mode)))
738 else if (GET_CODE (plus1) == REG
739 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
741 || mips16_simple_memory_operand (plus1, plus0, mode)))
748 /* We used to allow small symbol refs here (ie, stuff in .sdata
749 or .sbss), but this causes some bugs in G++. Also, it won't
750 interfere if the MIPS linker rewrites the store instruction
751 because the function is PIC. */
753 case LABEL_REF: /* never gp relative */
757 /* If -G 0, we can never have a GP relative memory operation.
758 Also, save some time if not optimizing. */
763 rtx offset = const0_rtx;
764 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
765 if (GET_CODE (op) != SYMBOL_REF)
768 /* let's be paranoid.... */
769 if (! SMALL_INT (offset))
776 return SYMBOL_REF_FLAG (addr);
779 /* This SYMBOL_REF case is for the mips16. If the above case is
780 reenabled, this one should be merged in. */
782 /* References to the constant pool on the mips16 use a small
783 offset if the function is small. The only time we care about
784 getting this right is during delayed branch scheduling, so
785 don't need to check until then. The machine_dependent_reorg
786 function will set the total length of the instructions used
787 in the function in current_frame_info. If that is small
788 enough, we know for sure that this is a small offset. It
789 would be better if we could take into account the location of
790 the instruction within the function, but we can't, because we
791 don't know where we are. */
793 && CONSTANT_POOL_ADDRESS_P (addr)
794 && current_frame_info.insns_len > 0)
798 size = current_frame_info.insns_len + get_pool_size ();
799 if (GET_MODE_SIZE (mode) == 4)
800 return size < 4 * 0x100;
801 else if (GET_MODE_SIZE (mode) == 8)
802 return size < 8 * 0x20;
816 /* Return nonzero for a memory address that can be used to load or store
820 double_memory_operand (op, mode)
822 enum machine_mode mode;
826 if (GET_CODE (op) != MEM
827 || ! memory_operand (op, mode))
829 /* During reload, we accept a pseudo register if it has an
830 appropriate memory address. If we don't do this, we will
831 wind up reloading into a register, and then reloading that
832 register from memory, when we could just reload directly from
834 if (reload_in_progress
835 && GET_CODE (op) == REG
836 && REGNO (op) >= FIRST_PSEUDO_REGISTER
837 && reg_renumber[REGNO (op)] < 0
838 && reg_equiv_mem[REGNO (op)] != 0
839 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
842 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
843 the same test performed for 'm' in find_reloads. */
845 if (reload_in_progress
847 && (GET_CODE (op) == MEM
848 || (GET_CODE (op) == REG
849 && REGNO (op) >= FIRST_PSEUDO_REGISTER
850 && reg_renumber[REGNO (op)] < 0)))
853 if (reload_in_progress
855 && GET_CODE (op) == MEM)
861 /* During reload on the mips16, we accept a large offset
862 from the frame pointer or the stack pointer. This large
863 address will get reloaded anyhow. */
864 if (GET_CODE (addr) == PLUS
865 && GET_CODE (XEXP (addr, 0)) == REG
866 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
867 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
868 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
869 && ! SMALL_INT (XEXP (addr, 1)))
870 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
871 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
874 /* Similarly, we accept a case where the memory address is
875 itself on the stack, and will be reloaded. */
876 if (GET_CODE (addr) == MEM)
880 maddr = XEXP (addr, 0);
881 if (GET_CODE (maddr) == PLUS
882 && GET_CODE (XEXP (maddr, 0)) == REG
883 && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM
884 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
885 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
886 && ! SMALL_INT (XEXP (maddr, 1)))
887 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
888 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
892 /* We also accept the same case when we have a 16 bit signed
893 offset mixed in as well. The large address will get
894 reloaded, and the 16 bit offset will be OK. */
895 if (GET_CODE (addr) == PLUS
896 && GET_CODE (XEXP (addr, 0)) == MEM
897 && GET_CODE (XEXP (addr, 1)) == CONST_INT
898 && SMALL_INT (XEXP (addr, 1)))
900 addr = XEXP (XEXP (addr, 0), 0);
901 if (GET_CODE (addr) == PLUS
902 && GET_CODE (XEXP (addr, 0)) == REG
903 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
904 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
905 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
906 && ! SMALL_INT (XEXP (addr, 1)))
907 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
908 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
918 /* In this case we can use an instruction like sd. */
922 /* Make sure that 4 added to the address is a valid memory address.
923 This essentially just checks for overflow in an added constant. */
927 if (CONSTANT_ADDRESS_P (addr))
930 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
933 plus_constant_for_output (addr, 4));
936 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
939 equality_op (op, mode)
941 enum machine_mode mode;
943 if (mode != GET_MODE (op))
946 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
949 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
954 enum machine_mode mode;
956 if (mode != GET_MODE (op))
959 return GET_RTX_CLASS (GET_CODE (op)) == '<';
962 /* Return nonzero if the operand is either the PC or a label_ref. */
965 pc_or_label_operand (op, mode)
967 enum machine_mode mode ATTRIBUTE_UNUSED;
972 if (GET_CODE (op) == LABEL_REF)
978 /* Test for a valid operand for a call instruction.
979 Don't allow the arg pointer register or virtual regs
980 since they may change into reg + const, which the patterns
984 call_insn_operand (op, mode)
986 enum machine_mode mode ATTRIBUTE_UNUSED;
988 return (CONSTANT_ADDRESS_P (op)
989 || (GET_CODE (op) == REG && op != arg_pointer_rtx
990 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
991 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
994 /* Return nonzero if OPERAND is valid as a source operand for a move
998 move_operand (op, mode)
1000 enum machine_mode mode;
1002 /* Accept any general operand after reload has started; doing so
1003 avoids losing if reload does an in-place replacement of a register
1004 with a SYMBOL_REF or CONST. */
1005 return (general_operand (op, mode)
1006 && (! (mips_split_addresses && mips_check_split (op, mode))
1007 || reload_in_progress || reload_completed)
1009 && GET_CODE (op) == SYMBOL_REF
1010 && ! mips16_constant (op, mode, 1, 0)));
1013 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1014 This accepts not only general_operand, but also sign extended
1015 constants and registers. We need to accept sign extended constants
1016 in case a sign extended register which is used in an expression,
1017 and is equivalent to a constant, is spilled. */
1020 movdi_operand (op, mode)
1022 enum machine_mode mode;
1026 && GET_CODE (op) == SIGN_EXTEND
1027 && GET_MODE (op) == DImode
1028 && (GET_MODE (XEXP (op, 0)) == SImode
1029 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1030 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1031 && (register_operand (XEXP (op, 0), SImode)
1032 || immediate_operand (XEXP (op, 0), SImode)))
1035 return (general_operand (op, mode)
1037 && GET_CODE (op) == SYMBOL_REF
1038 && ! mips16_constant (op, mode, 1, 0)));
1041 /* Like register_operand, but when in 64 bit mode also accept a sign
1042 extend of a 32 bit register, since the value is known to be already
1046 se_register_operand (op, mode)
1048 enum machine_mode mode;
1052 && GET_CODE (op) == SIGN_EXTEND
1053 && GET_MODE (op) == DImode
1054 && GET_MODE (XEXP (op, 0)) == SImode
1055 && register_operand (XEXP (op, 0), SImode))
1058 return register_operand (op, mode);
1061 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1062 extend of a 32 bit register, since the value is known to be already
1066 se_reg_or_0_operand (op, mode)
1068 enum machine_mode mode;
1072 && GET_CODE (op) == SIGN_EXTEND
1073 && GET_MODE (op) == DImode
1074 && GET_MODE (XEXP (op, 0)) == SImode
1075 && register_operand (XEXP (op, 0), SImode))
1078 return reg_or_0_operand (op, mode);
1081 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1082 extend of a 32 bit register, since the value is known to be already
1086 se_uns_arith_operand (op, mode)
1088 enum machine_mode mode;
1092 && GET_CODE (op) == SIGN_EXTEND
1093 && GET_MODE (op) == DImode
1094 && GET_MODE (XEXP (op, 0)) == SImode
1095 && register_operand (XEXP (op, 0), SImode))
1098 return uns_arith_operand (op, mode);
1101 /* Like arith_operand, but when in 64 bit mode also accept a sign
1102 extend of a 32 bit register, since the value is known to be already
1106 se_arith_operand (op, mode)
1108 enum machine_mode mode;
1112 && GET_CODE (op) == SIGN_EXTEND
1113 && GET_MODE (op) == DImode
1114 && GET_MODE (XEXP (op, 0)) == SImode
1115 && register_operand (XEXP (op, 0), SImode))
1118 return arith_operand (op, mode);
1121 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1122 extend of a 32 bit register, since the value is known to be already
1126 se_nonmemory_operand (op, mode)
1128 enum machine_mode mode;
1132 && GET_CODE (op) == SIGN_EXTEND
1133 && GET_MODE (op) == DImode
1134 && GET_MODE (XEXP (op, 0)) == SImode
1135 && register_operand (XEXP (op, 0), SImode))
1138 return nonmemory_operand (op, mode);
1141 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1142 sign extend of a 32 bit register, since the value is known to be
1143 already sign extended. */
1146 se_nonimmediate_operand (op, mode)
1148 enum machine_mode mode;
1152 && GET_CODE (op) == SIGN_EXTEND
1153 && GET_MODE (op) == DImode
1154 && GET_MODE (XEXP (op, 0)) == SImode
1155 && register_operand (XEXP (op, 0), SImode))
1158 return nonimmediate_operand (op, mode);
1161 /* Accept any operand that can appear in a mips16 constant table
1162 instruction. We can't use any of the standard operand functions
1163 because for these instructions we accept values that are not
1164 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1167 consttable_operand (op, mode)
1169 enum machine_mode mode ATTRIBUTE_UNUSED;
1171 return CONSTANT_P (op);
1174 /* Return nonzero if we split the address into high and low parts. */
1176 /* ??? We should also handle reg+array somewhere. We get four
1177 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1178 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1179 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1180 out of the address, then we have 4 instructions to combine. Perhaps
1181 add a 3->2 define_split for combine. */
1183 /* ??? We could also split a CONST_INT here if it is a large_int().
1184 However, it doesn't seem to be very useful to have %hi(constant).
1185 We would be better off by doing the masking ourselves and then putting
1186 the explicit high part of the constant in the RTL. This will give better
1187 optimization. Also, %hi(constant) needs assembler changes to work.
1188 There is already a define_split that does this. */
1191 mips_check_split (address, mode)
1193 enum machine_mode mode;
1195 /* ??? This is the same check used in simple_memory_operand.
1196 We use it here because LO_SUM is not offsettable. */
1197 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1200 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1201 || (GET_CODE (address) == CONST
1202 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1203 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1204 || GET_CODE (address) == LABEL_REF)
1210 /* We need a lot of little routines to check constant values on the
1211 mips16. These are used to figure out how long the instruction will
1212 be. It would be much better to do this using constraints, but
1213 there aren't nearly enough letters available. */
1216 m16_check_op (op, low, high, mask)
1222 return (GET_CODE (op) == CONST_INT
1223 && INTVAL (op) >= low
1224 && INTVAL (op) <= high
1225 && (INTVAL (op) & mask) == 0);
1229 m16_uimm3_b (op, mode)
1231 enum machine_mode mode ATTRIBUTE_UNUSED;
1233 return m16_check_op (op, 0x1, 0x8, 0);
1237 m16_simm4_1 (op, mode)
1239 enum machine_mode mode ATTRIBUTE_UNUSED;
1241 return m16_check_op (op, - 0x8, 0x7, 0);
1245 m16_nsimm4_1 (op, mode)
1247 enum machine_mode mode ATTRIBUTE_UNUSED;
1249 return m16_check_op (op, - 0x7, 0x8, 0);
1253 m16_simm5_1 (op, mode)
1255 enum machine_mode mode ATTRIBUTE_UNUSED;
1257 return m16_check_op (op, - 0x10, 0xf, 0);
1261 m16_nsimm5_1 (op, mode)
1263 enum machine_mode mode ATTRIBUTE_UNUSED;
1265 return m16_check_op (op, - 0xf, 0x10, 0);
1269 m16_uimm5_4 (op, mode)
1271 enum machine_mode mode ATTRIBUTE_UNUSED;
1273 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1277 m16_nuimm5_4 (op, mode)
1279 enum machine_mode mode ATTRIBUTE_UNUSED;
1281 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1285 m16_simm8_1 (op, mode)
1287 enum machine_mode mode ATTRIBUTE_UNUSED;
1289 return m16_check_op (op, - 0x80, 0x7f, 0);
1293 m16_nsimm8_1 (op, mode)
1295 enum machine_mode mode ATTRIBUTE_UNUSED;
1297 return m16_check_op (op, - 0x7f, 0x80, 0);
1301 m16_uimm8_1 (op, mode)
1303 enum machine_mode mode ATTRIBUTE_UNUSED;
1305 return m16_check_op (op, 0x0, 0xff, 0);
1309 m16_nuimm8_1 (op, mode)
1311 enum machine_mode mode ATTRIBUTE_UNUSED;
1313 return m16_check_op (op, - 0xff, 0x0, 0);
1317 m16_uimm8_m1_1 (op, mode)
1319 enum machine_mode mode ATTRIBUTE_UNUSED;
1321 return m16_check_op (op, - 0x1, 0xfe, 0);
1325 m16_uimm8_4 (op, mode)
1327 enum machine_mode mode ATTRIBUTE_UNUSED;
1329 return m16_check_op (op, 0x0, 0xff << 2, 3);
1333 m16_nuimm8_4 (op, mode)
1335 enum machine_mode mode ATTRIBUTE_UNUSED;
1337 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1341 m16_simm8_8 (op, mode)
1343 enum machine_mode mode ATTRIBUTE_UNUSED;
1345 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1349 m16_nsimm8_8 (op, mode)
1351 enum machine_mode mode ATTRIBUTE_UNUSED;
1353 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1356 /* References to the string table on the mips16 only use a small
1357 offset if the function is small. See the comment in the SYMBOL_REF
1358 case in simple_memory_operand. We can't check for LABEL_REF here,
1359 because the offset is always large if the label is before the
1360 referencing instruction. */
1363 m16_usym8_4 (op, mode)
1365 enum machine_mode mode ATTRIBUTE_UNUSED;
1367 if (GET_CODE (op) == SYMBOL_REF
1368 && SYMBOL_REF_FLAG (op)
1369 && current_frame_info.insns_len > 0
1370 && XSTR (op, 0)[0] == '*'
1371 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1372 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1373 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1376 struct string_constant *l;
1378 /* Make sure this symbol is on thelist of string constants to be
1379 output for this function. It is possible that it has already
1380 been output, in which case this requires a large offset. */
1381 for (l = string_constants; l != NULL; l = l->next)
1382 if (strcmp (l->label, XSTR (op, 0)) == 0)
1390 m16_usym5_4 (op, mode)
1392 enum machine_mode mode ATTRIBUTE_UNUSED;
1394 if (GET_CODE (op) == SYMBOL_REF
1395 && SYMBOL_REF_FLAG (op)
1396 && current_frame_info.insns_len > 0
1397 && XSTR (op, 0)[0] == '*'
1398 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1399 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1400 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1403 struct string_constant *l;
1405 /* Make sure this symbol is on thelist of string constants to be
1406 output for this function. It is possible that it has already
1407 been output, in which case this requires a large offset. */
1408 for (l = string_constants; l != NULL; l = l->next)
1409 if (strcmp (l->label, XSTR (op, 0)) == 0)
1416 /* Returns an operand string for the given instruction's delay slot,
1417 after updating filled delay slot statistics.
1419 We assume that operands[0] is the target register that is set.
1421 In order to check the next insn, most of this functionality is moved
1422 to FINAL_PRESCAN_INSN, and we just set the global variables that
1425 /* ??? This function no longer does anything useful, because final_prescan_insn
1426 now will never emit a nop. */
1429 mips_fill_delay_slot (ret, type, operands, cur_insn)
1430 char *ret; /* normal string to return */
1431 enum delay_type type; /* type of delay */
1432 rtx operands[]; /* operands to use */
1433 rtx cur_insn; /* current insn */
1435 register rtx set_reg;
1436 register enum machine_mode mode;
1437 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1438 register int num_nops;
1440 if (type == DELAY_LOAD || type == DELAY_FCMP)
1443 else if (type == DELAY_HILO)
1449 /* Make sure that we don't put nop's after labels. */
1450 next_insn = NEXT_INSN (cur_insn);
1451 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1452 next_insn = NEXT_INSN (next_insn);
1454 dslots_load_total += num_nops;
1455 if (TARGET_DEBUG_F_MODE
1457 || type == DELAY_NONE
1461 || GET_CODE (next_insn) == CODE_LABEL
1462 || (set_reg = operands[0]) == 0)
1464 dslots_number_nops = 0;
1472 set_reg = operands[0];
1476 while (GET_CODE (set_reg) == SUBREG)
1477 set_reg = SUBREG_REG (set_reg);
1479 mode = GET_MODE (set_reg);
1480 dslots_number_nops = num_nops;
1481 mips_load_reg = set_reg;
1482 if (GET_MODE_SIZE (mode)
1483 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1484 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1488 if (type == DELAY_HILO)
1490 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1491 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1503 /* Determine whether a memory reference takes one (based off of the GP
1504 pointer), two (normal), or three (label + reg) instructions, and bump the
1505 appropriate counter for -mstats. */
1508 mips_count_memory_refs (op, num)
1514 rtx addr, plus0, plus1;
1515 enum rtx_code code0, code1;
1518 if (TARGET_DEBUG_B_MODE)
1520 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1524 /* Skip MEM if passed, otherwise handle movsi of address. */
1525 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1527 /* Loop, going through the address RTL. */
1531 switch (GET_CODE (addr))
1539 plus0 = XEXP (addr, 0);
1540 plus1 = XEXP (addr, 1);
1541 code0 = GET_CODE (plus0);
1542 code1 = GET_CODE (plus1);
1552 if (code0 == CONST_INT)
1567 if (code1 == CONST_INT)
1574 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1581 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1591 n_words = 2; /* always 2 words */
1595 addr = XEXP (addr, 0);
1600 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1612 n_words += additional;
1616 num_refs[n_words-1] += num;
1620 /* Return RTL for the offset from the current function to the argument.
1622 ??? Which argument is this? */
1625 embedded_pic_offset (x)
1628 if (embedded_pic_fnaddr_rtx == NULL)
1632 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1634 /* Output code at function start to initialize the pseudo-reg. */
1635 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1636 inline functions, because it is called after RTL for the function
1637 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1638 does not get copied, and ends up not matching the rest of the RTL.
1639 This solution works, but means that we get unnecessary code to
1640 initialize this value every time a function is inlined into another
1643 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1644 XEXP (DECL_RTL (current_function_decl), 0)));
1645 seq = gen_sequence ();
1647 push_topmost_sequence ();
1648 emit_insn_after (seq, get_insns ());
1649 pop_topmost_sequence ();
1653 gen_rtx_CONST (Pmode,
1654 gen_rtx_MINUS (Pmode, x,
1655 XEXP (DECL_RTL (current_function_decl), 0)));
1658 /* Return the appropriate instructions to move one operand to another. */
1661 mips_move_1word (operands, insn, unsignedp)
1666 const char *ret = 0;
1667 rtx op0 = operands[0];
1668 rtx op1 = operands[1];
1669 enum rtx_code code0 = GET_CODE (op0);
1670 enum rtx_code code1 = GET_CODE (op1);
1671 enum machine_mode mode = GET_MODE (op0);
1672 int subreg_word0 = 0;
1673 int subreg_word1 = 0;
1674 enum delay_type delay = DELAY_NONE;
1676 while (code0 == SUBREG)
1678 subreg_word0 += SUBREG_WORD (op0);
1679 op0 = SUBREG_REG (op0);
1680 code0 = GET_CODE (op0);
1683 while (code1 == SUBREG)
1685 subreg_word1 += SUBREG_WORD (op1);
1686 op1 = SUBREG_REG (op1);
1687 code1 = GET_CODE (op1);
1690 /* For our purposes, a condition code mode is the same as SImode. */
1696 int regno0 = REGNO (op0) + subreg_word0;
1700 int regno1 = REGNO (op1) + subreg_word1;
1702 /* Just in case, don't do anything for assigning a register
1703 to itself, unless we are filling a delay slot. */
1704 if (regno0 == regno1 && set_nomacro == 0)
1707 else if (GP_REG_P (regno0))
1709 if (GP_REG_P (regno1))
1710 ret = "move\t%0,%1";
1712 else if (MD_REG_P (regno1))
1715 if (regno1 != HILO_REGNUM)
1721 else if (ST_REG_P (regno1) && mips_isa >= 4)
1722 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1727 if (FP_REG_P (regno1))
1728 ret = "mfc1\t%0,%1";
1730 else if (regno1 == FPSW_REGNUM && mips_isa < 4)
1731 ret = "cfc1\t%0,$31";
1735 else if (FP_REG_P (regno0))
1737 if (GP_REG_P (regno1))
1740 ret = "mtc1\t%1,%0";
1743 if (FP_REG_P (regno1))
1744 ret = "mov.s\t%0,%1";
1747 else if (MD_REG_P (regno0))
1749 if (GP_REG_P (regno1))
1752 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1757 else if (regno0 == FPSW_REGNUM && mips_isa < 4)
1759 if (GP_REG_P (regno1))
1762 ret = "ctc1\t%0,$31";
1767 else if (code1 == MEM)
1772 mips_count_memory_refs (op1, 1);
1774 if (GP_REG_P (regno0))
1776 /* For loads, use the mode of the memory item, instead of the
1777 target, so zero/sign extend can use this code as well. */
1778 switch (GET_MODE (op1))
1787 ret = ((unsignedp && TARGET_64BIT)
1792 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1795 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1800 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1803 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1805 size_t i = strlen (ret);
1806 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1809 sprintf (volatile_buffer, "%%{%s%%}", ret);
1810 ret = volatile_buffer;
1814 else if (code1 == CONST_INT
1815 || (code1 == CONST_DOUBLE
1816 && GET_MODE (op1) == VOIDmode))
1818 if (code1 == CONST_DOUBLE)
1820 /* This can happen when storing constants into long long
1821 bitfields. Just store the least significant word of
1823 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1826 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
1828 if (GP_REG_P (regno0))
1829 ret = "move\t%0,%z1";
1831 else if (FP_REG_P (regno0))
1834 ret = "mtc1\t%z1,%0";
1837 else if (MD_REG_P (regno0))
1844 else if (GP_REG_P (regno0))
1846 /* Don't use X format, because that will give out of
1847 range numbers for 64 bit host and 32 bit target. */
1848 if (! TARGET_MIPS16)
1849 ret = "li\t%0,%1\t\t\t# %X1";
1852 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
1854 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
1855 ret = "li\t%0,%n1\n\tneg\t%0";
1860 else if (code1 == CONST_DOUBLE && mode == SFmode)
1862 if (op1 == CONST0_RTX (SFmode))
1864 if (GP_REG_P (regno0))
1865 ret = "move\t%0,%.";
1867 else if (FP_REG_P (regno0))
1870 ret = "mtc1\t%.,%0";
1877 ret = "li.s\t%0,%1";
1881 else if (code1 == LABEL_REF)
1884 mips_count_memory_refs (op1, 1);
1889 else if (code1 == SYMBOL_REF || code1 == CONST)
1891 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
1893 rtx offset = const0_rtx;
1895 if (GET_CODE (op1) == CONST)
1896 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1898 if (GET_CODE (op1) == SYMBOL_REF)
1900 operands[2] = HALF_PIC_PTR (op1);
1903 mips_count_memory_refs (operands[2], 1);
1905 if (INTVAL (offset) == 0)
1908 ret = (unsignedp && TARGET_64BIT
1914 dslots_load_total++;
1915 operands[3] = offset;
1916 if (unsignedp && TARGET_64BIT)
1917 ret = (SMALL_INT (offset)
1918 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1919 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1921 ret = (SMALL_INT (offset)
1922 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1923 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1927 else if (TARGET_MIPS16
1929 && GET_CODE (XEXP (op1, 0)) == REG
1930 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
1932 /* This case arises on the mips16; see
1933 mips16_gp_pseudo_reg. */
1934 ret = "move\t%0,%+";
1936 else if (TARGET_MIPS16
1937 && code1 == SYMBOL_REF
1938 && SYMBOL_REF_FLAG (op1)
1939 && (XSTR (op1, 0)[0] != '*'
1940 || strncmp (XSTR (op1, 0) + 1,
1942 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
1944 /* This can occur when reloading the address of a GP
1945 relative symbol on the mips16. */
1946 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
1951 mips_count_memory_refs (op1, 1);
1957 else if (code1 == PLUS)
1959 rtx add_op0 = XEXP (op1, 0);
1960 rtx add_op1 = XEXP (op1, 1);
1962 if (GET_CODE (XEXP (op1, 1)) == REG
1963 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1964 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
1966 operands[2] = add_op0;
1967 operands[3] = add_op1;
1968 ret = "add%:\t%0,%2,%3";
1971 else if (code1 == HIGH)
1973 operands[1] = XEXP (op1, 0);
1974 ret = "lui\t%0,%%hi(%1)";
1978 else if (code0 == MEM)
1981 mips_count_memory_refs (op0, 1);
1985 int regno1 = REGNO (op1) + subreg_word1;
1987 if (GP_REG_P (regno1))
1991 case SFmode: ret = "sw\t%1,%0"; break;
1992 case SImode: ret = "sw\t%1,%0"; break;
1993 case HImode: ret = "sh\t%1,%0"; break;
1994 case QImode: ret = "sb\t%1,%0"; break;
1999 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2003 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2007 case SFmode: ret = "sw\t%z1,%0"; break;
2008 case SImode: ret = "sw\t%z1,%0"; break;
2009 case HImode: ret = "sh\t%z1,%0"; break;
2010 case QImode: ret = "sb\t%z1,%0"; break;
2015 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2019 case SFmode: ret = "sw\t%.,%0"; break;
2020 case SImode: ret = "sw\t%.,%0"; break;
2021 case HImode: ret = "sh\t%.,%0"; break;
2022 case QImode: ret = "sb\t%.,%0"; break;
2027 if (ret != 0 && MEM_VOLATILE_P (op0))
2029 size_t i = strlen (ret);
2031 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2034 sprintf (volatile_buffer, "%%{%s%%}", ret);
2035 ret = volatile_buffer;
2041 abort_with_insn (insn, "Bad move");
2045 if (delay != DELAY_NONE)
2046 return mips_fill_delay_slot (ret, delay, operands, insn);
2052 /* Return the appropriate instructions to move 2 words */
2055 mips_move_2words (operands, insn)
2059 const char *ret = 0;
2060 rtx op0 = operands[0];
2061 rtx op1 = operands[1];
2062 enum rtx_code code0 = GET_CODE (operands[0]);
2063 enum rtx_code code1 = GET_CODE (operands[1]);
2064 int subreg_word0 = 0;
2065 int subreg_word1 = 0;
2066 enum delay_type delay = DELAY_NONE;
2068 while (code0 == SUBREG)
2070 subreg_word0 += SUBREG_WORD (op0);
2071 op0 = SUBREG_REG (op0);
2072 code0 = GET_CODE (op0);
2075 if (code1 == SIGN_EXTEND)
2077 op1 = XEXP (op1, 0);
2078 code1 = GET_CODE (op1);
2081 while (code1 == SUBREG)
2083 subreg_word1 += SUBREG_WORD (op1);
2084 op1 = SUBREG_REG (op1);
2085 code1 = GET_CODE (op1);
2089 if (GET_CODE (operands[1]) == SIGN_EXTEND
2091 && code1 != CONST_INT
2092 /* The following three can happen as the result of a questionable
2094 && code1 != LABEL_REF
2095 && code1 != SYMBOL_REF
2101 int regno0 = REGNO (op0) + subreg_word0;
2105 int regno1 = REGNO (op1) + subreg_word1;
2107 /* Just in case, don't do anything for assigning a register
2108 to itself, unless we are filling a delay slot. */
2109 if (regno0 == regno1 && set_nomacro == 0)
2112 else if (FP_REG_P (regno0))
2114 if (FP_REG_P (regno1))
2115 ret = "mov.d\t%0,%1";
2123 abort_with_insn (insn, "Bad move");
2125 #ifdef TARGET_FP_CALL_32
2126 if (FP_CALL_GP_REG_P (regno1))
2127 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2130 ret = "dmtc1\t%1,%0";
2133 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2137 else if (FP_REG_P (regno1))
2143 abort_with_insn (insn, "Bad move");
2145 #ifdef TARGET_FP_CALL_32
2146 if (FP_CALL_GP_REG_P (regno0))
2147 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2150 ret = "dmfc1\t%0,%1";
2153 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2156 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2161 if (regno0 != HILO_REGNUM)
2163 else if (regno1 == 0)
2164 ret = "mtlo\t%.\n\tmthi\t%.";
2167 ret = "mthi\t%M1\n\tmtlo\t%L1";
2170 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2175 if (regno1 != HILO_REGNUM)
2179 ret = "mfhi\t%M0\n\tmflo\t%L0";
2182 else if (TARGET_64BIT)
2183 ret = "move\t%0,%1";
2185 else if (regno0 != (regno1+1))
2186 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2189 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2192 else if (code1 == CONST_DOUBLE)
2194 /* Move zero from $0 unless !TARGET_64BIT and recipient
2195 is 64-bit fp reg, in which case generate a constant. */
2196 if (op1 != CONST0_RTX (GET_MODE (op1))
2197 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2199 if (GET_MODE (op1) == DFmode)
2203 #ifdef TARGET_FP_CALL_32
2204 if (FP_CALL_GP_REG_P (regno0))
2206 if (TARGET_FLOAT64 && !TARGET_64BIT)
2208 split_double (op1, operands + 2, operands + 3);
2209 ret = "li\t%0,%2\n\tli\t%D0,%3";
2212 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2216 ret = "li.d\t%0,%1";
2219 else if (TARGET_64BIT)
2221 if (! TARGET_MIPS16)
2227 split_double (op1, operands + 2, operands + 3);
2228 ret = "li\t%0,%2\n\tli\t%D0,%3";
2234 if (GP_REG_P (regno0))
2236 #ifdef TARGET_FP_CALL_32
2237 && ! FP_CALL_GP_REG_P (regno0)
2240 : "move\t%0,%.\n\tmove\t%D0,%.");
2242 else if (FP_REG_P (regno0))
2247 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2252 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2254 if (GP_REG_P (regno0))
2257 : "move\t%0,%.\n\tmove\t%D0,%.");
2259 else if (FP_REG_P (regno0))
2266 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2268 else if (MD_REG_P (regno0))
2271 ret = (regno0 == HILO_REGNUM
2272 ? "mtlo\t%.\n\tmthi\t%."
2277 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2278 && GP_REG_P (regno0))
2284 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2286 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2287 ret = "li\t%0,%n1\n\tneg\t%0";
2289 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2290 ret = "li\t%0,%1\t\t# %X1";
2291 else if (HOST_BITS_PER_WIDE_INT < 64)
2292 /* We can't use 'X' for negative numbers, because then we won't
2293 get the right value for the upper 32 bits. */
2294 ret = (INTVAL (op1) < 0
2295 ? "dli\t%0,%1\t\t\t# %X1"
2296 : "dli\t%0,%X1\t\t# %1");
2298 /* We must use 'X', because otherwise LONG_MIN will print as
2299 a number that the assembler won't accept. */
2300 ret = "dli\t%0,%X1\t\t# %1";
2302 else if (HOST_BITS_PER_WIDE_INT < 64)
2304 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2307 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2308 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2309 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2311 operands[2] = GEN_INT (1);
2312 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2316 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2320 /* We use multiple shifts here, to avoid warnings about out
2321 of range shifts on 32 bit hosts. */
2322 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2324 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2325 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2329 else if (code1 == MEM)
2334 mips_count_memory_refs (op1, 2);
2336 if (FP_REG_P (regno0))
2339 else if (TARGET_64BIT)
2342 #ifdef TARGET_FP_CALL_32
2343 if (FP_CALL_GP_REG_P (regno0))
2344 ret = (double_memory_operand (op1, GET_MODE (op1))
2345 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2346 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2352 else if (double_memory_operand (op1, GET_MODE (op1)))
2354 operands[2] = adj_offsettable_operand (op1, 4);
2355 ret = (reg_mentioned_p (op0, op1)
2356 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2357 : "lw\t%0,%1\n\tlw\t%D0,%2");
2360 if (ret != 0 && MEM_VOLATILE_P (op1))
2362 size_t i = strlen (ret);
2364 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2367 sprintf (volatile_buffer, "%%{%s%%}", ret);
2368 ret = volatile_buffer;
2372 else if (code1 == LABEL_REF)
2375 mips_count_memory_refs (op1, 2);
2377 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2378 /* We deliberately remove the 'a' from '%1', so that we don't
2379 have to add SIGN_EXTEND support to print_operand_address.
2380 print_operand will just call print_operand_address in this
2381 case, so there is no problem. */
2384 ret = "dla\t%0,%a1";
2386 else if (code1 == SYMBOL_REF || code1 == CONST)
2390 && GET_CODE (XEXP (op1, 0)) == REG
2391 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2393 /* This case arises on the mips16; see
2394 mips16_gp_pseudo_reg. */
2395 ret = "move\t%0,%+";
2397 else if (TARGET_MIPS16
2398 && code1 == SYMBOL_REF
2399 && SYMBOL_REF_FLAG (op1)
2400 && (XSTR (op1, 0)[0] != '*'
2401 || strncmp (XSTR (op1, 0) + 1,
2403 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2405 /* This can occur when reloading the address of a GP
2406 relative symbol on the mips16. */
2407 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2412 mips_count_memory_refs (op1, 2);
2414 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2415 /* We deliberately remove the 'a' from '%1', so that we don't
2416 have to add SIGN_EXTEND support to print_operand_address.
2417 print_operand will just call print_operand_address in this
2418 case, so there is no problem. */
2421 ret = "dla\t%0,%a1";
2426 else if (code0 == MEM)
2430 int regno1 = REGNO (op1) + subreg_word1;
2432 if (FP_REG_P (regno1))
2435 else if (TARGET_64BIT)
2438 #ifdef TARGET_FP_CALL_32
2439 if (FP_CALL_GP_REG_P (regno1))
2440 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2446 else if (double_memory_operand (op0, GET_MODE (op0)))
2448 operands[2] = adj_offsettable_operand (op0, 4);
2449 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2453 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2454 || (code1 == CONST_DOUBLE
2455 && op1 == CONST0_RTX (GET_MODE (op1))))
2457 || double_memory_operand (op0, GET_MODE (op0))))
2463 operands[2] = adj_offsettable_operand (op0, 4);
2464 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2469 mips_count_memory_refs (op0, 2);
2471 if (ret != 0 && MEM_VOLATILE_P (op0))
2473 size_t i = strlen (ret);
2475 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2478 sprintf (volatile_buffer, "%%{%s%%}", ret);
2479 ret = volatile_buffer;
2485 abort_with_insn (insn, "Bad move");
2489 if (delay != DELAY_NONE)
2490 return mips_fill_delay_slot (ret, delay, operands, insn);
2495 /* Provide the costs of an addressing mode that contains ADDR.
2496 If ADDR is not a valid address, its cost is irrelevant. */
2499 mips_address_cost (addr)
2502 switch (GET_CODE (addr))
2512 rtx offset = const0_rtx;
2513 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2514 if (GET_CODE (addr) == LABEL_REF)
2517 if (GET_CODE (addr) != SYMBOL_REF)
2520 if (! SMALL_INT (offset))
2524 /* ... fall through ... */
2527 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2531 register rtx plus0 = XEXP (addr, 0);
2532 register rtx plus1 = XEXP (addr, 1);
2534 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2535 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2537 if (GET_CODE (plus0) != REG)
2540 switch (GET_CODE (plus1))
2543 return SMALL_INT (plus1) ? 1 : 2;
2550 return mips_address_cost (plus1) + 1;
2564 /* Return nonzero if X is an address which needs a temporary register when
2565 reloaded while generating PIC code. */
2568 pic_address_needs_scratch (x)
2571 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2572 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2573 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2574 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2575 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2581 /* Make normal rtx_code into something we can index from an array */
2583 static enum internal_test
2584 map_test_to_internal_test (test_code)
2585 enum rtx_code test_code;
2587 enum internal_test test = ITEST_MAX;
2591 case EQ: test = ITEST_EQ; break;
2592 case NE: test = ITEST_NE; break;
2593 case GT: test = ITEST_GT; break;
2594 case GE: test = ITEST_GE; break;
2595 case LT: test = ITEST_LT; break;
2596 case LE: test = ITEST_LE; break;
2597 case GTU: test = ITEST_GTU; break;
2598 case GEU: test = ITEST_GEU; break;
2599 case LTU: test = ITEST_LTU; break;
2600 case LEU: test = ITEST_LEU; break;
2608 /* Generate the code to compare two integer values. The return value is:
2609 (reg:SI xx) The pseudo register the comparison is in
2610 0 No register, generate a simple branch.
2612 ??? This is called with result nonzero by the Scond patterns in
2613 mips.md. These patterns are called with a target in the mode of
2614 the Scond instruction pattern. Since this must be a constant, we
2615 must use SImode. This means that if RESULT is non-zero, it will
2616 always be an SImode register, even if TARGET_64BIT is true. We
2617 cope with this by calling convert_move rather than emit_move_insn.
2618 This will sometimes lead to an unnecessary extension of the result;
2630 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2631 enum rtx_code test_code; /* relational test (EQ, etc) */
2632 rtx result; /* result to store comp. or 0 if branch */
2633 rtx cmp0; /* first operand to compare */
2634 rtx cmp1; /* second operand to compare */
2635 int *p_invert; /* NULL or ptr to hold whether branch needs */
2636 /* to reverse its test */
2640 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2641 int const_low; /* low bound of constant we can accept */
2642 int const_high; /* high bound of constant we can accept */
2643 int const_add; /* constant to add (convert LE -> LT) */
2644 int reverse_regs; /* reverse registers in test */
2645 int invert_const; /* != 0 if invert value if cmp1 is constant */
2646 int invert_reg; /* != 0 if invert value if cmp1 is register */
2647 int unsignedp; /* != 0 for unsigned comparisons. */
2650 static struct cmp_info info[ (int)ITEST_MAX ] = {
2652 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2653 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2654 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2655 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2656 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2657 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2658 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2659 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2660 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2661 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2664 enum internal_test test;
2665 enum machine_mode mode;
2666 struct cmp_info *p_info;
2673 test = map_test_to_internal_test (test_code);
2674 if (test == ITEST_MAX)
2677 p_info = &info[(int) test];
2678 eqne_p = (p_info->test_code == XOR);
2680 mode = GET_MODE (cmp0);
2681 if (mode == VOIDmode)
2682 mode = GET_MODE (cmp1);
2684 /* Eliminate simple branches */
2685 branch_p = (result == 0);
2688 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2690 /* Comparisons against zero are simple branches */
2691 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2692 && (! TARGET_MIPS16 || eqne_p))
2695 /* Test for beq/bne. */
2696 if (eqne_p && ! TARGET_MIPS16)
2700 /* allocate a pseudo to calculate the value in. */
2701 result = gen_reg_rtx (mode);
2704 /* Make sure we can handle any constants given to us. */
2705 if (GET_CODE (cmp0) == CONST_INT)
2706 cmp0 = force_reg (mode, cmp0);
2708 if (GET_CODE (cmp1) == CONST_INT)
2710 HOST_WIDE_INT value = INTVAL (cmp1);
2712 if (value < p_info->const_low
2713 || value > p_info->const_high
2714 /* ??? Why? And why wasn't the similar code below modified too? */
2716 && HOST_BITS_PER_WIDE_INT < 64
2717 && p_info->const_add != 0
2718 && ((p_info->unsignedp
2719 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2720 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2721 : (value + p_info->const_add) > INTVAL (cmp1))
2722 != (p_info->const_add > 0))))
2723 cmp1 = force_reg (mode, cmp1);
2726 /* See if we need to invert the result. */
2727 invert = (GET_CODE (cmp1) == CONST_INT
2728 ? p_info->invert_const : p_info->invert_reg);
2730 if (p_invert != (int *)0)
2736 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2737 Comparison between two registers, may involve switching operands. */
2738 if (GET_CODE (cmp1) == CONST_INT)
2740 if (p_info->const_add != 0)
2742 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2744 /* If modification of cmp1 caused overflow,
2745 we would get the wrong answer if we follow the usual path;
2746 thus, x > 0xffffffffU would turn into x > 0U. */
2747 if ((p_info->unsignedp
2748 ? (unsigned HOST_WIDE_INT) new >
2749 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2750 : new > INTVAL (cmp1))
2751 != (p_info->const_add > 0))
2753 /* This test is always true, but if INVERT is true then
2754 the result of the test needs to be inverted so 0 should
2755 be returned instead. */
2756 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2760 cmp1 = GEN_INT (new);
2764 else if (p_info->reverse_regs)
2771 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2775 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2776 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2779 if (test == ITEST_NE)
2781 if (! TARGET_MIPS16)
2783 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2788 reg2 = invert ? gen_reg_rtx (mode) : result;
2789 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2794 else if (test == ITEST_EQ)
2796 reg2 = invert ? gen_reg_rtx (mode) : result;
2797 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2805 if (! TARGET_MIPS16)
2809 /* The value is in $24. Copy it to another register, so
2810 that reload doesn't think it needs to store the $24 and
2811 the input to the XOR in the same location. */
2812 reg2 = gen_reg_rtx (mode);
2813 emit_move_insn (reg2, reg);
2815 one = force_reg (mode, const1_rtx);
2817 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
2823 /* Emit the common code for doing conditional branches.
2824 operand[0] is the label to jump to.
2825 The comparison operands are saved away by cmp{si,di,sf,df}. */
2828 gen_conditional_branch (operands, test_code)
2830 enum rtx_code test_code;
2832 enum cmp_type type = branch_type;
2833 rtx cmp0 = branch_cmp[0];
2834 rtx cmp1 = branch_cmp[1];
2835 enum machine_mode mode;
2844 mode = type == CMP_SI ? SImode : DImode;
2846 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
2854 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
2855 /* We don't want to build a comparison against a non-zero
2857 cmp1 = force_reg (mode, cmp1);
2864 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
2866 reg = gen_reg_rtx (CCmode);
2868 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2869 0 in the instruction built below. The MIPS FPU handles
2870 inequality testing by testing for equality and looking for a
2872 emit_insn (gen_rtx_SET (VOIDmode, reg,
2873 gen_rtx (test_code == NE ? EQ : test_code,
2874 CCmode, cmp0, cmp1)));
2876 test_code = test_code == NE ? EQ : NE;
2884 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
2887 /* Generate the branch. */
2889 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
2898 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2899 gen_rtx_IF_THEN_ELSE (VOIDmode,
2900 gen_rtx (test_code, mode,
2905 /* Emit the common code for conditional moves. OPERANDS is the array
2906 of operands passed to the conditional move defined_expand. */
2909 gen_conditional_move (operands)
2912 rtx op0 = branch_cmp[0];
2913 rtx op1 = branch_cmp[1];
2914 enum machine_mode mode = GET_MODE (branch_cmp[0]);
2915 enum rtx_code cmp_code = GET_CODE (operands[1]);
2916 enum rtx_code move_code = NE;
2917 enum machine_mode op_mode = GET_MODE (operands[0]);
2918 enum machine_mode cmp_mode;
2921 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
2940 op0 = force_reg (mode, branch_cmp[1]);
2941 op1 = branch_cmp[0];
2945 op0 = force_reg (mode, branch_cmp[1]);
2946 op1 = branch_cmp[0];
2957 op0 = force_reg (mode, branch_cmp[1]);
2958 op1 = branch_cmp[0];
2962 op0 = force_reg (mode, branch_cmp[1]);
2963 op1 = branch_cmp[0];
2970 else if (cmp_code == NE)
2971 cmp_code = EQ, move_code = EQ;
2973 if (mode == SImode || mode == DImode)
2975 else if (mode == SFmode || mode == DFmode)
2980 cmp_reg = gen_reg_rtx (cmp_mode);
2981 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
2982 gen_rtx (cmp_code, cmp_mode, op0, op1)));
2984 emit_insn (gen_rtx_SET (op_mode, operands[0],
2985 gen_rtx_IF_THEN_ELSE (op_mode,
2986 gen_rtx (move_code, VOIDmode,
2988 CONST0_RTX (SImode)),
2989 operands[2], operands[3])));
2992 /* Write a loop to move a constant number of bytes.
2993 Generate load/stores as follows:
2999 temp<last> = src[MAX_MOVE_REGS-1];
3003 dest[MAX_MOVE_REGS-1] = temp<last>;
3004 src += MAX_MOVE_REGS;
3005 dest += MAX_MOVE_REGS;
3006 } while (src != final);
3008 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3009 registers are needed.
3011 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3012 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3013 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3015 #define MAX_MOVE_REGS 4
3016 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3019 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3020 rtx dest_reg; /* register holding destination address */
3021 rtx src_reg; /* register holding source address */
3022 int bytes; /* # bytes to move */
3023 int align; /* alignment */
3024 rtx orig_dest; /* original dest for change_address */
3025 rtx orig_src; /* original source for making a reg note */
3027 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
3028 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
3029 rtx align_rtx = GEN_INT (align);
3035 if (bytes < 2 * MAX_MOVE_BYTES)
3038 leftover = bytes % MAX_MOVE_BYTES;
3041 label = gen_label_rtx ();
3042 final_src = gen_reg_rtx (Pmode);
3043 bytes_rtx = GEN_INT (bytes);
3047 if (Pmode == DImode)
3049 emit_insn (gen_movdi (final_src, bytes_rtx));
3050 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3054 emit_insn (gen_movsi (final_src, bytes_rtx));
3055 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3060 if (Pmode == DImode)
3061 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3063 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3068 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3069 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3071 if (Pmode == DImode)
3073 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3074 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3075 emit_insn (gen_cmpdi (src_reg, final_src));
3079 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3080 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3081 emit_insn (gen_cmpsi (src_reg, final_src));
3084 emit_jump_insn (gen_bne (label));
3087 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3091 /* Use a library function to move some bytes. */
3094 block_move_call (dest_reg, src_reg, bytes_rtx)
3099 /* We want to pass the size as Pmode, which will normally be SImode
3100 but will be DImode if we are using 64 bit longs and pointers. */
3101 if (GET_MODE (bytes_rtx) != VOIDmode
3102 && GET_MODE (bytes_rtx) != Pmode)
3103 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3105 #ifdef TARGET_MEM_FUNCTIONS
3106 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3107 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3108 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3109 TREE_UNSIGNED (sizetype)),
3110 TYPE_MODE (sizetype));
3112 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3113 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3114 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3115 TREE_UNSIGNED (integer_type_node)),
3116 TYPE_MODE (integer_type_node));
3120 /* Expand string/block move operations.
3122 operands[0] is the pointer to the destination.
3123 operands[1] is the pointer to the source.
3124 operands[2] is the number of bytes to move.
3125 operands[3] is the alignment. */
3128 expand_block_move (operands)
3131 rtx bytes_rtx = operands[2];
3132 rtx align_rtx = operands[3];
3133 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3134 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3135 int align = INTVAL (align_rtx);
3136 rtx orig_src = operands[1];
3137 rtx orig_dest = operands[0];
3141 if (constp && bytes <= 0)
3144 if (align > UNITS_PER_WORD)
3145 align = UNITS_PER_WORD;
3147 /* Move the address into scratch registers. */
3148 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3149 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3152 block_move_call (dest_reg, src_reg, bytes_rtx);
3154 else if (constp && bytes <= 2 * MAX_MOVE_BYTES
3155 && align == UNITS_PER_WORD)
3156 move_by_pieces (orig_dest, orig_src, bytes, align);
3158 else if (constp && bytes <= 2 * MAX_MOVE_BYTES)
3159 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3161 change_address (orig_src, BLKmode,
3163 bytes_rtx, align_rtx));
3165 else if (constp && align >= UNITS_PER_WORD && optimize)
3166 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3168 else if (constp && optimize)
3170 /* If the alignment is not word aligned, generate a test at
3171 runtime, to see whether things wound up aligned, and we
3172 can use the faster lw/sw instead ulw/usw. */
3174 rtx temp = gen_reg_rtx (Pmode);
3175 rtx aligned_label = gen_label_rtx ();
3176 rtx join_label = gen_label_rtx ();
3177 int leftover = bytes % MAX_MOVE_BYTES;
3181 if (Pmode == DImode)
3183 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3184 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3185 emit_insn (gen_cmpdi (temp, const0_rtx));
3189 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3190 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3191 emit_insn (gen_cmpsi (temp, const0_rtx));
3194 emit_jump_insn (gen_beq (aligned_label));
3196 /* Unaligned loop. */
3197 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3198 emit_jump_insn (gen_jump (join_label));
3202 emit_label (aligned_label);
3203 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3205 emit_label (join_label);
3207 /* Bytes at the end of the loop. */
3209 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3211 change_address (orig_src, BLKmode,
3218 block_move_call (dest_reg, src_reg, bytes_rtx);
3221 /* Emit load/stores for a small constant block_move.
3223 operands[0] is the memory address of the destination.
3224 operands[1] is the memory address of the source.
3225 operands[2] is the number of bytes to move.
3226 operands[3] is the alignment.
3227 operands[4] is a temp register.
3228 operands[5] is a temp register.
3230 operands[3+num_regs] is the last temp register.
3232 The block move type can be one of the following:
3233 BLOCK_MOVE_NORMAL Do all of the block move.
3234 BLOCK_MOVE_NOT_LAST Do all but the last store.
3235 BLOCK_MOVE_LAST Do just the last store. */
3238 output_block_move (insn, operands, num_regs, move_type)
3242 enum block_move_type move_type;
3244 rtx dest_reg = XEXP (operands[0], 0);
3245 rtx src_reg = XEXP (operands[1], 0);
3246 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3247 int align = INTVAL (operands[3]);
3250 int use_lwl_lwr = 0;
3251 int last_operand = num_regs + 4;
3257 const char *load; /* load insn without nop */
3258 const char *load_nop; /* load insn with trailing nop */
3259 const char *store; /* store insn */
3260 const char *final; /* if last_store used: NULL or swr */
3261 const char *last_store; /* last store instruction */
3262 int offset; /* current offset */
3263 enum machine_mode mode; /* mode to use on (MEM) */
3266 /* ??? Detect a bug in GCC, where it can give us a register
3267 the same as one of the addressing registers and reduce
3268 the number of registers available. */
3271 && safe_regs < (int)(sizeof(xoperands) / sizeof(xoperands[0]));
3273 if (! reg_mentioned_p (operands[i], operands[0])
3274 && ! reg_mentioned_p (operands[i], operands[1]))
3275 xoperands[safe_regs++] = operands[i];
3277 if (safe_regs < last_operand)
3279 xoperands[0] = operands[0];
3280 xoperands[1] = operands[1];
3281 xoperands[2] = operands[2];
3282 xoperands[3] = operands[3];
3283 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3286 /* If we are given global or static addresses, and we would be
3287 emitting a few instructions, try to save time by using a
3288 temporary register for the pointer. */
3289 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3290 an ldl/ldr instruction pair. We play it safe, and always move
3291 constant addresses into registers when generating N32/N64 code, just
3292 in case we might emit an unaligned load instruction. */
3293 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3294 || mips_abi == ABI_N32 || mips_abi == ABI_64))
3296 if (CONSTANT_P (src_reg))
3299 mips_count_memory_refs (operands[1], 1);
3301 src_reg = operands[3 + num_regs--];
3302 if (move_type != BLOCK_MOVE_LAST)
3304 xoperands[1] = operands[1];
3305 xoperands[0] = src_reg;
3306 if (Pmode == DImode)
3307 output_asm_insn ("dla\t%0,%1", xoperands);
3309 output_asm_insn ("la\t%0,%1", xoperands);
3313 if (CONSTANT_P (dest_reg))
3316 mips_count_memory_refs (operands[0], 1);
3318 dest_reg = operands[3 + num_regs--];
3319 if (move_type != BLOCK_MOVE_LAST)
3321 xoperands[1] = operands[0];
3322 xoperands[0] = dest_reg;
3323 if (Pmode == DImode)
3324 output_asm_insn ("dla\t%0,%1", xoperands);
3326 output_asm_insn ("la\t%0,%1", xoperands);
3331 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3332 are not offsettable, however, offsettable_address_p says they are
3333 offsettable. I think this is a bug in offsettable_address_p.
3334 For expediency, we fix this by just loading the address into a register
3335 if we happen to get one. */
3337 if (GET_CODE (src_reg) == LO_SUM)
3339 src_reg = operands[3 + num_regs--];
3340 if (move_type != BLOCK_MOVE_LAST)
3342 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3343 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3344 xoperands[0] = src_reg;
3345 if (Pmode == DImode)
3346 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3348 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3352 if (GET_CODE (dest_reg) == LO_SUM)
3354 dest_reg = operands[3 + num_regs--];
3355 if (move_type != BLOCK_MOVE_LAST)
3357 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3358 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3359 xoperands[0] = dest_reg;
3360 if (Pmode == DImode)
3361 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3363 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3367 if (num_regs > (int)(sizeof (load_store) / sizeof (load_store[0])))
3368 num_regs = sizeof (load_store) / sizeof (load_store[0]);
3370 else if (num_regs < 1)
3371 abort_with_insn (insn,
3372 "Cannot do block move, not enough scratch registers");
3376 load_store[num].offset = offset;
3378 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3380 load_store[num].load = "ld\t%0,%1";
3381 load_store[num].load_nop = "ld\t%0,%1%#";
3382 load_store[num].store = "sd\t%0,%1";
3383 load_store[num].last_store = "sd\t%0,%1";
3384 load_store[num].final = 0;
3385 load_store[num].mode = DImode;
3390 /* ??? Fails because of a MIPS assembler bug? */
3391 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3393 if (BYTES_BIG_ENDIAN)
3395 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3396 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3397 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3398 load_store[num].last_store = "sdr\t%0,%2";
3399 load_store[num].final = "sdl\t%0,%1";
3403 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3404 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3405 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3406 load_store[num].last_store = "sdr\t%0,%1";
3407 load_store[num].final = "sdl\t%0,%2";
3410 load_store[num].mode = DImode;
3416 else if (bytes >= 4 && align >= 4)
3418 load_store[num].load = "lw\t%0,%1";
3419 load_store[num].load_nop = "lw\t%0,%1%#";
3420 load_store[num].store = "sw\t%0,%1";
3421 load_store[num].last_store = "sw\t%0,%1";
3422 load_store[num].final = 0;
3423 load_store[num].mode = SImode;
3428 else if (bytes >= 4 && ! TARGET_MIPS16)
3430 if (BYTES_BIG_ENDIAN)
3432 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3433 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3434 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3435 load_store[num].last_store = "swr\t%0,%2";
3436 load_store[num].final = "swl\t%0,%1";
3440 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3441 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3442 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3443 load_store[num].last_store = "swr\t%0,%1";
3444 load_store[num].final = "swl\t%0,%2";
3447 load_store[num].mode = SImode;
3453 else if (bytes >= 2 && align >= 2)
3455 load_store[num].load = "lh\t%0,%1";
3456 load_store[num].load_nop = "lh\t%0,%1%#";
3457 load_store[num].store = "sh\t%0,%1";
3458 load_store[num].last_store = "sh\t%0,%1";
3459 load_store[num].final = 0;
3460 load_store[num].mode = HImode;
3466 load_store[num].load = "lb\t%0,%1";
3467 load_store[num].load_nop = "lb\t%0,%1%#";
3468 load_store[num].store = "sb\t%0,%1";
3469 load_store[num].last_store = "sb\t%0,%1";
3470 load_store[num].final = 0;
3471 load_store[num].mode = QImode;
3476 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3478 dslots_load_total++;
3479 dslots_load_filled++;
3481 if (CONSTANT_P (src_reg))
3482 mips_count_memory_refs (src_reg, 1);
3484 if (CONSTANT_P (dest_reg))
3485 mips_count_memory_refs (dest_reg, 1);
3488 /* Emit load/stores now if we have run out of registers or are
3489 at the end of the move. */
3491 if (++num == num_regs || bytes == 0)
3493 /* If only load/store, we need a NOP after the load. */
3496 load_store[0].load = load_store[0].load_nop;
3497 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3498 dslots_load_filled--;
3501 if (move_type != BLOCK_MOVE_LAST)
3503 for (i = 0; i < num; i++)
3507 if (!operands[i + 4])
3510 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3511 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3512 REGNO (operands[i + 4]));
3514 offset = load_store[i].offset;
3515 xoperands[0] = operands[i + 4];
3516 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3517 plus_constant (src_reg, offset));
3522 = GET_MODE_SIZE (load_store[i].mode) - 1;
3524 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3525 plus_constant (src_reg,
3530 output_asm_insn (load_store[i].load, xoperands);
3534 for (i = 0; i < num; i++)
3536 int last_p = (i == num-1 && bytes == 0);
3537 int offset = load_store[i].offset;
3539 xoperands[0] = operands[i + 4];
3540 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3541 plus_constant (dest_reg, offset));
3546 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3547 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3548 plus_constant (dest_reg,
3553 if (move_type == BLOCK_MOVE_NORMAL)
3554 output_asm_insn (load_store[i].store, xoperands);
3556 else if (move_type == BLOCK_MOVE_NOT_LAST)
3559 output_asm_insn (load_store[i].store, xoperands);
3561 else if (load_store[i].final != 0)
3562 output_asm_insn (load_store[i].final, xoperands);
3566 output_asm_insn (load_store[i].last_store, xoperands);
3569 num = 0; /* reset load_store */
3577 /* Argument support functions. */
3579 /* Initialize CUMULATIVE_ARGS for a function. */
3582 init_cumulative_args (cum, fntype, libname)
3583 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3584 tree fntype; /* tree ptr for function decl */
3585 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3587 static CUMULATIVE_ARGS zero_cum;
3588 tree param, next_param;
3590 if (TARGET_DEBUG_E_MODE)
3593 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3596 fputc ('\n', stderr);
3600 tree ret_type = TREE_TYPE (fntype);
3601 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3602 tree_code_name[(int)TREE_CODE (fntype)],
3603 tree_code_name[(int)TREE_CODE (ret_type)]);
3609 /* Determine if this function has variable arguments. This is
3610 indicated by the last argument being 'void_type_mode' if there
3611 are no variable arguments. The standard MIPS calling sequence
3612 passes all arguments in the general purpose registers in this case. */
3614 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3615 param != 0; param = next_param)
3617 next_param = TREE_CHAIN (param);
3618 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3619 cum->gp_reg_found = 1;
3623 /* Advance the argument to the next argument position. */
3626 function_arg_advance (cum, mode, type, named)
3627 CUMULATIVE_ARGS *cum; /* current arg information */
3628 enum machine_mode mode; /* current arg mode */
3629 tree type; /* type of the argument or 0 if lib support */
3630 int named; /* whether or not the argument was named */
3632 if (TARGET_DEBUG_E_MODE)
3635 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3636 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3637 GET_MODE_NAME (mode));
3638 fprintf (stderr, HOST_PTR_PRINTF, type);
3639 fprintf (stderr, ", %d )\n\n", named);
3649 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3650 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3653 cum->gp_reg_found = 1;
3654 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3659 cum->gp_reg_found = 1;
3660 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3665 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3666 cum->fp_arg_words++;
3669 if (! cum->gp_reg_found && cum->arg_number <= 2)
3670 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3674 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3675 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3677 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3678 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3679 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3683 cum->gp_reg_found = 1;
3684 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3690 cum->gp_reg_found = 1;
3696 /* Return an RTL expression containing the register for the given mode,
3697 or 0 if the argument is to be passed on the stack. */
3700 function_arg (cum, mode, type, named)
3701 CUMULATIVE_ARGS *cum; /* current arg information */
3702 enum machine_mode mode; /* current arg mode */
3703 tree type; /* type of the argument or 0 if lib support */
3704 int named; /* != 0 for normal args, == 0 for ... args */
3709 int *arg_words = &cum->arg_words;
3710 int struct_p = (type != 0
3711 && (TREE_CODE (type) == RECORD_TYPE
3712 || TREE_CODE (type) == UNION_TYPE
3713 || TREE_CODE (type) == QUAL_UNION_TYPE));
3715 if (TARGET_DEBUG_E_MODE)
3718 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3719 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3720 GET_MODE_NAME (mode));
3721 fprintf (stderr, HOST_PTR_PRINTF, type);
3722 fprintf (stderr, ", %d ) = ", named);
3726 cum->last_arg_fp = 0;
3730 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3732 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3733 regbase = GP_ARG_FIRST;
3736 regbase = FP_ARG_FIRST;
3738 /* If the first arg was a float in a floating point register,
3739 then set bias to align this float arg properly. */
3740 if (cum->arg_words == 1)
3744 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3747 cum->fp_arg_words += cum->fp_arg_words & 1;
3748 cum->last_arg_fp = 1;
3749 arg_words = &cum->fp_arg_words;
3750 regbase = FP_ARG_FIRST;
3753 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3759 if (mips_abi == ABI_EABI
3760 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3761 cum->fp_arg_words += cum->fp_arg_words & 1;
3763 cum->arg_words += cum->arg_words & 1;
3766 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3767 regbase = ((cum->gp_reg_found
3768 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
3769 || cum->arg_number >= 2)
3770 ? GP_ARG_FIRST : FP_ARG_FIRST);
3771 else if (mips_abi == ABI_EABI
3772 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3774 cum->last_arg_fp = 1;
3775 arg_words = &cum->fp_arg_words;
3776 regbase = FP_ARG_FIRST;
3779 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3780 ? GP_ARG_FIRST : FP_ARG_FIRST);
3784 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3785 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3788 /* Drops through. */
3790 if (type != (tree)0 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
3791 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3792 cum->arg_words += (cum->arg_words & 1);
3793 regbase = GP_ARG_FIRST;
3800 regbase = GP_ARG_FIRST;
3805 cum->arg_words += (cum->arg_words & 1);
3806 regbase = GP_ARG_FIRST;
3809 if (*arg_words >= MAX_ARGS_IN_REGISTERS)
3811 if (TARGET_DEBUG_E_MODE)
3812 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
3821 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
3822 || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named)
3823 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
3826 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3827 structure contains a double in its entirety, then that 64 bit
3828 chunk is passed in a floating point register. */
3831 /* First check to see if there is any such field. */
3832 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3833 if (TREE_CODE (field) == FIELD_DECL
3834 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3835 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3836 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3837 % BITS_PER_WORD == 0))
3840 /* If the whole struct fits a DFmode register,
3841 we don't need the PARALLEL. */
3842 if (! field || mode == DFmode)
3843 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
3846 /* Now handle the special case by returning a PARALLEL
3847 indicating where each 64 bit chunk goes. */
3853 /* ??? If this is a packed structure, then the last hunk won't
3856 chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
3857 if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
3858 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
3860 /* assign_parms checks the mode of ENTRY_PARM, so we must
3861 use the actual mode here. */
3862 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
3865 regno = regbase + *arg_words + bias;
3866 field = TYPE_FIELDS (type);
3867 for (i = 0; i < chunks; i++)
3871 for (; field; field = TREE_CHAIN (field))
3872 if (TREE_CODE (field) == FIELD_DECL
3873 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3878 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
3879 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3880 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3881 reg = gen_rtx_REG (DFmode,
3882 regno + FP_ARG_FIRST - GP_ARG_FIRST);
3884 reg = gen_rtx_REG (word_mode, regno);
3887 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3888 GEN_INT (bitpos / BITS_PER_UNIT));
3896 if (TARGET_DEBUG_E_MODE)
3897 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
3898 struct_p ? ", [struct]" : "");
3900 /* The following is a hack in order to pass 1 byte structures
3901 the same way that the MIPS compiler does (namely by passing
3902 the structure in the high byte or half word of the register).
3903 This also makes varargs work. If we have such a structure,
3904 we save the adjustment RTL, and the call define expands will
3905 emit them. For the VOIDmode argument (argument after the
3906 last real argument), pass back a parallel vector holding each
3907 of the adjustments. */
3909 /* ??? function_arg can be called more than once for each argument.
3910 As a result, we compute more adjustments than we need here.
3911 See the CUMULATIVE_ARGS definition in mips.h. */
3913 /* ??? This scheme requires everything smaller than the word size to
3914 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3915 that would mean every int needs to be shifted left, which is very
3916 inefficient. Let's not carry this compatibility to the 64 bit
3917 calling convention for now. */
3919 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
3920 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3922 rtx amount = GEN_INT (BITS_PER_WORD
3923 - int_size_in_bytes (type) * BITS_PER_UNIT);
3924 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
3927 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
3929 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
3933 /* We will be called with a mode of VOIDmode after the last argument
3934 has been seen. Whatever we return will be passed to the call
3935 insn. If we need any shifts for small structures, return them in
3936 a PARALLEL; in that case, stuff the mips16 fp_code in as the
3937 mode. Otherwise, if we have need a mips16 fp_code, return a REG
3938 with the code stored as the mode. */
3939 if (mode == VOIDmode)
3941 if (cum->num_adjusts > 0)
3942 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
3943 gen_rtvec_v (cum->num_adjusts, cum->adjust));
3944 else if (TARGET_MIPS16 && cum->fp_code != 0)
3945 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
3952 function_arg_partial_nregs (cum, mode, type, named)
3953 CUMULATIVE_ARGS *cum; /* current arg information */
3954 enum machine_mode mode; /* current arg mode */
3955 tree type; /* type of the argument or 0 if lib support */
3956 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
3958 if ((mode == BLKmode
3959 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3960 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3961 && cum->arg_words < MAX_ARGS_IN_REGISTERS
3962 && mips_abi != ABI_EABI)
3965 if (mode == BLKmode)
3966 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3969 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3971 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
3972 return 0; /* structure fits in registers */
3974 if (TARGET_DEBUG_E_MODE)
3975 fprintf (stderr, "function_arg_partial_nregs = %d\n",
3976 MAX_ARGS_IN_REGISTERS - cum->arg_words);
3978 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
3981 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
3982 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3984 if (TARGET_DEBUG_E_MODE)
3985 fprintf (stderr, "function_arg_partial_nregs = 1\n");
3993 /* Create the va_list data type. */
3996 mips_build_va_list ()
3998 if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4000 tree f_fpr, f_rem, f_gpr, record;
4002 record = make_node (RECORD_TYPE);
4004 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fp_regs"),
4006 f_rem = build_decl (FIELD_DECL, get_identifier ("__fp_left"),
4008 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gp_regs"),
4011 DECL_FIELD_CONTEXT (f_fpr) = record;
4012 DECL_FIELD_CONTEXT (f_rem) = record;
4013 DECL_FIELD_CONTEXT (f_gpr) = record;
4015 TYPE_FIELDS (record) = f_fpr;
4016 TREE_CHAIN (f_fpr) = f_rem;
4017 TREE_CHAIN (f_gpr) = f_gpr;
4019 layout_type (record);
4024 return ptr_type_node;
4027 /* Implement va_start. */
4030 mips_va_start (stdarg_p, valist, nextarg)
4035 int arg_words, fp_arg_words;
4038 arg_words = current_function_args_info.arg_words;
4039 fp_arg_words = current_function_args_info.fp_arg_words;
4041 if (mips_abi == ABI_EABI)
4043 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4045 tree f_fpr, f_rem, f_gpr, fpr, rem, gpr;
4049 f_fpr = TYPE_FIELDS (va_list_type_node);
4050 f_rem = TREE_CHAIN (f_fpr);
4051 f_gpr = TREE_CHAIN (f_gpr);
4053 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4054 rem = build (COMPONENT_REF, TREE_TYPE (f_rem), valist, f_rem);
4055 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4058 gpro = (8 - arg_words) * UNITS_PER_WORD;
4060 gpro = (stdarg_p ? 0 : UNITS_PER_WORD);
4062 gprv = make_tree (ptr_type_node, nextarg);
4065 gprv = build (PLUS_EXPR, ptr_type_node, gprv,
4066 build_int_2 (-gpro, -1));
4069 t = build (MODIFY_EXPR, ptr_type_node, gpr, gprv);
4070 TREE_SIDE_EFFECTS (t) = 1;
4071 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4073 t = build (MODIFY_EXPR, integer_type_node, rem,
4074 build_int_2 (8 - fp_arg_words, 0));
4075 TREE_SIDE_EFFECTS (t) = 1;
4076 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4078 fpro = (8 - fp_arg_words) * 8;
4082 fprv = fold (build (PLUS_EXPR, ptr_type_node, gprv,
4083 build_int_2 (-fpro, -1)));
4086 fprv = fold (build (BIT_AND_EXPR, ptr_type_node, fprv,
4087 build_int_2 (-8, -1)));
4089 t = build (MODIFY_EXPR, ptr_type_node, fpr, fprv);
4090 TREE_SIDE_EFFECTS (t) = 1;
4091 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4098 ofs = (stdarg_p ? 0 : UNITS_PER_WORD);
4100 ofs = (8 - arg_words) * UNITS_PER_WORD;
4102 nextarg = plus_constant (nextarg, -ofs);
4103 std_expand_builtin_va_start (1, valist, nextarg);
4114 /* ??? This had been conditional on
4115 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4116 and both iris5.h and iris6.h define _MIPS_SIM. */
4117 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4118 ofs = (arg_words >= 8 ? -UNITS_PER_WORD : 0);
4120 ofs = -UNITS_PER_WORD;
4123 nextarg = plus_constant (nextarg, ofs);
4124 std_expand_builtin_va_start (1, valist, nextarg);
4128 /* Implement va_arg. */
4131 mips_va_arg (valist, type)
4134 HOST_WIDE_INT size, rsize;
4138 size = int_size_in_bytes (type);
4139 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4141 if (mips_abi == ABI_EABI)
4145 rtx lab_over = NULL_RTX, lab_false, r;
4148 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4150 size = rsize = POINTER_SIZE / BITS_PER_UNIT;
4152 addr_rtx = gen_reg_rtx (Pmode);
4154 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4156 tree f_fpr, f_rem, f_gpr, fpr, rem;
4158 f_fpr = TYPE_FIELDS (va_list_type_node);
4159 f_rem = TREE_CHAIN (f_fpr);
4160 f_gpr = TREE_CHAIN (f_gpr);
4162 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4163 rem = build (COMPONENT_REF, TREE_TYPE (f_rem), valist, f_rem);
4164 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4166 if (TREE_CODE (type) == REAL_TYPE)
4168 lab_false = gen_label_rtx ();
4169 lab_over = gen_label_rtx ();
4171 r = expand_expr (rem, NULL_RTX, TYPE_MODE (TREE_TYPE (rem)),
4173 emit_cmp_and_jump_insns (r, const0_rtx, LE, const1_rtx,
4174 GET_MODE (r), 1, 1, lab_false);
4176 t = build (PLUS_EXPR, TREE_TYPE (rem), rem,
4177 build_int_2 (-1, -1));
4178 t = build (MODIFY_EXPR, TREE_TYPE (rem), rem, t);
4179 TREE_SIDE_EFFECTS (t) = 1;
4180 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4182 t = build (POSTINCREMENT_EXPR, TREE_TYPE (fpr), fpr,
4183 build_int_2 (8, 0));
4184 TREE_SIDE_EFFECTS (t) = 1;
4185 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4187 emit_move_insn (addr_rtx, r);
4189 emit_jump (gen_jump (lab_over));
4191 emit_label (lab_false);
4199 && TYPE_ALIGN (type) > BITS_PER_WORD)
4201 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4202 build_int_2 (2*UNITS_PER_WORD - 1, 0));
4203 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4204 build_int_2 (-2*UNITS_PER_WORD, -1));
4205 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4206 TREE_SIDE_EFFECTS (t) = 1;
4207 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4210 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr, rsize);
4211 TREE_SIDE_EFFECTS (t) = 1;
4212 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4214 emit_move_insn (addr_rtx, r);
4217 emit_label (lab_over);
4221 r = gen_rtx_MEM (Pmode, addr_rtx);
4222 MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4223 emit_move_insn (addr_rtx, r);
4227 if (BYTES_BIG_ENDIAN && rsize != size)
4228 addr_rtx = plus_constant (addr_rtx, rsize - size);
4235 /* ??? The original va-mips.h did always align, despite the fact
4236 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4237 increment mechanism. */
4241 else if (TYPE_ALIGN (type) > 32)
4246 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4247 build_int_2 (align - 1, 0));
4248 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4249 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4250 TREE_SIDE_EFFECTS (t) = 1;
4251 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4253 /* Everything past the alignment is standard. */
4254 return std_expand_builtin_va_arg (valist, type);
4258 /* Abort after printing out a specific insn. */
4261 abort_with_insn (insn, reason)
4270 /* Write a message to stderr (for use in macros expanded in files that do not
4271 include stdio.h). */
4277 fprintf (stderr, s, s1, s2);
4280 /* Set up the threshold for data to go into the small data area, instead
4281 of the normal data area, and detect any conflicts in the switches. */
4286 register int i, start;
4288 register enum machine_mode mode;
4290 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4292 if (mips_section_threshold <= 0)
4293 target_flags &= ~MASK_GPOPT;
4295 target_flags |= MASK_GPOPT;
4297 #ifndef MIPS_ISA_DEFAULT
4298 #define MIPS_ISA_DEFAULT 1
4301 /* If both single-float and soft-float are set, then clear the one that
4302 was set by TARGET_DEFAULT, leaving the one that was set by the
4303 user. We assume here that the specs prevent both being set by the
4305 #ifdef TARGET_DEFAULT
4306 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4307 target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT));
4310 /* Get the architectural level. */
4311 if (mips_isa_string == 0)
4312 mips_isa = MIPS_ISA_DEFAULT;
4314 else if (ISDIGIT (*mips_isa_string))
4316 mips_isa = atoi (mips_isa_string);
4319 /* -mno-mips16 overrides -mips16. */
4320 if (mips_no_mips16_string == NULL)
4322 target_flags |= MASK_MIPS16;
4326 mips_isa = MIPS_ISA_DEFAULT;
4330 mips_isa = MIPS_ISA_DEFAULT;
4333 else if (mips_isa < 1 || mips_isa > 4)
4335 error ("-mips%d not supported", mips_isa);
4342 error ("bad value (%s) for -mips switch", mips_isa_string);
4346 #ifdef MIPS_ABI_DEFAULT
4347 /* Get the ABI to use. */
4348 if (mips_abi_string == (char *) 0)
4349 mips_abi = MIPS_ABI_DEFAULT;
4350 else if (! strcmp (mips_abi_string, "32"))
4352 else if (! strcmp (mips_abi_string, "o64"))
4354 else if (! strcmp (mips_abi_string, "n32"))
4356 else if (! strcmp (mips_abi_string, "64"))
4358 else if (! strcmp (mips_abi_string, "eabi"))
4359 mips_abi = ABI_EABI;
4361 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4363 /* A specified ISA defaults the ABI if it was not specified. */
4364 if (mips_abi_string == 0 && mips_isa_string
4365 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4373 /* A specified ABI defaults the ISA if it was not specified. */
4374 else if (mips_isa_string == 0 && mips_abi_string
4375 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4377 if (mips_abi == ABI_32)
4379 else if (mips_abi == ABI_N32)
4385 /* If both ABI and ISA were specified, check for conflicts. */
4386 else if (mips_isa_string && mips_abi_string)
4388 if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64
4389 || mips_abi == ABI_O64))
4390 || (mips_isa >= 3 && mips_abi == ABI_32))
4391 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4394 /* Override TARGET_DEFAULT if necessary. */
4395 if (mips_abi == ABI_32)
4396 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4398 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4399 then set the type sizes. In the EABI in 64 bit mode, longs and
4400 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4401 if (mips_explicit_type_size_string == NULL
4402 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4403 || mips_abi == ABI_64))
4404 target_flags |= MASK_LONG64;
4406 /* ??? This doesn't work yet, so don't let people try to use it. */
4407 if (mips_abi == ABI_32)
4408 error ("The -mabi=32 support does not work yet.");
4411 if (mips_abi_string)
4412 error ("This target does not support the -mabi switch.");
4415 #ifdef MIPS_CPU_STRING_DEFAULT
4416 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4417 greater than that supported by the default processor, then the user gets
4418 an error. Normally, the compiler will just default to the base level cpu
4419 for the indicated isa. */
4420 if (mips_cpu_string == 0)
4421 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4424 /* Identify the processor type */
4425 if (mips_cpu_string == 0
4426 || !strcmp (mips_cpu_string, "default")
4427 || !strcmp (mips_cpu_string, "DEFAULT"))
4432 mips_cpu_string = "3000";
4433 mips_cpu = PROCESSOR_R3000;
4436 mips_cpu_string = "6000";
4437 mips_cpu = PROCESSOR_R6000;
4440 mips_cpu_string = "4000";
4441 mips_cpu = PROCESSOR_R4000;
4444 mips_cpu_string = "8000";
4445 mips_cpu = PROCESSOR_R8000;
4452 const char *p = mips_cpu_string;
4455 /* We need to cope with the various "vr" prefixes for the NEC 4300
4456 and 4100 processors. */
4457 if (*p == 'v' || *p == 'V')
4460 if (*p == 'r' || *p == 'R')
4463 /* Since there is no difference between a R2000 and R3000 in
4464 terms of the scheduler, we collapse them into just an R3000. */
4466 mips_cpu = PROCESSOR_DEFAULT;
4470 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4471 mips_cpu = PROCESSOR_R3000;
4475 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4476 mips_cpu = PROCESSOR_R3000;
4477 else if (!strcmp (p, "3900"))
4478 mips_cpu = PROCESSOR_R3900;
4482 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4483 mips_cpu = PROCESSOR_R4000;
4484 /* The vr4100 is a non-FP ISA III processor with some extra
4486 else if (!strcmp (p, "4100"))
4488 mips_cpu = PROCESSOR_R4100;
4489 target_flags |= MASK_SOFT_FLOAT ;
4491 /* The vr4300 is a standard ISA III processor, but with a different
4493 else if (!strcmp (p, "4300"))
4494 mips_cpu = PROCESSOR_R4300;
4495 /* The r4400 is exactly the same as the r4000 from the compiler's
4497 else if (!strcmp (p, "4400"))
4498 mips_cpu = PROCESSOR_R4000;
4499 else if (!strcmp (p, "4600"))
4500 mips_cpu = PROCESSOR_R4600;
4501 else if (!strcmp (p, "4650"))
4502 mips_cpu = PROCESSOR_R4650;
4506 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4507 mips_cpu = PROCESSOR_R5000;
4511 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4512 mips_cpu = PROCESSOR_R6000;
4516 if (!strcmp (p, "8000"))
4517 mips_cpu = PROCESSOR_R8000;
4521 if (!strcmp (p, "orion"))
4522 mips_cpu = PROCESSOR_R4600;
4527 && mips_cpu != PROCESSOR_R4300
4528 && mips_cpu != PROCESSOR_R4100
4529 && mips_cpu != PROCESSOR_R5000)
4530 mips_cpu = PROCESSOR_DEFAULT;
4532 if (mips_cpu == PROCESSOR_DEFAULT)
4534 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4535 mips_cpu_string = "default";
4539 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
4540 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
4541 || ((mips_cpu == PROCESSOR_R4000
4542 || mips_cpu == PROCESSOR_R4100
4543 || mips_cpu == PROCESSOR_R4300
4544 || mips_cpu == PROCESSOR_R4600
4545 || mips_cpu == PROCESSOR_R4650)
4547 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4549 /* make sure sizes of ints/longs/etc. are ok */
4553 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
4555 else if (TARGET_64BIT)
4556 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
4559 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4560 flag_pcc_struct_return = 0;
4562 /* Tell halfpic.c that we have half-pic code if we do. */
4563 if (TARGET_HALF_PIC)
4566 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4567 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4568 /* ??? -non_shared turns off pic code generation, but this is not
4570 if (TARGET_ABICALLS)
4572 mips_abicalls = MIPS_ABICALLS_YES;
4574 if (mips_section_threshold > 0)
4575 warning ("-G is incompatible with PIC code which is the default");
4578 mips_abicalls = MIPS_ABICALLS_NO;
4580 /* -membedded-pic is a form of PIC code suitable for embedded
4581 systems. All calls are made using PC relative addressing, and
4582 all data is addressed using the $gp register. This requires gas,
4583 which does most of the work, and GNU ld, which automatically
4584 expands PC relative calls which are out of range into a longer
4585 instruction sequence. All gcc really does differently is
4586 generate a different sequence for a switch. */
4587 if (TARGET_EMBEDDED_PIC)
4590 if (TARGET_ABICALLS)
4591 warning ("-membedded-pic and -mabicalls are incompatible");
4594 warning ("-G and -membedded-pic are incompatible");
4596 /* Setting mips_section_threshold is not required, because gas
4597 will force everything to be GP addressable anyhow, but
4598 setting it will cause gcc to make better estimates of the
4599 number of instructions required to access a particular data
4601 mips_section_threshold = 0x7fffffff;
4604 /* This optimization requires a linker that can support a R_MIPS_LO16
4605 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
4606 GNU ld has this support, but not all other MIPS linkers do, so we enable
4607 this optimization only if the user requests it, or if GNU ld is the
4608 standard linker for this configuration. */
4609 /* ??? This does not work when target addresses are DImode.
4610 This is because we are missing DImode high/lo_sum patterns. */
4611 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
4613 mips_split_addresses = 1;
4615 mips_split_addresses = 0;
4617 /* -mrnames says to use the MIPS software convention for register
4618 names instead of the hardware names (ie, $a0 instead of $4).
4619 We do this by switching the names in mips_reg_names, which the
4620 reg_names points into via the REGISTER_NAMES macro. */
4622 if (TARGET_NAME_REGS)
4623 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names,
4624 sizeof (mips_reg_names));
4626 /* When compiling for the mips16, we can not use floating point. We
4627 record the original hard float value in mips16_hard_float. */
4630 if (TARGET_SOFT_FLOAT)
4631 mips16_hard_float = 0;
4633 mips16_hard_float = 1;
4634 target_flags |= MASK_SOFT_FLOAT;
4636 /* Don't run the scheduler before reload, since it tends to
4637 increase register pressure. */
4638 flag_schedule_insns = 0;
4641 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
4642 to avoid using up another bit in target_flags. */
4643 if (mips_entry_string != NULL)
4645 if (*mips_entry_string != '\0')
4646 error ("Invalid option `entry%s'", mips_entry_string);
4648 if (! TARGET_MIPS16)
4649 warning ("-mentry is only meaningful with -mips-16");
4654 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
4655 attributes can access it. */
4661 /* Initialize the high and low values for legitimate floating point
4662 constants. Rather than trying to get the accuracy down to the
4663 last bit, just use approximate ranges. */
4664 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
4665 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
4666 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
4667 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
4669 mips_print_operand_punct['?'] = 1;
4670 mips_print_operand_punct['#'] = 1;
4671 mips_print_operand_punct['&'] = 1;
4672 mips_print_operand_punct['!'] = 1;
4673 mips_print_operand_punct['*'] = 1;
4674 mips_print_operand_punct['@'] = 1;
4675 mips_print_operand_punct['.'] = 1;
4676 mips_print_operand_punct['('] = 1;
4677 mips_print_operand_punct[')'] = 1;
4678 mips_print_operand_punct['['] = 1;
4679 mips_print_operand_punct[']'] = 1;
4680 mips_print_operand_punct['<'] = 1;
4681 mips_print_operand_punct['>'] = 1;
4682 mips_print_operand_punct['{'] = 1;
4683 mips_print_operand_punct['}'] = 1;
4684 mips_print_operand_punct['^'] = 1;
4685 mips_print_operand_punct['$'] = 1;
4686 mips_print_operand_punct['+'] = 1;
4687 mips_print_operand_punct['~'] = 1;
4689 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4690 mips_char_to_class['e'] = M16_NA_REGS;
4691 mips_char_to_class['t'] = T_REG;
4692 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4693 mips_char_to_class['h'] = HI_REG;
4694 mips_char_to_class['l'] = LO_REG;
4695 mips_char_to_class['a'] = HILO_REG;
4696 mips_char_to_class['x'] = MD_REGS;
4697 mips_char_to_class['b'] = ALL_REGS;
4698 mips_char_to_class['y'] = GR_REGS;
4699 mips_char_to_class['z'] = ST_REGS;
4701 /* Set up array to map GCC register number to debug register number.
4702 Ignore the special purpose register numbers. */
4704 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4705 mips_dbx_regno[i] = -1;
4707 start = GP_DBX_FIRST - GP_REG_FIRST;
4708 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4709 mips_dbx_regno[i] = i + start;
4711 start = FP_DBX_FIRST - FP_REG_FIRST;
4712 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4713 mips_dbx_regno[i] = i + start;
4715 /* Set up array giving whether a given register can hold a given mode.
4716 At present, restrict ints from being in FP registers, because reload
4717 is a little enthusiastic about storing extra values in FP registers,
4718 and this is not good for things like OS kernels. Also, due to the
4719 mandatory delay, it is as fast to load from cached memory as to move
4720 from the FP register. */
4722 for (mode = VOIDmode;
4723 mode != MAX_MACHINE_MODE;
4724 mode = (enum machine_mode) ((int)mode + 1))
4726 register int size = GET_MODE_SIZE (mode);
4727 register enum mode_class class = GET_MODE_CLASS (mode);
4729 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4736 temp = (regno == FPSW_REGNUM);
4738 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4739 || FP_REG_P (regno));
4742 else if (GP_REG_P (regno))
4743 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4745 else if (FP_REG_P (regno))
4746 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
4747 && (class == MODE_FLOAT
4748 || class == MODE_COMPLEX_FLOAT
4749 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
4750 && (! TARGET_SINGLE_FLOAT || size <= 4));
4752 else if (MD_REG_P (regno))
4753 temp = (class == MODE_INT
4754 && (size <= UNITS_PER_WORD
4755 || (regno == MD_REG_FIRST
4756 && size == 2 * UNITS_PER_WORD)));
4761 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4765 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4766 initialized yet, so we can't use that here. */
4767 gpr_mode = TARGET_64BIT ? DImode : SImode;
4769 /* Provide default values for align_* for 64-bit targets. */
4772 if (align_loops == 0)
4774 if (align_jumps == 0)
4776 if (align_functions == 0)
4777 align_functions = 8;
4780 /* Register global variables with the garbage collector. */
4781 mips_add_gc_roots ();
4784 /* On the mips16, we want to allocate $24 (T_REG) before other
4785 registers for instructions for which it is possible. This helps
4786 avoid shuffling registers around in order to set up for an xor,
4787 encouraging the compiler to use a cmp instead. */
4790 mips_order_regs_for_local_alloc ()
4794 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4795 reg_alloc_order[i] = i;
4799 /* It really doesn't matter where we put register 0, since it is
4800 a fixed register anyhow. */
4801 reg_alloc_order[0] = 24;
4802 reg_alloc_order[24] = 0;
4807 /* The MIPS debug format wants all automatic variables and arguments
4808 to be in terms of the virtual frame pointer (stack pointer before
4809 any adjustment in the function), while the MIPS 3.0 linker wants
4810 the frame pointer to be the stack pointer after the initial
4811 adjustment. So, we do the adjustment here. The arg pointer (which
4812 is eliminated) points to the virtual frame pointer, while the frame
4813 pointer (which may be eliminated) points to the stack pointer after
4814 the initial adjustments. */
4817 mips_debugger_offset (addr, offset)
4819 HOST_WIDE_INT offset;
4821 rtx offset2 = const0_rtx;
4822 rtx reg = eliminate_constant_term (addr, &offset2);
4825 offset = INTVAL (offset2);
4827 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4828 || reg == hard_frame_pointer_rtx)
4830 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
4831 ? compute_frame_size (get_frame_size ())
4832 : current_frame_info.total_size;
4834 /* MIPS16 frame is smaller */
4835 if (frame_pointer_needed && TARGET_MIPS16)
4836 frame_size -= current_function_outgoing_args_size;
4838 offset = offset - frame_size;
4841 /* sdbout_parms does not want this to crash for unrecognized cases. */
4843 else if (reg != arg_pointer_rtx)
4844 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
4850 /* A C compound statement to output to stdio stream STREAM the
4851 assembler syntax for an instruction operand X. X is an RTL
4854 CODE is a value that can be used to specify one of several ways
4855 of printing the operand. It is used when identical operands
4856 must be printed differently depending on the context. CODE
4857 comes from the `%' specification that was used to request
4858 printing of the operand. If the specification was just `%DIGIT'
4859 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4860 is the ASCII code for LTR.
4862 If X is a register, this macro should print the register's name.
4863 The names can be found in an array `reg_names' whose type is
4864 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4866 When the machine description has a specification `%PUNCT' (a `%'
4867 followed by a punctuation character), this macro is called with
4868 a null pointer for X and the punctuation character for CODE.
4870 The MIPS specific codes are:
4872 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4873 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4874 'd' output integer constant in decimal,
4875 'z' if the operand is 0, use $0 instead of normal operand.
4876 'D' print second register of double-word register operand.
4877 'L' print low-order register of double-word register operand.
4878 'M' print high-order register of double-word register operand.
4879 'C' print part of opcode for a branch condition.
4880 'F' print part of opcode for a floating-point branch condition.
4881 'N' print part of opcode for a branch condition, inverted.
4882 'W' print part of opcode for a floating-point branch condition, inverted.
4883 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
4884 'B' print 'z' for EQ, 'n' for NE
4885 'b' print 'n' for EQ, 'z' for NE
4886 'T' print 'f' for EQ, 't' for NE
4887 't' print 't' for EQ, 'f' for NE
4888 'Z' print register and a comma, but print nothing for $fcc0
4889 '(' Turn on .set noreorder
4890 ')' Turn on .set reorder
4891 '[' Turn on .set noat
4893 '<' Turn on .set nomacro
4894 '>' Turn on .set macro
4895 '{' Turn on .set volatile (not GAS)
4896 '}' Turn on .set novolatile (not GAS)
4897 '&' Turn on .set noreorder if filling delay slots
4898 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4899 '!' Turn on .set nomacro if filling delay slots
4900 '#' Print nop if in a .set noreorder section.
4901 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4902 '@' Print the name of the assembler temporary register (at or $1).
4903 '.' Print the name of the register with a hard-wired zero (zero or $0).
4904 '^' Print the name of the pic call-through register (t9 or $25).
4905 '$' Print the name of the stack pointer register (sp or $29).
4906 '+' Print the name of the gp register (gp or $28).
4907 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
4910 print_operand (file, op, letter)
4911 FILE *file; /* file to write to */
4912 rtx op; /* operand to print */
4913 int letter; /* %<letter> or 0 */
4915 register enum rtx_code code;
4917 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
4922 if (mips_branch_likely)
4927 fputs (reg_names [GP_REG_FIRST + 1], file);
4931 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
4935 fputs (reg_names [GP_REG_FIRST + 0], file);
4939 fputs (reg_names[STACK_POINTER_REGNUM], file);
4943 fputs (reg_names[GP_REG_FIRST + 28], file);
4947 if (final_sequence != 0 && set_noreorder++ == 0)
4948 fputs (".set\tnoreorder\n\t", file);
4952 if (final_sequence != 0)
4954 if (set_noreorder++ == 0)
4955 fputs (".set\tnoreorder\n\t", file);
4957 if (set_nomacro++ == 0)
4958 fputs (".set\tnomacro\n\t", file);
4963 if (final_sequence != 0 && set_nomacro++ == 0)
4964 fputs ("\n\t.set\tnomacro", file);
4968 if (set_noreorder != 0)
4969 fputs ("\n\tnop", file);
4970 else if (TARGET_STATS)
4971 fputs ("\n\t#nop", file);
4976 if (set_noreorder++ == 0)
4977 fputs (".set\tnoreorder\n\t", file);
4981 if (set_noreorder == 0)
4982 error ("internal error: %%) found without a %%( in assembler pattern");
4984 else if (--set_noreorder == 0)
4985 fputs ("\n\t.set\treorder", file);
4990 if (set_noat++ == 0)
4991 fputs (".set\tnoat\n\t", file);
4996 error ("internal error: %%] found without a %%[ in assembler pattern");
4997 else if (--set_noat == 0)
4998 fputs ("\n\t.set\tat", file);
5003 if (set_nomacro++ == 0)
5004 fputs (".set\tnomacro\n\t", file);
5008 if (set_nomacro == 0)
5009 error ("internal error: %%> found without a %%< in assembler pattern");
5010 else if (--set_nomacro == 0)
5011 fputs ("\n\t.set\tmacro", file);
5016 if (set_volatile++ == 0)
5017 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5021 if (set_volatile == 0)
5022 error ("internal error: %%} found without a %%{ in assembler pattern");
5023 else if (--set_volatile == 0)
5024 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5030 if (align_labels_log > 0)
5031 ASM_OUTPUT_ALIGN (file, align_labels_log);
5036 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
5045 error ("PRINT_OPERAND null pointer");
5049 code = GET_CODE (op);
5051 if (code == SIGN_EXTEND)
5052 op = XEXP (op, 0), code = GET_CODE (op);
5057 case EQ: fputs ("eq", file); break;
5058 case NE: fputs ("ne", file); break;
5059 case GT: fputs ("gt", file); break;
5060 case GE: fputs ("ge", file); break;
5061 case LT: fputs ("lt", file); break;
5062 case LE: fputs ("le", file); break;
5063 case GTU: fputs ("gtu", file); break;
5064 case GEU: fputs ("geu", file); break;
5065 case LTU: fputs ("ltu", file); break;
5066 case LEU: fputs ("leu", file); break;
5068 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5071 else if (letter == 'N')
5074 case EQ: fputs ("ne", file); break;
5075 case NE: fputs ("eq", file); break;
5076 case GT: fputs ("le", file); break;
5077 case GE: fputs ("lt", file); break;
5078 case LT: fputs ("ge", file); break;
5079 case LE: fputs ("gt", file); break;
5080 case GTU: fputs ("leu", file); break;
5081 case GEU: fputs ("ltu", file); break;
5082 case LTU: fputs ("geu", file); break;
5083 case LEU: fputs ("gtu", file); break;
5085 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5088 else if (letter == 'F')
5091 case EQ: fputs ("c1f", file); break;
5092 case NE: fputs ("c1t", file); break;
5094 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5097 else if (letter == 'W')
5100 case EQ: fputs ("c1t", file); break;
5101 case NE: fputs ("c1f", file); break;
5103 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5106 else if (letter == 'S')
5110 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5111 assemble_name (file, buffer);
5114 else if (letter == 'Z')
5116 register int regnum;
5121 regnum = REGNO (op);
5122 if (! ST_REG_P (regnum))
5125 if (regnum != ST_REG_FIRST)
5126 fprintf (file, "%s,", reg_names[regnum]);
5129 else if (code == REG || code == SUBREG)
5131 register int regnum;
5134 regnum = REGNO (op);
5136 regnum = true_regnum (op);
5138 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5139 || (letter == 'L' && WORDS_BIG_ENDIAN)
5143 fprintf (file, "%s", reg_names[regnum]);
5146 else if (code == MEM)
5147 output_address (XEXP (op, 0));
5149 else if (code == CONST_DOUBLE
5150 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5155 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5156 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5160 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5161 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5163 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5164 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5166 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5167 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5169 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5170 fputs (reg_names[GP_REG_FIRST], file);
5172 else if (letter == 'd' || letter == 'x' || letter == 'X')
5173 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
5176 else if (letter == 'B')
5177 fputs (code == EQ ? "z" : "n", file);
5178 else if (letter == 'b')
5179 fputs (code == EQ ? "n" : "z", file);
5180 else if (letter == 'T')
5181 fputs (code == EQ ? "f" : "t", file);
5182 else if (letter == 't')
5183 fputs (code == EQ ? "t" : "f", file);
5185 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5187 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5188 print_operand (file, XEXP (op, 0), letter);
5191 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5193 fputs ("%gprel(", file);
5194 mips16_output_gp_offset (file, op);
5199 output_addr_const (file, op);
5202 /* A C compound statement to output to stdio stream STREAM the
5203 assembler syntax for an instruction operand that is a memory
5204 reference whose address is ADDR. ADDR is an RTL expression.
5206 On some machines, the syntax for a symbolic address depends on
5207 the section that the address refers to. On these machines,
5208 define the macro `ENCODE_SECTION_INFO' to store the information
5209 into the `symbol_ref', and then check for it here. */
5212 print_operand_address (file, addr)
5217 error ("PRINT_OPERAND_ADDRESS, null pointer");
5220 switch (GET_CODE (addr))
5223 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5224 abort_with_insn (addr, "Arg pointer not eliminated.");
5226 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5231 register rtx arg0 = XEXP (addr, 0);
5232 register rtx arg1 = XEXP (addr, 1);
5234 if (! mips_split_addresses)
5235 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5237 if (GET_CODE (arg0) != REG)
5238 abort_with_insn (addr,
5239 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
5241 fprintf (file, "%%lo(");
5242 print_operand_address (file, arg1);
5243 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5249 register rtx reg = 0;
5250 register rtx offset = 0;
5251 register rtx arg0 = XEXP (addr, 0);
5252 register rtx arg1 = XEXP (addr, 1);
5254 if (GET_CODE (arg0) == REG)
5258 if (GET_CODE (offset) == REG)
5259 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5262 else if (GET_CODE (arg1) == REG)
5263 reg = arg1, offset = arg0;
5264 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5266 output_addr_const (file, addr);
5270 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5272 if (! CONSTANT_P (offset))
5273 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5275 if (REGNO (reg) == ARG_POINTER_REGNUM)
5276 abort_with_insn (addr, "Arg pointer not eliminated.");
5279 && GET_CODE (offset) == CONST
5280 && mips16_gp_offset_p (offset))
5282 fputs ("%gprel(", file);
5283 mips16_output_gp_offset (file, offset);
5287 output_addr_const (file, offset);
5288 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5296 output_addr_const (file, addr);
5300 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5306 /* If optimizing for the global pointer, keep track of all of the externs, so
5307 that at the end of the file, we can emit the appropriate .extern
5308 declaration for them, before writing out the text section. We assume all
5309 names passed to us are in the permanent obstack, so they will be valid at
5310 the end of the compilation.
5312 If we have -G 0, or the extern size is unknown, or the object is in a user
5313 specified section that is not .sbss/.sdata, don't bother emitting the
5314 .externs. In the case of user specified sections this behaviour is
5315 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5318 mips_output_external (file, decl, name)
5319 FILE *file ATTRIBUTE_UNUSED;
5323 register struct extern_list *p;
5328 && TREE_CODE (decl) != FUNCTION_DECL
5329 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5330 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5331 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5332 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5334 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5335 p->next = extern_head;
5341 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5342 if (TREE_CODE (decl) == FUNCTION_DECL
5343 /* ??? Don't include alloca, since gcc will always expand it
5344 inline. If we don't do this, the C++ library fails to build. */
5345 && strcmp (name, "alloca")
5346 /* ??? Don't include __builtin_next_arg, because then gcc will not
5347 bootstrap under Irix 5.1. */
5348 && strcmp (name, "__builtin_next_arg"))
5350 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5351 p->next = extern_head;
5361 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5363 mips_output_external_libcall (file, name)
5367 register struct extern_list *p;
5369 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5370 p->next = extern_head;
5379 /* Compute a string to use as a temporary file name. */
5381 /* On MSDOS, write temp files in current dir
5382 because there's no place else we can expect to use. */
5385 #define P_tmpdir "./"
5393 const char *base = getenv ("TMPDIR");
5399 if (access (P_tmpdir, R_OK | W_OK) == 0)
5403 if (access ("/usr/tmp", R_OK | W_OK) == 0)
5409 len = strlen (base);
5410 /* temp_filename is global, so we must use malloc, not alloca. */
5411 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
5412 strcpy (temp_filename, base);
5413 if (len > 0 && temp_filename[len-1] != '/')
5414 temp_filename[len++] = '/';
5416 strcpy (temp_filename + len, "ctXXXXXX");
5417 mktemp (temp_filename);
5419 stream = fopen (temp_filename, "w+");
5421 pfatal_with_name (temp_filename);
5424 /* In MSDOS, we cannot unlink the temporary file until we are finished using
5425 it. Otherwise, we delete it now, so that it will be gone even if the
5426 compiler happens to crash. */
5427 unlink (temp_filename);
5432 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5433 for .file's that start within a function. If we are smuggling stabs, try to
5434 put out a MIPS ECOFF file and a stab. */
5437 mips_output_filename (stream, name)
5441 static int first_time = 1;
5442 char ltext_label_name[100];
5448 current_function_file = name;
5449 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5450 /* This tells mips-tfile that stabs will follow. */
5451 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5452 fprintf (stream, "\t#@stabs\n");
5455 else if (write_symbols == DBX_DEBUG)
5457 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5458 fprintf (stream, "%s ", ASM_STABS_OP);
5459 output_quoted_string (stream, name);
5460 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5463 else if (name != current_function_file
5464 && strcmp (name, current_function_file) != 0)
5466 if (inside_function && !TARGET_GAS)
5468 if (!file_in_function_warning)
5470 file_in_function_warning = 1;
5471 ignore_line_number = 1;
5472 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5478 current_function_file = name;
5479 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5484 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5485 as well as a .loc, since it is possible that MIPS ECOFF might not be
5486 able to represent the location for inlines that come from a different
5490 mips_output_lineno (stream, line)
5494 if (write_symbols == DBX_DEBUG)
5497 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
5498 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5499 LOCAL_LABEL_PREFIX, sym_lineno);
5504 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5505 (ignore_line_number) ? "#" : "",
5506 num_source_filenames, line);
5508 LABEL_AFTER_LOC (stream);
5512 /* If defined, a C statement to be executed just prior to the output of
5513 assembler code for INSN, to modify the extracted operands so they will be
5516 Here the argument OPVEC is the vector containing the operands extracted
5517 from INSN, and NOPERANDS is the number of elements of the vector which
5518 contain meaningful data for this insn. The contents of this vector are
5519 what will be used to convert the insn template into assembler code, so you
5520 can change the assembler output by changing the contents of the vector.
5522 We use it to check if the current insn needs a nop in front of it because
5523 of load delays, and also to update the delay slot statistics. */
5525 /* ??? There is no real need for this function, because it never actually
5526 emits a NOP anymore. */
5529 final_prescan_insn (insn, opvec, noperands)
5531 rtx opvec[] ATTRIBUTE_UNUSED;
5532 int noperands ATTRIBUTE_UNUSED;
5534 if (dslots_number_nops > 0)
5536 rtx pattern = PATTERN (insn);
5537 int length = get_attr_length (insn);
5539 /* Do we need to emit a NOP? */
5541 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5542 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5543 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5544 || (mips_load_reg4 != 0
5545 && reg_mentioned_p (mips_load_reg4, pattern)))
5546 fputs ("\t#nop\n", asm_out_file);
5549 dslots_load_filled++;
5551 while (--dslots_number_nops > 0)
5552 fputs ("\t#nop\n", asm_out_file);
5561 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
5562 dslots_jump_total++;
5565 /* Output at beginning of assembler file.
5567 If we are optimizing to use the global pointer, create a temporary file to
5568 hold all of the text stuff, and write it out to the end. This is needed
5569 because the MIPS assembler is evidently one pass, and if it hasn't seen the
5570 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
5571 processed, it generates a two instruction sequence. */
5574 mips_asm_file_start (stream)
5577 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
5579 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5580 inside of a .set noreorder section jumps to a label outside of the .set
5581 noreorder section. Revision 2.20 just set nobopt silently rather than
5584 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5585 fprintf (stream, "\t.set\tnobopt\n");
5587 /* Generate the pseudo ops that System V.4 wants. */
5588 #ifndef ABICALLS_ASM_OP
5589 #define ABICALLS_ASM_OP ".abicalls"
5591 if (TARGET_ABICALLS)
5592 /* ??? but do not want this (or want pic0) if -non-shared? */
5593 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
5596 fprintf (stream, "\t.set\tmips16\n");
5598 /* Start a section, so that the first .popsection directive is guaranteed
5599 to have a previously defined section to pop back to. */
5600 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
5601 fprintf (stream, "\t.section\t.text\n");
5603 /* This code exists so that we can put all externs before all symbol
5604 references. This is necessary for the MIPS assembler's global pointer
5605 optimizations to work. */
5606 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5608 asm_out_data_file = stream;
5609 asm_out_text_file = make_temp_file ();
5613 asm_out_data_file = asm_out_text_file = stream;
5615 if (flag_verbose_asm)
5616 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
5618 mips_section_threshold, mips_cpu_string, mips_isa);
5621 /* If we are optimizing the global pointer, emit the text section now and any
5622 small externs which did not have .comm, etc that are needed. Also, give a
5623 warning if the data area is more than 32K and -pic because 3 instructions
5624 are needed to reference the data pointers. */
5627 mips_asm_file_end (file)
5632 struct extern_list *p;
5637 HALF_PIC_FINISH (file);
5644 for (p = extern_head; p != 0; p = p->next)
5646 name_tree = get_identifier (p->name);
5648 /* Positively ensure only one .extern for any given symbol. */
5649 if (! TREE_ASM_WRITTEN (name_tree))
5651 TREE_ASM_WRITTEN (name_tree) = 1;
5652 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5654 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
5658 fputs ("\t.extern\t", file);
5659 assemble_name (file, p->name);
5660 fprintf (file, ", %d\n", p->size);
5666 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5668 fprintf (file, "\n\t.text\n");
5669 rewind (asm_out_text_file);
5670 if (ferror (asm_out_text_file))
5671 fatal_io_error (temp_filename);
5673 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
5674 if ((int) fwrite (buffer, 1, len, file) != len)
5675 pfatal_with_name (asm_file_name);
5678 pfatal_with_name (temp_filename);
5680 if (fclose (asm_out_text_file) != 0)
5681 pfatal_with_name (temp_filename);
5684 unlink (temp_filename);
5689 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
5690 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
5693 mips_declare_object (stream, name, init_string, final_string, size)
5700 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
5701 assemble_name (stream, name);
5702 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
5706 tree name_tree = get_identifier (name);
5707 TREE_ASM_WRITTEN (name_tree) = 1;
5711 /* Output a double precision value to the assembler. If both the
5712 host and target are IEEE, emit the values in hex. */
5715 mips_output_double (stream, value)
5717 REAL_VALUE_TYPE value;
5719 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
5721 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
5723 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
5724 value_long[0], value, value_long[1]);
5726 fprintf (stream, "\t.double\t%.20g\n", value);
5730 /* Output a single precision value to the assembler. If both the
5731 host and target are IEEE, emit the values in hex. */
5734 mips_output_float (stream, value)
5736 REAL_VALUE_TYPE value;
5738 #ifdef REAL_VALUE_TO_TARGET_SINGLE
5740 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
5742 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
5744 fprintf (stream, "\t.float\t%.12g\n", value);
5748 /* Return the bytes needed to compute the frame pointer from the current
5751 Mips stack frames look like:
5753 Before call After call
5754 +-----------------------+ +-----------------------+
5757 | caller's temps. | | caller's temps. |
5759 +-----------------------+ +-----------------------+
5761 | arguments on stack. | | arguments on stack. |
5763 +-----------------------+ +-----------------------+
5764 | 4 words to save | | 4 words to save |
5765 | arguments passed | | arguments passed |
5766 | in registers, even | | in registers, even |
5767 SP->| if not passed. | VFP->| if not passed. |
5768 +-----------------------+ +-----------------------+
5770 | fp register save |
5772 +-----------------------+
5774 | gp register save |
5776 +-----------------------+
5780 +-----------------------+
5782 | alloca allocations |
5784 +-----------------------+
5786 | GP save for V.4 abi |
5788 +-----------------------+
5790 | arguments on stack |
5792 +-----------------------+
5794 | arguments passed |
5795 | in registers, even |
5796 low SP->| if not passed. |
5797 memory +-----------------------+
5802 compute_frame_size (size)
5803 HOST_WIDE_INT size; /* # of var. bytes allocated */
5806 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
5807 HOST_WIDE_INT var_size; /* # bytes that variables take up */
5808 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
5809 HOST_WIDE_INT extra_size; /* # extra bytes */
5810 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
5811 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
5812 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
5813 long mask; /* mask of saved gp registers */
5814 long fmask; /* mask of saved fp registers */
5815 int fp_inc; /* 1 or 2 depending on the size of fp regs */
5816 long fp_bits; /* bitmask to use for each fp register */
5822 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
5823 var_size = MIPS_STACK_ALIGN (size);
5824 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
5826 /* The MIPS 3.0 linker does not like functions that dynamically
5827 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5828 looks like we are trying to create a second frame pointer to the
5829 function, so allocate some stack space to make it happy. */
5831 if (args_size == 0 && current_function_calls_alloca)
5832 args_size = 4 * UNITS_PER_WORD;
5834 total_size = var_size + args_size + extra_size;
5836 /* Calculate space needed for gp registers. */
5837 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5839 /* $18 is a special case on the mips16. It may be used to call
5840 a function which returns a floating point value, but it is
5841 marked in call_used_regs. $31 is also a special case. When
5842 not using -mentry, it will be used to copy a return value
5843 into the floating point registers if the return value is
5845 if (MUST_SAVE_REGISTER (regno)
5847 && regno == GP_REG_FIRST + 18
5848 && regs_ever_live[regno])
5850 && regno == GP_REG_FIRST + 31
5851 && mips16_hard_float
5853 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
5854 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
5856 && (! TARGET_SINGLE_FLOAT
5857 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
5860 gp_reg_size += GET_MODE_SIZE (gpr_mode);
5861 mask |= 1L << (regno - GP_REG_FIRST);
5863 /* The entry and exit pseudo instructions can not save $17
5864 without also saving $16. */
5866 && regno == GP_REG_FIRST + 17
5867 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
5869 gp_reg_size += UNITS_PER_WORD;
5875 /* Calculate space needed for fp registers. */
5876 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
5887 /* This loop must iterate over the same space as its companion in
5888 save_restore_regs. */
5889 for (regno = (FP_REG_LAST - fp_inc + 1);
5890 regno >= FP_REG_FIRST;
5893 if (regs_ever_live[regno] && !call_used_regs[regno])
5895 fp_reg_size += fp_inc * UNITS_PER_FPREG;
5896 fmask |= fp_bits << (regno - FP_REG_FIRST);
5900 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5901 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
5903 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
5904 for leaf routines (total_size == extra_size) to save the gp reg.
5905 The gp reg is callee saved in the 64 bit ABI, so all routines must
5906 save the gp reg. This is not a leaf routine if -p, because of the
5908 if (total_size == extra_size
5909 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
5911 total_size = extra_size = 0;
5912 else if (TARGET_ABICALLS)
5914 /* Add the context-pointer to the saved registers. */
5915 gp_reg_size += UNITS_PER_WORD;
5916 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
5917 total_size -= gp_reg_rounded;
5918 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5919 total_size += gp_reg_rounded;
5922 /* Add in space reserved on the stack by the callee for storing arguments
5923 passed in registers. */
5924 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
5925 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
5927 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
5928 if (mips_entry && total_size > 0 && total_size < 32)
5931 /* Save other computed information. */
5932 current_frame_info.total_size = total_size;
5933 current_frame_info.var_size = var_size;
5934 current_frame_info.args_size = args_size;
5935 current_frame_info.extra_size = extra_size;
5936 current_frame_info.gp_reg_size = gp_reg_size;
5937 current_frame_info.fp_reg_size = fp_reg_size;
5938 current_frame_info.mask = mask;
5939 current_frame_info.fmask = fmask;
5940 current_frame_info.initialized = reload_completed;
5941 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
5942 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
5946 unsigned long offset;
5948 /* When using mips_entry, the registers are always saved at the
5949 top of the stack. */
5951 offset = (args_size + extra_size + var_size
5952 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
5954 offset = total_size - GET_MODE_SIZE (gpr_mode);
5956 current_frame_info.gp_sp_offset = offset;
5957 current_frame_info.gp_save_offset = offset - total_size;
5961 current_frame_info.gp_sp_offset = 0;
5962 current_frame_info.gp_save_offset = 0;
5967 unsigned long offset = (args_size + extra_size + var_size
5968 + gp_reg_rounded + fp_reg_size
5969 - fp_inc * UNITS_PER_FPREG);
5970 current_frame_info.fp_sp_offset = offset;
5971 current_frame_info.fp_save_offset = offset - total_size;
5975 current_frame_info.fp_sp_offset = 0;
5976 current_frame_info.fp_save_offset = 0;
5979 /* Ok, we're done. */
5983 /* Common code to emit the insns (or to write the instructions to a file)
5984 to save/restore registers.
5986 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
5987 is not modified within save_restore_insns. */
5989 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
5992 save_restore_insns (store_p, large_reg, large_offset, file)
5993 int store_p; /* true if this is prologue */
5994 rtx large_reg; /* register holding large offset constant or NULL */
5995 long large_offset; /* large constant offset value */
5996 FILE *file; /* file to write instructions instead of making RTL */
5998 long mask = current_frame_info.mask;
5999 long fmask = current_frame_info.fmask;
6002 HOST_WIDE_INT base_offset;
6003 HOST_WIDE_INT gp_offset;
6004 HOST_WIDE_INT fp_offset;
6005 HOST_WIDE_INT end_offset;
6008 if (frame_pointer_needed
6009 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6012 if (mask == 0 && fmask == 0)
6015 /* Save registers starting from high to low. The debuggers prefer at least
6016 the return register be stored at func+4, and also it allows us not to
6017 need a nop in the epilog if at least one register is reloaded in
6018 addition to return address. */
6020 /* Save GP registers if needed. */
6023 /* Pick which pointer to use as a base register. For small frames, just
6024 use the stack pointer. Otherwise, use a temporary register. Save 2
6025 cycles if the save area is near the end of a large frame, by reusing
6026 the constant created in the prologue/epilogue to adjust the stack
6029 gp_offset = current_frame_info.gp_sp_offset;
6031 = gp_offset - (current_frame_info.gp_reg_size
6032 - GET_MODE_SIZE (gpr_mode));
6034 if (gp_offset < 0 || end_offset < 0)
6035 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6036 (long) gp_offset, (long) end_offset);
6038 /* If we see a large frame in mips16 mode, we save the registers
6039 before adjusting the stack pointer, and load them afterward. */
6040 else if (TARGET_MIPS16 && large_offset > 32767)
6041 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6043 else if (gp_offset < 32768)
6044 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6046 else if (large_reg != 0
6047 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6048 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6050 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6051 base_offset = large_offset;
6054 if (Pmode == DImode)
6055 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6056 stack_pointer_rtx));
6058 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6059 stack_pointer_rtx));
6061 RTX_FRAME_RELATED_P (insn) = 1;
6064 fprintf (file, "\t%s\t%s,%s,%s\n",
6065 Pmode == DImode ? "daddu" : "addu",
6066 reg_names[MIPS_TEMP2_REGNUM],
6067 reg_names[REGNO (large_reg)],
6068 reg_names[STACK_POINTER_REGNUM]);
6073 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6074 base_offset = gp_offset;
6077 rtx gp_offset_rtx = GEN_INT (gp_offset);
6079 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6080 bit, so make sure that we don't emit anything that can be
6082 /* ??? There is no DImode ori immediate pattern, so we can only
6083 do this for 32 bit code. */
6084 if (large_int (gp_offset_rtx)
6085 && GET_MODE (base_reg_rtx) == SImode)
6087 insn = emit_move_insn (base_reg_rtx,
6088 GEN_INT (gp_offset & 0xffff0000));
6090 RTX_FRAME_RELATED_P (insn) = 1;
6092 = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6093 GEN_INT (gp_offset & 0x0000ffff)));
6095 RTX_FRAME_RELATED_P (insn) = 1;
6099 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
6101 RTX_FRAME_RELATED_P (insn) = 1;
6104 if (Pmode == DImode)
6105 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6106 stack_pointer_rtx));
6108 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6109 stack_pointer_rtx));
6111 RTX_FRAME_RELATED_P (insn) = 1;
6115 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6116 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6117 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6118 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6119 Pmode == DImode ? "daddu" : "addu",
6120 reg_names[MIPS_TEMP2_REGNUM],
6121 reg_names[MIPS_TEMP2_REGNUM],
6122 reg_names[STACK_POINTER_REGNUM]);
6126 /* When we restore the registers in MIPS16 mode, then if we are
6127 using a frame pointer, and this is not a large frame, the
6128 current stack pointer will be offset by
6129 current_function_outgoing_args_size. Doing it this way lets
6130 us avoid offsetting the frame pointer before copying it into
6131 the stack pointer; there is no instruction to set the stack
6132 pointer to the sum of a register and a constant. */
6135 && frame_pointer_needed
6136 && large_offset <= 32767)
6137 base_offset += current_function_outgoing_args_size;
6139 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6140 if (BITSET_P (mask, regno - GP_REG_FIRST))
6146 = gen_rtx (MEM, gpr_mode,
6147 gen_rtx (PLUS, Pmode, base_reg_rtx,
6148 GEN_INT (gp_offset - base_offset)));
6150 RTX_UNCHANGING_P (mem_rtx) = 1;
6152 /* The mips16 does not have an instruction to load
6153 $31, so we load $7 instead, and work things out
6155 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6156 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6157 /* The mips16 sometimes needs to save $18. */
6158 else if (TARGET_MIPS16
6159 && regno != GP_REG_FIRST + 31
6160 && ! M16_REG_P (regno))
6163 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6166 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6167 emit_move_insn (reg_rtx,
6168 gen_rtx (REG, gpr_mode, regno));
6172 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6176 insn = emit_move_insn (mem_rtx, reg_rtx);
6177 RTX_FRAME_RELATED_P (insn) = 1;
6179 else if (!TARGET_ABICALLS
6180 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6181 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6183 emit_move_insn (reg_rtx, mem_rtx);
6185 && regno != GP_REG_FIRST + 31
6186 && ! M16_REG_P (regno))
6187 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6193 if (store_p || !TARGET_ABICALLS
6194 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6195 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6199 /* The mips16 does not have an instruction to
6200 load $31, so we load $7 instead, and work
6201 things out in the caller. */
6202 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6203 r = GP_REG_FIRST + 7;
6204 /* The mips16 sometimes needs to save $18. */
6206 && regno != GP_REG_FIRST + 31
6207 && ! M16_REG_P (regno))
6210 r = GP_REG_FIRST + 6;
6213 r = GP_REG_FIRST + 3;
6214 fprintf (file, "\tmove\t%s,%s\n",
6215 reg_names[r], reg_names[regno]);
6218 fprintf (file, "\t%s\t%s,",
6220 ? (store_p) ? "sd" : "ld"
6221 : (store_p) ? "sw" : "lw"),
6223 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6224 gp_offset - base_offset);
6225 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6228 && regno != GP_REG_FIRST + 31
6229 && ! M16_REG_P (regno))
6230 fprintf (file, "\tmove\t%s,%s\n",
6231 reg_names[regno], reg_names[r]);
6235 gp_offset -= GET_MODE_SIZE (gpr_mode);
6239 base_reg_rtx = 0, base_offset = 0;
6241 /* Save floating point registers if needed. */
6244 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
6245 int fp_size = fp_inc * UNITS_PER_FPREG;
6247 /* Pick which pointer to use as a base register. */
6248 fp_offset = current_frame_info.fp_sp_offset;
6249 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
6251 if (fp_offset < 0 || end_offset < 0)
6252 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6253 (long) fp_offset, (long) end_offset);
6255 else if (fp_offset < 32768)
6256 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6258 else if (base_reg_rtx != 0
6259 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6260 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6261 ; /* already set up for gp registers above */
6263 else if (large_reg != 0
6264 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6265 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6267 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6268 base_offset = large_offset;
6271 if (Pmode == DImode)
6272 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6273 stack_pointer_rtx));
6275 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6276 stack_pointer_rtx));
6278 RTX_FRAME_RELATED_P (insn) = 1;
6282 fprintf (file, "\t%s\t%s,%s,%s\n",
6283 Pmode == DImode ? "daddu" : "addu",
6284 reg_names[MIPS_TEMP2_REGNUM],
6285 reg_names[REGNO (large_reg)],
6286 reg_names[STACK_POINTER_REGNUM]);
6291 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6292 base_offset = fp_offset;
6295 rtx fp_offset_rtx = GEN_INT (fp_offset);
6297 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6298 bit, so make sure that we don't emit anything that can be
6300 /* ??? There is no DImode ori immediate pattern, so we can only
6301 do this for 32 bit code. */
6302 if (large_int (fp_offset_rtx)
6303 && GET_MODE (base_reg_rtx) == SImode)
6305 insn = emit_move_insn (base_reg_rtx,
6306 GEN_INT (fp_offset & 0xffff0000));
6308 RTX_FRAME_RELATED_P (insn) = 1;
6309 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6310 GEN_INT (fp_offset & 0x0000ffff)));
6312 RTX_FRAME_RELATED_P (insn) = 1;
6316 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
6318 RTX_FRAME_RELATED_P (insn) = 1;
6322 RTX_FRAME_RELATED_P (insn) = 1;
6323 if (Pmode == DImode)
6324 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6325 stack_pointer_rtx));
6327 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6328 stack_pointer_rtx));
6330 RTX_FRAME_RELATED_P (insn) = 1;
6334 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6335 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6336 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6337 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6338 Pmode == DImode ? "daddu" : "addu",
6339 reg_names[MIPS_TEMP2_REGNUM],
6340 reg_names[MIPS_TEMP2_REGNUM],
6341 reg_names[STACK_POINTER_REGNUM]);
6345 /* This loop must iterate over the same space as its companion in
6346 compute_frame_size. */
6347 for (regno = (FP_REG_LAST - fp_inc + 1);
6348 regno >= FP_REG_FIRST;
6350 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6354 enum machine_mode sz
6355 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6356 rtx reg_rtx = gen_rtx (REG, sz, regno);
6357 rtx mem_rtx = gen_rtx (MEM, sz,
6358 gen_rtx (PLUS, Pmode, base_reg_rtx,
6361 RTX_UNCHANGING_P (mem_rtx) = 1;
6365 insn = emit_move_insn (mem_rtx, reg_rtx);
6366 RTX_FRAME_RELATED_P (insn) = 1;
6369 emit_move_insn (reg_rtx, mem_rtx);
6373 fprintf (file, "\t%s\t%s,",
6374 (TARGET_SINGLE_FLOAT
6375 ? (store_p ? "s.s" : "l.s")
6376 : (store_p ? "s.d" : "l.d")),
6378 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6379 fp_offset - base_offset);
6380 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6383 fp_offset -= fp_size;
6388 /* Set up the stack and frame (if desired) for the function. */
6391 function_prologue (file, size)
6393 int size ATTRIBUTE_UNUSED;
6395 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6398 long tsize = current_frame_info.total_size;
6400 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6402 #ifdef SDB_DEBUGGING_INFO
6403 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6404 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6407 /* In mips16 mode, we may need to generate a 32 bit to handle
6408 floating point arguments. The linker will arrange for any 32 bit
6409 functions to call this stub, which will then jump to the 16 bit
6411 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6412 && current_function_args_info.fp_code != 0)
6413 build_mips16_function_stub (file);
6415 inside_function = 1;
6417 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6418 /* Get the function name the same way that toplev.c does before calling
6419 assemble_start_function. This is needed so that the name used here
6420 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6421 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6423 if (!flag_inhibit_size_directive)
6425 fputs ("\t.ent\t", file);
6426 assemble_name (file, fnname);
6430 assemble_name (file, fnname);
6431 fputs (":\n", file);
6434 if (!flag_inhibit_size_directive)
6436 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6438 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6439 (reg_names[(frame_pointer_needed)
6440 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6441 ((frame_pointer_needed && TARGET_MIPS16)
6442 ? (tsize - current_function_outgoing_args_size)
6444 reg_names[31 + GP_REG_FIRST],
6445 current_frame_info.var_size,
6446 current_frame_info.num_gp,
6447 current_frame_info.num_fp,
6448 current_function_outgoing_args_size,
6449 current_frame_info.extra_size);
6451 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6452 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6453 current_frame_info.mask,
6454 current_frame_info.gp_save_offset,
6455 current_frame_info.fmask,
6456 current_frame_info.fp_save_offset);
6459 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6460 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6463 if (mips_entry && ! mips_can_use_return_insn ())
6465 int save16 = BITSET_P (current_frame_info.mask, 16);
6466 int save17 = BITSET_P (current_frame_info.mask, 17);
6467 int save31 = BITSET_P (current_frame_info.mask, 31);
6471 /* Look through the initial insns to see if any of them store
6472 the function parameters into the incoming parameter storage
6473 area. If they do, we delete the insn, and save the register
6474 using the entry pseudo-instruction instead. We don't try to
6475 look past a label, jump, or call. */
6476 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6478 rtx note, set, src, dest, base, offset;
6481 if (GET_CODE (insn) == CODE_LABEL
6482 || GET_CODE (insn) == JUMP_INSN
6483 || GET_CODE (insn) == CALL_INSN)
6485 if (GET_CODE (insn) != INSN)
6487 set = PATTERN (insn);
6488 if (GET_CODE (set) != SET)
6491 /* An insn storing a function parameter will still have a
6492 REG_EQUIV note on it mentioning the argument pointer. */
6493 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6494 if (note == NULL_RTX)
6496 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6499 src = SET_SRC (set);
6500 if (GET_CODE (src) != REG
6501 || REGNO (src) < GP_REG_FIRST + 4
6502 || REGNO (src) > GP_REG_FIRST + 7)
6505 dest = SET_DEST (set);
6506 if (GET_CODE (dest) != MEM)
6508 if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD)
6510 else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
6511 && REGNO (src) < GP_REG_FIRST + 7)
6515 offset = const0_rtx;
6516 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6517 if (GET_CODE (base) != REG
6518 || GET_CODE (offset) != CONST_INT)
6520 if (REGNO (base) == STACK_POINTER_REGNUM
6521 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6523 else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM
6526 + (REGNO (src) - 4) * UNITS_PER_WORD
6527 - current_function_outgoing_args_size)))
6532 /* This insn stores a parameter onto the stack, in the same
6533 location where the entry pseudo-instruction will put it.
6534 Delete the insn, and arrange to tell the entry
6535 instruction to save the register. */
6536 PUT_CODE (insn, NOTE);
6537 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6538 NOTE_SOURCE_FILE (insn) = 0;
6540 hireg = (REGNO (src)
6541 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6543 if (hireg > savearg)
6547 /* If this is a varargs function, we need to save all the
6548 registers onto the stack anyhow. */
6549 if (current_function_stdarg || current_function_varargs)
6550 savearg = GP_REG_FIRST + 7;
6552 fprintf (file, "\tentry\t");
6555 if (savearg == GP_REG_FIRST + 4)
6556 fprintf (file, "%s", reg_names[savearg]);
6558 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6559 reg_names[savearg]);
6561 if (save16 || save17)
6564 fprintf (file, ",");
6565 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6567 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6571 if (savearg > 0 || save16 || save17)
6572 fprintf (file, ",");
6573 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6575 fprintf (file, "\n");
6578 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
6580 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6582 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6583 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
6586 fprintf (file, "\t%s\t%s,%s,%ld\n",
6587 (Pmode == DImode ? "dsubu" : "subu"),
6588 sp_str, sp_str, tsize);
6589 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
6592 if (dwarf2out_do_frame ())
6593 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
6597 /* Expand the prologue into a bunch of separate insns. */
6600 mips_expand_prologue ()
6603 HOST_WIDE_INT tsize;
6606 tree fndecl = current_function_decl;
6607 tree fntype = TREE_TYPE (fndecl);
6608 tree fnargs = DECL_ARGUMENTS (fndecl);
6613 CUMULATIVE_ARGS args_so_far;
6614 rtx reg_18_save = NULL_RTX;
6616 /* If struct value address is treated as the first argument, make it so. */
6617 if (aggregate_value_p (DECL_RESULT (fndecl))
6618 && ! current_function_returns_pcc_struct
6619 && struct_value_incoming_rtx == 0)
6621 tree type = build_pointer_type (fntype);
6622 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
6624 DECL_ARG_TYPE (function_result_decl) = type;
6625 TREE_CHAIN (function_result_decl) = fnargs;
6626 fnargs = function_result_decl;
6629 /* Determine the last argument, and get its name. */
6631 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
6632 regno = GP_ARG_FIRST;
6634 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
6636 tree passed_type = DECL_ARG_TYPE (cur_arg);
6637 enum machine_mode passed_mode = TYPE_MODE (passed_type);
6640 if (TREE_ADDRESSABLE (passed_type))
6642 passed_type = build_pointer_type (passed_type);
6643 passed_mode = Pmode;
6646 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
6652 /* passed in a register, so will get homed automatically */
6653 if (GET_MODE (entry_parm) == BLKmode)
6654 words = (int_size_in_bytes (passed_type) + 3) / 4;
6656 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
6658 regno = REGNO (entry_parm) + words - 1;
6662 regno = GP_ARG_LAST+1;
6666 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
6668 next_arg = TREE_CHAIN (cur_arg);
6671 if (DECL_NAME (cur_arg))
6672 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
6678 /* In order to pass small structures by value in registers compatibly with
6679 the MIPS compiler, we need to shift the value into the high part of the
6680 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
6681 adjustments to be made as the next_arg_reg variable, so we split up the
6682 insns, and emit them separately. */
6684 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
6685 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
6687 rtvec adjust = XVEC (next_arg_reg, 0);
6688 int num = GET_NUM_ELEM (adjust);
6690 for (i = 0; i < num; i++)
6692 rtx pattern = RTVEC_ELT (adjust, i);
6693 if (GET_CODE (pattern) != SET
6694 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
6695 abort_with_insn (pattern, "Insn is not a shift");
6697 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
6698 emit_insn (pattern);
6702 tsize = compute_frame_size (get_frame_size ());
6704 /* If this function is a varargs function, store any registers that
6705 would normally hold arguments ($4 - $7) on the stack. */
6706 if ((mips_abi == ABI_32 || mips_abi == ABI_O64)
6707 && (! mips_entry || mips_can_use_return_insn ())
6708 && ((TYPE_ARG_TYPES (fntype) != 0
6709 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6712 && ((arg_name[0] == '_'
6713 && strcmp (arg_name, "__builtin_va_alist") == 0)
6714 || (arg_name[0] == 'v'
6715 && strcmp (arg_name, "va_alist") == 0)))))
6717 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
6718 rtx ptr = stack_pointer_rtx;
6720 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
6721 if (TARGET_ABICALLS)
6724 for (; regno <= GP_ARG_LAST; regno++)
6727 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
6728 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
6729 gen_rtx (REG, gpr_mode, regno));
6731 offset += GET_MODE_SIZE (gpr_mode);
6735 /* If we are using the entry pseudo instruction, it will
6736 automatically subtract 32 from the stack pointer, so we don't
6737 need to. The entry pseudo instruction is emitted by
6738 function_prologue. */
6739 if (mips_entry && ! mips_can_use_return_insn ())
6741 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
6745 /* If we are using a frame pointer with a small stack frame,
6746 we need to initialize it here since it won't be done
6748 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6750 rtx incr = GEN_INT (current_function_outgoing_args_size);
6751 if (Pmode == DImode)
6752 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6756 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6760 else if (Pmode == DImode)
6761 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6762 stack_pointer_rtx));
6764 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6765 stack_pointer_rtx));
6767 RTX_FRAME_RELATED_P (insn) = 1;
6770 /* We may need to save $18, if it is used to call a function
6771 which may return a floating point value. Set up a sequence
6772 of instructions to do so. Later on we emit them at the right
6774 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
6776 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
6777 long gp_offset, base_offset;
6779 gp_offset = current_frame_info.gp_sp_offset;
6780 if (BITSET_P (current_frame_info.mask, 16))
6781 gp_offset -= UNITS_PER_WORD;
6782 if (BITSET_P (current_frame_info.mask, 17))
6783 gp_offset -= UNITS_PER_WORD;
6784 if (BITSET_P (current_frame_info.mask, 31))
6785 gp_offset -= UNITS_PER_WORD;
6787 base_offset = tsize;
6791 emit_move_insn (reg_rtx,
6792 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
6793 emit_move_insn (gen_rtx (MEM, gpr_mode,
6794 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
6798 reg_18_save = gen_sequence ();
6807 if (reg_18_save != NULL_RTX)
6808 emit_insn (reg_18_save);
6814 rtx tsize_rtx = GEN_INT (tsize);
6816 /* If we are doing svr4-abi, sp move is done by
6817 function_prologue. In mips16 mode with a large frame, we
6818 save the registers before adjusting the stack. */
6819 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
6820 && (!TARGET_MIPS16 || tsize <= 32767))
6826 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
6828 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6829 bit, so make sure that we don't emit anything that can be
6831 /* ??? There is no DImode ori immediate pattern, so we can only
6832 do this for 32 bit code. */
6833 if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode)
6835 insn = emit_move_insn (tmp_rtx,
6836 GEN_INT (tsize & 0xffff0000));
6837 RTX_FRAME_RELATED_P (insn) = 1;
6838 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
6839 GEN_INT (tsize & 0x0000ffff)));
6840 RTX_FRAME_RELATED_P (insn) = 1;
6844 insn = emit_move_insn (tmp_rtx, tsize_rtx);
6845 RTX_FRAME_RELATED_P (insn) = 1;
6848 tsize_rtx = tmp_rtx;
6851 if (Pmode == DImode)
6852 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
6855 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
6858 RTX_FRAME_RELATED_P (insn) = 1;
6862 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
6863 else if (reg_18_save != NULL_RTX)
6864 emit_insn (reg_18_save);
6866 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
6872 if (!frame_pointer_needed)
6875 reg_rtx = gen_rtx (REG, Pmode, 3);
6876 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6877 emit_move_insn (reg_rtx, tsize_rtx);
6878 if (Pmode == DImode)
6879 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
6880 hard_frame_pointer_rtx,
6883 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
6884 hard_frame_pointer_rtx,
6886 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6889 if (frame_pointer_needed)
6893 /* On the mips16, we encourage the use of unextended
6894 instructions when using the frame pointer by pointing the
6895 frame pointer ahead of the argument space allocated on
6897 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
6901 /* In this case, we have already copied the stack
6902 pointer into the frame pointer, above. We need only
6903 adjust for the outgoing argument size. */
6904 if (current_function_outgoing_args_size != 0)
6906 rtx incr = GEN_INT (current_function_outgoing_args_size);
6907 if (Pmode == DImode)
6908 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6909 hard_frame_pointer_rtx,
6912 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6913 hard_frame_pointer_rtx,
6917 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6919 rtx incr = GEN_INT (current_function_outgoing_args_size);
6920 if (Pmode == DImode)
6921 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6925 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6929 else if (Pmode == DImode)
6930 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6931 stack_pointer_rtx));
6933 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6934 stack_pointer_rtx));
6937 RTX_FRAME_RELATED_P (insn) = 1;
6940 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
6941 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
6942 gen_rtx_REG (DImode, 25)));
6945 /* If we are profiling, make sure no instructions are scheduled before
6946 the call to mcount. */
6948 if (profile_flag || profile_block_flag)
6949 emit_insn (gen_blockage ());
6952 /* Do any necessary cleanup after a function to restore stack, frame,
6955 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
6956 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6959 function_epilogue (file, size)
6960 FILE *file ATTRIBUTE_UNUSED;
6961 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6965 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6966 /* Get the function name the same way that toplev.c does before calling
6967 assemble_start_function. This is needed so that the name used here
6968 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6969 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6971 if (!flag_inhibit_size_directive)
6973 fputs ("\t.end\t", file);
6974 assemble_name (file, fnname);
6981 int num_gp_regs = current_frame_info.gp_reg_size / 4;
6982 int num_fp_regs = current_frame_info.fp_reg_size / 8;
6983 int num_regs = num_gp_regs + num_fp_regs;
6984 char *name = fnname;
6989 dslots_load_total += num_regs;
6992 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
6993 name, frame_pointer_needed ? 'y' : 'n',
6994 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
6995 current_function_calls_alloca ? 'y' : 'n',
6996 current_function_calls_setjmp ? 'y' : 'n',
6997 current_frame_info.total_size,
6998 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
6999 dslots_load_total, dslots_load_filled,
7000 dslots_jump_total, dslots_jump_filled,
7001 num_refs[0], num_refs[1], num_refs[2]);
7003 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7006 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7007 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7010 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7013 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7014 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7017 fputc ('\n', stderr);
7020 /* Reset state info for each function. */
7021 inside_function = 0;
7022 ignore_line_number = 0;
7023 dslots_load_total = 0;
7024 dslots_jump_total = 0;
7025 dslots_load_filled = 0;
7026 dslots_jump_filled = 0;
7032 current_frame_info = zero_frame_info;
7034 while (string_constants != NULL)
7036 struct string_constant *next;
7038 next = string_constants->next;
7039 free (string_constants);
7040 string_constants = next;
7043 /* Restore the output file if optimizing the GP (optimizing the GP causes
7044 the text to be diverted to a tempfile, so that data decls come before
7045 references to the data). */
7047 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
7048 asm_out_file = asm_out_data_file;
7051 /* Expand the epilogue into a bunch of separate insns. */
7054 mips_expand_epilogue ()
7056 HOST_WIDE_INT tsize = current_frame_info.total_size;
7057 rtx tsize_rtx = GEN_INT (tsize);
7058 rtx tmp_rtx = (rtx)0;
7060 if (mips_can_use_return_insn ())
7062 emit_insn (gen_return ());
7066 if (mips_entry && ! mips_can_use_return_insn ())
7069 if (tsize > 32767 && ! TARGET_MIPS16)
7071 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7072 emit_move_insn (tmp_rtx, tsize_rtx);
7073 tsize_rtx = tmp_rtx;
7078 long orig_tsize = tsize;
7080 if (frame_pointer_needed)
7082 emit_insn (gen_blockage ());
7084 /* On the mips16, the frame pointer is offset from the stack
7085 pointer by current_function_outgoing_args_size. We
7086 account for that by changing tsize. Note that this can
7087 actually make tsize negative. */
7090 tsize -= current_function_outgoing_args_size;
7092 /* If we have a large frame, it's easier to add to $17
7093 than to $sp, since the mips16 has no instruction to
7094 add a register to $sp. */
7095 if (orig_tsize > 32767)
7097 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7099 emit_move_insn (g6_rtx, GEN_INT (tsize));
7100 if (Pmode == DImode)
7101 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7102 hard_frame_pointer_rtx,
7105 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7106 hard_frame_pointer_rtx,
7111 if (tsize && tsize != orig_tsize)
7112 tsize_rtx = GEN_INT (tsize);
7115 if (Pmode == DImode)
7116 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7118 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7121 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7122 are going to restore it, then we must emit a blockage insn to
7123 prevent the scheduler from moving the restore out of the epilogue. */
7124 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7125 && (current_frame_info.mask
7126 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7127 emit_insn (gen_blockage ());
7129 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
7131 /* In mips16 mode with a large frame, we adjust the stack
7132 pointer before restoring the registers. In this case, we
7133 should always be using a frame pointer, so everything should
7134 have been handled above. */
7135 if (tsize > 32767 && TARGET_MIPS16)
7138 emit_insn (gen_blockage ());
7139 if (Pmode == DImode && tsize != 0)
7140 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7142 else if (tsize != 0)
7143 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7147 /* The mips16 loads the return address into $7, not $31. */
7148 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7149 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7150 GP_REG_FIRST + 7)));
7152 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7153 GP_REG_FIRST + 31)));
7156 /* Return nonzero if this function is known to have a null epilogue.
7157 This allows the optimizer to omit jumps to jumps if no stack
7161 mips_can_use_return_insn ()
7163 if (! reload_completed)
7166 if (regs_ever_live[31] || profile_flag)
7169 /* In mips16 mode, a function which returns a floating point value
7170 needs to arrange to copy the return value into the floating point
7173 && mips16_hard_float
7174 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7175 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7177 && (! TARGET_SINGLE_FLOAT
7178 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7182 if (current_frame_info.initialized)
7183 return current_frame_info.total_size == 0;
7185 return compute_frame_size (get_frame_size ()) == 0;
7188 /* Returns non-zero if X contains a SYMBOL_REF. */
7191 symbolic_expression_p (x)
7194 if (GET_CODE (x) == SYMBOL_REF)
7197 if (GET_CODE (x) == CONST)
7198 return symbolic_expression_p (XEXP (x, 0));
7200 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7201 return symbolic_expression_p (XEXP (x, 0));
7203 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7204 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7205 return (symbolic_expression_p (XEXP (x, 0))
7206 || symbolic_expression_p (XEXP (x, 1)));
7211 /* Choose the section to use for the constant rtx expression X that has
7215 mips_select_rtx_section (mode, x)
7216 enum machine_mode mode;
7217 rtx x ATTRIBUTE_UNUSED;
7221 /* In mips16 mode, the constant table always goes in the same section
7222 as the function, so that constants can be loaded using PC relative
7224 function_section (current_function_decl);
7226 else if (TARGET_EMBEDDED_DATA)
7228 /* For embedded applications, always put constants in read-only data,
7229 in order to reduce RAM usage. */
7230 READONLY_DATA_SECTION ();
7234 /* For hosted applications, always put constants in small data if
7235 possible, as this gives the best performance. */
7237 if (GET_MODE_SIZE (mode) <= mips_section_threshold
7238 && mips_section_threshold > 0)
7239 SMALL_DATA_SECTION ();
7240 else if (flag_pic && symbolic_expression_p (x))
7241 /* Any expression involving a SYMBOL_REF might need a run-time
7242 relocation. (The symbol might be defined in a shared
7243 library loaded at an unexpected base address.) So, we must
7244 put such expressions in the data segment (which is
7245 writable), rather than the text segment (which is
7249 READONLY_DATA_SECTION ();
7253 /* Choose the section to use for DECL. RELOC is true if its value contains
7254 any relocatable expression.
7256 Some of the logic used here needs to be replicated in
7257 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7258 are done correctly. Specifically, at least all symbols assigned
7259 here to rom (.text and/or .rodata) must not be referenced via
7260 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7262 If you need to make a change here, you probably should check
7263 ENCODE_SECTION_INFO to see if it needs a similar change. */
7266 mips_select_section (decl, reloc)
7270 int size = int_size_in_bytes (TREE_TYPE (decl));
7272 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7273 && TREE_CODE (decl) == STRING_CST
7274 && !flag_writable_strings)
7275 /* For embedded position independent code, put constant strings in the
7276 text section, because the data section is limited to 64K in size.
7277 For mips16 code, put strings in the text section so that a PC
7278 relative load instruction can be used to get their address. */
7280 else if (TARGET_EMBEDDED_DATA)
7282 /* For embedded applications, always put an object in read-only data
7283 if possible, in order to reduce RAM usage. */
7285 if (((TREE_CODE (decl) == VAR_DECL
7286 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7287 && DECL_INITIAL (decl)
7288 && (DECL_INITIAL (decl) == error_mark_node
7289 || TREE_CONSTANT (DECL_INITIAL (decl))))
7290 /* Deal with calls from output_constant_def_contents. */
7291 || (TREE_CODE (decl) != VAR_DECL
7292 && (TREE_CODE (decl) != STRING_CST
7293 || !flag_writable_strings)))
7294 && ! (flag_pic && reloc))
7295 READONLY_DATA_SECTION ();
7296 else if (size > 0 && size <= mips_section_threshold)
7297 SMALL_DATA_SECTION ();
7303 /* For hosted applications, always put an object in small data if
7304 possible, as this gives the best performance. */
7306 if (size > 0 && size <= mips_section_threshold)
7307 SMALL_DATA_SECTION ();
7308 else if (((TREE_CODE (decl) == VAR_DECL
7309 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7310 && DECL_INITIAL (decl)
7311 && (DECL_INITIAL (decl) == error_mark_node
7312 || TREE_CONSTANT (DECL_INITIAL (decl))))
7313 /* Deal with calls from output_constant_def_contents. */
7314 || (TREE_CODE (decl) != VAR_DECL
7315 && (TREE_CODE (decl) != STRING_CST
7316 || !flag_writable_strings)))
7317 && ! (flag_pic && reloc))
7318 READONLY_DATA_SECTION ();
7324 #ifdef MIPS_ABI_DEFAULT
7326 /* Support functions for the 64 bit ABI. */
7328 /* Return register to use for a function return value with VALTYPE for function
7332 mips_function_value (valtype, func)
7334 tree func ATTRIBUTE_UNUSED;
7336 int reg = GP_RETURN;
7337 enum machine_mode mode = TYPE_MODE (valtype);
7338 enum mode_class mclass = GET_MODE_CLASS (mode);
7339 int unsignedp = TREE_UNSIGNED (valtype);
7341 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7342 just as PROMOTE_MODE does. */
7343 mode = promote_mode (valtype, mode, &unsignedp, 1);
7345 /* ??? How should we return complex float? */
7346 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
7348 if (TARGET_SINGLE_FLOAT
7349 && (mclass == MODE_FLOAT
7350 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7356 else if (TREE_CODE (valtype) == RECORD_TYPE
7357 && mips_abi != ABI_32
7358 && mips_abi != ABI_O64
7359 && mips_abi != ABI_EABI)
7361 /* A struct with only one or two floating point fields is returned in
7362 the floating point registers. */
7363 tree field, fields[2];
7366 for (i = 0, field = TYPE_FIELDS (valtype); field;
7367 field = TREE_CHAIN (field))
7369 if (TREE_CODE (field) != FIELD_DECL)
7372 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7375 fields[i++] = field;
7378 /* Must check i, so that we reject structures with no elements. */
7383 /* The structure has DImode, but we don't allow DImode values
7384 in FP registers, so we use a PARALLEL even though it isn't
7385 strictly necessary. */
7386 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7388 return gen_rtx_PARALLEL
7391 gen_rtx_EXPR_LIST (VOIDmode,
7392 gen_rtx_REG (field_mode,
7399 enum machine_mode first_mode
7400 = TYPE_MODE (TREE_TYPE (fields[0]));
7401 enum machine_mode second_mode
7402 = TYPE_MODE (TREE_TYPE (fields[1]));
7404 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
7406 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
7408 return gen_rtx_PARALLEL
7411 gen_rtx_EXPR_LIST (VOIDmode,
7412 gen_rtx_REG (first_mode,
7414 GEN_INT (first_offset
7416 gen_rtx_EXPR_LIST (VOIDmode,
7417 gen_rtx_REG (second_mode,
7419 GEN_INT (second_offset
7420 / BITS_PER_UNIT))));
7425 return gen_rtx_REG (mode, reg);
7428 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7429 nonzero when an argument must be passed by reference. */
7432 function_arg_pass_by_reference (cum, mode, type, named)
7433 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
7434 enum machine_mode mode;
7436 int named ATTRIBUTE_UNUSED;
7440 /* We must pass by reference if we would be both passing in registers
7441 and the stack. This is because any subsequent partial arg would be
7442 handled incorrectly in this case.
7444 ??? This is really a kludge. We should either fix GCC so that such
7445 a situation causes an abort and then do something in the MIPS port
7446 to prevent it, or add code to function.c to properly handle the case. */
7447 if (FUNCTION_ARG (*cum, mode, type, named) != 0
7448 && MUST_PASS_IN_STACK (mode, type))
7451 /* Otherwise, we only do this if EABI is selected. */
7452 if (mips_abi != ABI_EABI)
7455 /* ??? How should SCmode be handled? */
7456 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7459 size = int_size_in_bytes (type);
7460 return size == -1 || size > UNITS_PER_WORD;
7464 /* This function returns the register class required for a secondary
7465 register when copying between one of the registers in CLASS, and X,
7466 using MODE. If IN_P is nonzero, the copy is going from X to the
7467 register, otherwise the register is the source. A return value of
7468 NO_REGS means that no secondary register is required. */
7471 mips_secondary_reload_class (class, mode, x, in_p)
7472 enum reg_class class;
7473 enum machine_mode mode;
7477 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7481 if (GET_CODE (x) == SIGN_EXTEND)
7487 /* We may be called with reg_renumber NULL from regclass.
7488 ??? This is probably a bug. */
7490 regno = true_regnum (x);
7493 while (GET_CODE (x) == SUBREG)
7495 off += SUBREG_WORD (x);
7499 if (GET_CODE (x) == REG)
7500 regno = REGNO (x) + off;
7504 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7505 regno = true_regnum (x);
7507 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7509 /* We always require a general register when copying anything to
7510 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7511 to a general register, or when copying from register 0. */
7512 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
7515 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7516 ? NO_REGS : gr_regs);
7517 else if (regno == HILO_REGNUM)
7520 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7521 ? NO_REGS : gr_regs);
7523 /* Copying from HI or LO to anywhere other than a general register
7524 requires a general register. */
7525 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7527 if (TARGET_MIPS16 && in_p)
7529 /* We can't really copy to HI or LO at all in mips16 mode. */
7532 return gp_reg_p ? NO_REGS : gr_regs;
7534 if (MD_REG_P (regno))
7536 if (TARGET_MIPS16 && ! in_p)
7538 /* We can't really copy to HI or LO at all in mips16 mode. */
7541 return class == gr_regs ? NO_REGS : gr_regs;
7544 /* We can only copy a value to a condition code register from a
7545 floating point register, and even then we require a scratch
7546 floating point register. We can only copy a value out of a
7547 condition code register into a general register. */
7548 if (class == ST_REGS)
7552 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
7554 if (ST_REG_P (regno))
7558 return class == GR_REGS ? NO_REGS : GR_REGS;
7561 /* In mips16 mode, going between memory and anything but M16_REGS
7562 requires an M16_REG. */
7565 if (class != M16_REGS && class != M16_NA_REGS)
7573 /* The stack pointer isn't a valid operand to an add instruction,
7574 so we need to load it into M16_REGS first. This can happen as
7575 a result of register elimination and form_sum converting
7576 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
7577 need an extra register if the dest is the same as the other
7578 register. In that case, we can't fix the problem by loading SP
7579 into the dest first. */
7580 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
7581 && GET_CODE (XEXP (x, 1)) == REG
7582 && (XEXP (x, 0) == stack_pointer_rtx
7583 || XEXP (x, 1) == stack_pointer_rtx))
7584 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
7586 if (class == M16_REGS || class == M16_NA_REGS)
7595 /* For each mips16 function which refers to GP relative symbols, we
7596 use a pseudo register, initialized at the start of the function, to
7597 hold the $gp value. */
7600 mips16_gp_pseudo_reg ()
7602 if (mips16_gp_pseudo_rtx == NULL_RTX)
7607 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7608 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
7610 /* We want to initialize this to a value which gcc will believe
7612 const_gp = gen_rtx (CONST, Pmode,
7613 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
7616 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
7617 insn = gen_sequence ();
7620 push_topmost_sequence ();
7621 /* We need to emit the initialization after the FUNCTION_BEG
7622 note, so that it will be integrated. */
7623 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7624 if (GET_CODE (scan) == NOTE
7625 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7627 if (scan == NULL_RTX)
7628 scan = get_insns ();
7629 insn = emit_insn_after (insn, scan);
7630 pop_topmost_sequence ();
7633 return mips16_gp_pseudo_rtx;
7636 /* Return an RTX which represents the signed 16 bit offset from the
7637 $gp register for the given symbol. This is only used on the
7641 mips16_gp_offset (sym)
7646 if (GET_CODE (sym) != SYMBOL_REF
7647 || ! SYMBOL_REF_FLAG (sym))
7650 /* We use a special identifier to represent the value of the gp
7652 gp = get_identifier ("__mips16_gp_value");
7654 return gen_rtx (CONST, Pmode,
7655 gen_rtx (MINUS, Pmode, sym,
7656 gen_rtx (SYMBOL_REF, Pmode,
7657 IDENTIFIER_POINTER (gp))));
7660 /* Return nonzero if the given RTX represents a signed 16 bit offset
7661 from the $gp register. */
7664 mips16_gp_offset_p (x)
7667 if (GET_CODE (x) == CONST)
7670 /* It's OK to add a small integer value to a gp offset. */
7671 if (GET_CODE (x) == PLUS)
7673 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7674 && SMALL_INT (XEXP (x, 1)))
7675 return mips16_gp_offset_p (XEXP (x, 0));
7676 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7677 && SMALL_INT (XEXP (x, 0)))
7678 return mips16_gp_offset_p (XEXP (x, 1));
7682 /* Make sure it is in the form SYM - __mips16_gp_value. */
7683 return (GET_CODE (x) == MINUS
7684 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
7685 && SYMBOL_REF_FLAG (XEXP (x, 0))
7686 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7687 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
7690 /* Output a GP offset. We don't want to print the subtraction of
7691 __mips16_gp_value; it is implicitly represented by the %gprel which
7692 should have been printed by the caller. */
7695 mips16_output_gp_offset (file, x)
7699 if (GET_CODE (x) == CONST)
7702 if (GET_CODE (x) == PLUS)
7704 mips16_output_gp_offset (file, XEXP (x, 0));
7706 mips16_output_gp_offset (file, XEXP (x, 1));
7710 if (GET_CODE (x) == MINUS
7711 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7712 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
7714 mips16_output_gp_offset (file, XEXP (x, 0));
7718 output_addr_const (file, x);
7721 /* Return nonzero if a constant should not be output until after the
7722 function. This is true of most string constants, so that we can
7723 use a more efficient PC relative reference. However, a static
7724 inline function may never call assemble_function_end to write out
7725 the constant pool, so don't try to postpone the constant in that
7728 ??? It's really a bug that a static inline function can put stuff
7729 in the constant pool even if the function itself is not output.
7731 We record which string constants we've seen, so that we know which
7732 ones might use the more efficient reference. */
7735 mips16_constant_after_function_p (x)
7738 if (TREE_CODE (x) == STRING_CST
7739 && ! flag_writable_strings
7740 && current_function_decl != 0
7741 && ! DECL_DEFER_OUTPUT (current_function_decl)
7742 && ! (DECL_INLINE (current_function_decl)
7743 && ((! TREE_PUBLIC (current_function_decl)
7744 && ! TREE_ADDRESSABLE (current_function_decl)
7745 && ! flag_keep_inline_functions)
7746 || DECL_EXTERNAL (current_function_decl))))
7748 struct string_constant *n;
7750 n = (struct string_constant *) xmalloc (sizeof *n);
7751 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
7752 n->next = string_constants;
7753 string_constants = n;
7761 /* Validate a constant for the mips16. This rejects general symbolic
7762 addresses, which must be loaded from memory. If ADDR is nonzero,
7763 this should reject anything which is not a legal address. If
7764 ADDEND is nonzero, this is being added to something else. */
7767 mips16_constant (x, mode, addr, addend)
7769 enum machine_mode mode;
7773 while (GET_CODE (x) == CONST)
7776 switch (GET_CODE (x))
7782 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
7783 && mips16_constant (XEXP (x, 1), mode, addr, 1));
7786 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7788 if (CONSTANT_POOL_ADDRESS_P (x))
7791 /* If we aren't looking for a memory address, we can accept a GP
7792 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
7793 knows how to handle this. We can always accept a string
7794 constant, which is the other case in which SYMBOL_REF_FLAG
7796 if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode)
7799 /* We can accept a string constant, which will have
7800 SYMBOL_REF_FLAG set but must be recognized by name to
7801 distinguish from a GP accessible symbol. The name of a
7802 string constant will have been generated by
7803 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
7804 if (SYMBOL_REF_FLAG (x))
7806 char *name = XSTR (x, 0);
7808 return (name[0] == '*'
7809 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
7810 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
7816 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7821 if (addr && ! addend)
7823 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
7826 /* We need to treat $gp as a legitimate constant, because
7827 mips16_gp_pseudo_reg assumes that. */
7828 return REGNO (x) == GP_REG_FIRST + 28;
7832 /* Write out code to move floating point arguments in or out of
7833 general registers. Output the instructions to FILE. FP_CODE is
7834 the code describing which arguments are present (see the comment at
7835 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
7836 we are copying from the floating point registers. */
7839 mips16_fp_args (file, fp_code, from_fp_p)
7848 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7849 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
7856 gparg = GP_ARG_FIRST;
7857 fparg = FP_ARG_FIRST;
7858 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7862 if ((fparg & 1) != 0)
7864 fprintf (file, "\t%s\t%s,%s\n", s,
7865 reg_names[gparg], reg_names[fparg]);
7867 else if ((f & 3) == 2)
7870 fprintf (file, "\td%s\t%s,%s\n", s,
7871 reg_names[gparg], reg_names[fparg]);
7874 if ((fparg & 1) != 0)
7876 if (TARGET_BIG_ENDIAN)
7877 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7878 reg_names[gparg], reg_names[fparg + 1], s,
7879 reg_names[gparg + 1], reg_names[fparg]);
7881 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7882 reg_names[gparg], reg_names[fparg], s,
7883 reg_names[gparg + 1], reg_names[fparg + 1]);
7896 /* Build a mips16 function stub. This is used for functions which
7897 take aruments in the floating point registers. It is 32 bit code
7898 that moves the floating point args into the general registers, and
7899 then jumps to the 16 bit code. */
7902 build_mips16_function_stub (file)
7906 char *secname, *stubname;
7907 tree stubid, stubdecl;
7911 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7912 secname = (char *) alloca (strlen (fnname) + 20);
7913 sprintf (secname, ".mips16.fn.%s", fnname);
7914 stubname = (char *) alloca (strlen (fnname) + 20);
7915 sprintf (stubname, "__fn_stub_%s", fnname);
7916 stubid = get_identifier (stubname);
7917 stubdecl = build_decl (FUNCTION_DECL, stubid,
7918 build_function_type (void_type_node, NULL_TREE));
7919 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7921 fprintf (file, "\t# Stub function for %s (", current_function_name);
7923 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7925 fprintf (file, "%s%s",
7926 need_comma ? ", " : "",
7927 (f & 3) == 1 ? "float" : "double");
7930 fprintf (file, ")\n");
7932 fprintf (file, "\t.set\tnomips16\n");
7933 function_section (stubdecl);
7934 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7936 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7937 within a .ent, and we can not emit another .ent. */
7938 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7939 fputs ("\t.ent\t", file);
7940 assemble_name (file, stubname);
7944 assemble_name (file, stubname);
7945 fputs (":\n", file);
7947 /* We don't want the assembler to insert any nops here. */
7948 fprintf (file, "\t.set\tnoreorder\n");
7950 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7952 fprintf (asm_out_file, "\t.set\tnoat\n");
7953 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7954 assemble_name (file, fnname);
7955 fprintf (file, "\n");
7956 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7957 fprintf (asm_out_file, "\t.set\tat\n");
7959 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7960 with one of the mfc1 instructions, because the result is not
7961 available for one instruction, so if the very first instruction
7962 in the function refers to the register, it will see the wrong
7964 fprintf (file, "\tnop\n");
7966 fprintf (file, "\t.set\treorder\n");
7968 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7969 fputs ("\t.end\t", file);
7970 assemble_name (file, stubname);
7974 fprintf (file, "\t.set\tmips16\n");
7976 function_section (current_function_decl);
7979 /* We keep a list of functions for which we have already built stubs
7980 in build_mips16_call_stub. */
7984 struct mips16_stub *next;
7989 static struct mips16_stub *mips16_stubs;
7991 /* Build a call stub for a mips16 call. A stub is needed if we are
7992 passing any floating point values which should go into the floating
7993 point registers. If we are, and the call turns out to be to a 32
7994 bit function, the stub will be used to move the values into the
7995 floating point registers before calling the 32 bit function. The
7996 linker will magically adjust the function call to either the 16 bit
7997 function or the 32 bit stub, depending upon where the function call
7998 is actually defined.
8000 Similarly, we need a stub if the return value might come back in a
8001 floating point register.
8003 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8004 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8005 is the code built by function_arg. This function returns a nonzero
8006 value if it builds the call instruction itself. */
8009 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8017 char *fnname, *secname, *stubname;
8018 struct mips16_stub *l;
8019 tree stubid, stubdecl;
8023 /* We don't need to do anything if we aren't in mips16 mode, or if
8024 we were invoked with the -msoft-float option. */
8025 if (! TARGET_MIPS16 || ! mips16_hard_float)
8028 /* Figure out whether the value might come back in a floating point
8030 fpret = (retval != 0
8031 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8032 && (! TARGET_SINGLE_FLOAT
8033 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8035 /* We don't need to do anything if there were no floating point
8036 arguments and the value will not be returned in a floating point
8038 if (fp_code == 0 && ! fpret)
8041 if (GET_CODE (fnmem) != MEM)
8043 fn = XEXP (fnmem, 0);
8045 /* We don't need to do anything if this is a call to a special
8046 mips16 support function. */
8047 if (GET_CODE (fn) == SYMBOL_REF
8048 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8051 /* This code will only work for o32 and o64 abis. The other ABI's
8052 require more sophisticated support. */
8053 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8056 /* We can only handle SFmode and DFmode floating point return
8058 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8061 /* If we're calling via a function pointer, then we must always call
8062 via a stub. There are magic stubs provided in libgcc.a for each
8063 of the required cases. Each of them expects the function address
8064 to arrive in register $2. */
8066 if (GET_CODE (fn) != SYMBOL_REF)
8070 rtx stub_fn, stub_mem, insn;
8072 /* ??? If this code is modified to support other ABI's, we need
8073 to handle PARALLEL return values here. */
8075 sprintf (buf, "__mips16_call_stub_%s%d",
8077 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8080 id = get_identifier (buf);
8081 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8082 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8084 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8086 if (retval == NULL_RTX)
8087 insn = gen_call_internal0 (stub_mem, arg_size,
8088 gen_rtx (REG, SImode,
8089 GP_REG_FIRST + 31));
8091 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8092 gen_rtx (REG, SImode,
8093 GP_REG_FIRST + 31));
8094 insn = emit_call_insn (insn);
8096 /* Put the register usage information on the CALL. */
8097 if (GET_CODE (insn) != CALL_INSN)
8099 CALL_INSN_FUNCTION_USAGE (insn) =
8100 gen_rtx (EXPR_LIST, VOIDmode,
8101 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8102 CALL_INSN_FUNCTION_USAGE (insn));
8104 /* If we are handling a floating point return value, we need to
8105 save $18 in the function prologue. Putting a note on the
8106 call will mean that regs_ever_live[$18] will be true if the
8107 call is not eliminated, and we can check that in the prologue
8110 CALL_INSN_FUNCTION_USAGE (insn) =
8111 gen_rtx (EXPR_LIST, VOIDmode,
8112 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8113 CALL_INSN_FUNCTION_USAGE (insn));
8115 /* Return 1 to tell the caller that we've generated the call
8120 /* We know the function we are going to call. If we have already
8121 built a stub, we don't need to do anything further. */
8123 fnname = XSTR (fn, 0);
8124 for (l = mips16_stubs; l != NULL; l = l->next)
8125 if (strcmp (l->name, fnname) == 0)
8130 /* Build a special purpose stub. When the linker sees a
8131 function call in mips16 code, it will check where the target
8132 is defined. If the target is a 32 bit call, the linker will
8133 search for the section defined here. It can tell which
8134 symbol this section is associated with by looking at the
8135 relocation information (the name is unreliable, since this
8136 might be a static function). If such a section is found, the
8137 linker will redirect the call to the start of the magic
8140 If the function does not return a floating point value, the
8141 special stub section is named
8144 If the function does return a floating point value, the stub
8146 .mips16.call.fp.FNNAME
8149 secname = (char *) alloca (strlen (fnname) + 40);
8150 sprintf (secname, ".mips16.call.%s%s",
8153 stubname = (char *) alloca (strlen (fnname) + 20);
8154 sprintf (stubname, "__call_stub_%s%s",
8157 stubid = get_identifier (stubname);
8158 stubdecl = build_decl (FUNCTION_DECL, stubid,
8159 build_function_type (void_type_node, NULL_TREE));
8160 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8162 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8164 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8168 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8170 fprintf (asm_out_file, "%s%s",
8171 need_comma ? ", " : "",
8172 (f & 3) == 1 ? "float" : "double");
8175 fprintf (asm_out_file, ")\n");
8177 fprintf (asm_out_file, "\t.set\tnomips16\n");
8178 assemble_start_function (stubdecl, stubname);
8180 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8181 fputs ("\t.ent\t", asm_out_file);
8182 assemble_name (asm_out_file, stubname);
8183 fputs ("\n", asm_out_file);
8185 assemble_name (asm_out_file, stubname);
8186 fputs (":\n", asm_out_file);
8189 /* We build the stub code by hand. That's the only way we can
8190 do it, since we can't generate 32 bit code during a 16 bit
8193 /* We don't want the assembler to insert any nops here. */
8194 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8196 mips16_fp_args (asm_out_file, fp_code, 0);
8200 fprintf (asm_out_file, "\t.set\tnoat\n");
8201 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8203 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8204 fprintf (asm_out_file, "\t.set\tat\n");
8205 /* Unfortunately, we can't fill the jump delay slot. We
8206 can't fill with one of the mtc1 instructions, because the
8207 result is not available for one instruction, so if the
8208 very first instruction in the function refers to the
8209 register, it will see the wrong value. */
8210 fprintf (asm_out_file, "\tnop\n");
8214 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8215 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8216 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8217 /* As above, we can't fill the delay slot. */
8218 fprintf (asm_out_file, "\tnop\n");
8219 if (GET_MODE (retval) == SFmode)
8220 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8221 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8224 if (TARGET_BIG_ENDIAN)
8226 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8227 reg_names[GP_REG_FIRST + 2],
8228 reg_names[FP_REG_FIRST + 1]);
8229 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8230 reg_names[GP_REG_FIRST + 3],
8231 reg_names[FP_REG_FIRST + 0]);
8235 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8236 reg_names[GP_REG_FIRST + 2],
8237 reg_names[FP_REG_FIRST + 0]);
8238 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8239 reg_names[GP_REG_FIRST + 3],
8240 reg_names[FP_REG_FIRST + 1]);
8243 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8244 /* As above, we can't fill the delay slot. */
8245 fprintf (asm_out_file, "\tnop\n");
8248 fprintf (asm_out_file, "\t.set\treorder\n");
8250 #ifdef ASM_DECLARE_FUNCTION_SIZE
8251 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8254 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8255 fputs ("\t.end\t", asm_out_file);
8256 assemble_name (asm_out_file, stubname);
8257 fputs ("\n", asm_out_file);
8260 fprintf (asm_out_file, "\t.set\tmips16\n");
8262 /* Record this stub. */
8263 l = (struct mips16_stub *) xmalloc (sizeof *l);
8264 l->name = xstrdup (fnname);
8266 l->next = mips16_stubs;
8270 /* If we expect a floating point return value, but we've built a
8271 stub which does not expect one, then we're in trouble. We can't
8272 use the existing stub, because it won't handle the floating point
8273 value. We can't build a new stub, because the linker won't know
8274 which stub to use for the various calls in this object file.
8275 Fortunately, this case is illegal, since it means that a function
8276 was declared in two different ways in a single compilation. */
8277 if (fpret && ! l->fpret)
8278 error ("can not handle inconsistent calls to `%s'", fnname);
8280 /* If we are calling a stub which handles a floating point return
8281 value, we need to arrange to save $18 in the prologue. We do
8282 this by marking the function call as using the register. The
8283 prologue will later see that it is used, and emit code to save
8290 if (retval == NULL_RTX)
8291 insn = gen_call_internal0 (fnmem, arg_size,
8292 gen_rtx (REG, SImode,
8293 GP_REG_FIRST + 31));
8295 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8296 gen_rtx (REG, SImode,
8297 GP_REG_FIRST + 31));
8298 insn = emit_call_insn (insn);
8300 if (GET_CODE (insn) != CALL_INSN)
8303 CALL_INSN_FUNCTION_USAGE (insn) =
8304 gen_rtx (EXPR_LIST, VOIDmode,
8305 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8306 CALL_INSN_FUNCTION_USAGE (insn));
8308 /* Return 1 to tell the caller that we've generated the call
8313 /* Return 0 to let the caller generate the call insn. */
8317 /* This function looks through the code for a function, and tries to
8318 optimize the usage of the $gp register. We arrange to copy $gp
8319 into a pseudo-register, and then let gcc's normal reload handling
8320 deal with the pseudo-register. Unfortunately, if reload choose to
8321 put the pseudo-register into a call-clobbered register, it will
8322 emit saves and restores for that register around any function
8323 calls. We don't need the saves, and it's faster to copy $gp than
8324 to do an actual restore. ??? This still means that we waste a
8327 This is an optimization, and the code which gcc has actually
8328 generated is correct, so we do not need to catch all cases. */
8331 mips16_optimize_gp (first)
8334 rtx gpcopy, slot, insn;
8336 /* Look through the instructions. Set GPCOPY to the register which
8337 holds a copy of $gp. Set SLOT to the stack slot where it is
8338 saved. If we find an instruction which sets GPCOPY to anything
8339 other than $gp or SLOT, then we can't use it. If we find an
8340 instruction which sets SLOT to anything other than GPCOPY, we
8345 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8349 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8352 set = PATTERN (insn);
8354 /* We know that all references to memory will be inside a SET,
8355 because there is no other way to access memory on the mips16.
8356 We don't have to worry about a PARALLEL here, because the
8357 mips.md file will never generate them for memory references. */
8358 if (GET_CODE (set) != SET)
8361 if (gpcopy == NULL_RTX
8362 && GET_CODE (SET_SRC (set)) == CONST
8363 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8364 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8365 && GET_CODE (SET_DEST (set)) == REG
8366 && GET_MODE (SET_DEST (set)) == Pmode)
8367 gpcopy = SET_DEST (set);
8368 else if (slot == NULL_RTX
8369 && gpcopy != NULL_RTX
8370 && GET_CODE (SET_DEST (set)) == MEM
8371 && GET_CODE (SET_SRC (set)) == REG
8372 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8373 && GET_MODE (SET_DEST (set)) == Pmode)
8377 offset = const0_rtx;
8378 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8379 if (GET_CODE (base) == REG
8380 && (REGNO (base) == STACK_POINTER_REGNUM
8381 || REGNO (base) == FRAME_POINTER_REGNUM))
8382 slot = SET_DEST (set);
8384 else if (gpcopy != NULL_RTX
8385 && (GET_CODE (SET_DEST (set)) == REG
8386 || GET_CODE (SET_DEST (set)) == SUBREG)
8387 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8388 && (GET_CODE (SET_DEST (set)) != REG
8389 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8390 || GET_MODE (SET_DEST (set)) != Pmode
8391 || ((GET_CODE (SET_SRC (set)) != CONST
8392 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8393 || (REGNO (XEXP (SET_SRC (set), 0))
8394 != GP_REG_FIRST + 28))
8395 && ! rtx_equal_p (SET_SRC (set), slot))))
8397 else if (slot != NULL_RTX
8398 && GET_CODE (SET_DEST (set)) == MEM
8399 && rtx_equal_p (SET_DEST (set), slot)
8400 && (GET_CODE (SET_SRC (set)) != REG
8401 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8405 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8406 different optimization. Any time we find a copy of $28 into a
8407 register, followed by an add of a symbol_ref to that register, we
8408 convert it to load the value from the constant table instead.
8409 The copy and add will take six bytes, just as the load and
8410 constant table entry will take six bytes. However, it is
8411 possible that the constant table entry will be shared.
8413 This could be a peephole optimization, but I don't know if the
8414 peephole code can call force_const_mem.
8416 Using the same register for the copy of $28 and the add of the
8417 symbol_ref is actually pretty likely, since the add instruction
8418 requires the destination and the first addend to be the same
8421 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8425 /* This optimization is only reasonable if the constant table
8426 entries are only 4 bytes. */
8427 if (Pmode != SImode)
8430 for (insn = first; insn != NULL_RTX; insn = next)
8437 next = NEXT_INSN (next);
8439 while (next != NULL_RTX
8440 && (GET_CODE (next) == NOTE
8441 || (GET_CODE (next) == INSN
8442 && (GET_CODE (PATTERN (next)) == USE
8443 || GET_CODE (PATTERN (next)) == CLOBBER))));
8445 if (next == NULL_RTX)
8448 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8451 if (GET_RTX_CLASS (GET_CODE (next)) != 'i')
8454 set1 = PATTERN (insn);
8455 if (GET_CODE (set1) != SET)
8457 set2 = PATTERN (next);
8458 if (GET_CODE (set2) != SET)
8461 if (GET_CODE (SET_DEST (set1)) == REG
8462 && GET_CODE (SET_SRC (set1)) == CONST
8463 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8464 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8465 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8466 && GET_CODE (SET_SRC (set2)) == PLUS
8467 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8468 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8469 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8473 /* We've found a case we can change to load from the
8476 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8477 if (GET_CODE (sym) != SYMBOL_REF)
8479 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8480 force_const_mem (Pmode, sym)),
8483 PUT_CODE (insn, NOTE);
8484 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8485 NOTE_SOURCE_FILE (insn) = 0;
8487 PUT_CODE (next, NOTE);
8488 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8489 NOTE_SOURCE_FILE (next) = 0;
8496 /* We can safely remove all assignments to SLOT from GPCOPY, and
8497 replace all assignments from SLOT to GPCOPY with assignments from
8500 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8504 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8507 set = PATTERN (insn);
8508 if (GET_CODE (set) != SET
8509 || GET_MODE (SET_DEST (set)) != Pmode)
8512 if (GET_CODE (SET_DEST (set)) == MEM
8513 && rtx_equal_p (SET_DEST (set), slot)
8514 && GET_CODE (SET_SRC (set)) == REG
8515 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8517 PUT_CODE (insn, NOTE);
8518 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8519 NOTE_SOURCE_FILE (insn) = 0;
8521 else if (GET_CODE (SET_DEST (set)) == REG
8522 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8523 && GET_CODE (SET_SRC (set)) == MEM
8524 && rtx_equal_p (SET_SRC (set), slot))
8526 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
8527 gen_rtx (CONST, Pmode,
8528 gen_rtx (REG, Pmode,
8529 GP_REG_FIRST + 28))),
8531 PUT_CODE (insn, NOTE);
8532 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8533 NOTE_SOURCE_FILE (insn) = 0;
8538 /* We keep a list of constants we which we have to add to internal
8539 constant tables in the middle of large functions. */
8543 struct constant *next;
8546 enum machine_mode mode;
8549 /* Add a constant to the list in *PCONSTANTS. */
8552 add_constant (pconstants, val, mode)
8553 struct constant **pconstants;
8555 enum machine_mode mode;
8559 for (c = *pconstants; c != NULL; c = c->next)
8560 if (mode == c->mode && rtx_equal_p (val, c->value))
8563 c = (struct constant *) xmalloc (sizeof *c);
8566 c->label = gen_label_rtx ();
8567 c->next = *pconstants;
8572 /* Dump out the constants in CONSTANTS after INSN. */
8575 dump_constants (constants, insn)
8576 struct constant *constants;
8587 struct constant *next;
8589 switch (GET_MODE_SIZE (c->mode))
8596 insn = emit_insn_after (gen_align_2 (), insn);
8601 insn = emit_insn_after (gen_align_4 (), insn);
8606 insn = emit_insn_after (gen_align_8 (), insn);
8611 insn = emit_label_after (c->label, insn);
8616 r = gen_consttable_qi (c->value);
8619 r = gen_consttable_hi (c->value);
8622 r = gen_consttable_si (c->value);
8625 r = gen_consttable_sf (c->value);
8628 r = gen_consttable_di (c->value);
8631 r = gen_consttable_df (c->value);
8637 insn = emit_insn_after (r, insn);
8644 emit_barrier_after (insn);
8647 /* Find the symbol in an address expression. */
8650 mips_find_symbol (addr)
8653 if (GET_CODE (addr) == MEM)
8654 addr = XEXP (addr, 0);
8655 while (GET_CODE (addr) == CONST)
8656 addr = XEXP (addr, 0);
8657 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8659 if (GET_CODE (addr) == PLUS)
8663 l1 = mips_find_symbol (XEXP (addr, 0));
8664 l2 = mips_find_symbol (XEXP (addr, 1));
8665 if (l1 != NULL_RTX && l2 == NULL_RTX)
8667 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8673 /* Exported to toplev.c.
8675 Do a final pass over the function, just before delayed branch
8679 machine_dependent_reorg (first)
8682 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
8684 struct constant *constants;
8686 if (! TARGET_MIPS16)
8689 /* If $gp is used, try to remove stores, and replace loads with
8692 mips16_optimize_gp (first);
8694 /* Scan the function looking for PC relative loads which may be out
8695 of range. All such loads will either be from the constant table,
8696 or be getting the address of a constant string. If the size of
8697 the function plus the size of the constant table is less than
8698 0x8000, then all loads are in range. */
8701 for (insn = first; insn; insn = NEXT_INSN (insn))
8703 insns_len += get_attr_length (insn);
8705 /* ??? We put switch tables in .text, but we don't define
8706 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8707 compute their lengths correctly. */
8708 if (GET_CODE (insn) == JUMP_INSN)
8712 body = PATTERN (insn);
8713 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8714 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8715 * GET_MODE_SIZE (GET_MODE (body)));
8716 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8720 /* Store the original value of insns_len in current_frame_info, so
8721 that simple_memory_operand can look at it. */
8722 current_frame_info.insns_len = insns_len;
8724 pool_size = get_pool_size ();
8725 if (insns_len + pool_size + mips_string_length < 0x8000)
8728 /* Loop over the insns and figure out what the maximum internal pool
8730 max_internal_pool_size = 0;
8731 for (insn = first; insn; insn = NEXT_INSN (insn))
8733 if (GET_CODE (insn) == INSN
8734 && GET_CODE (PATTERN (insn)) == SET)
8738 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8739 if (src == NULL_RTX)
8741 if (CONSTANT_POOL_ADDRESS_P (src))
8742 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8743 else if (SYMBOL_REF_FLAG (src))
8744 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8750 first_constant_ref = -1;
8752 for (insn = first; insn; insn = NEXT_INSN (insn))
8754 if (GET_CODE (insn) == INSN
8755 && GET_CODE (PATTERN (insn)) == SET)
8758 enum machine_mode mode;
8761 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8762 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8764 /* ??? This is very conservative, which means that we
8765 will generate too many copies of the constant table.
8766 The only solution would seem to be some form of
8768 if (((insns_len - addr)
8769 + max_internal_pool_size
8770 + get_pool_offset (src))
8773 val = get_pool_constant (src);
8774 mode = get_pool_mode (src);
8776 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8778 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8780 /* Including all of mips_string_length is conservative,
8781 and so is including all of max_internal_pool_size. */
8782 if (((insns_len - addr)
8783 + max_internal_pool_size
8785 + mips_string_length)
8789 max_internal_pool_size -= Pmode;
8792 if (val != NULL_RTX)
8796 /* This PC relative load is out of range. ??? In the
8797 case of a string constant, we are only guessing that
8798 it is range, since we don't know the offset of a
8799 particular string constant. */
8801 lab = add_constant (&constants, val, mode);
8802 newsrc = gen_rtx (MEM, mode,
8803 gen_rtx (LABEL_REF, VOIDmode, lab));
8804 RTX_UNCHANGING_P (newsrc) = 1;
8805 PATTERN (insn) = gen_rtx (SET, VOIDmode,
8806 SET_DEST (PATTERN (insn)),
8808 INSN_CODE (insn) = -1;
8810 if (first_constant_ref < 0)
8811 first_constant_ref = addr;
8815 addr += get_attr_length (insn);
8817 /* ??? We put switch tables in .text, but we don't define
8818 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8819 compute their lengths correctly. */
8820 if (GET_CODE (insn) == JUMP_INSN)
8824 body = PATTERN (insn);
8825 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8826 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8827 * GET_MODE_SIZE (GET_MODE (body)));
8828 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8831 if (GET_CODE (insn) == BARRIER)
8833 /* Output any constants we have accumulated. Note that we
8834 don't need to change ADDR, since its only use is
8835 subtraction from INSNS_LEN, and both would be changed by
8837 ??? If the instructions up to the next barrier reuse a
8838 constant, it would often be better to continue
8840 if (constants != NULL)
8841 dump_constants (constants, insn);
8843 first_constant_ref = -1;
8846 if (constants != NULL
8847 && (NEXT_INSN (insn) == NULL
8848 || (first_constant_ref >= 0
8849 && (((addr - first_constant_ref)
8850 + 2 /* for alignment */
8851 + 2 /* for a short jump insn */
8855 /* If we haven't had a barrier within 0x8000 bytes of a
8856 constant reference or we are at the end of the function,
8857 emit a barrier now. */
8859 rtx label, jump, barrier;
8861 label = gen_label_rtx ();
8862 jump = emit_jump_insn_after (gen_jump (label), insn);
8863 JUMP_LABEL (jump) = label;
8864 LABEL_NUSES (label) = 1;
8865 barrier = emit_barrier_after (jump);
8866 emit_label_after (label, barrier);
8867 first_constant_ref = -1;
8871 /* ??? If we output all references to a constant in internal
8872 constants table, we don't need to output the constant in the real
8873 constant table, but we have no way to prevent that. */
8876 /* Return nonzero if X is a SIGN or ZERO extend operator. */
8878 extend_operator (x, mode)
8880 enum machine_mode mode ATTRIBUTE_UNUSED;
8882 enum rtx_code code = GET_CODE (x);
8883 return code == SIGN_EXTEND || code == ZERO_EXTEND;
8886 /* Accept any operator that can be used to shift the high half of the
8887 input value to the lower half, suitable for truncation. The
8888 remainder (the lower half of the input, and the upper half of the
8889 output) will be discarded. */
8891 highpart_shift_operator (x, mode)
8893 enum machine_mode mode ATTRIBUTE_UNUSED;
8895 enum rtx_code code = GET_CODE (x);
8896 return (code == LSHIFTRT
8902 /* Return the length of INSN. LENGTH is the initial length computed by
8903 attributes in the machine-description file. */
8906 mips_adjust_insn_length (insn, length)
8910 /* A unconditional jump has an unfilled delay slot if it is not part
8911 of a sequence. A conditional jump normally has a delay slot, but
8912 does not on MIPS16. */
8913 if (simplejump_p (insn)
8914 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8915 || GET_CODE (insn) == CALL_INSN)))
8918 /* All MIPS16 instructions are a measly two bytes. */
8925 /* Output assembly instructions to peform a conditional branch.
8927 INSN is the branch instruction. OPERANDS[0] is the condition.
8928 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8929 of the first operand to the condition. If TWO_OPERANDS_P is
8930 non-zero the comparison takes two operands; OPERANDS[3] will be the
8933 If INVERTED_P is non-zero we are to branch if the condition does
8934 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
8936 LENGTH is the length (in bytes) of the sequence we are to generate.
8937 That tells us whether to generate a simple conditional branch, or a
8938 reversed conditional branch around a `jr' instruction. */
8940 mips_output_conditional_branch (insn,
8953 static char buffer[200];
8954 /* The kind of comparison we are doing. */
8955 enum rtx_code code = GET_CODE (operands[0]);
8956 /* Non-zero if the opcode for the comparison needs a `z' indicating
8957 that it is a comparision against zero. */
8959 /* A string to use in the assembly output to represent the first
8962 /* A string to use in the assembly output to represent the second
8963 operand. Use the hard-wired zero register if there's no second
8965 char *op2 = (two_operands_p ? ",%z3" : ",%.");
8966 /* The operand-printing string for the comparison. */
8967 char *comp = (float_p ? "%F0" : "%C0");
8968 /* The operand-printing string for the inverted comparison. */
8969 char *inverted_comp = (float_p ? "%W0" : "%N0");
8971 /* The MIPS processors (for levels of the ISA at least two), have
8972 "likely" variants of each branch instruction. These instructions
8973 annul the instruction in the delay slot if the branch is not
8975 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8977 if (!two_operands_p)
8979 /* To compute whether than A > B, for example, we normally
8980 subtract B from A and then look at the sign bit. But, if we
8981 are doing an unsigned comparison, and B is zero, we don't
8982 have to do the subtraction. Instead, we can just check to
8983 see if A is non-zero. Thus, we change the CODE here to
8984 reflect the simpler comparison operation. */
8996 /* A condition which will always be true. */
9002 /* A condition which will always be false. */
9008 /* Not a special case. */
9013 /* Relative comparisons are always done against zero. But
9014 equality comparisons are done between two operands, and therefore
9015 do not require a `z' in the assembly language output. */
9016 need_z_p = (!float_p && code != EQ && code != NE);
9017 /* For comparisons against zero, the zero is not provided
9022 /* Begin by terminating the buffer. That way we can always use
9023 strcat to add to it. */
9030 /* Just a simple conditional branch. */
9032 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9033 inverted_p ? inverted_comp : comp);
9035 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9036 inverted_p ? inverted_comp : comp,
9037 need_z_p ? "z" : "",
9045 /* Generate a reversed conditional branch around ` j'
9057 Because we have to jump four bytes *past* the following
9058 instruction if this branch was annulled, we can't just use
9059 a label, as in the picture above; there's no way to put the
9060 label after the next instruction, as the assembler does not
9061 accept `.L+4' as the target of a branch. (We can't just
9062 wait until the next instruction is output; it might be a
9063 macro and take up more than four bytes. Once again, we see
9064 why we want to eliminate macros.)
9066 If the branch is annulled, we jump four more bytes that we
9067 would otherwise; that way we skip the annulled instruction
9068 in the delay slot. */
9071 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
9074 strcpy (buffer, "%(%<");
9075 c = strchr (buffer, '\0');
9076 /* Generate the reversed comparision. This takes four
9079 sprintf (c, "%%*b%s\t%%Z2%s",
9080 inverted_p ? comp : inverted_comp,
9083 sprintf (c, "%%*b%s%s\t%s%s,%s",
9084 inverted_p ? comp : inverted_comp,
9085 need_z_p ? "z" : "",
9089 strcat (c, "\n\tnop\n\tj\t%1");
9091 /* The delay slot was unfilled. Since we're inside
9092 .noreorder, the assembler will not fill in the NOP for
9093 us, so we must do it ourselves. */
9094 strcat (buffer, "\n\tnop");
9095 strcat (buffer, "%>%)");
9099 /* We do not currently use this code. It handles jumps to
9100 arbitrary locations, using `jr', even across a 256MB boundary.
9101 We could add a -mhuge switch, and then use this code instead of
9102 the `j' alternative above when -mhuge was used. */
9107 /* Generate a reversed conditional branch around a `jr'
9121 Not pretty, but allows a conditional branch anywhere in the
9122 32-bit address space. If the original branch is annulled,
9123 then the instruction in the delay slot should be executed
9124 only if the branch is taken. The la instruction is really
9125 a macro which will usually take eight bytes, but sometimes
9126 takes only four, if the instruction to which we're jumping
9127 gets its own entry in the global pointer table, which will
9128 happen if its a case label. The assembler will then
9129 generate only a four-byte sequence, rather than eight, and
9130 there seems to be no way to tell it not to. Thus, we can't
9131 just use a `.+x' addressing form; we don't know what value
9134 So, we resort to using the explicit relocation syntax
9135 available in the assembler and do:
9137 lw $at,%got_page(target)($gp)
9138 daddiu $at,$at,%got_ofst(target)
9140 That way, this always takes up eight bytes, and we can use
9141 the `.+x' form. Of course, these explicit machinations
9142 with relocation will not work with old assemblers. Then
9143 again, neither do out-of-range branches, so we haven't lost
9146 /* The target of the reversed branch. */
9148 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9149 char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9150 char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9153 strcpy (buffer, "%(%<%[");
9154 c = strchr (buffer, '\0');
9155 /* Generate the reversed comparision. This takes four
9158 sprintf (c, "%%*b%s\t%%Z2%s",
9159 inverted_p ? comp : inverted_comp,
9162 sprintf (c, "%%*b%s%s\t%s%s,%s",
9163 inverted_p ? comp : inverted_comp,
9164 need_z_p ? "z" : "",
9168 c = strchr (buffer, '\0');
9169 /* Generate the load-address, and jump. This takes twelve
9170 bytes, for a total of 16. */
9172 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9179 /* The delay slot was unfilled. Since we're inside
9180 .noreorder, the assembler will not fill in the NOP for
9181 us, so we must do it ourselves. */
9182 strcat (buffer, "\n\tnop");
9183 strcat (buffer, "%]%>%)");
9196 /* Called to register all of our global variables with the garbage
9200 mips_add_gc_roots ()
9202 ggc_add_rtx_root (&mips_load_reg, 1);
9203 ggc_add_rtx_root (&mips_load_reg2, 1);
9204 ggc_add_rtx_root (&mips_load_reg3, 1);
9205 ggc_add_rtx_root (&mips_load_reg4, 1);
9206 ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9207 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9208 ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);