1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-flags.h"
40 #include "insn-attr.h"
41 #include "insn-codes.h"
55 #if defined(USG) || !defined(HAVE_STAB_H)
56 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
58 #include <stab.h> /* On BSD, use the system's stab.h. */
62 #define STAB_CODE_TYPE enum __stab_debug_code
64 #define STAB_CODE_TYPE int
67 extern char *mktemp PARAMS ((char *));
68 extern tree lookup_name PARAMS ((tree));
70 /* Enumeration for all of the relational tests, so that we can build
71 arrays indexed by the test type, and not worry about the order
90 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
91 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
93 static int m16_check_op PARAMS ((rtx, int, int, int));
94 static void block_move_loop PARAMS ((rtx, rtx,
98 static void block_move_call PARAMS ((rtx, rtx, rtx));
99 static FILE *mips_make_temp_file PARAMS ((void));
100 static void save_restore_insns PARAMS ((int, rtx,
102 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
103 static void mips16_fp_args PARAMS ((FILE *, int, int));
104 static void build_mips16_function_stub PARAMS ((FILE *));
105 static void mips16_optimize_gp PARAMS ((rtx));
106 static rtx add_constant PARAMS ((struct constant **,
109 static void dump_constants PARAMS ((struct constant *,
111 static rtx mips_find_symbol PARAMS ((rtx));
112 static void abort_with_insn PARAMS ((rtx, const char *))
114 static int symbolic_expression_p PARAMS ((rtx));
115 static void mips_add_gc_roots PARAMS ((void));
117 /* Global variables for machine-dependent things. */
119 /* Threshold for data being put into the small data/bss area, instead
120 of the normal data area (references to the small data/bss area take
121 1 instruction, and use the global pointer, references to the normal
122 data area takes 2 instructions). */
123 int mips_section_threshold = -1;
125 /* Count the number of .file directives, so that .loc is up to date. */
126 int num_source_filenames = 0;
128 /* Count the number of sdb related labels are generated (to find block
129 start and end boundaries). */
130 int sdb_label_count = 0;
132 /* Next label # for each statement for Silicon Graphics IRIS systems. */
135 /* Non-zero if inside of a function, because the stupid MIPS asm can't
136 handle .files inside of functions. */
137 int inside_function = 0;
139 /* Files to separate the text and the data output, so that all of the data
140 can be emitted before the text, which will mean that the assembler will
141 generate smaller code, based on the global pointer. */
142 FILE *asm_out_data_file;
143 FILE *asm_out_text_file;
145 /* Linked list of all externals that are to be emitted when optimizing
146 for the global pointer if they haven't been declared by the end of
147 the program with an appropriate .comm or initialization. */
151 struct extern_list *next; /* next external */
152 const char *name; /* name of the external */
153 int size; /* size in bytes */
156 /* Name of the file containing the current function. */
157 const char *current_function_file = "";
159 /* Warning given that Mips ECOFF can't support changing files
160 within a function. */
161 int file_in_function_warning = FALSE;
163 /* Whether to suppress issuing .loc's because the user attempted
164 to change the filename within a function. */
165 int ignore_line_number = FALSE;
167 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
173 /* The next branch instruction is a branch likely, not branch normal. */
174 int mips_branch_likely;
176 /* Count of delay slots and how many are filled. */
177 int dslots_load_total;
178 int dslots_load_filled;
179 int dslots_jump_total;
180 int dslots_jump_filled;
182 /* # of nops needed by previous insn */
183 int dslots_number_nops;
185 /* Number of 1/2/3 word references to data items (ie, not jal's). */
188 /* registers to check for load delay */
189 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
191 /* Cached operands, and operator to compare for use in set/branch on
195 /* what type of branch to use */
196 enum cmp_type branch_type;
198 /* Number of previously seen half-pic pointers and references. */
199 static int prev_half_pic_ptrs = 0;
200 static int prev_half_pic_refs = 0;
202 /* which cpu are we scheduling for */
203 enum processor_type mips_cpu;
205 /* which instruction set architecture to use. */
208 #ifdef MIPS_ABI_DEFAULT
209 /* Which ABI to use. This is defined to a constant in mips.h if the target
210 doesn't support multiple ABIs. */
214 /* Strings to hold which cpu and instruction set architecture to use. */
215 const char *mips_cpu_string; /* for -mcpu=<xxx> */
216 const char *mips_isa_string; /* for -mips{1,2,3,4} */
217 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
219 /* Whether we are generating mips16 code. This is a synonym for
220 TARGET_MIPS16, and exists for use as an attribute. */
223 /* This variable is set by -mno-mips16. We only care whether
224 -mno-mips16 appears or not, and using a string in this fashion is
225 just a way to avoid using up another bit in target_flags. */
226 const char *mips_no_mips16_string;
228 /* This is only used to determine if an type size setting option was
229 explicitly specified (-mlong64, -mint64, -mlong32). The specs
230 set this option if such an option is used. */
231 const char *mips_explicit_type_size_string;
233 /* Whether we are generating mips16 hard float code. In mips16 mode
234 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
235 -msoft-float was not specified by the user, which means that we
236 should arrange to call mips32 hard floating point code. */
237 int mips16_hard_float;
239 /* This variable is set by -mentry. We only care whether -mentry
240 appears or not, and using a string in this fashion is just a way to
241 avoid using up another bit in target_flags. */
242 const char *mips_entry_string;
244 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
247 /* If TRUE, we split addresses into their high and low parts in the RTL. */
248 int mips_split_addresses;
250 /* Generating calls to position independent functions? */
251 enum mips_abicalls_type mips_abicalls;
253 /* High and low marks for floating point values which we will accept
254 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
255 initialized in override_options. */
256 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
258 /* Mode used for saving/restoring general purpose registers. */
259 static enum machine_mode gpr_mode;
261 /* Array giving truth value on whether or not a given hard register
262 can support a given mode. */
263 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
265 /* Current frame information calculated by compute_frame_size. */
266 struct mips_frame_info current_frame_info;
268 /* Zero structure to initialize current_frame_info. */
269 struct mips_frame_info zero_frame_info;
271 /* Temporary filename used to buffer .text until end of program
273 static char *temp_filename;
275 /* Pseudo-reg holding the address of the current function when
276 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
277 by mips_finalize_pic if it was created. */
278 rtx embedded_pic_fnaddr_rtx;
280 /* The length of all strings seen when compiling for the mips16. This
281 is used to tell how many strings are in the constant pool, so that
282 we can see if we may have an overflow. This is reset each time the
283 constant pool is output. */
284 int mips_string_length;
286 /* Pseudo-reg holding the value of $28 in a mips16 function which
287 refers to GP relative global variables. */
288 rtx mips16_gp_pseudo_rtx;
290 /* In mips16 mode, we build a list of all the string constants we see
291 in a particular function. */
293 struct string_constant
295 struct string_constant *next;
299 static struct string_constant *string_constants;
301 /* List of all MIPS punctuation characters used by print_operand. */
302 char mips_print_operand_punct[256];
304 /* Map GCC register number to debugger register number. */
305 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
307 /* Buffer to use to enclose a load/store operation with %{ %} to
308 turn on .set volatile. */
309 static char volatile_buffer[60];
311 /* Hardware names for the registers. If -mrnames is used, this
312 will be overwritten with mips_sw_reg_names. */
314 char mips_reg_names[][8] =
316 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
317 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
318 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
319 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
320 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
321 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
322 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
323 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
324 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
325 "$fcc5","$fcc6","$fcc7","$rap"
328 /* Mips software names for the registers, used to overwrite the
329 mips_reg_names array. */
331 char mips_sw_reg_names[][8] =
333 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
334 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
335 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
336 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
337 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
338 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
339 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
340 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
341 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
342 "$fcc5","$fcc6","$fcc7","$rap"
345 /* Map hard register number to register class */
346 enum reg_class mips_regno_to_class[] =
348 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
349 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
350 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
351 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
352 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
353 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
354 T_REG, GR_REGS, GR_REGS, GR_REGS,
355 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
356 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
357 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
358 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
359 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
360 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
361 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
362 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
363 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
364 HI_REG, LO_REG, HILO_REG, ST_REGS,
365 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
366 ST_REGS, ST_REGS, ST_REGS, GR_REGS
369 /* Map register constraint character to register class. */
370 enum reg_class mips_char_to_class[256] =
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
431 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
432 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
433 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
434 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
435 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
439 /* Return truth value of whether OP can be used as an operands
440 where a register or 16 bit unsigned integer is needed. */
443 uns_arith_operand (op, mode)
445 enum machine_mode mode;
447 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
450 return register_operand (op, mode);
453 /* Return truth value of whether OP can be used as an operands
454 where a 16 bit integer is needed */
457 arith_operand (op, mode)
459 enum machine_mode mode;
461 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
464 /* On the mips16, a GP relative value is a signed 16 bit offset. */
465 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
468 return register_operand (op, mode);
471 /* Return truth value of whether OP can be used as an operand in a two
472 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
475 arith32_operand (op, mode)
477 enum machine_mode mode;
479 if (GET_CODE (op) == CONST_INT)
482 return register_operand (op, mode);
485 /* Return truth value of whether OP is a integer which fits in 16 bits */
490 enum machine_mode mode ATTRIBUTE_UNUSED;
492 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
495 /* Return truth value of whether OP is a 32 bit integer which is too big to
496 be loaded with one instruction. */
501 enum machine_mode mode ATTRIBUTE_UNUSED;
505 if (GET_CODE (op) != CONST_INT)
510 /* ior reg,$r0,value */
511 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
514 /* subu reg,$r0,value */
515 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
518 /* lui reg,value>>16 */
519 if ((value & 0x0000ffff) == 0)
525 /* Return truth value of whether OP is a register or the constant 0.
526 In mips16 mode, we only accept a register, since the mips16 does
530 reg_or_0_operand (op, mode)
532 enum machine_mode mode;
534 switch (GET_CODE (op))
539 return INTVAL (op) == 0;
544 return op == CONST0_RTX (mode);
548 return register_operand (op, mode);
557 /* Return truth value of whether OP is a register or the constant 0,
558 even in mips16 mode. */
561 true_reg_or_0_operand (op, mode)
563 enum machine_mode mode;
565 switch (GET_CODE (op))
568 return INTVAL (op) == 0;
571 return op == CONST0_RTX (mode);
575 return register_operand (op, mode);
584 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
587 mips_const_double_ok (op, mode)
589 enum machine_mode mode;
593 if (GET_CODE (op) != CONST_DOUBLE)
596 if (mode == VOIDmode)
599 if (mode != SFmode && mode != DFmode)
602 if (op == CONST0_RTX (mode))
605 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
606 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
609 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
611 if (REAL_VALUE_ISNAN (d))
614 if (REAL_VALUE_NEGATIVE (d))
615 d = REAL_VALUE_NEGATE (d);
619 if (REAL_VALUES_LESS (d, dfhigh)
620 && REAL_VALUES_LESS (dflow, d))
625 if (REAL_VALUES_LESS (d, sfhigh)
626 && REAL_VALUES_LESS (sflow, d))
633 /* Accept the floating point constant 1 in the appropriate mode. */
636 const_float_1_operand (op, mode)
638 enum machine_mode mode;
641 static REAL_VALUE_TYPE onedf;
642 static REAL_VALUE_TYPE onesf;
643 static int one_initialized;
645 if (GET_CODE (op) != CONST_DOUBLE
646 || mode != GET_MODE (op)
647 || (mode != DFmode && mode != SFmode))
650 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
652 /* We only initialize these values if we need them, since we will
653 never get called unless mips_isa >= 4. */
654 if (! one_initialized)
656 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
657 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
662 return REAL_VALUES_EQUAL (d, onedf);
664 return REAL_VALUES_EQUAL (d, onesf);
667 /* Return true if a memory load or store of REG plus OFFSET in MODE
668 can be represented in a single word on the mips16. */
671 mips16_simple_memory_operand (reg, offset, mode)
674 enum machine_mode mode;
681 /* We can't tell, because we don't know how the value will
682 eventually be accessed. Returning 0 here does no great
683 harm; it just prevents some possible instruction scheduling. */
687 size = GET_MODE_SIZE (mode);
689 if (INTVAL (offset) % size != 0)
691 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
695 if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size)
700 /* Return truth value if a memory operand fits in a single instruction
701 (ie, register + small offset). */
704 simple_memory_operand (op, mode)
706 enum machine_mode mode;
708 rtx addr, plus0, plus1;
710 /* Eliminate non-memory operations */
711 if (GET_CODE (op) != MEM)
714 /* dword operations really put out 2 instructions, so eliminate them. */
715 /* ??? This isn't strictly correct. It is OK to accept multiword modes
716 here, since the length attributes are being set correctly, but only
717 if the address is offsettable. LO_SUM is not offsettable. */
718 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
721 /* Decode the address now. */
723 switch (GET_CODE (addr))
732 return SMALL_INT (op);
735 plus0 = XEXP (addr, 0);
736 plus1 = XEXP (addr, 1);
737 if (GET_CODE (plus0) == REG
738 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
740 || mips16_simple_memory_operand (plus0, plus1, mode)))
743 else if (GET_CODE (plus1) == REG
744 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
746 || mips16_simple_memory_operand (plus1, plus0, mode)))
753 /* We used to allow small symbol refs here (ie, stuff in .sdata
754 or .sbss), but this causes some bugs in G++. Also, it won't
755 interfere if the MIPS linker rewrites the store instruction
756 because the function is PIC. */
758 case LABEL_REF: /* never gp relative */
762 /* If -G 0, we can never have a GP relative memory operation.
763 Also, save some time if not optimizing. */
768 rtx offset = const0_rtx;
769 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
770 if (GET_CODE (op) != SYMBOL_REF)
773 /* let's be paranoid.... */
774 if (! SMALL_INT (offset))
781 return SYMBOL_REF_FLAG (addr);
784 /* This SYMBOL_REF case is for the mips16. If the above case is
785 reenabled, this one should be merged in. */
787 /* References to the constant pool on the mips16 use a small
788 offset if the function is small. The only time we care about
789 getting this right is during delayed branch scheduling, so
790 don't need to check until then. The machine_dependent_reorg
791 function will set the total length of the instructions used
792 in the function in current_frame_info. If that is small
793 enough, we know for sure that this is a small offset. It
794 would be better if we could take into account the location of
795 the instruction within the function, but we can't, because we
796 don't know where we are. */
798 && CONSTANT_POOL_ADDRESS_P (addr)
799 && current_frame_info.insns_len > 0)
803 size = current_frame_info.insns_len + get_pool_size ();
804 if (GET_MODE_SIZE (mode) == 4)
805 return size < 4 * 0x100;
806 else if (GET_MODE_SIZE (mode) == 8)
807 return size < 8 * 0x20;
821 /* Return nonzero for a memory address that can be used to load or store
825 double_memory_operand (op, mode)
827 enum machine_mode mode;
831 if (GET_CODE (op) != MEM
832 || ! memory_operand (op, mode))
834 /* During reload, we accept a pseudo register if it has an
835 appropriate memory address. If we don't do this, we will
836 wind up reloading into a register, and then reloading that
837 register from memory, when we could just reload directly from
839 if (reload_in_progress
840 && GET_CODE (op) == REG
841 && REGNO (op) >= FIRST_PSEUDO_REGISTER
842 && reg_renumber[REGNO (op)] < 0
843 && reg_equiv_mem[REGNO (op)] != 0
844 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
847 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
848 the same test performed for 'm' in find_reloads. */
850 if (reload_in_progress
852 && (GET_CODE (op) == MEM
853 || (GET_CODE (op) == REG
854 && REGNO (op) >= FIRST_PSEUDO_REGISTER
855 && reg_renumber[REGNO (op)] < 0)))
858 if (reload_in_progress
860 && GET_CODE (op) == MEM)
866 /* During reload on the mips16, we accept a large offset
867 from the frame pointer or the stack pointer. This large
868 address will get reloaded anyhow. */
869 if (GET_CODE (addr) == PLUS
870 && GET_CODE (XEXP (addr, 0)) == REG
871 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
872 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
873 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
874 && ! SMALL_INT (XEXP (addr, 1)))
875 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
876 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
879 /* Similarly, we accept a case where the memory address is
880 itself on the stack, and will be reloaded. */
881 if (GET_CODE (addr) == MEM)
885 maddr = XEXP (addr, 0);
886 if (GET_CODE (maddr) == PLUS
887 && GET_CODE (XEXP (maddr, 0)) == REG
888 && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM
889 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
890 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
891 && ! SMALL_INT (XEXP (maddr, 1)))
892 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
893 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
897 /* We also accept the same case when we have a 16 bit signed
898 offset mixed in as well. The large address will get
899 reloaded, and the 16 bit offset will be OK. */
900 if (GET_CODE (addr) == PLUS
901 && GET_CODE (XEXP (addr, 0)) == MEM
902 && GET_CODE (XEXP (addr, 1)) == CONST_INT
903 && SMALL_INT (XEXP (addr, 1)))
905 addr = XEXP (XEXP (addr, 0), 0);
906 if (GET_CODE (addr) == PLUS
907 && GET_CODE (XEXP (addr, 0)) == REG
908 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
909 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
910 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
911 && ! SMALL_INT (XEXP (addr, 1)))
912 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
913 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
923 /* In this case we can use an instruction like sd. */
927 /* Make sure that 4 added to the address is a valid memory address.
928 This essentially just checks for overflow in an added constant. */
932 if (CONSTANT_ADDRESS_P (addr))
935 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
938 plus_constant_for_output (addr, 4));
941 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
944 equality_op (op, mode)
946 enum machine_mode mode;
948 if (mode != GET_MODE (op))
951 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
954 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
959 enum machine_mode mode;
961 if (mode != GET_MODE (op))
964 return GET_RTX_CLASS (GET_CODE (op)) == '<';
967 /* Return nonzero if the operand is either the PC or a label_ref. */
970 pc_or_label_operand (op, mode)
972 enum machine_mode mode ATTRIBUTE_UNUSED;
977 if (GET_CODE (op) == LABEL_REF)
983 /* Test for a valid operand for a call instruction.
984 Don't allow the arg pointer register or virtual regs
985 since they may change into reg + const, which the patterns
989 call_insn_operand (op, mode)
991 enum machine_mode mode ATTRIBUTE_UNUSED;
993 return (CONSTANT_ADDRESS_P (op)
994 || (GET_CODE (op) == REG && op != arg_pointer_rtx
995 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
996 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
999 /* Return nonzero if OPERAND is valid as a source operand for a move
1003 move_operand (op, mode)
1005 enum machine_mode mode;
1007 /* Accept any general operand after reload has started; doing so
1008 avoids losing if reload does an in-place replacement of a register
1009 with a SYMBOL_REF or CONST. */
1010 return (general_operand (op, mode)
1011 && (! (mips_split_addresses && mips_check_split (op, mode))
1012 || reload_in_progress || reload_completed)
1014 && GET_CODE (op) == SYMBOL_REF
1015 && ! mips16_constant (op, mode, 1, 0)));
1018 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1019 This accepts not only general_operand, but also sign extended
1020 constants and registers. We need to accept sign extended constants
1021 in case a sign extended register which is used in an expression,
1022 and is equivalent to a constant, is spilled. */
1025 movdi_operand (op, mode)
1027 enum machine_mode mode;
1031 && GET_CODE (op) == SIGN_EXTEND
1032 && GET_MODE (op) == DImode
1033 && (GET_MODE (XEXP (op, 0)) == SImode
1034 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1035 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1036 && (register_operand (XEXP (op, 0), SImode)
1037 || immediate_operand (XEXP (op, 0), SImode)))
1040 return (general_operand (op, mode)
1042 && GET_CODE (op) == SYMBOL_REF
1043 && ! mips16_constant (op, mode, 1, 0)));
1046 /* Like register_operand, but when in 64 bit mode also accept a sign
1047 extend of a 32 bit register, since the value is known to be already
1051 se_register_operand (op, mode)
1053 enum machine_mode mode;
1057 && GET_CODE (op) == SIGN_EXTEND
1058 && GET_MODE (op) == DImode
1059 && GET_MODE (XEXP (op, 0)) == SImode
1060 && register_operand (XEXP (op, 0), SImode))
1063 return register_operand (op, mode);
1066 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1067 extend of a 32 bit register, since the value is known to be already
1071 se_reg_or_0_operand (op, mode)
1073 enum machine_mode mode;
1077 && GET_CODE (op) == SIGN_EXTEND
1078 && GET_MODE (op) == DImode
1079 && GET_MODE (XEXP (op, 0)) == SImode
1080 && register_operand (XEXP (op, 0), SImode))
1083 return reg_or_0_operand (op, mode);
1086 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1087 extend of a 32 bit register, since the value is known to be already
1091 se_uns_arith_operand (op, mode)
1093 enum machine_mode mode;
1097 && GET_CODE (op) == SIGN_EXTEND
1098 && GET_MODE (op) == DImode
1099 && GET_MODE (XEXP (op, 0)) == SImode
1100 && register_operand (XEXP (op, 0), SImode))
1103 return uns_arith_operand (op, mode);
1106 /* Like arith_operand, but when in 64 bit mode also accept a sign
1107 extend of a 32 bit register, since the value is known to be already
1111 se_arith_operand (op, mode)
1113 enum machine_mode mode;
1117 && GET_CODE (op) == SIGN_EXTEND
1118 && GET_MODE (op) == DImode
1119 && GET_MODE (XEXP (op, 0)) == SImode
1120 && register_operand (XEXP (op, 0), SImode))
1123 return arith_operand (op, mode);
1126 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1127 extend of a 32 bit register, since the value is known to be already
1131 se_nonmemory_operand (op, mode)
1133 enum machine_mode mode;
1137 && GET_CODE (op) == SIGN_EXTEND
1138 && GET_MODE (op) == DImode
1139 && GET_MODE (XEXP (op, 0)) == SImode
1140 && register_operand (XEXP (op, 0), SImode))
1143 return nonmemory_operand (op, mode);
1146 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1147 sign extend of a 32 bit register, since the value is known to be
1148 already sign extended. */
1151 se_nonimmediate_operand (op, mode)
1153 enum machine_mode mode;
1157 && GET_CODE (op) == SIGN_EXTEND
1158 && GET_MODE (op) == DImode
1159 && GET_MODE (XEXP (op, 0)) == SImode
1160 && register_operand (XEXP (op, 0), SImode))
1163 return nonimmediate_operand (op, mode);
1166 /* Accept any operand that can appear in a mips16 constant table
1167 instruction. We can't use any of the standard operand functions
1168 because for these instructions we accept values that are not
1169 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1172 consttable_operand (op, mode)
1174 enum machine_mode mode ATTRIBUTE_UNUSED;
1176 return CONSTANT_P (op);
1179 /* Return nonzero if we split the address into high and low parts. */
1181 /* ??? We should also handle reg+array somewhere. We get four
1182 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1183 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1184 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1185 out of the address, then we have 4 instructions to combine. Perhaps
1186 add a 3->2 define_split for combine. */
1188 /* ??? We could also split a CONST_INT here if it is a large_int().
1189 However, it doesn't seem to be very useful to have %hi(constant).
1190 We would be better off by doing the masking ourselves and then putting
1191 the explicit high part of the constant in the RTL. This will give better
1192 optimization. Also, %hi(constant) needs assembler changes to work.
1193 There is already a define_split that does this. */
1196 mips_check_split (address, mode)
1198 enum machine_mode mode;
1200 /* ??? This is the same check used in simple_memory_operand.
1201 We use it here because LO_SUM is not offsettable. */
1202 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1205 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1206 || (GET_CODE (address) == CONST
1207 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1208 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1209 || GET_CODE (address) == LABEL_REF)
1215 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1218 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1220 enum machine_mode mode;
1224 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1225 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1228 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1229 returns a nonzero value if XINSN is a legitimate address for a
1230 memory operand of the indicated MODE. STRICT is non-zero if this
1231 function is called during reload. */
1234 mips_legitimate_address_p (mode, xinsn, strict)
1235 enum machine_mode mode;
1239 if (TARGET_DEBUG_B_MODE)
1241 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1242 strict ? "" : "not ");
1243 GO_DEBUG_RTX (xinsn);
1246 /* Check for constant before stripping off SUBREG, so that we don't
1247 accept (subreg (const_int)) which will fail to reload. */
1248 if (CONSTANT_ADDRESS_P (xinsn)
1249 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1250 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1253 while (GET_CODE (xinsn) == SUBREG)
1254 xinsn = SUBREG_REG (xinsn);
1256 /* The mips16 can only use the stack pointer as a base register when
1257 loading SImode or DImode values. */
1258 if (GET_CODE (xinsn) == REG
1259 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1262 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1264 register rtx xlow0 = XEXP (xinsn, 0);
1265 register rtx xlow1 = XEXP (xinsn, 1);
1267 while (GET_CODE (xlow0) == SUBREG)
1268 xlow0 = SUBREG_REG (xlow0);
1269 if (GET_CODE (xlow0) == REG
1270 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1271 && mips_check_split (xlow1, mode))
1275 if (GET_CODE (xinsn) == PLUS)
1277 register rtx xplus0 = XEXP (xinsn, 0);
1278 register rtx xplus1 = XEXP (xinsn, 1);
1279 register enum rtx_code code0;
1280 register enum rtx_code code1;
1282 while (GET_CODE (xplus0) == SUBREG)
1283 xplus0 = SUBREG_REG (xplus0);
1284 code0 = GET_CODE (xplus0);
1286 while (GET_CODE (xplus1) == SUBREG)
1287 xplus1 = SUBREG_REG (xplus1);
1288 code1 = GET_CODE (xplus1);
1290 /* The mips16 can only use the stack pointer as a base register
1291 when loading SImode or DImode values. */
1293 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1295 if (code1 == CONST_INT && SMALL_INT (xplus1))
1298 /* On the mips16, we represent GP relative offsets in RTL.
1299 These are 16 bit signed values, and can serve as register
1302 && mips16_gp_offset_p (xplus1))
1305 /* For some code sequences, you actually get better code by
1306 pretending that the MIPS supports an address mode of a
1307 constant address + a register, even though the real
1308 machine doesn't support it. This is because the
1309 assembler can use $r1 to load just the high 16 bits, add
1310 in the register, and fold the low 16 bits into the memory
1311 reference, whereas the compiler generates a 4 instruction
1312 sequence. On the other hand, CSE is not as effective.
1313 It would be a win to generate the lui directly, but the
1314 MIPS assembler does not have syntax to generate the
1315 appropriate relocation. */
1317 /* Also accept CONST_INT addresses here, so no else. */
1318 /* Reject combining an embedded PIC text segment reference
1319 with a register. That requires an additional
1321 /* ??? Reject combining an address with a register for the MIPS
1322 64 bit ABI, because the SGI assembler can not handle this. */
1323 if (!TARGET_DEBUG_A_MODE
1324 && (mips_abi == ABI_32
1325 || mips_abi == ABI_O64
1326 || mips_abi == ABI_EABI)
1327 && CONSTANT_ADDRESS_P (xplus1)
1328 && ! mips_split_addresses
1329 && (!TARGET_EMBEDDED_PIC
1331 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1337 if (TARGET_DEBUG_B_MODE)
1338 GO_PRINTF ("Not a legitimate address\n");
1340 /* The address was not legitimate. */
1345 /* We need a lot of little routines to check constant values on the
1346 mips16. These are used to figure out how long the instruction will
1347 be. It would be much better to do this using constraints, but
1348 there aren't nearly enough letters available. */
1351 m16_check_op (op, low, high, mask)
1357 return (GET_CODE (op) == CONST_INT
1358 && INTVAL (op) >= low
1359 && INTVAL (op) <= high
1360 && (INTVAL (op) & mask) == 0);
1364 m16_uimm3_b (op, mode)
1366 enum machine_mode mode ATTRIBUTE_UNUSED;
1368 return m16_check_op (op, 0x1, 0x8, 0);
1372 m16_simm4_1 (op, mode)
1374 enum machine_mode mode ATTRIBUTE_UNUSED;
1376 return m16_check_op (op, - 0x8, 0x7, 0);
1380 m16_nsimm4_1 (op, mode)
1382 enum machine_mode mode ATTRIBUTE_UNUSED;
1384 return m16_check_op (op, - 0x7, 0x8, 0);
1388 m16_simm5_1 (op, mode)
1390 enum machine_mode mode ATTRIBUTE_UNUSED;
1392 return m16_check_op (op, - 0x10, 0xf, 0);
1396 m16_nsimm5_1 (op, mode)
1398 enum machine_mode mode ATTRIBUTE_UNUSED;
1400 return m16_check_op (op, - 0xf, 0x10, 0);
1404 m16_uimm5_4 (op, mode)
1406 enum machine_mode mode ATTRIBUTE_UNUSED;
1408 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1412 m16_nuimm5_4 (op, mode)
1414 enum machine_mode mode ATTRIBUTE_UNUSED;
1416 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1420 m16_simm8_1 (op, mode)
1422 enum machine_mode mode ATTRIBUTE_UNUSED;
1424 return m16_check_op (op, - 0x80, 0x7f, 0);
1428 m16_nsimm8_1 (op, mode)
1430 enum machine_mode mode ATTRIBUTE_UNUSED;
1432 return m16_check_op (op, - 0x7f, 0x80, 0);
1436 m16_uimm8_1 (op, mode)
1438 enum machine_mode mode ATTRIBUTE_UNUSED;
1440 return m16_check_op (op, 0x0, 0xff, 0);
1444 m16_nuimm8_1 (op, mode)
1446 enum machine_mode mode ATTRIBUTE_UNUSED;
1448 return m16_check_op (op, - 0xff, 0x0, 0);
1452 m16_uimm8_m1_1 (op, mode)
1454 enum machine_mode mode ATTRIBUTE_UNUSED;
1456 return m16_check_op (op, - 0x1, 0xfe, 0);
1460 m16_uimm8_4 (op, mode)
1462 enum machine_mode mode ATTRIBUTE_UNUSED;
1464 return m16_check_op (op, 0x0, 0xff << 2, 3);
1468 m16_nuimm8_4 (op, mode)
1470 enum machine_mode mode ATTRIBUTE_UNUSED;
1472 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1476 m16_simm8_8 (op, mode)
1478 enum machine_mode mode ATTRIBUTE_UNUSED;
1480 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1484 m16_nsimm8_8 (op, mode)
1486 enum machine_mode mode ATTRIBUTE_UNUSED;
1488 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1491 /* References to the string table on the mips16 only use a small
1492 offset if the function is small. See the comment in the SYMBOL_REF
1493 case in simple_memory_operand. We can't check for LABEL_REF here,
1494 because the offset is always large if the label is before the
1495 referencing instruction. */
1498 m16_usym8_4 (op, mode)
1500 enum machine_mode mode ATTRIBUTE_UNUSED;
1502 if (GET_CODE (op) == SYMBOL_REF
1503 && SYMBOL_REF_FLAG (op)
1504 && current_frame_info.insns_len > 0
1505 && XSTR (op, 0)[0] == '*'
1506 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1507 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1508 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1511 struct string_constant *l;
1513 /* Make sure this symbol is on thelist of string constants to be
1514 output for this function. It is possible that it has already
1515 been output, in which case this requires a large offset. */
1516 for (l = string_constants; l != NULL; l = l->next)
1517 if (strcmp (l->label, XSTR (op, 0)) == 0)
1525 m16_usym5_4 (op, mode)
1527 enum machine_mode mode ATTRIBUTE_UNUSED;
1529 if (GET_CODE (op) == SYMBOL_REF
1530 && SYMBOL_REF_FLAG (op)
1531 && current_frame_info.insns_len > 0
1532 && XSTR (op, 0)[0] == '*'
1533 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1534 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1535 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1538 struct string_constant *l;
1540 /* Make sure this symbol is on thelist of string constants to be
1541 output for this function. It is possible that it has already
1542 been output, in which case this requires a large offset. */
1543 for (l = string_constants; l != NULL; l = l->next)
1544 if (strcmp (l->label, XSTR (op, 0)) == 0)
1551 /* Returns an operand string for the given instruction's delay slot,
1552 after updating filled delay slot statistics.
1554 We assume that operands[0] is the target register that is set.
1556 In order to check the next insn, most of this functionality is moved
1557 to FINAL_PRESCAN_INSN, and we just set the global variables that
1560 /* ??? This function no longer does anything useful, because final_prescan_insn
1561 now will never emit a nop. */
1564 mips_fill_delay_slot (ret, type, operands, cur_insn)
1565 const char *ret; /* normal string to return */
1566 enum delay_type type; /* type of delay */
1567 rtx operands[]; /* operands to use */
1568 rtx cur_insn; /* current insn */
1570 register rtx set_reg;
1571 register enum machine_mode mode;
1572 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1573 register int num_nops;
1575 if (type == DELAY_LOAD || type == DELAY_FCMP)
1578 else if (type == DELAY_HILO)
1584 /* Make sure that we don't put nop's after labels. */
1585 next_insn = NEXT_INSN (cur_insn);
1586 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1587 next_insn = NEXT_INSN (next_insn);
1589 dslots_load_total += num_nops;
1590 if (TARGET_DEBUG_F_MODE
1592 || type == DELAY_NONE
1596 || GET_CODE (next_insn) == CODE_LABEL
1597 || (set_reg = operands[0]) == 0)
1599 dslots_number_nops = 0;
1607 set_reg = operands[0];
1611 while (GET_CODE (set_reg) == SUBREG)
1612 set_reg = SUBREG_REG (set_reg);
1614 mode = GET_MODE (set_reg);
1615 dslots_number_nops = num_nops;
1616 mips_load_reg = set_reg;
1617 if (GET_MODE_SIZE (mode)
1618 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1619 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1623 if (type == DELAY_HILO)
1625 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1626 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1638 /* Determine whether a memory reference takes one (based off of the GP
1639 pointer), two (normal), or three (label + reg) instructions, and bump the
1640 appropriate counter for -mstats. */
1643 mips_count_memory_refs (op, num)
1649 rtx addr, plus0, plus1;
1650 enum rtx_code code0, code1;
1653 if (TARGET_DEBUG_B_MODE)
1655 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1659 /* Skip MEM if passed, otherwise handle movsi of address. */
1660 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1662 /* Loop, going through the address RTL. */
1666 switch (GET_CODE (addr))
1674 plus0 = XEXP (addr, 0);
1675 plus1 = XEXP (addr, 1);
1676 code0 = GET_CODE (plus0);
1677 code1 = GET_CODE (plus1);
1687 if (code0 == CONST_INT)
1702 if (code1 == CONST_INT)
1709 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1716 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1726 n_words = 2; /* always 2 words */
1730 addr = XEXP (addr, 0);
1735 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1747 n_words += additional;
1751 num_refs[n_words-1] += num;
1755 /* Return RTL for the offset from the current function to the argument.
1757 ??? Which argument is this? */
1760 embedded_pic_offset (x)
1763 if (embedded_pic_fnaddr_rtx == NULL)
1767 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1769 /* Output code at function start to initialize the pseudo-reg. */
1770 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1771 inline functions, because it is called after RTL for the function
1772 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1773 does not get copied, and ends up not matching the rest of the RTL.
1774 This solution works, but means that we get unnecessary code to
1775 initialize this value every time a function is inlined into another
1778 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1779 XEXP (DECL_RTL (current_function_decl), 0)));
1780 seq = gen_sequence ();
1782 push_topmost_sequence ();
1783 emit_insn_after (seq, get_insns ());
1784 pop_topmost_sequence ();
1788 gen_rtx_CONST (Pmode,
1789 gen_rtx_MINUS (Pmode, x,
1790 XEXP (DECL_RTL (current_function_decl), 0)));
1793 /* Return the appropriate instructions to move one operand to another. */
1796 mips_move_1word (operands, insn, unsignedp)
1801 const char *ret = 0;
1802 rtx op0 = operands[0];
1803 rtx op1 = operands[1];
1804 enum rtx_code code0 = GET_CODE (op0);
1805 enum rtx_code code1 = GET_CODE (op1);
1806 enum machine_mode mode = GET_MODE (op0);
1807 int subreg_word0 = 0;
1808 int subreg_word1 = 0;
1809 enum delay_type delay = DELAY_NONE;
1811 while (code0 == SUBREG)
1813 subreg_word0 += SUBREG_WORD (op0);
1814 op0 = SUBREG_REG (op0);
1815 code0 = GET_CODE (op0);
1818 while (code1 == SUBREG)
1820 subreg_word1 += SUBREG_WORD (op1);
1821 op1 = SUBREG_REG (op1);
1822 code1 = GET_CODE (op1);
1825 /* For our purposes, a condition code mode is the same as SImode. */
1831 int regno0 = REGNO (op0) + subreg_word0;
1835 int regno1 = REGNO (op1) + subreg_word1;
1837 /* Just in case, don't do anything for assigning a register
1838 to itself, unless we are filling a delay slot. */
1839 if (regno0 == regno1 && set_nomacro == 0)
1842 else if (GP_REG_P (regno0))
1844 if (GP_REG_P (regno1))
1845 ret = "move\t%0,%1";
1847 else if (MD_REG_P (regno1))
1850 if (regno1 != HILO_REGNUM)
1856 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
1857 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1862 if (FP_REG_P (regno1))
1863 ret = "mfc1\t%0,%1";
1865 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
1866 ret = "cfc1\t%0,$31";
1870 else if (FP_REG_P (regno0))
1872 if (GP_REG_P (regno1))
1875 ret = "mtc1\t%1,%0";
1878 if (FP_REG_P (regno1))
1879 ret = "mov.s\t%0,%1";
1882 else if (MD_REG_P (regno0))
1884 if (GP_REG_P (regno1))
1887 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1892 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
1894 if (GP_REG_P (regno1))
1897 ret = "ctc1\t%0,$31";
1902 else if (code1 == MEM)
1907 mips_count_memory_refs (op1, 1);
1909 if (GP_REG_P (regno0))
1911 /* For loads, use the mode of the memory item, instead of the
1912 target, so zero/sign extend can use this code as well. */
1913 switch (GET_MODE (op1))
1922 ret = ((unsignedp && TARGET_64BIT)
1927 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1930 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1935 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1938 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1940 size_t i = strlen (ret);
1941 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1944 sprintf (volatile_buffer, "%%{%s%%}", ret);
1945 ret = volatile_buffer;
1949 else if (code1 == CONST_INT
1950 || (code1 == CONST_DOUBLE
1951 && GET_MODE (op1) == VOIDmode))
1953 if (code1 == CONST_DOUBLE)
1955 /* This can happen when storing constants into long long
1956 bitfields. Just store the least significant word of
1958 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1961 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
1963 if (GP_REG_P (regno0))
1964 ret = "move\t%0,%z1";
1966 else if (FP_REG_P (regno0))
1969 ret = "mtc1\t%z1,%0";
1972 else if (MD_REG_P (regno0))
1979 else if (GP_REG_P (regno0))
1981 /* Don't use X format, because that will give out of
1982 range numbers for 64 bit host and 32 bit target. */
1983 if (! TARGET_MIPS16)
1984 ret = "li\t%0,%1\t\t\t# %X1";
1987 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
1989 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
1990 ret = "li\t%0,%n1\n\tneg\t%0";
1995 else if (code1 == CONST_DOUBLE && mode == SFmode)
1997 if (op1 == CONST0_RTX (SFmode))
1999 if (GP_REG_P (regno0))
2000 ret = "move\t%0,%.";
2002 else if (FP_REG_P (regno0))
2005 ret = "mtc1\t%.,%0";
2012 ret = "li.s\t%0,%1";
2016 else if (code1 == LABEL_REF)
2019 mips_count_memory_refs (op1, 1);
2024 else if (code1 == SYMBOL_REF || code1 == CONST)
2026 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
2028 rtx offset = const0_rtx;
2030 if (GET_CODE (op1) == CONST)
2031 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2033 if (GET_CODE (op1) == SYMBOL_REF)
2035 operands[2] = HALF_PIC_PTR (op1);
2038 mips_count_memory_refs (operands[2], 1);
2040 if (INTVAL (offset) == 0)
2043 ret = (unsignedp && TARGET_64BIT
2049 dslots_load_total++;
2050 operands[3] = offset;
2051 if (unsignedp && TARGET_64BIT)
2052 ret = (SMALL_INT (offset)
2053 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2054 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2056 ret = (SMALL_INT (offset)
2057 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2058 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2062 else if (TARGET_MIPS16
2064 && GET_CODE (XEXP (op1, 0)) == REG
2065 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2067 /* This case arises on the mips16; see
2068 mips16_gp_pseudo_reg. */
2069 ret = "move\t%0,%+";
2071 else if (TARGET_MIPS16
2072 && code1 == SYMBOL_REF
2073 && SYMBOL_REF_FLAG (op1)
2074 && (XSTR (op1, 0)[0] != '*'
2075 || strncmp (XSTR (op1, 0) + 1,
2077 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2079 /* This can occur when reloading the address of a GP
2080 relative symbol on the mips16. */
2081 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2086 mips_count_memory_refs (op1, 1);
2092 else if (code1 == PLUS)
2094 rtx add_op0 = XEXP (op1, 0);
2095 rtx add_op1 = XEXP (op1, 1);
2097 if (GET_CODE (XEXP (op1, 1)) == REG
2098 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2099 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2101 operands[2] = add_op0;
2102 operands[3] = add_op1;
2103 ret = "add%:\t%0,%2,%3";
2106 else if (code1 == HIGH)
2108 operands[1] = XEXP (op1, 0);
2109 ret = "lui\t%0,%%hi(%1)";
2113 else if (code0 == MEM)
2116 mips_count_memory_refs (op0, 1);
2120 int regno1 = REGNO (op1) + subreg_word1;
2122 if (GP_REG_P (regno1))
2126 case SFmode: ret = "sw\t%1,%0"; break;
2127 case SImode: ret = "sw\t%1,%0"; break;
2128 case HImode: ret = "sh\t%1,%0"; break;
2129 case QImode: ret = "sb\t%1,%0"; break;
2134 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2138 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2142 case SFmode: ret = "sw\t%z1,%0"; break;
2143 case SImode: ret = "sw\t%z1,%0"; break;
2144 case HImode: ret = "sh\t%z1,%0"; break;
2145 case QImode: ret = "sb\t%z1,%0"; break;
2150 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2154 case SFmode: ret = "sw\t%.,%0"; break;
2155 case SImode: ret = "sw\t%.,%0"; break;
2156 case HImode: ret = "sh\t%.,%0"; break;
2157 case QImode: ret = "sb\t%.,%0"; break;
2162 if (ret != 0 && MEM_VOLATILE_P (op0))
2164 size_t i = strlen (ret);
2166 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2169 sprintf (volatile_buffer, "%%{%s%%}", ret);
2170 ret = volatile_buffer;
2176 abort_with_insn (insn, "Bad move");
2180 if (delay != DELAY_NONE)
2181 return mips_fill_delay_slot (ret, delay, operands, insn);
2187 /* Return the appropriate instructions to move 2 words */
2190 mips_move_2words (operands, insn)
2194 const char *ret = 0;
2195 rtx op0 = operands[0];
2196 rtx op1 = operands[1];
2197 enum rtx_code code0 = GET_CODE (operands[0]);
2198 enum rtx_code code1 = GET_CODE (operands[1]);
2199 int subreg_word0 = 0;
2200 int subreg_word1 = 0;
2201 enum delay_type delay = DELAY_NONE;
2203 while (code0 == SUBREG)
2205 subreg_word0 += SUBREG_WORD (op0);
2206 op0 = SUBREG_REG (op0);
2207 code0 = GET_CODE (op0);
2210 if (code1 == SIGN_EXTEND)
2212 op1 = XEXP (op1, 0);
2213 code1 = GET_CODE (op1);
2216 while (code1 == SUBREG)
2218 subreg_word1 += SUBREG_WORD (op1);
2219 op1 = SUBREG_REG (op1);
2220 code1 = GET_CODE (op1);
2224 if (GET_CODE (operands[1]) == SIGN_EXTEND
2226 && code1 != CONST_INT
2227 /* The following three can happen as the result of a questionable
2229 && code1 != LABEL_REF
2230 && code1 != SYMBOL_REF
2236 int regno0 = REGNO (op0) + subreg_word0;
2240 int regno1 = REGNO (op1) + subreg_word1;
2242 /* Just in case, don't do anything for assigning a register
2243 to itself, unless we are filling a delay slot. */
2244 if (regno0 == regno1 && set_nomacro == 0)
2247 else if (FP_REG_P (regno0))
2249 if (FP_REG_P (regno1))
2250 ret = "mov.d\t%0,%1";
2258 abort_with_insn (insn, "Bad move");
2260 #ifdef TARGET_FP_CALL_32
2261 if (FP_CALL_GP_REG_P (regno1))
2262 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2265 ret = "dmtc1\t%1,%0";
2268 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2272 else if (FP_REG_P (regno1))
2278 abort_with_insn (insn, "Bad move");
2280 #ifdef TARGET_FP_CALL_32
2281 if (FP_CALL_GP_REG_P (regno0))
2282 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2285 ret = "dmfc1\t%0,%1";
2288 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2291 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2296 if (regno0 != HILO_REGNUM)
2298 else if (regno1 == 0)
2299 ret = "mtlo\t%.\n\tmthi\t%.";
2302 ret = "mthi\t%M1\n\tmtlo\t%L1";
2305 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2310 if (regno1 != HILO_REGNUM)
2314 ret = "mfhi\t%M0\n\tmflo\t%L0";
2317 else if (TARGET_64BIT)
2318 ret = "move\t%0,%1";
2320 else if (regno0 != (regno1+1))
2321 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2324 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2327 else if (code1 == CONST_DOUBLE)
2329 /* Move zero from $0 unless !TARGET_64BIT and recipient
2330 is 64-bit fp reg, in which case generate a constant. */
2331 if (op1 != CONST0_RTX (GET_MODE (op1))
2332 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2334 if (GET_MODE (op1) == DFmode)
2338 #ifdef TARGET_FP_CALL_32
2339 if (FP_CALL_GP_REG_P (regno0))
2341 if (TARGET_FLOAT64 && !TARGET_64BIT)
2343 split_double (op1, operands + 2, operands + 3);
2344 ret = "li\t%0,%2\n\tli\t%D0,%3";
2347 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2351 /* GNU as emits 64-bit code for li.d if the ISA is 3
2352 or higher. For !TARGET_64BIT && gp registers we
2353 need to avoid this by using two li instructions
2355 if (ISA_HAS_64BIT_REGS
2357 && ! FP_REG_P (regno0))
2359 split_double (op1, operands + 2, operands + 3);
2360 ret = "li\t%0,%2\n\tli\t%D0,%3";
2363 ret = "li.d\t%0,%1";
2366 else if (TARGET_64BIT)
2368 if (! TARGET_MIPS16)
2374 split_double (op1, operands + 2, operands + 3);
2375 ret = "li\t%0,%2\n\tli\t%D0,%3";
2381 if (GP_REG_P (regno0))
2383 #ifdef TARGET_FP_CALL_32
2384 && ! FP_CALL_GP_REG_P (regno0)
2387 : "move\t%0,%.\n\tmove\t%D0,%.");
2389 else if (FP_REG_P (regno0))
2394 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2399 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2401 if (GP_REG_P (regno0))
2404 : "move\t%0,%.\n\tmove\t%D0,%.");
2406 else if (FP_REG_P (regno0))
2413 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2415 else if (MD_REG_P (regno0))
2418 ret = (regno0 == HILO_REGNUM
2419 ? "mtlo\t%.\n\tmthi\t%."
2424 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2425 && GP_REG_P (regno0))
2431 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2433 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2434 ret = "li\t%0,%n1\n\tneg\t%0";
2436 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2437 ret = "li\t%0,%1\t\t# %X1";
2438 else if (HOST_BITS_PER_WIDE_INT < 64)
2439 /* We can't use 'X' for negative numbers, because then we won't
2440 get the right value for the upper 32 bits. */
2441 ret = (INTVAL (op1) < 0
2442 ? "dli\t%0,%1\t\t\t# %X1"
2443 : "dli\t%0,%X1\t\t# %1");
2445 /* We must use 'X', because otherwise LONG_MIN will print as
2446 a number that the assembler won't accept. */
2447 ret = "dli\t%0,%X1\t\t# %1";
2449 else if (HOST_BITS_PER_WIDE_INT < 64)
2451 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2454 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2455 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2456 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2458 operands[2] = GEN_INT (1);
2459 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2463 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2467 /* We use multiple shifts here, to avoid warnings about out
2468 of range shifts on 32 bit hosts. */
2469 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2471 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2472 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2476 else if (code1 == MEM)
2481 mips_count_memory_refs (op1, 2);
2483 if (FP_REG_P (regno0))
2486 else if (TARGET_64BIT)
2489 #ifdef TARGET_FP_CALL_32
2490 if (FP_CALL_GP_REG_P (regno0))
2491 ret = (double_memory_operand (op1, GET_MODE (op1))
2492 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2493 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2499 else if (double_memory_operand (op1, GET_MODE (op1)))
2501 operands[2] = adj_offsettable_operand (op1, 4);
2502 ret = (reg_mentioned_p (op0, op1)
2503 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2504 : "lw\t%0,%1\n\tlw\t%D0,%2");
2507 if (ret != 0 && MEM_VOLATILE_P (op1))
2509 size_t i = strlen (ret);
2511 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2514 sprintf (volatile_buffer, "%%{%s%%}", ret);
2515 ret = volatile_buffer;
2519 else if (code1 == LABEL_REF)
2522 mips_count_memory_refs (op1, 2);
2524 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2525 /* We deliberately remove the 'a' from '%1', so that we don't
2526 have to add SIGN_EXTEND support to print_operand_address.
2527 print_operand will just call print_operand_address in this
2528 case, so there is no problem. */
2531 ret = "dla\t%0,%a1";
2533 else if (code1 == SYMBOL_REF || code1 == CONST)
2537 && GET_CODE (XEXP (op1, 0)) == REG
2538 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2540 /* This case arises on the mips16; see
2541 mips16_gp_pseudo_reg. */
2542 ret = "move\t%0,%+";
2544 else if (TARGET_MIPS16
2545 && code1 == SYMBOL_REF
2546 && SYMBOL_REF_FLAG (op1)
2547 && (XSTR (op1, 0)[0] != '*'
2548 || strncmp (XSTR (op1, 0) + 1,
2550 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2552 /* This can occur when reloading the address of a GP
2553 relative symbol on the mips16. */
2554 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2559 mips_count_memory_refs (op1, 2);
2561 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2562 /* We deliberately remove the 'a' from '%1', so that we don't
2563 have to add SIGN_EXTEND support to print_operand_address.
2564 print_operand will just call print_operand_address in this
2565 case, so there is no problem. */
2568 ret = "dla\t%0,%a1";
2573 else if (code0 == MEM)
2577 int regno1 = REGNO (op1) + subreg_word1;
2579 if (FP_REG_P (regno1))
2582 else if (TARGET_64BIT)
2585 #ifdef TARGET_FP_CALL_32
2586 if (FP_CALL_GP_REG_P (regno1))
2587 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2593 else if (double_memory_operand (op0, GET_MODE (op0)))
2595 operands[2] = adj_offsettable_operand (op0, 4);
2596 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2600 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2601 || (code1 == CONST_DOUBLE
2602 && op1 == CONST0_RTX (GET_MODE (op1))))
2604 || double_memory_operand (op0, GET_MODE (op0))))
2610 operands[2] = adj_offsettable_operand (op0, 4);
2611 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2616 mips_count_memory_refs (op0, 2);
2618 if (ret != 0 && MEM_VOLATILE_P (op0))
2620 size_t i = strlen (ret);
2622 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2625 sprintf (volatile_buffer, "%%{%s%%}", ret);
2626 ret = volatile_buffer;
2632 abort_with_insn (insn, "Bad move");
2636 if (delay != DELAY_NONE)
2637 return mips_fill_delay_slot (ret, delay, operands, insn);
2642 /* Provide the costs of an addressing mode that contains ADDR.
2643 If ADDR is not a valid address, its cost is irrelevant. */
2646 mips_address_cost (addr)
2649 switch (GET_CODE (addr))
2659 rtx offset = const0_rtx;
2660 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2661 if (GET_CODE (addr) == LABEL_REF)
2664 if (GET_CODE (addr) != SYMBOL_REF)
2667 if (! SMALL_INT (offset))
2671 /* ... fall through ... */
2674 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2678 register rtx plus0 = XEXP (addr, 0);
2679 register rtx plus1 = XEXP (addr, 1);
2681 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2682 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2684 if (GET_CODE (plus0) != REG)
2687 switch (GET_CODE (plus1))
2690 return SMALL_INT (plus1) ? 1 : 2;
2697 return mips_address_cost (plus1) + 1;
2711 /* Return nonzero if X is an address which needs a temporary register when
2712 reloaded while generating PIC code. */
2715 pic_address_needs_scratch (x)
2718 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2719 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2720 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2721 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2722 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2728 /* Make normal rtx_code into something we can index from an array */
2730 static enum internal_test
2731 map_test_to_internal_test (test_code)
2732 enum rtx_code test_code;
2734 enum internal_test test = ITEST_MAX;
2738 case EQ: test = ITEST_EQ; break;
2739 case NE: test = ITEST_NE; break;
2740 case GT: test = ITEST_GT; break;
2741 case GE: test = ITEST_GE; break;
2742 case LT: test = ITEST_LT; break;
2743 case LE: test = ITEST_LE; break;
2744 case GTU: test = ITEST_GTU; break;
2745 case GEU: test = ITEST_GEU; break;
2746 case LTU: test = ITEST_LTU; break;
2747 case LEU: test = ITEST_LEU; break;
2755 /* Generate the code to compare two integer values. The return value is:
2756 (reg:SI xx) The pseudo register the comparison is in
2757 0 No register, generate a simple branch.
2759 ??? This is called with result nonzero by the Scond patterns in
2760 mips.md. These patterns are called with a target in the mode of
2761 the Scond instruction pattern. Since this must be a constant, we
2762 must use SImode. This means that if RESULT is non-zero, it will
2763 always be an SImode register, even if TARGET_64BIT is true. We
2764 cope with this by calling convert_move rather than emit_move_insn.
2765 This will sometimes lead to an unnecessary extension of the result;
2777 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2778 enum rtx_code test_code; /* relational test (EQ, etc) */
2779 rtx result; /* result to store comp. or 0 if branch */
2780 rtx cmp0; /* first operand to compare */
2781 rtx cmp1; /* second operand to compare */
2782 int *p_invert; /* NULL or ptr to hold whether branch needs */
2783 /* to reverse its test */
2787 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2788 int const_low; /* low bound of constant we can accept */
2789 int const_high; /* high bound of constant we can accept */
2790 int const_add; /* constant to add (convert LE -> LT) */
2791 int reverse_regs; /* reverse registers in test */
2792 int invert_const; /* != 0 if invert value if cmp1 is constant */
2793 int invert_reg; /* != 0 if invert value if cmp1 is register */
2794 int unsignedp; /* != 0 for unsigned comparisons. */
2797 static struct cmp_info info[ (int)ITEST_MAX ] = {
2799 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2800 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2801 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2802 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2803 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2804 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2805 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2806 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2807 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2808 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2811 enum internal_test test;
2812 enum machine_mode mode;
2813 struct cmp_info *p_info;
2820 test = map_test_to_internal_test (test_code);
2821 if (test == ITEST_MAX)
2824 p_info = &info[(int) test];
2825 eqne_p = (p_info->test_code == XOR);
2827 mode = GET_MODE (cmp0);
2828 if (mode == VOIDmode)
2829 mode = GET_MODE (cmp1);
2831 /* Eliminate simple branches */
2832 branch_p = (result == 0);
2835 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2837 /* Comparisons against zero are simple branches */
2838 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2839 && (! TARGET_MIPS16 || eqne_p))
2842 /* Test for beq/bne. */
2843 if (eqne_p && ! TARGET_MIPS16)
2847 /* allocate a pseudo to calculate the value in. */
2848 result = gen_reg_rtx (mode);
2851 /* Make sure we can handle any constants given to us. */
2852 if (GET_CODE (cmp0) == CONST_INT)
2853 cmp0 = force_reg (mode, cmp0);
2855 if (GET_CODE (cmp1) == CONST_INT)
2857 HOST_WIDE_INT value = INTVAL (cmp1);
2859 if (value < p_info->const_low
2860 || value > p_info->const_high
2861 /* ??? Why? And why wasn't the similar code below modified too? */
2863 && HOST_BITS_PER_WIDE_INT < 64
2864 && p_info->const_add != 0
2865 && ((p_info->unsignedp
2866 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2867 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2868 : (value + p_info->const_add) > INTVAL (cmp1))
2869 != (p_info->const_add > 0))))
2870 cmp1 = force_reg (mode, cmp1);
2873 /* See if we need to invert the result. */
2874 invert = (GET_CODE (cmp1) == CONST_INT
2875 ? p_info->invert_const : p_info->invert_reg);
2877 if (p_invert != (int *)0)
2883 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2884 Comparison between two registers, may involve switching operands. */
2885 if (GET_CODE (cmp1) == CONST_INT)
2887 if (p_info->const_add != 0)
2889 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2891 /* If modification of cmp1 caused overflow,
2892 we would get the wrong answer if we follow the usual path;
2893 thus, x > 0xffffffffU would turn into x > 0U. */
2894 if ((p_info->unsignedp
2895 ? (unsigned HOST_WIDE_INT) new >
2896 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2897 : new > INTVAL (cmp1))
2898 != (p_info->const_add > 0))
2900 /* This test is always true, but if INVERT is true then
2901 the result of the test needs to be inverted so 0 should
2902 be returned instead. */
2903 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2907 cmp1 = GEN_INT (new);
2911 else if (p_info->reverse_regs)
2918 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2922 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2923 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2926 if (test == ITEST_NE)
2928 if (! TARGET_MIPS16)
2930 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2935 reg2 = invert ? gen_reg_rtx (mode) : result;
2936 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2941 else if (test == ITEST_EQ)
2943 reg2 = invert ? gen_reg_rtx (mode) : result;
2944 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2952 if (! TARGET_MIPS16)
2956 /* The value is in $24. Copy it to another register, so
2957 that reload doesn't think it needs to store the $24 and
2958 the input to the XOR in the same location. */
2959 reg2 = gen_reg_rtx (mode);
2960 emit_move_insn (reg2, reg);
2962 one = force_reg (mode, const1_rtx);
2964 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
2970 /* Emit the common code for doing conditional branches.
2971 operand[0] is the label to jump to.
2972 The comparison operands are saved away by cmp{si,di,sf,df}. */
2975 gen_conditional_branch (operands, test_code)
2977 enum rtx_code test_code;
2979 enum cmp_type type = branch_type;
2980 rtx cmp0 = branch_cmp[0];
2981 rtx cmp1 = branch_cmp[1];
2982 enum machine_mode mode;
2991 mode = type == CMP_SI ? SImode : DImode;
2993 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3001 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3002 /* We don't want to build a comparison against a non-zero
3004 cmp1 = force_reg (mode, cmp1);
3011 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3013 reg = gen_reg_rtx (CCmode);
3015 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3016 0 in the instruction built below. The MIPS FPU handles
3017 inequality testing by testing for equality and looking for a
3019 emit_insn (gen_rtx_SET (VOIDmode, reg,
3020 gen_rtx (test_code == NE ? EQ : test_code,
3021 CCmode, cmp0, cmp1)));
3023 test_code = test_code == NE ? EQ : NE;
3031 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3034 /* Generate the branch. */
3036 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3045 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3046 gen_rtx_IF_THEN_ELSE (VOIDmode,
3047 gen_rtx (test_code, mode,
3052 /* Emit the common code for conditional moves. OPERANDS is the array
3053 of operands passed to the conditional move defined_expand. */
3056 gen_conditional_move (operands)
3059 rtx op0 = branch_cmp[0];
3060 rtx op1 = branch_cmp[1];
3061 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3062 enum rtx_code cmp_code = GET_CODE (operands[1]);
3063 enum rtx_code move_code = NE;
3064 enum machine_mode op_mode = GET_MODE (operands[0]);
3065 enum machine_mode cmp_mode;
3068 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3087 op0 = force_reg (mode, branch_cmp[1]);
3088 op1 = branch_cmp[0];
3092 op0 = force_reg (mode, branch_cmp[1]);
3093 op1 = branch_cmp[0];
3104 op0 = force_reg (mode, branch_cmp[1]);
3105 op1 = branch_cmp[0];
3109 op0 = force_reg (mode, branch_cmp[1]);
3110 op1 = branch_cmp[0];
3117 else if (cmp_code == NE)
3118 cmp_code = EQ, move_code = EQ;
3120 if (mode == SImode || mode == DImode)
3122 else if (mode == SFmode || mode == DFmode)
3127 cmp_reg = gen_reg_rtx (cmp_mode);
3128 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3129 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3131 emit_insn (gen_rtx_SET (op_mode, operands[0],
3132 gen_rtx_IF_THEN_ELSE (op_mode,
3133 gen_rtx (move_code, VOIDmode,
3135 CONST0_RTX (SImode)),
3136 operands[2], operands[3])));
3139 /* Write a loop to move a constant number of bytes.
3140 Generate load/stores as follows:
3146 temp<last> = src[MAX_MOVE_REGS-1];
3150 dest[MAX_MOVE_REGS-1] = temp<last>;
3151 src += MAX_MOVE_REGS;
3152 dest += MAX_MOVE_REGS;
3153 } while (src != final);
3155 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3156 registers are needed.
3158 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3159 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3160 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3162 #define MAX_MOVE_REGS 4
3163 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3166 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3167 rtx dest_reg; /* register holding destination address */
3168 rtx src_reg; /* register holding source address */
3169 unsigned int bytes; /* # bytes to move */
3170 int align; /* alignment */
3171 rtx orig_dest; /* original dest for change_address */
3172 rtx orig_src; /* original source for making a reg note */
3174 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
3175 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
3176 rtx align_rtx = GEN_INT (align);
3182 if (bytes < 2 * MAX_MOVE_BYTES)
3185 leftover = bytes % MAX_MOVE_BYTES;
3188 label = gen_label_rtx ();
3189 final_src = gen_reg_rtx (Pmode);
3190 bytes_rtx = GEN_INT (bytes);
3194 if (Pmode == DImode)
3196 emit_insn (gen_movdi (final_src, bytes_rtx));
3197 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3201 emit_insn (gen_movsi (final_src, bytes_rtx));
3202 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3207 if (Pmode == DImode)
3208 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3210 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3215 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3216 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3218 if (Pmode == DImode)
3220 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3221 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3222 emit_insn (gen_cmpdi (src_reg, final_src));
3226 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3227 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3228 emit_insn (gen_cmpsi (src_reg, final_src));
3231 emit_jump_insn (gen_bne (label));
3234 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3238 /* Use a library function to move some bytes. */
3241 block_move_call (dest_reg, src_reg, bytes_rtx)
3246 /* We want to pass the size as Pmode, which will normally be SImode
3247 but will be DImode if we are using 64 bit longs and pointers. */
3248 if (GET_MODE (bytes_rtx) != VOIDmode
3249 && GET_MODE (bytes_rtx) != Pmode)
3250 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3252 #ifdef TARGET_MEM_FUNCTIONS
3253 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3254 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3255 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3256 TREE_UNSIGNED (sizetype)),
3257 TYPE_MODE (sizetype));
3259 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3260 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3261 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3262 TREE_UNSIGNED (integer_type_node)),
3263 TYPE_MODE (integer_type_node));
3267 /* Expand string/block move operations.
3269 operands[0] is the pointer to the destination.
3270 operands[1] is the pointer to the source.
3271 operands[2] is the number of bytes to move.
3272 operands[3] is the alignment. */
3275 expand_block_move (operands)
3278 rtx bytes_rtx = operands[2];
3279 rtx align_rtx = operands[3];
3280 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3281 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3282 unsigned int align = INTVAL (align_rtx);
3283 rtx orig_src = operands[1];
3284 rtx orig_dest = operands[0];
3288 if (constp && bytes == 0)
3291 if (align > UNITS_PER_WORD)
3292 align = UNITS_PER_WORD;
3294 /* Move the address into scratch registers. */
3295 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3296 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3299 block_move_call (dest_reg, src_reg, bytes_rtx);
3301 else if (constp && bytes <= 2 * MAX_MOVE_BYTES
3302 && align == UNITS_PER_WORD)
3303 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3305 else if (constp && bytes <= 2 * MAX_MOVE_BYTES)
3306 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3308 change_address (orig_src, BLKmode,
3310 bytes_rtx, align_rtx));
3312 else if (constp && align >= UNITS_PER_WORD && optimize)
3313 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3315 else if (constp && optimize)
3317 /* If the alignment is not word aligned, generate a test at
3318 runtime, to see whether things wound up aligned, and we
3319 can use the faster lw/sw instead ulw/usw. */
3321 rtx temp = gen_reg_rtx (Pmode);
3322 rtx aligned_label = gen_label_rtx ();
3323 rtx join_label = gen_label_rtx ();
3324 int leftover = bytes % MAX_MOVE_BYTES;
3328 if (Pmode == DImode)
3330 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3331 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3332 emit_insn (gen_cmpdi (temp, const0_rtx));
3336 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3337 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3338 emit_insn (gen_cmpsi (temp, const0_rtx));
3341 emit_jump_insn (gen_beq (aligned_label));
3343 /* Unaligned loop. */
3344 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3345 emit_jump_insn (gen_jump (join_label));
3349 emit_label (aligned_label);
3350 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3352 emit_label (join_label);
3354 /* Bytes at the end of the loop. */
3356 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3358 change_address (orig_src, BLKmode,
3365 block_move_call (dest_reg, src_reg, bytes_rtx);
3368 /* Emit load/stores for a small constant block_move.
3370 operands[0] is the memory address of the destination.
3371 operands[1] is the memory address of the source.
3372 operands[2] is the number of bytes to move.
3373 operands[3] is the alignment.
3374 operands[4] is a temp register.
3375 operands[5] is a temp register.
3377 operands[3+num_regs] is the last temp register.
3379 The block move type can be one of the following:
3380 BLOCK_MOVE_NORMAL Do all of the block move.
3381 BLOCK_MOVE_NOT_LAST Do all but the last store.
3382 BLOCK_MOVE_LAST Do just the last store. */
3385 output_block_move (insn, operands, num_regs, move_type)
3389 enum block_move_type move_type;
3391 rtx dest_reg = XEXP (operands[0], 0);
3392 rtx src_reg = XEXP (operands[1], 0);
3393 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3394 int align = INTVAL (operands[3]);
3397 int use_lwl_lwr = 0;
3398 int last_operand = num_regs + 4;
3404 const char *load; /* load insn without nop */
3405 const char *load_nop; /* load insn with trailing nop */
3406 const char *store; /* store insn */
3407 const char *final; /* if last_store used: NULL or swr */
3408 const char *last_store; /* last store instruction */
3409 int offset; /* current offset */
3410 enum machine_mode mode; /* mode to use on (MEM) */
3413 /* ??? Detect a bug in GCC, where it can give us a register
3414 the same as one of the addressing registers and reduce
3415 the number of registers available. */
3418 && safe_regs < (int)(sizeof(xoperands) / sizeof(xoperands[0]));
3420 if (! reg_mentioned_p (operands[i], operands[0])
3421 && ! reg_mentioned_p (operands[i], operands[1]))
3422 xoperands[safe_regs++] = operands[i];
3424 if (safe_regs < last_operand)
3426 xoperands[0] = operands[0];
3427 xoperands[1] = operands[1];
3428 xoperands[2] = operands[2];
3429 xoperands[3] = operands[3];
3430 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3433 /* If we are given global or static addresses, and we would be
3434 emitting a few instructions, try to save time by using a
3435 temporary register for the pointer. */
3436 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3437 an ldl/ldr instruction pair. We play it safe, and always move
3438 constant addresses into registers when generating N32/N64 code, just
3439 in case we might emit an unaligned load instruction. */
3440 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3441 || mips_abi == ABI_N32 || mips_abi == ABI_64))
3443 if (CONSTANT_P (src_reg))
3446 mips_count_memory_refs (operands[1], 1);
3448 src_reg = operands[3 + num_regs--];
3449 if (move_type != BLOCK_MOVE_LAST)
3451 xoperands[1] = operands[1];
3452 xoperands[0] = src_reg;
3453 if (Pmode == DImode)
3454 output_asm_insn ("dla\t%0,%1", xoperands);
3456 output_asm_insn ("la\t%0,%1", xoperands);
3460 if (CONSTANT_P (dest_reg))
3463 mips_count_memory_refs (operands[0], 1);
3465 dest_reg = operands[3 + num_regs--];
3466 if (move_type != BLOCK_MOVE_LAST)
3468 xoperands[1] = operands[0];
3469 xoperands[0] = dest_reg;
3470 if (Pmode == DImode)
3471 output_asm_insn ("dla\t%0,%1", xoperands);
3473 output_asm_insn ("la\t%0,%1", xoperands);
3478 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3479 are not offsettable, however, offsettable_address_p says they are
3480 offsettable. I think this is a bug in offsettable_address_p.
3481 For expediency, we fix this by just loading the address into a register
3482 if we happen to get one. */
3484 if (GET_CODE (src_reg) == LO_SUM)
3486 src_reg = operands[3 + num_regs--];
3487 if (move_type != BLOCK_MOVE_LAST)
3489 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3490 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3491 xoperands[0] = src_reg;
3492 if (Pmode == DImode)
3493 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3495 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3499 if (GET_CODE (dest_reg) == LO_SUM)
3501 dest_reg = operands[3 + num_regs--];
3502 if (move_type != BLOCK_MOVE_LAST)
3504 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3505 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3506 xoperands[0] = dest_reg;
3507 if (Pmode == DImode)
3508 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3510 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3514 if (num_regs > (int)(sizeof (load_store) / sizeof (load_store[0])))
3515 num_regs = sizeof (load_store) / sizeof (load_store[0]);
3517 else if (num_regs < 1)
3518 abort_with_insn (insn,
3519 "Cannot do block move, not enough scratch registers");
3523 load_store[num].offset = offset;
3525 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3527 load_store[num].load = "ld\t%0,%1";
3528 load_store[num].load_nop = "ld\t%0,%1%#";
3529 load_store[num].store = "sd\t%0,%1";
3530 load_store[num].last_store = "sd\t%0,%1";
3531 load_store[num].final = 0;
3532 load_store[num].mode = DImode;
3537 /* ??? Fails because of a MIPS assembler bug? */
3538 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3540 if (BYTES_BIG_ENDIAN)
3542 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3543 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3544 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3545 load_store[num].last_store = "sdr\t%0,%2";
3546 load_store[num].final = "sdl\t%0,%1";
3550 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3551 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3552 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3553 load_store[num].last_store = "sdr\t%0,%1";
3554 load_store[num].final = "sdl\t%0,%2";
3557 load_store[num].mode = DImode;
3563 else if (bytes >= 4 && align >= 4)
3565 load_store[num].load = "lw\t%0,%1";
3566 load_store[num].load_nop = "lw\t%0,%1%#";
3567 load_store[num].store = "sw\t%0,%1";
3568 load_store[num].last_store = "sw\t%0,%1";
3569 load_store[num].final = 0;
3570 load_store[num].mode = SImode;
3575 else if (bytes >= 4 && ! TARGET_MIPS16)
3577 if (BYTES_BIG_ENDIAN)
3579 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3580 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3581 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3582 load_store[num].last_store = "swr\t%0,%2";
3583 load_store[num].final = "swl\t%0,%1";
3587 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3588 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3589 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3590 load_store[num].last_store = "swr\t%0,%1";
3591 load_store[num].final = "swl\t%0,%2";
3594 load_store[num].mode = SImode;
3600 else if (bytes >= 2 && align >= 2)
3602 load_store[num].load = "lh\t%0,%1";
3603 load_store[num].load_nop = "lh\t%0,%1%#";
3604 load_store[num].store = "sh\t%0,%1";
3605 load_store[num].last_store = "sh\t%0,%1";
3606 load_store[num].final = 0;
3607 load_store[num].mode = HImode;
3613 load_store[num].load = "lb\t%0,%1";
3614 load_store[num].load_nop = "lb\t%0,%1%#";
3615 load_store[num].store = "sb\t%0,%1";
3616 load_store[num].last_store = "sb\t%0,%1";
3617 load_store[num].final = 0;
3618 load_store[num].mode = QImode;
3623 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3625 dslots_load_total++;
3626 dslots_load_filled++;
3628 if (CONSTANT_P (src_reg))
3629 mips_count_memory_refs (src_reg, 1);
3631 if (CONSTANT_P (dest_reg))
3632 mips_count_memory_refs (dest_reg, 1);
3635 /* Emit load/stores now if we have run out of registers or are
3636 at the end of the move. */
3638 if (++num == num_regs || bytes == 0)
3640 /* If only load/store, we need a NOP after the load. */
3643 load_store[0].load = load_store[0].load_nop;
3644 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3645 dslots_load_filled--;
3648 if (move_type != BLOCK_MOVE_LAST)
3650 for (i = 0; i < num; i++)
3654 if (!operands[i + 4])
3657 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3658 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3659 REGNO (operands[i + 4]));
3661 offset = load_store[i].offset;
3662 xoperands[0] = operands[i + 4];
3663 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3664 plus_constant (src_reg, offset));
3669 = GET_MODE_SIZE (load_store[i].mode) - 1;
3671 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3672 plus_constant (src_reg,
3677 output_asm_insn (load_store[i].load, xoperands);
3681 for (i = 0; i < num; i++)
3683 int last_p = (i == num-1 && bytes == 0);
3684 int offset = load_store[i].offset;
3686 xoperands[0] = operands[i + 4];
3687 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3688 plus_constant (dest_reg, offset));
3693 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3694 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3695 plus_constant (dest_reg,
3700 if (move_type == BLOCK_MOVE_NORMAL)
3701 output_asm_insn (load_store[i].store, xoperands);
3703 else if (move_type == BLOCK_MOVE_NOT_LAST)
3706 output_asm_insn (load_store[i].store, xoperands);
3708 else if (load_store[i].final != 0)
3709 output_asm_insn (load_store[i].final, xoperands);
3713 output_asm_insn (load_store[i].last_store, xoperands);
3716 num = 0; /* reset load_store */
3724 /* Argument support functions. */
3726 /* Initialize CUMULATIVE_ARGS for a function. */
3729 init_cumulative_args (cum, fntype, libname)
3730 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3731 tree fntype; /* tree ptr for function decl */
3732 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3734 static CUMULATIVE_ARGS zero_cum;
3735 tree param, next_param;
3737 if (TARGET_DEBUG_E_MODE)
3740 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3743 fputc ('\n', stderr);
3747 tree ret_type = TREE_TYPE (fntype);
3748 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3749 tree_code_name[(int)TREE_CODE (fntype)],
3750 tree_code_name[(int)TREE_CODE (ret_type)]);
3756 /* Determine if this function has variable arguments. This is
3757 indicated by the last argument being 'void_type_mode' if there
3758 are no variable arguments. The standard MIPS calling sequence
3759 passes all arguments in the general purpose registers in this case. */
3761 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3762 param != 0; param = next_param)
3764 next_param = TREE_CHAIN (param);
3765 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3766 cum->gp_reg_found = 1;
3770 /* Advance the argument to the next argument position. */
3773 function_arg_advance (cum, mode, type, named)
3774 CUMULATIVE_ARGS *cum; /* current arg information */
3775 enum machine_mode mode; /* current arg mode */
3776 tree type; /* type of the argument or 0 if lib support */
3777 int named; /* whether or not the argument was named */
3779 if (TARGET_DEBUG_E_MODE)
3782 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3783 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3784 GET_MODE_NAME (mode));
3785 fprintf (stderr, HOST_PTR_PRINTF, type);
3786 fprintf (stderr, ", %d )\n\n", named);
3796 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3797 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3800 cum->gp_reg_found = 1;
3801 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3806 cum->gp_reg_found = 1;
3807 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3812 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3813 cum->fp_arg_words++;
3816 if (! cum->gp_reg_found && cum->arg_number <= 2)
3817 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3821 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3822 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3824 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3825 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3826 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3830 cum->gp_reg_found = 1;
3831 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3837 cum->gp_reg_found = 1;
3843 /* Return an RTL expression containing the register for the given mode,
3844 or 0 if the argument is to be passed on the stack. */
3847 function_arg (cum, mode, type, named)
3848 CUMULATIVE_ARGS *cum; /* current arg information */
3849 enum machine_mode mode; /* current arg mode */
3850 tree type; /* type of the argument or 0 if lib support */
3851 int named; /* != 0 for normal args, == 0 for ... args */
3856 int *arg_words = &cum->arg_words;
3857 int struct_p = (type != 0
3858 && (TREE_CODE (type) == RECORD_TYPE
3859 || TREE_CODE (type) == UNION_TYPE
3860 || TREE_CODE (type) == QUAL_UNION_TYPE));
3862 if (TARGET_DEBUG_E_MODE)
3865 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3866 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3867 GET_MODE_NAME (mode));
3868 fprintf (stderr, HOST_PTR_PRINTF, type);
3869 fprintf (stderr, ", %d ) = ", named);
3873 cum->last_arg_fp = 0;
3877 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3879 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3880 regbase = GP_ARG_FIRST;
3883 regbase = FP_ARG_FIRST;
3885 /* If the first arg was a float in a floating point register,
3886 then set bias to align this float arg properly. */
3887 if (cum->arg_words == 1)
3891 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3894 cum->fp_arg_words += cum->fp_arg_words & 1;
3895 cum->last_arg_fp = 1;
3896 arg_words = &cum->fp_arg_words;
3897 regbase = FP_ARG_FIRST;
3900 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3906 if (mips_abi == ABI_EABI
3907 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3908 cum->fp_arg_words += cum->fp_arg_words & 1;
3910 cum->arg_words += cum->arg_words & 1;
3913 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3914 regbase = ((cum->gp_reg_found
3915 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
3916 || cum->arg_number >= 2)
3917 ? GP_ARG_FIRST : FP_ARG_FIRST);
3918 else if (mips_abi == ABI_EABI
3919 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3921 cum->last_arg_fp = 1;
3922 arg_words = &cum->fp_arg_words;
3923 regbase = FP_ARG_FIRST;
3926 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3927 ? GP_ARG_FIRST : FP_ARG_FIRST);
3931 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3932 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3935 /* Drops through. */
3937 if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD
3938 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3939 cum->arg_words += (cum->arg_words & 1);
3940 regbase = GP_ARG_FIRST;
3947 regbase = GP_ARG_FIRST;
3952 cum->arg_words += (cum->arg_words & 1);
3953 regbase = GP_ARG_FIRST;
3956 if (*arg_words >= MAX_ARGS_IN_REGISTERS)
3958 if (TARGET_DEBUG_E_MODE)
3959 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
3968 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
3969 || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named
3970 || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
3971 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
3974 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3975 structure contains a double in its entirety, then that 64 bit
3976 chunk is passed in a floating point register. */
3979 /* First check to see if there is any such field. */
3980 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3981 if (TREE_CODE (field) == FIELD_DECL
3982 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3983 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3984 && host_integerp (bit_position (field), 0)
3985 && int_bit_position (field) % BITS_PER_WORD == 0)
3988 /* If the whole struct fits a DFmode register,
3989 we don't need the PARALLEL. */
3990 if (! field || mode == DFmode)
3991 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
3994 /* Now handle the special case by returning a PARALLEL
3995 indicating where each 64 bit chunk goes. */
3996 unsigned int chunks;
3997 HOST_WIDE_INT bitpos;
4001 /* ??? If this is a packed structure, then the last hunk won't
4005 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
4006 if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
4007 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
4009 /* assign_parms checks the mode of ENTRY_PARM, so we must
4010 use the actual mode here. */
4011 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
4014 regno = regbase + *arg_words + bias;
4015 field = TYPE_FIELDS (type);
4016 for (i = 0; i < chunks; i++)
4020 for (; field; field = TREE_CHAIN (field))
4021 if (TREE_CODE (field) == FIELD_DECL
4022 && int_bit_position (field) >= bitpos)
4026 && int_bit_position (field) == bitpos
4027 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4028 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4029 reg = gen_rtx_REG (DFmode,
4030 regno + FP_ARG_FIRST - GP_ARG_FIRST);
4032 reg = gen_rtx_REG (word_mode, regno);
4035 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4036 GEN_INT (bitpos / BITS_PER_UNIT));
4044 if (TARGET_DEBUG_E_MODE)
4045 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
4046 struct_p ? ", [struct]" : "");
4048 /* The following is a hack in order to pass 1 byte structures
4049 the same way that the MIPS compiler does (namely by passing
4050 the structure in the high byte or half word of the register).
4051 This also makes varargs work. If we have such a structure,
4052 we save the adjustment RTL, and the call define expands will
4053 emit them. For the VOIDmode argument (argument after the
4054 last real argument), pass back a parallel vector holding each
4055 of the adjustments. */
4057 /* ??? function_arg can be called more than once for each argument.
4058 As a result, we compute more adjustments than we need here.
4059 See the CUMULATIVE_ARGS definition in mips.h. */
4061 /* ??? This scheme requires everything smaller than the word size to
4062 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4063 that would mean every int needs to be shifted left, which is very
4064 inefficient. Let's not carry this compatibility to the 64 bit
4065 calling convention for now. */
4067 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
4068 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4070 rtx amount = GEN_INT (BITS_PER_WORD
4071 - int_size_in_bytes (type) * BITS_PER_UNIT);
4072 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
4075 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
4077 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
4081 /* We will be called with a mode of VOIDmode after the last argument
4082 has been seen. Whatever we return will be passed to the call
4083 insn. If we need any shifts for small structures, return them in
4084 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4085 mode. Otherwise, if we have need a mips16 fp_code, return a REG
4086 with the code stored as the mode. */
4087 if (mode == VOIDmode)
4089 if (cum->num_adjusts > 0)
4090 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
4091 gen_rtvec_v (cum->num_adjusts, cum->adjust));
4092 else if (TARGET_MIPS16 && cum->fp_code != 0)
4093 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
4100 function_arg_partial_nregs (cum, mode, type, named)
4101 CUMULATIVE_ARGS *cum; /* current arg information */
4102 enum machine_mode mode; /* current arg mode */
4103 tree type; /* type of the argument or 0 if lib support */
4104 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
4106 if ((mode == BLKmode
4107 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4108 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4109 && cum->arg_words < MAX_ARGS_IN_REGISTERS
4110 && mips_abi != ABI_EABI)
4113 if (mode == BLKmode)
4114 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
4117 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4119 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
4120 return 0; /* structure fits in registers */
4122 if (TARGET_DEBUG_E_MODE)
4123 fprintf (stderr, "function_arg_partial_nregs = %d\n",
4124 MAX_ARGS_IN_REGISTERS - cum->arg_words);
4126 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
4129 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
4130 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4132 if (TARGET_DEBUG_E_MODE)
4133 fprintf (stderr, "function_arg_partial_nregs = 1\n");
4141 /* Create the va_list data type. */
4144 mips_build_va_list ()
4146 if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4148 tree f_fpr, f_rem, f_gpr, record;
4150 record = make_node (RECORD_TYPE);
4152 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fp_regs"),
4154 f_rem = build_decl (FIELD_DECL, get_identifier ("__fp_left"),
4156 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gp_regs"),
4159 DECL_FIELD_CONTEXT (f_fpr) = record;
4160 DECL_FIELD_CONTEXT (f_rem) = record;
4161 DECL_FIELD_CONTEXT (f_gpr) = record;
4163 TYPE_FIELDS (record) = f_fpr;
4164 TREE_CHAIN (f_fpr) = f_rem;
4165 TREE_CHAIN (f_rem) = f_gpr;
4167 layout_type (record);
4172 return ptr_type_node;
4175 /* Implement va_start. */
4178 mips_va_start (stdarg_p, valist, nextarg)
4186 arg_words = current_function_args_info.arg_words;
4188 if (mips_abi == ABI_EABI)
4190 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4192 tree f_fpr, f_rem, f_gpr, fpr, rem, gpr;
4196 fpro = (8 - current_function_args_info.fp_arg_words);
4201 f_fpr = TYPE_FIELDS (va_list_type_node);
4202 f_rem = TREE_CHAIN (f_fpr);
4203 f_gpr = TREE_CHAIN (f_rem);
4205 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4206 rem = build (COMPONENT_REF, TREE_TYPE (f_rem), valist, f_rem);
4207 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4210 gpro = (8 - arg_words) * UNITS_PER_WORD;
4212 gpro = (stdarg_p ? 0 : UNITS_PER_WORD);
4214 gprv = make_tree (ptr_type_node, nextarg);
4217 gprv = build (PLUS_EXPR, ptr_type_node, gprv,
4218 build_int_2 (-gpro, -1));
4221 t = build (MODIFY_EXPR, ptr_type_node, gpr, gprv);
4222 TREE_SIDE_EFFECTS (t) = 1;
4223 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4225 t = build (MODIFY_EXPR, integer_type_node, rem,
4226 build_int_2 (fpro, 0));
4227 TREE_SIDE_EFFECTS (t) = 1;
4228 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4233 fprv = fold (build (PLUS_EXPR, ptr_type_node, gprv,
4234 build_int_2 (-(fpro*8), -1)));
4237 fprv = fold (build (BIT_AND_EXPR, ptr_type_node, fprv,
4238 build_int_2 (-8, -1)));
4240 t = build (MODIFY_EXPR, ptr_type_node, fpr, fprv);
4241 TREE_SIDE_EFFECTS (t) = 1;
4242 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4249 ofs = (stdarg_p ? 0 : UNITS_PER_WORD);
4251 ofs = (8 - arg_words) * UNITS_PER_WORD;
4253 nextarg = plus_constant (nextarg, -ofs);
4254 std_expand_builtin_va_start (1, valist, nextarg);
4265 /* ??? This had been conditional on
4266 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4267 and both iris5.h and iris6.h define _MIPS_SIM. */
4268 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4269 ofs = (arg_words >= 8 ? -UNITS_PER_WORD : 0);
4271 ofs = -UNITS_PER_WORD;
4274 nextarg = plus_constant (nextarg, ofs);
4275 std_expand_builtin_va_start (1, valist, nextarg);
4279 /* Implement va_arg. */
4282 mips_va_arg (valist, type)
4285 HOST_WIDE_INT size, rsize;
4289 size = int_size_in_bytes (type);
4290 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4292 if (mips_abi == ABI_EABI)
4296 rtx lab_over = NULL_RTX, lab_false, r;
4299 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4301 size = rsize = POINTER_SIZE / BITS_PER_UNIT;
4303 addr_rtx = gen_reg_rtx (Pmode);
4305 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4307 tree f_fpr, f_rem, f_gpr, fpr, rem;
4309 f_fpr = TYPE_FIELDS (va_list_type_node);
4310 f_rem = TREE_CHAIN (f_fpr);
4311 f_gpr = TREE_CHAIN (f_rem);
4313 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4314 rem = build (COMPONENT_REF, TREE_TYPE (f_rem), valist, f_rem);
4315 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4317 if (TREE_CODE (type) == REAL_TYPE)
4319 lab_false = gen_label_rtx ();
4320 lab_over = gen_label_rtx ();
4322 r = expand_expr (rem, NULL_RTX, TYPE_MODE (TREE_TYPE (rem)),
4324 emit_cmp_and_jump_insns (r, const0_rtx, LE, const1_rtx,
4325 GET_MODE (r), 1, 1, lab_false);
4327 t = build (PLUS_EXPR, TREE_TYPE (rem), rem,
4328 build_int_2 (-1, -1));
4329 t = build (MODIFY_EXPR, TREE_TYPE (rem), rem, t);
4330 TREE_SIDE_EFFECTS (t) = 1;
4331 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4333 t = build (POSTINCREMENT_EXPR, TREE_TYPE (fpr), fpr,
4334 build_int_2 (8, 0));
4335 TREE_SIDE_EFFECTS (t) = 1;
4336 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4338 emit_move_insn (addr_rtx, r);
4340 /* Ensure that the POSTINCREMENT is emitted before lab_over */
4343 emit_jump (lab_over);
4345 emit_label (lab_false);
4353 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4355 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4356 build_int_2 (2*UNITS_PER_WORD - 1, 0));
4357 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4358 build_int_2 (-2*UNITS_PER_WORD, -1));
4359 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4360 TREE_SIDE_EFFECTS (t) = 1;
4361 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4364 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr, size_int (rsize));
4365 TREE_SIDE_EFFECTS (t) = 1;
4366 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4368 emit_move_insn (addr_rtx, r);
4370 /* Ensure that the above POSTINCREMENT is emitted before lab_over */
4374 emit_label (lab_over);
4378 r = gen_rtx_MEM (Pmode, addr_rtx);
4379 MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4380 emit_move_insn (addr_rtx, r);
4384 if (BYTES_BIG_ENDIAN && rsize != size)
4385 addr_rtx = plus_constant (addr_rtx, rsize - size);
4394 /* ??? The original va-mips.h did always align, despite the fact
4395 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4396 increment mechanism. */
4400 else if (TYPE_ALIGN (type) > 32)
4405 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4406 build_int_2 (align - 1, 0));
4407 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4408 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4409 TREE_SIDE_EFFECTS (t) = 1;
4410 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4412 /* Everything past the alignment is standard. */
4413 return std_expand_builtin_va_arg (valist, type);
4417 /* Abort after printing out a specific insn. */
4420 abort_with_insn (insn, reason)
4429 /* Set up the threshold for data to go into the small data area, instead
4430 of the normal data area, and detect any conflicts in the switches. */
4435 register int i, start;
4437 register enum machine_mode mode;
4439 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4441 if (mips_section_threshold <= 0)
4442 target_flags &= ~MASK_GPOPT;
4444 target_flags |= MASK_GPOPT;
4446 /* If both single-float and soft-float are set, then clear the one that
4447 was set by TARGET_DEFAULT, leaving the one that was set by the
4448 user. We assume here that the specs prevent both being set by the
4450 #ifdef TARGET_DEFAULT
4451 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4452 target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT));
4455 /* Get the architectural level. */
4456 if (mips_isa_string == 0)
4457 mips_isa = MIPS_ISA_DEFAULT;
4459 else if (ISDIGIT (*mips_isa_string))
4461 mips_isa = atoi (mips_isa_string);
4464 /* -mno-mips16 overrides -mips16. */
4465 if (mips_no_mips16_string == NULL)
4467 target_flags |= MASK_MIPS16;
4471 mips_isa = MIPS_ISA_DEFAULT;
4475 mips_isa = MIPS_ISA_DEFAULT;
4478 else if (mips_isa < 1 || mips_isa > 4)
4480 error ("-mips%d not supported", mips_isa);
4487 error ("bad value (%s) for -mips switch", mips_isa_string);
4491 #ifdef MIPS_ABI_DEFAULT
4492 /* Get the ABI to use. */
4493 if (mips_abi_string == (char *) 0)
4494 mips_abi = MIPS_ABI_DEFAULT;
4495 else if (! strcmp (mips_abi_string, "32"))
4497 else if (! strcmp (mips_abi_string, "o64"))
4499 else if (! strcmp (mips_abi_string, "n32"))
4501 else if (! strcmp (mips_abi_string, "64"))
4503 else if (! strcmp (mips_abi_string, "eabi"))
4504 mips_abi = ABI_EABI;
4506 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4508 /* A specified ISA defaults the ABI if it was not specified. */
4509 if (mips_abi_string == 0 && mips_isa_string
4510 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4512 if (! ISA_HAS_64BIT_REGS)
4518 /* A specified ABI defaults the ISA if it was not specified. */
4519 else if (mips_isa_string == 0 && mips_abi_string
4520 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4522 if (mips_abi == ABI_32)
4524 else if (mips_abi == ABI_N32)
4530 /* If both ABI and ISA were specified, check for conflicts. */
4531 else if (mips_isa_string && mips_abi_string)
4533 if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
4534 || mips_abi == ABI_O64))
4535 || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32))
4536 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4539 /* Override TARGET_DEFAULT if necessary. */
4540 if (mips_abi == ABI_32)
4541 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4543 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4544 then set the type sizes. In the EABI in 64 bit mode, longs and
4545 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4546 if (mips_explicit_type_size_string == NULL
4547 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4548 || mips_abi == ABI_64))
4549 target_flags |= MASK_LONG64;
4551 /* ??? This doesn't work yet, so don't let people try to use it. */
4552 if (mips_abi == ABI_32)
4553 error ("The -mabi=32 support does not work yet.");
4556 if (mips_abi_string)
4557 error ("This target does not support the -mabi switch.");
4560 #ifdef MIPS_CPU_STRING_DEFAULT
4561 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4562 greater than that supported by the default processor, then the user gets
4563 an error. Normally, the compiler will just default to the base level cpu
4564 for the indicated isa. */
4565 if (mips_cpu_string == 0)
4566 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4569 /* Identify the processor type */
4570 if (mips_cpu_string == 0
4571 || !strcmp (mips_cpu_string, "default")
4572 || !strcmp (mips_cpu_string, "DEFAULT"))
4577 mips_cpu_string = "3000";
4578 mips_cpu = PROCESSOR_R3000;
4581 mips_cpu_string = "6000";
4582 mips_cpu = PROCESSOR_R6000;
4585 mips_cpu_string = "4000";
4586 mips_cpu = PROCESSOR_R4000;
4589 mips_cpu_string = "8000";
4590 mips_cpu = PROCESSOR_R8000;
4597 const char *p = mips_cpu_string;
4600 /* We need to cope with the various "vr" prefixes for the NEC 4300
4601 and 4100 processors. */
4602 if (*p == 'v' || *p == 'V')
4605 if (*p == 'r' || *p == 'R')
4608 /* Since there is no difference between a R2000 and R3000 in
4609 terms of the scheduler, we collapse them into just an R3000. */
4611 mips_cpu = PROCESSOR_DEFAULT;
4615 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4616 mips_cpu = PROCESSOR_R3000;
4620 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4621 mips_cpu = PROCESSOR_R3000;
4622 else if (!strcmp (p, "3900"))
4623 mips_cpu = PROCESSOR_R3900;
4627 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4628 mips_cpu = PROCESSOR_R4000;
4629 /* The vr4100 is a non-FP ISA III processor with some extra
4631 else if (!strcmp (p, "4100"))
4633 mips_cpu = PROCESSOR_R4100;
4634 target_flags |= MASK_SOFT_FLOAT ;
4636 /* The vr4300 is a standard ISA III processor, but with a different
4638 else if (!strcmp (p, "4300"))
4639 mips_cpu = PROCESSOR_R4300;
4640 /* The r4400 is exactly the same as the r4000 from the compiler's
4642 else if (!strcmp (p, "4400"))
4643 mips_cpu = PROCESSOR_R4000;
4644 else if (!strcmp (p, "4600"))
4645 mips_cpu = PROCESSOR_R4600;
4646 else if (!strcmp (p, "4650"))
4647 mips_cpu = PROCESSOR_R4650;
4651 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4652 mips_cpu = PROCESSOR_R5000;
4656 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4657 mips_cpu = PROCESSOR_R6000;
4661 if (!strcmp (p, "8000"))
4662 mips_cpu = PROCESSOR_R8000;
4666 if (!strcmp (p, "orion"))
4667 mips_cpu = PROCESSOR_R4600;
4672 && mips_cpu != PROCESSOR_R4300
4673 && mips_cpu != PROCESSOR_R4100
4674 && mips_cpu != PROCESSOR_R5000)
4675 mips_cpu = PROCESSOR_DEFAULT;
4677 if (mips_cpu == PROCESSOR_DEFAULT)
4679 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4680 mips_cpu_string = "default";
4684 if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
4685 || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
4686 || ((mips_cpu == PROCESSOR_R4000
4687 || mips_cpu == PROCESSOR_R4100
4688 || mips_cpu == PROCESSOR_R4300
4689 || mips_cpu == PROCESSOR_R4600
4690 || mips_cpu == PROCESSOR_R4650)
4691 && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
4692 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4694 /* make sure sizes of ints/longs/etc. are ok */
4695 if (! ISA_HAS_64BIT_REGS)
4698 fatal ("-mips%d does not support 64 bit fp registers", mips_isa);
4700 else if (TARGET_64BIT)
4701 fatal ("-mips%d does not support 64 bit gp registers", mips_isa);
4704 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4705 flag_pcc_struct_return = 0;
4707 /* Tell halfpic.c that we have half-pic code if we do. */
4708 if (TARGET_HALF_PIC)
4711 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4712 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4713 /* ??? -non_shared turns off pic code generation, but this is not
4715 if (TARGET_ABICALLS)
4717 mips_abicalls = MIPS_ABICALLS_YES;
4719 if (mips_section_threshold > 0)
4720 warning ("-G is incompatible with PIC code which is the default");
4723 mips_abicalls = MIPS_ABICALLS_NO;
4725 /* -membedded-pic is a form of PIC code suitable for embedded
4726 systems. All calls are made using PC relative addressing, and
4727 all data is addressed using the $gp register. This requires gas,
4728 which does most of the work, and GNU ld, which automatically
4729 expands PC relative calls which are out of range into a longer
4730 instruction sequence. All gcc really does differently is
4731 generate a different sequence for a switch. */
4732 if (TARGET_EMBEDDED_PIC)
4735 if (TARGET_ABICALLS)
4736 warning ("-membedded-pic and -mabicalls are incompatible");
4739 warning ("-G and -membedded-pic are incompatible");
4741 /* Setting mips_section_threshold is not required, because gas
4742 will force everything to be GP addressable anyhow, but
4743 setting it will cause gcc to make better estimates of the
4744 number of instructions required to access a particular data
4746 mips_section_threshold = 0x7fffffff;
4749 /* This optimization requires a linker that can support a R_MIPS_LO16
4750 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
4751 GNU ld has this support, but not all other MIPS linkers do, so we enable
4752 this optimization only if the user requests it, or if GNU ld is the
4753 standard linker for this configuration. */
4754 /* ??? This does not work when target addresses are DImode.
4755 This is because we are missing DImode high/lo_sum patterns. */
4756 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
4758 mips_split_addresses = 1;
4760 mips_split_addresses = 0;
4762 /* -mrnames says to use the MIPS software convention for register
4763 names instead of the hardware names (ie, $a0 instead of $4).
4764 We do this by switching the names in mips_reg_names, which the
4765 reg_names points into via the REGISTER_NAMES macro. */
4767 if (TARGET_NAME_REGS)
4768 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names,
4769 sizeof (mips_reg_names));
4771 /* When compiling for the mips16, we can not use floating point. We
4772 record the original hard float value in mips16_hard_float. */
4775 if (TARGET_SOFT_FLOAT)
4776 mips16_hard_float = 0;
4778 mips16_hard_float = 1;
4779 target_flags |= MASK_SOFT_FLOAT;
4781 /* Don't run the scheduler before reload, since it tends to
4782 increase register pressure. */
4783 flag_schedule_insns = 0;
4786 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
4787 to avoid using up another bit in target_flags. */
4788 if (mips_entry_string != NULL)
4790 if (*mips_entry_string != '\0')
4791 error ("Invalid option `entry%s'", mips_entry_string);
4793 if (! TARGET_MIPS16)
4794 warning ("-mentry is only meaningful with -mips-16");
4799 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
4800 attributes can access it. */
4806 /* Initialize the high and low values for legitimate floating point
4807 constants. Rather than trying to get the accuracy down to the
4808 last bit, just use approximate ranges. */
4809 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
4810 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
4811 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
4812 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
4814 mips_print_operand_punct['?'] = 1;
4815 mips_print_operand_punct['#'] = 1;
4816 mips_print_operand_punct['&'] = 1;
4817 mips_print_operand_punct['!'] = 1;
4818 mips_print_operand_punct['*'] = 1;
4819 mips_print_operand_punct['@'] = 1;
4820 mips_print_operand_punct['.'] = 1;
4821 mips_print_operand_punct['('] = 1;
4822 mips_print_operand_punct[')'] = 1;
4823 mips_print_operand_punct['['] = 1;
4824 mips_print_operand_punct[']'] = 1;
4825 mips_print_operand_punct['<'] = 1;
4826 mips_print_operand_punct['>'] = 1;
4827 mips_print_operand_punct['{'] = 1;
4828 mips_print_operand_punct['}'] = 1;
4829 mips_print_operand_punct['^'] = 1;
4830 mips_print_operand_punct['$'] = 1;
4831 mips_print_operand_punct['+'] = 1;
4832 mips_print_operand_punct['~'] = 1;
4834 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4835 mips_char_to_class['e'] = M16_NA_REGS;
4836 mips_char_to_class['t'] = T_REG;
4837 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4838 mips_char_to_class['h'] = HI_REG;
4839 mips_char_to_class['l'] = LO_REG;
4840 mips_char_to_class['a'] = HILO_REG;
4841 mips_char_to_class['x'] = MD_REGS;
4842 mips_char_to_class['b'] = ALL_REGS;
4843 mips_char_to_class['y'] = GR_REGS;
4844 mips_char_to_class['z'] = ST_REGS;
4846 /* Set up array to map GCC register number to debug register number.
4847 Ignore the special purpose register numbers. */
4849 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4850 mips_dbx_regno[i] = -1;
4852 start = GP_DBX_FIRST - GP_REG_FIRST;
4853 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4854 mips_dbx_regno[i] = i + start;
4856 start = FP_DBX_FIRST - FP_REG_FIRST;
4857 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4858 mips_dbx_regno[i] = i + start;
4860 /* Set up array giving whether a given register can hold a given mode.
4861 At present, restrict ints from being in FP registers, because reload
4862 is a little enthusiastic about storing extra values in FP registers,
4863 and this is not good for things like OS kernels. Also, due to the
4864 mandatory delay, it is as fast to load from cached memory as to move
4865 from the FP register. */
4867 for (mode = VOIDmode;
4868 mode != MAX_MACHINE_MODE;
4869 mode = (enum machine_mode) ((int)mode + 1))
4871 register int size = GET_MODE_SIZE (mode);
4872 register enum mode_class class = GET_MODE_CLASS (mode);
4874 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4881 temp = (regno == FPSW_REGNUM);
4883 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4884 || FP_REG_P (regno));
4887 else if (GP_REG_P (regno))
4888 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4890 else if (FP_REG_P (regno))
4891 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
4892 && (class == MODE_FLOAT
4893 || class == MODE_COMPLEX_FLOAT
4894 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
4895 && (! TARGET_SINGLE_FLOAT || size <= 4));
4897 else if (MD_REG_P (regno))
4898 temp = (class == MODE_INT
4899 && (size <= UNITS_PER_WORD
4900 || (regno == MD_REG_FIRST
4901 && size == 2 * UNITS_PER_WORD)));
4906 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4910 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4911 initialized yet, so we can't use that here. */
4912 gpr_mode = TARGET_64BIT ? DImode : SImode;
4914 /* Provide default values for align_* for 64-bit targets. */
4915 if (TARGET_64BIT && !TARGET_MIPS16)
4917 if (align_loops == 0)
4919 if (align_jumps == 0)
4921 if (align_functions == 0)
4922 align_functions = 8;
4925 /* Register global variables with the garbage collector. */
4926 mips_add_gc_roots ();
4929 /* On the mips16, we want to allocate $24 (T_REG) before other
4930 registers for instructions for which it is possible. This helps
4931 avoid shuffling registers around in order to set up for an xor,
4932 encouraging the compiler to use a cmp instead. */
4935 mips_order_regs_for_local_alloc ()
4939 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4940 reg_alloc_order[i] = i;
4944 /* It really doesn't matter where we put register 0, since it is
4945 a fixed register anyhow. */
4946 reg_alloc_order[0] = 24;
4947 reg_alloc_order[24] = 0;
4952 /* The MIPS debug format wants all automatic variables and arguments
4953 to be in terms of the virtual frame pointer (stack pointer before
4954 any adjustment in the function), while the MIPS 3.0 linker wants
4955 the frame pointer to be the stack pointer after the initial
4956 adjustment. So, we do the adjustment here. The arg pointer (which
4957 is eliminated) points to the virtual frame pointer, while the frame
4958 pointer (which may be eliminated) points to the stack pointer after
4959 the initial adjustments. */
4962 mips_debugger_offset (addr, offset)
4964 HOST_WIDE_INT offset;
4966 rtx offset2 = const0_rtx;
4967 rtx reg = eliminate_constant_term (addr, &offset2);
4970 offset = INTVAL (offset2);
4972 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4973 || reg == hard_frame_pointer_rtx)
4975 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
4976 ? compute_frame_size (get_frame_size ())
4977 : current_frame_info.total_size;
4979 /* MIPS16 frame is smaller */
4980 if (frame_pointer_needed && TARGET_MIPS16)
4981 frame_size -= current_function_outgoing_args_size;
4983 offset = offset - frame_size;
4986 /* sdbout_parms does not want this to crash for unrecognized cases. */
4988 else if (reg != arg_pointer_rtx)
4989 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
4995 /* A C compound statement to output to stdio stream STREAM the
4996 assembler syntax for an instruction operand X. X is an RTL
4999 CODE is a value that can be used to specify one of several ways
5000 of printing the operand. It is used when identical operands
5001 must be printed differently depending on the context. CODE
5002 comes from the `%' specification that was used to request
5003 printing of the operand. If the specification was just `%DIGIT'
5004 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5005 is the ASCII code for LTR.
5007 If X is a register, this macro should print the register's name.
5008 The names can be found in an array `reg_names' whose type is
5009 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5011 When the machine description has a specification `%PUNCT' (a `%'
5012 followed by a punctuation character), this macro is called with
5013 a null pointer for X and the punctuation character for CODE.
5015 The MIPS specific codes are:
5017 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5018 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5019 'd' output integer constant in decimal,
5020 'z' if the operand is 0, use $0 instead of normal operand.
5021 'D' print second register of double-word register operand.
5022 'L' print low-order register of double-word register operand.
5023 'M' print high-order register of double-word register operand.
5024 'C' print part of opcode for a branch condition.
5025 'F' print part of opcode for a floating-point branch condition.
5026 'N' print part of opcode for a branch condition, inverted.
5027 'W' print part of opcode for a floating-point branch condition, inverted.
5028 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5029 'B' print 'z' for EQ, 'n' for NE
5030 'b' print 'n' for EQ, 'z' for NE
5031 'T' print 'f' for EQ, 't' for NE
5032 't' print 't' for EQ, 'f' for NE
5033 'Z' print register and a comma, but print nothing for $fcc0
5034 '(' Turn on .set noreorder
5035 ')' Turn on .set reorder
5036 '[' Turn on .set noat
5038 '<' Turn on .set nomacro
5039 '>' Turn on .set macro
5040 '{' Turn on .set volatile (not GAS)
5041 '}' Turn on .set novolatile (not GAS)
5042 '&' Turn on .set noreorder if filling delay slots
5043 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5044 '!' Turn on .set nomacro if filling delay slots
5045 '#' Print nop if in a .set noreorder section.
5046 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5047 '@' Print the name of the assembler temporary register (at or $1).
5048 '.' Print the name of the register with a hard-wired zero (zero or $0).
5049 '^' Print the name of the pic call-through register (t9 or $25).
5050 '$' Print the name of the stack pointer register (sp or $29).
5051 '+' Print the name of the gp register (gp or $28).
5052 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5055 print_operand (file, op, letter)
5056 FILE *file; /* file to write to */
5057 rtx op; /* operand to print */
5058 int letter; /* %<letter> or 0 */
5060 register enum rtx_code code;
5062 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5067 if (mips_branch_likely)
5072 fputs (reg_names [GP_REG_FIRST + 1], file);
5076 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5080 fputs (reg_names [GP_REG_FIRST + 0], file);
5084 fputs (reg_names[STACK_POINTER_REGNUM], file);
5088 fputs (reg_names[GP_REG_FIRST + 28], file);
5092 if (final_sequence != 0 && set_noreorder++ == 0)
5093 fputs (".set\tnoreorder\n\t", file);
5097 if (final_sequence != 0)
5099 if (set_noreorder++ == 0)
5100 fputs (".set\tnoreorder\n\t", file);
5102 if (set_nomacro++ == 0)
5103 fputs (".set\tnomacro\n\t", file);
5108 if (final_sequence != 0 && set_nomacro++ == 0)
5109 fputs ("\n\t.set\tnomacro", file);
5113 if (set_noreorder != 0)
5114 fputs ("\n\tnop", file);
5115 else if (TARGET_STATS)
5116 fputs ("\n\t#nop", file);
5121 if (set_noreorder++ == 0)
5122 fputs (".set\tnoreorder\n\t", file);
5126 if (set_noreorder == 0)
5127 error ("internal error: %%) found without a %%( in assembler pattern");
5129 else if (--set_noreorder == 0)
5130 fputs ("\n\t.set\treorder", file);
5135 if (set_noat++ == 0)
5136 fputs (".set\tnoat\n\t", file);
5141 error ("internal error: %%] found without a %%[ in assembler pattern");
5142 else if (--set_noat == 0)
5143 fputs ("\n\t.set\tat", file);
5148 if (set_nomacro++ == 0)
5149 fputs (".set\tnomacro\n\t", file);
5153 if (set_nomacro == 0)
5154 error ("internal error: %%> found without a %%< in assembler pattern");
5155 else if (--set_nomacro == 0)
5156 fputs ("\n\t.set\tmacro", file);
5161 if (set_volatile++ == 0)
5162 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5166 if (set_volatile == 0)
5167 error ("internal error: %%} found without a %%{ in assembler pattern");
5168 else if (--set_volatile == 0)
5169 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5175 if (align_labels_log > 0)
5176 ASM_OUTPUT_ALIGN (file, align_labels_log);
5181 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
5190 error ("PRINT_OPERAND null pointer");
5194 code = GET_CODE (op);
5196 if (code == SIGN_EXTEND)
5197 op = XEXP (op, 0), code = GET_CODE (op);
5202 case EQ: fputs ("eq", file); break;
5203 case NE: fputs ("ne", file); break;
5204 case GT: fputs ("gt", file); break;
5205 case GE: fputs ("ge", file); break;
5206 case LT: fputs ("lt", file); break;
5207 case LE: fputs ("le", file); break;
5208 case GTU: fputs ("gtu", file); break;
5209 case GEU: fputs ("geu", file); break;
5210 case LTU: fputs ("ltu", file); break;
5211 case LEU: fputs ("leu", file); break;
5213 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5216 else if (letter == 'N')
5219 case EQ: fputs ("ne", file); break;
5220 case NE: fputs ("eq", file); break;
5221 case GT: fputs ("le", file); break;
5222 case GE: fputs ("lt", file); break;
5223 case LT: fputs ("ge", file); break;
5224 case LE: fputs ("gt", file); break;
5225 case GTU: fputs ("leu", file); break;
5226 case GEU: fputs ("ltu", file); break;
5227 case LTU: fputs ("geu", file); break;
5228 case LEU: fputs ("gtu", file); break;
5230 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5233 else if (letter == 'F')
5236 case EQ: fputs ("c1f", file); break;
5237 case NE: fputs ("c1t", file); break;
5239 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5242 else if (letter == 'W')
5245 case EQ: fputs ("c1t", file); break;
5246 case NE: fputs ("c1f", file); break;
5248 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5251 else if (letter == 'S')
5255 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5256 assemble_name (file, buffer);
5259 else if (letter == 'Z')
5261 register int regnum;
5266 regnum = REGNO (op);
5267 if (! ST_REG_P (regnum))
5270 if (regnum != ST_REG_FIRST)
5271 fprintf (file, "%s,", reg_names[regnum]);
5274 else if (code == REG || code == SUBREG)
5276 register int regnum;
5279 regnum = REGNO (op);
5281 regnum = true_regnum (op);
5283 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5284 || (letter == 'L' && WORDS_BIG_ENDIAN)
5288 fprintf (file, "%s", reg_names[regnum]);
5291 else if (code == MEM)
5292 output_address (XEXP (op, 0));
5294 else if (code == CONST_DOUBLE
5295 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5300 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5301 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5305 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5306 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5308 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5309 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5311 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5312 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5314 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5315 fputs (reg_names[GP_REG_FIRST], file);
5317 else if (letter == 'd' || letter == 'x' || letter == 'X')
5318 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
5321 else if (letter == 'B')
5322 fputs (code == EQ ? "z" : "n", file);
5323 else if (letter == 'b')
5324 fputs (code == EQ ? "n" : "z", file);
5325 else if (letter == 'T')
5326 fputs (code == EQ ? "f" : "t", file);
5327 else if (letter == 't')
5328 fputs (code == EQ ? "t" : "f", file);
5330 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5332 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5333 print_operand (file, XEXP (op, 0), letter);
5336 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5338 fputs ("%gprel(", file);
5339 mips16_output_gp_offset (file, op);
5344 output_addr_const (file, op);
5347 /* A C compound statement to output to stdio stream STREAM the
5348 assembler syntax for an instruction operand that is a memory
5349 reference whose address is ADDR. ADDR is an RTL expression.
5351 On some machines, the syntax for a symbolic address depends on
5352 the section that the address refers to. On these machines,
5353 define the macro `ENCODE_SECTION_INFO' to store the information
5354 into the `symbol_ref', and then check for it here. */
5357 print_operand_address (file, addr)
5362 error ("PRINT_OPERAND_ADDRESS, null pointer");
5365 switch (GET_CODE (addr))
5368 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5369 abort_with_insn (addr, "Arg pointer not eliminated.");
5371 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5376 register rtx arg0 = XEXP (addr, 0);
5377 register rtx arg1 = XEXP (addr, 1);
5379 if (! mips_split_addresses)
5380 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5382 if (GET_CODE (arg0) != REG)
5383 abort_with_insn (addr,
5384 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
5386 fprintf (file, "%%lo(");
5387 print_operand_address (file, arg1);
5388 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5394 register rtx reg = 0;
5395 register rtx offset = 0;
5396 register rtx arg0 = XEXP (addr, 0);
5397 register rtx arg1 = XEXP (addr, 1);
5399 if (GET_CODE (arg0) == REG)
5403 if (GET_CODE (offset) == REG)
5404 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5407 else if (GET_CODE (arg1) == REG)
5408 reg = arg1, offset = arg0;
5409 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5411 output_addr_const (file, addr);
5415 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5417 if (! CONSTANT_P (offset))
5418 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5420 if (REGNO (reg) == ARG_POINTER_REGNUM)
5421 abort_with_insn (addr, "Arg pointer not eliminated.");
5424 && GET_CODE (offset) == CONST
5425 && mips16_gp_offset_p (offset))
5427 fputs ("%gprel(", file);
5428 mips16_output_gp_offset (file, offset);
5432 output_addr_const (file, offset);
5433 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5441 output_addr_const (file, addr);
5445 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5451 /* If optimizing for the global pointer, keep track of all of the externs, so
5452 that at the end of the file, we can emit the appropriate .extern
5453 declaration for them, before writing out the text section. We assume all
5454 names passed to us are in the permanent obstack, so they will be valid at
5455 the end of the compilation.
5457 If we have -G 0, or the extern size is unknown, or the object is in a user
5458 specified section that is not .sbss/.sdata, don't bother emitting the
5459 .externs. In the case of user specified sections this behaviour is
5460 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5463 mips_output_external (file, decl, name)
5464 FILE *file ATTRIBUTE_UNUSED;
5468 register struct extern_list *p;
5473 && TREE_CODE (decl) != FUNCTION_DECL
5474 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5475 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5476 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5477 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5479 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5480 p->next = extern_head;
5486 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5487 if (TREE_CODE (decl) == FUNCTION_DECL
5488 /* ??? Don't include alloca, since gcc will always expand it
5489 inline. If we don't do this, the C++ library fails to build. */
5490 && strcmp (name, "alloca")
5491 /* ??? Don't include __builtin_next_arg, because then gcc will not
5492 bootstrap under Irix 5.1. */
5493 && strcmp (name, "__builtin_next_arg"))
5495 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5496 p->next = extern_head;
5506 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5508 mips_output_external_libcall (file, name)
5512 register struct extern_list *p;
5514 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5515 p->next = extern_head;
5524 /* Compute a string to use as a temporary file name. */
5526 /* On MSDOS, write temp files in current dir
5527 because there's no place else we can expect to use. */
5530 #define P_tmpdir "./"
5535 mips_make_temp_file ()
5538 const char *base = getenv ("TMPDIR");
5544 if (access (P_tmpdir, R_OK | W_OK) == 0)
5548 if (access ("/usr/tmp", R_OK | W_OK) == 0)
5554 len = strlen (base);
5555 /* temp_filename is global, so we must use malloc, not alloca. */
5556 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
5557 strcpy (temp_filename, base);
5558 if (len > 0 && temp_filename[len-1] != '/')
5559 temp_filename[len++] = '/';
5561 strcpy (temp_filename + len, "ctXXXXXX");
5562 mktemp (temp_filename);
5564 stream = fopen (temp_filename, "w+");
5566 pfatal_with_name (temp_filename);
5569 /* In MSDOS, we cannot unlink the temporary file until we are finished using
5570 it. Otherwise, we delete it now, so that it will be gone even if the
5571 compiler happens to crash. */
5572 unlink (temp_filename);
5577 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5578 for .file's that start within a function. If we are smuggling stabs, try to
5579 put out a MIPS ECOFF file and a stab. */
5582 mips_output_filename (stream, name)
5586 static int first_time = 1;
5587 char ltext_label_name[100];
5593 current_function_file = name;
5594 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5595 /* This tells mips-tfile that stabs will follow. */
5596 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5597 fprintf (stream, "\t#@stabs\n");
5600 else if (write_symbols == DBX_DEBUG)
5602 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5603 fprintf (stream, "%s ", ASM_STABS_OP);
5604 output_quoted_string (stream, name);
5605 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5608 else if (name != current_function_file
5609 && strcmp (name, current_function_file) != 0)
5611 if (inside_function && !TARGET_GAS)
5613 if (!file_in_function_warning)
5615 file_in_function_warning = 1;
5616 ignore_line_number = 1;
5617 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5623 current_function_file = name;
5624 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5629 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5630 as well as a .loc, since it is possible that MIPS ECOFF might not be
5631 able to represent the location for inlines that come from a different
5635 mips_output_lineno (stream, line)
5639 if (write_symbols == DBX_DEBUG)
5642 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
5643 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5644 LOCAL_LABEL_PREFIX, sym_lineno);
5649 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5650 (ignore_line_number) ? "#" : "",
5651 num_source_filenames, line);
5653 LABEL_AFTER_LOC (stream);
5657 /* If defined, a C statement to be executed just prior to the output of
5658 assembler code for INSN, to modify the extracted operands so they will be
5661 Here the argument OPVEC is the vector containing the operands extracted
5662 from INSN, and NOPERANDS is the number of elements of the vector which
5663 contain meaningful data for this insn. The contents of this vector are
5664 what will be used to convert the insn template into assembler code, so you
5665 can change the assembler output by changing the contents of the vector.
5667 We use it to check if the current insn needs a nop in front of it because
5668 of load delays, and also to update the delay slot statistics. */
5670 /* ??? There is no real need for this function, because it never actually
5671 emits a NOP anymore. */
5674 final_prescan_insn (insn, opvec, noperands)
5676 rtx opvec[] ATTRIBUTE_UNUSED;
5677 int noperands ATTRIBUTE_UNUSED;
5679 if (dslots_number_nops > 0)
5681 rtx pattern = PATTERN (insn);
5682 int length = get_attr_length (insn);
5684 /* Do we need to emit a NOP? */
5686 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5687 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5688 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5689 || (mips_load_reg4 != 0
5690 && reg_mentioned_p (mips_load_reg4, pattern)))
5691 fputs ("\t#nop\n", asm_out_file);
5694 dslots_load_filled++;
5696 while (--dslots_number_nops > 0)
5697 fputs ("\t#nop\n", asm_out_file);
5706 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
5707 dslots_jump_total++;
5710 /* Output at beginning of assembler file.
5712 If we are optimizing to use the global pointer, create a temporary file to
5713 hold all of the text stuff, and write it out to the end. This is needed
5714 because the MIPS assembler is evidently one pass, and if it hasn't seen the
5715 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
5716 processed, it generates a two instruction sequence. */
5719 mips_asm_file_start (stream)
5722 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
5724 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5725 inside of a .set noreorder section jumps to a label outside of the .set
5726 noreorder section. Revision 2.20 just set nobopt silently rather than
5729 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5730 fprintf (stream, "\t.set\tnobopt\n");
5732 /* Generate the pseudo ops that System V.4 wants. */
5733 #ifndef ABICALLS_ASM_OP
5734 #define ABICALLS_ASM_OP ".abicalls"
5736 if (TARGET_ABICALLS)
5737 /* ??? but do not want this (or want pic0) if -non-shared? */
5738 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
5741 fprintf (stream, "\t.set\tmips16\n");
5743 /* Start a section, so that the first .popsection directive is guaranteed
5744 to have a previously defined section to pop back to. */
5745 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
5746 fprintf (stream, "\t.section\t.text\n");
5748 /* This code exists so that we can put all externs before all symbol
5749 references. This is necessary for the MIPS assembler's global pointer
5750 optimizations to work. */
5751 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5753 asm_out_data_file = stream;
5754 asm_out_text_file = mips_make_temp_file ();
5758 asm_out_data_file = asm_out_text_file = stream;
5760 if (flag_verbose_asm)
5761 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
5763 mips_section_threshold, mips_cpu_string, mips_isa);
5766 /* If we are optimizing the global pointer, emit the text section now and any
5767 small externs which did not have .comm, etc that are needed. Also, give a
5768 warning if the data area is more than 32K and -pic because 3 instructions
5769 are needed to reference the data pointers. */
5772 mips_asm_file_end (file)
5777 struct extern_list *p;
5782 HALF_PIC_FINISH (file);
5789 for (p = extern_head; p != 0; p = p->next)
5791 name_tree = get_identifier (p->name);
5793 /* Positively ensure only one .extern for any given symbol. */
5794 if (! TREE_ASM_WRITTEN (name_tree))
5796 TREE_ASM_WRITTEN (name_tree) = 1;
5797 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5799 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
5803 fputs ("\t.extern\t", file);
5804 assemble_name (file, p->name);
5805 fprintf (file, ", %d\n", p->size);
5811 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5813 fprintf (file, "\n\t.text\n");
5814 rewind (asm_out_text_file);
5815 if (ferror (asm_out_text_file))
5816 fatal_io_error (temp_filename);
5818 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
5819 if ((int) fwrite (buffer, 1, len, file) != len)
5820 pfatal_with_name (asm_file_name);
5823 pfatal_with_name (temp_filename);
5825 if (fclose (asm_out_text_file) != 0)
5826 pfatal_with_name (temp_filename);
5829 unlink (temp_filename);
5834 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
5835 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
5838 mips_declare_object (stream, name, init_string, final_string, size)
5841 const char *init_string;
5842 const char *final_string;
5845 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
5846 assemble_name (stream, name);
5847 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
5851 tree name_tree = get_identifier (name);
5852 TREE_ASM_WRITTEN (name_tree) = 1;
5856 /* Output a double precision value to the assembler. If both the
5857 host and target are IEEE, emit the values in hex. */
5860 mips_output_double (stream, value)
5862 REAL_VALUE_TYPE value;
5864 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
5866 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
5868 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
5869 value_long[0], value, value_long[1]);
5871 fprintf (stream, "\t.double\t%.20g\n", value);
5875 /* Output a single precision value to the assembler. If both the
5876 host and target are IEEE, emit the values in hex. */
5879 mips_output_float (stream, value)
5881 REAL_VALUE_TYPE value;
5883 #ifdef REAL_VALUE_TO_TARGET_SINGLE
5885 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
5887 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
5889 fprintf (stream, "\t.float\t%.12g\n", value);
5893 /* Return the bytes needed to compute the frame pointer from the current
5896 Mips stack frames look like:
5898 Before call After call
5899 +-----------------------+ +-----------------------+
5902 | caller's temps. | | caller's temps. |
5904 +-----------------------+ +-----------------------+
5906 | arguments on stack. | | arguments on stack. |
5908 +-----------------------+ +-----------------------+
5909 | 4 words to save | | 4 words to save |
5910 | arguments passed | | arguments passed |
5911 | in registers, even | | in registers, even |
5912 SP->| if not passed. | VFP->| if not passed. |
5913 +-----------------------+ +-----------------------+
5915 | fp register save |
5917 +-----------------------+
5919 | gp register save |
5921 +-----------------------+
5925 +-----------------------+
5927 | alloca allocations |
5929 +-----------------------+
5931 | GP save for V.4 abi |
5933 +-----------------------+
5935 | arguments on stack |
5937 +-----------------------+
5939 | arguments passed |
5940 | in registers, even |
5941 low SP->| if not passed. |
5942 memory +-----------------------+
5947 compute_frame_size (size)
5948 HOST_WIDE_INT size; /* # of var. bytes allocated */
5951 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
5952 HOST_WIDE_INT var_size; /* # bytes that variables take up */
5953 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
5954 HOST_WIDE_INT extra_size; /* # extra bytes */
5955 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
5956 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
5957 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
5958 long mask; /* mask of saved gp registers */
5959 long fmask; /* mask of saved fp registers */
5960 int fp_inc; /* 1 or 2 depending on the size of fp regs */
5961 long fp_bits; /* bitmask to use for each fp register */
5967 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
5968 var_size = MIPS_STACK_ALIGN (size);
5969 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
5971 /* The MIPS 3.0 linker does not like functions that dynamically
5972 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5973 looks like we are trying to create a second frame pointer to the
5974 function, so allocate some stack space to make it happy. */
5976 if (args_size == 0 && current_function_calls_alloca)
5977 args_size = 4 * UNITS_PER_WORD;
5979 total_size = var_size + args_size + extra_size;
5981 /* Calculate space needed for gp registers. */
5982 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5984 /* $18 is a special case on the mips16. It may be used to call
5985 a function which returns a floating point value, but it is
5986 marked in call_used_regs. $31 is also a special case. When
5987 not using -mentry, it will be used to copy a return value
5988 into the floating point registers if the return value is
5990 if (MUST_SAVE_REGISTER (regno)
5992 && regno == GP_REG_FIRST + 18
5993 && regs_ever_live[regno])
5995 && regno == GP_REG_FIRST + 31
5996 && mips16_hard_float
5998 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
5999 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6001 && (! TARGET_SINGLE_FLOAT
6002 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6005 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6006 mask |= 1L << (regno - GP_REG_FIRST);
6008 /* The entry and exit pseudo instructions can not save $17
6009 without also saving $16. */
6011 && regno == GP_REG_FIRST + 17
6012 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6014 gp_reg_size += UNITS_PER_WORD;
6020 /* Calculate space needed for fp registers. */
6021 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
6032 /* This loop must iterate over the same space as its companion in
6033 save_restore_regs. */
6034 for (regno = (FP_REG_LAST - fp_inc + 1);
6035 regno >= FP_REG_FIRST;
6038 if (regs_ever_live[regno] && !call_used_regs[regno])
6040 fp_reg_size += fp_inc * UNITS_PER_FPREG;
6041 fmask |= fp_bits << (regno - FP_REG_FIRST);
6045 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6046 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6048 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6049 for leaf routines (total_size == extra_size) to save the gp reg.
6050 The gp reg is callee saved in the 64 bit ABI, so all routines must
6051 save the gp reg. This is not a leaf routine if -p, because of the
6053 if (total_size == extra_size
6054 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6056 total_size = extra_size = 0;
6057 else if (TARGET_ABICALLS)
6059 /* Add the context-pointer to the saved registers. */
6060 gp_reg_size += UNITS_PER_WORD;
6061 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6062 total_size -= gp_reg_rounded;
6063 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6064 total_size += gp_reg_rounded;
6067 /* Add in space reserved on the stack by the callee for storing arguments
6068 passed in registers. */
6069 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6070 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6072 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6073 if (mips_entry && total_size > 0 && total_size < 32)
6076 /* Save other computed information. */
6077 current_frame_info.total_size = total_size;
6078 current_frame_info.var_size = var_size;
6079 current_frame_info.args_size = args_size;
6080 current_frame_info.extra_size = extra_size;
6081 current_frame_info.gp_reg_size = gp_reg_size;
6082 current_frame_info.fp_reg_size = fp_reg_size;
6083 current_frame_info.mask = mask;
6084 current_frame_info.fmask = fmask;
6085 current_frame_info.initialized = reload_completed;
6086 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6087 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
6091 unsigned long offset;
6093 /* When using mips_entry, the registers are always saved at the
6094 top of the stack. */
6096 offset = (args_size + extra_size + var_size
6097 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6099 offset = total_size - GET_MODE_SIZE (gpr_mode);
6101 current_frame_info.gp_sp_offset = offset;
6102 current_frame_info.gp_save_offset = offset - total_size;
6106 current_frame_info.gp_sp_offset = 0;
6107 current_frame_info.gp_save_offset = 0;
6112 unsigned long offset = (args_size + extra_size + var_size
6113 + gp_reg_rounded + fp_reg_size
6114 - fp_inc * UNITS_PER_FPREG);
6115 current_frame_info.fp_sp_offset = offset;
6116 current_frame_info.fp_save_offset = offset - total_size;
6120 current_frame_info.fp_sp_offset = 0;
6121 current_frame_info.fp_save_offset = 0;
6124 /* Ok, we're done. */
6128 /* Common code to emit the insns (or to write the instructions to a file)
6129 to save/restore registers.
6131 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6132 is not modified within save_restore_insns. */
6134 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6137 save_restore_insns (store_p, large_reg, large_offset, file)
6138 int store_p; /* true if this is prologue */
6139 rtx large_reg; /* register holding large offset constant or NULL */
6140 long large_offset; /* large constant offset value */
6141 FILE *file; /* file to write instructions instead of making RTL */
6143 long mask = current_frame_info.mask;
6144 long fmask = current_frame_info.fmask;
6147 HOST_WIDE_INT base_offset;
6148 HOST_WIDE_INT gp_offset;
6149 HOST_WIDE_INT fp_offset;
6150 HOST_WIDE_INT end_offset;
6153 if (frame_pointer_needed
6154 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6157 if (mask == 0 && fmask == 0)
6160 /* Save registers starting from high to low. The debuggers prefer at least
6161 the return register be stored at func+4, and also it allows us not to
6162 need a nop in the epilog if at least one register is reloaded in
6163 addition to return address. */
6165 /* Save GP registers if needed. */
6168 /* Pick which pointer to use as a base register. For small frames, just
6169 use the stack pointer. Otherwise, use a temporary register. Save 2
6170 cycles if the save area is near the end of a large frame, by reusing
6171 the constant created in the prologue/epilogue to adjust the stack
6174 gp_offset = current_frame_info.gp_sp_offset;
6176 = gp_offset - (current_frame_info.gp_reg_size
6177 - GET_MODE_SIZE (gpr_mode));
6179 if (gp_offset < 0 || end_offset < 0)
6180 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6181 (long) gp_offset, (long) end_offset);
6183 /* If we see a large frame in mips16 mode, we save the registers
6184 before adjusting the stack pointer, and load them afterward. */
6185 else if (TARGET_MIPS16 && large_offset > 32767)
6186 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6188 else if (gp_offset < 32768)
6189 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6191 else if (large_reg != 0
6192 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6193 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6195 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6196 base_offset = large_offset;
6199 if (Pmode == DImode)
6200 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6201 stack_pointer_rtx));
6203 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6204 stack_pointer_rtx));
6206 RTX_FRAME_RELATED_P (insn) = 1;
6209 fprintf (file, "\t%s\t%s,%s,%s\n",
6210 Pmode == DImode ? "daddu" : "addu",
6211 reg_names[MIPS_TEMP2_REGNUM],
6212 reg_names[REGNO (large_reg)],
6213 reg_names[STACK_POINTER_REGNUM]);
6218 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6219 base_offset = gp_offset;
6222 rtx gp_offset_rtx = GEN_INT (gp_offset);
6224 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6225 bit, so make sure that we don't emit anything that can be
6227 /* ??? There is no DImode ori immediate pattern, so we can only
6228 do this for 32 bit code. */
6229 if (large_int (gp_offset_rtx, GET_MODE (gp_offset_rtx))
6230 && GET_MODE (base_reg_rtx) == SImode)
6232 insn = emit_move_insn (base_reg_rtx,
6233 GEN_INT (gp_offset & 0xffff0000));
6235 RTX_FRAME_RELATED_P (insn) = 1;
6237 = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6238 GEN_INT (gp_offset & 0x0000ffff)));
6240 RTX_FRAME_RELATED_P (insn) = 1;
6244 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
6246 RTX_FRAME_RELATED_P (insn) = 1;
6249 if (Pmode == DImode)
6250 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6251 stack_pointer_rtx));
6253 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6254 stack_pointer_rtx));
6256 RTX_FRAME_RELATED_P (insn) = 1;
6260 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6261 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6262 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6263 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6264 Pmode == DImode ? "daddu" : "addu",
6265 reg_names[MIPS_TEMP2_REGNUM],
6266 reg_names[MIPS_TEMP2_REGNUM],
6267 reg_names[STACK_POINTER_REGNUM]);
6271 /* When we restore the registers in MIPS16 mode, then if we are
6272 using a frame pointer, and this is not a large frame, the
6273 current stack pointer will be offset by
6274 current_function_outgoing_args_size. Doing it this way lets
6275 us avoid offsetting the frame pointer before copying it into
6276 the stack pointer; there is no instruction to set the stack
6277 pointer to the sum of a register and a constant. */
6280 && frame_pointer_needed
6281 && large_offset <= 32767)
6282 base_offset += current_function_outgoing_args_size;
6284 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6285 if (BITSET_P (mask, regno - GP_REG_FIRST))
6291 = gen_rtx (MEM, gpr_mode,
6292 gen_rtx (PLUS, Pmode, base_reg_rtx,
6293 GEN_INT (gp_offset - base_offset)));
6295 RTX_UNCHANGING_P (mem_rtx) = 1;
6297 /* The mips16 does not have an instruction to load
6298 $31, so we load $7 instead, and work things out
6300 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6301 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6302 /* The mips16 sometimes needs to save $18. */
6303 else if (TARGET_MIPS16
6304 && regno != GP_REG_FIRST + 31
6305 && ! M16_REG_P (regno))
6308 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6311 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6312 emit_move_insn (reg_rtx,
6313 gen_rtx (REG, gpr_mode, regno));
6317 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6321 insn = emit_move_insn (mem_rtx, reg_rtx);
6322 RTX_FRAME_RELATED_P (insn) = 1;
6324 else if (!TARGET_ABICALLS
6325 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6326 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6328 emit_move_insn (reg_rtx, mem_rtx);
6330 && regno != GP_REG_FIRST + 31
6331 && ! M16_REG_P (regno))
6332 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6338 if (store_p || !TARGET_ABICALLS
6339 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6340 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6344 /* The mips16 does not have an instruction to
6345 load $31, so we load $7 instead, and work
6346 things out in the caller. */
6347 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6348 r = GP_REG_FIRST + 7;
6349 /* The mips16 sometimes needs to save $18. */
6351 && regno != GP_REG_FIRST + 31
6352 && ! M16_REG_P (regno))
6355 r = GP_REG_FIRST + 6;
6358 r = GP_REG_FIRST + 3;
6359 fprintf (file, "\tmove\t%s,%s\n",
6360 reg_names[r], reg_names[regno]);
6363 fprintf (file, "\t%s\t%s,",
6365 ? (store_p) ? "sd" : "ld"
6366 : (store_p) ? "sw" : "lw"),
6368 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6369 gp_offset - base_offset);
6370 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6373 && regno != GP_REG_FIRST + 31
6374 && ! M16_REG_P (regno))
6375 fprintf (file, "\tmove\t%s,%s\n",
6376 reg_names[regno], reg_names[r]);
6380 gp_offset -= GET_MODE_SIZE (gpr_mode);
6384 base_reg_rtx = 0, base_offset = 0;
6386 /* Save floating point registers if needed. */
6389 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
6390 int fp_size = fp_inc * UNITS_PER_FPREG;
6392 /* Pick which pointer to use as a base register. */
6393 fp_offset = current_frame_info.fp_sp_offset;
6394 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
6396 if (fp_offset < 0 || end_offset < 0)
6397 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6398 (long) fp_offset, (long) end_offset);
6400 else if (fp_offset < 32768)
6401 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6403 else if (base_reg_rtx != 0
6404 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6405 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6406 ; /* already set up for gp registers above */
6408 else if (large_reg != 0
6409 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6410 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6412 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6413 base_offset = large_offset;
6416 if (Pmode == DImode)
6417 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6418 stack_pointer_rtx));
6420 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6421 stack_pointer_rtx));
6423 RTX_FRAME_RELATED_P (insn) = 1;
6427 fprintf (file, "\t%s\t%s,%s,%s\n",
6428 Pmode == DImode ? "daddu" : "addu",
6429 reg_names[MIPS_TEMP2_REGNUM],
6430 reg_names[REGNO (large_reg)],
6431 reg_names[STACK_POINTER_REGNUM]);
6436 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6437 base_offset = fp_offset;
6440 rtx fp_offset_rtx = GEN_INT (fp_offset);
6442 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6443 bit, so make sure that we don't emit anything that can be
6445 /* ??? There is no DImode ori immediate pattern, so we can only
6446 do this for 32 bit code. */
6447 if (large_int (fp_offset_rtx, GET_MODE (fp_offset_rtx))
6448 && GET_MODE (base_reg_rtx) == SImode)
6450 insn = emit_move_insn (base_reg_rtx,
6451 GEN_INT (fp_offset & 0xffff0000));
6453 RTX_FRAME_RELATED_P (insn) = 1;
6454 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
6455 GEN_INT (fp_offset & 0x0000ffff)));
6457 RTX_FRAME_RELATED_P (insn) = 1;
6461 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
6463 RTX_FRAME_RELATED_P (insn) = 1;
6467 RTX_FRAME_RELATED_P (insn) = 1;
6468 if (Pmode == DImode)
6469 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6470 stack_pointer_rtx));
6472 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6473 stack_pointer_rtx));
6475 RTX_FRAME_RELATED_P (insn) = 1;
6479 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6480 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
6481 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6482 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6483 Pmode == DImode ? "daddu" : "addu",
6484 reg_names[MIPS_TEMP2_REGNUM],
6485 reg_names[MIPS_TEMP2_REGNUM],
6486 reg_names[STACK_POINTER_REGNUM]);
6490 /* This loop must iterate over the same space as its companion in
6491 compute_frame_size. */
6492 for (regno = (FP_REG_LAST - fp_inc + 1);
6493 regno >= FP_REG_FIRST;
6495 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6499 enum machine_mode sz
6500 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6501 rtx reg_rtx = gen_rtx (REG, sz, regno);
6502 rtx mem_rtx = gen_rtx (MEM, sz,
6503 gen_rtx (PLUS, Pmode, base_reg_rtx,
6506 RTX_UNCHANGING_P (mem_rtx) = 1;
6510 insn = emit_move_insn (mem_rtx, reg_rtx);
6511 RTX_FRAME_RELATED_P (insn) = 1;
6514 emit_move_insn (reg_rtx, mem_rtx);
6518 fprintf (file, "\t%s\t%s,",
6519 (TARGET_SINGLE_FLOAT
6520 ? (store_p ? "s.s" : "l.s")
6521 : (store_p ? "s.d" : "l.d")),
6523 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6524 fp_offset - base_offset);
6525 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6528 fp_offset -= fp_size;
6533 /* Set up the stack and frame (if desired) for the function. */
6536 function_prologue (file, size)
6538 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6540 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6543 long tsize = current_frame_info.total_size;
6545 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6547 #ifdef SDB_DEBUGGING_INFO
6548 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6549 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6552 /* In mips16 mode, we may need to generate a 32 bit to handle
6553 floating point arguments. The linker will arrange for any 32 bit
6554 functions to call this stub, which will then jump to the 16 bit
6556 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6557 && current_function_args_info.fp_code != 0)
6558 build_mips16_function_stub (file);
6560 inside_function = 1;
6562 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6563 /* Get the function name the same way that toplev.c does before calling
6564 assemble_start_function. This is needed so that the name used here
6565 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6566 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6568 if (!flag_inhibit_size_directive)
6570 fputs ("\t.ent\t", file);
6571 assemble_name (file, fnname);
6575 assemble_name (file, fnname);
6576 fputs (":\n", file);
6579 if (!flag_inhibit_size_directive)
6581 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6583 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6584 (reg_names[(frame_pointer_needed)
6585 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6586 ((frame_pointer_needed && TARGET_MIPS16)
6587 ? (tsize - current_function_outgoing_args_size)
6589 reg_names[31 + GP_REG_FIRST],
6590 current_frame_info.var_size,
6591 current_frame_info.num_gp,
6592 current_frame_info.num_fp,
6593 current_function_outgoing_args_size,
6594 current_frame_info.extra_size);
6596 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6597 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6598 current_frame_info.mask,
6599 current_frame_info.gp_save_offset,
6600 current_frame_info.fmask,
6601 current_frame_info.fp_save_offset);
6604 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6605 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6608 if (mips_entry && ! mips_can_use_return_insn ())
6610 int save16 = BITSET_P (current_frame_info.mask, 16);
6611 int save17 = BITSET_P (current_frame_info.mask, 17);
6612 int save31 = BITSET_P (current_frame_info.mask, 31);
6616 /* Look through the initial insns to see if any of them store
6617 the function parameters into the incoming parameter storage
6618 area. If they do, we delete the insn, and save the register
6619 using the entry pseudo-instruction instead. We don't try to
6620 look past a label, jump, or call. */
6621 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6623 rtx note, set, src, dest, base, offset;
6626 if (GET_CODE (insn) == CODE_LABEL
6627 || GET_CODE (insn) == JUMP_INSN
6628 || GET_CODE (insn) == CALL_INSN)
6630 if (GET_CODE (insn) != INSN)
6632 set = PATTERN (insn);
6633 if (GET_CODE (set) != SET)
6636 /* An insn storing a function parameter will still have a
6637 REG_EQUIV note on it mentioning the argument pointer. */
6638 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6639 if (note == NULL_RTX)
6641 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6644 src = SET_SRC (set);
6645 if (GET_CODE (src) != REG
6646 || REGNO (src) < GP_REG_FIRST + 4
6647 || REGNO (src) > GP_REG_FIRST + 7)
6650 dest = SET_DEST (set);
6651 if (GET_CODE (dest) != MEM)
6653 if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD)
6655 else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
6656 && REGNO (src) < GP_REG_FIRST + 7)
6660 offset = const0_rtx;
6661 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6662 if (GET_CODE (base) != REG
6663 || GET_CODE (offset) != CONST_INT)
6665 if (REGNO (base) == STACK_POINTER_REGNUM
6666 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6668 else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM
6671 + (REGNO (src) - 4) * UNITS_PER_WORD
6672 - current_function_outgoing_args_size)))
6677 /* This insn stores a parameter onto the stack, in the same
6678 location where the entry pseudo-instruction will put it.
6679 Delete the insn, and arrange to tell the entry
6680 instruction to save the register. */
6681 PUT_CODE (insn, NOTE);
6682 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6683 NOTE_SOURCE_FILE (insn) = 0;
6685 hireg = (REGNO (src)
6686 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6688 if (hireg > savearg)
6692 /* If this is a varargs function, we need to save all the
6693 registers onto the stack anyhow. */
6694 if (current_function_stdarg || current_function_varargs)
6695 savearg = GP_REG_FIRST + 7;
6697 fprintf (file, "\tentry\t");
6700 if (savearg == GP_REG_FIRST + 4)
6701 fprintf (file, "%s", reg_names[savearg]);
6703 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6704 reg_names[savearg]);
6706 if (save16 || save17)
6709 fprintf (file, ",");
6710 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6712 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6716 if (savearg > 0 || save16 || save17)
6717 fprintf (file, ",");
6718 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6720 fprintf (file, "\n");
6723 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
6725 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
6727 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6728 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
6731 fprintf (file, "\t%s\t%s,%s,%ld\n",
6732 (Pmode == DImode ? "dsubu" : "subu"),
6733 sp_str, sp_str, tsize);
6734 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
6737 if (dwarf2out_do_frame ())
6738 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
6742 /* Expand the prologue into a bunch of separate insns. */
6745 mips_expand_prologue ()
6748 HOST_WIDE_INT tsize;
6750 int last_arg_is_vararg_marker = 0;
6751 tree fndecl = current_function_decl;
6752 tree fntype = TREE_TYPE (fndecl);
6753 tree fnargs = DECL_ARGUMENTS (fndecl);
6758 CUMULATIVE_ARGS args_so_far;
6759 rtx reg_18_save = NULL_RTX;
6761 /* If struct value address is treated as the first argument, make it so. */
6762 if (aggregate_value_p (DECL_RESULT (fndecl))
6763 && ! current_function_returns_pcc_struct
6764 && struct_value_incoming_rtx == 0)
6766 tree type = build_pointer_type (fntype);
6767 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
6769 DECL_ARG_TYPE (function_result_decl) = type;
6770 TREE_CHAIN (function_result_decl) = fnargs;
6771 fnargs = function_result_decl;
6774 /* For arguments passed in registers, find the register number
6775 of the first argument in the variable part of the argument list,
6776 otherwise GP_ARG_LAST+1. Note also if the last argument is
6777 the varargs special argument, and treat it as part of the
6778 variable arguments. */
6780 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
6781 regno = GP_ARG_FIRST;
6783 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
6785 tree passed_type = DECL_ARG_TYPE (cur_arg);
6786 enum machine_mode passed_mode = TYPE_MODE (passed_type);
6789 if (TREE_ADDRESSABLE (passed_type))
6791 passed_type = build_pointer_type (passed_type);
6792 passed_mode = Pmode;
6795 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
6797 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
6798 next_arg = TREE_CHAIN (cur_arg);
6803 && DECL_NAME (cur_arg)
6804 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
6805 "__builtin_va_alist"))
6806 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
6809 last_arg_is_vararg_marker = 1;
6816 /* passed in a register, so will get homed automatically */
6817 if (GET_MODE (entry_parm) == BLKmode)
6818 words = (int_size_in_bytes (passed_type) + 3) / 4;
6820 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
6822 regno = REGNO (entry_parm) + words - 1;
6827 regno = GP_ARG_LAST+1;
6832 /* In order to pass small structures by value in registers compatibly with
6833 the MIPS compiler, we need to shift the value into the high part of the
6834 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
6835 adjustments to be made as the next_arg_reg variable, so we split up the
6836 insns, and emit them separately. */
6838 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
6839 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
6841 rtvec adjust = XVEC (next_arg_reg, 0);
6842 int num = GET_NUM_ELEM (adjust);
6844 for (i = 0; i < num; i++)
6846 rtx pattern = RTVEC_ELT (adjust, i);
6847 if (GET_CODE (pattern) != SET
6848 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
6849 abort_with_insn (pattern, "Insn is not a shift");
6851 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
6852 emit_insn (pattern);
6856 tsize = compute_frame_size (get_frame_size ());
6858 /* If this function is a varargs function, store any registers that
6859 would normally hold arguments ($4 - $7) on the stack. */
6860 if ((mips_abi == ABI_32 || mips_abi == ABI_O64)
6861 && (! mips_entry || mips_can_use_return_insn ())
6862 && ((TYPE_ARG_TYPES (fntype) != 0
6863 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6865 || last_arg_is_vararg_marker))
6867 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
6868 rtx ptr = stack_pointer_rtx;
6870 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
6871 if (TARGET_ABICALLS)
6874 for (; regno <= GP_ARG_LAST; regno++)
6877 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
6878 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
6879 gen_rtx (REG, gpr_mode, regno));
6881 offset += GET_MODE_SIZE (gpr_mode);
6885 /* If we are using the entry pseudo instruction, it will
6886 automatically subtract 32 from the stack pointer, so we don't
6887 need to. The entry pseudo instruction is emitted by
6888 function_prologue. */
6889 if (mips_entry && ! mips_can_use_return_insn ())
6891 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
6895 /* If we are using a frame pointer with a small stack frame,
6896 we need to initialize it here since it won't be done
6898 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6900 rtx incr = GEN_INT (current_function_outgoing_args_size);
6901 if (Pmode == DImode)
6902 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6906 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6910 else if (Pmode == DImode)
6911 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
6912 stack_pointer_rtx));
6914 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
6915 stack_pointer_rtx));
6917 RTX_FRAME_RELATED_P (insn) = 1;
6920 /* We may need to save $18, if it is used to call a function
6921 which may return a floating point value. Set up a sequence
6922 of instructions to do so. Later on we emit them at the right
6924 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
6926 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
6927 long gp_offset, base_offset;
6929 gp_offset = current_frame_info.gp_sp_offset;
6930 if (BITSET_P (current_frame_info.mask, 16))
6931 gp_offset -= UNITS_PER_WORD;
6932 if (BITSET_P (current_frame_info.mask, 17))
6933 gp_offset -= UNITS_PER_WORD;
6934 if (BITSET_P (current_frame_info.mask, 31))
6935 gp_offset -= UNITS_PER_WORD;
6937 base_offset = tsize;
6941 emit_move_insn (reg_rtx,
6942 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
6943 emit_move_insn (gen_rtx (MEM, gpr_mode,
6944 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
6948 reg_18_save = gen_sequence ();
6957 if (reg_18_save != NULL_RTX)
6958 emit_insn (reg_18_save);
6964 rtx tsize_rtx = GEN_INT (tsize);
6966 /* If we are doing svr4-abi, sp move is done by
6967 function_prologue. In mips16 mode with a large frame, we
6968 save the registers before adjusting the stack. */
6969 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
6970 && (!TARGET_MIPS16 || tsize <= 32767))
6976 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
6978 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6979 bit, so make sure that we don't emit anything that can be
6981 /* ??? There is no DImode ori immediate pattern, so we can only
6982 do this for 32 bit code. */
6983 if (large_int (tsize_rtx, GET_MODE (tsize_rtx))
6984 && GET_MODE (tmp_rtx) == SImode)
6986 insn = emit_move_insn (tmp_rtx,
6987 GEN_INT (tsize & 0xffff0000));
6988 RTX_FRAME_RELATED_P (insn) = 1;
6989 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
6990 GEN_INT (tsize & 0x0000ffff)));
6991 RTX_FRAME_RELATED_P (insn) = 1;
6995 insn = emit_move_insn (tmp_rtx, tsize_rtx);
6996 RTX_FRAME_RELATED_P (insn) = 1;
6999 tsize_rtx = tmp_rtx;
7002 if (Pmode == DImode)
7003 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7006 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7009 RTX_FRAME_RELATED_P (insn) = 1;
7013 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
7014 else if (reg_18_save != NULL_RTX)
7015 emit_insn (reg_18_save);
7017 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7023 if (!frame_pointer_needed)
7026 reg_rtx = gen_rtx (REG, Pmode, 3);
7027 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7028 emit_move_insn (reg_rtx, tsize_rtx);
7029 if (Pmode == DImode)
7030 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7031 hard_frame_pointer_rtx,
7034 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7035 hard_frame_pointer_rtx,
7037 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7040 if (frame_pointer_needed)
7044 /* On the mips16, we encourage the use of unextended
7045 instructions when using the frame pointer by pointing the
7046 frame pointer ahead of the argument space allocated on
7048 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7052 /* In this case, we have already copied the stack
7053 pointer into the frame pointer, above. We need only
7054 adjust for the outgoing argument size. */
7055 if (current_function_outgoing_args_size != 0)
7057 rtx incr = GEN_INT (current_function_outgoing_args_size);
7058 if (Pmode == DImode)
7059 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7060 hard_frame_pointer_rtx,
7063 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7064 hard_frame_pointer_rtx,
7068 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7070 rtx incr = GEN_INT (current_function_outgoing_args_size);
7071 if (Pmode == DImode)
7072 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7076 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7080 else if (Pmode == DImode)
7081 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7082 stack_pointer_rtx));
7084 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7085 stack_pointer_rtx));
7088 RTX_FRAME_RELATED_P (insn) = 1;
7091 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7092 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7093 gen_rtx_REG (DImode, 25)));
7096 /* If we are profiling, make sure no instructions are scheduled before
7097 the call to mcount. */
7099 if (profile_flag || profile_block_flag)
7100 emit_insn (gen_blockage ());
7103 /* Do any necessary cleanup after a function to restore stack, frame,
7106 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
7107 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7110 function_epilogue (file, size)
7111 FILE *file ATTRIBUTE_UNUSED;
7112 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7116 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7117 /* Get the function name the same way that toplev.c does before calling
7118 assemble_start_function. This is needed so that the name used here
7119 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7120 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7122 if (!flag_inhibit_size_directive)
7124 fputs ("\t.end\t", file);
7125 assemble_name (file, fnname);
7132 int num_gp_regs = current_frame_info.gp_reg_size / 4;
7133 int num_fp_regs = current_frame_info.fp_reg_size / 8;
7134 int num_regs = num_gp_regs + num_fp_regs;
7135 const char *name = fnname;
7140 dslots_load_total += num_regs;
7143 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7144 name, frame_pointer_needed ? 'y' : 'n',
7145 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7146 current_function_calls_alloca ? 'y' : 'n',
7147 current_function_calls_setjmp ? 'y' : 'n',
7148 current_frame_info.total_size,
7149 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7150 dslots_load_total, dslots_load_filled,
7151 dslots_jump_total, dslots_jump_filled,
7152 num_refs[0], num_refs[1], num_refs[2]);
7154 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7157 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7158 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7161 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7164 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7165 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7168 fputc ('\n', stderr);
7171 /* Reset state info for each function. */
7172 inside_function = 0;
7173 ignore_line_number = 0;
7174 dslots_load_total = 0;
7175 dslots_jump_total = 0;
7176 dslots_load_filled = 0;
7177 dslots_jump_filled = 0;
7183 current_frame_info = zero_frame_info;
7185 while (string_constants != NULL)
7187 struct string_constant *next;
7189 next = string_constants->next;
7190 free (string_constants);
7191 string_constants = next;
7194 /* Restore the output file if optimizing the GP (optimizing the GP causes
7195 the text to be diverted to a tempfile, so that data decls come before
7196 references to the data). */
7198 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
7199 asm_out_file = asm_out_data_file;
7202 /* Expand the epilogue into a bunch of separate insns. */
7205 mips_expand_epilogue ()
7207 HOST_WIDE_INT tsize = current_frame_info.total_size;
7208 rtx tsize_rtx = GEN_INT (tsize);
7209 rtx tmp_rtx = (rtx)0;
7211 if (mips_can_use_return_insn ())
7213 emit_insn (gen_return ());
7217 if (mips_entry && ! mips_can_use_return_insn ())
7220 if (tsize > 32767 && ! TARGET_MIPS16)
7222 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7223 emit_move_insn (tmp_rtx, tsize_rtx);
7224 tsize_rtx = tmp_rtx;
7229 long orig_tsize = tsize;
7231 if (frame_pointer_needed)
7233 emit_insn (gen_blockage ());
7235 /* On the mips16, the frame pointer is offset from the stack
7236 pointer by current_function_outgoing_args_size. We
7237 account for that by changing tsize. Note that this can
7238 actually make tsize negative. */
7241 tsize -= current_function_outgoing_args_size;
7243 /* If we have a large frame, it's easier to add to $17
7244 than to $sp, since the mips16 has no instruction to
7245 add a register to $sp. */
7246 if (orig_tsize > 32767)
7248 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7250 emit_move_insn (g6_rtx, GEN_INT (tsize));
7251 if (Pmode == DImode)
7252 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7253 hard_frame_pointer_rtx,
7256 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7257 hard_frame_pointer_rtx,
7262 if (tsize && tsize != orig_tsize)
7263 tsize_rtx = GEN_INT (tsize);
7266 if (Pmode == DImode)
7267 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7269 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7272 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7273 are going to restore it, then we must emit a blockage insn to
7274 prevent the scheduler from moving the restore out of the epilogue. */
7275 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7276 && (current_frame_info.mask
7277 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7278 emit_insn (gen_blockage ());
7280 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
7282 /* In mips16 mode with a large frame, we adjust the stack
7283 pointer before restoring the registers. In this case, we
7284 should always be using a frame pointer, so everything should
7285 have been handled above. */
7286 if (tsize > 32767 && TARGET_MIPS16)
7289 emit_insn (gen_blockage ());
7290 if (Pmode == DImode && tsize != 0)
7291 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7293 else if (tsize != 0)
7294 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7298 /* The mips16 loads the return address into $7, not $31. */
7299 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7300 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7301 GP_REG_FIRST + 7)));
7303 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7304 GP_REG_FIRST + 31)));
7307 /* Return nonzero if this function is known to have a null epilogue.
7308 This allows the optimizer to omit jumps to jumps if no stack
7312 mips_can_use_return_insn ()
7314 if (! reload_completed)
7317 if (regs_ever_live[31] || profile_flag)
7320 /* In mips16 mode, a function which returns a floating point value
7321 needs to arrange to copy the return value into the floating point
7324 && mips16_hard_float
7325 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7326 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7328 && (! TARGET_SINGLE_FLOAT
7329 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7333 if (current_frame_info.initialized)
7334 return current_frame_info.total_size == 0;
7336 return compute_frame_size (get_frame_size ()) == 0;
7339 /* Returns non-zero if X contains a SYMBOL_REF. */
7342 symbolic_expression_p (x)
7345 if (GET_CODE (x) == SYMBOL_REF)
7348 if (GET_CODE (x) == CONST)
7349 return symbolic_expression_p (XEXP (x, 0));
7351 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7352 return symbolic_expression_p (XEXP (x, 0));
7354 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7355 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7356 return (symbolic_expression_p (XEXP (x, 0))
7357 || symbolic_expression_p (XEXP (x, 1)));
7362 /* Choose the section to use for the constant rtx expression X that has
7366 mips_select_rtx_section (mode, x)
7367 enum machine_mode mode;
7368 rtx x ATTRIBUTE_UNUSED;
7372 /* In mips16 mode, the constant table always goes in the same section
7373 as the function, so that constants can be loaded using PC relative
7375 function_section (current_function_decl);
7377 else if (TARGET_EMBEDDED_DATA)
7379 /* For embedded applications, always put constants in read-only data,
7380 in order to reduce RAM usage. */
7381 READONLY_DATA_SECTION ();
7385 /* For hosted applications, always put constants in small data if
7386 possible, as this gives the best performance. */
7388 if (GET_MODE_SIZE (mode) <= mips_section_threshold
7389 && mips_section_threshold > 0)
7390 SMALL_DATA_SECTION ();
7391 else if (flag_pic && symbolic_expression_p (x))
7392 /* Any expression involving a SYMBOL_REF might need a run-time
7393 relocation. (The symbol might be defined in a shared
7394 library loaded at an unexpected base address.) So, we must
7395 put such expressions in the data segment (which is
7396 writable), rather than the text segment (which is
7400 READONLY_DATA_SECTION ();
7404 /* Choose the section to use for DECL. RELOC is true if its value contains
7405 any relocatable expression.
7407 Some of the logic used here needs to be replicated in
7408 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7409 are done correctly. Specifically, at least all symbols assigned
7410 here to rom (.text and/or .rodata) must not be referenced via
7411 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7413 If you need to make a change here, you probably should check
7414 ENCODE_SECTION_INFO to see if it needs a similar change. */
7417 mips_select_section (decl, reloc)
7421 int size = int_size_in_bytes (TREE_TYPE (decl));
7423 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7424 && TREE_CODE (decl) == STRING_CST
7425 && !flag_writable_strings)
7426 /* For embedded position independent code, put constant strings in the
7427 text section, because the data section is limited to 64K in size.
7428 For mips16 code, put strings in the text section so that a PC
7429 relative load instruction can be used to get their address. */
7431 else if (TARGET_EMBEDDED_DATA)
7433 /* For embedded applications, always put an object in read-only data
7434 if possible, in order to reduce RAM usage. */
7436 if (((TREE_CODE (decl) == VAR_DECL
7437 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7438 && DECL_INITIAL (decl)
7439 && (DECL_INITIAL (decl) == error_mark_node
7440 || TREE_CONSTANT (DECL_INITIAL (decl))))
7441 /* Deal with calls from output_constant_def_contents. */
7442 || (TREE_CODE (decl) != VAR_DECL
7443 && (TREE_CODE (decl) != STRING_CST
7444 || !flag_writable_strings)))
7445 && ! (flag_pic && reloc))
7446 READONLY_DATA_SECTION ();
7447 else if (size > 0 && size <= mips_section_threshold)
7448 SMALL_DATA_SECTION ();
7454 /* For hosted applications, always put an object in small data if
7455 possible, as this gives the best performance. */
7457 if (size > 0 && size <= mips_section_threshold)
7458 SMALL_DATA_SECTION ();
7459 else if (((TREE_CODE (decl) == VAR_DECL
7460 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7461 && DECL_INITIAL (decl)
7462 && (DECL_INITIAL (decl) == error_mark_node
7463 || TREE_CONSTANT (DECL_INITIAL (decl))))
7464 /* Deal with calls from output_constant_def_contents. */
7465 || (TREE_CODE (decl) != VAR_DECL
7466 && (TREE_CODE (decl) != STRING_CST
7467 || !flag_writable_strings)))
7468 && ! (flag_pic && reloc))
7469 READONLY_DATA_SECTION ();
7475 #ifdef MIPS_ABI_DEFAULT
7477 /* Support functions for the 64 bit ABI. */
7479 /* Return register to use for a function return value with VALTYPE for function
7483 mips_function_value (valtype, func)
7485 tree func ATTRIBUTE_UNUSED;
7487 int reg = GP_RETURN;
7488 enum machine_mode mode = TYPE_MODE (valtype);
7489 enum mode_class mclass = GET_MODE_CLASS (mode);
7490 int unsignedp = TREE_UNSIGNED (valtype);
7492 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7493 just as PROMOTE_MODE does. */
7494 mode = promote_mode (valtype, mode, &unsignedp, 1);
7496 /* ??? How should we return complex float? */
7497 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
7499 if (TARGET_SINGLE_FLOAT
7500 && (mclass == MODE_FLOAT
7501 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7507 else if (TREE_CODE (valtype) == RECORD_TYPE
7508 && mips_abi != ABI_32
7509 && mips_abi != ABI_O64
7510 && mips_abi != ABI_EABI)
7512 /* A struct with only one or two floating point fields is returned in
7513 the floating point registers. */
7514 tree field, fields[2];
7517 for (i = 0, field = TYPE_FIELDS (valtype); field;
7518 field = TREE_CHAIN (field))
7520 if (TREE_CODE (field) != FIELD_DECL)
7523 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7526 fields[i++] = field;
7529 /* Must check i, so that we reject structures with no elements. */
7534 /* The structure has DImode, but we don't allow DImode values
7535 in FP registers, so we use a PARALLEL even though it isn't
7536 strictly necessary. */
7537 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7539 return gen_rtx_PARALLEL
7542 gen_rtx_EXPR_LIST (VOIDmode,
7543 gen_rtx_REG (field_mode,
7550 enum machine_mode first_mode
7551 = TYPE_MODE (TREE_TYPE (fields[0]));
7552 enum machine_mode second_mode
7553 = TYPE_MODE (TREE_TYPE (fields[1]));
7554 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
7555 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
7557 return gen_rtx_PARALLEL
7560 gen_rtx_EXPR_LIST (VOIDmode,
7561 gen_rtx_REG (first_mode,
7563 GEN_INT (first_offset)),
7564 gen_rtx_EXPR_LIST (VOIDmode,
7565 gen_rtx_REG (second_mode,
7567 GEN_INT (second_offset))));
7572 return gen_rtx_REG (mode, reg);
7576 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7577 nonzero when an argument must be passed by reference. */
7580 function_arg_pass_by_reference (cum, mode, type, named)
7581 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
7582 enum machine_mode mode;
7584 int named ATTRIBUTE_UNUSED;
7588 /* We must pass by reference if we would be both passing in registers
7589 and the stack. This is because any subsequent partial arg would be
7590 handled incorrectly in this case.
7592 ??? This is really a kludge. We should either fix GCC so that such
7593 a situation causes an abort and then do something in the MIPS port
7594 to prevent it, or add code to function.c to properly handle the case. */
7595 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
7596 here hopefully is not relevant to mips_va_arg. */
7597 if (cum && MUST_PASS_IN_STACK (mode, type))
7599 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
7600 get double copies of any offsets generated for small structs
7601 passed in registers. */
7602 CUMULATIVE_ARGS temp = *cum;
7603 if (FUNCTION_ARG (temp, mode, type, named) != 0)
7608 /* Otherwise, we only do this if EABI is selected. */
7609 if (mips_abi != ABI_EABI)
7612 /* ??? How should SCmode be handled? */
7613 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7616 size = int_size_in_bytes (type);
7617 return size == -1 || size > UNITS_PER_WORD;
7620 /* This function returns the register class required for a secondary
7621 register when copying between one of the registers in CLASS, and X,
7622 using MODE. If IN_P is nonzero, the copy is going from X to the
7623 register, otherwise the register is the source. A return value of
7624 NO_REGS means that no secondary register is required. */
7627 mips_secondary_reload_class (class, mode, x, in_p)
7628 enum reg_class class;
7629 enum machine_mode mode;
7633 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7637 if (GET_CODE (x) == SIGN_EXTEND)
7643 /* We may be called with reg_renumber NULL from regclass.
7644 ??? This is probably a bug. */
7646 regno = true_regnum (x);
7649 while (GET_CODE (x) == SUBREG)
7651 off += SUBREG_WORD (x);
7655 if (GET_CODE (x) == REG)
7656 regno = REGNO (x) + off;
7660 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7661 regno = true_regnum (x);
7663 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7665 /* We always require a general register when copying anything to
7666 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7667 to a general register, or when copying from register 0. */
7668 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
7671 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7672 ? NO_REGS : gr_regs);
7673 else if (regno == HILO_REGNUM)
7676 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7677 ? NO_REGS : gr_regs);
7679 /* Copying from HI or LO to anywhere other than a general register
7680 requires a general register. */
7681 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7683 if (TARGET_MIPS16 && in_p)
7685 /* We can't really copy to HI or LO at all in mips16 mode. */
7688 return gp_reg_p ? NO_REGS : gr_regs;
7690 if (MD_REG_P (regno))
7692 if (TARGET_MIPS16 && ! in_p)
7694 /* We can't really copy to HI or LO at all in mips16 mode. */
7697 return class == gr_regs ? NO_REGS : gr_regs;
7700 /* We can only copy a value to a condition code register from a
7701 floating point register, and even then we require a scratch
7702 floating point register. We can only copy a value out of a
7703 condition code register into a general register. */
7704 if (class == ST_REGS)
7708 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
7710 if (ST_REG_P (regno))
7714 return class == GR_REGS ? NO_REGS : GR_REGS;
7717 /* In mips16 mode, going between memory and anything but M16_REGS
7718 requires an M16_REG. */
7721 if (class != M16_REGS && class != M16_NA_REGS)
7729 /* The stack pointer isn't a valid operand to an add instruction,
7730 so we need to load it into M16_REGS first. This can happen as
7731 a result of register elimination and form_sum converting
7732 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
7733 need an extra register if the dest is the same as the other
7734 register. In that case, we can't fix the problem by loading SP
7735 into the dest first. */
7736 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
7737 && GET_CODE (XEXP (x, 1)) == REG
7738 && (XEXP (x, 0) == stack_pointer_rtx
7739 || XEXP (x, 1) == stack_pointer_rtx))
7740 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
7742 if (class == M16_REGS || class == M16_NA_REGS)
7751 /* For each mips16 function which refers to GP relative symbols, we
7752 use a pseudo register, initialized at the start of the function, to
7753 hold the $gp value. */
7756 mips16_gp_pseudo_reg ()
7758 if (mips16_gp_pseudo_rtx == NULL_RTX)
7763 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7764 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
7766 /* We want to initialize this to a value which gcc will believe
7768 const_gp = gen_rtx (CONST, Pmode,
7769 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
7772 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
7773 insn = gen_sequence ();
7776 push_topmost_sequence ();
7777 /* We need to emit the initialization after the FUNCTION_BEG
7778 note, so that it will be integrated. */
7779 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7780 if (GET_CODE (scan) == NOTE
7781 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7783 if (scan == NULL_RTX)
7784 scan = get_insns ();
7785 insn = emit_insn_after (insn, scan);
7786 pop_topmost_sequence ();
7789 return mips16_gp_pseudo_rtx;
7792 /* Return an RTX which represents the signed 16 bit offset from the
7793 $gp register for the given symbol. This is only used on the
7797 mips16_gp_offset (sym)
7802 if (GET_CODE (sym) != SYMBOL_REF
7803 || ! SYMBOL_REF_FLAG (sym))
7806 /* We use a special identifier to represent the value of the gp
7808 gp = get_identifier ("__mips16_gp_value");
7810 return gen_rtx (CONST, Pmode,
7811 gen_rtx (MINUS, Pmode, sym,
7812 gen_rtx (SYMBOL_REF, Pmode,
7813 IDENTIFIER_POINTER (gp))));
7816 /* Return nonzero if the given RTX represents a signed 16 bit offset
7817 from the $gp register. */
7820 mips16_gp_offset_p (x)
7823 if (GET_CODE (x) == CONST)
7826 /* It's OK to add a small integer value to a gp offset. */
7827 if (GET_CODE (x) == PLUS)
7829 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7830 && SMALL_INT (XEXP (x, 1)))
7831 return mips16_gp_offset_p (XEXP (x, 0));
7832 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7833 && SMALL_INT (XEXP (x, 0)))
7834 return mips16_gp_offset_p (XEXP (x, 1));
7838 /* Make sure it is in the form SYM - __mips16_gp_value. */
7839 return (GET_CODE (x) == MINUS
7840 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
7841 && SYMBOL_REF_FLAG (XEXP (x, 0))
7842 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7843 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
7846 /* Output a GP offset. We don't want to print the subtraction of
7847 __mips16_gp_value; it is implicitly represented by the %gprel which
7848 should have been printed by the caller. */
7851 mips16_output_gp_offset (file, x)
7855 if (GET_CODE (x) == CONST)
7858 if (GET_CODE (x) == PLUS)
7860 mips16_output_gp_offset (file, XEXP (x, 0));
7862 mips16_output_gp_offset (file, XEXP (x, 1));
7866 if (GET_CODE (x) == MINUS
7867 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7868 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
7870 mips16_output_gp_offset (file, XEXP (x, 0));
7874 output_addr_const (file, x);
7877 /* Return nonzero if a constant should not be output until after the
7878 function. This is true of most string constants, so that we can
7879 use a more efficient PC relative reference. However, a static
7880 inline function may never call assemble_function_end to write out
7881 the constant pool, so don't try to postpone the constant in that
7884 ??? It's really a bug that a static inline function can put stuff
7885 in the constant pool even if the function itself is not output.
7887 We record which string constants we've seen, so that we know which
7888 ones might use the more efficient reference. */
7891 mips16_constant_after_function_p (x)
7894 if (TREE_CODE (x) == STRING_CST
7895 && ! flag_writable_strings
7896 && current_function_decl != 0
7897 && ! DECL_DEFER_OUTPUT (current_function_decl)
7898 && ! (DECL_INLINE (current_function_decl)
7899 && ((! TREE_PUBLIC (current_function_decl)
7900 && ! TREE_ADDRESSABLE (current_function_decl)
7901 && ! flag_keep_inline_functions)
7902 || DECL_EXTERNAL (current_function_decl))))
7904 struct string_constant *n;
7906 n = (struct string_constant *) xmalloc (sizeof *n);
7907 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
7908 n->next = string_constants;
7909 string_constants = n;
7917 /* Validate a constant for the mips16. This rejects general symbolic
7918 addresses, which must be loaded from memory. If ADDR is nonzero,
7919 this should reject anything which is not a legal address. If
7920 ADDEND is nonzero, this is being added to something else. */
7923 mips16_constant (x, mode, addr, addend)
7925 enum machine_mode mode;
7929 while (GET_CODE (x) == CONST)
7932 switch (GET_CODE (x))
7938 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
7939 && mips16_constant (XEXP (x, 1), mode, addr, 1));
7942 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7944 if (CONSTANT_POOL_ADDRESS_P (x))
7947 /* If we aren't looking for a memory address, we can accept a GP
7948 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
7949 knows how to handle this. We can always accept a string
7950 constant, which is the other case in which SYMBOL_REF_FLAG
7952 if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode)
7955 /* We can accept a string constant, which will have
7956 SYMBOL_REF_FLAG set but must be recognized by name to
7957 distinguish from a GP accessible symbol. The name of a
7958 string constant will have been generated by
7959 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
7960 if (SYMBOL_REF_FLAG (x))
7962 const char *name = XSTR (x, 0);
7964 return (name[0] == '*'
7965 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
7966 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
7972 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7977 if (addr && ! addend)
7979 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
7982 /* We need to treat $gp as a legitimate constant, because
7983 mips16_gp_pseudo_reg assumes that. */
7984 return REGNO (x) == GP_REG_FIRST + 28;
7988 /* Write out code to move floating point arguments in or out of
7989 general registers. Output the instructions to FILE. FP_CODE is
7990 the code describing which arguments are present (see the comment at
7991 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
7992 we are copying from the floating point registers. */
7995 mips16_fp_args (file, fp_code, from_fp_p)
8004 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8005 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8012 gparg = GP_ARG_FIRST;
8013 fparg = FP_ARG_FIRST;
8014 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8018 if ((fparg & 1) != 0)
8020 fprintf (file, "\t%s\t%s,%s\n", s,
8021 reg_names[gparg], reg_names[fparg]);
8023 else if ((f & 3) == 2)
8026 fprintf (file, "\td%s\t%s,%s\n", s,
8027 reg_names[gparg], reg_names[fparg]);
8030 if ((fparg & 1) != 0)
8032 if (TARGET_BIG_ENDIAN)
8033 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8034 reg_names[gparg], reg_names[fparg + 1], s,
8035 reg_names[gparg + 1], reg_names[fparg]);
8037 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8038 reg_names[gparg], reg_names[fparg], s,
8039 reg_names[gparg + 1], reg_names[fparg + 1]);
8052 /* Build a mips16 function stub. This is used for functions which
8053 take aruments in the floating point registers. It is 32 bit code
8054 that moves the floating point args into the general registers, and
8055 then jumps to the 16 bit code. */
8058 build_mips16_function_stub (file)
8062 char *secname, *stubname;
8063 tree stubid, stubdecl;
8067 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8068 secname = (char *) alloca (strlen (fnname) + 20);
8069 sprintf (secname, ".mips16.fn.%s", fnname);
8070 stubname = (char *) alloca (strlen (fnname) + 20);
8071 sprintf (stubname, "__fn_stub_%s", fnname);
8072 stubid = get_identifier (stubname);
8073 stubdecl = build_decl (FUNCTION_DECL, stubid,
8074 build_function_type (void_type_node, NULL_TREE));
8075 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8077 fprintf (file, "\t# Stub function for %s (", current_function_name);
8079 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8081 fprintf (file, "%s%s",
8082 need_comma ? ", " : "",
8083 (f & 3) == 1 ? "float" : "double");
8086 fprintf (file, ")\n");
8088 fprintf (file, "\t.set\tnomips16\n");
8089 function_section (stubdecl);
8090 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8092 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8093 within a .ent, and we can not emit another .ent. */
8094 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8095 fputs ("\t.ent\t", file);
8096 assemble_name (file, stubname);
8100 assemble_name (file, stubname);
8101 fputs (":\n", file);
8103 /* We don't want the assembler to insert any nops here. */
8104 fprintf (file, "\t.set\tnoreorder\n");
8106 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8108 fprintf (asm_out_file, "\t.set\tnoat\n");
8109 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8110 assemble_name (file, fnname);
8111 fprintf (file, "\n");
8112 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8113 fprintf (asm_out_file, "\t.set\tat\n");
8115 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8116 with one of the mfc1 instructions, because the result is not
8117 available for one instruction, so if the very first instruction
8118 in the function refers to the register, it will see the wrong
8120 fprintf (file, "\tnop\n");
8122 fprintf (file, "\t.set\treorder\n");
8124 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8125 fputs ("\t.end\t", file);
8126 assemble_name (file, stubname);
8130 fprintf (file, "\t.set\tmips16\n");
8132 function_section (current_function_decl);
8135 /* We keep a list of functions for which we have already built stubs
8136 in build_mips16_call_stub. */
8140 struct mips16_stub *next;
8145 static struct mips16_stub *mips16_stubs;
8147 /* Build a call stub for a mips16 call. A stub is needed if we are
8148 passing any floating point values which should go into the floating
8149 point registers. If we are, and the call turns out to be to a 32
8150 bit function, the stub will be used to move the values into the
8151 floating point registers before calling the 32 bit function. The
8152 linker will magically adjust the function call to either the 16 bit
8153 function or the 32 bit stub, depending upon where the function call
8154 is actually defined.
8156 Similarly, we need a stub if the return value might come back in a
8157 floating point register.
8159 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8160 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8161 is the code built by function_arg. This function returns a nonzero
8162 value if it builds the call instruction itself. */
8165 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8174 char *secname, *stubname;
8175 struct mips16_stub *l;
8176 tree stubid, stubdecl;
8180 /* We don't need to do anything if we aren't in mips16 mode, or if
8181 we were invoked with the -msoft-float option. */
8182 if (! TARGET_MIPS16 || ! mips16_hard_float)
8185 /* Figure out whether the value might come back in a floating point
8187 fpret = (retval != 0
8188 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8189 && (! TARGET_SINGLE_FLOAT
8190 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8192 /* We don't need to do anything if there were no floating point
8193 arguments and the value will not be returned in a floating point
8195 if (fp_code == 0 && ! fpret)
8198 if (GET_CODE (fnmem) != MEM)
8200 fn = XEXP (fnmem, 0);
8202 /* We don't need to do anything if this is a call to a special
8203 mips16 support function. */
8204 if (GET_CODE (fn) == SYMBOL_REF
8205 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8208 /* This code will only work for o32 and o64 abis. The other ABI's
8209 require more sophisticated support. */
8210 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8213 /* We can only handle SFmode and DFmode floating point return
8215 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8218 /* If we're calling via a function pointer, then we must always call
8219 via a stub. There are magic stubs provided in libgcc.a for each
8220 of the required cases. Each of them expects the function address
8221 to arrive in register $2. */
8223 if (GET_CODE (fn) != SYMBOL_REF)
8227 rtx stub_fn, stub_mem, insn;
8229 /* ??? If this code is modified to support other ABI's, we need
8230 to handle PARALLEL return values here. */
8232 sprintf (buf, "__mips16_call_stub_%s%d",
8234 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8237 id = get_identifier (buf);
8238 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8239 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8241 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8243 if (retval == NULL_RTX)
8244 insn = gen_call_internal0 (stub_mem, arg_size,
8245 gen_rtx (REG, SImode,
8246 GP_REG_FIRST + 31));
8248 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8249 gen_rtx (REG, SImode,
8250 GP_REG_FIRST + 31));
8251 insn = emit_call_insn (insn);
8253 /* Put the register usage information on the CALL. */
8254 if (GET_CODE (insn) != CALL_INSN)
8256 CALL_INSN_FUNCTION_USAGE (insn) =
8257 gen_rtx (EXPR_LIST, VOIDmode,
8258 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8259 CALL_INSN_FUNCTION_USAGE (insn));
8261 /* If we are handling a floating point return value, we need to
8262 save $18 in the function prologue. Putting a note on the
8263 call will mean that regs_ever_live[$18] will be true if the
8264 call is not eliminated, and we can check that in the prologue
8267 CALL_INSN_FUNCTION_USAGE (insn) =
8268 gen_rtx (EXPR_LIST, VOIDmode,
8269 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8270 CALL_INSN_FUNCTION_USAGE (insn));
8272 /* Return 1 to tell the caller that we've generated the call
8277 /* We know the function we are going to call. If we have already
8278 built a stub, we don't need to do anything further. */
8280 fnname = XSTR (fn, 0);
8281 for (l = mips16_stubs; l != NULL; l = l->next)
8282 if (strcmp (l->name, fnname) == 0)
8287 /* Build a special purpose stub. When the linker sees a
8288 function call in mips16 code, it will check where the target
8289 is defined. If the target is a 32 bit call, the linker will
8290 search for the section defined here. It can tell which
8291 symbol this section is associated with by looking at the
8292 relocation information (the name is unreliable, since this
8293 might be a static function). If such a section is found, the
8294 linker will redirect the call to the start of the magic
8297 If the function does not return a floating point value, the
8298 special stub section is named
8301 If the function does return a floating point value, the stub
8303 .mips16.call.fp.FNNAME
8306 secname = (char *) alloca (strlen (fnname) + 40);
8307 sprintf (secname, ".mips16.call.%s%s",
8310 stubname = (char *) alloca (strlen (fnname) + 20);
8311 sprintf (stubname, "__call_stub_%s%s",
8314 stubid = get_identifier (stubname);
8315 stubdecl = build_decl (FUNCTION_DECL, stubid,
8316 build_function_type (void_type_node, NULL_TREE));
8317 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8319 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8321 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8325 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8327 fprintf (asm_out_file, "%s%s",
8328 need_comma ? ", " : "",
8329 (f & 3) == 1 ? "float" : "double");
8332 fprintf (asm_out_file, ")\n");
8334 fprintf (asm_out_file, "\t.set\tnomips16\n");
8335 assemble_start_function (stubdecl, stubname);
8337 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8338 fputs ("\t.ent\t", asm_out_file);
8339 assemble_name (asm_out_file, stubname);
8340 fputs ("\n", asm_out_file);
8342 assemble_name (asm_out_file, stubname);
8343 fputs (":\n", asm_out_file);
8346 /* We build the stub code by hand. That's the only way we can
8347 do it, since we can't generate 32 bit code during a 16 bit
8350 /* We don't want the assembler to insert any nops here. */
8351 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8353 mips16_fp_args (asm_out_file, fp_code, 0);
8357 fprintf (asm_out_file, "\t.set\tnoat\n");
8358 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8360 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8361 fprintf (asm_out_file, "\t.set\tat\n");
8362 /* Unfortunately, we can't fill the jump delay slot. We
8363 can't fill with one of the mtc1 instructions, because the
8364 result is not available for one instruction, so if the
8365 very first instruction in the function refers to the
8366 register, it will see the wrong value. */
8367 fprintf (asm_out_file, "\tnop\n");
8371 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8372 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8373 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8374 /* As above, we can't fill the delay slot. */
8375 fprintf (asm_out_file, "\tnop\n");
8376 if (GET_MODE (retval) == SFmode)
8377 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8378 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8381 if (TARGET_BIG_ENDIAN)
8383 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8384 reg_names[GP_REG_FIRST + 2],
8385 reg_names[FP_REG_FIRST + 1]);
8386 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8387 reg_names[GP_REG_FIRST + 3],
8388 reg_names[FP_REG_FIRST + 0]);
8392 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8393 reg_names[GP_REG_FIRST + 2],
8394 reg_names[FP_REG_FIRST + 0]);
8395 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8396 reg_names[GP_REG_FIRST + 3],
8397 reg_names[FP_REG_FIRST + 1]);
8400 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8401 /* As above, we can't fill the delay slot. */
8402 fprintf (asm_out_file, "\tnop\n");
8405 fprintf (asm_out_file, "\t.set\treorder\n");
8407 #ifdef ASM_DECLARE_FUNCTION_SIZE
8408 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8411 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8412 fputs ("\t.end\t", asm_out_file);
8413 assemble_name (asm_out_file, stubname);
8414 fputs ("\n", asm_out_file);
8417 fprintf (asm_out_file, "\t.set\tmips16\n");
8419 /* Record this stub. */
8420 l = (struct mips16_stub *) xmalloc (sizeof *l);
8421 l->name = xstrdup (fnname);
8423 l->next = mips16_stubs;
8427 /* If we expect a floating point return value, but we've built a
8428 stub which does not expect one, then we're in trouble. We can't
8429 use the existing stub, because it won't handle the floating point
8430 value. We can't build a new stub, because the linker won't know
8431 which stub to use for the various calls in this object file.
8432 Fortunately, this case is illegal, since it means that a function
8433 was declared in two different ways in a single compilation. */
8434 if (fpret && ! l->fpret)
8435 error ("can not handle inconsistent calls to `%s'", fnname);
8437 /* If we are calling a stub which handles a floating point return
8438 value, we need to arrange to save $18 in the prologue. We do
8439 this by marking the function call as using the register. The
8440 prologue will later see that it is used, and emit code to save
8447 if (retval == NULL_RTX)
8448 insn = gen_call_internal0 (fnmem, arg_size,
8449 gen_rtx (REG, SImode,
8450 GP_REG_FIRST + 31));
8452 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8453 gen_rtx (REG, SImode,
8454 GP_REG_FIRST + 31));
8455 insn = emit_call_insn (insn);
8457 if (GET_CODE (insn) != CALL_INSN)
8460 CALL_INSN_FUNCTION_USAGE (insn) =
8461 gen_rtx (EXPR_LIST, VOIDmode,
8462 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8463 CALL_INSN_FUNCTION_USAGE (insn));
8465 /* Return 1 to tell the caller that we've generated the call
8470 /* Return 0 to let the caller generate the call insn. */
8474 /* This function looks through the code for a function, and tries to
8475 optimize the usage of the $gp register. We arrange to copy $gp
8476 into a pseudo-register, and then let gcc's normal reload handling
8477 deal with the pseudo-register. Unfortunately, if reload choose to
8478 put the pseudo-register into a call-clobbered register, it will
8479 emit saves and restores for that register around any function
8480 calls. We don't need the saves, and it's faster to copy $gp than
8481 to do an actual restore. ??? This still means that we waste a
8484 This is an optimization, and the code which gcc has actually
8485 generated is correct, so we do not need to catch all cases. */
8488 mips16_optimize_gp (first)
8491 rtx gpcopy, slot, insn;
8493 /* Look through the instructions. Set GPCOPY to the register which
8494 holds a copy of $gp. Set SLOT to the stack slot where it is
8495 saved. If we find an instruction which sets GPCOPY to anything
8496 other than $gp or SLOT, then we can't use it. If we find an
8497 instruction which sets SLOT to anything other than GPCOPY, we
8502 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8506 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8509 set = PATTERN (insn);
8511 /* We know that all references to memory will be inside a SET,
8512 because there is no other way to access memory on the mips16.
8513 We don't have to worry about a PARALLEL here, because the
8514 mips.md file will never generate them for memory references. */
8515 if (GET_CODE (set) != SET)
8518 if (gpcopy == NULL_RTX
8519 && GET_CODE (SET_SRC (set)) == CONST
8520 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8521 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8522 && GET_CODE (SET_DEST (set)) == REG
8523 && GET_MODE (SET_DEST (set)) == Pmode)
8524 gpcopy = SET_DEST (set);
8525 else if (slot == NULL_RTX
8526 && gpcopy != NULL_RTX
8527 && GET_CODE (SET_DEST (set)) == MEM
8528 && GET_CODE (SET_SRC (set)) == REG
8529 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8530 && GET_MODE (SET_DEST (set)) == Pmode)
8534 offset = const0_rtx;
8535 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8536 if (GET_CODE (base) == REG
8537 && (REGNO (base) == STACK_POINTER_REGNUM
8538 || REGNO (base) == FRAME_POINTER_REGNUM))
8539 slot = SET_DEST (set);
8541 else if (gpcopy != NULL_RTX
8542 && (GET_CODE (SET_DEST (set)) == REG
8543 || GET_CODE (SET_DEST (set)) == SUBREG)
8544 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8545 && (GET_CODE (SET_DEST (set)) != REG
8546 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8547 || GET_MODE (SET_DEST (set)) != Pmode
8548 || ((GET_CODE (SET_SRC (set)) != CONST
8549 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8550 || (REGNO (XEXP (SET_SRC (set), 0))
8551 != GP_REG_FIRST + 28))
8552 && ! rtx_equal_p (SET_SRC (set), slot))))
8554 else if (slot != NULL_RTX
8555 && GET_CODE (SET_DEST (set)) == MEM
8556 && rtx_equal_p (SET_DEST (set), slot)
8557 && (GET_CODE (SET_SRC (set)) != REG
8558 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8562 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8563 different optimization. Any time we find a copy of $28 into a
8564 register, followed by an add of a symbol_ref to that register, we
8565 convert it to load the value from the constant table instead.
8566 The copy and add will take six bytes, just as the load and
8567 constant table entry will take six bytes. However, it is
8568 possible that the constant table entry will be shared.
8570 This could be a peephole optimization, but I don't know if the
8571 peephole code can call force_const_mem.
8573 Using the same register for the copy of $28 and the add of the
8574 symbol_ref is actually pretty likely, since the add instruction
8575 requires the destination and the first addend to be the same
8578 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8582 /* This optimization is only reasonable if the constant table
8583 entries are only 4 bytes. */
8584 if (Pmode != SImode)
8587 for (insn = first; insn != NULL_RTX; insn = next)
8594 next = NEXT_INSN (next);
8596 while (next != NULL_RTX
8597 && (GET_CODE (next) == NOTE
8598 || (GET_CODE (next) == INSN
8599 && (GET_CODE (PATTERN (next)) == USE
8600 || GET_CODE (PATTERN (next)) == CLOBBER))));
8602 if (next == NULL_RTX)
8605 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8608 if (GET_RTX_CLASS (GET_CODE (next)) != 'i')
8611 set1 = PATTERN (insn);
8612 if (GET_CODE (set1) != SET)
8614 set2 = PATTERN (next);
8615 if (GET_CODE (set2) != SET)
8618 if (GET_CODE (SET_DEST (set1)) == REG
8619 && GET_CODE (SET_SRC (set1)) == CONST
8620 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8621 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8622 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8623 && GET_CODE (SET_SRC (set2)) == PLUS
8624 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8625 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8626 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8630 /* We've found a case we can change to load from the
8633 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8634 if (GET_CODE (sym) != SYMBOL_REF)
8636 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8637 force_const_mem (Pmode, sym)),
8640 PUT_CODE (insn, NOTE);
8641 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8642 NOTE_SOURCE_FILE (insn) = 0;
8644 PUT_CODE (next, NOTE);
8645 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8646 NOTE_SOURCE_FILE (next) = 0;
8653 /* We can safely remove all assignments to SLOT from GPCOPY, and
8654 replace all assignments from SLOT to GPCOPY with assignments from
8657 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8661 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8664 set = PATTERN (insn);
8665 if (GET_CODE (set) != SET
8666 || GET_MODE (SET_DEST (set)) != Pmode)
8669 if (GET_CODE (SET_DEST (set)) == MEM
8670 && rtx_equal_p (SET_DEST (set), slot)
8671 && GET_CODE (SET_SRC (set)) == REG
8672 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8674 PUT_CODE (insn, NOTE);
8675 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8676 NOTE_SOURCE_FILE (insn) = 0;
8678 else if (GET_CODE (SET_DEST (set)) == REG
8679 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8680 && GET_CODE (SET_SRC (set)) == MEM
8681 && rtx_equal_p (SET_SRC (set), slot))
8683 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
8684 gen_rtx (CONST, Pmode,
8685 gen_rtx (REG, Pmode,
8686 GP_REG_FIRST + 28))),
8688 PUT_CODE (insn, NOTE);
8689 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8690 NOTE_SOURCE_FILE (insn) = 0;
8695 /* We keep a list of constants we which we have to add to internal
8696 constant tables in the middle of large functions. */
8700 struct constant *next;
8703 enum machine_mode mode;
8706 /* Add a constant to the list in *PCONSTANTS. */
8709 add_constant (pconstants, val, mode)
8710 struct constant **pconstants;
8712 enum machine_mode mode;
8716 for (c = *pconstants; c != NULL; c = c->next)
8717 if (mode == c->mode && rtx_equal_p (val, c->value))
8720 c = (struct constant *) xmalloc (sizeof *c);
8723 c->label = gen_label_rtx ();
8724 c->next = *pconstants;
8729 /* Dump out the constants in CONSTANTS after INSN. */
8732 dump_constants (constants, insn)
8733 struct constant *constants;
8744 struct constant *next;
8746 switch (GET_MODE_SIZE (c->mode))
8753 insn = emit_insn_after (gen_align_2 (), insn);
8758 insn = emit_insn_after (gen_align_4 (), insn);
8763 insn = emit_insn_after (gen_align_8 (), insn);
8768 insn = emit_label_after (c->label, insn);
8773 r = gen_consttable_qi (c->value);
8776 r = gen_consttable_hi (c->value);
8779 r = gen_consttable_si (c->value);
8782 r = gen_consttable_sf (c->value);
8785 r = gen_consttable_di (c->value);
8788 r = gen_consttable_df (c->value);
8794 insn = emit_insn_after (r, insn);
8801 emit_barrier_after (insn);
8804 /* Find the symbol in an address expression. */
8807 mips_find_symbol (addr)
8810 if (GET_CODE (addr) == MEM)
8811 addr = XEXP (addr, 0);
8812 while (GET_CODE (addr) == CONST)
8813 addr = XEXP (addr, 0);
8814 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8816 if (GET_CODE (addr) == PLUS)
8820 l1 = mips_find_symbol (XEXP (addr, 0));
8821 l2 = mips_find_symbol (XEXP (addr, 1));
8822 if (l1 != NULL_RTX && l2 == NULL_RTX)
8824 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8830 /* Exported to toplev.c.
8832 Do a final pass over the function, just before delayed branch
8836 machine_dependent_reorg (first)
8839 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
8841 struct constant *constants;
8843 if (! TARGET_MIPS16)
8846 /* If $gp is used, try to remove stores, and replace loads with
8849 mips16_optimize_gp (first);
8851 /* Scan the function looking for PC relative loads which may be out
8852 of range. All such loads will either be from the constant table,
8853 or be getting the address of a constant string. If the size of
8854 the function plus the size of the constant table is less than
8855 0x8000, then all loads are in range. */
8858 for (insn = first; insn; insn = NEXT_INSN (insn))
8860 insns_len += get_attr_length (insn);
8862 /* ??? We put switch tables in .text, but we don't define
8863 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8864 compute their lengths correctly. */
8865 if (GET_CODE (insn) == JUMP_INSN)
8869 body = PATTERN (insn);
8870 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8871 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8872 * GET_MODE_SIZE (GET_MODE (body)));
8873 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8877 /* Store the original value of insns_len in current_frame_info, so
8878 that simple_memory_operand can look at it. */
8879 current_frame_info.insns_len = insns_len;
8881 pool_size = get_pool_size ();
8882 if (insns_len + pool_size + mips_string_length < 0x8000)
8885 /* Loop over the insns and figure out what the maximum internal pool
8887 max_internal_pool_size = 0;
8888 for (insn = first; insn; insn = NEXT_INSN (insn))
8890 if (GET_CODE (insn) == INSN
8891 && GET_CODE (PATTERN (insn)) == SET)
8895 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8896 if (src == NULL_RTX)
8898 if (CONSTANT_POOL_ADDRESS_P (src))
8899 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8900 else if (SYMBOL_REF_FLAG (src))
8901 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8907 first_constant_ref = -1;
8909 for (insn = first; insn; insn = NEXT_INSN (insn))
8911 if (GET_CODE (insn) == INSN
8912 && GET_CODE (PATTERN (insn)) == SET)
8915 enum machine_mode mode;
8918 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8919 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8921 /* ??? This is very conservative, which means that we
8922 will generate too many copies of the constant table.
8923 The only solution would seem to be some form of
8925 if (((insns_len - addr)
8926 + max_internal_pool_size
8927 + get_pool_offset (src))
8930 val = get_pool_constant (src);
8931 mode = get_pool_mode (src);
8933 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8935 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8937 /* Including all of mips_string_length is conservative,
8938 and so is including all of max_internal_pool_size. */
8939 if (((insns_len - addr)
8940 + max_internal_pool_size
8942 + mips_string_length)
8946 max_internal_pool_size -= Pmode;
8949 if (val != NULL_RTX)
8953 /* This PC relative load is out of range. ??? In the
8954 case of a string constant, we are only guessing that
8955 it is range, since we don't know the offset of a
8956 particular string constant. */
8958 lab = add_constant (&constants, val, mode);
8959 newsrc = gen_rtx (MEM, mode,
8960 gen_rtx (LABEL_REF, VOIDmode, lab));
8961 RTX_UNCHANGING_P (newsrc) = 1;
8962 PATTERN (insn) = gen_rtx (SET, VOIDmode,
8963 SET_DEST (PATTERN (insn)),
8965 INSN_CODE (insn) = -1;
8967 if (first_constant_ref < 0)
8968 first_constant_ref = addr;
8972 addr += get_attr_length (insn);
8974 /* ??? We put switch tables in .text, but we don't define
8975 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8976 compute their lengths correctly. */
8977 if (GET_CODE (insn) == JUMP_INSN)
8981 body = PATTERN (insn);
8982 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8983 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8984 * GET_MODE_SIZE (GET_MODE (body)));
8985 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8988 if (GET_CODE (insn) == BARRIER)
8990 /* Output any constants we have accumulated. Note that we
8991 don't need to change ADDR, since its only use is
8992 subtraction from INSNS_LEN, and both would be changed by
8994 ??? If the instructions up to the next barrier reuse a
8995 constant, it would often be better to continue
8997 if (constants != NULL)
8998 dump_constants (constants, insn);
9000 first_constant_ref = -1;
9003 if (constants != NULL
9004 && (NEXT_INSN (insn) == NULL
9005 || (first_constant_ref >= 0
9006 && (((addr - first_constant_ref)
9007 + 2 /* for alignment */
9008 + 2 /* for a short jump insn */
9012 /* If we haven't had a barrier within 0x8000 bytes of a
9013 constant reference or we are at the end of the function,
9014 emit a barrier now. */
9016 rtx label, jump, barrier;
9018 label = gen_label_rtx ();
9019 jump = emit_jump_insn_after (gen_jump (label), insn);
9020 JUMP_LABEL (jump) = label;
9021 LABEL_NUSES (label) = 1;
9022 barrier = emit_barrier_after (jump);
9023 emit_label_after (label, barrier);
9024 first_constant_ref = -1;
9028 /* ??? If we output all references to a constant in internal
9029 constants table, we don't need to output the constant in the real
9030 constant table, but we have no way to prevent that. */
9033 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9035 extend_operator (x, mode)
9037 enum machine_mode mode ATTRIBUTE_UNUSED;
9039 enum rtx_code code = GET_CODE (x);
9040 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9043 /* Accept any operator that can be used to shift the high half of the
9044 input value to the lower half, suitable for truncation. The
9045 remainder (the lower half of the input, and the upper half of the
9046 output) will be discarded. */
9048 highpart_shift_operator (x, mode)
9050 enum machine_mode mode ATTRIBUTE_UNUSED;
9052 enum rtx_code code = GET_CODE (x);
9053 return (code == LSHIFTRT
9059 /* Return the length of INSN. LENGTH is the initial length computed by
9060 attributes in the machine-description file. */
9063 mips_adjust_insn_length (insn, length)
9067 /* A unconditional jump has an unfilled delay slot if it is not part
9068 of a sequence. A conditional jump normally has a delay slot, but
9069 does not on MIPS16. */
9070 if (simplejump_p (insn)
9071 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9072 || GET_CODE (insn) == CALL_INSN)))
9075 /* All MIPS16 instructions are a measly two bytes. */
9082 /* Output assembly instructions to peform a conditional branch.
9084 INSN is the branch instruction. OPERANDS[0] is the condition.
9085 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9086 of the first operand to the condition. If TWO_OPERANDS_P is
9087 non-zero the comparison takes two operands; OPERANDS[3] will be the
9090 If INVERTED_P is non-zero we are to branch if the condition does
9091 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9093 LENGTH is the length (in bytes) of the sequence we are to generate.
9094 That tells us whether to generate a simple conditional branch, or a
9095 reversed conditional branch around a `jr' instruction. */
9097 mips_output_conditional_branch (insn,
9110 static char buffer[200];
9111 /* The kind of comparison we are doing. */
9112 enum rtx_code code = GET_CODE (operands[0]);
9113 /* Non-zero if the opcode for the comparison needs a `z' indicating
9114 that it is a comparision against zero. */
9116 /* A string to use in the assembly output to represent the first
9118 const char *op1 = "%z2";
9119 /* A string to use in the assembly output to represent the second
9120 operand. Use the hard-wired zero register if there's no second
9122 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9123 /* The operand-printing string for the comparison. */
9124 const char *comp = (float_p ? "%F0" : "%C0");
9125 /* The operand-printing string for the inverted comparison. */
9126 const char *inverted_comp = (float_p ? "%W0" : "%N0");
9128 /* The MIPS processors (for levels of the ISA at least two), have
9129 "likely" variants of each branch instruction. These instructions
9130 annul the instruction in the delay slot if the branch is not
9132 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9134 if (!two_operands_p)
9136 /* To compute whether than A > B, for example, we normally
9137 subtract B from A and then look at the sign bit. But, if we
9138 are doing an unsigned comparison, and B is zero, we don't
9139 have to do the subtraction. Instead, we can just check to
9140 see if A is non-zero. Thus, we change the CODE here to
9141 reflect the simpler comparison operation. */
9153 /* A condition which will always be true. */
9159 /* A condition which will always be false. */
9165 /* Not a special case. */
9170 /* Relative comparisons are always done against zero. But
9171 equality comparisons are done between two operands, and therefore
9172 do not require a `z' in the assembly language output. */
9173 need_z_p = (!float_p && code != EQ && code != NE);
9174 /* For comparisons against zero, the zero is not provided
9179 /* Begin by terminating the buffer. That way we can always use
9180 strcat to add to it. */
9187 /* Just a simple conditional branch. */
9189 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9190 inverted_p ? inverted_comp : comp);
9192 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9193 inverted_p ? inverted_comp : comp,
9194 need_z_p ? "z" : "",
9202 /* Generate a reversed conditional branch around ` j'
9214 Because we have to jump four bytes *past* the following
9215 instruction if this branch was annulled, we can't just use
9216 a label, as in the picture above; there's no way to put the
9217 label after the next instruction, as the assembler does not
9218 accept `.L+4' as the target of a branch. (We can't just
9219 wait until the next instruction is output; it might be a
9220 macro and take up more than four bytes. Once again, we see
9221 why we want to eliminate macros.)
9223 If the branch is annulled, we jump four more bytes that we
9224 would otherwise; that way we skip the annulled instruction
9225 in the delay slot. */
9228 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
9231 strcpy (buffer, "%(%<");
9232 c = strchr (buffer, '\0');
9233 /* Generate the reversed comparision. This takes four
9236 sprintf (c, "%%*b%s\t%%Z2%s",
9237 inverted_p ? comp : inverted_comp,
9240 sprintf (c, "%%*b%s%s\t%s%s,%s",
9241 inverted_p ? comp : inverted_comp,
9242 need_z_p ? "z" : "",
9246 strcat (c, "\n\tnop\n\tj\t%1");
9248 /* The delay slot was unfilled. Since we're inside
9249 .noreorder, the assembler will not fill in the NOP for
9250 us, so we must do it ourselves. */
9251 strcat (buffer, "\n\tnop");
9252 strcat (buffer, "%>%)");
9256 /* We do not currently use this code. It handles jumps to
9257 arbitrary locations, using `jr', even across a 256MB boundary.
9258 We could add a -mhuge switch, and then use this code instead of
9259 the `j' alternative above when -mhuge was used. */
9264 /* Generate a reversed conditional branch around a `jr'
9278 Not pretty, but allows a conditional branch anywhere in the
9279 32-bit address space. If the original branch is annulled,
9280 then the instruction in the delay slot should be executed
9281 only if the branch is taken. The la instruction is really
9282 a macro which will usually take eight bytes, but sometimes
9283 takes only four, if the instruction to which we're jumping
9284 gets its own entry in the global pointer table, which will
9285 happen if its a case label. The assembler will then
9286 generate only a four-byte sequence, rather than eight, and
9287 there seems to be no way to tell it not to. Thus, we can't
9288 just use a `.+x' addressing form; we don't know what value
9291 So, we resort to using the explicit relocation syntax
9292 available in the assembler and do:
9294 lw $at,%got_page(target)($gp)
9295 daddiu $at,$at,%got_ofst(target)
9297 That way, this always takes up eight bytes, and we can use
9298 the `.+x' form. Of course, these explicit machinations
9299 with relocation will not work with old assemblers. Then
9300 again, neither do out-of-range branches, so we haven't lost
9303 /* The target of the reversed branch. */
9305 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9306 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9307 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9310 strcpy (buffer, "%(%<%[");
9311 c = strchr (buffer, '\0');
9312 /* Generate the reversed comparision. This takes four
9315 sprintf (c, "%%*b%s\t%%Z2%s",
9316 inverted_p ? comp : inverted_comp,
9319 sprintf (c, "%%*b%s%s\t%s%s,%s",
9320 inverted_p ? comp : inverted_comp,
9321 need_z_p ? "z" : "",
9325 c = strchr (buffer, '\0');
9326 /* Generate the load-address, and jump. This takes twelve
9327 bytes, for a total of 16. */
9329 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9336 /* The delay slot was unfilled. Since we're inside
9337 .noreorder, the assembler will not fill in the NOP for
9338 us, so we must do it ourselves. */
9339 strcat (buffer, "\n\tnop");
9340 strcat (buffer, "%]%>%)");
9353 /* Called to register all of our global variables with the garbage
9357 mips_add_gc_roots ()
9359 ggc_add_rtx_root (&mips_load_reg, 1);
9360 ggc_add_rtx_root (&mips_load_reg2, 1);
9361 ggc_add_rtx_root (&mips_load_reg3, 1);
9362 ggc_add_rtx_root (&mips_load_reg4, 1);
9363 ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9364 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9365 ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);