1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
75 to initialize the mips16 gp pseudo register. */
76 #define CONST_GP_P(X) \
77 (GET_CODE (X) == CONST \
78 && GET_CODE (XEXP (X, 0)) == UNSPEC \
79 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
81 /* The maximum distance between the top of the stack frame and the
82 value $sp has when we save & restore registers.
84 Use a maximum gap of 0x100 in the mips16 case. We can then use
85 unextended instructions to save and restore registers, and to
86 allocate and deallocate the top part of the frame.
88 The value in the !mips16 case must be a SMALL_OPERAND and must
89 preserve the maximum stack alignment. It could really be 0x7ff0,
90 but SGI's assemblers implement daddiu $sp,$sp,-0x7ff0 as a
91 multi-instruction addu sequence. Use 0x7fe0 to work around this. */
92 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
94 /* True if INSN is a mips.md pattern or asm statement. */
95 #define USEFUL_INSN_P(INSN) \
97 && GET_CODE (PATTERN (INSN)) != USE \
98 && GET_CODE (PATTERN (INSN)) != CLOBBER \
99 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
100 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
102 /* If INSN is a delayed branch sequence, return the first instruction
103 in the sequence, otherwise return INSN itself. */
104 #define SEQ_BEGIN(INSN) \
105 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
106 ? XVECEXP (PATTERN (INSN), 0, 0) \
109 /* Likewise for the last instruction in a delayed branch sequence. */
110 #define SEQ_END(INSN) \
111 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
112 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
115 /* Execute the following loop body with SUBINSN set to each instruction
116 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
117 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
118 for ((SUBINSN) = SEQ_BEGIN (INSN); \
119 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
120 (SUBINSN) = NEXT_INSN (SUBINSN))
122 /* Classifies an address.
125 A natural register + offset address. The register satisfies
126 mips_valid_base_register_p and the offset is a const_arith_operand.
129 A LO_SUM rtx. The first operand is a valid base register and
130 the second operand is a symbolic address.
133 A signed 16-bit constant address.
136 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
137 enum mips_address_type {
144 /* A function to save or store a register. The first argument is the
145 register and the second is the stack slot. */
146 typedef void (*mips_save_restore_fn) (rtx, rtx);
148 struct mips16_constant;
149 struct mips_arg_info;
150 struct mips_address_info;
151 struct mips_integer_op;
154 static enum mips_symbol_type mips_classify_symbol (rtx);
155 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
156 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
157 static bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
158 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
159 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
160 static bool mips_classify_address (struct mips_address_info *, rtx,
161 enum machine_mode, int);
162 static int mips_symbol_insns (enum mips_symbol_type);
163 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
164 static rtx mips_force_temporary (rtx, rtx);
165 static rtx mips_split_symbol (rtx, rtx);
166 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
167 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
168 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
169 static unsigned int mips_build_lower (struct mips_integer_op *,
170 unsigned HOST_WIDE_INT);
171 static unsigned int mips_build_integer (struct mips_integer_op *,
172 unsigned HOST_WIDE_INT);
173 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
174 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
175 static int m16_check_op (rtx, int, int, int);
176 static bool mips_rtx_costs (rtx, int, int, int *);
177 static int mips_address_cost (rtx);
178 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
179 static void mips_load_call_address (rtx, rtx, int);
180 static bool mips_function_ok_for_sibcall (tree, tree);
181 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
182 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
183 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
184 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
185 tree, int, struct mips_arg_info *);
186 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
187 static void mips_set_architecture (const struct mips_cpu_info *);
188 static void mips_set_tune (const struct mips_cpu_info *);
189 static struct machine_function *mips_init_machine_status (void);
190 static void print_operand_reloc (FILE *, rtx, const char **);
191 static bool mips_assemble_integer (rtx, unsigned int, int);
192 static void mips_file_start (void);
193 static void mips_file_end (void);
194 static bool mips_rewrite_small_data_p (rtx);
195 static int small_data_pattern_1 (rtx *, void *);
196 static int mips_rewrite_small_data_1 (rtx *, void *);
197 static bool mips_function_has_gp_insn (void);
198 static unsigned int mips_global_pointer (void);
199 static bool mips_save_reg_p (unsigned int);
200 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
201 mips_save_restore_fn);
202 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
203 static void mips_output_cplocal (void);
204 static void mips_emit_loadgp (void);
205 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
206 static void mips_set_frame_expr (rtx);
207 static rtx mips_frame_set (rtx, rtx);
208 static void mips_save_reg (rtx, rtx);
209 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
210 static void mips_restore_reg (rtx, rtx);
211 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
212 HOST_WIDE_INT, tree);
213 static int symbolic_expression_p (rtx);
214 static void mips_select_rtx_section (enum machine_mode, rtx,
215 unsigned HOST_WIDE_INT);
216 static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
218 static bool mips_in_small_data_p (tree);
219 static int mips_fpr_return_fields (tree, tree *);
220 static bool mips_return_in_msb (tree);
221 static rtx mips_return_fpr_pair (enum machine_mode mode,
222 enum machine_mode mode1, HOST_WIDE_INT,
223 enum machine_mode mode2, HOST_WIDE_INT);
224 static rtx mips16_gp_pseudo_reg (void);
225 static void mips16_fp_args (FILE *, int, int);
226 static void build_mips16_function_stub (FILE *);
227 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
228 static void dump_constants (struct mips16_constant *, rtx);
229 static int mips16_insn_length (rtx);
230 static int mips16_rewrite_pool_refs (rtx *, void *);
231 static void mips16_lay_out_constants (void);
232 static void mips_sim_reset (struct mips_sim *);
233 static void mips_sim_init (struct mips_sim *, state_t);
234 static void mips_sim_next_cycle (struct mips_sim *);
235 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
236 static int mips_sim_wait_regs_2 (rtx *, void *);
237 static void mips_sim_wait_regs_1 (rtx *, void *);
238 static void mips_sim_wait_regs (struct mips_sim *, rtx);
239 static void mips_sim_wait_units (struct mips_sim *, rtx);
240 static void mips_sim_wait_insn (struct mips_sim *, rtx);
241 static void mips_sim_record_set (rtx, rtx, void *);
242 static void mips_sim_issue_insn (struct mips_sim *, rtx);
243 static void mips_sim_issue_nop (struct mips_sim *);
244 static void mips_sim_finish_insn (struct mips_sim *, rtx);
245 static void vr4130_avoid_branch_rt_conflict (rtx);
246 static void vr4130_align_insns (void);
247 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
248 static void mips_avoid_hazards (void);
249 static void mips_reorg (void);
250 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
251 static bool mips_matching_cpu_name_p (const char *, const char *);
252 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
253 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
254 static bool mips_return_in_memory (tree, tree);
255 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
256 static void mips_macc_chains_record (rtx);
257 static void mips_macc_chains_reorder (rtx *, int);
258 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
259 static bool vr4130_true_reg_dependence_p (rtx);
260 static bool vr4130_swap_insns_p (rtx, rtx);
261 static void vr4130_reorder (rtx *, int);
262 static void mips_promote_ready (rtx *, int, int);
263 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
264 static int mips_variable_issue (FILE *, int, rtx, int);
265 static int mips_adjust_cost (rtx, rtx, rtx, int);
266 static int mips_issue_rate (void);
267 static int mips_multipass_dfa_lookahead (void);
268 static void mips_init_libfuncs (void);
269 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
271 static tree mips_build_builtin_va_list (void);
272 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
273 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
277 static void irix_asm_named_section_1 (const char *, unsigned int,
279 static void irix_asm_named_section (const char *, unsigned int);
280 static int irix_section_align_entry_eq (const void *, const void *);
281 static hashval_t irix_section_align_entry_hash (const void *);
282 static void irix_file_start (void);
283 static int irix_section_align_1 (void **, void *);
284 static void copy_file_data (FILE *, FILE *);
285 static void irix_file_end (void);
286 static unsigned int irix_section_type_flags (tree, const char *, int);
289 /* Structure to be filled in by compute_frame_size with register
290 save masks, and offsets for the current function. */
292 struct mips_frame_info GTY(())
294 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
295 HOST_WIDE_INT var_size; /* # bytes that variables take up */
296 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
297 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
298 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
299 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
300 unsigned int mask; /* mask of saved gp registers */
301 unsigned int fmask; /* mask of saved fp registers */
302 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
303 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
304 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
305 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
306 bool initialized; /* true if frame size already calculated */
307 int num_gp; /* number of gp registers saved */
308 int num_fp; /* number of fp registers saved */
311 struct machine_function GTY(()) {
312 /* Pseudo-reg holding the value of $28 in a mips16 function which
313 refers to GP relative global variables. */
314 rtx mips16_gp_pseudo_rtx;
316 /* Current frame information, calculated by compute_frame_size. */
317 struct mips_frame_info frame;
319 /* The register to use as the global pointer within this function. */
320 unsigned int global_pointer;
322 /* True if mips_adjust_insn_length should ignore an instruction's
324 bool ignore_hazard_length_p;
326 /* True if the whole function is suitable for .set noreorder and
328 bool all_noreorder_p;
330 /* True if the function is known to have an instruction that needs $gp. */
334 /* Information about a single argument. */
337 /* True if the argument is passed in a floating-point register, or
338 would have been if we hadn't run out of registers. */
341 /* The argument's size, in bytes. */
342 unsigned int num_bytes;
344 /* The number of words passed in registers, rounded up. */
345 unsigned int reg_words;
347 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
348 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
350 unsigned int reg_offset;
352 /* The number of words that must be passed on the stack, rounded up. */
353 unsigned int stack_words;
355 /* The offset from the start of the stack overflow area of the argument's
356 first stack word. Only meaningful when STACK_WORDS is nonzero. */
357 unsigned int stack_offset;
361 /* Information about an address described by mips_address_type.
367 REG is the base register and OFFSET is the constant offset.
370 REG is the register that contains the high part of the address,
371 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
372 is the type of OFFSET's symbol.
375 SYMBOL_TYPE is the type of symbol being referenced. */
377 struct mips_address_info
379 enum mips_address_type type;
382 enum mips_symbol_type symbol_type;
386 /* One stage in a constant building sequence. These sequences have
390 A = A CODE[1] VALUE[1]
391 A = A CODE[2] VALUE[2]
394 where A is an accumulator, each CODE[i] is a binary rtl operation
395 and each VALUE[i] is a constant integer. */
396 struct mips_integer_op {
398 unsigned HOST_WIDE_INT value;
402 /* The largest number of operations needed to load an integer constant.
403 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
404 When the lowest bit is clear, we can try, but reject a sequence with
405 an extra SLL at the end. */
406 #define MIPS_MAX_INTEGER_OPS 7
409 /* Global variables for machine-dependent things. */
411 /* Threshold for data being put into the small data/bss area, instead
412 of the normal data area. */
413 int mips_section_threshold = -1;
415 /* Count the number of .file directives, so that .loc is up to date. */
416 int num_source_filenames = 0;
418 /* Count the number of sdb related labels are generated (to find block
419 start and end boundaries). */
420 int sdb_label_count = 0;
422 /* Next label # for each statement for Silicon Graphics IRIS systems. */
425 /* Linked list of all externals that are to be emitted when optimizing
426 for the global pointer if they haven't been declared by the end of
427 the program with an appropriate .comm or initialization. */
429 struct extern_list GTY (())
431 struct extern_list *next; /* next external */
432 const char *name; /* name of the external */
433 int size; /* size in bytes */
436 static GTY (()) struct extern_list *extern_head = 0;
438 /* Name of the file containing the current function. */
439 const char *current_function_file = "";
441 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
447 /* The next branch instruction is a branch likely, not branch normal. */
448 int mips_branch_likely;
450 /* The operands passed to the last cmpMM expander. */
453 /* The target cpu for code generation. */
454 enum processor_type mips_arch;
455 const struct mips_cpu_info *mips_arch_info;
457 /* The target cpu for optimization and scheduling. */
458 enum processor_type mips_tune;
459 const struct mips_cpu_info *mips_tune_info;
461 /* Which instruction set architecture to use. */
464 /* Which ABI to use. */
467 /* Strings to hold which cpu and instruction set architecture to use. */
468 const char *mips_arch_string; /* for -march=<xxx> */
469 const char *mips_tune_string; /* for -mtune=<xxx> */
470 const char *mips_isa_string; /* for -mips{1,2,3,4} */
471 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
473 /* Whether we are generating mips16 hard float code. In mips16 mode
474 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
475 -msoft-float was not specified by the user, which means that we
476 should arrange to call mips32 hard floating point code. */
477 int mips16_hard_float;
479 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
481 /* If TRUE, we split addresses into their high and low parts in the RTL. */
482 int mips_split_addresses;
484 /* Mode used for saving/restoring general purpose registers. */
485 static enum machine_mode gpr_mode;
487 /* Array giving truth value on whether or not a given hard register
488 can support a given mode. */
489 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
491 /* List of all MIPS punctuation characters used by print_operand. */
492 char mips_print_operand_punct[256];
494 /* Map GCC register number to debugger register number. */
495 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
497 /* A copy of the original flag_delayed_branch: see override_options. */
498 static int mips_flag_delayed_branch;
500 static GTY (()) int mips_output_filename_first_time = 1;
502 /* mips_split_p[X] is true if symbols of type X can be split by
503 mips_split_symbol(). */
504 static bool mips_split_p[NUM_SYMBOL_TYPES];
506 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
507 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
508 if they are matched by a special .md file pattern. */
509 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
511 /* Likewise for HIGHs. */
512 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
514 /* Map hard register number to register class */
515 const enum reg_class mips_regno_to_class[] =
517 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
518 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
519 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
520 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
521 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
522 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
523 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
524 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
525 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
526 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
527 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
528 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
529 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
530 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
531 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
532 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
533 HI_REG, LO_REG, NO_REGS, ST_REGS,
534 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
535 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
536 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
537 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
538 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
539 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
540 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
541 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
542 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
543 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
544 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
545 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
546 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
547 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
548 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
549 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
550 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
551 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
552 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
553 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
554 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
555 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
556 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
557 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
558 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
559 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
560 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
563 /* Map register constraint character to register class. */
564 enum reg_class mips_char_to_class[256];
566 /* A table describing all the processors gcc knows about. Names are
567 matched in the order listed. The first mention of an ISA level is
568 taken as the canonical name for that ISA.
570 To ease comparison, please keep this table in the same order as
571 gas's mips_cpu_info_table[]. */
572 const struct mips_cpu_info mips_cpu_info_table[] = {
573 /* Entries for generic ISAs */
574 { "mips1", PROCESSOR_R3000, 1 },
575 { "mips2", PROCESSOR_R6000, 2 },
576 { "mips3", PROCESSOR_R4000, 3 },
577 { "mips4", PROCESSOR_R8000, 4 },
578 { "mips32", PROCESSOR_4KC, 32 },
579 { "mips32r2", PROCESSOR_M4K, 33 },
580 { "mips64", PROCESSOR_5KC, 64 },
583 { "r3000", PROCESSOR_R3000, 1 },
584 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
585 { "r3900", PROCESSOR_R3900, 1 },
588 { "r6000", PROCESSOR_R6000, 2 },
591 { "r4000", PROCESSOR_R4000, 3 },
592 { "vr4100", PROCESSOR_R4100, 3 },
593 { "vr4111", PROCESSOR_R4111, 3 },
594 { "vr4120", PROCESSOR_R4120, 3 },
595 { "vr4130", PROCESSOR_R4130, 3 },
596 { "vr4300", PROCESSOR_R4300, 3 },
597 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
598 { "r4600", PROCESSOR_R4600, 3 },
599 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
600 { "r4650", PROCESSOR_R4650, 3 },
603 { "r8000", PROCESSOR_R8000, 4 },
604 { "vr5000", PROCESSOR_R5000, 4 },
605 { "vr5400", PROCESSOR_R5400, 4 },
606 { "vr5500", PROCESSOR_R5500, 4 },
607 { "rm7000", PROCESSOR_R7000, 4 },
608 { "rm9000", PROCESSOR_R9000, 4 },
611 { "4kc", PROCESSOR_4KC, 32 },
612 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
614 /* MIPS32 Release 2 */
615 { "m4k", PROCESSOR_M4K, 33 },
618 { "5kc", PROCESSOR_5KC, 64 },
619 { "20kc", PROCESSOR_20KC, 64 },
620 { "sb1", PROCESSOR_SB1, 64 },
621 { "sr71000", PROCESSOR_SR71000, 64 },
627 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
628 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
629 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
632 /* Initialize the GCC target structure. */
633 #undef TARGET_ASM_ALIGNED_HI_OP
634 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
635 #undef TARGET_ASM_ALIGNED_SI_OP
636 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
637 #undef TARGET_ASM_INTEGER
638 #define TARGET_ASM_INTEGER mips_assemble_integer
640 #undef TARGET_ASM_FUNCTION_PROLOGUE
641 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
642 #undef TARGET_ASM_FUNCTION_EPILOGUE
643 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
644 #undef TARGET_ASM_SELECT_RTX_SECTION
645 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
647 #undef TARGET_SCHED_REORDER
648 #define TARGET_SCHED_REORDER mips_sched_reorder
649 #undef TARGET_SCHED_VARIABLE_ISSUE
650 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
651 #undef TARGET_SCHED_ADJUST_COST
652 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
653 #undef TARGET_SCHED_ISSUE_RATE
654 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
655 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
656 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
657 mips_multipass_dfa_lookahead
659 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
660 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
662 #undef TARGET_VALID_POINTER_MODE
663 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
664 #undef TARGET_RTX_COSTS
665 #define TARGET_RTX_COSTS mips_rtx_costs
666 #undef TARGET_ADDRESS_COST
667 #define TARGET_ADDRESS_COST mips_address_cost
669 #undef TARGET_IN_SMALL_DATA_P
670 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
672 #undef TARGET_MACHINE_DEPENDENT_REORG
673 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
675 #undef TARGET_ASM_FILE_START
676 #undef TARGET_ASM_FILE_END
678 #define TARGET_ASM_FILE_START irix_file_start
679 #define TARGET_ASM_FILE_END irix_file_end
681 #define TARGET_ASM_FILE_START mips_file_start
682 #define TARGET_ASM_FILE_END mips_file_end
684 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
685 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
688 #undef TARGET_SECTION_TYPE_FLAGS
689 #define TARGET_SECTION_TYPE_FLAGS irix_section_type_flags
692 #undef TARGET_INIT_LIBFUNCS
693 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
695 #undef TARGET_BUILD_BUILTIN_VA_LIST
696 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
697 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
698 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
700 #undef TARGET_PROMOTE_FUNCTION_ARGS
701 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
702 #undef TARGET_PROMOTE_FUNCTION_RETURN
703 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
704 #undef TARGET_PROMOTE_PROTOTYPES
705 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
707 #undef TARGET_RETURN_IN_MEMORY
708 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
709 #undef TARGET_RETURN_IN_MSB
710 #define TARGET_RETURN_IN_MSB mips_return_in_msb
712 #undef TARGET_ASM_OUTPUT_MI_THUNK
713 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
714 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
715 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
717 #undef TARGET_SETUP_INCOMING_VARARGS
718 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
719 #undef TARGET_STRICT_ARGUMENT_NAMING
720 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
721 #undef TARGET_MUST_PASS_IN_STACK
722 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
723 #undef TARGET_PASS_BY_REFERENCE
724 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
726 struct gcc_target targetm = TARGET_INITIALIZER;
728 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
730 static enum mips_symbol_type
731 mips_classify_symbol (rtx x)
733 if (GET_CODE (x) == LABEL_REF)
736 return SYMBOL_CONSTANT_POOL;
738 return SYMBOL_GOT_LOCAL;
739 return SYMBOL_GENERAL;
742 if (GET_CODE (x) != SYMBOL_REF)
745 if (CONSTANT_POOL_ADDRESS_P (x))
748 return SYMBOL_CONSTANT_POOL;
751 return SYMBOL_GOT_LOCAL;
753 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
754 return SYMBOL_SMALL_DATA;
756 return SYMBOL_GENERAL;
759 if (SYMBOL_REF_SMALL_P (x))
760 return SYMBOL_SMALL_DATA;
764 if (SYMBOL_REF_DECL (x) == 0)
765 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
767 /* There are three cases to consider:
769 - o32 PIC (either with or without explicit relocs)
770 - n32/n64 PIC without explicit relocs
771 - n32/n64 PIC with explicit relocs
773 In the first case, both local and global accesses will use an
774 R_MIPS_GOT16 relocation. We must correctly predict which of
775 the two semantics (local or global) the assembler and linker
776 will apply. The choice doesn't depend on the symbol's
777 visibility, so we deliberately ignore decl_visibility and
780 In the second case, the assembler will not use R_MIPS_GOT16
781 relocations, but it chooses between local and global accesses
782 in the same way as for o32 PIC.
784 In the third case we have more freedom since both forms of
785 access will work for any kind of symbol. However, there seems
786 little point in doing things differently. */
787 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
788 return SYMBOL_GOT_GLOBAL;
790 return SYMBOL_GOT_LOCAL;
793 return SYMBOL_GENERAL;
797 /* Split X into a base and a constant offset, storing them in *BASE
798 and *OFFSET respectively. */
801 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
805 if (GET_CODE (x) == CONST)
808 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
810 *offset += INTVAL (XEXP (x, 1));
817 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
818 to the same object as SYMBOL. */
821 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
823 if (GET_CODE (symbol) != SYMBOL_REF)
826 if (CONSTANT_POOL_ADDRESS_P (symbol)
828 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
831 if (SYMBOL_REF_DECL (symbol) != 0
833 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
840 /* Return true if X is a symbolic constant that can be calculated in
841 the same way as a bare symbol. If it is, store the type of the
842 symbol in *SYMBOL_TYPE. */
845 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
847 HOST_WIDE_INT offset;
849 mips_split_const (x, &x, &offset);
850 if (UNSPEC_ADDRESS_P (x))
851 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
852 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
853 *symbol_type = mips_classify_symbol (x);
860 /* Check whether a nonzero offset is valid for the underlying
862 switch (*symbol_type)
868 /* If the target has 64-bit pointers and the object file only
869 supports 32-bit symbols, the values of those symbols will be
870 sign-extended. In this case we can't allow an arbitrary offset
871 in case the 32-bit value X + OFFSET has a different sign from X. */
872 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
873 return mips_offset_within_object_p (x, offset);
875 /* In other cases the relocations can handle any offset. */
878 case SYMBOL_CONSTANT_POOL:
879 /* Allow constant pool references to be converted to LABEL+CONSTANT.
880 In this case, we no longer have access to the underlying constant,
881 but the original symbol-based access was known to be valid. */
882 if (GET_CODE (x) == LABEL_REF)
887 case SYMBOL_SMALL_DATA:
888 /* Make sure that the offset refers to something within the
889 underlying object. This should guarantee that the final
890 PC- or GP-relative offset is within the 16-bit limit. */
891 return mips_offset_within_object_p (x, offset);
893 case SYMBOL_GOT_LOCAL:
894 case SYMBOL_GOTOFF_PAGE:
895 /* The linker should provide enough local GOT entries for a
896 16-bit offset. Larger offsets may lead to GOT overflow. */
897 return SMALL_OPERAND (offset);
899 case SYMBOL_GOT_GLOBAL:
900 case SYMBOL_GOTOFF_GLOBAL:
901 case SYMBOL_GOTOFF_CALL:
902 case SYMBOL_GOTOFF_LOADGP:
909 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
912 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
914 if (regno >= FIRST_PSEUDO_REGISTER)
918 regno = reg_renumber[regno];
921 /* These fake registers will be eliminated to either the stack or
922 hard frame pointer, both of which are usually valid base registers.
923 Reload deals with the cases where the eliminated form isn't valid. */
924 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
927 /* In mips16 mode, the stack pointer can only address word and doubleword
928 values, nothing smaller. There are two problems here:
930 (a) Instantiating virtual registers can introduce new uses of the
931 stack pointer. If these virtual registers are valid addresses,
932 the stack pointer should be too.
934 (b) Most uses of the stack pointer are not made explicit until
935 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
936 We don't know until that stage whether we'll be eliminating to the
937 stack pointer (which needs the restriction) or the hard frame
938 pointer (which doesn't).
940 All in all, it seems more consistent to only enforce this restriction
941 during and after reload. */
942 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
943 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
945 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
949 /* Return true if X is a valid base register for the given mode.
950 Allow only hard registers if STRICT. */
953 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
955 if (!strict && GET_CODE (x) == SUBREG)
958 return (GET_CODE (x) == REG
959 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
963 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
964 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
967 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
968 enum machine_mode mode)
973 return !TARGET_MIPS16;
975 case SYMBOL_SMALL_DATA:
978 case SYMBOL_CONSTANT_POOL:
979 /* PC-relative addressing is only available for lw and ld. */
980 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
982 case SYMBOL_GOT_LOCAL:
985 case SYMBOL_GOT_GLOBAL:
986 /* The address will have to be loaded from the GOT first. */
989 case SYMBOL_GOTOFF_PAGE:
990 case SYMBOL_GOTOFF_GLOBAL:
991 case SYMBOL_GOTOFF_CALL:
992 case SYMBOL_GOTOFF_LOADGP:
1002 /* Return true if X is a valid address for machine mode MODE. If it is,
1003 fill in INFO appropriately. STRICT is true if we should only accept
1004 hard base registers. */
1007 mips_classify_address (struct mips_address_info *info, rtx x,
1008 enum machine_mode mode, int strict)
1010 switch (GET_CODE (x))
1014 info->type = ADDRESS_REG;
1016 info->offset = const0_rtx;
1017 return mips_valid_base_register_p (info->reg, mode, strict);
1020 info->type = ADDRESS_REG;
1021 info->reg = XEXP (x, 0);
1022 info->offset = XEXP (x, 1);
1023 return (mips_valid_base_register_p (info->reg, mode, strict)
1024 && const_arith_operand (info->offset, VOIDmode));
1027 info->type = ADDRESS_LO_SUM;
1028 info->reg = XEXP (x, 0);
1029 info->offset = XEXP (x, 1);
1030 return (mips_valid_base_register_p (info->reg, mode, strict)
1031 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1032 && mips_symbolic_address_p (info->symbol_type, mode)
1033 && mips_lo_relocs[info->symbol_type] != 0);
1036 /* Small-integer addresses don't occur very often, but they
1037 are legitimate if $0 is a valid base register. */
1038 info->type = ADDRESS_CONST_INT;
1039 return !TARGET_MIPS16 && SMALL_INT (x);
1044 info->type = ADDRESS_SYMBOLIC;
1045 return (mips_symbolic_constant_p (x, &info->symbol_type)
1046 && mips_symbolic_address_p (info->symbol_type, mode)
1047 && !mips_split_p[info->symbol_type]);
1054 /* Return the number of instructions needed to load a symbol of the
1055 given type into a register. If valid in an address, the same number
1056 of instructions are needed for loads and stores. Treat extended
1057 mips16 instructions as two instructions. */
1060 mips_symbol_insns (enum mips_symbol_type type)
1064 case SYMBOL_GENERAL:
1065 /* In mips16 code, general symbols must be fetched from the
1070 /* When using 64-bit symbols, we need 5 preparatory instructions,
1073 lui $at,%highest(symbol)
1074 daddiu $at,$at,%higher(symbol)
1076 daddiu $at,$at,%hi(symbol)
1079 The final address is then $at + %lo(symbol). With 32-bit
1080 symbols we just need a preparatory lui. */
1081 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1083 case SYMBOL_SMALL_DATA:
1086 case SYMBOL_CONSTANT_POOL:
1087 /* This case is for mips16 only. Assume we'll need an
1088 extended instruction. */
1091 case SYMBOL_GOT_LOCAL:
1092 case SYMBOL_GOT_GLOBAL:
1093 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1094 the local/global classification is accurate. See override_options
1097 The worst cases are:
1099 (1) For local symbols when generating o32 or o64 code. The assembler
1105 ...and the final address will be $at + %lo(symbol).
1107 (2) For global symbols when -mxgot. The assembler will use:
1109 lui $at,%got_hi(symbol)
1112 ...and the final address will be $at + %got_lo(symbol). */
1115 case SYMBOL_GOTOFF_PAGE:
1116 case SYMBOL_GOTOFF_GLOBAL:
1117 case SYMBOL_GOTOFF_CALL:
1118 case SYMBOL_GOTOFF_LOADGP:
1119 case SYMBOL_64_HIGH:
1122 /* Check whether the offset is a 16- or 32-bit value. */
1123 return mips_split_p[type] ? 2 : 1;
1129 /* Return true if a value at OFFSET bytes from BASE can be accessed
1130 using an unextended mips16 instruction. MODE is the mode of the
1133 Usually the offset in an unextended instruction is a 5-bit field.
1134 The offset is unsigned and shifted left once for HIs, twice
1135 for SIs, and so on. An exception is SImode accesses off the
1136 stack pointer, which have an 8-bit immediate field. */
1139 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1142 && GET_CODE (offset) == CONST_INT
1143 && INTVAL (offset) >= 0
1144 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1146 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1147 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1148 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1154 /* Return the number of instructions needed to load or store a value
1155 of mode MODE at X. Return 0 if X isn't valid for MODE.
1157 For mips16 code, count extended instructions as two instructions. */
1160 mips_address_insns (rtx x, enum machine_mode mode)
1162 struct mips_address_info addr;
1165 if (mode == BLKmode)
1166 /* BLKmode is used for single unaligned loads and stores. */
1169 /* Each word of a multi-word value will be accessed individually. */
1170 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1172 if (mips_classify_address (&addr, x, mode, false))
1177 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1181 case ADDRESS_LO_SUM:
1182 return (TARGET_MIPS16 ? factor * 2 : factor);
1184 case ADDRESS_CONST_INT:
1187 case ADDRESS_SYMBOLIC:
1188 return factor * mips_symbol_insns (addr.symbol_type);
1194 /* Likewise for constant X. */
1197 mips_const_insns (rtx x)
1199 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1200 enum mips_symbol_type symbol_type;
1201 HOST_WIDE_INT offset;
1203 switch (GET_CODE (x))
1207 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1208 || !mips_split_p[symbol_type])
1215 /* Unsigned 8-bit constants can be loaded using an unextended
1216 LI instruction. Unsigned 16-bit constants can be loaded
1217 using an extended LI. Negative constants must be loaded
1218 using LI and then negated. */
1219 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1220 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1221 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1222 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1225 return mips_build_integer (codes, INTVAL (x));
1228 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1234 /* See if we can refer to X directly. */
1235 if (mips_symbolic_constant_p (x, &symbol_type))
1236 return mips_symbol_insns (symbol_type);
1238 /* Otherwise try splitting the constant into a base and offset.
1239 16-bit offsets can be added using an extra addiu. Larger offsets
1240 must be calculated separately and then added to the base. */
1241 mips_split_const (x, &x, &offset);
1244 int n = mips_const_insns (x);
1247 if (SMALL_OPERAND (offset))
1250 return n + 1 + mips_build_integer (codes, offset);
1257 return mips_symbol_insns (mips_classify_symbol (x));
1265 /* Return the number of instructions needed for memory reference X.
1266 Count extended mips16 instructions as two instructions. */
1269 mips_fetch_insns (rtx x)
1271 if (GET_CODE (x) != MEM)
1274 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1278 /* Return the number of instructions needed for an integer division. */
1281 mips_idiv_insns (void)
1286 if (TARGET_CHECK_ZERO_DIV)
1288 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1294 /* Return truth value of whether OP can be used as an operands
1295 where a register or 16 bit unsigned integer is needed. */
1298 uns_arith_operand (rtx op, enum machine_mode mode)
1300 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1303 return register_operand (op, mode);
1307 /* True if OP can be treated as a signed 16-bit constant. */
1310 const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1312 return GET_CODE (op) == CONST_INT && SMALL_INT (op);
1316 /* Return true if OP is a register operand or a signed 16-bit constant. */
1319 arith_operand (rtx op, enum machine_mode mode)
1321 return const_arith_operand (op, mode) || register_operand (op, mode);
1324 /* Return true if OP can be used as the second argument to an LE operation. */
1327 sle_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1329 return GET_CODE (op) == CONST_INT && SMALL_OPERAND (INTVAL (op) + 1);
1335 sleu_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1337 return (GET_CODE (op) == CONST_INT
1338 && INTVAL (op) + 1 != 0
1339 && SMALL_OPERAND (INTVAL (op) + 1));
1342 /* Return truth value of whether OP is an integer which fits in 16 bits. */
1345 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1347 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1350 /* Return truth value of whether OP is a register or the constant 0.
1351 Do not accept 0 in mips16 mode since $0 is not one of the core 8
1355 reg_or_0_operand (rtx op, enum machine_mode mode)
1357 switch (GET_CODE (op))
1362 return INTVAL (op) == 0;
1367 return op == CONST0_RTX (mode);
1370 return register_operand (op, mode);
1374 /* Accept a register or the floating point constant 1 in the
1375 appropriate mode. */
1378 reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
1380 return const_float_1_operand (op, mode) || register_operand (op, mode);
1383 /* Accept the floating point constant 1 in the appropriate mode. */
1386 const_float_1_operand (rtx op, enum machine_mode mode)
1390 if (GET_CODE (op) != CONST_DOUBLE
1391 || mode != GET_MODE (op)
1392 || (mode != DFmode && mode != SFmode))
1395 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1397 return REAL_VALUES_EQUAL (d, dconst1);
1400 /* Return true if OP is either the HI or LO register. */
1403 hilo_operand (rtx op, enum machine_mode mode)
1405 return ((mode == VOIDmode || mode == GET_MODE (op))
1406 && REG_P (op) && MD_REG_P (REGNO (op)));
1409 /* Return true if OP is an extension operator. */
1412 extend_operator (rtx op, enum machine_mode mode)
1414 return ((mode == VOIDmode || mode == GET_MODE (op))
1415 && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
1418 /* Return true if X is the right hand side of a "macc" or "msac" instruction.
1419 This predicate is intended for use in peephole optimizations. */
1422 macc_msac_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1424 if (ISA_HAS_MACC && GET_CODE (x) == PLUS && REG_P (XEXP (x, 1)))
1426 else if (ISA_HAS_MSAC && GET_CODE (x) == MINUS && REG_P (XEXP (x, 0)))
1431 return GET_CODE (x) == MULT && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1));
1434 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1437 equality_op (rtx op, enum machine_mode mode)
1439 if (mode != GET_MODE (op))
1442 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1445 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1448 cmp_op (rtx op, enum machine_mode mode)
1450 if (mode != GET_MODE (op))
1453 return COMPARISON_P (op);
1456 /* Return nonzero if the code is a relational operation suitable for a
1457 conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
1458 We need this in the insn that expands `trap_if' in order to prevent
1459 combine from erroneously altering the condition. */
1462 trap_cmp_op (rtx op, enum machine_mode mode)
1464 if (mode != GET_MODE (op))
1467 switch (GET_CODE (op))
1482 /* Return nonzero if the operand is either the PC or a label_ref. */
1485 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1490 if (GET_CODE (op) == LABEL_REF)
1496 /* Test for a valid call address. */
1499 call_insn_operand (rtx op, enum machine_mode mode)
1501 enum mips_symbol_type symbol_type;
1503 if (mips_symbolic_constant_p (op, &symbol_type))
1504 switch (symbol_type)
1506 case SYMBOL_GENERAL:
1507 /* If -mlong-calls, force all calls to use register addressing. */
1508 return !TARGET_LONG_CALLS;
1510 case SYMBOL_GOT_GLOBAL:
1511 /* Without explicit relocs, there is no special syntax for
1512 loading the address of a call destination into a register.
1513 Using "la $25,foo; jal $25" would prevent the lazy binding
1514 of "foo", so keep the address of global symbols with the
1516 return !TARGET_EXPLICIT_RELOCS;
1521 return register_operand (op, mode);
1525 /* Return nonzero if OP is valid as a source operand for a move
1529 move_operand (rtx op, enum machine_mode mode)
1531 enum mips_symbol_type symbol_type;
1533 if (!general_operand (op, mode))
1536 switch (GET_CODE (op))
1539 /* When generating mips16 code, LEGITIMATE_CONSTANT_P rejects
1540 CONST_INTs that can't be loaded using simple insns. */
1544 /* When generating 32-bit code, allow DImode move_operands to
1545 match arbitrary constants. We split them after reload. */
1546 if (!TARGET_64BIT && mode == DImode)
1549 /* Otherwise check whether the constant can be loaded in a single
1551 return LUI_INT (op) || SMALL_INT (op) || SMALL_INT_UNSIGNED (op);
1556 if (CONST_GP_P (op))
1559 return (mips_symbolic_constant_p (op, &symbol_type)
1560 && !mips_split_p[symbol_type]);
1568 /* Accept any operand that can appear in a mips16 constant table
1569 instruction. We can't use any of the standard operand functions
1570 because for these instructions we accept values that are not
1571 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1574 consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1576 return CONSTANT_P (op);
1579 /* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1580 possibly with an offset. */
1583 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1585 enum mips_symbol_type symbol_type;
1587 return mips_symbolic_constant_p (op, &symbol_type);
1591 /* Return true if OP is a symbolic constant of type SYMBOL_GENERAL. */
1594 general_symbolic_operand (rtx op, enum machine_mode mode)
1596 enum mips_symbol_type symbol_type;
1598 return ((mode == VOIDmode || mode == GET_MODE (op))
1599 && mips_symbolic_constant_p (op, &symbol_type)
1600 && symbol_type == SYMBOL_GENERAL);
1604 /* Return true if we're generating PIC and OP is a global symbol. */
1607 global_got_operand (rtx op, enum machine_mode mode)
1609 enum mips_symbol_type symbol_type;
1611 return ((mode == VOIDmode || mode == GET_MODE (op))
1612 && mips_symbolic_constant_p (op, &symbol_type)
1613 && symbol_type == SYMBOL_GOT_GLOBAL);
1617 /* Likewise for local symbols. */
1620 local_got_operand (rtx op, enum machine_mode mode)
1622 enum mips_symbol_type symbol_type;
1624 return ((mode == VOIDmode || mode == GET_MODE (op))
1625 && mips_symbolic_constant_p (op, &symbol_type)
1626 && symbol_type == SYMBOL_GOT_LOCAL);
1630 /* Return true if OP is a memory reference that uses the stack pointer
1631 as a base register. */
1634 stack_operand (rtx op, enum machine_mode mode)
1636 struct mips_address_info addr;
1638 return ((mode == VOIDmode || mode == GET_MODE (op))
1639 && GET_CODE (op) == MEM
1640 && mips_classify_address (&addr, XEXP (op, 0), GET_MODE (op), false)
1641 && addr.type == ADDRESS_REG
1642 && addr.reg == stack_pointer_rtx);
1645 /* Helper function for DFA schedulers. Return true if OP is a floating
1649 fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1651 return REG_P (op) && FP_REG_P (REGNO (op));
1654 /* Helper function for DFA schedulers. Return true if OP is a LO reg. */
1657 lo_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1659 return REG_P (op) && REGNO (op) == LO_REGNUM;
1663 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1664 returns a nonzero value if X is a legitimate address for a memory
1665 operand of the indicated MODE. STRICT is nonzero if this function
1666 is called during reload. */
1669 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1671 struct mips_address_info addr;
1673 return mips_classify_address (&addr, x, mode, strict);
1677 /* Copy VALUE to a register and return that register. If new psuedos
1678 are allowed, copy it into a new register, otherwise use DEST. */
1681 mips_force_temporary (rtx dest, rtx value)
1683 if (!no_new_pseudos)
1684 return force_reg (Pmode, value);
1687 emit_move_insn (copy_rtx (dest), value);
1693 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1694 and is used to load the high part into a register. */
1697 mips_split_symbol (rtx temp, rtx addr)
1702 high = mips16_gp_pseudo_reg ();
1704 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1705 return gen_rtx_LO_SUM (Pmode, high, addr);
1709 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1710 type SYMBOL_TYPE. */
1713 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1716 HOST_WIDE_INT offset;
1718 mips_split_const (address, &base, &offset);
1719 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1720 UNSPEC_ADDRESS_FIRST + symbol_type);
1721 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1725 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1726 high part to BASE and return the result. Just return BASE otherwise.
1727 TEMP is available as a temporary register if needed.
1729 The returned expression can be used as the first operand to a LO_SUM. */
1732 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1733 enum mips_symbol_type symbol_type)
1735 if (mips_split_p[symbol_type])
1737 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1738 addr = mips_force_temporary (temp, addr);
1739 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1745 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1746 mips_force_temporary; it is only needed when OFFSET is not a
1750 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1752 if (!SMALL_OPERAND (offset))
1757 /* Load the full offset into a register so that we can use
1758 an unextended instruction for the address itself. */
1759 high = GEN_INT (offset);
1764 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1765 high = GEN_INT (CONST_HIGH_PART (offset));
1766 offset = CONST_LOW_PART (offset);
1768 high = mips_force_temporary (temp, high);
1769 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1771 return plus_constant (reg, offset);
1775 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1776 be legitimized in a way that the generic machinery might not expect,
1777 put the new address in *XLOC and return true. MODE is the mode of
1778 the memory being accessed. */
1781 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1783 enum mips_symbol_type symbol_type;
1785 /* See if the address can split into a high part and a LO_SUM. */
1786 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1787 && mips_symbolic_address_p (symbol_type, mode)
1788 && mips_split_p[symbol_type])
1790 *xloc = mips_split_symbol (0, *xloc);
1794 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1796 /* Handle REG + CONSTANT using mips_add_offset. */
1799 reg = XEXP (*xloc, 0);
1800 if (!mips_valid_base_register_p (reg, mode, 0))
1801 reg = copy_to_mode_reg (Pmode, reg);
1802 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
1810 /* Subroutine of mips_build_integer (with the same interface).
1811 Assume that the final action in the sequence should be a left shift. */
1814 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1816 unsigned int i, shift;
1818 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1819 since signed numbers are easier to load than unsigned ones. */
1821 while ((value & 1) == 0)
1822 value /= 2, shift++;
1824 i = mips_build_integer (codes, value);
1825 codes[i].code = ASHIFT;
1826 codes[i].value = shift;
1831 /* As for mips_build_shift, but assume that the final action will be
1832 an IOR or PLUS operation. */
1835 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1837 unsigned HOST_WIDE_INT high;
1840 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1841 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1843 /* The constant is too complex to load with a simple lui/ori pair
1844 so our goal is to clear as many trailing zeros as possible.
1845 In this case, we know bit 16 is set and that the low 16 bits
1846 form a negative number. If we subtract that number from VALUE,
1847 we will clear at least the lowest 17 bits, maybe more. */
1848 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1849 codes[i].code = PLUS;
1850 codes[i].value = CONST_LOW_PART (value);
1854 i = mips_build_integer (codes, high);
1855 codes[i].code = IOR;
1856 codes[i].value = value & 0xffff;
1862 /* Fill CODES with a sequence of rtl operations to load VALUE.
1863 Return the number of operations needed. */
1866 mips_build_integer (struct mips_integer_op *codes,
1867 unsigned HOST_WIDE_INT value)
1869 if (SMALL_OPERAND (value)
1870 || SMALL_OPERAND_UNSIGNED (value)
1871 || LUI_OPERAND (value))
1873 /* The value can be loaded with a single instruction. */
1874 codes[0].code = NIL;
1875 codes[0].value = value;
1878 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1880 /* Either the constant is a simple LUI/ORI combination or its
1881 lowest bit is set. We don't want to shift in this case. */
1882 return mips_build_lower (codes, value);
1884 else if ((value & 0xffff) == 0)
1886 /* The constant will need at least three actions. The lowest
1887 16 bits are clear, so the final action will be a shift. */
1888 return mips_build_shift (codes, value);
1892 /* The final action could be a shift, add or inclusive OR.
1893 Rather than use a complex condition to select the best
1894 approach, try both mips_build_shift and mips_build_lower
1895 and pick the one that gives the shortest sequence.
1896 Note that this case is only used once per constant. */
1897 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1898 unsigned int cost, alt_cost;
1900 cost = mips_build_shift (codes, value);
1901 alt_cost = mips_build_lower (alt_codes, value);
1902 if (alt_cost < cost)
1904 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1912 /* Move VALUE into register DEST. */
1915 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1917 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1918 enum machine_mode mode;
1919 unsigned int i, cost;
1922 mode = GET_MODE (dest);
1923 cost = mips_build_integer (codes, value);
1925 /* Apply each binary operation to X. Invariant: X is a legitimate
1926 source operand for a SET pattern. */
1927 x = GEN_INT (codes[0].value);
1928 for (i = 1; i < cost; i++)
1931 emit_move_insn (dest, x), x = dest;
1933 x = force_reg (mode, x);
1934 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1937 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1941 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1942 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1946 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1949 HOST_WIDE_INT offset;
1950 enum mips_symbol_type symbol_type;
1952 /* Split moves of big integers into smaller pieces. In mips16 code,
1953 it's better to force the constant into memory instead. */
1954 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1956 mips_move_integer (dest, INTVAL (src));
1960 /* See if the symbol can be split. For mips16, this is often worse than
1961 forcing it in the constant pool since it needs the single-register form
1962 of addiu or daddiu. */
1964 && mips_symbolic_constant_p (src, &symbol_type)
1965 && mips_split_p[symbol_type])
1967 emit_move_insn (dest, mips_split_symbol (dest, src));
1971 /* If we have (const (plus symbol offset)), load the symbol first
1972 and then add in the offset. This is usually better than forcing
1973 the constant into memory, at least in non-mips16 code. */
1974 mips_split_const (src, &base, &offset);
1977 && (!no_new_pseudos || SMALL_OPERAND (offset)))
1979 base = mips_force_temporary (dest, base);
1980 emit_move_insn (dest, mips_add_offset (0, base, offset));
1984 src = force_const_mem (mode, src);
1986 /* When using explicit relocs, constant pool references are sometimes
1987 not legitimate addresses. */
1988 if (!memory_operand (src, VOIDmode))
1989 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
1990 emit_move_insn (dest, src);
1994 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1995 sequence that is valid. */
1998 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2000 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2002 emit_move_insn (dest, force_reg (mode, src));
2006 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2007 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2008 && REG_P (src) && MD_REG_P (REGNO (src))
2009 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2011 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2012 if (GET_MODE_SIZE (mode) <= 4)
2013 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2014 gen_rtx_REG (SImode, REGNO (src)),
2015 gen_rtx_REG (SImode, other_regno)));
2017 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2018 gen_rtx_REG (DImode, REGNO (src)),
2019 gen_rtx_REG (DImode, other_regno)));
2023 /* We need to deal with constants that would be legitimate
2024 immediate_operands but not legitimate move_operands. */
2025 if (CONSTANT_P (src) && !move_operand (src, mode))
2027 mips_legitimize_const_move (mode, dest, src);
2028 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2034 /* We need a lot of little routines to check constant values on the
2035 mips16. These are used to figure out how long the instruction will
2036 be. It would be much better to do this using constraints, but
2037 there aren't nearly enough letters available. */
2040 m16_check_op (rtx op, int low, int high, int mask)
2042 return (GET_CODE (op) == CONST_INT
2043 && INTVAL (op) >= low
2044 && INTVAL (op) <= high
2045 && (INTVAL (op) & mask) == 0);
2049 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2051 return m16_check_op (op, 0x1, 0x8, 0);
2055 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2057 return m16_check_op (op, - 0x8, 0x7, 0);
2061 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2063 return m16_check_op (op, - 0x7, 0x8, 0);
2067 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2069 return m16_check_op (op, - 0x10, 0xf, 0);
2073 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2075 return m16_check_op (op, - 0xf, 0x10, 0);
2079 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2081 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2085 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2087 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2091 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2093 return m16_check_op (op, - 0x80, 0x7f, 0);
2097 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2099 return m16_check_op (op, - 0x7f, 0x80, 0);
2103 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2105 return m16_check_op (op, 0x0, 0xff, 0);
2109 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2111 return m16_check_op (op, - 0xff, 0x0, 0);
2115 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2117 return m16_check_op (op, - 0x1, 0xfe, 0);
2121 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2123 return m16_check_op (op, 0x0, 0xff << 2, 3);
2127 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2129 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2133 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2135 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2139 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2141 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2145 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2147 enum machine_mode mode = GET_MODE (x);
2154 /* Always return 0, since we don't have different sized
2155 instructions, hence different costs according to Richard
2161 /* A number between 1 and 8 inclusive is efficient for a shift.
2162 Otherwise, we will need an extended instruction. */
2163 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2164 || (outer_code) == LSHIFTRT)
2166 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2169 *total = COSTS_N_INSNS (1);
2173 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2174 if ((outer_code) == XOR
2175 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2181 /* We may be able to use slt or sltu for a comparison with a
2182 signed 16 bit value. (The boundary conditions aren't quite
2183 right, but this is just a heuristic anyhow.) */
2184 if (((outer_code) == LT || (outer_code) == LE
2185 || (outer_code) == GE || (outer_code) == GT
2186 || (outer_code) == LTU || (outer_code) == LEU
2187 || (outer_code) == GEU || (outer_code) == GTU)
2188 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2194 /* Equality comparisons with 0 are cheap. */
2195 if (((outer_code) == EQ || (outer_code) == NE)
2202 /* Constants in the range 0...255 can be loaded with an unextended
2203 instruction. They are therefore as cheap as a register move.
2205 Given the choice between "li R1,0...255" and "move R1,R2"
2206 (where R2 is a known constant), it is usually better to use "li",
2207 since we do not want to unnessarily extend the lifetime of R2. */
2208 if (outer_code == SET
2210 && INTVAL (x) < 256)
2216 /* Otherwise fall through to the handling below. */
2222 if (LEGITIMATE_CONSTANT_P (x))
2224 *total = COSTS_N_INSNS (1);
2229 /* The value will need to be fetched from the constant pool. */
2230 *total = CONSTANT_POOL_COST;
2236 /* If the address is legitimate, return the number of
2237 instructions it needs, otherwise use the default handling. */
2238 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2241 *total = COSTS_N_INSNS (1 + n);
2248 *total = COSTS_N_INSNS (6);
2252 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2258 if (mode == DImode && !TARGET_64BIT)
2260 *total = COSTS_N_INSNS (2);
2268 if (mode == DImode && !TARGET_64BIT)
2270 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2277 if (mode == SFmode || mode == DFmode)
2278 *total = COSTS_N_INSNS (1);
2280 *total = COSTS_N_INSNS (4);
2284 *total = COSTS_N_INSNS (1);
2289 if (mode == SFmode || mode == DFmode)
2291 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2292 *total = COSTS_N_INSNS (2);
2293 else if (TUNE_MIPS6000)
2294 *total = COSTS_N_INSNS (3);
2296 *total = COSTS_N_INSNS (4);
2298 *total = COSTS_N_INSNS (6);
2301 if (mode == DImode && !TARGET_64BIT)
2303 *total = COSTS_N_INSNS (4);
2309 if (mode == DImode && !TARGET_64BIT)
2323 *total = COSTS_N_INSNS (4);
2324 else if (TUNE_MIPS6000
2327 *total = COSTS_N_INSNS (5);
2329 *total = COSTS_N_INSNS (7);
2336 *total = COSTS_N_INSNS (4);
2337 else if (TUNE_MIPS3000
2340 *total = COSTS_N_INSNS (5);
2341 else if (TUNE_MIPS6000
2344 *total = COSTS_N_INSNS (6);
2346 *total = COSTS_N_INSNS (8);
2351 *total = COSTS_N_INSNS (12);
2352 else if (TUNE_MIPS3900)
2353 *total = COSTS_N_INSNS (2);
2354 else if (TUNE_MIPS4130)
2355 *total = COSTS_N_INSNS (mode == DImode ? 6 : 4);
2356 else if (TUNE_MIPS5400 || TUNE_SB1)
2357 *total = COSTS_N_INSNS (mode == DImode ? 4 : 3);
2358 else if (TUNE_MIPS5500 || TUNE_MIPS7000)
2359 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2360 else if (TUNE_MIPS9000)
2361 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2362 else if (TUNE_MIPS6000)
2363 *total = COSTS_N_INSNS (17);
2364 else if (TUNE_MIPS5000)
2365 *total = COSTS_N_INSNS (5);
2367 *total = COSTS_N_INSNS (10);
2376 *total = COSTS_N_INSNS (12);
2377 else if (TUNE_MIPS6000)
2378 *total = COSTS_N_INSNS (15);
2380 *total = COSTS_N_INSNS (24);
2381 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2382 *total = COSTS_N_INSNS (30);
2384 *total = COSTS_N_INSNS (23);
2392 *total = COSTS_N_INSNS (19);
2393 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2394 *total = COSTS_N_INSNS (59);
2395 else if (TUNE_MIPS6000)
2396 *total = COSTS_N_INSNS (16);
2398 *total = COSTS_N_INSNS (32);
2400 *total = COSTS_N_INSNS (36);
2409 *total = COSTS_N_INSNS (35);
2410 else if (TUNE_MIPS6000)
2411 *total = COSTS_N_INSNS (38);
2412 else if (TUNE_MIPS5000)
2413 *total = COSTS_N_INSNS (36);
2415 *total = COSTS_N_INSNS ((mode == SImode) ? 36 : 68);
2416 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2417 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2419 *total = COSTS_N_INSNS (69);
2423 /* A sign extend from SImode to DImode in 64 bit mode is often
2424 zero instructions, because the result can often be used
2425 directly by another instruction; we'll call it one. */
2426 if (TARGET_64BIT && mode == DImode
2427 && GET_MODE (XEXP (x, 0)) == SImode)
2428 *total = COSTS_N_INSNS (1);
2430 *total = COSTS_N_INSNS (2);
2434 if (TARGET_64BIT && mode == DImode
2435 && GET_MODE (XEXP (x, 0)) == SImode)
2436 *total = COSTS_N_INSNS (2);
2438 *total = COSTS_N_INSNS (1);
2446 /* Provide the costs of an addressing mode that contains ADDR.
2447 If ADDR is not a valid address, its cost is irrelevant. */
2450 mips_address_cost (rtx addr)
2452 return mips_address_insns (addr, SImode);
2455 /* Return one word of double-word value OP, taking into account the fixed
2456 endianness of certain registers. HIGH_P is true to select the high part,
2457 false to select the low part. */
2460 mips_subword (rtx op, int high_p)
2463 enum machine_mode mode;
2465 mode = GET_MODE (op);
2466 if (mode == VOIDmode)
2469 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2470 byte = UNITS_PER_WORD;
2474 if (GET_CODE (op) == REG)
2476 if (FP_REG_P (REGNO (op)))
2477 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2478 if (REGNO (op) == HI_REGNUM)
2479 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2482 if (GET_CODE (op) == MEM)
2483 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2485 return simplify_gen_subreg (word_mode, op, mode, byte);
2489 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2492 mips_split_64bit_move_p (rtx dest, rtx src)
2497 /* FP->FP moves can be done in a single instruction. */
2498 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2501 /* Check for floating-point loads and stores. They can be done using
2502 ldc1 and sdc1 on MIPS II and above. */
2505 if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
2507 if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
2514 /* Split a 64-bit move from SRC to DEST assuming that
2515 mips_split_64bit_move_p holds.
2517 Moves into and out of FPRs cause some difficulty here. Such moves
2518 will always be DFmode, since paired FPRs are not allowed to store
2519 DImode values. The most natural representation would be two separate
2520 32-bit moves, such as:
2522 (set (reg:SI $f0) (mem:SI ...))
2523 (set (reg:SI $f1) (mem:SI ...))
2525 However, the second insn is invalid because odd-numbered FPRs are
2526 not allowed to store independent values. Use the patterns load_df_low,
2527 load_df_high and store_df_high instead. */
2530 mips_split_64bit_move (rtx dest, rtx src)
2532 if (FP_REG_RTX_P (dest))
2534 /* Loading an FPR from memory or from GPRs. */
2535 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2536 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2539 else if (FP_REG_RTX_P (src))
2541 /* Storing an FPR into memory or GPRs. */
2542 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2543 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2547 /* The operation can be split into two normal moves. Decide in
2548 which order to do them. */
2551 low_dest = mips_subword (dest, 0);
2552 if (GET_CODE (low_dest) == REG
2553 && reg_overlap_mentioned_p (low_dest, src))
2555 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2556 emit_move_insn (low_dest, mips_subword (src, 0));
2560 emit_move_insn (low_dest, mips_subword (src, 0));
2561 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2566 /* Return the appropriate instructions to move SRC into DEST. Assume
2567 that SRC is operand 1 and DEST is operand 0. */
2570 mips_output_move (rtx dest, rtx src)
2572 enum rtx_code dest_code, src_code;
2575 dest_code = GET_CODE (dest);
2576 src_code = GET_CODE (src);
2577 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2579 if (dbl_p && mips_split_64bit_move_p (dest, src))
2582 if ((src_code == REG && GP_REG_P (REGNO (src)))
2583 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2585 if (dest_code == REG)
2587 if (GP_REG_P (REGNO (dest)))
2588 return "move\t%0,%z1";
2590 if (MD_REG_P (REGNO (dest)))
2593 if (FP_REG_P (REGNO (dest)))
2594 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2596 if (ALL_COP_REG_P (REGNO (dest)))
2598 static char retval[] = "dmtc_\t%z1,%0";
2600 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2601 return (dbl_p ? retval : retval + 1);
2604 if (dest_code == MEM)
2605 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2607 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2609 if (src_code == REG)
2611 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2612 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2614 if (FP_REG_P (REGNO (src)))
2615 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2617 if (ALL_COP_REG_P (REGNO (src)))
2619 static char retval[] = "dmfc_\t%0,%1";
2621 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2622 return (dbl_p ? retval : retval + 1);
2626 if (src_code == MEM)
2627 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2629 if (src_code == CONST_INT)
2631 /* Don't use the X format, because that will give out of
2632 range numbers for 64 bit hosts and 32 bit targets. */
2634 return "li\t%0,%1\t\t\t# %X1";
2636 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2639 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2643 if (src_code == HIGH)
2644 return "lui\t%0,%h1";
2646 if (CONST_GP_P (src))
2647 return "move\t%0,%1";
2649 if (symbolic_operand (src, VOIDmode))
2650 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2652 if (src_code == REG && FP_REG_P (REGNO (src)))
2654 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2655 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2657 if (dest_code == MEM)
2658 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2660 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2662 if (src_code == MEM)
2663 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2665 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2667 static char retval[] = "l_c_\t%0,%1";
2669 retval[1] = (dbl_p ? 'd' : 'w');
2670 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2673 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2675 static char retval[] = "s_c_\t%1,%0";
2677 retval[1] = (dbl_p ? 'd' : 'w');
2678 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2684 /* Restore $gp from its save slot. Valid only when using o32 or
2688 mips_restore_gp (void)
2692 if (!TARGET_ABICALLS || !TARGET_OLDABI)
2695 address = mips_add_offset (pic_offset_table_rtx,
2696 frame_pointer_needed
2697 ? hard_frame_pointer_rtx
2698 : stack_pointer_rtx,
2699 current_function_outgoing_args_size);
2700 slot = gen_rtx_MEM (Pmode, address);
2701 RTX_UNCHANGING_P (slot) = 1;
2703 emit_move_insn (pic_offset_table_rtx, slot);
2704 if (!TARGET_EXPLICIT_RELOCS)
2705 emit_insn (gen_blockage ());
2708 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2711 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2713 emit_insn (gen_rtx_SET (VOIDmode, target,
2714 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2717 /* Return true if CMP1 is a suitable second operand for relational
2718 operator CODE. See also the *sCC patterns in mips.md. */
2721 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
2727 return reg_or_0_operand (cmp1, VOIDmode);
2731 return !TARGET_MIPS16 && cmp1 == const1_rtx;
2735 return arith_operand (cmp1, VOIDmode);
2738 return sle_operand (cmp1, VOIDmode);
2741 return sleu_operand (cmp1, VOIDmode);
2748 /* Compare CMP0 and CMP1 using relational operator CODE and store the
2749 result in TARGET. CMP0 and TARGET are register_operands that have
2750 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
2751 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
2754 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
2755 rtx target, rtx cmp0, rtx cmp1)
2757 /* First see if there is a MIPS instruction that can do this operation
2758 with CMP1 in its current form. If not, try doing the same for the
2759 inverse operation. If that also fails, force CMP1 into a register
2761 if (mips_relational_operand_ok_p (code, cmp1))
2762 mips_emit_binary (code, target, cmp0, cmp1);
2765 enum rtx_code inv_code = reverse_condition (code);
2766 if (!mips_relational_operand_ok_p (inv_code, cmp1))
2768 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
2769 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
2771 else if (invert_ptr == 0)
2773 rtx inv_target = gen_reg_rtx (GET_MODE (target));
2774 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
2775 mips_emit_binary (XOR, target, inv_target, const1_rtx);
2779 *invert_ptr = !*invert_ptr;
2780 mips_emit_binary (inv_code, target, cmp0, cmp1);
2785 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2786 The register will have the same mode as CMP0. */
2789 mips_zero_if_equal (rtx cmp0, rtx cmp1)
2791 if (cmp1 == const0_rtx)
2794 if (uns_arith_operand (cmp1, VOIDmode))
2795 return expand_binop (GET_MODE (cmp0), xor_optab,
2796 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2798 return expand_binop (GET_MODE (cmp0), sub_optab,
2799 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2802 /* Convert a comparison into something that can be used in a branch or
2803 conditional move. cmp_operands[0] and cmp_operands[1] are the values
2804 being compared and *CODE is the code used to compare them.
2806 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
2807 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
2808 otherwise any standard branch condition can be used. The standard branch
2811 - EQ/NE between two registers.
2812 - any comparison between a register and zero. */
2815 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
2817 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
2819 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
2821 *op0 = cmp_operands[0];
2822 *op1 = cmp_operands[1];
2824 else if (*code == EQ || *code == NE)
2828 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
2833 *op0 = cmp_operands[0];
2834 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
2839 /* The comparison needs a separate scc instruction. Store the
2840 result of the scc in *OP0 and compare it against zero. */
2841 bool invert = false;
2842 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
2844 mips_emit_int_relational (*code, &invert, *op0,
2845 cmp_operands[0], cmp_operands[1]);
2846 *code = (invert ? EQ : NE);
2851 enum rtx_code cmp_code;
2853 /* Floating-point tests use a separate c.cond.fmt comparison to
2854 set a condition code register. The branch or conditional move
2855 will then compare that register against zero.
2857 Set CMP_CODE to the code of the comparison instruction and
2858 *CODE to the code that the branch or move should use. */
2866 cmp_code = reverse_condition_maybe_unordered (*code);
2876 ? gen_reg_rtx (CCmode)
2877 : gen_rtx_REG (CCmode, FPSW_REGNUM));
2879 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
2883 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
2884 Store the result in TARGET and return true if successful.
2886 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
2889 mips_emit_scc (enum rtx_code code, rtx target)
2891 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
2894 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
2895 if (code == EQ || code == NE)
2897 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
2898 mips_emit_binary (code, target, zie, const0_rtx);
2901 mips_emit_int_relational (code, 0, target,
2902 cmp_operands[0], cmp_operands[1]);
2906 /* Emit the common code for doing conditional branches.
2907 operand[0] is the label to jump to.
2908 The comparison operands are saved away by cmp{si,di,sf,df}. */
2911 gen_conditional_branch (rtx *operands, enum rtx_code code)
2913 rtx op0, op1, target;
2915 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
2916 target = gen_rtx_IF_THEN_ELSE (VOIDmode,
2917 gen_rtx_fmt_ee (code, GET_MODE (op0),
2919 gen_rtx_LABEL_REF (VOIDmode, operands[0]),
2921 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, target));
2924 /* Emit the common code for conditional moves. OPERANDS is the array
2925 of operands passed to the conditional move define_expand. */
2928 gen_conditional_move (rtx *operands)
2933 code = GET_CODE (operands[1]);
2934 mips_emit_compare (&code, &op0, &op1, true);
2935 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2936 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2937 gen_rtx_fmt_ee (code, VOIDmode,
2939 operands[2], operands[3])));
2942 /* Emit a conditional trap. OPERANDS is the array of operands passed to
2943 the conditional_trap expander. */
2946 mips_gen_conditional_trap (rtx *operands)
2949 enum rtx_code cmp_code = GET_CODE (operands[0]);
2950 enum machine_mode mode = GET_MODE (cmp_operands[0]);
2952 /* MIPS conditional trap machine instructions don't have GT or LE
2953 flavors, so we must invert the comparison and convert to LT and
2954 GE, respectively. */
2957 case GT: cmp_code = LT; break;
2958 case LE: cmp_code = GE; break;
2959 case GTU: cmp_code = LTU; break;
2960 case LEU: cmp_code = GEU; break;
2963 if (cmp_code == GET_CODE (operands[0]))
2965 op0 = force_reg (mode, cmp_operands[0]);
2966 op1 = cmp_operands[1];
2970 op0 = force_reg (mode, cmp_operands[1]);
2971 op1 = cmp_operands[0];
2973 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
2974 op1 = force_reg (mode, op1);
2976 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
2977 gen_rtx_fmt_ee (cmp_code, GET_MODE (operands[0]),
2982 /* Load function address ADDR into register DEST. SIBCALL_P is true
2983 if the address is needed for a sibling call. */
2986 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
2988 /* If we're generating PIC, and this call is to a global function,
2989 try to allow its address to be resolved lazily. This isn't
2990 possible for NewABI sibcalls since the value of $gp on entry
2991 to the stub would be our caller's gp, not ours. */
2992 if (TARGET_EXPLICIT_RELOCS
2993 && !(sibcall_p && TARGET_NEWABI)
2994 && global_got_operand (addr, VOIDmode))
2996 rtx high, lo_sum_symbol;
2998 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
2999 addr, SYMBOL_GOTOFF_CALL);
3000 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3001 if (Pmode == SImode)
3002 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3004 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3007 emit_move_insn (dest, addr);
3011 /* Expand a call or call_value instruction. RESULT is where the
3012 result will go (null for calls), ADDR is the address of the
3013 function, ARGS_SIZE is the size of the arguments and AUX is
3014 the value passed to us by mips_function_arg. SIBCALL_P is true
3015 if we are expanding a sibling call, false if we're expanding
3019 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3021 rtx orig_addr, pattern, insn;
3024 if (!call_insn_operand (addr, VOIDmode))
3026 addr = gen_reg_rtx (Pmode);
3027 mips_load_call_address (addr, orig_addr, sibcall_p);
3031 && mips16_hard_float
3032 && build_mips16_call_stub (result, addr, args_size,
3033 aux == 0 ? 0 : (int) GET_MODE (aux)))
3037 pattern = (sibcall_p
3038 ? gen_sibcall_internal (addr, args_size)
3039 : gen_call_internal (addr, args_size));
3040 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3044 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3045 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3048 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3049 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3052 pattern = (sibcall_p
3053 ? gen_sibcall_value_internal (result, addr, args_size)
3054 : gen_call_value_internal (result, addr, args_size));
3056 insn = emit_call_insn (pattern);
3058 /* Lazy-binding stubs require $gp to be valid on entry. */
3059 if (global_got_operand (orig_addr, VOIDmode))
3060 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3064 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3067 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3068 tree exp ATTRIBUTE_UNUSED)
3070 return TARGET_SIBCALLS;
3073 /* Return true if operand OP is a condition code register.
3074 Only for use during or after reload. */
3077 fcc_register_operand (rtx op, enum machine_mode mode)
3079 return ((mode == VOIDmode || mode == GET_MODE (op))
3080 && (reload_in_progress || reload_completed)
3081 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3082 && ST_REG_P (true_regnum (op)));
3085 /* Emit code to move general operand SRC into condition-code
3086 register DEST. SCRATCH is a scratch TFmode float register.
3093 where FP1 and FP2 are single-precision float registers
3094 taken from SCRATCH. */
3097 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3101 /* Change the source to SFmode. */
3102 if (GET_CODE (src) == MEM)
3103 src = adjust_address (src, SFmode, 0);
3104 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3105 src = gen_rtx_REG (SFmode, true_regnum (src));
3107 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3108 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3110 emit_move_insn (copy_rtx (fp1), src);
3111 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3112 emit_insn (gen_slt_sf (dest, fp2, fp1));
3115 /* Emit code to change the current function's return address to
3116 ADDRESS. SCRATCH is available as a scratch register, if needed.
3117 ADDRESS and SCRATCH are both word-mode GPRs. */
3120 mips_set_return_address (rtx address, rtx scratch)
3124 compute_frame_size (get_frame_size ());
3125 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3127 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3128 cfun->machine->frame.gp_sp_offset);
3130 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3133 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3134 Assume that the areas do not overlap. */
3137 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3139 HOST_WIDE_INT offset, delta;
3140 unsigned HOST_WIDE_INT bits;
3142 enum machine_mode mode;
3145 /* Work out how many bits to move at a time. If both operands have
3146 half-word alignment, it is usually better to move in half words.
3147 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3148 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3149 Otherwise move word-sized chunks. */
3150 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3151 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3152 bits = BITS_PER_WORD / 2;
3154 bits = BITS_PER_WORD;
3156 mode = mode_for_size (bits, MODE_INT, 0);
3157 delta = bits / BITS_PER_UNIT;
3159 /* Allocate a buffer for the temporary registers. */
3160 regs = alloca (sizeof (rtx) * length / delta);
3162 /* Load as many BITS-sized chunks as possible. Use a normal load if
3163 the source has enough alignment, otherwise use left/right pairs. */
3164 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3166 regs[i] = gen_reg_rtx (mode);
3167 if (MEM_ALIGN (src) >= bits)
3168 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3171 rtx part = adjust_address (src, BLKmode, offset);
3172 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3177 /* Copy the chunks to the destination. */
3178 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3179 if (MEM_ALIGN (dest) >= bits)
3180 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3183 rtx part = adjust_address (dest, BLKmode, offset);
3184 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3188 /* Mop up any left-over bytes. */
3189 if (offset < length)
3191 src = adjust_address (src, BLKmode, offset);
3192 dest = adjust_address (dest, BLKmode, offset);
3193 move_by_pieces (dest, src, length - offset,
3194 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3198 #define MAX_MOVE_REGS 4
3199 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3202 /* Helper function for doing a loop-based block operation on memory
3203 reference MEM. Each iteration of the loop will operate on LENGTH
3206 Create a new base register for use within the loop and point it to
3207 the start of MEM. Create a new memory reference that uses this
3208 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3211 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3212 rtx *loop_reg, rtx *loop_mem)
3214 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3216 /* Although the new mem does not refer to a known location,
3217 it does keep up to LENGTH bytes of alignment. */
3218 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3219 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3223 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3224 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3225 memory regions do not overlap. */
3228 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3230 rtx label, src_reg, dest_reg, final_src;
3231 HOST_WIDE_INT leftover;
3233 leftover = length % MAX_MOVE_BYTES;
3236 /* Create registers and memory references for use within the loop. */
3237 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3238 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3240 /* Calculate the value that SRC_REG should have after the last iteration
3242 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3245 /* Emit the start of the loop. */
3246 label = gen_label_rtx ();
3249 /* Emit the loop body. */
3250 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3252 /* Move on to the next block. */
3253 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3254 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3256 /* Emit the loop condition. */
3257 if (Pmode == DImode)
3258 emit_insn (gen_cmpdi (src_reg, final_src));
3260 emit_insn (gen_cmpsi (src_reg, final_src));
3261 emit_jump_insn (gen_bne (label));
3263 /* Mop up any left-over bytes. */
3265 mips_block_move_straight (dest, src, leftover);
3268 /* Expand a movmemsi instruction. */
3271 mips_expand_block_move (rtx dest, rtx src, rtx length)
3273 if (GET_CODE (length) == CONST_INT)
3275 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3277 mips_block_move_straight (dest, src, INTVAL (length));
3282 mips_block_move_loop (dest, src, INTVAL (length));
3289 /* Argument support functions. */
3291 /* Initialize CUMULATIVE_ARGS for a function. */
3294 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3295 rtx libname ATTRIBUTE_UNUSED)
3297 static CUMULATIVE_ARGS zero_cum;
3298 tree param, next_param;
3301 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3303 /* Determine if this function has variable arguments. This is
3304 indicated by the last argument being 'void_type_mode' if there
3305 are no variable arguments. The standard MIPS calling sequence
3306 passes all arguments in the general purpose registers in this case. */
3308 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3309 param != 0; param = next_param)
3311 next_param = TREE_CHAIN (param);
3312 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3313 cum->gp_reg_found = 1;
3318 /* Fill INFO with information about a single argument. CUM is the
3319 cumulative state for earlier arguments. MODE is the mode of this
3320 argument and TYPE is its type (if known). NAMED is true if this
3321 is a named (fixed) argument rather than a variable one. */
3324 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3325 tree type, int named, struct mips_arg_info *info)
3328 unsigned int num_words, max_regs;
3330 /* Decide whether this argument should go in a floating-point register,
3331 assuming one is free. Later code checks for availability. */
3333 info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
3334 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3341 info->fpr_p = (!cum->gp_reg_found
3342 && cum->arg_number < 2
3343 && (type == 0 || FLOAT_TYPE_P (type)));
3348 info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
3352 /* Now decide whether the argument must go in an even-numbered register. */
3357 /* Under the O64 ABI, the second float argument goes in $f13 if it
3358 is a double, but $f14 if it is a single. Otherwise, on a
3359 32-bit double-float machine, each FP argument must start in a
3360 new register pair. */
3361 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
3362 || (mips_abi == ABI_O64 && mode == SFmode)
3365 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
3367 if (GET_MODE_CLASS (mode) == MODE_INT
3368 || GET_MODE_CLASS (mode) == MODE_FLOAT)
3369 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
3371 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
3375 /* Set REG_OFFSET to the register count we're interested in.
3376 The EABI allocates the floating-point registers separately,
3377 but the other ABIs allocate them like integer registers. */
3378 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3383 info->reg_offset += info->reg_offset & 1;
3385 /* The alignment applied to registers is also applied to stack arguments. */
3386 info->stack_offset = cum->stack_words;
3388 info->stack_offset += info->stack_offset & 1;
3390 if (mode == BLKmode)
3391 info->num_bytes = int_size_in_bytes (type);
3393 info->num_bytes = GET_MODE_SIZE (mode);
3395 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3396 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3398 /* Partition the argument between registers and stack. */
3399 info->reg_words = MIN (num_words, max_regs);
3400 info->stack_words = num_words - info->reg_words;
3404 /* Implement FUNCTION_ARG_ADVANCE. */
3407 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3408 tree type, int named)
3410 struct mips_arg_info info;
3412 mips_arg_info (cum, mode, type, named, &info);
3415 cum->gp_reg_found = true;
3417 /* See the comment above the cumulative args structure in mips.h
3418 for an explanation of what this code does. It assumes the O32
3419 ABI, which passes at most 2 arguments in float registers. */
3420 if (cum->arg_number < 2 && info.fpr_p)
3421 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3423 if (mips_abi != ABI_EABI || !info.fpr_p)
3424 cum->num_gprs = info.reg_offset + info.reg_words;
3425 else if (info.reg_words > 0)
3426 cum->num_fprs += FP_INC;
3428 if (info.stack_words > 0)
3429 cum->stack_words = info.stack_offset + info.stack_words;
3434 /* Implement FUNCTION_ARG. */
3437 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3438 tree type, int named)
3440 struct mips_arg_info info;
3442 /* We will be called with a mode of VOIDmode after the last argument
3443 has been seen. Whatever we return will be passed to the call
3444 insn. If we need a mips16 fp_code, return a REG with the code
3445 stored as the mode. */
3446 if (mode == VOIDmode)
3448 if (TARGET_MIPS16 && cum->fp_code != 0)
3449 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3455 mips_arg_info (cum, mode, type, named, &info);
3457 /* Return straight away if the whole argument is passed on the stack. */
3458 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3462 && TREE_CODE (type) == RECORD_TYPE
3464 && TYPE_SIZE_UNIT (type)
3465 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3468 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3469 structure contains a double in its entirety, then that 64 bit
3470 chunk is passed in a floating point register. */
3473 /* First check to see if there is any such field. */
3474 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3475 if (TREE_CODE (field) == FIELD_DECL
3476 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3477 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3478 && host_integerp (bit_position (field), 0)
3479 && int_bit_position (field) % BITS_PER_WORD == 0)
3484 /* Now handle the special case by returning a PARALLEL
3485 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3486 chunks are passed in registers. */
3488 HOST_WIDE_INT bitpos;
3491 /* assign_parms checks the mode of ENTRY_PARM, so we must
3492 use the actual mode here. */
3493 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3496 field = TYPE_FIELDS (type);
3497 for (i = 0; i < info.reg_words; i++)
3501 for (; field; field = TREE_CHAIN (field))
3502 if (TREE_CODE (field) == FIELD_DECL
3503 && int_bit_position (field) >= bitpos)
3507 && int_bit_position (field) == bitpos
3508 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3509 && !TARGET_SOFT_FLOAT
3510 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3511 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3513 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3516 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3517 GEN_INT (bitpos / BITS_PER_UNIT));
3519 bitpos += BITS_PER_WORD;
3526 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3528 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3532 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3535 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3536 enum machine_mode mode, tree type, int named)
3538 struct mips_arg_info info;
3540 mips_arg_info (cum, mode, type, named, &info);
3541 return info.stack_words > 0 ? info.reg_words : 0;
3545 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3546 upward rather than downward. In other words, return true if the
3547 first byte of the stack slot has useful data, false if the last
3551 mips_pad_arg_upward (enum machine_mode mode, tree type)
3553 /* On little-endian targets, the first byte of every stack argument
3554 is passed in the first byte of the stack slot. */
3555 if (!BYTES_BIG_ENDIAN)
3558 /* Otherwise, integral types are padded downward: the last byte of a
3559 stack argument is passed in the last byte of the stack slot. */
3561 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3562 : GET_MODE_CLASS (mode) == MODE_INT)
3565 /* Big-endian o64 pads floating-point arguments downward. */
3566 if (mips_abi == ABI_O64)
3567 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3570 /* Other types are padded upward for o32, o64, n32 and n64. */
3571 if (mips_abi != ABI_EABI)
3574 /* Arguments smaller than a stack slot are padded downward. */
3575 if (mode != BLKmode)
3576 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3578 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3582 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3583 if the least significant byte of the register has useful data. Return
3584 the opposite if the most significant byte does. */
3587 mips_pad_reg_upward (enum machine_mode mode, tree type)
3589 /* No shifting is required for floating-point arguments. */
3590 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3591 return !BYTES_BIG_ENDIAN;
3593 /* Otherwise, apply the same padding to register arguments as we do
3594 to stack arguments. */
3595 return mips_pad_arg_upward (mode, type);
3599 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3600 tree type, int *pretend_size, int no_rtl)
3602 CUMULATIVE_ARGS local_cum;
3603 int gp_saved, fp_saved;
3605 /* The caller has advanced CUM up to, but not beyond, the last named
3606 argument. Advance a local copy of CUM past the last "real" named
3607 argument, to find out how many registers are left over. */
3610 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3612 /* Found out how many registers we need to save. */
3613 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3614 fp_saved = (EABI_FLOAT_VARARGS_P
3615 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3624 ptr = virtual_incoming_args_rtx;
3629 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3633 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3636 mem = gen_rtx_MEM (BLKmode, ptr);
3637 set_mem_alias_set (mem, get_varargs_alias_set ());
3639 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3644 /* We can't use move_block_from_reg, because it will use
3646 enum machine_mode mode;
3649 /* Set OFF to the offset from virtual_incoming_args_rtx of
3650 the first float register. The FP save area lies below
3651 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3652 off = -gp_saved * UNITS_PER_WORD;
3653 off &= ~(UNITS_PER_FPVALUE - 1);
3654 off -= fp_saved * UNITS_PER_FPREG;
3656 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3658 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3662 ptr = plus_constant (virtual_incoming_args_rtx, off);
3663 mem = gen_rtx_MEM (mode, ptr);
3664 set_mem_alias_set (mem, get_varargs_alias_set ());
3665 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3666 off += UNITS_PER_HWFPVALUE;
3672 /* No need for pretend arguments: the register parameter area was
3673 allocated by the caller. */
3677 *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3680 /* Create the va_list data type.
3681 We keep 3 pointers, and two offsets.
3682 Two pointers are to the overflow area, which starts at the CFA.
3683 One of these is constant, for addressing into the GPR save area below it.
3684 The other is advanced up the stack through the overflow region.
3685 The third pointer is to the GPR save area. Since the FPR save area
3686 is just below it, we can address FPR slots off this pointer.
3687 We also keep two one-byte offsets, which are to be subtracted from the
3688 constant pointers to yield addresses in the GPR and FPR save areas.
3689 These are downcounted as float or non-float arguments are used,
3690 and when they get to zero, the argument must be obtained from the
3692 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3693 pointer is enough. It's started at the GPR save area, and is
3695 Note that the GPR save area is not constant size, due to optimization
3696 in the prologue. Hence, we can't use a design with two pointers
3697 and two offsets, although we could have designed this with two pointers
3698 and three offsets. */
3701 mips_build_builtin_va_list (void)
3703 if (EABI_FLOAT_VARARGS_P)
3705 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3708 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3710 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
3712 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
3714 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
3716 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
3717 unsigned_char_type_node);
3718 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
3719 unsigned_char_type_node);
3720 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
3721 warn on every user file. */
3722 index = build_int_2 (GET_MODE_SIZE (ptr_mode) - 2 - 1, 0);
3723 array = build_array_type (unsigned_char_type_node,
3724 build_index_type (index));
3725 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
3727 DECL_FIELD_CONTEXT (f_ovfl) = record;
3728 DECL_FIELD_CONTEXT (f_gtop) = record;
3729 DECL_FIELD_CONTEXT (f_ftop) = record;
3730 DECL_FIELD_CONTEXT (f_goff) = record;
3731 DECL_FIELD_CONTEXT (f_foff) = record;
3732 DECL_FIELD_CONTEXT (f_res) = record;
3734 TYPE_FIELDS (record) = f_ovfl;
3735 TREE_CHAIN (f_ovfl) = f_gtop;
3736 TREE_CHAIN (f_gtop) = f_ftop;
3737 TREE_CHAIN (f_ftop) = f_goff;
3738 TREE_CHAIN (f_goff) = f_foff;
3739 TREE_CHAIN (f_foff) = f_res;
3741 layout_type (record);
3744 else if (TARGET_IRIX && !TARGET_IRIX5)
3745 /* On IRIX 6, this type is 'char *'. */
3746 return build_pointer_type (char_type_node);
3748 /* Otherwise, we use 'void *'. */
3749 return ptr_type_node;
3752 /* Implement va_start. */
3755 mips_va_start (tree valist, rtx nextarg)
3757 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
3759 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
3760 since the stack is aligned for a pair of argument-passing slots,
3761 and the beginning of a variable argument list may be an odd slot,
3762 we have to decrease its alignment. */
3763 if (cfun && cfun->emit->regno_pointer_align)
3764 while (((current_function_pretend_args_size * BITS_PER_UNIT)
3765 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
3766 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
3768 if (mips_abi == ABI_EABI)
3770 int gpr_save_area_size;
3773 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
3775 if (EABI_FLOAT_VARARGS_P)
3777 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
3778 tree ovfl, gtop, ftop, goff, foff;
3781 int fpr_save_area_size;
3783 f_ovfl = TYPE_FIELDS (va_list_type_node);
3784 f_gtop = TREE_CHAIN (f_ovfl);
3785 f_ftop = TREE_CHAIN (f_gtop);
3786 f_goff = TREE_CHAIN (f_ftop);
3787 f_foff = TREE_CHAIN (f_goff);
3789 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
3791 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
3793 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
3795 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
3797 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
3800 /* Emit code to initialize OVFL, which points to the next varargs
3801 stack argument. CUM->STACK_WORDS gives the number of stack
3802 words used by named arguments. */
3803 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
3804 if (cum->stack_words > 0)
3805 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
3806 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
3807 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
3808 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3810 /* Emit code to initialize GTOP, the top of the GPR save area. */
3811 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
3812 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
3813 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3815 /* Emit code to initialize FTOP, the top of the FPR save area.
3816 This address is gpr_save_area_bytes below GTOP, rounded
3817 down to the next fp-aligned boundary. */
3818 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
3819 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
3820 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
3822 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
3823 build_int_2 (-fpr_offset, -1));
3824 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
3825 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3827 /* Emit code to initialize GOFF, the offset from GTOP of the
3828 next GPR argument. */
3829 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
3830 build_int_2 (gpr_save_area_size, 0));
3831 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3833 /* Likewise emit code to initialize FOFF, the offset from FTOP
3834 of the next FPR argument. */
3836 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
3837 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
3838 build_int_2 (fpr_save_area_size, 0));
3839 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3843 /* Everything is in the GPR save area, or in the overflow
3844 area which is contiguous with it. */
3845 nextarg = plus_constant (nextarg, -gpr_save_area_size);
3846 std_expand_builtin_va_start (valist, nextarg);
3850 std_expand_builtin_va_start (valist, nextarg);
3853 /* Implement va_arg. */
3856 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
3858 HOST_WIDE_INT size, rsize;
3862 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
3865 type = build_pointer_type (type);
3867 size = int_size_in_bytes (type);
3868 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
3870 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
3871 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
3874 /* Not a simple merged stack. */
3876 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
3877 tree ovfl, top, off, align;
3878 HOST_WIDE_INT osize;
3881 f_ovfl = TYPE_FIELDS (va_list_type_node);
3882 f_gtop = TREE_CHAIN (f_ovfl);
3883 f_ftop = TREE_CHAIN (f_gtop);
3884 f_goff = TREE_CHAIN (f_ftop);
3885 f_foff = TREE_CHAIN (f_goff);
3887 /* We maintain separate pointers and offsets for floating-point
3888 and integer arguments, but we need similar code in both cases.
3891 TOP be the top of the register save area;
3892 OFF be the offset from TOP of the next register;
3893 ADDR_RTX be the address of the argument;
3894 RSIZE be the number of bytes used to store the argument
3895 when it's in the register save area;
3896 OSIZE be the number of bytes used to store it when it's
3897 in the stack overflow area; and
3898 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
3900 The code we want is:
3902 1: off &= -rsize; // round down
3905 4: addr_rtx = top - off;
3910 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
3911 10: addr_rtx = ovfl + PADDING;
3915 [1] and [9] can sometimes be optimized away. */
3917 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
3920 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
3921 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
3923 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
3925 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
3928 /* When floating-point registers are saved to the stack,
3929 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
3930 of the float's precision. */
3931 rsize = UNITS_PER_HWFPVALUE;
3933 /* Overflow arguments are padded to UNITS_PER_WORD bytes
3934 (= PARM_BOUNDARY bits). This can be different from RSIZE
3937 (1) On 32-bit targets when TYPE is a structure such as:
3939 struct s { float f; };
3941 Such structures are passed in paired FPRs, so RSIZE
3942 will be 8 bytes. However, the structure only takes
3943 up 4 bytes of memory, so OSIZE will only be 4.
3945 (2) In combinations such as -mgp64 -msingle-float
3946 -fshort-double. Doubles passed in registers
3947 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
3948 but those passed on the stack take up
3949 UNITS_PER_WORD bytes. */
3950 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
3954 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
3956 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
3958 if (rsize > UNITS_PER_WORD)
3960 /* [1] Emit code for: off &= -rsize. */
3961 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
3962 build_int_2 (-rsize, -1));
3963 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
3964 gimplify_and_add (t, pre_p);
3969 /* [2] Emit code to branch if off == 0. */
3970 t = lang_hooks.truthvalue_conversion (off);
3971 addr = build (COND_EXPR, ptr_type_node, t, NULL, NULL);
3973 /* [5] Emit code for: off -= rsize. We do this as a form of
3974 post-increment not available to C. Also widen for the
3975 coming pointer arithmetic. */
3976 t = fold_convert (TREE_TYPE (off), build_int_2 (rsize, 0));
3977 t = build (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
3978 t = fold_convert (sizetype, t);
3979 t = fold_convert (TREE_TYPE (top), t);
3981 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
3982 the argument has RSIZE - SIZE bytes of leading padding. */
3983 t = build (MINUS_EXPR, TREE_TYPE (top), top, t);
3984 if (BYTES_BIG_ENDIAN && rsize > size)
3986 u = fold_convert (TREE_TYPE (t), build_int_2 (rsize - size, 0));
3987 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
3989 COND_EXPR_THEN (addr) = t;
3991 if (osize > UNITS_PER_WORD)
3993 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
3994 u = fold_convert (TREE_TYPE (ovfl), build_int_2 (osize - 1, 0));
3995 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
3996 u = fold_convert (TREE_TYPE (ovfl), build_int_2 (-osize, -1));
3997 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
3998 align = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4003 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4004 post-increment ovfl by osize. On big-endian machines,
4005 the argument has OSIZE - SIZE bytes of leading padding. */
4006 u = fold_convert (TREE_TYPE (ovfl), build_int_2 (osize, 0));
4007 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4008 if (BYTES_BIG_ENDIAN && osize > size)
4010 u = fold_convert (TREE_TYPE (t), build_int_2 (osize - size, 0));
4011 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4014 /* String [9] and [10,11] together. */
4016 t = build (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4017 COND_EXPR_ELSE (addr) = t;
4019 addr = fold_convert (build_pointer_type (type), addr);
4020 addr = build_fold_indirect_ref (addr);
4024 addr = build_fold_indirect_ref (addr);
4029 /* Return true if it is possible to use left/right accesses for a
4030 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4031 returning true, update *OP, *LEFT and *RIGHT as follows:
4033 *OP is a BLKmode reference to the whole field.
4035 *LEFT is a QImode reference to the first byte if big endian or
4036 the last byte if little endian. This address can be used in the
4037 left-side instructions (lwl, swl, ldl, sdl).
4039 *RIGHT is a QImode reference to the opposite end of the field and
4040 can be used in the parterning right-side instruction. */
4043 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4044 rtx *left, rtx *right)
4048 /* Check that the operand really is a MEM. Not all the extv and
4049 extzv predicates are checked. */
4050 if (GET_CODE (*op) != MEM)
4053 /* Check that the size is valid. */
4054 if (width != 32 && (!TARGET_64BIT || width != 64))
4057 /* We can only access byte-aligned values. Since we are always passed
4058 a reference to the first byte of the field, it is not necessary to
4059 do anything with BITPOS after this check. */
4060 if (bitpos % BITS_PER_UNIT != 0)
4063 /* Reject aligned bitfields: we want to use a normal load or store
4064 instead of a left/right pair. */
4065 if (MEM_ALIGN (*op) >= width)
4068 /* Adjust *OP to refer to the whole field. This also has the effect
4069 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4070 *op = adjust_address (*op, BLKmode, 0);
4071 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4073 /* Get references to both ends of the field. We deliberately don't
4074 use the original QImode *OP for FIRST since the new BLKmode one
4075 might have a simpler address. */
4076 first = adjust_address (*op, QImode, 0);
4077 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4079 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4080 be the upper word and RIGHT the lower word. */
4081 if (TARGET_BIG_ENDIAN)
4082 *left = first, *right = last;
4084 *left = last, *right = first;
4090 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4091 Return true on success. We only handle cases where zero_extract is
4092 equivalent to sign_extract. */
4095 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4097 rtx left, right, temp;
4099 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4100 paradoxical word_mode subreg. This is the only case in which
4101 we allow the destination to be larger than the source. */
4102 if (GET_CODE (dest) == SUBREG
4103 && GET_MODE (dest) == DImode
4104 && SUBREG_BYTE (dest) == 0
4105 && GET_MODE (SUBREG_REG (dest)) == SImode)
4106 dest = SUBREG_REG (dest);
4108 /* After the above adjustment, the destination must be the same
4109 width as the source. */
4110 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4113 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4116 temp = gen_reg_rtx (GET_MODE (dest));
4117 if (GET_MODE (dest) == DImode)
4119 emit_insn (gen_mov_ldl (temp, src, left));
4120 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4124 emit_insn (gen_mov_lwl (temp, src, left));
4125 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4131 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4135 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4139 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4142 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4144 if (GET_MODE (src) == DImode)
4146 emit_insn (gen_mov_sdl (dest, src, left));
4147 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4151 emit_insn (gen_mov_swl (dest, src, left));
4152 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4157 /* Set up globals to generate code for the ISA or processor
4158 described by INFO. */
4161 mips_set_architecture (const struct mips_cpu_info *info)
4165 mips_arch_info = info;
4166 mips_arch = info->cpu;
4167 mips_isa = info->isa;
4172 /* Likewise for tuning. */
4175 mips_set_tune (const struct mips_cpu_info *info)
4179 mips_tune_info = info;
4180 mips_tune = info->cpu;
4185 /* Set up the threshold for data to go into the small data area, instead
4186 of the normal data area, and detect any conflicts in the switches. */
4189 override_options (void)
4191 int i, start, regno;
4192 enum machine_mode mode;
4194 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4196 /* Interpret -mabi. */
4197 mips_abi = MIPS_ABI_DEFAULT;
4198 if (mips_abi_string != 0)
4200 if (strcmp (mips_abi_string, "32") == 0)
4202 else if (strcmp (mips_abi_string, "o64") == 0)
4204 else if (strcmp (mips_abi_string, "n32") == 0)
4206 else if (strcmp (mips_abi_string, "64") == 0)
4208 else if (strcmp (mips_abi_string, "eabi") == 0)
4209 mips_abi = ABI_EABI;
4211 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4214 /* The following code determines the architecture and register size.
4215 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4216 The GAS and GCC code should be kept in sync as much as possible. */
4218 if (mips_arch_string != 0)
4219 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4221 if (mips_isa_string != 0)
4223 /* Handle -mipsN. */
4224 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4225 const struct mips_cpu_info *isa_info;
4227 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4228 free (whole_isa_str);
4230 /* -march takes precedence over -mipsN, since it is more descriptive.
4231 There's no harm in specifying both as long as the ISA levels
4233 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4234 error ("-mips%s conflicts with the other architecture options, "
4235 "which specify a MIPS%d processor",
4236 mips_isa_string, mips_isa);
4238 /* Set architecture based on the given option. */
4239 mips_set_architecture (isa_info);
4242 if (mips_arch_info == 0)
4244 #ifdef MIPS_CPU_STRING_DEFAULT
4245 mips_set_architecture (mips_parse_cpu ("default CPU",
4246 MIPS_CPU_STRING_DEFAULT));
4248 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4252 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4253 error ("-march=%s is not compatible with the selected ABI",
4254 mips_arch_info->name);
4256 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4257 if (mips_tune_string != 0)
4258 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4260 if (mips_tune_info == 0)
4261 mips_set_tune (mips_arch_info);
4263 if ((target_flags_explicit & MASK_64BIT) != 0)
4265 /* The user specified the size of the integer registers. Make sure
4266 it agrees with the ABI and ISA. */
4267 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4268 error ("-mgp64 used with a 32-bit processor");
4269 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4270 error ("-mgp32 used with a 64-bit ABI");
4271 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4272 error ("-mgp64 used with a 32-bit ABI");
4276 /* Infer the integer register size from the ABI and processor.
4277 Restrict ourselves to 32-bit registers if that's all the
4278 processor has, or if the ABI cannot handle 64-bit registers. */
4279 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4280 target_flags &= ~MASK_64BIT;
4282 target_flags |= MASK_64BIT;
4285 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4287 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4288 only one right answer here. */
4289 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4290 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4291 else if (!TARGET_64BIT && TARGET_FLOAT64)
4292 error ("unsupported combination: %s", "-mgp32 -mfp64");
4293 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4294 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4298 /* -msingle-float selects 32-bit float registers. Otherwise the
4299 float registers should be the same size as the integer ones. */
4300 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4301 target_flags |= MASK_FLOAT64;
4303 target_flags &= ~MASK_FLOAT64;
4306 /* End of code shared with GAS. */
4308 if ((target_flags_explicit & MASK_LONG64) == 0)
4310 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4311 were used, then set the type sizes. In the EABI in 64 bit mode,
4312 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4314 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4315 target_flags |= MASK_LONG64;
4317 target_flags &= ~MASK_LONG64;
4320 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4321 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4323 /* For some configurations, it is useful to have -march control
4324 the default setting of MASK_SOFT_FLOAT. */
4325 switch ((int) mips_arch)
4327 case PROCESSOR_R4100:
4328 case PROCESSOR_R4111:
4329 case PROCESSOR_R4120:
4330 case PROCESSOR_R4130:
4331 target_flags |= MASK_SOFT_FLOAT;
4335 target_flags &= ~MASK_SOFT_FLOAT;
4341 flag_pcc_struct_return = 0;
4343 #if defined(USE_COLLECT2)
4344 /* For IRIX 5 or IRIX 6 with integrated O32 ABI support, USE_COLLECT2 is
4345 always defined when GNU as is not in use, but collect2 is only used
4346 for the O32 ABI, so override the toplev.c and target-def.h defaults
4347 for flag_gnu_linker, TARGET_ASM_{CONSTRUCTOR, DESTRUCTOR} and
4348 TARGET_HAVE_CTORS_DTORS.
4350 Since the IRIX 5 and IRIX 6 O32 assemblers cannot handle named
4351 sections, constructor/destructor handling depends on the ABI in use.
4353 Since USE_COLLECT2 is defined, we only need to restore the non-collect2
4354 defaults for the N32/N64 ABIs. */
4355 if (TARGET_IRIX && !TARGET_SGI_O32_AS)
4357 targetm.have_ctors_dtors = true;
4358 targetm.asm_out.constructor = default_named_section_asm_out_constructor;
4359 targetm.asm_out.destructor = default_named_section_asm_out_destructor;
4363 /* Handle some quirks of the IRIX 5 and IRIX 6 O32 assemblers. */
4365 if (TARGET_SGI_O32_AS)
4367 /* They don't recognize `.[248]byte'. */
4368 targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
4369 targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
4370 /* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
4371 contrary to the documentation, so disable it. */
4372 targetm.asm_out.unaligned_op.di = NULL;
4374 /* They cannot handle named sections. */
4375 targetm.have_named_sections = false;
4376 /* Therefore, EH_FRAME_SECTION_NAME isn't defined and we must use
4378 targetm.terminate_dw2_eh_frame_info = true;
4379 targetm.asm_out.eh_frame_section = collect2_eh_frame_section;
4381 /* They cannot handle debug information. */
4382 if (write_symbols != NO_DEBUG)
4384 /* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
4385 so -mabi=32 isn't usually specified. */
4387 inform ("-g is only supported using GNU as,");
4389 inform ("-g is only supported using GNU as with -mabi=32,");
4390 inform ("-g option disabled");
4391 write_symbols = NO_DEBUG;
4395 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4397 /* If neither -mbranch-likely nor -mno-branch-likely was given
4398 on the command line, set MASK_BRANCHLIKELY based on the target
4401 By default, we enable use of Branch Likely instructions on
4402 all architectures which support them with the following
4403 exceptions: when creating MIPS32 or MIPS64 code, and when
4404 tuning for architectures where their use tends to hurt
4407 The MIPS32 and MIPS64 architecture specifications say "Software
4408 is strongly encouraged to avoid use of Branch Likely
4409 instructions, as they will be removed from a future revision
4410 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4411 issue those instructions unless instructed to do so by
4413 if (ISA_HAS_BRANCHLIKELY
4414 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4415 && !(TUNE_MIPS5500 || TUNE_SB1))
4416 target_flags |= MASK_BRANCHLIKELY;
4418 target_flags &= ~MASK_BRANCHLIKELY;
4420 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4421 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4423 /* The effect of -mabicalls isn't defined for the EABI. */
4424 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4426 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4427 target_flags &= ~MASK_ABICALLS;
4430 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4431 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4432 /* ??? -non_shared turns off pic code generation, but this is not
4434 if (TARGET_ABICALLS)
4437 if (mips_section_threshold > 0)
4438 warning ("-G is incompatible with PIC code which is the default");
4441 /* The MIPS and SGI o32 assemblers expect small-data variables to
4442 be declared before they are used. Although we once had code to
4443 do this, it was very invasive and fragile. It no longer seems
4444 worth the effort. */
4445 if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
4446 mips_section_threshold = 0;
4448 /* We switch to small data sections using ".section", which the native
4449 o32 irix assemblers don't understand. Disable -G accordingly.
4450 We must do this regardless of command-line options since otherwise
4451 the compiler would abort. */
4452 if (!targetm.have_named_sections)
4453 mips_section_threshold = 0;
4455 /* mips_split_addresses is a half-way house between explicit
4456 relocations and the traditional assembler macros. It can
4457 split absolute 32-bit symbolic constants into a high/lo_sum
4458 pair but uses macros for other sorts of access.
4460 Like explicit relocation support for REL targets, it relies
4461 on GNU extensions in the assembler and the linker.
4463 Although this code should work for -O0, it has traditionally
4464 been treated as an optimization. */
4465 if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4466 && optimize && !flag_pic
4467 && !ABI_HAS_64BIT_SYMBOLS)
4468 mips_split_addresses = 1;
4470 mips_split_addresses = 0;
4472 /* Explicit relocations for "old" ABIs are a GNU extension. Unless
4473 the user has said otherwise, assume that they are not available
4474 with assemblers other than gas. */
4475 if (!TARGET_NEWABI && !TARGET_GAS
4476 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4477 target_flags &= ~MASK_EXPLICIT_RELOCS;
4479 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4480 faster code, but at the expense of more nops. Enable it at -O3 and
4482 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4483 target_flags |= MASK_VR4130_ALIGN;
4485 /* When compiling for the mips16, we can not use floating point. We
4486 record the original hard float value in mips16_hard_float. */
4489 if (TARGET_SOFT_FLOAT)
4490 mips16_hard_float = 0;
4492 mips16_hard_float = 1;
4493 target_flags |= MASK_SOFT_FLOAT;
4495 /* Don't run the scheduler before reload, since it tends to
4496 increase register pressure. */
4497 flag_schedule_insns = 0;
4499 /* Silently disable -mexplicit-relocs since it doesn't apply
4500 to mips16 code. Even so, it would overly pedantic to warn
4501 about "-mips16 -mexplicit-relocs", especially given that
4502 we use a %gprel() operator. */
4503 target_flags &= ~MASK_EXPLICIT_RELOCS;
4506 /* When using explicit relocs, we call dbr_schedule from within
4508 if (TARGET_EXPLICIT_RELOCS)
4510 mips_flag_delayed_branch = flag_delayed_branch;
4511 flag_delayed_branch = 0;
4514 #ifdef MIPS_TFMODE_FORMAT
4515 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4518 mips_print_operand_punct['?'] = 1;
4519 mips_print_operand_punct['#'] = 1;
4520 mips_print_operand_punct['/'] = 1;
4521 mips_print_operand_punct['&'] = 1;
4522 mips_print_operand_punct['!'] = 1;
4523 mips_print_operand_punct['*'] = 1;
4524 mips_print_operand_punct['@'] = 1;
4525 mips_print_operand_punct['.'] = 1;
4526 mips_print_operand_punct['('] = 1;
4527 mips_print_operand_punct[')'] = 1;
4528 mips_print_operand_punct['['] = 1;
4529 mips_print_operand_punct[']'] = 1;
4530 mips_print_operand_punct['<'] = 1;
4531 mips_print_operand_punct['>'] = 1;
4532 mips_print_operand_punct['{'] = 1;
4533 mips_print_operand_punct['}'] = 1;
4534 mips_print_operand_punct['^'] = 1;
4535 mips_print_operand_punct['$'] = 1;
4536 mips_print_operand_punct['+'] = 1;
4537 mips_print_operand_punct['~'] = 1;
4539 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4540 mips_char_to_class['t'] = T_REG;
4541 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4542 mips_char_to_class['h'] = HI_REG;
4543 mips_char_to_class['l'] = LO_REG;
4544 mips_char_to_class['x'] = MD_REGS;
4545 mips_char_to_class['b'] = ALL_REGS;
4546 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4547 TARGET_MIPS16 ? M16_NA_REGS :
4549 mips_char_to_class['e'] = LEA_REGS;
4550 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4551 mips_char_to_class['y'] = GR_REGS;
4552 mips_char_to_class['z'] = ST_REGS;
4553 mips_char_to_class['B'] = COP0_REGS;
4554 mips_char_to_class['C'] = COP2_REGS;
4555 mips_char_to_class['D'] = COP3_REGS;
4557 /* Set up array to map GCC register number to debug register number.
4558 Ignore the special purpose register numbers. */
4560 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4561 mips_dbx_regno[i] = -1;
4563 start = GP_DBX_FIRST - GP_REG_FIRST;
4564 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4565 mips_dbx_regno[i] = i + start;
4567 start = FP_DBX_FIRST - FP_REG_FIRST;
4568 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4569 mips_dbx_regno[i] = i + start;
4571 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4572 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4574 /* Set up array giving whether a given register can hold a given mode. */
4576 for (mode = VOIDmode;
4577 mode != MAX_MACHINE_MODE;
4578 mode = (enum machine_mode) ((int)mode + 1))
4580 register int size = GET_MODE_SIZE (mode);
4581 register enum mode_class class = GET_MODE_CLASS (mode);
4583 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4590 temp = (regno == FPSW_REGNUM);
4592 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4593 || FP_REG_P (regno));
4596 else if (GP_REG_P (regno))
4597 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4599 else if (FP_REG_P (regno))
4600 temp = ((regno % FP_INC) == 0)
4601 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
4602 && size <= UNITS_PER_FPVALUE)
4603 /* Allow integer modes that fit into a single
4604 register. We need to put integers into FPRs
4605 when using instructions like cvt and trunc. */
4606 || (class == MODE_INT && size <= UNITS_PER_FPREG)
4607 /* Allow TFmode for CCmode reloads. */
4608 || (ISA_HAS_8CC && mode == TFmode));
4610 else if (MD_REG_P (regno))
4611 temp = (INTEGRAL_MODE_P (mode)
4612 && (size <= UNITS_PER_WORD
4613 || (regno == MD_REG_FIRST
4614 && size == 2 * UNITS_PER_WORD)));
4616 else if (ALL_COP_REG_P (regno))
4617 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4621 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4625 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4626 initialized yet, so we can't use that here. */
4627 gpr_mode = TARGET_64BIT ? DImode : SImode;
4629 /* Provide default values for align_* for 64-bit targets. */
4630 if (TARGET_64BIT && !TARGET_MIPS16)
4632 if (align_loops == 0)
4634 if (align_jumps == 0)
4636 if (align_functions == 0)
4637 align_functions = 8;
4640 /* Function to allocate machine-dependent function status. */
4641 init_machine_status = &mips_init_machine_status;
4643 if (ABI_HAS_64BIT_SYMBOLS)
4645 if (TARGET_EXPLICIT_RELOCS)
4647 mips_split_p[SYMBOL_64_HIGH] = true;
4648 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4649 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4651 mips_split_p[SYMBOL_64_MID] = true;
4652 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4653 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4655 mips_split_p[SYMBOL_64_LOW] = true;
4656 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4657 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
4659 mips_split_p[SYMBOL_GENERAL] = true;
4660 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4665 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
4667 mips_split_p[SYMBOL_GENERAL] = true;
4668 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
4669 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4675 /* The high part is provided by a pseudo copy of $gp. */
4676 mips_split_p[SYMBOL_SMALL_DATA] = true;
4677 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
4680 if (TARGET_EXPLICIT_RELOCS)
4682 /* Small data constants are kept whole until after reload,
4683 then lowered by mips_rewrite_small_data. */
4684 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
4686 mips_split_p[SYMBOL_GOT_LOCAL] = true;
4689 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
4690 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
4694 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
4695 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
4700 /* The HIGH and LO_SUM are matched by special .md patterns. */
4701 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
4703 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
4704 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
4705 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
4707 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
4708 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
4709 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
4714 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
4716 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
4717 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
4723 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
4724 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
4725 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
4728 /* Default to working around R4000 errata only if the processor
4729 was selected explicitly. */
4730 if ((target_flags_explicit & MASK_FIX_R4000) == 0
4731 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
4732 target_flags |= MASK_FIX_R4000;
4734 /* Default to working around R4400 errata only if the processor
4735 was selected explicitly. */
4736 if ((target_flags_explicit & MASK_FIX_R4400) == 0
4737 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
4738 target_flags |= MASK_FIX_R4400;
4741 /* Implement CONDITIONAL_REGISTER_USAGE. */
4744 mips_conditional_register_usage (void)
4746 if (!TARGET_HARD_FLOAT)
4750 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
4751 fixed_regs[regno] = call_used_regs[regno] = 1;
4752 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4753 fixed_regs[regno] = call_used_regs[regno] = 1;
4755 else if (! ISA_HAS_8CC)
4759 /* We only have a single condition code register. We
4760 implement this by hiding all the condition code registers,
4761 and generating RTL that refers directly to ST_REG_FIRST. */
4762 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4763 fixed_regs[regno] = call_used_regs[regno] = 1;
4765 /* In mips16 mode, we permit the $t temporary registers to be used
4766 for reload. We prohibit the unused $s registers, since they
4767 are caller saved, and saving them via a mips16 register would
4768 probably waste more time than just reloading the value. */
4771 fixed_regs[18] = call_used_regs[18] = 1;
4772 fixed_regs[19] = call_used_regs[19] = 1;
4773 fixed_regs[20] = call_used_regs[20] = 1;
4774 fixed_regs[21] = call_used_regs[21] = 1;
4775 fixed_regs[22] = call_used_regs[22] = 1;
4776 fixed_regs[23] = call_used_regs[23] = 1;
4777 fixed_regs[26] = call_used_regs[26] = 1;
4778 fixed_regs[27] = call_used_regs[27] = 1;
4779 fixed_regs[30] = call_used_regs[30] = 1;
4781 /* fp20-23 are now caller saved. */
4782 if (mips_abi == ABI_64)
4785 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
4786 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4788 /* Odd registers from fp21 to fp31 are now caller saved. */
4789 if (mips_abi == ABI_N32)
4792 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
4793 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4797 /* Allocate a chunk of memory for per-function machine-dependent data. */
4798 static struct machine_function *
4799 mips_init_machine_status (void)
4801 return ((struct machine_function *)
4802 ggc_alloc_cleared (sizeof (struct machine_function)));
4805 /* On the mips16, we want to allocate $24 (T_REG) before other
4806 registers for instructions for which it is possible. This helps
4807 avoid shuffling registers around in order to set up for an xor,
4808 encouraging the compiler to use a cmp instead. */
4811 mips_order_regs_for_local_alloc (void)
4815 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4816 reg_alloc_order[i] = i;
4820 /* It really doesn't matter where we put register 0, since it is
4821 a fixed register anyhow. */
4822 reg_alloc_order[0] = 24;
4823 reg_alloc_order[24] = 0;
4828 /* The MIPS debug format wants all automatic variables and arguments
4829 to be in terms of the virtual frame pointer (stack pointer before
4830 any adjustment in the function), while the MIPS 3.0 linker wants
4831 the frame pointer to be the stack pointer after the initial
4832 adjustment. So, we do the adjustment here. The arg pointer (which
4833 is eliminated) points to the virtual frame pointer, while the frame
4834 pointer (which may be eliminated) points to the stack pointer after
4835 the initial adjustments. */
4838 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
4840 rtx offset2 = const0_rtx;
4841 rtx reg = eliminate_constant_term (addr, &offset2);
4844 offset = INTVAL (offset2);
4846 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4847 || reg == hard_frame_pointer_rtx)
4849 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
4850 ? compute_frame_size (get_frame_size ())
4851 : cfun->machine->frame.total_size;
4853 /* MIPS16 frame is smaller */
4854 if (frame_pointer_needed && TARGET_MIPS16)
4855 frame_size -= cfun->machine->frame.args_size;
4857 offset = offset - frame_size;
4860 /* sdbout_parms does not want this to crash for unrecognized cases. */
4862 else if (reg != arg_pointer_rtx)
4863 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
4870 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
4872 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4873 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4874 'h' OP is HIGH, prints %hi(X),
4875 'd' output integer constant in decimal,
4876 'z' if the operand is 0, use $0 instead of normal operand.
4877 'D' print second part of double-word register or memory operand.
4878 'L' print low-order register of double-word register operand.
4879 'M' print high-order register of double-word register operand.
4880 'C' print part of opcode for a branch condition.
4881 'F' print part of opcode for a floating-point branch condition.
4882 'N' print part of opcode for a branch condition, inverted.
4883 'W' print part of opcode for a floating-point branch condition, inverted.
4884 'B' print 'z' for EQ, 'n' for NE
4885 'b' print 'n' for EQ, 'z' for NE
4886 'T' print 'f' for EQ, 't' for NE
4887 't' print 't' for EQ, 'f' for NE
4888 'Z' print register and a comma, but print nothing for $fcc0
4889 'R' print the reloc associated with LO_SUM
4891 The punctuation characters are:
4893 '(' Turn on .set noreorder
4894 ')' Turn on .set reorder
4895 '[' Turn on .set noat
4897 '<' Turn on .set nomacro
4898 '>' Turn on .set macro
4899 '{' Turn on .set volatile (not GAS)
4900 '}' Turn on .set novolatile (not GAS)
4901 '&' Turn on .set noreorder if filling delay slots
4902 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4903 '!' Turn on .set nomacro if filling delay slots
4904 '#' Print nop if in a .set noreorder section.
4905 '/' Like '#', but does nothing within a delayed branch sequence
4906 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4907 '@' Print the name of the assembler temporary register (at or $1).
4908 '.' Print the name of the register with a hard-wired zero (zero or $0).
4909 '^' Print the name of the pic call-through register (t9 or $25).
4910 '$' Print the name of the stack pointer register (sp or $29).
4911 '+' Print the name of the gp register (usually gp or $28).
4912 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
4915 print_operand (FILE *file, rtx op, int letter)
4917 register enum rtx_code code;
4919 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
4924 if (mips_branch_likely)
4929 fputs (reg_names [GP_REG_FIRST + 1], file);
4933 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
4937 fputs (reg_names [GP_REG_FIRST + 0], file);
4941 fputs (reg_names[STACK_POINTER_REGNUM], file);
4945 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
4949 if (final_sequence != 0 && set_noreorder++ == 0)
4950 fputs (".set\tnoreorder\n\t", file);
4954 if (final_sequence != 0)
4956 if (set_noreorder++ == 0)
4957 fputs (".set\tnoreorder\n\t", file);
4959 if (set_nomacro++ == 0)
4960 fputs (".set\tnomacro\n\t", file);
4965 if (final_sequence != 0 && set_nomacro++ == 0)
4966 fputs ("\n\t.set\tnomacro", file);
4970 if (set_noreorder != 0)
4971 fputs ("\n\tnop", file);
4975 /* Print an extra newline so that the delayed insn is separated
4976 from the following ones. This looks neater and is consistent
4977 with non-nop delayed sequences. */
4978 if (set_noreorder != 0 && final_sequence == 0)
4979 fputs ("\n\tnop\n", file);
4983 if (set_noreorder++ == 0)
4984 fputs (".set\tnoreorder\n\t", file);
4988 if (set_noreorder == 0)
4989 error ("internal error: %%) found without a %%( in assembler pattern");
4991 else if (--set_noreorder == 0)
4992 fputs ("\n\t.set\treorder", file);
4997 if (set_noat++ == 0)
4998 fputs (".set\tnoat\n\t", file);
5003 error ("internal error: %%] found without a %%[ in assembler pattern");
5004 else if (--set_noat == 0)
5005 fputs ("\n\t.set\tat", file);
5010 if (set_nomacro++ == 0)
5011 fputs (".set\tnomacro\n\t", file);
5015 if (set_nomacro == 0)
5016 error ("internal error: %%> found without a %%< in assembler pattern");
5017 else if (--set_nomacro == 0)
5018 fputs ("\n\t.set\tmacro", file);
5023 if (set_volatile++ == 0)
5024 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5028 if (set_volatile == 0)
5029 error ("internal error: %%} found without a %%{ in assembler pattern");
5030 else if (--set_volatile == 0)
5031 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5037 if (align_labels_log > 0)
5038 ASM_OUTPUT_ALIGN (file, align_labels_log);
5043 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5052 error ("PRINT_OPERAND null pointer");
5056 code = GET_CODE (op);
5061 case EQ: fputs ("eq", file); break;
5062 case NE: fputs ("ne", file); break;
5063 case GT: fputs ("gt", file); break;
5064 case GE: fputs ("ge", file); break;
5065 case LT: fputs ("lt", file); break;
5066 case LE: fputs ("le", file); break;
5067 case GTU: fputs ("gtu", file); break;
5068 case GEU: fputs ("geu", file); break;
5069 case LTU: fputs ("ltu", file); break;
5070 case LEU: fputs ("leu", file); break;
5072 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5075 else if (letter == 'N')
5078 case EQ: fputs ("ne", file); break;
5079 case NE: fputs ("eq", file); break;
5080 case GT: fputs ("le", file); break;
5081 case GE: fputs ("lt", file); break;
5082 case LT: fputs ("ge", file); break;
5083 case LE: fputs ("gt", file); break;
5084 case GTU: fputs ("leu", file); break;
5085 case GEU: fputs ("ltu", file); break;
5086 case LTU: fputs ("geu", file); break;
5087 case LEU: fputs ("gtu", file); break;
5089 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5092 else if (letter == 'F')
5095 case EQ: fputs ("c1f", file); break;
5096 case NE: fputs ("c1t", file); break;
5098 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5101 else if (letter == 'W')
5104 case EQ: fputs ("c1t", file); break;
5105 case NE: fputs ("c1f", file); break;
5107 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5110 else if (letter == 'h')
5112 if (GET_CODE (op) == HIGH)
5115 print_operand_reloc (file, op, mips_hi_relocs);
5118 else if (letter == 'R')
5119 print_operand_reloc (file, op, mips_lo_relocs);
5121 else if (letter == 'Z')
5123 register int regnum;
5128 regnum = REGNO (op);
5129 if (! ST_REG_P (regnum))
5132 if (regnum != ST_REG_FIRST)
5133 fprintf (file, "%s,", reg_names[regnum]);
5136 else if (code == REG || code == SUBREG)
5138 register int regnum;
5141 regnum = REGNO (op);
5143 regnum = true_regnum (op);
5145 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5146 || (letter == 'L' && WORDS_BIG_ENDIAN)
5150 fprintf (file, "%s", reg_names[regnum]);
5153 else if (code == MEM)
5156 output_address (plus_constant (XEXP (op, 0), 4));
5158 output_address (XEXP (op, 0));
5161 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5162 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5164 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5165 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5167 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5168 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5170 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5171 fputs (reg_names[GP_REG_FIRST], file);
5173 else if (letter == 'd' || letter == 'x' || letter == 'X')
5174 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5176 else if (letter == 'B')
5177 fputs (code == EQ ? "z" : "n", file);
5178 else if (letter == 'b')
5179 fputs (code == EQ ? "n" : "z", file);
5180 else if (letter == 'T')
5181 fputs (code == EQ ? "f" : "t", file);
5182 else if (letter == 't')
5183 fputs (code == EQ ? "t" : "f", file);
5185 else if (CONST_GP_P (op))
5186 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5189 output_addr_const (file, op);
5193 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5194 RELOCS is the array of relocations to use. */
5197 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5199 enum mips_symbol_type symbol_type;
5202 HOST_WIDE_INT offset;
5204 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5205 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5207 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5208 mips_split_const (op, &base, &offset);
5209 if (UNSPEC_ADDRESS_P (base))
5210 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5212 fputs (relocs[symbol_type], file);
5213 output_addr_const (file, op);
5214 for (p = relocs[symbol_type]; *p != 0; p++)
5219 /* Output address operand X to FILE. */
5222 print_operand_address (FILE *file, rtx x)
5224 struct mips_address_info addr;
5226 if (mips_classify_address (&addr, x, word_mode, true))
5230 print_operand (file, addr.offset, 0);
5231 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5234 case ADDRESS_LO_SUM:
5235 print_operand (file, addr.offset, 'R');
5236 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5239 case ADDRESS_CONST_INT:
5240 case ADDRESS_SYMBOLIC:
5241 output_addr_const (file, x);
5247 /* Target hook for assembling integer objects. It appears that the Irix
5248 6 assembler can't handle 64-bit decimal integers, so avoid printing
5249 such an integer here. */
5252 mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
5254 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5256 fputs ("\t.dword\t", asm_out_file);
5257 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5258 output_addr_const (asm_out_file, x);
5260 print_operand (asm_out_file, x, 'X');
5261 fputc ('\n', asm_out_file);
5264 return default_assemble_integer (x, size, aligned_p);
5267 /* When using assembler macros, keep track of all of small-data externs
5268 so that mips_file_end can emit the appropriate declarations for them.
5270 In most cases it would be safe (though pointless) to emit .externs
5271 for other symbols too. One exception is when an object is within
5272 the -G limit but declared by the user to be in a section other
5273 than .sbss or .sdata. */
5276 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5278 register struct extern_list *p;
5280 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5282 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5283 p->next = extern_head;
5285 p->size = int_size_in_bytes (TREE_TYPE (decl));
5289 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5291 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5292 p->next = extern_head;
5303 irix_output_external_libcall (rtx fun)
5305 register struct extern_list *p;
5307 if (mips_abi == ABI_32)
5309 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5310 p->next = extern_head;
5311 p->name = XSTR (fun, 0);
5318 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5319 put out a MIPS ECOFF file and a stab. */
5322 mips_output_filename (FILE *stream, const char *name)
5324 char ltext_label_name[100];
5326 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5328 if (write_symbols == DWARF2_DEBUG)
5330 else if (mips_output_filename_first_time)
5332 mips_output_filename_first_time = 0;
5334 current_function_file = name;
5335 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5336 /* This tells mips-tfile that stabs will follow. */
5337 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5338 fprintf (stream, "\t#@stabs\n");
5341 else if (write_symbols == DBX_DEBUG)
5343 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5344 fprintf (stream, "%s", ASM_STABS_OP);
5345 output_quoted_string (stream, name);
5346 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5349 else if (name != current_function_file
5350 && strcmp (name, current_function_file) != 0)
5353 current_function_file = name;
5354 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5358 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5359 as well as a .loc, since it is possible that MIPS ECOFF might not be
5360 able to represent the location for inlines that come from a different
5364 mips_output_lineno (FILE *stream, int line)
5366 if (write_symbols == DBX_DEBUG)
5369 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5370 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5371 LOCAL_LABEL_PREFIX, sym_lineno);
5375 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
5376 LABEL_AFTER_LOC (stream);
5380 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5381 that should be written before the opening quote, such as "\t.ascii\t"
5382 for real string data or "\t# " for a comment. */
5385 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5390 register const unsigned char *string =
5391 (const unsigned char *)string_param;
5393 fprintf (stream, "%s\"", prefix);
5394 for (i = 0; i < len; i++)
5396 register int c = string[i];
5402 putc ('\\', stream);
5407 case TARGET_NEWLINE:
5408 fputs ("\\n", stream);
5410 && (((c = string[i+1]) >= '\040' && c <= '~')
5411 || c == TARGET_TAB))
5412 cur_pos = 32767; /* break right here */
5418 fputs ("\\t", stream);
5423 fputs ("\\f", stream);
5428 fputs ("\\b", stream);
5433 fputs ("\\r", stream);
5438 if (c >= ' ' && c < 0177)
5445 fprintf (stream, "\\%03o", c);
5450 if (cur_pos > 72 && i+1 < len)
5453 fprintf (stream, "\"\n%s\"", prefix);
5456 fprintf (stream, "\"\n");
5459 /* Implement TARGET_ASM_FILE_START. */
5462 mips_file_start (void)
5464 default_file_start ();
5466 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5467 inside of a .set noreorder section jumps to a label outside of the .set
5468 noreorder section. Revision 2.20 just set nobopt silently rather than
5471 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5472 fprintf (asm_out_file, "\t.set\tnobopt\n");
5476 #if defined(OBJECT_FORMAT_ELF) && !TARGET_IRIX
5477 /* Generate a special section to describe the ABI switches used to
5478 produce the resultant binary. This used to be done by the assembler
5479 setting bits in the ELF header's flags field, but we have run out of
5480 bits. GDB needs this information in order to be able to correctly
5481 debug these binaries. See the function mips_gdbarch_init() in
5482 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5483 causes unnecessary IRIX 6 ld warnings. */
5484 const char * abi_string = NULL;
5488 case ABI_32: abi_string = "abi32"; break;
5489 case ABI_N32: abi_string = "abiN32"; break;
5490 case ABI_64: abi_string = "abi64"; break;
5491 case ABI_O64: abi_string = "abiO64"; break;
5492 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5496 /* Note - we use fprintf directly rather than called named_section()
5497 because in this way we can avoid creating an allocated section. We
5498 do not want this section to take up any space in the running
5500 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5502 /* There is no ELF header flag to distinguish long32 forms of the
5503 EABI from long64 forms. Emit a special section to help tools
5505 if (mips_abi == ABI_EABI)
5506 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5507 TARGET_LONG64 ? 64 : 32);
5509 /* Restore the default section. */
5510 fprintf (asm_out_file, "\t.previous\n");
5514 /* Generate the pseudo ops that System V.4 wants. */
5515 #ifndef ABICALLS_ASM_OP
5516 #define ABICALLS_ASM_OP "\t.abicalls"
5518 if (TARGET_ABICALLS)
5519 /* ??? but do not want this (or want pic0) if -non-shared? */
5520 fprintf (asm_out_file, "%s\n", ABICALLS_ASM_OP);
5523 fprintf (asm_out_file, "\t.set\tmips16\n");
5525 if (flag_verbose_asm)
5526 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5528 mips_section_threshold, mips_arch_info->name, mips_isa);
5531 #ifdef BSS_SECTION_ASM_OP
5532 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5533 in the use of sbss. */
5536 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5537 unsigned HOST_WIDE_INT size, int align)
5539 extern tree last_assemble_variable_decl;
5541 if (mips_in_small_data_p (decl))
5542 named_section (0, ".sbss", 0);
5545 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5546 last_assemble_variable_decl = decl;
5547 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5548 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5552 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5553 .externs for any small-data variables that turned out to be external. */
5556 mips_file_end (void)
5559 struct extern_list *p;
5563 fputs ("\n", asm_out_file);
5565 for (p = extern_head; p != 0; p = p->next)
5567 name_tree = get_identifier (p->name);
5569 /* Positively ensure only one .extern for any given symbol. */
5570 if (!TREE_ASM_WRITTEN (name_tree)
5571 && TREE_SYMBOL_REFERENCED (name_tree))
5573 TREE_ASM_WRITTEN (name_tree) = 1;
5574 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5575 `.global name .text' directive for every used but
5576 undefined function. If we don't, the linker may perform
5577 an optimization (skipping over the insns that set $gp)
5578 when it is unsafe. */
5579 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5581 fputs ("\t.globl ", asm_out_file);
5582 assemble_name (asm_out_file, p->name);
5583 fputs (" .text\n", asm_out_file);
5587 fputs ("\t.extern\t", asm_out_file);
5588 assemble_name (asm_out_file, p->name);
5589 fprintf (asm_out_file, ", %d\n", p->size);
5596 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as
5597 the elfos.h version, but we also need to handle -muninit-const-in-rodata
5598 and the limitations of the SGI o32 assembler. */
5601 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5602 unsigned HOST_WIDE_INT size,
5605 /* If the target wants uninitialized const declarations in
5606 .rdata then don't put them in .comm. */
5607 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5608 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5609 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5611 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5612 targetm.asm_out.globalize_label (stream, name);
5614 readonly_data_section ();
5615 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5616 mips_declare_object (stream, name, "",
5617 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5621 /* The SGI o32 assembler doesn't accept an alignment. */
5622 mips_declare_common_object (stream, name, "\n\t.comm\t",
5623 size, align, !TARGET_SGI_O32_AS);
5626 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5627 NAME is the name of the object and ALIGN is the required alignment
5628 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5629 alignment argument. */
5632 mips_declare_common_object (FILE *stream, const char *name,
5633 const char *init_string,
5634 unsigned HOST_WIDE_INT size,
5635 unsigned int align, bool takes_alignment_p)
5637 if (!takes_alignment_p)
5639 size += (align / BITS_PER_UNIT) - 1;
5640 size -= size % (align / BITS_PER_UNIT);
5641 mips_declare_object (stream, name, init_string,
5642 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5645 mips_declare_object (stream, name, init_string,
5646 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5647 size, align / BITS_PER_UNIT);
5650 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5651 macros, mark the symbol as written so that mips_file_end won't emit an
5652 .extern for it. STREAM is the output file, NAME is the name of the
5653 symbol, INIT_STRING is the string that should be written before the
5654 symbol and FINAL_STRING is the string that should be written after it.
5655 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5658 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5659 const char *final_string, ...)
5663 fputs (init_string, stream);
5664 assemble_name (stream, name);
5665 va_start (ap, final_string);
5666 vfprintf (stream, final_string, ap);
5669 if (!TARGET_EXPLICIT_RELOCS)
5671 tree name_tree = get_identifier (name);
5672 TREE_ASM_WRITTEN (name_tree) = 1;
5676 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5677 extern int size_directive_output;
5679 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5680 definitions except that it uses mips_declare_object() to emit the label. */
5683 mips_declare_object_name (FILE *stream, const char *name,
5684 tree decl ATTRIBUTE_UNUSED)
5686 if (!TARGET_SGI_O32_AS)
5688 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5689 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5692 size_directive_output = 0;
5693 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5697 size_directive_output = 1;
5698 size = int_size_in_bytes (TREE_TYPE (decl));
5699 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5703 mips_declare_object (stream, name, "", ":\n", 0);
5706 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5709 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5713 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5714 if (!TARGET_SGI_O32_AS
5715 && !flag_inhibit_size_directive
5716 && DECL_SIZE (decl) != 0
5717 && !at_end && top_level
5718 && DECL_INITIAL (decl) == error_mark_node
5719 && !size_directive_output)
5723 size_directive_output = 1;
5724 size = int_size_in_bytes (TREE_TYPE (decl));
5725 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5730 /* Return true if X is a small data address that can be rewritten
5734 mips_rewrite_small_data_p (rtx x)
5736 enum mips_symbol_type symbol_type;
5738 return (TARGET_EXPLICIT_RELOCS
5739 && mips_symbolic_constant_p (x, &symbol_type)
5740 && symbol_type == SYMBOL_SMALL_DATA);
5744 /* A for_each_rtx callback for small_data_pattern. */
5747 small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5749 if (GET_CODE (*loc) == LO_SUM)
5752 return mips_rewrite_small_data_p (*loc);
5755 /* Return true if OP refers to small data symbols directly, not through
5759 small_data_pattern (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5761 return (GET_CODE (op) != SEQUENCE
5762 && for_each_rtx (&op, small_data_pattern_1, 0));
5765 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
5768 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5770 if (mips_rewrite_small_data_p (*loc))
5771 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
5773 if (GET_CODE (*loc) == LO_SUM)
5779 /* If possible, rewrite OP so that it refers to small data using
5780 explicit relocations. */
5783 mips_rewrite_small_data (rtx op)
5785 op = copy_insn (op);
5786 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
5790 /* Return true if the current function has an insn that implicitly
5794 mips_function_has_gp_insn (void)
5796 /* Don't bother rechecking if we found one last time. */
5797 if (!cfun->machine->has_gp_insn_p)
5801 push_topmost_sequence ();
5802 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5804 && GET_CODE (PATTERN (insn)) != USE
5805 && GET_CODE (PATTERN (insn)) != CLOBBER
5806 && (get_attr_got (insn) != GOT_UNSET
5807 || small_data_pattern (PATTERN (insn), VOIDmode)))
5809 pop_topmost_sequence ();
5811 cfun->machine->has_gp_insn_p = (insn != 0);
5813 return cfun->machine->has_gp_insn_p;
5817 /* Return the register that should be used as the global pointer
5818 within this function. Return 0 if the function doesn't need
5819 a global pointer. */
5822 mips_global_pointer (void)
5826 /* $gp is always available in non-abicalls code. */
5827 if (!TARGET_ABICALLS)
5828 return GLOBAL_POINTER_REGNUM;
5830 /* We must always provide $gp when it is used implicitly. */
5831 if (!TARGET_EXPLICIT_RELOCS)
5832 return GLOBAL_POINTER_REGNUM;
5834 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
5836 if (current_function_profile)
5837 return GLOBAL_POINTER_REGNUM;
5839 /* If the function has a nonlocal goto, $gp must hold the correct
5840 global pointer for the target function. */
5841 if (current_function_has_nonlocal_goto)
5842 return GLOBAL_POINTER_REGNUM;
5844 /* If the gp is never referenced, there's no need to initialize it.
5845 Note that reload can sometimes introduce constant pool references
5846 into a function that otherwise didn't need them. For example,
5847 suppose we have an instruction like:
5849 (set (reg:DF R1) (float:DF (reg:SI R2)))
5851 If R2 turns out to be constant such as 1, the instruction may have a
5852 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
5853 using this constant if R2 doesn't get allocated to a register.
5855 In cases like these, reload will have added the constant to the pool
5856 but no instruction will yet refer to it. */
5857 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
5858 && !current_function_uses_const_pool
5859 && !mips_function_has_gp_insn ())
5862 /* We need a global pointer, but perhaps we can use a call-clobbered
5863 register instead of $gp. */
5864 if (TARGET_NEWABI && current_function_is_leaf)
5865 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5866 if (!regs_ever_live[regno]
5867 && call_used_regs[regno]
5868 && !fixed_regs[regno]
5869 && regno != PIC_FUNCTION_ADDR_REGNUM)
5872 return GLOBAL_POINTER_REGNUM;
5876 /* Return true if the current function must save REGNO. */
5879 mips_save_reg_p (unsigned int regno)
5881 /* We only need to save $gp for NewABI PIC. */
5882 if (regno == GLOBAL_POINTER_REGNUM)
5883 return (TARGET_ABICALLS && TARGET_NEWABI
5884 && cfun->machine->global_pointer == regno);
5886 /* Check call-saved registers. */
5887 if (regs_ever_live[regno] && !call_used_regs[regno])
5890 /* We need to save the old frame pointer before setting up a new one. */
5891 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
5894 /* We need to save the incoming return address if it is ever clobbered
5895 within the function. */
5896 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
5903 return_type = DECL_RESULT (current_function_decl);
5905 /* $18 is a special case in mips16 code. It may be used to call
5906 a function which returns a floating point value, but it is
5907 marked in call_used_regs. */
5908 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
5911 /* $31 is also a special case. It will be used to copy a return
5912 value into the floating point registers if the return value is
5914 if (regno == GP_REG_FIRST + 31
5915 && mips16_hard_float
5916 && !aggregate_value_p (return_type, current_function_decl)
5917 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
5918 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
5926 /* Return the bytes needed to compute the frame pointer from the current
5927 stack pointer. SIZE is the size (in bytes) of the local variables.
5929 Mips stack frames look like:
5931 Before call After call
5932 +-----------------------+ +-----------------------+
5935 | caller's temps. | | caller's temps. |
5937 +-----------------------+ +-----------------------+
5939 | arguments on stack. | | arguments on stack. |
5941 +-----------------------+ +-----------------------+
5942 | 4 words to save | | 4 words to save |
5943 | arguments passed | | arguments passed |
5944 | in registers, even | | in registers, even |
5945 SP->| if not passed. | VFP->| if not passed. |
5946 +-----------------------+ +-----------------------+
5948 | fp register save |
5950 +-----------------------+
5952 | gp register save |
5954 +-----------------------+
5958 +-----------------------+
5960 | alloca allocations |
5962 +-----------------------+
5964 | GP save for V.4 abi |
5966 +-----------------------+
5968 | arguments on stack |
5970 +-----------------------+
5972 | arguments passed |
5973 | in registers, even |
5974 low SP->| if not passed. |
5975 memory +-----------------------+
5980 compute_frame_size (HOST_WIDE_INT size)
5983 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
5984 HOST_WIDE_INT var_size; /* # bytes that variables take up */
5985 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
5986 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
5987 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
5988 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
5989 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
5990 unsigned int mask; /* mask of saved gp registers */
5991 unsigned int fmask; /* mask of saved fp registers */
5993 cfun->machine->global_pointer = mips_global_pointer ();
5999 var_size = MIPS_STACK_ALIGN (size);
6000 args_size = current_function_outgoing_args_size;
6001 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6003 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6004 functions. If the function has local variables, we're committed
6005 to allocating it anyway. Otherwise reclaim it here. */
6006 if (var_size == 0 && current_function_is_leaf)
6007 cprestore_size = args_size = 0;
6009 /* The MIPS 3.0 linker does not like functions that dynamically
6010 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6011 looks like we are trying to create a second frame pointer to the
6012 function, so allocate some stack space to make it happy. */
6014 if (args_size == 0 && current_function_calls_alloca)
6015 args_size = 4 * UNITS_PER_WORD;
6017 total_size = var_size + args_size + cprestore_size;
6019 /* Calculate space needed for gp registers. */
6020 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6021 if (mips_save_reg_p (regno))
6023 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6024 mask |= 1 << (regno - GP_REG_FIRST);
6027 /* We need to restore these for the handler. */
6028 if (current_function_calls_eh_return)
6033 regno = EH_RETURN_DATA_REGNO (i);
6034 if (regno == INVALID_REGNUM)
6036 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6037 mask |= 1 << (regno - GP_REG_FIRST);
6041 /* This loop must iterate over the same space as its companion in
6042 save_restore_insns. */
6043 for (regno = (FP_REG_LAST - FP_INC + 1);
6044 regno >= FP_REG_FIRST;
6047 if (mips_save_reg_p (regno))
6049 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6050 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6054 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6055 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6057 /* Add in space reserved on the stack by the callee for storing arguments
6058 passed in registers. */
6060 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6062 /* Save other computed information. */
6063 cfun->machine->frame.total_size = total_size;
6064 cfun->machine->frame.var_size = var_size;
6065 cfun->machine->frame.args_size = args_size;
6066 cfun->machine->frame.cprestore_size = cprestore_size;
6067 cfun->machine->frame.gp_reg_size = gp_reg_size;
6068 cfun->machine->frame.fp_reg_size = fp_reg_size;
6069 cfun->machine->frame.mask = mask;
6070 cfun->machine->frame.fmask = fmask;
6071 cfun->machine->frame.initialized = reload_completed;
6072 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6073 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6077 HOST_WIDE_INT offset;
6079 offset = (args_size + cprestore_size + var_size
6080 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6081 cfun->machine->frame.gp_sp_offset = offset;
6082 cfun->machine->frame.gp_save_offset = offset - total_size;
6086 cfun->machine->frame.gp_sp_offset = 0;
6087 cfun->machine->frame.gp_save_offset = 0;
6092 HOST_WIDE_INT offset;
6094 offset = (args_size + cprestore_size + var_size
6095 + gp_reg_rounded + fp_reg_size
6096 - FP_INC * UNITS_PER_FPREG);
6097 cfun->machine->frame.fp_sp_offset = offset;
6098 cfun->machine->frame.fp_save_offset = offset - total_size;
6102 cfun->machine->frame.fp_sp_offset = 0;
6103 cfun->machine->frame.fp_save_offset = 0;
6106 /* Ok, we're done. */
6110 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6111 pointer or argument pointer. TO is either the stack pointer or
6112 hard frame pointer. */
6115 mips_initial_elimination_offset (int from, int to)
6117 HOST_WIDE_INT offset;
6119 compute_frame_size (get_frame_size ());
6121 /* Set OFFSET to the offset from the stack pointer. */
6124 case FRAME_POINTER_REGNUM:
6128 case ARG_POINTER_REGNUM:
6129 offset = cfun->machine->frame.total_size;
6131 offset -= current_function_pretend_args_size;
6138 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6139 offset -= cfun->machine->frame.args_size;
6144 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6145 back to a previous frame. */
6147 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6152 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6155 /* Use FN to save or restore register REGNO. MODE is the register's
6156 mode and OFFSET is the offset of its save slot from the current
6160 mips_save_restore_reg (enum machine_mode mode, int regno,
6161 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6165 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6166 if (!current_function_calls_eh_return)
6167 RTX_UNCHANGING_P (mem) = 1;
6169 fn (gen_rtx_REG (mode, regno), mem);
6173 /* Call FN for each register that is saved by the current function.
6174 SP_OFFSET is the offset of the current stack pointer from the start
6178 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6180 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6182 enum machine_mode fpr_mode;
6183 HOST_WIDE_INT offset;
6186 /* Save registers starting from high to low. The debuggers prefer at least
6187 the return register be stored at func+4, and also it allows us not to
6188 need a nop in the epilog if at least one register is reloaded in
6189 addition to return address. */
6190 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6191 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6192 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6194 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6195 offset -= GET_MODE_SIZE (gpr_mode);
6198 /* This loop must iterate over the same space as its companion in
6199 compute_frame_size. */
6200 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6201 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6202 for (regno = (FP_REG_LAST - FP_INC + 1);
6203 regno >= FP_REG_FIRST;
6205 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6207 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6208 offset -= GET_MODE_SIZE (fpr_mode);
6213 /* If we're generating n32 or n64 abicalls, and the current function
6214 does not use $28 as its global pointer, emit a cplocal directive.
6215 Use pic_offset_table_rtx as the argument to the directive. */
6218 mips_output_cplocal (void)
6220 if (!TARGET_EXPLICIT_RELOCS
6221 && cfun->machine->global_pointer > 0
6222 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6223 output_asm_insn (".cplocal %+", 0);
6226 /* If we're generating n32 or n64 abicalls, emit instructions
6227 to set up the global pointer. */
6230 mips_emit_loadgp (void)
6232 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6234 rtx addr, offset, incoming_address;
6236 addr = XEXP (DECL_RTL (current_function_decl), 0);
6237 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6238 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6239 emit_insn (gen_loadgp (offset, incoming_address));
6240 if (!TARGET_EXPLICIT_RELOCS)
6241 emit_insn (gen_loadgp_blockage ());
6245 /* Set up the stack and frame (if desired) for the function. */
6248 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6251 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6253 /* ??? When is this really needed? At least the GNU assembler does not
6254 need the source filename more than once in the file, beyond what is
6255 emitted by the debug information. */
6257 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6259 #ifdef SDB_DEBUGGING_INFO
6260 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6261 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl), 0);
6264 /* In mips16 mode, we may need to generate a 32 bit to handle
6265 floating point arguments. The linker will arrange for any 32 bit
6266 functions to call this stub, which will then jump to the 16 bit
6268 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6269 && current_function_args_info.fp_code != 0)
6270 build_mips16_function_stub (file);
6272 if (!FUNCTION_NAME_ALREADY_DECLARED)
6274 /* Get the function name the same way that toplev.c does before calling
6275 assemble_start_function. This is needed so that the name used here
6276 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6277 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6279 if (!flag_inhibit_size_directive)
6281 fputs ("\t.ent\t", file);
6282 assemble_name (file, fnname);
6286 assemble_name (file, fnname);
6287 fputs (":\n", file);
6290 if (!flag_inhibit_size_directive)
6292 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6294 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6295 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6296 ", args= " HOST_WIDE_INT_PRINT_DEC
6297 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6298 (reg_names[(frame_pointer_needed)
6299 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6300 ((frame_pointer_needed && TARGET_MIPS16)
6301 ? tsize - cfun->machine->frame.args_size
6303 reg_names[GP_REG_FIRST + 31],
6304 cfun->machine->frame.var_size,
6305 cfun->machine->frame.num_gp,
6306 cfun->machine->frame.num_fp,
6307 cfun->machine->frame.args_size,
6308 cfun->machine->frame.cprestore_size);
6310 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6311 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6312 cfun->machine->frame.mask,
6313 cfun->machine->frame.gp_save_offset);
6314 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6315 cfun->machine->frame.fmask,
6316 cfun->machine->frame.fp_save_offset);
6319 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6320 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6323 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6325 /* Handle the initialization of $gp for SVR4 PIC. */
6326 if (!cfun->machine->all_noreorder_p)
6327 output_asm_insn ("%(.cpload\t%^%)", 0);
6329 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6331 else if (cfun->machine->all_noreorder_p)
6332 output_asm_insn ("%(%<", 0);
6334 /* Tell the assembler which register we're using as the global
6335 pointer. This is needed for thunks, since they can use either
6336 explicit relocs or assembler macros. */
6337 mips_output_cplocal ();
6340 /* Make the last instruction frame related and note that it performs
6341 the operation described by FRAME_PATTERN. */
6344 mips_set_frame_expr (rtx frame_pattern)
6348 insn = get_last_insn ();
6349 RTX_FRAME_RELATED_P (insn) = 1;
6350 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6356 /* Return a frame-related rtx that stores REG at MEM.
6357 REG must be a single register. */
6360 mips_frame_set (rtx mem, rtx reg)
6362 rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6363 RTX_FRAME_RELATED_P (set) = 1;
6368 /* Save register REG to MEM. Make the instruction frame-related. */
6371 mips_save_reg (rtx reg, rtx mem)
6373 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6377 if (mips_split_64bit_move_p (mem, reg))
6378 mips_split_64bit_move (mem, reg);
6380 emit_move_insn (mem, reg);
6382 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6383 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6384 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6389 && REGNO (reg) != GP_REG_FIRST + 31
6390 && !M16_REG_P (REGNO (reg)))
6392 /* Save a non-mips16 register by moving it through a temporary.
6393 We don't need to do this for $31 since there's a special
6394 instruction for it. */
6395 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6396 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6399 emit_move_insn (mem, reg);
6401 mips_set_frame_expr (mips_frame_set (mem, reg));
6406 /* Expand the prologue into a bunch of separate insns. */
6409 mips_expand_prologue (void)
6413 if (cfun->machine->global_pointer > 0)
6414 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6416 size = compute_frame_size (get_frame_size ());
6418 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6419 bytes beforehand; this is enough to cover the register save area
6420 without going out of range. */
6421 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6423 HOST_WIDE_INT step1;
6425 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6426 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6428 GEN_INT (-step1)))) = 1;
6430 mips_for_each_saved_reg (size, mips_save_reg);
6433 /* Allocate the rest of the frame. */
6436 if (SMALL_OPERAND (-size))
6437 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6439 GEN_INT (-size)))) = 1;
6442 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6445 /* There are no instructions to add or subtract registers
6446 from the stack pointer, so use the frame pointer as a
6447 temporary. We should always be using a frame pointer
6448 in this case anyway. */
6449 if (!frame_pointer_needed)
6452 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6453 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6454 hard_frame_pointer_rtx,
6455 MIPS_PROLOGUE_TEMP (Pmode)));
6456 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6459 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6461 MIPS_PROLOGUE_TEMP (Pmode)));
6463 /* Describe the combined effect of the previous instructions. */
6465 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6466 plus_constant (stack_pointer_rtx, -size)));
6470 /* Set up the frame pointer, if we're using one. In mips16 code,
6471 we point the frame pointer ahead of the outgoing argument area.
6472 This should allow more variables & incoming arguments to be
6473 accessed with unextended instructions. */
6474 if (frame_pointer_needed)
6476 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6478 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6480 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6485 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6486 stack_pointer_rtx)) = 1;
6489 /* If generating o32/o64 abicalls, save $gp on the stack. */
6490 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6491 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6493 mips_emit_loadgp ();
6495 /* If we are profiling, make sure no instructions are scheduled before
6496 the call to mcount. */
6498 if (current_function_profile)
6499 emit_insn (gen_blockage ());
6502 /* Do any necessary cleanup after a function to restore stack, frame,
6505 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6508 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6509 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6511 /* Reinstate the normal $gp. */
6512 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6513 mips_output_cplocal ();
6515 if (cfun->machine->all_noreorder_p)
6517 /* Avoid using %>%) since it adds excess whitespace. */
6518 output_asm_insn (".set\tmacro", 0);
6519 output_asm_insn (".set\treorder", 0);
6520 set_noreorder = set_nomacro = 0;
6523 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6527 /* Get the function name the same way that toplev.c does before calling
6528 assemble_start_function. This is needed so that the name used here
6529 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6530 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6531 fputs ("\t.end\t", file);
6532 assemble_name (file, fnname);
6537 /* Emit instructions to restore register REG from slot MEM. */
6540 mips_restore_reg (rtx reg, rtx mem)
6542 /* There's no mips16 instruction to load $31 directly. Load into
6543 $7 instead and adjust the return insn appropriately. */
6544 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6545 reg = gen_rtx_REG (GET_MODE (reg), 7);
6547 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6549 /* Can't restore directly; move through a temporary. */
6550 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6551 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6554 emit_move_insn (reg, mem);
6558 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6559 if this epilogue precedes a sibling call, false if it is for a normal
6560 "epilogue" pattern. */
6563 mips_expand_epilogue (int sibcall_p)
6565 HOST_WIDE_INT step1, step2;
6568 if (!sibcall_p && mips_can_use_return_insn ())
6570 emit_jump_insn (gen_return ());
6574 /* Split the frame into two. STEP1 is the amount of stack we should
6575 deallocate before restoring the registers. STEP2 is the amount we
6576 should deallocate afterwards.
6578 Start off by assuming that no registers need to be restored. */
6579 step1 = cfun->machine->frame.total_size;
6582 /* Work out which register holds the frame address. Account for the
6583 frame pointer offset used by mips16 code. */
6584 if (!frame_pointer_needed)
6585 base = stack_pointer_rtx;
6588 base = hard_frame_pointer_rtx;
6590 step1 -= cfun->machine->frame.args_size;
6593 /* If we need to restore registers, deallocate as much stack as
6594 possible in the second step without going out of range. */
6595 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6597 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6601 /* Set TARGET to BASE + STEP1. */
6607 /* Get an rtx for STEP1 that we can add to BASE. */
6608 adjust = GEN_INT (step1);
6609 if (!SMALL_OPERAND (step1))
6611 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6612 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6615 /* Normal mode code can copy the result straight into $sp. */
6617 target = stack_pointer_rtx;
6619 emit_insn (gen_add3_insn (target, base, adjust));
6622 /* Copy TARGET into the stack pointer. */
6623 if (target != stack_pointer_rtx)
6624 emit_move_insn (stack_pointer_rtx, target);
6626 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6627 implicitly used by all SYMBOL_REFs. We must emit a blockage
6628 insn before restoring it. */
6629 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6630 emit_insn (gen_blockage ());
6632 /* Restore the registers. */
6633 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6636 /* Deallocate the final bit of the frame. */
6638 emit_insn (gen_add3_insn (stack_pointer_rtx,
6642 /* Add in the __builtin_eh_return stack adjustment. We need to
6643 use a temporary in mips16 code. */
6644 if (current_function_calls_eh_return)
6648 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6649 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6650 MIPS_EPILOGUE_TEMP (Pmode),
6651 EH_RETURN_STACKADJ_RTX));
6652 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6655 emit_insn (gen_add3_insn (stack_pointer_rtx,
6657 EH_RETURN_STACKADJ_RTX));
6662 /* The mips16 loads the return address into $7, not $31. */
6663 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6664 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6665 GP_REG_FIRST + 7)));
6667 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6668 GP_REG_FIRST + 31)));
6672 /* Return nonzero if this function is known to have a null epilogue.
6673 This allows the optimizer to omit jumps to jumps if no stack
6677 mips_can_use_return_insn (void)
6681 if (! reload_completed)
6684 if (regs_ever_live[31] || current_function_profile)
6687 return_type = DECL_RESULT (current_function_decl);
6689 /* In mips16 mode, a function which returns a floating point value
6690 needs to arrange to copy the return value into the floating point
6693 && mips16_hard_float
6694 && ! aggregate_value_p (return_type, current_function_decl)
6695 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6696 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6699 if (cfun->machine->frame.initialized)
6700 return cfun->machine->frame.total_size == 0;
6702 return compute_frame_size (get_frame_size ()) == 0;
6705 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6706 in order to avoid duplicating too much logic from elsewhere. */
6709 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6710 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6713 rtx this, temp1, temp2, insn, fnaddr;
6715 /* Pretend to be a post-reload pass while generating rtl. */
6717 reload_completed = 1;
6718 reset_block_changes ();
6720 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6721 for TARGET_NEWABI since the latter is a call-saved register. */
6722 if (TARGET_ABICALLS)
6723 cfun->machine->global_pointer
6724 = REGNO (pic_offset_table_rtx)
6725 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
6727 /* Set up the global pointer for n32 or n64 abicalls. */
6728 mips_emit_loadgp ();
6730 /* We need two temporary registers in some cases. */
6731 temp1 = gen_rtx_REG (Pmode, 2);
6732 temp2 = gen_rtx_REG (Pmode, 3);
6734 /* Find out which register contains the "this" pointer. */
6735 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
6736 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
6738 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
6740 /* Add DELTA to THIS. */
6743 rtx offset = GEN_INT (delta);
6744 if (!SMALL_OPERAND (delta))
6746 emit_move_insn (temp1, offset);
6749 emit_insn (gen_add3_insn (this, this, offset));
6752 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
6753 if (vcall_offset != 0)
6757 /* Set TEMP1 to *THIS. */
6758 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
6760 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
6761 addr = mips_add_offset (temp2, temp1, vcall_offset);
6763 /* Load the offset and add it to THIS. */
6764 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
6765 emit_insn (gen_add3_insn (this, this, temp1));
6768 /* Jump to the target function. Use a sibcall if direct jumps are
6769 allowed, otherwise load the address into a register first. */
6770 fnaddr = XEXP (DECL_RTL (function), 0);
6771 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
6773 /* This is messy. gas treats "la $25,foo" as part of a call
6774 sequence and may allow a global "foo" to be lazily bound.
6775 The general move patterns therefore reject this combination.
6777 In this context, lazy binding would actually be OK for o32 and o64,
6778 but it's still wrong for n32 and n64; see mips_load_call_address.
6779 We must therefore load the address via a temporary register if
6780 mips_dangerous_for_la25_p.
6782 If we jump to the temporary register rather than $25, the assembler
6783 can use the move insn to fill the jump's delay slot. */
6784 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
6785 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6786 mips_load_call_address (temp1, fnaddr, true);
6788 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
6789 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
6790 emit_jump_insn (gen_indirect_jump (temp1));
6794 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
6795 SIBLING_CALL_P (insn) = 1;
6798 /* Run just enough of rest_of_compilation. This sequence was
6799 "borrowed" from alpha.c. */
6800 insn = get_insns ();
6801 insn_locators_initialize ();
6802 split_all_insns_noflow ();
6804 mips16_lay_out_constants ();
6805 shorten_branches (insn);
6806 final_start_function (insn, file, 1);
6807 final (insn, file, 1, 0);
6808 final_end_function ();
6810 /* Clean up the vars set above. Note that final_end_function resets
6811 the global pointer for us. */
6812 reload_completed = 0;
6816 /* Returns nonzero if X contains a SYMBOL_REF. */
6819 symbolic_expression_p (rtx x)
6821 if (GET_CODE (x) == SYMBOL_REF)
6824 if (GET_CODE (x) == CONST)
6825 return symbolic_expression_p (XEXP (x, 0));
6828 return symbolic_expression_p (XEXP (x, 0));
6830 if (ARITHMETIC_P (x))
6831 return (symbolic_expression_p (XEXP (x, 0))
6832 || symbolic_expression_p (XEXP (x, 1)));
6837 /* Choose the section to use for the constant rtx expression X that has
6841 mips_select_rtx_section (enum machine_mode mode, rtx x,
6842 unsigned HOST_WIDE_INT align)
6846 /* In mips16 mode, the constant table always goes in the same section
6847 as the function, so that constants can be loaded using PC relative
6849 function_section (current_function_decl);
6851 else if (TARGET_EMBEDDED_DATA)
6853 /* For embedded applications, always put constants in read-only data,
6854 in order to reduce RAM usage. */
6855 mergeable_constant_section (mode, align, 0);
6859 /* For hosted applications, always put constants in small data if
6860 possible, as this gives the best performance. */
6861 /* ??? Consider using mergeable small data sections. */
6863 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
6864 && mips_section_threshold > 0)
6865 named_section (0, ".sdata", 0);
6866 else if (flag_pic && symbolic_expression_p (x))
6868 if (targetm.have_named_sections)
6869 named_section (0, ".data.rel.ro", 3);
6874 mergeable_constant_section (mode, align, 0);
6878 /* Choose the section to use for DECL. RELOC is true if its value contains
6879 any relocatable expression. */
6882 mips_select_section (tree decl, int reloc,
6883 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
6885 if (targetm.have_named_sections)
6886 default_elf_select_section (decl, reloc, align);
6888 /* The native irix o32 assembler doesn't support named sections. */
6889 default_select_section (decl, reloc, align);
6893 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
6894 access DECL using %gp_rel(...)($gp). */
6897 mips_in_small_data_p (tree decl)
6901 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6904 /* We don't yet generate small-data references for -mabicalls. See related
6905 -G handling in override_options. */
6906 if (TARGET_ABICALLS)
6909 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6913 /* Reject anything that isn't in a known small-data section. */
6914 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6915 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6918 /* If a symbol is defined externally, the assembler will use the
6919 usual -G rules when deciding how to implement macros. */
6920 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
6923 else if (TARGET_EMBEDDED_DATA)
6925 /* Don't put constants into the small data section: we want them
6926 to be in ROM rather than RAM. */
6927 if (TREE_CODE (decl) != VAR_DECL)
6930 if (TREE_READONLY (decl)
6931 && !TREE_SIDE_EFFECTS (decl)
6932 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6936 size = int_size_in_bytes (TREE_TYPE (decl));
6937 return (size > 0 && size <= mips_section_threshold);
6940 /* See whether VALTYPE is a record whose fields should be returned in
6941 floating-point registers. If so, return the number of fields and
6942 list them in FIELDS (which should have two elements). Return 0
6945 For n32 & n64, a structure with one or two fields is returned in
6946 floating-point registers as long as every field has a floating-point
6950 mips_fpr_return_fields (tree valtype, tree *fields)
6958 if (TREE_CODE (valtype) != RECORD_TYPE)
6962 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
6964 if (TREE_CODE (field) != FIELD_DECL)
6967 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
6973 fields[i++] = field;
6979 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
6980 a value in the most significant part of $2/$3 if:
6982 - the target is big-endian;
6984 - the value has a structure or union type (we generalize this to
6985 cover aggregates from other languages too); and
6987 - the structure is not returned in floating-point registers. */
6990 mips_return_in_msb (tree valtype)
6994 return (TARGET_NEWABI
6995 && TARGET_BIG_ENDIAN
6996 && AGGREGATE_TYPE_P (valtype)
6997 && mips_fpr_return_fields (valtype, fields) == 0);
7001 /* Return a composite value in a pair of floating-point registers.
7002 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7003 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7006 For n32 & n64, $f0 always holds the first value and $f2 the second.
7007 Otherwise the values are packed together as closely as possible. */
7010 mips_return_fpr_pair (enum machine_mode mode,
7011 enum machine_mode mode1, HOST_WIDE_INT offset1,
7012 enum machine_mode mode2, HOST_WIDE_INT offset2)
7016 inc = (TARGET_NEWABI ? 2 : FP_INC);
7017 return gen_rtx_PARALLEL
7020 gen_rtx_EXPR_LIST (VOIDmode,
7021 gen_rtx_REG (mode1, FP_RETURN),
7023 gen_rtx_EXPR_LIST (VOIDmode,
7024 gen_rtx_REG (mode2, FP_RETURN + inc),
7025 GEN_INT (offset2))));
7030 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7031 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7032 VALTYPE is null and MODE is the mode of the return value. */
7035 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7036 enum machine_mode mode)
7043 mode = TYPE_MODE (valtype);
7044 unsignedp = TYPE_UNSIGNED (valtype);
7046 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7047 true, we must promote the mode just as PROMOTE_MODE does. */
7048 mode = promote_mode (valtype, mode, &unsignedp, 1);
7050 /* Handle structures whose fields are returned in $f0/$f2. */
7051 switch (mips_fpr_return_fields (valtype, fields))
7054 return gen_rtx_REG (mode, FP_RETURN);
7057 return mips_return_fpr_pair (mode,
7058 TYPE_MODE (TREE_TYPE (fields[0])),
7059 int_byte_position (fields[0]),
7060 TYPE_MODE (TREE_TYPE (fields[1])),
7061 int_byte_position (fields[1]));
7064 /* If a value is passed in the most significant part of a register, see
7065 whether we have to round the mode up to a whole number of words. */
7066 if (mips_return_in_msb (valtype))
7068 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7069 if (size % UNITS_PER_WORD != 0)
7071 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7072 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7077 if (GET_MODE_CLASS (mode) == MODE_FLOAT
7078 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7079 return gen_rtx_REG (mode, FP_RETURN);
7081 /* Handle long doubles for n32 & n64. */
7083 return mips_return_fpr_pair (mode,
7085 DImode, GET_MODE_SIZE (mode) / 2);
7087 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7088 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7089 return mips_return_fpr_pair (mode,
7090 GET_MODE_INNER (mode), 0,
7091 GET_MODE_INNER (mode),
7092 GET_MODE_SIZE (mode) / 2);
7094 return gen_rtx_REG (mode, GP_RETURN);
7097 /* Return nonzero when an argument must be passed by reference. */
7100 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7101 enum machine_mode mode, tree type,
7102 bool named ATTRIBUTE_UNUSED)
7104 if (mips_abi == ABI_EABI)
7108 /* ??? How should SCmode be handled? */
7109 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7112 size = int_size_in_bytes (type);
7113 return size == -1 || size > UNITS_PER_WORD;
7117 /* If we have a variable-sized parameter, we have no choice. */
7118 return targetm.calls.must_pass_in_stack (mode, type);
7122 /* Return the class of registers for which a mode change from FROM to TO
7125 In little-endian mode, the hi-lo registers are numbered backwards,
7126 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
7129 Similarly, when using paired floating-point registers, the first
7130 register holds the low word, regardless of endianness. So in big
7131 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
7134 Also, loading a 32-bit value into a 64-bit floating-point register
7135 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7136 We can't allow 64-bit float registers to change from a 32-bit
7137 mode to a 64-bit mode. */
7140 mips_cannot_change_mode_class (enum machine_mode from,
7141 enum machine_mode to, enum reg_class class)
7143 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7145 if (TARGET_BIG_ENDIAN)
7146 return reg_classes_intersect_p (FP_REGS, class);
7148 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
7149 return reg_classes_intersect_p (HI_REG, class);
7154 /* Return true if X should not be moved directly into register $25.
7155 We need this because many versions of GAS will treat "la $25,foo" as
7156 part of a call sequence and so allow a global "foo" to be lazily bound. */
7159 mips_dangerous_for_la25_p (rtx x)
7161 HOST_WIDE_INT offset;
7163 if (TARGET_EXPLICIT_RELOCS)
7166 mips_split_const (x, &x, &offset);
7167 return global_got_operand (x, VOIDmode);
7170 /* Implement PREFERRED_RELOAD_CLASS. */
7173 mips_preferred_reload_class (rtx x, enum reg_class class)
7175 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7178 if (TARGET_HARD_FLOAT
7179 && FLOAT_MODE_P (GET_MODE (x))
7180 && reg_class_subset_p (FP_REGS, class))
7183 if (reg_class_subset_p (GR_REGS, class))
7186 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7192 /* This function returns the register class required for a secondary
7193 register when copying between one of the registers in CLASS, and X,
7194 using MODE. If IN_P is nonzero, the copy is going from X to the
7195 register, otherwise the register is the source. A return value of
7196 NO_REGS means that no secondary register is required. */
7199 mips_secondary_reload_class (enum reg_class class,
7200 enum machine_mode mode, rtx x, int in_p)
7202 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7206 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7207 regno = true_regnum (x);
7209 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7211 if (mips_dangerous_for_la25_p (x))
7214 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7218 /* Copying from HI or LO to anywhere other than a general register
7219 requires a general register. */
7220 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7222 if (TARGET_MIPS16 && in_p)
7224 /* We can't really copy to HI or LO at all in mips16 mode. */
7227 return gp_reg_p ? NO_REGS : gr_regs;
7229 if (MD_REG_P (regno))
7231 if (TARGET_MIPS16 && ! in_p)
7233 /* We can't really copy to HI or LO at all in mips16 mode. */
7236 return class == gr_regs ? NO_REGS : gr_regs;
7239 /* We can only copy a value to a condition code register from a
7240 floating point register, and even then we require a scratch
7241 floating point register. We can only copy a value out of a
7242 condition code register into a general register. */
7243 if (class == ST_REGS)
7247 return gp_reg_p ? NO_REGS : gr_regs;
7249 if (ST_REG_P (regno))
7253 return class == gr_regs ? NO_REGS : gr_regs;
7256 if (class == FP_REGS)
7258 if (GET_CODE (x) == MEM)
7260 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7263 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7265 /* We can use the l.s and l.d macros to load floating-point
7266 constants. ??? For l.s, we could probably get better
7267 code by returning GR_REGS here. */
7270 else if (gp_reg_p || x == CONST0_RTX (mode))
7272 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7275 else if (FP_REG_P (regno))
7277 /* In this case we can use mov.s or mov.d. */
7282 /* Otherwise, we need to reload through an integer register. */
7287 /* In mips16 mode, going between memory and anything but M16_REGS
7288 requires an M16_REG. */
7291 if (class != M16_REGS && class != M16_NA_REGS)
7299 if (class == M16_REGS || class == M16_NA_REGS)
7308 /* Implement CLASS_MAX_NREGS.
7310 Usually all registers are word-sized. The only supported exception
7311 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7312 registers. A word-based calculation is correct even in that case,
7313 since -msingle-float disallows multi-FPR values. */
7316 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7317 enum machine_mode mode)
7319 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7323 mips_valid_pointer_mode (enum machine_mode mode)
7325 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7329 /* If we can access small data directly (using gp-relative relocation
7330 operators) return the small data pointer, otherwise return null.
7332 For each mips16 function which refers to GP relative symbols, we
7333 use a pseudo register, initialized at the start of the function, to
7334 hold the $gp value. */
7337 mips16_gp_pseudo_reg (void)
7339 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7344 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7345 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
7347 /* We want to initialize this to a value which gcc will believe
7350 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7351 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7352 gen_rtx_CONST (Pmode, unspec));
7353 insn = get_insns ();
7356 push_topmost_sequence ();
7357 /* We need to emit the initialization after the FUNCTION_BEG
7358 note, so that it will be integrated. */
7359 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7360 if (GET_CODE (scan) == NOTE
7361 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7363 if (scan == NULL_RTX)
7364 scan = get_insns ();
7365 insn = emit_insn_after (insn, scan);
7366 pop_topmost_sequence ();
7369 return cfun->machine->mips16_gp_pseudo_rtx;
7372 /* Write out code to move floating point arguments in or out of
7373 general registers. Output the instructions to FILE. FP_CODE is
7374 the code describing which arguments are present (see the comment at
7375 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7376 we are copying from the floating point registers. */
7379 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7385 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7393 gparg = GP_ARG_FIRST;
7394 fparg = FP_ARG_FIRST;
7395 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7399 if ((fparg & 1) != 0)
7401 fprintf (file, "\t%s\t%s,%s\n", s,
7402 reg_names[gparg], reg_names[fparg]);
7404 else if ((f & 3) == 2)
7407 fprintf (file, "\td%s\t%s,%s\n", s,
7408 reg_names[gparg], reg_names[fparg]);
7411 if ((fparg & 1) != 0)
7413 if (TARGET_BIG_ENDIAN)
7414 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7415 reg_names[gparg], reg_names[fparg + 1], s,
7416 reg_names[gparg + 1], reg_names[fparg]);
7418 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7419 reg_names[gparg], reg_names[fparg], s,
7420 reg_names[gparg + 1], reg_names[fparg + 1]);
7433 /* Build a mips16 function stub. This is used for functions which
7434 take arguments in the floating point registers. It is 32 bit code
7435 that moves the floating point args into the general registers, and
7436 then jumps to the 16 bit code. */
7439 build_mips16_function_stub (FILE *file)
7442 char *secname, *stubname;
7443 tree stubid, stubdecl;
7447 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7448 secname = (char *) alloca (strlen (fnname) + 20);
7449 sprintf (secname, ".mips16.fn.%s", fnname);
7450 stubname = (char *) alloca (strlen (fnname) + 20);
7451 sprintf (stubname, "__fn_stub_%s", fnname);
7452 stubid = get_identifier (stubname);
7453 stubdecl = build_decl (FUNCTION_DECL, stubid,
7454 build_function_type (void_type_node, NULL_TREE));
7455 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7457 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7459 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7461 fprintf (file, "%s%s",
7462 need_comma ? ", " : "",
7463 (f & 3) == 1 ? "float" : "double");
7466 fprintf (file, ")\n");
7468 fprintf (file, "\t.set\tnomips16\n");
7469 function_section (stubdecl);
7470 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7472 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7473 within a .ent, and we can not emit another .ent. */
7474 if (!FUNCTION_NAME_ALREADY_DECLARED)
7476 fputs ("\t.ent\t", file);
7477 assemble_name (file, stubname);
7481 assemble_name (file, stubname);
7482 fputs (":\n", file);
7484 /* We don't want the assembler to insert any nops here. */
7485 fprintf (file, "\t.set\tnoreorder\n");
7487 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7489 fprintf (asm_out_file, "\t.set\tnoat\n");
7490 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7491 assemble_name (file, fnname);
7492 fprintf (file, "\n");
7493 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7494 fprintf (asm_out_file, "\t.set\tat\n");
7496 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7497 with one of the mfc1 instructions, because the result is not
7498 available for one instruction, so if the very first instruction
7499 in the function refers to the register, it will see the wrong
7501 fprintf (file, "\tnop\n");
7503 fprintf (file, "\t.set\treorder\n");
7505 if (!FUNCTION_NAME_ALREADY_DECLARED)
7507 fputs ("\t.end\t", file);
7508 assemble_name (file, stubname);
7512 fprintf (file, "\t.set\tmips16\n");
7514 function_section (current_function_decl);
7517 /* We keep a list of functions for which we have already built stubs
7518 in build_mips16_call_stub. */
7522 struct mips16_stub *next;
7527 static struct mips16_stub *mips16_stubs;
7529 /* Build a call stub for a mips16 call. A stub is needed if we are
7530 passing any floating point values which should go into the floating
7531 point registers. If we are, and the call turns out to be to a 32
7532 bit function, the stub will be used to move the values into the
7533 floating point registers before calling the 32 bit function. The
7534 linker will magically adjust the function call to either the 16 bit
7535 function or the 32 bit stub, depending upon where the function call
7536 is actually defined.
7538 Similarly, we need a stub if the return value might come back in a
7539 floating point register.
7541 RETVAL is the location of the return value, or null if this is
7542 a call rather than a call_value. FN is the address of the
7543 function and ARG_SIZE is the size of the arguments. FP_CODE
7544 is the code built by function_arg. This function returns a nonzero
7545 value if it builds the call instruction itself. */
7548 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7552 char *secname, *stubname;
7553 struct mips16_stub *l;
7554 tree stubid, stubdecl;
7558 /* We don't need to do anything if we aren't in mips16 mode, or if
7559 we were invoked with the -msoft-float option. */
7560 if (! TARGET_MIPS16 || ! mips16_hard_float)
7563 /* Figure out whether the value might come back in a floating point
7565 fpret = (retval != 0
7566 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7567 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7569 /* We don't need to do anything if there were no floating point
7570 arguments and the value will not be returned in a floating point
7572 if (fp_code == 0 && ! fpret)
7575 /* We don't need to do anything if this is a call to a special
7576 mips16 support function. */
7577 if (GET_CODE (fn) == SYMBOL_REF
7578 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7581 /* This code will only work for o32 and o64 abis. The other ABI's
7582 require more sophisticated support. */
7586 /* We can only handle SFmode and DFmode floating point return
7588 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
7591 /* If we're calling via a function pointer, then we must always call
7592 via a stub. There are magic stubs provided in libgcc.a for each
7593 of the required cases. Each of them expects the function address
7594 to arrive in register $2. */
7596 if (GET_CODE (fn) != SYMBOL_REF)
7602 /* ??? If this code is modified to support other ABI's, we need
7603 to handle PARALLEL return values here. */
7605 sprintf (buf, "__mips16_call_stub_%s%d",
7607 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7610 id = get_identifier (buf);
7611 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7613 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7615 if (retval == NULL_RTX)
7616 insn = gen_call_internal (stub_fn, arg_size);
7618 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7619 insn = emit_call_insn (insn);
7621 /* Put the register usage information on the CALL. */
7622 if (GET_CODE (insn) != CALL_INSN)
7624 CALL_INSN_FUNCTION_USAGE (insn) =
7625 gen_rtx_EXPR_LIST (VOIDmode,
7626 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
7627 CALL_INSN_FUNCTION_USAGE (insn));
7629 /* If we are handling a floating point return value, we need to
7630 save $18 in the function prologue. Putting a note on the
7631 call will mean that regs_ever_live[$18] will be true if the
7632 call is not eliminated, and we can check that in the prologue
7635 CALL_INSN_FUNCTION_USAGE (insn) =
7636 gen_rtx_EXPR_LIST (VOIDmode,
7637 gen_rtx_USE (VOIDmode,
7638 gen_rtx_REG (word_mode, 18)),
7639 CALL_INSN_FUNCTION_USAGE (insn));
7641 /* Return 1 to tell the caller that we've generated the call
7646 /* We know the function we are going to call. If we have already
7647 built a stub, we don't need to do anything further. */
7649 fnname = XSTR (fn, 0);
7650 for (l = mips16_stubs; l != NULL; l = l->next)
7651 if (strcmp (l->name, fnname) == 0)
7656 /* Build a special purpose stub. When the linker sees a
7657 function call in mips16 code, it will check where the target
7658 is defined. If the target is a 32 bit call, the linker will
7659 search for the section defined here. It can tell which
7660 symbol this section is associated with by looking at the
7661 relocation information (the name is unreliable, since this
7662 might be a static function). If such a section is found, the
7663 linker will redirect the call to the start of the magic
7666 If the function does not return a floating point value, the
7667 special stub section is named
7670 If the function does return a floating point value, the stub
7672 .mips16.call.fp.FNNAME
7675 secname = (char *) alloca (strlen (fnname) + 40);
7676 sprintf (secname, ".mips16.call.%s%s",
7679 stubname = (char *) alloca (strlen (fnname) + 20);
7680 sprintf (stubname, "__call_stub_%s%s",
7683 stubid = get_identifier (stubname);
7684 stubdecl = build_decl (FUNCTION_DECL, stubid,
7685 build_function_type (void_type_node, NULL_TREE));
7686 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7688 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7690 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7694 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7696 fprintf (asm_out_file, "%s%s",
7697 need_comma ? ", " : "",
7698 (f & 3) == 1 ? "float" : "double");
7701 fprintf (asm_out_file, ")\n");
7703 fprintf (asm_out_file, "\t.set\tnomips16\n");
7704 assemble_start_function (stubdecl, stubname);
7706 if (!FUNCTION_NAME_ALREADY_DECLARED)
7708 fputs ("\t.ent\t", asm_out_file);
7709 assemble_name (asm_out_file, stubname);
7710 fputs ("\n", asm_out_file);
7712 assemble_name (asm_out_file, stubname);
7713 fputs (":\n", asm_out_file);
7716 /* We build the stub code by hand. That's the only way we can
7717 do it, since we can't generate 32 bit code during a 16 bit
7720 /* We don't want the assembler to insert any nops here. */
7721 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7723 mips16_fp_args (asm_out_file, fp_code, 0);
7727 fprintf (asm_out_file, "\t.set\tnoat\n");
7728 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7730 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7731 fprintf (asm_out_file, "\t.set\tat\n");
7732 /* Unfortunately, we can't fill the jump delay slot. We
7733 can't fill with one of the mtc1 instructions, because the
7734 result is not available for one instruction, so if the
7735 very first instruction in the function refers to the
7736 register, it will see the wrong value. */
7737 fprintf (asm_out_file, "\tnop\n");
7741 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7742 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7743 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7744 /* As above, we can't fill the delay slot. */
7745 fprintf (asm_out_file, "\tnop\n");
7746 if (GET_MODE (retval) == SFmode)
7747 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7748 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7751 if (TARGET_BIG_ENDIAN)
7753 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7754 reg_names[GP_REG_FIRST + 2],
7755 reg_names[FP_REG_FIRST + 1]);
7756 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7757 reg_names[GP_REG_FIRST + 3],
7758 reg_names[FP_REG_FIRST + 0]);
7762 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7763 reg_names[GP_REG_FIRST + 2],
7764 reg_names[FP_REG_FIRST + 0]);
7765 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7766 reg_names[GP_REG_FIRST + 3],
7767 reg_names[FP_REG_FIRST + 1]);
7770 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7771 /* As above, we can't fill the delay slot. */
7772 fprintf (asm_out_file, "\tnop\n");
7775 fprintf (asm_out_file, "\t.set\treorder\n");
7777 #ifdef ASM_DECLARE_FUNCTION_SIZE
7778 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7781 if (!FUNCTION_NAME_ALREADY_DECLARED)
7783 fputs ("\t.end\t", asm_out_file);
7784 assemble_name (asm_out_file, stubname);
7785 fputs ("\n", asm_out_file);
7788 fprintf (asm_out_file, "\t.set\tmips16\n");
7790 /* Record this stub. */
7791 l = (struct mips16_stub *) xmalloc (sizeof *l);
7792 l->name = xstrdup (fnname);
7794 l->next = mips16_stubs;
7798 /* If we expect a floating point return value, but we've built a
7799 stub which does not expect one, then we're in trouble. We can't
7800 use the existing stub, because it won't handle the floating point
7801 value. We can't build a new stub, because the linker won't know
7802 which stub to use for the various calls in this object file.
7803 Fortunately, this case is illegal, since it means that a function
7804 was declared in two different ways in a single compilation. */
7805 if (fpret && ! l->fpret)
7806 error ("can not handle inconsistent calls to `%s'", fnname);
7808 /* If we are calling a stub which handles a floating point return
7809 value, we need to arrange to save $18 in the prologue. We do
7810 this by marking the function call as using the register. The
7811 prologue will later see that it is used, and emit code to save
7818 if (retval == NULL_RTX)
7819 insn = gen_call_internal (fn, arg_size);
7821 insn = gen_call_value_internal (retval, fn, arg_size);
7822 insn = emit_call_insn (insn);
7824 if (GET_CODE (insn) != CALL_INSN)
7827 CALL_INSN_FUNCTION_USAGE (insn) =
7828 gen_rtx_EXPR_LIST (VOIDmode,
7829 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
7830 CALL_INSN_FUNCTION_USAGE (insn));
7832 /* Return 1 to tell the caller that we've generated the call
7837 /* Return 0 to let the caller generate the call insn. */
7841 /* An entry in the mips16 constant pool. VALUE is the pool constant,
7842 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
7844 struct mips16_constant {
7845 struct mips16_constant *next;
7848 enum machine_mode mode;
7851 /* Information about an incomplete mips16 constant pool. FIRST is the
7852 first constant, HIGHEST_ADDRESS is the highest address that the first
7853 byte of the pool can have, and INSN_ADDRESS is the current instruction
7856 struct mips16_constant_pool {
7857 struct mips16_constant *first;
7858 int highest_address;
7862 /* Add constant VALUE to POOL and return its label. MODE is the
7863 value's mode (used for CONST_INTs, etc.). */
7866 add_constant (struct mips16_constant_pool *pool,
7867 rtx value, enum machine_mode mode)
7869 struct mips16_constant **p, *c;
7870 bool first_of_size_p;
7872 /* See whether the constant is already in the pool. If so, return the
7873 existing label, otherwise leave P pointing to the place where the
7874 constant should be added.
7876 Keep the pool sorted in increasing order of mode size so that we can
7877 reduce the number of alignments needed. */
7878 first_of_size_p = true;
7879 for (p = &pool->first; *p != 0; p = &(*p)->next)
7881 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
7883 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
7885 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
7886 first_of_size_p = false;
7889 /* In the worst case, the constant needed by the earliest instruction
7890 will end up at the end of the pool. The entire pool must then be
7891 accessible from that instruction.
7893 When adding the first constant, set the pool's highest address to
7894 the address of the first out-of-range byte. Adjust this address
7895 downwards each time a new constant is added. */
7896 if (pool->first == 0)
7897 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
7898 is the address of the instruction with the lowest two bits clear.
7899 The base PC value for ld has the lowest three bits clear. Assume
7900 the worst case here. */
7901 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
7902 pool->highest_address -= GET_MODE_SIZE (mode);
7903 if (first_of_size_p)
7904 /* Take into account the worst possible padding due to alignment. */
7905 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
7907 /* Create a new entry. */
7908 c = (struct mips16_constant *) xmalloc (sizeof *c);
7911 c->label = gen_label_rtx ();
7918 /* Output constant VALUE after instruction INSN and return the last
7919 instruction emitted. MODE is the mode of the constant. */
7922 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
7924 switch (GET_MODE_CLASS (mode))
7928 rtx size = GEN_INT (GET_MODE_SIZE (mode));
7929 return emit_insn_after (gen_consttable_int (value, size), insn);
7933 return emit_insn_after (gen_consttable_float (value), insn);
7935 case MODE_VECTOR_FLOAT:
7936 case MODE_VECTOR_INT:
7939 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
7940 insn = dump_constants_1 (GET_MODE_INNER (mode),
7941 CONST_VECTOR_ELT (value, i), insn);
7951 /* Dump out the constants in CONSTANTS after INSN. */
7954 dump_constants (struct mips16_constant *constants, rtx insn)
7956 struct mips16_constant *c, *next;
7960 for (c = constants; c != NULL; c = next)
7962 /* If necessary, increase the alignment of PC. */
7963 if (align < GET_MODE_SIZE (c->mode))
7965 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
7966 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
7968 align = GET_MODE_SIZE (c->mode);
7970 insn = emit_label_after (c->label, insn);
7971 insn = dump_constants_1 (c->mode, c->value, insn);
7977 emit_barrier_after (insn);
7980 /* Return the length of instruction INSN.
7982 ??? MIPS16 switch tables go in .text, but we don't define
7983 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
7984 compute their lengths correctly. */
7987 mips16_insn_length (rtx insn)
7989 if (GET_CODE (insn) == JUMP_INSN)
7991 rtx body = PATTERN (insn);
7992 if (GET_CODE (body) == ADDR_VEC)
7993 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
7994 if (GET_CODE (body) == ADDR_DIFF_VEC)
7995 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
7997 return get_attr_length (insn);
8000 /* Rewrite *X so that constant pool references refer to the constant's
8001 label instead. DATA points to the constant pool structure. */
8004 mips16_rewrite_pool_refs (rtx *x, void *data)
8006 struct mips16_constant_pool *pool = data;
8007 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8008 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8009 get_pool_constant (*x),
8010 get_pool_mode (*x)));
8014 /* Build MIPS16 constant pools. */
8017 mips16_lay_out_constants (void)
8019 struct mips16_constant_pool pool;
8023 memset (&pool, 0, sizeof (pool));
8024 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8026 /* Rewrite constant pool references in INSN. */
8028 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8030 pool.insn_address += mips16_insn_length (insn);
8032 if (pool.first != NULL)
8034 /* If there are no natural barriers between the first user of
8035 the pool and the highest acceptable address, we'll need to
8036 create a new instruction to jump around the constant pool.
8037 In the worst case, this instruction will be 4 bytes long.
8039 If it's too late to do this transformation after INSN,
8040 do it immediately before INSN. */
8041 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8045 label = gen_label_rtx ();
8047 jump = emit_jump_insn_before (gen_jump (label), insn);
8048 JUMP_LABEL (jump) = label;
8049 LABEL_NUSES (label) = 1;
8050 barrier = emit_barrier_after (jump);
8052 emit_label_after (label, barrier);
8053 pool.insn_address += 4;
8056 /* See whether the constant pool is now out of range of the first
8057 user. If so, output the constants after the previous barrier.
8058 Note that any instructions between BARRIER and INSN (inclusive)
8059 will use negative offsets to refer to the pool. */
8060 if (pool.insn_address > pool.highest_address)
8062 dump_constants (pool.first, barrier);
8066 else if (BARRIER_P (insn))
8070 dump_constants (pool.first, get_last_insn ());
8073 /* A temporary variable used by for_each_rtx callbacks, etc. */
8074 static rtx mips_sim_insn;
8076 /* A structure representing the state of the processor pipeline.
8077 Used by the mips_sim_* family of functions. */
8079 /* The maximum number of instructions that can be issued in a cycle.
8080 (Caches mips_issue_rate.) */
8081 unsigned int issue_rate;
8083 /* The current simulation time. */
8086 /* How many more instructions can be issued in the current cycle. */
8087 unsigned int insns_left;
8089 /* LAST_SET[X].INSN is the last instruction to set register X.
8090 LAST_SET[X].TIME is the time at which that instruction was issued.
8091 INSN is null if no instruction has yet set register X. */
8095 } last_set[FIRST_PSEUDO_REGISTER];
8097 /* The pipeline's current DFA state. */
8101 /* Reset STATE to the initial simulation state. */
8104 mips_sim_reset (struct mips_sim *state)
8107 state->insns_left = state->issue_rate;
8108 memset (&state->last_set, 0, sizeof (state->last_set));
8109 state_reset (state->dfa_state);
8112 /* Initialize STATE before its first use. DFA_STATE points to an
8113 allocated but uninitialized DFA state. */
8116 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8118 state->issue_rate = mips_issue_rate ();
8119 state->dfa_state = dfa_state;
8120 mips_sim_reset (state);
8123 /* Advance STATE by one clock cycle. */
8126 mips_sim_next_cycle (struct mips_sim *state)
8129 state->insns_left = state->issue_rate;
8130 state_transition (state->dfa_state, 0);
8133 /* Advance simulation state STATE until instruction INSN can read
8137 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8141 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8142 if (state->last_set[REGNO (reg) + i].insn != 0)
8146 t = state->last_set[REGNO (reg) + i].time;
8147 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8148 while (state->time < t)
8149 mips_sim_next_cycle (state);
8153 /* A for_each_rtx callback. If *X is a register, advance simulation state
8154 DATA until mips_sim_insn can read the register's value. */
8157 mips_sim_wait_regs_2 (rtx *x, void *data)
8160 mips_sim_wait_reg (data, mips_sim_insn, *x);
8164 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8167 mips_sim_wait_regs_1 (rtx *x, void *data)
8169 for_each_rtx (x, mips_sim_wait_regs_2, data);
8172 /* Advance simulation state STATE until all of INSN's register
8173 dependencies are satisfied. */
8176 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8178 mips_sim_insn = insn;
8179 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8182 /* Advance simulation state STATE until the units required by
8183 instruction INSN are available. */
8186 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8190 tmp_state = alloca (state_size ());
8191 while (state->insns_left == 0
8192 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8193 state_transition (tmp_state, insn) >= 0))
8194 mips_sim_next_cycle (state);
8197 /* Advance simulation state STATE until INSN is ready to issue. */
8200 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8202 mips_sim_wait_regs (state, insn);
8203 mips_sim_wait_units (state, insn);
8206 /* mips_sim_insn has just set X. Update the LAST_SET array
8207 in simulation state DATA. */
8210 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8212 struct mips_sim *state;
8217 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8219 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8220 state->last_set[REGNO (x) + i].time = state->time;
8224 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8225 can issue immediately (i.e., that mips_sim_wait_insn has already
8229 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8231 state_transition (state->dfa_state, insn);
8232 state->insns_left--;
8234 mips_sim_insn = insn;
8235 note_stores (PATTERN (insn), mips_sim_record_set, state);
8238 /* Simulate issuing a NOP in state STATE. */
8241 mips_sim_issue_nop (struct mips_sim *state)
8243 if (state->insns_left == 0)
8244 mips_sim_next_cycle (state);
8245 state->insns_left--;
8248 /* Update simulation state STATE so that it's ready to accept the instruction
8249 after INSN. INSN should be part of the main rtl chain, not a member of a
8253 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8255 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8257 mips_sim_issue_nop (state);
8259 switch (GET_CODE (SEQ_BEGIN (insn)))
8263 /* We can't predict the processor state after a call or label. */
8264 mips_sim_reset (state);
8268 /* The delay slots of branch likely instructions are only executed
8269 when the branch is taken. Therefore, if the caller has simulated
8270 the delay slot instruction, STATE does not really reflect the state
8271 of the pipeline for the instruction after the delay slot. Also,
8272 branch likely instructions tend to incur a penalty when not taken,
8273 so there will probably be an extra delay between the branch and
8274 the instruction after the delay slot. */
8275 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8276 mips_sim_reset (state);
8284 /* The VR4130 pipeline issues aligned pairs of instructions together,
8285 but it stalls the second instruction if it depends on the first.
8286 In order to cut down the amount of logic required, this dependence
8287 check is not based on a full instruction decode. Instead, any non-SPECIAL
8288 instruction is assumed to modify the register specified by bits 20-16
8289 (which is usually the "rt" field).
8291 In beq, beql, bne and bnel instructions, the rt field is actually an
8292 input, so we can end up with a false dependence between the branch
8293 and its delay slot. If this situation occurs in instruction INSN,
8294 try to avoid it by swapping rs and rt. */
8297 vr4130_avoid_branch_rt_conflict (rtx insn)
8301 first = SEQ_BEGIN (insn);
8302 second = SEQ_END (insn);
8303 if (GET_CODE (first) == JUMP_INSN
8304 && GET_CODE (second) == INSN
8305 && GET_CODE (PATTERN (first)) == SET
8306 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8307 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8309 /* Check for the right kind of condition. */
8310 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8311 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8312 && REG_P (XEXP (cond, 0))
8313 && REG_P (XEXP (cond, 1))
8314 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8315 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8317 /* SECOND mentions the rt register but not the rs register. */
8318 rtx tmp = XEXP (cond, 0);
8319 XEXP (cond, 0) = XEXP (cond, 1);
8320 XEXP (cond, 1) = tmp;
8325 /* Implement -mvr4130-align. Go through each basic block and simulate the
8326 processor pipeline. If we find that a pair of instructions could execute
8327 in parallel, and the first of those instruction is not 8-byte aligned,
8328 insert a nop to make it aligned. */
8331 vr4130_align_insns (void)
8333 struct mips_sim state;
8334 rtx insn, subinsn, last, last2, next;
8339 /* LAST is the last instruction before INSN to have a nonzero length.
8340 LAST2 is the last such instruction before LAST. */
8344 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8347 mips_sim_init (&state, alloca (state_size ()));
8348 for (insn = get_insns (); insn != 0; insn = next)
8350 unsigned int length;
8352 next = NEXT_INSN (insn);
8354 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8355 This isn't really related to the alignment pass, but we do it on
8356 the fly to avoid a separate instruction walk. */
8357 vr4130_avoid_branch_rt_conflict (insn);
8359 if (USEFUL_INSN_P (insn))
8360 FOR_EACH_SUBINSN (subinsn, insn)
8362 mips_sim_wait_insn (&state, subinsn);
8364 /* If we want this instruction to issue in parallel with the
8365 previous one, make sure that the previous instruction is
8366 aligned. There are several reasons why this isn't worthwhile
8367 when the second instruction is a call:
8369 - Calls are less likely to be performance critical,
8370 - There's a good chance that the delay slot can execute
8371 in parallel with the call.
8372 - The return address would then be unaligned.
8374 In general, if we're going to insert a nop between instructions
8375 X and Y, it's better to insert it immediately after X. That
8376 way, if the nop makes Y aligned, it will also align any labels
8378 if (state.insns_left != state.issue_rate
8379 && GET_CODE (subinsn) != CALL_INSN)
8381 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8383 /* SUBINSN is the first instruction in INSN and INSN is
8384 aligned. We want to align the previous instruction
8385 instead, so insert a nop between LAST2 and LAST.
8387 Note that LAST could be either a single instruction
8388 or a branch with a delay slot. In the latter case,
8389 LAST, like INSN, is already aligned, but the delay
8390 slot must have some extra delay that stops it from
8391 issuing at the same time as the branch. We therefore
8392 insert a nop before the branch in order to align its
8394 emit_insn_after (gen_nop (), last2);
8397 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8399 /* SUBINSN is the delay slot of INSN, but INSN is
8400 currently unaligned. Insert a nop between
8401 LAST and INSN to align it. */
8402 emit_insn_after (gen_nop (), last);
8406 mips_sim_issue_insn (&state, subinsn);
8408 mips_sim_finish_insn (&state, insn);
8410 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8411 length = get_attr_length (insn);
8414 /* If the instruction is an asm statement or multi-instruction
8415 mips.md patern, the length is only an estimate. Insert an
8416 8 byte alignment after it so that the following instructions
8417 can be handled correctly. */
8418 if (GET_CODE (SEQ_BEGIN (insn)) == INSN
8419 && (recog_memoized (insn) < 0 || length >= 8))
8421 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8422 next = NEXT_INSN (next);
8423 mips_sim_next_cycle (&state);
8426 else if (length & 4)
8427 aligned_p = !aligned_p;
8432 /* See whether INSN is an aligned label. */
8433 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8439 /* Subroutine of mips_reorg. If there is a hazard between INSN
8440 and a previous instruction, avoid it by inserting nops after
8443 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8444 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8445 before using the value of that register. *HILO_DELAY counts the
8446 number of instructions since the last hilo hazard (that is,
8447 the number of instructions since the last mflo or mfhi).
8449 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8450 for the next instruction.
8452 LO_REG is an rtx for the LO register, used in dependence checking. */
8455 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8456 rtx *delayed_reg, rtx lo_reg)
8464 pattern = PATTERN (insn);
8466 /* Do not put the whole function in .set noreorder if it contains
8467 an asm statement. We don't know whether there will be hazards
8468 between the asm statement and the gcc-generated code. */
8469 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8470 cfun->machine->all_noreorder_p = false;
8472 /* Ignore zero-length instructions (barriers and the like). */
8473 ninsns = get_attr_length (insn) / 4;
8477 /* Work out how many nops are needed. Note that we only care about
8478 registers that are explicitly mentioned in the instruction's pattern.
8479 It doesn't matter that calls use the argument registers or that they
8480 clobber hi and lo. */
8481 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8482 nops = 2 - *hilo_delay;
8483 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8488 /* Insert the nops between this instruction and the previous one.
8489 Each new nop takes us further from the last hilo hazard. */
8490 *hilo_delay += nops;
8492 emit_insn_after (gen_hazard_nop (), after);
8494 /* Set up the state for the next instruction. */
8495 *hilo_delay += ninsns;
8497 if (INSN_CODE (insn) >= 0)
8498 switch (get_attr_hazard (insn))
8508 set = single_set (insn);
8511 *delayed_reg = SET_DEST (set);
8517 /* Go through the instruction stream and insert nops where necessary.
8518 See if the whole function can then be put into .set noreorder &
8522 mips_avoid_hazards (void)
8524 rtx insn, last_insn, lo_reg, delayed_reg;
8527 /* Force all instructions to be split into their final form. */
8528 split_all_insns_noflow ();
8530 /* Recalculate instruction lengths without taking nops into account. */
8531 cfun->machine->ignore_hazard_length_p = true;
8532 shorten_branches (get_insns ());
8534 /* The profiler code uses assembler macros. -mfix-vr4120 relies on
8535 assembler nop insertion. */
8536 cfun->machine->all_noreorder_p = (!current_function_profile
8537 && !TARGET_FIX_VR4120);
8542 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8544 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8547 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8548 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8549 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8550 &hilo_delay, &delayed_reg, lo_reg);
8552 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8553 &delayed_reg, lo_reg);
8560 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8566 mips16_lay_out_constants ();
8567 else if (TARGET_EXPLICIT_RELOCS)
8569 if (mips_flag_delayed_branch)
8570 dbr_schedule (get_insns (), dump_file);
8571 mips_avoid_hazards ();
8572 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
8573 vr4130_align_insns ();
8577 /* This function does three things:
8579 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8580 - Register the mips16 hardware floating point stubs.
8581 - Register the gofast functions if selected using --enable-gofast. */
8583 #include "config/gofast.h"
8586 mips_init_libfuncs (void)
8588 if (TARGET_FIX_VR4120)
8590 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8591 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8594 if (TARGET_MIPS16 && mips16_hard_float)
8596 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8597 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8598 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8599 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8601 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8602 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8603 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8604 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8605 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8606 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8608 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8609 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8611 if (TARGET_DOUBLE_FLOAT)
8613 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8614 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8615 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8616 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8618 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8619 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8620 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8621 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8622 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8623 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8625 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8626 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8628 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8629 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8633 gofast_maybe_init_libfuncs ();
8636 /* Return a number assessing the cost of moving a register in class
8637 FROM to class TO. The classes are expressed using the enumeration
8638 values such as `GENERAL_REGS'. A value of 2 is the default; other
8639 values are interpreted relative to that.
8641 It is not required that the cost always equal 2 when FROM is the
8642 same as TO; on some machines it is expensive to move between
8643 registers if they are not general registers.
8645 If reload sees an insn consisting of a single `set' between two
8646 hard registers, and if `REGISTER_MOVE_COST' applied to their
8647 classes returns a value of 2, reload does not check to ensure that
8648 the constraints of the insn are met. Setting a cost of other than
8649 2 will allow reload to verify that the constraints are met. You
8650 should do this if the `movM' pattern's constraints do not allow
8653 ??? We make the cost of moving from HI/LO into general
8654 registers the same as for one of moving general registers to
8655 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8656 pseudo to HI/LO. This might hurt optimizations though, it
8657 isn't clear if it is wise. And it might not work in all cases. We
8658 could solve the DImode LO reg problem by using a multiply, just
8659 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8660 problem by using divide instructions. divu puts the remainder in
8661 the HI reg, so doing a divide by -1 will move the value in the HI
8662 reg for all values except -1. We could handle that case by using a
8663 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8664 a compare/branch to test the input value to see which instruction
8665 we need to use. This gets pretty messy, but it is feasible. */
8668 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8669 enum reg_class to, enum reg_class from)
8671 if (from == M16_REGS && GR_REG_CLASS_P (to))
8673 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8675 else if (GR_REG_CLASS_P (from))
8679 else if (to == M16_NA_REGS)
8681 else if (GR_REG_CLASS_P (to))
8688 else if (to == FP_REGS)
8690 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8697 else if (COP_REG_CLASS_P (to))
8701 } /* GR_REG_CLASS_P (from) */
8702 else if (from == FP_REGS)
8704 if (GR_REG_CLASS_P (to))
8706 else if (to == FP_REGS)
8708 else if (to == ST_REGS)
8710 } /* from == FP_REGS */
8711 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8713 if (GR_REG_CLASS_P (to))
8720 } /* from == HI_REG, etc. */
8721 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8723 else if (COP_REG_CLASS_P (from))
8726 } /* COP_REG_CLASS_P (from) */
8733 /* Return the length of INSN. LENGTH is the initial length computed by
8734 attributes in the machine-description file. */
8737 mips_adjust_insn_length (rtx insn, int length)
8739 /* A unconditional jump has an unfilled delay slot if it is not part
8740 of a sequence. A conditional jump normally has a delay slot, but
8741 does not on MIPS16. */
8742 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
8745 /* See how many nops might be needed to avoid hardware hazards. */
8746 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8747 switch (get_attr_hazard (insn))
8761 /* All MIPS16 instructions are a measly two bytes. */
8769 /* Return an asm sequence to start a noat block and load the address
8770 of a label into $1. */
8773 mips_output_load_label (void)
8775 if (TARGET_EXPLICIT_RELOCS)
8779 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8782 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8785 if (ISA_HAS_LOAD_DELAY)
8786 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8787 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8791 if (Pmode == DImode)
8792 return "%[dla\t%@,%0";
8794 return "%[la\t%@,%0";
8799 /* Output assembly instructions to peform a conditional branch.
8801 INSN is the branch instruction. OPERANDS[0] is the condition.
8802 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8803 of the first operand to the condition. If TWO_OPERANDS_P is
8804 nonzero the comparison takes two operands; OPERANDS[3] will be the
8807 If INVERTED_P is nonzero we are to branch if the condition does
8808 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
8810 LENGTH is the length (in bytes) of the sequence we are to generate.
8811 That tells us whether to generate a simple conditional branch, or a
8812 reversed conditional branch around a `jr' instruction. */
8814 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
8815 int float_p, int inverted_p, int length)
8817 static char buffer[200];
8818 /* The kind of comparison we are doing. */
8819 enum rtx_code code = GET_CODE (operands[0]);
8820 /* Nonzero if the opcode for the comparison needs a `z' indicating
8821 that it is a comparison against zero. */
8823 /* A string to use in the assembly output to represent the first
8825 const char *op1 = "%z2";
8826 /* A string to use in the assembly output to represent the second
8827 operand. Use the hard-wired zero register if there's no second
8829 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
8830 /* The operand-printing string for the comparison. */
8831 const char *const comp = (float_p ? "%F0" : "%C0");
8832 /* The operand-printing string for the inverted comparison. */
8833 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
8835 /* The MIPS processors (for levels of the ISA at least two), have
8836 "likely" variants of each branch instruction. These instructions
8837 annul the instruction in the delay slot if the branch is not
8839 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8841 if (!two_operands_p)
8843 /* To compute whether than A > B, for example, we normally
8844 subtract B from A and then look at the sign bit. But, if we
8845 are doing an unsigned comparison, and B is zero, we don't
8846 have to do the subtraction. Instead, we can just check to
8847 see if A is nonzero. Thus, we change the CODE here to
8848 reflect the simpler comparison operation. */
8860 /* A condition which will always be true. */
8866 /* A condition which will always be false. */
8872 /* Not a special case. */
8877 /* Relative comparisons are always done against zero. But
8878 equality comparisons are done between two operands, and therefore
8879 do not require a `z' in the assembly language output. */
8880 need_z_p = (!float_p && code != EQ && code != NE);
8881 /* For comparisons against zero, the zero is not provided
8886 /* Begin by terminating the buffer. That way we can always use
8887 strcat to add to it. */
8894 /* Just a simple conditional branch. */
8896 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
8897 inverted_p ? inverted_comp : comp);
8899 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
8900 inverted_p ? inverted_comp : comp,
8901 need_z_p ? "z" : "",
8911 /* Generate a reversed conditional branch around ` j'
8924 If the original branch was a likely branch, the delay slot
8925 must be executed only if the branch is taken, so generate:
8937 When generating PIC, instead of:
8950 rtx target = gen_label_rtx ();
8952 orig_target = operands[1];
8953 operands[1] = target;
8954 /* Generate the reversed comparison. This takes four
8957 sprintf (buffer, "%%*b%s\t%%Z2%%1",
8958 inverted_p ? comp : inverted_comp);
8960 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
8961 inverted_p ? comp : inverted_comp,
8962 need_z_p ? "z" : "",
8965 output_asm_insn (buffer, operands);
8967 if (length != 16 && length != 28 && ! mips_branch_likely)
8969 /* Output delay slot instruction. */
8970 rtx insn = final_sequence;
8971 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
8972 optimize, 0, 1, NULL);
8973 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
8976 output_asm_insn ("%#", 0);
8979 output_asm_insn ("j\t%0", &orig_target);
8982 output_asm_insn (mips_output_load_label (), &orig_target);
8983 output_asm_insn ("jr\t%@%]", 0);
8986 if (length != 16 && length != 28 && mips_branch_likely)
8988 /* Output delay slot instruction. */
8989 rtx insn = final_sequence;
8990 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
8991 optimize, 0, 1, NULL);
8992 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
8995 output_asm_insn ("%#", 0);
8997 (*targetm.asm_out.internal_label) (asm_out_file, "L",
8998 CODE_LABEL_NUMBER (target));
9011 /* Used to output div or ddiv instruction DIVISION, which has the operands
9012 given by OPERANDS. Add in a divide-by-zero check if needed.
9014 When working around R4000 and R4400 errata, we need to make sure that
9015 the division is not immediately followed by a shift[1][2]. We also
9016 need to stop the division from being put into a branch delay slot[3].
9017 The easiest way to avoid both problems is to add a nop after the
9018 division. When a divide-by-zero check is needed, this nop can be
9019 used to fill the branch delay slot.
9021 [1] If a double-word or a variable shift executes immediately
9022 after starting an integer division, the shift may give an
9023 incorrect result. See quotations of errata #16 and #28 from
9024 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9025 in mips.md for details.
9027 [2] A similar bug to [1] exists for all revisions of the
9028 R4000 and the R4400 when run in an MC configuration.
9029 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9031 "19. In this following sequence:
9033 ddiv (or ddivu or div or divu)
9034 dsll32 (or dsrl32, dsra32)
9036 if an MPT stall occurs, while the divide is slipping the cpu
9037 pipeline, then the following double shift would end up with an
9040 Workaround: The compiler needs to avoid generating any
9041 sequence with divide followed by extended double shift."
9043 This erratum is also present in "MIPS R4400MC Errata, Processor
9044 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9045 & 3.0" as errata #10 and #4, respectively.
9047 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9048 (also valid for MIPS R4000MC processors):
9050 "52. R4000SC: This bug does not apply for the R4000PC.
9052 There are two flavors of this bug:
9054 1) If the instruction just after divide takes an RF exception
9055 (tlb-refill, tlb-invalid) and gets an instruction cache
9056 miss (both primary and secondary) and the line which is
9057 currently in secondary cache at this index had the first
9058 data word, where the bits 5..2 are set, then R4000 would
9059 get a wrong result for the div.
9064 ------------------- # end-of page. -tlb-refill
9069 ------------------- # end-of page. -tlb-invalid
9072 2) If the divide is in the taken branch delay slot, where the
9073 target takes RF exception and gets an I-cache miss for the
9074 exception vector or where I-cache miss occurs for the
9075 target address, under the above mentioned scenarios, the
9076 div would get wrong results.
9079 j r2 # to next page mapped or unmapped
9080 div r8,r9 # this bug would be there as long
9081 # as there is an ICache miss and
9082 nop # the "data pattern" is present
9085 beq r0, r0, NextPage # to Next page
9089 This bug is present for div, divu, ddiv, and ddivu
9092 Workaround: For item 1), OS could make sure that the next page
9093 after the divide instruction is also mapped. For item 2), the
9094 compiler could make sure that the divide instruction is not in
9095 the branch delay slot."
9097 These processors have PRId values of 0x00004220 and 0x00004300 for
9098 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9101 mips_output_division (const char *division, rtx *operands)
9106 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9108 output_asm_insn (s, operands);
9111 if (TARGET_CHECK_ZERO_DIV)
9115 output_asm_insn (s, operands);
9116 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9120 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9121 output_asm_insn (s, operands);
9122 s = "break\t7%)\n1:";
9128 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9129 with a final "000" replaced by "k". Ignore case.
9131 Note: this function is shared between GCC and GAS. */
9134 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9136 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9137 given++, canonical++;
9139 return ((*given == 0 && *canonical == 0)
9140 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9144 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9145 CPU name. We've traditionally allowed a lot of variation here.
9147 Note: this function is shared between GCC and GAS. */
9150 mips_matching_cpu_name_p (const char *canonical, const char *given)
9152 /* First see if the name matches exactly, or with a final "000"
9154 if (mips_strict_matching_cpu_name_p (canonical, given))
9157 /* If not, try comparing based on numerical designation alone.
9158 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9159 if (TOLOWER (*given) == 'r')
9161 if (!ISDIGIT (*given))
9164 /* Skip over some well-known prefixes in the canonical name,
9165 hoping to find a number there too. */
9166 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9168 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9170 else if (TOLOWER (canonical[0]) == 'r')
9173 return mips_strict_matching_cpu_name_p (canonical, given);
9177 /* Parse an option that takes the name of a processor as its argument.
9178 OPTION is the name of the option and CPU_STRING is the argument.
9179 Return the corresponding processor enumeration if the CPU_STRING is
9180 recognized, otherwise report an error and return null.
9182 A similar function exists in GAS. */
9184 static const struct mips_cpu_info *
9185 mips_parse_cpu (const char *option, const char *cpu_string)
9187 const struct mips_cpu_info *p;
9190 /* In the past, we allowed upper-case CPU names, but it doesn't
9191 work well with the multilib machinery. */
9192 for (s = cpu_string; *s != 0; s++)
9195 warning ("the cpu name must be lower case");
9199 /* 'from-abi' selects the most compatible architecture for the given
9200 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9201 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9202 version. Look first at the -mgp options, if given, otherwise base
9203 the choice on MASK_64BIT in TARGET_DEFAULT. */
9204 if (strcasecmp (cpu_string, "from-abi") == 0)
9205 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9206 : ABI_NEEDS_64BIT_REGS ? 3
9207 : (TARGET_64BIT ? 3 : 1));
9209 /* 'default' has traditionally been a no-op. Probably not very useful. */
9210 if (strcasecmp (cpu_string, "default") == 0)
9213 for (p = mips_cpu_info_table; p->name != 0; p++)
9214 if (mips_matching_cpu_name_p (p->name, cpu_string))
9217 error ("bad value (%s) for %s", cpu_string, option);
9222 /* Return the processor associated with the given ISA level, or null
9223 if the ISA isn't valid. */
9225 static const struct mips_cpu_info *
9226 mips_cpu_info_from_isa (int isa)
9228 const struct mips_cpu_info *p;
9230 for (p = mips_cpu_info_table; p->name != 0; p++)
9237 /* Implement HARD_REGNO_NREGS. The size of FP registers are controlled
9238 by UNITS_PER_FPREG. All other registers are word sized. */
9241 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9243 if (! FP_REG_P (regno))
9244 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9246 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9249 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9250 all BLKmode objects are returned in memory. Under the new (N32 and
9251 64-bit MIPS ABIs) small structures are returned in a register.
9252 Objects with varying size must still be returned in memory, of
9256 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9259 return (TYPE_MODE (type) == BLKmode);
9261 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9262 || (int_size_in_bytes (type) == -1));
9266 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9268 return !TARGET_OLDABI;
9271 /* Return true if INSN is a multiply-add or multiply-subtract
9272 instruction and PREV assigns to the accumulator operand. */
9275 mips_linked_madd_p (rtx prev, rtx insn)
9279 x = single_set (insn);
9285 if (GET_CODE (x) == PLUS
9286 && GET_CODE (XEXP (x, 0)) == MULT
9287 && reg_set_p (XEXP (x, 1), prev))
9290 if (GET_CODE (x) == MINUS
9291 && GET_CODE (XEXP (x, 1)) == MULT
9292 && reg_set_p (XEXP (x, 0), prev))
9298 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9299 that may clobber hi or lo. */
9301 static rtx mips_macc_chains_last_hilo;
9303 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9304 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9307 mips_macc_chains_record (rtx insn)
9309 if (get_attr_may_clobber_hilo (insn))
9310 mips_macc_chains_last_hilo = insn;
9313 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9314 has NREADY elements, looking for a multiply-add or multiply-subtract
9315 instruction that is cumulative with mips_macc_chains_last_hilo.
9316 If there is one, promote it ahead of anything else that might
9317 clobber hi or lo. */
9320 mips_macc_chains_reorder (rtx *ready, int nready)
9324 if (mips_macc_chains_last_hilo != 0)
9325 for (i = nready - 1; i >= 0; i--)
9326 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9328 for (j = nready - 1; j > i; j--)
9329 if (recog_memoized (ready[j]) >= 0
9330 && get_attr_may_clobber_hilo (ready[j]))
9332 mips_promote_ready (ready, i, j);
9339 /* The last instruction to be scheduled. */
9341 static rtx vr4130_last_insn;
9343 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9344 points to an rtx that is initially an instruction. Nullify the rtx
9345 if the instruction uses the value of register X. */
9348 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9350 rtx *insn_ptr = data;
9353 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9357 /* Return true if there is true register dependence between vr4130_last_insn
9361 vr4130_true_reg_dependence_p (rtx insn)
9363 note_stores (PATTERN (vr4130_last_insn),
9364 vr4130_true_reg_dependence_p_1, &insn);
9368 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9369 the ready queue and that INSN2 is the instruction after it, return
9370 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9371 in which INSN1 and INSN2 can probably issue in parallel, but for
9372 which (INSN2, INSN1) should be less sensitive to instruction
9373 alignment than (INSN1, INSN2). See 4130.md for more details. */
9376 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9380 /* Check for the following case:
9382 1) there is some other instruction X with an anti dependence on INSN1;
9383 2) X has a higher priority than INSN2; and
9384 3) X is an arithmetic instruction (and thus has no unit restrictions).
9386 If INSN1 is the last instruction blocking X, it would better to
9387 choose (INSN1, X) over (INSN2, INSN1). */
9388 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9389 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9390 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9391 && recog_memoized (XEXP (dep, 0)) >= 0
9392 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9395 if (vr4130_last_insn != 0
9396 && recog_memoized (insn1) >= 0
9397 && recog_memoized (insn2) >= 0)
9399 /* See whether INSN1 and INSN2 use different execution units,
9400 or if they are both ALU-type instructions. If so, they can
9401 probably execute in parallel. */
9402 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9403 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9404 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9406 /* If only one of the instructions has a dependence on
9407 vr4130_last_insn, prefer to schedule the other one first. */
9408 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9409 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9413 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9414 is not an ALU-type instruction and if INSN1 uses the same
9415 execution unit. (Note that if this condition holds, we already
9416 know that INSN2 uses a different execution unit.) */
9417 if (class1 != VR4130_CLASS_ALU
9418 && recog_memoized (vr4130_last_insn) >= 0
9419 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9426 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9427 queue with at least two instructions. Swap the first two if
9428 vr4130_swap_insns_p says that it could be worthwhile. */
9431 vr4130_reorder (rtx *ready, int nready)
9433 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9434 mips_promote_ready (ready, nready - 2, nready - 1);
9437 /* Remove the instruction at index LOWER from ready queue READY and
9438 reinsert it in front of the instruction at index HIGHER. LOWER must
9442 mips_promote_ready (rtx *ready, int lower, int higher)
9447 new_head = ready[lower];
9448 for (i = lower; i < higher; i++)
9449 ready[i] = ready[i + 1];
9450 ready[i] = new_head;
9453 /* Implement TARGET_SCHED_REORDER. */
9456 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9457 rtx *ready, int *nreadyp, int cycle)
9459 if (!reload_completed && TUNE_MACC_CHAINS)
9462 mips_macc_chains_last_hilo = 0;
9464 mips_macc_chains_reorder (ready, *nreadyp);
9466 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9469 vr4130_last_insn = 0;
9471 vr4130_reorder (ready, *nreadyp);
9473 return mips_issue_rate ();
9476 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9479 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9482 switch (GET_CODE (PATTERN (insn)))
9486 /* Don't count USEs and CLOBBERs against the issue rate. */
9491 if (!reload_completed && TUNE_MACC_CHAINS)
9492 mips_macc_chains_record (insn);
9493 vr4130_last_insn = insn;
9499 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9500 dependencies have no cost. */
9503 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9504 rtx dep ATTRIBUTE_UNUSED, int cost)
9506 if (REG_NOTE_KIND (link) != 0)
9511 /* Return the number of instructions that can be issued per cycle. */
9514 mips_issue_rate (void)
9518 case PROCESSOR_R4130:
9519 case PROCESSOR_R5400:
9520 case PROCESSOR_R5500:
9521 case PROCESSOR_R7000:
9522 case PROCESSOR_R9000:
9526 /* This is actually 4, but we get better performance if we claim 3.
9527 This is partly because of unwanted speculative code motion with the
9528 larger number, and partly because in most common cases we can't
9529 reach the theoretical max of 4. */
9540 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9541 be as wide as the scheduling freedom in the DFA. */
9544 mips_multipass_dfa_lookahead (void)
9546 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9547 if (mips_tune == PROCESSOR_SB1)
9555 mips_emit_prefetch (rtx *operands)
9557 int write = INTVAL (operands[1]);
9558 int locality = INTVAL (operands[2]);
9559 int indexed = GET_CODE (operands[3]) == REG;
9564 code = (write ? 5 : 4); /* store_streamed / load_streamed. */
9565 else if (locality <= 2)
9566 code = (write ? 1 : 0); /* store / load. */
9568 code = (write ? 7 : 6); /* store_retained / load_retained. */
9570 sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
9571 output_asm_insn (buffer, operands);
9578 /* Output assembly to switch to section NAME with attribute FLAGS. */
9581 irix_asm_named_section_1 (const char *name, unsigned int flags,
9584 unsigned int sh_type, sh_flags, sh_entsize;
9587 if (!(flags & SECTION_DEBUG))
9588 sh_flags |= 2; /* SHF_ALLOC */
9589 if (flags & SECTION_WRITE)
9590 sh_flags |= 1; /* SHF_WRITE */
9591 if (flags & SECTION_CODE)
9592 sh_flags |= 4; /* SHF_EXECINSTR */
9593 if (flags & SECTION_SMALL)
9594 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9595 if (strcmp (name, ".debug_frame") == 0)
9596 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9597 if (flags & SECTION_DEBUG)
9598 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9599 else if (flags & SECTION_BSS)
9600 sh_type = 8; /* SHT_NOBITS */
9602 sh_type = 1; /* SHT_PROGBITS */
9604 if (flags & SECTION_CODE)
9609 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9610 name, sh_type, sh_flags, sh_entsize, align);
9614 irix_asm_named_section (const char *name, unsigned int flags)
9616 if (TARGET_SGI_O32_AS)
9617 default_no_named_section (name, flags);
9618 else if (mips_abi == ABI_32 && TARGET_GAS)
9619 default_elf_asm_named_section (name, flags);
9621 irix_asm_named_section_1 (name, flags, 0);
9624 /* In addition to emitting a .align directive, record the maximum
9625 alignment requested for the current section. */
9627 struct irix_section_align_entry GTY (())
9634 static htab_t irix_section_align_htab;
9635 static FILE *irix_orig_asm_out_file;
9638 irix_section_align_entry_eq (const void *p1, const void *p2)
9640 const struct irix_section_align_entry *old = p1;
9641 const char *new = p2;
9643 return strcmp (old->name, new) == 0;
9647 irix_section_align_entry_hash (const void *p)
9649 const struct irix_section_align_entry *old = p;
9650 return htab_hash_string (old->name);
9654 irix_asm_output_align (FILE *file, unsigned int log)
9656 const char *section = current_section_name ();
9657 struct irix_section_align_entry **slot, *entry;
9659 if (mips_abi != ABI_32)
9664 slot = (struct irix_section_align_entry **)
9665 htab_find_slot_with_hash (irix_section_align_htab, section,
9666 htab_hash_string (section), INSERT);
9670 entry = (struct irix_section_align_entry *)
9671 xmalloc (sizeof (struct irix_section_align_entry));
9673 entry->name = section;
9675 entry->flags = current_section_flags ();
9677 else if (entry->log < log)
9681 fprintf (file, "\t.align\t%u\n", log);
9684 /* The IRIX assembler does not record alignment from .align directives,
9685 but takes it from the first .section directive seen. Play file
9686 switching games so that we can emit a .section directive at the
9687 beginning of the file with the proper alignment attached. */
9690 irix_file_start (void)
9694 if (mips_abi == ABI_32)
9697 irix_orig_asm_out_file = asm_out_file;
9698 asm_out_file = tmpfile ();
9700 irix_section_align_htab = htab_create (31, irix_section_align_entry_hash,
9701 irix_section_align_entry_eq, NULL);
9705 irix_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
9707 const struct irix_section_align_entry *entry
9708 = *(const struct irix_section_align_entry **) slot;
9710 irix_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
9715 copy_file_data (FILE *to, FILE *from)
9721 fatal_error ("can't rewind temp file: %m");
9723 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
9724 if (fwrite (buffer, 1, len, to) != len)
9725 fatal_error ("can't write to output file: %m");
9728 fatal_error ("can't read from temp file: %m");
9731 fatal_error ("can't close temp file: %m");
9735 irix_file_end (void)
9737 if (mips_abi != ABI_32)
9739 /* Emit section directives with the proper alignment at the top of the
9740 real output file. */
9741 FILE *temp = asm_out_file;
9742 asm_out_file = irix_orig_asm_out_file;
9743 htab_traverse (irix_section_align_htab, irix_section_align_1, NULL);
9745 /* Copy the data emitted to the temp file to the real output file. */
9746 copy_file_data (asm_out_file, temp);
9753 /* Implement TARGET_SECTION_TYPE_FLAGS. Make sure that .sdata and
9754 .sbss sections get the SECTION_SMALL flag: this isn't set by the
9758 irix_section_type_flags (tree decl, const char *section, int relocs_p)
9762 flags = default_section_type_flags (decl, section, relocs_p);
9764 if (strcmp (section, ".sdata") == 0
9765 || strcmp (section, ".sbss") == 0
9766 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9767 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9768 flags |= SECTION_SMALL;
9773 #endif /* TARGET_IRIX */
9775 #include "gt-mips.h"