1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
60 #include "diagnostic.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (NONDEBUG_INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Return the opcode for a ptr_mode load of the form:
130 l[wd] DEST, OFFSET(BASE). */
131 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
132 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
137 /* Return the opcode to move register SRC into register DEST. */
138 #define MIPS_MOVE(DEST, SRC) \
139 ((TARGET_64BIT ? 0x2d : 0x21) \
143 /* Return the opcode for:
146 #define MIPS_LUI(DEST, VALUE) \
147 ((0xf << 26) | ((DEST) << 16) | (VALUE))
149 /* Return the opcode to jump to register DEST. */
150 #define MIPS_JR(DEST) \
151 (((DEST) << 21) | 0x8)
153 /* Return the opcode for:
155 bal . + (1 + OFFSET) * 4. */
156 #define MIPS_BAL(OFFSET) \
157 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
159 /* Return the usual opcode for a nop. */
162 /* Classifies an address.
165 A natural register + offset address. The register satisfies
166 mips_valid_base_register_p and the offset is a const_arith_operand.
169 A LO_SUM rtx. The first operand is a valid base register and
170 the second operand is a symbolic address.
173 A signed 16-bit constant address.
176 A constant symbolic address. */
177 enum mips_address_type {
184 /* Enumerates the setting of the -mr10k-cache-barrier option. */
185 enum mips_r10k_cache_barrier_setting {
186 R10K_CACHE_BARRIER_NONE,
187 R10K_CACHE_BARRIER_STORE,
188 R10K_CACHE_BARRIER_LOAD_STORE
191 /* Macros to create an enumeration identifier for a function prototype. */
192 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
193 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
194 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
195 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
197 /* Classifies the prototype of a built-in function. */
198 enum mips_function_type {
199 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
200 #include "config/mips/mips-ftypes.def"
201 #undef DEF_MIPS_FTYPE
205 /* Specifies how a built-in function should be converted into rtl. */
206 enum mips_builtin_type {
207 /* The function corresponds directly to an .md pattern. The return
208 value is mapped to operand 0 and the arguments are mapped to
209 operands 1 and above. */
212 /* The function corresponds directly to an .md pattern. There is no return
213 value and the arguments are mapped to operands 0 and above. */
214 MIPS_BUILTIN_DIRECT_NO_TARGET,
216 /* The function corresponds to a comparison instruction followed by
217 a mips_cond_move_tf_ps pattern. The first two arguments are the
218 values to compare and the second two arguments are the vector
219 operands for the movt.ps or movf.ps instruction (in assembly order). */
223 /* The function corresponds to a V2SF comparison instruction. Operand 0
224 of this instruction is the result of the comparison, which has mode
225 CCV2 or CCV4. The function arguments are mapped to operands 1 and
226 above. The function's return value is an SImode boolean that is
227 true under the following conditions:
229 MIPS_BUILTIN_CMP_ANY: one of the registers is true
230 MIPS_BUILTIN_CMP_ALL: all of the registers are true
231 MIPS_BUILTIN_CMP_LOWER: the first register is true
232 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
233 MIPS_BUILTIN_CMP_ANY,
234 MIPS_BUILTIN_CMP_ALL,
235 MIPS_BUILTIN_CMP_UPPER,
236 MIPS_BUILTIN_CMP_LOWER,
238 /* As above, but the instruction only sets a single $fcc register. */
239 MIPS_BUILTIN_CMP_SINGLE,
241 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
242 MIPS_BUILTIN_BPOSGE32
245 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
246 #define MIPS_FP_CONDITIONS(MACRO) \
264 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
265 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
266 enum mips_fp_condition {
267 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
270 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
271 #define STRINGIFY(X) #X
272 static const char *const mips_fp_conditions[] = {
273 MIPS_FP_CONDITIONS (STRINGIFY)
276 /* Information about a function's frame layout. */
277 struct GTY(()) mips_frame_info {
278 /* The size of the frame in bytes. */
279 HOST_WIDE_INT total_size;
281 /* The number of bytes allocated to variables. */
282 HOST_WIDE_INT var_size;
284 /* The number of bytes allocated to outgoing function arguments. */
285 HOST_WIDE_INT args_size;
287 /* The number of bytes allocated to the .cprestore slot, or 0 if there
289 HOST_WIDE_INT cprestore_size;
291 /* Bit X is set if the function saves or restores GPR X. */
294 /* Likewise FPR X. */
297 /* Likewise doubleword accumulator X ($acX). */
298 unsigned int acc_mask;
300 /* The number of GPRs, FPRs, doubleword accumulators and COP0
304 unsigned int num_acc;
305 unsigned int num_cop0_regs;
307 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
308 save slots from the top of the frame, or zero if no such slots are
310 HOST_WIDE_INT gp_save_offset;
311 HOST_WIDE_INT fp_save_offset;
312 HOST_WIDE_INT acc_save_offset;
313 HOST_WIDE_INT cop0_save_offset;
315 /* Likewise, but giving offsets from the bottom of the frame. */
316 HOST_WIDE_INT gp_sp_offset;
317 HOST_WIDE_INT fp_sp_offset;
318 HOST_WIDE_INT acc_sp_offset;
319 HOST_WIDE_INT cop0_sp_offset;
321 /* Similar, but the value passed to _mcount. */
322 HOST_WIDE_INT ra_fp_offset;
324 /* The offset of arg_pointer_rtx from the bottom of the frame. */
325 HOST_WIDE_INT arg_pointer_offset;
327 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
328 HOST_WIDE_INT hard_frame_pointer_offset;
331 struct GTY(()) machine_function {
332 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
333 rtx mips16_gp_pseudo_rtx;
335 /* The number of extra stack bytes taken up by register varargs.
336 This area is allocated by the callee at the very top of the frame. */
339 /* The current frame information, calculated by mips_compute_frame_info. */
340 struct mips_frame_info frame;
342 /* The register to use as the function's global pointer, or INVALID_REGNUM
343 if the function doesn't need one. */
344 unsigned int global_pointer;
346 /* How many instructions it takes to load a label into $AT, or 0 if
347 this property hasn't yet been calculated. */
348 unsigned int load_label_length;
350 /* True if mips_adjust_insn_length should ignore an instruction's
352 bool ignore_hazard_length_p;
354 /* True if the whole function is suitable for .set noreorder and
356 bool all_noreorder_p;
358 /* True if the function has "inflexible" and "flexible" references
359 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
360 and mips_cfun_has_flexible_gp_ref_p for details. */
361 bool has_inflexible_gp_insn_p;
362 bool has_flexible_gp_insn_p;
364 /* True if the function's prologue must load the global pointer
365 value into pic_offset_table_rtx and store the same value in
366 the function's cprestore slot (if any). Even if this value
367 is currently false, we may decide to set it to true later;
368 see mips_must_initialize_gp_p () for details. */
369 bool must_initialize_gp_p;
371 /* True if the current function must restore $gp after any potential
372 clobber. This value is only meaningful during the first post-epilogue
373 split_insns pass; see mips_must_initialize_gp_p () for details. */
374 bool must_restore_gp_when_clobbered_p;
376 /* True if we have emitted an instruction to initialize
377 mips16_gp_pseudo_rtx. */
378 bool initialized_mips16_gp_pseudo_p;
380 /* True if this is an interrupt handler. */
381 bool interrupt_handler_p;
383 /* True if this is an interrupt handler that uses shadow registers. */
384 bool use_shadow_register_set_p;
386 /* True if this is an interrupt handler that should keep interrupts
388 bool keep_interrupts_masked_p;
390 /* True if this is an interrupt handler that should use DERET
392 bool use_debug_exception_return_p;
395 /* Information about a single argument. */
396 struct mips_arg_info {
397 /* True if the argument is passed in a floating-point register, or
398 would have been if we hadn't run out of registers. */
401 /* The number of words passed in registers, rounded up. */
402 unsigned int reg_words;
404 /* For EABI, the offset of the first register from GP_ARG_FIRST or
405 FP_ARG_FIRST. For other ABIs, the offset of the first register from
406 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
407 comment for details).
409 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
411 unsigned int reg_offset;
413 /* The number of words that must be passed on the stack, rounded up. */
414 unsigned int stack_words;
416 /* The offset from the start of the stack overflow area of the argument's
417 first stack word. Only meaningful when STACK_WORDS is nonzero. */
418 unsigned int stack_offset;
421 /* Information about an address described by mips_address_type.
427 REG is the base register and OFFSET is the constant offset.
430 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
431 is the type of symbol it references.
434 SYMBOL_TYPE is the type of symbol that the address references. */
435 struct mips_address_info {
436 enum mips_address_type type;
439 enum mips_symbol_type symbol_type;
442 /* One stage in a constant building sequence. These sequences have
446 A = A CODE[1] VALUE[1]
447 A = A CODE[2] VALUE[2]
450 where A is an accumulator, each CODE[i] is a binary rtl operation
451 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
452 struct mips_integer_op {
454 unsigned HOST_WIDE_INT value;
457 /* The largest number of operations needed to load an integer constant.
458 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
459 When the lowest bit is clear, we can try, but reject a sequence with
460 an extra SLL at the end. */
461 #define MIPS_MAX_INTEGER_OPS 7
463 /* Information about a MIPS16e SAVE or RESTORE instruction. */
464 struct mips16e_save_restore_info {
465 /* The number of argument registers saved by a SAVE instruction.
466 0 for RESTORE instructions. */
469 /* Bit X is set if the instruction saves or restores GPR X. */
472 /* The total number of bytes to allocate. */
476 /* Global variables for machine-dependent things. */
478 /* The -G setting, or the configuration's default small-data limit if
479 no -G option is given. */
480 static unsigned int mips_small_data_threshold;
482 /* The number of file directives written by mips_output_filename. */
483 int num_source_filenames;
485 /* The name that appeared in the last .file directive written by
486 mips_output_filename, or "" if mips_output_filename hasn't
487 written anything yet. */
488 const char *current_function_file = "";
490 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
493 /* Arrays that map GCC register numbers to debugger register numbers. */
494 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
495 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
497 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
498 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
499 struct mips_asm_switch mips_nomacro = { "macro", 0 };
500 struct mips_asm_switch mips_noat = { "at", 0 };
502 /* True if we're writing out a branch-likely instruction rather than a
504 static bool mips_branch_likely;
506 /* The current instruction-set architecture. */
507 enum processor_type mips_arch;
508 const struct mips_cpu_info *mips_arch_info;
510 /* The processor that we should tune the code for. */
511 enum processor_type mips_tune;
512 const struct mips_cpu_info *mips_tune_info;
514 /* The ISA level associated with mips_arch. */
517 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
518 static const struct mips_cpu_info *mips_isa_option_info;
520 /* Which ABI to use. */
521 int mips_abi = MIPS_ABI_DEFAULT;
523 /* Which cost information to use. */
524 const struct mips_rtx_cost_data *mips_cost;
526 /* The ambient target flags, excluding MASK_MIPS16. */
527 static int mips_base_target_flags;
529 /* True if MIPS16 is the default mode. */
530 bool mips_base_mips16;
532 /* The ambient values of other global variables. */
533 static int mips_base_schedule_insns; /* flag_schedule_insns */
534 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
535 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
536 static int mips_base_align_loops; /* align_loops */
537 static int mips_base_align_jumps; /* align_jumps */
538 static int mips_base_align_functions; /* align_functions */
540 /* The -mcode-readable setting. */
541 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
543 /* The -mr10k-cache-barrier setting. */
544 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
546 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
547 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
549 /* Index C is true if character C is a valid PRINT_OPERAND punctation
551 bool mips_print_operand_punct[256];
553 static GTY (()) int mips_output_filename_first_time = 1;
555 /* mips_split_p[X] is true if symbols of type X can be split by
556 mips_split_symbol. */
557 bool mips_split_p[NUM_SYMBOL_TYPES];
559 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
560 can be split by mips_split_symbol. */
561 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
563 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
564 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
565 if they are matched by a special .md file pattern. */
566 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
568 /* Likewise for HIGHs. */
569 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
571 /* Index R is the smallest register class that contains register R. */
572 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
573 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
574 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
575 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
576 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
577 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
578 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
579 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
580 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
581 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
582 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
583 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
584 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
585 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
586 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
587 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
588 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
589 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
590 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
591 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
592 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
593 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
594 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
595 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
596 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
597 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
598 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
599 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
600 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
601 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
602 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
603 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
604 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
605 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
606 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
607 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
608 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
609 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
610 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
611 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
612 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
613 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
614 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
615 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
616 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
617 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
618 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
619 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
622 /* The value of TARGET_ATTRIBUTE_TABLE. */
623 static const struct attribute_spec mips_attribute_table[] = {
624 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
625 { "long_call", 0, 0, false, true, true, NULL },
626 { "far", 0, 0, false, true, true, NULL },
627 { "near", 0, 0, false, true, true, NULL },
628 /* We would really like to treat "mips16" and "nomips16" as type
629 attributes, but GCC doesn't provide the hooks we need to support
630 the right conversion rules. As declaration attributes, they affect
631 code generation but don't carry other semantics. */
632 { "mips16", 0, 0, true, false, false, NULL },
633 { "nomips16", 0, 0, true, false, false, NULL },
634 /* Allow functions to be specified as interrupt handlers */
635 { "interrupt", 0, 0, false, true, true, NULL },
636 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
637 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
638 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
639 { NULL, 0, 0, false, false, false, NULL }
642 /* A table describing all the processors GCC knows about. Names are
643 matched in the order listed. The first mention of an ISA level is
644 taken as the canonical name for that ISA.
646 To ease comparison, please keep this table in the same order
647 as GAS's mips_cpu_info_table. Please also make sure that
648 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
649 options correctly. */
650 static const struct mips_cpu_info mips_cpu_info_table[] = {
651 /* Entries for generic ISAs. */
652 { "mips1", PROCESSOR_R3000, 1, 0 },
653 { "mips2", PROCESSOR_R6000, 2, 0 },
654 { "mips3", PROCESSOR_R4000, 3, 0 },
655 { "mips4", PROCESSOR_R8000, 4, 0 },
656 /* Prefer not to use branch-likely instructions for generic MIPS32rX
657 and MIPS64rX code. The instructions were officially deprecated
658 in revisions 2 and earlier, but revision 3 is likely to downgrade
659 that to a recommendation to avoid the instructions in code that
660 isn't tuned to a specific processor. */
661 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
662 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
663 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
664 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
665 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
667 /* MIPS I processors. */
668 { "r3000", PROCESSOR_R3000, 1, 0 },
669 { "r2000", PROCESSOR_R3000, 1, 0 },
670 { "r3900", PROCESSOR_R3900, 1, 0 },
672 /* MIPS II processors. */
673 { "r6000", PROCESSOR_R6000, 2, 0 },
675 /* MIPS III processors. */
676 { "r4000", PROCESSOR_R4000, 3, 0 },
677 { "vr4100", PROCESSOR_R4100, 3, 0 },
678 { "vr4111", PROCESSOR_R4111, 3, 0 },
679 { "vr4120", PROCESSOR_R4120, 3, 0 },
680 { "vr4130", PROCESSOR_R4130, 3, 0 },
681 { "vr4300", PROCESSOR_R4300, 3, 0 },
682 { "r4400", PROCESSOR_R4000, 3, 0 },
683 { "r4600", PROCESSOR_R4600, 3, 0 },
684 { "orion", PROCESSOR_R4600, 3, 0 },
685 { "r4650", PROCESSOR_R4650, 3, 0 },
686 /* ST Loongson 2E/2F processors. */
687 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
688 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
690 /* MIPS IV processors. */
691 { "r8000", PROCESSOR_R8000, 4, 0 },
692 { "r10000", PROCESSOR_R10000, 4, 0 },
693 { "r12000", PROCESSOR_R10000, 4, 0 },
694 { "r14000", PROCESSOR_R10000, 4, 0 },
695 { "r16000", PROCESSOR_R10000, 4, 0 },
696 { "vr5000", PROCESSOR_R5000, 4, 0 },
697 { "vr5400", PROCESSOR_R5400, 4, 0 },
698 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
699 { "rm7000", PROCESSOR_R7000, 4, 0 },
700 { "rm9000", PROCESSOR_R9000, 4, 0 },
702 /* MIPS32 processors. */
703 { "4kc", PROCESSOR_4KC, 32, 0 },
704 { "4km", PROCESSOR_4KC, 32, 0 },
705 { "4kp", PROCESSOR_4KP, 32, 0 },
706 { "4ksc", PROCESSOR_4KC, 32, 0 },
708 /* MIPS32 Release 2 processors. */
709 { "m4k", PROCESSOR_M4K, 33, 0 },
710 { "4kec", PROCESSOR_4KC, 33, 0 },
711 { "4kem", PROCESSOR_4KC, 33, 0 },
712 { "4kep", PROCESSOR_4KP, 33, 0 },
713 { "4ksd", PROCESSOR_4KC, 33, 0 },
715 { "24kc", PROCESSOR_24KC, 33, 0 },
716 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
717 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
718 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
719 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
720 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
722 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
723 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
724 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
725 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
726 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
727 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
729 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
730 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
731 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
732 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
733 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
734 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
736 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
737 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
738 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
739 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
740 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
741 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
742 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
744 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
745 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
746 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
747 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
749 /* MIPS64 processors. */
750 { "5kc", PROCESSOR_5KC, 64, 0 },
751 { "5kf", PROCESSOR_5KF, 64, 0 },
752 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
753 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
754 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
755 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
756 { "xlr", PROCESSOR_XLR, 64, 0 },
758 /* MIPS64 Release 2 processors. */
759 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
762 /* Default costs. If these are used for a processor we should look
763 up the actual costs. */
764 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
765 COSTS_N_INSNS (7), /* fp_mult_sf */ \
766 COSTS_N_INSNS (8), /* fp_mult_df */ \
767 COSTS_N_INSNS (23), /* fp_div_sf */ \
768 COSTS_N_INSNS (36), /* fp_div_df */ \
769 COSTS_N_INSNS (10), /* int_mult_si */ \
770 COSTS_N_INSNS (10), /* int_mult_di */ \
771 COSTS_N_INSNS (69), /* int_div_si */ \
772 COSTS_N_INSNS (69), /* int_div_di */ \
773 2, /* branch_cost */ \
774 4 /* memory_latency */
776 /* Floating-point costs for processors without an FPU. Just assume that
777 all floating-point libcalls are very expensive. */
778 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
779 COSTS_N_INSNS (256), /* fp_mult_sf */ \
780 COSTS_N_INSNS (256), /* fp_mult_df */ \
781 COSTS_N_INSNS (256), /* fp_div_sf */ \
782 COSTS_N_INSNS (256) /* fp_div_df */
784 /* Costs to use when optimizing for size. */
785 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
786 COSTS_N_INSNS (1), /* fp_add */
787 COSTS_N_INSNS (1), /* fp_mult_sf */
788 COSTS_N_INSNS (1), /* fp_mult_df */
789 COSTS_N_INSNS (1), /* fp_div_sf */
790 COSTS_N_INSNS (1), /* fp_div_df */
791 COSTS_N_INSNS (1), /* int_mult_si */
792 COSTS_N_INSNS (1), /* int_mult_di */
793 COSTS_N_INSNS (1), /* int_div_si */
794 COSTS_N_INSNS (1), /* int_div_di */
796 4 /* memory_latency */
799 /* Costs to use when optimizing for speed, indexed by processor. */
800 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
802 COSTS_N_INSNS (2), /* fp_add */
803 COSTS_N_INSNS (4), /* fp_mult_sf */
804 COSTS_N_INSNS (5), /* fp_mult_df */
805 COSTS_N_INSNS (12), /* fp_div_sf */
806 COSTS_N_INSNS (19), /* fp_div_df */
807 COSTS_N_INSNS (12), /* int_mult_si */
808 COSTS_N_INSNS (12), /* int_mult_di */
809 COSTS_N_INSNS (35), /* int_div_si */
810 COSTS_N_INSNS (35), /* int_div_di */
812 4 /* memory_latency */
816 COSTS_N_INSNS (6), /* int_mult_si */
817 COSTS_N_INSNS (6), /* int_mult_di */
818 COSTS_N_INSNS (36), /* int_div_si */
819 COSTS_N_INSNS (36), /* int_div_di */
821 4 /* memory_latency */
825 COSTS_N_INSNS (36), /* int_mult_si */
826 COSTS_N_INSNS (36), /* int_mult_di */
827 COSTS_N_INSNS (37), /* int_div_si */
828 COSTS_N_INSNS (37), /* int_div_di */
830 4 /* memory_latency */
834 COSTS_N_INSNS (4), /* int_mult_si */
835 COSTS_N_INSNS (11), /* int_mult_di */
836 COSTS_N_INSNS (36), /* int_div_si */
837 COSTS_N_INSNS (68), /* int_div_di */
839 4 /* memory_latency */
842 COSTS_N_INSNS (4), /* fp_add */
843 COSTS_N_INSNS (4), /* fp_mult_sf */
844 COSTS_N_INSNS (5), /* fp_mult_df */
845 COSTS_N_INSNS (17), /* fp_div_sf */
846 COSTS_N_INSNS (32), /* fp_div_df */
847 COSTS_N_INSNS (4), /* int_mult_si */
848 COSTS_N_INSNS (11), /* int_mult_di */
849 COSTS_N_INSNS (36), /* int_div_si */
850 COSTS_N_INSNS (68), /* int_div_di */
852 4 /* memory_latency */
855 COSTS_N_INSNS (4), /* fp_add */
856 COSTS_N_INSNS (4), /* fp_mult_sf */
857 COSTS_N_INSNS (5), /* fp_mult_df */
858 COSTS_N_INSNS (17), /* fp_div_sf */
859 COSTS_N_INSNS (32), /* fp_div_df */
860 COSTS_N_INSNS (4), /* int_mult_si */
861 COSTS_N_INSNS (7), /* int_mult_di */
862 COSTS_N_INSNS (42), /* int_div_si */
863 COSTS_N_INSNS (72), /* int_div_di */
865 4 /* memory_latency */
869 COSTS_N_INSNS (5), /* int_mult_si */
870 COSTS_N_INSNS (5), /* int_mult_di */
871 COSTS_N_INSNS (41), /* int_div_si */
872 COSTS_N_INSNS (41), /* int_div_di */
874 4 /* memory_latency */
877 COSTS_N_INSNS (8), /* fp_add */
878 COSTS_N_INSNS (8), /* fp_mult_sf */
879 COSTS_N_INSNS (10), /* fp_mult_df */
880 COSTS_N_INSNS (34), /* fp_div_sf */
881 COSTS_N_INSNS (64), /* fp_div_df */
882 COSTS_N_INSNS (5), /* int_mult_si */
883 COSTS_N_INSNS (5), /* int_mult_di */
884 COSTS_N_INSNS (41), /* int_div_si */
885 COSTS_N_INSNS (41), /* int_div_di */
887 4 /* memory_latency */
890 COSTS_N_INSNS (4), /* fp_add */
891 COSTS_N_INSNS (4), /* fp_mult_sf */
892 COSTS_N_INSNS (5), /* fp_mult_df */
893 COSTS_N_INSNS (17), /* fp_div_sf */
894 COSTS_N_INSNS (32), /* fp_div_df */
895 COSTS_N_INSNS (5), /* int_mult_si */
896 COSTS_N_INSNS (5), /* int_mult_di */
897 COSTS_N_INSNS (41), /* int_div_si */
898 COSTS_N_INSNS (41), /* int_div_di */
900 4 /* memory_latency */
904 COSTS_N_INSNS (5), /* int_mult_si */
905 COSTS_N_INSNS (5), /* int_mult_di */
906 COSTS_N_INSNS (41), /* int_div_si */
907 COSTS_N_INSNS (41), /* int_div_di */
909 4 /* memory_latency */
912 COSTS_N_INSNS (8), /* fp_add */
913 COSTS_N_INSNS (8), /* fp_mult_sf */
914 COSTS_N_INSNS (10), /* fp_mult_df */
915 COSTS_N_INSNS (34), /* fp_div_sf */
916 COSTS_N_INSNS (64), /* fp_div_df */
917 COSTS_N_INSNS (5), /* int_mult_si */
918 COSTS_N_INSNS (5), /* int_mult_di */
919 COSTS_N_INSNS (41), /* int_div_si */
920 COSTS_N_INSNS (41), /* int_div_di */
922 4 /* memory_latency */
925 COSTS_N_INSNS (4), /* fp_add */
926 COSTS_N_INSNS (4), /* fp_mult_sf */
927 COSTS_N_INSNS (5), /* fp_mult_df */
928 COSTS_N_INSNS (17), /* fp_div_sf */
929 COSTS_N_INSNS (32), /* fp_div_df */
930 COSTS_N_INSNS (5), /* int_mult_si */
931 COSTS_N_INSNS (5), /* int_mult_di */
932 COSTS_N_INSNS (41), /* int_div_si */
933 COSTS_N_INSNS (41), /* int_div_di */
935 4 /* memory_latency */
938 COSTS_N_INSNS (6), /* fp_add */
939 COSTS_N_INSNS (6), /* fp_mult_sf */
940 COSTS_N_INSNS (7), /* fp_mult_df */
941 COSTS_N_INSNS (25), /* fp_div_sf */
942 COSTS_N_INSNS (48), /* fp_div_df */
943 COSTS_N_INSNS (5), /* int_mult_si */
944 COSTS_N_INSNS (5), /* int_mult_di */
945 COSTS_N_INSNS (41), /* int_div_si */
946 COSTS_N_INSNS (41), /* int_div_di */
948 4 /* memory_latency */
962 COSTS_N_INSNS (5), /* int_mult_si */
963 COSTS_N_INSNS (5), /* int_mult_di */
964 COSTS_N_INSNS (72), /* int_div_si */
965 COSTS_N_INSNS (72), /* int_div_di */
967 4 /* memory_latency */
970 COSTS_N_INSNS (2), /* fp_add */
971 COSTS_N_INSNS (4), /* fp_mult_sf */
972 COSTS_N_INSNS (5), /* fp_mult_df */
973 COSTS_N_INSNS (12), /* fp_div_sf */
974 COSTS_N_INSNS (19), /* fp_div_df */
975 COSTS_N_INSNS (2), /* int_mult_si */
976 COSTS_N_INSNS (2), /* int_mult_di */
977 COSTS_N_INSNS (35), /* int_div_si */
978 COSTS_N_INSNS (35), /* int_div_di */
980 4 /* memory_latency */
983 COSTS_N_INSNS (3), /* fp_add */
984 COSTS_N_INSNS (5), /* fp_mult_sf */
985 COSTS_N_INSNS (6), /* fp_mult_df */
986 COSTS_N_INSNS (15), /* fp_div_sf */
987 COSTS_N_INSNS (16), /* fp_div_df */
988 COSTS_N_INSNS (17), /* int_mult_si */
989 COSTS_N_INSNS (17), /* int_mult_di */
990 COSTS_N_INSNS (38), /* int_div_si */
991 COSTS_N_INSNS (38), /* int_div_di */
993 6 /* memory_latency */
996 COSTS_N_INSNS (6), /* fp_add */
997 COSTS_N_INSNS (7), /* fp_mult_sf */
998 COSTS_N_INSNS (8), /* fp_mult_df */
999 COSTS_N_INSNS (23), /* fp_div_sf */
1000 COSTS_N_INSNS (36), /* fp_div_df */
1001 COSTS_N_INSNS (10), /* int_mult_si */
1002 COSTS_N_INSNS (10), /* int_mult_di */
1003 COSTS_N_INSNS (69), /* int_div_si */
1004 COSTS_N_INSNS (69), /* int_div_di */
1005 2, /* branch_cost */
1006 6 /* memory_latency */
1018 /* The only costs that appear to be updated here are
1019 integer multiplication. */
1021 COSTS_N_INSNS (4), /* int_mult_si */
1022 COSTS_N_INSNS (6), /* int_mult_di */
1023 COSTS_N_INSNS (69), /* int_div_si */
1024 COSTS_N_INSNS (69), /* int_div_di */
1025 1, /* branch_cost */
1026 4 /* memory_latency */
1038 COSTS_N_INSNS (6), /* fp_add */
1039 COSTS_N_INSNS (4), /* fp_mult_sf */
1040 COSTS_N_INSNS (5), /* fp_mult_df */
1041 COSTS_N_INSNS (23), /* fp_div_sf */
1042 COSTS_N_INSNS (36), /* fp_div_df */
1043 COSTS_N_INSNS (5), /* int_mult_si */
1044 COSTS_N_INSNS (5), /* int_mult_di */
1045 COSTS_N_INSNS (36), /* int_div_si */
1046 COSTS_N_INSNS (36), /* int_div_di */
1047 1, /* branch_cost */
1048 4 /* memory_latency */
1051 COSTS_N_INSNS (6), /* fp_add */
1052 COSTS_N_INSNS (5), /* fp_mult_sf */
1053 COSTS_N_INSNS (6), /* fp_mult_df */
1054 COSTS_N_INSNS (30), /* fp_div_sf */
1055 COSTS_N_INSNS (59), /* fp_div_df */
1056 COSTS_N_INSNS (3), /* int_mult_si */
1057 COSTS_N_INSNS (4), /* int_mult_di */
1058 COSTS_N_INSNS (42), /* int_div_si */
1059 COSTS_N_INSNS (74), /* int_div_di */
1060 1, /* branch_cost */
1061 4 /* memory_latency */
1064 COSTS_N_INSNS (6), /* fp_add */
1065 COSTS_N_INSNS (5), /* fp_mult_sf */
1066 COSTS_N_INSNS (6), /* fp_mult_df */
1067 COSTS_N_INSNS (30), /* fp_div_sf */
1068 COSTS_N_INSNS (59), /* fp_div_df */
1069 COSTS_N_INSNS (5), /* int_mult_si */
1070 COSTS_N_INSNS (9), /* int_mult_di */
1071 COSTS_N_INSNS (42), /* int_div_si */
1072 COSTS_N_INSNS (74), /* int_div_di */
1073 1, /* branch_cost */
1074 4 /* memory_latency */
1077 /* The only costs that are changed here are
1078 integer multiplication. */
1079 COSTS_N_INSNS (6), /* fp_add */
1080 COSTS_N_INSNS (7), /* fp_mult_sf */
1081 COSTS_N_INSNS (8), /* fp_mult_df */
1082 COSTS_N_INSNS (23), /* fp_div_sf */
1083 COSTS_N_INSNS (36), /* fp_div_df */
1084 COSTS_N_INSNS (5), /* int_mult_si */
1085 COSTS_N_INSNS (9), /* int_mult_di */
1086 COSTS_N_INSNS (69), /* int_div_si */
1087 COSTS_N_INSNS (69), /* int_div_di */
1088 1, /* branch_cost */
1089 4 /* memory_latency */
1095 /* The only costs that are changed here are
1096 integer multiplication. */
1097 COSTS_N_INSNS (6), /* fp_add */
1098 COSTS_N_INSNS (7), /* fp_mult_sf */
1099 COSTS_N_INSNS (8), /* fp_mult_df */
1100 COSTS_N_INSNS (23), /* fp_div_sf */
1101 COSTS_N_INSNS (36), /* fp_div_df */
1102 COSTS_N_INSNS (3), /* int_mult_si */
1103 COSTS_N_INSNS (8), /* int_mult_di */
1104 COSTS_N_INSNS (69), /* int_div_si */
1105 COSTS_N_INSNS (69), /* int_div_di */
1106 1, /* branch_cost */
1107 4 /* memory_latency */
1110 COSTS_N_INSNS (2), /* fp_add */
1111 COSTS_N_INSNS (2), /* fp_mult_sf */
1112 COSTS_N_INSNS (2), /* fp_mult_df */
1113 COSTS_N_INSNS (12), /* fp_div_sf */
1114 COSTS_N_INSNS (19), /* fp_div_df */
1115 COSTS_N_INSNS (5), /* int_mult_si */
1116 COSTS_N_INSNS (9), /* int_mult_di */
1117 COSTS_N_INSNS (34), /* int_div_si */
1118 COSTS_N_INSNS (66), /* int_div_di */
1119 1, /* branch_cost */
1120 4 /* memory_latency */
1123 /* These costs are the same as the SB-1A below. */
1124 COSTS_N_INSNS (4), /* fp_add */
1125 COSTS_N_INSNS (4), /* fp_mult_sf */
1126 COSTS_N_INSNS (4), /* fp_mult_df */
1127 COSTS_N_INSNS (24), /* fp_div_sf */
1128 COSTS_N_INSNS (32), /* fp_div_df */
1129 COSTS_N_INSNS (3), /* int_mult_si */
1130 COSTS_N_INSNS (4), /* int_mult_di */
1131 COSTS_N_INSNS (36), /* int_div_si */
1132 COSTS_N_INSNS (68), /* int_div_di */
1133 1, /* branch_cost */
1134 4 /* memory_latency */
1137 /* These costs are the same as the SB-1 above. */
1138 COSTS_N_INSNS (4), /* fp_add */
1139 COSTS_N_INSNS (4), /* fp_mult_sf */
1140 COSTS_N_INSNS (4), /* fp_mult_df */
1141 COSTS_N_INSNS (24), /* fp_div_sf */
1142 COSTS_N_INSNS (32), /* fp_div_df */
1143 COSTS_N_INSNS (3), /* int_mult_si */
1144 COSTS_N_INSNS (4), /* int_mult_di */
1145 COSTS_N_INSNS (36), /* int_div_si */
1146 COSTS_N_INSNS (68), /* int_div_di */
1147 1, /* branch_cost */
1148 4 /* memory_latency */
1155 COSTS_N_INSNS (8), /* int_mult_si */
1156 COSTS_N_INSNS (8), /* int_mult_di */
1157 COSTS_N_INSNS (72), /* int_div_si */
1158 COSTS_N_INSNS (72), /* int_div_di */
1159 1, /* branch_cost */
1160 4 /* memory_latency */
1164 static rtx mips_find_pic_call_symbol (rtx, rtx);
1166 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1167 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1168 struct GTY (()) mflip_mips16_entry {
1172 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1174 /* Hash table callbacks for mflip_mips16_htab. */
1177 mflip_mips16_htab_hash (const void *entry)
1179 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1183 mflip_mips16_htab_eq (const void *entry, const void *name)
1185 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1186 (const char *) name) == 0;
1189 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1190 mode, false if it should next add an attribute for the opposite mode. */
1191 static GTY(()) bool mips16_flipper;
1193 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1194 for -mflip-mips16. Return true if it should use "mips16" and false if
1195 it should use "nomips16". */
1198 mflip_mips16_use_mips16_p (tree decl)
1200 struct mflip_mips16_entry *entry;
1205 /* Use the opposite of the command-line setting for anonymous decls. */
1206 if (!DECL_NAME (decl))
1207 return !mips_base_mips16;
1209 if (!mflip_mips16_htab)
1210 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1211 mflip_mips16_htab_eq, NULL);
1213 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1214 hash = htab_hash_string (name);
1215 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1216 entry = (struct mflip_mips16_entry *) *slot;
1219 mips16_flipper = !mips16_flipper;
1220 entry = GGC_NEW (struct mflip_mips16_entry);
1222 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1225 return entry->mips16_p;
1228 /* Predicates to test for presence of "near" and "far"/"long_call"
1229 attributes on the given TYPE. */
1232 mips_near_type_p (const_tree type)
1234 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1238 mips_far_type_p (const_tree type)
1240 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1241 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1244 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1247 mips_mips16_decl_p (const_tree decl)
1249 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1253 mips_nomips16_decl_p (const_tree decl)
1255 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1258 /* Check if the interrupt attribute is set for a function. */
1261 mips_interrupt_type_p (tree type)
1263 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1266 /* Check if the attribute to use shadow register set is set for a function. */
1269 mips_use_shadow_register_set_p (tree type)
1271 return lookup_attribute ("use_shadow_register_set",
1272 TYPE_ATTRIBUTES (type)) != NULL;
1275 /* Check if the attribute to keep interrupts masked is set for a function. */
1278 mips_keep_interrupts_masked_p (tree type)
1280 return lookup_attribute ("keep_interrupts_masked",
1281 TYPE_ATTRIBUTES (type)) != NULL;
1284 /* Check if the attribute to use debug exception return is set for
1288 mips_use_debug_exception_return_p (tree type)
1290 return lookup_attribute ("use_debug_exception_return",
1291 TYPE_ATTRIBUTES (type)) != NULL;
1294 /* Return true if function DECL is a MIPS16 function. Return the ambient
1295 setting if DECL is null. */
1298 mips_use_mips16_mode_p (tree decl)
1302 /* Nested functions must use the same frame pointer as their
1303 parent and must therefore use the same ISA mode. */
1304 tree parent = decl_function_context (decl);
1307 if (mips_mips16_decl_p (decl))
1309 if (mips_nomips16_decl_p (decl))
1312 return mips_base_mips16;
1315 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1318 mips_comp_type_attributes (const_tree type1, const_tree type2)
1320 /* Disallow mixed near/far attributes. */
1321 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1323 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1328 /* Implement TARGET_INSERT_ATTRIBUTES. */
1331 mips_insert_attributes (tree decl, tree *attributes)
1334 bool mips16_p, nomips16_p;
1336 /* Check for "mips16" and "nomips16" attributes. */
1337 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1338 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1339 if (TREE_CODE (decl) != FUNCTION_DECL)
1342 error ("%qs attribute only applies to functions", "mips16");
1344 error ("%qs attribute only applies to functions", "nomips16");
1348 mips16_p |= mips_mips16_decl_p (decl);
1349 nomips16_p |= mips_nomips16_decl_p (decl);
1350 if (mips16_p || nomips16_p)
1352 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1353 if (mips16_p && nomips16_p)
1354 error ("%qE cannot have both %<mips16%> and "
1355 "%<nomips16%> attributes",
1358 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1360 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1361 "mips16" attribute, arbitrarily pick one. We must pick the same
1362 setting for duplicate declarations of a function. */
1363 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1364 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1369 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1372 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1374 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1375 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1376 error ("%qE redeclared with conflicting %qs attributes",
1377 DECL_NAME (newdecl), "mips16");
1378 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1379 error ("%qE redeclared with conflicting %qs attributes",
1380 DECL_NAME (newdecl), "nomips16");
1382 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1383 DECL_ATTRIBUTES (newdecl));
1386 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1387 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1390 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1392 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1394 *base_ptr = XEXP (x, 0);
1395 *offset_ptr = INTVAL (XEXP (x, 1));
1404 static unsigned int mips_build_integer (struct mips_integer_op *,
1405 unsigned HOST_WIDE_INT);
1407 /* A subroutine of mips_build_integer, with the same interface.
1408 Assume that the final action in the sequence should be a left shift. */
1411 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1413 unsigned int i, shift;
1415 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1416 since signed numbers are easier to load than unsigned ones. */
1418 while ((value & 1) == 0)
1419 value /= 2, shift++;
1421 i = mips_build_integer (codes, value);
1422 codes[i].code = ASHIFT;
1423 codes[i].value = shift;
1427 /* As for mips_build_shift, but assume that the final action will be
1428 an IOR or PLUS operation. */
1431 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1433 unsigned HOST_WIDE_INT high;
1436 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1437 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1439 /* The constant is too complex to load with a simple LUI/ORI pair,
1440 so we want to give the recursive call as many trailing zeros as
1441 possible. In this case, we know bit 16 is set and that the
1442 low 16 bits form a negative number. If we subtract that number
1443 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1444 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1445 codes[i].code = PLUS;
1446 codes[i].value = CONST_LOW_PART (value);
1450 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1451 bits gives a value with at least 17 trailing zeros. */
1452 i = mips_build_integer (codes, high);
1453 codes[i].code = IOR;
1454 codes[i].value = value & 0xffff;
1459 /* Fill CODES with a sequence of rtl operations to load VALUE.
1460 Return the number of operations needed. */
1463 mips_build_integer (struct mips_integer_op *codes,
1464 unsigned HOST_WIDE_INT value)
1466 if (SMALL_OPERAND (value)
1467 || SMALL_OPERAND_UNSIGNED (value)
1468 || LUI_OPERAND (value))
1470 /* The value can be loaded with a single instruction. */
1471 codes[0].code = UNKNOWN;
1472 codes[0].value = value;
1475 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1477 /* Either the constant is a simple LUI/ORI combination or its
1478 lowest bit is set. We don't want to shift in this case. */
1479 return mips_build_lower (codes, value);
1481 else if ((value & 0xffff) == 0)
1483 /* The constant will need at least three actions. The lowest
1484 16 bits are clear, so the final action will be a shift. */
1485 return mips_build_shift (codes, value);
1489 /* The final action could be a shift, add or inclusive OR.
1490 Rather than use a complex condition to select the best
1491 approach, try both mips_build_shift and mips_build_lower
1492 and pick the one that gives the shortest sequence.
1493 Note that this case is only used once per constant. */
1494 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1495 unsigned int cost, alt_cost;
1497 cost = mips_build_shift (codes, value);
1498 alt_cost = mips_build_lower (alt_codes, value);
1499 if (alt_cost < cost)
1501 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1508 /* Return true if symbols of type TYPE require a GOT access. */
1511 mips_got_symbol_type_p (enum mips_symbol_type type)
1515 case SYMBOL_GOT_PAGE_OFST:
1516 case SYMBOL_GOT_DISP:
1524 /* Return true if X is a thread-local symbol. */
1527 mips_tls_symbol_p (rtx x)
1529 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1532 /* Return true if SYMBOL_REF X is associated with a global symbol
1533 (in the STB_GLOBAL sense). */
1536 mips_global_symbol_p (const_rtx x)
1538 const_tree decl = SYMBOL_REF_DECL (x);
1541 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1543 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1544 or weak symbols. Relocations in the object file will be against
1545 the target symbol, so it's that symbol's binding that matters here. */
1546 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1549 /* Return true if function X is a libgcc MIPS16 stub function. */
1552 mips16_stub_function_p (const_rtx x)
1554 return (GET_CODE (x) == SYMBOL_REF
1555 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1558 /* Return true if function X is a locally-defined and locally-binding
1562 mips16_local_function_p (const_rtx x)
1564 return (GET_CODE (x) == SYMBOL_REF
1565 && SYMBOL_REF_LOCAL_P (x)
1566 && !SYMBOL_REF_EXTERNAL_P (x)
1567 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1570 /* Return true if SYMBOL_REF X binds locally. */
1573 mips_symbol_binds_local_p (const_rtx x)
1575 return (SYMBOL_REF_DECL (x)
1576 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1577 : SYMBOL_REF_LOCAL_P (x));
1580 /* Return true if rtx constants of mode MODE should be put into a small
1584 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1586 return (!TARGET_EMBEDDED_DATA
1587 && TARGET_LOCAL_SDATA
1588 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1591 /* Return true if X should not be moved directly into register $25.
1592 We need this because many versions of GAS will treat "la $25,foo" as
1593 part of a call sequence and so allow a global "foo" to be lazily bound. */
1596 mips_dangerous_for_la25_p (rtx x)
1598 return (!TARGET_EXPLICIT_RELOCS
1600 && GET_CODE (x) == SYMBOL_REF
1601 && mips_global_symbol_p (x));
1604 /* Return true if calls to X might need $25 to be valid on entry. */
1607 mips_use_pic_fn_addr_reg_p (const_rtx x)
1609 if (!TARGET_USE_PIC_FN_ADDR_REG)
1612 /* MIPS16 stub functions are guaranteed not to use $25. */
1613 if (mips16_stub_function_p (x))
1616 if (GET_CODE (x) == SYMBOL_REF)
1618 /* If PLTs and copy relocations are available, the static linker
1619 will make sure that $25 is valid on entry to the target function. */
1620 if (TARGET_ABICALLS_PIC0)
1623 /* Locally-defined functions use absolute accesses to set up
1624 the global pointer. */
1625 if (TARGET_ABSOLUTE_ABICALLS
1626 && mips_symbol_binds_local_p (x)
1627 && !SYMBOL_REF_EXTERNAL_P (x))
1634 /* Return the method that should be used to access SYMBOL_REF or
1635 LABEL_REF X in context CONTEXT. */
1637 static enum mips_symbol_type
1638 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1641 return SYMBOL_GOT_DISP;
1643 if (GET_CODE (x) == LABEL_REF)
1645 /* LABEL_REFs are used for jump tables as well as text labels.
1646 Only return SYMBOL_PC_RELATIVE if we know the label is in
1647 the text section. */
1648 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1649 return SYMBOL_PC_RELATIVE;
1651 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1652 return SYMBOL_GOT_PAGE_OFST;
1654 return SYMBOL_ABSOLUTE;
1657 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1659 if (SYMBOL_REF_TLS_MODEL (x))
1662 if (CONSTANT_POOL_ADDRESS_P (x))
1664 if (TARGET_MIPS16_TEXT_LOADS)
1665 return SYMBOL_PC_RELATIVE;
1667 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1668 return SYMBOL_PC_RELATIVE;
1670 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1671 return SYMBOL_GP_RELATIVE;
1674 /* Do not use small-data accesses for weak symbols; they may end up
1676 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1677 return SYMBOL_GP_RELATIVE;
1679 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1681 if (TARGET_ABICALLS_PIC2
1682 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1684 /* There are three cases to consider:
1686 - o32 PIC (either with or without explicit relocs)
1687 - n32/n64 PIC without explicit relocs
1688 - n32/n64 PIC with explicit relocs
1690 In the first case, both local and global accesses will use an
1691 R_MIPS_GOT16 relocation. We must correctly predict which of
1692 the two semantics (local or global) the assembler and linker
1693 will apply. The choice depends on the symbol's binding rather
1694 than its visibility.
1696 In the second case, the assembler will not use R_MIPS_GOT16
1697 relocations, but it chooses between local and global accesses
1698 in the same way as for o32 PIC.
1700 In the third case we have more freedom since both forms of
1701 access will work for any kind of symbol. However, there seems
1702 little point in doing things differently. */
1703 if (mips_global_symbol_p (x))
1704 return SYMBOL_GOT_DISP;
1706 return SYMBOL_GOT_PAGE_OFST;
1709 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1710 return SYMBOL_FORCE_TO_MEM;
1712 return SYMBOL_ABSOLUTE;
1715 /* Classify the base of symbolic expression X, given that X appears in
1718 static enum mips_symbol_type
1719 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1723 split_const (x, &x, &offset);
1724 if (UNSPEC_ADDRESS_P (x))
1725 return UNSPEC_ADDRESS_TYPE (x);
1727 return mips_classify_symbol (x, context);
1730 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1731 is the alignment in bytes of SYMBOL_REF X. */
1734 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1736 HOST_WIDE_INT align;
1738 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1739 return IN_RANGE (offset, 0, align - 1);
1742 /* Return true if X is a symbolic constant that can be used in context
1743 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1746 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1747 enum mips_symbol_type *symbol_type)
1751 split_const (x, &x, &offset);
1752 if (UNSPEC_ADDRESS_P (x))
1754 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1755 x = UNSPEC_ADDRESS (x);
1757 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1759 *symbol_type = mips_classify_symbol (x, context);
1760 if (*symbol_type == SYMBOL_TLS)
1766 if (offset == const0_rtx)
1769 /* Check whether a nonzero offset is valid for the underlying
1771 switch (*symbol_type)
1773 case SYMBOL_ABSOLUTE:
1774 case SYMBOL_FORCE_TO_MEM:
1775 case SYMBOL_32_HIGH:
1776 case SYMBOL_64_HIGH:
1779 /* If the target has 64-bit pointers and the object file only
1780 supports 32-bit symbols, the values of those symbols will be
1781 sign-extended. In this case we can't allow an arbitrary offset
1782 in case the 32-bit value X + OFFSET has a different sign from X. */
1783 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1784 return offset_within_block_p (x, INTVAL (offset));
1786 /* In other cases the relocations can handle any offset. */
1789 case SYMBOL_PC_RELATIVE:
1790 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1791 In this case, we no longer have access to the underlying constant,
1792 but the original symbol-based access was known to be valid. */
1793 if (GET_CODE (x) == LABEL_REF)
1798 case SYMBOL_GP_RELATIVE:
1799 /* Make sure that the offset refers to something within the
1800 same object block. This should guarantee that the final
1801 PC- or GP-relative offset is within the 16-bit limit. */
1802 return offset_within_block_p (x, INTVAL (offset));
1804 case SYMBOL_GOT_PAGE_OFST:
1805 case SYMBOL_GOTOFF_PAGE:
1806 /* If the symbol is global, the GOT entry will contain the symbol's
1807 address, and we will apply a 16-bit offset after loading it.
1808 If the symbol is local, the linker should provide enough local
1809 GOT entries for a 16-bit offset, but larger offsets may lead
1811 return SMALL_INT (offset);
1815 /* There is no carry between the HI and LO REL relocations, so the
1816 offset is only valid if we know it won't lead to such a carry. */
1817 return mips_offset_within_alignment_p (x, INTVAL (offset));
1819 case SYMBOL_GOT_DISP:
1820 case SYMBOL_GOTOFF_DISP:
1821 case SYMBOL_GOTOFF_CALL:
1822 case SYMBOL_GOTOFF_LOADGP:
1825 case SYMBOL_GOTTPREL:
1833 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1834 single instruction. We rely on the fact that, in the worst case,
1835 all instructions involved in a MIPS16 address calculation are usually
1839 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1843 case SYMBOL_ABSOLUTE:
1844 /* When using 64-bit symbols, we need 5 preparatory instructions,
1847 lui $at,%highest(symbol)
1848 daddiu $at,$at,%higher(symbol)
1850 daddiu $at,$at,%hi(symbol)
1853 The final address is then $at + %lo(symbol). With 32-bit
1854 symbols we just need a preparatory LUI for normal mode and
1855 a preparatory LI and SLL for MIPS16. */
1856 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1858 case SYMBOL_GP_RELATIVE:
1859 /* Treat GP-relative accesses as taking a single instruction on
1860 MIPS16 too; the copy of $gp can often be shared. */
1863 case SYMBOL_PC_RELATIVE:
1864 /* PC-relative constants can be only be used with ADDIUPC,
1865 DADDIUPC, LWPC and LDPC. */
1866 if (mode == MAX_MACHINE_MODE
1867 || GET_MODE_SIZE (mode) == 4
1868 || GET_MODE_SIZE (mode) == 8)
1871 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1874 case SYMBOL_FORCE_TO_MEM:
1875 /* LEAs will be converted into constant-pool references by
1877 if (mode == MAX_MACHINE_MODE)
1880 /* The constant must be loaded and then dereferenced. */
1883 case SYMBOL_GOT_DISP:
1884 /* The constant will have to be loaded from the GOT before it
1885 is used in an address. */
1886 if (mode != MAX_MACHINE_MODE)
1891 case SYMBOL_GOT_PAGE_OFST:
1892 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1893 local/global classification is accurate. The worst cases are:
1895 (1) For local symbols when generating o32 or o64 code. The assembler
1901 ...and the final address will be $at + %lo(symbol).
1903 (2) For global symbols when -mxgot. The assembler will use:
1905 lui $at,%got_hi(symbol)
1908 ...and the final address will be $at + %got_lo(symbol). */
1911 case SYMBOL_GOTOFF_PAGE:
1912 case SYMBOL_GOTOFF_DISP:
1913 case SYMBOL_GOTOFF_CALL:
1914 case SYMBOL_GOTOFF_LOADGP:
1915 case SYMBOL_32_HIGH:
1916 case SYMBOL_64_HIGH:
1922 case SYMBOL_GOTTPREL:
1925 /* A 16-bit constant formed by a single relocation, or a 32-bit
1926 constant formed from a high 16-bit relocation and a low 16-bit
1927 relocation. Use mips_split_p to determine which. 32-bit
1928 constants need an "lui; addiu" sequence for normal mode and
1929 an "li; sll; addiu" sequence for MIPS16 mode. */
1930 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1933 /* We don't treat a bare TLS symbol as a constant. */
1939 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1940 to load symbols of type TYPE into a register. Return 0 if the given
1941 type of symbol cannot be used as an immediate operand.
1943 Otherwise, return the number of instructions needed to load or store
1944 values of mode MODE to or from addresses of type TYPE. Return 0 if
1945 the given type of symbol is not valid in addresses.
1947 In both cases, treat extended MIPS16 instructions as two instructions. */
1950 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1952 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1955 /* A for_each_rtx callback. Stop the search if *X references a
1956 thread-local symbol. */
1959 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1961 return mips_tls_symbol_p (*x);
1964 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1967 mips_cannot_force_const_mem (rtx x)
1969 enum mips_symbol_type type;
1972 /* There is no assembler syntax for expressing an address-sized
1974 if (GET_CODE (x) == HIGH)
1977 /* As an optimization, reject constants that mips_legitimize_move
1980 Suppose we have a multi-instruction sequence that loads constant C
1981 into register R. If R does not get allocated a hard register, and
1982 R is used in an operand that allows both registers and memory
1983 references, reload will consider forcing C into memory and using
1984 one of the instruction's memory alternatives. Returning false
1985 here will force it to use an input reload instead. */
1986 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
1989 split_const (x, &base, &offset);
1990 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1991 && type != SYMBOL_FORCE_TO_MEM)
1993 /* The same optimization as for CONST_INT. */
1994 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1997 /* If MIPS16 constant pools live in the text section, they should
1998 not refer to anything that might need run-time relocation. */
1999 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2003 /* TLS symbols must be computed by mips_legitimize_move. */
2004 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2010 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2011 constants when we're using a per-function constant pool. */
2014 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2015 const_rtx x ATTRIBUTE_UNUSED)
2017 return !TARGET_MIPS16_PCREL_LOADS;
2020 /* Return true if register REGNO is a valid base register for mode MODE.
2021 STRICT_P is true if REG_OK_STRICT is in effect. */
2024 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2027 if (!HARD_REGISTER_NUM_P (regno))
2031 regno = reg_renumber[regno];
2034 /* These fake registers will be eliminated to either the stack or
2035 hard frame pointer, both of which are usually valid base registers.
2036 Reload deals with the cases where the eliminated form isn't valid. */
2037 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2040 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2041 values, nothing smaller. There are two problems here:
2043 (a) Instantiating virtual registers can introduce new uses of the
2044 stack pointer. If these virtual registers are valid addresses,
2045 the stack pointer should be too.
2047 (b) Most uses of the stack pointer are not made explicit until
2048 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2049 We don't know until that stage whether we'll be eliminating to the
2050 stack pointer (which needs the restriction) or the hard frame
2051 pointer (which doesn't).
2053 All in all, it seems more consistent to only enforce this restriction
2054 during and after reload. */
2055 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2056 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2058 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2061 /* Return true if X is a valid base register for mode MODE.
2062 STRICT_P is true if REG_OK_STRICT is in effect. */
2065 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2067 if (!strict_p && GET_CODE (x) == SUBREG)
2071 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2074 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2075 can address a value of mode MODE. */
2078 mips_valid_offset_p (rtx x, enum machine_mode mode)
2080 /* Check that X is a signed 16-bit number. */
2081 if (!const_arith_operand (x, Pmode))
2084 /* We may need to split multiword moves, so make sure that every word
2086 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2087 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2093 /* Return true if a LO_SUM can address a value of mode MODE when the
2094 LO_SUM symbol has type SYMBOL_TYPE. */
2097 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2099 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2101 if (mips_symbol_insns (symbol_type, mode) == 0)
2104 /* Check that there is a known low-part relocation. */
2105 if (mips_lo_relocs[symbol_type] == NULL)
2108 /* We may need to split multiword moves, so make sure that each word
2109 can be accessed without inducing a carry. This is mainly needed
2110 for o64, which has historically only guaranteed 64-bit alignment
2111 for 128-bit types. */
2112 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2113 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2119 /* Return true if X is a valid address for machine mode MODE. If it is,
2120 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2124 mips_classify_address (struct mips_address_info *info, rtx x,
2125 enum machine_mode mode, bool strict_p)
2127 switch (GET_CODE (x))
2131 info->type = ADDRESS_REG;
2133 info->offset = const0_rtx;
2134 return mips_valid_base_register_p (info->reg, mode, strict_p);
2137 info->type = ADDRESS_REG;
2138 info->reg = XEXP (x, 0);
2139 info->offset = XEXP (x, 1);
2140 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2141 && mips_valid_offset_p (info->offset, mode));
2144 info->type = ADDRESS_LO_SUM;
2145 info->reg = XEXP (x, 0);
2146 info->offset = XEXP (x, 1);
2147 /* We have to trust the creator of the LO_SUM to do something vaguely
2148 sane. Target-independent code that creates a LO_SUM should also
2149 create and verify the matching HIGH. Target-independent code that
2150 adds an offset to a LO_SUM must prove that the offset will not
2151 induce a carry. Failure to do either of these things would be
2152 a bug, and we are not required to check for it here. The MIPS
2153 backend itself should only create LO_SUMs for valid symbolic
2154 constants, with the high part being either a HIGH or a copy
2157 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2158 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2159 && mips_valid_lo_sum_p (info->symbol_type, mode));
2162 /* Small-integer addresses don't occur very often, but they
2163 are legitimate if $0 is a valid base register. */
2164 info->type = ADDRESS_CONST_INT;
2165 return !TARGET_MIPS16 && SMALL_INT (x);
2170 info->type = ADDRESS_SYMBOLIC;
2171 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2173 && mips_symbol_insns (info->symbol_type, mode) > 0
2174 && !mips_split_p[info->symbol_type]);
2181 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2184 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2186 struct mips_address_info addr;
2188 return mips_classify_address (&addr, x, mode, strict_p);
2191 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2194 mips_stack_address_p (rtx x, enum machine_mode mode)
2196 struct mips_address_info addr;
2198 return (mips_classify_address (&addr, x, mode, false)
2199 && addr.type == ADDRESS_REG
2200 && addr.reg == stack_pointer_rtx);
2203 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2204 address instruction. Note that such addresses are not considered
2205 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2206 is so restricted. */
2209 mips_lwxs_address_p (rtx addr)
2212 && GET_CODE (addr) == PLUS
2213 && REG_P (XEXP (addr, 1)))
2215 rtx offset = XEXP (addr, 0);
2216 if (GET_CODE (offset) == MULT
2217 && REG_P (XEXP (offset, 0))
2218 && CONST_INT_P (XEXP (offset, 1))
2219 && INTVAL (XEXP (offset, 1)) == 4)
2225 /* Return true if a value at OFFSET bytes from base register BASE can be
2226 accessed using an unextended MIPS16 instruction. MODE is the mode of
2229 Usually the offset in an unextended instruction is a 5-bit field.
2230 The offset is unsigned and shifted left once for LH and SH, twice
2231 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2232 an 8-bit immediate field that's shifted left twice. */
2235 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2236 unsigned HOST_WIDE_INT offset)
2238 if (offset % GET_MODE_SIZE (mode) == 0)
2240 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2241 return offset < 256U * GET_MODE_SIZE (mode);
2242 return offset < 32U * GET_MODE_SIZE (mode);
2247 /* Return the number of instructions needed to load or store a value
2248 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2249 Assume that multiword moves may need to be split into word moves
2250 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2253 For MIPS16 code, count extended instructions as two instructions. */
2256 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2258 struct mips_address_info addr;
2261 /* BLKmode is used for single unaligned loads and stores and should
2262 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2263 meaningless, so we have to single it out as a special case one way
2265 if (mode != BLKmode && might_split_p)
2266 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2270 if (mips_classify_address (&addr, x, mode, false))
2275 && !mips16_unextended_reference_p (mode, addr.reg,
2276 UINTVAL (addr.offset)))
2280 case ADDRESS_LO_SUM:
2281 return TARGET_MIPS16 ? factor * 2 : factor;
2283 case ADDRESS_CONST_INT:
2286 case ADDRESS_SYMBOLIC:
2287 return factor * mips_symbol_insns (addr.symbol_type, mode);
2292 /* Return the number of instructions needed to load constant X.
2293 Return 0 if X isn't a valid constant. */
2296 mips_const_insns (rtx x)
2298 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2299 enum mips_symbol_type symbol_type;
2302 switch (GET_CODE (x))
2305 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2307 || !mips_split_p[symbol_type])
2310 /* This is simply an LUI for normal mode. It is an extended
2311 LI followed by an extended SLL for MIPS16. */
2312 return TARGET_MIPS16 ? 4 : 1;
2316 /* Unsigned 8-bit constants can be loaded using an unextended
2317 LI instruction. Unsigned 16-bit constants can be loaded
2318 using an extended LI. Negative constants must be loaded
2319 using LI and then negated. */
2320 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2321 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2322 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2323 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2326 return mips_build_integer (codes, INTVAL (x));
2330 /* Allow zeros for normal mode, where we can use $0. */
2331 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2337 /* See if we can refer to X directly. */
2338 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2339 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2341 /* Otherwise try splitting the constant into a base and offset.
2342 If the offset is a 16-bit value, we can load the base address
2343 into a register and then use (D)ADDIU to add in the offset.
2344 If the offset is larger, we can load the base and offset
2345 into separate registers and add them together with (D)ADDU.
2346 However, the latter is only possible before reload; during
2347 and after reload, we must have the option of forcing the
2348 constant into the pool instead. */
2349 split_const (x, &x, &offset);
2352 int n = mips_const_insns (x);
2355 if (SMALL_INT (offset))
2357 else if (!targetm.cannot_force_const_mem (x))
2358 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2365 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2373 /* X is a doubleword constant that can be handled by splitting it into
2374 two words and loading each word separately. Return the number of
2375 instructions required to do this. */
2378 mips_split_const_insns (rtx x)
2380 unsigned int low, high;
2382 low = mips_const_insns (mips_subword (x, false));
2383 high = mips_const_insns (mips_subword (x, true));
2384 gcc_assert (low > 0 && high > 0);
2388 /* Return the number of instructions needed to implement INSN,
2389 given that it loads from or stores to MEM. Count extended
2390 MIPS16 instructions as two instructions. */
2393 mips_load_store_insns (rtx mem, rtx insn)
2395 enum machine_mode mode;
2399 gcc_assert (MEM_P (mem));
2400 mode = GET_MODE (mem);
2402 /* Try to prove that INSN does not need to be split. */
2403 might_split_p = true;
2404 if (GET_MODE_BITSIZE (mode) == 64)
2406 set = single_set (insn);
2407 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2408 might_split_p = false;
2411 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2414 /* Return the number of instructions needed for an integer division. */
2417 mips_idiv_insns (void)
2422 if (TARGET_CHECK_ZERO_DIV)
2424 if (GENERATE_DIVIDE_TRAPS)
2430 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2435 /* Emit a move from SRC to DEST. Assume that the move expanders can
2436 handle all moves if !can_create_pseudo_p (). The distinction is
2437 important because, unlike emit_move_insn, the move expanders know
2438 how to force Pmode objects into the constant pool even when the
2439 constant pool address is not itself legitimate. */
2442 mips_emit_move (rtx dest, rtx src)
2444 return (can_create_pseudo_p ()
2445 ? emit_move_insn (dest, src)
2446 : emit_move_insn_1 (dest, src));
2449 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2452 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2454 emit_insn (gen_rtx_SET (VOIDmode, target,
2455 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2458 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2459 Return that new register. */
2462 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2466 reg = gen_reg_rtx (mode);
2467 mips_emit_unary (code, reg, op0);
2471 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2474 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2476 emit_insn (gen_rtx_SET (VOIDmode, target,
2477 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2480 /* Compute (CODE OP0 OP1) and store the result in a new register
2481 of mode MODE. Return that new register. */
2484 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2488 reg = gen_reg_rtx (mode);
2489 mips_emit_binary (code, reg, op0, op1);
2493 /* Copy VALUE to a register and return that register. If new pseudos
2494 are allowed, copy it into a new register, otherwise use DEST. */
2497 mips_force_temporary (rtx dest, rtx value)
2499 if (can_create_pseudo_p ())
2500 return force_reg (Pmode, value);
2503 mips_emit_move (dest, value);
2508 /* Emit a call sequence with call pattern PATTERN and return the call
2509 instruction itself (which is not necessarily the last instruction
2510 emitted). ORIG_ADDR is the original, unlegitimized address,
2511 ADDR is the legitimized form, and LAZY_P is true if the call
2512 address is lazily-bound. */
2515 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2519 insn = emit_call_insn (pattern);
2521 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2523 /* MIPS16 JALRs only take MIPS16 registers. If the target
2524 function requires $25 to be valid on entry, we must copy it
2525 there separately. The move instruction can be put in the
2526 call's delay slot. */
2527 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2528 emit_insn_before (gen_move_insn (reg, addr), insn);
2529 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2533 /* Lazy-binding stubs require $gp to be valid on entry. */
2534 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2538 /* See the comment above load_call<mode> for details. */
2539 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2540 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2541 emit_insn (gen_update_got_version ());
2546 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2547 then add CONST_INT OFFSET to the result. */
2550 mips_unspec_address_offset (rtx base, rtx offset,
2551 enum mips_symbol_type symbol_type)
2553 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2554 UNSPEC_ADDRESS_FIRST + symbol_type);
2555 if (offset != const0_rtx)
2556 base = gen_rtx_PLUS (Pmode, base, offset);
2557 return gen_rtx_CONST (Pmode, base);
2560 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2561 type SYMBOL_TYPE. */
2564 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2568 split_const (address, &base, &offset);
2569 return mips_unspec_address_offset (base, offset, symbol_type);
2572 /* If OP is an UNSPEC address, return the address to which it refers,
2573 otherwise return OP itself. */
2576 mips_strip_unspec_address (rtx op)
2580 split_const (op, &base, &offset);
2581 if (UNSPEC_ADDRESS_P (base))
2582 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2586 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2587 high part to BASE and return the result. Just return BASE otherwise.
2588 TEMP is as for mips_force_temporary.
2590 The returned expression can be used as the first operand to a LO_SUM. */
2593 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2594 enum mips_symbol_type symbol_type)
2596 if (mips_split_p[symbol_type])
2598 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2599 addr = mips_force_temporary (temp, addr);
2600 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2605 /* Return an instruction that copies $gp into register REG. We want
2606 GCC to treat the register's value as constant, so that its value
2607 can be rematerialized on demand. */
2610 gen_load_const_gp (rtx reg)
2612 return (Pmode == SImode
2613 ? gen_load_const_gp_si (reg)
2614 : gen_load_const_gp_di (reg));
2617 /* Return a pseudo register that contains the value of $gp throughout
2618 the current function. Such registers are needed by MIPS16 functions,
2619 for which $gp itself is not a valid base register or addition operand. */
2622 mips16_gp_pseudo_reg (void)
2624 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2625 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2627 /* Don't emit an instruction to initialize the pseudo register if
2628 we are being called from the tree optimizers' cost-calculation
2630 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2631 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2635 push_topmost_sequence ();
2637 scan = get_insns ();
2638 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2639 scan = NEXT_INSN (scan);
2641 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2642 emit_insn_after (insn, scan);
2644 pop_topmost_sequence ();
2646 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2649 return cfun->machine->mips16_gp_pseudo_rtx;
2652 /* Return a base register that holds pic_offset_table_rtx.
2653 TEMP, if nonnull, is a scratch Pmode base register. */
2656 mips_pic_base_register (rtx temp)
2659 return pic_offset_table_rtx;
2661 if (can_create_pseudo_p ())
2662 return mips16_gp_pseudo_reg ();
2665 /* The first post-reload split exposes all references to $gp
2666 (both uses and definitions). All references must remain
2667 explicit after that point.
2669 It is safe to introduce uses of $gp at any time, so for
2670 simplicity, we do that before the split too. */
2671 mips_emit_move (temp, pic_offset_table_rtx);
2673 emit_insn (gen_load_const_gp (temp));
2677 /* Return the RHS of a load_call<mode> insn. */
2680 mips_unspec_call (rtx reg, rtx symbol)
2684 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2685 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2688 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2689 reference. Return NULL_RTX otherwise. */
2692 mips_strip_unspec_call (rtx src)
2694 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2695 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2699 /* Create and return a GOT reference of type TYPE for address ADDR.
2700 TEMP, if nonnull, is a scratch Pmode base register. */
2703 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2705 rtx base, high, lo_sum_symbol;
2707 base = mips_pic_base_register (temp);
2709 /* If we used the temporary register to load $gp, we can't use
2710 it for the high part as well. */
2711 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2714 high = mips_unspec_offset_high (temp, base, addr, type);
2715 lo_sum_symbol = mips_unspec_address (addr, type);
2717 if (type == SYMBOL_GOTOFF_CALL)
2718 return mips_unspec_call (high, lo_sum_symbol);
2720 return (Pmode == SImode
2721 ? gen_unspec_gotsi (high, lo_sum_symbol)
2722 : gen_unspec_gotdi (high, lo_sum_symbol));
2725 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2726 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2727 constant in that context and can be split into high and low parts.
2728 If so, and if LOW_OUT is nonnull, emit the high part and store the
2729 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2731 TEMP is as for mips_force_temporary and is used to load the high
2732 part into a register.
2734 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2735 a legitimize SET_SRC for an .md pattern, otherwise the low part
2736 is guaranteed to be a legitimate address for mode MODE. */
2739 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2741 enum mips_symbol_context context;
2742 enum mips_symbol_type symbol_type;
2745 context = (mode == MAX_MACHINE_MODE
2746 ? SYMBOL_CONTEXT_LEA
2747 : SYMBOL_CONTEXT_MEM);
2748 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2750 addr = XEXP (addr, 0);
2751 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2752 && mips_symbol_insns (symbol_type, mode) > 0
2753 && mips_split_hi_p[symbol_type])
2756 switch (symbol_type)
2758 case SYMBOL_GOT_PAGE_OFST:
2759 /* The high part of a page/ofst pair is loaded from the GOT. */
2760 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2771 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2772 && mips_symbol_insns (symbol_type, mode) > 0
2773 && mips_split_p[symbol_type])
2776 switch (symbol_type)
2778 case SYMBOL_GOT_DISP:
2779 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2780 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2783 case SYMBOL_GP_RELATIVE:
2784 high = mips_pic_base_register (temp);
2785 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2789 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2790 high = mips_force_temporary (temp, high);
2791 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2800 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2801 mips_force_temporary; it is only needed when OFFSET is not a
2805 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2807 if (!SMALL_OPERAND (offset))
2813 /* Load the full offset into a register so that we can use
2814 an unextended instruction for the address itself. */
2815 high = GEN_INT (offset);
2820 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2821 The addition inside the macro CONST_HIGH_PART may cause an
2822 overflow, so we need to force a sign-extension check. */
2823 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2824 offset = CONST_LOW_PART (offset);
2826 high = mips_force_temporary (temp, high);
2827 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2829 return plus_constant (reg, offset);
2832 /* The __tls_get_attr symbol. */
2833 static GTY(()) rtx mips_tls_symbol;
2835 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2836 the TLS symbol we are referencing and TYPE is the symbol type to use
2837 (either global dynamic or local dynamic). V0 is an RTX for the
2838 return value location. */
2841 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2845 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2847 if (!mips_tls_symbol)
2848 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2850 loc = mips_unspec_address (sym, type);
2854 emit_insn (gen_rtx_SET (Pmode, a0,
2855 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2856 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2857 const0_rtx, NULL_RTX, false);
2858 RTL_CONST_CALL_P (insn) = 1;
2859 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2860 insn = get_insns ();
2867 /* Return a pseudo register that contains the current thread pointer. */
2874 tp = gen_reg_rtx (Pmode);
2875 if (Pmode == DImode)
2876 emit_insn (gen_tls_get_tp_di (tp));
2878 emit_insn (gen_tls_get_tp_si (tp));
2882 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2883 its address. The return value will be both a valid address and a valid
2884 SET_SRC (either a REG or a LO_SUM). */
2887 mips_legitimize_tls_address (rtx loc)
2889 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2890 enum tls_model model;
2894 sorry ("MIPS16 TLS");
2895 return gen_reg_rtx (Pmode);
2898 model = SYMBOL_REF_TLS_MODEL (loc);
2899 /* Only TARGET_ABICALLS code can have more than one module; other
2900 code must be be static and should not use a GOT. All TLS models
2901 reduce to local exec in this situation. */
2902 if (!TARGET_ABICALLS)
2903 model = TLS_MODEL_LOCAL_EXEC;
2907 case TLS_MODEL_GLOBAL_DYNAMIC:
2908 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2909 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2910 dest = gen_reg_rtx (Pmode);
2911 emit_libcall_block (insn, dest, v0, loc);
2914 case TLS_MODEL_LOCAL_DYNAMIC:
2915 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2916 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2917 tmp1 = gen_reg_rtx (Pmode);
2919 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2920 share the LDM result with other LD model accesses. */
2921 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2923 emit_libcall_block (insn, tmp1, v0, eqv);
2925 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2926 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2927 mips_unspec_address (loc, SYMBOL_DTPREL));
2930 case TLS_MODEL_INITIAL_EXEC:
2931 tp = mips_get_tp ();
2932 tmp1 = gen_reg_rtx (Pmode);
2933 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2934 if (Pmode == DImode)
2935 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2937 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2938 dest = gen_reg_rtx (Pmode);
2939 emit_insn (gen_add3_insn (dest, tmp1, tp));
2942 case TLS_MODEL_LOCAL_EXEC:
2943 tp = mips_get_tp ();
2944 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2945 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2946 mips_unspec_address (loc, SYMBOL_TPREL));
2955 /* If X is not a valid address for mode MODE, force it into a register. */
2958 mips_force_address (rtx x, enum machine_mode mode)
2960 if (!mips_legitimate_address_p (mode, x, false))
2961 x = force_reg (Pmode, x);
2965 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2966 be legitimized in a way that the generic machinery might not expect,
2967 return a new address, otherwise return NULL. MODE is the mode of
2968 the memory being accessed. */
2971 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2972 enum machine_mode mode)
2975 HOST_WIDE_INT offset;
2977 if (mips_tls_symbol_p (x))
2978 return mips_legitimize_tls_address (x);
2980 /* See if the address can split into a high part and a LO_SUM. */
2981 if (mips_split_symbol (NULL, x, mode, &addr))
2982 return mips_force_address (addr, mode);
2984 /* Handle BASE + OFFSET using mips_add_offset. */
2985 mips_split_plus (x, &base, &offset);
2988 if (!mips_valid_base_register_p (base, mode, false))
2989 base = copy_to_mode_reg (Pmode, base);
2990 addr = mips_add_offset (NULL, base, offset);
2991 return mips_force_address (addr, mode);
2997 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3000 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3002 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3003 enum machine_mode mode;
3004 unsigned int i, num_ops;
3007 mode = GET_MODE (dest);
3008 num_ops = mips_build_integer (codes, value);
3010 /* Apply each binary operation to X. Invariant: X is a legitimate
3011 source operand for a SET pattern. */
3012 x = GEN_INT (codes[0].value);
3013 for (i = 1; i < num_ops; i++)
3015 if (!can_create_pseudo_p ())
3017 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3021 x = force_reg (mode, x);
3022 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3025 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3028 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3029 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3033 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3037 /* Split moves of big integers into smaller pieces. */
3038 if (splittable_const_int_operand (src, mode))
3040 mips_move_integer (dest, dest, INTVAL (src));
3044 /* Split moves of symbolic constants into high/low pairs. */
3045 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3047 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3051 /* Generate the appropriate access sequences for TLS symbols. */
3052 if (mips_tls_symbol_p (src))
3054 mips_emit_move (dest, mips_legitimize_tls_address (src));
3058 /* If we have (const (plus symbol offset)), and that expression cannot
3059 be forced into memory, load the symbol first and add in the offset.
3060 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3061 forced into memory, as it usually produces better code. */
3062 split_const (src, &base, &offset);
3063 if (offset != const0_rtx
3064 && (targetm.cannot_force_const_mem (src)
3065 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3067 base = mips_force_temporary (dest, base);
3068 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3072 src = force_const_mem (mode, src);
3074 /* When using explicit relocs, constant pool references are sometimes
3075 not legitimate addresses. */
3076 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3077 mips_emit_move (dest, src);
3080 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3081 sequence that is valid. */
3084 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3086 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3088 mips_emit_move (dest, force_reg (mode, src));
3092 /* We need to deal with constants that would be legitimate
3093 immediate_operands but aren't legitimate move_operands. */
3094 if (CONSTANT_P (src) && !move_operand (src, mode))
3096 mips_legitimize_const_move (mode, dest, src);
3097 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3103 /* Return true if value X in context CONTEXT is a small-data address
3104 that can be rewritten as a LO_SUM. */
3107 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3109 enum mips_symbol_type symbol_type;
3111 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3112 && !mips_split_p[SYMBOL_GP_RELATIVE]
3113 && mips_symbolic_constant_p (x, context, &symbol_type)
3114 && symbol_type == SYMBOL_GP_RELATIVE);
3117 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3118 containing MEM, or null if none. */
3121 mips_small_data_pattern_1 (rtx *loc, void *data)
3123 enum mips_symbol_context context;
3125 if (GET_CODE (*loc) == LO_SUM)
3130 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3135 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3136 return mips_rewrite_small_data_p (*loc, context);
3139 /* Return true if OP refers to small data symbols directly, not through
3143 mips_small_data_pattern_p (rtx op)
3145 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3148 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3149 DATA is the containing MEM, or null if none. */
3152 mips_rewrite_small_data_1 (rtx *loc, void *data)
3154 enum mips_symbol_context context;
3158 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3162 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3163 if (mips_rewrite_small_data_p (*loc, context))
3164 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3166 if (GET_CODE (*loc) == LO_SUM)
3172 /* Rewrite instruction pattern PATTERN so that it refers to small data
3173 using explicit relocations. */
3176 mips_rewrite_small_data (rtx pattern)
3178 pattern = copy_insn (pattern);
3179 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3183 /* We need a lot of little routines to check the range of MIPS16 immediate
3187 m16_check_op (rtx op, int low, int high, int mask)
3189 return (CONST_INT_P (op)
3190 && IN_RANGE (INTVAL (op), low, high)
3191 && (INTVAL (op) & mask) == 0);
3195 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3197 return m16_check_op (op, 0x1, 0x8, 0);
3201 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3203 return m16_check_op (op, -0x8, 0x7, 0);
3207 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3209 return m16_check_op (op, -0x7, 0x8, 0);
3213 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3215 return m16_check_op (op, -0x10, 0xf, 0);
3219 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3221 return m16_check_op (op, -0xf, 0x10, 0);
3225 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3227 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3231 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3233 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3237 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3239 return m16_check_op (op, -0x80, 0x7f, 0);
3243 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3245 return m16_check_op (op, -0x7f, 0x80, 0);
3249 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3251 return m16_check_op (op, 0x0, 0xff, 0);
3255 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3257 return m16_check_op (op, -0xff, 0x0, 0);
3261 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3263 return m16_check_op (op, -0x1, 0xfe, 0);
3267 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3269 return m16_check_op (op, 0x0, 0xff << 2, 3);
3273 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3275 return m16_check_op (op, -0xff << 2, 0x0, 3);
3279 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3281 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3285 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3287 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3290 /* The cost of loading values from the constant pool. It should be
3291 larger than the cost of any constant we want to synthesize inline. */
3292 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3294 /* Return the cost of X when used as an operand to the MIPS16 instruction
3295 that implements CODE. Return -1 if there is no such instruction, or if
3296 X is not a valid immediate operand for it. */
3299 mips16_constant_cost (int code, HOST_WIDE_INT x)
3306 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3307 other shifts are extended. The shift patterns truncate the shift
3308 count to the right size, so there are no out-of-range values. */
3309 if (IN_RANGE (x, 1, 8))
3311 return COSTS_N_INSNS (1);
3314 if (IN_RANGE (x, -128, 127))
3316 if (SMALL_OPERAND (x))
3317 return COSTS_N_INSNS (1);
3321 /* Like LE, but reject the always-true case. */
3325 /* We add 1 to the immediate and use SLT. */
3328 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3331 if (IN_RANGE (x, 0, 255))
3333 if (SMALL_OPERAND_UNSIGNED (x))
3334 return COSTS_N_INSNS (1);
3339 /* Equality comparisons with 0 are cheap. */
3349 /* Return true if there is a non-MIPS16 instruction that implements CODE
3350 and if that instruction accepts X as an immediate operand. */
3353 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3360 /* All shift counts are truncated to a valid constant. */
3365 /* Likewise rotates, if the target supports rotates at all. */
3371 /* These instructions take 16-bit unsigned immediates. */
3372 return SMALL_OPERAND_UNSIGNED (x);
3377 /* These instructions take 16-bit signed immediates. */
3378 return SMALL_OPERAND (x);
3384 /* The "immediate" forms of these instructions are really
3385 implemented as comparisons with register 0. */
3390 /* Likewise, meaning that the only valid immediate operand is 1. */
3394 /* We add 1 to the immediate and use SLT. */
3395 return SMALL_OPERAND (x + 1);
3398 /* Likewise SLTU, but reject the always-true case. */
3399 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3403 /* The bit position and size are immediate operands. */
3404 return ISA_HAS_EXT_INS;
3407 /* By default assume that $0 can be used for 0. */
3412 /* Return the cost of binary operation X, given that the instruction
3413 sequence for a word-sized or smaller operation has cost SINGLE_COST
3414 and that the sequence of a double-word operation has cost DOUBLE_COST.
3415 If SPEED is true, optimize for speed otherwise optimize for size. */
3418 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3422 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3427 + rtx_cost (XEXP (x, 0), SET, speed)
3428 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3431 /* Return the cost of floating-point multiplications of mode MODE. */
3434 mips_fp_mult_cost (enum machine_mode mode)
3436 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3439 /* Return the cost of floating-point divisions of mode MODE. */
3442 mips_fp_div_cost (enum machine_mode mode)
3444 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3447 /* Return the cost of sign-extending OP to mode MODE, not including the
3448 cost of OP itself. */
3451 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3454 /* Extended loads are as cheap as unextended ones. */
3457 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3458 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3461 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3462 /* We can use SEB or SEH. */
3463 return COSTS_N_INSNS (1);
3465 /* We need to use a shift left and a shift right. */
3466 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3469 /* Return the cost of zero-extending OP to mode MODE, not including the
3470 cost of OP itself. */
3473 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3476 /* Extended loads are as cheap as unextended ones. */
3479 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3480 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3481 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3483 if (GENERATE_MIPS16E)
3484 /* We can use ZEB or ZEH. */
3485 return COSTS_N_INSNS (1);
3488 /* We need to load 0xff or 0xffff into a register and use AND. */
3489 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3491 /* We can use ANDI. */
3492 return COSTS_N_INSNS (1);
3495 /* Implement TARGET_RTX_COSTS. */
3498 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3500 enum machine_mode mode = GET_MODE (x);
3501 bool float_mode_p = FLOAT_MODE_P (mode);
3505 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3506 appear in the instruction stream, and the cost of a comparison is
3507 really the cost of the branch or scc condition. At the time of
3508 writing, GCC only uses an explicit outer COMPARE code when optabs
3509 is testing whether a constant is expensive enough to force into a
3510 register. We want optabs to pass such constants through the MIPS
3511 expanders instead, so make all constants very cheap here. */
3512 if (outer_code == COMPARE)
3514 gcc_assert (CONSTANT_P (x));
3522 /* Treat *clear_upper32-style ANDs as having zero cost in the
3523 second operand. The cost is entirely in the first operand.
3525 ??? This is needed because we would otherwise try to CSE
3526 the constant operand. Although that's the right thing for
3527 instructions that continue to be a register operation throughout
3528 compilation, it is disastrous for instructions that could
3529 later be converted into a memory operation. */
3531 && outer_code == AND
3532 && UINTVAL (x) == 0xffffffff)
3540 cost = mips16_constant_cost (outer_code, INTVAL (x));
3549 /* When not optimizing for size, we care more about the cost
3550 of hot code, and hot code is often in a loop. If a constant
3551 operand needs to be forced into a register, we will often be
3552 able to hoist the constant load out of the loop, so the load
3553 should not contribute to the cost. */
3554 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3566 if (force_to_mem_operand (x, VOIDmode))
3568 *total = COSTS_N_INSNS (1);
3571 cost = mips_const_insns (x);
3574 /* If the constant is likely to be stored in a GPR, SETs of
3575 single-insn constants are as cheap as register sets; we
3576 never want to CSE them.
3578 Don't reduce the cost of storing a floating-point zero in
3579 FPRs. If we have a zero in an FPR for other reasons, we
3580 can get better cfg-cleanup and delayed-branch results by
3581 using it consistently, rather than using $0 sometimes and
3582 an FPR at other times. Also, moves between floating-point
3583 registers are sometimes cheaper than (D)MTC1 $0. */
3585 && outer_code == SET
3586 && !(float_mode_p && TARGET_HARD_FLOAT))
3588 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3589 want to CSE the constant itself. It is usually better to
3590 have N copies of the last operation in the sequence and one
3591 shared copy of the other operations. (Note that this is
3592 not true for MIPS16 code, where the final operation in the
3593 sequence is often an extended instruction.)
3595 Also, if we have a CONST_INT, we don't know whether it is
3596 for a word or doubleword operation, so we cannot rely on
3597 the result of mips_build_integer. */
3598 else if (!TARGET_MIPS16
3599 && (outer_code == SET || mode == VOIDmode))
3601 *total = COSTS_N_INSNS (cost);
3604 /* The value will need to be fetched from the constant pool. */
3605 *total = CONSTANT_POOL_COST;
3609 /* If the address is legitimate, return the number of
3610 instructions it needs. */
3612 cost = mips_address_insns (addr, mode, true);
3615 *total = COSTS_N_INSNS (cost + 1);
3618 /* Check for a scaled indexed address. */
3619 if (mips_lwxs_address_p (addr))
3621 *total = COSTS_N_INSNS (2);
3624 /* Otherwise use the default handling. */
3628 *total = COSTS_N_INSNS (6);
3632 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3636 /* Check for a *clear_upper32 pattern and treat it like a zero
3637 extension. See the pattern's comment for details. */
3640 && CONST_INT_P (XEXP (x, 1))
3641 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3643 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3644 + rtx_cost (XEXP (x, 0), SET, speed));
3651 /* Double-word operations use two single-word operations. */
3652 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3661 if (CONSTANT_P (XEXP (x, 1)))
3662 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3665 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3671 *total = mips_cost->fp_add;
3673 *total = COSTS_N_INSNS (4);
3677 /* Low-part immediates need an extended MIPS16 instruction. */
3678 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3679 + rtx_cost (XEXP (x, 0), SET, speed));
3694 /* Branch comparisons have VOIDmode, so use the first operand's
3696 mode = GET_MODE (XEXP (x, 0));
3697 if (FLOAT_MODE_P (mode))
3699 *total = mips_cost->fp_add;
3702 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3708 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3709 && TARGET_FUSED_MADD
3710 && !HONOR_NANS (mode)
3711 && !HONOR_SIGNED_ZEROS (mode))
3713 /* See if we can use NMADD or NMSUB. See mips.md for the
3714 associated patterns. */
3715 rtx op0 = XEXP (x, 0);
3716 rtx op1 = XEXP (x, 1);
3717 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3719 *total = (mips_fp_mult_cost (mode)
3720 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3721 + rtx_cost (XEXP (op0, 1), SET, speed)
3722 + rtx_cost (op1, SET, speed));
3725 if (GET_CODE (op1) == MULT)
3727 *total = (mips_fp_mult_cost (mode)
3728 + rtx_cost (op0, SET, speed)
3729 + rtx_cost (XEXP (op1, 0), SET, speed)
3730 + rtx_cost (XEXP (op1, 1), SET, speed));
3739 /* If this is part of a MADD or MSUB, treat the PLUS as
3742 && TARGET_FUSED_MADD
3743 && GET_CODE (XEXP (x, 0)) == MULT)
3746 *total = mips_cost->fp_add;
3750 /* Double-word operations require three single-word operations and
3751 an SLTU. The MIPS16 version then needs to move the result of
3752 the SLTU from $24 to a MIPS16 register. */
3753 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3754 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3760 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3761 && TARGET_FUSED_MADD
3762 && !HONOR_NANS (mode)
3763 && HONOR_SIGNED_ZEROS (mode))
3765 /* See if we can use NMADD or NMSUB. See mips.md for the
3766 associated patterns. */
3767 rtx op = XEXP (x, 0);
3768 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3769 && GET_CODE (XEXP (op, 0)) == MULT)
3771 *total = (mips_fp_mult_cost (mode)
3772 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3773 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3774 + rtx_cost (XEXP (op, 1), SET, speed));
3780 *total = mips_cost->fp_add;
3782 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3787 *total = mips_fp_mult_cost (mode);
3788 else if (mode == DImode && !TARGET_64BIT)
3789 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3790 where the mulsidi3 always includes an MFHI and an MFLO. */
3792 ? mips_cost->int_mult_si * 3 + 6
3793 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3795 *total = (ISA_HAS_MUL3 ? 1 : 2);
3796 else if (mode == DImode)
3797 *total = mips_cost->int_mult_di;
3799 *total = mips_cost->int_mult_si;
3803 /* Check for a reciprocal. */
3806 && flag_unsafe_math_optimizations
3807 && XEXP (x, 0) == CONST1_RTX (mode))
3809 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3810 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3811 division as being free. */
3812 *total = rtx_cost (XEXP (x, 1), SET, speed);
3814 *total = (mips_fp_div_cost (mode)
3815 + rtx_cost (XEXP (x, 1), SET, speed));
3824 *total = mips_fp_div_cost (mode);
3833 /* It is our responsibility to make division by a power of 2
3834 as cheap as 2 register additions if we want the division
3835 expanders to be used for such operations; see the setting
3836 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3837 should always produce shorter code than using
3838 expand_sdiv2_pow2. */
3840 && CONST_INT_P (XEXP (x, 1))
3841 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3843 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3846 *total = COSTS_N_INSNS (mips_idiv_insns ());
3848 else if (mode == DImode)
3849 *total = mips_cost->int_div_di;
3851 *total = mips_cost->int_div_si;
3855 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3859 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3863 case UNSIGNED_FLOAT:
3866 case FLOAT_TRUNCATE:
3867 *total = mips_cost->fp_add;
3875 /* Implement TARGET_ADDRESS_COST. */
3878 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3880 return mips_address_insns (addr, SImode, false);
3883 /* Information about a single instruction in a multi-instruction
3885 struct mips_multi_member {
3886 /* True if this is a label, false if it is code. */
3889 /* The output_asm_insn format of the instruction. */
3892 /* The operands to the instruction. */
3893 rtx operands[MAX_RECOG_OPERANDS];
3895 typedef struct mips_multi_member mips_multi_member;
3897 /* Vector definitions for the above. */
3898 DEF_VEC_O(mips_multi_member);
3899 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3901 /* The instructions that make up the current multi-insn sequence. */
3902 static VEC (mips_multi_member, heap) *mips_multi_members;
3904 /* How many instructions (as opposed to labels) are in the current
3905 multi-insn sequence. */
3906 static unsigned int mips_multi_num_insns;
3908 /* Start a new multi-insn sequence. */
3911 mips_multi_start (void)
3913 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3914 mips_multi_num_insns = 0;
3917 /* Add a new, uninitialized member to the current multi-insn sequence. */
3919 static struct mips_multi_member *
3920 mips_multi_add (void)
3922 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3925 /* Add a normal insn with the given asm format to the current multi-insn
3926 sequence. The other arguments are a null-terminated list of operands. */
3929 mips_multi_add_insn (const char *format, ...)
3931 struct mips_multi_member *member;
3936 member = mips_multi_add ();
3937 member->is_label_p = false;
3938 member->format = format;
3939 va_start (ap, format);
3941 while ((op = va_arg (ap, rtx)))
3942 member->operands[i++] = op;
3944 mips_multi_num_insns++;
3947 /* Add the given label definition to the current multi-insn sequence.
3948 The definition should include the colon. */
3951 mips_multi_add_label (const char *label)
3953 struct mips_multi_member *member;
3955 member = mips_multi_add ();
3956 member->is_label_p = true;
3957 member->format = label;
3960 /* Return the index of the last member of the current multi-insn sequence. */
3963 mips_multi_last_index (void)
3965 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3968 /* Add a copy of an existing instruction to the current multi-insn
3969 sequence. I is the index of the instruction that should be copied. */
3972 mips_multi_copy_insn (unsigned int i)
3974 struct mips_multi_member *member;
3976 member = mips_multi_add ();
3977 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
3979 gcc_assert (!member->is_label_p);
3982 /* Change the operand of an existing instruction in the current
3983 multi-insn sequence. I is the index of the instruction,
3984 OP is the index of the operand, and X is the new value. */
3987 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
3989 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
3992 /* Write out the asm code for the current multi-insn sequence. */
3995 mips_multi_write (void)
3997 struct mips_multi_member *member;
4001 VEC_iterate (mips_multi_member, mips_multi_members, i, member);
4003 if (member->is_label_p)
4004 fprintf (asm_out_file, "%s\n", member->format);
4006 output_asm_insn (member->format, member->operands);
4009 /* Return one word of double-word value OP, taking into account the fixed
4010 endianness of certain registers. HIGH_P is true to select the high part,
4011 false to select the low part. */
4014 mips_subword (rtx op, bool high_p)
4016 unsigned int byte, offset;
4017 enum machine_mode mode;
4019 mode = GET_MODE (op);
4020 if (mode == VOIDmode)
4021 mode = TARGET_64BIT ? TImode : DImode;
4023 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4024 byte = UNITS_PER_WORD;
4028 if (FP_REG_RTX_P (op))
4030 /* Paired FPRs are always ordered little-endian. */
4031 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4032 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4036 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4038 return simplify_gen_subreg (word_mode, op, mode, byte);
4041 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4044 mips_split_64bit_move_p (rtx dest, rtx src)
4049 /* FPR-to-FPR moves can be done in a single instruction, if they're
4051 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4054 /* Check for floating-point loads and stores. */
4055 if (ISA_HAS_LDC1_SDC1)
4057 if (FP_REG_RTX_P (dest) && MEM_P (src))
4059 if (FP_REG_RTX_P (src) && MEM_P (dest))
4065 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4066 this function handles 64-bit moves for which mips_split_64bit_move_p
4067 holds. For 64-bit targets, this function handles 128-bit moves. */
4070 mips_split_doubleword_move (rtx dest, rtx src)
4074 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4076 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4077 emit_insn (gen_move_doubleword_fprdi (dest, src));
4078 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4079 emit_insn (gen_move_doubleword_fprdf (dest, src));
4080 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4081 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4082 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4083 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4084 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4085 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4086 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4087 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4088 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4089 emit_insn (gen_move_doubleword_fprtf (dest, src));
4093 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4095 low_dest = mips_subword (dest, false);
4096 mips_emit_move (low_dest, mips_subword (src, false));
4098 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4100 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4102 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4104 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4106 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4108 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4112 /* The operation can be split into two normal moves. Decide in
4113 which order to do them. */
4114 low_dest = mips_subword (dest, false);
4115 if (REG_P (low_dest)
4116 && reg_overlap_mentioned_p (low_dest, src))
4118 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4119 mips_emit_move (low_dest, mips_subword (src, false));
4123 mips_emit_move (low_dest, mips_subword (src, false));
4124 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4129 /* Return the appropriate instructions to move SRC into DEST. Assume
4130 that SRC is operand 1 and DEST is operand 0. */
4133 mips_output_move (rtx dest, rtx src)
4135 enum rtx_code dest_code, src_code;
4136 enum machine_mode mode;
4137 enum mips_symbol_type symbol_type;
4140 dest_code = GET_CODE (dest);
4141 src_code = GET_CODE (src);
4142 mode = GET_MODE (dest);
4143 dbl_p = (GET_MODE_SIZE (mode) == 8);
4145 if (dbl_p && mips_split_64bit_move_p (dest, src))
4148 if ((src_code == REG && GP_REG_P (REGNO (src)))
4149 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4151 if (dest_code == REG)
4153 if (GP_REG_P (REGNO (dest)))
4154 return "move\t%0,%z1";
4156 /* Moves to HI are handled by special .md insns. */
4157 if (REGNO (dest) == LO_REGNUM)
4160 if (DSP_ACC_REG_P (REGNO (dest)))
4162 static char retval[] = "mt__\t%z1,%q0";
4164 retval[2] = reg_names[REGNO (dest)][4];
4165 retval[3] = reg_names[REGNO (dest)][5];
4169 if (FP_REG_P (REGNO (dest)))
4170 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4172 if (ALL_COP_REG_P (REGNO (dest)))
4174 static char retval[] = "dmtc_\t%z1,%0";
4176 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4177 return dbl_p ? retval : retval + 1;
4180 if (dest_code == MEM)
4181 switch (GET_MODE_SIZE (mode))
4183 case 1: return "sb\t%z1,%0";
4184 case 2: return "sh\t%z1,%0";
4185 case 4: return "sw\t%z1,%0";
4186 case 8: return "sd\t%z1,%0";
4189 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4191 if (src_code == REG)
4193 /* Moves from HI are handled by special .md insns. */
4194 if (REGNO (src) == LO_REGNUM)
4196 /* When generating VR4120 or VR4130 code, we use MACC and
4197 DMACC instead of MFLO. This avoids both the normal
4198 MIPS III HI/LO hazards and the errata related to
4201 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4205 if (DSP_ACC_REG_P (REGNO (src)))
4207 static char retval[] = "mf__\t%0,%q1";
4209 retval[2] = reg_names[REGNO (src)][4];
4210 retval[3] = reg_names[REGNO (src)][5];
4214 if (FP_REG_P (REGNO (src)))
4215 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4217 if (ALL_COP_REG_P (REGNO (src)))
4219 static char retval[] = "dmfc_\t%0,%1";
4221 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4222 return dbl_p ? retval : retval + 1;
4225 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4226 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4229 if (src_code == MEM)
4230 switch (GET_MODE_SIZE (mode))
4232 case 1: return "lbu\t%0,%1";
4233 case 2: return "lhu\t%0,%1";
4234 case 4: return "lw\t%0,%1";
4235 case 8: return "ld\t%0,%1";
4238 if (src_code == CONST_INT)
4240 /* Don't use the X format for the operand itself, because that
4241 will give out-of-range numbers for 64-bit hosts and 32-bit
4244 return "li\t%0,%1\t\t\t# %X1";
4246 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4249 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4253 if (src_code == HIGH)
4254 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4256 if (CONST_GP_P (src))
4257 return "move\t%0,%1";
4259 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4260 && mips_lo_relocs[symbol_type] != 0)
4262 /* A signed 16-bit constant formed by applying a relocation
4263 operator to a symbolic address. */
4264 gcc_assert (!mips_split_p[symbol_type]);
4265 return "li\t%0,%R1";
4268 if (symbolic_operand (src, VOIDmode))
4270 gcc_assert (TARGET_MIPS16
4271 ? TARGET_MIPS16_TEXT_LOADS
4272 : !TARGET_EXPLICIT_RELOCS);
4273 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4276 if (src_code == REG && FP_REG_P (REGNO (src)))
4278 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4280 if (GET_MODE (dest) == V2SFmode)
4281 return "mov.ps\t%0,%1";
4283 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4286 if (dest_code == MEM)
4287 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4289 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4291 if (src_code == MEM)
4292 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4294 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4296 static char retval[] = "l_c_\t%0,%1";
4298 retval[1] = (dbl_p ? 'd' : 'w');
4299 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4302 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4304 static char retval[] = "s_c_\t%1,%0";
4306 retval[1] = (dbl_p ? 'd' : 'w');
4307 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4313 /* Return true if CMP1 is a suitable second operand for integer ordering
4314 test CODE. See also the *sCC patterns in mips.md. */
4317 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4323 return reg_or_0_operand (cmp1, VOIDmode);
4327 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4331 return arith_operand (cmp1, VOIDmode);
4334 return sle_operand (cmp1, VOIDmode);
4337 return sleu_operand (cmp1, VOIDmode);
4344 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4345 integer ordering test *CODE, or if an equivalent combination can
4346 be formed by adjusting *CODE and *CMP1. When returning true, update
4347 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4351 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4352 enum machine_mode mode)
4354 HOST_WIDE_INT plus_one;
4356 if (mips_int_order_operand_ok_p (*code, *cmp1))
4359 if (CONST_INT_P (*cmp1))
4363 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4364 if (INTVAL (*cmp1) < plus_one)
4367 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4373 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4377 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4388 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4389 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4390 is nonnull, it's OK to set TARGET to the inverse of the result and
4391 flip *INVERT_PTR instead. */
4394 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4395 rtx target, rtx cmp0, rtx cmp1)
4397 enum machine_mode mode;
4399 /* First see if there is a MIPS instruction that can do this operation.
4400 If not, try doing the same for the inverse operation. If that also
4401 fails, force CMP1 into a register and try again. */
4402 mode = GET_MODE (cmp0);
4403 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4404 mips_emit_binary (code, target, cmp0, cmp1);
4407 enum rtx_code inv_code = reverse_condition (code);
4408 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4410 cmp1 = force_reg (mode, cmp1);
4411 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4413 else if (invert_ptr == 0)
4417 inv_target = mips_force_binary (GET_MODE (target),
4418 inv_code, cmp0, cmp1);
4419 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4423 *invert_ptr = !*invert_ptr;
4424 mips_emit_binary (inv_code, target, cmp0, cmp1);
4429 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4430 The register will have the same mode as CMP0. */
4433 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4435 if (cmp1 == const0_rtx)
4438 if (uns_arith_operand (cmp1, VOIDmode))
4439 return expand_binop (GET_MODE (cmp0), xor_optab,
4440 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4442 return expand_binop (GET_MODE (cmp0), sub_optab,
4443 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4446 /* Convert *CODE into a code that can be used in a floating-point
4447 scc instruction (C.cond.fmt). Return true if the values of
4448 the condition code registers will be inverted, with 0 indicating
4449 that the condition holds. */
4452 mips_reversed_fp_cond (enum rtx_code *code)
4459 *code = reverse_condition_maybe_unordered (*code);
4467 /* Convert a comparison into something that can be used in a branch or
4468 conditional move. On entry, *OP0 and *OP1 are the values being
4469 compared and *CODE is the code used to compare them.
4471 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4472 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4473 otherwise any standard branch condition can be used. The standard branch
4476 - EQ or NE between two registers.
4477 - any comparison between a register and zero. */
4480 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4485 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4487 if (!need_eq_ne_p && *op1 == const0_rtx)
4489 else if (*code == EQ || *code == NE)
4493 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4497 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4501 /* The comparison needs a separate scc instruction. Store the
4502 result of the scc in *OP0 and compare it against zero. */
4503 bool invert = false;
4504 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4505 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4506 *code = (invert ? EQ : NE);
4510 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4512 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4513 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4519 enum rtx_code cmp_code;
4521 /* Floating-point tests use a separate C.cond.fmt comparison to
4522 set a condition code register. The branch or conditional move
4523 will then compare that register against zero.
4525 Set CMP_CODE to the code of the comparison instruction and
4526 *CODE to the code that the branch or move should use. */
4528 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4530 ? gen_reg_rtx (CCmode)
4531 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4533 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4537 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4538 and OPERAND[3]. Store the result in OPERANDS[0].
4540 On 64-bit targets, the mode of the comparison and target will always be
4541 SImode, thus possibly narrower than that of the comparison's operands. */
4544 mips_expand_scc (rtx operands[])
4546 rtx target = operands[0];
4547 enum rtx_code code = GET_CODE (operands[1]);
4548 rtx op0 = operands[2];
4549 rtx op1 = operands[3];
4551 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4553 if (code == EQ || code == NE)
4556 && reg_imm10_operand (op1, GET_MODE (op1)))
4557 mips_emit_binary (code, target, op0, op1);
4560 rtx zie = mips_zero_if_equal (op0, op1);
4561 mips_emit_binary (code, target, zie, const0_rtx);
4565 mips_emit_int_order_test (code, 0, target, op0, op1);
4568 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4569 CODE and jump to OPERANDS[3] if the condition holds. */
4572 mips_expand_conditional_branch (rtx *operands)
4574 enum rtx_code code = GET_CODE (operands[0]);
4575 rtx op0 = operands[1];
4576 rtx op1 = operands[2];
4579 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4580 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4581 emit_jump_insn (gen_condjump (condition, operands[3]));
4586 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4587 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4590 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4591 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4596 reversed_p = mips_reversed_fp_cond (&cond);
4597 cmp_result = gen_reg_rtx (CCV2mode);
4598 emit_insn (gen_scc_ps (cmp_result,
4599 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4601 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4604 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4608 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4609 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4612 mips_expand_conditional_move (rtx *operands)
4615 enum rtx_code code = GET_CODE (operands[1]);
4616 rtx op0 = XEXP (operands[1], 0);
4617 rtx op1 = XEXP (operands[1], 1);
4619 mips_emit_compare (&code, &op0, &op1, true);
4620 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4621 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4622 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4623 operands[2], operands[3])));
4626 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4629 mips_expand_conditional_trap (rtx comparison)
4632 enum machine_mode mode;
4635 /* MIPS conditional trap instructions don't have GT or LE flavors,
4636 so we must swap the operands and convert to LT and GE respectively. */
4637 code = GET_CODE (comparison);
4644 code = swap_condition (code);
4645 op0 = XEXP (comparison, 1);
4646 op1 = XEXP (comparison, 0);
4650 op0 = XEXP (comparison, 0);
4651 op1 = XEXP (comparison, 1);
4655 mode = GET_MODE (XEXP (comparison, 0));
4656 op0 = force_reg (mode, op0);
4657 if (!arith_operand (op1, mode))
4658 op1 = force_reg (mode, op1);
4660 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4661 gen_rtx_fmt_ee (code, mode, op0, op1),
4665 /* Initialize *CUM for a call to a function of type FNTYPE. */
4668 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4670 memset (cum, 0, sizeof (*cum));
4671 cum->prototype = (fntype && prototype_p (fntype));
4672 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4675 /* Fill INFO with information about a single argument. CUM is the
4676 cumulative state for earlier arguments. MODE is the mode of this
4677 argument and TYPE is its type (if known). NAMED is true if this
4678 is a named (fixed) argument rather than a variable one. */
4681 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4682 enum machine_mode mode, tree type, int named)
4684 bool doubleword_aligned_p;
4685 unsigned int num_bytes, num_words, max_regs;
4687 /* Work out the size of the argument. */
4688 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4689 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4691 /* Decide whether it should go in a floating-point register, assuming
4692 one is free. Later code checks for availability.
4694 The checks against UNITS_PER_FPVALUE handle the soft-float and
4695 single-float cases. */
4699 /* The EABI conventions have traditionally been defined in terms
4700 of TYPE_MODE, regardless of the actual type. */
4701 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4702 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4703 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4708 /* Only leading floating-point scalars are passed in
4709 floating-point registers. We also handle vector floats the same
4710 say, which is OK because they are not covered by the standard ABI. */
4711 info->fpr_p = (!cum->gp_reg_found
4712 && cum->arg_number < 2
4714 || SCALAR_FLOAT_TYPE_P (type)
4715 || VECTOR_FLOAT_TYPE_P (type))
4716 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4717 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4718 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4723 /* Scalar, complex and vector floating-point types are passed in
4724 floating-point registers, as long as this is a named rather
4725 than a variable argument. */
4726 info->fpr_p = (named
4727 && (type == 0 || FLOAT_TYPE_P (type))
4728 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4729 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4730 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4731 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4733 /* ??? According to the ABI documentation, the real and imaginary
4734 parts of complex floats should be passed in individual registers.
4735 The real and imaginary parts of stack arguments are supposed
4736 to be contiguous and there should be an extra word of padding
4739 This has two problems. First, it makes it impossible to use a
4740 single "void *" va_list type, since register and stack arguments
4741 are passed differently. (At the time of writing, MIPSpro cannot
4742 handle complex float varargs correctly.) Second, it's unclear
4743 what should happen when there is only one register free.
4745 For now, we assume that named complex floats should go into FPRs
4746 if there are two FPRs free, otherwise they should be passed in the
4747 same way as a struct containing two floats. */
4749 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4750 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4752 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4753 info->fpr_p = false;
4763 /* See whether the argument has doubleword alignment. */
4764 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4766 /* Set REG_OFFSET to the register count we're interested in.
4767 The EABI allocates the floating-point registers separately,
4768 but the other ABIs allocate them like integer registers. */
4769 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4773 /* Advance to an even register if the argument is doubleword-aligned. */
4774 if (doubleword_aligned_p)
4775 info->reg_offset += info->reg_offset & 1;
4777 /* Work out the offset of a stack argument. */
4778 info->stack_offset = cum->stack_words;
4779 if (doubleword_aligned_p)
4780 info->stack_offset += info->stack_offset & 1;
4782 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4784 /* Partition the argument between registers and stack. */
4785 info->reg_words = MIN (num_words, max_regs);
4786 info->stack_words = num_words - info->reg_words;
4789 /* INFO describes a register argument that has the normal format for the
4790 argument's mode. Return the register it uses, assuming that FPRs are
4791 available if HARD_FLOAT_P. */
4794 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4796 if (!info->fpr_p || !hard_float_p)
4797 return GP_ARG_FIRST + info->reg_offset;
4798 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4799 /* In o32, the second argument is always passed in $f14
4800 for TARGET_DOUBLE_FLOAT, regardless of whether the
4801 first argument was a word or doubleword. */
4802 return FP_ARG_FIRST + 2;
4804 return FP_ARG_FIRST + info->reg_offset;
4807 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4810 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4812 return !TARGET_OLDABI;
4815 /* Implement FUNCTION_ARG. */
4818 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4819 tree type, int named)
4821 struct mips_arg_info info;
4823 /* We will be called with a mode of VOIDmode after the last argument
4824 has been seen. Whatever we return will be passed to the call expander.
4825 If we need a MIPS16 fp_code, return a REG with the code stored as
4827 if (mode == VOIDmode)
4829 if (TARGET_MIPS16 && cum->fp_code != 0)
4830 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4835 mips_get_arg_info (&info, cum, mode, type, named);
4837 /* Return straight away if the whole argument is passed on the stack. */
4838 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4841 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4842 contains a double in its entirety, then that 64-bit chunk is passed
4843 in a floating-point register. */
4845 && TARGET_HARD_FLOAT
4848 && TREE_CODE (type) == RECORD_TYPE
4849 && TYPE_SIZE_UNIT (type)
4850 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4854 /* First check to see if there is any such field. */
4855 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4856 if (TREE_CODE (field) == FIELD_DECL
4857 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4858 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4859 && host_integerp (bit_position (field), 0)
4860 && int_bit_position (field) % BITS_PER_WORD == 0)
4865 /* Now handle the special case by returning a PARALLEL
4866 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4867 chunks are passed in registers. */
4869 HOST_WIDE_INT bitpos;
4872 /* assign_parms checks the mode of ENTRY_PARM, so we must
4873 use the actual mode here. */
4874 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4877 field = TYPE_FIELDS (type);
4878 for (i = 0; i < info.reg_words; i++)
4882 for (; field; field = TREE_CHAIN (field))
4883 if (TREE_CODE (field) == FIELD_DECL
4884 && int_bit_position (field) >= bitpos)
4888 && int_bit_position (field) == bitpos
4889 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4890 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4891 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4893 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4896 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4897 GEN_INT (bitpos / BITS_PER_UNIT));
4899 bitpos += BITS_PER_WORD;
4905 /* Handle the n32/n64 conventions for passing complex floating-point
4906 arguments in FPR pairs. The real part goes in the lower register
4907 and the imaginary part goes in the upper register. */
4910 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4913 enum machine_mode inner;
4916 inner = GET_MODE_INNER (mode);
4917 regno = FP_ARG_FIRST + info.reg_offset;
4918 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4920 /* Real part in registers, imaginary part on stack. */
4921 gcc_assert (info.stack_words == info.reg_words);
4922 return gen_rtx_REG (inner, regno);
4926 gcc_assert (info.stack_words == 0);
4927 real = gen_rtx_EXPR_LIST (VOIDmode,
4928 gen_rtx_REG (inner, regno),
4930 imag = gen_rtx_EXPR_LIST (VOIDmode,
4932 regno + info.reg_words / 2),
4933 GEN_INT (GET_MODE_SIZE (inner)));
4934 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4938 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4941 /* Implement FUNCTION_ARG_ADVANCE. */
4944 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4945 tree type, int named)
4947 struct mips_arg_info info;
4949 mips_get_arg_info (&info, cum, mode, type, named);
4952 cum->gp_reg_found = true;
4954 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4955 an explanation of what this code does. It assumes that we're using
4956 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4958 if (cum->arg_number < 2 && info.fpr_p)
4959 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4961 /* Advance the register count. This has the effect of setting
4962 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4963 argument required us to skip the final GPR and pass the whole
4964 argument on the stack. */
4965 if (mips_abi != ABI_EABI || !info.fpr_p)
4966 cum->num_gprs = info.reg_offset + info.reg_words;
4967 else if (info.reg_words > 0)
4968 cum->num_fprs += MAX_FPRS_PER_FMT;
4970 /* Advance the stack word count. */
4971 if (info.stack_words > 0)
4972 cum->stack_words = info.stack_offset + info.stack_words;
4977 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4980 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4981 enum machine_mode mode, tree type, bool named)
4983 struct mips_arg_info info;
4985 mips_get_arg_info (&info, cum, mode, type, named);
4986 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4989 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4990 PARM_BOUNDARY bits of alignment, but will be given anything up
4991 to STACK_BOUNDARY bits if the type requires it. */
4994 mips_function_arg_boundary (enum machine_mode mode, tree type)
4996 unsigned int alignment;
4998 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4999 if (alignment < PARM_BOUNDARY)
5000 alignment = PARM_BOUNDARY;
5001 if (alignment > STACK_BOUNDARY)
5002 alignment = STACK_BOUNDARY;
5006 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5007 upward rather than downward. In other words, return true if the
5008 first byte of the stack slot has useful data, false if the last
5012 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5014 /* On little-endian targets, the first byte of every stack argument
5015 is passed in the first byte of the stack slot. */
5016 if (!BYTES_BIG_ENDIAN)
5019 /* Otherwise, integral types are padded downward: the last byte of a
5020 stack argument is passed in the last byte of the stack slot. */
5022 ? (INTEGRAL_TYPE_P (type)
5023 || POINTER_TYPE_P (type)
5024 || FIXED_POINT_TYPE_P (type))
5025 : (SCALAR_INT_MODE_P (mode)
5026 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5029 /* Big-endian o64 pads floating-point arguments downward. */
5030 if (mips_abi == ABI_O64)
5031 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5034 /* Other types are padded upward for o32, o64, n32 and n64. */
5035 if (mips_abi != ABI_EABI)
5038 /* Arguments smaller than a stack slot are padded downward. */
5039 if (mode != BLKmode)
5040 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5042 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5045 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5046 if the least significant byte of the register has useful data. Return
5047 the opposite if the most significant byte does. */
5050 mips_pad_reg_upward (enum machine_mode mode, tree type)
5052 /* No shifting is required for floating-point arguments. */
5053 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5054 return !BYTES_BIG_ENDIAN;
5056 /* Otherwise, apply the same padding to register arguments as we do
5057 to stack arguments. */
5058 return mips_pad_arg_upward (mode, type);
5061 /* Return nonzero when an argument must be passed by reference. */
5064 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5065 enum machine_mode mode, const_tree type,
5066 bool named ATTRIBUTE_UNUSED)
5068 if (mips_abi == ABI_EABI)
5072 /* ??? How should SCmode be handled? */
5073 if (mode == DImode || mode == DFmode
5074 || mode == DQmode || mode == UDQmode
5075 || mode == DAmode || mode == UDAmode)
5078 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5079 return size == -1 || size > UNITS_PER_WORD;
5083 /* If we have a variable-sized parameter, we have no choice. */
5084 return targetm.calls.must_pass_in_stack (mode, type);
5088 /* Implement TARGET_CALLEE_COPIES. */
5091 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5092 enum machine_mode mode ATTRIBUTE_UNUSED,
5093 const_tree type ATTRIBUTE_UNUSED, bool named)
5095 return mips_abi == ABI_EABI && named;
5098 /* See whether VALTYPE is a record whose fields should be returned in
5099 floating-point registers. If so, return the number of fields and
5100 list them in FIELDS (which should have two elements). Return 0
5103 For n32 & n64, a structure with one or two fields is returned in
5104 floating-point registers as long as every field has a floating-point
5108 mips_fpr_return_fields (const_tree valtype, tree *fields)
5116 if (TREE_CODE (valtype) != RECORD_TYPE)
5120 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
5122 if (TREE_CODE (field) != FIELD_DECL)
5125 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5131 fields[i++] = field;
5136 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5137 a value in the most significant part of $2/$3 if:
5139 - the target is big-endian;
5141 - the value has a structure or union type (we generalize this to
5142 cover aggregates from other languages too); and
5144 - the structure is not returned in floating-point registers. */
5147 mips_return_in_msb (const_tree valtype)
5151 return (TARGET_NEWABI
5152 && TARGET_BIG_ENDIAN
5153 && AGGREGATE_TYPE_P (valtype)
5154 && mips_fpr_return_fields (valtype, fields) == 0);
5157 /* Return true if the function return value MODE will get returned in a
5158 floating-point register. */
5161 mips_return_mode_in_fpr_p (enum machine_mode mode)
5163 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5164 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5165 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5166 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5169 /* Return the representation of an FPR return register when the
5170 value being returned in FP_RETURN has mode VALUE_MODE and the
5171 return type itself has mode TYPE_MODE. On NewABI targets,
5172 the two modes may be different for structures like:
5174 struct __attribute__((packed)) foo { float f; }
5176 where we return the SFmode value of "f" in FP_RETURN, but where
5177 the structure itself has mode BLKmode. */
5180 mips_return_fpr_single (enum machine_mode type_mode,
5181 enum machine_mode value_mode)
5185 x = gen_rtx_REG (value_mode, FP_RETURN);
5186 if (type_mode != value_mode)
5188 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5189 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5194 /* Return a composite value in a pair of floating-point registers.
5195 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5196 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5199 For n32 & n64, $f0 always holds the first value and $f2 the second.
5200 Otherwise the values are packed together as closely as possible. */
5203 mips_return_fpr_pair (enum machine_mode mode,
5204 enum machine_mode mode1, HOST_WIDE_INT offset1,
5205 enum machine_mode mode2, HOST_WIDE_INT offset2)
5209 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5210 return gen_rtx_PARALLEL
5213 gen_rtx_EXPR_LIST (VOIDmode,
5214 gen_rtx_REG (mode1, FP_RETURN),
5216 gen_rtx_EXPR_LIST (VOIDmode,
5217 gen_rtx_REG (mode2, FP_RETURN + inc),
5218 GEN_INT (offset2))));
5222 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5223 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5224 VALTYPE is null and MODE is the mode of the return value. */
5227 mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
5234 mode = TYPE_MODE (valtype);
5235 unsigned_p = TYPE_UNSIGNED (valtype);
5237 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5238 return values, promote the mode here too. */
5239 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5241 /* Handle structures whose fields are returned in $f0/$f2. */
5242 switch (mips_fpr_return_fields (valtype, fields))
5245 return mips_return_fpr_single (mode,
5246 TYPE_MODE (TREE_TYPE (fields[0])));
5249 return mips_return_fpr_pair (mode,
5250 TYPE_MODE (TREE_TYPE (fields[0])),
5251 int_byte_position (fields[0]),
5252 TYPE_MODE (TREE_TYPE (fields[1])),
5253 int_byte_position (fields[1]));
5256 /* If a value is passed in the most significant part of a register, see
5257 whether we have to round the mode up to a whole number of words. */
5258 if (mips_return_in_msb (valtype))
5260 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5261 if (size % UNITS_PER_WORD != 0)
5263 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5264 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5268 /* For EABI, the class of return register depends entirely on MODE.
5269 For example, "struct { some_type x; }" and "union { some_type x; }"
5270 are returned in the same way as a bare "some_type" would be.
5271 Other ABIs only use FPRs for scalar, complex or vector types. */
5272 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5273 return gen_rtx_REG (mode, GP_RETURN);
5278 /* Handle long doubles for n32 & n64. */
5280 return mips_return_fpr_pair (mode,
5282 DImode, GET_MODE_SIZE (mode) / 2);
5284 if (mips_return_mode_in_fpr_p (mode))
5286 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5287 return mips_return_fpr_pair (mode,
5288 GET_MODE_INNER (mode), 0,
5289 GET_MODE_INNER (mode),
5290 GET_MODE_SIZE (mode) / 2);
5292 return gen_rtx_REG (mode, FP_RETURN);
5296 return gen_rtx_REG (mode, GP_RETURN);
5299 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5300 all BLKmode objects are returned in memory. Under the n32, n64
5301 and embedded ABIs, small structures are returned in a register.
5302 Objects with varying size must still be returned in memory, of
5306 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5308 return (TARGET_OLDABI
5309 ? TYPE_MODE (type) == BLKmode
5310 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5313 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5316 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5317 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5320 CUMULATIVE_ARGS local_cum;
5321 int gp_saved, fp_saved;
5323 /* The caller has advanced CUM up to, but not beyond, the last named
5324 argument. Advance a local copy of CUM past the last "real" named
5325 argument, to find out how many registers are left over. */
5327 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5329 /* Found out how many registers we need to save. */
5330 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5331 fp_saved = (EABI_FLOAT_VARARGS_P
5332 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5341 ptr = plus_constant (virtual_incoming_args_rtx,
5342 REG_PARM_STACK_SPACE (cfun->decl)
5343 - gp_saved * UNITS_PER_WORD);
5344 mem = gen_frame_mem (BLKmode, ptr);
5345 set_mem_alias_set (mem, get_varargs_alias_set ());
5347 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5352 /* We can't use move_block_from_reg, because it will use
5354 enum machine_mode mode;
5357 /* Set OFF to the offset from virtual_incoming_args_rtx of
5358 the first float register. The FP save area lies below
5359 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5360 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5361 off -= fp_saved * UNITS_PER_FPREG;
5363 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5365 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5366 i += MAX_FPRS_PER_FMT)
5370 ptr = plus_constant (virtual_incoming_args_rtx, off);
5371 mem = gen_frame_mem (mode, ptr);
5372 set_mem_alias_set (mem, get_varargs_alias_set ());
5373 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5374 off += UNITS_PER_HWFPVALUE;
5378 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5379 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5380 + fp_saved * UNITS_PER_FPREG);
5383 /* Implement TARGET_BUILTIN_VA_LIST. */
5386 mips_build_builtin_va_list (void)
5388 if (EABI_FLOAT_VARARGS_P)
5390 /* We keep 3 pointers, and two offsets.
5392 Two pointers are to the overflow area, which starts at the CFA.
5393 One of these is constant, for addressing into the GPR save area
5394 below it. The other is advanced up the stack through the
5397 The third pointer is to the bottom of the GPR save area.
5398 Since the FPR save area is just below it, we can address
5399 FPR slots off this pointer.
5401 We also keep two one-byte offsets, which are to be subtracted
5402 from the constant pointers to yield addresses in the GPR and
5403 FPR save areas. These are downcounted as float or non-float
5404 arguments are used, and when they get to zero, the argument
5405 must be obtained from the overflow region. */
5406 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5409 record = lang_hooks.types.make_type (RECORD_TYPE);
5411 f_ovfl = build_decl (BUILTINS_LOCATION,
5412 FIELD_DECL, get_identifier ("__overflow_argptr"),
5414 f_gtop = build_decl (BUILTINS_LOCATION,
5415 FIELD_DECL, get_identifier ("__gpr_top"),
5417 f_ftop = build_decl (BUILTINS_LOCATION,
5418 FIELD_DECL, get_identifier ("__fpr_top"),
5420 f_goff = build_decl (BUILTINS_LOCATION,
5421 FIELD_DECL, get_identifier ("__gpr_offset"),
5422 unsigned_char_type_node);
5423 f_foff = build_decl (BUILTINS_LOCATION,
5424 FIELD_DECL, get_identifier ("__fpr_offset"),
5425 unsigned_char_type_node);
5426 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5427 warn on every user file. */
5428 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5429 array = build_array_type (unsigned_char_type_node,
5430 build_index_type (index));
5431 f_res = build_decl (BUILTINS_LOCATION,
5432 FIELD_DECL, get_identifier ("__reserved"), array);
5434 DECL_FIELD_CONTEXT (f_ovfl) = record;
5435 DECL_FIELD_CONTEXT (f_gtop) = record;
5436 DECL_FIELD_CONTEXT (f_ftop) = record;
5437 DECL_FIELD_CONTEXT (f_goff) = record;
5438 DECL_FIELD_CONTEXT (f_foff) = record;
5439 DECL_FIELD_CONTEXT (f_res) = record;
5441 TYPE_FIELDS (record) = f_ovfl;
5442 TREE_CHAIN (f_ovfl) = f_gtop;
5443 TREE_CHAIN (f_gtop) = f_ftop;
5444 TREE_CHAIN (f_ftop) = f_goff;
5445 TREE_CHAIN (f_goff) = f_foff;
5446 TREE_CHAIN (f_foff) = f_res;
5448 layout_type (record);
5451 else if (TARGET_IRIX6)
5452 /* On IRIX 6, this type is 'char *'. */
5453 return build_pointer_type (char_type_node);
5455 /* Otherwise, we use 'void *'. */
5456 return ptr_type_node;
5459 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5462 mips_va_start (tree valist, rtx nextarg)
5464 if (EABI_FLOAT_VARARGS_P)
5466 const CUMULATIVE_ARGS *cum;
5467 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5468 tree ovfl, gtop, ftop, goff, foff;
5470 int gpr_save_area_size;
5471 int fpr_save_area_size;
5474 cum = &crtl->args.info;
5476 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5478 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5480 f_ovfl = TYPE_FIELDS (va_list_type_node);
5481 f_gtop = TREE_CHAIN (f_ovfl);
5482 f_ftop = TREE_CHAIN (f_gtop);
5483 f_goff = TREE_CHAIN (f_ftop);
5484 f_foff = TREE_CHAIN (f_goff);
5486 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5488 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5490 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5492 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5494 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5497 /* Emit code to initialize OVFL, which points to the next varargs
5498 stack argument. CUM->STACK_WORDS gives the number of stack
5499 words used by named arguments. */
5500 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5501 if (cum->stack_words > 0)
5502 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5503 size_int (cum->stack_words * UNITS_PER_WORD));
5504 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5505 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5507 /* Emit code to initialize GTOP, the top of the GPR save area. */
5508 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5509 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5510 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5512 /* Emit code to initialize FTOP, the top of the FPR save area.
5513 This address is gpr_save_area_bytes below GTOP, rounded
5514 down to the next fp-aligned boundary. */
5515 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5516 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5517 fpr_offset &= -UNITS_PER_FPVALUE;
5519 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5520 size_int (-fpr_offset));
5521 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5522 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5524 /* Emit code to initialize GOFF, the offset from GTOP of the
5525 next GPR argument. */
5526 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5527 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5528 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5530 /* Likewise emit code to initialize FOFF, the offset from FTOP
5531 of the next FPR argument. */
5532 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5533 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5534 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5538 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5539 std_expand_builtin_va_start (valist, nextarg);
5543 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5546 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5552 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5554 type = build_pointer_type (type);
5556 if (!EABI_FLOAT_VARARGS_P)
5557 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5560 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5561 tree ovfl, top, off, align;
5562 HOST_WIDE_INT size, rsize, osize;
5565 f_ovfl = TYPE_FIELDS (va_list_type_node);
5566 f_gtop = TREE_CHAIN (f_ovfl);
5567 f_ftop = TREE_CHAIN (f_gtop);
5568 f_goff = TREE_CHAIN (f_ftop);
5569 f_foff = TREE_CHAIN (f_goff);
5573 TOP be the top of the GPR or FPR save area;
5574 OFF be the offset from TOP of the next register;
5575 ADDR_RTX be the address of the argument;
5576 SIZE be the number of bytes in the argument type;
5577 RSIZE be the number of bytes used to store the argument
5578 when it's in the register save area; and
5579 OSIZE be the number of bytes used to store it when it's
5580 in the stack overflow area.
5582 The code we want is:
5584 1: off &= -rsize; // round down
5587 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5592 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5593 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5597 [1] and [9] can sometimes be optimized away. */
5599 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5601 size = int_size_in_bytes (type);
5603 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5604 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5606 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5607 unshare_expr (valist), f_ftop, NULL_TREE);
5608 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5609 unshare_expr (valist), f_foff, NULL_TREE);
5611 /* When va_start saves FPR arguments to the stack, each slot
5612 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5613 argument's precision. */
5614 rsize = UNITS_PER_HWFPVALUE;
5616 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5617 (= PARM_BOUNDARY bits). This can be different from RSIZE
5620 (1) On 32-bit targets when TYPE is a structure such as:
5622 struct s { float f; };
5624 Such structures are passed in paired FPRs, so RSIZE
5625 will be 8 bytes. However, the structure only takes
5626 up 4 bytes of memory, so OSIZE will only be 4.
5628 (2) In combinations such as -mgp64 -msingle-float
5629 -fshort-double. Doubles passed in registers will then take
5630 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5631 stack take up UNITS_PER_WORD bytes. */
5632 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5636 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5637 unshare_expr (valist), f_gtop, NULL_TREE);
5638 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5639 unshare_expr (valist), f_goff, NULL_TREE);
5640 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5641 if (rsize > UNITS_PER_WORD)
5643 /* [1] Emit code for: off &= -rsize. */
5644 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5645 build_int_cst (TREE_TYPE (off), -rsize));
5646 gimplify_assign (unshare_expr (off), t, pre_p);
5651 /* [2] Emit code to branch if off == 0. */
5652 t = build2 (NE_EXPR, boolean_type_node, off,
5653 build_int_cst (TREE_TYPE (off), 0));
5654 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5656 /* [5] Emit code for: off -= rsize. We do this as a form of
5657 post-decrement not available to C. */
5658 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5659 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5661 /* [4] Emit code for:
5662 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5663 t = fold_convert (sizetype, t);
5664 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5665 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5666 if (BYTES_BIG_ENDIAN && rsize > size)
5668 u = size_int (rsize - size);
5669 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5671 COND_EXPR_THEN (addr) = t;
5673 if (osize > UNITS_PER_WORD)
5675 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5676 u = size_int (osize - 1);
5677 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5678 unshare_expr (ovfl), u);
5679 t = fold_convert (sizetype, t);
5680 u = size_int (-osize);
5681 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5682 t = fold_convert (TREE_TYPE (ovfl), t);
5683 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5684 unshare_expr (ovfl), t);
5689 /* [10, 11] Emit code for:
5690 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5692 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5693 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5694 if (BYTES_BIG_ENDIAN && osize > size)
5696 u = size_int (osize - size);
5697 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5700 /* String [9] and [10, 11] together. */
5702 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5703 COND_EXPR_ELSE (addr) = t;
5705 addr = fold_convert (build_pointer_type (type), addr);
5706 addr = build_va_arg_indirect_ref (addr);
5710 addr = build_va_arg_indirect_ref (addr);
5715 /* Start a definition of function NAME. MIPS16_P indicates whether the
5716 function contains MIPS16 code. */
5719 mips_start_function_definition (const char *name, bool mips16_p)
5722 fprintf (asm_out_file, "\t.set\tmips16\n");
5724 fprintf (asm_out_file, "\t.set\tnomips16\n");
5726 if (!flag_inhibit_size_directive)
5728 fputs ("\t.ent\t", asm_out_file);
5729 assemble_name (asm_out_file, name);
5730 fputs ("\n", asm_out_file);
5733 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5735 /* Start the definition proper. */
5736 assemble_name (asm_out_file, name);
5737 fputs (":\n", asm_out_file);
5740 /* End a function definition started by mips_start_function_definition. */
5743 mips_end_function_definition (const char *name)
5745 if (!flag_inhibit_size_directive)
5747 fputs ("\t.end\t", asm_out_file);
5748 assemble_name (asm_out_file, name);
5749 fputs ("\n", asm_out_file);
5753 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5756 mips_ok_for_lazy_binding_p (rtx x)
5758 return (TARGET_USE_GOT
5759 && GET_CODE (x) == SYMBOL_REF
5760 && !SYMBOL_REF_BIND_NOW_P (x)
5761 && !mips_symbol_binds_local_p (x));
5764 /* Load function address ADDR into register DEST. TYPE is as for
5765 mips_expand_call. Return true if we used an explicit lazy-binding
5769 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5771 /* If we're generating PIC, and this call is to a global function,
5772 try to allow its address to be resolved lazily. This isn't
5773 possible for sibcalls when $gp is call-saved because the value
5774 of $gp on entry to the stub would be our caller's gp, not ours. */
5775 if (TARGET_EXPLICIT_RELOCS
5776 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5777 && mips_ok_for_lazy_binding_p (addr))
5779 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5780 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5785 mips_emit_move (dest, addr);
5790 /* Each locally-defined hard-float MIPS16 function has a local symbol
5791 associated with it. This hash table maps the function symbol (FUNC)
5792 to the local symbol (LOCAL). */
5793 struct GTY(()) mips16_local_alias {
5797 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5799 /* Hash table callbacks for mips16_local_aliases. */
5802 mips16_local_aliases_hash (const void *entry)
5804 const struct mips16_local_alias *alias;
5806 alias = (const struct mips16_local_alias *) entry;
5807 return htab_hash_string (XSTR (alias->func, 0));
5811 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5813 const struct mips16_local_alias *alias1, *alias2;
5815 alias1 = (const struct mips16_local_alias *) entry1;
5816 alias2 = (const struct mips16_local_alias *) entry2;
5817 return rtx_equal_p (alias1->func, alias2->func);
5820 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5821 Return a local alias for it, creating a new one if necessary. */
5824 mips16_local_alias (rtx func)
5826 struct mips16_local_alias *alias, tmp_alias;
5829 /* Create the hash table if this is the first call. */
5830 if (mips16_local_aliases == NULL)
5831 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5832 mips16_local_aliases_eq, NULL);
5834 /* Look up the function symbol, creating a new entry if need be. */
5835 tmp_alias.func = func;
5836 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5837 gcc_assert (slot != NULL);
5839 alias = (struct mips16_local_alias *) *slot;
5842 const char *func_name, *local_name;
5845 /* Create a new SYMBOL_REF for the local symbol. The choice of
5846 __fn_local_* is based on the __fn_stub_* names that we've
5847 traditionally used for the non-MIPS16 stub. */
5848 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5849 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5850 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5851 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5853 /* Create a new structure to represent the mapping. */
5854 alias = GGC_NEW (struct mips16_local_alias);
5856 alias->local = local;
5859 return alias->local;
5862 /* A chained list of functions for which mips16_build_call_stub has already
5863 generated a stub. NAME is the name of the function and FP_RET_P is true
5864 if the function returns a value in floating-point registers. */
5865 struct mips16_stub {
5866 struct mips16_stub *next;
5870 static struct mips16_stub *mips16_stubs;
5872 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5875 mips16_stub_function (const char *name)
5879 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5880 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5884 /* Return the two-character string that identifies floating-point
5885 return mode MODE in the name of a MIPS16 function stub. */
5888 mips16_call_stub_mode_suffix (enum machine_mode mode)
5892 else if (mode == DFmode)
5894 else if (mode == SCmode)
5896 else if (mode == DCmode)
5898 else if (mode == V2SFmode)
5904 /* Write instructions to move a 32-bit value between general register
5905 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5906 from GPREG to FPREG and 'f' to move in the opposite direction. */
5909 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5911 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5912 reg_names[gpreg], reg_names[fpreg]);
5915 /* Likewise for 64-bit values. */
5918 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5921 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5922 reg_names[gpreg], reg_names[fpreg]);
5923 else if (TARGET_FLOAT64)
5925 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5926 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5927 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5928 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5932 /* Move the least-significant word. */
5933 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5934 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5935 /* ...then the most significant word. */
5936 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5937 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5941 /* Write out code to move floating-point arguments into or out of
5942 general registers. FP_CODE is the code describing which arguments
5943 are present (see the comment above the definition of CUMULATIVE_ARGS
5944 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5947 mips_output_args_xfer (int fp_code, char direction)
5949 unsigned int gparg, fparg, f;
5950 CUMULATIVE_ARGS cum;
5952 /* This code only works for o32 and o64. */
5953 gcc_assert (TARGET_OLDABI);
5955 mips_init_cumulative_args (&cum, NULL);
5957 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5959 enum machine_mode mode;
5960 struct mips_arg_info info;
5964 else if ((f & 3) == 2)
5969 mips_get_arg_info (&info, &cum, mode, NULL, true);
5970 gparg = mips_arg_regno (&info, false);
5971 fparg = mips_arg_regno (&info, true);
5974 mips_output_32bit_xfer (direction, gparg, fparg);
5976 mips_output_64bit_xfer (direction, gparg, fparg);
5978 mips_function_arg_advance (&cum, mode, NULL, true);
5982 /* Write a MIPS16 stub for the current function. This stub is used
5983 for functions which take arguments in the floating-point registers.
5984 It is normal-mode code that moves the floating-point arguments
5985 into the general registers and then jumps to the MIPS16 code. */
5988 mips16_build_function_stub (void)
5990 const char *fnname, *alias_name, *separator;
5991 char *secname, *stubname;
5996 /* Create the name of the stub, and its unique section. */
5997 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5998 alias = mips16_local_alias (symbol);
6000 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6001 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6002 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6003 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6005 /* Build a decl for the stub. */
6006 stubdecl = build_decl (BUILTINS_LOCATION,
6007 FUNCTION_DECL, get_identifier (stubname),
6008 build_function_type (void_type_node, NULL_TREE));
6009 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6010 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6011 RESULT_DECL, NULL_TREE, void_type_node);
6013 /* Output a comment. */
6014 fprintf (asm_out_file, "\t# Stub function for %s (",
6015 current_function_name ());
6017 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6019 fprintf (asm_out_file, "%s%s", separator,
6020 (f & 3) == 1 ? "float" : "double");
6023 fprintf (asm_out_file, ")\n");
6025 /* Start the function definition. */
6026 assemble_start_function (stubdecl, stubname);
6027 mips_start_function_definition (stubname, false);
6029 /* If generating pic2 code, either set up the global pointer or
6031 if (TARGET_ABICALLS_PIC2)
6033 if (TARGET_ABSOLUTE_ABICALLS)
6034 fprintf (asm_out_file, "\t.option\tpic0\n");
6037 output_asm_insn ("%(.cpload\t%^%)", NULL);
6038 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6039 target function is. Use a local GOT access when loading the
6040 symbol, to cut down on the number of unnecessary GOT entries
6041 for stubs that aren't needed. */
6042 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6047 /* Load the address of the MIPS16 function into $25. Do this first so
6048 that targets with coprocessor interlocks can use an MFC1 to fill the
6050 output_asm_insn ("la\t%^,%0", &symbol);
6052 /* Move the arguments from floating-point registers to general registers. */
6053 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6055 /* Jump to the MIPS16 function. */
6056 output_asm_insn ("jr\t%^", NULL);
6058 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6059 fprintf (asm_out_file, "\t.option\tpic2\n");
6061 mips_end_function_definition (stubname);
6063 /* If the linker needs to create a dynamic symbol for the target
6064 function, it will associate the symbol with the stub (which,
6065 unlike the target function, follows the proper calling conventions).
6066 It is therefore useful to have a local alias for the target function,
6067 so that it can still be identified as MIPS16 code. As an optimization,
6068 this symbol can also be used for indirect MIPS16 references from
6069 within this file. */
6070 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6072 switch_to_section (function_section (current_function_decl));
6075 /* The current function is a MIPS16 function that returns a value in an FPR.
6076 Copy the return value from its soft-float to its hard-float location.
6077 libgcc2 has special non-MIPS16 helper functions for each case. */
6080 mips16_copy_fpr_return_value (void)
6082 rtx fn, insn, retval;
6084 enum machine_mode return_mode;
6087 return_type = DECL_RESULT (current_function_decl);
6088 return_mode = DECL_MODE (return_type);
6090 name = ACONCAT (("__mips16_ret_",
6091 mips16_call_stub_mode_suffix (return_mode),
6093 fn = mips16_stub_function (name);
6095 /* The function takes arguments in $2 (and possibly $3), so calls
6096 to it cannot be lazily bound. */
6097 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6099 /* Model the call as something that takes the GPR return value as
6100 argument and returns an "updated" value. */
6101 retval = gen_rtx_REG (return_mode, GP_RETURN);
6102 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6103 const0_rtx, NULL_RTX, false);
6104 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6107 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6108 RETVAL is the location of the return value, or null if this is
6109 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6110 arguments and FP_CODE is the code built by mips_function_arg;
6111 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6113 There are three alternatives:
6115 - If a stub was needed, emit the call and return the call insn itself.
6117 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6118 to the new target and return null.
6120 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6123 A stub is needed for calls to functions that, in normal mode,
6124 receive arguments in FPRs or return values in FPRs. The stub
6125 copies the arguments from their soft-float positions to their
6126 hard-float positions, calls the real function, then copies the
6127 return value from its hard-float position to its soft-float
6130 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6131 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6132 automatically redirects the JAL to the stub, otherwise the JAL
6133 continues to call FN directly. */
6136 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6140 struct mips16_stub *l;
6143 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6144 we were invoked with the -msoft-float option. */
6145 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6148 /* Figure out whether the value might come back in a floating-point
6150 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6152 /* We don't need to do anything if there were no floating-point
6153 arguments and the value will not be returned in a floating-point
6155 if (fp_code == 0 && !fp_ret_p)
6158 /* We don't need to do anything if this is a call to a special
6159 MIPS16 support function. */
6161 if (mips16_stub_function_p (fn))
6164 /* This code will only work for o32 and o64 abis. The other ABI's
6165 require more sophisticated support. */
6166 gcc_assert (TARGET_OLDABI);
6168 /* If we're calling via a function pointer, use one of the magic
6169 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6170 Each stub expects the function address to arrive in register $2. */
6171 if (GET_CODE (fn) != SYMBOL_REF
6172 || !call_insn_operand (fn, VOIDmode))
6175 rtx stub_fn, insn, addr;
6178 /* If this is a locally-defined and locally-binding function,
6179 avoid the stub by calling the local alias directly. */
6180 if (mips16_local_function_p (fn))
6182 *fn_ptr = mips16_local_alias (fn);
6186 /* Create a SYMBOL_REF for the libgcc.a function. */
6188 sprintf (buf, "__mips16_call_stub_%s_%d",
6189 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6192 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6193 stub_fn = mips16_stub_function (buf);
6195 /* The function uses $2 as an argument, so calls to it
6196 cannot be lazily bound. */
6197 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6199 /* Load the target function into $2. */
6200 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6201 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6203 /* Emit the call. */
6204 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6205 args_size, NULL_RTX, lazy_p);
6207 /* Tell GCC that this call does indeed use the value of $2. */
6208 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6210 /* If we are handling a floating-point return value, we need to
6211 save $18 in the function prologue. Putting a note on the
6212 call will mean that df_regs_ever_live_p ($18) will be true if the
6213 call is not eliminated, and we can check that in the prologue
6216 CALL_INSN_FUNCTION_USAGE (insn) =
6217 gen_rtx_EXPR_LIST (VOIDmode,
6218 gen_rtx_CLOBBER (VOIDmode,
6219 gen_rtx_REG (word_mode, 18)),
6220 CALL_INSN_FUNCTION_USAGE (insn));
6225 /* We know the function we are going to call. If we have already
6226 built a stub, we don't need to do anything further. */
6227 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6228 for (l = mips16_stubs; l != NULL; l = l->next)
6229 if (strcmp (l->name, fnname) == 0)
6234 const char *separator;
6235 char *secname, *stubname;
6236 tree stubid, stubdecl;
6239 /* If the function does not return in FPRs, the special stub
6243 If the function does return in FPRs, the stub section is named
6244 .mips16.call.fp.FNNAME
6246 Build a decl for the stub. */
6247 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6249 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6251 stubid = get_identifier (stubname);
6252 stubdecl = build_decl (BUILTINS_LOCATION,
6253 FUNCTION_DECL, stubid,
6254 build_function_type (void_type_node, NULL_TREE));
6255 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6256 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6257 RESULT_DECL, NULL_TREE,
6260 /* Output a comment. */
6261 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6263 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6267 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6269 fprintf (asm_out_file, "%s%s", separator,
6270 (f & 3) == 1 ? "float" : "double");
6273 fprintf (asm_out_file, ")\n");
6275 /* Start the function definition. */
6276 assemble_start_function (stubdecl, stubname);
6277 mips_start_function_definition (stubname, false);
6281 /* Load the address of the MIPS16 function into $25. Do this
6282 first so that targets with coprocessor interlocks can use
6283 an MFC1 to fill the delay slot. */
6284 if (TARGET_EXPLICIT_RELOCS)
6286 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6287 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6290 output_asm_insn ("la\t%^,%0", &fn);
6293 /* Move the arguments from general registers to floating-point
6295 mips_output_args_xfer (fp_code, 't');
6299 /* Jump to the previously-loaded address. */
6300 output_asm_insn ("jr\t%^", NULL);
6304 /* Save the return address in $18 and call the non-MIPS16 function.
6305 The stub's caller knows that $18 might be clobbered, even though
6306 $18 is usually a call-saved register. */
6307 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6308 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6309 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6311 /* Move the result from floating-point registers to
6312 general registers. */
6313 switch (GET_MODE (retval))
6316 mips_output_32bit_xfer ('f', GP_RETURN + 1,
6317 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6320 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6321 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6323 /* On 64-bit targets, complex floats are returned in
6324 a single GPR, such that "sd" on a suitably-aligned
6325 target would store the value correctly. */
6326 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6327 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6328 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6329 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6330 reg_names[GP_RETURN],
6331 reg_names[GP_RETURN],
6332 reg_names[GP_RETURN + 1]);
6337 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6338 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6342 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6348 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6351 #ifdef ASM_DECLARE_FUNCTION_SIZE
6352 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6355 mips_end_function_definition (stubname);
6357 /* Record this stub. */
6358 l = XNEW (struct mips16_stub);
6359 l->name = xstrdup (fnname);
6360 l->fp_ret_p = fp_ret_p;
6361 l->next = mips16_stubs;
6365 /* If we expect a floating-point return value, but we've built a
6366 stub which does not expect one, then we're in trouble. We can't
6367 use the existing stub, because it won't handle the floating-point
6368 value. We can't build a new stub, because the linker won't know
6369 which stub to use for the various calls in this object file.
6370 Fortunately, this case is illegal, since it means that a function
6371 was declared in two different ways in a single compilation. */
6372 if (fp_ret_p && !l->fp_ret_p)
6373 error ("cannot handle inconsistent calls to %qs", fnname);
6375 if (retval == NULL_RTX)
6376 insn = gen_call_internal_direct (fn, args_size);
6378 insn = gen_call_value_internal_direct (retval, fn, args_size);
6379 insn = mips_emit_call_insn (insn, fn, fn, false);
6381 /* If we are calling a stub which handles a floating-point return
6382 value, we need to arrange to save $18 in the prologue. We do this
6383 by marking the function call as using the register. The prologue
6384 will later see that it is used, and emit code to save it. */
6386 CALL_INSN_FUNCTION_USAGE (insn) =
6387 gen_rtx_EXPR_LIST (VOIDmode,
6388 gen_rtx_CLOBBER (VOIDmode,
6389 gen_rtx_REG (word_mode, 18)),
6390 CALL_INSN_FUNCTION_USAGE (insn));
6395 /* Expand a call of type TYPE. RESULT is where the result will go (null
6396 for "call"s and "sibcall"s), ADDR is the address of the function,
6397 ARGS_SIZE is the size of the arguments and AUX is the value passed
6398 to us by mips_function_arg. LAZY_P is true if this call already
6399 involves a lazily-bound function address (such as when calling
6400 functions through a MIPS16 hard-float stub).
6402 Return the call itself. */
6405 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6406 rtx args_size, rtx aux, bool lazy_p)
6408 rtx orig_addr, pattern, insn;
6411 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6412 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6415 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6420 if (!call_insn_operand (addr, VOIDmode))
6422 if (type == MIPS_CALL_EPILOGUE)
6423 addr = MIPS_EPILOGUE_TEMP (Pmode);
6425 addr = gen_reg_rtx (Pmode);
6426 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6431 rtx (*fn) (rtx, rtx);
6433 if (type == MIPS_CALL_SIBCALL)
6434 fn = gen_sibcall_internal;
6436 fn = gen_call_internal;
6438 pattern = fn (addr, args_size);
6440 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6442 /* Handle return values created by mips_return_fpr_pair. */
6443 rtx (*fn) (rtx, rtx, rtx, rtx);
6446 if (type == MIPS_CALL_SIBCALL)
6447 fn = gen_sibcall_value_multiple_internal;
6449 fn = gen_call_value_multiple_internal;
6451 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6452 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6453 pattern = fn (reg1, addr, args_size, reg2);
6457 rtx (*fn) (rtx, rtx, rtx);
6459 if (type == MIPS_CALL_SIBCALL)
6460 fn = gen_sibcall_value_internal;
6462 fn = gen_call_value_internal;
6464 /* Handle return values created by mips_return_fpr_single. */
6465 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6466 result = XEXP (XVECEXP (result, 0, 0), 0);
6467 pattern = fn (result, addr, args_size);
6470 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6473 /* Split call instruction INSN into a $gp-clobbering call and
6474 (where necessary) an instruction to restore $gp from its save slot.
6475 CALL_PATTERN is the pattern of the new call. */
6478 mips_split_call (rtx insn, rtx call_pattern)
6482 new_insn = emit_call_insn (call_pattern);
6483 CALL_INSN_FUNCTION_USAGE (new_insn)
6484 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6485 if (!find_reg_note (insn, REG_NORETURN, 0))
6486 /* Pick a temporary register that is suitable for both MIPS16 and
6487 non-MIPS16 code. $4 and $5 are used for returning complex double
6488 values in soft-float code, so $6 is the first suitable candidate. */
6489 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6492 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6495 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6497 if (!TARGET_SIBCALLS)
6500 /* Interrupt handlers need special epilogue code and therefore can't
6502 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6505 /* We can't do a sibcall if the called function is a MIPS16 function
6506 because there is no direct "jx" instruction equivalent to "jalx" to
6507 switch the ISA mode. We only care about cases where the sibling
6508 and normal calls would both be direct. */
6510 && mips_use_mips16_mode_p (decl)
6511 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6514 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6515 functions could be MIPS16 ones unless an attribute explicitly tells
6517 if (TARGET_INTERLINK_MIPS16
6519 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6520 && !mips_nomips16_decl_p (decl)
6521 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6528 /* Emit code to move general operand SRC into condition-code
6529 register DEST given that SCRATCH is a scratch TFmode FPR.
6536 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6539 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6543 /* Change the source to SFmode. */
6545 src = adjust_address (src, SFmode, 0);
6546 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6547 src = gen_rtx_REG (SFmode, true_regnum (src));
6549 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6550 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6552 mips_emit_move (copy_rtx (fp1), src);
6553 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6554 emit_insn (gen_slt_sf (dest, fp2, fp1));
6557 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6558 Assume that the areas do not overlap. */
6561 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6563 HOST_WIDE_INT offset, delta;
6564 unsigned HOST_WIDE_INT bits;
6566 enum machine_mode mode;
6569 /* Work out how many bits to move at a time. If both operands have
6570 half-word alignment, it is usually better to move in half words.
6571 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6572 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6573 Otherwise move word-sized chunks. */
6574 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6575 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6576 bits = BITS_PER_WORD / 2;
6578 bits = BITS_PER_WORD;
6580 mode = mode_for_size (bits, MODE_INT, 0);
6581 delta = bits / BITS_PER_UNIT;
6583 /* Allocate a buffer for the temporary registers. */
6584 regs = XALLOCAVEC (rtx, length / delta);
6586 /* Load as many BITS-sized chunks as possible. Use a normal load if
6587 the source has enough alignment, otherwise use left/right pairs. */
6588 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6590 regs[i] = gen_reg_rtx (mode);
6591 if (MEM_ALIGN (src) >= bits)
6592 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6595 rtx part = adjust_address (src, BLKmode, offset);
6596 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6601 /* Copy the chunks to the destination. */
6602 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6603 if (MEM_ALIGN (dest) >= bits)
6604 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6607 rtx part = adjust_address (dest, BLKmode, offset);
6608 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6612 /* Mop up any left-over bytes. */
6613 if (offset < length)
6615 src = adjust_address (src, BLKmode, offset);
6616 dest = adjust_address (dest, BLKmode, offset);
6617 move_by_pieces (dest, src, length - offset,
6618 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6622 /* Helper function for doing a loop-based block operation on memory
6623 reference MEM. Each iteration of the loop will operate on LENGTH
6626 Create a new base register for use within the loop and point it to
6627 the start of MEM. Create a new memory reference that uses this
6628 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6631 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6632 rtx *loop_reg, rtx *loop_mem)
6634 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6636 /* Although the new mem does not refer to a known location,
6637 it does keep up to LENGTH bytes of alignment. */
6638 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6639 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6642 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6643 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6644 the memory regions do not overlap. */
6647 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6648 HOST_WIDE_INT bytes_per_iter)
6650 rtx label, src_reg, dest_reg, final_src, test;
6651 HOST_WIDE_INT leftover;
6653 leftover = length % bytes_per_iter;
6656 /* Create registers and memory references for use within the loop. */
6657 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6658 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6660 /* Calculate the value that SRC_REG should have after the last iteration
6662 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6665 /* Emit the start of the loop. */
6666 label = gen_label_rtx ();
6669 /* Emit the loop body. */
6670 mips_block_move_straight (dest, src, bytes_per_iter);
6672 /* Move on to the next block. */
6673 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6674 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6676 /* Emit the loop condition. */
6677 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6678 if (Pmode == DImode)
6679 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6681 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6683 /* Mop up any left-over bytes. */
6685 mips_block_move_straight (dest, src, leftover);
6688 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6689 memory reference SRC to memory reference DEST. */
6692 mips_expand_block_move (rtx dest, rtx src, rtx length)
6694 if (CONST_INT_P (length))
6696 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6698 mips_block_move_straight (dest, src, INTVAL (length));
6703 mips_block_move_loop (dest, src, INTVAL (length),
6704 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6711 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6714 mips_expand_synci_loop (rtx begin, rtx end)
6716 rtx inc, label, end_label, cmp_result, mask, length;
6718 /* Create end_label. */
6719 end_label = gen_label_rtx ();
6721 /* Check if begin equals end. */
6722 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6723 emit_jump_insn (gen_condjump (cmp_result, end_label));
6725 /* Load INC with the cache line size (rdhwr INC,$1). */
6726 inc = gen_reg_rtx (Pmode);
6727 emit_insn (Pmode == SImode
6728 ? gen_rdhwr_synci_step_si (inc)
6729 : gen_rdhwr_synci_step_di (inc));
6731 /* Check if inc is 0. */
6732 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
6733 emit_jump_insn (gen_condjump (cmp_result, end_label));
6735 /* Calculate mask. */
6736 mask = mips_force_unary (Pmode, NEG, inc);
6738 /* Mask out begin by mask. */
6739 begin = mips_force_binary (Pmode, AND, begin, mask);
6741 /* Calculate length. */
6742 length = mips_force_binary (Pmode, MINUS, end, begin);
6744 /* Loop back to here. */
6745 label = gen_label_rtx ();
6748 emit_insn (gen_synci (begin));
6750 /* Update length. */
6751 mips_emit_binary (MINUS, length, length, inc);
6754 mips_emit_binary (PLUS, begin, begin, inc);
6756 /* Check if length is greater than 0. */
6757 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
6758 emit_jump_insn (gen_condjump (cmp_result, label));
6760 emit_label (end_label);
6763 /* Expand a QI or HI mode atomic memory operation.
6765 GENERATOR contains a pointer to the gen_* function that generates
6766 the SI mode underlying atomic operation using masks that we
6769 RESULT is the return register for the operation. Its value is NULL
6772 MEM is the location of the atomic access.
6774 OLDVAL is the first operand for the operation.
6776 NEWVAL is the optional second operand for the operation. Its value
6777 is NULL if unused. */
6780 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6781 rtx result, rtx mem, rtx oldval, rtx newval)
6783 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6784 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6786 enum machine_mode mode;
6788 mode = GET_MODE (mem);
6790 /* Compute the address of the containing SImode value. */
6791 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6792 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6793 force_reg (Pmode, GEN_INT (-4)));
6795 /* Create a memory reference for it. */
6796 memsi = gen_rtx_MEM (SImode, memsi_addr);
6797 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6798 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6800 /* Work out the byte offset of the QImode or HImode value,
6801 counting from the least significant byte. */
6802 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6803 if (TARGET_BIG_ENDIAN)
6804 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6806 /* Multiply by eight to convert the shift value from bytes to bits. */
6807 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6809 /* Make the final shift an SImode value, so that it can be used in
6810 SImode operations. */
6811 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6813 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6814 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6815 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6816 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6818 /* Compute the equivalent exclusive mask. */
6819 inverted_mask = gen_reg_rtx (SImode);
6820 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6821 gen_rtx_NOT (SImode, mask)));
6823 /* Shift the old value into place. */
6824 if (oldval != const0_rtx)
6826 oldval = convert_modes (SImode, mode, oldval, true);
6827 oldval = force_reg (SImode, oldval);
6828 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6831 /* Do the same for the new value. */
6832 if (newval && newval != const0_rtx)
6834 newval = convert_modes (SImode, mode, newval, true);
6835 newval = force_reg (SImode, newval);
6836 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6839 /* Do the SImode atomic access. */
6841 res = gen_reg_rtx (SImode);
6843 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6845 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6847 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6853 /* Shift and convert the result. */
6854 mips_emit_binary (AND, res, res, mask);
6855 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6856 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6860 /* Return true if it is possible to use left/right accesses for a
6861 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6862 returning true, update *OP, *LEFT and *RIGHT as follows:
6864 *OP is a BLKmode reference to the whole field.
6866 *LEFT is a QImode reference to the first byte if big endian or
6867 the last byte if little endian. This address can be used in the
6868 left-side instructions (LWL, SWL, LDL, SDL).
6870 *RIGHT is a QImode reference to the opposite end of the field and
6871 can be used in the patterning right-side instruction. */
6874 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6875 rtx *left, rtx *right)
6879 /* Check that the operand really is a MEM. Not all the extv and
6880 extzv predicates are checked. */
6884 /* Check that the size is valid. */
6885 if (width != 32 && (!TARGET_64BIT || width != 64))
6888 /* We can only access byte-aligned values. Since we are always passed
6889 a reference to the first byte of the field, it is not necessary to
6890 do anything with BITPOS after this check. */
6891 if (bitpos % BITS_PER_UNIT != 0)
6894 /* Reject aligned bitfields: we want to use a normal load or store
6895 instead of a left/right pair. */
6896 if (MEM_ALIGN (*op) >= width)
6899 /* Adjust *OP to refer to the whole field. This also has the effect
6900 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6901 *op = adjust_address (*op, BLKmode, 0);
6902 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6904 /* Get references to both ends of the field. We deliberately don't
6905 use the original QImode *OP for FIRST since the new BLKmode one
6906 might have a simpler address. */
6907 first = adjust_address (*op, QImode, 0);
6908 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6910 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6911 correspond to the MSB and RIGHT to the LSB. */
6912 if (TARGET_BIG_ENDIAN)
6913 *left = first, *right = last;
6915 *left = last, *right = first;
6920 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6921 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6922 the operation is the equivalent of:
6924 (set DEST (*_extract SRC WIDTH BITPOS))
6926 Return true on success. */
6929 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6930 HOST_WIDE_INT bitpos)
6932 rtx left, right, temp;
6934 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6935 be a paradoxical word_mode subreg. This is the only case in which
6936 we allow the destination to be larger than the source. */
6937 if (GET_CODE (dest) == SUBREG
6938 && GET_MODE (dest) == DImode
6939 && GET_MODE (SUBREG_REG (dest)) == SImode)
6940 dest = SUBREG_REG (dest);
6942 /* After the above adjustment, the destination must be the same
6943 width as the source. */
6944 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6947 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6950 temp = gen_reg_rtx (GET_MODE (dest));
6951 if (GET_MODE (dest) == DImode)
6953 emit_insn (gen_mov_ldl (temp, src, left));
6954 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6958 emit_insn (gen_mov_lwl (temp, src, left));
6959 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6964 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6965 BITPOS and SRC are the operands passed to the expander; the operation
6966 is the equivalent of:
6968 (set (zero_extract DEST WIDTH BITPOS) SRC)
6970 Return true on success. */
6973 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6974 HOST_WIDE_INT bitpos)
6977 enum machine_mode mode;
6979 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6982 mode = mode_for_size (width, MODE_INT, 0);
6983 src = gen_lowpart (mode, src);
6986 emit_insn (gen_mov_sdl (dest, src, left));
6987 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6991 emit_insn (gen_mov_swl (dest, src, left));
6992 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6997 /* Return true if X is a MEM with the same size as MODE. */
7000 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7007 size = MEM_SIZE (x);
7008 return size && INTVAL (size) == GET_MODE_SIZE (mode);
7011 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7012 source of an "ext" instruction or the destination of an "ins"
7013 instruction. OP must be a register operand and the following
7014 conditions must hold:
7016 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7017 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7018 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7020 Also reject lengths equal to a word as they are better handled
7021 by the move patterns. */
7024 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7026 if (!ISA_HAS_EXT_INS
7027 || !register_operand (op, VOIDmode)
7028 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7031 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7034 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7040 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7041 operation if MAXLEN is the maxium length of consecutive bits that
7042 can make up MASK. MODE is the mode of the operation. See
7043 mask_low_and_shift_len for the actual definition. */
7046 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7048 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7051 /* Return true iff OP1 and OP2 are valid operands together for the
7052 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7053 see the table in the comment before the pattern. */
7056 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7058 return (memory_operand (op1, mode)
7059 ? and_load_operand (op2, mode)
7060 : and_reg_operand (op2, mode));
7063 /* The canonical form of a mask-low-and-shift-left operation is
7064 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7065 cleared. Thus we need to shift MASK to the right before checking if it
7066 is a valid mask value. MODE is the mode of the operation. If true
7067 return the length of the mask, otherwise return -1. */
7070 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7072 HOST_WIDE_INT shval;
7074 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7075 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7078 /* Return true if -msplit-addresses is selected and should be honored.
7080 -msplit-addresses is a half-way house between explicit relocations
7081 and the traditional assembler macros. It can split absolute 32-bit
7082 symbolic constants into a high/lo_sum pair but uses macros for other
7085 Like explicit relocation support for REL targets, it relies
7086 on GNU extensions in the assembler and the linker.
7088 Although this code should work for -O0, it has traditionally
7089 been treated as an optimization. */
7092 mips_split_addresses_p (void)
7094 return (TARGET_SPLIT_ADDRESSES
7098 && !ABI_HAS_64BIT_SYMBOLS);
7101 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7104 mips_init_relocs (void)
7106 memset (mips_split_p, '\0', sizeof (mips_split_p));
7107 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7108 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7109 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7111 if (ABI_HAS_64BIT_SYMBOLS)
7113 if (TARGET_EXPLICIT_RELOCS)
7115 mips_split_p[SYMBOL_64_HIGH] = true;
7116 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7117 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7119 mips_split_p[SYMBOL_64_MID] = true;
7120 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7121 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7123 mips_split_p[SYMBOL_64_LOW] = true;
7124 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7125 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7127 mips_split_p[SYMBOL_ABSOLUTE] = true;
7128 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7133 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7135 mips_split_p[SYMBOL_ABSOLUTE] = true;
7136 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7137 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7139 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7145 /* The high part is provided by a pseudo copy of $gp. */
7146 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7147 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7149 else if (TARGET_EXPLICIT_RELOCS)
7150 /* Small data constants are kept whole until after reload,
7151 then lowered by mips_rewrite_small_data. */
7152 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7154 if (TARGET_EXPLICIT_RELOCS)
7156 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7159 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7160 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7164 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7165 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7168 /* Expose the use of $28 as soon as possible. */
7169 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7173 /* The HIGH and LO_SUM are matched by special .md patterns. */
7174 mips_split_p[SYMBOL_GOT_DISP] = true;
7176 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7177 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7178 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7180 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7181 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7182 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7187 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7189 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7190 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7192 /* Expose the use of $28 as soon as possible. */
7193 mips_split_p[SYMBOL_GOT_DISP] = true;
7199 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7200 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7201 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7204 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7205 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7207 mips_split_p[SYMBOL_DTPREL] = true;
7208 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7209 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7211 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7213 mips_split_p[SYMBOL_TPREL] = true;
7214 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7215 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7217 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7220 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7221 in context CONTEXT. RELOCS is the array of relocations to use. */
7224 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7225 const char **relocs)
7227 enum mips_symbol_type symbol_type;
7230 symbol_type = mips_classify_symbolic_expression (op, context);
7231 gcc_assert (relocs[symbol_type]);
7233 fputs (relocs[symbol_type], file);
7234 output_addr_const (file, mips_strip_unspec_address (op));
7235 for (p = relocs[symbol_type]; *p != 0; p++)
7240 /* Start a new block with the given asm switch enabled. If we need
7241 to print a directive, emit PREFIX before it and SUFFIX after it. */
7244 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7245 const char *prefix, const char *suffix)
7247 if (asm_switch->nesting_level == 0)
7248 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7249 asm_switch->nesting_level++;
7252 /* Likewise, but end a block. */
7255 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7256 const char *prefix, const char *suffix)
7258 gcc_assert (asm_switch->nesting_level);
7259 asm_switch->nesting_level--;
7260 if (asm_switch->nesting_level == 0)
7261 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7264 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7265 that either print a complete line or print nothing. */
7268 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7270 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7274 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7276 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7279 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7280 The punctuation characters are:
7282 '(' Start a nested ".set noreorder" block.
7283 ')' End a nested ".set noreorder" block.
7284 '[' Start a nested ".set noat" block.
7285 ']' End a nested ".set noat" block.
7286 '<' Start a nested ".set nomacro" block.
7287 '>' End a nested ".set nomacro" block.
7288 '*' Behave like %(%< if generating a delayed-branch sequence.
7289 '#' Print a nop if in a ".set noreorder" block.
7290 '/' Like '#', but do nothing within a delayed-branch sequence.
7291 '?' Print "l" if mips_branch_likely is true
7292 '~' Print a nop if mips_branch_likely is true
7293 '.' Print the name of the register with a hard-wired zero (zero or $0).
7294 '@' Print the name of the assembler temporary register (at or $1).
7295 '^' Print the name of the pic call-through register (t9 or $25).
7296 '+' Print the name of the gp register (usually gp or $28).
7297 '$' Print the name of the stack pointer register (sp or $29).
7299 See also mips_init_print_operand_pucnt. */
7302 mips_print_operand_punctuation (FILE *file, int ch)
7307 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7311 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7315 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7319 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7323 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7327 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7331 if (final_sequence != 0)
7333 mips_print_operand_punctuation (file, '(');
7334 mips_print_operand_punctuation (file, '<');
7339 if (mips_noreorder.nesting_level > 0)
7340 fputs ("\n\tnop", file);
7344 /* Print an extra newline so that the delayed insn is separated
7345 from the following ones. This looks neater and is consistent
7346 with non-nop delayed sequences. */
7347 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7348 fputs ("\n\tnop\n", file);
7352 if (mips_branch_likely)
7357 if (mips_branch_likely)
7358 fputs ("\n\tnop", file);
7362 fputs (reg_names[GP_REG_FIRST + 0], file);
7366 fputs (reg_names[AT_REGNUM], file);
7370 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7374 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7378 fputs (reg_names[STACK_POINTER_REGNUM], file);
7387 /* Initialize mips_print_operand_punct. */
7390 mips_init_print_operand_punct (void)
7394 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7395 mips_print_operand_punct[(unsigned char) *p] = true;
7398 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7399 associated with condition CODE. Print the condition part of the
7403 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7417 /* Conveniently, the MIPS names for these conditions are the same
7418 as their RTL equivalents. */
7419 fputs (GET_RTX_NAME (code), file);
7423 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7428 /* Likewise floating-point branches. */
7431 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7436 fputs ("c1f", file);
7440 fputs ("c1t", file);
7444 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7449 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7451 'X' Print CONST_INT OP in hexadecimal format.
7452 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7453 'd' Print CONST_INT OP in decimal.
7454 'm' Print one less than CONST_INT OP in decimal.
7455 'h' Print the high-part relocation associated with OP, after stripping
7457 'R' Print the low-part relocation associated with OP.
7458 'C' Print the integer branch condition for comparison OP.
7459 'N' Print the inverse of the integer branch condition for comparison OP.
7460 'F' Print the FPU branch condition for comparison OP.
7461 'W' Print the inverse of the FPU branch condition for comparison OP.
7462 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7463 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7464 't' Like 'T', but with the EQ/NE cases reversed
7465 'Y' Print mips_fp_conditions[INTVAL (OP)]
7466 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7467 'q' Print a DSP accumulator register.
7468 'D' Print the second part of a double-word register or memory operand.
7469 'L' Print the low-order register in a double-word register operand.
7470 'M' Print high-order register in a double-word register operand.
7471 'z' Print $0 if OP is zero, otherwise print OP normally. */
7474 mips_print_operand (FILE *file, rtx op, int letter)
7478 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7480 mips_print_operand_punctuation (file, letter);
7485 code = GET_CODE (op);
7490 if (CONST_INT_P (op))
7491 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7493 output_operand_lossage ("invalid use of '%%%c'", letter);
7497 if (CONST_INT_P (op))
7498 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7500 output_operand_lossage ("invalid use of '%%%c'", letter);
7504 if (CONST_INT_P (op))
7505 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7507 output_operand_lossage ("invalid use of '%%%c'", letter);
7511 if (CONST_INT_P (op))
7512 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7514 output_operand_lossage ("invalid use of '%%%c'", letter);
7520 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7524 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7528 mips_print_int_branch_condition (file, code, letter);
7532 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7536 mips_print_float_branch_condition (file, code, letter);
7540 mips_print_float_branch_condition (file, reverse_condition (code),
7547 int truth = (code == NE) == (letter == 'T');
7548 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7553 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7554 fputs (mips_fp_conditions[UINTVAL (op)], file);
7556 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7563 mips_print_operand (file, op, 0);
7569 if (code == REG && MD_REG_P (REGNO (op)))
7570 fprintf (file, "$ac0");
7571 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7572 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7574 output_operand_lossage ("invalid use of '%%%c'", letter);
7582 unsigned int regno = REGNO (op);
7583 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7584 || (letter == 'L' && TARGET_BIG_ENDIAN)
7587 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7588 output_operand_lossage ("invalid use of '%%%c'", letter);
7589 /* We need to print $0 .. $31 for COP0 registers. */
7590 if (COP0_REG_P (regno))
7591 fprintf (file, "$%s", ®_names[regno][4]);
7593 fprintf (file, "%s", reg_names[regno]);
7599 output_address (plus_constant (XEXP (op, 0), 4));
7600 else if (letter && letter != 'z')
7601 output_operand_lossage ("invalid use of '%%%c'", letter);
7603 output_address (XEXP (op, 0));
7607 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7608 fputs (reg_names[GP_REG_FIRST], file);
7609 else if (letter && letter != 'z')
7610 output_operand_lossage ("invalid use of '%%%c'", letter);
7611 else if (CONST_GP_P (op))
7612 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7614 output_addr_const (file, mips_strip_unspec_address (op));
7620 /* Output address operand X to FILE. */
7623 mips_print_operand_address (FILE *file, rtx x)
7625 struct mips_address_info addr;
7627 if (mips_classify_address (&addr, x, word_mode, true))
7631 mips_print_operand (file, addr.offset, 0);
7632 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7635 case ADDRESS_LO_SUM:
7636 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7638 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7641 case ADDRESS_CONST_INT:
7642 output_addr_const (file, x);
7643 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7646 case ADDRESS_SYMBOLIC:
7647 output_addr_const (file, mips_strip_unspec_address (x));
7653 /* Implement TARGET_ENCODE_SECTION_INFO. */
7656 mips_encode_section_info (tree decl, rtx rtl, int first)
7658 default_encode_section_info (decl, rtl, first);
7660 if (TREE_CODE (decl) == FUNCTION_DECL)
7662 rtx symbol = XEXP (rtl, 0);
7663 tree type = TREE_TYPE (decl);
7665 /* Encode whether the symbol is short or long. */
7666 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7667 || mips_far_type_p (type))
7668 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7672 /* Implement TARGET_SELECT_RTX_SECTION. */
7675 mips_select_rtx_section (enum machine_mode mode, rtx x,
7676 unsigned HOST_WIDE_INT align)
7678 /* ??? Consider using mergeable small data sections. */
7679 if (mips_rtx_constant_in_small_data_p (mode))
7680 return get_named_section (NULL, ".sdata", 0);
7682 return default_elf_select_rtx_section (mode, x, align);
7685 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7687 The complication here is that, with the combination TARGET_ABICALLS
7688 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7689 absolute addresses, and should therefore not be included in the
7690 read-only part of a DSO. Handle such cases by selecting a normal
7691 data section instead of a read-only one. The logic apes that in
7692 default_function_rodata_section. */
7695 mips_function_rodata_section (tree decl)
7697 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7698 return default_function_rodata_section (decl);
7700 if (decl && DECL_SECTION_NAME (decl))
7702 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7703 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7705 char *rname = ASTRDUP (name);
7707 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7709 else if (flag_function_sections
7710 && flag_data_sections
7711 && strncmp (name, ".text.", 6) == 0)
7713 char *rname = ASTRDUP (name);
7714 memcpy (rname + 1, "data", 4);
7715 return get_section (rname, SECTION_WRITE, decl);
7718 return data_section;
7721 /* Implement TARGET_IN_SMALL_DATA_P. */
7724 mips_in_small_data_p (const_tree decl)
7726 unsigned HOST_WIDE_INT size;
7728 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7731 /* We don't yet generate small-data references for -mabicalls
7732 or VxWorks RTP code. See the related -G handling in
7733 mips_override_options. */
7734 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7737 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7741 /* Reject anything that isn't in a known small-data section. */
7742 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7743 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7746 /* If a symbol is defined externally, the assembler will use the
7747 usual -G rules when deciding how to implement macros. */
7748 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7751 else if (TARGET_EMBEDDED_DATA)
7753 /* Don't put constants into the small data section: we want them
7754 to be in ROM rather than RAM. */
7755 if (TREE_CODE (decl) != VAR_DECL)
7758 if (TREE_READONLY (decl)
7759 && !TREE_SIDE_EFFECTS (decl)
7760 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7764 /* Enforce -mlocal-sdata. */
7765 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7768 /* Enforce -mextern-sdata. */
7769 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7771 if (DECL_EXTERNAL (decl))
7773 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7777 /* We have traditionally not treated zero-sized objects as small data,
7778 so this is now effectively part of the ABI. */
7779 size = int_size_in_bytes (TREE_TYPE (decl));
7780 return size > 0 && size <= mips_small_data_threshold;
7783 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7784 anchors for small data: the GP register acts as an anchor in that
7785 case. We also don't want to use them for PC-relative accesses,
7786 where the PC acts as an anchor. */
7789 mips_use_anchors_for_symbol_p (const_rtx symbol)
7791 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7793 case SYMBOL_PC_RELATIVE:
7794 case SYMBOL_GP_RELATIVE:
7798 return default_use_anchors_for_symbol_p (symbol);
7802 /* The MIPS debug format wants all automatic variables and arguments
7803 to be in terms of the virtual frame pointer (stack pointer before
7804 any adjustment in the function), while the MIPS 3.0 linker wants
7805 the frame pointer to be the stack pointer after the initial
7806 adjustment. So, we do the adjustment here. The arg pointer (which
7807 is eliminated) points to the virtual frame pointer, while the frame
7808 pointer (which may be eliminated) points to the stack pointer after
7809 the initial adjustments. */
7812 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7814 rtx offset2 = const0_rtx;
7815 rtx reg = eliminate_constant_term (addr, &offset2);
7818 offset = INTVAL (offset2);
7820 if (reg == stack_pointer_rtx
7821 || reg == frame_pointer_rtx
7822 || reg == hard_frame_pointer_rtx)
7824 offset -= cfun->machine->frame.total_size;
7825 if (reg == hard_frame_pointer_rtx)
7826 offset += cfun->machine->frame.hard_frame_pointer_offset;
7829 /* sdbout_parms does not want this to crash for unrecognized cases. */
7831 else if (reg != arg_pointer_rtx)
7832 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7839 /* Implement ASM_OUTPUT_EXTERNAL. */
7842 mips_output_external (FILE *file, tree decl, const char *name)
7844 default_elf_asm_output_external (file, decl, name);
7846 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7847 set in order to avoid putting out names that are never really
7849 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7851 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7853 /* When using assembler macros, emit .extern directives for
7854 all small-data externs so that the assembler knows how
7857 In most cases it would be safe (though pointless) to emit
7858 .externs for other symbols too. One exception is when an
7859 object is within the -G limit but declared by the user to
7860 be in a section other than .sbss or .sdata. */
7861 fputs ("\t.extern\t", file);
7862 assemble_name (file, name);
7863 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7864 int_size_in_bytes (TREE_TYPE (decl)));
7869 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7872 mips_output_filename (FILE *stream, const char *name)
7874 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7876 if (write_symbols == DWARF2_DEBUG)
7878 else if (mips_output_filename_first_time)
7880 mips_output_filename_first_time = 0;
7881 num_source_filenames += 1;
7882 current_function_file = name;
7883 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7884 output_quoted_string (stream, name);
7885 putc ('\n', stream);
7887 /* If we are emitting stabs, let dbxout.c handle this (except for
7888 the mips_output_filename_first_time case). */
7889 else if (write_symbols == DBX_DEBUG)
7891 else if (name != current_function_file
7892 && strcmp (name, current_function_file) != 0)
7894 num_source_filenames += 1;
7895 current_function_file = name;
7896 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7897 output_quoted_string (stream, name);
7898 putc ('\n', stream);
7902 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7904 static void ATTRIBUTE_UNUSED
7905 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7910 fputs ("\t.dtprelword\t", file);
7914 fputs ("\t.dtpreldword\t", file);
7920 output_addr_const (file, x);
7921 fputs ("+0x8000", file);
7924 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7927 mips_dwarf_register_span (rtx reg)
7930 enum machine_mode mode;
7932 /* By default, GCC maps increasing register numbers to increasing
7933 memory locations, but paired FPRs are always little-endian,
7934 regardless of the prevailing endianness. */
7935 mode = GET_MODE (reg);
7936 if (FP_REG_P (REGNO (reg))
7937 && TARGET_BIG_ENDIAN
7938 && MAX_FPRS_PER_FMT > 1
7939 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7941 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7942 high = mips_subword (reg, true);
7943 low = mips_subword (reg, false);
7944 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7950 /* Implement ASM_OUTPUT_ASCII. */
7953 mips_output_ascii (FILE *stream, const char *string, size_t len)
7959 fprintf (stream, "\t.ascii\t\"");
7960 for (i = 0; i < len; i++)
7964 c = (unsigned char) string[i];
7967 if (c == '\\' || c == '\"')
7969 putc ('\\', stream);
7977 fprintf (stream, "\\%03o", c);
7981 if (cur_pos > 72 && i+1 < len)
7984 fprintf (stream, "\"\n\t.ascii\t\"");
7987 fprintf (stream, "\"\n");
7990 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7991 macros, mark the symbol as written so that mips_asm_output_external
7992 won't emit an .extern for it. STREAM is the output file, NAME is the
7993 name of the symbol, INIT_STRING is the string that should be written
7994 before the symbol and FINAL_STRING is the string that should be
7995 written after it. FINAL_STRING is a printf format that consumes the
7996 remaining arguments. */
7999 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8000 const char *final_string, ...)
8004 fputs (init_string, stream);
8005 assemble_name (stream, name);
8006 va_start (ap, final_string);
8007 vfprintf (stream, final_string, ap);
8010 if (!TARGET_EXPLICIT_RELOCS)
8012 tree name_tree = get_identifier (name);
8013 TREE_ASM_WRITTEN (name_tree) = 1;
8017 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8018 NAME is the name of the object and ALIGN is the required alignment
8019 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8020 alignment argument. */
8023 mips_declare_common_object (FILE *stream, const char *name,
8024 const char *init_string,
8025 unsigned HOST_WIDE_INT size,
8026 unsigned int align, bool takes_alignment_p)
8028 if (!takes_alignment_p)
8030 size += (align / BITS_PER_UNIT) - 1;
8031 size -= size % (align / BITS_PER_UNIT);
8032 mips_declare_object (stream, name, init_string,
8033 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8036 mips_declare_object (stream, name, init_string,
8037 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8038 size, align / BITS_PER_UNIT);
8041 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8042 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8045 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8046 unsigned HOST_WIDE_INT size,
8049 /* If the target wants uninitialized const declarations in
8050 .rdata then don't put them in .comm. */
8051 if (TARGET_EMBEDDED_DATA
8052 && TARGET_UNINIT_CONST_IN_RODATA
8053 && TREE_CODE (decl) == VAR_DECL
8054 && TREE_READONLY (decl)
8055 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8057 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8058 targetm.asm_out.globalize_label (stream, name);
8060 switch_to_section (readonly_data_section);
8061 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8062 mips_declare_object (stream, name, "",
8063 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8067 mips_declare_common_object (stream, name, "\n\t.comm\t",
8071 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8072 extern int size_directive_output;
8074 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8075 definitions except that it uses mips_declare_object to emit the label. */
8078 mips_declare_object_name (FILE *stream, const char *name,
8079 tree decl ATTRIBUTE_UNUSED)
8081 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8082 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8085 size_directive_output = 0;
8086 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8090 size_directive_output = 1;
8091 size = int_size_in_bytes (TREE_TYPE (decl));
8092 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8095 mips_declare_object (stream, name, "", ":\n");
8098 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8101 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8105 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8106 if (!flag_inhibit_size_directive
8107 && DECL_SIZE (decl) != 0
8110 && DECL_INITIAL (decl) == error_mark_node
8111 && !size_directive_output)
8115 size_directive_output = 1;
8116 size = int_size_in_bytes (TREE_TYPE (decl));
8117 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8122 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8123 with the current ABI. */
8126 mips_mdebug_abi_name (void)
8139 return TARGET_64BIT ? "eabi64" : "eabi32";
8145 /* Implement TARGET_ASM_FILE_START. */
8148 mips_file_start (void)
8150 default_file_start ();
8152 /* Generate a special section to describe the ABI switches used to
8153 produce the resultant binary. This is unnecessary on IRIX and
8154 causes unwanted warnings from the native linker. */
8157 /* Record the ABI itself. Modern versions of binutils encode
8158 this information in the ELF header flags, but GDB needs the
8159 information in order to correctly debug binaries produced by
8160 older binutils. See the function mips_gdbarch_init in
8162 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8163 mips_mdebug_abi_name ());
8165 /* There is no ELF header flag to distinguish long32 forms of the
8166 EABI from long64 forms. Emit a special section to help tools
8167 such as GDB. Do the same for o64, which is sometimes used with
8169 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8170 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8171 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8173 #ifdef HAVE_AS_GNU_ATTRIBUTE
8177 /* No floating-point operations, -mno-float. */
8178 if (TARGET_NO_FLOAT)
8180 /* Soft-float code, -msoft-float. */
8181 else if (!TARGET_HARD_FLOAT_ABI)
8183 /* Single-float code, -msingle-float. */
8184 else if (!TARGET_DOUBLE_FLOAT)
8186 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8187 else if (!TARGET_64BIT && TARGET_FLOAT64)
8189 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8193 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8198 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8199 if (TARGET_ABICALLS)
8201 fprintf (asm_out_file, "\t.abicalls\n");
8202 if (TARGET_ABICALLS_PIC0)
8203 fprintf (asm_out_file, "\t.option\tpic0\n");
8206 if (flag_verbose_asm)
8207 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8209 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8212 /* Make the last instruction frame-related and note that it performs
8213 the operation described by FRAME_PATTERN. */
8216 mips_set_frame_expr (rtx frame_pattern)
8220 insn = get_last_insn ();
8221 RTX_FRAME_RELATED_P (insn) = 1;
8222 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8227 /* Return a frame-related rtx that stores REG at MEM.
8228 REG must be a single register. */
8231 mips_frame_set (rtx mem, rtx reg)
8235 /* If we're saving the return address register and the DWARF return
8236 address column differs from the hard register number, adjust the
8237 note reg to refer to the former. */
8238 if (REGNO (reg) == RETURN_ADDR_REGNUM
8239 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8240 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8242 set = gen_rtx_SET (VOIDmode, mem, reg);
8243 RTX_FRAME_RELATED_P (set) = 1;
8248 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8249 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8250 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8251 static const unsigned char mips16e_s2_s8_regs[] = {
8252 30, 23, 22, 21, 20, 19, 18
8254 static const unsigned char mips16e_a0_a3_regs[] = {
8258 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8259 ordered from the uppermost in memory to the lowest in memory. */
8260 static const unsigned char mips16e_save_restore_regs[] = {
8261 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8264 /* Return the index of the lowest X in the range [0, SIZE) for which
8265 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8268 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8273 for (i = 0; i < size; i++)
8274 if (BITSET_P (mask, regs[i]))
8280 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8281 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8282 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8283 is true for all indexes (X, SIZE). */
8286 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8287 unsigned int size, unsigned int *num_regs_ptr)
8291 i = mips16e_find_first_register (*mask_ptr, regs, size);
8292 for (i++; i < size; i++)
8293 if (!BITSET_P (*mask_ptr, regs[i]))
8296 *mask_ptr |= 1 << regs[i];
8300 /* Return a simplified form of X using the register values in REG_VALUES.
8301 REG_VALUES[R] is the last value assigned to hard register R, or null
8302 if R has not been modified.
8304 This function is rather limited, but is good enough for our purposes. */
8307 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8309 x = avoid_constant_pool_reference (x);
8313 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8314 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8315 x0, GET_MODE (XEXP (x, 0)));
8318 if (ARITHMETIC_P (x))
8320 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8321 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8322 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8326 && reg_values[REGNO (x)]
8327 && !rtx_unstable_p (reg_values[REGNO (x)]))
8328 return reg_values[REGNO (x)];
8333 /* Return true if (set DEST SRC) stores an argument register into its
8334 caller-allocated save slot, storing the number of that argument
8335 register in *REGNO_PTR if so. REG_VALUES is as for
8336 mips16e_collect_propagate_value. */
8339 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8340 unsigned int *regno_ptr)
8342 unsigned int argno, regno;
8343 HOST_WIDE_INT offset, required_offset;
8346 /* Check that this is a word-mode store. */
8347 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8350 /* Check that the register being saved is an unmodified argument
8352 regno = REGNO (src);
8353 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8355 argno = regno - GP_ARG_FIRST;
8357 /* Check whether the address is an appropriate stack-pointer or
8358 frame-pointer access. */
8359 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8360 mips_split_plus (addr, &base, &offset);
8361 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8362 if (base == hard_frame_pointer_rtx)
8363 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8364 else if (base != stack_pointer_rtx)
8366 if (offset != required_offset)
8373 /* A subroutine of mips_expand_prologue, called only when generating
8374 MIPS16e SAVE instructions. Search the start of the function for any
8375 instructions that save argument registers into their caller-allocated
8376 save slots. Delete such instructions and return a value N such that
8377 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8378 instructions redundant. */
8381 mips16e_collect_argument_saves (void)
8383 rtx reg_values[FIRST_PSEUDO_REGISTER];
8384 rtx insn, next, set, dest, src;
8385 unsigned int nargs, regno;
8387 push_topmost_sequence ();
8389 memset (reg_values, 0, sizeof (reg_values));
8390 for (insn = get_insns (); insn; insn = next)
8392 next = NEXT_INSN (insn);
8393 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8399 set = PATTERN (insn);
8400 if (GET_CODE (set) != SET)
8403 dest = SET_DEST (set);
8404 src = SET_SRC (set);
8405 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8407 if (!BITSET_P (cfun->machine->frame.mask, regno))
8410 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8413 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8414 reg_values[REGNO (dest)]
8415 = mips16e_collect_propagate_value (src, reg_values);
8419 pop_topmost_sequence ();
8424 /* Return a move between register REGNO and memory location SP + OFFSET.
8425 Make the move a load if RESTORE_P, otherwise make it a frame-related
8429 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8434 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8435 reg = gen_rtx_REG (SImode, regno);
8437 ? gen_rtx_SET (VOIDmode, reg, mem)
8438 : mips_frame_set (mem, reg));
8441 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8442 The instruction must:
8444 - Allocate or deallocate SIZE bytes in total; SIZE is known
8447 - Save or restore as many registers in *MASK_PTR as possible.
8448 The instruction saves the first registers at the top of the
8449 allocated area, with the other registers below it.
8451 - Save NARGS argument registers above the allocated area.
8453 (NARGS is always zero if RESTORE_P.)
8455 The SAVE and RESTORE instructions cannot save and restore all general
8456 registers, so there may be some registers left over for the caller to
8457 handle. Destructively modify *MASK_PTR so that it contains the registers
8458 that still need to be saved or restored. The caller can save these
8459 registers in the memory immediately below *OFFSET_PTR, which is a
8460 byte offset from the bottom of the allocated stack area. */
8463 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8464 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8468 HOST_WIDE_INT offset, top_offset;
8469 unsigned int i, regno;
8472 gcc_assert (cfun->machine->frame.num_fp == 0);
8474 /* Calculate the number of elements in the PARALLEL. We need one element
8475 for the stack adjustment, one for each argument register save, and one
8476 for each additional register move. */
8478 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8479 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8482 /* Create the final PARALLEL. */
8483 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8486 /* Add the stack pointer adjustment. */
8487 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8488 plus_constant (stack_pointer_rtx,
8489 restore_p ? size : -size));
8490 RTX_FRAME_RELATED_P (set) = 1;
8491 XVECEXP (pattern, 0, n++) = set;
8493 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8494 top_offset = restore_p ? size : 0;
8496 /* Save the arguments. */
8497 for (i = 0; i < nargs; i++)
8499 offset = top_offset + i * UNITS_PER_WORD;
8500 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8501 XVECEXP (pattern, 0, n++) = set;
8504 /* Then fill in the other register moves. */
8505 offset = top_offset;
8506 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8508 regno = mips16e_save_restore_regs[i];
8509 if (BITSET_P (*mask_ptr, regno))
8511 offset -= UNITS_PER_WORD;
8512 set = mips16e_save_restore_reg (restore_p, offset, regno);
8513 XVECEXP (pattern, 0, n++) = set;
8514 *mask_ptr &= ~(1 << regno);
8518 /* Tell the caller what offset it should use for the remaining registers. */
8519 *offset_ptr = size + (offset - top_offset);
8521 gcc_assert (n == XVECLEN (pattern, 0));
8526 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8527 pointer. Return true if PATTERN matches the kind of instruction
8528 generated by mips16e_build_save_restore. If INFO is nonnull,
8529 initialize it when returning true. */
8532 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8533 struct mips16e_save_restore_info *info)
8535 unsigned int i, nargs, mask, extra;
8536 HOST_WIDE_INT top_offset, save_offset, offset;
8537 rtx set, reg, mem, base;
8540 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8543 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8544 top_offset = adjust > 0 ? adjust : 0;
8546 /* Interpret all other members of the PARALLEL. */
8547 save_offset = top_offset - UNITS_PER_WORD;
8551 for (n = 1; n < XVECLEN (pattern, 0); n++)
8553 /* Check that we have a SET. */
8554 set = XVECEXP (pattern, 0, n);
8555 if (GET_CODE (set) != SET)
8558 /* Check that the SET is a load (if restoring) or a store
8560 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8564 /* Check that the address is the sum of the stack pointer and a
8565 possibly-zero constant offset. */
8566 mips_split_plus (XEXP (mem, 0), &base, &offset);
8567 if (base != stack_pointer_rtx)
8570 /* Check that SET's other operand is a register. */
8571 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8575 /* Check for argument saves. */
8576 if (offset == top_offset + nargs * UNITS_PER_WORD
8577 && REGNO (reg) == GP_ARG_FIRST + nargs)
8579 else if (offset == save_offset)
8581 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8582 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8585 mask |= 1 << REGNO (reg);
8586 save_offset -= UNITS_PER_WORD;
8592 /* Check that the restrictions on register ranges are met. */
8594 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8595 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8596 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8597 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8601 /* Make sure that the topmost argument register is not saved twice.
8602 The checks above ensure that the same is then true for the other
8603 argument registers. */
8604 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8607 /* Pass back information, if requested. */
8610 info->nargs = nargs;
8612 info->size = (adjust > 0 ? adjust : -adjust);
8618 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8619 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8620 the null terminator. */
8623 mips16e_add_register_range (char *s, unsigned int min_reg,
8624 unsigned int max_reg)
8626 if (min_reg != max_reg)
8627 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8629 s += sprintf (s, ",%s", reg_names[min_reg]);
8633 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8634 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8637 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8639 static char buffer[300];
8641 struct mips16e_save_restore_info info;
8642 unsigned int i, end;
8645 /* Parse the pattern. */
8646 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8649 /* Add the mnemonic. */
8650 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8653 /* Save the arguments. */
8655 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8656 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8657 else if (info.nargs == 1)
8658 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8660 /* Emit the amount of stack space to allocate or deallocate. */
8661 s += sprintf (s, "%d", (int) info.size);
8663 /* Save or restore $16. */
8664 if (BITSET_P (info.mask, 16))
8665 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8667 /* Save or restore $17. */
8668 if (BITSET_P (info.mask, 17))
8669 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8671 /* Save or restore registers in the range $s2...$s8, which
8672 mips16e_s2_s8_regs lists in decreasing order. Note that this
8673 is a software register range; the hardware registers are not
8674 numbered consecutively. */
8675 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8676 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8678 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8679 mips16e_s2_s8_regs[i]);
8681 /* Save or restore registers in the range $a0...$a3. */
8682 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8683 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8685 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8686 mips16e_a0_a3_regs[end - 1]);
8688 /* Save or restore $31. */
8689 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8690 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8695 /* Return true if the current function returns its value in a floating-point
8696 register in MIPS16 mode. */
8699 mips16_cfun_returns_in_fpr_p (void)
8701 tree return_type = DECL_RESULT (current_function_decl);
8702 return (TARGET_MIPS16
8703 && TARGET_HARD_FLOAT_ABI
8704 && !aggregate_value_p (return_type, current_function_decl)
8705 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8708 /* Return true if predicate PRED is true for at least one instruction.
8709 Cache the result in *CACHE, and assume that the result is true
8710 if *CACHE is already true. */
8713 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8719 push_topmost_sequence ();
8720 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8721 if (USEFUL_INSN_P (insn) && pred (insn))
8726 pop_topmost_sequence ();
8731 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8732 See mips_cfun_has_inflexible_gp_ref_p for details. */
8735 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8737 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8738 indicate that the target could be a traditional MIPS
8739 lazily-binding stub. */
8740 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8743 /* Return true if the current function refers to the global pointer
8744 in a way that forces $28 to be valid. This means that we can't
8745 change the choice of global pointer, even for NewABI code.
8747 One example of this (and one which needs several checks) is that
8748 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8749 (This restriction does not apply to PLTs.) */
8752 mips_cfun_has_inflexible_gp_ref_p (void)
8754 /* If the function has a nonlocal goto, $28 must hold the correct
8755 global pointer for the target function. That is, the target
8756 of the goto implicitly uses $28. */
8757 if (crtl->has_nonlocal_goto)
8760 if (TARGET_ABICALLS_PIC2)
8762 /* Symbolic accesses implicitly use the global pointer unless
8763 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8764 might go to traditional MIPS lazy-binding stubs. */
8765 if (!TARGET_EXPLICIT_RELOCS)
8768 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8769 can be lazily-bound. */
8773 /* MIPS16 functions that return in FPRs need to call an
8774 external libgcc routine. This call is only made explict
8775 during mips_expand_epilogue, and it too might be lazily bound. */
8776 if (mips16_cfun_returns_in_fpr_p ())
8780 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8781 mips_insn_has_inflexible_gp_ref_p);
8784 /* Return true if INSN refers to the global pointer in a "flexible" way.
8785 See mips_cfun_has_flexible_gp_ref_p for details. */
8788 mips_insn_has_flexible_gp_ref_p (rtx insn)
8790 return (get_attr_got (insn) != GOT_UNSET
8791 || mips_small_data_pattern_p (PATTERN (insn))
8792 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8795 /* Return true if the current function references the global pointer,
8796 but if those references do not inherently require the global pointer
8797 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8800 mips_cfun_has_flexible_gp_ref_p (void)
8802 /* Reload can sometimes introduce constant pool references
8803 into a function that otherwise didn't need them. For example,
8804 suppose we have an instruction like:
8806 (set (reg:DF R1) (float:DF (reg:SI R2)))
8808 If R2 turns out to be a constant such as 1, the instruction may
8809 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8810 the option of using this constant if R2 doesn't get allocated
8813 In cases like these, reload will have added the constant to the
8814 pool but no instruction will yet refer to it. */
8815 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8818 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8819 mips_insn_has_flexible_gp_ref_p);
8822 /* Return the register that should be used as the global pointer
8823 within this function. Return INVALID_REGNUM if the function
8824 doesn't need a global pointer. */
8827 mips_global_pointer (void)
8831 /* $gp is always available unless we're using a GOT. */
8832 if (!TARGET_USE_GOT)
8833 return GLOBAL_POINTER_REGNUM;
8835 /* If there are inflexible references to $gp, we must use the
8836 standard register. */
8837 if (mips_cfun_has_inflexible_gp_ref_p ())
8838 return GLOBAL_POINTER_REGNUM;
8840 /* If there are no current references to $gp, then the only uses
8841 we can introduce later are those involved in long branches. */
8842 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8843 return INVALID_REGNUM;
8845 /* If the global pointer is call-saved, try to use a call-clobbered
8847 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8848 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8849 if (!df_regs_ever_live_p (regno)
8850 && call_really_used_regs[regno]
8851 && !fixed_regs[regno]
8852 && regno != PIC_FUNCTION_ADDR_REGNUM)
8855 return GLOBAL_POINTER_REGNUM;
8858 /* Return true if the current function's prologue must load the global
8859 pointer value into pic_offset_table_rtx and store the same value in
8860 the function's cprestore slot (if any).
8862 One problem we have to deal with is that, when emitting GOT-based
8863 position independent code, long-branch sequences will need to load
8864 the address of the branch target from the GOT. We don't know until
8865 the very end of compilation whether (and where) the function needs
8866 long branches, so we must ensure that _any_ branch can access the
8867 global pointer in some form. However, we do not want to pessimize
8868 the usual case in which all branches are short.
8870 We handle this as follows:
8872 (1) During reload, we set cfun->machine->global_pointer to
8873 INVALID_REGNUM if we _know_ that the current function
8874 doesn't need a global pointer. This is only valid if
8875 long branches don't need the GOT.
8877 Otherwise, we assume that we might need a global pointer
8878 and pick an appropriate register.
8880 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8881 we ensure that the global pointer is available at every
8882 block boundary bar entry and exit. We do this in one of two ways:
8884 - If the function has a cprestore slot, we ensure that this
8885 slot is valid at every branch. However, as explained in
8886 point (6) below, there is no guarantee that pic_offset_table_rtx
8887 itself is valid if new uses of the global pointer are introduced
8888 after the first post-epilogue split.
8890 We guarantee that the cprestore slot is valid by loading it
8891 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8892 this register live at every block boundary bar function entry
8893 and exit. It is then invalid to move the load (and thus the
8894 preceding store) across a block boundary.
8896 - If the function has no cprestore slot, we guarantee that
8897 pic_offset_table_rtx itself is valid at every branch.
8899 See mips_eh_uses for the handling of the register liveness.
8901 (3) During prologue and epilogue generation, we emit "ghost"
8902 placeholder instructions to manipulate the global pointer.
8904 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8905 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8906 that the function needs a global pointer. (There is no need to set
8907 them earlier than this, and doing it as late as possible leads to
8908 fewer false positives.)
8910 (5) If cfun->machine->must_initialize_gp_p is true during a
8911 split_insns pass, we split the ghost instructions into real
8912 instructions. These split instructions can then be optimized in
8913 the usual way. Otherwise, we keep the ghost instructions intact,
8914 and optimize for the case where they aren't needed. We still
8915 have the option of splitting them later, if we need to introduce
8916 new uses of the global pointer.
8918 For example, the scheduler ignores a ghost instruction that
8919 stores $28 to the stack, but it handles the split form of
8920 the ghost instruction as an ordinary store.
8922 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8923 is true during the first post-epilogue split_insns pass, we split
8924 calls and restore_gp patterns into instructions that explicitly
8925 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8926 we split these patterns into instructions that _don't_ load from
8929 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8930 time of the split, then any instructions that exist at that time
8931 can make free use of pic_offset_table_rtx. However, if we want
8932 to introduce new uses of the global pointer after the split,
8933 we must explicitly load the value from the cprestore slot, since
8934 pic_offset_table_rtx itself might not be valid at a given point
8937 The idea is that we want to be able to delete redundant
8938 loads from the cprestore slot in the usual case where no
8939 long branches are needed.
8941 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8942 of md_reorg, we decide whether the global pointer is needed for
8943 long branches. If so, we set cfun->machine->must_initialize_gp_p
8944 to true and split the ghost instructions into real instructions
8947 Note that the ghost instructions must have a zero length for three reasons:
8949 - Giving the length of the underlying $gp sequence might cause
8950 us to use long branches in cases where they aren't really needed.
8952 - They would perturb things like alignment calculations.
8954 - More importantly, the hazard detection in md_reorg relies on
8955 empty instructions having a zero length.
8957 If we find a long branch and split the ghost instructions at the
8958 end of md_reorg, the split could introduce more long branches.
8959 That isn't a problem though, because we still do the split before
8960 the final shorten_branches pass.
8962 This is extremely ugly, but it seems like the best compromise between
8963 correctness and efficiency. */
8966 mips_must_initialize_gp_p (void)
8968 return cfun->machine->must_initialize_gp_p;
8971 /* Return true if REGNO is a register that is ordinarily call-clobbered
8972 but must nevertheless be preserved by an interrupt handler. */
8975 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8977 if (MD_REG_P (regno))
8980 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8983 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8985 /* $0 is hard-wired. */
8986 if (regno == GP_REG_FIRST)
8989 /* The interrupt handler can treat kernel registers as
8990 scratch registers. */
8991 if (KERNEL_REG_P (regno))
8994 /* The function will return the stack pointer to its original value
8996 if (regno == STACK_POINTER_REGNUM)
8999 /* Otherwise, return true for registers that aren't ordinarily
9001 return call_really_used_regs[regno];
9007 /* Return true if the current function should treat register REGNO
9011 mips_cfun_call_saved_reg_p (unsigned int regno)
9013 /* Interrupt handlers need to save extra registers. */
9014 if (cfun->machine->interrupt_handler_p
9015 && mips_interrupt_extra_call_saved_reg_p (regno))
9018 /* call_insns preserve $28 unless they explicitly say otherwise,
9019 so call_really_used_regs[] treats $28 as call-saved. However,
9020 we want the ABI property rather than the default call_insn
9022 return (regno == GLOBAL_POINTER_REGNUM
9023 ? TARGET_CALL_SAVED_GP
9024 : !call_really_used_regs[regno]);
9027 /* Return true if the function body might clobber register REGNO.
9028 We know that REGNO is call-saved. */
9031 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9033 /* Some functions should be treated as clobbering all call-saved
9035 if (crtl->saves_all_registers)
9038 /* DF handles cases where a register is explicitly referenced in
9039 the rtl. Incoming values are passed in call-clobbered registers,
9040 so we can assume that any live call-saved register is set within
9042 if (df_regs_ever_live_p (regno))
9045 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9046 These clobbers are not explicit in the rtl. */
9047 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9050 /* If we're using a call-saved global pointer, the function's
9051 prologue will need to set it up. */
9052 if (cfun->machine->global_pointer == regno)
9055 /* The function's prologue will need to set the frame pointer if
9056 frame_pointer_needed. */
9057 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9060 /* If a MIPS16 function returns a value in FPRs, its epilogue
9061 will need to call an external libgcc routine. This yet-to-be
9062 generated call_insn will clobber $31. */
9063 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9066 /* If REGNO is ordinarily call-clobbered, we must assume that any
9067 called function could modify it. */
9068 if (cfun->machine->interrupt_handler_p
9069 && !current_function_is_leaf
9070 && mips_interrupt_extra_call_saved_reg_p (regno))
9076 /* Return true if the current function must save register REGNO. */
9079 mips_save_reg_p (unsigned int regno)
9081 if (mips_cfun_call_saved_reg_p (regno))
9083 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9086 /* Save both registers in an FPR pair if either one is used. This is
9087 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9088 register to be used without the even register. */
9089 if (FP_REG_P (regno)
9090 && MAX_FPRS_PER_FMT == 2
9091 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9095 /* We need to save the incoming return address if __builtin_eh_return
9096 is being used to set a different return address. */
9097 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9103 /* Populate the current function's mips_frame_info structure.
9105 MIPS stack frames look like:
9107 +-------------------------------+
9109 | incoming stack arguments |
9111 +-------------------------------+
9113 | caller-allocated save area |
9114 A | for register arguments |
9116 +-------------------------------+ <-- incoming stack pointer
9118 | callee-allocated save area |
9119 B | for arguments that are |
9120 | split between registers and |
9123 +-------------------------------+ <-- arg_pointer_rtx
9125 C | callee-allocated save area |
9126 | for register varargs |
9128 +-------------------------------+ <-- frame_pointer_rtx
9129 | | + cop0_sp_offset
9130 | COP0 reg save area | + UNITS_PER_WORD
9132 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9133 | | + UNITS_PER_WORD
9134 | accumulator save area |
9136 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9137 | | + UNITS_PER_HWFPVALUE
9140 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9141 | | + UNITS_PER_WORD
9144 +-------------------------------+ <-- frame_pointer_rtx with
9145 | | \ -fstack-protector
9146 | local variables | | var_size
9148 +-------------------------------+
9150 | $gp save area | | cprestore_size
9152 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9154 | outgoing stack arguments | |
9156 +-------------------------------+ | args_size
9158 | caller-allocated save area | |
9159 | for register arguments | |
9161 +-------------------------------+ <-- stack_pointer_rtx
9162 frame_pointer_rtx without
9164 hard_frame_pointer_rtx for
9167 At least two of A, B and C will be empty.
9169 Dynamic stack allocations such as alloca insert data at point P.
9170 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9171 hard_frame_pointer_rtx unchanged. */
9174 mips_compute_frame_info (void)
9176 struct mips_frame_info *frame;
9177 HOST_WIDE_INT offset, size;
9178 unsigned int regno, i;
9180 /* Set this function's interrupt properties. */
9181 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9184 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9185 else if (TARGET_HARD_FLOAT)
9186 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9187 else if (TARGET_MIPS16)
9188 error ("interrupt handlers cannot be MIPS16 functions");
9191 cfun->machine->interrupt_handler_p = true;
9192 cfun->machine->use_shadow_register_set_p =
9193 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9194 cfun->machine->keep_interrupts_masked_p =
9195 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9196 cfun->machine->use_debug_exception_return_p =
9197 mips_use_debug_exception_return_p (TREE_TYPE
9198 (current_function_decl));
9202 frame = &cfun->machine->frame;
9203 memset (frame, 0, sizeof (*frame));
9204 size = get_frame_size ();
9206 cfun->machine->global_pointer = mips_global_pointer ();
9208 /* The first two blocks contain the outgoing argument area and the $gp save
9209 slot. This area isn't needed in leaf functions, but if the
9210 target-independent frame size is nonzero, we have already committed to
9211 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9212 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9214 /* The MIPS 3.0 linker does not like functions that dynamically
9215 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9216 looks like we are trying to create a second frame pointer to the
9217 function, so allocate some stack space to make it happy. */
9218 if (cfun->calls_alloca)
9219 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9221 frame->args_size = 0;
9222 frame->cprestore_size = 0;
9226 frame->args_size = crtl->outgoing_args_size;
9227 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9229 offset = frame->args_size + frame->cprestore_size;
9231 /* Move above the local variables. */
9232 frame->var_size = MIPS_STACK_ALIGN (size);
9233 offset += frame->var_size;
9235 /* Find out which GPRs we need to save. */
9236 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9237 if (mips_save_reg_p (regno))
9240 frame->mask |= 1 << (regno - GP_REG_FIRST);
9243 /* If this function calls eh_return, we must also save and restore the
9244 EH data registers. */
9245 if (crtl->calls_eh_return)
9246 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9249 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9252 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9253 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9254 save all later registers too. */
9255 if (GENERATE_MIPS16E_SAVE_RESTORE)
9257 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9258 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9259 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9260 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9263 /* Move above the GPR save area. */
9264 if (frame->num_gp > 0)
9266 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9267 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9270 /* Find out which FPRs we need to save. This loop must iterate over
9271 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9272 if (TARGET_HARD_FLOAT)
9273 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9274 if (mips_save_reg_p (regno))
9276 frame->num_fp += MAX_FPRS_PER_FMT;
9277 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9280 /* Move above the FPR save area. */
9281 if (frame->num_fp > 0)
9283 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9284 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9287 /* Add in space for the interrupt context information. */
9288 if (cfun->machine->interrupt_handler_p)
9291 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9294 frame->acc_mask |= (1 << 0);
9297 /* Check accumulators 1, 2, 3. */
9298 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9299 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9302 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9305 /* All interrupt context functions need space to preserve STATUS. */
9306 frame->num_cop0_regs++;
9308 /* If we don't keep interrupts masked, we need to save EPC. */
9309 if (!cfun->machine->keep_interrupts_masked_p)
9310 frame->num_cop0_regs++;
9313 /* Move above the accumulator save area. */
9314 if (frame->num_acc > 0)
9316 /* Each accumulator needs 2 words. */
9317 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9318 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9321 /* Move above the COP0 register save area. */
9322 if (frame->num_cop0_regs > 0)
9324 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9325 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9328 /* Move above the callee-allocated varargs save area. */
9329 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9330 frame->arg_pointer_offset = offset;
9332 /* Move above the callee-allocated area for pretend stack arguments. */
9333 offset += crtl->args.pretend_args_size;
9334 frame->total_size = offset;
9336 /* Work out the offsets of the save areas from the top of the frame. */
9337 if (frame->gp_sp_offset > 0)
9338 frame->gp_save_offset = frame->gp_sp_offset - offset;
9339 if (frame->fp_sp_offset > 0)
9340 frame->fp_save_offset = frame->fp_sp_offset - offset;
9341 if (frame->acc_sp_offset > 0)
9342 frame->acc_save_offset = frame->acc_sp_offset - offset;
9343 if (frame->num_cop0_regs > 0)
9344 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9346 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9347 arguments. This tends to increase the chances of using unextended
9348 instructions for local variables and incoming arguments. */
9350 frame->hard_frame_pointer_offset = frame->args_size;
9353 /* Return the style of GP load sequence that is being used for the
9354 current function. */
9356 enum mips_loadgp_style
9357 mips_current_loadgp_style (void)
9359 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9365 if (TARGET_ABSOLUTE_ABICALLS)
9366 return LOADGP_ABSOLUTE;
9368 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9371 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9374 mips_frame_pointer_required (void)
9376 /* If the function contains dynamic stack allocations, we need to
9377 use the frame pointer to access the static parts of the frame. */
9378 if (cfun->calls_alloca)
9381 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9382 reload may be unable to compute the address of a local variable,
9383 since there is no way to add a large constant to the stack pointer
9384 without using a second temporary register. */
9387 mips_compute_frame_info ();
9388 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9395 /* Make sure that we're not trying to eliminate to the wrong hard frame
9399 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9401 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9404 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9405 or argument pointer. TO is either the stack pointer or hard frame
9409 mips_initial_elimination_offset (int from, int to)
9411 HOST_WIDE_INT offset;
9413 mips_compute_frame_info ();
9415 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9418 case FRAME_POINTER_REGNUM:
9419 if (FRAME_GROWS_DOWNWARD)
9420 offset = (cfun->machine->frame.args_size
9421 + cfun->machine->frame.cprestore_size
9422 + cfun->machine->frame.var_size);
9427 case ARG_POINTER_REGNUM:
9428 offset = cfun->machine->frame.arg_pointer_offset;
9435 if (to == HARD_FRAME_POINTER_REGNUM)
9436 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9441 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9444 mips_extra_live_on_entry (bitmap regs)
9448 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9449 the global pointer. */
9450 if (!TARGET_ABSOLUTE_ABICALLS)
9451 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9453 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9454 the global pointer. */
9456 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9458 /* See the comment above load_call<mode> for details. */
9459 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9463 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9467 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9472 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9475 /* Emit code to change the current function's return address to
9476 ADDRESS. SCRATCH is available as a scratch register, if needed.
9477 ADDRESS and SCRATCH are both word-mode GPRs. */
9480 mips_set_return_address (rtx address, rtx scratch)
9484 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9485 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9486 cfun->machine->frame.gp_sp_offset);
9487 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9490 /* Return true if the current function has a cprestore slot. */
9493 mips_cfun_has_cprestore_slot_p (void)
9495 return (cfun->machine->global_pointer != INVALID_REGNUM
9496 && cfun->machine->frame.cprestore_size > 0);
9499 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9500 cprestore slot. LOAD_P is true if the caller wants to load from
9501 the cprestore slot; it is false if the caller wants to store to
9505 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9508 const struct mips_frame_info *frame;
9510 frame = &cfun->machine->frame;
9511 /* .cprestore always uses the stack pointer instead of the frame pointer.
9512 We have a free choice for direct stores for non-MIPS16 functions,
9513 and for MIPS16 functions whose cprestore slot is in range of the
9514 stack pointer. Using the stack pointer would sometimes give more
9515 (early) scheduling freedom, but using the frame pointer would
9516 sometimes give more (late) scheduling freedom. It's hard to
9517 predict which applies to a given function, so let's keep things
9520 Loads must always use the frame pointer in functions that call
9521 alloca, and there's little benefit to using the stack pointer
9523 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9525 *base = hard_frame_pointer_rtx;
9526 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9530 *base = stack_pointer_rtx;
9531 *offset = frame->args_size;
9535 /* Return true if X is the load or store address of the cprestore slot;
9536 LOAD_P says which. */
9539 mips_cprestore_address_p (rtx x, bool load_p)
9541 rtx given_base, required_base;
9542 HOST_WIDE_INT given_offset, required_offset;
9544 mips_split_plus (x, &given_base, &given_offset);
9545 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9546 return given_base == required_base && given_offset == required_offset;
9549 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9550 going to load from it, false if we are going to store to it.
9551 Use TEMP as a temporary register if need be. */
9554 mips_cprestore_slot (rtx temp, bool load_p)
9557 HOST_WIDE_INT offset;
9559 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9560 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9563 /* Emit instructions to save global pointer value GP into cprestore
9564 slot MEM. OFFSET is the offset that MEM applies to the base register.
9566 MEM may not be a legitimate address. If it isn't, TEMP is a
9567 temporary register that can be used, otherwise it is a SCRATCH. */
9570 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9572 if (TARGET_CPRESTORE_DIRECTIVE)
9574 gcc_assert (gp == pic_offset_table_rtx);
9575 emit_insn (gen_cprestore (mem, offset));
9578 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9581 /* Restore $gp from its save slot, using TEMP as a temporary base register
9582 if need be. This function is for o32 and o64 abicalls only.
9584 See mips_must_initialize_gp_p for details about how we manage the
9588 mips_restore_gp_from_cprestore_slot (rtx temp)
9590 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9592 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9594 emit_note (NOTE_INSN_DELETED);
9600 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9601 mips_emit_move (pic_offset_table_rtx, temp);
9604 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9605 if (!TARGET_EXPLICIT_RELOCS)
9606 emit_insn (gen_blockage ());
9609 /* A function to save or store a register. The first argument is the
9610 register and the second is the stack slot. */
9611 typedef void (*mips_save_restore_fn) (rtx, rtx);
9613 /* Use FN to save or restore register REGNO. MODE is the register's
9614 mode and OFFSET is the offset of its save slot from the current
9618 mips_save_restore_reg (enum machine_mode mode, int regno,
9619 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9623 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9624 fn (gen_rtx_REG (mode, regno), mem);
9627 /* Call FN for each accumlator that is saved by the current function.
9628 SP_OFFSET is the offset of the current stack pointer from the start
9632 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9634 HOST_WIDE_INT offset;
9637 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9638 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9640 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9641 offset -= UNITS_PER_WORD;
9642 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9643 offset -= UNITS_PER_WORD;
9646 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9647 if (BITSET_P (cfun->machine->frame.acc_mask,
9648 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9650 mips_save_restore_reg (word_mode, regno, offset, fn);
9651 offset -= UNITS_PER_WORD;
9655 /* Call FN for each register that is saved by the current function.
9656 SP_OFFSET is the offset of the current stack pointer from the start
9660 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9661 mips_save_restore_fn fn)
9663 enum machine_mode fpr_mode;
9664 HOST_WIDE_INT offset;
9667 /* Save registers starting from high to low. The debuggers prefer at least
9668 the return register be stored at func+4, and also it allows us not to
9669 need a nop in the epilogue if at least one register is reloaded in
9670 addition to return address. */
9671 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9672 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9673 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9675 /* Record the ra offset for use by mips_function_profiler. */
9676 if (regno == RETURN_ADDR_REGNUM)
9677 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
9678 mips_save_restore_reg (word_mode, regno, offset, fn);
9679 offset -= UNITS_PER_WORD;
9682 /* This loop must iterate over the same space as its companion in
9683 mips_compute_frame_info. */
9684 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9685 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9686 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9687 regno >= FP_REG_FIRST;
9688 regno -= MAX_FPRS_PER_FMT)
9689 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9691 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9692 offset -= GET_MODE_SIZE (fpr_mode);
9696 /* Return true if a move between register REGNO and its save slot (MEM)
9697 can be done in a single move. LOAD_P is true if we are loading
9698 from the slot, false if we are storing to it. */
9701 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9703 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9704 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9707 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9708 GET_MODE (mem), mem, load_p) == NO_REGS;
9711 /* Emit a move from SRC to DEST, given that one of them is a register
9712 save slot and that the other is a register. TEMP is a temporary
9713 GPR of the same mode that is available if need be. */
9716 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9723 regno = REGNO (src);
9728 regno = REGNO (dest);
9732 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9734 /* We don't yet know whether we'll need this instruction or not.
9735 Postpone the decision by emitting a ghost move. This move
9736 is specifically not frame-related; only the split version is. */
9738 emit_insn (gen_move_gpdi (dest, src));
9740 emit_insn (gen_move_gpsi (dest, src));
9744 if (regno == HI_REGNUM)
9748 mips_emit_move (temp, src);
9750 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9751 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9753 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9754 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9759 emit_insn (gen_mfhidi_ti (temp,
9760 gen_rtx_REG (TImode, MD_REG_FIRST)));
9762 emit_insn (gen_mfhisi_di (temp,
9763 gen_rtx_REG (DImode, MD_REG_FIRST)));
9764 mips_emit_move (dest, temp);
9767 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9768 mips_emit_move (dest, src);
9771 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9772 mips_emit_move (temp, src);
9773 mips_emit_move (dest, temp);
9776 mips_set_frame_expr (mips_frame_set (dest, src));
9779 /* If we're generating n32 or n64 abicalls, and the current function
9780 does not use $28 as its global pointer, emit a cplocal directive.
9781 Use pic_offset_table_rtx as the argument to the directive. */
9784 mips_output_cplocal (void)
9786 if (!TARGET_EXPLICIT_RELOCS
9787 && mips_must_initialize_gp_p ()
9788 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9789 output_asm_insn (".cplocal %+", 0);
9792 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9795 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9799 #ifdef SDB_DEBUGGING_INFO
9800 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9801 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9804 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9805 floating-point arguments. */
9807 && TARGET_HARD_FLOAT_ABI
9808 && crtl->args.info.fp_code != 0)
9809 mips16_build_function_stub ();
9811 /* Get the function name the same way that toplev.c does before calling
9812 assemble_start_function. This is needed so that the name used here
9813 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9814 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9815 mips_start_function_definition (fnname, TARGET_MIPS16);
9817 /* Output MIPS-specific frame information. */
9818 if (!flag_inhibit_size_directive)
9820 const struct mips_frame_info *frame;
9822 frame = &cfun->machine->frame;
9824 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9826 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9827 "# vars= " HOST_WIDE_INT_PRINT_DEC
9829 ", args= " HOST_WIDE_INT_PRINT_DEC
9830 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9831 reg_names[frame_pointer_needed
9832 ? HARD_FRAME_POINTER_REGNUM
9833 : STACK_POINTER_REGNUM],
9834 (frame_pointer_needed
9835 ? frame->total_size - frame->hard_frame_pointer_offset
9836 : frame->total_size),
9837 reg_names[RETURN_ADDR_REGNUM],
9839 frame->num_gp, frame->num_fp,
9841 frame->cprestore_size);
9843 /* .mask MASK, OFFSET. */
9844 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9845 frame->mask, frame->gp_save_offset);
9847 /* .fmask MASK, OFFSET. */
9848 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9849 frame->fmask, frame->fp_save_offset);
9852 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9853 Also emit the ".set noreorder; .set nomacro" sequence for functions
9855 if (mips_must_initialize_gp_p ()
9856 && mips_current_loadgp_style () == LOADGP_OLDABI)
9860 /* This is a fixed-form sequence. The position of the
9861 first two instructions is important because of the
9862 way _gp_disp is defined. */
9863 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9864 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9865 output_asm_insn ("sll\t$2,16", 0);
9866 output_asm_insn ("addu\t$2,$3", 0);
9870 /* .cpload must be in a .set noreorder but not a
9871 .set nomacro block. */
9872 mips_push_asm_switch (&mips_noreorder);
9873 output_asm_insn (".cpload\t%^", 0);
9874 if (!cfun->machine->all_noreorder_p)
9875 mips_pop_asm_switch (&mips_noreorder);
9877 mips_push_asm_switch (&mips_nomacro);
9880 else if (cfun->machine->all_noreorder_p)
9882 mips_push_asm_switch (&mips_noreorder);
9883 mips_push_asm_switch (&mips_nomacro);
9886 /* Tell the assembler which register we're using as the global
9887 pointer. This is needed for thunks, since they can use either
9888 explicit relocs or assembler macros. */
9889 mips_output_cplocal ();
9892 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9895 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9896 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9900 /* Reinstate the normal $gp. */
9901 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9902 mips_output_cplocal ();
9904 if (cfun->machine->all_noreorder_p)
9906 mips_pop_asm_switch (&mips_nomacro);
9907 mips_pop_asm_switch (&mips_noreorder);
9910 /* Get the function name the same way that toplev.c does before calling
9911 assemble_start_function. This is needed so that the name used here
9912 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9913 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9914 mips_end_function_definition (fnname);
9917 /* Save register REG to MEM. Make the instruction frame-related. */
9920 mips_save_reg (rtx reg, rtx mem)
9922 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9926 if (mips_split_64bit_move_p (mem, reg))
9927 mips_split_doubleword_move (mem, reg);
9929 mips_emit_move (mem, reg);
9931 x1 = mips_frame_set (mips_subword (mem, false),
9932 mips_subword (reg, false));
9933 x2 = mips_frame_set (mips_subword (mem, true),
9934 mips_subword (reg, true));
9935 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9938 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9941 /* The __gnu_local_gp symbol. */
9943 static GTY(()) rtx mips_gnu_local_gp;
9945 /* If we're generating n32 or n64 abicalls, emit instructions
9946 to set up the global pointer. */
9949 mips_emit_loadgp (void)
9951 rtx addr, offset, incoming_address, base, index, pic_reg;
9953 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9954 switch (mips_current_loadgp_style ())
9956 case LOADGP_ABSOLUTE:
9957 if (mips_gnu_local_gp == NULL)
9959 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9960 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9962 emit_insn (Pmode == SImode
9963 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9964 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9968 /* Added by mips_output_function_prologue. */
9972 addr = XEXP (DECL_RTL (current_function_decl), 0);
9973 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9974 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9975 emit_insn (Pmode == SImode
9976 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9977 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9981 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9982 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9983 emit_insn (Pmode == SImode
9984 ? gen_loadgp_rtp_si (pic_reg, base, index)
9985 : gen_loadgp_rtp_di (pic_reg, base, index));
9993 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9995 /* Emit a blockage if there are implicit uses of the GP register.
9996 This includes profiled functions, because FUNCTION_PROFILE uses
9998 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9999 emit_insn (gen_loadgp_blockage ());
10002 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10005 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10007 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10010 /* Expand the "prologue" pattern. */
10013 mips_expand_prologue (void)
10015 const struct mips_frame_info *frame;
10016 HOST_WIDE_INT size;
10017 unsigned int nargs;
10020 if (cfun->machine->global_pointer != INVALID_REGNUM)
10022 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10023 or implicitly. If so, we can commit to using a global pointer
10024 straight away, otherwise we need to defer the decision. */
10025 if (mips_cfun_has_inflexible_gp_ref_p ()
10026 || mips_cfun_has_flexible_gp_ref_p ())
10028 cfun->machine->must_initialize_gp_p = true;
10029 cfun->machine->must_restore_gp_when_clobbered_p = true;
10032 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10035 frame = &cfun->machine->frame;
10036 size = frame->total_size;
10038 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10039 bytes beforehand; this is enough to cover the register save area
10040 without going out of range. */
10041 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10042 || frame->num_cop0_regs > 0)
10044 HOST_WIDE_INT step1;
10046 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10047 if (GENERATE_MIPS16E_SAVE_RESTORE)
10049 HOST_WIDE_INT offset;
10050 unsigned int mask, regno;
10052 /* Try to merge argument stores into the save instruction. */
10053 nargs = mips16e_collect_argument_saves ();
10055 /* Build the save instruction. */
10056 mask = frame->mask;
10057 insn = mips16e_build_save_restore (false, &mask, &offset,
10059 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10062 /* Check if we need to save other registers. */
10063 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10064 if (BITSET_P (mask, regno - GP_REG_FIRST))
10066 offset -= UNITS_PER_WORD;
10067 mips_save_restore_reg (word_mode, regno,
10068 offset, mips_save_reg);
10073 if (cfun->machine->interrupt_handler_p)
10075 HOST_WIDE_INT offset;
10078 /* If this interrupt is using a shadow register set, we need to
10079 get the stack pointer from the previous register set. */
10080 if (cfun->machine->use_shadow_register_set_p)
10081 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10082 stack_pointer_rtx));
10084 if (!cfun->machine->keep_interrupts_masked_p)
10086 /* Move from COP0 Cause to K0. */
10087 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10088 gen_rtx_REG (SImode,
10089 COP0_CAUSE_REG_NUM)));
10090 /* Move from COP0 EPC to K1. */
10091 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10092 gen_rtx_REG (SImode,
10093 COP0_EPC_REG_NUM)));
10096 /* Allocate the first part of the frame. */
10097 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10099 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10102 /* Start at the uppermost location for saving. */
10103 offset = frame->cop0_sp_offset - size;
10104 if (!cfun->machine->keep_interrupts_masked_p)
10106 /* Push EPC into its stack slot. */
10107 mem = gen_frame_mem (word_mode,
10108 plus_constant (stack_pointer_rtx,
10110 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10111 offset -= UNITS_PER_WORD;
10114 /* Move from COP0 Status to K1. */
10115 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10116 gen_rtx_REG (SImode,
10117 COP0_STATUS_REG_NUM)));
10119 /* Right justify the RIPL in k0. */
10120 if (!cfun->machine->keep_interrupts_masked_p)
10121 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10122 gen_rtx_REG (SImode, K0_REG_NUM),
10123 GEN_INT (CAUSE_IPL)));
10125 /* Push Status into its stack slot. */
10126 mem = gen_frame_mem (word_mode,
10127 plus_constant (stack_pointer_rtx, offset));
10128 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10129 offset -= UNITS_PER_WORD;
10131 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10132 if (!cfun->machine->keep_interrupts_masked_p)
10133 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10136 gen_rtx_REG (SImode, K0_REG_NUM)));
10138 if (!cfun->machine->keep_interrupts_masked_p)
10139 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10140 IE is already the correct value, so we don't have to do
10141 anything explicit. */
10142 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10145 gen_rtx_REG (SImode, GP_REG_FIRST)));
10147 /* Disable interrupts by clearing the KSU, ERL, EXL,
10149 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10152 gen_rtx_REG (SImode, GP_REG_FIRST)));
10156 insn = gen_add3_insn (stack_pointer_rtx,
10159 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10162 mips_for_each_saved_acc (size, mips_save_reg);
10163 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10167 /* Allocate the rest of the frame. */
10170 if (SMALL_OPERAND (-size))
10171 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10173 GEN_INT (-size)))) = 1;
10176 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10179 /* There are no instructions to add or subtract registers
10180 from the stack pointer, so use the frame pointer as a
10181 temporary. We should always be using a frame pointer
10182 in this case anyway. */
10183 gcc_assert (frame_pointer_needed);
10184 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10185 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10186 hard_frame_pointer_rtx,
10187 MIPS_PROLOGUE_TEMP (Pmode)));
10188 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10191 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10193 MIPS_PROLOGUE_TEMP (Pmode)));
10195 /* Describe the combined effect of the previous instructions. */
10196 mips_set_frame_expr
10197 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10198 plus_constant (stack_pointer_rtx, -size)));
10202 /* Set up the frame pointer, if we're using one. */
10203 if (frame_pointer_needed)
10205 HOST_WIDE_INT offset;
10207 offset = frame->hard_frame_pointer_offset;
10210 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10211 RTX_FRAME_RELATED_P (insn) = 1;
10213 else if (SMALL_OPERAND (offset))
10215 insn = gen_add3_insn (hard_frame_pointer_rtx,
10216 stack_pointer_rtx, GEN_INT (offset));
10217 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10221 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10222 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10223 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10224 hard_frame_pointer_rtx,
10225 MIPS_PROLOGUE_TEMP (Pmode)));
10226 mips_set_frame_expr
10227 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10228 plus_constant (stack_pointer_rtx, offset)));
10232 mips_emit_loadgp ();
10234 /* Initialize the $gp save slot. */
10235 if (mips_cfun_has_cprestore_slot_p ())
10237 rtx base, mem, gp, temp;
10238 HOST_WIDE_INT offset;
10240 mips_get_cprestore_base_and_offset (&base, &offset, false);
10241 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10242 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10243 temp = (SMALL_OPERAND (offset)
10244 ? gen_rtx_SCRATCH (Pmode)
10245 : MIPS_PROLOGUE_TEMP (Pmode));
10246 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10248 mips_get_cprestore_base_and_offset (&base, &offset, true);
10249 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10250 emit_insn (gen_use_cprestore (mem));
10253 /* We need to search back to the last use of K0 or K1. */
10254 if (cfun->machine->interrupt_handler_p)
10256 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10258 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10260 /* Emit a move from K1 to COP0 Status after insn. */
10261 gcc_assert (insn != NULL_RTX);
10262 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10263 gen_rtx_REG (SImode, K1_REG_NUM)),
10267 /* If we are profiling, make sure no instructions are scheduled before
10268 the call to mcount. */
10270 emit_insn (gen_blockage ());
10273 /* Emit instructions to restore register REG from slot MEM. */
10276 mips_restore_reg (rtx reg, rtx mem)
10278 /* There's no MIPS16 instruction to load $31 directly. Load into
10279 $7 instead and adjust the return insn appropriately. */
10280 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10281 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10283 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10286 /* Emit any instructions needed before a return. */
10289 mips_expand_before_return (void)
10291 /* When using a call-clobbered gp, we start out with unified call
10292 insns that include instructions to restore the gp. We then split
10293 these unified calls after reload. These split calls explicitly
10294 clobber gp, so there is no need to define
10295 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10297 For consistency, we should also insert an explicit clobber of $28
10298 before return insns, so that the post-reload optimizers know that
10299 the register is not live on exit. */
10300 if (TARGET_CALL_CLOBBERED_GP)
10301 emit_clobber (pic_offset_table_rtx);
10304 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10308 mips_expand_epilogue (bool sibcall_p)
10310 const struct mips_frame_info *frame;
10311 HOST_WIDE_INT step1, step2;
10312 rtx base, target, insn;
10314 if (!sibcall_p && mips_can_use_return_insn ())
10316 emit_jump_insn (gen_return ());
10320 /* In MIPS16 mode, if the return value should go into a floating-point
10321 register, we need to call a helper routine to copy it over. */
10322 if (mips16_cfun_returns_in_fpr_p ())
10323 mips16_copy_fpr_return_value ();
10325 /* Split the frame into two. STEP1 is the amount of stack we should
10326 deallocate before restoring the registers. STEP2 is the amount we
10327 should deallocate afterwards.
10329 Start off by assuming that no registers need to be restored. */
10330 frame = &cfun->machine->frame;
10331 step1 = frame->total_size;
10334 /* Work out which register holds the frame address. */
10335 if (!frame_pointer_needed)
10336 base = stack_pointer_rtx;
10339 base = hard_frame_pointer_rtx;
10340 step1 -= frame->hard_frame_pointer_offset;
10343 /* If we need to restore registers, deallocate as much stack as
10344 possible in the second step without going out of range. */
10345 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10346 || frame->num_cop0_regs > 0)
10348 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10352 /* Set TARGET to BASE + STEP1. */
10358 /* Get an rtx for STEP1 that we can add to BASE. */
10359 adjust = GEN_INT (step1);
10360 if (!SMALL_OPERAND (step1))
10362 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10363 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10366 /* Normal mode code can copy the result straight into $sp. */
10367 if (!TARGET_MIPS16)
10368 target = stack_pointer_rtx;
10370 emit_insn (gen_add3_insn (target, base, adjust));
10373 /* Copy TARGET into the stack pointer. */
10374 if (target != stack_pointer_rtx)
10375 mips_emit_move (stack_pointer_rtx, target);
10377 /* If we're using addressing macros, $gp is implicitly used by all
10378 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10380 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10381 emit_insn (gen_blockage ());
10383 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10385 unsigned int regno, mask;
10386 HOST_WIDE_INT offset;
10389 /* Generate the restore instruction. */
10390 mask = frame->mask;
10391 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10393 /* Restore any other registers manually. */
10394 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10395 if (BITSET_P (mask, regno - GP_REG_FIRST))
10397 offset -= UNITS_PER_WORD;
10398 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10401 /* Restore the remaining registers and deallocate the final bit
10403 emit_insn (restore);
10407 /* Restore the registers. */
10408 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10409 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10412 if (cfun->machine->interrupt_handler_p)
10414 HOST_WIDE_INT offset;
10417 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10418 if (!cfun->machine->keep_interrupts_masked_p)
10420 /* Restore the original EPC. */
10421 mem = gen_frame_mem (word_mode,
10422 plus_constant (stack_pointer_rtx, offset));
10423 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10424 offset -= UNITS_PER_WORD;
10426 /* Move to COP0 EPC. */
10427 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10428 gen_rtx_REG (SImode, K0_REG_NUM)));
10431 /* Restore the original Status. */
10432 mem = gen_frame_mem (word_mode,
10433 plus_constant (stack_pointer_rtx, offset));
10434 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10435 offset -= UNITS_PER_WORD;
10437 /* If we don't use shoadow register set, we need to update SP. */
10438 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10439 emit_insn (gen_add3_insn (stack_pointer_rtx,
10443 /* Move to COP0 Status. */
10444 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10445 gen_rtx_REG (SImode, K0_REG_NUM)));
10449 /* Deallocate the final bit of the frame. */
10451 emit_insn (gen_add3_insn (stack_pointer_rtx,
10457 /* Add in the __builtin_eh_return stack adjustment. We need to
10458 use a temporary in MIPS16 code. */
10459 if (crtl->calls_eh_return)
10463 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10464 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10465 MIPS_EPILOGUE_TEMP (Pmode),
10466 EH_RETURN_STACKADJ_RTX));
10467 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10470 emit_insn (gen_add3_insn (stack_pointer_rtx,
10472 EH_RETURN_STACKADJ_RTX));
10477 mips_expand_before_return ();
10478 if (cfun->machine->interrupt_handler_p)
10480 /* Interrupt handlers generate eret or deret. */
10481 if (cfun->machine->use_debug_exception_return_p)
10482 emit_jump_insn (gen_mips_deret ());
10484 emit_jump_insn (gen_mips_eret ());
10488 unsigned int regno;
10490 /* When generating MIPS16 code, the normal
10491 mips_for_each_saved_gpr_and_fpr path will restore the return
10492 address into $7 rather than $31. */
10494 && !GENERATE_MIPS16E_SAVE_RESTORE
10495 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10496 regno = GP_REG_FIRST + 7;
10498 regno = RETURN_ADDR_REGNUM;
10499 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10503 /* Search from the beginning to the first use of K0 or K1. */
10504 if (cfun->machine->interrupt_handler_p
10505 && !cfun->machine->keep_interrupts_masked_p)
10507 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10509 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10511 gcc_assert (insn != NULL_RTX);
10512 /* Insert disable interrupts before the first use of K0 or K1. */
10513 emit_insn_before (gen_mips_di (), insn);
10514 emit_insn_before (gen_mips_ehb (), insn);
10518 /* Return nonzero if this function is known to have a null epilogue.
10519 This allows the optimizer to omit jumps to jumps if no stack
10523 mips_can_use_return_insn (void)
10525 /* Interrupt handlers need to go through the epilogue. */
10526 if (cfun->machine->interrupt_handler_p)
10529 if (!reload_completed)
10535 /* In MIPS16 mode, a function that returns a floating-point value
10536 needs to arrange to copy the return value into the floating-point
10538 if (mips16_cfun_returns_in_fpr_p ())
10541 return cfun->machine->frame.total_size == 0;
10544 /* Return true if register REGNO can store a value of mode MODE.
10545 The result of this function is cached in mips_hard_regno_mode_ok. */
10548 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10551 enum mode_class mclass;
10553 if (mode == CCV2mode)
10554 return (ISA_HAS_8CC
10555 && ST_REG_P (regno)
10556 && (regno - ST_REG_FIRST) % 2 == 0);
10558 if (mode == CCV4mode)
10559 return (ISA_HAS_8CC
10560 && ST_REG_P (regno)
10561 && (regno - ST_REG_FIRST) % 4 == 0);
10563 if (mode == CCmode)
10566 return regno == FPSW_REGNUM;
10568 return (ST_REG_P (regno)
10569 || GP_REG_P (regno)
10570 || FP_REG_P (regno));
10573 size = GET_MODE_SIZE (mode);
10574 mclass = GET_MODE_CLASS (mode);
10576 if (GP_REG_P (regno))
10577 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10579 if (FP_REG_P (regno)
10580 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10581 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10583 /* Allow TFmode for CCmode reloads. */
10584 if (mode == TFmode && ISA_HAS_8CC)
10587 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10588 if (TARGET_LOONGSON_VECTORS
10589 && (mode == V2SImode
10590 || mode == V4HImode
10591 || mode == V8QImode
10592 || mode == DImode))
10595 if (mclass == MODE_FLOAT
10596 || mclass == MODE_COMPLEX_FLOAT
10597 || mclass == MODE_VECTOR_FLOAT)
10598 return size <= UNITS_PER_FPVALUE;
10600 /* Allow integer modes that fit into a single register. We need
10601 to put integers into FPRs when using instructions like CVT
10602 and TRUNC. There's no point allowing sizes smaller than a word,
10603 because the FPU has no appropriate load/store instructions. */
10604 if (mclass == MODE_INT)
10605 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10608 if (ACC_REG_P (regno)
10609 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10611 if (MD_REG_P (regno))
10613 /* After a multiplication or division, clobbering HI makes
10614 the value of LO unpredictable, and vice versa. This means
10615 that, for all interesting cases, HI and LO are effectively
10618 We model this by requiring that any value that uses HI
10620 if (size <= UNITS_PER_WORD * 2)
10621 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10625 /* DSP accumulators do not have the same restrictions as
10626 HI and LO, so we can treat them as normal doubleword
10628 if (size <= UNITS_PER_WORD)
10631 if (size <= UNITS_PER_WORD * 2
10632 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10637 if (ALL_COP_REG_P (regno))
10638 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10640 if (regno == GOT_VERSION_REGNUM)
10641 return mode == SImode;
10646 /* Implement HARD_REGNO_NREGS. */
10649 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10651 if (ST_REG_P (regno))
10652 /* The size of FP status registers is always 4, because they only hold
10653 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10654 return (GET_MODE_SIZE (mode) + 3) / 4;
10656 if (FP_REG_P (regno))
10657 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10659 /* All other registers are word-sized. */
10660 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10663 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10664 in mips_hard_regno_nregs. */
10667 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10673 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10674 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10676 size = MIN (size, 4);
10677 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10679 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10681 size = MIN (size, UNITS_PER_FPREG);
10682 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10684 if (!hard_reg_set_empty_p (left))
10685 size = MIN (size, UNITS_PER_WORD);
10686 return (GET_MODE_SIZE (mode) + size - 1) / size;
10689 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10692 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10693 enum machine_mode to ATTRIBUTE_UNUSED,
10694 enum reg_class rclass)
10696 /* There are several problems with changing the modes of values
10697 in floating-point registers:
10699 - When a multi-word value is stored in paired floating-point
10700 registers, the first register always holds the low word.
10701 We therefore can't allow FPRs to change between single-word
10702 and multi-word modes on big-endian targets.
10704 - GCC assumes that each word of a multiword register can be accessed
10705 individually using SUBREGs. This is not true for floating-point
10706 registers if they are bigger than a word.
10708 - Loading a 32-bit value into a 64-bit floating-point register
10709 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10710 We can't allow FPRs to change from SImode to to a wider mode on
10713 - If the FPU has already interpreted a value in one format, we must
10714 not ask it to treat the value as having a different format.
10716 We therefore disallow all mode changes involving FPRs. */
10717 return reg_classes_intersect_p (FP_REGS, rclass);
10720 /* Implement target hook small_register_classes_for_mode_p. */
10723 mips_small_register_classes_for_mode_p (enum machine_mode mode
10726 return TARGET_MIPS16;
10729 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10732 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10737 return TARGET_HARD_FLOAT;
10740 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10743 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10750 /* Implement MODES_TIEABLE_P. */
10753 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10755 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10756 prefer to put one of them in FPRs. */
10757 return (mode1 == mode2
10758 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10759 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10762 /* Implement PREFERRED_RELOAD_CLASS. */
10765 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10767 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10770 if (reg_class_subset_p (FP_REGS, rclass)
10771 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10774 if (reg_class_subset_p (GR_REGS, rclass))
10777 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10783 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10784 Return a "canonical" class to represent it in later calculations. */
10786 static enum reg_class
10787 mips_canonicalize_move_class (enum reg_class rclass)
10789 /* All moves involving accumulator registers have the same cost. */
10790 if (reg_class_subset_p (rclass, ACC_REGS))
10793 /* Likewise promote subclasses of general registers to the most
10794 interesting containing class. */
10795 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10797 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10798 rclass = GENERAL_REGS;
10803 /* Return the cost of moving a value of mode MODE from a register of
10804 class FROM to a GPR. Return 0 for classes that are unions of other
10805 classes handled by this function. */
10808 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10809 enum reg_class from)
10814 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10818 /* MFLO and MFHI. */
10826 /* LUI followed by MOVF. */
10832 /* This choice of value is historical. */
10840 /* Return the cost of moving a value of mode MODE from a GPR to a
10841 register of class TO. Return 0 for classes that are unions of
10842 other classes handled by this function. */
10845 mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to)
10850 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10854 /* MTLO and MTHI. */
10862 /* A secondary reload through an FPR scratch. */
10863 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10864 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10869 /* This choice of value is historical. */
10877 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
10878 maximum of the move costs for subclasses; regclass will work out
10879 the maximum for us. */
10882 mips_register_move_cost (enum machine_mode mode,
10883 enum reg_class from, enum reg_class to)
10885 enum reg_class dregs;
10888 from = mips_canonicalize_move_class (from);
10889 to = mips_canonicalize_move_class (to);
10891 /* Handle moves that can be done without using general-purpose registers. */
10892 if (from == FP_REGS)
10894 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10898 /* The sequence generated by mips_expand_fcc_reload. */
10902 /* Handle cases in which only one class deviates from the ideal. */
10903 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10905 return mips_move_from_gpr_cost (mode, to);
10907 return mips_move_to_gpr_cost (mode, from);
10909 /* Handles cases that require a GPR temporary. */
10910 cost1 = mips_move_to_gpr_cost (mode, from);
10913 cost2 = mips_move_from_gpr_cost (mode, to);
10915 return cost1 + cost2;
10921 /* Implement TARGET_IRA_COVER_CLASSES. */
10923 static const enum reg_class *
10924 mips_ira_cover_classes (void)
10926 static const enum reg_class acc_classes[] = {
10927 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10928 ST_REGS, LIM_REG_CLASSES
10930 static const enum reg_class no_acc_classes[] = {
10931 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10932 ST_REGS, LIM_REG_CLASSES
10935 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10936 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10937 as a cover class only works well when we keep per-register costs.
10938 Using it when not optimizing can cause us to think accumulators
10939 have the same cost as GPRs in cases where GPRs are actually much
10941 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10944 /* Return the register class required for a secondary register when
10945 copying between one of the registers in RCLASS and value X, which
10946 has mode MODE. X is the source of the move if IN_P, otherwise it
10947 is the destination. Return NO_REGS if no secondary register is
10951 mips_secondary_reload_class (enum reg_class rclass,
10952 enum machine_mode mode, rtx x, bool in_p)
10956 /* If X is a constant that cannot be loaded into $25, it must be loaded
10957 into some other GPR. No other register class allows a direct move. */
10958 if (mips_dangerous_for_la25_p (x))
10959 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
10961 regno = true_regnum (x);
10964 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10965 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
10971 /* Copying from accumulator registers to anywhere other than a general
10972 register requires a temporary general register. */
10973 if (reg_class_subset_p (rclass, ACC_REGS))
10974 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10975 if (ACC_REG_P (regno))
10976 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10978 /* We can only copy a value to a condition code register from a
10979 floating-point register, and even then we require a scratch
10980 floating-point register. We can only copy a value out of a
10981 condition-code register into a general register. */
10982 if (reg_class_subset_p (rclass, ST_REGS))
10986 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10988 if (ST_REG_P (regno))
10992 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10995 if (reg_class_subset_p (rclass, FP_REGS))
10998 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
10999 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11000 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11003 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11004 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11007 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
11008 /* We can force the constant to memory and use lwc1
11009 and ldc1. As above, we will use pairs of lwc1s if
11010 ldc1 is not supported. */
11013 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11014 /* In this case we can use mov.fmt. */
11017 /* Otherwise, we need to reload through an integer register. */
11020 if (FP_REG_P (regno))
11021 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11026 /* Implement TARGET_MODE_REP_EXTENDED. */
11029 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11031 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11032 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11033 return SIGN_EXTEND;
11038 /* Implement TARGET_VALID_POINTER_MODE. */
11041 mips_valid_pointer_mode (enum machine_mode mode)
11043 return mode == SImode || (TARGET_64BIT && mode == DImode);
11046 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11049 mips_vector_mode_supported_p (enum machine_mode mode)
11054 return TARGET_PAIRED_SINGLE_FLOAT;
11069 return TARGET_LOONGSON_VECTORS;
11076 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11079 mips_scalar_mode_supported_p (enum machine_mode mode)
11081 if (ALL_FIXED_POINT_MODE_P (mode)
11082 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11085 return default_scalar_mode_supported_p (mode);
11088 /* Implement TARGET_INIT_LIBFUNCS. */
11090 #include "config/gofast.h"
11093 mips_init_libfuncs (void)
11095 if (TARGET_FIX_VR4120)
11097 /* Register the special divsi3 and modsi3 functions needed to work
11098 around VR4120 division errata. */
11099 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11100 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11103 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11105 /* Register the MIPS16 -mhard-float stubs. */
11106 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11107 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11108 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11109 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11111 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11112 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11113 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11114 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11115 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11116 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11117 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11119 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11120 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11121 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11123 if (TARGET_DOUBLE_FLOAT)
11125 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11126 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11127 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11128 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11130 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11131 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11132 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11133 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11134 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11135 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11136 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11138 set_conv_libfunc (sext_optab, DFmode, SFmode,
11139 "__mips16_extendsfdf2");
11140 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11141 "__mips16_truncdfsf2");
11142 set_conv_libfunc (sfix_optab, SImode, DFmode,
11143 "__mips16_fix_truncdfsi");
11144 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11145 "__mips16_floatsidf");
11146 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11147 "__mips16_floatunsidf");
11151 /* Register the gofast functions if selected using --enable-gofast. */
11152 gofast_maybe_init_libfuncs ();
11154 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11155 on an external non-MIPS16 routine to implement __sync_synchronize. */
11157 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11160 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11163 mips_process_load_label (rtx target)
11165 rtx base, gp, intop;
11166 HOST_WIDE_INT offset;
11168 mips_multi_start ();
11172 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11173 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11177 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11178 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11182 gp = pic_offset_table_rtx;
11183 if (mips_cfun_has_cprestore_slot_p ())
11185 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11186 mips_get_cprestore_base_and_offset (&base, &offset, true);
11187 if (!SMALL_OPERAND (offset))
11189 intop = GEN_INT (CONST_HIGH_PART (offset));
11190 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11191 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11194 offset = CONST_LOW_PART (offset);
11196 intop = GEN_INT (offset);
11197 if (ISA_HAS_LOAD_DELAY)
11198 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11200 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11202 if (ISA_HAS_LOAD_DELAY)
11203 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11205 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11206 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11211 /* Return the number of instructions needed to load a label into $AT. */
11213 static unsigned int
11214 mips_load_label_length (void)
11216 if (cfun->machine->load_label_length == 0)
11218 mips_process_load_label (pc_rtx);
11219 cfun->machine->load_label_length = mips_multi_num_insns;
11221 return cfun->machine->load_label_length;
11224 /* Emit an asm sequence to start a noat block and load the address
11225 of a label into $1. */
11228 mips_output_load_label (rtx target)
11230 mips_push_asm_switch (&mips_noat);
11231 if (TARGET_EXPLICIT_RELOCS)
11233 mips_process_load_label (target);
11234 mips_multi_write ();
11238 if (Pmode == DImode)
11239 output_asm_insn ("dla\t%@,%0", &target);
11241 output_asm_insn ("la\t%@,%0", &target);
11245 /* Return the length of INSN. LENGTH is the initial length computed by
11246 attributes in the machine-description file. */
11249 mips_adjust_insn_length (rtx insn, int length)
11251 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11252 of a PIC long-branch sequence. Substitute the correct value. */
11253 if (length == MAX_PIC_BRANCH_LENGTH
11254 && INSN_CODE (insn) >= 0
11255 && get_attr_type (insn) == TYPE_BRANCH)
11257 /* Add the branch-over instruction and its delay slot, if this
11258 is a conditional branch. */
11259 length = simplejump_p (insn) ? 0 : 8;
11261 /* Load the label into $AT and jump to it. Ignore the delay
11262 slot of the jump. */
11263 length += mips_load_label_length () + 4;
11266 /* A unconditional jump has an unfilled delay slot if it is not part
11267 of a sequence. A conditional jump normally has a delay slot, but
11268 does not on MIPS16. */
11269 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11272 /* See how many nops might be needed to avoid hardware hazards. */
11273 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11274 switch (get_attr_hazard (insn))
11288 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11289 the .md file length attributes are 4-based for both modes.
11290 Adjust the MIPS16 ones here. */
11297 /* Return the assembly code for INSN, which has the operands given by
11298 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11299 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11300 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11301 version of BRANCH_IF_TRUE. */
11304 mips_output_conditional_branch (rtx insn, rtx *operands,
11305 const char *branch_if_true,
11306 const char *branch_if_false)
11308 unsigned int length;
11309 rtx taken, not_taken;
11311 gcc_assert (LABEL_P (operands[0]));
11313 length = get_attr_length (insn);
11316 /* Just a simple conditional branch. */
11317 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11318 return branch_if_true;
11321 /* Generate a reversed branch around a direct jump. This fallback does
11322 not use branch-likely instructions. */
11323 mips_branch_likely = false;
11324 not_taken = gen_label_rtx ();
11325 taken = operands[0];
11327 /* Generate the reversed branch to NOT_TAKEN. */
11328 operands[0] = not_taken;
11329 output_asm_insn (branch_if_false, operands);
11331 /* If INSN has a delay slot, we must provide delay slots for both the
11332 branch to NOT_TAKEN and the conditional jump. We must also ensure
11333 that INSN's delay slot is executed in the appropriate cases. */
11334 if (final_sequence)
11336 /* This first delay slot will always be executed, so use INSN's
11337 delay slot if is not annulled. */
11338 if (!INSN_ANNULLED_BRANCH_P (insn))
11340 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11341 asm_out_file, optimize, 1, NULL);
11342 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11345 output_asm_insn ("nop", 0);
11346 fprintf (asm_out_file, "\n");
11349 /* Output the unconditional branch to TAKEN. */
11350 if (TARGET_ABSOLUTE_JUMPS)
11351 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11354 mips_output_load_label (taken);
11355 output_asm_insn ("jr\t%@%]%/", 0);
11358 /* Now deal with its delay slot; see above. */
11359 if (final_sequence)
11361 /* This delay slot will only be executed if the branch is taken.
11362 Use INSN's delay slot if is annulled. */
11363 if (INSN_ANNULLED_BRANCH_P (insn))
11365 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11366 asm_out_file, optimize, 1, NULL);
11367 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11370 output_asm_insn ("nop", 0);
11371 fprintf (asm_out_file, "\n");
11374 /* Output NOT_TAKEN. */
11375 targetm.asm_out.internal_label (asm_out_file, "L",
11376 CODE_LABEL_NUMBER (not_taken));
11380 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11381 if some ordering condition is true. The condition is given by
11382 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11383 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11384 its second is always zero. */
11387 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11389 const char *branch[2];
11391 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11392 Make BRANCH[0] branch on the inverse condition. */
11393 switch (GET_CODE (operands[1]))
11395 /* These cases are equivalent to comparisons against zero. */
11397 inverted_p = !inverted_p;
11398 /* Fall through. */
11400 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11401 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11404 /* These cases are always true or always false. */
11406 inverted_p = !inverted_p;
11407 /* Fall through. */
11409 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11410 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11414 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11415 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11418 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11421 /* Start a block of code that needs access to the LL, SC and SYNC
11425 mips_start_ll_sc_sync_block (void)
11427 if (!ISA_HAS_LL_SC)
11429 output_asm_insn (".set\tpush", 0);
11430 output_asm_insn (".set\tmips2", 0);
11434 /* End a block started by mips_start_ll_sc_sync_block. */
11437 mips_end_ll_sc_sync_block (void)
11439 if (!ISA_HAS_LL_SC)
11440 output_asm_insn (".set\tpop", 0);
11443 /* Output and/or return the asm template for a sync instruction. */
11446 mips_output_sync (void)
11448 mips_start_ll_sc_sync_block ();
11449 output_asm_insn ("sync", 0);
11450 mips_end_ll_sc_sync_block ();
11454 /* Return the asm template associated with sync_insn1 value TYPE.
11455 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11457 static const char *
11458 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11462 case SYNC_INSN1_MOVE:
11463 return "move\t%0,%z2";
11464 case SYNC_INSN1_LI:
11465 return "li\t%0,%2";
11466 case SYNC_INSN1_ADDU:
11467 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11468 case SYNC_INSN1_ADDIU:
11469 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11470 case SYNC_INSN1_SUBU:
11471 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11472 case SYNC_INSN1_AND:
11473 return "and\t%0,%1,%z2";
11474 case SYNC_INSN1_ANDI:
11475 return "andi\t%0,%1,%2";
11476 case SYNC_INSN1_OR:
11477 return "or\t%0,%1,%z2";
11478 case SYNC_INSN1_ORI:
11479 return "ori\t%0,%1,%2";
11480 case SYNC_INSN1_XOR:
11481 return "xor\t%0,%1,%z2";
11482 case SYNC_INSN1_XORI:
11483 return "xori\t%0,%1,%2";
11485 gcc_unreachable ();
11488 /* Return the asm template associated with sync_insn2 value TYPE. */
11490 static const char *
11491 mips_sync_insn2_template (enum attr_sync_insn2 type)
11495 case SYNC_INSN2_NOP:
11496 gcc_unreachable ();
11497 case SYNC_INSN2_AND:
11498 return "and\t%0,%1,%z2";
11499 case SYNC_INSN2_XOR:
11500 return "xor\t%0,%1,%z2";
11501 case SYNC_INSN2_NOT:
11502 return "nor\t%0,%1,%.";
11504 gcc_unreachable ();
11507 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11508 the value of the one of the sync_* attributes. Return the operand
11509 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11510 have the associated attribute. */
11513 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11516 default_value = operands[index - 1];
11517 return default_value;
11520 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11521 sequence for it. */
11524 mips_process_sync_loop (rtx insn, rtx *operands)
11526 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11527 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11528 unsigned int tmp3_insn;
11529 enum attr_sync_insn1 insn1;
11530 enum attr_sync_insn2 insn2;
11533 /* Read an operand from the sync_WHAT attribute and store it in
11534 variable WHAT. DEFAULT is the default value if no attribute
11536 #define READ_OPERAND(WHAT, DEFAULT) \
11537 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11540 /* Read the memory. */
11541 READ_OPERAND (mem, 0);
11543 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11545 /* Read the other attributes. */
11546 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11547 READ_OPERAND (oldval, at);
11548 READ_OPERAND (newval, at);
11549 READ_OPERAND (inclusive_mask, 0);
11550 READ_OPERAND (exclusive_mask, 0);
11551 READ_OPERAND (required_oldval, 0);
11552 READ_OPERAND (insn1_op2, 0);
11553 insn1 = get_attr_sync_insn1 (insn);
11554 insn2 = get_attr_sync_insn2 (insn);
11556 mips_multi_start ();
11558 /* Output the release side of the memory barrier. */
11559 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11561 if (required_oldval == 0 && TARGET_OCTEON)
11563 /* Octeon doesn't reorder reads, so a full barrier can be
11564 created by using SYNCW to order writes combined with the
11565 write from the following SC. When the SC successfully
11566 completes, we know that all preceding writes are also
11567 committed to the coherent memory system. It is possible
11568 for a single SYNCW to fail, but a pair of them will never
11569 fail, so we use two. */
11570 mips_multi_add_insn ("syncw", NULL);
11571 mips_multi_add_insn ("syncw", NULL);
11574 mips_multi_add_insn ("sync", NULL);
11577 /* Output the branch-back label. */
11578 mips_multi_add_label ("1:");
11580 /* OLDVAL = *MEM. */
11581 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11582 oldval, mem, NULL);
11584 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11585 if (required_oldval)
11587 if (inclusive_mask == 0)
11591 gcc_assert (oldval != at);
11592 mips_multi_add_insn ("and\t%0,%1,%2",
11593 at, oldval, inclusive_mask, NULL);
11596 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11599 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11600 if (exclusive_mask == 0)
11604 gcc_assert (oldval != at);
11605 mips_multi_add_insn ("and\t%0,%1,%z2",
11606 at, oldval, exclusive_mask, NULL);
11610 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11612 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11613 at least one instruction in that case. */
11614 if (insn1 == SYNC_INSN1_MOVE
11615 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11619 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11620 newval, oldval, insn1_op2, NULL);
11624 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11625 if (insn2 == SYNC_INSN2_NOP)
11629 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11630 newval, tmp2, inclusive_mask, NULL);
11633 tmp3_insn = mips_multi_last_index ();
11635 /* $AT = $TMP1 | $TMP3. */
11636 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11638 mips_multi_set_operand (tmp3_insn, 0, at);
11643 gcc_assert (tmp1 != tmp3);
11644 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11647 /* if (!commit (*MEM = $AT)) goto 1.
11649 This will sometimes be a delayed branch; see the write code below
11651 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11652 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11654 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11655 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11657 mips_multi_copy_insn (tmp3_insn);
11658 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11661 mips_multi_add_insn ("nop", NULL);
11663 /* Output the acquire side of the memory barrier. */
11664 if (TARGET_SYNC_AFTER_SC)
11665 mips_multi_add_insn ("sync", NULL);
11667 /* Output the exit label, if needed. */
11668 if (required_oldval)
11669 mips_multi_add_label ("2:");
11671 #undef READ_OPERAND
11674 /* Output and/or return the asm template for sync loop INSN, which has
11675 the operands given by OPERANDS. */
11678 mips_output_sync_loop (rtx insn, rtx *operands)
11680 mips_process_sync_loop (insn, operands);
11682 /* Use branch-likely instructions to work around the LL/SC R10000
11684 mips_branch_likely = TARGET_FIX_R10000;
11686 mips_push_asm_switch (&mips_noreorder);
11687 mips_push_asm_switch (&mips_nomacro);
11688 mips_push_asm_switch (&mips_noat);
11689 mips_start_ll_sc_sync_block ();
11691 mips_multi_write ();
11693 mips_end_ll_sc_sync_block ();
11694 mips_pop_asm_switch (&mips_noat);
11695 mips_pop_asm_switch (&mips_nomacro);
11696 mips_pop_asm_switch (&mips_noreorder);
11701 /* Return the number of individual instructions in sync loop INSN,
11702 which has the operands given by OPERANDS. */
11705 mips_sync_loop_insns (rtx insn, rtx *operands)
11707 mips_process_sync_loop (insn, operands);
11708 return mips_multi_num_insns;
11711 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11712 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11714 When working around R4000 and R4400 errata, we need to make sure that
11715 the division is not immediately followed by a shift[1][2]. We also
11716 need to stop the division from being put into a branch delay slot[3].
11717 The easiest way to avoid both problems is to add a nop after the
11718 division. When a divide-by-zero check is needed, this nop can be
11719 used to fill the branch delay slot.
11721 [1] If a double-word or a variable shift executes immediately
11722 after starting an integer division, the shift may give an
11723 incorrect result. See quotations of errata #16 and #28 from
11724 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11725 in mips.md for details.
11727 [2] A similar bug to [1] exists for all revisions of the
11728 R4000 and the R4400 when run in an MC configuration.
11729 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11731 "19. In this following sequence:
11733 ddiv (or ddivu or div or divu)
11734 dsll32 (or dsrl32, dsra32)
11736 if an MPT stall occurs, while the divide is slipping the cpu
11737 pipeline, then the following double shift would end up with an
11740 Workaround: The compiler needs to avoid generating any
11741 sequence with divide followed by extended double shift."
11743 This erratum is also present in "MIPS R4400MC Errata, Processor
11744 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11745 & 3.0" as errata #10 and #4, respectively.
11747 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11748 (also valid for MIPS R4000MC processors):
11750 "52. R4000SC: This bug does not apply for the R4000PC.
11752 There are two flavors of this bug:
11754 1) If the instruction just after divide takes an RF exception
11755 (tlb-refill, tlb-invalid) and gets an instruction cache
11756 miss (both primary and secondary) and the line which is
11757 currently in secondary cache at this index had the first
11758 data word, where the bits 5..2 are set, then R4000 would
11759 get a wrong result for the div.
11764 ------------------- # end-of page. -tlb-refill
11769 ------------------- # end-of page. -tlb-invalid
11772 2) If the divide is in the taken branch delay slot, where the
11773 target takes RF exception and gets an I-cache miss for the
11774 exception vector or where I-cache miss occurs for the
11775 target address, under the above mentioned scenarios, the
11776 div would get wrong results.
11779 j r2 # to next page mapped or unmapped
11780 div r8,r9 # this bug would be there as long
11781 # as there is an ICache miss and
11782 nop # the "data pattern" is present
11785 beq r0, r0, NextPage # to Next page
11789 This bug is present for div, divu, ddiv, and ddivu
11792 Workaround: For item 1), OS could make sure that the next page
11793 after the divide instruction is also mapped. For item 2), the
11794 compiler could make sure that the divide instruction is not in
11795 the branch delay slot."
11797 These processors have PRId values of 0x00004220 and 0x00004300 for
11798 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11801 mips_output_division (const char *division, rtx *operands)
11806 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11808 output_asm_insn (s, operands);
11811 if (TARGET_CHECK_ZERO_DIV)
11815 output_asm_insn (s, operands);
11816 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11818 else if (GENERATE_DIVIDE_TRAPS)
11820 /* Avoid long replay penalty on load miss by putting the trap before
11823 output_asm_insn ("teq\t%2,%.,7", operands);
11826 output_asm_insn (s, operands);
11827 s = "teq\t%2,%.,7";
11832 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11833 output_asm_insn (s, operands);
11834 s = "break\t7%)\n1:";
11840 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11841 instruction and if OUT_INSN assigns to the accumulator operand. */
11844 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11848 x = single_set (in_insn);
11854 if (GET_CODE (x) == PLUS
11855 && GET_CODE (XEXP (x, 0)) == MULT
11856 && reg_set_p (XEXP (x, 1), out_insn))
11859 if (GET_CODE (x) == MINUS
11860 && GET_CODE (XEXP (x, 1)) == MULT
11861 && reg_set_p (XEXP (x, 0), out_insn))
11867 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11868 data rather than the address. We need this because the cprestore
11869 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11870 which causes the default routine to abort. We just return false
11874 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11876 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11879 return !store_data_bypass_p (out_insn, in_insn);
11883 /* Variables and flags used in scheduler hooks when tuning for
11887 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11890 /* If true, then next ALU1/2 instruction will go to ALU1. */
11893 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11896 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11897 int alu1_core_unit_code;
11898 int alu2_core_unit_code;
11899 int falu1_core_unit_code;
11900 int falu2_core_unit_code;
11902 /* True if current cycle has a multi instruction.
11903 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11904 bool cycle_has_multi_p;
11906 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11907 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11909 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11910 instruction to go ALU1. */
11911 rtx alu1_turn_enabled_insn;
11912 rtx alu2_turn_enabled_insn;
11913 rtx falu1_turn_enabled_insn;
11914 rtx falu2_turn_enabled_insn;
11917 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11918 dependencies have no cost, except on the 20Kc where output-dependence
11919 is treated like input-dependence. */
11922 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11923 rtx dep ATTRIBUTE_UNUSED, int cost)
11925 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11928 if (REG_NOTE_KIND (link) != 0)
11933 /* Return the number of instructions that can be issued per cycle. */
11936 mips_issue_rate (void)
11940 case PROCESSOR_74KC:
11941 case PROCESSOR_74KF2_1:
11942 case PROCESSOR_74KF1_1:
11943 case PROCESSOR_74KF3_2:
11944 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11945 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11946 but in reality only a maximum of 3 insns can be issued as
11947 floating-point loads and stores also require a slot in the
11949 case PROCESSOR_R10000:
11950 /* All R10K Processors are quad-issue (being the first MIPS
11951 processors to support this feature). */
11954 case PROCESSOR_20KC:
11955 case PROCESSOR_R4130:
11956 case PROCESSOR_R5400:
11957 case PROCESSOR_R5500:
11958 case PROCESSOR_R7000:
11959 case PROCESSOR_R9000:
11960 case PROCESSOR_OCTEON:
11963 case PROCESSOR_SB1:
11964 case PROCESSOR_SB1A:
11965 /* This is actually 4, but we get better performance if we claim 3.
11966 This is partly because of unwanted speculative code motion with the
11967 larger number, and partly because in most common cases we can't
11968 reach the theoretical max of 4. */
11971 case PROCESSOR_LOONGSON_2E:
11972 case PROCESSOR_LOONGSON_2F:
11980 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11983 mips_ls2_init_dfa_post_cycle_insn (void)
11986 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11987 mips_ls2.alu1_turn_enabled_insn = get_insns ();
11991 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11992 mips_ls2.alu2_turn_enabled_insn = get_insns ();
11996 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11997 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12001 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12002 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12005 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12006 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12007 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12008 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12011 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12012 Init data used in mips_dfa_post_advance_cycle. */
12015 mips_init_dfa_post_cycle_insn (void)
12017 if (TUNE_LOONGSON_2EF)
12018 mips_ls2_init_dfa_post_cycle_insn ();
12021 /* Initialize STATE when scheduling for Loongson 2E/2F.
12022 Support round-robin dispatch scheme by enabling only one of
12023 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12027 mips_ls2_dfa_post_advance_cycle (state_t state)
12029 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12031 /* Though there are no non-pipelined ALU1 insns,
12032 we can get an instruction of type 'multi' before reload. */
12033 gcc_assert (mips_ls2.cycle_has_multi_p);
12034 mips_ls2.alu1_turn_p = false;
12037 mips_ls2.cycle_has_multi_p = false;
12039 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12040 /* We have a non-pipelined alu instruction in the core,
12041 adjust round-robin counter. */
12042 mips_ls2.alu1_turn_p = true;
12044 if (mips_ls2.alu1_turn_p)
12046 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12047 gcc_unreachable ();
12051 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12052 gcc_unreachable ();
12055 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12057 /* There are no non-pipelined FALU1 insns. */
12058 gcc_unreachable ();
12059 mips_ls2.falu1_turn_p = false;
12062 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12063 /* We have a non-pipelined falu instruction in the core,
12064 adjust round-robin counter. */
12065 mips_ls2.falu1_turn_p = true;
12067 if (mips_ls2.falu1_turn_p)
12069 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12070 gcc_unreachable ();
12074 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12075 gcc_unreachable ();
12079 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12080 This hook is being called at the start of each cycle. */
12083 mips_dfa_post_advance_cycle (void)
12085 if (TUNE_LOONGSON_2EF)
12086 mips_ls2_dfa_post_advance_cycle (curr_state);
12089 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12090 be as wide as the scheduling freedom in the DFA. */
12093 mips_multipass_dfa_lookahead (void)
12095 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12099 if (TUNE_LOONGSON_2EF)
12108 /* Remove the instruction at index LOWER from ready queue READY and
12109 reinsert it in front of the instruction at index HIGHER. LOWER must
12113 mips_promote_ready (rtx *ready, int lower, int higher)
12118 new_head = ready[lower];
12119 for (i = lower; i < higher; i++)
12120 ready[i] = ready[i + 1];
12121 ready[i] = new_head;
12124 /* If the priority of the instruction at POS2 in the ready queue READY
12125 is within LIMIT units of that of the instruction at POS1, swap the
12126 instructions if POS2 is not already less than POS1. */
12129 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12132 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12136 temp = ready[pos1];
12137 ready[pos1] = ready[pos2];
12138 ready[pos2] = temp;
12142 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12143 that may clobber hi or lo. */
12144 static rtx mips_macc_chains_last_hilo;
12146 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12147 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12150 mips_macc_chains_record (rtx insn)
12152 if (get_attr_may_clobber_hilo (insn))
12153 mips_macc_chains_last_hilo = insn;
12156 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12157 has NREADY elements, looking for a multiply-add or multiply-subtract
12158 instruction that is cumulative with mips_macc_chains_last_hilo.
12159 If there is one, promote it ahead of anything else that might
12160 clobber hi or lo. */
12163 mips_macc_chains_reorder (rtx *ready, int nready)
12167 if (mips_macc_chains_last_hilo != 0)
12168 for (i = nready - 1; i >= 0; i--)
12169 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12171 for (j = nready - 1; j > i; j--)
12172 if (recog_memoized (ready[j]) >= 0
12173 && get_attr_may_clobber_hilo (ready[j]))
12175 mips_promote_ready (ready, i, j);
12182 /* The last instruction to be scheduled. */
12183 static rtx vr4130_last_insn;
12185 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12186 points to an rtx that is initially an instruction. Nullify the rtx
12187 if the instruction uses the value of register X. */
12190 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12195 insn_ptr = (rtx *) data;
12198 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12202 /* Return true if there is true register dependence between vr4130_last_insn
12206 vr4130_true_reg_dependence_p (rtx insn)
12208 note_stores (PATTERN (vr4130_last_insn),
12209 vr4130_true_reg_dependence_p_1, &insn);
12213 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12214 the ready queue and that INSN2 is the instruction after it, return
12215 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12216 in which INSN1 and INSN2 can probably issue in parallel, but for
12217 which (INSN2, INSN1) should be less sensitive to instruction
12218 alignment than (INSN1, INSN2). See 4130.md for more details. */
12221 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12223 sd_iterator_def sd_it;
12226 /* Check for the following case:
12228 1) there is some other instruction X with an anti dependence on INSN1;
12229 2) X has a higher priority than INSN2; and
12230 3) X is an arithmetic instruction (and thus has no unit restrictions).
12232 If INSN1 is the last instruction blocking X, it would better to
12233 choose (INSN1, X) over (INSN2, INSN1). */
12234 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12235 if (DEP_TYPE (dep) == REG_DEP_ANTI
12236 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12237 && recog_memoized (DEP_CON (dep)) >= 0
12238 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12241 if (vr4130_last_insn != 0
12242 && recog_memoized (insn1) >= 0
12243 && recog_memoized (insn2) >= 0)
12245 /* See whether INSN1 and INSN2 use different execution units,
12246 or if they are both ALU-type instructions. If so, they can
12247 probably execute in parallel. */
12248 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12249 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12250 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12252 /* If only one of the instructions has a dependence on
12253 vr4130_last_insn, prefer to schedule the other one first. */
12254 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12255 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12256 if (dep1_p != dep2_p)
12259 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12260 is not an ALU-type instruction and if INSN1 uses the same
12261 execution unit. (Note that if this condition holds, we already
12262 know that INSN2 uses a different execution unit.) */
12263 if (class1 != VR4130_CLASS_ALU
12264 && recog_memoized (vr4130_last_insn) >= 0
12265 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12272 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12273 queue with at least two instructions. Swap the first two if
12274 vr4130_swap_insns_p says that it could be worthwhile. */
12277 vr4130_reorder (rtx *ready, int nready)
12279 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12280 mips_promote_ready (ready, nready - 2, nready - 1);
12283 /* Record whether last 74k AGEN instruction was a load or store. */
12284 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12286 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12287 resets to TYPE_UNKNOWN state. */
12290 mips_74k_agen_init (rtx insn)
12292 if (!insn || CALL_P (insn) || JUMP_P (insn))
12293 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12296 enum attr_type type = get_attr_type (insn);
12297 if (type == TYPE_LOAD || type == TYPE_STORE)
12298 mips_last_74k_agen_insn = type;
12302 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12303 loads to be grouped together, and multiple stores to be grouped
12304 together. Swap things around in the ready queue to make this happen. */
12307 mips_74k_agen_reorder (rtx *ready, int nready)
12310 int store_pos, load_pos;
12315 for (i = nready - 1; i >= 0; i--)
12317 rtx insn = ready[i];
12318 if (USEFUL_INSN_P (insn))
12319 switch (get_attr_type (insn))
12322 if (store_pos == -1)
12327 if (load_pos == -1)
12336 if (load_pos == -1 || store_pos == -1)
12339 switch (mips_last_74k_agen_insn)
12342 /* Prefer to schedule loads since they have a higher latency. */
12344 /* Swap loads to the front of the queue. */
12345 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12348 /* Swap stores to the front of the queue. */
12349 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12356 /* Implement TARGET_SCHED_INIT. */
12359 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12360 int max_ready ATTRIBUTE_UNUSED)
12362 mips_macc_chains_last_hilo = 0;
12363 vr4130_last_insn = 0;
12364 mips_74k_agen_init (NULL_RTX);
12366 /* When scheduling for Loongson2, branch instructions go to ALU1,
12367 therefore basic block is most likely to start with round-robin counter
12368 pointed to ALU2. */
12369 mips_ls2.alu1_turn_p = false;
12370 mips_ls2.falu1_turn_p = true;
12373 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12376 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12377 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12379 if (!reload_completed
12380 && TUNE_MACC_CHAINS
12382 mips_macc_chains_reorder (ready, *nreadyp);
12384 if (reload_completed
12386 && !TARGET_VR4130_ALIGN
12388 vr4130_reorder (ready, *nreadyp);
12391 mips_74k_agen_reorder (ready, *nreadyp);
12393 return mips_issue_rate ();
12396 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12399 mips_ls2_variable_issue (rtx insn)
12401 if (mips_ls2.alu1_turn_p)
12403 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12404 mips_ls2.alu1_turn_p = false;
12408 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12409 mips_ls2.alu1_turn_p = true;
12412 if (mips_ls2.falu1_turn_p)
12414 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12415 mips_ls2.falu1_turn_p = false;
12419 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12420 mips_ls2.falu1_turn_p = true;
12423 if (recog_memoized (insn) >= 0)
12424 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12427 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12430 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12431 rtx insn, int more)
12433 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12434 if (USEFUL_INSN_P (insn))
12436 if (get_attr_type (insn) != TYPE_GHOST)
12438 if (!reload_completed && TUNE_MACC_CHAINS)
12439 mips_macc_chains_record (insn);
12440 vr4130_last_insn = insn;
12442 mips_74k_agen_init (insn);
12443 else if (TUNE_LOONGSON_2EF)
12444 mips_ls2_variable_issue (insn);
12447 /* Instructions of type 'multi' should all be split before
12448 the second scheduling pass. */
12449 gcc_assert (!reload_completed
12450 || recog_memoized (insn) < 0
12451 || get_attr_type (insn) != TYPE_MULTI);
12456 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12457 return the first operand of the associated PREF or PREFX insn. */
12460 mips_prefetch_cookie (rtx write, rtx locality)
12462 /* store_streamed / load_streamed. */
12463 if (INTVAL (locality) <= 0)
12464 return GEN_INT (INTVAL (write) + 4);
12466 /* store / load. */
12467 if (INTVAL (locality) <= 2)
12470 /* store_retained / load_retained. */
12471 return GEN_INT (INTVAL (write) + 6);
12474 /* Flags that indicate when a built-in function is available.
12476 BUILTIN_AVAIL_NON_MIPS16
12477 The function is available on the current target, but only
12478 in non-MIPS16 mode. */
12479 #define BUILTIN_AVAIL_NON_MIPS16 1
12481 /* Declare an availability predicate for built-in functions that
12482 require non-MIPS16 mode and also require COND to be true.
12483 NAME is the main part of the predicate's name. */
12484 #define AVAIL_NON_MIPS16(NAME, COND) \
12485 static unsigned int \
12486 mips_builtin_avail_##NAME (void) \
12488 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12491 /* This structure describes a single built-in function. */
12492 struct mips_builtin_description {
12493 /* The code of the main .md file instruction. See mips_builtin_type
12494 for more information. */
12495 enum insn_code icode;
12497 /* The floating-point comparison code to use with ICODE, if any. */
12498 enum mips_fp_condition cond;
12500 /* The name of the built-in function. */
12503 /* Specifies how the function should be expanded. */
12504 enum mips_builtin_type builtin_type;
12506 /* The function's prototype. */
12507 enum mips_function_type function_type;
12509 /* Whether the function is available. */
12510 unsigned int (*avail) (void);
12513 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12514 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12515 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12516 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12517 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12518 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12519 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12520 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12521 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12523 /* Construct a mips_builtin_description from the given arguments.
12525 INSN is the name of the associated instruction pattern, without the
12526 leading CODE_FOR_mips_.
12528 CODE is the floating-point condition code associated with the
12529 function. It can be 'f' if the field is not applicable.
12531 NAME is the name of the function itself, without the leading
12534 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12536 AVAIL is the name of the availability predicate, without the leading
12537 mips_builtin_avail_. */
12538 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12539 FUNCTION_TYPE, AVAIL) \
12540 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12541 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12542 mips_builtin_avail_ ## AVAIL }
12544 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12545 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12546 are as for MIPS_BUILTIN. */
12547 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12548 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12550 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12551 are subject to mips_builtin_avail_<AVAIL>. */
12552 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12553 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12554 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12555 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12556 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12558 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12559 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12560 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12561 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12562 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12563 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12565 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12566 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12568 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12569 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12571 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12572 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12575 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12576 are subject to mips_builtin_avail_mips3d. */
12577 #define CMP_4S_BUILTINS(INSN, COND) \
12578 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12579 MIPS_BUILTIN_CMP_ANY, \
12580 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12581 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12582 MIPS_BUILTIN_CMP_ALL, \
12583 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12585 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12586 instruction requires mips_builtin_avail_<AVAIL>. */
12587 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12588 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12589 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12591 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12592 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12595 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12596 #define CMP_BUILTINS(COND) \
12597 MOVTF_BUILTINS (c, COND, paired_single), \
12598 MOVTF_BUILTINS (cabs, COND, mips3d), \
12599 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12600 CMP_PS_BUILTINS (c, COND, paired_single), \
12601 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12602 CMP_4S_BUILTINS (c, COND), \
12603 CMP_4S_BUILTINS (cabs, COND)
12605 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12606 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12607 and AVAIL are as for MIPS_BUILTIN. */
12608 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12609 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12610 FUNCTION_TYPE, AVAIL)
12612 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12613 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12614 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12615 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12616 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12618 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12619 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12620 builtin_description field. */
12621 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12622 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12623 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12624 FUNCTION_TYPE, mips_builtin_avail_loongson }
12626 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12627 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12628 builtin_description field. */
12629 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12630 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12632 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12633 We use functions of this form when the same insn can be usefully applied
12634 to more than one datatype. */
12635 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12636 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12638 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12639 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12640 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12641 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12642 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12643 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12645 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12646 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12647 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12648 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12649 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12650 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12651 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12652 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12653 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12654 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12655 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12656 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12657 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12658 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12659 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12660 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12661 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12662 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12663 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12664 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12665 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12666 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12667 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12668 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12669 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12670 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12671 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12672 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12673 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12675 static const struct mips_builtin_description mips_builtins[] = {
12676 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12677 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12678 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12679 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12680 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12681 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12682 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12683 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12685 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12686 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12687 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12688 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12689 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12691 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12692 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12693 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12694 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12695 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12696 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12698 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12699 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12700 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12701 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12702 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12703 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12705 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12707 /* Built-in functions for the SB-1 processor. */
12708 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12710 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12711 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12712 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12713 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12714 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12715 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12716 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12717 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12718 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12719 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12720 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12721 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12722 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12723 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12724 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12725 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12726 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12727 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12728 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12729 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12730 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12731 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12732 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12733 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12734 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12735 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12736 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12737 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12738 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12739 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12740 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12741 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12742 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12743 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12744 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12745 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12746 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12747 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12748 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12749 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12750 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12751 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12752 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12753 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12754 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12755 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12756 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12757 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12758 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12759 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12760 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12761 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12762 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12763 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12764 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12765 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12766 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12767 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12768 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12769 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12770 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12771 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12772 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12773 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12774 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12775 BPOSGE_BUILTIN (32, dsp),
12777 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12778 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12779 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12780 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12781 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12782 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12783 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12784 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12785 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12786 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12787 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12788 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12789 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12790 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12791 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12792 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12793 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12794 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12795 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12796 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12797 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12798 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12799 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12800 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12801 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12802 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12803 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12804 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12805 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12806 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12807 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12808 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12809 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12810 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12811 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12813 /* Built-in functions for the DSP ASE (32-bit only). */
12814 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12815 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12816 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12817 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12818 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12819 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12820 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12821 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12822 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12823 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12824 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12825 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12826 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12827 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12828 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12829 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12830 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12831 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12832 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12833 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12834 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12836 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12837 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12838 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12839 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12840 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12841 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12842 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12843 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12844 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
12845 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
12846 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12847 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12848 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12849 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12850 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12851 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12853 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12854 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12855 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12856 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12857 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12858 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12859 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12860 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12861 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12862 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12863 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12864 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12865 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12866 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12867 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12868 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12869 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12870 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12871 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12872 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12873 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12874 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12875 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12876 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12877 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12878 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12879 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12880 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12881 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12882 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12883 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12884 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12885 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12886 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12887 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12888 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12889 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12890 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12891 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12892 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12893 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12894 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12895 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12896 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12897 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12898 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12899 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12900 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12901 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
12902 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12903 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12904 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12905 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12906 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
12907 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
12908 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12909 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12910 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12911 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
12912 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12913 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
12914 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
12915 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
12916 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
12917 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12918 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12919 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12920 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12921 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12922 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12923 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12924 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12925 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12926 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12927 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12928 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12929 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12930 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12931 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12932 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12933 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12934 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12935 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
12936 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
12937 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12938 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12939 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12940 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12941 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12942 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12943 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12944 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12945 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12946 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12947 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12948 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12949 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12950 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12951 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12952 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12954 /* Sundry other built-in functions. */
12955 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
12958 /* MODE is a vector mode whose elements have type TYPE. Return the type
12959 of the vector itself. */
12962 mips_builtin_vector_type (tree type, enum machine_mode mode)
12964 static tree types[2 * (int) MAX_MACHINE_MODE];
12967 mode_index = (int) mode;
12969 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
12970 mode_index += MAX_MACHINE_MODE;
12972 if (types[mode_index] == NULL_TREE)
12973 types[mode_index] = build_vector_type_for_mode (type, mode);
12974 return types[mode_index];
12977 /* Return a type for 'const volatile void *'. */
12980 mips_build_cvpointer_type (void)
12984 if (cache == NULL_TREE)
12985 cache = build_pointer_type (build_qualified_type
12987 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
12991 /* Source-level argument types. */
12992 #define MIPS_ATYPE_VOID void_type_node
12993 #define MIPS_ATYPE_INT integer_type_node
12994 #define MIPS_ATYPE_POINTER ptr_type_node
12995 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12997 /* Standard mode-based argument types. */
12998 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12999 #define MIPS_ATYPE_SI intSI_type_node
13000 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13001 #define MIPS_ATYPE_DI intDI_type_node
13002 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13003 #define MIPS_ATYPE_SF float_type_node
13004 #define MIPS_ATYPE_DF double_type_node
13006 /* Vector argument types. */
13007 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13008 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13009 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13010 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13011 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13012 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13013 #define MIPS_ATYPE_UV2SI \
13014 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13015 #define MIPS_ATYPE_UV4HI \
13016 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13017 #define MIPS_ATYPE_UV8QI \
13018 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13020 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13021 their associated MIPS_ATYPEs. */
13022 #define MIPS_FTYPE_ATYPES1(A, B) \
13023 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13025 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13026 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13028 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13029 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13031 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13032 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13035 /* Return the function type associated with function prototype TYPE. */
13038 mips_build_function_type (enum mips_function_type type)
13040 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13042 if (types[(int) type] == NULL_TREE)
13045 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13046 case MIPS_FTYPE_NAME##NUM ARGS: \
13047 types[(int) type] \
13048 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13051 #include "config/mips/mips-ftypes.def"
13052 #undef DEF_MIPS_FTYPE
13054 gcc_unreachable ();
13057 return types[(int) type];
13060 /* Implement TARGET_INIT_BUILTINS. */
13063 mips_init_builtins (void)
13065 const struct mips_builtin_description *d;
13068 /* Iterate through all of the bdesc arrays, initializing all of the
13069 builtin functions. */
13070 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13072 d = &mips_builtins[i];
13074 add_builtin_function (d->name,
13075 mips_build_function_type (d->function_type),
13076 i, BUILT_IN_MD, NULL, NULL);
13080 /* Take argument ARGNO from EXP's argument list and convert it into a
13081 form suitable for input operand OPNO of instruction ICODE. Return the
13085 mips_prepare_builtin_arg (enum insn_code icode,
13086 unsigned int opno, tree exp, unsigned int argno)
13090 enum machine_mode mode;
13092 arg = CALL_EXPR_ARG (exp, argno);
13093 value = expand_normal (arg);
13094 mode = insn_data[icode].operand[opno].mode;
13095 if (!insn_data[icode].operand[opno].predicate (value, mode))
13097 /* We need to get the mode from ARG for two reasons:
13099 - to cope with address operands, where MODE is the mode of the
13100 memory, rather than of VALUE itself.
13102 - to cope with special predicates like pmode_register_operand,
13103 where MODE is VOIDmode. */
13104 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
13106 /* Check the predicate again. */
13107 if (!insn_data[icode].operand[opno].predicate (value, mode))
13109 error ("invalid argument to built-in function");
13117 /* Return an rtx suitable for output operand OP of instruction ICODE.
13118 If TARGET is non-null, try to use it where possible. */
13121 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
13123 enum machine_mode mode;
13125 mode = insn_data[icode].operand[op].mode;
13126 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
13127 target = gen_reg_rtx (mode);
13132 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13133 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13134 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13135 suggests a good place to put the result. */
13138 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13141 rtx ops[MAX_RECOG_OPERANDS];
13144 /* Map any target to operand 0. */
13148 target = mips_prepare_builtin_target (icode, opno, target);
13149 ops[opno] = target;
13153 /* Map the arguments to the other operands. The n_operands value
13154 for an expander includes match_dups and match_scratches as well as
13155 match_operands, so n_operands is only an upper bound on the number
13156 of arguments to the expander function. */
13157 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
13158 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
13159 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
13164 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
13168 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
13172 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
13176 gcc_unreachable ();
13181 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13182 function; TYPE says which. EXP is the CALL_EXPR that calls the
13183 function, ICODE is the instruction that should be used to compare
13184 the first two arguments, and COND is the condition it should test.
13185 TARGET, if nonnull, suggests a good place to put the result. */
13188 mips_expand_builtin_movtf (enum mips_builtin_type type,
13189 enum insn_code icode, enum mips_fp_condition cond,
13190 rtx target, tree exp)
13192 rtx cmp_result, op0, op1;
13194 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13195 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
13196 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
13197 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
13199 icode = CODE_FOR_mips_cond_move_tf_ps;
13200 target = mips_prepare_builtin_target (icode, 0, target);
13201 if (type == MIPS_BUILTIN_MOVT)
13203 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
13204 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
13208 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
13209 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
13211 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
13215 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13216 into TARGET otherwise. Return TARGET. */
13219 mips_builtin_branch_and_move (rtx condition, rtx target,
13220 rtx value_if_true, rtx value_if_false)
13222 rtx true_label, done_label;
13224 true_label = gen_label_rtx ();
13225 done_label = gen_label_rtx ();
13227 /* First assume that CONDITION is false. */
13228 mips_emit_move (target, value_if_false);
13230 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13231 emit_jump_insn (gen_condjump (condition, true_label));
13232 emit_jump_insn (gen_jump (done_label));
13235 /* Fix TARGET if CONDITION is true. */
13236 emit_label (true_label);
13237 mips_emit_move (target, value_if_true);
13239 emit_label (done_label);
13243 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13244 the CALL_EXPR that calls the function, ICODE is the code of the
13245 comparison instruction, and COND is the condition it should test.
13246 TARGET, if nonnull, suggests a good place to put the boolean result. */
13249 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13250 enum insn_code icode, enum mips_fp_condition cond,
13251 rtx target, tree exp)
13253 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
13256 if (target == 0 || GET_MODE (target) != SImode)
13257 target = gen_reg_rtx (SImode);
13259 /* The instruction should have a target operand, an operand for each
13260 argument, and an operand for COND. */
13261 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
13263 /* Prepare the operands to the comparison. */
13264 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13265 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13266 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
13268 switch (insn_data[icode].n_operands)
13271 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13276 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13277 args[2], args[3], GEN_INT (cond)));
13281 gcc_unreachable ();
13284 /* If the comparison sets more than one register, we define the result
13285 to be 0 if all registers are false and -1 if all registers are true.
13286 The value of the complete result is indeterminate otherwise. */
13287 switch (builtin_type)
13289 case MIPS_BUILTIN_CMP_ALL:
13290 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13291 return mips_builtin_branch_and_move (condition, target,
13292 const0_rtx, const1_rtx);
13294 case MIPS_BUILTIN_CMP_UPPER:
13295 case MIPS_BUILTIN_CMP_LOWER:
13296 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13297 condition = gen_single_cc (cmp_result, offset);
13298 return mips_builtin_branch_and_move (condition, target,
13299 const1_rtx, const0_rtx);
13302 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13303 return mips_builtin_branch_and_move (condition, target,
13304 const1_rtx, const0_rtx);
13308 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13309 if nonnull, suggests a good place to put the boolean result. */
13312 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13314 rtx condition, cmp_result;
13317 if (target == 0 || GET_MODE (target) != SImode)
13318 target = gen_reg_rtx (SImode);
13320 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13322 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13327 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13328 return mips_builtin_branch_and_move (condition, target,
13329 const1_rtx, const0_rtx);
13332 /* Implement TARGET_EXPAND_BUILTIN. */
13335 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13336 enum machine_mode mode, int ignore)
13339 unsigned int fcode, avail;
13340 const struct mips_builtin_description *d;
13342 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13343 fcode = DECL_FUNCTION_CODE (fndecl);
13344 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13345 d = &mips_builtins[fcode];
13346 avail = d->avail ();
13347 gcc_assert (avail != 0);
13350 error ("built-in function %qE not supported for MIPS16",
13351 DECL_NAME (fndecl));
13352 return ignore ? const0_rtx : CONST0_RTX (mode);
13354 switch (d->builtin_type)
13356 case MIPS_BUILTIN_DIRECT:
13357 return mips_expand_builtin_direct (d->icode, target, exp, true);
13359 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13360 return mips_expand_builtin_direct (d->icode, target, exp, false);
13362 case MIPS_BUILTIN_MOVT:
13363 case MIPS_BUILTIN_MOVF:
13364 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13365 d->cond, target, exp);
13367 case MIPS_BUILTIN_CMP_ANY:
13368 case MIPS_BUILTIN_CMP_ALL:
13369 case MIPS_BUILTIN_CMP_UPPER:
13370 case MIPS_BUILTIN_CMP_LOWER:
13371 case MIPS_BUILTIN_CMP_SINGLE:
13372 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13373 d->cond, target, exp);
13375 case MIPS_BUILTIN_BPOSGE32:
13376 return mips_expand_builtin_bposge (d->builtin_type, target);
13378 gcc_unreachable ();
13381 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13382 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13383 struct mips16_constant {
13384 struct mips16_constant *next;
13387 enum machine_mode mode;
13390 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13391 first constant, HIGHEST_ADDRESS is the highest address that the first
13392 byte of the pool can have, and INSN_ADDRESS is the current instruction
13394 struct mips16_constant_pool {
13395 struct mips16_constant *first;
13396 int highest_address;
13400 /* Add constant VALUE to POOL and return its label. MODE is the
13401 value's mode (used for CONST_INTs, etc.). */
13404 mips16_add_constant (struct mips16_constant_pool *pool,
13405 rtx value, enum machine_mode mode)
13407 struct mips16_constant **p, *c;
13408 bool first_of_size_p;
13410 /* See whether the constant is already in the pool. If so, return the
13411 existing label, otherwise leave P pointing to the place where the
13412 constant should be added.
13414 Keep the pool sorted in increasing order of mode size so that we can
13415 reduce the number of alignments needed. */
13416 first_of_size_p = true;
13417 for (p = &pool->first; *p != 0; p = &(*p)->next)
13419 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13420 return (*p)->label;
13421 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13423 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13424 first_of_size_p = false;
13427 /* In the worst case, the constant needed by the earliest instruction
13428 will end up at the end of the pool. The entire pool must then be
13429 accessible from that instruction.
13431 When adding the first constant, set the pool's highest address to
13432 the address of the first out-of-range byte. Adjust this address
13433 downwards each time a new constant is added. */
13434 if (pool->first == 0)
13435 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13436 of the instruction with the lowest two bits clear. The base PC
13437 value for LDPC has the lowest three bits clear. Assume the worst
13438 case here; namely that the PC-relative instruction occupies the
13439 last 2 bytes in an aligned word. */
13440 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13441 pool->highest_address -= GET_MODE_SIZE (mode);
13442 if (first_of_size_p)
13443 /* Take into account the worst possible padding due to alignment. */
13444 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13446 /* Create a new entry. */
13447 c = XNEW (struct mips16_constant);
13450 c->label = gen_label_rtx ();
13457 /* Output constant VALUE after instruction INSN and return the last
13458 instruction emitted. MODE is the mode of the constant. */
13461 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13463 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13465 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13466 return emit_insn_after (gen_consttable_int (value, size), insn);
13469 if (SCALAR_FLOAT_MODE_P (mode))
13470 return emit_insn_after (gen_consttable_float (value), insn);
13472 if (VECTOR_MODE_P (mode))
13476 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13477 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13478 CONST_VECTOR_ELT (value, i), insn);
13482 gcc_unreachable ();
13485 /* Dump out the constants in CONSTANTS after INSN. */
13488 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13490 struct mips16_constant *c, *next;
13494 for (c = constants; c != NULL; c = next)
13496 /* If necessary, increase the alignment of PC. */
13497 if (align < GET_MODE_SIZE (c->mode))
13499 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13500 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13502 align = GET_MODE_SIZE (c->mode);
13504 insn = emit_label_after (c->label, insn);
13505 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13511 emit_barrier_after (insn);
13514 /* Return the length of instruction INSN. */
13517 mips16_insn_length (rtx insn)
13521 rtx body = PATTERN (insn);
13522 if (GET_CODE (body) == ADDR_VEC)
13523 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13524 if (GET_CODE (body) == ADDR_DIFF_VEC)
13525 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13527 return get_attr_length (insn);
13530 /* If *X is a symbolic constant that refers to the constant pool, add
13531 the constant to POOL and rewrite *X to use the constant's label. */
13534 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13536 rtx base, offset, label;
13538 split_const (*x, &base, &offset);
13539 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13541 label = mips16_add_constant (pool, get_pool_constant (base),
13542 get_pool_mode (base));
13543 base = gen_rtx_LABEL_REF (Pmode, label);
13544 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13548 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13549 INSN is the instruction we're rewriting and POOL points to the current
13551 struct mips16_rewrite_pool_refs_info {
13553 struct mips16_constant_pool *pool;
13556 /* Rewrite *X so that constant pool references refer to the constant's
13557 label instead. DATA points to a mips16_rewrite_pool_refs_info
13561 mips16_rewrite_pool_refs (rtx *x, void *data)
13563 struct mips16_rewrite_pool_refs_info *info =
13564 (struct mips16_rewrite_pool_refs_info *) data;
13566 if (force_to_mem_operand (*x, Pmode))
13568 rtx mem = force_const_mem (GET_MODE (*x), *x);
13569 validate_change (info->insn, x, mem, false);
13574 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13578 if (TARGET_MIPS16_TEXT_LOADS)
13579 mips16_rewrite_pool_constant (info->pool, x);
13581 return GET_CODE (*x) == CONST ? -1 : 0;
13584 /* Return whether CFG is used in mips_reorg. */
13587 mips_cfg_in_reorg (void)
13589 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13590 || TARGET_RELAX_PIC_CALLS);
13593 /* Build MIPS16 constant pools. */
13596 mips16_lay_out_constants (void)
13598 struct mips16_constant_pool pool;
13599 struct mips16_rewrite_pool_refs_info info;
13602 if (!TARGET_MIPS16_PCREL_LOADS)
13605 if (mips_cfg_in_reorg ())
13606 split_all_insns ();
13608 split_all_insns_noflow ();
13610 memset (&pool, 0, sizeof (pool));
13611 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13613 /* Rewrite constant pool references in INSN. */
13614 if (USEFUL_INSN_P (insn))
13618 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13621 pool.insn_address += mips16_insn_length (insn);
13623 if (pool.first != NULL)
13625 /* If there are no natural barriers between the first user of
13626 the pool and the highest acceptable address, we'll need to
13627 create a new instruction to jump around the constant pool.
13628 In the worst case, this instruction will be 4 bytes long.
13630 If it's too late to do this transformation after INSN,
13631 do it immediately before INSN. */
13632 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13636 label = gen_label_rtx ();
13638 jump = emit_jump_insn_before (gen_jump (label), insn);
13639 JUMP_LABEL (jump) = label;
13640 LABEL_NUSES (label) = 1;
13641 barrier = emit_barrier_after (jump);
13643 emit_label_after (label, barrier);
13644 pool.insn_address += 4;
13647 /* See whether the constant pool is now out of range of the first
13648 user. If so, output the constants after the previous barrier.
13649 Note that any instructions between BARRIER and INSN (inclusive)
13650 will use negative offsets to refer to the pool. */
13651 if (pool.insn_address > pool.highest_address)
13653 mips16_emit_constants (pool.first, barrier);
13657 else if (BARRIER_P (insn))
13661 mips16_emit_constants (pool.first, get_last_insn ());
13664 /* Return true if it is worth r10k_simplify_address's while replacing
13665 an address with X. We are looking for constants, and for addresses
13666 at a known offset from the incoming stack pointer. */
13669 r10k_simplified_address_p (rtx x)
13671 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13673 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13676 /* X is an expression that appears in INSN. Try to use the UD chains
13677 to simplify it, returning the simplified form on success and the
13678 original form otherwise. Replace the incoming value of $sp with
13679 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13682 r10k_simplify_address (rtx x, rtx insn)
13684 rtx newx, op0, op1, set, def_insn, note;
13686 struct df_link *defs;
13691 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13692 if (op0 != XEXP (x, 0))
13693 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13694 op0, GET_MODE (XEXP (x, 0)));
13696 else if (BINARY_P (x))
13698 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13699 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13700 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13701 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13703 else if (GET_CODE (x) == LO_SUM)
13705 /* LO_SUMs can be offset from HIGHs, if we know they won't
13706 overflow. See mips_classify_address for the rationale behind
13708 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13709 if (GET_CODE (op0) == HIGH)
13710 newx = XEXP (x, 1);
13712 else if (REG_P (x))
13714 /* Uses are recorded by regno_reg_rtx, not X itself. */
13715 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13717 defs = DF_REF_CHAIN (use);
13719 /* Require a single definition. */
13720 if (defs && defs->next == NULL)
13723 if (DF_REF_IS_ARTIFICIAL (def))
13725 /* Replace the incoming value of $sp with
13726 virtual_incoming_args_rtx. */
13727 if (x == stack_pointer_rtx
13728 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13729 newx = virtual_incoming_args_rtx;
13731 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13734 /* Make sure that DEF_INSN is a single set of REG. */
13735 def_insn = DF_REF_INSN (def);
13736 if (NONJUMP_INSN_P (def_insn))
13738 set = single_set (def_insn);
13739 if (set && rtx_equal_p (SET_DEST (set), x))
13741 /* Prefer to use notes, since the def-use chains
13742 are often shorter. */
13743 note = find_reg_equal_equiv_note (def_insn);
13745 newx = XEXP (note, 0);
13747 newx = SET_SRC (set);
13748 newx = r10k_simplify_address (newx, def_insn);
13754 if (newx && r10k_simplified_address_p (newx))
13759 /* Return true if ADDRESS is known to be an uncached address
13760 on R10K systems. */
13763 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13765 unsigned HOST_WIDE_INT upper;
13767 /* Check for KSEG1. */
13768 if (address + 0x60000000 < 0x20000000)
13771 /* Check for uncached XKPHYS addresses. */
13772 if (Pmode == DImode)
13774 upper = (address >> 40) & 0xf9ffff;
13775 if (upper == 0x900000 || upper == 0xb80000)
13781 /* Return true if we can prove that an access to address X in instruction
13782 INSN would be safe from R10K speculation. This X is a general
13783 expression; it might not be a legitimate address. */
13786 r10k_safe_address_p (rtx x, rtx insn)
13789 HOST_WIDE_INT offset_val;
13791 x = r10k_simplify_address (x, insn);
13793 /* Check for references to the stack frame. It doesn't really matter
13794 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13795 allows us to assume that accesses to any part of the eventual frame
13796 is safe from speculation at any point in the function. */
13797 mips_split_plus (x, &base, &offset_val);
13798 if (base == virtual_incoming_args_rtx
13799 && offset_val >= -cfun->machine->frame.total_size
13800 && offset_val < cfun->machine->frame.args_size)
13803 /* Check for uncached addresses. */
13804 if (CONST_INT_P (x))
13805 return r10k_uncached_address_p (INTVAL (x));
13807 /* Check for accesses to a static object. */
13808 split_const (x, &base, &offset);
13809 return offset_within_block_p (base, INTVAL (offset));
13812 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13813 an in-range access to an automatic variable, or to an object with
13814 a link-time-constant address. */
13817 r10k_safe_mem_expr_p (tree expr, rtx offset)
13819 if (expr == NULL_TREE
13820 || offset == NULL_RTX
13821 || !CONST_INT_P (offset)
13822 || INTVAL (offset) < 0
13823 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13826 while (TREE_CODE (expr) == COMPONENT_REF)
13828 expr = TREE_OPERAND (expr, 0);
13829 if (expr == NULL_TREE)
13833 return DECL_P (expr);
13836 /* A for_each_rtx callback for which DATA points to the instruction
13837 containing *X. Stop the search if we find a MEM that is not safe
13838 from R10K speculation. */
13841 r10k_needs_protection_p_1 (rtx *loc, void *data)
13849 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13852 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13858 /* A note_stores callback for which DATA points to an instruction pointer.
13859 If *DATA is nonnull, make it null if it X contains a MEM that is not
13860 safe from R10K speculation. */
13863 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13868 insn_ptr = (rtx *) data;
13869 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13870 *insn_ptr = NULL_RTX;
13873 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13874 Return nonzero if the call is not to a declared function. */
13877 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13886 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13892 /* Return true if instruction INSN needs to be protected by an R10K
13896 r10k_needs_protection_p (rtx insn)
13899 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13901 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13903 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13904 return insn == NULL_RTX;
13907 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
13910 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13911 edge is unconditional. */
13914 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
13919 FOR_EACH_EDGE (e, ei, bb->preds)
13920 if (!single_succ_p (e->src)
13921 || !TEST_BIT (protected_bbs, e->src->index)
13922 || (e->flags & EDGE_COMPLEX) != 0)
13927 /* Implement -mr10k-cache-barrier= for the current function. */
13930 r10k_insert_cache_barriers (void)
13932 int *rev_post_order;
13935 sbitmap protected_bbs;
13936 rtx insn, end, unprotected_region;
13940 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
13944 /* Calculate dominators. */
13945 calculate_dominance_info (CDI_DOMINATORS);
13947 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
13948 X is protected by a cache barrier. */
13949 protected_bbs = sbitmap_alloc (last_basic_block);
13950 sbitmap_zero (protected_bbs);
13952 /* Iterate over the basic blocks in reverse post-order. */
13953 rev_post_order = XNEWVEC (int, last_basic_block);
13954 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
13955 for (i = 0; i < n; i++)
13957 bb = BASIC_BLOCK (rev_post_order[i]);
13959 /* If this block is only reached by unconditional edges, and if the
13960 source of every edge is protected, the beginning of the block is
13962 if (r10k_protected_bb_p (bb, protected_bbs))
13963 unprotected_region = NULL_RTX;
13965 unprotected_region = pc_rtx;
13966 end = NEXT_INSN (BB_END (bb));
13968 /* UNPROTECTED_REGION is:
13970 - null if we are processing a protected region,
13971 - pc_rtx if we are processing an unprotected region but have
13972 not yet found the first instruction in it
13973 - the first instruction in an unprotected region otherwise. */
13974 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
13976 if (unprotected_region && USEFUL_INSN_P (insn))
13978 if (recog_memoized (insn) == CODE_FOR_mips_cache)
13979 /* This CACHE instruction protects the following code. */
13980 unprotected_region = NULL_RTX;
13983 /* See if INSN is the first instruction in this
13984 unprotected region. */
13985 if (unprotected_region == pc_rtx)
13986 unprotected_region = insn;
13988 /* See if INSN needs to be protected. If so,
13989 we must insert a cache barrier somewhere between
13990 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13991 clear which position is better performance-wise,
13992 but as a tie-breaker, we assume that it is better
13993 to allow delay slots to be back-filled where
13994 possible, and that it is better not to insert
13995 barriers in the middle of already-scheduled code.
13996 We therefore insert the barrier at the beginning
13998 if (r10k_needs_protection_p (insn))
14000 emit_insn_before (gen_r10k_cache_barrier (),
14001 unprotected_region);
14002 unprotected_region = NULL_RTX;
14008 /* The called function is not required to protect the exit path.
14009 The code that follows a call is therefore unprotected. */
14010 unprotected_region = pc_rtx;
14013 /* Record whether the end of this block is protected. */
14014 if (unprotected_region == NULL_RTX)
14015 SET_BIT (protected_bbs, bb->index);
14017 XDELETEVEC (rev_post_order);
14019 sbitmap_free (protected_bbs);
14021 free_dominance_info (CDI_DOMINATORS);
14024 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14025 otherwise. If INSN has two call rtx, then store the second one in
14029 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14034 if (!CALL_P (insn))
14037 x = PATTERN (insn);
14038 if (GET_CODE (x) == PARALLEL)
14040 /* Calls returning complex values have two CALL rtx. Look for the second
14041 one here, and return it via the SECOND_CALL arg. */
14042 x2 = XVECEXP (x, 0, 1);
14043 if (GET_CODE (x2) == SET)
14045 if (GET_CODE (x2) == CALL)
14048 x = XVECEXP (x, 0, 0);
14050 if (GET_CODE (x) == SET)
14052 gcc_assert (GET_CODE (x) == CALL);
14057 /* REG is set in DEF. See if the definition is one of the ways we load a
14058 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
14059 it is return the symbol reference of the function, otherwise return
14063 mips_pic_call_symbol_from_set (df_ref def, rtx reg)
14067 if (DF_REF_IS_ARTIFICIAL (def))
14070 def_insn = DF_REF_INSN (def);
14071 set = single_set (def_insn);
14072 if (set && rtx_equal_p (SET_DEST (set), reg))
14074 rtx note, src, symbol;
14076 /* First, look at REG_EQUAL/EQUIV notes. */
14077 note = find_reg_equal_equiv_note (def_insn);
14078 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14079 return XEXP (note, 0);
14081 /* For %call16 references we don't have REG_EQUAL. */
14082 src = SET_SRC (set);
14083 symbol = mips_strip_unspec_call (src);
14086 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14090 /* Follow simple register copies. */
14092 return mips_find_pic_call_symbol (def_insn, src);
14098 /* Find the definition of the use of REG in INSN. See if the definition is
14099 one of the ways we load a register with a symbol address for a
14100 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14101 the function, otherwise return NULL_RTX. */
14104 mips_find_pic_call_symbol (rtx insn, rtx reg)
14107 struct df_link *defs;
14110 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14113 defs = DF_REF_CHAIN (use);
14116 symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
14120 /* If we have more than one definition, they need to be identical. */
14121 for (defs = defs->next; defs; defs = defs->next)
14125 other = mips_pic_call_symbol_from_set (defs->ref, reg);
14126 if (!rtx_equal_p (symbol, other))
14133 /* Replace the args_size operand of the call expression CALL with the
14134 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14137 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14141 args_size = XEXP (call, 1);
14142 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14143 gen_rtvec (2, args_size, symbol),
14147 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14148 if instead of the arg_size argument it contains the call attributes. If
14149 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14150 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14154 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14156 rtx args_size, symbol;
14158 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14161 args_size = operands[args_size_opno];
14162 if (GET_CODE (args_size) != UNSPEC)
14164 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14166 symbol = XVECEXP (args_size, 0, 1);
14167 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14169 operands[args_size_opno] = symbol;
14173 /* Use DF to annotate PIC indirect calls with the function symbol they
14177 mips_annotate_pic_calls (void)
14183 FOR_BB_INSNS (bb, insn)
14185 rtx call, reg, symbol, second_call;
14188 call = mips_call_expr_from_insn (insn, &second_call);
14191 gcc_assert (MEM_P (XEXP (call, 0)));
14192 reg = XEXP (XEXP (call, 0), 0);
14196 symbol = mips_find_pic_call_symbol (insn, reg);
14199 mips_annotate_pic_call_expr (call, symbol);
14201 mips_annotate_pic_call_expr (second_call, symbol);
14206 /* A temporary variable used by for_each_rtx callbacks, etc. */
14207 static rtx mips_sim_insn;
14209 /* A structure representing the state of the processor pipeline.
14210 Used by the mips_sim_* family of functions. */
14212 /* The maximum number of instructions that can be issued in a cycle.
14213 (Caches mips_issue_rate.) */
14214 unsigned int issue_rate;
14216 /* The current simulation time. */
14219 /* How many more instructions can be issued in the current cycle. */
14220 unsigned int insns_left;
14222 /* LAST_SET[X].INSN is the last instruction to set register X.
14223 LAST_SET[X].TIME is the time at which that instruction was issued.
14224 INSN is null if no instruction has yet set register X. */
14228 } last_set[FIRST_PSEUDO_REGISTER];
14230 /* The pipeline's current DFA state. */
14234 /* Reset STATE to the initial simulation state. */
14237 mips_sim_reset (struct mips_sim *state)
14240 state->insns_left = state->issue_rate;
14241 memset (&state->last_set, 0, sizeof (state->last_set));
14242 state_reset (state->dfa_state);
14245 /* Initialize STATE before its first use. DFA_STATE points to an
14246 allocated but uninitialized DFA state. */
14249 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14251 state->issue_rate = mips_issue_rate ();
14252 state->dfa_state = dfa_state;
14253 mips_sim_reset (state);
14256 /* Advance STATE by one clock cycle. */
14259 mips_sim_next_cycle (struct mips_sim *state)
14262 state->insns_left = state->issue_rate;
14263 state_transition (state->dfa_state, 0);
14266 /* Advance simulation state STATE until instruction INSN can read
14270 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14272 unsigned int regno, end_regno;
14274 end_regno = END_REGNO (reg);
14275 for (regno = REGNO (reg); regno < end_regno; regno++)
14276 if (state->last_set[regno].insn != 0)
14280 t = (state->last_set[regno].time
14281 + insn_latency (state->last_set[regno].insn, insn));
14282 while (state->time < t)
14283 mips_sim_next_cycle (state);
14287 /* A for_each_rtx callback. If *X is a register, advance simulation state
14288 DATA until mips_sim_insn can read the register's value. */
14291 mips_sim_wait_regs_2 (rtx *x, void *data)
14294 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14298 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14301 mips_sim_wait_regs_1 (rtx *x, void *data)
14303 for_each_rtx (x, mips_sim_wait_regs_2, data);
14306 /* Advance simulation state STATE until all of INSN's register
14307 dependencies are satisfied. */
14310 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14312 mips_sim_insn = insn;
14313 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14316 /* Advance simulation state STATE until the units required by
14317 instruction INSN are available. */
14320 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14324 tmp_state = alloca (state_size ());
14325 while (state->insns_left == 0
14326 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14327 state_transition (tmp_state, insn) >= 0))
14328 mips_sim_next_cycle (state);
14331 /* Advance simulation state STATE until INSN is ready to issue. */
14334 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14336 mips_sim_wait_regs (state, insn);
14337 mips_sim_wait_units (state, insn);
14340 /* mips_sim_insn has just set X. Update the LAST_SET array
14341 in simulation state DATA. */
14344 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14346 struct mips_sim *state;
14348 state = (struct mips_sim *) data;
14351 unsigned int regno, end_regno;
14353 end_regno = END_REGNO (x);
14354 for (regno = REGNO (x); regno < end_regno; regno++)
14356 state->last_set[regno].insn = mips_sim_insn;
14357 state->last_set[regno].time = state->time;
14362 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14363 can issue immediately (i.e., that mips_sim_wait_insn has already
14367 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14369 state_transition (state->dfa_state, insn);
14370 state->insns_left--;
14372 mips_sim_insn = insn;
14373 note_stores (PATTERN (insn), mips_sim_record_set, state);
14376 /* Simulate issuing a NOP in state STATE. */
14379 mips_sim_issue_nop (struct mips_sim *state)
14381 if (state->insns_left == 0)
14382 mips_sim_next_cycle (state);
14383 state->insns_left--;
14386 /* Update simulation state STATE so that it's ready to accept the instruction
14387 after INSN. INSN should be part of the main rtl chain, not a member of a
14391 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14393 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14395 mips_sim_issue_nop (state);
14397 switch (GET_CODE (SEQ_BEGIN (insn)))
14401 /* We can't predict the processor state after a call or label. */
14402 mips_sim_reset (state);
14406 /* The delay slots of branch likely instructions are only executed
14407 when the branch is taken. Therefore, if the caller has simulated
14408 the delay slot instruction, STATE does not really reflect the state
14409 of the pipeline for the instruction after the delay slot. Also,
14410 branch likely instructions tend to incur a penalty when not taken,
14411 so there will probably be an extra delay between the branch and
14412 the instruction after the delay slot. */
14413 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14414 mips_sim_reset (state);
14422 /* The VR4130 pipeline issues aligned pairs of instructions together,
14423 but it stalls the second instruction if it depends on the first.
14424 In order to cut down the amount of logic required, this dependence
14425 check is not based on a full instruction decode. Instead, any non-SPECIAL
14426 instruction is assumed to modify the register specified by bits 20-16
14427 (which is usually the "rt" field).
14429 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14430 input, so we can end up with a false dependence between the branch
14431 and its delay slot. If this situation occurs in instruction INSN,
14432 try to avoid it by swapping rs and rt. */
14435 vr4130_avoid_branch_rt_conflict (rtx insn)
14439 first = SEQ_BEGIN (insn);
14440 second = SEQ_END (insn);
14442 && NONJUMP_INSN_P (second)
14443 && GET_CODE (PATTERN (first)) == SET
14444 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14445 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14447 /* Check for the right kind of condition. */
14448 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14449 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14450 && REG_P (XEXP (cond, 0))
14451 && REG_P (XEXP (cond, 1))
14452 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14453 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14455 /* SECOND mentions the rt register but not the rs register. */
14456 rtx tmp = XEXP (cond, 0);
14457 XEXP (cond, 0) = XEXP (cond, 1);
14458 XEXP (cond, 1) = tmp;
14463 /* Implement -mvr4130-align. Go through each basic block and simulate the
14464 processor pipeline. If we find that a pair of instructions could execute
14465 in parallel, and the first of those instructions is not 8-byte aligned,
14466 insert a nop to make it aligned. */
14469 vr4130_align_insns (void)
14471 struct mips_sim state;
14472 rtx insn, subinsn, last, last2, next;
14477 /* LAST is the last instruction before INSN to have a nonzero length.
14478 LAST2 is the last such instruction before LAST. */
14482 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14485 mips_sim_init (&state, alloca (state_size ()));
14486 for (insn = get_insns (); insn != 0; insn = next)
14488 unsigned int length;
14490 next = NEXT_INSN (insn);
14492 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14493 This isn't really related to the alignment pass, but we do it on
14494 the fly to avoid a separate instruction walk. */
14495 vr4130_avoid_branch_rt_conflict (insn);
14497 if (USEFUL_INSN_P (insn))
14498 FOR_EACH_SUBINSN (subinsn, insn)
14500 mips_sim_wait_insn (&state, subinsn);
14502 /* If we want this instruction to issue in parallel with the
14503 previous one, make sure that the previous instruction is
14504 aligned. There are several reasons why this isn't worthwhile
14505 when the second instruction is a call:
14507 - Calls are less likely to be performance critical,
14508 - There's a good chance that the delay slot can execute
14509 in parallel with the call.
14510 - The return address would then be unaligned.
14512 In general, if we're going to insert a nop between instructions
14513 X and Y, it's better to insert it immediately after X. That
14514 way, if the nop makes Y aligned, it will also align any labels
14515 between X and Y. */
14516 if (state.insns_left != state.issue_rate
14517 && !CALL_P (subinsn))
14519 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14521 /* SUBINSN is the first instruction in INSN and INSN is
14522 aligned. We want to align the previous instruction
14523 instead, so insert a nop between LAST2 and LAST.
14525 Note that LAST could be either a single instruction
14526 or a branch with a delay slot. In the latter case,
14527 LAST, like INSN, is already aligned, but the delay
14528 slot must have some extra delay that stops it from
14529 issuing at the same time as the branch. We therefore
14530 insert a nop before the branch in order to align its
14532 emit_insn_after (gen_nop (), last2);
14535 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14537 /* SUBINSN is the delay slot of INSN, but INSN is
14538 currently unaligned. Insert a nop between
14539 LAST and INSN to align it. */
14540 emit_insn_after (gen_nop (), last);
14544 mips_sim_issue_insn (&state, subinsn);
14546 mips_sim_finish_insn (&state, insn);
14548 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14549 length = get_attr_length (insn);
14552 /* If the instruction is an asm statement or multi-instruction
14553 mips.md patern, the length is only an estimate. Insert an
14554 8 byte alignment after it so that the following instructions
14555 can be handled correctly. */
14556 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14557 && (recog_memoized (insn) < 0 || length >= 8))
14559 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14560 next = NEXT_INSN (next);
14561 mips_sim_next_cycle (&state);
14564 else if (length & 4)
14565 aligned_p = !aligned_p;
14570 /* See whether INSN is an aligned label. */
14571 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14577 /* This structure records that the current function has a LO_SUM
14578 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14579 the largest offset applied to BASE by all such LO_SUMs. */
14580 struct mips_lo_sum_offset {
14582 HOST_WIDE_INT offset;
14585 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14588 mips_hash_base (rtx base)
14590 int do_not_record_p;
14592 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14595 /* Hash-table callbacks for mips_lo_sum_offsets. */
14598 mips_lo_sum_offset_hash (const void *entry)
14600 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14604 mips_lo_sum_offset_eq (const void *entry, const void *value)
14606 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14607 (const_rtx) value);
14610 /* Look up symbolic constant X in HTAB, which is a hash table of
14611 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14612 paired with a recorded LO_SUM, otherwise record X in the table. */
14615 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14619 struct mips_lo_sum_offset *entry;
14621 /* Split X into a base and offset. */
14622 split_const (x, &base, &offset);
14623 if (UNSPEC_ADDRESS_P (base))
14624 base = UNSPEC_ADDRESS (base);
14626 /* Look up the base in the hash table. */
14627 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14631 entry = (struct mips_lo_sum_offset *) *slot;
14632 if (option == INSERT)
14636 entry = XNEW (struct mips_lo_sum_offset);
14637 entry->base = base;
14638 entry->offset = INTVAL (offset);
14643 if (INTVAL (offset) > entry->offset)
14644 entry->offset = INTVAL (offset);
14647 return INTVAL (offset) <= entry->offset;
14650 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14651 Record every LO_SUM in *LOC. */
14654 mips_record_lo_sum (rtx *loc, void *data)
14656 if (GET_CODE (*loc) == LO_SUM)
14657 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14661 /* Return true if INSN is a SET of an orphaned high-part relocation.
14662 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14663 LO_SUMs in the current function. */
14666 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14668 enum mips_symbol_type type;
14671 set = single_set (insn);
14674 /* Check for %his. */
14676 if (GET_CODE (x) == HIGH
14677 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14678 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14680 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14681 if (GET_CODE (x) == UNSPEC
14682 && XINT (x, 1) == UNSPEC_LOAD_GOT
14683 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14684 SYMBOL_CONTEXT_LEA, &type)
14685 && type == SYMBOL_GOTOFF_PAGE)
14686 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14691 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14692 INSN and a previous instruction, avoid it by inserting nops after
14695 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14696 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14697 before using the value of that register. *HILO_DELAY counts the
14698 number of instructions since the last hilo hazard (that is,
14699 the number of instructions since the last MFLO or MFHI).
14701 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14702 for the next instruction.
14704 LO_REG is an rtx for the LO register, used in dependence checking. */
14707 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14708 rtx *delayed_reg, rtx lo_reg)
14713 pattern = PATTERN (insn);
14715 /* Do not put the whole function in .set noreorder if it contains
14716 an asm statement. We don't know whether there will be hazards
14717 between the asm statement and the gcc-generated code. */
14718 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14719 cfun->machine->all_noreorder_p = false;
14721 /* Ignore zero-length instructions (barriers and the like). */
14722 ninsns = get_attr_length (insn) / 4;
14726 /* Work out how many nops are needed. Note that we only care about
14727 registers that are explicitly mentioned in the instruction's pattern.
14728 It doesn't matter that calls use the argument registers or that they
14729 clobber hi and lo. */
14730 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14731 nops = 2 - *hilo_delay;
14732 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14737 /* Insert the nops between this instruction and the previous one.
14738 Each new nop takes us further from the last hilo hazard. */
14739 *hilo_delay += nops;
14741 emit_insn_after (gen_hazard_nop (), after);
14743 /* Set up the state for the next instruction. */
14744 *hilo_delay += ninsns;
14746 if (INSN_CODE (insn) >= 0)
14747 switch (get_attr_hazard (insn))
14757 set = single_set (insn);
14759 *delayed_reg = SET_DEST (set);
14764 /* Go through the instruction stream and insert nops where necessary.
14765 Also delete any high-part relocations whose partnering low parts
14766 are now all dead. See if the whole function can then be put into
14767 .set noreorder and .set nomacro. */
14770 mips_reorg_process_insns (void)
14772 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14776 /* Force all instructions to be split into their final form. */
14777 split_all_insns_noflow ();
14779 /* Recalculate instruction lengths without taking nops into account. */
14780 cfun->machine->ignore_hazard_length_p = true;
14781 shorten_branches (get_insns ());
14783 cfun->machine->all_noreorder_p = true;
14785 /* We don't track MIPS16 PC-relative offsets closely enough to make
14786 a good job of "set .noreorder" code in MIPS16 mode. */
14788 cfun->machine->all_noreorder_p = false;
14790 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14791 if (!TARGET_EXPLICIT_RELOCS)
14792 cfun->machine->all_noreorder_p = false;
14794 /* Profiled functions can't be all noreorder because the profiler
14795 support uses assembler macros. */
14797 cfun->machine->all_noreorder_p = false;
14799 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14800 we rely on the assembler to work around some errata. */
14801 if (TARGET_FIX_VR4120)
14802 cfun->machine->all_noreorder_p = false;
14804 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14805 MFHI instructions. Note that we avoid using MFLO and MFHI if
14806 the VR4130 MACC and DMACC instructions are available instead;
14807 see the *mfhilo_{si,di}_macc patterns. */
14808 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14809 cfun->machine->all_noreorder_p = false;
14811 htab = htab_create (37, mips_lo_sum_offset_hash,
14812 mips_lo_sum_offset_eq, free);
14814 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14815 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14816 FOR_EACH_SUBINSN (subinsn, insn)
14817 if (USEFUL_INSN_P (subinsn))
14818 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14823 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14825 /* Make a second pass over the instructions. Delete orphaned
14826 high-part relocations or turn them into NOPs. Avoid hazards
14827 by inserting NOPs. */
14828 for (insn = get_insns (); insn != 0; insn = next_insn)
14830 next_insn = NEXT_INSN (insn);
14831 if (USEFUL_INSN_P (insn))
14833 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14835 /* If we find an orphaned high-part relocation in a delay
14836 slot, it's easier to turn that instruction into a NOP than
14837 to delete it. The delay slot will be a NOP either way. */
14838 FOR_EACH_SUBINSN (subinsn, insn)
14839 if (INSN_P (subinsn))
14841 if (mips_orphaned_high_part_p (htab, subinsn))
14843 PATTERN (subinsn) = gen_nop ();
14844 INSN_CODE (subinsn) = CODE_FOR_nop;
14846 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14847 &delayed_reg, lo_reg);
14853 /* INSN is a single instruction. Delete it if it's an
14854 orphaned high-part relocation. */
14855 if (mips_orphaned_high_part_p (htab, insn))
14856 delete_insn (insn);
14857 /* Also delete cache barriers if the last instruction
14858 was an annulled branch. INSN will not be speculatively
14860 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14862 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14863 delete_insn (insn);
14866 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14867 &delayed_reg, lo_reg);
14874 htab_delete (htab);
14877 /* If we are using a GOT, but have not decided to use a global pointer yet,
14878 see whether we need one to implement long branches. Convert the ghost
14879 global-pointer instructions into real ones if so. */
14882 mips_expand_ghost_gp_insns (void)
14887 /* Quick exit if we already know that we will or won't need a
14889 if (!TARGET_USE_GOT
14890 || cfun->machine->global_pointer == INVALID_REGNUM
14891 || mips_must_initialize_gp_p ())
14894 shorten_branches (get_insns ());
14896 /* Look for a branch that is longer than normal. The normal length for
14897 non-MIPS16 branches is 8, because the length includes the delay slot.
14898 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14899 but they have no delay slot. */
14900 normal_length = (TARGET_MIPS16 ? 4 : 8);
14901 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14903 && USEFUL_INSN_P (insn)
14904 && get_attr_length (insn) > normal_length)
14907 if (insn == NULL_RTX)
14910 /* We've now established that we need $gp. */
14911 cfun->machine->must_initialize_gp_p = true;
14912 split_all_insns_noflow ();
14917 /* Subroutine of mips_reorg to manage passes that require DF. */
14920 mips_df_reorg (void)
14922 /* Create def-use chains. */
14923 df_set_flags (DF_EQ_NOTES);
14924 df_chain_add_problem (DF_UD_CHAIN);
14927 if (TARGET_RELAX_PIC_CALLS)
14928 mips_annotate_pic_calls ();
14930 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
14931 r10k_insert_cache_barriers ();
14933 df_finish_pass (false);
14936 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
14941 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
14942 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
14943 to date if the CFG is available. */
14944 if (mips_cfg_in_reorg ())
14945 compute_bb_for_insn ();
14946 mips16_lay_out_constants ();
14947 if (mips_cfg_in_reorg ())
14950 free_bb_for_insn ();
14953 if (optimize > 0 && flag_delayed_branch)
14954 dbr_schedule (get_insns ());
14955 mips_reorg_process_insns ();
14957 && TARGET_EXPLICIT_RELOCS
14959 && TARGET_VR4130_ALIGN)
14960 vr4130_align_insns ();
14961 if (mips_expand_ghost_gp_insns ())
14962 /* The expansion could invalidate some of the VR4130 alignment
14963 optimizations, but this should be an extremely rare case anyhow. */
14964 mips_reorg_process_insns ();
14967 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
14968 in order to avoid duplicating too much logic from elsewhere. */
14971 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14972 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14975 rtx this_rtx, temp1, temp2, insn, fnaddr;
14976 bool use_sibcall_p;
14978 /* Pretend to be a post-reload pass while generating rtl. */
14979 reload_completed = 1;
14981 /* Mark the end of the (empty) prologue. */
14982 emit_note (NOTE_INSN_PROLOGUE_END);
14984 /* Determine if we can use a sibcall to call FUNCTION directly. */
14985 fnaddr = XEXP (DECL_RTL (function), 0);
14986 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
14987 && const_call_insn_operand (fnaddr, Pmode));
14989 /* Determine if we need to load FNADDR from the GOT. */
14991 && (mips_got_symbol_type_p
14992 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
14994 /* Pick a global pointer. Use a call-clobbered register if
14995 TARGET_CALL_SAVED_GP. */
14996 cfun->machine->global_pointer
14997 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
14998 cfun->machine->must_initialize_gp_p = true;
14999 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15001 /* Set up the global pointer for n32 or n64 abicalls. */
15002 mips_emit_loadgp ();
15005 /* We need two temporary registers in some cases. */
15006 temp1 = gen_rtx_REG (Pmode, 2);
15007 temp2 = gen_rtx_REG (Pmode, 3);
15009 /* Find out which register contains the "this" pointer. */
15010 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15011 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15013 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15015 /* Add DELTA to THIS_RTX. */
15018 rtx offset = GEN_INT (delta);
15019 if (!SMALL_OPERAND (delta))
15021 mips_emit_move (temp1, offset);
15024 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15027 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15028 if (vcall_offset != 0)
15032 /* Set TEMP1 to *THIS_RTX. */
15033 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15035 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15036 addr = mips_add_offset (temp2, temp1, vcall_offset);
15038 /* Load the offset and add it to THIS_RTX. */
15039 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15040 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15043 /* Jump to the target function. Use a sibcall if direct jumps are
15044 allowed, otherwise load the address into a register first. */
15047 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15048 SIBLING_CALL_P (insn) = 1;
15052 /* This is messy. GAS treats "la $25,foo" as part of a call
15053 sequence and may allow a global "foo" to be lazily bound.
15054 The general move patterns therefore reject this combination.
15056 In this context, lazy binding would actually be OK
15057 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15058 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15059 We must therefore load the address via a temporary
15060 register if mips_dangerous_for_la25_p.
15062 If we jump to the temporary register rather than $25,
15063 the assembler can use the move insn to fill the jump's
15066 We can use the same technique for MIPS16 code, where $25
15067 is not a valid JR register. */
15068 if (TARGET_USE_PIC_FN_ADDR_REG
15070 && !mips_dangerous_for_la25_p (fnaddr))
15071 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15072 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15074 if (TARGET_USE_PIC_FN_ADDR_REG
15075 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15076 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15077 emit_jump_insn (gen_indirect_jump (temp1));
15080 /* Run just enough of rest_of_compilation. This sequence was
15081 "borrowed" from alpha.c. */
15082 insn = get_insns ();
15083 insn_locators_alloc ();
15084 split_all_insns_noflow ();
15085 mips16_lay_out_constants ();
15086 shorten_branches (insn);
15087 final_start_function (insn, file, 1);
15088 final (insn, file, 1);
15089 final_end_function ();
15091 /* Clean up the vars set above. Note that final_end_function resets
15092 the global pointer for us. */
15093 reload_completed = 0;
15096 /* The last argument passed to mips_set_mips16_mode, or negative if the
15097 function hasn't been called yet.
15099 There are two copies of this information. One is saved and restored
15100 by the PCH process while the other is specific to this compiler
15101 invocation. The information calculated by mips_set_mips16_mode
15102 is invalid unless the two variables are the same. */
15103 static int was_mips16_p = -1;
15104 static GTY(()) int was_mips16_pch_p = -1;
15106 /* Set up the target-dependent global state so that it matches the
15107 current function's ISA mode. */
15110 mips_set_mips16_mode (int mips16_p)
15112 if (mips16_p == was_mips16_p
15113 && mips16_p == was_mips16_pch_p)
15116 /* Restore base settings of various flags. */
15117 target_flags = mips_base_target_flags;
15118 flag_schedule_insns = mips_base_schedule_insns;
15119 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15120 flag_move_loop_invariants = mips_base_move_loop_invariants;
15121 align_loops = mips_base_align_loops;
15122 align_jumps = mips_base_align_jumps;
15123 align_functions = mips_base_align_functions;
15127 /* Switch to MIPS16 mode. */
15128 target_flags |= MASK_MIPS16;
15130 /* Don't run the scheduler before reload, since it tends to
15131 increase register pressure. */
15132 flag_schedule_insns = 0;
15134 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15135 the whole function to be in a single section. */
15136 flag_reorder_blocks_and_partition = 0;
15138 /* Don't move loop invariants, because it tends to increase
15139 register pressure. It also introduces an extra move in cases
15140 where the constant is the first operand in a two-operand binary
15141 instruction, or when it forms a register argument to a functon
15143 flag_move_loop_invariants = 0;
15145 target_flags |= MASK_EXPLICIT_RELOCS;
15147 /* Experiments suggest we get the best overall section-anchor
15148 results from using the range of an unextended LW or SW. Code
15149 that makes heavy use of byte or short accesses can do better
15150 with ranges of 0...31 and 0...63 respectively, but most code is
15151 sensitive to the range of LW and SW instead. */
15152 targetm.min_anchor_offset = 0;
15153 targetm.max_anchor_offset = 127;
15155 targetm.const_anchor = 0;
15157 /* MIPS16 has no BAL instruction. */
15158 target_flags &= ~MASK_RELAX_PIC_CALLS;
15160 if (flag_pic && !TARGET_OLDABI)
15161 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15164 sorry ("MIPS16 -mxgot code");
15166 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15167 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15171 /* Switch to normal (non-MIPS16) mode. */
15172 target_flags &= ~MASK_MIPS16;
15174 /* Provide default values for align_* for 64-bit targets. */
15177 if (align_loops == 0)
15179 if (align_jumps == 0)
15181 if (align_functions == 0)
15182 align_functions = 8;
15185 targetm.min_anchor_offset = -32768;
15186 targetm.max_anchor_offset = 32767;
15188 targetm.const_anchor = 0x8000;
15191 /* (Re)initialize MIPS target internals for new ISA. */
15192 mips_init_relocs ();
15194 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
15195 /* Reinitialize target-dependent state. */
15198 was_mips16_p = mips16_p;
15199 was_mips16_pch_p = mips16_p;
15202 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15203 function should use the MIPS16 ISA and switch modes accordingly. */
15206 mips_set_current_function (tree fndecl)
15208 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15211 /* Allocate a chunk of memory for per-function machine-dependent data. */
15213 static struct machine_function *
15214 mips_init_machine_status (void)
15216 return ((struct machine_function *)
15217 ggc_alloc_cleared (sizeof (struct machine_function)));
15220 /* Return the processor associated with the given ISA level, or null
15221 if the ISA isn't valid. */
15223 static const struct mips_cpu_info *
15224 mips_cpu_info_from_isa (int isa)
15228 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15229 if (mips_cpu_info_table[i].isa == isa)
15230 return mips_cpu_info_table + i;
15235 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15236 with a final "000" replaced by "k". Ignore case.
15238 Note: this function is shared between GCC and GAS. */
15241 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15243 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15244 given++, canonical++;
15246 return ((*given == 0 && *canonical == 0)
15247 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15250 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15251 CPU name. We've traditionally allowed a lot of variation here.
15253 Note: this function is shared between GCC and GAS. */
15256 mips_matching_cpu_name_p (const char *canonical, const char *given)
15258 /* First see if the name matches exactly, or with a final "000"
15259 turned into "k". */
15260 if (mips_strict_matching_cpu_name_p (canonical, given))
15263 /* If not, try comparing based on numerical designation alone.
15264 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15265 if (TOLOWER (*given) == 'r')
15267 if (!ISDIGIT (*given))
15270 /* Skip over some well-known prefixes in the canonical name,
15271 hoping to find a number there too. */
15272 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15274 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15276 else if (TOLOWER (canonical[0]) == 'r')
15279 return mips_strict_matching_cpu_name_p (canonical, given);
15282 /* Return the mips_cpu_info entry for the processor or ISA given
15283 by CPU_STRING. Return null if the string isn't recognized.
15285 A similar function exists in GAS. */
15287 static const struct mips_cpu_info *
15288 mips_parse_cpu (const char *cpu_string)
15293 /* In the past, we allowed upper-case CPU names, but it doesn't
15294 work well with the multilib machinery. */
15295 for (s = cpu_string; *s != 0; s++)
15298 warning (0, "CPU names must be lower case");
15302 /* 'from-abi' selects the most compatible architecture for the given
15303 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15304 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15306 if (strcasecmp (cpu_string, "from-abi") == 0)
15307 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15308 : ABI_NEEDS_64BIT_REGS ? 3
15309 : (TARGET_64BIT ? 3 : 1));
15311 /* 'default' has traditionally been a no-op. Probably not very useful. */
15312 if (strcasecmp (cpu_string, "default") == 0)
15315 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15316 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
15317 return mips_cpu_info_table + i;
15322 /* Set up globals to generate code for the ISA or processor
15323 described by INFO. */
15326 mips_set_architecture (const struct mips_cpu_info *info)
15330 mips_arch_info = info;
15331 mips_arch = info->cpu;
15332 mips_isa = info->isa;
15336 /* Likewise for tuning. */
15339 mips_set_tune (const struct mips_cpu_info *info)
15343 mips_tune_info = info;
15344 mips_tune = info->cpu;
15348 /* Implement TARGET_HANDLE_OPTION. */
15351 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
15356 if (strcmp (arg, "32") == 0)
15358 else if (strcmp (arg, "o64") == 0)
15359 mips_abi = ABI_O64;
15360 else if (strcmp (arg, "n32") == 0)
15361 mips_abi = ABI_N32;
15362 else if (strcmp (arg, "64") == 0)
15364 else if (strcmp (arg, "eabi") == 0)
15365 mips_abi = ABI_EABI;
15372 return mips_parse_cpu (arg) != 0;
15375 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
15376 return mips_isa_option_info != 0;
15378 case OPT_mno_flush_func:
15379 mips_cache_flush_func = NULL;
15382 case OPT_mcode_readable_:
15383 if (strcmp (arg, "yes") == 0)
15384 mips_code_readable = CODE_READABLE_YES;
15385 else if (strcmp (arg, "pcrel") == 0)
15386 mips_code_readable = CODE_READABLE_PCREL;
15387 else if (strcmp (arg, "no") == 0)
15388 mips_code_readable = CODE_READABLE_NO;
15393 case OPT_mr10k_cache_barrier_:
15394 if (strcmp (arg, "load-store") == 0)
15395 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
15396 else if (strcmp (arg, "store") == 0)
15397 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
15398 else if (strcmp (arg, "none") == 0)
15399 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15409 /* Implement OVERRIDE_OPTIONS. */
15412 mips_override_options (void)
15414 int i, start, regno, mode;
15416 /* Process flags as though we were generating non-MIPS16 code. */
15417 mips_base_mips16 = TARGET_MIPS16;
15418 target_flags &= ~MASK_MIPS16;
15420 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15421 SUBTARGET_OVERRIDE_OPTIONS;
15424 /* -mno-float overrides -mhard-float and -msoft-float. */
15425 if (TARGET_NO_FLOAT)
15427 target_flags |= MASK_SOFT_FLOAT_ABI;
15428 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15431 /* Set the small data limit. */
15432 mips_small_data_threshold = (g_switch_set
15434 : MIPS_DEFAULT_GVALUE);
15436 /* The following code determines the architecture and register size.
15437 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15438 The GAS and GCC code should be kept in sync as much as possible. */
15440 if (mips_arch_string != 0)
15441 mips_set_architecture (mips_parse_cpu (mips_arch_string));
15443 if (mips_isa_option_info != 0)
15445 if (mips_arch_info == 0)
15446 mips_set_architecture (mips_isa_option_info);
15447 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15448 error ("%<-%s%> conflicts with the other architecture options, "
15449 "which specify a %s processor",
15450 mips_isa_option_info->name,
15451 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15454 if (mips_arch_info == 0)
15456 #ifdef MIPS_CPU_STRING_DEFAULT
15457 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
15459 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
15463 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15464 error ("%<-march=%s%> is not compatible with the selected ABI",
15465 mips_arch_info->name);
15467 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15468 if (mips_tune_string != 0)
15469 mips_set_tune (mips_parse_cpu (mips_tune_string));
15471 if (mips_tune_info == 0)
15472 mips_set_tune (mips_arch_info);
15474 if ((target_flags_explicit & MASK_64BIT) != 0)
15476 /* The user specified the size of the integer registers. Make sure
15477 it agrees with the ABI and ISA. */
15478 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15479 error ("%<-mgp64%> used with a 32-bit processor");
15480 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15481 error ("%<-mgp32%> used with a 64-bit ABI");
15482 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15483 error ("%<-mgp64%> used with a 32-bit ABI");
15487 /* Infer the integer register size from the ABI and processor.
15488 Restrict ourselves to 32-bit registers if that's all the
15489 processor has, or if the ABI cannot handle 64-bit registers. */
15490 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15491 target_flags &= ~MASK_64BIT;
15493 target_flags |= MASK_64BIT;
15496 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15498 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15499 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15500 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15501 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15502 else if (!TARGET_64BIT && TARGET_FLOAT64)
15504 if (!ISA_HAS_MXHC1)
15505 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15506 " the target supports the mfhc1 and mthc1 instructions");
15507 else if (mips_abi != ABI_32)
15508 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15514 /* -msingle-float selects 32-bit float registers. Otherwise the
15515 float registers should be the same size as the integer ones. */
15516 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15517 target_flags |= MASK_FLOAT64;
15519 target_flags &= ~MASK_FLOAT64;
15522 /* End of code shared with GAS. */
15524 /* If no -mlong* option was given, infer it from the other options. */
15525 if ((target_flags_explicit & MASK_LONG64) == 0)
15527 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15528 target_flags |= MASK_LONG64;
15530 target_flags &= ~MASK_LONG64;
15533 if (!TARGET_OLDABI)
15534 flag_pcc_struct_return = 0;
15536 /* Decide which rtx_costs structure to use. */
15538 mips_cost = &mips_rtx_cost_optimize_size;
15540 mips_cost = &mips_rtx_cost_data[mips_tune];
15542 /* If the user hasn't specified a branch cost, use the processor's
15544 if (mips_branch_cost == 0)
15545 mips_branch_cost = mips_cost->branch_cost;
15547 /* If neither -mbranch-likely nor -mno-branch-likely was given
15548 on the command line, set MASK_BRANCHLIKELY based on the target
15549 architecture and tuning flags. Annulled delay slots are a
15550 size win, so we only consider the processor-specific tuning
15551 for !optimize_size. */
15552 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15554 if (ISA_HAS_BRANCHLIKELY
15556 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15557 target_flags |= MASK_BRANCHLIKELY;
15559 target_flags &= ~MASK_BRANCHLIKELY;
15561 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15562 warning (0, "the %qs architecture does not support branch-likely"
15563 " instructions", mips_arch_info->name);
15565 /* The effect of -mabicalls isn't defined for the EABI. */
15566 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15568 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15569 target_flags &= ~MASK_ABICALLS;
15572 if (TARGET_ABICALLS_PIC2)
15573 /* We need to set flag_pic for executables as well as DSOs
15574 because we may reference symbols that are not defined in
15575 the final executable. (MIPS does not use things like
15576 copy relocs, for example.)
15578 There is a body of code that uses __PIC__ to distinguish
15579 between -mabicalls and -mno-abicalls code. The non-__PIC__
15580 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15581 long as any indirect jumps use $25. */
15584 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15585 faster code, but at the expense of more nops. Enable it at -O3 and
15587 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15588 target_flags |= MASK_VR4130_ALIGN;
15590 /* Prefer a call to memcpy over inline code when optimizing for size,
15591 though see MOVE_RATIO in mips.h. */
15592 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15593 target_flags |= MASK_MEMCPY;
15595 /* If we have a nonzero small-data limit, check that the -mgpopt
15596 setting is consistent with the other target flags. */
15597 if (mips_small_data_threshold > 0)
15601 if (!TARGET_EXPLICIT_RELOCS)
15602 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15604 TARGET_LOCAL_SDATA = false;
15605 TARGET_EXTERN_SDATA = false;
15609 if (TARGET_VXWORKS_RTP)
15610 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15612 if (TARGET_ABICALLS)
15613 warning (0, "cannot use small-data accesses for %qs",
15618 #ifdef MIPS_TFMODE_FORMAT
15619 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15622 /* Make sure that the user didn't turn off paired single support when
15623 MIPS-3D support is requested. */
15625 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15626 && !TARGET_PAIRED_SINGLE_FLOAT)
15627 error ("%<-mips3d%> requires %<-mpaired-single%>");
15629 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15631 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15633 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15634 and TARGET_HARD_FLOAT_ABI are both true. */
15635 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15636 error ("%qs must be used with %qs",
15637 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15638 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15640 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15642 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15643 warning (0, "the %qs architecture does not support paired-single"
15644 " instructions", mips_arch_info->name);
15646 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15647 && !TARGET_CACHE_BUILTIN)
15649 error ("%qs requires a target that provides the %qs instruction",
15650 "-mr10k-cache-barrier", "cache");
15651 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15654 /* If TARGET_DSPR2, enable MASK_DSP. */
15656 target_flags |= MASK_DSP;
15658 /* .eh_frame addresses should be the same width as a C pointer.
15659 Most MIPS ABIs support only one pointer size, so the assembler
15660 will usually know exactly how big an .eh_frame address is.
15662 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15663 originally defined to use 64-bit pointers (i.e. it is LP64), and
15664 this is still the default mode. However, we also support an n32-like
15665 ILP32 mode, which is selected by -mlong32. The problem is that the
15666 assembler has traditionally not had an -mlong option, so it has
15667 traditionally not known whether we're using the ILP32 or LP64 form.
15669 As it happens, gas versions up to and including 2.19 use _32-bit_
15670 addresses for EABI64 .cfi_* directives. This is wrong for the
15671 default LP64 mode, so we can't use the directives by default.
15672 Moreover, since gas's current behavior is at odds with gcc's
15673 default behavior, it seems unwise to rely on future versions
15674 of gas behaving the same way. We therefore avoid using .cfi
15675 directives for -mlong32 as well. */
15676 if (mips_abi == ABI_EABI && TARGET_64BIT)
15677 flag_dwarf2_cfi_asm = 0;
15679 /* .cfi_* directives generate a read-only section, so fall back on
15680 manual .eh_frame creation if we need the section to be writable. */
15681 if (TARGET_WRITABLE_EH_FRAME)
15682 flag_dwarf2_cfi_asm = 0;
15684 mips_init_print_operand_punct ();
15686 /* Set up array to map GCC register number to debug register number.
15687 Ignore the special purpose register numbers. */
15689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15691 mips_dbx_regno[i] = INVALID_REGNUM;
15692 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15693 mips_dwarf_regno[i] = i;
15695 mips_dwarf_regno[i] = INVALID_REGNUM;
15698 start = GP_DBX_FIRST - GP_REG_FIRST;
15699 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15700 mips_dbx_regno[i] = i + start;
15702 start = FP_DBX_FIRST - FP_REG_FIRST;
15703 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15704 mips_dbx_regno[i] = i + start;
15706 /* Accumulator debug registers use big-endian ordering. */
15707 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15708 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15709 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15710 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15711 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15713 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15714 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15717 /* Set up mips_hard_regno_mode_ok. */
15718 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15719 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15720 mips_hard_regno_mode_ok[mode][regno]
15721 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15723 /* Function to allocate machine-dependent function status. */
15724 init_machine_status = &mips_init_machine_status;
15726 /* Default to working around R4000 errata only if the processor
15727 was selected explicitly. */
15728 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15729 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
15730 target_flags |= MASK_FIX_R4000;
15732 /* Default to working around R4400 errata only if the processor
15733 was selected explicitly. */
15734 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15735 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
15736 target_flags |= MASK_FIX_R4400;
15738 /* Default to working around R10000 errata only if the processor
15739 was selected explicitly. */
15740 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15741 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
15742 target_flags |= MASK_FIX_R10000;
15744 /* Make sure that branch-likely instructions available when using
15745 -mfix-r10000. The instructions are not available if either:
15747 1. -mno-branch-likely was passed.
15748 2. The selected ISA does not support branch-likely and
15749 the command line does not include -mbranch-likely. */
15750 if (TARGET_FIX_R10000
15751 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15752 ? !ISA_HAS_BRANCHLIKELY
15753 : !TARGET_BRANCHLIKELY))
15754 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15756 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15758 warning (0, "the %qs architecture does not support the synci "
15759 "instruction", mips_arch_info->name);
15760 target_flags &= ~MASK_SYNCI;
15763 /* Only optimize PIC indirect calls if they are actually required. */
15764 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15765 target_flags &= ~MASK_RELAX_PIC_CALLS;
15767 /* Save base state of options. */
15768 mips_base_target_flags = target_flags;
15769 mips_base_schedule_insns = flag_schedule_insns;
15770 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15771 mips_base_move_loop_invariants = flag_move_loop_invariants;
15772 mips_base_align_loops = align_loops;
15773 mips_base_align_jumps = align_jumps;
15774 mips_base_align_functions = align_functions;
15776 /* Now select the ISA mode.
15778 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15779 MIPS16 mode afterwards if need be. */
15780 mips_set_mips16_mode (false);
15783 /* Swap the register information for registers I and I + 1, which
15784 currently have the wrong endianness. Note that the registers'
15785 fixedness and call-clobberedness might have been set on the
15789 mips_swap_registers (unsigned int i)
15794 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15795 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15797 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15798 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15799 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15800 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15806 /* Implement CONDITIONAL_REGISTER_USAGE. */
15809 mips_conditional_register_usage (void)
15814 /* These DSP control register fields are global. */
15815 global_regs[CCDSP_PO_REGNUM] = 1;
15816 global_regs[CCDSP_SC_REGNUM] = 1;
15822 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15823 fixed_regs[regno] = call_used_regs[regno] = 1;
15825 if (!TARGET_HARD_FLOAT)
15829 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15830 fixed_regs[regno] = call_used_regs[regno] = 1;
15831 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15832 fixed_regs[regno] = call_used_regs[regno] = 1;
15834 else if (! ISA_HAS_8CC)
15838 /* We only have a single condition-code register. We implement
15839 this by fixing all the condition-code registers and generating
15840 RTL that refers directly to ST_REG_FIRST. */
15841 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15842 fixed_regs[regno] = call_used_regs[regno] = 1;
15844 /* In MIPS16 mode, we permit the $t temporary registers to be used
15845 for reload. We prohibit the unused $s registers, since they
15846 are call-saved, and saving them via a MIPS16 register would
15847 probably waste more time than just reloading the value. */
15850 fixed_regs[18] = call_used_regs[18] = 1;
15851 fixed_regs[19] = call_used_regs[19] = 1;
15852 fixed_regs[20] = call_used_regs[20] = 1;
15853 fixed_regs[21] = call_used_regs[21] = 1;
15854 fixed_regs[22] = call_used_regs[22] = 1;
15855 fixed_regs[23] = call_used_regs[23] = 1;
15856 fixed_regs[26] = call_used_regs[26] = 1;
15857 fixed_regs[27] = call_used_regs[27] = 1;
15858 fixed_regs[30] = call_used_regs[30] = 1;
15860 /* $f20-$f23 are call-clobbered for n64. */
15861 if (mips_abi == ABI_64)
15864 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15865 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15867 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15869 if (mips_abi == ABI_N32)
15872 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15873 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15875 /* Make sure that double-register accumulator values are correctly
15876 ordered for the current endianness. */
15877 if (TARGET_LITTLE_ENDIAN)
15879 unsigned int regno;
15881 mips_swap_registers (MD_REG_FIRST);
15882 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15883 mips_swap_registers (regno);
15887 /* Initialize vector TARGET to VALS. */
15890 mips_expand_vector_init (rtx target, rtx vals)
15892 enum machine_mode mode;
15893 enum machine_mode inner;
15894 unsigned int i, n_elts;
15897 mode = GET_MODE (target);
15898 inner = GET_MODE_INNER (mode);
15899 n_elts = GET_MODE_NUNITS (mode);
15901 gcc_assert (VECTOR_MODE_P (mode));
15903 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
15904 for (i = 0; i < n_elts; i++)
15905 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
15906 XVECEXP (vals, 0, i));
15908 emit_move_insn (target, mem);
15911 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15912 other registers for instructions for which it is possible. This
15913 encourages the compiler to use CMP in cases where an XOR would
15914 require some register shuffling. */
15917 mips_order_regs_for_local_alloc (void)
15921 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15922 reg_alloc_order[i] = i;
15926 /* It really doesn't matter where we put register 0, since it is
15927 a fixed register anyhow. */
15928 reg_alloc_order[0] = 24;
15929 reg_alloc_order[24] = 0;
15933 /* Implement EH_USES. */
15936 mips_eh_uses (unsigned int regno)
15938 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
15940 /* We need to force certain registers to be live in order to handle
15941 PIC long branches correctly. See mips_must_initialize_gp_p for
15943 if (mips_cfun_has_cprestore_slot_p ())
15945 if (regno == CPRESTORE_SLOT_REGNUM)
15950 if (cfun->machine->global_pointer == regno)
15958 /* Implement EPILOGUE_USES. */
15961 mips_epilogue_uses (unsigned int regno)
15963 /* Say that the epilogue uses the return address register. Note that
15964 in the case of sibcalls, the values "used by the epilogue" are
15965 considered live at the start of the called function. */
15966 if (regno == RETURN_ADDR_REGNUM)
15969 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
15970 See the comment above load_call<mode> for details. */
15971 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
15974 /* An interrupt handler must preserve some registers that are
15975 ordinarily call-clobbered. */
15976 if (cfun->machine->interrupt_handler_p
15977 && mips_interrupt_extra_call_saved_reg_p (regno))
15983 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
15986 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
15988 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
15991 /* Return true if INSN needs to be wrapped in ".set noat".
15992 INSN has NOPERANDS operands, stored in OPVEC. */
15995 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
15999 if (recog_memoized (insn) >= 0)
16000 for (i = 0; i < noperands; i++)
16001 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16006 /* Implement FINAL_PRESCAN_INSN. */
16009 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16011 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16012 mips_push_asm_switch (&mips_noat);
16015 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16018 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16019 rtx *opvec, int noperands)
16021 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16022 mips_pop_asm_switch (&mips_noat);
16025 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16026 EXT_CODE is the code of the extension used. Return NULL if widening
16027 multiplication shouldn't be used. */
16030 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16034 signed_p = ext_code == SIGN_EXTEND;
16037 /* Don't use widening multiplication with MULT when we have DMUL. Even
16038 with the extension of its input operands DMUL is faster. Note that
16039 the extension is not needed for signed multiplication. In order to
16040 ensure that we always remove the redundant sign-extension in this
16041 case we still expand mulsidi3 for DMUL. */
16043 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16044 if (TARGET_FIX_R4000)
16046 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16050 if (TARGET_FIX_R4000)
16051 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16053 return signed_p ? gen_mips_mult : gen_mips_multu;
16054 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16058 /* Return the size in bytes of the trampoline code, padded to
16059 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16060 function address immediately follow. */
16063 mips_trampoline_code_size (void)
16065 if (TARGET_USE_PIC_FN_ADDR_REG)
16067 else if (ptr_mode == DImode)
16069 else if (ISA_HAS_LOAD_DELAY)
16075 /* Implement TARGET_TRAMPOLINE_INIT. */
16078 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16080 rtx addr, end_addr, high, low, opcode, mem;
16083 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16085 /* Work out the offsets of the pointers from the start of the
16086 trampoline code. */
16087 end_addr_offset = mips_trampoline_code_size ();
16088 static_chain_offset = end_addr_offset;
16089 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16091 /* Get pointers to the beginning and end of the code block. */
16092 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16093 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16095 #define OP(X) gen_int_mode (X, SImode)
16097 /* Build up the code in TRAMPOLINE. */
16099 if (TARGET_USE_PIC_FN_ADDR_REG)
16101 /* $25 contains the address of the trampoline. Emit code of the form:
16103 l[wd] $1, target_function_offset($25)
16104 l[wd] $static_chain, static_chain_offset($25)
16107 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16108 target_function_offset,
16109 PIC_FUNCTION_ADDR_REGNUM));
16110 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16111 static_chain_offset,
16112 PIC_FUNCTION_ADDR_REGNUM));
16113 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16114 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16116 else if (ptr_mode == DImode)
16118 /* It's too cumbersome to create the full 64-bit address, so let's
16124 1: l[wd] $25, target_function_offset - 12($31)
16125 l[wd] $static_chain, static_chain_offset - 12($31)
16129 where 12 is the offset of "1:" from the start of the code block. */
16130 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16131 trampoline[i++] = OP (MIPS_BAL (1));
16132 trampoline[i++] = OP (MIPS_NOP);
16133 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16134 target_function_offset - 12,
16135 RETURN_ADDR_REGNUM));
16136 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16137 static_chain_offset - 12,
16138 RETURN_ADDR_REGNUM));
16139 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16140 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16144 /* If the target has load delays, emit:
16146 lui $1, %hi(end_addr)
16147 lw $25, %lo(end_addr + ...)($1)
16148 lw $static_chain, %lo(end_addr + ...)($1)
16154 lui $1, %hi(end_addr)
16155 lw $25, %lo(end_addr + ...)($1)
16157 lw $static_chain, %lo(end_addr + ...)($1). */
16159 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16160 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16161 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16162 NULL, false, OPTAB_WIDEN);
16163 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16164 NULL, false, OPTAB_WIDEN);
16165 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16167 /* Emit the LUI. */
16168 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16169 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16170 NULL, false, OPTAB_WIDEN);
16172 /* Emit the load of the target function. */
16173 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16174 target_function_offset - end_addr_offset,
16176 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16177 NULL, false, OPTAB_WIDEN);
16179 /* Emit the JR here, if we can. */
16180 if (!ISA_HAS_LOAD_DELAY)
16181 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16183 /* Emit the load of the static chain register. */
16184 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16185 static_chain_offset - end_addr_offset,
16187 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16188 NULL, false, OPTAB_WIDEN);
16190 /* Emit the JR, if we couldn't above. */
16191 if (ISA_HAS_LOAD_DELAY)
16193 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16194 trampoline[i++] = OP (MIPS_NOP);
16200 /* Copy the trampoline code. Leave any padding uninitialized. */
16201 for (j = 0; j < i; j++)
16203 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16204 mips_emit_move (mem, trampoline[j]);
16207 /* Set up the static chain pointer field. */
16208 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16209 mips_emit_move (mem, chain_value);
16211 /* Set up the target function field. */
16212 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16213 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16215 /* Flush the code part of the trampoline. */
16216 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16217 emit_insn (gen_clear_cache (addr, end_addr));
16220 /* Implement FUNCTION_PROFILER. */
16222 void mips_function_profiler (FILE *file)
16225 sorry ("mips16 function profiling");
16226 if (TARGET_LONG_CALLS)
16228 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16229 if (Pmode == DImode)
16230 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16232 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16234 mips_push_asm_switch (&mips_noat);
16235 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16236 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16237 /* _mcount treats $2 as the static chain register. */
16238 if (cfun->static_chain_decl != NULL)
16239 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16240 reg_names[STATIC_CHAIN_REGNUM]);
16241 if (TARGET_MCOUNT_RA_ADDRESS)
16243 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16244 ra save location. */
16245 if (cfun->machine->frame.ra_fp_offset == 0)
16246 /* ra not saved, pass zero. */
16247 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16249 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16250 Pmode == DImode ? "dla" : "la", reg_names[12],
16251 cfun->machine->frame.ra_fp_offset,
16252 reg_names[STACK_POINTER_REGNUM]);
16254 if (!TARGET_NEWABI)
16256 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16257 TARGET_64BIT ? "dsubu" : "subu",
16258 reg_names[STACK_POINTER_REGNUM],
16259 reg_names[STACK_POINTER_REGNUM],
16260 Pmode == DImode ? 16 : 8);
16262 if (TARGET_LONG_CALLS)
16263 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16265 fprintf (file, "\tjal\t_mcount\n");
16266 mips_pop_asm_switch (&mips_noat);
16267 /* _mcount treats $2 as the static chain register. */
16268 if (cfun->static_chain_decl != NULL)
16269 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16273 /* Initialize the GCC target structure. */
16274 #undef TARGET_ASM_ALIGNED_HI_OP
16275 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16276 #undef TARGET_ASM_ALIGNED_SI_OP
16277 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16278 #undef TARGET_ASM_ALIGNED_DI_OP
16279 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16281 #undef TARGET_LEGITIMIZE_ADDRESS
16282 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16284 #undef TARGET_ASM_FUNCTION_PROLOGUE
16285 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16286 #undef TARGET_ASM_FUNCTION_EPILOGUE
16287 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16288 #undef TARGET_ASM_SELECT_RTX_SECTION
16289 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16290 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16291 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16293 #undef TARGET_SCHED_INIT
16294 #define TARGET_SCHED_INIT mips_sched_init
16295 #undef TARGET_SCHED_REORDER
16296 #define TARGET_SCHED_REORDER mips_sched_reorder
16297 #undef TARGET_SCHED_REORDER2
16298 #define TARGET_SCHED_REORDER2 mips_sched_reorder
16299 #undef TARGET_SCHED_VARIABLE_ISSUE
16300 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16301 #undef TARGET_SCHED_ADJUST_COST
16302 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16303 #undef TARGET_SCHED_ISSUE_RATE
16304 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16305 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16306 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16307 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16308 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16309 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16310 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16311 mips_multipass_dfa_lookahead
16312 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16313 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16314 mips_small_register_classes_for_mode_p
16316 #undef TARGET_DEFAULT_TARGET_FLAGS
16317 #define TARGET_DEFAULT_TARGET_FLAGS \
16319 | TARGET_CPU_DEFAULT \
16320 | TARGET_ENDIAN_DEFAULT \
16321 | TARGET_FP_EXCEPTIONS_DEFAULT \
16322 | MASK_CHECK_ZERO_DIV \
16324 #undef TARGET_HANDLE_OPTION
16325 #define TARGET_HANDLE_OPTION mips_handle_option
16327 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16328 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16330 #undef TARGET_INSERT_ATTRIBUTES
16331 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16332 #undef TARGET_MERGE_DECL_ATTRIBUTES
16333 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16334 #undef TARGET_SET_CURRENT_FUNCTION
16335 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16337 #undef TARGET_VALID_POINTER_MODE
16338 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16339 #undef TARGET_RTX_COSTS
16340 #define TARGET_RTX_COSTS mips_rtx_costs
16341 #undef TARGET_ADDRESS_COST
16342 #define TARGET_ADDRESS_COST mips_address_cost
16344 #undef TARGET_IN_SMALL_DATA_P
16345 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16347 #undef TARGET_MACHINE_DEPENDENT_REORG
16348 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16350 #undef TARGET_ASM_FILE_START
16351 #define TARGET_ASM_FILE_START mips_file_start
16352 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16353 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16355 #undef TARGET_INIT_LIBFUNCS
16356 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16358 #undef TARGET_BUILD_BUILTIN_VA_LIST
16359 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16360 #undef TARGET_EXPAND_BUILTIN_VA_START
16361 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16362 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16363 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16365 #undef TARGET_PROMOTE_FUNCTION_MODE
16366 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16367 #undef TARGET_PROMOTE_PROTOTYPES
16368 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16370 #undef TARGET_RETURN_IN_MEMORY
16371 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16372 #undef TARGET_RETURN_IN_MSB
16373 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16375 #undef TARGET_ASM_OUTPUT_MI_THUNK
16376 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16377 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16378 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16380 #undef TARGET_SETUP_INCOMING_VARARGS
16381 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16382 #undef TARGET_STRICT_ARGUMENT_NAMING
16383 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16384 #undef TARGET_MUST_PASS_IN_STACK
16385 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16386 #undef TARGET_PASS_BY_REFERENCE
16387 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16388 #undef TARGET_CALLEE_COPIES
16389 #define TARGET_CALLEE_COPIES mips_callee_copies
16390 #undef TARGET_ARG_PARTIAL_BYTES
16391 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16393 #undef TARGET_MODE_REP_EXTENDED
16394 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16396 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16397 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16399 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16400 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16402 #undef TARGET_INIT_BUILTINS
16403 #define TARGET_INIT_BUILTINS mips_init_builtins
16404 #undef TARGET_EXPAND_BUILTIN
16405 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16407 #undef TARGET_HAVE_TLS
16408 #define TARGET_HAVE_TLS HAVE_AS_TLS
16410 #undef TARGET_CANNOT_FORCE_CONST_MEM
16411 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16413 #undef TARGET_ENCODE_SECTION_INFO
16414 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16416 #undef TARGET_ATTRIBUTE_TABLE
16417 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16418 /* All our function attributes are related to how out-of-line copies should
16419 be compiled or called. They don't in themselves prevent inlining. */
16420 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16421 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16423 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16424 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16426 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16427 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16428 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16429 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16431 #undef TARGET_COMP_TYPE_ATTRIBUTES
16432 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16434 #ifdef HAVE_AS_DTPRELWORD
16435 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16436 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16438 #undef TARGET_DWARF_REGISTER_SPAN
16439 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16441 #undef TARGET_IRA_COVER_CLASSES
16442 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
16444 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16445 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16447 #undef TARGET_LEGITIMATE_ADDRESS_P
16448 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16450 #undef TARGET_FRAME_POINTER_REQUIRED
16451 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16453 #undef TARGET_CAN_ELIMINATE
16454 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16456 #undef TARGET_TRAMPOLINE_INIT
16457 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16459 struct gcc_target targetm = TARGET_INITIALIZER;
16461 #include "gt-mips.h"