1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* The maximum distance between the top of the stack frame and the
75 value $sp has when we save & restore registers.
77 Use a maximum gap of 0x100 in the mips16 case. We can then use
78 unextended instructions to save and restore registers, and to
79 allocate and deallocate the top part of the frame.
81 The value in the !mips16 case must be a SMALL_OPERAND and must
82 preserve the maximum stack alignment. */
83 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
85 /* True if INSN is a mips.md pattern or asm statement. */
86 #define USEFUL_INSN_P(INSN) \
88 && GET_CODE (PATTERN (INSN)) != USE \
89 && GET_CODE (PATTERN (INSN)) != CLOBBER \
90 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
91 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
93 /* If INSN is a delayed branch sequence, return the first instruction
94 in the sequence, otherwise return INSN itself. */
95 #define SEQ_BEGIN(INSN) \
96 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
97 ? XVECEXP (PATTERN (INSN), 0, 0) \
100 /* Likewise for the last instruction in a delayed branch sequence. */
101 #define SEQ_END(INSN) \
102 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
103 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
106 /* Execute the following loop body with SUBINSN set to each instruction
107 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
108 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
109 for ((SUBINSN) = SEQ_BEGIN (INSN); \
110 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
111 (SUBINSN) = NEXT_INSN (SUBINSN))
113 /* Classifies an address.
116 A natural register + offset address. The register satisfies
117 mips_valid_base_register_p and the offset is a const_arith_operand.
120 A LO_SUM rtx. The first operand is a valid base register and
121 the second operand is a symbolic address.
124 A signed 16-bit constant address.
127 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
128 enum mips_address_type {
135 /* Classifies the prototype of a builtin function. */
136 enum mips_function_type
138 MIPS_V2SF_FTYPE_V2SF,
139 MIPS_V2SF_FTYPE_V2SF_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
142 MIPS_V2SF_FTYPE_SF_SF,
143 MIPS_INT_FTYPE_V2SF_V2SF,
144 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
145 MIPS_INT_FTYPE_SF_SF,
146 MIPS_INT_FTYPE_DF_DF,
157 /* Specifies how a builtin function should be converted into rtl. */
158 enum mips_builtin_type
160 /* The builtin corresponds directly to an .md pattern. The return
161 value is mapped to operand 0 and the arguments are mapped to
162 operands 1 and above. */
165 /* The builtin corresponds to a comparison instruction followed by
166 a mips_cond_move_tf_ps pattern. The first two arguments are the
167 values to compare and the second two arguments are the vector
168 operands for the movt.ps or movf.ps instruction (in assembly order). */
172 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
173 of this instruction is the result of the comparison, which has mode
174 CCV2 or CCV4. The function arguments are mapped to operands 1 and
175 above. The function's return value is an SImode boolean that is
176 true under the following conditions:
178 MIPS_BUILTIN_CMP_ANY: one of the registers is true
179 MIPS_BUILTIN_CMP_ALL: all of the registers are true
180 MIPS_BUILTIN_CMP_LOWER: the first register is true
181 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
182 MIPS_BUILTIN_CMP_ANY,
183 MIPS_BUILTIN_CMP_ALL,
184 MIPS_BUILTIN_CMP_UPPER,
185 MIPS_BUILTIN_CMP_LOWER,
187 /* As above, but the instruction only sets a single $fcc register. */
188 MIPS_BUILTIN_CMP_SINGLE
191 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
192 #define MIPS_FP_CONDITIONS(MACRO) \
210 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
211 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
212 enum mips_fp_condition {
213 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
216 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
217 #define STRINGIFY(X) #X
218 static const char *const mips_fp_conditions[] = {
219 MIPS_FP_CONDITIONS (STRINGIFY)
222 /* A function to save or store a register. The first argument is the
223 register and the second is the stack slot. */
224 typedef void (*mips_save_restore_fn) (rtx, rtx);
226 struct mips16_constant;
227 struct mips_arg_info;
228 struct mips_address_info;
229 struct mips_integer_op;
232 static enum mips_symbol_type mips_classify_symbol (rtx);
233 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
234 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
235 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
236 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
237 static bool mips_classify_address (struct mips_address_info *, rtx,
238 enum machine_mode, int);
239 static bool mips_cannot_force_const_mem (rtx);
240 static int mips_symbol_insns (enum mips_symbol_type);
241 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
242 static rtx mips_force_temporary (rtx, rtx);
243 static rtx mips_split_symbol (rtx, rtx);
244 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
245 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
246 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
247 static unsigned int mips_build_lower (struct mips_integer_op *,
248 unsigned HOST_WIDE_INT);
249 static unsigned int mips_build_integer (struct mips_integer_op *,
250 unsigned HOST_WIDE_INT);
251 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
252 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
253 static int m16_check_op (rtx, int, int, int);
254 static bool mips_rtx_costs (rtx, int, int, int *);
255 static int mips_address_cost (rtx);
256 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
257 static void mips_load_call_address (rtx, rtx, int);
258 static bool mips_function_ok_for_sibcall (tree, tree);
259 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
260 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
261 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
262 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
263 tree, int, struct mips_arg_info *);
264 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
265 static void mips_set_architecture (const struct mips_cpu_info *);
266 static void mips_set_tune (const struct mips_cpu_info *);
267 static bool mips_handle_option (size_t, const char *, int);
268 static struct machine_function *mips_init_machine_status (void);
269 static void print_operand_reloc (FILE *, rtx, const char **);
271 static void irix_output_external_libcall (rtx);
273 static void mips_file_start (void);
274 static void mips_file_end (void);
275 static bool mips_rewrite_small_data_p (rtx);
276 static int mips_small_data_pattern_1 (rtx *, void *);
277 static int mips_rewrite_small_data_1 (rtx *, void *);
278 static bool mips_function_has_gp_insn (void);
279 static unsigned int mips_global_pointer (void);
280 static bool mips_save_reg_p (unsigned int);
281 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
282 mips_save_restore_fn);
283 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
284 static void mips_output_cplocal (void);
285 static void mips_emit_loadgp (void);
286 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
287 static void mips_set_frame_expr (rtx);
288 static rtx mips_frame_set (rtx, rtx);
289 static void mips_save_reg (rtx, rtx);
290 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
291 static void mips_restore_reg (rtx, rtx);
292 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
293 HOST_WIDE_INT, tree);
294 static int symbolic_expression_p (rtx);
295 static void mips_select_rtx_section (enum machine_mode, rtx,
296 unsigned HOST_WIDE_INT);
297 static void mips_function_rodata_section (tree);
298 static bool mips_in_small_data_p (tree);
299 static int mips_fpr_return_fields (tree, tree *);
300 static bool mips_return_in_msb (tree);
301 static rtx mips_return_fpr_pair (enum machine_mode mode,
302 enum machine_mode mode1, HOST_WIDE_INT,
303 enum machine_mode mode2, HOST_WIDE_INT);
304 static rtx mips16_gp_pseudo_reg (void);
305 static void mips16_fp_args (FILE *, int, int);
306 static void build_mips16_function_stub (FILE *);
307 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
308 static void dump_constants (struct mips16_constant *, rtx);
309 static int mips16_insn_length (rtx);
310 static int mips16_rewrite_pool_refs (rtx *, void *);
311 static void mips16_lay_out_constants (void);
312 static void mips_sim_reset (struct mips_sim *);
313 static void mips_sim_init (struct mips_sim *, state_t);
314 static void mips_sim_next_cycle (struct mips_sim *);
315 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
316 static int mips_sim_wait_regs_2 (rtx *, void *);
317 static void mips_sim_wait_regs_1 (rtx *, void *);
318 static void mips_sim_wait_regs (struct mips_sim *, rtx);
319 static void mips_sim_wait_units (struct mips_sim *, rtx);
320 static void mips_sim_wait_insn (struct mips_sim *, rtx);
321 static void mips_sim_record_set (rtx, rtx, void *);
322 static void mips_sim_issue_insn (struct mips_sim *, rtx);
323 static void mips_sim_issue_nop (struct mips_sim *);
324 static void mips_sim_finish_insn (struct mips_sim *, rtx);
325 static void vr4130_avoid_branch_rt_conflict (rtx);
326 static void vr4130_align_insns (void);
327 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
328 static void mips_avoid_hazards (void);
329 static void mips_reorg (void);
330 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
331 static bool mips_matching_cpu_name_p (const char *, const char *);
332 static const struct mips_cpu_info *mips_parse_cpu (const char *);
333 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
334 static bool mips_return_in_memory (tree, tree);
335 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
336 static void mips_macc_chains_record (rtx);
337 static void mips_macc_chains_reorder (rtx *, int);
338 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
339 static bool vr4130_true_reg_dependence_p (rtx);
340 static bool vr4130_swap_insns_p (rtx, rtx);
341 static void vr4130_reorder (rtx *, int);
342 static void mips_promote_ready (rtx *, int, int);
343 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
344 static int mips_variable_issue (FILE *, int, rtx, int);
345 static int mips_adjust_cost (rtx, rtx, rtx, int);
346 static int mips_issue_rate (void);
347 static int mips_multipass_dfa_lookahead (void);
348 static void mips_init_libfuncs (void);
349 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
351 static tree mips_build_builtin_va_list (void);
352 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
353 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
355 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
357 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
359 static bool mips_valid_pointer_mode (enum machine_mode);
360 static bool mips_vector_mode_supported_p (enum machine_mode);
361 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
362 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
363 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
364 static void mips_init_builtins (void);
365 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree);
366 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
367 enum insn_code, enum mips_fp_condition,
369 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
370 enum insn_code, enum mips_fp_condition,
373 /* Structure to be filled in by compute_frame_size with register
374 save masks, and offsets for the current function. */
376 struct mips_frame_info GTY(())
378 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
379 HOST_WIDE_INT var_size; /* # bytes that variables take up */
380 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
381 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
382 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
383 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
384 unsigned int mask; /* mask of saved gp registers */
385 unsigned int fmask; /* mask of saved fp registers */
386 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
387 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
388 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
389 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
390 bool initialized; /* true if frame size already calculated */
391 int num_gp; /* number of gp registers saved */
392 int num_fp; /* number of fp registers saved */
395 struct machine_function GTY(()) {
396 /* Pseudo-reg holding the value of $28 in a mips16 function which
397 refers to GP relative global variables. */
398 rtx mips16_gp_pseudo_rtx;
400 /* The number of extra stack bytes taken up by register varargs.
401 This area is allocated by the callee at the very top of the frame. */
404 /* Current frame information, calculated by compute_frame_size. */
405 struct mips_frame_info frame;
407 /* The register to use as the global pointer within this function. */
408 unsigned int global_pointer;
410 /* True if mips_adjust_insn_length should ignore an instruction's
412 bool ignore_hazard_length_p;
414 /* True if the whole function is suitable for .set noreorder and
416 bool all_noreorder_p;
418 /* True if the function is known to have an instruction that needs $gp. */
422 /* Information about a single argument. */
425 /* True if the argument is passed in a floating-point register, or
426 would have been if we hadn't run out of registers. */
429 /* The number of words passed in registers, rounded up. */
430 unsigned int reg_words;
432 /* For EABI, the offset of the first register from GP_ARG_FIRST or
433 FP_ARG_FIRST. For other ABIs, the offset of the first register from
434 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
435 comment for details).
437 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
439 unsigned int reg_offset;
441 /* The number of words that must be passed on the stack, rounded up. */
442 unsigned int stack_words;
444 /* The offset from the start of the stack overflow area of the argument's
445 first stack word. Only meaningful when STACK_WORDS is nonzero. */
446 unsigned int stack_offset;
450 /* Information about an address described by mips_address_type.
456 REG is the base register and OFFSET is the constant offset.
459 REG is the register that contains the high part of the address,
460 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
461 is the type of OFFSET's symbol.
464 SYMBOL_TYPE is the type of symbol being referenced. */
466 struct mips_address_info
468 enum mips_address_type type;
471 enum mips_symbol_type symbol_type;
475 /* One stage in a constant building sequence. These sequences have
479 A = A CODE[1] VALUE[1]
480 A = A CODE[2] VALUE[2]
483 where A is an accumulator, each CODE[i] is a binary rtl operation
484 and each VALUE[i] is a constant integer. */
485 struct mips_integer_op {
487 unsigned HOST_WIDE_INT value;
491 /* The largest number of operations needed to load an integer constant.
492 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
493 When the lowest bit is clear, we can try, but reject a sequence with
494 an extra SLL at the end. */
495 #define MIPS_MAX_INTEGER_OPS 7
498 /* Global variables for machine-dependent things. */
500 /* Threshold for data being put into the small data/bss area, instead
501 of the normal data area. */
502 int mips_section_threshold = -1;
504 /* Count the number of .file directives, so that .loc is up to date. */
505 int num_source_filenames = 0;
507 /* Count the number of sdb related labels are generated (to find block
508 start and end boundaries). */
509 int sdb_label_count = 0;
511 /* Next label # for each statement for Silicon Graphics IRIS systems. */
514 /* Linked list of all externals that are to be emitted when optimizing
515 for the global pointer if they haven't been declared by the end of
516 the program with an appropriate .comm or initialization. */
518 struct extern_list GTY (())
520 struct extern_list *next; /* next external */
521 const char *name; /* name of the external */
522 int size; /* size in bytes */
525 static GTY (()) struct extern_list *extern_head = 0;
527 /* Name of the file containing the current function. */
528 const char *current_function_file = "";
530 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
536 /* The next branch instruction is a branch likely, not branch normal. */
537 int mips_branch_likely;
539 /* The operands passed to the last cmpMM expander. */
542 /* The target cpu for code generation. */
543 enum processor_type mips_arch;
544 const struct mips_cpu_info *mips_arch_info;
546 /* The target cpu for optimization and scheduling. */
547 enum processor_type mips_tune;
548 const struct mips_cpu_info *mips_tune_info;
550 /* Which instruction set architecture to use. */
553 /* Which ABI to use. */
554 int mips_abi = MIPS_ABI_DEFAULT;
556 /* Cost information to use. */
557 const struct mips_rtx_cost_data *mips_cost;
559 /* Whether we are generating mips16 hard float code. In mips16 mode
560 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
561 -msoft-float was not specified by the user, which means that we
562 should arrange to call mips32 hard floating point code. */
563 int mips16_hard_float;
565 /* The architecture selected by -mipsN. */
566 static const struct mips_cpu_info *mips_isa_info;
568 /* If TRUE, we split addresses into their high and low parts in the RTL. */
569 int mips_split_addresses;
571 /* Mode used for saving/restoring general purpose registers. */
572 static enum machine_mode gpr_mode;
574 /* Array giving truth value on whether or not a given hard register
575 can support a given mode. */
576 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
578 /* List of all MIPS punctuation characters used by print_operand. */
579 char mips_print_operand_punct[256];
581 /* Map GCC register number to debugger register number. */
582 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
584 /* A copy of the original flag_delayed_branch: see override_options. */
585 static int mips_flag_delayed_branch;
587 static GTY (()) int mips_output_filename_first_time = 1;
589 /* mips_split_p[X] is true if symbols of type X can be split by
590 mips_split_symbol(). */
591 static bool mips_split_p[NUM_SYMBOL_TYPES];
593 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
594 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
595 if they are matched by a special .md file pattern. */
596 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
598 /* Likewise for HIGHs. */
599 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
601 /* Map hard register number to register class */
602 const enum reg_class mips_regno_to_class[] =
604 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
605 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
606 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
607 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
608 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
609 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
610 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
611 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
612 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
613 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
614 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
615 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
616 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
617 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
618 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
619 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
620 HI_REG, LO_REG, NO_REGS, ST_REGS,
621 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
622 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
623 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
624 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
625 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
626 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
627 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
628 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
629 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
630 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
631 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
632 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
633 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
634 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
635 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
636 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
637 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
638 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
639 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
640 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
641 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
642 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
643 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
644 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
645 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
646 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
647 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
650 /* Map register constraint character to register class. */
651 enum reg_class mips_char_to_class[256];
653 /* A table describing all the processors gcc knows about. Names are
654 matched in the order listed. The first mention of an ISA level is
655 taken as the canonical name for that ISA.
657 To ease comparison, please keep this table in the same order as
658 gas's mips_cpu_info_table[]. */
659 const struct mips_cpu_info mips_cpu_info_table[] = {
660 /* Entries for generic ISAs */
661 { "mips1", PROCESSOR_R3000, 1 },
662 { "mips2", PROCESSOR_R6000, 2 },
663 { "mips3", PROCESSOR_R4000, 3 },
664 { "mips4", PROCESSOR_R8000, 4 },
665 { "mips32", PROCESSOR_4KC, 32 },
666 { "mips32r2", PROCESSOR_M4K, 33 },
667 { "mips64", PROCESSOR_5KC, 64 },
670 { "r3000", PROCESSOR_R3000, 1 },
671 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
672 { "r3900", PROCESSOR_R3900, 1 },
675 { "r6000", PROCESSOR_R6000, 2 },
678 { "r4000", PROCESSOR_R4000, 3 },
679 { "vr4100", PROCESSOR_R4100, 3 },
680 { "vr4111", PROCESSOR_R4111, 3 },
681 { "vr4120", PROCESSOR_R4120, 3 },
682 { "vr4130", PROCESSOR_R4130, 3 },
683 { "vr4300", PROCESSOR_R4300, 3 },
684 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
685 { "r4600", PROCESSOR_R4600, 3 },
686 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
687 { "r4650", PROCESSOR_R4650, 3 },
690 { "r8000", PROCESSOR_R8000, 4 },
691 { "vr5000", PROCESSOR_R5000, 4 },
692 { "vr5400", PROCESSOR_R5400, 4 },
693 { "vr5500", PROCESSOR_R5500, 4 },
694 { "rm7000", PROCESSOR_R7000, 4 },
695 { "rm9000", PROCESSOR_R9000, 4 },
698 { "4kc", PROCESSOR_4KC, 32 },
699 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
700 { "4kp", PROCESSOR_4KP, 32 },
702 /* MIPS32 Release 2 */
703 { "m4k", PROCESSOR_M4K, 33 },
704 { "24k", PROCESSOR_24K, 33 },
705 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
706 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
707 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
710 { "5kc", PROCESSOR_5KC, 64 },
711 { "20kc", PROCESSOR_20KC, 64 },
712 { "sb1", PROCESSOR_SB1, 64 },
713 { "sr71000", PROCESSOR_SR71000, 64 },
719 /* Default costs. If these are used for a processor we should look
720 up the actual costs. */
721 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
722 COSTS_N_INSNS (7), /* fp_mult_sf */ \
723 COSTS_N_INSNS (8), /* fp_mult_df */ \
724 COSTS_N_INSNS (23), /* fp_div_sf */ \
725 COSTS_N_INSNS (36), /* fp_div_df */ \
726 COSTS_N_INSNS (10), /* int_mult_si */ \
727 COSTS_N_INSNS (10), /* int_mult_di */ \
728 COSTS_N_INSNS (69), /* int_div_si */ \
729 COSTS_N_INSNS (69), /* int_div_di */ \
730 2, /* branch_cost */ \
731 4 /* memory_latency */
733 /* Need to replace these with the costs of calling the appropriate
735 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
736 COSTS_N_INSNS (256), /* fp_mult_sf */ \
737 COSTS_N_INSNS (256), /* fp_mult_df */ \
738 COSTS_N_INSNS (256), /* fp_div_sf */ \
739 COSTS_N_INSNS (256) /* fp_div_df */
741 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
744 COSTS_N_INSNS (2), /* fp_add */
745 COSTS_N_INSNS (4), /* fp_mult_sf */
746 COSTS_N_INSNS (5), /* fp_mult_df */
747 COSTS_N_INSNS (12), /* fp_div_sf */
748 COSTS_N_INSNS (19), /* fp_div_df */
749 COSTS_N_INSNS (12), /* int_mult_si */
750 COSTS_N_INSNS (12), /* int_mult_di */
751 COSTS_N_INSNS (35), /* int_div_si */
752 COSTS_N_INSNS (35), /* int_div_di */
754 4 /* memory_latency */
779 COSTS_N_INSNS (2), /* fp_add */
780 COSTS_N_INSNS (4), /* fp_mult_sf */
781 COSTS_N_INSNS (5), /* fp_mult_df */
782 COSTS_N_INSNS (12), /* fp_div_sf */
783 COSTS_N_INSNS (19), /* fp_div_df */
784 COSTS_N_INSNS (2), /* int_mult_si */
785 COSTS_N_INSNS (2), /* int_mult_di */
786 COSTS_N_INSNS (35), /* int_div_si */
787 COSTS_N_INSNS (35), /* int_div_di */
789 4 /* memory_latency */
792 COSTS_N_INSNS (3), /* fp_add */
793 COSTS_N_INSNS (5), /* fp_mult_sf */
794 COSTS_N_INSNS (6), /* fp_mult_df */
795 COSTS_N_INSNS (15), /* fp_div_sf */
796 COSTS_N_INSNS (16), /* fp_div_df */
797 COSTS_N_INSNS (17), /* int_mult_si */
798 COSTS_N_INSNS (17), /* int_mult_di */
799 COSTS_N_INSNS (38), /* int_div_si */
800 COSTS_N_INSNS (38), /* int_div_di */
802 6 /* memory_latency */
805 COSTS_N_INSNS (6), /* fp_add */
806 COSTS_N_INSNS (7), /* fp_mult_sf */
807 COSTS_N_INSNS (8), /* fp_mult_df */
808 COSTS_N_INSNS (23), /* fp_div_sf */
809 COSTS_N_INSNS (36), /* fp_div_df */
810 COSTS_N_INSNS (10), /* int_mult_si */
811 COSTS_N_INSNS (10), /* int_mult_di */
812 COSTS_N_INSNS (69), /* int_div_si */
813 COSTS_N_INSNS (69), /* int_div_di */
815 6 /* memory_latency */
827 /* The only costs that appear to be updated here are
828 integer multiplication. */
830 COSTS_N_INSNS (4), /* int_mult_si */
831 COSTS_N_INSNS (6), /* int_mult_di */
832 COSTS_N_INSNS (69), /* int_div_si */
833 COSTS_N_INSNS (69), /* int_div_di */
835 4 /* memory_latency */
847 COSTS_N_INSNS (6), /* fp_add */
848 COSTS_N_INSNS (4), /* fp_mult_sf */
849 COSTS_N_INSNS (5), /* fp_mult_df */
850 COSTS_N_INSNS (23), /* fp_div_sf */
851 COSTS_N_INSNS (36), /* fp_div_df */
852 COSTS_N_INSNS (5), /* int_mult_si */
853 COSTS_N_INSNS (5), /* int_mult_di */
854 COSTS_N_INSNS (36), /* int_div_si */
855 COSTS_N_INSNS (36), /* int_div_di */
857 4 /* memory_latency */
860 COSTS_N_INSNS (6), /* fp_add */
861 COSTS_N_INSNS (5), /* fp_mult_sf */
862 COSTS_N_INSNS (6), /* fp_mult_df */
863 COSTS_N_INSNS (30), /* fp_div_sf */
864 COSTS_N_INSNS (59), /* fp_div_df */
865 COSTS_N_INSNS (3), /* int_mult_si */
866 COSTS_N_INSNS (4), /* int_mult_di */
867 COSTS_N_INSNS (42), /* int_div_si */
868 COSTS_N_INSNS (74), /* int_div_di */
870 4 /* memory_latency */
873 COSTS_N_INSNS (6), /* fp_add */
874 COSTS_N_INSNS (5), /* fp_mult_sf */
875 COSTS_N_INSNS (6), /* fp_mult_df */
876 COSTS_N_INSNS (30), /* fp_div_sf */
877 COSTS_N_INSNS (59), /* fp_div_df */
878 COSTS_N_INSNS (5), /* int_mult_si */
879 COSTS_N_INSNS (9), /* int_mult_di */
880 COSTS_N_INSNS (42), /* int_div_si */
881 COSTS_N_INSNS (74), /* int_div_di */
883 4 /* memory_latency */
886 /* The only costs that are changed here are
887 integer multiplication. */
888 COSTS_N_INSNS (6), /* fp_add */
889 COSTS_N_INSNS (7), /* fp_mult_sf */
890 COSTS_N_INSNS (8), /* fp_mult_df */
891 COSTS_N_INSNS (23), /* fp_div_sf */
892 COSTS_N_INSNS (36), /* fp_div_df */
893 COSTS_N_INSNS (5), /* int_mult_si */
894 COSTS_N_INSNS (9), /* int_mult_di */
895 COSTS_N_INSNS (69), /* int_div_si */
896 COSTS_N_INSNS (69), /* int_div_di */
898 4 /* memory_latency */
904 /* The only costs that are changed here are
905 integer multiplication. */
906 COSTS_N_INSNS (6), /* fp_add */
907 COSTS_N_INSNS (7), /* fp_mult_sf */
908 COSTS_N_INSNS (8), /* fp_mult_df */
909 COSTS_N_INSNS (23), /* fp_div_sf */
910 COSTS_N_INSNS (36), /* fp_div_df */
911 COSTS_N_INSNS (3), /* int_mult_si */
912 COSTS_N_INSNS (8), /* int_mult_di */
913 COSTS_N_INSNS (69), /* int_div_si */
914 COSTS_N_INSNS (69), /* int_div_di */
916 4 /* memory_latency */
919 COSTS_N_INSNS (4), /* fp_add */
920 COSTS_N_INSNS (4), /* fp_mult_sf */
921 COSTS_N_INSNS (4), /* fp_mult_df */
922 COSTS_N_INSNS (24), /* fp_div_sf */
923 COSTS_N_INSNS (32), /* fp_div_df */
924 COSTS_N_INSNS (3), /* int_mult_si */
925 COSTS_N_INSNS (4), /* int_mult_di */
926 COSTS_N_INSNS (36), /* int_div_si */
927 COSTS_N_INSNS (68), /* int_div_di */
929 4 /* memory_latency */
937 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
938 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
939 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
942 /* Initialize the GCC target structure. */
943 #undef TARGET_ASM_ALIGNED_HI_OP
944 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
945 #undef TARGET_ASM_ALIGNED_SI_OP
946 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
947 #undef TARGET_ASM_ALIGNED_DI_OP
948 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
950 #undef TARGET_ASM_FUNCTION_PROLOGUE
951 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
952 #undef TARGET_ASM_FUNCTION_EPILOGUE
953 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
954 #undef TARGET_ASM_SELECT_RTX_SECTION
955 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
956 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
957 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
959 #undef TARGET_SCHED_REORDER
960 #define TARGET_SCHED_REORDER mips_sched_reorder
961 #undef TARGET_SCHED_VARIABLE_ISSUE
962 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
963 #undef TARGET_SCHED_ADJUST_COST
964 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
965 #undef TARGET_SCHED_ISSUE_RATE
966 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
967 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
968 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
969 mips_multipass_dfa_lookahead
971 #undef TARGET_DEFAULT_TARGET_FLAGS
972 #define TARGET_DEFAULT_TARGET_FLAGS \
974 | TARGET_CPU_DEFAULT \
975 | TARGET_ENDIAN_DEFAULT \
976 | TARGET_FP_EXCEPTIONS_DEFAULT \
977 | MASK_CHECK_ZERO_DIV \
979 #undef TARGET_HANDLE_OPTION
980 #define TARGET_HANDLE_OPTION mips_handle_option
982 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
983 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
985 #undef TARGET_VALID_POINTER_MODE
986 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
987 #undef TARGET_RTX_COSTS
988 #define TARGET_RTX_COSTS mips_rtx_costs
989 #undef TARGET_ADDRESS_COST
990 #define TARGET_ADDRESS_COST mips_address_cost
992 #undef TARGET_IN_SMALL_DATA_P
993 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
995 #undef TARGET_MACHINE_DEPENDENT_REORG
996 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
998 #undef TARGET_ASM_FILE_START
999 #undef TARGET_ASM_FILE_END
1000 #define TARGET_ASM_FILE_START mips_file_start
1001 #define TARGET_ASM_FILE_END mips_file_end
1002 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1003 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1005 #undef TARGET_INIT_LIBFUNCS
1006 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1008 #undef TARGET_BUILD_BUILTIN_VA_LIST
1009 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1010 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1011 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1013 #undef TARGET_PROMOTE_FUNCTION_ARGS
1014 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1015 #undef TARGET_PROMOTE_FUNCTION_RETURN
1016 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1017 #undef TARGET_PROMOTE_PROTOTYPES
1018 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1020 #undef TARGET_RETURN_IN_MEMORY
1021 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1022 #undef TARGET_RETURN_IN_MSB
1023 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1025 #undef TARGET_ASM_OUTPUT_MI_THUNK
1026 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1027 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1028 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1030 #undef TARGET_SETUP_INCOMING_VARARGS
1031 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1032 #undef TARGET_STRICT_ARGUMENT_NAMING
1033 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1034 #undef TARGET_MUST_PASS_IN_STACK
1035 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1036 #undef TARGET_PASS_BY_REFERENCE
1037 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1038 #undef TARGET_CALLEE_COPIES
1039 #define TARGET_CALLEE_COPIES mips_callee_copies
1040 #undef TARGET_ARG_PARTIAL_BYTES
1041 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1043 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1044 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1046 #undef TARGET_INIT_BUILTINS
1047 #define TARGET_INIT_BUILTINS mips_init_builtins
1048 #undef TARGET_EXPAND_BUILTIN
1049 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1051 #undef TARGET_HAVE_TLS
1052 #define TARGET_HAVE_TLS HAVE_AS_TLS
1054 #undef TARGET_CANNOT_FORCE_CONST_MEM
1055 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1057 struct gcc_target targetm = TARGET_INITIALIZER;
1059 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1061 static enum mips_symbol_type
1062 mips_classify_symbol (rtx x)
1064 if (GET_CODE (x) == LABEL_REF)
1067 return SYMBOL_CONSTANT_POOL;
1068 if (TARGET_ABICALLS)
1069 return SYMBOL_GOT_LOCAL;
1070 return SYMBOL_GENERAL;
1073 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1075 if (SYMBOL_REF_TLS_MODEL (x))
1078 if (CONSTANT_POOL_ADDRESS_P (x))
1081 return SYMBOL_CONSTANT_POOL;
1083 if (TARGET_ABICALLS)
1084 return SYMBOL_GOT_LOCAL;
1086 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1087 return SYMBOL_SMALL_DATA;
1089 return SYMBOL_GENERAL;
1092 if (SYMBOL_REF_SMALL_P (x))
1093 return SYMBOL_SMALL_DATA;
1095 if (TARGET_ABICALLS)
1097 if (SYMBOL_REF_DECL (x) == 0)
1098 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
1100 /* There are three cases to consider:
1102 - o32 PIC (either with or without explicit relocs)
1103 - n32/n64 PIC without explicit relocs
1104 - n32/n64 PIC with explicit relocs
1106 In the first case, both local and global accesses will use an
1107 R_MIPS_GOT16 relocation. We must correctly predict which of
1108 the two semantics (local or global) the assembler and linker
1109 will apply. The choice doesn't depend on the symbol's
1110 visibility, so we deliberately ignore decl_visibility and
1113 In the second case, the assembler will not use R_MIPS_GOT16
1114 relocations, but it chooses between local and global accesses
1115 in the same way as for o32 PIC.
1117 In the third case we have more freedom since both forms of
1118 access will work for any kind of symbol. However, there seems
1119 little point in doing things differently. */
1120 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
1121 return SYMBOL_GOT_GLOBAL;
1123 return SYMBOL_GOT_LOCAL;
1126 return SYMBOL_GENERAL;
1130 /* Split X into a base and a constant offset, storing them in *BASE
1131 and *OFFSET respectively. */
1134 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1138 if (GET_CODE (x) == CONST)
1141 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1143 *offset += INTVAL (XEXP (x, 1));
1150 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1151 to the same object as SYMBOL. */
1154 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1156 if (GET_CODE (symbol) != SYMBOL_REF)
1159 if (CONSTANT_POOL_ADDRESS_P (symbol)
1161 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1164 if (SYMBOL_REF_DECL (symbol) != 0
1166 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1173 /* Return true if X is a symbolic constant that can be calculated in
1174 the same way as a bare symbol. If it is, store the type of the
1175 symbol in *SYMBOL_TYPE. */
1178 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1180 HOST_WIDE_INT offset;
1182 mips_split_const (x, &x, &offset);
1183 if (UNSPEC_ADDRESS_P (x))
1184 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1185 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1187 *symbol_type = mips_classify_symbol (x);
1188 if (*symbol_type == SYMBOL_TLS)
1197 /* Check whether a nonzero offset is valid for the underlying
1199 switch (*symbol_type)
1201 case SYMBOL_GENERAL:
1202 case SYMBOL_64_HIGH:
1205 /* If the target has 64-bit pointers and the object file only
1206 supports 32-bit symbols, the values of those symbols will be
1207 sign-extended. In this case we can't allow an arbitrary offset
1208 in case the 32-bit value X + OFFSET has a different sign from X. */
1209 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1210 return mips_offset_within_object_p (x, offset);
1212 /* In other cases the relocations can handle any offset. */
1215 case SYMBOL_CONSTANT_POOL:
1216 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1217 In this case, we no longer have access to the underlying constant,
1218 but the original symbol-based access was known to be valid. */
1219 if (GET_CODE (x) == LABEL_REF)
1224 case SYMBOL_SMALL_DATA:
1225 /* Make sure that the offset refers to something within the
1226 underlying object. This should guarantee that the final
1227 PC- or GP-relative offset is within the 16-bit limit. */
1228 return mips_offset_within_object_p (x, offset);
1230 case SYMBOL_GOT_LOCAL:
1231 case SYMBOL_GOTOFF_PAGE:
1232 /* The linker should provide enough local GOT entries for a
1233 16-bit offset. Larger offsets may lead to GOT overflow. */
1234 return SMALL_OPERAND (offset);
1236 case SYMBOL_GOT_GLOBAL:
1237 case SYMBOL_GOTOFF_GLOBAL:
1238 case SYMBOL_GOTOFF_CALL:
1239 case SYMBOL_GOTOFF_LOADGP:
1244 case SYMBOL_GOTTPREL:
1252 /* Return true if X is a symbolic constant whose value is not split
1253 into separate relocations. */
1256 mips_atomic_symbolic_constant_p (rtx x)
1258 enum mips_symbol_type type;
1259 return mips_symbolic_constant_p (x, &type) && !mips_split_p[type];
1263 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1266 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1268 if (regno >= FIRST_PSEUDO_REGISTER)
1272 regno = reg_renumber[regno];
1275 /* These fake registers will be eliminated to either the stack or
1276 hard frame pointer, both of which are usually valid base registers.
1277 Reload deals with the cases where the eliminated form isn't valid. */
1278 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1281 /* In mips16 mode, the stack pointer can only address word and doubleword
1282 values, nothing smaller. There are two problems here:
1284 (a) Instantiating virtual registers can introduce new uses of the
1285 stack pointer. If these virtual registers are valid addresses,
1286 the stack pointer should be too.
1288 (b) Most uses of the stack pointer are not made explicit until
1289 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1290 We don't know until that stage whether we'll be eliminating to the
1291 stack pointer (which needs the restriction) or the hard frame
1292 pointer (which doesn't).
1294 All in all, it seems more consistent to only enforce this restriction
1295 during and after reload. */
1296 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1297 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1299 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1303 /* Return true if X is a valid base register for the given mode.
1304 Allow only hard registers if STRICT. */
1307 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1309 if (!strict && GET_CODE (x) == SUBREG)
1313 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1317 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1318 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1321 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1322 enum machine_mode mode)
1324 switch (symbol_type)
1326 case SYMBOL_GENERAL:
1327 return !TARGET_MIPS16;
1329 case SYMBOL_SMALL_DATA:
1332 case SYMBOL_CONSTANT_POOL:
1333 /* PC-relative addressing is only available for lw and ld. */
1334 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1336 case SYMBOL_GOT_LOCAL:
1339 case SYMBOL_GOT_GLOBAL:
1340 /* The address will have to be loaded from the GOT first. */
1347 case SYMBOL_GOTTPREL:
1351 case SYMBOL_GOTOFF_PAGE:
1352 case SYMBOL_GOTOFF_GLOBAL:
1353 case SYMBOL_GOTOFF_CALL:
1354 case SYMBOL_GOTOFF_LOADGP:
1355 case SYMBOL_64_HIGH:
1364 /* Return true if X is a valid address for machine mode MODE. If it is,
1365 fill in INFO appropriately. STRICT is true if we should only accept
1366 hard base registers. */
1369 mips_classify_address (struct mips_address_info *info, rtx x,
1370 enum machine_mode mode, int strict)
1372 switch (GET_CODE (x))
1376 info->type = ADDRESS_REG;
1378 info->offset = const0_rtx;
1379 return mips_valid_base_register_p (info->reg, mode, strict);
1382 info->type = ADDRESS_REG;
1383 info->reg = XEXP (x, 0);
1384 info->offset = XEXP (x, 1);
1385 return (mips_valid_base_register_p (info->reg, mode, strict)
1386 && const_arith_operand (info->offset, VOIDmode));
1389 info->type = ADDRESS_LO_SUM;
1390 info->reg = XEXP (x, 0);
1391 info->offset = XEXP (x, 1);
1392 return (mips_valid_base_register_p (info->reg, mode, strict)
1393 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1394 && mips_symbolic_address_p (info->symbol_type, mode)
1395 && mips_lo_relocs[info->symbol_type] != 0);
1398 /* Small-integer addresses don't occur very often, but they
1399 are legitimate if $0 is a valid base register. */
1400 info->type = ADDRESS_CONST_INT;
1401 return !TARGET_MIPS16 && SMALL_INT (x);
1406 info->type = ADDRESS_SYMBOLIC;
1407 return (mips_symbolic_constant_p (x, &info->symbol_type)
1408 && mips_symbolic_address_p (info->symbol_type, mode)
1409 && !mips_split_p[info->symbol_type]);
1416 /* Return true if X is a thread-local symbol. */
1419 mips_tls_operand_p (rtx x)
1421 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1424 /* Return true if X can not be forced into a constant pool. */
1427 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1429 return mips_tls_operand_p (*x);
1432 /* Return true if X can not be forced into a constant pool. */
1435 mips_cannot_force_const_mem (rtx x)
1437 if (! TARGET_HAVE_TLS)
1440 return for_each_rtx (&x, &mips_tls_symbol_ref_1, 0);
1443 /* Return the number of instructions needed to load a symbol of the
1444 given type into a register. If valid in an address, the same number
1445 of instructions are needed for loads and stores. Treat extended
1446 mips16 instructions as two instructions. */
1449 mips_symbol_insns (enum mips_symbol_type type)
1453 case SYMBOL_GENERAL:
1454 /* In mips16 code, general symbols must be fetched from the
1459 /* When using 64-bit symbols, we need 5 preparatory instructions,
1462 lui $at,%highest(symbol)
1463 daddiu $at,$at,%higher(symbol)
1465 daddiu $at,$at,%hi(symbol)
1468 The final address is then $at + %lo(symbol). With 32-bit
1469 symbols we just need a preparatory lui. */
1470 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1472 case SYMBOL_SMALL_DATA:
1475 case SYMBOL_CONSTANT_POOL:
1476 /* This case is for mips16 only. Assume we'll need an
1477 extended instruction. */
1480 case SYMBOL_GOT_LOCAL:
1481 case SYMBOL_GOT_GLOBAL:
1482 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1483 the local/global classification is accurate. See override_options
1486 The worst cases are:
1488 (1) For local symbols when generating o32 or o64 code. The assembler
1494 ...and the final address will be $at + %lo(symbol).
1496 (2) For global symbols when -mxgot. The assembler will use:
1498 lui $at,%got_hi(symbol)
1501 ...and the final address will be $at + %got_lo(symbol). */
1504 case SYMBOL_GOTOFF_PAGE:
1505 case SYMBOL_GOTOFF_GLOBAL:
1506 case SYMBOL_GOTOFF_CALL:
1507 case SYMBOL_GOTOFF_LOADGP:
1508 case SYMBOL_64_HIGH:
1514 case SYMBOL_GOTTPREL:
1516 /* Check whether the offset is a 16- or 32-bit value. */
1517 return mips_split_p[type] ? 2 : 1;
1520 /* We don't treat a bare TLS symbol as a constant. */
1526 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1529 mips_stack_address_p (rtx x, enum machine_mode mode)
1531 struct mips_address_info addr;
1533 return (mips_classify_address (&addr, x, mode, false)
1534 && addr.type == ADDRESS_REG
1535 && addr.reg == stack_pointer_rtx);
1538 /* Return true if a value at OFFSET bytes from BASE can be accessed
1539 using an unextended mips16 instruction. MODE is the mode of the
1542 Usually the offset in an unextended instruction is a 5-bit field.
1543 The offset is unsigned and shifted left once for HIs, twice
1544 for SIs, and so on. An exception is SImode accesses off the
1545 stack pointer, which have an 8-bit immediate field. */
1548 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1551 && GET_CODE (offset) == CONST_INT
1552 && INTVAL (offset) >= 0
1553 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1555 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1556 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1557 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1563 /* Return the number of instructions needed to load or store a value
1564 of mode MODE at X. Return 0 if X isn't valid for MODE.
1566 For mips16 code, count extended instructions as two instructions. */
1569 mips_address_insns (rtx x, enum machine_mode mode)
1571 struct mips_address_info addr;
1574 if (mode == BLKmode)
1575 /* BLKmode is used for single unaligned loads and stores. */
1578 /* Each word of a multi-word value will be accessed individually. */
1579 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1581 if (mips_classify_address (&addr, x, mode, false))
1586 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1590 case ADDRESS_LO_SUM:
1591 return (TARGET_MIPS16 ? factor * 2 : factor);
1593 case ADDRESS_CONST_INT:
1596 case ADDRESS_SYMBOLIC:
1597 return factor * mips_symbol_insns (addr.symbol_type);
1603 /* Likewise for constant X. */
1606 mips_const_insns (rtx x)
1608 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1609 enum mips_symbol_type symbol_type;
1610 HOST_WIDE_INT offset;
1612 switch (GET_CODE (x))
1616 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1617 || !mips_split_p[symbol_type])
1624 /* Unsigned 8-bit constants can be loaded using an unextended
1625 LI instruction. Unsigned 16-bit constants can be loaded
1626 using an extended LI. Negative constants must be loaded
1627 using LI and then negated. */
1628 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1629 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1630 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1631 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1634 return mips_build_integer (codes, INTVAL (x));
1638 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1644 /* See if we can refer to X directly. */
1645 if (mips_symbolic_constant_p (x, &symbol_type))
1646 return mips_symbol_insns (symbol_type);
1648 /* Otherwise try splitting the constant into a base and offset.
1649 16-bit offsets can be added using an extra addiu. Larger offsets
1650 must be calculated separately and then added to the base. */
1651 mips_split_const (x, &x, &offset);
1654 int n = mips_const_insns (x);
1657 if (SMALL_OPERAND (offset))
1660 return n + 1 + mips_build_integer (codes, offset);
1667 return mips_symbol_insns (mips_classify_symbol (x));
1675 /* Return the number of instructions needed for memory reference X.
1676 Count extended mips16 instructions as two instructions. */
1679 mips_fetch_insns (rtx x)
1681 gcc_assert (MEM_P (x));
1682 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1686 /* Return the number of instructions needed for an integer division. */
1689 mips_idiv_insns (void)
1694 if (TARGET_CHECK_ZERO_DIV)
1696 if (GENERATE_DIVIDE_TRAPS)
1702 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1707 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1708 returns a nonzero value if X is a legitimate address for a memory
1709 operand of the indicated MODE. STRICT is nonzero if this function
1710 is called during reload. */
1713 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1715 struct mips_address_info addr;
1717 return mips_classify_address (&addr, x, mode, strict);
1721 /* Copy VALUE to a register and return that register. If new psuedos
1722 are allowed, copy it into a new register, otherwise use DEST. */
1725 mips_force_temporary (rtx dest, rtx value)
1727 if (!no_new_pseudos)
1728 return force_reg (Pmode, value);
1731 emit_move_insn (copy_rtx (dest), value);
1737 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1738 and is used to load the high part into a register. */
1741 mips_split_symbol (rtx temp, rtx addr)
1746 high = mips16_gp_pseudo_reg ();
1748 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1749 return gen_rtx_LO_SUM (Pmode, high, addr);
1753 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1754 type SYMBOL_TYPE. */
1757 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1760 HOST_WIDE_INT offset;
1762 mips_split_const (address, &base, &offset);
1763 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1764 UNSPEC_ADDRESS_FIRST + symbol_type);
1765 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1769 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1770 high part to BASE and return the result. Just return BASE otherwise.
1771 TEMP is available as a temporary register if needed.
1773 The returned expression can be used as the first operand to a LO_SUM. */
1776 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1777 enum mips_symbol_type symbol_type)
1779 if (mips_split_p[symbol_type])
1781 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1782 addr = mips_force_temporary (temp, addr);
1783 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1789 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1790 mips_force_temporary; it is only needed when OFFSET is not a
1794 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1796 if (!SMALL_OPERAND (offset))
1801 /* Load the full offset into a register so that we can use
1802 an unextended instruction for the address itself. */
1803 high = GEN_INT (offset);
1808 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1809 high = GEN_INT (CONST_HIGH_PART (offset));
1810 offset = CONST_LOW_PART (offset);
1812 high = mips_force_temporary (temp, high);
1813 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1815 return plus_constant (reg, offset);
1818 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1819 referencing, and TYPE is the symbol type to use (either global
1820 dynamic or local dynamic). V0 is an RTX for the return value
1821 location. The entire insn sequence is returned. */
1823 static GTY(()) rtx mips_tls_symbol;
1826 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
1828 rtx insn, loc, tga, a0;
1830 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
1832 if (!mips_tls_symbol)
1833 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
1835 loc = mips_unspec_address (sym, type);
1839 emit_insn (gen_rtx_SET (Pmode, a0,
1840 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
1841 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
1842 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
1843 CONST_OR_PURE_CALL_P (insn) = 1;
1844 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
1845 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
1846 insn = get_insns ();
1853 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
1854 return value will be a valid address and move_operand (either a REG
1858 mips_legitimize_tls_address (rtx loc)
1860 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
1861 enum tls_model model;
1863 v0 = gen_rtx_REG (Pmode, GP_RETURN);
1864 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
1866 model = SYMBOL_REF_TLS_MODEL (loc);
1870 case TLS_MODEL_GLOBAL_DYNAMIC:
1871 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
1872 dest = gen_reg_rtx (Pmode);
1873 emit_libcall_block (insn, dest, v0, loc);
1876 case TLS_MODEL_LOCAL_DYNAMIC:
1877 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
1878 tmp1 = gen_reg_rtx (Pmode);
1880 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
1881 share the LDM result with other LD model accesses. */
1882 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1884 emit_libcall_block (insn, tmp1, v0, eqv);
1886 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
1887 dest = gen_rtx_LO_SUM (Pmode, tmp2,
1888 mips_unspec_address (loc, SYMBOL_DTPREL));
1891 case TLS_MODEL_INITIAL_EXEC:
1892 tmp1 = gen_reg_rtx (Pmode);
1893 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
1894 if (Pmode == DImode)
1896 emit_insn (gen_tls_get_tp_di (v1));
1897 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
1901 emit_insn (gen_tls_get_tp_si (v1));
1902 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
1904 dest = gen_reg_rtx (Pmode);
1905 emit_insn (gen_add3_insn (dest, tmp1, v1));
1908 case TLS_MODEL_LOCAL_EXEC:
1910 if (Pmode == DImode)
1911 emit_insn (gen_tls_get_tp_di (v1));
1913 emit_insn (gen_tls_get_tp_si (v1));
1915 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
1916 dest = gen_rtx_LO_SUM (Pmode, tmp1,
1917 mips_unspec_address (loc, SYMBOL_TPREL));
1927 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1928 be legitimized in a way that the generic machinery might not expect,
1929 put the new address in *XLOC and return true. MODE is the mode of
1930 the memory being accessed. */
1933 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1935 enum mips_symbol_type symbol_type;
1937 if (mips_tls_operand_p (*xloc))
1939 *xloc = mips_legitimize_tls_address (*xloc);
1943 /* See if the address can split into a high part and a LO_SUM. */
1944 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1945 && mips_symbolic_address_p (symbol_type, mode)
1946 && mips_split_p[symbol_type])
1948 *xloc = mips_split_symbol (0, *xloc);
1952 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1954 /* Handle REG + CONSTANT using mips_add_offset. */
1957 reg = XEXP (*xloc, 0);
1958 if (!mips_valid_base_register_p (reg, mode, 0))
1959 reg = copy_to_mode_reg (Pmode, reg);
1960 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
1968 /* Subroutine of mips_build_integer (with the same interface).
1969 Assume that the final action in the sequence should be a left shift. */
1972 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1974 unsigned int i, shift;
1976 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1977 since signed numbers are easier to load than unsigned ones. */
1979 while ((value & 1) == 0)
1980 value /= 2, shift++;
1982 i = mips_build_integer (codes, value);
1983 codes[i].code = ASHIFT;
1984 codes[i].value = shift;
1989 /* As for mips_build_shift, but assume that the final action will be
1990 an IOR or PLUS operation. */
1993 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1995 unsigned HOST_WIDE_INT high;
1998 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1999 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2001 /* The constant is too complex to load with a simple lui/ori pair
2002 so our goal is to clear as many trailing zeros as possible.
2003 In this case, we know bit 16 is set and that the low 16 bits
2004 form a negative number. If we subtract that number from VALUE,
2005 we will clear at least the lowest 17 bits, maybe more. */
2006 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2007 codes[i].code = PLUS;
2008 codes[i].value = CONST_LOW_PART (value);
2012 i = mips_build_integer (codes, high);
2013 codes[i].code = IOR;
2014 codes[i].value = value & 0xffff;
2020 /* Fill CODES with a sequence of rtl operations to load VALUE.
2021 Return the number of operations needed. */
2024 mips_build_integer (struct mips_integer_op *codes,
2025 unsigned HOST_WIDE_INT value)
2027 if (SMALL_OPERAND (value)
2028 || SMALL_OPERAND_UNSIGNED (value)
2029 || LUI_OPERAND (value))
2031 /* The value can be loaded with a single instruction. */
2032 codes[0].code = UNKNOWN;
2033 codes[0].value = value;
2036 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2038 /* Either the constant is a simple LUI/ORI combination or its
2039 lowest bit is set. We don't want to shift in this case. */
2040 return mips_build_lower (codes, value);
2042 else if ((value & 0xffff) == 0)
2044 /* The constant will need at least three actions. The lowest
2045 16 bits are clear, so the final action will be a shift. */
2046 return mips_build_shift (codes, value);
2050 /* The final action could be a shift, add or inclusive OR.
2051 Rather than use a complex condition to select the best
2052 approach, try both mips_build_shift and mips_build_lower
2053 and pick the one that gives the shortest sequence.
2054 Note that this case is only used once per constant. */
2055 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2056 unsigned int cost, alt_cost;
2058 cost = mips_build_shift (codes, value);
2059 alt_cost = mips_build_lower (alt_codes, value);
2060 if (alt_cost < cost)
2062 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2070 /* Move VALUE into register DEST. */
2073 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
2075 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2076 enum machine_mode mode;
2077 unsigned int i, cost;
2080 mode = GET_MODE (dest);
2081 cost = mips_build_integer (codes, value);
2083 /* Apply each binary operation to X. Invariant: X is a legitimate
2084 source operand for a SET pattern. */
2085 x = GEN_INT (codes[0].value);
2086 for (i = 1; i < cost; i++)
2089 emit_move_insn (dest, x), x = dest;
2091 x = force_reg (mode, x);
2092 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2095 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2099 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2100 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2104 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2107 HOST_WIDE_INT offset;
2108 enum mips_symbol_type symbol_type;
2110 /* Split moves of big integers into smaller pieces. In mips16 code,
2111 it's better to force the constant into memory instead. */
2112 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
2114 mips_move_integer (dest, INTVAL (src));
2118 if (mips_tls_operand_p (src))
2120 emit_move_insn (dest, mips_legitimize_tls_address (src));
2124 /* See if the symbol can be split. For mips16, this is often worse than
2125 forcing it in the constant pool since it needs the single-register form
2126 of addiu or daddiu. */
2128 && mips_symbolic_constant_p (src, &symbol_type)
2129 && mips_split_p[symbol_type])
2131 emit_move_insn (dest, mips_split_symbol (dest, src));
2135 /* If we have (const (plus symbol offset)), load the symbol first
2136 and then add in the offset. This is usually better than forcing
2137 the constant into memory, at least in non-mips16 code. */
2138 mips_split_const (src, &base, &offset);
2141 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2143 base = mips_force_temporary (dest, base);
2144 emit_move_insn (dest, mips_add_offset (0, base, offset));
2148 src = force_const_mem (mode, src);
2150 /* When using explicit relocs, constant pool references are sometimes
2151 not legitimate addresses. */
2152 if (!memory_operand (src, VOIDmode))
2153 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2154 emit_move_insn (dest, src);
2158 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2159 sequence that is valid. */
2162 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2164 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2166 emit_move_insn (dest, force_reg (mode, src));
2170 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2171 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2172 && REG_P (src) && MD_REG_P (REGNO (src))
2173 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2175 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2176 if (GET_MODE_SIZE (mode) <= 4)
2177 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2178 gen_rtx_REG (SImode, REGNO (src)),
2179 gen_rtx_REG (SImode, other_regno)));
2181 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2182 gen_rtx_REG (DImode, REGNO (src)),
2183 gen_rtx_REG (DImode, other_regno)));
2187 /* We need to deal with constants that would be legitimate
2188 immediate_operands but not legitimate move_operands. */
2189 if (CONSTANT_P (src) && !move_operand (src, mode))
2191 mips_legitimize_const_move (mode, dest, src);
2192 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2198 /* We need a lot of little routines to check constant values on the
2199 mips16. These are used to figure out how long the instruction will
2200 be. It would be much better to do this using constraints, but
2201 there aren't nearly enough letters available. */
2204 m16_check_op (rtx op, int low, int high, int mask)
2206 return (GET_CODE (op) == CONST_INT
2207 && INTVAL (op) >= low
2208 && INTVAL (op) <= high
2209 && (INTVAL (op) & mask) == 0);
2213 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2215 return m16_check_op (op, 0x1, 0x8, 0);
2219 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2221 return m16_check_op (op, - 0x8, 0x7, 0);
2225 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2227 return m16_check_op (op, - 0x7, 0x8, 0);
2231 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2233 return m16_check_op (op, - 0x10, 0xf, 0);
2237 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2239 return m16_check_op (op, - 0xf, 0x10, 0);
2243 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2245 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2249 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2251 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2255 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2257 return m16_check_op (op, - 0x80, 0x7f, 0);
2261 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2263 return m16_check_op (op, - 0x7f, 0x80, 0);
2267 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2269 return m16_check_op (op, 0x0, 0xff, 0);
2273 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2275 return m16_check_op (op, - 0xff, 0x0, 0);
2279 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2281 return m16_check_op (op, - 0x1, 0xfe, 0);
2285 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2287 return m16_check_op (op, 0x0, 0xff << 2, 3);
2291 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2293 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2297 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2299 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2303 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2305 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2309 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2311 enum machine_mode mode = GET_MODE (x);
2312 bool float_mode_p = FLOAT_MODE_P (mode);
2319 /* A number between 1 and 8 inclusive is efficient for a shift.
2320 Otherwise, we will need an extended instruction. */
2321 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2322 || (outer_code) == LSHIFTRT)
2324 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2327 *total = COSTS_N_INSNS (1);
2331 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2332 if ((outer_code) == XOR
2333 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2339 /* We may be able to use slt or sltu for a comparison with a
2340 signed 16 bit value. (The boundary conditions aren't quite
2341 right, but this is just a heuristic anyhow.) */
2342 if (((outer_code) == LT || (outer_code) == LE
2343 || (outer_code) == GE || (outer_code) == GT
2344 || (outer_code) == LTU || (outer_code) == LEU
2345 || (outer_code) == GEU || (outer_code) == GTU)
2346 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2352 /* Equality comparisons with 0 are cheap. */
2353 if (((outer_code) == EQ || (outer_code) == NE)
2360 /* Constants in the range 0...255 can be loaded with an unextended
2361 instruction. They are therefore as cheap as a register move.
2363 Given the choice between "li R1,0...255" and "move R1,R2"
2364 (where R2 is a known constant), it is usually better to use "li",
2365 since we do not want to unnecessarily extend the lifetime
2367 if (outer_code == SET
2369 && INTVAL (x) < 256)
2377 /* These can be used anywhere. */
2382 /* Otherwise fall through to the handling below because
2383 we'll need to construct the constant. */
2389 if (LEGITIMATE_CONSTANT_P (x))
2391 *total = COSTS_N_INSNS (1);
2396 /* The value will need to be fetched from the constant pool. */
2397 *total = CONSTANT_POOL_COST;
2403 /* If the address is legitimate, return the number of
2404 instructions it needs, otherwise use the default handling. */
2405 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2408 *total = COSTS_N_INSNS (n + 1);
2415 *total = COSTS_N_INSNS (6);
2419 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2425 if (mode == DImode && !TARGET_64BIT)
2427 *total = COSTS_N_INSNS (2);
2435 if (mode == DImode && !TARGET_64BIT)
2437 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2445 *total = COSTS_N_INSNS (1);
2447 *total = COSTS_N_INSNS (4);
2451 *total = COSTS_N_INSNS (1);
2458 *total = mips_cost->fp_add;
2462 else if (mode == DImode && !TARGET_64BIT)
2464 *total = COSTS_N_INSNS (4);
2470 if (mode == DImode && !TARGET_64BIT)
2472 *total = COSTS_N_INSNS (4);
2479 *total = mips_cost->fp_mult_sf;
2481 else if (mode == DFmode)
2482 *total = mips_cost->fp_mult_df;
2484 else if (mode == SImode)
2485 *total = mips_cost->int_mult_si;
2488 *total = mips_cost->int_mult_di;
2497 *total = mips_cost->fp_div_sf;
2499 *total = mips_cost->fp_div_df;
2508 *total = mips_cost->int_div_di;
2510 *total = mips_cost->int_div_si;
2515 /* A sign extend from SImode to DImode in 64 bit mode is often
2516 zero instructions, because the result can often be used
2517 directly by another instruction; we'll call it one. */
2518 if (TARGET_64BIT && mode == DImode
2519 && GET_MODE (XEXP (x, 0)) == SImode)
2520 *total = COSTS_N_INSNS (1);
2522 *total = COSTS_N_INSNS (2);
2526 if (TARGET_64BIT && mode == DImode
2527 && GET_MODE (XEXP (x, 0)) == SImode)
2528 *total = COSTS_N_INSNS (2);
2530 *total = COSTS_N_INSNS (1);
2534 case UNSIGNED_FLOAT:
2537 case FLOAT_TRUNCATE:
2539 *total = mips_cost->fp_add;
2547 /* Provide the costs of an addressing mode that contains ADDR.
2548 If ADDR is not a valid address, its cost is irrelevant. */
2551 mips_address_cost (rtx addr)
2553 return mips_address_insns (addr, SImode);
2556 /* Return one word of double-word value OP, taking into account the fixed
2557 endianness of certain registers. HIGH_P is true to select the high part,
2558 false to select the low part. */
2561 mips_subword (rtx op, int high_p)
2564 enum machine_mode mode;
2566 mode = GET_MODE (op);
2567 if (mode == VOIDmode)
2570 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2571 byte = UNITS_PER_WORD;
2577 if (FP_REG_P (REGNO (op)))
2578 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2579 if (REGNO (op) == HI_REGNUM)
2580 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2584 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2586 return simplify_gen_subreg (word_mode, op, mode, byte);
2590 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2593 mips_split_64bit_move_p (rtx dest, rtx src)
2598 /* FP->FP moves can be done in a single instruction. */
2599 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2602 /* Check for floating-point loads and stores. They can be done using
2603 ldc1 and sdc1 on MIPS II and above. */
2606 if (FP_REG_RTX_P (dest) && MEM_P (src))
2608 if (FP_REG_RTX_P (src) && MEM_P (dest))
2615 /* Split a 64-bit move from SRC to DEST assuming that
2616 mips_split_64bit_move_p holds.
2618 Moves into and out of FPRs cause some difficulty here. Such moves
2619 will always be DFmode, since paired FPRs are not allowed to store
2620 DImode values. The most natural representation would be two separate
2621 32-bit moves, such as:
2623 (set (reg:SI $f0) (mem:SI ...))
2624 (set (reg:SI $f1) (mem:SI ...))
2626 However, the second insn is invalid because odd-numbered FPRs are
2627 not allowed to store independent values. Use the patterns load_df_low,
2628 load_df_high and store_df_high instead. */
2631 mips_split_64bit_move (rtx dest, rtx src)
2633 if (FP_REG_RTX_P (dest))
2635 /* Loading an FPR from memory or from GPRs. */
2636 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2637 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2640 else if (FP_REG_RTX_P (src))
2642 /* Storing an FPR into memory or GPRs. */
2643 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2644 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2648 /* The operation can be split into two normal moves. Decide in
2649 which order to do them. */
2652 low_dest = mips_subword (dest, 0);
2653 if (REG_P (low_dest)
2654 && reg_overlap_mentioned_p (low_dest, src))
2656 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2657 emit_move_insn (low_dest, mips_subword (src, 0));
2661 emit_move_insn (low_dest, mips_subword (src, 0));
2662 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2667 /* Return the appropriate instructions to move SRC into DEST. Assume
2668 that SRC is operand 1 and DEST is operand 0. */
2671 mips_output_move (rtx dest, rtx src)
2673 enum rtx_code dest_code, src_code;
2676 dest_code = GET_CODE (dest);
2677 src_code = GET_CODE (src);
2678 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2680 if (dbl_p && mips_split_64bit_move_p (dest, src))
2683 if ((src_code == REG && GP_REG_P (REGNO (src)))
2684 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2686 if (dest_code == REG)
2688 if (GP_REG_P (REGNO (dest)))
2689 return "move\t%0,%z1";
2691 if (MD_REG_P (REGNO (dest)))
2694 if (FP_REG_P (REGNO (dest)))
2695 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2697 if (ALL_COP_REG_P (REGNO (dest)))
2699 static char retval[] = "dmtc_\t%z1,%0";
2701 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2702 return (dbl_p ? retval : retval + 1);
2705 if (dest_code == MEM)
2706 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2708 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2710 if (src_code == REG)
2712 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2713 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2715 if (FP_REG_P (REGNO (src)))
2716 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2718 if (ALL_COP_REG_P (REGNO (src)))
2720 static char retval[] = "dmfc_\t%0,%1";
2722 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2723 return (dbl_p ? retval : retval + 1);
2727 if (src_code == MEM)
2728 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2730 if (src_code == CONST_INT)
2732 /* Don't use the X format, because that will give out of
2733 range numbers for 64 bit hosts and 32 bit targets. */
2735 return "li\t%0,%1\t\t\t# %X1";
2737 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2740 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2744 if (src_code == HIGH)
2745 return "lui\t%0,%h1";
2747 if (CONST_GP_P (src))
2748 return "move\t%0,%1";
2750 if (symbolic_operand (src, VOIDmode))
2751 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2753 if (src_code == REG && FP_REG_P (REGNO (src)))
2755 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2757 if (GET_MODE (dest) == V2SFmode)
2758 return "mov.ps\t%0,%1";
2760 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2763 if (dest_code == MEM)
2764 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2766 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2768 if (src_code == MEM)
2769 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2771 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2773 static char retval[] = "l_c_\t%0,%1";
2775 retval[1] = (dbl_p ? 'd' : 'w');
2776 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2779 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2781 static char retval[] = "s_c_\t%1,%0";
2783 retval[1] = (dbl_p ? 'd' : 'w');
2784 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2790 /* Restore $gp from its save slot. Valid only when using o32 or
2794 mips_restore_gp (void)
2798 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2800 address = mips_add_offset (pic_offset_table_rtx,
2801 frame_pointer_needed
2802 ? hard_frame_pointer_rtx
2803 : stack_pointer_rtx,
2804 current_function_outgoing_args_size);
2805 slot = gen_rtx_MEM (Pmode, address);
2807 emit_move_insn (pic_offset_table_rtx, slot);
2808 if (!TARGET_EXPLICIT_RELOCS)
2809 emit_insn (gen_blockage ());
2812 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2815 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2817 emit_insn (gen_rtx_SET (VOIDmode, target,
2818 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2821 /* Return true if CMP1 is a suitable second operand for relational
2822 operator CODE. See also the *sCC patterns in mips.md. */
2825 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
2831 return reg_or_0_operand (cmp1, VOIDmode);
2835 return !TARGET_MIPS16 && cmp1 == const1_rtx;
2839 return arith_operand (cmp1, VOIDmode);
2842 return sle_operand (cmp1, VOIDmode);
2845 return sleu_operand (cmp1, VOIDmode);
2852 /* Compare CMP0 and CMP1 using relational operator CODE and store the
2853 result in TARGET. CMP0 and TARGET are register_operands that have
2854 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
2855 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
2858 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
2859 rtx target, rtx cmp0, rtx cmp1)
2861 /* First see if there is a MIPS instruction that can do this operation
2862 with CMP1 in its current form. If not, try doing the same for the
2863 inverse operation. If that also fails, force CMP1 into a register
2865 if (mips_relational_operand_ok_p (code, cmp1))
2866 mips_emit_binary (code, target, cmp0, cmp1);
2869 enum rtx_code inv_code = reverse_condition (code);
2870 if (!mips_relational_operand_ok_p (inv_code, cmp1))
2872 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
2873 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
2875 else if (invert_ptr == 0)
2877 rtx inv_target = gen_reg_rtx (GET_MODE (target));
2878 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
2879 mips_emit_binary (XOR, target, inv_target, const1_rtx);
2883 *invert_ptr = !*invert_ptr;
2884 mips_emit_binary (inv_code, target, cmp0, cmp1);
2889 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2890 The register will have the same mode as CMP0. */
2893 mips_zero_if_equal (rtx cmp0, rtx cmp1)
2895 if (cmp1 == const0_rtx)
2898 if (uns_arith_operand (cmp1, VOIDmode))
2899 return expand_binop (GET_MODE (cmp0), xor_optab,
2900 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2902 return expand_binop (GET_MODE (cmp0), sub_optab,
2903 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2906 /* Convert a comparison into something that can be used in a branch or
2907 conditional move. cmp_operands[0] and cmp_operands[1] are the values
2908 being compared and *CODE is the code used to compare them.
2910 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
2911 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
2912 otherwise any standard branch condition can be used. The standard branch
2915 - EQ/NE between two registers.
2916 - any comparison between a register and zero. */
2919 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
2921 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
2923 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
2925 *op0 = cmp_operands[0];
2926 *op1 = cmp_operands[1];
2928 else if (*code == EQ || *code == NE)
2932 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
2937 *op0 = cmp_operands[0];
2938 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
2943 /* The comparison needs a separate scc instruction. Store the
2944 result of the scc in *OP0 and compare it against zero. */
2945 bool invert = false;
2946 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
2948 mips_emit_int_relational (*code, &invert, *op0,
2949 cmp_operands[0], cmp_operands[1]);
2950 *code = (invert ? EQ : NE);
2955 enum rtx_code cmp_code;
2957 /* Floating-point tests use a separate c.cond.fmt comparison to
2958 set a condition code register. The branch or conditional move
2959 will then compare that register against zero.
2961 Set CMP_CODE to the code of the comparison instruction and
2962 *CODE to the code that the branch or move should use. */
2968 cmp_code = reverse_condition_maybe_unordered (*code);
2978 ? gen_reg_rtx (CCmode)
2979 : gen_rtx_REG (CCmode, FPSW_REGNUM));
2981 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
2985 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
2986 Store the result in TARGET and return true if successful.
2988 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
2991 mips_emit_scc (enum rtx_code code, rtx target)
2993 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
2996 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
2997 if (code == EQ || code == NE)
2999 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3000 mips_emit_binary (code, target, zie, const0_rtx);
3003 mips_emit_int_relational (code, 0, target,
3004 cmp_operands[0], cmp_operands[1]);
3008 /* Emit the common code for doing conditional branches.
3009 operand[0] is the label to jump to.
3010 The comparison operands are saved away by cmp{si,di,sf,df}. */
3013 gen_conditional_branch (rtx *operands, enum rtx_code code)
3015 rtx op0, op1, target;
3017 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3018 target = gen_rtx_IF_THEN_ELSE (VOIDmode,
3019 gen_rtx_fmt_ee (code, GET_MODE (op0),
3021 gen_rtx_LABEL_REF (VOIDmode, operands[0]),
3023 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, target));
3026 /* Emit the common code for conditional moves. OPERANDS is the array
3027 of operands passed to the conditional move define_expand. */
3030 gen_conditional_move (rtx *operands)
3035 code = GET_CODE (operands[1]);
3036 mips_emit_compare (&code, &op0, &op1, true);
3037 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3038 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3039 gen_rtx_fmt_ee (code,
3042 operands[2], operands[3])));
3045 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3046 the conditional_trap expander. */
3049 mips_gen_conditional_trap (rtx *operands)
3052 enum rtx_code cmp_code = GET_CODE (operands[0]);
3053 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3055 /* MIPS conditional trap machine instructions don't have GT or LE
3056 flavors, so we must invert the comparison and convert to LT and
3057 GE, respectively. */
3060 case GT: cmp_code = LT; break;
3061 case LE: cmp_code = GE; break;
3062 case GTU: cmp_code = LTU; break;
3063 case LEU: cmp_code = GEU; break;
3066 if (cmp_code == GET_CODE (operands[0]))
3068 op0 = cmp_operands[0];
3069 op1 = cmp_operands[1];
3073 op0 = cmp_operands[1];
3074 op1 = cmp_operands[0];
3076 op0 = force_reg (mode, op0);
3077 if (!arith_operand (op1, mode))
3078 op1 = force_reg (mode, op1);
3080 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3081 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3085 /* Load function address ADDR into register DEST. SIBCALL_P is true
3086 if the address is needed for a sibling call. */
3089 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3091 /* If we're generating PIC, and this call is to a global function,
3092 try to allow its address to be resolved lazily. This isn't
3093 possible for NewABI sibcalls since the value of $gp on entry
3094 to the stub would be our caller's gp, not ours. */
3095 if (TARGET_EXPLICIT_RELOCS
3096 && !(sibcall_p && TARGET_NEWABI)
3097 && global_got_operand (addr, VOIDmode))
3099 rtx high, lo_sum_symbol;
3101 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3102 addr, SYMBOL_GOTOFF_CALL);
3103 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3104 if (Pmode == SImode)
3105 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3107 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3110 emit_move_insn (dest, addr);
3114 /* Expand a call or call_value instruction. RESULT is where the
3115 result will go (null for calls), ADDR is the address of the
3116 function, ARGS_SIZE is the size of the arguments and AUX is
3117 the value passed to us by mips_function_arg. SIBCALL_P is true
3118 if we are expanding a sibling call, false if we're expanding
3122 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3124 rtx orig_addr, pattern, insn;
3127 if (!call_insn_operand (addr, VOIDmode))
3129 addr = gen_reg_rtx (Pmode);
3130 mips_load_call_address (addr, orig_addr, sibcall_p);
3134 && mips16_hard_float
3135 && build_mips16_call_stub (result, addr, args_size,
3136 aux == 0 ? 0 : (int) GET_MODE (aux)))
3140 pattern = (sibcall_p
3141 ? gen_sibcall_internal (addr, args_size)
3142 : gen_call_internal (addr, args_size));
3143 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3147 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3148 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3151 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3152 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3155 pattern = (sibcall_p
3156 ? gen_sibcall_value_internal (result, addr, args_size)
3157 : gen_call_value_internal (result, addr, args_size));
3159 insn = emit_call_insn (pattern);
3161 /* Lazy-binding stubs require $gp to be valid on entry. */
3162 if (global_got_operand (orig_addr, VOIDmode))
3163 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3167 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3170 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3171 tree exp ATTRIBUTE_UNUSED)
3173 return TARGET_SIBCALLS;
3176 /* Emit code to move general operand SRC into condition-code
3177 register DEST. SCRATCH is a scratch TFmode float register.
3184 where FP1 and FP2 are single-precision float registers
3185 taken from SCRATCH. */
3188 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3192 /* Change the source to SFmode. */
3194 src = adjust_address (src, SFmode, 0);
3195 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3196 src = gen_rtx_REG (SFmode, true_regnum (src));
3198 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3199 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3201 emit_move_insn (copy_rtx (fp1), src);
3202 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3203 emit_insn (gen_slt_sf (dest, fp2, fp1));
3206 /* Emit code to change the current function's return address to
3207 ADDRESS. SCRATCH is available as a scratch register, if needed.
3208 ADDRESS and SCRATCH are both word-mode GPRs. */
3211 mips_set_return_address (rtx address, rtx scratch)
3215 compute_frame_size (get_frame_size ());
3216 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3217 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3218 cfun->machine->frame.gp_sp_offset);
3220 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3223 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3224 Assume that the areas do not overlap. */
3227 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3229 HOST_WIDE_INT offset, delta;
3230 unsigned HOST_WIDE_INT bits;
3232 enum machine_mode mode;
3235 /* Work out how many bits to move at a time. If both operands have
3236 half-word alignment, it is usually better to move in half words.
3237 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3238 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3239 Otherwise move word-sized chunks. */
3240 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3241 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3242 bits = BITS_PER_WORD / 2;
3244 bits = BITS_PER_WORD;
3246 mode = mode_for_size (bits, MODE_INT, 0);
3247 delta = bits / BITS_PER_UNIT;
3249 /* Allocate a buffer for the temporary registers. */
3250 regs = alloca (sizeof (rtx) * length / delta);
3252 /* Load as many BITS-sized chunks as possible. Use a normal load if
3253 the source has enough alignment, otherwise use left/right pairs. */
3254 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3256 regs[i] = gen_reg_rtx (mode);
3257 if (MEM_ALIGN (src) >= bits)
3258 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3261 rtx part = adjust_address (src, BLKmode, offset);
3262 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3267 /* Copy the chunks to the destination. */
3268 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3269 if (MEM_ALIGN (dest) >= bits)
3270 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3273 rtx part = adjust_address (dest, BLKmode, offset);
3274 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3278 /* Mop up any left-over bytes. */
3279 if (offset < length)
3281 src = adjust_address (src, BLKmode, offset);
3282 dest = adjust_address (dest, BLKmode, offset);
3283 move_by_pieces (dest, src, length - offset,
3284 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3288 #define MAX_MOVE_REGS 4
3289 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3292 /* Helper function for doing a loop-based block operation on memory
3293 reference MEM. Each iteration of the loop will operate on LENGTH
3296 Create a new base register for use within the loop and point it to
3297 the start of MEM. Create a new memory reference that uses this
3298 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3301 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3302 rtx *loop_reg, rtx *loop_mem)
3304 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3306 /* Although the new mem does not refer to a known location,
3307 it does keep up to LENGTH bytes of alignment. */
3308 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3309 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3313 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3314 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3315 memory regions do not overlap. */
3318 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3320 rtx label, src_reg, dest_reg, final_src;
3321 HOST_WIDE_INT leftover;
3323 leftover = length % MAX_MOVE_BYTES;
3326 /* Create registers and memory references for use within the loop. */
3327 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3328 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3330 /* Calculate the value that SRC_REG should have after the last iteration
3332 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3335 /* Emit the start of the loop. */
3336 label = gen_label_rtx ();
3339 /* Emit the loop body. */
3340 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3342 /* Move on to the next block. */
3343 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3344 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3346 /* Emit the loop condition. */
3347 if (Pmode == DImode)
3348 emit_insn (gen_cmpdi (src_reg, final_src));
3350 emit_insn (gen_cmpsi (src_reg, final_src));
3351 emit_jump_insn (gen_bne (label));
3353 /* Mop up any left-over bytes. */
3355 mips_block_move_straight (dest, src, leftover);
3358 /* Expand a movmemsi instruction. */
3361 mips_expand_block_move (rtx dest, rtx src, rtx length)
3363 if (GET_CODE (length) == CONST_INT)
3365 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3367 mips_block_move_straight (dest, src, INTVAL (length));
3372 mips_block_move_loop (dest, src, INTVAL (length));
3379 /* Argument support functions. */
3381 /* Initialize CUMULATIVE_ARGS for a function. */
3384 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3385 rtx libname ATTRIBUTE_UNUSED)
3387 static CUMULATIVE_ARGS zero_cum;
3388 tree param, next_param;
3391 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3393 /* Determine if this function has variable arguments. This is
3394 indicated by the last argument being 'void_type_mode' if there
3395 are no variable arguments. The standard MIPS calling sequence
3396 passes all arguments in the general purpose registers in this case. */
3398 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3399 param != 0; param = next_param)
3401 next_param = TREE_CHAIN (param);
3402 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3403 cum->gp_reg_found = 1;
3408 /* Fill INFO with information about a single argument. CUM is the
3409 cumulative state for earlier arguments. MODE is the mode of this
3410 argument and TYPE is its type (if known). NAMED is true if this
3411 is a named (fixed) argument rather than a variable one. */
3414 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3415 tree type, int named, struct mips_arg_info *info)
3417 bool doubleword_aligned_p;
3418 unsigned int num_bytes, num_words, max_regs;
3420 /* Work out the size of the argument. */
3421 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3422 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3424 /* Decide whether it should go in a floating-point register, assuming
3425 one is free. Later code checks for availability.
3427 The checks against UNITS_PER_FPVALUE handle the soft-float and
3428 single-float cases. */
3432 /* The EABI conventions have traditionally been defined in terms
3433 of TYPE_MODE, regardless of the actual type. */
3434 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3435 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3436 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3441 /* Only leading floating-point scalars are passed in
3442 floating-point registers. We also handle vector floats the same
3443 say, which is OK because they are not covered by the standard ABI. */
3444 info->fpr_p = (!cum->gp_reg_found
3445 && cum->arg_number < 2
3446 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3447 || VECTOR_FLOAT_TYPE_P (type))
3448 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3449 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3450 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3455 /* Scalar and complex floating-point types are passed in
3456 floating-point registers. */
3457 info->fpr_p = (named
3458 && (type == 0 || FLOAT_TYPE_P (type))
3459 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3460 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3461 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3462 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3464 /* ??? According to the ABI documentation, the real and imaginary
3465 parts of complex floats should be passed in individual registers.
3466 The real and imaginary parts of stack arguments are supposed
3467 to be contiguous and there should be an extra word of padding
3470 This has two problems. First, it makes it impossible to use a
3471 single "void *" va_list type, since register and stack arguments
3472 are passed differently. (At the time of writing, MIPSpro cannot
3473 handle complex float varargs correctly.) Second, it's unclear
3474 what should happen when there is only one register free.
3476 For now, we assume that named complex floats should go into FPRs
3477 if there are two FPRs free, otherwise they should be passed in the
3478 same way as a struct containing two floats. */
3480 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3481 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3483 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3484 info->fpr_p = false;
3494 /* See whether the argument has doubleword alignment. */
3495 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3497 /* Set REG_OFFSET to the register count we're interested in.
3498 The EABI allocates the floating-point registers separately,
3499 but the other ABIs allocate them like integer registers. */
3500 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3504 /* Advance to an even register if the argument is doubleword-aligned. */
3505 if (doubleword_aligned_p)
3506 info->reg_offset += info->reg_offset & 1;
3508 /* Work out the offset of a stack argument. */
3509 info->stack_offset = cum->stack_words;
3510 if (doubleword_aligned_p)
3511 info->stack_offset += info->stack_offset & 1;
3513 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3515 /* Partition the argument between registers and stack. */
3516 info->reg_words = MIN (num_words, max_regs);
3517 info->stack_words = num_words - info->reg_words;
3521 /* Implement FUNCTION_ARG_ADVANCE. */
3524 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3525 tree type, int named)
3527 struct mips_arg_info info;
3529 mips_arg_info (cum, mode, type, named, &info);
3532 cum->gp_reg_found = true;
3534 /* See the comment above the cumulative args structure in mips.h
3535 for an explanation of what this code does. It assumes the O32
3536 ABI, which passes at most 2 arguments in float registers. */
3537 if (cum->arg_number < 2 && info.fpr_p)
3538 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3540 if (mips_abi != ABI_EABI || !info.fpr_p)
3541 cum->num_gprs = info.reg_offset + info.reg_words;
3542 else if (info.reg_words > 0)
3543 cum->num_fprs += FP_INC;
3545 if (info.stack_words > 0)
3546 cum->stack_words = info.stack_offset + info.stack_words;
3551 /* Implement FUNCTION_ARG. */
3554 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3555 tree type, int named)
3557 struct mips_arg_info info;
3559 /* We will be called with a mode of VOIDmode after the last argument
3560 has been seen. Whatever we return will be passed to the call
3561 insn. If we need a mips16 fp_code, return a REG with the code
3562 stored as the mode. */
3563 if (mode == VOIDmode)
3565 if (TARGET_MIPS16 && cum->fp_code != 0)
3566 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3572 mips_arg_info (cum, mode, type, named, &info);
3574 /* Return straight away if the whole argument is passed on the stack. */
3575 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3579 && TREE_CODE (type) == RECORD_TYPE
3581 && TYPE_SIZE_UNIT (type)
3582 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3585 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3586 structure contains a double in its entirety, then that 64 bit
3587 chunk is passed in a floating point register. */
3590 /* First check to see if there is any such field. */
3591 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3592 if (TREE_CODE (field) == FIELD_DECL
3593 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3594 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3595 && host_integerp (bit_position (field), 0)
3596 && int_bit_position (field) % BITS_PER_WORD == 0)
3601 /* Now handle the special case by returning a PARALLEL
3602 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3603 chunks are passed in registers. */
3605 HOST_WIDE_INT bitpos;
3608 /* assign_parms checks the mode of ENTRY_PARM, so we must
3609 use the actual mode here. */
3610 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3613 field = TYPE_FIELDS (type);
3614 for (i = 0; i < info.reg_words; i++)
3618 for (; field; field = TREE_CHAIN (field))
3619 if (TREE_CODE (field) == FIELD_DECL
3620 && int_bit_position (field) >= bitpos)
3624 && int_bit_position (field) == bitpos
3625 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3626 && !TARGET_SOFT_FLOAT
3627 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3628 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3630 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3633 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3634 GEN_INT (bitpos / BITS_PER_UNIT));
3636 bitpos += BITS_PER_WORD;
3642 /* Handle the n32/n64 conventions for passing complex floating-point
3643 arguments in FPR pairs. The real part goes in the lower register
3644 and the imaginary part goes in the upper register. */
3647 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3650 enum machine_mode inner;
3653 inner = GET_MODE_INNER (mode);
3654 reg = FP_ARG_FIRST + info.reg_offset;
3655 real = gen_rtx_EXPR_LIST (VOIDmode,
3656 gen_rtx_REG (inner, reg),
3658 imag = gen_rtx_EXPR_LIST (VOIDmode,
3659 gen_rtx_REG (inner, reg + info.reg_words / 2),
3660 GEN_INT (GET_MODE_SIZE (inner)));
3661 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3665 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3666 else if (info.reg_offset == 1)
3667 /* This code handles the special o32 case in which the second word
3668 of the argument structure is passed in floating-point registers. */
3669 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3671 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3675 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3678 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3679 enum machine_mode mode, tree type, bool named)
3681 struct mips_arg_info info;
3683 mips_arg_info (cum, mode, type, named, &info);
3684 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3688 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3689 PARM_BOUNDARY bits of alignment, but will be given anything up
3690 to STACK_BOUNDARY bits if the type requires it. */
3693 function_arg_boundary (enum machine_mode mode, tree type)
3695 unsigned int alignment;
3697 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3698 if (alignment < PARM_BOUNDARY)
3699 alignment = PARM_BOUNDARY;
3700 if (alignment > STACK_BOUNDARY)
3701 alignment = STACK_BOUNDARY;
3705 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3706 upward rather than downward. In other words, return true if the
3707 first byte of the stack slot has useful data, false if the last
3711 mips_pad_arg_upward (enum machine_mode mode, tree type)
3713 /* On little-endian targets, the first byte of every stack argument
3714 is passed in the first byte of the stack slot. */
3715 if (!BYTES_BIG_ENDIAN)
3718 /* Otherwise, integral types are padded downward: the last byte of a
3719 stack argument is passed in the last byte of the stack slot. */
3721 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3722 : GET_MODE_CLASS (mode) == MODE_INT)
3725 /* Big-endian o64 pads floating-point arguments downward. */
3726 if (mips_abi == ABI_O64)
3727 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3730 /* Other types are padded upward for o32, o64, n32 and n64. */
3731 if (mips_abi != ABI_EABI)
3734 /* Arguments smaller than a stack slot are padded downward. */
3735 if (mode != BLKmode)
3736 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3738 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3742 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3743 if the least significant byte of the register has useful data. Return
3744 the opposite if the most significant byte does. */
3747 mips_pad_reg_upward (enum machine_mode mode, tree type)
3749 /* No shifting is required for floating-point arguments. */
3750 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3751 return !BYTES_BIG_ENDIAN;
3753 /* Otherwise, apply the same padding to register arguments as we do
3754 to stack arguments. */
3755 return mips_pad_arg_upward (mode, type);
3759 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3760 tree type, int *pretend_size ATTRIBUTE_UNUSED,
3763 CUMULATIVE_ARGS local_cum;
3764 int gp_saved, fp_saved;
3766 /* The caller has advanced CUM up to, but not beyond, the last named
3767 argument. Advance a local copy of CUM past the last "real" named
3768 argument, to find out how many registers are left over. */
3771 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3773 /* Found out how many registers we need to save. */
3774 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3775 fp_saved = (EABI_FLOAT_VARARGS_P
3776 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3785 ptr = plus_constant (virtual_incoming_args_rtx,
3786 REG_PARM_STACK_SPACE (cfun->decl)
3787 - gp_saved * UNITS_PER_WORD);
3788 mem = gen_rtx_MEM (BLKmode, ptr);
3789 set_mem_alias_set (mem, get_varargs_alias_set ());
3791 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3796 /* We can't use move_block_from_reg, because it will use
3798 enum machine_mode mode;
3801 /* Set OFF to the offset from virtual_incoming_args_rtx of
3802 the first float register. The FP save area lies below
3803 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3804 off = -gp_saved * UNITS_PER_WORD;
3805 off &= ~(UNITS_PER_FPVALUE - 1);
3806 off -= fp_saved * UNITS_PER_FPREG;
3808 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3810 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3814 ptr = plus_constant (virtual_incoming_args_rtx, off);
3815 mem = gen_rtx_MEM (mode, ptr);
3816 set_mem_alias_set (mem, get_varargs_alias_set ());
3817 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3818 off += UNITS_PER_HWFPVALUE;
3822 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
3823 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
3824 + fp_saved * UNITS_PER_FPREG);
3827 /* Create the va_list data type.
3828 We keep 3 pointers, and two offsets.
3829 Two pointers are to the overflow area, which starts at the CFA.
3830 One of these is constant, for addressing into the GPR save area below it.
3831 The other is advanced up the stack through the overflow region.
3832 The third pointer is to the GPR save area. Since the FPR save area
3833 is just below it, we can address FPR slots off this pointer.
3834 We also keep two one-byte offsets, which are to be subtracted from the
3835 constant pointers to yield addresses in the GPR and FPR save areas.
3836 These are downcounted as float or non-float arguments are used,
3837 and when they get to zero, the argument must be obtained from the
3839 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3840 pointer is enough. It's started at the GPR save area, and is
3842 Note that the GPR save area is not constant size, due to optimization
3843 in the prologue. Hence, we can't use a design with two pointers
3844 and two offsets, although we could have designed this with two pointers
3845 and three offsets. */
3848 mips_build_builtin_va_list (void)
3850 if (EABI_FLOAT_VARARGS_P)
3852 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3855 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3857 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
3859 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
3861 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
3863 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
3864 unsigned_char_type_node);
3865 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
3866 unsigned_char_type_node);
3867 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
3868 warn on every user file. */
3869 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
3870 array = build_array_type (unsigned_char_type_node,
3871 build_index_type (index));
3872 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
3874 DECL_FIELD_CONTEXT (f_ovfl) = record;
3875 DECL_FIELD_CONTEXT (f_gtop) = record;
3876 DECL_FIELD_CONTEXT (f_ftop) = record;
3877 DECL_FIELD_CONTEXT (f_goff) = record;
3878 DECL_FIELD_CONTEXT (f_foff) = record;
3879 DECL_FIELD_CONTEXT (f_res) = record;
3881 TYPE_FIELDS (record) = f_ovfl;
3882 TREE_CHAIN (f_ovfl) = f_gtop;
3883 TREE_CHAIN (f_gtop) = f_ftop;
3884 TREE_CHAIN (f_ftop) = f_goff;
3885 TREE_CHAIN (f_goff) = f_foff;
3886 TREE_CHAIN (f_foff) = f_res;
3888 layout_type (record);
3891 else if (TARGET_IRIX && TARGET_IRIX6)
3892 /* On IRIX 6, this type is 'char *'. */
3893 return build_pointer_type (char_type_node);
3895 /* Otherwise, we use 'void *'. */
3896 return ptr_type_node;
3899 /* Implement va_start. */
3902 mips_va_start (tree valist, rtx nextarg)
3904 if (EABI_FLOAT_VARARGS_P)
3906 const CUMULATIVE_ARGS *cum;
3907 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
3908 tree ovfl, gtop, ftop, goff, foff;
3910 int gpr_save_area_size;
3911 int fpr_save_area_size;
3914 cum = ¤t_function_args_info;
3916 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
3918 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
3920 f_ovfl = TYPE_FIELDS (va_list_type_node);
3921 f_gtop = TREE_CHAIN (f_ovfl);
3922 f_ftop = TREE_CHAIN (f_gtop);
3923 f_goff = TREE_CHAIN (f_ftop);
3924 f_foff = TREE_CHAIN (f_goff);
3926 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
3928 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
3930 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
3932 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
3934 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
3937 /* Emit code to initialize OVFL, which points to the next varargs
3938 stack argument. CUM->STACK_WORDS gives the number of stack
3939 words used by named arguments. */
3940 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
3941 if (cum->stack_words > 0)
3942 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
3943 build_int_cst (NULL_TREE,
3944 cum->stack_words * UNITS_PER_WORD));
3945 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
3946 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3948 /* Emit code to initialize GTOP, the top of the GPR save area. */
3949 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
3950 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
3951 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3953 /* Emit code to initialize FTOP, the top of the FPR save area.
3954 This address is gpr_save_area_bytes below GTOP, rounded
3955 down to the next fp-aligned boundary. */
3956 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
3957 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
3958 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
3960 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
3961 build_int_cst (NULL_TREE, -fpr_offset));
3962 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
3963 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3965 /* Emit code to initialize GOFF, the offset from GTOP of the
3966 next GPR argument. */
3967 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
3968 build_int_cst (NULL_TREE, gpr_save_area_size));
3969 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3971 /* Likewise emit code to initialize FOFF, the offset from FTOP
3972 of the next FPR argument. */
3973 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
3974 build_int_cst (NULL_TREE, fpr_save_area_size));
3975 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3979 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
3980 std_expand_builtin_va_start (valist, nextarg);
3984 /* Implement va_arg. */
3987 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
3989 HOST_WIDE_INT size, rsize;
3993 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
3996 type = build_pointer_type (type);
3998 size = int_size_in_bytes (type);
3999 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4001 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4002 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4005 /* Not a simple merged stack. */
4007 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4008 tree ovfl, top, off, align;
4009 HOST_WIDE_INT osize;
4012 f_ovfl = TYPE_FIELDS (va_list_type_node);
4013 f_gtop = TREE_CHAIN (f_ovfl);
4014 f_ftop = TREE_CHAIN (f_gtop);
4015 f_goff = TREE_CHAIN (f_ftop);
4016 f_foff = TREE_CHAIN (f_goff);
4018 /* We maintain separate pointers and offsets for floating-point
4019 and integer arguments, but we need similar code in both cases.
4022 TOP be the top of the register save area;
4023 OFF be the offset from TOP of the next register;
4024 ADDR_RTX be the address of the argument;
4025 RSIZE be the number of bytes used to store the argument
4026 when it's in the register save area;
4027 OSIZE be the number of bytes used to store it when it's
4028 in the stack overflow area; and
4029 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4031 The code we want is:
4033 1: off &= -rsize; // round down
4036 4: addr_rtx = top - off;
4041 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4042 10: addr_rtx = ovfl + PADDING;
4046 [1] and [9] can sometimes be optimized away. */
4048 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4051 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4052 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4054 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4056 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4059 /* When floating-point registers are saved to the stack,
4060 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4061 of the float's precision. */
4062 rsize = UNITS_PER_HWFPVALUE;
4064 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4065 (= PARM_BOUNDARY bits). This can be different from RSIZE
4068 (1) On 32-bit targets when TYPE is a structure such as:
4070 struct s { float f; };
4072 Such structures are passed in paired FPRs, so RSIZE
4073 will be 8 bytes. However, the structure only takes
4074 up 4 bytes of memory, so OSIZE will only be 4.
4076 (2) In combinations such as -mgp64 -msingle-float
4077 -fshort-double. Doubles passed in registers
4078 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4079 but those passed on the stack take up
4080 UNITS_PER_WORD bytes. */
4081 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4085 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4087 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4089 if (rsize > UNITS_PER_WORD)
4091 /* [1] Emit code for: off &= -rsize. */
4092 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4093 build_int_cst (NULL_TREE, -rsize));
4094 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4095 gimplify_and_add (t, pre_p);
4100 /* [2] Emit code to branch if off == 0. */
4101 t = build (NE_EXPR, boolean_type_node, off,
4102 build_int_cst (TREE_TYPE (off), 0));
4103 addr = build (COND_EXPR, ptr_type_node, t, NULL, NULL);
4105 /* [5] Emit code for: off -= rsize. We do this as a form of
4106 post-increment not available to C. Also widen for the
4107 coming pointer arithmetic. */
4108 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4109 t = build (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4110 t = fold_convert (sizetype, t);
4111 t = fold_convert (TREE_TYPE (top), t);
4113 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4114 the argument has RSIZE - SIZE bytes of leading padding. */
4115 t = build (MINUS_EXPR, TREE_TYPE (top), top, t);
4116 if (BYTES_BIG_ENDIAN && rsize > size)
4118 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4120 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4122 COND_EXPR_THEN (addr) = t;
4124 if (osize > UNITS_PER_WORD)
4126 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4127 u = fold_convert (TREE_TYPE (ovfl),
4128 build_int_cst (NULL_TREE, osize - 1));
4129 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4130 u = fold_convert (TREE_TYPE (ovfl),
4131 build_int_cst (NULL_TREE, -osize));
4132 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4133 align = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4138 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4139 post-increment ovfl by osize. On big-endian machines,
4140 the argument has OSIZE - SIZE bytes of leading padding. */
4141 u = fold_convert (TREE_TYPE (ovfl),
4142 build_int_cst (NULL_TREE, osize));
4143 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4144 if (BYTES_BIG_ENDIAN && osize > size)
4146 u = fold_convert (TREE_TYPE (t),
4147 build_int_cst (NULL_TREE, osize - size));
4148 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4151 /* String [9] and [10,11] together. */
4153 t = build (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4154 COND_EXPR_ELSE (addr) = t;
4156 addr = fold_convert (build_pointer_type (type), addr);
4157 addr = build_fold_indirect_ref (addr);
4161 addr = build_fold_indirect_ref (addr);
4166 /* Return true if it is possible to use left/right accesses for a
4167 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4168 returning true, update *OP, *LEFT and *RIGHT as follows:
4170 *OP is a BLKmode reference to the whole field.
4172 *LEFT is a QImode reference to the first byte if big endian or
4173 the last byte if little endian. This address can be used in the
4174 left-side instructions (lwl, swl, ldl, sdl).
4176 *RIGHT is a QImode reference to the opposite end of the field and
4177 can be used in the patterning right-side instruction. */
4180 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4181 rtx *left, rtx *right)
4185 /* Check that the operand really is a MEM. Not all the extv and
4186 extzv predicates are checked. */
4190 /* Check that the size is valid. */
4191 if (width != 32 && (!TARGET_64BIT || width != 64))
4194 /* We can only access byte-aligned values. Since we are always passed
4195 a reference to the first byte of the field, it is not necessary to
4196 do anything with BITPOS after this check. */
4197 if (bitpos % BITS_PER_UNIT != 0)
4200 /* Reject aligned bitfields: we want to use a normal load or store
4201 instead of a left/right pair. */
4202 if (MEM_ALIGN (*op) >= width)
4205 /* Adjust *OP to refer to the whole field. This also has the effect
4206 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4207 *op = adjust_address (*op, BLKmode, 0);
4208 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4210 /* Get references to both ends of the field. We deliberately don't
4211 use the original QImode *OP for FIRST since the new BLKmode one
4212 might have a simpler address. */
4213 first = adjust_address (*op, QImode, 0);
4214 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4216 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4217 be the upper word and RIGHT the lower word. */
4218 if (TARGET_BIG_ENDIAN)
4219 *left = first, *right = last;
4221 *left = last, *right = first;
4227 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4228 Return true on success. We only handle cases where zero_extract is
4229 equivalent to sign_extract. */
4232 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4234 rtx left, right, temp;
4236 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4237 paradoxical word_mode subreg. This is the only case in which
4238 we allow the destination to be larger than the source. */
4239 if (GET_CODE (dest) == SUBREG
4240 && GET_MODE (dest) == DImode
4241 && SUBREG_BYTE (dest) == 0
4242 && GET_MODE (SUBREG_REG (dest)) == SImode)
4243 dest = SUBREG_REG (dest);
4245 /* After the above adjustment, the destination must be the same
4246 width as the source. */
4247 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4250 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4253 temp = gen_reg_rtx (GET_MODE (dest));
4254 if (GET_MODE (dest) == DImode)
4256 emit_insn (gen_mov_ldl (temp, src, left));
4257 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4261 emit_insn (gen_mov_lwl (temp, src, left));
4262 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4268 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4272 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4276 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4279 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4281 if (GET_MODE (src) == DImode)
4283 emit_insn (gen_mov_sdl (dest, src, left));
4284 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4288 emit_insn (gen_mov_swl (dest, src, left));
4289 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4294 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4295 source of an "ext" instruction or the destination of an "ins"
4296 instruction. OP must be a register operand and the following
4297 conditions must hold:
4299 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4300 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4301 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4303 Also reject lengths equal to a word as they are better handled
4304 by the move patterns. */
4307 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4309 HOST_WIDE_INT len, pos;
4311 if (!ISA_HAS_EXT_INS
4312 || !register_operand (op, VOIDmode)
4313 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4316 len = INTVAL (size);
4317 pos = INTVAL (position);
4319 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4320 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4326 /* Set up globals to generate code for the ISA or processor
4327 described by INFO. */
4330 mips_set_architecture (const struct mips_cpu_info *info)
4334 mips_arch_info = info;
4335 mips_arch = info->cpu;
4336 mips_isa = info->isa;
4341 /* Likewise for tuning. */
4344 mips_set_tune (const struct mips_cpu_info *info)
4348 mips_tune_info = info;
4349 mips_tune = info->cpu;
4353 /* Implement TARGET_HANDLE_OPTION. */
4356 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4361 if (strcmp (arg, "32") == 0)
4363 else if (strcmp (arg, "o64") == 0)
4365 else if (strcmp (arg, "n32") == 0)
4367 else if (strcmp (arg, "64") == 0)
4369 else if (strcmp (arg, "eabi") == 0)
4370 mips_abi = ABI_EABI;
4377 return mips_parse_cpu (arg) != 0;
4380 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4381 return mips_isa_info != 0;
4383 case OPT_mno_flush_func:
4384 mips_cache_flush_func = NULL;
4392 /* Set up the threshold for data to go into the small data area, instead
4393 of the normal data area, and detect any conflicts in the switches. */
4396 override_options (void)
4398 int i, start, regno;
4399 enum machine_mode mode;
4401 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4403 /* The following code determines the architecture and register size.
4404 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4405 The GAS and GCC code should be kept in sync as much as possible. */
4407 if (mips_arch_string != 0)
4408 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4410 if (mips_isa_info != 0)
4412 if (mips_arch_info == 0)
4413 mips_set_architecture (mips_isa_info);
4414 else if (mips_arch_info->isa != mips_isa_info->isa)
4415 error ("-%s conflicts with the other architecture options, "
4416 "which specify a %s processor",
4417 mips_isa_info->name,
4418 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4421 if (mips_arch_info == 0)
4423 #ifdef MIPS_CPU_STRING_DEFAULT
4424 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4426 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4430 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4431 error ("-march=%s is not compatible with the selected ABI",
4432 mips_arch_info->name);
4434 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4435 if (mips_tune_string != 0)
4436 mips_set_tune (mips_parse_cpu (mips_tune_string));
4438 if (mips_tune_info == 0)
4439 mips_set_tune (mips_arch_info);
4441 /* Set cost structure for the processor. */
4442 mips_cost = &mips_rtx_cost_data[mips_tune];
4444 if ((target_flags_explicit & MASK_64BIT) != 0)
4446 /* The user specified the size of the integer registers. Make sure
4447 it agrees with the ABI and ISA. */
4448 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4449 error ("-mgp64 used with a 32-bit processor");
4450 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4451 error ("-mgp32 used with a 64-bit ABI");
4452 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4453 error ("-mgp64 used with a 32-bit ABI");
4457 /* Infer the integer register size from the ABI and processor.
4458 Restrict ourselves to 32-bit registers if that's all the
4459 processor has, or if the ABI cannot handle 64-bit registers. */
4460 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4461 target_flags &= ~MASK_64BIT;
4463 target_flags |= MASK_64BIT;
4466 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4468 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4469 only one right answer here. */
4470 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4471 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4472 else if (!TARGET_64BIT && TARGET_FLOAT64)
4473 error ("unsupported combination: %s", "-mgp32 -mfp64");
4474 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4475 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4479 /* -msingle-float selects 32-bit float registers. Otherwise the
4480 float registers should be the same size as the integer ones. */
4481 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4482 target_flags |= MASK_FLOAT64;
4484 target_flags &= ~MASK_FLOAT64;
4487 /* End of code shared with GAS. */
4489 if ((target_flags_explicit & MASK_LONG64) == 0)
4491 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4492 target_flags |= MASK_LONG64;
4494 target_flags &= ~MASK_LONG64;
4497 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4498 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4500 /* For some configurations, it is useful to have -march control
4501 the default setting of MASK_SOFT_FLOAT. */
4502 switch ((int) mips_arch)
4504 case PROCESSOR_R4100:
4505 case PROCESSOR_R4111:
4506 case PROCESSOR_R4120:
4507 case PROCESSOR_R4130:
4508 target_flags |= MASK_SOFT_FLOAT;
4512 target_flags &= ~MASK_SOFT_FLOAT;
4518 flag_pcc_struct_return = 0;
4520 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4522 /* If neither -mbranch-likely nor -mno-branch-likely was given
4523 on the command line, set MASK_BRANCHLIKELY based on the target
4526 By default, we enable use of Branch Likely instructions on
4527 all architectures which support them with the following
4528 exceptions: when creating MIPS32 or MIPS64 code, and when
4529 tuning for architectures where their use tends to hurt
4532 The MIPS32 and MIPS64 architecture specifications say "Software
4533 is strongly encouraged to avoid use of Branch Likely
4534 instructions, as they will be removed from a future revision
4535 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4536 issue those instructions unless instructed to do so by
4538 if (ISA_HAS_BRANCHLIKELY
4539 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4540 && !(TUNE_MIPS5500 || TUNE_SB1))
4541 target_flags |= MASK_BRANCHLIKELY;
4543 target_flags &= ~MASK_BRANCHLIKELY;
4545 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4546 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4548 /* The effect of -mabicalls isn't defined for the EABI. */
4549 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4551 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4552 target_flags &= ~MASK_ABICALLS;
4555 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4556 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4557 /* ??? -non_shared turns off pic code generation, but this is not
4559 if (TARGET_ABICALLS)
4562 if (mips_section_threshold > 0)
4563 warning (0, "-G is incompatible with PIC code which is the default");
4566 /* mips_split_addresses is a half-way house between explicit
4567 relocations and the traditional assembler macros. It can
4568 split absolute 32-bit symbolic constants into a high/lo_sum
4569 pair but uses macros for other sorts of access.
4571 Like explicit relocation support for REL targets, it relies
4572 on GNU extensions in the assembler and the linker.
4574 Although this code should work for -O0, it has traditionally
4575 been treated as an optimization. */
4576 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4577 && optimize && !flag_pic
4578 && !ABI_HAS_64BIT_SYMBOLS)
4579 mips_split_addresses = 1;
4581 mips_split_addresses = 0;
4583 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4584 faster code, but at the expense of more nops. Enable it at -O3 and
4586 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4587 target_flags |= MASK_VR4130_ALIGN;
4589 /* When compiling for the mips16, we cannot use floating point. We
4590 record the original hard float value in mips16_hard_float. */
4593 if (TARGET_SOFT_FLOAT)
4594 mips16_hard_float = 0;
4596 mips16_hard_float = 1;
4597 target_flags |= MASK_SOFT_FLOAT;
4599 /* Don't run the scheduler before reload, since it tends to
4600 increase register pressure. */
4601 flag_schedule_insns = 0;
4603 /* Don't do hot/cold partitioning. The constant layout code expects
4604 the whole function to be in a single section. */
4605 flag_reorder_blocks_and_partition = 0;
4607 /* Silently disable -mexplicit-relocs since it doesn't apply
4608 to mips16 code. Even so, it would overly pedantic to warn
4609 about "-mips16 -mexplicit-relocs", especially given that
4610 we use a %gprel() operator. */
4611 target_flags &= ~MASK_EXPLICIT_RELOCS;
4614 /* When using explicit relocs, we call dbr_schedule from within
4616 if (TARGET_EXPLICIT_RELOCS)
4618 mips_flag_delayed_branch = flag_delayed_branch;
4619 flag_delayed_branch = 0;
4622 #ifdef MIPS_TFMODE_FORMAT
4623 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4626 /* Make sure that the user didn't turn off paired single support when
4627 MIPS-3D support is requested. */
4628 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4629 && !TARGET_PAIRED_SINGLE_FLOAT)
4630 error ("-mips3d requires -mpaired-single");
4632 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4634 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4636 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4637 and TARGET_HARD_FLOAT are both true. */
4638 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4639 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4641 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4643 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4644 error ("-mips3d/-mpaired-single must be used with -mips64");
4646 mips_print_operand_punct['?'] = 1;
4647 mips_print_operand_punct['#'] = 1;
4648 mips_print_operand_punct['/'] = 1;
4649 mips_print_operand_punct['&'] = 1;
4650 mips_print_operand_punct['!'] = 1;
4651 mips_print_operand_punct['*'] = 1;
4652 mips_print_operand_punct['@'] = 1;
4653 mips_print_operand_punct['.'] = 1;
4654 mips_print_operand_punct['('] = 1;
4655 mips_print_operand_punct[')'] = 1;
4656 mips_print_operand_punct['['] = 1;
4657 mips_print_operand_punct[']'] = 1;
4658 mips_print_operand_punct['<'] = 1;
4659 mips_print_operand_punct['>'] = 1;
4660 mips_print_operand_punct['{'] = 1;
4661 mips_print_operand_punct['}'] = 1;
4662 mips_print_operand_punct['^'] = 1;
4663 mips_print_operand_punct['$'] = 1;
4664 mips_print_operand_punct['+'] = 1;
4665 mips_print_operand_punct['~'] = 1;
4667 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4668 mips_char_to_class['t'] = T_REG;
4669 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4670 mips_char_to_class['h'] = HI_REG;
4671 mips_char_to_class['l'] = LO_REG;
4672 mips_char_to_class['x'] = MD_REGS;
4673 mips_char_to_class['b'] = ALL_REGS;
4674 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4675 TARGET_MIPS16 ? M16_NA_REGS :
4677 mips_char_to_class['e'] = LEA_REGS;
4678 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4679 mips_char_to_class['v'] = V1_REG;
4680 mips_char_to_class['y'] = GR_REGS;
4681 mips_char_to_class['z'] = ST_REGS;
4682 mips_char_to_class['B'] = COP0_REGS;
4683 mips_char_to_class['C'] = COP2_REGS;
4684 mips_char_to_class['D'] = COP3_REGS;
4686 /* Set up array to map GCC register number to debug register number.
4687 Ignore the special purpose register numbers. */
4689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4690 mips_dbx_regno[i] = -1;
4692 start = GP_DBX_FIRST - GP_REG_FIRST;
4693 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4694 mips_dbx_regno[i] = i + start;
4696 start = FP_DBX_FIRST - FP_REG_FIRST;
4697 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4698 mips_dbx_regno[i] = i + start;
4700 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4701 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4703 /* Set up array giving whether a given register can hold a given mode. */
4705 for (mode = VOIDmode;
4706 mode != MAX_MACHINE_MODE;
4707 mode = (enum machine_mode) ((int)mode + 1))
4709 register int size = GET_MODE_SIZE (mode);
4710 register enum mode_class class = GET_MODE_CLASS (mode);
4712 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4716 if (mode == CCV2mode)
4719 && (regno - ST_REG_FIRST) % 2 == 0);
4721 else if (mode == CCV4mode)
4724 && (regno - ST_REG_FIRST) % 4 == 0);
4726 else if (mode == CCmode)
4729 temp = (regno == FPSW_REGNUM);
4731 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4732 || FP_REG_P (regno));
4735 else if (GP_REG_P (regno))
4736 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4738 else if (FP_REG_P (regno))
4739 temp = ((regno % FP_INC) == 0)
4740 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
4741 || class == MODE_VECTOR_FLOAT)
4742 && size <= UNITS_PER_FPVALUE)
4743 /* Allow integer modes that fit into a single
4744 register. We need to put integers into FPRs
4745 when using instructions like cvt and trunc. */
4746 || (class == MODE_INT && size <= UNITS_PER_FPREG)
4747 /* Allow TFmode for CCmode reloads. */
4748 || (ISA_HAS_8CC && mode == TFmode));
4750 else if (MD_REG_P (regno))
4751 temp = (INTEGRAL_MODE_P (mode)
4752 && (size <= UNITS_PER_WORD
4753 || (regno == MD_REG_FIRST
4754 && size == 2 * UNITS_PER_WORD)));
4756 else if (ALL_COP_REG_P (regno))
4757 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4761 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4765 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4766 initialized yet, so we can't use that here. */
4767 gpr_mode = TARGET_64BIT ? DImode : SImode;
4769 /* Provide default values for align_* for 64-bit targets. */
4770 if (TARGET_64BIT && !TARGET_MIPS16)
4772 if (align_loops == 0)
4774 if (align_jumps == 0)
4776 if (align_functions == 0)
4777 align_functions = 8;
4780 /* Function to allocate machine-dependent function status. */
4781 init_machine_status = &mips_init_machine_status;
4783 if (ABI_HAS_64BIT_SYMBOLS)
4785 if (TARGET_EXPLICIT_RELOCS)
4787 mips_split_p[SYMBOL_64_HIGH] = true;
4788 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4789 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4791 mips_split_p[SYMBOL_64_MID] = true;
4792 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4793 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4795 mips_split_p[SYMBOL_64_LOW] = true;
4796 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4797 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
4799 mips_split_p[SYMBOL_GENERAL] = true;
4800 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4805 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
4807 mips_split_p[SYMBOL_GENERAL] = true;
4808 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
4809 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4815 /* The high part is provided by a pseudo copy of $gp. */
4816 mips_split_p[SYMBOL_SMALL_DATA] = true;
4817 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
4820 if (TARGET_EXPLICIT_RELOCS)
4822 /* Small data constants are kept whole until after reload,
4823 then lowered by mips_rewrite_small_data. */
4824 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
4826 mips_split_p[SYMBOL_GOT_LOCAL] = true;
4829 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
4830 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
4834 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
4835 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
4840 /* The HIGH and LO_SUM are matched by special .md patterns. */
4841 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
4843 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
4844 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
4845 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
4847 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
4848 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
4849 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
4854 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
4856 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
4857 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
4863 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
4864 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
4865 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
4868 /* Thread-local relocation operators. */
4869 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
4870 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
4871 mips_split_p[SYMBOL_DTPREL] = 1;
4872 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
4873 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
4874 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
4875 mips_split_p[SYMBOL_TPREL] = 1;
4876 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
4877 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
4879 /* We don't have a thread pointer access instruction on MIPS16, or
4880 appropriate TLS relocations. */
4882 targetm.have_tls = false;
4884 /* Default to working around R4000 errata only if the processor
4885 was selected explicitly. */
4886 if ((target_flags_explicit & MASK_FIX_R4000) == 0
4887 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
4888 target_flags |= MASK_FIX_R4000;
4890 /* Default to working around R4400 errata only if the processor
4891 was selected explicitly. */
4892 if ((target_flags_explicit & MASK_FIX_R4400) == 0
4893 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
4894 target_flags |= MASK_FIX_R4400;
4897 /* Implement CONDITIONAL_REGISTER_USAGE. */
4900 mips_conditional_register_usage (void)
4902 if (!TARGET_HARD_FLOAT)
4906 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
4907 fixed_regs[regno] = call_used_regs[regno] = 1;
4908 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4909 fixed_regs[regno] = call_used_regs[regno] = 1;
4911 else if (! ISA_HAS_8CC)
4915 /* We only have a single condition code register. We
4916 implement this by hiding all the condition code registers,
4917 and generating RTL that refers directly to ST_REG_FIRST. */
4918 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4919 fixed_regs[regno] = call_used_regs[regno] = 1;
4921 /* In mips16 mode, we permit the $t temporary registers to be used
4922 for reload. We prohibit the unused $s registers, since they
4923 are caller saved, and saving them via a mips16 register would
4924 probably waste more time than just reloading the value. */
4927 fixed_regs[18] = call_used_regs[18] = 1;
4928 fixed_regs[19] = call_used_regs[19] = 1;
4929 fixed_regs[20] = call_used_regs[20] = 1;
4930 fixed_regs[21] = call_used_regs[21] = 1;
4931 fixed_regs[22] = call_used_regs[22] = 1;
4932 fixed_regs[23] = call_used_regs[23] = 1;
4933 fixed_regs[26] = call_used_regs[26] = 1;
4934 fixed_regs[27] = call_used_regs[27] = 1;
4935 fixed_regs[30] = call_used_regs[30] = 1;
4937 /* fp20-23 are now caller saved. */
4938 if (mips_abi == ABI_64)
4941 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
4942 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4944 /* Odd registers from fp21 to fp31 are now caller saved. */
4945 if (mips_abi == ABI_N32)
4948 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
4949 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4953 /* Allocate a chunk of memory for per-function machine-dependent data. */
4954 static struct machine_function *
4955 mips_init_machine_status (void)
4957 return ((struct machine_function *)
4958 ggc_alloc_cleared (sizeof (struct machine_function)));
4961 /* On the mips16, we want to allocate $24 (T_REG) before other
4962 registers for instructions for which it is possible. This helps
4963 avoid shuffling registers around in order to set up for an xor,
4964 encouraging the compiler to use a cmp instead. */
4967 mips_order_regs_for_local_alloc (void)
4971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4972 reg_alloc_order[i] = i;
4976 /* It really doesn't matter where we put register 0, since it is
4977 a fixed register anyhow. */
4978 reg_alloc_order[0] = 24;
4979 reg_alloc_order[24] = 0;
4984 /* The MIPS debug format wants all automatic variables and arguments
4985 to be in terms of the virtual frame pointer (stack pointer before
4986 any adjustment in the function), while the MIPS 3.0 linker wants
4987 the frame pointer to be the stack pointer after the initial
4988 adjustment. So, we do the adjustment here. The arg pointer (which
4989 is eliminated) points to the virtual frame pointer, while the frame
4990 pointer (which may be eliminated) points to the stack pointer after
4991 the initial adjustments. */
4994 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
4996 rtx offset2 = const0_rtx;
4997 rtx reg = eliminate_constant_term (addr, &offset2);
5000 offset = INTVAL (offset2);
5002 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5003 || reg == hard_frame_pointer_rtx)
5005 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5006 ? compute_frame_size (get_frame_size ())
5007 : cfun->machine->frame.total_size;
5009 /* MIPS16 frame is smaller */
5010 if (frame_pointer_needed && TARGET_MIPS16)
5011 frame_size -= cfun->machine->frame.args_size;
5013 offset = offset - frame_size;
5016 /* sdbout_parms does not want this to crash for unrecognized cases. */
5018 else if (reg != arg_pointer_rtx)
5019 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5026 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5028 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5029 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5030 'h' OP is HIGH, prints %hi(X),
5031 'd' output integer constant in decimal,
5032 'z' if the operand is 0, use $0 instead of normal operand.
5033 'D' print second part of double-word register or memory operand.
5034 'L' print low-order register of double-word register operand.
5035 'M' print high-order register of double-word register operand.
5036 'C' print part of opcode for a branch condition.
5037 'F' print part of opcode for a floating-point branch condition.
5038 'N' print part of opcode for a branch condition, inverted.
5039 'W' print part of opcode for a floating-point branch condition, inverted.
5040 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5041 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5042 't' like 'T', but with the EQ/NE cases reversed
5043 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5044 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5045 'R' print the reloc associated with LO_SUM
5047 The punctuation characters are:
5049 '(' Turn on .set noreorder
5050 ')' Turn on .set reorder
5051 '[' Turn on .set noat
5053 '<' Turn on .set nomacro
5054 '>' Turn on .set macro
5055 '{' Turn on .set volatile (not GAS)
5056 '}' Turn on .set novolatile (not GAS)
5057 '&' Turn on .set noreorder if filling delay slots
5058 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5059 '!' Turn on .set nomacro if filling delay slots
5060 '#' Print nop if in a .set noreorder section.
5061 '/' Like '#', but does nothing within a delayed branch sequence
5062 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5063 '@' Print the name of the assembler temporary register (at or $1).
5064 '.' Print the name of the register with a hard-wired zero (zero or $0).
5065 '^' Print the name of the pic call-through register (t9 or $25).
5066 '$' Print the name of the stack pointer register (sp or $29).
5067 '+' Print the name of the gp register (usually gp or $28).
5068 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5071 print_operand (FILE *file, rtx op, int letter)
5073 register enum rtx_code code;
5075 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5080 if (mips_branch_likely)
5085 fputs (reg_names [GP_REG_FIRST + 1], file);
5089 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5093 fputs (reg_names [GP_REG_FIRST + 0], file);
5097 fputs (reg_names[STACK_POINTER_REGNUM], file);
5101 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5105 if (final_sequence != 0 && set_noreorder++ == 0)
5106 fputs (".set\tnoreorder\n\t", file);
5110 if (final_sequence != 0)
5112 if (set_noreorder++ == 0)
5113 fputs (".set\tnoreorder\n\t", file);
5115 if (set_nomacro++ == 0)
5116 fputs (".set\tnomacro\n\t", file);
5121 if (final_sequence != 0 && set_nomacro++ == 0)
5122 fputs ("\n\t.set\tnomacro", file);
5126 if (set_noreorder != 0)
5127 fputs ("\n\tnop", file);
5131 /* Print an extra newline so that the delayed insn is separated
5132 from the following ones. This looks neater and is consistent
5133 with non-nop delayed sequences. */
5134 if (set_noreorder != 0 && final_sequence == 0)
5135 fputs ("\n\tnop\n", file);
5139 if (set_noreorder++ == 0)
5140 fputs (".set\tnoreorder\n\t", file);
5144 if (set_noreorder == 0)
5145 error ("internal error: %%) found without a %%( in assembler pattern");
5147 else if (--set_noreorder == 0)
5148 fputs ("\n\t.set\treorder", file);
5153 if (set_noat++ == 0)
5154 fputs (".set\tnoat\n\t", file);
5159 error ("internal error: %%] found without a %%[ in assembler pattern");
5160 else if (--set_noat == 0)
5161 fputs ("\n\t.set\tat", file);
5166 if (set_nomacro++ == 0)
5167 fputs (".set\tnomacro\n\t", file);
5171 if (set_nomacro == 0)
5172 error ("internal error: %%> found without a %%< in assembler pattern");
5173 else if (--set_nomacro == 0)
5174 fputs ("\n\t.set\tmacro", file);
5179 if (set_volatile++ == 0)
5180 fputs ("#.set\tvolatile\n\t", file);
5184 if (set_volatile == 0)
5185 error ("internal error: %%} found without a %%{ in assembler pattern");
5186 else if (--set_volatile == 0)
5187 fputs ("\n\t#.set\tnovolatile", file);
5193 if (align_labels_log > 0)
5194 ASM_OUTPUT_ALIGN (file, align_labels_log);
5199 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5208 error ("PRINT_OPERAND null pointer");
5212 code = GET_CODE (op);
5217 case EQ: fputs ("eq", file); break;
5218 case NE: fputs ("ne", file); break;
5219 case GT: fputs ("gt", file); break;
5220 case GE: fputs ("ge", file); break;
5221 case LT: fputs ("lt", file); break;
5222 case LE: fputs ("le", file); break;
5223 case GTU: fputs ("gtu", file); break;
5224 case GEU: fputs ("geu", file); break;
5225 case LTU: fputs ("ltu", file); break;
5226 case LEU: fputs ("leu", file); break;
5228 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5231 else if (letter == 'N')
5234 case EQ: fputs ("ne", file); break;
5235 case NE: fputs ("eq", file); break;
5236 case GT: fputs ("le", file); break;
5237 case GE: fputs ("lt", file); break;
5238 case LT: fputs ("ge", file); break;
5239 case LE: fputs ("gt", file); break;
5240 case GTU: fputs ("leu", file); break;
5241 case GEU: fputs ("ltu", file); break;
5242 case LTU: fputs ("geu", file); break;
5243 case LEU: fputs ("gtu", file); break;
5245 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5248 else if (letter == 'F')
5251 case EQ: fputs ("c1f", file); break;
5252 case NE: fputs ("c1t", file); break;
5254 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5257 else if (letter == 'W')
5260 case EQ: fputs ("c1t", file); break;
5261 case NE: fputs ("c1f", file); break;
5263 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5266 else if (letter == 'h')
5268 if (GET_CODE (op) == HIGH)
5271 print_operand_reloc (file, op, mips_hi_relocs);
5274 else if (letter == 'R')
5275 print_operand_reloc (file, op, mips_lo_relocs);
5277 else if (letter == 'Y')
5279 if (GET_CODE (op) == CONST_INT
5280 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5281 < ARRAY_SIZE (mips_fp_conditions)))
5282 fputs (mips_fp_conditions[INTVAL (op)], file);
5284 output_operand_lossage ("invalid %%Y value");
5287 else if (letter == 'Z')
5291 print_operand (file, op, 0);
5296 else if (code == REG || code == SUBREG)
5298 register int regnum;
5301 regnum = REGNO (op);
5303 regnum = true_regnum (op);
5305 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5306 || (letter == 'L' && WORDS_BIG_ENDIAN)
5310 fprintf (file, "%s", reg_names[regnum]);
5313 else if (code == MEM)
5316 output_address (plus_constant (XEXP (op, 0), 4));
5318 output_address (XEXP (op, 0));
5321 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5322 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5324 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5325 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5327 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5328 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5330 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5331 fputs (reg_names[GP_REG_FIRST], file);
5333 else if (letter == 'd' || letter == 'x' || letter == 'X')
5334 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5336 else if (letter == 'T' || letter == 't')
5338 int truth = (code == NE) == (letter == 'T');
5339 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5342 else if (CONST_GP_P (op))
5343 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5346 output_addr_const (file, op);
5350 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5351 RELOCS is the array of relocations to use. */
5354 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5356 enum mips_symbol_type symbol_type;
5359 HOST_WIDE_INT offset;
5361 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5362 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5364 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5365 mips_split_const (op, &base, &offset);
5366 if (UNSPEC_ADDRESS_P (base))
5367 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5369 fputs (relocs[symbol_type], file);
5370 output_addr_const (file, op);
5371 for (p = relocs[symbol_type]; *p != 0; p++)
5376 /* Output address operand X to FILE. */
5379 print_operand_address (FILE *file, rtx x)
5381 struct mips_address_info addr;
5383 if (mips_classify_address (&addr, x, word_mode, true))
5387 print_operand (file, addr.offset, 0);
5388 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5391 case ADDRESS_LO_SUM:
5392 print_operand (file, addr.offset, 'R');
5393 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5396 case ADDRESS_CONST_INT:
5397 output_addr_const (file, x);
5398 fprintf (file, "(%s)", reg_names[0]);
5401 case ADDRESS_SYMBOLIC:
5402 output_addr_const (file, x);
5408 /* When using assembler macros, keep track of all of small-data externs
5409 so that mips_file_end can emit the appropriate declarations for them.
5411 In most cases it would be safe (though pointless) to emit .externs
5412 for other symbols too. One exception is when an object is within
5413 the -G limit but declared by the user to be in a section other
5414 than .sbss or .sdata. */
5417 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5419 register struct extern_list *p;
5421 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5423 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5424 p->next = extern_head;
5426 p->size = int_size_in_bytes (TREE_TYPE (decl));
5430 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5432 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5433 p->next = extern_head;
5444 irix_output_external_libcall (rtx fun)
5446 register struct extern_list *p;
5448 if (mips_abi == ABI_32)
5450 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5451 p->next = extern_head;
5452 p->name = XSTR (fun, 0);
5459 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5460 put out a MIPS ECOFF file and a stab. */
5463 mips_output_filename (FILE *stream, const char *name)
5466 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5468 if (write_symbols == DWARF2_DEBUG)
5470 else if (mips_output_filename_first_time)
5472 mips_output_filename_first_time = 0;
5473 num_source_filenames += 1;
5474 current_function_file = name;
5475 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5476 output_quoted_string (stream, name);
5477 putc ('\n', stream);
5480 /* If we are emitting stabs, let dbxout.c handle this (except for
5481 the mips_output_filename_first_time case). */
5482 else if (write_symbols == DBX_DEBUG)
5485 else if (name != current_function_file
5486 && strcmp (name, current_function_file) != 0)
5488 num_source_filenames += 1;
5489 current_function_file = name;
5490 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5491 output_quoted_string (stream, name);
5492 putc ('\n', stream);
5496 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5497 that should be written before the opening quote, such as "\t.ascii\t"
5498 for real string data or "\t# " for a comment. */
5501 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5506 register const unsigned char *string =
5507 (const unsigned char *)string_param;
5509 fprintf (stream, "%s\"", prefix);
5510 for (i = 0; i < len; i++)
5512 register int c = string[i];
5516 if (c == '\\' || c == '\"')
5518 putc ('\\', stream);
5526 fprintf (stream, "\\%03o", c);
5530 if (cur_pos > 72 && i+1 < len)
5533 fprintf (stream, "\"\n%s\"", prefix);
5536 fprintf (stream, "\"\n");
5539 /* Implement TARGET_ASM_FILE_START. */
5542 mips_file_start (void)
5544 default_file_start ();
5548 /* Generate a special section to describe the ABI switches used to
5549 produce the resultant binary. This used to be done by the assembler
5550 setting bits in the ELF header's flags field, but we have run out of
5551 bits. GDB needs this information in order to be able to correctly
5552 debug these binaries. See the function mips_gdbarch_init() in
5553 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5554 causes unnecessary IRIX 6 ld warnings. */
5555 const char * abi_string = NULL;
5559 case ABI_32: abi_string = "abi32"; break;
5560 case ABI_N32: abi_string = "abiN32"; break;
5561 case ABI_64: abi_string = "abi64"; break;
5562 case ABI_O64: abi_string = "abiO64"; break;
5563 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5567 /* Note - we use fprintf directly rather than called named_section()
5568 because in this way we can avoid creating an allocated section. We
5569 do not want this section to take up any space in the running
5571 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5573 /* There is no ELF header flag to distinguish long32 forms of the
5574 EABI from long64 forms. Emit a special section to help tools
5576 if (mips_abi == ABI_EABI)
5577 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5578 TARGET_LONG64 ? 64 : 32);
5580 /* Restore the default section. */
5581 fprintf (asm_out_file, "\t.previous\n");
5584 /* Generate the pseudo ops that System V.4 wants. */
5585 if (TARGET_ABICALLS)
5586 /* ??? but do not want this (or want pic0) if -non-shared? */
5587 fprintf (asm_out_file, "\t.abicalls\n");
5590 fprintf (asm_out_file, "\t.set\tmips16\n");
5592 if (flag_verbose_asm)
5593 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5595 mips_section_threshold, mips_arch_info->name, mips_isa);
5598 #ifdef BSS_SECTION_ASM_OP
5599 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5600 in the use of sbss. */
5603 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5604 unsigned HOST_WIDE_INT size, int align)
5606 extern tree last_assemble_variable_decl;
5608 if (mips_in_small_data_p (decl))
5609 named_section (0, ".sbss", 0);
5612 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5613 last_assemble_variable_decl = decl;
5614 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5615 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5619 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5620 .externs for any small-data variables that turned out to be external. */
5623 mips_file_end (void)
5626 struct extern_list *p;
5630 fputs ("\n", asm_out_file);
5632 for (p = extern_head; p != 0; p = p->next)
5634 name_tree = get_identifier (p->name);
5636 /* Positively ensure only one .extern for any given symbol. */
5637 if (!TREE_ASM_WRITTEN (name_tree)
5638 && TREE_SYMBOL_REFERENCED (name_tree))
5640 TREE_ASM_WRITTEN (name_tree) = 1;
5641 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5642 `.global name .text' directive for every used but
5643 undefined function. If we don't, the linker may perform
5644 an optimization (skipping over the insns that set $gp)
5645 when it is unsafe. */
5646 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5648 fputs ("\t.globl ", asm_out_file);
5649 assemble_name (asm_out_file, p->name);
5650 fputs (" .text\n", asm_out_file);
5654 fputs ("\t.extern\t", asm_out_file);
5655 assemble_name (asm_out_file, p->name);
5656 fprintf (asm_out_file, ", %d\n", p->size);
5663 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5664 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5667 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5668 unsigned HOST_WIDE_INT size,
5671 /* If the target wants uninitialized const declarations in
5672 .rdata then don't put them in .comm. */
5673 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5674 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5675 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5677 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5678 targetm.asm_out.globalize_label (stream, name);
5680 readonly_data_section ();
5681 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5682 mips_declare_object (stream, name, "",
5683 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5687 mips_declare_common_object (stream, name, "\n\t.comm\t",
5691 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5692 NAME is the name of the object and ALIGN is the required alignment
5693 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5694 alignment argument. */
5697 mips_declare_common_object (FILE *stream, const char *name,
5698 const char *init_string,
5699 unsigned HOST_WIDE_INT size,
5700 unsigned int align, bool takes_alignment_p)
5702 if (!takes_alignment_p)
5704 size += (align / BITS_PER_UNIT) - 1;
5705 size -= size % (align / BITS_PER_UNIT);
5706 mips_declare_object (stream, name, init_string,
5707 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5710 mips_declare_object (stream, name, init_string,
5711 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5712 size, align / BITS_PER_UNIT);
5715 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5716 macros, mark the symbol as written so that mips_file_end won't emit an
5717 .extern for it. STREAM is the output file, NAME is the name of the
5718 symbol, INIT_STRING is the string that should be written before the
5719 symbol and FINAL_STRING is the string that should be written after it.
5720 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5723 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5724 const char *final_string, ...)
5728 fputs (init_string, stream);
5729 assemble_name (stream, name);
5730 va_start (ap, final_string);
5731 vfprintf (stream, final_string, ap);
5734 if (!TARGET_EXPLICIT_RELOCS)
5736 tree name_tree = get_identifier (name);
5737 TREE_ASM_WRITTEN (name_tree) = 1;
5741 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5742 extern int size_directive_output;
5744 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5745 definitions except that it uses mips_declare_object() to emit the label. */
5748 mips_declare_object_name (FILE *stream, const char *name,
5749 tree decl ATTRIBUTE_UNUSED)
5751 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5752 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5755 size_directive_output = 0;
5756 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5760 size_directive_output = 1;
5761 size = int_size_in_bytes (TREE_TYPE (decl));
5762 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5765 mips_declare_object (stream, name, "", ":\n");
5768 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5771 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5775 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5776 if (!flag_inhibit_size_directive
5777 && DECL_SIZE (decl) != 0
5778 && !at_end && top_level
5779 && DECL_INITIAL (decl) == error_mark_node
5780 && !size_directive_output)
5784 size_directive_output = 1;
5785 size = int_size_in_bytes (TREE_TYPE (decl));
5786 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5791 /* Return true if X is a small data address that can be rewritten
5795 mips_rewrite_small_data_p (rtx x)
5797 enum mips_symbol_type symbol_type;
5799 return (TARGET_EXPLICIT_RELOCS
5800 && mips_symbolic_constant_p (x, &symbol_type)
5801 && symbol_type == SYMBOL_SMALL_DATA);
5805 /* A for_each_rtx callback for mips_small_data_pattern_p. */
5808 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5810 if (GET_CODE (*loc) == LO_SUM)
5813 return mips_rewrite_small_data_p (*loc);
5816 /* Return true if OP refers to small data symbols directly, not through
5820 mips_small_data_pattern_p (rtx op)
5822 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
5825 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
5828 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5830 if (mips_rewrite_small_data_p (*loc))
5831 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
5833 if (GET_CODE (*loc) == LO_SUM)
5839 /* If possible, rewrite OP so that it refers to small data using
5840 explicit relocations. */
5843 mips_rewrite_small_data (rtx op)
5845 op = copy_insn (op);
5846 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
5850 /* Return true if the current function has an insn that implicitly
5854 mips_function_has_gp_insn (void)
5856 /* Don't bother rechecking if we found one last time. */
5857 if (!cfun->machine->has_gp_insn_p)
5861 push_topmost_sequence ();
5862 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5864 && GET_CODE (PATTERN (insn)) != USE
5865 && GET_CODE (PATTERN (insn)) != CLOBBER
5866 && (get_attr_got (insn) != GOT_UNSET
5867 || small_data_pattern (PATTERN (insn), VOIDmode)))
5869 pop_topmost_sequence ();
5871 cfun->machine->has_gp_insn_p = (insn != 0);
5873 return cfun->machine->has_gp_insn_p;
5877 /* Return the register that should be used as the global pointer
5878 within this function. Return 0 if the function doesn't need
5879 a global pointer. */
5882 mips_global_pointer (void)
5886 /* $gp is always available in non-abicalls code. */
5887 if (!TARGET_ABICALLS)
5888 return GLOBAL_POINTER_REGNUM;
5890 /* We must always provide $gp when it is used implicitly. */
5891 if (!TARGET_EXPLICIT_RELOCS)
5892 return GLOBAL_POINTER_REGNUM;
5894 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
5896 if (current_function_profile)
5897 return GLOBAL_POINTER_REGNUM;
5899 /* If the function has a nonlocal goto, $gp must hold the correct
5900 global pointer for the target function. */
5901 if (current_function_has_nonlocal_goto)
5902 return GLOBAL_POINTER_REGNUM;
5904 /* If the gp is never referenced, there's no need to initialize it.
5905 Note that reload can sometimes introduce constant pool references
5906 into a function that otherwise didn't need them. For example,
5907 suppose we have an instruction like:
5909 (set (reg:DF R1) (float:DF (reg:SI R2)))
5911 If R2 turns out to be constant such as 1, the instruction may have a
5912 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
5913 using this constant if R2 doesn't get allocated to a register.
5915 In cases like these, reload will have added the constant to the pool
5916 but no instruction will yet refer to it. */
5917 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
5918 && !current_function_uses_const_pool
5919 && !mips_function_has_gp_insn ())
5922 /* We need a global pointer, but perhaps we can use a call-clobbered
5923 register instead of $gp. */
5924 if (TARGET_NEWABI && current_function_is_leaf)
5925 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5926 if (!regs_ever_live[regno]
5927 && call_used_regs[regno]
5928 && !fixed_regs[regno]
5929 && regno != PIC_FUNCTION_ADDR_REGNUM)
5932 return GLOBAL_POINTER_REGNUM;
5936 /* Return true if the current function must save REGNO. */
5939 mips_save_reg_p (unsigned int regno)
5941 /* We only need to save $gp for NewABI PIC. */
5942 if (regno == GLOBAL_POINTER_REGNUM)
5943 return (TARGET_ABICALLS && TARGET_NEWABI
5944 && cfun->machine->global_pointer == regno);
5946 /* Check call-saved registers. */
5947 if (regs_ever_live[regno] && !call_used_regs[regno])
5950 /* We need to save the old frame pointer before setting up a new one. */
5951 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
5954 /* We need to save the incoming return address if it is ever clobbered
5955 within the function. */
5956 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
5963 return_type = DECL_RESULT (current_function_decl);
5965 /* $18 is a special case in mips16 code. It may be used to call
5966 a function which returns a floating point value, but it is
5967 marked in call_used_regs. */
5968 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
5971 /* $31 is also a special case. It will be used to copy a return
5972 value into the floating point registers if the return value is
5974 if (regno == GP_REG_FIRST + 31
5975 && mips16_hard_float
5976 && !aggregate_value_p (return_type, current_function_decl)
5977 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
5978 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
5986 /* Return the bytes needed to compute the frame pointer from the current
5987 stack pointer. SIZE is the size (in bytes) of the local variables.
5989 Mips stack frames look like:
5991 Before call After call
5992 +-----------------------+ +-----------------------+
5995 | caller's temps. | | caller's temps. |
5997 +-----------------------+ +-----------------------+
5999 | arguments on stack. | | arguments on stack. |
6001 +-----------------------+ +-----------------------+
6002 | 4 words to save | | 4 words to save |
6003 | arguments passed | | arguments passed |
6004 | in registers, even | | in registers, even |
6005 SP->| if not passed. | VFP->| if not passed. |
6006 +-----------------------+ +-----------------------+
6008 | fp register save |
6010 +-----------------------+
6012 | gp register save |
6014 +-----------------------+
6018 +-----------------------+
6020 | alloca allocations |
6022 +-----------------------+
6024 | GP save for V.4 abi |
6026 +-----------------------+
6028 | arguments on stack |
6030 +-----------------------+
6032 | arguments passed |
6033 | in registers, even |
6034 low SP->| if not passed. |
6035 memory +-----------------------+
6040 compute_frame_size (HOST_WIDE_INT size)
6043 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6044 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6045 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6046 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6047 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6048 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6049 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6050 unsigned int mask; /* mask of saved gp registers */
6051 unsigned int fmask; /* mask of saved fp registers */
6053 cfun->machine->global_pointer = mips_global_pointer ();
6059 var_size = MIPS_STACK_ALIGN (size);
6060 args_size = current_function_outgoing_args_size;
6061 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6063 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6064 functions. If the function has local variables, we're committed
6065 to allocating it anyway. Otherwise reclaim it here. */
6066 if (var_size == 0 && current_function_is_leaf)
6067 cprestore_size = args_size = 0;
6069 /* The MIPS 3.0 linker does not like functions that dynamically
6070 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6071 looks like we are trying to create a second frame pointer to the
6072 function, so allocate some stack space to make it happy. */
6074 if (args_size == 0 && current_function_calls_alloca)
6075 args_size = 4 * UNITS_PER_WORD;
6077 total_size = var_size + args_size + cprestore_size;
6079 /* Calculate space needed for gp registers. */
6080 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6081 if (mips_save_reg_p (regno))
6083 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6084 mask |= 1 << (regno - GP_REG_FIRST);
6087 /* We need to restore these for the handler. */
6088 if (current_function_calls_eh_return)
6093 regno = EH_RETURN_DATA_REGNO (i);
6094 if (regno == INVALID_REGNUM)
6096 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6097 mask |= 1 << (regno - GP_REG_FIRST);
6101 /* This loop must iterate over the same space as its companion in
6102 save_restore_insns. */
6103 for (regno = (FP_REG_LAST - FP_INC + 1);
6104 regno >= FP_REG_FIRST;
6107 if (mips_save_reg_p (regno))
6109 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6110 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6114 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6115 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6117 /* Add in the space required for saving incoming register arguments. */
6118 total_size += current_function_pretend_args_size;
6119 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6121 /* Save other computed information. */
6122 cfun->machine->frame.total_size = total_size;
6123 cfun->machine->frame.var_size = var_size;
6124 cfun->machine->frame.args_size = args_size;
6125 cfun->machine->frame.cprestore_size = cprestore_size;
6126 cfun->machine->frame.gp_reg_size = gp_reg_size;
6127 cfun->machine->frame.fp_reg_size = fp_reg_size;
6128 cfun->machine->frame.mask = mask;
6129 cfun->machine->frame.fmask = fmask;
6130 cfun->machine->frame.initialized = reload_completed;
6131 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6132 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6136 HOST_WIDE_INT offset;
6138 offset = (args_size + cprestore_size + var_size
6139 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6140 cfun->machine->frame.gp_sp_offset = offset;
6141 cfun->machine->frame.gp_save_offset = offset - total_size;
6145 cfun->machine->frame.gp_sp_offset = 0;
6146 cfun->machine->frame.gp_save_offset = 0;
6151 HOST_WIDE_INT offset;
6153 offset = (args_size + cprestore_size + var_size
6154 + gp_reg_rounded + fp_reg_size
6155 - FP_INC * UNITS_PER_FPREG);
6156 cfun->machine->frame.fp_sp_offset = offset;
6157 cfun->machine->frame.fp_save_offset = offset - total_size;
6161 cfun->machine->frame.fp_sp_offset = 0;
6162 cfun->machine->frame.fp_save_offset = 0;
6165 /* Ok, we're done. */
6169 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6170 pointer or argument pointer. TO is either the stack pointer or
6171 hard frame pointer. */
6174 mips_initial_elimination_offset (int from, int to)
6176 HOST_WIDE_INT offset;
6178 compute_frame_size (get_frame_size ());
6180 /* Set OFFSET to the offset from the stack pointer. */
6183 case FRAME_POINTER_REGNUM:
6187 case ARG_POINTER_REGNUM:
6188 offset = (cfun->machine->frame.total_size
6189 - current_function_pretend_args_size);
6196 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6197 offset -= cfun->machine->frame.args_size;
6202 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6203 back to a previous frame. */
6205 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6210 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6213 /* Use FN to save or restore register REGNO. MODE is the register's
6214 mode and OFFSET is the offset of its save slot from the current
6218 mips_save_restore_reg (enum machine_mode mode, int regno,
6219 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6223 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6225 fn (gen_rtx_REG (mode, regno), mem);
6229 /* Call FN for each register that is saved by the current function.
6230 SP_OFFSET is the offset of the current stack pointer from the start
6234 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6236 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6238 enum machine_mode fpr_mode;
6239 HOST_WIDE_INT offset;
6242 /* Save registers starting from high to low. The debuggers prefer at least
6243 the return register be stored at func+4, and also it allows us not to
6244 need a nop in the epilog if at least one register is reloaded in
6245 addition to return address. */
6246 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6247 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6248 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6250 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6251 offset -= GET_MODE_SIZE (gpr_mode);
6254 /* This loop must iterate over the same space as its companion in
6255 compute_frame_size. */
6256 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6257 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6258 for (regno = (FP_REG_LAST - FP_INC + 1);
6259 regno >= FP_REG_FIRST;
6261 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6263 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6264 offset -= GET_MODE_SIZE (fpr_mode);
6269 /* If we're generating n32 or n64 abicalls, and the current function
6270 does not use $28 as its global pointer, emit a cplocal directive.
6271 Use pic_offset_table_rtx as the argument to the directive. */
6274 mips_output_cplocal (void)
6276 if (!TARGET_EXPLICIT_RELOCS
6277 && cfun->machine->global_pointer > 0
6278 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6279 output_asm_insn (".cplocal %+", 0);
6282 /* If we're generating n32 or n64 abicalls, emit instructions
6283 to set up the global pointer. */
6286 mips_emit_loadgp (void)
6288 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6290 rtx addr, offset, incoming_address;
6292 addr = XEXP (DECL_RTL (current_function_decl), 0);
6293 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6294 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6295 emit_insn (gen_loadgp (offset, incoming_address));
6296 if (!TARGET_EXPLICIT_RELOCS)
6297 emit_insn (gen_loadgp_blockage ());
6301 /* Set up the stack and frame (if desired) for the function. */
6304 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6307 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6309 #ifdef SDB_DEBUGGING_INFO
6310 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6311 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6314 /* In mips16 mode, we may need to generate a 32 bit to handle
6315 floating point arguments. The linker will arrange for any 32 bit
6316 functions to call this stub, which will then jump to the 16 bit
6318 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6319 && current_function_args_info.fp_code != 0)
6320 build_mips16_function_stub (file);
6322 if (!FUNCTION_NAME_ALREADY_DECLARED)
6324 /* Get the function name the same way that toplev.c does before calling
6325 assemble_start_function. This is needed so that the name used here
6326 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6327 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6329 if (!flag_inhibit_size_directive)
6331 fputs ("\t.ent\t", file);
6332 assemble_name (file, fnname);
6336 assemble_name (file, fnname);
6337 fputs (":\n", file);
6340 /* Stop mips_file_end from treating this function as external. */
6341 if (TARGET_IRIX && mips_abi == ABI_32)
6342 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6344 if (!flag_inhibit_size_directive)
6346 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6348 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6349 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6350 ", args= " HOST_WIDE_INT_PRINT_DEC
6351 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6352 (reg_names[(frame_pointer_needed)
6353 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6354 ((frame_pointer_needed && TARGET_MIPS16)
6355 ? tsize - cfun->machine->frame.args_size
6357 reg_names[GP_REG_FIRST + 31],
6358 cfun->machine->frame.var_size,
6359 cfun->machine->frame.num_gp,
6360 cfun->machine->frame.num_fp,
6361 cfun->machine->frame.args_size,
6362 cfun->machine->frame.cprestore_size);
6364 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6365 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6366 cfun->machine->frame.mask,
6367 cfun->machine->frame.gp_save_offset);
6368 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6369 cfun->machine->frame.fmask,
6370 cfun->machine->frame.fp_save_offset);
6373 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6374 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6377 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6379 /* Handle the initialization of $gp for SVR4 PIC. */
6380 if (!cfun->machine->all_noreorder_p)
6381 output_asm_insn ("%(.cpload\t%^%)", 0);
6383 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6385 else if (cfun->machine->all_noreorder_p)
6386 output_asm_insn ("%(%<", 0);
6388 /* Tell the assembler which register we're using as the global
6389 pointer. This is needed for thunks, since they can use either
6390 explicit relocs or assembler macros. */
6391 mips_output_cplocal ();
6394 /* Make the last instruction frame related and note that it performs
6395 the operation described by FRAME_PATTERN. */
6398 mips_set_frame_expr (rtx frame_pattern)
6402 insn = get_last_insn ();
6403 RTX_FRAME_RELATED_P (insn) = 1;
6404 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6410 /* Return a frame-related rtx that stores REG at MEM.
6411 REG must be a single register. */
6414 mips_frame_set (rtx mem, rtx reg)
6418 /* If we're saving the return address register and the dwarf return
6419 address column differs from the hard register number, adjust the
6420 note reg to refer to the former. */
6421 if (REGNO (reg) == GP_REG_FIRST + 31
6422 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6423 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6425 set = gen_rtx_SET (VOIDmode, mem, reg);
6426 RTX_FRAME_RELATED_P (set) = 1;
6432 /* Save register REG to MEM. Make the instruction frame-related. */
6435 mips_save_reg (rtx reg, rtx mem)
6437 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6441 if (mips_split_64bit_move_p (mem, reg))
6442 mips_split_64bit_move (mem, reg);
6444 emit_move_insn (mem, reg);
6446 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6447 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6448 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6453 && REGNO (reg) != GP_REG_FIRST + 31
6454 && !M16_REG_P (REGNO (reg)))
6456 /* Save a non-mips16 register by moving it through a temporary.
6457 We don't need to do this for $31 since there's a special
6458 instruction for it. */
6459 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6460 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6463 emit_move_insn (mem, reg);
6465 mips_set_frame_expr (mips_frame_set (mem, reg));
6470 /* Expand the prologue into a bunch of separate insns. */
6473 mips_expand_prologue (void)
6477 if (cfun->machine->global_pointer > 0)
6478 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6480 size = compute_frame_size (get_frame_size ());
6482 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6483 bytes beforehand; this is enough to cover the register save area
6484 without going out of range. */
6485 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6487 HOST_WIDE_INT step1;
6489 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6490 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6492 GEN_INT (-step1)))) = 1;
6494 mips_for_each_saved_reg (size, mips_save_reg);
6497 /* Allocate the rest of the frame. */
6500 if (SMALL_OPERAND (-size))
6501 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6503 GEN_INT (-size)))) = 1;
6506 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6509 /* There are no instructions to add or subtract registers
6510 from the stack pointer, so use the frame pointer as a
6511 temporary. We should always be using a frame pointer
6512 in this case anyway. */
6513 gcc_assert (frame_pointer_needed);
6514 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6515 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6516 hard_frame_pointer_rtx,
6517 MIPS_PROLOGUE_TEMP (Pmode)));
6518 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6521 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6523 MIPS_PROLOGUE_TEMP (Pmode)));
6525 /* Describe the combined effect of the previous instructions. */
6527 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6528 plus_constant (stack_pointer_rtx, -size)));
6532 /* Set up the frame pointer, if we're using one. In mips16 code,
6533 we point the frame pointer ahead of the outgoing argument area.
6534 This should allow more variables & incoming arguments to be
6535 accessed with unextended instructions. */
6536 if (frame_pointer_needed)
6538 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6540 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6542 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6547 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6548 stack_pointer_rtx)) = 1;
6551 /* If generating o32/o64 abicalls, save $gp on the stack. */
6552 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6553 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6555 mips_emit_loadgp ();
6557 /* If we are profiling, make sure no instructions are scheduled before
6558 the call to mcount. */
6560 if (current_function_profile)
6561 emit_insn (gen_blockage ());
6564 /* Do any necessary cleanup after a function to restore stack, frame,
6567 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6570 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6571 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6573 /* Reinstate the normal $gp. */
6574 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6575 mips_output_cplocal ();
6577 if (cfun->machine->all_noreorder_p)
6579 /* Avoid using %>%) since it adds excess whitespace. */
6580 output_asm_insn (".set\tmacro", 0);
6581 output_asm_insn (".set\treorder", 0);
6582 set_noreorder = set_nomacro = 0;
6585 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6589 /* Get the function name the same way that toplev.c does before calling
6590 assemble_start_function. This is needed so that the name used here
6591 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6592 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6593 fputs ("\t.end\t", file);
6594 assemble_name (file, fnname);
6599 /* Emit instructions to restore register REG from slot MEM. */
6602 mips_restore_reg (rtx reg, rtx mem)
6604 /* There's no mips16 instruction to load $31 directly. Load into
6605 $7 instead and adjust the return insn appropriately. */
6606 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6607 reg = gen_rtx_REG (GET_MODE (reg), 7);
6609 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6611 /* Can't restore directly; move through a temporary. */
6612 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6613 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6616 emit_move_insn (reg, mem);
6620 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6621 if this epilogue precedes a sibling call, false if it is for a normal
6622 "epilogue" pattern. */
6625 mips_expand_epilogue (int sibcall_p)
6627 HOST_WIDE_INT step1, step2;
6630 if (!sibcall_p && mips_can_use_return_insn ())
6632 emit_jump_insn (gen_return ());
6636 /* Split the frame into two. STEP1 is the amount of stack we should
6637 deallocate before restoring the registers. STEP2 is the amount we
6638 should deallocate afterwards.
6640 Start off by assuming that no registers need to be restored. */
6641 step1 = cfun->machine->frame.total_size;
6644 /* Work out which register holds the frame address. Account for the
6645 frame pointer offset used by mips16 code. */
6646 if (!frame_pointer_needed)
6647 base = stack_pointer_rtx;
6650 base = hard_frame_pointer_rtx;
6652 step1 -= cfun->machine->frame.args_size;
6655 /* If we need to restore registers, deallocate as much stack as
6656 possible in the second step without going out of range. */
6657 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6659 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6663 /* Set TARGET to BASE + STEP1. */
6669 /* Get an rtx for STEP1 that we can add to BASE. */
6670 adjust = GEN_INT (step1);
6671 if (!SMALL_OPERAND (step1))
6673 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6674 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6677 /* Normal mode code can copy the result straight into $sp. */
6679 target = stack_pointer_rtx;
6681 emit_insn (gen_add3_insn (target, base, adjust));
6684 /* Copy TARGET into the stack pointer. */
6685 if (target != stack_pointer_rtx)
6686 emit_move_insn (stack_pointer_rtx, target);
6688 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6689 implicitly used by all SYMBOL_REFs. We must emit a blockage
6690 insn before restoring it. */
6691 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6692 emit_insn (gen_blockage ());
6694 /* Restore the registers. */
6695 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6698 /* Deallocate the final bit of the frame. */
6700 emit_insn (gen_add3_insn (stack_pointer_rtx,
6704 /* Add in the __builtin_eh_return stack adjustment. We need to
6705 use a temporary in mips16 code. */
6706 if (current_function_calls_eh_return)
6710 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6711 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6712 MIPS_EPILOGUE_TEMP (Pmode),
6713 EH_RETURN_STACKADJ_RTX));
6714 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6717 emit_insn (gen_add3_insn (stack_pointer_rtx,
6719 EH_RETURN_STACKADJ_RTX));
6724 /* The mips16 loads the return address into $7, not $31. */
6725 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6726 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6727 GP_REG_FIRST + 7)));
6729 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6730 GP_REG_FIRST + 31)));
6734 /* Return nonzero if this function is known to have a null epilogue.
6735 This allows the optimizer to omit jumps to jumps if no stack
6739 mips_can_use_return_insn (void)
6743 if (! reload_completed)
6746 if (regs_ever_live[31] || current_function_profile)
6749 return_type = DECL_RESULT (current_function_decl);
6751 /* In mips16 mode, a function which returns a floating point value
6752 needs to arrange to copy the return value into the floating point
6755 && mips16_hard_float
6756 && ! aggregate_value_p (return_type, current_function_decl)
6757 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6758 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6761 if (cfun->machine->frame.initialized)
6762 return cfun->machine->frame.total_size == 0;
6764 return compute_frame_size (get_frame_size ()) == 0;
6767 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6768 in order to avoid duplicating too much logic from elsewhere. */
6771 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6772 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6775 rtx this, temp1, temp2, insn, fnaddr;
6777 /* Pretend to be a post-reload pass while generating rtl. */
6779 reload_completed = 1;
6780 reset_block_changes ();
6782 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6783 for TARGET_NEWABI since the latter is a call-saved register. */
6784 if (TARGET_ABICALLS)
6785 cfun->machine->global_pointer
6786 = REGNO (pic_offset_table_rtx)
6787 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
6789 /* Set up the global pointer for n32 or n64 abicalls. */
6790 mips_emit_loadgp ();
6792 /* We need two temporary registers in some cases. */
6793 temp1 = gen_rtx_REG (Pmode, 2);
6794 temp2 = gen_rtx_REG (Pmode, 3);
6796 /* Find out which register contains the "this" pointer. */
6797 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
6798 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
6800 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
6802 /* Add DELTA to THIS. */
6805 rtx offset = GEN_INT (delta);
6806 if (!SMALL_OPERAND (delta))
6808 emit_move_insn (temp1, offset);
6811 emit_insn (gen_add3_insn (this, this, offset));
6814 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
6815 if (vcall_offset != 0)
6819 /* Set TEMP1 to *THIS. */
6820 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
6822 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
6823 addr = mips_add_offset (temp2, temp1, vcall_offset);
6825 /* Load the offset and add it to THIS. */
6826 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
6827 emit_insn (gen_add3_insn (this, this, temp1));
6830 /* Jump to the target function. Use a sibcall if direct jumps are
6831 allowed, otherwise load the address into a register first. */
6832 fnaddr = XEXP (DECL_RTL (function), 0);
6833 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
6835 /* This is messy. gas treats "la $25,foo" as part of a call
6836 sequence and may allow a global "foo" to be lazily bound.
6837 The general move patterns therefore reject this combination.
6839 In this context, lazy binding would actually be OK for o32 and o64,
6840 but it's still wrong for n32 and n64; see mips_load_call_address.
6841 We must therefore load the address via a temporary register if
6842 mips_dangerous_for_la25_p.
6844 If we jump to the temporary register rather than $25, the assembler
6845 can use the move insn to fill the jump's delay slot. */
6846 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
6847 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6848 mips_load_call_address (temp1, fnaddr, true);
6850 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
6851 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
6852 emit_jump_insn (gen_indirect_jump (temp1));
6856 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
6857 SIBLING_CALL_P (insn) = 1;
6860 /* Run just enough of rest_of_compilation. This sequence was
6861 "borrowed" from alpha.c. */
6862 insn = get_insns ();
6863 insn_locators_initialize ();
6864 split_all_insns_noflow ();
6866 mips16_lay_out_constants ();
6867 shorten_branches (insn);
6868 final_start_function (insn, file, 1);
6869 final (insn, file, 1);
6870 final_end_function ();
6872 /* Clean up the vars set above. Note that final_end_function resets
6873 the global pointer for us. */
6874 reload_completed = 0;
6878 /* Returns nonzero if X contains a SYMBOL_REF. */
6881 symbolic_expression_p (rtx x)
6883 if (GET_CODE (x) == SYMBOL_REF)
6886 if (GET_CODE (x) == CONST)
6887 return symbolic_expression_p (XEXP (x, 0));
6890 return symbolic_expression_p (XEXP (x, 0));
6892 if (ARITHMETIC_P (x))
6893 return (symbolic_expression_p (XEXP (x, 0))
6894 || symbolic_expression_p (XEXP (x, 1)));
6899 /* Choose the section to use for the constant rtx expression X that has
6903 mips_select_rtx_section (enum machine_mode mode, rtx x,
6904 unsigned HOST_WIDE_INT align)
6908 /* In mips16 mode, the constant table always goes in the same section
6909 as the function, so that constants can be loaded using PC relative
6911 function_section (current_function_decl);
6913 else if (TARGET_EMBEDDED_DATA)
6915 /* For embedded applications, always put constants in read-only data,
6916 in order to reduce RAM usage. */
6917 mergeable_constant_section (mode, align, 0);
6921 /* For hosted applications, always put constants in small data if
6922 possible, as this gives the best performance. */
6923 /* ??? Consider using mergeable small data sections. */
6925 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
6926 && mips_section_threshold > 0)
6927 named_section (0, ".sdata", 0);
6928 else if (flag_pic && symbolic_expression_p (x))
6929 named_section (0, ".data.rel.ro", 3);
6931 mergeable_constant_section (mode, align, 0);
6935 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6937 The complication here is that, with the combination TARGET_ABICALLS
6938 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6939 therefore not be included in the read-only part of a DSO. Handle such
6940 cases by selecting a normal data section instead of a read-only one.
6941 The logic apes that in default_function_rodata_section. */
6944 mips_function_rodata_section (tree decl)
6946 if (!TARGET_ABICALLS || TARGET_GPWORD)
6947 default_function_rodata_section (decl);
6948 else if (decl && DECL_SECTION_NAME (decl))
6950 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6951 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6953 char *rname = ASTRDUP (name);
6955 named_section_real (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6957 else if (flag_function_sections && flag_data_sections
6958 && strncmp (name, ".text.", 6) == 0)
6960 char *rname = ASTRDUP (name);
6961 memcpy (rname + 1, "data", 4);
6962 named_section_flags (rname, SECTION_WRITE);
6971 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
6972 access DECL using %gp_rel(...)($gp). */
6975 mips_in_small_data_p (tree decl)
6979 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6982 /* We don't yet generate small-data references for -mabicalls. See related
6983 -G handling in override_options. */
6984 if (TARGET_ABICALLS)
6987 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6991 /* Reject anything that isn't in a known small-data section. */
6992 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6993 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6996 /* If a symbol is defined externally, the assembler will use the
6997 usual -G rules when deciding how to implement macros. */
6998 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7001 else if (TARGET_EMBEDDED_DATA)
7003 /* Don't put constants into the small data section: we want them
7004 to be in ROM rather than RAM. */
7005 if (TREE_CODE (decl) != VAR_DECL)
7008 if (TREE_READONLY (decl)
7009 && !TREE_SIDE_EFFECTS (decl)
7010 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7014 size = int_size_in_bytes (TREE_TYPE (decl));
7015 return (size > 0 && size <= mips_section_threshold);
7018 /* See whether VALTYPE is a record whose fields should be returned in
7019 floating-point registers. If so, return the number of fields and
7020 list them in FIELDS (which should have two elements). Return 0
7023 For n32 & n64, a structure with one or two fields is returned in
7024 floating-point registers as long as every field has a floating-point
7028 mips_fpr_return_fields (tree valtype, tree *fields)
7036 if (TREE_CODE (valtype) != RECORD_TYPE)
7040 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7042 if (TREE_CODE (field) != FIELD_DECL)
7045 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7051 fields[i++] = field;
7057 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7058 a value in the most significant part of $2/$3 if:
7060 - the target is big-endian;
7062 - the value has a structure or union type (we generalize this to
7063 cover aggregates from other languages too); and
7065 - the structure is not returned in floating-point registers. */
7068 mips_return_in_msb (tree valtype)
7072 return (TARGET_NEWABI
7073 && TARGET_BIG_ENDIAN
7074 && AGGREGATE_TYPE_P (valtype)
7075 && mips_fpr_return_fields (valtype, fields) == 0);
7079 /* Return a composite value in a pair of floating-point registers.
7080 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7081 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7084 For n32 & n64, $f0 always holds the first value and $f2 the second.
7085 Otherwise the values are packed together as closely as possible. */
7088 mips_return_fpr_pair (enum machine_mode mode,
7089 enum machine_mode mode1, HOST_WIDE_INT offset1,
7090 enum machine_mode mode2, HOST_WIDE_INT offset2)
7094 inc = (TARGET_NEWABI ? 2 : FP_INC);
7095 return gen_rtx_PARALLEL
7098 gen_rtx_EXPR_LIST (VOIDmode,
7099 gen_rtx_REG (mode1, FP_RETURN),
7101 gen_rtx_EXPR_LIST (VOIDmode,
7102 gen_rtx_REG (mode2, FP_RETURN + inc),
7103 GEN_INT (offset2))));
7108 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7109 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7110 VALTYPE is null and MODE is the mode of the return value. */
7113 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7114 enum machine_mode mode)
7121 mode = TYPE_MODE (valtype);
7122 unsignedp = TYPE_UNSIGNED (valtype);
7124 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7125 true, we must promote the mode just as PROMOTE_MODE does. */
7126 mode = promote_mode (valtype, mode, &unsignedp, 1);
7128 /* Handle structures whose fields are returned in $f0/$f2. */
7129 switch (mips_fpr_return_fields (valtype, fields))
7132 return gen_rtx_REG (mode, FP_RETURN);
7135 return mips_return_fpr_pair (mode,
7136 TYPE_MODE (TREE_TYPE (fields[0])),
7137 int_byte_position (fields[0]),
7138 TYPE_MODE (TREE_TYPE (fields[1])),
7139 int_byte_position (fields[1]));
7142 /* If a value is passed in the most significant part of a register, see
7143 whether we have to round the mode up to a whole number of words. */
7144 if (mips_return_in_msb (valtype))
7146 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7147 if (size % UNITS_PER_WORD != 0)
7149 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7150 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7154 /* For EABI, the class of return register depends entirely on MODE.
7155 For example, "struct { some_type x; }" and "union { some_type x; }"
7156 are returned in the same way as a bare "some_type" would be.
7157 Other ABIs only use FPRs for scalar, complex or vector types. */
7158 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7159 return gen_rtx_REG (mode, GP_RETURN);
7162 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7163 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7164 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7165 return gen_rtx_REG (mode, FP_RETURN);
7167 /* Handle long doubles for n32 & n64. */
7169 return mips_return_fpr_pair (mode,
7171 DImode, GET_MODE_SIZE (mode) / 2);
7173 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7174 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7175 return mips_return_fpr_pair (mode,
7176 GET_MODE_INNER (mode), 0,
7177 GET_MODE_INNER (mode),
7178 GET_MODE_SIZE (mode) / 2);
7180 return gen_rtx_REG (mode, GP_RETURN);
7183 /* Return nonzero when an argument must be passed by reference. */
7186 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7187 enum machine_mode mode, tree type,
7188 bool named ATTRIBUTE_UNUSED)
7190 if (mips_abi == ABI_EABI)
7194 /* ??? How should SCmode be handled? */
7195 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7198 size = int_size_in_bytes (type);
7199 return size == -1 || size > UNITS_PER_WORD;
7203 /* If we have a variable-sized parameter, we have no choice. */
7204 return targetm.calls.must_pass_in_stack (mode, type);
7209 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7210 enum machine_mode mode ATTRIBUTE_UNUSED,
7211 tree type ATTRIBUTE_UNUSED, bool named)
7213 return mips_abi == ABI_EABI && named;
7216 /* Return true if registers of class CLASS cannot change from mode FROM
7220 mips_cannot_change_mode_class (enum machine_mode from,
7221 enum machine_mode to, enum reg_class class)
7223 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7224 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7226 if (TARGET_BIG_ENDIAN)
7228 /* When a multi-word value is stored in paired floating-point
7229 registers, the first register always holds the low word.
7230 We therefore can't allow FPRs to change between single-word
7231 and multi-word modes. */
7232 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7237 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7238 in LO and HI, the high word always comes first. We therefore
7239 can't allow values stored in HI to change between single-word
7240 and multi-word modes. */
7241 if (reg_classes_intersect_p (HI_REG, class))
7245 /* Loading a 32-bit value into a 64-bit floating-point register
7246 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7247 We can't allow 64-bit float registers to change from SImode to
7251 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7252 && reg_classes_intersect_p (FP_REGS, class))
7257 /* Return true if X should not be moved directly into register $25.
7258 We need this because many versions of GAS will treat "la $25,foo" as
7259 part of a call sequence and so allow a global "foo" to be lazily bound. */
7262 mips_dangerous_for_la25_p (rtx x)
7264 HOST_WIDE_INT offset;
7266 if (TARGET_EXPLICIT_RELOCS)
7269 mips_split_const (x, &x, &offset);
7270 return global_got_operand (x, VOIDmode);
7273 /* Implement PREFERRED_RELOAD_CLASS. */
7276 mips_preferred_reload_class (rtx x, enum reg_class class)
7278 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7281 if (TARGET_HARD_FLOAT
7282 && FLOAT_MODE_P (GET_MODE (x))
7283 && reg_class_subset_p (FP_REGS, class))
7286 if (reg_class_subset_p (GR_REGS, class))
7289 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7295 /* This function returns the register class required for a secondary
7296 register when copying between one of the registers in CLASS, and X,
7297 using MODE. If IN_P is nonzero, the copy is going from X to the
7298 register, otherwise the register is the source. A return value of
7299 NO_REGS means that no secondary register is required. */
7302 mips_secondary_reload_class (enum reg_class class,
7303 enum machine_mode mode, rtx x, int in_p)
7305 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7309 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7310 regno = true_regnum (x);
7312 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7314 if (mips_dangerous_for_la25_p (x))
7317 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7321 /* Copying from HI or LO to anywhere other than a general register
7322 requires a general register. */
7323 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7325 if (TARGET_MIPS16 && in_p)
7327 /* We can't really copy to HI or LO at all in mips16 mode. */
7330 return gp_reg_p ? NO_REGS : gr_regs;
7332 if (MD_REG_P (regno))
7334 if (TARGET_MIPS16 && ! in_p)
7336 /* We can't really copy to HI or LO at all in mips16 mode. */
7339 return class == gr_regs ? NO_REGS : gr_regs;
7342 /* We can only copy a value to a condition code register from a
7343 floating point register, and even then we require a scratch
7344 floating point register. We can only copy a value out of a
7345 condition code register into a general register. */
7346 if (class == ST_REGS)
7350 return gp_reg_p ? NO_REGS : gr_regs;
7352 if (ST_REG_P (regno))
7356 return class == gr_regs ? NO_REGS : gr_regs;
7359 if (class == FP_REGS)
7363 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7366 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7368 /* We can use the l.s and l.d macros to load floating-point
7369 constants. ??? For l.s, we could probably get better
7370 code by returning GR_REGS here. */
7373 else if (gp_reg_p || x == CONST0_RTX (mode))
7375 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7378 else if (FP_REG_P (regno))
7380 /* In this case we can use mov.s or mov.d. */
7385 /* Otherwise, we need to reload through an integer register. */
7390 /* In mips16 mode, going between memory and anything but M16_REGS
7391 requires an M16_REG. */
7394 if (class != M16_REGS && class != M16_NA_REGS)
7402 if (class == M16_REGS || class == M16_NA_REGS)
7411 /* Implement CLASS_MAX_NREGS.
7413 Usually all registers are word-sized. The only supported exception
7414 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7415 registers. A word-based calculation is correct even in that case,
7416 since -msingle-float disallows multi-FPR values.
7418 The FP status registers are an exception to this rule. They are always
7419 4 bytes wide as they only hold condition code modes, and CCmode is always
7420 considered to be 4 bytes wide. */
7423 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7424 enum machine_mode mode)
7426 if (class == ST_REGS)
7427 return (GET_MODE_SIZE (mode) + 3) / 4;
7429 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7433 mips_valid_pointer_mode (enum machine_mode mode)
7435 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7438 /* Target hook for vector_mode_supported_p. */
7441 mips_vector_mode_supported_p (enum machine_mode mode)
7443 if (mode == V2SFmode && TARGET_PAIRED_SINGLE_FLOAT)
7449 /* If we can access small data directly (using gp-relative relocation
7450 operators) return the small data pointer, otherwise return null.
7452 For each mips16 function which refers to GP relative symbols, we
7453 use a pseudo register, initialized at the start of the function, to
7454 hold the $gp value. */
7457 mips16_gp_pseudo_reg (void)
7459 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7464 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7466 /* We want to initialize this to a value which gcc will believe
7469 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7470 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7471 gen_rtx_CONST (Pmode, unspec));
7472 insn = get_insns ();
7475 push_topmost_sequence ();
7476 /* We need to emit the initialization after the FUNCTION_BEG
7477 note, so that it will be integrated. */
7478 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7480 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7482 if (scan == NULL_RTX)
7483 scan = get_insns ();
7484 insn = emit_insn_after (insn, scan);
7485 pop_topmost_sequence ();
7488 return cfun->machine->mips16_gp_pseudo_rtx;
7491 /* Write out code to move floating point arguments in or out of
7492 general registers. Output the instructions to FILE. FP_CODE is
7493 the code describing which arguments are present (see the comment at
7494 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7495 we are copying from the floating point registers. */
7498 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7504 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7505 gcc_assert (TARGET_OLDABI);
7511 gparg = GP_ARG_FIRST;
7512 fparg = FP_ARG_FIRST;
7513 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7517 if ((fparg & 1) != 0)
7519 fprintf (file, "\t%s\t%s,%s\n", s,
7520 reg_names[gparg], reg_names[fparg]);
7522 else if ((f & 3) == 2)
7525 fprintf (file, "\td%s\t%s,%s\n", s,
7526 reg_names[gparg], reg_names[fparg]);
7529 if ((fparg & 1) != 0)
7531 if (TARGET_BIG_ENDIAN)
7532 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7533 reg_names[gparg], reg_names[fparg + 1], s,
7534 reg_names[gparg + 1], reg_names[fparg]);
7536 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7537 reg_names[gparg], reg_names[fparg], s,
7538 reg_names[gparg + 1], reg_names[fparg + 1]);
7551 /* Build a mips16 function stub. This is used for functions which
7552 take arguments in the floating point registers. It is 32 bit code
7553 that moves the floating point args into the general registers, and
7554 then jumps to the 16 bit code. */
7557 build_mips16_function_stub (FILE *file)
7560 char *secname, *stubname;
7561 tree stubid, stubdecl;
7565 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7566 secname = (char *) alloca (strlen (fnname) + 20);
7567 sprintf (secname, ".mips16.fn.%s", fnname);
7568 stubname = (char *) alloca (strlen (fnname) + 20);
7569 sprintf (stubname, "__fn_stub_%s", fnname);
7570 stubid = get_identifier (stubname);
7571 stubdecl = build_decl (FUNCTION_DECL, stubid,
7572 build_function_type (void_type_node, NULL_TREE));
7573 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7575 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7577 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7579 fprintf (file, "%s%s",
7580 need_comma ? ", " : "",
7581 (f & 3) == 1 ? "float" : "double");
7584 fprintf (file, ")\n");
7586 fprintf (file, "\t.set\tnomips16\n");
7587 function_section (stubdecl);
7588 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7590 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7591 within a .ent, and we cannot emit another .ent. */
7592 if (!FUNCTION_NAME_ALREADY_DECLARED)
7594 fputs ("\t.ent\t", file);
7595 assemble_name (file, stubname);
7599 assemble_name (file, stubname);
7600 fputs (":\n", file);
7602 /* We don't want the assembler to insert any nops here. */
7603 fprintf (file, "\t.set\tnoreorder\n");
7605 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7607 fprintf (asm_out_file, "\t.set\tnoat\n");
7608 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7609 assemble_name (file, fnname);
7610 fprintf (file, "\n");
7611 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7612 fprintf (asm_out_file, "\t.set\tat\n");
7614 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7615 with one of the mfc1 instructions, because the result is not
7616 available for one instruction, so if the very first instruction
7617 in the function refers to the register, it will see the wrong
7619 fprintf (file, "\tnop\n");
7621 fprintf (file, "\t.set\treorder\n");
7623 if (!FUNCTION_NAME_ALREADY_DECLARED)
7625 fputs ("\t.end\t", file);
7626 assemble_name (file, stubname);
7630 fprintf (file, "\t.set\tmips16\n");
7632 function_section (current_function_decl);
7635 /* We keep a list of functions for which we have already built stubs
7636 in build_mips16_call_stub. */
7640 struct mips16_stub *next;
7645 static struct mips16_stub *mips16_stubs;
7647 /* Build a call stub for a mips16 call. A stub is needed if we are
7648 passing any floating point values which should go into the floating
7649 point registers. If we are, and the call turns out to be to a 32
7650 bit function, the stub will be used to move the values into the
7651 floating point registers before calling the 32 bit function. The
7652 linker will magically adjust the function call to either the 16 bit
7653 function or the 32 bit stub, depending upon where the function call
7654 is actually defined.
7656 Similarly, we need a stub if the return value might come back in a
7657 floating point register.
7659 RETVAL is the location of the return value, or null if this is
7660 a call rather than a call_value. FN is the address of the
7661 function and ARG_SIZE is the size of the arguments. FP_CODE
7662 is the code built by function_arg. This function returns a nonzero
7663 value if it builds the call instruction itself. */
7666 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7670 char *secname, *stubname;
7671 struct mips16_stub *l;
7672 tree stubid, stubdecl;
7676 /* We don't need to do anything if we aren't in mips16 mode, or if
7677 we were invoked with the -msoft-float option. */
7678 if (! TARGET_MIPS16 || ! mips16_hard_float)
7681 /* Figure out whether the value might come back in a floating point
7683 fpret = (retval != 0
7684 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7685 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7687 /* We don't need to do anything if there were no floating point
7688 arguments and the value will not be returned in a floating point
7690 if (fp_code == 0 && ! fpret)
7693 /* We don't need to do anything if this is a call to a special
7694 mips16 support function. */
7695 if (GET_CODE (fn) == SYMBOL_REF
7696 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7699 /* This code will only work for o32 and o64 abis. The other ABI's
7700 require more sophisticated support. */
7701 gcc_assert (TARGET_OLDABI);
7703 /* We can only handle SFmode and DFmode floating point return
7706 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
7708 /* If we're calling via a function pointer, then we must always call
7709 via a stub. There are magic stubs provided in libgcc.a for each
7710 of the required cases. Each of them expects the function address
7711 to arrive in register $2. */
7713 if (GET_CODE (fn) != SYMBOL_REF)
7719 /* ??? If this code is modified to support other ABI's, we need
7720 to handle PARALLEL return values here. */
7722 sprintf (buf, "__mips16_call_stub_%s%d",
7724 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7727 id = get_identifier (buf);
7728 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7730 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7732 if (retval == NULL_RTX)
7733 insn = gen_call_internal (stub_fn, arg_size);
7735 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7736 insn = emit_call_insn (insn);
7738 /* Put the register usage information on the CALL. */
7739 CALL_INSN_FUNCTION_USAGE (insn) =
7740 gen_rtx_EXPR_LIST (VOIDmode,
7741 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
7742 CALL_INSN_FUNCTION_USAGE (insn));
7744 /* If we are handling a floating point return value, we need to
7745 save $18 in the function prologue. Putting a note on the
7746 call will mean that regs_ever_live[$18] will be true if the
7747 call is not eliminated, and we can check that in the prologue
7750 CALL_INSN_FUNCTION_USAGE (insn) =
7751 gen_rtx_EXPR_LIST (VOIDmode,
7752 gen_rtx_USE (VOIDmode,
7753 gen_rtx_REG (word_mode, 18)),
7754 CALL_INSN_FUNCTION_USAGE (insn));
7756 /* Return 1 to tell the caller that we've generated the call
7761 /* We know the function we are going to call. If we have already
7762 built a stub, we don't need to do anything further. */
7764 fnname = XSTR (fn, 0);
7765 for (l = mips16_stubs; l != NULL; l = l->next)
7766 if (strcmp (l->name, fnname) == 0)
7771 /* Build a special purpose stub. When the linker sees a
7772 function call in mips16 code, it will check where the target
7773 is defined. If the target is a 32 bit call, the linker will
7774 search for the section defined here. It can tell which
7775 symbol this section is associated with by looking at the
7776 relocation information (the name is unreliable, since this
7777 might be a static function). If such a section is found, the
7778 linker will redirect the call to the start of the magic
7781 If the function does not return a floating point value, the
7782 special stub section is named
7785 If the function does return a floating point value, the stub
7787 .mips16.call.fp.FNNAME
7790 secname = (char *) alloca (strlen (fnname) + 40);
7791 sprintf (secname, ".mips16.call.%s%s",
7794 stubname = (char *) alloca (strlen (fnname) + 20);
7795 sprintf (stubname, "__call_stub_%s%s",
7798 stubid = get_identifier (stubname);
7799 stubdecl = build_decl (FUNCTION_DECL, stubid,
7800 build_function_type (void_type_node, NULL_TREE));
7801 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7803 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7805 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7809 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7811 fprintf (asm_out_file, "%s%s",
7812 need_comma ? ", " : "",
7813 (f & 3) == 1 ? "float" : "double");
7816 fprintf (asm_out_file, ")\n");
7818 fprintf (asm_out_file, "\t.set\tnomips16\n");
7819 assemble_start_function (stubdecl, stubname);
7821 if (!FUNCTION_NAME_ALREADY_DECLARED)
7823 fputs ("\t.ent\t", asm_out_file);
7824 assemble_name (asm_out_file, stubname);
7825 fputs ("\n", asm_out_file);
7827 assemble_name (asm_out_file, stubname);
7828 fputs (":\n", asm_out_file);
7831 /* We build the stub code by hand. That's the only way we can
7832 do it, since we can't generate 32 bit code during a 16 bit
7835 /* We don't want the assembler to insert any nops here. */
7836 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7838 mips16_fp_args (asm_out_file, fp_code, 0);
7842 fprintf (asm_out_file, "\t.set\tnoat\n");
7843 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7845 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7846 fprintf (asm_out_file, "\t.set\tat\n");
7847 /* Unfortunately, we can't fill the jump delay slot. We
7848 can't fill with one of the mtc1 instructions, because the
7849 result is not available for one instruction, so if the
7850 very first instruction in the function refers to the
7851 register, it will see the wrong value. */
7852 fprintf (asm_out_file, "\tnop\n");
7856 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7857 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7858 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7859 /* As above, we can't fill the delay slot. */
7860 fprintf (asm_out_file, "\tnop\n");
7861 if (GET_MODE (retval) == SFmode)
7862 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7863 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7866 if (TARGET_BIG_ENDIAN)
7868 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7869 reg_names[GP_REG_FIRST + 2],
7870 reg_names[FP_REG_FIRST + 1]);
7871 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7872 reg_names[GP_REG_FIRST + 3],
7873 reg_names[FP_REG_FIRST + 0]);
7877 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7878 reg_names[GP_REG_FIRST + 2],
7879 reg_names[FP_REG_FIRST + 0]);
7880 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7881 reg_names[GP_REG_FIRST + 3],
7882 reg_names[FP_REG_FIRST + 1]);
7885 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7886 /* As above, we can't fill the delay slot. */
7887 fprintf (asm_out_file, "\tnop\n");
7890 fprintf (asm_out_file, "\t.set\treorder\n");
7892 #ifdef ASM_DECLARE_FUNCTION_SIZE
7893 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7896 if (!FUNCTION_NAME_ALREADY_DECLARED)
7898 fputs ("\t.end\t", asm_out_file);
7899 assemble_name (asm_out_file, stubname);
7900 fputs ("\n", asm_out_file);
7903 fprintf (asm_out_file, "\t.set\tmips16\n");
7905 /* Record this stub. */
7906 l = (struct mips16_stub *) xmalloc (sizeof *l);
7907 l->name = xstrdup (fnname);
7909 l->next = mips16_stubs;
7913 /* If we expect a floating point return value, but we've built a
7914 stub which does not expect one, then we're in trouble. We can't
7915 use the existing stub, because it won't handle the floating point
7916 value. We can't build a new stub, because the linker won't know
7917 which stub to use for the various calls in this object file.
7918 Fortunately, this case is illegal, since it means that a function
7919 was declared in two different ways in a single compilation. */
7920 if (fpret && ! l->fpret)
7921 error ("cannot handle inconsistent calls to %qs", fnname);
7923 /* If we are calling a stub which handles a floating point return
7924 value, we need to arrange to save $18 in the prologue. We do
7925 this by marking the function call as using the register. The
7926 prologue will later see that it is used, and emit code to save
7933 if (retval == NULL_RTX)
7934 insn = gen_call_internal (fn, arg_size);
7936 insn = gen_call_value_internal (retval, fn, arg_size);
7937 insn = emit_call_insn (insn);
7939 CALL_INSN_FUNCTION_USAGE (insn) =
7940 gen_rtx_EXPR_LIST (VOIDmode,
7941 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
7942 CALL_INSN_FUNCTION_USAGE (insn));
7944 /* Return 1 to tell the caller that we've generated the call
7949 /* Return 0 to let the caller generate the call insn. */
7953 /* An entry in the mips16 constant pool. VALUE is the pool constant,
7954 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
7956 struct mips16_constant {
7957 struct mips16_constant *next;
7960 enum machine_mode mode;
7963 /* Information about an incomplete mips16 constant pool. FIRST is the
7964 first constant, HIGHEST_ADDRESS is the highest address that the first
7965 byte of the pool can have, and INSN_ADDRESS is the current instruction
7968 struct mips16_constant_pool {
7969 struct mips16_constant *first;
7970 int highest_address;
7974 /* Add constant VALUE to POOL and return its label. MODE is the
7975 value's mode (used for CONST_INTs, etc.). */
7978 add_constant (struct mips16_constant_pool *pool,
7979 rtx value, enum machine_mode mode)
7981 struct mips16_constant **p, *c;
7982 bool first_of_size_p;
7984 /* See whether the constant is already in the pool. If so, return the
7985 existing label, otherwise leave P pointing to the place where the
7986 constant should be added.
7988 Keep the pool sorted in increasing order of mode size so that we can
7989 reduce the number of alignments needed. */
7990 first_of_size_p = true;
7991 for (p = &pool->first; *p != 0; p = &(*p)->next)
7993 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
7995 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
7997 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
7998 first_of_size_p = false;
8001 /* In the worst case, the constant needed by the earliest instruction
8002 will end up at the end of the pool. The entire pool must then be
8003 accessible from that instruction.
8005 When adding the first constant, set the pool's highest address to
8006 the address of the first out-of-range byte. Adjust this address
8007 downwards each time a new constant is added. */
8008 if (pool->first == 0)
8009 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8010 is the address of the instruction with the lowest two bits clear.
8011 The base PC value for ld has the lowest three bits clear. Assume
8012 the worst case here. */
8013 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8014 pool->highest_address -= GET_MODE_SIZE (mode);
8015 if (first_of_size_p)
8016 /* Take into account the worst possible padding due to alignment. */
8017 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8019 /* Create a new entry. */
8020 c = (struct mips16_constant *) xmalloc (sizeof *c);
8023 c->label = gen_label_rtx ();
8030 /* Output constant VALUE after instruction INSN and return the last
8031 instruction emitted. MODE is the mode of the constant. */
8034 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8036 switch (GET_MODE_CLASS (mode))
8040 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8041 return emit_insn_after (gen_consttable_int (value, size), insn);
8045 return emit_insn_after (gen_consttable_float (value), insn);
8047 case MODE_VECTOR_FLOAT:
8048 case MODE_VECTOR_INT:
8051 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8052 insn = dump_constants_1 (GET_MODE_INNER (mode),
8053 CONST_VECTOR_ELT (value, i), insn);
8063 /* Dump out the constants in CONSTANTS after INSN. */
8066 dump_constants (struct mips16_constant *constants, rtx insn)
8068 struct mips16_constant *c, *next;
8072 for (c = constants; c != NULL; c = next)
8074 /* If necessary, increase the alignment of PC. */
8075 if (align < GET_MODE_SIZE (c->mode))
8077 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8078 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8080 align = GET_MODE_SIZE (c->mode);
8082 insn = emit_label_after (c->label, insn);
8083 insn = dump_constants_1 (c->mode, c->value, insn);
8089 emit_barrier_after (insn);
8092 /* Return the length of instruction INSN. */
8095 mips16_insn_length (rtx insn)
8099 rtx body = PATTERN (insn);
8100 if (GET_CODE (body) == ADDR_VEC)
8101 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8102 if (GET_CODE (body) == ADDR_DIFF_VEC)
8103 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8105 return get_attr_length (insn);
8108 /* Rewrite *X so that constant pool references refer to the constant's
8109 label instead. DATA points to the constant pool structure. */
8112 mips16_rewrite_pool_refs (rtx *x, void *data)
8114 struct mips16_constant_pool *pool = data;
8115 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8116 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8117 get_pool_constant (*x),
8118 get_pool_mode (*x)));
8122 /* Build MIPS16 constant pools. */
8125 mips16_lay_out_constants (void)
8127 struct mips16_constant_pool pool;
8131 memset (&pool, 0, sizeof (pool));
8132 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8134 /* Rewrite constant pool references in INSN. */
8136 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8138 pool.insn_address += mips16_insn_length (insn);
8140 if (pool.first != NULL)
8142 /* If there are no natural barriers between the first user of
8143 the pool and the highest acceptable address, we'll need to
8144 create a new instruction to jump around the constant pool.
8145 In the worst case, this instruction will be 4 bytes long.
8147 If it's too late to do this transformation after INSN,
8148 do it immediately before INSN. */
8149 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8153 label = gen_label_rtx ();
8155 jump = emit_jump_insn_before (gen_jump (label), insn);
8156 JUMP_LABEL (jump) = label;
8157 LABEL_NUSES (label) = 1;
8158 barrier = emit_barrier_after (jump);
8160 emit_label_after (label, barrier);
8161 pool.insn_address += 4;
8164 /* See whether the constant pool is now out of range of the first
8165 user. If so, output the constants after the previous barrier.
8166 Note that any instructions between BARRIER and INSN (inclusive)
8167 will use negative offsets to refer to the pool. */
8168 if (pool.insn_address > pool.highest_address)
8170 dump_constants (pool.first, barrier);
8174 else if (BARRIER_P (insn))
8178 dump_constants (pool.first, get_last_insn ());
8181 /* A temporary variable used by for_each_rtx callbacks, etc. */
8182 static rtx mips_sim_insn;
8184 /* A structure representing the state of the processor pipeline.
8185 Used by the mips_sim_* family of functions. */
8187 /* The maximum number of instructions that can be issued in a cycle.
8188 (Caches mips_issue_rate.) */
8189 unsigned int issue_rate;
8191 /* The current simulation time. */
8194 /* How many more instructions can be issued in the current cycle. */
8195 unsigned int insns_left;
8197 /* LAST_SET[X].INSN is the last instruction to set register X.
8198 LAST_SET[X].TIME is the time at which that instruction was issued.
8199 INSN is null if no instruction has yet set register X. */
8203 } last_set[FIRST_PSEUDO_REGISTER];
8205 /* The pipeline's current DFA state. */
8209 /* Reset STATE to the initial simulation state. */
8212 mips_sim_reset (struct mips_sim *state)
8215 state->insns_left = state->issue_rate;
8216 memset (&state->last_set, 0, sizeof (state->last_set));
8217 state_reset (state->dfa_state);
8220 /* Initialize STATE before its first use. DFA_STATE points to an
8221 allocated but uninitialized DFA state. */
8224 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8226 state->issue_rate = mips_issue_rate ();
8227 state->dfa_state = dfa_state;
8228 mips_sim_reset (state);
8231 /* Advance STATE by one clock cycle. */
8234 mips_sim_next_cycle (struct mips_sim *state)
8237 state->insns_left = state->issue_rate;
8238 state_transition (state->dfa_state, 0);
8241 /* Advance simulation state STATE until instruction INSN can read
8245 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8249 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8250 if (state->last_set[REGNO (reg) + i].insn != 0)
8254 t = state->last_set[REGNO (reg) + i].time;
8255 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8256 while (state->time < t)
8257 mips_sim_next_cycle (state);
8261 /* A for_each_rtx callback. If *X is a register, advance simulation state
8262 DATA until mips_sim_insn can read the register's value. */
8265 mips_sim_wait_regs_2 (rtx *x, void *data)
8268 mips_sim_wait_reg (data, mips_sim_insn, *x);
8272 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8275 mips_sim_wait_regs_1 (rtx *x, void *data)
8277 for_each_rtx (x, mips_sim_wait_regs_2, data);
8280 /* Advance simulation state STATE until all of INSN's register
8281 dependencies are satisfied. */
8284 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8286 mips_sim_insn = insn;
8287 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8290 /* Advance simulation state STATE until the units required by
8291 instruction INSN are available. */
8294 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8298 tmp_state = alloca (state_size ());
8299 while (state->insns_left == 0
8300 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8301 state_transition (tmp_state, insn) >= 0))
8302 mips_sim_next_cycle (state);
8305 /* Advance simulation state STATE until INSN is ready to issue. */
8308 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8310 mips_sim_wait_regs (state, insn);
8311 mips_sim_wait_units (state, insn);
8314 /* mips_sim_insn has just set X. Update the LAST_SET array
8315 in simulation state DATA. */
8318 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8320 struct mips_sim *state;
8325 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8327 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8328 state->last_set[REGNO (x) + i].time = state->time;
8332 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8333 can issue immediately (i.e., that mips_sim_wait_insn has already
8337 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8339 state_transition (state->dfa_state, insn);
8340 state->insns_left--;
8342 mips_sim_insn = insn;
8343 note_stores (PATTERN (insn), mips_sim_record_set, state);
8346 /* Simulate issuing a NOP in state STATE. */
8349 mips_sim_issue_nop (struct mips_sim *state)
8351 if (state->insns_left == 0)
8352 mips_sim_next_cycle (state);
8353 state->insns_left--;
8356 /* Update simulation state STATE so that it's ready to accept the instruction
8357 after INSN. INSN should be part of the main rtl chain, not a member of a
8361 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8363 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8365 mips_sim_issue_nop (state);
8367 switch (GET_CODE (SEQ_BEGIN (insn)))
8371 /* We can't predict the processor state after a call or label. */
8372 mips_sim_reset (state);
8376 /* The delay slots of branch likely instructions are only executed
8377 when the branch is taken. Therefore, if the caller has simulated
8378 the delay slot instruction, STATE does not really reflect the state
8379 of the pipeline for the instruction after the delay slot. Also,
8380 branch likely instructions tend to incur a penalty when not taken,
8381 so there will probably be an extra delay between the branch and
8382 the instruction after the delay slot. */
8383 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8384 mips_sim_reset (state);
8392 /* The VR4130 pipeline issues aligned pairs of instructions together,
8393 but it stalls the second instruction if it depends on the first.
8394 In order to cut down the amount of logic required, this dependence
8395 check is not based on a full instruction decode. Instead, any non-SPECIAL
8396 instruction is assumed to modify the register specified by bits 20-16
8397 (which is usually the "rt" field).
8399 In beq, beql, bne and bnel instructions, the rt field is actually an
8400 input, so we can end up with a false dependence between the branch
8401 and its delay slot. If this situation occurs in instruction INSN,
8402 try to avoid it by swapping rs and rt. */
8405 vr4130_avoid_branch_rt_conflict (rtx insn)
8409 first = SEQ_BEGIN (insn);
8410 second = SEQ_END (insn);
8412 && NONJUMP_INSN_P (second)
8413 && GET_CODE (PATTERN (first)) == SET
8414 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8415 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8417 /* Check for the right kind of condition. */
8418 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8419 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8420 && REG_P (XEXP (cond, 0))
8421 && REG_P (XEXP (cond, 1))
8422 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8423 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8425 /* SECOND mentions the rt register but not the rs register. */
8426 rtx tmp = XEXP (cond, 0);
8427 XEXP (cond, 0) = XEXP (cond, 1);
8428 XEXP (cond, 1) = tmp;
8433 /* Implement -mvr4130-align. Go through each basic block and simulate the
8434 processor pipeline. If we find that a pair of instructions could execute
8435 in parallel, and the first of those instruction is not 8-byte aligned,
8436 insert a nop to make it aligned. */
8439 vr4130_align_insns (void)
8441 struct mips_sim state;
8442 rtx insn, subinsn, last, last2, next;
8447 /* LAST is the last instruction before INSN to have a nonzero length.
8448 LAST2 is the last such instruction before LAST. */
8452 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8455 mips_sim_init (&state, alloca (state_size ()));
8456 for (insn = get_insns (); insn != 0; insn = next)
8458 unsigned int length;
8460 next = NEXT_INSN (insn);
8462 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8463 This isn't really related to the alignment pass, but we do it on
8464 the fly to avoid a separate instruction walk. */
8465 vr4130_avoid_branch_rt_conflict (insn);
8467 if (USEFUL_INSN_P (insn))
8468 FOR_EACH_SUBINSN (subinsn, insn)
8470 mips_sim_wait_insn (&state, subinsn);
8472 /* If we want this instruction to issue in parallel with the
8473 previous one, make sure that the previous instruction is
8474 aligned. There are several reasons why this isn't worthwhile
8475 when the second instruction is a call:
8477 - Calls are less likely to be performance critical,
8478 - There's a good chance that the delay slot can execute
8479 in parallel with the call.
8480 - The return address would then be unaligned.
8482 In general, if we're going to insert a nop between instructions
8483 X and Y, it's better to insert it immediately after X. That
8484 way, if the nop makes Y aligned, it will also align any labels
8486 if (state.insns_left != state.issue_rate
8487 && !CALL_P (subinsn))
8489 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8491 /* SUBINSN is the first instruction in INSN and INSN is
8492 aligned. We want to align the previous instruction
8493 instead, so insert a nop between LAST2 and LAST.
8495 Note that LAST could be either a single instruction
8496 or a branch with a delay slot. In the latter case,
8497 LAST, like INSN, is already aligned, but the delay
8498 slot must have some extra delay that stops it from
8499 issuing at the same time as the branch. We therefore
8500 insert a nop before the branch in order to align its
8502 emit_insn_after (gen_nop (), last2);
8505 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8507 /* SUBINSN is the delay slot of INSN, but INSN is
8508 currently unaligned. Insert a nop between
8509 LAST and INSN to align it. */
8510 emit_insn_after (gen_nop (), last);
8514 mips_sim_issue_insn (&state, subinsn);
8516 mips_sim_finish_insn (&state, insn);
8518 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8519 length = get_attr_length (insn);
8522 /* If the instruction is an asm statement or multi-instruction
8523 mips.md patern, the length is only an estimate. Insert an
8524 8 byte alignment after it so that the following instructions
8525 can be handled correctly. */
8526 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8527 && (recog_memoized (insn) < 0 || length >= 8))
8529 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8530 next = NEXT_INSN (next);
8531 mips_sim_next_cycle (&state);
8534 else if (length & 4)
8535 aligned_p = !aligned_p;
8540 /* See whether INSN is an aligned label. */
8541 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8547 /* Subroutine of mips_reorg. If there is a hazard between INSN
8548 and a previous instruction, avoid it by inserting nops after
8551 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8552 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8553 before using the value of that register. *HILO_DELAY counts the
8554 number of instructions since the last hilo hazard (that is,
8555 the number of instructions since the last mflo or mfhi).
8557 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8558 for the next instruction.
8560 LO_REG is an rtx for the LO register, used in dependence checking. */
8563 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8564 rtx *delayed_reg, rtx lo_reg)
8572 pattern = PATTERN (insn);
8574 /* Do not put the whole function in .set noreorder if it contains
8575 an asm statement. We don't know whether there will be hazards
8576 between the asm statement and the gcc-generated code. */
8577 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8578 cfun->machine->all_noreorder_p = false;
8580 /* Ignore zero-length instructions (barriers and the like). */
8581 ninsns = get_attr_length (insn) / 4;
8585 /* Work out how many nops are needed. Note that we only care about
8586 registers that are explicitly mentioned in the instruction's pattern.
8587 It doesn't matter that calls use the argument registers or that they
8588 clobber hi and lo. */
8589 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8590 nops = 2 - *hilo_delay;
8591 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8596 /* Insert the nops between this instruction and the previous one.
8597 Each new nop takes us further from the last hilo hazard. */
8598 *hilo_delay += nops;
8600 emit_insn_after (gen_hazard_nop (), after);
8602 /* Set up the state for the next instruction. */
8603 *hilo_delay += ninsns;
8605 if (INSN_CODE (insn) >= 0)
8606 switch (get_attr_hazard (insn))
8616 set = single_set (insn);
8617 gcc_assert (set != 0);
8618 *delayed_reg = SET_DEST (set);
8624 /* Go through the instruction stream and insert nops where necessary.
8625 See if the whole function can then be put into .set noreorder &
8629 mips_avoid_hazards (void)
8631 rtx insn, last_insn, lo_reg, delayed_reg;
8634 /* Force all instructions to be split into their final form. */
8635 split_all_insns_noflow ();
8637 /* Recalculate instruction lengths without taking nops into account. */
8638 cfun->machine->ignore_hazard_length_p = true;
8639 shorten_branches (get_insns ());
8641 cfun->machine->all_noreorder_p = true;
8643 /* Profiled functions can't be all noreorder because the profiler
8644 support uses assembler macros. */
8645 if (current_function_profile)
8646 cfun->machine->all_noreorder_p = false;
8648 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8649 we rely on the assembler to work around some errata. */
8650 if (TARGET_FIX_VR4120)
8651 cfun->machine->all_noreorder_p = false;
8653 /* The same is true for -mfix-vr4130 if we might generate mflo or
8654 mfhi instructions. Note that we avoid using mflo and mfhi if
8655 the VR4130 macc and dmacc instructions are available instead;
8656 see the *mfhilo_{si,di}_macc patterns. */
8657 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
8658 cfun->machine->all_noreorder_p = false;
8663 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8665 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8668 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8669 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8670 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8671 &hilo_delay, &delayed_reg, lo_reg);
8673 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8674 &delayed_reg, lo_reg);
8681 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8687 mips16_lay_out_constants ();
8688 else if (TARGET_EXPLICIT_RELOCS)
8690 if (mips_flag_delayed_branch)
8691 dbr_schedule (get_insns (), dump_file);
8692 mips_avoid_hazards ();
8693 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
8694 vr4130_align_insns ();
8698 /* This function does three things:
8700 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8701 - Register the mips16 hardware floating point stubs.
8702 - Register the gofast functions if selected using --enable-gofast. */
8704 #include "config/gofast.h"
8707 mips_init_libfuncs (void)
8709 if (TARGET_FIX_VR4120)
8711 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8712 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8715 if (TARGET_MIPS16 && mips16_hard_float)
8717 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8718 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8719 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8720 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8722 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8723 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8724 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8725 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8726 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8727 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8729 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8730 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8732 if (TARGET_DOUBLE_FLOAT)
8734 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8735 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8736 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8737 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8739 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8740 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8741 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8742 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8743 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8744 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8746 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8747 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8749 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8750 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8754 gofast_maybe_init_libfuncs ();
8757 /* Return a number assessing the cost of moving a register in class
8758 FROM to class TO. The classes are expressed using the enumeration
8759 values such as `GENERAL_REGS'. A value of 2 is the default; other
8760 values are interpreted relative to that.
8762 It is not required that the cost always equal 2 when FROM is the
8763 same as TO; on some machines it is expensive to move between
8764 registers if they are not general registers.
8766 If reload sees an insn consisting of a single `set' between two
8767 hard registers, and if `REGISTER_MOVE_COST' applied to their
8768 classes returns a value of 2, reload does not check to ensure that
8769 the constraints of the insn are met. Setting a cost of other than
8770 2 will allow reload to verify that the constraints are met. You
8771 should do this if the `movM' pattern's constraints do not allow
8774 ??? We make the cost of moving from HI/LO into general
8775 registers the same as for one of moving general registers to
8776 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8777 pseudo to HI/LO. This might hurt optimizations though, it
8778 isn't clear if it is wise. And it might not work in all cases. We
8779 could solve the DImode LO reg problem by using a multiply, just
8780 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8781 problem by using divide instructions. divu puts the remainder in
8782 the HI reg, so doing a divide by -1 will move the value in the HI
8783 reg for all values except -1. We could handle that case by using a
8784 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8785 a compare/branch to test the input value to see which instruction
8786 we need to use. This gets pretty messy, but it is feasible. */
8789 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8790 enum reg_class to, enum reg_class from)
8792 if (from == M16_REGS && GR_REG_CLASS_P (to))
8794 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8796 else if (GR_REG_CLASS_P (from))
8800 else if (to == M16_NA_REGS)
8802 else if (GR_REG_CLASS_P (to))
8809 else if (to == FP_REGS)
8811 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8818 else if (COP_REG_CLASS_P (to))
8823 else if (from == FP_REGS)
8825 if (GR_REG_CLASS_P (to))
8827 else if (to == FP_REGS)
8829 else if (to == ST_REGS)
8832 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8834 if (GR_REG_CLASS_P (to))
8842 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8844 else if (COP_REG_CLASS_P (from))
8850 ??? What cases are these? Shouldn't we return 2 here? */
8855 /* Return the length of INSN. LENGTH is the initial length computed by
8856 attributes in the machine-description file. */
8859 mips_adjust_insn_length (rtx insn, int length)
8861 /* A unconditional jump has an unfilled delay slot if it is not part
8862 of a sequence. A conditional jump normally has a delay slot, but
8863 does not on MIPS16. */
8864 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
8867 /* See how many nops might be needed to avoid hardware hazards. */
8868 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8869 switch (get_attr_hazard (insn))
8883 /* All MIPS16 instructions are a measly two bytes. */
8891 /* Return an asm sequence to start a noat block and load the address
8892 of a label into $1. */
8895 mips_output_load_label (void)
8897 if (TARGET_EXPLICIT_RELOCS)
8901 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8904 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8907 if (ISA_HAS_LOAD_DELAY)
8908 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8909 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8913 if (Pmode == DImode)
8914 return "%[dla\t%@,%0";
8916 return "%[la\t%@,%0";
8921 /* Output assembly instructions to peform a conditional branch.
8923 INSN is the branch instruction. OPERANDS[0] is the condition.
8924 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8925 of the first operand to the condition. If TWO_OPERANDS_P is
8926 nonzero the comparison takes two operands; OPERANDS[3] will be the
8929 If INVERTED_P is nonzero we are to branch if the condition does
8930 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
8932 LENGTH is the length (in bytes) of the sequence we are to generate.
8933 That tells us whether to generate a simple conditional branch, or a
8934 reversed conditional branch around a `jr' instruction. */
8936 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
8937 int float_p, int inverted_p, int length)
8939 static char buffer[200];
8940 /* The kind of comparison we are doing. */
8941 enum rtx_code code = GET_CODE (operands[0]);
8942 /* Nonzero if the opcode for the comparison needs a `z' indicating
8943 that it is a comparison against zero. */
8945 /* A string to use in the assembly output to represent the first
8947 const char *op1 = "%z2";
8948 /* A string to use in the assembly output to represent the second
8949 operand. Use the hard-wired zero register if there's no second
8951 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
8952 /* The operand-printing string for the comparison. */
8953 const char *const comp = (float_p ? "%F0" : "%C0");
8954 /* The operand-printing string for the inverted comparison. */
8955 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
8957 /* The MIPS processors (for levels of the ISA at least two), have
8958 "likely" variants of each branch instruction. These instructions
8959 annul the instruction in the delay slot if the branch is not
8961 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8963 if (!two_operands_p)
8965 /* To compute whether than A > B, for example, we normally
8966 subtract B from A and then look at the sign bit. But, if we
8967 are doing an unsigned comparison, and B is zero, we don't
8968 have to do the subtraction. Instead, we can just check to
8969 see if A is nonzero. Thus, we change the CODE here to
8970 reflect the simpler comparison operation. */
8982 /* A condition which will always be true. */
8988 /* A condition which will always be false. */
8994 /* Not a special case. */
8999 /* Relative comparisons are always done against zero. But
9000 equality comparisons are done between two operands, and therefore
9001 do not require a `z' in the assembly language output. */
9002 need_z_p = (!float_p && code != EQ && code != NE);
9003 /* For comparisons against zero, the zero is not provided
9008 /* Begin by terminating the buffer. That way we can always use
9009 strcat to add to it. */
9016 /* Just a simple conditional branch. */
9018 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
9019 inverted_p ? inverted_comp : comp);
9021 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
9022 inverted_p ? inverted_comp : comp,
9023 need_z_p ? "z" : "",
9033 /* Generate a reversed conditional branch around ` j'
9046 If the original branch was a likely branch, the delay slot
9047 must be executed only if the branch is taken, so generate:
9059 When generating PIC, instead of:
9072 rtx target = gen_label_rtx ();
9074 orig_target = operands[1];
9075 operands[1] = target;
9076 /* Generate the reversed comparison. This takes four
9079 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9080 inverted_p ? comp : inverted_comp);
9082 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9083 inverted_p ? comp : inverted_comp,
9084 need_z_p ? "z" : "",
9087 output_asm_insn (buffer, operands);
9089 if (length != 16 && length != 28 && ! mips_branch_likely)
9091 /* Output delay slot instruction. */
9092 rtx insn = final_sequence;
9093 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9095 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9098 output_asm_insn ("%#", 0);
9101 output_asm_insn ("j\t%0", &orig_target);
9104 output_asm_insn (mips_output_load_label (), &orig_target);
9105 output_asm_insn ("jr\t%@%]", 0);
9108 if (length != 16 && length != 28 && mips_branch_likely)
9110 /* Output delay slot instruction. */
9111 rtx insn = final_sequence;
9112 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9114 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9117 output_asm_insn ("%#", 0);
9119 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9120 CODE_LABEL_NUMBER (target));
9133 /* Used to output div or ddiv instruction DIVISION, which has the operands
9134 given by OPERANDS. Add in a divide-by-zero check if needed.
9136 When working around R4000 and R4400 errata, we need to make sure that
9137 the division is not immediately followed by a shift[1][2]. We also
9138 need to stop the division from being put into a branch delay slot[3].
9139 The easiest way to avoid both problems is to add a nop after the
9140 division. When a divide-by-zero check is needed, this nop can be
9141 used to fill the branch delay slot.
9143 [1] If a double-word or a variable shift executes immediately
9144 after starting an integer division, the shift may give an
9145 incorrect result. See quotations of errata #16 and #28 from
9146 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9147 in mips.md for details.
9149 [2] A similar bug to [1] exists for all revisions of the
9150 R4000 and the R4400 when run in an MC configuration.
9151 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9153 "19. In this following sequence:
9155 ddiv (or ddivu or div or divu)
9156 dsll32 (or dsrl32, dsra32)
9158 if an MPT stall occurs, while the divide is slipping the cpu
9159 pipeline, then the following double shift would end up with an
9162 Workaround: The compiler needs to avoid generating any
9163 sequence with divide followed by extended double shift."
9165 This erratum is also present in "MIPS R4400MC Errata, Processor
9166 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9167 & 3.0" as errata #10 and #4, respectively.
9169 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9170 (also valid for MIPS R4000MC processors):
9172 "52. R4000SC: This bug does not apply for the R4000PC.
9174 There are two flavors of this bug:
9176 1) If the instruction just after divide takes an RF exception
9177 (tlb-refill, tlb-invalid) and gets an instruction cache
9178 miss (both primary and secondary) and the line which is
9179 currently in secondary cache at this index had the first
9180 data word, where the bits 5..2 are set, then R4000 would
9181 get a wrong result for the div.
9186 ------------------- # end-of page. -tlb-refill
9191 ------------------- # end-of page. -tlb-invalid
9194 2) If the divide is in the taken branch delay slot, where the
9195 target takes RF exception and gets an I-cache miss for the
9196 exception vector or where I-cache miss occurs for the
9197 target address, under the above mentioned scenarios, the
9198 div would get wrong results.
9201 j r2 # to next page mapped or unmapped
9202 div r8,r9 # this bug would be there as long
9203 # as there is an ICache miss and
9204 nop # the "data pattern" is present
9207 beq r0, r0, NextPage # to Next page
9211 This bug is present for div, divu, ddiv, and ddivu
9214 Workaround: For item 1), OS could make sure that the next page
9215 after the divide instruction is also mapped. For item 2), the
9216 compiler could make sure that the divide instruction is not in
9217 the branch delay slot."
9219 These processors have PRId values of 0x00004220 and 0x00004300 for
9220 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9223 mips_output_division (const char *division, rtx *operands)
9228 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9230 output_asm_insn (s, operands);
9233 if (TARGET_CHECK_ZERO_DIV)
9237 output_asm_insn (s, operands);
9238 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9240 else if (GENERATE_DIVIDE_TRAPS)
9242 output_asm_insn (s, operands);
9247 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9248 output_asm_insn (s, operands);
9249 s = "break\t7%)\n1:";
9255 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9256 with a final "000" replaced by "k". Ignore case.
9258 Note: this function is shared between GCC and GAS. */
9261 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9263 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9264 given++, canonical++;
9266 return ((*given == 0 && *canonical == 0)
9267 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9271 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9272 CPU name. We've traditionally allowed a lot of variation here.
9274 Note: this function is shared between GCC and GAS. */
9277 mips_matching_cpu_name_p (const char *canonical, const char *given)
9279 /* First see if the name matches exactly, or with a final "000"
9281 if (mips_strict_matching_cpu_name_p (canonical, given))
9284 /* If not, try comparing based on numerical designation alone.
9285 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9286 if (TOLOWER (*given) == 'r')
9288 if (!ISDIGIT (*given))
9291 /* Skip over some well-known prefixes in the canonical name,
9292 hoping to find a number there too. */
9293 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9295 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9297 else if (TOLOWER (canonical[0]) == 'r')
9300 return mips_strict_matching_cpu_name_p (canonical, given);
9304 /* Return the mips_cpu_info entry for the processor or ISA given
9305 by CPU_STRING. Return null if the string isn't recognized.
9307 A similar function exists in GAS. */
9309 static const struct mips_cpu_info *
9310 mips_parse_cpu (const char *cpu_string)
9312 const struct mips_cpu_info *p;
9315 /* In the past, we allowed upper-case CPU names, but it doesn't
9316 work well with the multilib machinery. */
9317 for (s = cpu_string; *s != 0; s++)
9320 warning (0, "the cpu name must be lower case");
9324 /* 'from-abi' selects the most compatible architecture for the given
9325 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9326 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9327 version. Look first at the -mgp options, if given, otherwise base
9328 the choice on MASK_64BIT in TARGET_DEFAULT. */
9329 if (strcasecmp (cpu_string, "from-abi") == 0)
9330 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9331 : ABI_NEEDS_64BIT_REGS ? 3
9332 : (TARGET_64BIT ? 3 : 1));
9334 /* 'default' has traditionally been a no-op. Probably not very useful. */
9335 if (strcasecmp (cpu_string, "default") == 0)
9338 for (p = mips_cpu_info_table; p->name != 0; p++)
9339 if (mips_matching_cpu_name_p (p->name, cpu_string))
9346 /* Return the processor associated with the given ISA level, or null
9347 if the ISA isn't valid. */
9349 static const struct mips_cpu_info *
9350 mips_cpu_info_from_isa (int isa)
9352 const struct mips_cpu_info *p;
9354 for (p = mips_cpu_info_table; p->name != 0; p++)
9361 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9362 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9363 they only hold condition code modes, and CCmode is always considered to
9364 be 4 bytes wide. All other registers are word sized. */
9367 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9369 if (ST_REG_P (regno))
9370 return ((GET_MODE_SIZE (mode) + 3) / 4);
9371 else if (! FP_REG_P (regno))
9372 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9374 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9377 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9378 all BLKmode objects are returned in memory. Under the new (N32 and
9379 64-bit MIPS ABIs) small structures are returned in a register.
9380 Objects with varying size must still be returned in memory, of
9384 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9387 return (TYPE_MODE (type) == BLKmode);
9389 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9390 || (int_size_in_bytes (type) == -1));
9394 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9396 return !TARGET_OLDABI;
9399 /* Return true if INSN is a multiply-add or multiply-subtract
9400 instruction and PREV assigns to the accumulator operand. */
9403 mips_linked_madd_p (rtx prev, rtx insn)
9407 x = single_set (insn);
9413 if (GET_CODE (x) == PLUS
9414 && GET_CODE (XEXP (x, 0)) == MULT
9415 && reg_set_p (XEXP (x, 1), prev))
9418 if (GET_CODE (x) == MINUS
9419 && GET_CODE (XEXP (x, 1)) == MULT
9420 && reg_set_p (XEXP (x, 0), prev))
9426 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9427 that may clobber hi or lo. */
9429 static rtx mips_macc_chains_last_hilo;
9431 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9432 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9435 mips_macc_chains_record (rtx insn)
9437 if (get_attr_may_clobber_hilo (insn))
9438 mips_macc_chains_last_hilo = insn;
9441 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9442 has NREADY elements, looking for a multiply-add or multiply-subtract
9443 instruction that is cumulative with mips_macc_chains_last_hilo.
9444 If there is one, promote it ahead of anything else that might
9445 clobber hi or lo. */
9448 mips_macc_chains_reorder (rtx *ready, int nready)
9452 if (mips_macc_chains_last_hilo != 0)
9453 for (i = nready - 1; i >= 0; i--)
9454 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9456 for (j = nready - 1; j > i; j--)
9457 if (recog_memoized (ready[j]) >= 0
9458 && get_attr_may_clobber_hilo (ready[j]))
9460 mips_promote_ready (ready, i, j);
9467 /* The last instruction to be scheduled. */
9469 static rtx vr4130_last_insn;
9471 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9472 points to an rtx that is initially an instruction. Nullify the rtx
9473 if the instruction uses the value of register X. */
9476 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9478 rtx *insn_ptr = data;
9481 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9485 /* Return true if there is true register dependence between vr4130_last_insn
9489 vr4130_true_reg_dependence_p (rtx insn)
9491 note_stores (PATTERN (vr4130_last_insn),
9492 vr4130_true_reg_dependence_p_1, &insn);
9496 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9497 the ready queue and that INSN2 is the instruction after it, return
9498 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9499 in which INSN1 and INSN2 can probably issue in parallel, but for
9500 which (INSN2, INSN1) should be less sensitive to instruction
9501 alignment than (INSN1, INSN2). See 4130.md for more details. */
9504 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9508 /* Check for the following case:
9510 1) there is some other instruction X with an anti dependence on INSN1;
9511 2) X has a higher priority than INSN2; and
9512 3) X is an arithmetic instruction (and thus has no unit restrictions).
9514 If INSN1 is the last instruction blocking X, it would better to
9515 choose (INSN1, X) over (INSN2, INSN1). */
9516 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9517 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9518 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9519 && recog_memoized (XEXP (dep, 0)) >= 0
9520 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9523 if (vr4130_last_insn != 0
9524 && recog_memoized (insn1) >= 0
9525 && recog_memoized (insn2) >= 0)
9527 /* See whether INSN1 and INSN2 use different execution units,
9528 or if they are both ALU-type instructions. If so, they can
9529 probably execute in parallel. */
9530 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9531 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9532 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9534 /* If only one of the instructions has a dependence on
9535 vr4130_last_insn, prefer to schedule the other one first. */
9536 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9537 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9541 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9542 is not an ALU-type instruction and if INSN1 uses the same
9543 execution unit. (Note that if this condition holds, we already
9544 know that INSN2 uses a different execution unit.) */
9545 if (class1 != VR4130_CLASS_ALU
9546 && recog_memoized (vr4130_last_insn) >= 0
9547 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9554 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9555 queue with at least two instructions. Swap the first two if
9556 vr4130_swap_insns_p says that it could be worthwhile. */
9559 vr4130_reorder (rtx *ready, int nready)
9561 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9562 mips_promote_ready (ready, nready - 2, nready - 1);
9565 /* Remove the instruction at index LOWER from ready queue READY and
9566 reinsert it in front of the instruction at index HIGHER. LOWER must
9570 mips_promote_ready (rtx *ready, int lower, int higher)
9575 new_head = ready[lower];
9576 for (i = lower; i < higher; i++)
9577 ready[i] = ready[i + 1];
9578 ready[i] = new_head;
9581 /* Implement TARGET_SCHED_REORDER. */
9584 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9585 rtx *ready, int *nreadyp, int cycle)
9587 if (!reload_completed && TUNE_MACC_CHAINS)
9590 mips_macc_chains_last_hilo = 0;
9592 mips_macc_chains_reorder (ready, *nreadyp);
9594 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9597 vr4130_last_insn = 0;
9599 vr4130_reorder (ready, *nreadyp);
9601 return mips_issue_rate ();
9604 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9607 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9610 switch (GET_CODE (PATTERN (insn)))
9614 /* Don't count USEs and CLOBBERs against the issue rate. */
9619 if (!reload_completed && TUNE_MACC_CHAINS)
9620 mips_macc_chains_record (insn);
9621 vr4130_last_insn = insn;
9627 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9628 dependencies have no cost. */
9631 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9632 rtx dep ATTRIBUTE_UNUSED, int cost)
9634 if (REG_NOTE_KIND (link) != 0)
9639 /* Return the number of instructions that can be issued per cycle. */
9642 mips_issue_rate (void)
9646 case PROCESSOR_R4130:
9647 case PROCESSOR_R5400:
9648 case PROCESSOR_R5500:
9649 case PROCESSOR_R7000:
9650 case PROCESSOR_R9000:
9654 /* This is actually 4, but we get better performance if we claim 3.
9655 This is partly because of unwanted speculative code motion with the
9656 larger number, and partly because in most common cases we can't
9657 reach the theoretical max of 4. */
9665 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9666 be as wide as the scheduling freedom in the DFA. */
9669 mips_multipass_dfa_lookahead (void)
9671 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9672 if (mips_tune == PROCESSOR_SB1)
9678 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9679 return the first operand of the associated "pref" or "prefx" insn. */
9682 mips_prefetch_cookie (rtx write, rtx locality)
9684 /* store_streamed / load_streamed. */
9685 if (INTVAL (locality) <= 0)
9686 return GEN_INT (INTVAL (write) + 4);
9689 if (INTVAL (locality) <= 2)
9692 /* store_retained / load_retained. */
9693 return GEN_INT (INTVAL (write) + 6);
9696 /* MIPS builtin function support. */
9698 struct builtin_description
9700 /* The code of the main .md file instruction. See mips_builtin_type
9701 for more information. */
9702 enum insn_code icode;
9704 /* The floating-point comparison code to use with ICODE, if any. */
9705 enum mips_fp_condition cond;
9707 /* The name of the builtin function. */
9710 /* Specifies how the function should be expanded. */
9711 enum mips_builtin_type builtin_type;
9713 /* The function's prototype. */
9714 enum mips_function_type function_type;
9716 /* The target flags required for this function. */
9720 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9721 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9722 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9723 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9724 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9726 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9728 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9729 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9730 "__builtin_mips_" #INSN "_" #COND "_s", \
9731 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9732 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9733 "__builtin_mips_" #INSN "_" #COND "_d", \
9734 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9736 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9737 The lower and upper forms require TARGET_FLAGS while the any and all
9738 forms require MASK_MIPS3D. */
9739 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9740 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9741 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9742 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9743 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9744 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9745 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9746 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9747 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9748 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9749 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9750 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9751 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9753 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9754 require MASK_MIPS3D. */
9755 #define CMP_4S_BUILTINS(INSN, COND) \
9756 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9757 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9758 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9760 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9761 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9762 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9765 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
9766 instruction requires TARGET_FLAGS. */
9767 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
9768 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9769 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
9770 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9772 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9773 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
9774 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9777 /* Define all the builtins related to c.cond.fmt condition COND. */
9778 #define CMP_BUILTINS(COND) \
9779 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9780 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
9781 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
9782 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9783 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
9784 CMP_4S_BUILTINS (c, COND), \
9785 CMP_4S_BUILTINS (cabs, COND)
9787 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
9788 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
9790 static const struct builtin_description mips_bdesc[] =
9792 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9793 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9794 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9795 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9796 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
9797 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9798 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9799 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9801 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
9802 MASK_PAIRED_SINGLE_FLOAT),
9803 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9804 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9805 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9806 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9808 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9809 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9810 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9811 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9812 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9813 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9815 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9816 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9817 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9818 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9819 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9820 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9822 MIPS_FP_CONDITIONS (CMP_BUILTINS)
9825 /* Builtin functions for the SB-1 processor. */
9827 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
9829 static const struct builtin_description sb1_bdesc[] =
9831 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
9834 /* This helps provide a mapping from builtin function codes to bdesc
9839 /* The builtin function table that this entry describes. */
9840 const struct builtin_description *bdesc;
9842 /* The number of entries in the builtin function table. */
9845 /* The target processor that supports these builtin functions.
9846 PROCESSOR_MAX means we enable them for all processors. */
9847 enum processor_type proc;
9850 static const struct bdesc_map bdesc_arrays[] =
9852 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
9853 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 }
9856 /* Take the head of argument list *ARGLIST and convert it into a form
9857 suitable for input operand OP of instruction ICODE. Return the value
9858 and point *ARGLIST at the next element of the list. */
9861 mips_prepare_builtin_arg (enum insn_code icode,
9862 unsigned int op, tree *arglist)
9865 enum machine_mode mode;
9867 value = expand_expr (TREE_VALUE (*arglist), NULL_RTX, VOIDmode, 0);
9868 mode = insn_data[icode].operand[op].mode;
9869 if (!insn_data[icode].operand[op].predicate (value, mode))
9870 value = copy_to_mode_reg (mode, value);
9872 *arglist = TREE_CHAIN (*arglist);
9876 /* Return an rtx suitable for output operand OP of instruction ICODE.
9877 If TARGET is non-null, try to use it where possible. */
9880 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
9882 enum machine_mode mode;
9884 mode = insn_data[icode].operand[op].mode;
9885 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
9886 target = gen_reg_rtx (mode);
9891 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
9894 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9895 enum machine_mode mode ATTRIBUTE_UNUSED,
9896 int ignore ATTRIBUTE_UNUSED)
9898 enum insn_code icode;
9899 enum mips_builtin_type type;
9900 tree fndecl, arglist;
9902 const struct builtin_description *bdesc;
9903 const struct bdesc_map *m;
9905 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9906 arglist = TREE_OPERAND (exp, 1);
9907 fcode = DECL_FUNCTION_CODE (fndecl);
9910 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
9912 if (fcode < m->size)
9915 icode = bdesc[fcode].icode;
9916 type = bdesc[fcode].builtin_type;
9926 case MIPS_BUILTIN_DIRECT:
9927 return mips_expand_builtin_direct (icode, target, arglist);
9929 case MIPS_BUILTIN_MOVT:
9930 case MIPS_BUILTIN_MOVF:
9931 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
9934 case MIPS_BUILTIN_CMP_ANY:
9935 case MIPS_BUILTIN_CMP_ALL:
9936 case MIPS_BUILTIN_CMP_UPPER:
9937 case MIPS_BUILTIN_CMP_LOWER:
9938 case MIPS_BUILTIN_CMP_SINGLE:
9939 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
9947 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
9950 mips_init_builtins (void)
9952 const struct builtin_description *d;
9953 const struct bdesc_map *m;
9954 tree types[(int) MIPS_MAX_FTYPE_MAX];
9955 tree V2SF_type_node;
9956 unsigned int offset;
9958 /* We have only builtins for -mpaired-single and -mips3d. */
9959 if (!TARGET_PAIRED_SINGLE_FLOAT)
9962 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
9964 types[MIPS_V2SF_FTYPE_V2SF]
9965 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
9967 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
9968 = build_function_type_list (V2SF_type_node,
9969 V2SF_type_node, V2SF_type_node, NULL_TREE);
9971 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
9972 = build_function_type_list (V2SF_type_node,
9973 V2SF_type_node, V2SF_type_node,
9974 integer_type_node, NULL_TREE);
9976 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
9977 = build_function_type_list (V2SF_type_node,
9978 V2SF_type_node, V2SF_type_node,
9979 V2SF_type_node, V2SF_type_node, NULL_TREE);
9981 types[MIPS_V2SF_FTYPE_SF_SF]
9982 = build_function_type_list (V2SF_type_node,
9983 float_type_node, float_type_node, NULL_TREE);
9985 types[MIPS_INT_FTYPE_V2SF_V2SF]
9986 = build_function_type_list (integer_type_node,
9987 V2SF_type_node, V2SF_type_node, NULL_TREE);
9989 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
9990 = build_function_type_list (integer_type_node,
9991 V2SF_type_node, V2SF_type_node,
9992 V2SF_type_node, V2SF_type_node, NULL_TREE);
9994 types[MIPS_INT_FTYPE_SF_SF]
9995 = build_function_type_list (integer_type_node,
9996 float_type_node, float_type_node, NULL_TREE);
9998 types[MIPS_INT_FTYPE_DF_DF]
9999 = build_function_type_list (integer_type_node,
10000 double_type_node, double_type_node, NULL_TREE);
10002 types[MIPS_SF_FTYPE_V2SF]
10003 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10005 types[MIPS_SF_FTYPE_SF]
10006 = build_function_type_list (float_type_node,
10007 float_type_node, NULL_TREE);
10009 types[MIPS_SF_FTYPE_SF_SF]
10010 = build_function_type_list (float_type_node,
10011 float_type_node, float_type_node, NULL_TREE);
10013 types[MIPS_DF_FTYPE_DF]
10014 = build_function_type_list (double_type_node,
10015 double_type_node, NULL_TREE);
10017 types[MIPS_DF_FTYPE_DF_DF]
10018 = build_function_type_list (double_type_node,
10019 double_type_node, double_type_node, NULL_TREE);
10021 /* Iterate through all of the bdesc arrays, initializing all of the
10022 builtin functions. */
10025 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10027 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10028 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10029 if ((d->target_flags & target_flags) == d->target_flags)
10030 lang_hooks.builtin_function (d->name, types[d->function_type],
10031 d - m->bdesc + offset,
10032 BUILT_IN_MD, NULL, NULL);
10037 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10038 .md pattern and ARGLIST is the list of function arguments. TARGET,
10039 if nonnull, suggests a good place to put the result. */
10042 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist)
10044 rtx ops[MAX_RECOG_OPERANDS];
10047 target = mips_prepare_builtin_target (icode, 0, target);
10048 for (i = 1; i < insn_data[icode].n_operands; i++)
10049 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10051 switch (insn_data[icode].n_operands)
10054 emit_insn (GEN_FCN (icode) (target, ops[1]));
10058 emit_insn (GEN_FCN (icode) (target, ops[1], ops[2]));
10062 emit_insn (GEN_FCN (icode) (target, ops[1], ops[2], ops[3]));
10066 gcc_unreachable ();
10071 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10072 function (TYPE says which). ARGLIST is the list of arguments to the
10073 function, ICODE is the instruction that should be used to compare
10074 the first two arguments, and COND is the condition it should test.
10075 TARGET, if nonnull, suggests a good place to put the result. */
10078 mips_expand_builtin_movtf (enum mips_builtin_type type,
10079 enum insn_code icode, enum mips_fp_condition cond,
10080 rtx target, tree arglist)
10082 rtx cmp_result, op0, op1;
10084 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10085 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10086 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10087 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10089 icode = CODE_FOR_mips_cond_move_tf_ps;
10090 target = mips_prepare_builtin_target (icode, 0, target);
10091 if (type == MIPS_BUILTIN_MOVT)
10093 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10094 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10098 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10099 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10101 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10105 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10106 of the comparison instruction and COND is the condition it should test.
10107 ARGLIST is the list of function arguments and TARGET, if nonnull,
10108 suggests a good place to put the boolean result. */
10111 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10112 enum insn_code icode, enum mips_fp_condition cond,
10113 rtx target, tree arglist)
10115 rtx label1, label2, if_then_else;
10116 rtx pat, cmp_result, ops[MAX_RECOG_OPERANDS];
10117 rtx target_if_equal, target_if_unequal;
10120 if (target == 0 || GET_MODE (target) != SImode)
10121 target = gen_reg_rtx (SImode);
10123 /* Prepare the operands to the comparison. */
10124 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10125 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10126 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10128 switch (insn_data[icode].n_operands)
10131 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond));
10135 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10136 ops[3], ops[4], GEN_INT (cond));
10140 gcc_unreachable ();
10143 /* If the comparison sets more than one register, we define the result
10144 to be 0 if all registers are false and -1 if all registers are true.
10145 The value of the complete result is indeterminate otherwise. It is
10146 possible to test individual registers using SUBREGs.
10148 Set up CMP_RESULT, CMP_VALUE, TARGET_IF_EQUAL and TARGET_IF_UNEQUAL so
10149 that the result should be TARGET_IF_EQUAL if (EQ CMP_RESULT CMP_VALUE)
10150 and TARGET_IF_UNEQUAL otherwise. */
10151 if (builtin_type == MIPS_BUILTIN_CMP_ALL)
10154 target_if_equal = const1_rtx;
10155 target_if_unequal = const0_rtx;
10160 target_if_equal = const0_rtx;
10161 target_if_unequal = const1_rtx;
10162 if (builtin_type == MIPS_BUILTIN_CMP_UPPER)
10163 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 4);
10164 else if (builtin_type == MIPS_BUILTIN_CMP_LOWER)
10165 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 0);
10168 /* First assume that CMP_RESULT == CMP_VALUE. */
10169 emit_move_insn (target, target_if_equal);
10171 /* Branch to LABEL1 if CMP_RESULT != CMP_VALUE. */
10173 label1 = gen_label_rtx ();
10174 label2 = gen_label_rtx ();
10176 = gen_rtx_IF_THEN_ELSE (VOIDmode,
10177 gen_rtx_fmt_ee (NE, GET_MODE (cmp_result),
10178 cmp_result, GEN_INT (cmp_value)),
10179 gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
10180 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
10181 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10182 gen_rtx_LABEL_REF (VOIDmode, label2)));
10184 emit_label (label1);
10186 /* Fix TARGET for CMP_RESULT != CMP_VALUE. */
10187 emit_move_insn (target, target_if_unequal);
10188 emit_label (label2);
10193 #include "gt-mips.h"