2008-04-03 Jan Hubicka <jh@suse.cz>

[pf3gnuchains/gcc-fork.git] / gcc / config / mips / mips.c

/* Subroutines used for MIPS code generation.
   Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
   Free Software Foundation, Inc.
   Contributed by A. Lichnewsky, lich@inria.inria.fr.
   Changes by Michael Meissner, meissner@osf.org.
   64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
   Brendan Eich, brendan@microunity.com.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3.  If not see
<http://www.gnu.org/licenses/>.  */

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include <signal.h>
#include "rtl.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "real.h"
#include "insn-config.h"
#include "conditions.h"
#include "insn-attr.h"
#include "recog.h"
#include "toplev.h"
#include "output.h"
#include "tree.h"
#include "function.h"
#include "expr.h"
#include "optabs.h"
#include "flags.h"
#include "reload.h"
#include "tm_p.h"
#include "ggc.h"
#include "gstab.h"
#include "hashtab.h"
#include "debug.h"
#include "target.h"
#include "target-def.h"
#include "integrate.h"
#include "langhooks.h"
#include "cfglayout.h"
#include "sched-int.h"
#include "tree-gimple.h"
#include "bitmap.h"
#include "diagnostic.h"

/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF.  */
#define UNSPEC_ADDRESS_P(X)                                     \
  (GET_CODE (X) == UNSPEC                                       \
   && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST                       \
   && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)

/* Extract the symbol or label from UNSPEC wrapper X.  */
#define UNSPEC_ADDRESS(X) \
  XVECEXP (X, 0, 0)

/* Extract the symbol type from UNSPEC wrapper X.  */
#define UNSPEC_ADDRESS_TYPE(X) \
  ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))

/* The maximum distance between the top of the stack frame and the
   value $sp has when we save and restore registers.

   The value for normal-mode code must be a SMALL_OPERAND and must
   preserve the maximum stack alignment.  We therefore use a value
   of 0x7ff0 in this case.

   MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
   up to 0x7f8 bytes and can usually save or restore all the registers
   that we need to save or restore.  (Note that we can only use these
   instructions for o32, for which the stack alignment is 8 bytes.)

   We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
   RESTORE are not available.  We can then use unextended instructions
   to save and restore registers, and to allocate and deallocate the top
   part of the frame.  */
#define MIPS_MAX_FIRST_STACK_STEP                                       \
  (!TARGET_MIPS16 ? 0x7ff0                                              \
   : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8                              \
   : TARGET_64BIT ? 0x100 : 0x400)

/* True if INSN is a mips.md pattern or asm statement.  */
#define USEFUL_INSN_P(INSN)                                             \
  (INSN_P (INSN)                                                        \
   && GET_CODE (PATTERN (INSN)) != USE                                  \
   && GET_CODE (PATTERN (INSN)) != CLOBBER                              \
   && GET_CODE (PATTERN (INSN)) != ADDR_VEC                             \
   && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)

/* If INSN is a delayed branch sequence, return the first instruction
   in the sequence, otherwise return INSN itself.  */
#define SEQ_BEGIN(INSN)                                                 \
  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \
   ? XVECEXP (PATTERN (INSN), 0, 0)                                     \
   : (INSN))

/* Likewise for the last instruction in a delayed branch sequence.  */
#define SEQ_END(INSN)                                                   \
  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \
   ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1)       \
   : (INSN))

/* Execute the following loop body with SUBINSN set to each instruction
   between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive.  */
#define FOR_EACH_SUBINSN(SUBINSN, INSN)                                 \
  for ((SUBINSN) = SEQ_BEGIN (INSN);                                    \
       (SUBINSN) != NEXT_INSN (SEQ_END (INSN));                         \
       (SUBINSN) = NEXT_INSN (SUBINSN))

/* True if bit BIT is set in VALUE.  */
#define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)

/* Classifies an address.

   ADDRESS_REG
       A natural register + offset address.  The register satisfies
       mips_valid_base_register_p and the offset is a const_arith_operand.

   ADDRESS_LO_SUM
       A LO_SUM rtx.  The first operand is a valid base register and
       the second operand is a symbolic address.

   ADDRESS_CONST_INT
       A signed 16-bit constant address.

   ADDRESS_SYMBOLIC:
       A constant symbolic address.  */
enum mips_address_type {
  ADDRESS_REG,
  ADDRESS_LO_SUM,
  ADDRESS_CONST_INT,
  ADDRESS_SYMBOLIC
};

/* Macros to create an enumeration identifier for a function prototype.  */
#define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
#define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
#define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
#define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E

/* Classifies the prototype of a built-in function.  */
enum mips_function_type {
#define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
#include "config/mips/mips-ftypes.def"
#undef DEF_MIPS_FTYPE
  MIPS_MAX_FTYPE_MAX
};

/* Specifies how a built-in function should be converted into rtl.  */
enum mips_builtin_type {
  /* The function corresponds directly to an .md pattern.  The return
     value is mapped to operand 0 and the arguments are mapped to
     operands 1 and above.  */
  MIPS_BUILTIN_DIRECT,

  /* The function corresponds directly to an .md pattern.  There is no return
     value and the arguments are mapped to operands 0 and above.  */
  MIPS_BUILTIN_DIRECT_NO_TARGET,

  /* The function corresponds to a comparison instruction followed by
     a mips_cond_move_tf_ps pattern.  The first two arguments are the
     values to compare and the second two arguments are the vector
     operands for the movt.ps or movf.ps instruction (in assembly order).  */
  MIPS_BUILTIN_MOVF,
  MIPS_BUILTIN_MOVT,

  /* The function corresponds to a V2SF comparison instruction.  Operand 0
     of this instruction is the result of the comparison, which has mode
     CCV2 or CCV4.  The function arguments are mapped to operands 1 and
     above.  The function's return value is an SImode boolean that is
     true under the following conditions:

     MIPS_BUILTIN_CMP_ANY: one of the registers is true
     MIPS_BUILTIN_CMP_ALL: all of the registers are true
     MIPS_BUILTIN_CMP_LOWER: the first register is true
     MIPS_BUILTIN_CMP_UPPER: the second register is true.  */
  MIPS_BUILTIN_CMP_ANY,
  MIPS_BUILTIN_CMP_ALL,
  MIPS_BUILTIN_CMP_UPPER,
  MIPS_BUILTIN_CMP_LOWER,

  /* As above, but the instruction only sets a single $fcc register.  */
  MIPS_BUILTIN_CMP_SINGLE,

  /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */
  MIPS_BUILTIN_BPOSGE32
};

/* Invoke MACRO (COND) for each C.cond.fmt condition.  */
#define MIPS_FP_CONDITIONS(MACRO) \
  MACRO (f),    \
  MACRO (un),   \
  MACRO (eq),   \
  MACRO (ueq),  \
  MACRO (olt),  \
  MACRO (ult),  \
  MACRO (ole),  \
  MACRO (ule),  \
  MACRO (sf),   \
  MACRO (ngle), \
  MACRO (seq),  \
  MACRO (ngl),  \
  MACRO (lt),   \
  MACRO (nge),  \
  MACRO (le),   \
  MACRO (ngt)

/* Enumerates the codes above as MIPS_FP_COND_<X>.  */
#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
enum mips_fp_condition {
  MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
};

/* Index X provides the string representation of MIPS_FP_COND_<X>.  */
#define STRINGIFY(X) #X
static const char *const mips_fp_conditions[] = {
  MIPS_FP_CONDITIONS (STRINGIFY)
};

/* Information about a function's frame layout.  */
struct mips_frame_info GTY(()) {
  /* The size of the frame in bytes.  */
  HOST_WIDE_INT total_size;

  /* The number of bytes allocated to variables.  */
  HOST_WIDE_INT var_size;

  /* The number of bytes allocated to outgoing function arguments.  */
  HOST_WIDE_INT args_size;

  /* The number of bytes allocated to the .cprestore slot, or 0 if there
     is no such slot.  */
  HOST_WIDE_INT cprestore_size;

  /* Bit X is set if the function saves or restores GPR X.  */
  unsigned int mask;

  /* Likewise FPR X.  */
  unsigned int fmask;

  /* The number of GPRs and FPRs saved.  */
  unsigned int num_gp;
  unsigned int num_fp;

  /* The offset of the topmost GPR and FPR save slots from the top of
     the frame, or zero if no such slots are needed.  */
  HOST_WIDE_INT gp_save_offset;
  HOST_WIDE_INT fp_save_offset;

  /* Likewise, but giving offsets from the bottom of the frame.  */
  HOST_WIDE_INT gp_sp_offset;
  HOST_WIDE_INT fp_sp_offset;

  /* The offset of arg_pointer_rtx from frame_pointer_rtx.  */
  HOST_WIDE_INT arg_pointer_offset;

  /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx.  */
  HOST_WIDE_INT hard_frame_pointer_offset;
};

struct machine_function GTY(()) {
  /* The register returned by mips16_gp_pseudo_reg; see there for details.  */
  rtx mips16_gp_pseudo_rtx;

  /* The number of extra stack bytes taken up by register varargs.
     This area is allocated by the callee at the very top of the frame.  */
  int varargs_size;

  /* The current frame information, calculated by mips_compute_frame_info.  */
  struct mips_frame_info frame;

  /* The register to use as the function's global pointer.  */
  unsigned int global_pointer;

  /* True if mips_adjust_insn_length should ignore an instruction's
     hazard attribute.  */
  bool ignore_hazard_length_p;

  /* True if the whole function is suitable for .set noreorder and
     .set nomacro.  */
  bool all_noreorder_p;

  /* True if the function is known to have an instruction that needs $gp.  */
  bool has_gp_insn_p;

  /* True if we have emitted an instruction to initialize
     mips16_gp_pseudo_rtx.  */
  bool initialized_mips16_gp_pseudo_p;
};

/* Information about a single argument.  */
struct mips_arg_info {
  /* True if the argument is passed in a floating-point register, or
     would have been if we hadn't run out of registers.  */
  bool fpr_p;

  /* The number of words passed in registers, rounded up.  */
  unsigned int reg_words;

  /* For EABI, the offset of the first register from GP_ARG_FIRST or
     FP_ARG_FIRST.  For other ABIs, the offset of the first register from
     the start of the ABI's argument structure (see the CUMULATIVE_ARGS
     comment for details).

     The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
     on the stack.  */
  unsigned int reg_offset;

  /* The number of words that must be passed on the stack, rounded up.  */
  unsigned int stack_words;

  /* The offset from the start of the stack overflow area of the argument's
     first stack word.  Only meaningful when STACK_WORDS is nonzero.  */
  unsigned int stack_offset;
};

/* Information about an address described by mips_address_type.

   ADDRESS_CONST_INT
       No fields are used.

   ADDRESS_REG
       REG is the base register and OFFSET is the constant offset.

   ADDRESS_LO_SUM
       REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
       is the type of symbol it references.

   ADDRESS_SYMBOLIC
       SYMBOL_TYPE is the type of symbol that the address references.  */
struct mips_address_info {
  enum mips_address_type type;
  rtx reg;
  rtx offset;
  enum mips_symbol_type symbol_type;
};

/* One stage in a constant building sequence.  These sequences have
   the form:

        A = VALUE[0]
        A = A CODE[1] VALUE[1]
        A = A CODE[2] VALUE[2]
        ...

   where A is an accumulator, each CODE[i] is a binary rtl operation
   and each VALUE[i] is a constant integer.  CODE[0] is undefined.  */
struct mips_integer_op {
  enum rtx_code code;
  unsigned HOST_WIDE_INT value;
};

/* The largest number of operations needed to load an integer constant.
   The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
   When the lowest bit is clear, we can try, but reject a sequence with
   an extra SLL at the end.  */
#define MIPS_MAX_INTEGER_OPS 7

/* Information about a MIPS16e SAVE or RESTORE instruction.  */
struct mips16e_save_restore_info {
  /* The number of argument registers saved by a SAVE instruction.
     0 for RESTORE instructions.  */
  unsigned int nargs;

  /* Bit X is set if the instruction saves or restores GPR X.  */
  unsigned int mask;

  /* The total number of bytes to allocate.  */
  HOST_WIDE_INT size;
};

/* Global variables for machine-dependent things.  */

/* The -G setting, or the configuration's default small-data limit if
   no -G option is given.  */
static unsigned int mips_small_data_threshold;

/* The number of file directives written by mips_output_filename.  */
int num_source_filenames;

/* The name that appeared in the last .file directive written by
   mips_output_filename, or "" if mips_output_filename hasn't
   written anything yet.  */
const char *current_function_file = "";

/* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END.  */
int sdb_label_count;

/* Arrays that map GCC register numbers to debugger register numbers.  */
int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];

/* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs.  */
int set_noreorder;
int set_nomacro;
static int set_noat;

/* True if we're writing out a branch-likely instruction rather than a
   normal branch.  */
static bool mips_branch_likely;

/* The operands passed to the last cmpMM expander.  */
rtx cmp_operands[2];

/* The current instruction-set architecture.  */
enum processor_type mips_arch;
const struct mips_cpu_info *mips_arch_info;

/* The processor that we should tune the code for.  */
enum processor_type mips_tune;
const struct mips_cpu_info *mips_tune_info;

/* The ISA level associated with mips_arch.  */
int mips_isa;

/* The architecture selected by -mipsN, or null if -mipsN wasn't used.  */
static const struct mips_cpu_info *mips_isa_option_info;

/* Which ABI to use.  */
int mips_abi = MIPS_ABI_DEFAULT;

/* Which cost information to use.  */
const struct mips_rtx_cost_data *mips_cost;

/* The ambient target flags, excluding MASK_MIPS16.  */
static int mips_base_target_flags;

/* True if MIPS16 is the default mode.  */
static bool mips_base_mips16;

/* The ambient values of other global variables.  */
static int mips_base_delayed_branch; /* flag_delayed_branch */
static int mips_base_schedule_insns; /* flag_schedule_insns */
static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
static int mips_base_align_loops; /* align_loops */
static int mips_base_align_jumps; /* align_jumps */
static int mips_base_align_functions; /* align_functions */

/* The -mcode-readable setting.  */
enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;

/* Index [M][R] is true if register R is allowed to hold a value of mode M.  */
bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];

/* Index C is true if character C is a valid PRINT_OPERAND punctation
   character.  */
bool mips_print_operand_punct[256];

static GTY (()) int mips_output_filename_first_time = 1;

/* mips_split_p[X] is true if symbols of type X can be split by
   mips_split_symbol.  */
bool mips_split_p[NUM_SYMBOL_TYPES];

/* mips_lo_relocs[X] is the relocation to use when a symbol of type X
   appears in a LO_SUM.  It can be null if such LO_SUMs aren't valid or
   if they are matched by a special .md file pattern.  */
static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];

/* Likewise for HIGHs.  */
static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];

/* Index R is the smallest register class that contains register R.  */
const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
  LEA_REGS,     LEA_REGS,       M16_NA_REGS,    V1_REG,
  M16_REGS,     M16_REGS,       M16_REGS,       M16_REGS,
  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
  M16_NA_REGS,  M16_NA_REGS,    LEA_REGS,       LEA_REGS,
  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
  T_REG,        PIC_FN_ADDR_REG, LEA_REGS,      LEA_REGS,
  LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
  FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
  MD0_REG,      MD1_REG,        NO_REGS,        ST_REGS,
  ST_REGS,      ST_REGS,        ST_REGS,        ST_REGS,
  ST_REGS,      ST_REGS,        ST_REGS,        NO_REGS,
  NO_REGS,      ALL_REGS,       ALL_REGS,       NO_REGS,
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
  COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
  COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
  COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
  DSP_ACC_REGS, DSP_ACC_REGS,   DSP_ACC_REGS,   DSP_ACC_REGS,
  DSP_ACC_REGS, DSP_ACC_REGS,   ALL_REGS,       ALL_REGS,
  ALL_REGS,     ALL_REGS,       ALL_REGS,       ALL_REGS
};

/* The value of TARGET_ATTRIBUTE_TABLE.  */
const struct attribute_spec mips_attribute_table[] = {
  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
  { "long_call",   0, 0, false, true,  true,  NULL },
  { "far",         0, 0, false, true,  true,  NULL },
  { "near",        0, 0, false, true,  true,  NULL },
  /* We would really like to treat "mips16" and "nomips16" as type
     attributes, but GCC doesn't provide the hooks we need to support
     the right conversion rules.  As declaration attributes, they affect
     code generation but don't carry other semantics.  */
  { "mips16",      0, 0, true,  false, false, NULL },
  { "nomips16",    0, 0, true,  false, false, NULL },
  { NULL,          0, 0, false, false, false, NULL }
};
\f
/* A table describing all the processors GCC knows about.  Names are
   matched in the order listed.  The first mention of an ISA level is
   taken as the canonical name for that ISA.

   To ease comparison, please keep this table in the same order
   as GAS's mips_cpu_info_table.  Please also make sure that
   MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
   options correctly.  */
static const struct mips_cpu_info mips_cpu_info_table[] = {
  /* Entries for generic ISAs.  */
  { "mips1", PROCESSOR_R3000, 1, 0 },
  { "mips2", PROCESSOR_R6000, 2, 0 },
  { "mips3", PROCESSOR_R4000, 3, 0 },
  { "mips4", PROCESSOR_R8000, 4, 0 },
  /* Prefer not to use branch-likely instructions for generic MIPS32rX
     and MIPS64rX code.  The instructions were officially deprecated
     in revisions 2 and earlier, but revision 3 is likely to downgrade
     that to a recommendation to avoid the instructions in code that
     isn't tuned to a specific processor.  */
  { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
  { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
  { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },

  /* MIPS I processors.  */
  { "r3000", PROCESSOR_R3000, 1, 0 },
  { "r2000", PROCESSOR_R3000, 1, 0 },
  { "r3900", PROCESSOR_R3900, 1, 0 },

  /* MIPS II processors.  */
  { "r6000", PROCESSOR_R6000, 2, 0 },

  /* MIPS III processors.  */
  { "r4000", PROCESSOR_R4000, 3, 0 },
  { "vr4100", PROCESSOR_R4100, 3, 0 },
  { "vr4111", PROCESSOR_R4111, 3, 0 },
  { "vr4120", PROCESSOR_R4120, 3, 0 },
  { "vr4130", PROCESSOR_R4130, 3, 0 },
  { "vr4300", PROCESSOR_R4300, 3, 0 },
  { "r4400", PROCESSOR_R4000, 3, 0 },
  { "r4600", PROCESSOR_R4600, 3, 0 },
  { "orion", PROCESSOR_R4600, 3, 0 },
  { "r4650", PROCESSOR_R4650, 3, 0 },

  /* MIPS IV processors. */
  { "r8000", PROCESSOR_R8000, 4, 0 },
  { "vr5000", PROCESSOR_R5000, 4, 0 },
  { "vr5400", PROCESSOR_R5400, 4, 0 },
  { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
  { "rm7000", PROCESSOR_R7000, 4, 0 },
  { "rm9000", PROCESSOR_R9000, 4, 0 },

  /* MIPS32 processors.  */
  { "4kc", PROCESSOR_4KC, 32, 0 },
  { "4km", PROCESSOR_4KC, 32, 0 },
  { "4kp", PROCESSOR_4KP, 32, 0 },
  { "4ksc", PROCESSOR_4KC, 32, 0 },

  /* MIPS32 Release 2 processors.  */
  { "m4k", PROCESSOR_M4K, 33, 0 },
  { "4kec", PROCESSOR_4KC, 33, 0 },
  { "4kem", PROCESSOR_4KC, 33, 0 },
  { "4kep", PROCESSOR_4KP, 33, 0 },
  { "4ksd", PROCESSOR_4KC, 33, 0 },

  { "24kc", PROCESSOR_24KC, 33, 0 },
  { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
  { "24kf", PROCESSOR_24KF2_1, 33, 0 },
  { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
  { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
  { "24kx", PROCESSOR_24KF1_1, 33, 0 },

  { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP.  */
  { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
  { "24kef", PROCESSOR_24KF2_1, 33, 0 },
  { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
  { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
  { "24kex", PROCESSOR_24KF1_1, 33, 0 },

  { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP.  */
  { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
  { "34kf", PROCESSOR_24KF2_1, 33, 0 },
  { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
  { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
  { "34kx", PROCESSOR_24KF1_1, 33, 0 },

  { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2.  */
  { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
  { "74kf", PROCESSOR_74KF2_1, 33, 0 },
  { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
  { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
  { "74kx", PROCESSOR_74KF1_1, 33, 0 },
  { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },

  /* MIPS64 processors.  */
  { "5kc", PROCESSOR_5KC, 64, 0 },
  { "5kf", PROCESSOR_5KF, 64, 0 },
  { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
  { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
  { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
  { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
};

/* Default costs.  If these are used for a processor we should look
   up the actual costs.  */
#define DEFAULT_COSTS COSTS_N_INSNS (6),  /* fp_add */       \
                      COSTS_N_INSNS (7),  /* fp_mult_sf */   \
                      COSTS_N_INSNS (8),  /* fp_mult_df */   \
                      COSTS_N_INSNS (23), /* fp_div_sf */    \
                      COSTS_N_INSNS (36), /* fp_div_df */    \
                      COSTS_N_INSNS (10), /* int_mult_si */  \
                      COSTS_N_INSNS (10), /* int_mult_di */  \
                      COSTS_N_INSNS (69), /* int_div_si */   \
                      COSTS_N_INSNS (69), /* int_div_di */   \
                                       2, /* branch_cost */  \
                                       4  /* memory_latency */

/* Floating-point costs for processors without an FPU.  Just assume that
   all floating-point libcalls are very expensive.  */
#define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */       \
                      COSTS_N_INSNS (256), /* fp_mult_sf */   \
                      COSTS_N_INSNS (256), /* fp_mult_df */   \
                      COSTS_N_INSNS (256), /* fp_div_sf */    \
                      COSTS_N_INSNS (256)  /* fp_div_df */

/* Costs to use when optimizing for size.  */
static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
  COSTS_N_INSNS (1),            /* fp_add */
  COSTS_N_INSNS (1),            /* fp_mult_sf */
  COSTS_N_INSNS (1),            /* fp_mult_df */
  COSTS_N_INSNS (1),            /* fp_div_sf */
  COSTS_N_INSNS (1),            /* fp_div_df */
  COSTS_N_INSNS (1),            /* int_mult_si */
  COSTS_N_INSNS (1),            /* int_mult_di */
  COSTS_N_INSNS (1),            /* int_div_si */
  COSTS_N_INSNS (1),            /* int_div_di */
                   2,           /* branch_cost */
                   4            /* memory_latency */
};

/* Costs to use when optimizing for speed, indexed by processor.  */
static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
  { /* R3000 */
    COSTS_N_INSNS (2),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (5),            /* fp_mult_df */
    COSTS_N_INSNS (12),           /* fp_div_sf */
    COSTS_N_INSNS (19),           /* fp_div_df */
    COSTS_N_INSNS (12),           /* int_mult_si */
    COSTS_N_INSNS (12),           /* int_mult_di */
    COSTS_N_INSNS (35),           /* int_div_si */
    COSTS_N_INSNS (35),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 4KC */
    SOFT_FP_COSTS,
    COSTS_N_INSNS (6),            /* int_mult_si */
    COSTS_N_INSNS (6),            /* int_mult_di */
    COSTS_N_INSNS (36),           /* int_div_si */
    COSTS_N_INSNS (36),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 4KP */
    SOFT_FP_COSTS,
    COSTS_N_INSNS (36),           /* int_mult_si */
    COSTS_N_INSNS (36),           /* int_mult_di */
    COSTS_N_INSNS (37),           /* int_div_si */
    COSTS_N_INSNS (37),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 5KC */
    SOFT_FP_COSTS,
    COSTS_N_INSNS (4),            /* int_mult_si */
    COSTS_N_INSNS (11),           /* int_mult_di */
    COSTS_N_INSNS (36),           /* int_div_si */
    COSTS_N_INSNS (68),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 5KF */
    COSTS_N_INSNS (4),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (5),            /* fp_mult_df */
    COSTS_N_INSNS (17),           /* fp_div_sf */
    COSTS_N_INSNS (32),           /* fp_div_df */
    COSTS_N_INSNS (4),            /* int_mult_si */
    COSTS_N_INSNS (11),           /* int_mult_di */
    COSTS_N_INSNS (36),           /* int_div_si */
    COSTS_N_INSNS (68),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 20KC */
    COSTS_N_INSNS (4),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (5),            /* fp_mult_df */
    COSTS_N_INSNS (17),           /* fp_div_sf */
    COSTS_N_INSNS (32),           /* fp_div_df */
    COSTS_N_INSNS (4),            /* int_mult_si */
    COSTS_N_INSNS (7),            /* int_mult_di */
    COSTS_N_INSNS (42),           /* int_div_si */
    COSTS_N_INSNS (72),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 24KC */
    SOFT_FP_COSTS,
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (5),            /* int_mult_di */
    COSTS_N_INSNS (41),           /* int_div_si */
    COSTS_N_INSNS (41),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 24KF2_1 */
    COSTS_N_INSNS (8),            /* fp_add */
    COSTS_N_INSNS (8),            /* fp_mult_sf */
    COSTS_N_INSNS (10),           /* fp_mult_df */
    COSTS_N_INSNS (34),           /* fp_div_sf */
    COSTS_N_INSNS (64),           /* fp_div_df */
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (5),            /* int_mult_di */
    COSTS_N_INSNS (41),           /* int_div_si */
    COSTS_N_INSNS (41),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 24KF1_1 */
    COSTS_N_INSNS (4),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (5),            /* fp_mult_df */
    COSTS_N_INSNS (17),           /* fp_div_sf */
    COSTS_N_INSNS (32),           /* fp_div_df */
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (5),            /* int_mult_di */
    COSTS_N_INSNS (41),           /* int_div_si */
    COSTS_N_INSNS (41),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 74KC */
    SOFT_FP_COSTS,
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (5),            /* int_mult_di */
    COSTS_N_INSNS (41),           /* int_div_si */
    COSTS_N_INSNS (41),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 74KF2_1 */
    COSTS_N_INSNS (8),            /* fp_add */
    COSTS_N_INSNS (8),            /* fp_mult_sf */
    COSTS_N_INSNS (10),           /* fp_mult_df */
    COSTS_N_INSNS (34),           /* fp_div_sf */
    COSTS_N_INSNS (64),           /* fp_div_df */
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (5),            /* int_mult_di */
    COSTS_N_INSNS (41),           /* int_div_si */
    COSTS_N_INSNS (41),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 74KF1_1 */
    COSTS_N_INSNS (4),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (5),            /* fp_mult_df */
    COSTS_N_INSNS (17),           /* fp_div_sf */
    COSTS_N_INSNS (32),           /* fp_div_df */
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (5),            /* int_mult_di */
    COSTS_N_INSNS (41),           /* int_div_si */
    COSTS_N_INSNS (41),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* 74KF3_2 */
    COSTS_N_INSNS (6),            /* fp_add */
    COSTS_N_INSNS (6),            /* fp_mult_sf */
    COSTS_N_INSNS (7),            /* fp_mult_df */
    COSTS_N_INSNS (25),           /* fp_div_sf */
    COSTS_N_INSNS (48),           /* fp_div_df */
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (5),            /* int_mult_di */
    COSTS_N_INSNS (41),           /* int_div_si */
    COSTS_N_INSNS (41),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* M4k */
    DEFAULT_COSTS
  },
  { /* R3900 */
    COSTS_N_INSNS (2),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (5),            /* fp_mult_df */
    COSTS_N_INSNS (12),           /* fp_div_sf */
    COSTS_N_INSNS (19),           /* fp_div_df */
    COSTS_N_INSNS (2),            /* int_mult_si */
    COSTS_N_INSNS (2),            /* int_mult_di */
    COSTS_N_INSNS (35),           /* int_div_si */
    COSTS_N_INSNS (35),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* R6000 */
    COSTS_N_INSNS (3),            /* fp_add */
    COSTS_N_INSNS (5),            /* fp_mult_sf */
    COSTS_N_INSNS (6),            /* fp_mult_df */
    COSTS_N_INSNS (15),           /* fp_div_sf */
    COSTS_N_INSNS (16),           /* fp_div_df */
    COSTS_N_INSNS (17),           /* int_mult_si */
    COSTS_N_INSNS (17),           /* int_mult_di */
    COSTS_N_INSNS (38),           /* int_div_si */
    COSTS_N_INSNS (38),           /* int_div_di */
                     2,           /* branch_cost */
                     6            /* memory_latency */
  },
  { /* R4000 */
     COSTS_N_INSNS (6),           /* fp_add */
     COSTS_N_INSNS (7),           /* fp_mult_sf */
     COSTS_N_INSNS (8),           /* fp_mult_df */
     COSTS_N_INSNS (23),          /* fp_div_sf */
     COSTS_N_INSNS (36),          /* fp_div_df */
     COSTS_N_INSNS (10),          /* int_mult_si */
     COSTS_N_INSNS (10),          /* int_mult_di */
     COSTS_N_INSNS (69),          /* int_div_si */
     COSTS_N_INSNS (69),          /* int_div_di */
                      2,          /* branch_cost */
                      6           /* memory_latency */
  },
  { /* R4100 */
    DEFAULT_COSTS
  },
  { /* R4111 */
    DEFAULT_COSTS
  },
  { /* R4120 */
    DEFAULT_COSTS
  },
  { /* R4130 */
    /* The only costs that appear to be updated here are
       integer multiplication.  */
    SOFT_FP_COSTS,
    COSTS_N_INSNS (4),            /* int_mult_si */
    COSTS_N_INSNS (6),            /* int_mult_di */
    COSTS_N_INSNS (69),           /* int_div_si */
    COSTS_N_INSNS (69),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* R4300 */
    DEFAULT_COSTS
  },
  { /* R4600 */
    DEFAULT_COSTS
  },
  { /* R4650 */
    DEFAULT_COSTS
  },
  { /* R5000 */
    COSTS_N_INSNS (6),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (5),            /* fp_mult_df */
    COSTS_N_INSNS (23),           /* fp_div_sf */
    COSTS_N_INSNS (36),           /* fp_div_df */
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (5),            /* int_mult_di */
    COSTS_N_INSNS (36),           /* int_div_si */
    COSTS_N_INSNS (36),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* R5400 */
    COSTS_N_INSNS (6),            /* fp_add */
    COSTS_N_INSNS (5),            /* fp_mult_sf */
    COSTS_N_INSNS (6),            /* fp_mult_df */
    COSTS_N_INSNS (30),           /* fp_div_sf */
    COSTS_N_INSNS (59),           /* fp_div_df */
    COSTS_N_INSNS (3),            /* int_mult_si */
    COSTS_N_INSNS (4),            /* int_mult_di */
    COSTS_N_INSNS (42),           /* int_div_si */
    COSTS_N_INSNS (74),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* R5500 */
    COSTS_N_INSNS (6),            /* fp_add */
    COSTS_N_INSNS (5),            /* fp_mult_sf */
    COSTS_N_INSNS (6),            /* fp_mult_df */
    COSTS_N_INSNS (30),           /* fp_div_sf */
    COSTS_N_INSNS (59),           /* fp_div_df */
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (9),            /* int_mult_di */
    COSTS_N_INSNS (42),           /* int_div_si */
    COSTS_N_INSNS (74),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* R7000 */
    /* The only costs that are changed here are
       integer multiplication.  */
    COSTS_N_INSNS (6),            /* fp_add */
    COSTS_N_INSNS (7),            /* fp_mult_sf */
    COSTS_N_INSNS (8),            /* fp_mult_df */
    COSTS_N_INSNS (23),           /* fp_div_sf */
    COSTS_N_INSNS (36),           /* fp_div_df */
    COSTS_N_INSNS (5),            /* int_mult_si */
    COSTS_N_INSNS (9),            /* int_mult_di */
    COSTS_N_INSNS (69),           /* int_div_si */
    COSTS_N_INSNS (69),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* R8000 */
    DEFAULT_COSTS
  },
  { /* R9000 */
    /* The only costs that are changed here are
       integer multiplication.  */
    COSTS_N_INSNS (6),            /* fp_add */
    COSTS_N_INSNS (7),            /* fp_mult_sf */
    COSTS_N_INSNS (8),            /* fp_mult_df */
    COSTS_N_INSNS (23),           /* fp_div_sf */
    COSTS_N_INSNS (36),           /* fp_div_df */
    COSTS_N_INSNS (3),            /* int_mult_si */
    COSTS_N_INSNS (8),            /* int_mult_di */
    COSTS_N_INSNS (69),           /* int_div_si */
    COSTS_N_INSNS (69),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* SB1 */
    /* These costs are the same as the SB-1A below.  */
    COSTS_N_INSNS (4),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (4),            /* fp_mult_df */
    COSTS_N_INSNS (24),           /* fp_div_sf */
    COSTS_N_INSNS (32),           /* fp_div_df */
    COSTS_N_INSNS (3),            /* int_mult_si */
    COSTS_N_INSNS (4),            /* int_mult_di */
    COSTS_N_INSNS (36),           /* int_div_si */
    COSTS_N_INSNS (68),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* SB1-A */
    /* These costs are the same as the SB-1 above.  */
    COSTS_N_INSNS (4),            /* fp_add */
    COSTS_N_INSNS (4),            /* fp_mult_sf */
    COSTS_N_INSNS (4),            /* fp_mult_df */
    COSTS_N_INSNS (24),           /* fp_div_sf */
    COSTS_N_INSNS (32),           /* fp_div_df */
    COSTS_N_INSNS (3),            /* int_mult_si */
    COSTS_N_INSNS (4),            /* int_mult_di */
    COSTS_N_INSNS (36),           /* int_div_si */
    COSTS_N_INSNS (68),           /* int_div_di */
                     1,           /* branch_cost */
                     4            /* memory_latency */
  },
  { /* SR71000 */
    DEFAULT_COSTS
  },
};
\f
/* This hash table keeps track of implicit "mips16" and "nomips16" attributes
   for -mflip_mips16.  It maps decl names onto a boolean mode setting.  */
struct mflip_mips16_entry GTY (()) {
  const char *name;
  bool mips16_p;
};
static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;

/* Hash table callbacks for mflip_mips16_htab.  */

static hashval_t
mflip_mips16_htab_hash (const void *entry)
{
  return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
}

static int
mflip_mips16_htab_eq (const void *entry, const void *name)
{
  return strcmp (((const struct mflip_mips16_entry *) entry)->name,
                 (const char *) name) == 0;
}

/* True if -mflip-mips16 should next add an attribute for the default MIPS16
   mode, false if it should next add an attribute for the opposite mode.  */
static GTY(()) bool mips16_flipper;

/* DECL is a function that needs a default "mips16" or "nomips16" attribute
   for -mflip-mips16.  Return true if it should use "mips16" and false if
   it should use "nomips16".  */

static bool
mflip_mips16_use_mips16_p (tree decl)
{
  struct mflip_mips16_entry *entry;
  const char *name;
  hashval_t hash;
  void **slot;

  /* Use the opposite of the command-line setting for anonymous decls.  */
  if (!DECL_NAME (decl))
    return !mips_base_mips16;

  if (!mflip_mips16_htab)
    mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
                                         mflip_mips16_htab_eq, NULL);

  name = IDENTIFIER_POINTER (DECL_NAME (decl));
  hash = htab_hash_string (name);
  slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
  entry = (struct mflip_mips16_entry *) *slot;
  if (!entry)
    {
      mips16_flipper = !mips16_flipper;
      entry = GGC_NEW (struct mflip_mips16_entry);
      entry->name = name;
      entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
      *slot = entry;
    }
  return entry->mips16_p;
}
\f
/* Predicates to test for presence of "near" and "far"/"long_call"
   attributes on the given TYPE.  */

static bool
mips_near_type_p (const_tree type)
{
  return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
}

static bool
mips_far_type_p (const_tree type)
{
  return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
          || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
}

/* Similar predicates for "mips16"/"nomips16" function attributes.  */

static bool
mips_mips16_decl_p (const_tree decl)
{
  return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
}

static bool
mips_nomips16_decl_p (const_tree decl)
{
  return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
}

/* Return true if function DECL is a MIPS16 function.  Return the ambient
   setting if DECL is null.  */

static bool
mips_use_mips16_mode_p (tree decl)
{
  if (decl)
    {
      /* Nested functions must use the same frame pointer as their
         parent and must therefore use the same ISA mode.  */
      tree parent = decl_function_context (decl);
      if (parent)
        decl = parent;
      if (mips_mips16_decl_p (decl))
        return true;
      if (mips_nomips16_decl_p (decl))
        return false;
    }
  return mips_base_mips16;
}

/* Implement TARGET_COMP_TYPE_ATTRIBUTES.  */

static int
mips_comp_type_attributes (const_tree type1, const_tree type2)
{
  /* Disallow mixed near/far attributes.  */
  if (mips_far_type_p (type1) && mips_near_type_p (type2))
    return 0;
  if (mips_near_type_p (type1) && mips_far_type_p (type2))
    return 0;
  return 1;
}

/* Implement TARGET_INSERT_ATTRIBUTES.  */

static void
mips_insert_attributes (tree decl, tree *attributes)
{
  const char *name;
  bool mips16_p, nomips16_p;

  /* Check for "mips16" and "nomips16" attributes.  */
  mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
  nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
  if (TREE_CODE (decl) != FUNCTION_DECL)
    {
      if (mips16_p)
        error ("%qs attribute only applies to functions", "mips16");
      if (nomips16_p)
        error ("%qs attribute only applies to functions", "nomips16");
    }
  else
    {
      mips16_p |= mips_mips16_decl_p (decl);
      nomips16_p |= mips_nomips16_decl_p (decl);
      if (mips16_p || nomips16_p)
        {
          /* DECL cannot be simultaneously "mips16" and "nomips16".  */
          if (mips16_p && nomips16_p)
            error ("%qs cannot have both %<mips16%> and "
                   "%<nomips16%> attributes",
                   IDENTIFIER_POINTER (DECL_NAME (decl)));
        }
      else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
        {
          /* Implement -mflip-mips16.  If DECL has neither a "nomips16" nor a
             "mips16" attribute, arbitrarily pick one.  We must pick the same
             setting for duplicate declarations of a function.  */
          name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
          *attributes = tree_cons (get_identifier (name), NULL, *attributes);
        }
    }
}

/* Implement TARGET_MERGE_DECL_ATTRIBUTES.  */

static tree
mips_merge_decl_attributes (tree olddecl, tree newdecl)
{
  /* The decls' "mips16" and "nomips16" attributes must match exactly.  */
  if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
    error ("%qs redeclared with conflicting %qs attributes",
           IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
  if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
    error ("%qs redeclared with conflicting %qs attributes",
           IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");

  return merge_attributes (DECL_ATTRIBUTES (olddecl),
                           DECL_ATTRIBUTES (newdecl));
}
\f
/* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
   and *OFFSET_PTR.  Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise.  */

static void
mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
{
  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
    {
      *base_ptr = XEXP (x, 0);
      *offset_ptr = INTVAL (XEXP (x, 1));
    }
  else
    {
      *base_ptr = x;
      *offset_ptr = 0;
    }
}
\f
static unsigned int mips_build_integer (struct mips_integer_op *,
                                        unsigned HOST_WIDE_INT);

/* A subroutine of mips_build_integer, with the same interface.
   Assume that the final action in the sequence should be a left shift.  */

static unsigned int
mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
{
  unsigned int i, shift;

  /* Shift VALUE right until its lowest bit is set.  Shift arithmetically
     since signed numbers are easier to load than unsigned ones.  */
  shift = 0;
  while ((value & 1) == 0)
    value /= 2, shift++;

  i = mips_build_integer (codes, value);
  codes[i].code = ASHIFT;
  codes[i].value = shift;
  return i + 1;
}

/* As for mips_build_shift, but assume that the final action will be
   an IOR or PLUS operation.  */

static unsigned int
mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
{
  unsigned HOST_WIDE_INT high;
  unsigned int i;

  high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
  if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
    {
      /* The constant is too complex to load with a simple LUI/ORI pair,
         so we want to give the recursive call as many trailing zeros as
         possible.  In this case, we know bit 16 is set and that the
         low 16 bits form a negative number.  If we subtract that number
         from VALUE, we will clear at least the lowest 17 bits, maybe more.  */
      i = mips_build_integer (codes, CONST_HIGH_PART (value));
      codes[i].code = PLUS;
      codes[i].value = CONST_LOW_PART (value);
    }
  else
    {
      /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
         bits gives a value with at least 17 trailing zeros.  */
      i = mips_build_integer (codes, high);
      codes[i].code = IOR;
      codes[i].value = value & 0xffff;
    }
  return i + 1;
}

/* Fill CODES with a sequence of rtl operations to load VALUE.
   Return the number of operations needed.  */

static unsigned int
mips_build_integer (struct mips_integer_op *codes,
                    unsigned HOST_WIDE_INT value)
{
  if (SMALL_OPERAND (value)
      || SMALL_OPERAND_UNSIGNED (value)
      || LUI_OPERAND (value))
    {
      /* The value can be loaded with a single instruction.  */
      codes[0].code = UNKNOWN;
      codes[0].value = value;
      return 1;
    }
  else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
    {
      /* Either the constant is a simple LUI/ORI combination or its
         lowest bit is set.  We don't want to shift in this case.  */
      return mips_build_lower (codes, value);
    }
  else if ((value & 0xffff) == 0)
    {
      /* The constant will need at least three actions.  The lowest
         16 bits are clear, so the final action will be a shift.  */
      return mips_build_shift (codes, value);
    }
  else
    {
      /* The final action could be a shift, add or inclusive OR.
         Rather than use a complex condition to select the best
         approach, try both mips_build_shift and mips_build_lower
         and pick the one that gives the shortest sequence.
         Note that this case is only used once per constant.  */
      struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
      unsigned int cost, alt_cost;

      cost = mips_build_shift (codes, value);
      alt_cost = mips_build_lower (alt_codes, value);
      if (alt_cost < cost)
        {
          memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
          cost = alt_cost;
        }
      return cost;
    }
}
\f
/* Return true if X is a thread-local symbol.  */

static bool
mips_tls_symbol_p (rtx x)
{
  return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
}

/* Return true if SYMBOL_REF X is associated with a global symbol
   (in the STB_GLOBAL sense).  */

static bool
mips_global_symbol_p (const_rtx x)
{
  const_tree decl = SYMBOL_REF_DECL (x);

  if (!decl)
    return !SYMBOL_REF_LOCAL_P (x);

  /* Weakref symbols are not TREE_PUBLIC, but their targets are global
     or weak symbols.  Relocations in the object file will be against
     the target symbol, so it's that symbol's binding that matters here.  */
  return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
}

/* Return true if SYMBOL_REF X binds locally.  */

static bool
mips_symbol_binds_local_p (const_rtx x)
{
  return (SYMBOL_REF_DECL (x)
          ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
          : SYMBOL_REF_LOCAL_P (x));
}

/* Return true if rtx constants of mode MODE should be put into a small
   data section.  */

static bool
mips_rtx_constant_in_small_data_p (enum machine_mode mode)
{
  return (!TARGET_EMBEDDED_DATA
          && TARGET_LOCAL_SDATA
          && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
}

/* Return true if X should not be moved directly into register $25.
   We need this because many versions of GAS will treat "la $25,foo" as
   part of a call sequence and so allow a global "foo" to be lazily bound.  */

bool
mips_dangerous_for_la25_p (rtx x)
{
  return (!TARGET_EXPLICIT_RELOCS
          && TARGET_USE_GOT
          && GET_CODE (x) == SYMBOL_REF
          && mips_global_symbol_p (x));
}

/* Return the method that should be used to access SYMBOL_REF or
   LABEL_REF X in context CONTEXT.  */

static enum mips_symbol_type
mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
{
  if (TARGET_RTP_PIC)
    return SYMBOL_GOT_DISP;

  if (GET_CODE (x) == LABEL_REF)
    {
      /* LABEL_REFs are used for jump tables as well as text labels.
         Only return SYMBOL_PC_RELATIVE if we know the label is in
         the text section.  */
      if (TARGET_MIPS16_SHORT_JUMP_TABLES)
        return SYMBOL_PC_RELATIVE;

      if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
        return SYMBOL_GOT_PAGE_OFST;

      return SYMBOL_ABSOLUTE;
    }

  gcc_assert (GET_CODE (x) == SYMBOL_REF);

  if (SYMBOL_REF_TLS_MODEL (x))
    return SYMBOL_TLS;

  if (CONSTANT_POOL_ADDRESS_P (x))
    {
      if (TARGET_MIPS16_TEXT_LOADS)
        return SYMBOL_PC_RELATIVE;

      if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
        return SYMBOL_PC_RELATIVE;

      if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
        return SYMBOL_GP_RELATIVE;
    }

  /* Do not use small-data accesses for weak symbols; they may end up
     being zero.  */
  if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
    return SYMBOL_GP_RELATIVE;

  /* Don't use GOT accesses for locally-binding symbols when -mno-shared
     is in effect.  */
  if (TARGET_ABICALLS
      && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
    {
      /* There are three cases to consider:

            - o32 PIC (either with or without explicit relocs)
            - n32/n64 PIC without explicit relocs
            - n32/n64 PIC with explicit relocs

         In the first case, both local and global accesses will use an
         R_MIPS_GOT16 relocation.  We must correctly predict which of
         the two semantics (local or global) the assembler and linker
         will apply.  The choice depends on the symbol's binding rather
         than its visibility.

         In the second case, the assembler will not use R_MIPS_GOT16
         relocations, but it chooses between local and global accesses
         in the same way as for o32 PIC.

         In the third case we have more freedom since both forms of
         access will work for any kind of symbol.  However, there seems
         little point in doing things differently.  */
      if (mips_global_symbol_p (x))
        return SYMBOL_GOT_DISP;

      return SYMBOL_GOT_PAGE_OFST;
    }

  if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
    return SYMBOL_FORCE_TO_MEM;

  return SYMBOL_ABSOLUTE;
}

/* Classify the base of symbolic expression X, given that X appears in
   context CONTEXT.  */

static enum mips_symbol_type
mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
{
  rtx offset;

  split_const (x, &x, &offset);
  if (UNSPEC_ADDRESS_P (x))
    return UNSPEC_ADDRESS_TYPE (x);

  return mips_classify_symbol (x, context);
}

/* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
   is the alignment in bytes of SYMBOL_REF X.  */

static bool
mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
{
  HOST_WIDE_INT align;

  align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
  return IN_RANGE (offset, 0, align - 1);
}

/* Return true if X is a symbolic constant that can be used in context
   CONTEXT.  If it is, store the type of the symbol in *SYMBOL_TYPE.  */

bool
mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
                          enum mips_symbol_type *symbol_type)
{
  rtx offset;

  split_const (x, &x, &offset);
  if (UNSPEC_ADDRESS_P (x))
    {
      *symbol_type = UNSPEC_ADDRESS_TYPE (x);
      x = UNSPEC_ADDRESS (x);
    }
  else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
    {
      *symbol_type = mips_classify_symbol (x, context);
      if (*symbol_type == SYMBOL_TLS)
        return false;
    }
  else
    return false;

  if (offset == const0_rtx)
    return true;

  /* Check whether a nonzero offset is valid for the underlying
     relocations.  */
  switch (*symbol_type)
    {
    case SYMBOL_ABSOLUTE:
    case SYMBOL_FORCE_TO_MEM:
    case SYMBOL_32_HIGH:
    case SYMBOL_64_HIGH:
    case SYMBOL_64_MID:
    case SYMBOL_64_LOW:
      /* If the target has 64-bit pointers and the object file only
         supports 32-bit symbols, the values of those symbols will be
         sign-extended.  In this case we can't allow an arbitrary offset
         in case the 32-bit value X + OFFSET has a different sign from X.  */
      if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
        return offset_within_block_p (x, INTVAL (offset));

      /* In other cases the relocations can handle any offset.  */
      return true;

    case SYMBOL_PC_RELATIVE:
      /* Allow constant pool references to be converted to LABEL+CONSTANT.
         In this case, we no longer have access to the underlying constant,
         but the original symbol-based access was known to be valid.  */
      if (GET_CODE (x) == LABEL_REF)
        return true;

      /* Fall through.  */

    case SYMBOL_GP_RELATIVE:
      /* Make sure that the offset refers to something within the
         same object block.  This should guarantee that the final
         PC- or GP-relative offset is within the 16-bit limit.  */
      return offset_within_block_p (x, INTVAL (offset));

    case SYMBOL_GOT_PAGE_OFST:
    case SYMBOL_GOTOFF_PAGE:
      /* If the symbol is global, the GOT entry will contain the symbol's
         address, and we will apply a 16-bit offset after loading it.
         If the symbol is local, the linker should provide enough local
         GOT entries for a 16-bit offset, but larger offsets may lead
         to GOT overflow.  */
      return SMALL_INT (offset);

    case SYMBOL_TPREL:
    case SYMBOL_DTPREL:
      /* There is no carry between the HI and LO REL relocations, so the
         offset is only valid if we know it won't lead to such a carry.  */
      return mips_offset_within_alignment_p (x, INTVAL (offset));

    case SYMBOL_GOT_DISP:
    case SYMBOL_GOTOFF_DISP:
    case SYMBOL_GOTOFF_CALL:
    case SYMBOL_GOTOFF_LOADGP:
    case SYMBOL_TLSGD:
    case SYMBOL_TLSLDM:
    case SYMBOL_GOTTPREL:
    case SYMBOL_TLS:
    case SYMBOL_HALF:
      return false;
    }
  gcc_unreachable ();
}
\f
/* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
   single instruction.  We rely on the fact that, in the worst case,
   all instructions involved in a MIPS16 address calculation are usually
   extended ones.  */

static int
mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
{
  switch (type)
    {
    case SYMBOL_ABSOLUTE:
      /* When using 64-bit symbols, we need 5 preparatory instructions,
         such as:

             lui     $at,%highest(symbol)
             daddiu  $at,$at,%higher(symbol)
             dsll    $at,$at,16
             daddiu  $at,$at,%hi(symbol)
             dsll    $at,$at,16

         The final address is then $at + %lo(symbol).  With 32-bit
         symbols we just need a preparatory LUI for normal mode and
         a preparatory LI and SLL for MIPS16.  */
      return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;

    case SYMBOL_GP_RELATIVE:
      /* Treat GP-relative accesses as taking a single instruction on
         MIPS16 too; the copy of $gp can often be shared.  */
      return 1;

    case SYMBOL_PC_RELATIVE:
      /* PC-relative constants can be only be used with ADDIUPC,
         DADDIUPC, LWPC and LDPC.  */
      if (mode == MAX_MACHINE_MODE
          || GET_MODE_SIZE (mode) == 4
          || GET_MODE_SIZE (mode) == 8)
        return 1;

      /* The constant must be loaded using ADDIUPC or DADDIUPC first.  */
      return 0;

    case SYMBOL_FORCE_TO_MEM:
      /* LEAs will be converted into constant-pool references by
         mips_reorg.  */
      if (mode == MAX_MACHINE_MODE)
        return 1;

      /* The constant must be loaded and then dereferenced.  */
      return 0;

    case SYMBOL_GOT_DISP:
      /* The constant will have to be loaded from the GOT before it
         is used in an address.  */
      if (mode != MAX_MACHINE_MODE)
        return 0;

      /* Fall through.  */

    case SYMBOL_GOT_PAGE_OFST:
      /* Unless -funit-at-a-time is in effect, we can't be sure whether the
         local/global classification is accurate.  The worst cases are:

         (1) For local symbols when generating o32 or o64 code.  The assembler
             will use:

                 lw           $at,%got(symbol)
                 nop

             ...and the final address will be $at + %lo(symbol).

         (2) For global symbols when -mxgot.  The assembler will use:

                 lui     $at,%got_hi(symbol)
                 (d)addu $at,$at,$gp

             ...and the final address will be $at + %got_lo(symbol).  */
      return 3;

    case SYMBOL_GOTOFF_PAGE:
    case SYMBOL_GOTOFF_DISP:
    case SYMBOL_GOTOFF_CALL:
    case SYMBOL_GOTOFF_LOADGP:
    case SYMBOL_32_HIGH:
    case SYMBOL_64_HIGH:
    case SYMBOL_64_MID:
    case SYMBOL_64_LOW:
    case SYMBOL_TLSGD:
    case SYMBOL_TLSLDM:
    case SYMBOL_DTPREL:
    case SYMBOL_GOTTPREL:
    case SYMBOL_TPREL:
    case SYMBOL_HALF:
      /* A 16-bit constant formed by a single relocation, or a 32-bit
         constant formed from a high 16-bit relocation and a low 16-bit
         relocation.  Use mips_split_p to determine which.  32-bit
         constants need an "lui; addiu" sequence for normal mode and
         an "li; sll; addiu" sequence for MIPS16 mode.  */
      return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;

    case SYMBOL_TLS:
      /* We don't treat a bare TLS symbol as a constant.  */
      return 0;
    }
  gcc_unreachable ();
}

/* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
   to load symbols of type TYPE into a register.  Return 0 if the given
   type of symbol cannot be used as an immediate operand.

   Otherwise, return the number of instructions needed to load or store
   values of mode MODE to or from addresses of type TYPE.  Return 0 if
   the given type of symbol is not valid in addresses.

   In both cases, treat extended MIPS16 instructions as two instructions.  */

static int
mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
{
  return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
}
\f
/* A for_each_rtx callback.  Stop the search if *X references a
   thread-local symbol.  */

static int
mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
{
  return mips_tls_symbol_p (*x);
}

/* Implement TARGET_CANNOT_FORCE_CONST_MEM.  */

static bool
mips_cannot_force_const_mem (rtx x)
{
  rtx base, offset;

  if (!TARGET_MIPS16)
    {
      /* As an optimization, reject constants that mips_legitimize_move
         can expand inline.

         Suppose we have a multi-instruction sequence that loads constant C
         into register R.  If R does not get allocated a hard register, and
         R is used in an operand that allows both registers and memory
         references, reload will consider forcing C into memory and using
         one of the instruction's memory alternatives.  Returning false
         here will force it to use an input reload instead.  */
      if (GET_CODE (x) == CONST_INT)
        return true;

      split_const (x, &base, &offset);
      if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
        return true;
    }

  /* TLS symbols must be computed by mips_legitimize_move.  */
  if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
    return true;

  return false;
}

/* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P.  We can't use blocks for
   constants when we're using a per-function constant pool.  */

static bool
mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
                                const_rtx x ATTRIBUTE_UNUSED)
{
  return !TARGET_MIPS16_PCREL_LOADS;
}
\f
/* Return true if register REGNO is a valid base register for mode MODE.
   STRICT_P is true if REG_OK_STRICT is in effect.  */

int
mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
                               bool strict_p)
{
  if (!HARD_REGISTER_NUM_P (regno))
    {
      if (!strict_p)
        return true;
      regno = reg_renumber[regno];
    }

  /* These fake registers will be eliminated to either the stack or
     hard frame pointer, both of which are usually valid base registers.
     Reload deals with the cases where the eliminated form isn't valid.  */
  if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
    return true;

  /* In MIPS16 mode, the stack pointer can only address word and doubleword
     values, nothing smaller.  There are two problems here:

       (a) Instantiating virtual registers can introduce new uses of the
           stack pointer.  If these virtual registers are valid addresses,
           the stack pointer should be too.

       (b) Most uses of the stack pointer are not made explicit until
           FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
           We don't know until that stage whether we'll be eliminating to the
           stack pointer (which needs the restriction) or the hard frame
           pointer (which doesn't).

     All in all, it seems more consistent to only enforce this restriction
     during and after reload.  */
  if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
    return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;

  return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
}

/* Return true if X is a valid base register for mode MODE.
   STRICT_P is true if REG_OK_STRICT is in effect.  */

static bool
mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
{
  if (!strict_p && GET_CODE (x) == SUBREG)
    x = SUBREG_REG (x);

  return (REG_P (x)
          && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
}

/* Return true if X is a valid address for machine mode MODE.  If it is,
   fill in INFO appropriately.  STRICT_P is true if REG_OK_STRICT is in
   effect.  */

static bool
mips_classify_address (struct mips_address_info *info, rtx x,
                       enum machine_mode mode, bool strict_p)
{
  switch (GET_CODE (x))
    {
    case REG:
    case SUBREG:
      info->type = ADDRESS_REG;
      info->reg = x;
      info->offset = const0_rtx;
      return mips_valid_base_register_p (info->reg, mode, strict_p);

    case PLUS:
      info->type = ADDRESS_REG;
      info->reg = XEXP (x, 0);
      info->offset = XEXP (x, 1);
      return (mips_valid_base_register_p (info->reg, mode, strict_p)
              && const_arith_operand (info->offset, VOIDmode));

    case LO_SUM:
      info->type = ADDRESS_LO_SUM;
      info->reg = XEXP (x, 0);
      info->offset = XEXP (x, 1);
      /* We have to trust the creator of the LO_SUM to do something vaguely
         sane.  Target-independent code that creates a LO_SUM should also
         create and verify the matching HIGH.  Target-independent code that
         adds an offset to a LO_SUM must prove that the offset will not
         induce a carry.  Failure to do either of these things would be
         a bug, and we are not required to check for it here.  The MIPS
         backend itself should only create LO_SUMs for valid symbolic
         constants, with the high part being either a HIGH or a copy
         of _gp. */
      info->symbol_type
        = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
      return (mips_valid_base_register_p (info->reg, mode, strict_p)
              && mips_symbol_insns (info->symbol_type, mode) > 0
              && mips_lo_relocs[info->symbol_type] != 0);

    case CONST_INT:
      /* Small-integer addresses don't occur very often, but they
         are legitimate if $0 is a valid base register.  */
      info->type = ADDRESS_CONST_INT;
      return !TARGET_MIPS16 && SMALL_INT (x);

    case CONST:
    case LABEL_REF:
    case SYMBOL_REF:
      info->type = ADDRESS_SYMBOLIC;
      return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
                                        &info->symbol_type)
              && mips_symbol_insns (info->symbol_type, mode) > 0
              && !mips_split_p[info->symbol_type]);

    default:
      return false;
    }
}

/* Return true if X is a legitimate address for a memory operand of mode
   MODE.  STRICT_P is true if REG_OK_STRICT is in effect.  */

bool
mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
{
  struct mips_address_info addr;

  return mips_classify_address (&addr, x, mode, strict_p);
}

/* Return true if X is a legitimate $sp-based address for mode MDOE.  */

bool
mips_stack_address_p (rtx x, enum machine_mode mode)
{
  struct mips_address_info addr;

  return (mips_classify_address (&addr, x, mode, false)
          && addr.type == ADDRESS_REG
          && addr.reg == stack_pointer_rtx);
}

/* Return true if ADDR matches the pattern for the LWXS load scaled indexed
   address instruction.  Note that such addresses are not considered
   legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
   is so restricted.  */

static bool
mips_lwxs_address_p (rtx addr)
{
  if (ISA_HAS_LWXS
      && GET_CODE (addr) == PLUS
      && REG_P (XEXP (addr, 1)))
    {
      rtx offset = XEXP (addr, 0);
      if (GET_CODE (offset) == MULT
          && REG_P (XEXP (offset, 0))
          && GET_CODE (XEXP (offset, 1)) == CONST_INT
          && INTVAL (XEXP (offset, 1)) == 4)
        return true;
    }
  return false;
}
\f
/* Return true if a value at OFFSET bytes from base register BASE can be
   accessed using an unextended MIPS16 instruction.  MODE is the mode of
   the value.

   Usually the offset in an unextended instruction is a 5-bit field.
   The offset is unsigned and shifted left once for LH and SH, twice
   for LW and SW, and so on.  An exception is LWSP and SWSP, which have
   an 8-bit immediate field that's shifted left twice.  */

static bool
mips16_unextended_reference_p (enum machine_mode mode, rtx base,
                               unsigned HOST_WIDE_INT offset)
{
  if (offset % GET_MODE_SIZE (mode) == 0)
    {
      if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
        return offset < 256U * GET_MODE_SIZE (mode);
      return offset < 32U * GET_MODE_SIZE (mode);
    }
  return false;
}

/* Return the number of instructions needed to load or store a value
   of mode MODE at address X.  Return 0 if X isn't valid for MODE.
   Assume that multiword moves may need to be split into word moves
   if MIGHT_SPLIT_P, otherwise assume that a single load or store is
   enough.

   For MIPS16 code, count extended instructions as two instructions.  */

int
mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
{
  struct mips_address_info addr;
  int factor;

  /* BLKmode is used for single unaligned loads and stores and should
     not count as a multiword mode.  (GET_MODE_SIZE (BLKmode) is pretty
     meaningless, so we have to single it out as a special case one way
     or the other.)  */
  if (mode != BLKmode && might_split_p)
    factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
  else
    factor = 1;

  if (mips_classify_address (&addr, x, mode, false))
    switch (addr.type)
      {
      case ADDRESS_REG:
        if (TARGET_MIPS16
            && !mips16_unextended_reference_p (mode, addr.reg,
                                               UINTVAL (addr.offset)))
          return factor * 2;
        return factor;

      case ADDRESS_LO_SUM:
        return TARGET_MIPS16 ? factor * 2 : factor;

      case ADDRESS_CONST_INT:
        return factor;

      case ADDRESS_SYMBOLIC:
        return factor * mips_symbol_insns (addr.symbol_type, mode);
      }
  return 0;
}

/* Return the number of instructions needed to load constant X.
   Return 0 if X isn't a valid constant.  */

int
mips_const_insns (rtx x)
{
  struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
  enum mips_symbol_type symbol_type;
  rtx offset;

  switch (GET_CODE (x))
    {
    case HIGH:
      if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
                                     &symbol_type)
          || !mips_split_p[symbol_type])
        return 0;

      /* This is simply an LUI for normal mode.  It is an extended
         LI followed by an extended SLL for MIPS16.  */
      return TARGET_MIPS16 ? 4 : 1;

    case CONST_INT:
      if (TARGET_MIPS16)
        /* Unsigned 8-bit constants can be loaded using an unextended
           LI instruction.  Unsigned 16-bit constants can be loaded
           using an extended LI.  Negative constants must be loaded
           using LI and then negated.  */
        return (IN_RANGE (INTVAL (x), 0, 255) ? 1
                : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
                : IN_RANGE (-INTVAL (x), 0, 255) ? 2
                : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
                : 0);

      return mips_build_integer (codes, INTVAL (x));

    case CONST_DOUBLE:
    case CONST_VECTOR:
      /* Allow zeros for normal mode, where we can use $0.  */
      return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;

    case CONST:
      if (CONST_GP_P (x))
        return 1;

      /* See if we can refer to X directly.  */
      if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
        return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);

      /* Otherwise try splitting the constant into a base and offset.
         16-bit offsets can be added using an extra ADDIU.  Larger offsets
         must be calculated separately and then added to the base.  */
      split_const (x, &x, &offset);
      if (offset != 0)
        {
          int n = mips_const_insns (x);
          if (n != 0)
            {
              if (SMALL_INT (offset))
                return n + 1;
              else
                return n + 1 + mips_build_integer (codes, INTVAL (offset));
            }
        }
      return 0;

    case SYMBOL_REF:
    case LABEL_REF:
      return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
                                MAX_MACHINE_MODE);

    default:
      return 0;
    }
}

/* Return the number of instructions needed to implement INSN,
   given that it loads from or stores to MEM.  Count extended
   MIPS16 instructions as two instructions.  */

int
mips_load_store_insns (rtx mem, rtx insn)
{
  enum machine_mode mode;
  bool might_split_p;
  rtx set;

  gcc_assert (MEM_P (mem));
  mode = GET_MODE (mem);

  /* Try to prove that INSN does not need to be split.  */
  might_split_p = true;
  if (GET_MODE_BITSIZE (mode) == 64)
    {
      set = single_set (insn);
      if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
        might_split_p = false;
    }

  return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
}

/* Return the number of instructions needed for an integer division.  */

int
mips_idiv_insns (void)
{
  int count;

  count = 1;
  if (TARGET_CHECK_ZERO_DIV)
    {
      if (GENERATE_DIVIDE_TRAPS)
        count++;
      else
        count += 2;
    }

  if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
    count++;
  return count;
}
\f
/* Emit a move from SRC to DEST.  Assume that the move expanders can
   handle all moves if !can_create_pseudo_p ().  The distinction is
   important because, unlike emit_move_insn, the move expanders know
   how to force Pmode objects into the constant pool even when the
   constant pool address is not itself legitimate.  */

rtx
mips_emit_move (rtx dest, rtx src)
{
  return (can_create_pseudo_p ()
          ? emit_move_insn (dest, src)
          : emit_move_insn_1 (dest, src));
}

/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)).  */

static void
mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
{
  emit_insn (gen_rtx_SET (VOIDmode, target,
                          gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
}

/* Copy VALUE to a register and return that register.  If new pseudos
   are allowed, copy it into a new register, otherwise use DEST.  */

static rtx
mips_force_temporary (rtx dest, rtx value)
{
  if (can_create_pseudo_p ())
    return force_reg (Pmode, value);
  else
    {
      mips_emit_move (dest, value);
      return dest;
    }
}

/* Emit a call sequence with call pattern PATTERN and return the call
   instruction itself (which is not necessarily the last instruction
   emitted).  LAZY_P is true if the call address is lazily-bound.  */

static rtx
mips_emit_call_insn (rtx pattern, bool lazy_p)
{
  rtx insn;

  insn = emit_call_insn (pattern);

  /* Lazy-binding stubs require $gp to be valid on entry.  */
  if (lazy_p)
    use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);

  if (TARGET_USE_GOT)
    {
      /* See the comment above load_call<mode> for details.  */
      use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
               gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
      emit_insn (gen_update_got_version ());
    }
  return insn;
}
\f
/* Return an instruction that copies $gp into register REG.  We want
   GCC to treat the register's value as constant, so that its value
   can be rematerialized on demand.  */

static rtx
gen_load_const_gp (rtx reg)
{
  return (Pmode == SImode
          ? gen_load_const_gp_si (reg)
          : gen_load_const_gp_di (reg));
}

/* Return a pseudo register that contains the value of $gp throughout
   the current function.  Such registers are needed by MIPS16 functions,
   for which $gp itself is not a valid base register or addition operand.  */

static rtx
mips16_gp_pseudo_reg (void)
{
  if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
    cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);

  /* Don't emit an instruction to initialize the pseudo register if
     we are being called from the tree optimizers' cost-calculation
     routines.  */
  if (!cfun->machine->initialized_mips16_gp_pseudo_p
      && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
    {
      rtx insn, scan, after;

      insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);

      push_topmost_sequence ();
      /* We need to emit the initialization after the FUNCTION_BEG
         note, so that it will be integrated.  */
      after = get_insns ();
      for (scan = after; scan != NULL_RTX; scan = NEXT_INSN (scan))
        if (NOTE_P (scan) && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
          {
            after = scan;
            break;
          }
      insn = emit_insn_after (insn, after);
      pop_topmost_sequence ();

      cfun->machine->initialized_mips16_gp_pseudo_p = true;
    }

  return cfun->machine->mips16_gp_pseudo_rtx;
}

/* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
   it appears in a MEM of that mode.  Return true if ADDR is a legitimate
   constant in that context and can be split into a high part and a LO_SUM.
   If so, and if LO_SUM_OUT is nonnull, emit the high part and return
   the LO_SUM in *LO_SUM_OUT.  Leave *LO_SUM_OUT unchanged otherwise.

   TEMP is as for mips_force_temporary and is used to load the high
   part into a register.  */

bool
mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *lo_sum_out)
{
  enum mips_symbol_context context;
  enum mips_symbol_type symbol_type;
  rtx high;

  context = (mode == MAX_MACHINE_MODE
             ? SYMBOL_CONTEXT_LEA
             : SYMBOL_CONTEXT_MEM);
  if (!mips_symbolic_constant_p (addr, context, &symbol_type)
      || mips_symbol_insns (symbol_type, mode) == 0
      || !mips_split_p[symbol_type])
    return false;

  if (lo_sum_out)
    {
      if (symbol_type == SYMBOL_GP_RELATIVE)
        {
          if (!can_create_pseudo_p ())
            {
              emit_insn (gen_load_const_gp (temp));
              high = temp;
            }
          else
            high = mips16_gp_pseudo_reg ();
        }
      else
        {
          high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
          high = mips_force_temporary (temp, high);
        }
      *lo_sum_out = gen_rtx_LO_SUM (Pmode, high, addr);
    }
  return true;
}

/* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
   then add CONST_INT OFFSET to the result.  */

static rtx
mips_unspec_address_offset (rtx base, rtx offset,
                            enum mips_symbol_type symbol_type)
{
  base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
                         UNSPEC_ADDRESS_FIRST + symbol_type);
  if (offset != const0_rtx)
    base = gen_rtx_PLUS (Pmode, base, offset);
  return gen_rtx_CONST (Pmode, base);
}

/* Return an UNSPEC address with underlying address ADDRESS and symbol
   type SYMBOL_TYPE.  */

rtx
mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
{
  rtx base, offset;

  split_const (address, &base, &offset);
  return mips_unspec_address_offset (base, offset, symbol_type);
}

/* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
   high part to BASE and return the result.  Just return BASE otherwise.
   TEMP is as for mips_force_temporary.

   The returned expression can be used as the first operand to a LO_SUM.  */

static rtx
mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
                         enum mips_symbol_type symbol_type)
{
  if (mips_split_p[symbol_type])
    {
      addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
      addr = mips_force_temporary (temp, addr);
      base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
    }
  return base;
}

/* Return a legitimate address for REG + OFFSET.  TEMP is as for
   mips_force_temporary; it is only needed when OFFSET is not a
   SMALL_OPERAND.  */

static rtx
mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
{
  if (!SMALL_OPERAND (offset))
    {
      rtx high;

      if (TARGET_MIPS16)
        {
          /* Load the full offset into a register so that we can use
             an unextended instruction for the address itself.  */
          high = GEN_INT (offset);
          offset = 0;
        }
      else
        {
          /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.  */
          high = GEN_INT (CONST_HIGH_PART (offset));
          offset = CONST_LOW_PART (offset);
        }
      high = mips_force_temporary (temp, high);
      reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
    }
  return plus_constant (reg, offset);
}
\f
/* The __tls_get_attr symbol.  */
static GTY(()) rtx mips_tls_symbol;

/* Return an instruction sequence that calls __tls_get_addr.  SYM is
   the TLS symbol we are referencing and TYPE is the symbol type to use
   (either global dynamic or local dynamic).  V0 is an RTX for the
   return value location.  */

static rtx
mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
{
  rtx insn, loc, a0;

  a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);

  if (!mips_tls_symbol)
    mips_tls_symbol = init_one_libfunc ("__tls_get_addr");

  loc = mips_unspec_address (sym, type);

  start_sequence ();

  emit_insn (gen_rtx_SET (Pmode, a0,
                          gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
  insn = mips_expand_call (v0, mips_tls_symbol, const0_rtx, const0_rtx, false);
  CONST_OR_PURE_CALL_P (insn) = 1;
  use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
  insn = get_insns ();

  end_sequence ();

  return insn;
}

/* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
   its address.  The return value will be both a valid address and a valid
   SET_SRC (either a REG or a LO_SUM).  */

static rtx
mips_legitimize_tls_address (rtx loc)
{
  rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
  enum tls_model model;

  if (TARGET_MIPS16)
    {
      sorry ("MIPS16 TLS");
      return gen_reg_rtx (Pmode);
    }

  model = SYMBOL_REF_TLS_MODEL (loc);
  /* Only TARGET_ABICALLS code can have more than one module; other
     code must be be static and should not use a GOT.  All TLS models
     reduce to local exec in this situation.  */
  if (!TARGET_ABICALLS)
    model = TLS_MODEL_LOCAL_EXEC;

  switch (model)
    {
    case TLS_MODEL_GLOBAL_DYNAMIC:
      v0 = gen_rtx_REG (Pmode, GP_RETURN);
      insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
      dest = gen_reg_rtx (Pmode);
      emit_libcall_block (insn, dest, v0, loc);
      break;

    case TLS_MODEL_LOCAL_DYNAMIC:
      v0 = gen_rtx_REG (Pmode, GP_RETURN);
      insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
      tmp1 = gen_reg_rtx (Pmode);

      /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
         share the LDM result with other LD model accesses.  */
      eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
                            UNSPEC_TLS_LDM);
      emit_libcall_block (insn, tmp1, v0, eqv);

      tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
      dest = gen_rtx_LO_SUM (Pmode, tmp2,
                             mips_unspec_address (loc, SYMBOL_DTPREL));
      break;

    case TLS_MODEL_INITIAL_EXEC:
      v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
      tmp1 = gen_reg_rtx (Pmode);
      tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
      if (Pmode == DImode)
        {
          emit_insn (gen_tls_get_tp_di (v1));
          emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
        }
      else
        {
          emit_insn (gen_tls_get_tp_si (v1));
          emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
        }
      dest = gen_reg_rtx (Pmode);
      emit_insn (gen_add3_insn (dest, tmp1, v1));
      break;

    case TLS_MODEL_LOCAL_EXEC:
      v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
      if (Pmode == DImode)
        emit_insn (gen_tls_get_tp_di (v1));
      else
        emit_insn (gen_tls_get_tp_si (v1));

      tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
      dest = gen_rtx_LO_SUM (Pmode, tmp1,
                             mips_unspec_address (loc, SYMBOL_TPREL));
      break;

    default:
      gcc_unreachable ();
    }
  return dest;
}
\f
/* This function is used to implement LEGITIMIZE_ADDRESS.  If *XLOC can
   be legitimized in a way that the generic machinery might not expect,
   put the new address in *XLOC and return true.  MODE is the mode of
   the memory being accessed.  */

bool
mips_legitimize_address (rtx *xloc, enum machine_mode mode)
{
  rtx base;
  HOST_WIDE_INT offset;

  if (mips_tls_symbol_p (*xloc))
    {
      *xloc = mips_legitimize_tls_address (*xloc);
      return true;
    }

  /* See if the address can split into a high part and a LO_SUM.  */
  if (mips_split_symbol (NULL, *xloc, mode, xloc))
    return true;

  /* Handle BASE + OFFSET using mips_add_offset.  */
  mips_split_plus (*xloc, &base, &offset);
  if (offset != 0)
    {
      if (!mips_valid_base_register_p (base, mode, false))
        base = copy_to_mode_reg (Pmode, base);
      *xloc = mips_add_offset (NULL, base, offset);
      return true;
    }
  return false;
}

/* Load VALUE into DEST.  TEMP is as for mips_force_temporary.  */

void
mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
{
  struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
  enum machine_mode mode;
  unsigned int i, num_ops;
  rtx x;

  mode = GET_MODE (dest);
  num_ops = mips_build_integer (codes, value);

  /* Apply each binary operation to X.  Invariant: X is a legitimate
     source operand for a SET pattern.  */
  x = GEN_INT (codes[0].value);
  for (i = 1; i < num_ops; i++)
    {
      if (!can_create_pseudo_p ())
        {
          emit_insn (gen_rtx_SET (VOIDmode, temp, x));
          x = temp;
        }
      else
        x = force_reg (mode, x);
      x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
    }

  emit_insn (gen_rtx_SET (VOIDmode, dest, x));
}

/* Subroutine of mips_legitimize_move.  Move constant SRC into register
   DEST given that SRC satisfies immediate_operand but doesn't satisfy
   move_operand.  */

static void
mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
{
  rtx base, offset;

  /* Split moves of big integers into smaller pieces.  */
  if (splittable_const_int_operand (src, mode))
    {
      mips_move_integer (dest, dest, INTVAL (src));
      return;
    }

  /* Split moves of symbolic constants into high/low pairs.  */
  if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
    {
      emit_insn (gen_rtx_SET (VOIDmode, dest, src));
      return;
    }

  /* Generate the appropriate access sequences for TLS symbols.  */
  if (mips_tls_symbol_p (src))
    {
      mips_emit_move (dest, mips_legitimize_tls_address (src));
      return;
    }

  /* If we have (const (plus symbol offset)), and that expression cannot
     be forced into memory, load the symbol first and add in the offset.
     In non-MIPS16 mode, prefer to do this even if the constant _can_ be
     forced into memory, as it usually produces better code.  */
  split_const (src, &base, &offset);
  if (offset != const0_rtx
      && (targetm.cannot_force_const_mem (src)
          || (!TARGET_MIPS16 && can_create_pseudo_p ())))
    {
      base = mips_force_temporary (dest, base);
      mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
      return;
    }

  src = force_const_mem (mode, src);

  /* When using explicit relocs, constant pool references are sometimes
     not legitimate addresses.  */
  mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
  mips_emit_move (dest, src);
}

/* If (set DEST SRC) is not a valid move instruction, emit an equivalent
   sequence that is valid.  */

bool
mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
{
  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
    {
      mips_emit_move (dest, force_reg (mode, src));
      return true;
    }

  /* Check for individual, fully-reloaded mflo and mfhi instructions.  */
  if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
      && REG_P (src) && MD_REG_P (REGNO (src))
      && REG_P (dest) && GP_REG_P (REGNO (dest)))
    {
      int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
      if (GET_MODE_SIZE (mode) <= 4)
        emit_insn (gen_mfhilo_si (gen_lowpart (SImode, dest),
                                  gen_lowpart (SImode, src),
                                  gen_rtx_REG (SImode, other_regno)));
      else
        emit_insn (gen_mfhilo_di (gen_lowpart (DImode, dest),
                                  gen_lowpart (DImode, src),
                                  gen_rtx_REG (DImode, other_regno)));
      return true;
    }

  /* We need to deal with constants that would be legitimate
     immediate_operands but aren't legitimate move_operands.  */
  if (CONSTANT_P (src) && !move_operand (src, mode))
    {
      mips_legitimize_const_move (mode, dest, src);
      set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
      return true;
    }
  return false;
}
\f
/* Return true if value X in context CONTEXT is a small-data address
   that can be rewritten as a LO_SUM.  */

static bool
mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
{
  enum mips_symbol_type symbol_type;

  return (TARGET_EXPLICIT_RELOCS
          && mips_symbolic_constant_p (x, context, &symbol_type)
          && symbol_type == SYMBOL_GP_RELATIVE);
}

/* A for_each_rtx callback for mips_small_data_pattern_p.  DATA is the
   containing MEM, or null if none.  */

static int
mips_small_data_pattern_1 (rtx *loc, void *data)
{
  enum mips_symbol_context context;

  if (GET_CODE (*loc) == LO_SUM)
    return -1;

  if (MEM_P (*loc))
    {
      if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
        return 1;
      return -1;
    }

  context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
  return mips_rewrite_small_data_p (*loc, context);
}

/* Return true if OP refers to small data symbols directly, not through
   a LO_SUM.  */

bool
mips_small_data_pattern_p (rtx op)
{
  return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
}

/* A for_each_rtx callback, used by mips_rewrite_small_data.
   DATA is the containing MEM, or null if none.  */

static int
mips_rewrite_small_data_1 (rtx *loc, void *data)
{
  enum mips_symbol_context context;

  if (MEM_P (*loc))
    {
      for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
      return -1;
    }

  context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
  if (mips_rewrite_small_data_p (*loc, context))
    *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);

  if (GET_CODE (*loc) == LO_SUM)
    return -1;

  return 0;
}

/* Rewrite instruction pattern PATTERN so that it refers to small data
   using explicit relocations.  */

rtx
mips_rewrite_small_data (rtx pattern)
{
  pattern = copy_insn (pattern);
  for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
  return pattern;
}
\f
/* We need a lot of little routines to check the range of MIPS16 immediate
   operands.  */

static int
m16_check_op (rtx op, int low, int high, int mask)
{
  return (GET_CODE (op) == CONST_INT
          && IN_RANGE (INTVAL (op), low, high)
          && (INTVAL (op) & mask) == 0);
}

int
m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, 0x1, 0x8, 0);
}

int
m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x8, 0x7, 0);
}

int
m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x7, 0x8, 0);
}

int
m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x10, 0xf, 0);
}

int
m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0xf, 0x10, 0);
}

int
m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
}

int
m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
}

int
m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x80, 0x7f, 0);
}

int
m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x7f, 0x80, 0);
}

int
m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, 0x0, 0xff, 0);
}

int
m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0xff, 0x0, 0);
}

int
m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x1, 0xfe, 0);
}

int
m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, 0x0, 0xff << 2, 3);
}

int
m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0xff << 2, 0x0, 3);
}

int
m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
}

int
m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
  return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
}
\f
/* The cost of loading values from the constant pool.  It should be
   larger than the cost of any constant we want to synthesize inline.  */
#define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)

/* Return the cost of X when used as an operand to the MIPS16 instruction
   that implements CODE.  Return -1 if there is no such instruction, or if
   X is not a valid immediate operand for it.  */

static int
mips16_constant_cost (int code, HOST_WIDE_INT x)
{
  switch (code)
    {
    case ASHIFT:
    case ASHIFTRT:
    case LSHIFTRT:
      /* Shifts by between 1 and 8 bits (inclusive) are unextended,
         other shifts are extended.  The shift patterns truncate the shift
         count to the right size, so there are no out-of-range values.  */
      if (IN_RANGE (x, 1, 8))
        return 0;
      return COSTS_N_INSNS (1);

    case PLUS:
      if (IN_RANGE (x, -128, 127))
        return 0;
      if (SMALL_OPERAND (x))
        return COSTS_N_INSNS (1);
      return -1;

    case LEU:
      /* Like LE, but reject the always-true case.  */
      if (x == -1)
        return -1;
    case LE:
      /* We add 1 to the immediate and use SLT.  */
      x += 1;
    case XOR:
      /* We can use CMPI for an xor with an unsigned 16-bit X.  */
    case LT:
    case LTU:
      if (IN_RANGE (x, 0, 255))
        return 0;
      if (SMALL_OPERAND_UNSIGNED (x))
        return COSTS_N_INSNS (1);
      return -1;

    case EQ:
    case NE:
      /* Equality comparisons with 0 are cheap.  */
      if (x == 0)
        return 0;
      return -1;

    default:
      return -1;
    }
}

/* Return true if there is a non-MIPS16 instruction that implements CODE
   and if that instruction accepts X as an immediate operand.  */

static int
mips_immediate_operand_p (int code, HOST_WIDE_INT x)
{
  switch (code)
    {
    case ASHIFT:
    case ASHIFTRT:
    case LSHIFTRT:
      /* All shift counts are truncated to a valid constant.  */
      return true;

    case ROTATE:
    case ROTATERT:
      /* Likewise rotates, if the target supports rotates at all.  */
      return ISA_HAS_ROR;

    case AND:
    case IOR:
    case XOR:
      /* These instructions take 16-bit unsigned immediates.  */
      return SMALL_OPERAND_UNSIGNED (x);

    case PLUS:
    case LT:
    case LTU:
      /* These instructions take 16-bit signed immediates.  */
      return SMALL_OPERAND (x);

    case EQ:
    case NE:
    case GT:
    case GTU:
      /* The "immediate" forms of these instructions are really
         implemented as comparisons with register 0.  */
      return x == 0;

    case GE:
    case GEU:
      /* Likewise, meaning that the only valid immediate operand is 1.  */
      return x == 1;

    case LE:
      /* We add 1 to the immediate and use SLT.  */
      return SMALL_OPERAND (x + 1);

    case LEU:
      /* Likewise SLTU, but reject the always-true case.  */
      return SMALL_OPERAND (x + 1) && x + 1 != 0;

    case SIGN_EXTRACT:
    case ZERO_EXTRACT:
      /* The bit position and size are immediate operands.  */
      return ISA_HAS_EXT_INS;

    default:
      /* By default assume that $0 can be used for 0.  */
      return x == 0;
    }
}

/* Return the cost of binary operation X, given that the instruction
   sequence for a word-sized or smaller operation has cost SINGLE_COST
   and that the sequence of a double-word operation has cost DOUBLE_COST.  */

static int
mips_binary_cost (rtx x, int single_cost, int double_cost)
{
  int cost;

  if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
    cost = double_cost;
  else
    cost = single_cost;
  return (cost
          + rtx_cost (XEXP (x, 0), 0)
          + rtx_cost (XEXP (x, 1), GET_CODE (x)));
}

/* Return the cost of floating-point multiplications of mode MODE.  */

static int
mips_fp_mult_cost (enum machine_mode mode)
{
  return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
}

/* Return the cost of floating-point divisions of mode MODE.  */

static int
mips_fp_div_cost (enum machine_mode mode)
{
  return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
}

/* Return the cost of sign-extending OP to mode MODE, not including the
   cost of OP itself.  */

static int
mips_sign_extend_cost (enum machine_mode mode, rtx op)
{
  if (MEM_P (op))
    /* Extended loads are as cheap as unextended ones.  */
    return 0;

  if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
    /* A sign extension from SImode to DImode in 64-bit mode is free.  */
    return 0;

  if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
    /* We can use SEB or SEH.  */
    return COSTS_N_INSNS (1);

  /* We need to use a shift left and a shift right.  */
  return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
}

/* Return the cost of zero-extending OP to mode MODE, not including the
   cost of OP itself.  */

static int
mips_zero_extend_cost (enum machine_mode mode, rtx op)
{
  if (MEM_P (op))
    /* Extended loads are as cheap as unextended ones.  */
    return 0;

  if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
    /* We need a shift left by 32 bits and a shift right by 32 bits.  */
    return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);

  if (GENERATE_MIPS16E)
    /* We can use ZEB or ZEH.  */
    return COSTS_N_INSNS (1);

  if (TARGET_MIPS16)
    /* We need to load 0xff or 0xffff into a register and use AND.  */
    return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);

  /* We can use ANDI.  */
  return COSTS_N_INSNS (1);
}

/* Implement TARGET_RTX_COSTS.  */

static bool
mips_rtx_costs (rtx x, int code, int outer_code, int *total)
{
  enum machine_mode mode = GET_MODE (x);
  bool float_mode_p = FLOAT_MODE_P (mode);
  int cost;
  rtx addr;

  /* The cost of a COMPARE is hard to define for MIPS.  COMPAREs don't
     appear in the instruction stream, and the cost of a comparison is
     really the cost of the branch or scc condition.  At the time of
     writing, GCC only uses an explicit outer COMPARE code when optabs
     is testing whether a constant is expensive enough to force into a
     register.  We want optabs to pass such constants through the MIPS
     expanders instead, so make all constants very cheap here.  */
  if (outer_code == COMPARE)
    {
      gcc_assert (CONSTANT_P (x));
      *total = 0;
      return true;
    }

  switch (code)
    {
    case CONST_INT:
      /* Treat *clear_upper32-style ANDs as having zero cost in the
         second operand.  The cost is entirely in the first operand.

         ??? This is needed because we would otherwise try to CSE
         the constant operand.  Although that's the right thing for
         instructions that continue to be a register operation throughout
         compilation, it is disastrous for instructions that could
         later be converted into a memory operation.  */
      if (TARGET_64BIT
          && outer_code == AND
          && UINTVAL (x) == 0xffffffff)
        {
          *total = 0;
          return true;
        }

      if (TARGET_MIPS16)
        {
          cost = mips16_constant_cost (outer_code, INTVAL (x));
          if (cost >= 0)
            {
              *total = cost;
              return true;
            }
        }
      else
        {
          /* When not optimizing for size, we care more about the cost
             of hot code, and hot code is often in a loop.  If a constant
             operand needs to be forced into a register, we will often be
             able to hoist the constant load out of the loop, so the load
             should not contribute to the cost.  */
          if (!optimize_size
              || mips_immediate_operand_p (outer_code, INTVAL (x)))
            {
              *total = 0;
              return true;
            }
        }
      /* Fall through.  */

    case CONST:
    case SYMBOL_REF:
    case LABEL_REF:
    case CONST_DOUBLE:
      if (force_to_mem_operand (x, VOIDmode))
        {
          *total = COSTS_N_INSNS (1);
          return true;
        }
      cost = mips_const_insns (x);
      if (cost > 0)
        {
          /* If the constant is likely to be stored in a GPR, SETs of
             single-insn constants are as cheap as register sets; we
             never want to CSE them.

             Don't reduce the cost of storing a floating-point zero in
             FPRs.  If we have a zero in an FPR for other reasons, we
             can get better cfg-cleanup and delayed-branch results by
             using it consistently, rather than using $0 sometimes and
             an FPR at other times.  Also, moves between floating-point
             registers are sometimes cheaper than (D)MTC1 $0.  */
          if (cost == 1
              && outer_code == SET
              && !(float_mode_p && TARGET_HARD_FLOAT))
            cost = 0;
          /* When non-MIPS16 code loads a constant N>1 times, we rarely
             want to CSE the constant itself.  It is usually better to
             have N copies of the last operation in the sequence and one
             shared copy of the other operations.  (Note that this is
             not true for MIPS16 code, where the final operation in the
             sequence is often an extended instruction.)

             Also, if we have a CONST_INT, we don't know whether it is
             for a word or doubleword operation, so we cannot rely on
             the result of mips_build_integer.  */
          else if (!TARGET_MIPS16
                   && (outer_code == SET || mode == VOIDmode))
            cost = 1;
          *total = COSTS_N_INSNS (cost);
          return true;
        }
      /* The value will need to be fetched from the constant pool.  */
      *total = CONSTANT_POOL_COST;
      return true;

    case MEM:
      /* If the address is legitimate, return the number of
         instructions it needs.  */
      addr = XEXP (x, 0);
      cost = mips_address_insns (addr, mode, true);
      if (cost > 0)
        {
          *total = COSTS_N_INSNS (cost + 1);
          return true;
        }
      /* Check for a scaled indexed address.  */
      if (mips_lwxs_address_p (addr))
        {
          *total = COSTS_N_INSNS (2);
          return true;
        }
      /* Otherwise use the default handling.  */
      return false;

    case FFS:
      *total = COSTS_N_INSNS (6);
      return false;

    case NOT:
      *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
      return false;

    case AND:
      /* Check for a *clear_upper32 pattern and treat it like a zero
         extension.  See the pattern's comment for details.  */
      if (TARGET_64BIT
          && mode == DImode
          && CONST_INT_P (XEXP (x, 1))
          && UINTVAL (XEXP (x, 1)) == 0xffffffff)
        {
          *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
                    + rtx_cost (XEXP (x, 0), 0));
          return true;
        }
      /* Fall through.  */

    case IOR:
    case XOR:
      /* Double-word operations use two single-word operations.  */
      *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
      return true;

    case ASHIFT:
    case ASHIFTRT:
    case LSHIFTRT:
    case ROTATE:
    case ROTATERT:
      if (CONSTANT_P (XEXP (x, 1)))
        *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
      else
        *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
      return true;

    case ABS:
      if (float_mode_p)
        *total = mips_cost->fp_add;
      else
        *total = COSTS_N_INSNS (4);
      return false;

    case LO_SUM:
      /* Low-part immediates need an extended MIPS16 instruction.  */
      *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
                + rtx_cost (XEXP (x, 0), 0));
      return true;

    case LT:
    case LTU:
    case LE:
    case LEU:
    case GT:
    case GTU:
    case GE:
    case GEU:
    case EQ:
    case NE:
    case UNORDERED:
    case LTGT:
      /* Branch comparisons have VOIDmode, so use the first operand's
         mode instead.  */
      mode = GET_MODE (XEXP (x, 0));
      if (FLOAT_MODE_P (mode))
        {
          *total = mips_cost->fp_add;
          return false;
        }
      *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
      return true;

    case MINUS:
      if (float_mode_p
          && ISA_HAS_NMADD_NMSUB (mode)
          && TARGET_FUSED_MADD
          && !HONOR_NANS (mode)
          && !HONOR_SIGNED_ZEROS (mode))
        {
          /* See if we can use NMADD or NMSUB.  See mips.md for the
             associated patterns.  */
          rtx op0 = XEXP (x, 0);
          rtx op1 = XEXP (x, 1);
          if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
            {
              *total = (mips_fp_mult_cost (mode)
                        + rtx_cost (XEXP (XEXP (op0, 0), 0), 0)
                        + rtx_cost (XEXP (op0, 1), 0)
                        + rtx_cost (op1, 0));
              return true;
            }
          if (GET_CODE (op1) == MULT)
            {
              *total = (mips_fp_mult_cost (mode)
                        + rtx_cost (op0, 0)
                        + rtx_cost (XEXP (op1, 0), 0)
                        + rtx_cost (XEXP (op1, 1), 0));
              return true;
            }
        }
      /* Fall through.  */

    case PLUS:
      if (float_mode_p)
        {
          /* If this is part of a MADD or MSUB, treat the PLUS as
             being free.  */
          if (ISA_HAS_FP4
              && TARGET_FUSED_MADD
              && GET_CODE (XEXP (x, 0)) == MULT)
            *total = 0;
          else
            *total = mips_cost->fp_add;
          return false;
        }

      /* Double-word operations require three single-word operations and
         an SLTU.  The MIPS16 version then needs to move the result of
         the SLTU from $24 to a MIPS16 register.  */
      *total = mips_binary_cost (x, COSTS_N_INSNS (1),
                                 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
      return true;

    case NEG:
      if (float_mode_p
          && ISA_HAS_NMADD_NMSUB (mode)
          && TARGET_FUSED_MADD
          && !HONOR_NANS (mode)
          && HONOR_SIGNED_ZEROS (mode))
        {
          /* See if we can use NMADD or NMSUB.  See mips.md for the
             associated patterns.  */
          rtx op = XEXP (x, 0);
          if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
              && GET_CODE (XEXP (op, 0)) == MULT)
            {
              *total = (mips_fp_mult_cost (mode)
                        + rtx_cost (XEXP (XEXP (op, 0), 0), 0)
                        + rtx_cost (XEXP (XEXP (op, 0), 1), 0)
                        + rtx_cost (XEXP (op, 1), 0));
              return true;
            }
        }

      if (float_mode_p)
        *total = mips_cost->fp_add;
      else
        *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
      return false;

    case MULT:
      if (float_mode_p)
        *total = mips_fp_mult_cost (mode);
      else if (mode == DImode && !TARGET_64BIT)
        /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
           where the mulsidi3 always includes an MFHI and an MFLO.  */
        *total = (optimize_size
                  ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
                  : mips_cost->int_mult_si * 3 + 6);
      else if (optimize_size)
        *total = (ISA_HAS_MUL3 ? 1 : 2);
      else if (mode == DImode)
        *total = mips_cost->int_mult_di;
      else
        *total = mips_cost->int_mult_si;
      return false;

    case DIV:
      /* Check for a reciprocal.  */
      if (float_mode_p
          && ISA_HAS_FP4
          && flag_unsafe_math_optimizations
          && XEXP (x, 0) == CONST1_RTX (mode))
        {
          if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
            /* An rsqrt<mode>a or rsqrt<mode>b pattern.  Count the
               division as being free.  */
            *total = rtx_cost (XEXP (x, 1), 0);
          else
            *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0);
          return true;
        }
      /* Fall through.  */

    case SQRT:
    case MOD:
      if (float_mode_p)
        {
          *total = mips_fp_div_cost (mode);
          return false;
        }
      /* Fall through.  */

    case UDIV:
    case UMOD:
      if (optimize_size)
        {
          /* It is our responsibility to make division by a power of 2
             as cheap as 2 register additions if we want the division
             expanders to be used for such operations; see the setting
             of sdiv_pow2_cheap in optabs.c.  Using (D)DIV for MIPS16
             should always produce shorter code than using
             expand_sdiv2_pow2.  */
          if (TARGET_MIPS16
              && CONST_INT_P (XEXP (x, 1))
              && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
            {
              *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0);
              return true;
            }
          *total = COSTS_N_INSNS (mips_idiv_insns ());
        }
      else if (mode == DImode)
        *total = mips_cost->int_div_di;
      else
        *total = mips_cost->int_div_si;
      return false;

    case SIGN_EXTEND:
      *total = mips_sign_extend_cost (mode, XEXP (x, 0));
      return false;

    case ZERO_EXTEND:
      *total = mips_zero_extend_cost (mode, XEXP (x, 0));
      return false;

    case FLOAT:
    case UNSIGNED_FLOAT:
    case FIX:
    case FLOAT_EXTEND:
    case FLOAT_TRUNCATE:
      *total = mips_cost->fp_add;
      return false;

    default:
      return false;
    }
}

/* Implement TARGET_ADDRESS_COST.  */

static int
mips_address_cost (rtx addr)
{
  return mips_address_insns (addr, SImode, false);
}
\f
/* Return one word of double-word value OP, taking into account the fixed
   endianness of certain registers.  HIGH_P is true to select the high part,
   false to select the low part.  */

rtx
mips_subword (rtx op, bool high_p)
{
  unsigned int byte, offset;
  enum machine_mode mode;

  mode = GET_MODE (op);
  if (mode == VOIDmode)
    mode = DImode;

  if (TARGET_BIG_ENDIAN ? !high_p : high_p)
    byte = UNITS_PER_WORD;
  else
    byte = 0;

  if (FP_REG_RTX_P (op))
    {
      /* Paired FPRs are always ordered little-endian.  */
      offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
      return gen_rtx_REG (word_mode, REGNO (op) + offset);
    }

  if (MEM_P (op))
    return mips_rewrite_small_data (adjust_address (op, word_mode, byte));

  return simplify_gen_subreg (word_mode, op, mode, byte);
}

/* Return true if a 64-bit move from SRC to DEST should be split into two.  */

bool
mips_split_64bit_move_p (rtx dest, rtx src)
{
  if (TARGET_64BIT)
    return false;

  /* FPR-to-FPR moves can be done in a single instruction, if they're
     allowed at all.  */
  if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
    return false;

  /* Check for floating-point loads and stores.  */
  if (ISA_HAS_LDC1_SDC1)
    {
      if (FP_REG_RTX_P (dest) && MEM_P (src))
        return false;
      if (FP_REG_RTX_P (src) && MEM_P (dest))
        return false;
    }
  return true;
}

/* Split a doubleword move from SRC to DEST.  On 32-bit targets,
   this function handles 64-bit moves for which mips_split_64bit_move_p
   holds.  For 64-bit targets, this function handles 128-bit moves.  */

void
mips_split_doubleword_move (rtx dest, rtx src)