1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "integrate.h"
54 #include "langhooks.h"
55 #include "cfglayout.h"
56 #include "sched-int.h"
59 #include "diagnostic.h"
60 #include "target-globals.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (NONDEBUG_INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Return the opcode for a ptr_mode load of the form:
130 l[wd] DEST, OFFSET(BASE). */
131 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
132 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
137 /* Return the opcode to move register SRC into register DEST. */
138 #define MIPS_MOVE(DEST, SRC) \
139 ((TARGET_64BIT ? 0x2d : 0x21) \
143 /* Return the opcode for:
146 #define MIPS_LUI(DEST, VALUE) \
147 ((0xf << 26) | ((DEST) << 16) | (VALUE))
149 /* Return the opcode to jump to register DEST. */
150 #define MIPS_JR(DEST) \
151 (((DEST) << 21) | 0x8)
153 /* Return the opcode for:
155 bal . + (1 + OFFSET) * 4. */
156 #define MIPS_BAL(OFFSET) \
157 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
159 /* Return the usual opcode for a nop. */
162 /* Classifies an address.
165 A natural register + offset address. The register satisfies
166 mips_valid_base_register_p and the offset is a const_arith_operand.
169 A LO_SUM rtx. The first operand is a valid base register and
170 the second operand is a symbolic address.
173 A signed 16-bit constant address.
176 A constant symbolic address. */
177 enum mips_address_type {
184 /* Enumerates the setting of the -mr10k-cache-barrier option. */
185 enum mips_r10k_cache_barrier_setting {
186 R10K_CACHE_BARRIER_NONE,
187 R10K_CACHE_BARRIER_STORE,
188 R10K_CACHE_BARRIER_LOAD_STORE
191 /* Macros to create an enumeration identifier for a function prototype. */
192 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
193 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
194 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
195 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
197 /* Classifies the prototype of a built-in function. */
198 enum mips_function_type {
199 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
200 #include "config/mips/mips-ftypes.def"
201 #undef DEF_MIPS_FTYPE
205 /* Specifies how a built-in function should be converted into rtl. */
206 enum mips_builtin_type {
207 /* The function corresponds directly to an .md pattern. The return
208 value is mapped to operand 0 and the arguments are mapped to
209 operands 1 and above. */
212 /* The function corresponds directly to an .md pattern. There is no return
213 value and the arguments are mapped to operands 0 and above. */
214 MIPS_BUILTIN_DIRECT_NO_TARGET,
216 /* The function corresponds to a comparison instruction followed by
217 a mips_cond_move_tf_ps pattern. The first two arguments are the
218 values to compare and the second two arguments are the vector
219 operands for the movt.ps or movf.ps instruction (in assembly order). */
223 /* The function corresponds to a V2SF comparison instruction. Operand 0
224 of this instruction is the result of the comparison, which has mode
225 CCV2 or CCV4. The function arguments are mapped to operands 1 and
226 above. The function's return value is an SImode boolean that is
227 true under the following conditions:
229 MIPS_BUILTIN_CMP_ANY: one of the registers is true
230 MIPS_BUILTIN_CMP_ALL: all of the registers are true
231 MIPS_BUILTIN_CMP_LOWER: the first register is true
232 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
233 MIPS_BUILTIN_CMP_ANY,
234 MIPS_BUILTIN_CMP_ALL,
235 MIPS_BUILTIN_CMP_UPPER,
236 MIPS_BUILTIN_CMP_LOWER,
238 /* As above, but the instruction only sets a single $fcc register. */
239 MIPS_BUILTIN_CMP_SINGLE,
241 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
242 MIPS_BUILTIN_BPOSGE32
245 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
246 #define MIPS_FP_CONDITIONS(MACRO) \
264 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
265 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
266 enum mips_fp_condition {
267 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
270 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
271 #define STRINGIFY(X) #X
272 static const char *const mips_fp_conditions[] = {
273 MIPS_FP_CONDITIONS (STRINGIFY)
276 /* Information about a function's frame layout. */
277 struct GTY(()) mips_frame_info {
278 /* The size of the frame in bytes. */
279 HOST_WIDE_INT total_size;
281 /* The number of bytes allocated to variables. */
282 HOST_WIDE_INT var_size;
284 /* The number of bytes allocated to outgoing function arguments. */
285 HOST_WIDE_INT args_size;
287 /* The number of bytes allocated to the .cprestore slot, or 0 if there
289 HOST_WIDE_INT cprestore_size;
291 /* Bit X is set if the function saves or restores GPR X. */
294 /* Likewise FPR X. */
297 /* Likewise doubleword accumulator X ($acX). */
298 unsigned int acc_mask;
300 /* The number of GPRs, FPRs, doubleword accumulators and COP0
304 unsigned int num_acc;
305 unsigned int num_cop0_regs;
307 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
308 save slots from the top of the frame, or zero if no such slots are
310 HOST_WIDE_INT gp_save_offset;
311 HOST_WIDE_INT fp_save_offset;
312 HOST_WIDE_INT acc_save_offset;
313 HOST_WIDE_INT cop0_save_offset;
315 /* Likewise, but giving offsets from the bottom of the frame. */
316 HOST_WIDE_INT gp_sp_offset;
317 HOST_WIDE_INT fp_sp_offset;
318 HOST_WIDE_INT acc_sp_offset;
319 HOST_WIDE_INT cop0_sp_offset;
321 /* Similar, but the value passed to _mcount. */
322 HOST_WIDE_INT ra_fp_offset;
324 /* The offset of arg_pointer_rtx from the bottom of the frame. */
325 HOST_WIDE_INT arg_pointer_offset;
327 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
328 HOST_WIDE_INT hard_frame_pointer_offset;
331 struct GTY(()) machine_function {
332 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
333 rtx mips16_gp_pseudo_rtx;
335 /* The number of extra stack bytes taken up by register varargs.
336 This area is allocated by the callee at the very top of the frame. */
339 /* The current frame information, calculated by mips_compute_frame_info. */
340 struct mips_frame_info frame;
342 /* The register to use as the function's global pointer, or INVALID_REGNUM
343 if the function doesn't need one. */
344 unsigned int global_pointer;
346 /* How many instructions it takes to load a label into $AT, or 0 if
347 this property hasn't yet been calculated. */
348 unsigned int load_label_num_insns;
350 /* True if mips_adjust_insn_length should ignore an instruction's
352 bool ignore_hazard_length_p;
354 /* True if the whole function is suitable for .set noreorder and
356 bool all_noreorder_p;
358 /* True if the function has "inflexible" and "flexible" references
359 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
360 and mips_cfun_has_flexible_gp_ref_p for details. */
361 bool has_inflexible_gp_insn_p;
362 bool has_flexible_gp_insn_p;
364 /* True if the function's prologue must load the global pointer
365 value into pic_offset_table_rtx and store the same value in
366 the function's cprestore slot (if any). Even if this value
367 is currently false, we may decide to set it to true later;
368 see mips_must_initialize_gp_p () for details. */
369 bool must_initialize_gp_p;
371 /* True if the current function must restore $gp after any potential
372 clobber. This value is only meaningful during the first post-epilogue
373 split_insns pass; see mips_must_initialize_gp_p () for details. */
374 bool must_restore_gp_when_clobbered_p;
376 /* True if this is an interrupt handler. */
377 bool interrupt_handler_p;
379 /* True if this is an interrupt handler that uses shadow registers. */
380 bool use_shadow_register_set_p;
382 /* True if this is an interrupt handler that should keep interrupts
384 bool keep_interrupts_masked_p;
386 /* True if this is an interrupt handler that should use DERET
388 bool use_debug_exception_return_p;
391 /* Information about a single argument. */
392 struct mips_arg_info {
393 /* True if the argument is passed in a floating-point register, or
394 would have been if we hadn't run out of registers. */
397 /* The number of words passed in registers, rounded up. */
398 unsigned int reg_words;
400 /* For EABI, the offset of the first register from GP_ARG_FIRST or
401 FP_ARG_FIRST. For other ABIs, the offset of the first register from
402 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
403 comment for details).
405 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
407 unsigned int reg_offset;
409 /* The number of words that must be passed on the stack, rounded up. */
410 unsigned int stack_words;
412 /* The offset from the start of the stack overflow area of the argument's
413 first stack word. Only meaningful when STACK_WORDS is nonzero. */
414 unsigned int stack_offset;
417 /* Information about an address described by mips_address_type.
423 REG is the base register and OFFSET is the constant offset.
426 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
427 is the type of symbol it references.
430 SYMBOL_TYPE is the type of symbol that the address references. */
431 struct mips_address_info {
432 enum mips_address_type type;
435 enum mips_symbol_type symbol_type;
438 /* One stage in a constant building sequence. These sequences have
442 A = A CODE[1] VALUE[1]
443 A = A CODE[2] VALUE[2]
446 where A is an accumulator, each CODE[i] is a binary rtl operation
447 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
448 struct mips_integer_op {
450 unsigned HOST_WIDE_INT value;
453 /* The largest number of operations needed to load an integer constant.
454 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
455 When the lowest bit is clear, we can try, but reject a sequence with
456 an extra SLL at the end. */
457 #define MIPS_MAX_INTEGER_OPS 7
459 /* Information about a MIPS16e SAVE or RESTORE instruction. */
460 struct mips16e_save_restore_info {
461 /* The number of argument registers saved by a SAVE instruction.
462 0 for RESTORE instructions. */
465 /* Bit X is set if the instruction saves or restores GPR X. */
468 /* The total number of bytes to allocate. */
472 /* Costs of various operations on the different architectures. */
474 struct mips_rtx_cost_data
476 unsigned short fp_add;
477 unsigned short fp_mult_sf;
478 unsigned short fp_mult_df;
479 unsigned short fp_div_sf;
480 unsigned short fp_div_df;
481 unsigned short int_mult_si;
482 unsigned short int_mult_di;
483 unsigned short int_div_si;
484 unsigned short int_div_di;
485 unsigned short branch_cost;
486 unsigned short memory_latency;
489 /* Global variables for machine-dependent things. */
491 /* The -G setting, or the configuration's default small-data limit if
492 no -G option is given. */
493 static unsigned int mips_small_data_threshold;
495 /* The number of file directives written by mips_output_filename. */
496 int num_source_filenames;
498 /* The name that appeared in the last .file directive written by
499 mips_output_filename, or "" if mips_output_filename hasn't
500 written anything yet. */
501 const char *current_function_file = "";
503 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
506 /* Arrays that map GCC register numbers to debugger register numbers. */
507 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
508 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
510 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
511 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
512 struct mips_asm_switch mips_nomacro = { "macro", 0 };
513 struct mips_asm_switch mips_noat = { "at", 0 };
515 /* True if we're writing out a branch-likely instruction rather than a
517 static bool mips_branch_likely;
519 /* The current instruction-set architecture. */
520 enum processor mips_arch;
521 const struct mips_cpu_info *mips_arch_info;
523 /* The processor that we should tune the code for. */
524 enum processor mips_tune;
525 const struct mips_cpu_info *mips_tune_info;
527 /* The ISA level associated with mips_arch. */
530 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
531 static const struct mips_cpu_info *mips_isa_option_info;
533 /* Which ABI to use. */
534 int mips_abi = MIPS_ABI_DEFAULT;
536 /* Which cost information to use. */
537 static const struct mips_rtx_cost_data *mips_cost;
539 /* The ambient target flags, excluding MASK_MIPS16. */
540 static int mips_base_target_flags;
542 /* True if MIPS16 is the default mode. */
543 bool mips_base_mips16;
545 /* The ambient values of other global variables. */
546 static int mips_base_schedule_insns; /* flag_schedule_insns */
547 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
548 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
549 static int mips_base_align_loops; /* align_loops */
550 static int mips_base_align_jumps; /* align_jumps */
551 static int mips_base_align_functions; /* align_functions */
553 /* The -mcode-readable setting. */
554 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
556 /* The -mr10k-cache-barrier setting. */
557 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
559 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
560 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
562 /* Index C is true if character C is a valid PRINT_OPERAND punctation
564 static bool mips_print_operand_punct[256];
566 static GTY (()) int mips_output_filename_first_time = 1;
568 /* mips_split_p[X] is true if symbols of type X can be split by
569 mips_split_symbol. */
570 bool mips_split_p[NUM_SYMBOL_TYPES];
572 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
573 can be split by mips_split_symbol. */
574 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
576 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
577 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
578 if they are matched by a special .md file pattern. */
579 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
581 /* Likewise for HIGHs. */
582 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
584 /* Target state for MIPS16. */
585 struct target_globals *mips16_globals;
587 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
588 and returned from mips_sched_reorder2. */
589 static int cached_can_issue_more;
591 /* Index R is the smallest register class that contains register R. */
592 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
593 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
594 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
595 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
596 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
597 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
598 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
599 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
600 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
601 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
602 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
603 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
604 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
610 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
611 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
612 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
613 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
614 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
615 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
616 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
622 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
623 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
624 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
630 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
631 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
632 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
638 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
639 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
642 /* The value of TARGET_ATTRIBUTE_TABLE. */
643 static const struct attribute_spec mips_attribute_table[] = {
644 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
645 { "long_call", 0, 0, false, true, true, NULL },
646 { "far", 0, 0, false, true, true, NULL },
647 { "near", 0, 0, false, true, true, NULL },
648 /* We would really like to treat "mips16" and "nomips16" as type
649 attributes, but GCC doesn't provide the hooks we need to support
650 the right conversion rules. As declaration attributes, they affect
651 code generation but don't carry other semantics. */
652 { "mips16", 0, 0, true, false, false, NULL },
653 { "nomips16", 0, 0, true, false, false, NULL },
654 /* Allow functions to be specified as interrupt handlers */
655 { "interrupt", 0, 0, false, true, true, NULL },
656 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
657 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
658 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
659 { NULL, 0, 0, false, false, false, NULL }
662 /* A table describing all the processors GCC knows about. Names are
663 matched in the order listed. The first mention of an ISA level is
664 taken as the canonical name for that ISA.
666 To ease comparison, please keep this table in the same order
667 as GAS's mips_cpu_info_table. Please also make sure that
668 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
669 options correctly. */
670 static const struct mips_cpu_info mips_cpu_info_table[] = {
671 /* Entries for generic ISAs. */
672 { "mips1", PROCESSOR_R3000, 1, 0 },
673 { "mips2", PROCESSOR_R6000, 2, 0 },
674 { "mips3", PROCESSOR_R4000, 3, 0 },
675 { "mips4", PROCESSOR_R8000, 4, 0 },
676 /* Prefer not to use branch-likely instructions for generic MIPS32rX
677 and MIPS64rX code. The instructions were officially deprecated
678 in revisions 2 and earlier, but revision 3 is likely to downgrade
679 that to a recommendation to avoid the instructions in code that
680 isn't tuned to a specific processor. */
681 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
682 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
683 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
684 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
685 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
687 /* MIPS I processors. */
688 { "r3000", PROCESSOR_R3000, 1, 0 },
689 { "r2000", PROCESSOR_R3000, 1, 0 },
690 { "r3900", PROCESSOR_R3900, 1, 0 },
692 /* MIPS II processors. */
693 { "r6000", PROCESSOR_R6000, 2, 0 },
695 /* MIPS III processors. */
696 { "r4000", PROCESSOR_R4000, 3, 0 },
697 { "vr4100", PROCESSOR_R4100, 3, 0 },
698 { "vr4111", PROCESSOR_R4111, 3, 0 },
699 { "vr4120", PROCESSOR_R4120, 3, 0 },
700 { "vr4130", PROCESSOR_R4130, 3, 0 },
701 { "vr4300", PROCESSOR_R4300, 3, 0 },
702 { "r4400", PROCESSOR_R4000, 3, 0 },
703 { "r4600", PROCESSOR_R4600, 3, 0 },
704 { "orion", PROCESSOR_R4600, 3, 0 },
705 { "r4650", PROCESSOR_R4650, 3, 0 },
706 /* ST Loongson 2E/2F processors. */
707 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
708 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
710 /* MIPS IV processors. */
711 { "r8000", PROCESSOR_R8000, 4, 0 },
712 { "r10000", PROCESSOR_R10000, 4, 0 },
713 { "r12000", PROCESSOR_R10000, 4, 0 },
714 { "r14000", PROCESSOR_R10000, 4, 0 },
715 { "r16000", PROCESSOR_R10000, 4, 0 },
716 { "vr5000", PROCESSOR_R5000, 4, 0 },
717 { "vr5400", PROCESSOR_R5400, 4, 0 },
718 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
719 { "rm7000", PROCESSOR_R7000, 4, 0 },
720 { "rm9000", PROCESSOR_R9000, 4, 0 },
722 /* MIPS32 processors. */
723 { "4kc", PROCESSOR_4KC, 32, 0 },
724 { "4km", PROCESSOR_4KC, 32, 0 },
725 { "4kp", PROCESSOR_4KP, 32, 0 },
726 { "4ksc", PROCESSOR_4KC, 32, 0 },
728 /* MIPS32 Release 2 processors. */
729 { "m4k", PROCESSOR_M4K, 33, 0 },
730 { "4kec", PROCESSOR_4KC, 33, 0 },
731 { "4kem", PROCESSOR_4KC, 33, 0 },
732 { "4kep", PROCESSOR_4KP, 33, 0 },
733 { "4ksd", PROCESSOR_4KC, 33, 0 },
735 { "24kc", PROCESSOR_24KC, 33, 0 },
736 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
737 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
738 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
739 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
740 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
742 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
743 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
744 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
745 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
746 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
747 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
749 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
750 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
751 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
752 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
753 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
754 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
756 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
757 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
758 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
759 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
760 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
761 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
762 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
764 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
765 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
766 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
767 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
769 /* MIPS64 processors. */
770 { "5kc", PROCESSOR_5KC, 64, 0 },
771 { "5kf", PROCESSOR_5KF, 64, 0 },
772 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
773 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
774 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
775 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
776 { "xlr", PROCESSOR_XLR, 64, 0 },
777 { "loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY },
779 /* MIPS64 Release 2 processors. */
780 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
783 /* Default costs. If these are used for a processor we should look
784 up the actual costs. */
785 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
786 COSTS_N_INSNS (7), /* fp_mult_sf */ \
787 COSTS_N_INSNS (8), /* fp_mult_df */ \
788 COSTS_N_INSNS (23), /* fp_div_sf */ \
789 COSTS_N_INSNS (36), /* fp_div_df */ \
790 COSTS_N_INSNS (10), /* int_mult_si */ \
791 COSTS_N_INSNS (10), /* int_mult_di */ \
792 COSTS_N_INSNS (69), /* int_div_si */ \
793 COSTS_N_INSNS (69), /* int_div_di */ \
794 2, /* branch_cost */ \
795 4 /* memory_latency */
797 /* Floating-point costs for processors without an FPU. Just assume that
798 all floating-point libcalls are very expensive. */
799 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
800 COSTS_N_INSNS (256), /* fp_mult_sf */ \
801 COSTS_N_INSNS (256), /* fp_mult_df */ \
802 COSTS_N_INSNS (256), /* fp_div_sf */ \
803 COSTS_N_INSNS (256) /* fp_div_df */
805 /* Costs to use when optimizing for size. */
806 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
807 COSTS_N_INSNS (1), /* fp_add */
808 COSTS_N_INSNS (1), /* fp_mult_sf */
809 COSTS_N_INSNS (1), /* fp_mult_df */
810 COSTS_N_INSNS (1), /* fp_div_sf */
811 COSTS_N_INSNS (1), /* fp_div_df */
812 COSTS_N_INSNS (1), /* int_mult_si */
813 COSTS_N_INSNS (1), /* int_mult_di */
814 COSTS_N_INSNS (1), /* int_div_si */
815 COSTS_N_INSNS (1), /* int_div_di */
817 4 /* memory_latency */
820 /* Costs to use when optimizing for speed, indexed by processor. */
821 static const struct mips_rtx_cost_data
822 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
824 COSTS_N_INSNS (2), /* fp_add */
825 COSTS_N_INSNS (4), /* fp_mult_sf */
826 COSTS_N_INSNS (5), /* fp_mult_df */
827 COSTS_N_INSNS (12), /* fp_div_sf */
828 COSTS_N_INSNS (19), /* fp_div_df */
829 COSTS_N_INSNS (12), /* int_mult_si */
830 COSTS_N_INSNS (12), /* int_mult_di */
831 COSTS_N_INSNS (35), /* int_div_si */
832 COSTS_N_INSNS (35), /* int_div_di */
834 4 /* memory_latency */
838 COSTS_N_INSNS (6), /* int_mult_si */
839 COSTS_N_INSNS (6), /* int_mult_di */
840 COSTS_N_INSNS (36), /* int_div_si */
841 COSTS_N_INSNS (36), /* int_div_di */
843 4 /* memory_latency */
847 COSTS_N_INSNS (36), /* int_mult_si */
848 COSTS_N_INSNS (36), /* int_mult_di */
849 COSTS_N_INSNS (37), /* int_div_si */
850 COSTS_N_INSNS (37), /* int_div_di */
852 4 /* memory_latency */
856 COSTS_N_INSNS (4), /* int_mult_si */
857 COSTS_N_INSNS (11), /* int_mult_di */
858 COSTS_N_INSNS (36), /* int_div_si */
859 COSTS_N_INSNS (68), /* int_div_di */
861 4 /* memory_latency */
864 COSTS_N_INSNS (4), /* fp_add */
865 COSTS_N_INSNS (4), /* fp_mult_sf */
866 COSTS_N_INSNS (5), /* fp_mult_df */
867 COSTS_N_INSNS (17), /* fp_div_sf */
868 COSTS_N_INSNS (32), /* fp_div_df */
869 COSTS_N_INSNS (4), /* int_mult_si */
870 COSTS_N_INSNS (11), /* int_mult_di */
871 COSTS_N_INSNS (36), /* int_div_si */
872 COSTS_N_INSNS (68), /* int_div_di */
874 4 /* memory_latency */
877 COSTS_N_INSNS (4), /* fp_add */
878 COSTS_N_INSNS (4), /* fp_mult_sf */
879 COSTS_N_INSNS (5), /* fp_mult_df */
880 COSTS_N_INSNS (17), /* fp_div_sf */
881 COSTS_N_INSNS (32), /* fp_div_df */
882 COSTS_N_INSNS (4), /* int_mult_si */
883 COSTS_N_INSNS (7), /* int_mult_di */
884 COSTS_N_INSNS (42), /* int_div_si */
885 COSTS_N_INSNS (72), /* int_div_di */
887 4 /* memory_latency */
891 COSTS_N_INSNS (5), /* int_mult_si */
892 COSTS_N_INSNS (5), /* int_mult_di */
893 COSTS_N_INSNS (41), /* int_div_si */
894 COSTS_N_INSNS (41), /* int_div_di */
896 4 /* memory_latency */
899 COSTS_N_INSNS (8), /* fp_add */
900 COSTS_N_INSNS (8), /* fp_mult_sf */
901 COSTS_N_INSNS (10), /* fp_mult_df */
902 COSTS_N_INSNS (34), /* fp_div_sf */
903 COSTS_N_INSNS (64), /* fp_div_df */
904 COSTS_N_INSNS (5), /* int_mult_si */
905 COSTS_N_INSNS (5), /* int_mult_di */
906 COSTS_N_INSNS (41), /* int_div_si */
907 COSTS_N_INSNS (41), /* int_div_di */
909 4 /* memory_latency */
912 COSTS_N_INSNS (4), /* fp_add */
913 COSTS_N_INSNS (4), /* fp_mult_sf */
914 COSTS_N_INSNS (5), /* fp_mult_df */
915 COSTS_N_INSNS (17), /* fp_div_sf */
916 COSTS_N_INSNS (32), /* fp_div_df */
917 COSTS_N_INSNS (5), /* int_mult_si */
918 COSTS_N_INSNS (5), /* int_mult_di */
919 COSTS_N_INSNS (41), /* int_div_si */
920 COSTS_N_INSNS (41), /* int_div_di */
922 4 /* memory_latency */
926 COSTS_N_INSNS (5), /* int_mult_si */
927 COSTS_N_INSNS (5), /* int_mult_di */
928 COSTS_N_INSNS (41), /* int_div_si */
929 COSTS_N_INSNS (41), /* int_div_di */
931 4 /* memory_latency */
934 COSTS_N_INSNS (8), /* fp_add */
935 COSTS_N_INSNS (8), /* fp_mult_sf */
936 COSTS_N_INSNS (10), /* fp_mult_df */
937 COSTS_N_INSNS (34), /* fp_div_sf */
938 COSTS_N_INSNS (64), /* fp_div_df */
939 COSTS_N_INSNS (5), /* int_mult_si */
940 COSTS_N_INSNS (5), /* int_mult_di */
941 COSTS_N_INSNS (41), /* int_div_si */
942 COSTS_N_INSNS (41), /* int_div_di */
944 4 /* memory_latency */
947 COSTS_N_INSNS (4), /* fp_add */
948 COSTS_N_INSNS (4), /* fp_mult_sf */
949 COSTS_N_INSNS (5), /* fp_mult_df */
950 COSTS_N_INSNS (17), /* fp_div_sf */
951 COSTS_N_INSNS (32), /* fp_div_df */
952 COSTS_N_INSNS (5), /* int_mult_si */
953 COSTS_N_INSNS (5), /* int_mult_di */
954 COSTS_N_INSNS (41), /* int_div_si */
955 COSTS_N_INSNS (41), /* int_div_di */
957 4 /* memory_latency */
960 COSTS_N_INSNS (6), /* fp_add */
961 COSTS_N_INSNS (6), /* fp_mult_sf */
962 COSTS_N_INSNS (7), /* fp_mult_df */
963 COSTS_N_INSNS (25), /* fp_div_sf */
964 COSTS_N_INSNS (48), /* fp_div_df */
965 COSTS_N_INSNS (5), /* int_mult_si */
966 COSTS_N_INSNS (5), /* int_mult_di */
967 COSTS_N_INSNS (41), /* int_div_si */
968 COSTS_N_INSNS (41), /* int_div_di */
970 4 /* memory_latency */
987 COSTS_N_INSNS (5), /* int_mult_si */
988 COSTS_N_INSNS (5), /* int_mult_di */
989 COSTS_N_INSNS (72), /* int_div_si */
990 COSTS_N_INSNS (72), /* int_div_di */
992 4 /* memory_latency */
995 COSTS_N_INSNS (2), /* fp_add */
996 COSTS_N_INSNS (4), /* fp_mult_sf */
997 COSTS_N_INSNS (5), /* fp_mult_df */
998 COSTS_N_INSNS (12), /* fp_div_sf */
999 COSTS_N_INSNS (19), /* fp_div_df */
1000 COSTS_N_INSNS (2), /* int_mult_si */
1001 COSTS_N_INSNS (2), /* int_mult_di */
1002 COSTS_N_INSNS (35), /* int_div_si */
1003 COSTS_N_INSNS (35), /* int_div_di */
1004 1, /* branch_cost */
1005 4 /* memory_latency */
1008 COSTS_N_INSNS (3), /* fp_add */
1009 COSTS_N_INSNS (5), /* fp_mult_sf */
1010 COSTS_N_INSNS (6), /* fp_mult_df */
1011 COSTS_N_INSNS (15), /* fp_div_sf */
1012 COSTS_N_INSNS (16), /* fp_div_df */
1013 COSTS_N_INSNS (17), /* int_mult_si */
1014 COSTS_N_INSNS (17), /* int_mult_di */
1015 COSTS_N_INSNS (38), /* int_div_si */
1016 COSTS_N_INSNS (38), /* int_div_di */
1017 2, /* branch_cost */
1018 6 /* memory_latency */
1021 COSTS_N_INSNS (6), /* fp_add */
1022 COSTS_N_INSNS (7), /* fp_mult_sf */
1023 COSTS_N_INSNS (8), /* fp_mult_df */
1024 COSTS_N_INSNS (23), /* fp_div_sf */
1025 COSTS_N_INSNS (36), /* fp_div_df */
1026 COSTS_N_INSNS (10), /* int_mult_si */
1027 COSTS_N_INSNS (10), /* int_mult_di */
1028 COSTS_N_INSNS (69), /* int_div_si */
1029 COSTS_N_INSNS (69), /* int_div_di */
1030 2, /* branch_cost */
1031 6 /* memory_latency */
1043 /* The only costs that appear to be updated here are
1044 integer multiplication. */
1046 COSTS_N_INSNS (4), /* int_mult_si */
1047 COSTS_N_INSNS (6), /* int_mult_di */
1048 COSTS_N_INSNS (69), /* int_div_si */
1049 COSTS_N_INSNS (69), /* int_div_di */
1050 1, /* branch_cost */
1051 4 /* memory_latency */
1063 COSTS_N_INSNS (6), /* fp_add */
1064 COSTS_N_INSNS (4), /* fp_mult_sf */
1065 COSTS_N_INSNS (5), /* fp_mult_df */
1066 COSTS_N_INSNS (23), /* fp_div_sf */
1067 COSTS_N_INSNS (36), /* fp_div_df */
1068 COSTS_N_INSNS (5), /* int_mult_si */
1069 COSTS_N_INSNS (5), /* int_mult_di */
1070 COSTS_N_INSNS (36), /* int_div_si */
1071 COSTS_N_INSNS (36), /* int_div_di */
1072 1, /* branch_cost */
1073 4 /* memory_latency */
1076 COSTS_N_INSNS (6), /* fp_add */
1077 COSTS_N_INSNS (5), /* fp_mult_sf */
1078 COSTS_N_INSNS (6), /* fp_mult_df */
1079 COSTS_N_INSNS (30), /* fp_div_sf */
1080 COSTS_N_INSNS (59), /* fp_div_df */
1081 COSTS_N_INSNS (3), /* int_mult_si */
1082 COSTS_N_INSNS (4), /* int_mult_di */
1083 COSTS_N_INSNS (42), /* int_div_si */
1084 COSTS_N_INSNS (74), /* int_div_di */
1085 1, /* branch_cost */
1086 4 /* memory_latency */
1089 COSTS_N_INSNS (6), /* fp_add */
1090 COSTS_N_INSNS (5), /* fp_mult_sf */
1091 COSTS_N_INSNS (6), /* fp_mult_df */
1092 COSTS_N_INSNS (30), /* fp_div_sf */
1093 COSTS_N_INSNS (59), /* fp_div_df */
1094 COSTS_N_INSNS (5), /* int_mult_si */
1095 COSTS_N_INSNS (9), /* int_mult_di */
1096 COSTS_N_INSNS (42), /* int_div_si */
1097 COSTS_N_INSNS (74), /* int_div_di */
1098 1, /* branch_cost */
1099 4 /* memory_latency */
1102 /* The only costs that are changed here are
1103 integer multiplication. */
1104 COSTS_N_INSNS (6), /* fp_add */
1105 COSTS_N_INSNS (7), /* fp_mult_sf */
1106 COSTS_N_INSNS (8), /* fp_mult_df */
1107 COSTS_N_INSNS (23), /* fp_div_sf */
1108 COSTS_N_INSNS (36), /* fp_div_df */
1109 COSTS_N_INSNS (5), /* int_mult_si */
1110 COSTS_N_INSNS (9), /* int_mult_di */
1111 COSTS_N_INSNS (69), /* int_div_si */
1112 COSTS_N_INSNS (69), /* int_div_di */
1113 1, /* branch_cost */
1114 4 /* memory_latency */
1120 /* The only costs that are changed here are
1121 integer multiplication. */
1122 COSTS_N_INSNS (6), /* fp_add */
1123 COSTS_N_INSNS (7), /* fp_mult_sf */
1124 COSTS_N_INSNS (8), /* fp_mult_df */
1125 COSTS_N_INSNS (23), /* fp_div_sf */
1126 COSTS_N_INSNS (36), /* fp_div_df */
1127 COSTS_N_INSNS (3), /* int_mult_si */
1128 COSTS_N_INSNS (8), /* int_mult_di */
1129 COSTS_N_INSNS (69), /* int_div_si */
1130 COSTS_N_INSNS (69), /* int_div_di */
1131 1, /* branch_cost */
1132 4 /* memory_latency */
1135 COSTS_N_INSNS (2), /* fp_add */
1136 COSTS_N_INSNS (2), /* fp_mult_sf */
1137 COSTS_N_INSNS (2), /* fp_mult_df */
1138 COSTS_N_INSNS (12), /* fp_div_sf */
1139 COSTS_N_INSNS (19), /* fp_div_df */
1140 COSTS_N_INSNS (5), /* int_mult_si */
1141 COSTS_N_INSNS (9), /* int_mult_di */
1142 COSTS_N_INSNS (34), /* int_div_si */
1143 COSTS_N_INSNS (66), /* int_div_di */
1144 1, /* branch_cost */
1145 4 /* memory_latency */
1148 /* These costs are the same as the SB-1A below. */
1149 COSTS_N_INSNS (4), /* fp_add */
1150 COSTS_N_INSNS (4), /* fp_mult_sf */
1151 COSTS_N_INSNS (4), /* fp_mult_df */
1152 COSTS_N_INSNS (24), /* fp_div_sf */
1153 COSTS_N_INSNS (32), /* fp_div_df */
1154 COSTS_N_INSNS (3), /* int_mult_si */
1155 COSTS_N_INSNS (4), /* int_mult_di */
1156 COSTS_N_INSNS (36), /* int_div_si */
1157 COSTS_N_INSNS (68), /* int_div_di */
1158 1, /* branch_cost */
1159 4 /* memory_latency */
1162 /* These costs are the same as the SB-1 above. */
1163 COSTS_N_INSNS (4), /* fp_add */
1164 COSTS_N_INSNS (4), /* fp_mult_sf */
1165 COSTS_N_INSNS (4), /* fp_mult_df */
1166 COSTS_N_INSNS (24), /* fp_div_sf */
1167 COSTS_N_INSNS (32), /* fp_div_df */
1168 COSTS_N_INSNS (3), /* int_mult_si */
1169 COSTS_N_INSNS (4), /* int_mult_di */
1170 COSTS_N_INSNS (36), /* int_div_si */
1171 COSTS_N_INSNS (68), /* int_div_di */
1172 1, /* branch_cost */
1173 4 /* memory_latency */
1180 COSTS_N_INSNS (8), /* int_mult_si */
1181 COSTS_N_INSNS (8), /* int_mult_di */
1182 COSTS_N_INSNS (72), /* int_div_si */
1183 COSTS_N_INSNS (72), /* int_div_di */
1184 1, /* branch_cost */
1185 4 /* memory_latency */
1189 static rtx mips_find_pic_call_symbol (rtx, rtx);
1190 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1192 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1194 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1195 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1196 struct GTY (()) mflip_mips16_entry {
1200 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1202 /* Hash table callbacks for mflip_mips16_htab. */
1205 mflip_mips16_htab_hash (const void *entry)
1207 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1211 mflip_mips16_htab_eq (const void *entry, const void *name)
1213 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1214 (const char *) name) == 0;
1217 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1218 mode, false if it should next add an attribute for the opposite mode. */
1219 static GTY(()) bool mips16_flipper;
1221 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1222 for -mflip-mips16. Return true if it should use "mips16" and false if
1223 it should use "nomips16". */
1226 mflip_mips16_use_mips16_p (tree decl)
1228 struct mflip_mips16_entry *entry;
1233 /* Use the opposite of the command-line setting for anonymous decls. */
1234 if (!DECL_NAME (decl))
1235 return !mips_base_mips16;
1237 if (!mflip_mips16_htab)
1238 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1239 mflip_mips16_htab_eq, NULL);
1241 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1242 hash = htab_hash_string (name);
1243 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1244 entry = (struct mflip_mips16_entry *) *slot;
1247 mips16_flipper = !mips16_flipper;
1248 entry = ggc_alloc_mflip_mips16_entry ();
1250 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1253 return entry->mips16_p;
1256 /* Predicates to test for presence of "near" and "far"/"long_call"
1257 attributes on the given TYPE. */
1260 mips_near_type_p (const_tree type)
1262 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1266 mips_far_type_p (const_tree type)
1268 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1269 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1272 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1275 mips_mips16_decl_p (const_tree decl)
1277 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1281 mips_nomips16_decl_p (const_tree decl)
1283 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1286 /* Check if the interrupt attribute is set for a function. */
1289 mips_interrupt_type_p (tree type)
1291 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1294 /* Check if the attribute to use shadow register set is set for a function. */
1297 mips_use_shadow_register_set_p (tree type)
1299 return lookup_attribute ("use_shadow_register_set",
1300 TYPE_ATTRIBUTES (type)) != NULL;
1303 /* Check if the attribute to keep interrupts masked is set for a function. */
1306 mips_keep_interrupts_masked_p (tree type)
1308 return lookup_attribute ("keep_interrupts_masked",
1309 TYPE_ATTRIBUTES (type)) != NULL;
1312 /* Check if the attribute to use debug exception return is set for
1316 mips_use_debug_exception_return_p (tree type)
1318 return lookup_attribute ("use_debug_exception_return",
1319 TYPE_ATTRIBUTES (type)) != NULL;
1322 /* Return true if function DECL is a MIPS16 function. Return the ambient
1323 setting if DECL is null. */
1326 mips_use_mips16_mode_p (tree decl)
1330 /* Nested functions must use the same frame pointer as their
1331 parent and must therefore use the same ISA mode. */
1332 tree parent = decl_function_context (decl);
1335 if (mips_mips16_decl_p (decl))
1337 if (mips_nomips16_decl_p (decl))
1340 return mips_base_mips16;
1343 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1346 mips_comp_type_attributes (const_tree type1, const_tree type2)
1348 /* Disallow mixed near/far attributes. */
1349 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1351 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1356 /* Implement TARGET_INSERT_ATTRIBUTES. */
1359 mips_insert_attributes (tree decl, tree *attributes)
1362 bool mips16_p, nomips16_p;
1364 /* Check for "mips16" and "nomips16" attributes. */
1365 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1366 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1367 if (TREE_CODE (decl) != FUNCTION_DECL)
1370 error ("%qs attribute only applies to functions", "mips16");
1372 error ("%qs attribute only applies to functions", "nomips16");
1376 mips16_p |= mips_mips16_decl_p (decl);
1377 nomips16_p |= mips_nomips16_decl_p (decl);
1378 if (mips16_p || nomips16_p)
1380 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1381 if (mips16_p && nomips16_p)
1382 error ("%qE cannot have both %<mips16%> and "
1383 "%<nomips16%> attributes",
1386 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1388 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1389 "mips16" attribute, arbitrarily pick one. We must pick the same
1390 setting for duplicate declarations of a function. */
1391 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1392 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1397 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1400 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1402 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1403 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1404 error ("%qE redeclared with conflicting %qs attributes",
1405 DECL_NAME (newdecl), "mips16");
1406 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1407 error ("%qE redeclared with conflicting %qs attributes",
1408 DECL_NAME (newdecl), "nomips16");
1410 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1411 DECL_ATTRIBUTES (newdecl));
1414 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1415 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1418 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1420 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1422 *base_ptr = XEXP (x, 0);
1423 *offset_ptr = INTVAL (XEXP (x, 1));
1432 static unsigned int mips_build_integer (struct mips_integer_op *,
1433 unsigned HOST_WIDE_INT);
1435 /* A subroutine of mips_build_integer, with the same interface.
1436 Assume that the final action in the sequence should be a left shift. */
1439 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1441 unsigned int i, shift;
1443 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1444 since signed numbers are easier to load than unsigned ones. */
1446 while ((value & 1) == 0)
1447 value /= 2, shift++;
1449 i = mips_build_integer (codes, value);
1450 codes[i].code = ASHIFT;
1451 codes[i].value = shift;
1455 /* As for mips_build_shift, but assume that the final action will be
1456 an IOR or PLUS operation. */
1459 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1461 unsigned HOST_WIDE_INT high;
1464 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1465 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1467 /* The constant is too complex to load with a simple LUI/ORI pair,
1468 so we want to give the recursive call as many trailing zeros as
1469 possible. In this case, we know bit 16 is set and that the
1470 low 16 bits form a negative number. If we subtract that number
1471 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1472 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1473 codes[i].code = PLUS;
1474 codes[i].value = CONST_LOW_PART (value);
1478 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1479 bits gives a value with at least 17 trailing zeros. */
1480 i = mips_build_integer (codes, high);
1481 codes[i].code = IOR;
1482 codes[i].value = value & 0xffff;
1487 /* Fill CODES with a sequence of rtl operations to load VALUE.
1488 Return the number of operations needed. */
1491 mips_build_integer (struct mips_integer_op *codes,
1492 unsigned HOST_WIDE_INT value)
1494 if (SMALL_OPERAND (value)
1495 || SMALL_OPERAND_UNSIGNED (value)
1496 || LUI_OPERAND (value))
1498 /* The value can be loaded with a single instruction. */
1499 codes[0].code = UNKNOWN;
1500 codes[0].value = value;
1503 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1505 /* Either the constant is a simple LUI/ORI combination or its
1506 lowest bit is set. We don't want to shift in this case. */
1507 return mips_build_lower (codes, value);
1509 else if ((value & 0xffff) == 0)
1511 /* The constant will need at least three actions. The lowest
1512 16 bits are clear, so the final action will be a shift. */
1513 return mips_build_shift (codes, value);
1517 /* The final action could be a shift, add or inclusive OR.
1518 Rather than use a complex condition to select the best
1519 approach, try both mips_build_shift and mips_build_lower
1520 and pick the one that gives the shortest sequence.
1521 Note that this case is only used once per constant. */
1522 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1523 unsigned int cost, alt_cost;
1525 cost = mips_build_shift (codes, value);
1526 alt_cost = mips_build_lower (alt_codes, value);
1527 if (alt_cost < cost)
1529 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1536 /* Return true if symbols of type TYPE require a GOT access. */
1539 mips_got_symbol_type_p (enum mips_symbol_type type)
1543 case SYMBOL_GOT_PAGE_OFST:
1544 case SYMBOL_GOT_DISP:
1552 /* Return true if X is a thread-local symbol. */
1555 mips_tls_symbol_p (rtx x)
1557 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1560 /* Return true if SYMBOL_REF X is associated with a global symbol
1561 (in the STB_GLOBAL sense). */
1564 mips_global_symbol_p (const_rtx x)
1566 const_tree decl = SYMBOL_REF_DECL (x);
1569 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1571 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1572 or weak symbols. Relocations in the object file will be against
1573 the target symbol, so it's that symbol's binding that matters here. */
1574 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1577 /* Return true if function X is a libgcc MIPS16 stub function. */
1580 mips16_stub_function_p (const_rtx x)
1582 return (GET_CODE (x) == SYMBOL_REF
1583 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1586 /* Return true if function X is a locally-defined and locally-binding
1590 mips16_local_function_p (const_rtx x)
1592 return (GET_CODE (x) == SYMBOL_REF
1593 && SYMBOL_REF_LOCAL_P (x)
1594 && !SYMBOL_REF_EXTERNAL_P (x)
1595 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1598 /* Return true if SYMBOL_REF X binds locally. */
1601 mips_symbol_binds_local_p (const_rtx x)
1603 return (SYMBOL_REF_DECL (x)
1604 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1605 : SYMBOL_REF_LOCAL_P (x));
1608 /* Return true if rtx constants of mode MODE should be put into a small
1612 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1614 return (!TARGET_EMBEDDED_DATA
1615 && TARGET_LOCAL_SDATA
1616 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1619 /* Return true if X should not be moved directly into register $25.
1620 We need this because many versions of GAS will treat "la $25,foo" as
1621 part of a call sequence and so allow a global "foo" to be lazily bound. */
1624 mips_dangerous_for_la25_p (rtx x)
1626 return (!TARGET_EXPLICIT_RELOCS
1628 && GET_CODE (x) == SYMBOL_REF
1629 && mips_global_symbol_p (x));
1632 /* Return true if calls to X might need $25 to be valid on entry. */
1635 mips_use_pic_fn_addr_reg_p (const_rtx x)
1637 if (!TARGET_USE_PIC_FN_ADDR_REG)
1640 /* MIPS16 stub functions are guaranteed not to use $25. */
1641 if (mips16_stub_function_p (x))
1644 if (GET_CODE (x) == SYMBOL_REF)
1646 /* If PLTs and copy relocations are available, the static linker
1647 will make sure that $25 is valid on entry to the target function. */
1648 if (TARGET_ABICALLS_PIC0)
1651 /* Locally-defined functions use absolute accesses to set up
1652 the global pointer. */
1653 if (TARGET_ABSOLUTE_ABICALLS
1654 && mips_symbol_binds_local_p (x)
1655 && !SYMBOL_REF_EXTERNAL_P (x))
1662 /* Return the method that should be used to access SYMBOL_REF or
1663 LABEL_REF X in context CONTEXT. */
1665 static enum mips_symbol_type
1666 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1669 return SYMBOL_GOT_DISP;
1671 if (GET_CODE (x) == LABEL_REF)
1673 /* LABEL_REFs are used for jump tables as well as text labels.
1674 Only return SYMBOL_PC_RELATIVE if we know the label is in
1675 the text section. */
1676 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1677 return SYMBOL_PC_RELATIVE;
1679 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1680 return SYMBOL_GOT_PAGE_OFST;
1682 return SYMBOL_ABSOLUTE;
1685 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1687 if (SYMBOL_REF_TLS_MODEL (x))
1690 if (CONSTANT_POOL_ADDRESS_P (x))
1692 if (TARGET_MIPS16_TEXT_LOADS)
1693 return SYMBOL_PC_RELATIVE;
1695 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1696 return SYMBOL_PC_RELATIVE;
1698 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1699 return SYMBOL_GP_RELATIVE;
1702 /* Do not use small-data accesses for weak symbols; they may end up
1704 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1705 return SYMBOL_GP_RELATIVE;
1707 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1709 if (TARGET_ABICALLS_PIC2
1710 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1712 /* There are three cases to consider:
1714 - o32 PIC (either with or without explicit relocs)
1715 - n32/n64 PIC without explicit relocs
1716 - n32/n64 PIC with explicit relocs
1718 In the first case, both local and global accesses will use an
1719 R_MIPS_GOT16 relocation. We must correctly predict which of
1720 the two semantics (local or global) the assembler and linker
1721 will apply. The choice depends on the symbol's binding rather
1722 than its visibility.
1724 In the second case, the assembler will not use R_MIPS_GOT16
1725 relocations, but it chooses between local and global accesses
1726 in the same way as for o32 PIC.
1728 In the third case we have more freedom since both forms of
1729 access will work for any kind of symbol. However, there seems
1730 little point in doing things differently. */
1731 if (mips_global_symbol_p (x))
1732 return SYMBOL_GOT_DISP;
1734 return SYMBOL_GOT_PAGE_OFST;
1737 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1738 return SYMBOL_FORCE_TO_MEM;
1740 return SYMBOL_ABSOLUTE;
1743 /* Classify the base of symbolic expression X, given that X appears in
1746 static enum mips_symbol_type
1747 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1751 split_const (x, &x, &offset);
1752 if (UNSPEC_ADDRESS_P (x))
1753 return UNSPEC_ADDRESS_TYPE (x);
1755 return mips_classify_symbol (x, context);
1758 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1759 is the alignment in bytes of SYMBOL_REF X. */
1762 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1764 HOST_WIDE_INT align;
1766 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1767 return IN_RANGE (offset, 0, align - 1);
1770 /* Return true if X is a symbolic constant that can be used in context
1771 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1774 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1775 enum mips_symbol_type *symbol_type)
1779 split_const (x, &x, &offset);
1780 if (UNSPEC_ADDRESS_P (x))
1782 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1783 x = UNSPEC_ADDRESS (x);
1785 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1787 *symbol_type = mips_classify_symbol (x, context);
1788 if (*symbol_type == SYMBOL_TLS)
1794 if (offset == const0_rtx)
1797 /* Check whether a nonzero offset is valid for the underlying
1799 switch (*symbol_type)
1801 case SYMBOL_ABSOLUTE:
1802 case SYMBOL_FORCE_TO_MEM:
1803 case SYMBOL_32_HIGH:
1804 case SYMBOL_64_HIGH:
1807 /* If the target has 64-bit pointers and the object file only
1808 supports 32-bit symbols, the values of those symbols will be
1809 sign-extended. In this case we can't allow an arbitrary offset
1810 in case the 32-bit value X + OFFSET has a different sign from X. */
1811 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1812 return offset_within_block_p (x, INTVAL (offset));
1814 /* In other cases the relocations can handle any offset. */
1817 case SYMBOL_PC_RELATIVE:
1818 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1819 In this case, we no longer have access to the underlying constant,
1820 but the original symbol-based access was known to be valid. */
1821 if (GET_CODE (x) == LABEL_REF)
1826 case SYMBOL_GP_RELATIVE:
1827 /* Make sure that the offset refers to something within the
1828 same object block. This should guarantee that the final
1829 PC- or GP-relative offset is within the 16-bit limit. */
1830 return offset_within_block_p (x, INTVAL (offset));
1832 case SYMBOL_GOT_PAGE_OFST:
1833 case SYMBOL_GOTOFF_PAGE:
1834 /* If the symbol is global, the GOT entry will contain the symbol's
1835 address, and we will apply a 16-bit offset after loading it.
1836 If the symbol is local, the linker should provide enough local
1837 GOT entries for a 16-bit offset, but larger offsets may lead
1839 return SMALL_INT (offset);
1843 /* There is no carry between the HI and LO REL relocations, so the
1844 offset is only valid if we know it won't lead to such a carry. */
1845 return mips_offset_within_alignment_p (x, INTVAL (offset));
1847 case SYMBOL_GOT_DISP:
1848 case SYMBOL_GOTOFF_DISP:
1849 case SYMBOL_GOTOFF_CALL:
1850 case SYMBOL_GOTOFF_LOADGP:
1853 case SYMBOL_GOTTPREL:
1861 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1862 single instruction. We rely on the fact that, in the worst case,
1863 all instructions involved in a MIPS16 address calculation are usually
1867 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1871 case SYMBOL_ABSOLUTE:
1872 /* When using 64-bit symbols, we need 5 preparatory instructions,
1875 lui $at,%highest(symbol)
1876 daddiu $at,$at,%higher(symbol)
1878 daddiu $at,$at,%hi(symbol)
1881 The final address is then $at + %lo(symbol). With 32-bit
1882 symbols we just need a preparatory LUI for normal mode and
1883 a preparatory LI and SLL for MIPS16. */
1884 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1886 case SYMBOL_GP_RELATIVE:
1887 /* Treat GP-relative accesses as taking a single instruction on
1888 MIPS16 too; the copy of $gp can often be shared. */
1891 case SYMBOL_PC_RELATIVE:
1892 /* PC-relative constants can be only be used with ADDIUPC,
1893 DADDIUPC, LWPC and LDPC. */
1894 if (mode == MAX_MACHINE_MODE
1895 || GET_MODE_SIZE (mode) == 4
1896 || GET_MODE_SIZE (mode) == 8)
1899 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1902 case SYMBOL_FORCE_TO_MEM:
1903 /* LEAs will be converted into constant-pool references by
1905 if (mode == MAX_MACHINE_MODE)
1908 /* The constant must be loaded and then dereferenced. */
1911 case SYMBOL_GOT_DISP:
1912 /* The constant will have to be loaded from the GOT before it
1913 is used in an address. */
1914 if (mode != MAX_MACHINE_MODE)
1919 case SYMBOL_GOT_PAGE_OFST:
1920 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1921 local/global classification is accurate. The worst cases are:
1923 (1) For local symbols when generating o32 or o64 code. The assembler
1929 ...and the final address will be $at + %lo(symbol).
1931 (2) For global symbols when -mxgot. The assembler will use:
1933 lui $at,%got_hi(symbol)
1936 ...and the final address will be $at + %got_lo(symbol). */
1939 case SYMBOL_GOTOFF_PAGE:
1940 case SYMBOL_GOTOFF_DISP:
1941 case SYMBOL_GOTOFF_CALL:
1942 case SYMBOL_GOTOFF_LOADGP:
1943 case SYMBOL_32_HIGH:
1944 case SYMBOL_64_HIGH:
1950 case SYMBOL_GOTTPREL:
1953 /* A 16-bit constant formed by a single relocation, or a 32-bit
1954 constant formed from a high 16-bit relocation and a low 16-bit
1955 relocation. Use mips_split_p to determine which. 32-bit
1956 constants need an "lui; addiu" sequence for normal mode and
1957 an "li; sll; addiu" sequence for MIPS16 mode. */
1958 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1961 /* We don't treat a bare TLS symbol as a constant. */
1967 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1968 to load symbols of type TYPE into a register. Return 0 if the given
1969 type of symbol cannot be used as an immediate operand.
1971 Otherwise, return the number of instructions needed to load or store
1972 values of mode MODE to or from addresses of type TYPE. Return 0 if
1973 the given type of symbol is not valid in addresses.
1975 In both cases, treat extended MIPS16 instructions as two instructions. */
1978 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1980 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1983 /* A for_each_rtx callback. Stop the search if *X references a
1984 thread-local symbol. */
1987 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1989 return mips_tls_symbol_p (*x);
1992 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1995 mips_cannot_force_const_mem (rtx x)
1997 enum mips_symbol_type type;
2000 /* There is no assembler syntax for expressing an address-sized
2002 if (GET_CODE (x) == HIGH)
2005 /* As an optimization, reject constants that mips_legitimize_move
2008 Suppose we have a multi-instruction sequence that loads constant C
2009 into register R. If R does not get allocated a hard register, and
2010 R is used in an operand that allows both registers and memory
2011 references, reload will consider forcing C into memory and using
2012 one of the instruction's memory alternatives. Returning false
2013 here will force it to use an input reload instead. */
2014 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
2017 split_const (x, &base, &offset);
2018 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
2019 && type != SYMBOL_FORCE_TO_MEM)
2021 /* The same optimization as for CONST_INT. */
2022 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2025 /* If MIPS16 constant pools live in the text section, they should
2026 not refer to anything that might need run-time relocation. */
2027 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2031 /* TLS symbols must be computed by mips_legitimize_move. */
2032 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2038 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2039 constants when we're using a per-function constant pool. */
2042 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2043 const_rtx x ATTRIBUTE_UNUSED)
2045 return !TARGET_MIPS16_PCREL_LOADS;
2048 /* Return true if register REGNO is a valid base register for mode MODE.
2049 STRICT_P is true if REG_OK_STRICT is in effect. */
2052 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2055 if (!HARD_REGISTER_NUM_P (regno))
2059 regno = reg_renumber[regno];
2062 /* These fake registers will be eliminated to either the stack or
2063 hard frame pointer, both of which are usually valid base registers.
2064 Reload deals with the cases where the eliminated form isn't valid. */
2065 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2068 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2069 values, nothing smaller. There are two problems here:
2071 (a) Instantiating virtual registers can introduce new uses of the
2072 stack pointer. If these virtual registers are valid addresses,
2073 the stack pointer should be too.
2075 (b) Most uses of the stack pointer are not made explicit until
2076 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2077 We don't know until that stage whether we'll be eliminating to the
2078 stack pointer (which needs the restriction) or the hard frame
2079 pointer (which doesn't).
2081 All in all, it seems more consistent to only enforce this restriction
2082 during and after reload. */
2083 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2084 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2086 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2089 /* Return true if X is a valid base register for mode MODE.
2090 STRICT_P is true if REG_OK_STRICT is in effect. */
2093 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2095 if (!strict_p && GET_CODE (x) == SUBREG)
2099 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2102 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2103 can address a value of mode MODE. */
2106 mips_valid_offset_p (rtx x, enum machine_mode mode)
2108 /* Check that X is a signed 16-bit number. */
2109 if (!const_arith_operand (x, Pmode))
2112 /* We may need to split multiword moves, so make sure that every word
2114 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2115 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2121 /* Return true if a LO_SUM can address a value of mode MODE when the
2122 LO_SUM symbol has type SYMBOL_TYPE. */
2125 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2127 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2129 if (mips_symbol_insns (symbol_type, mode) == 0)
2132 /* Check that there is a known low-part relocation. */
2133 if (mips_lo_relocs[symbol_type] == NULL)
2136 /* We may need to split multiword moves, so make sure that each word
2137 can be accessed without inducing a carry. This is mainly needed
2138 for o64, which has historically only guaranteed 64-bit alignment
2139 for 128-bit types. */
2140 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2141 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2147 /* Return true if X is a valid address for machine mode MODE. If it is,
2148 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2152 mips_classify_address (struct mips_address_info *info, rtx x,
2153 enum machine_mode mode, bool strict_p)
2155 switch (GET_CODE (x))
2159 info->type = ADDRESS_REG;
2161 info->offset = const0_rtx;
2162 return mips_valid_base_register_p (info->reg, mode, strict_p);
2165 info->type = ADDRESS_REG;
2166 info->reg = XEXP (x, 0);
2167 info->offset = XEXP (x, 1);
2168 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2169 && mips_valid_offset_p (info->offset, mode));
2172 info->type = ADDRESS_LO_SUM;
2173 info->reg = XEXP (x, 0);
2174 info->offset = XEXP (x, 1);
2175 /* We have to trust the creator of the LO_SUM to do something vaguely
2176 sane. Target-independent code that creates a LO_SUM should also
2177 create and verify the matching HIGH. Target-independent code that
2178 adds an offset to a LO_SUM must prove that the offset will not
2179 induce a carry. Failure to do either of these things would be
2180 a bug, and we are not required to check for it here. The MIPS
2181 backend itself should only create LO_SUMs for valid symbolic
2182 constants, with the high part being either a HIGH or a copy
2185 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2186 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2187 && mips_valid_lo_sum_p (info->symbol_type, mode));
2190 /* Small-integer addresses don't occur very often, but they
2191 are legitimate if $0 is a valid base register. */
2192 info->type = ADDRESS_CONST_INT;
2193 return !TARGET_MIPS16 && SMALL_INT (x);
2198 info->type = ADDRESS_SYMBOLIC;
2199 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2201 && mips_symbol_insns (info->symbol_type, mode) > 0
2202 && !mips_split_p[info->symbol_type]);
2209 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2212 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2214 struct mips_address_info addr;
2216 return mips_classify_address (&addr, x, mode, strict_p);
2219 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2222 mips_stack_address_p (rtx x, enum machine_mode mode)
2224 struct mips_address_info addr;
2226 return (mips_classify_address (&addr, x, mode, false)
2227 && addr.type == ADDRESS_REG
2228 && addr.reg == stack_pointer_rtx);
2231 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2232 address instruction. Note that such addresses are not considered
2233 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2234 is so restricted. */
2237 mips_lwxs_address_p (rtx addr)
2240 && GET_CODE (addr) == PLUS
2241 && REG_P (XEXP (addr, 1)))
2243 rtx offset = XEXP (addr, 0);
2244 if (GET_CODE (offset) == MULT
2245 && REG_P (XEXP (offset, 0))
2246 && CONST_INT_P (XEXP (offset, 1))
2247 && INTVAL (XEXP (offset, 1)) == 4)
2253 /* Return true if a value at OFFSET bytes from base register BASE can be
2254 accessed using an unextended MIPS16 instruction. MODE is the mode of
2257 Usually the offset in an unextended instruction is a 5-bit field.
2258 The offset is unsigned and shifted left once for LH and SH, twice
2259 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2260 an 8-bit immediate field that's shifted left twice. */
2263 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2264 unsigned HOST_WIDE_INT offset)
2266 if (offset % GET_MODE_SIZE (mode) == 0)
2268 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2269 return offset < 256U * GET_MODE_SIZE (mode);
2270 return offset < 32U * GET_MODE_SIZE (mode);
2275 /* Return the number of instructions needed to load or store a value
2276 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2277 Assume that multiword moves may need to be split into word moves
2278 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2281 For MIPS16 code, count extended instructions as two instructions. */
2284 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2286 struct mips_address_info addr;
2289 /* BLKmode is used for single unaligned loads and stores and should
2290 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2291 meaningless, so we have to single it out as a special case one way
2293 if (mode != BLKmode && might_split_p)
2294 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2298 if (mips_classify_address (&addr, x, mode, false))
2303 && !mips16_unextended_reference_p (mode, addr.reg,
2304 UINTVAL (addr.offset)))
2308 case ADDRESS_LO_SUM:
2309 return TARGET_MIPS16 ? factor * 2 : factor;
2311 case ADDRESS_CONST_INT:
2314 case ADDRESS_SYMBOLIC:
2315 return factor * mips_symbol_insns (addr.symbol_type, mode);
2320 /* Return the number of instructions needed to load constant X.
2321 Return 0 if X isn't a valid constant. */
2324 mips_const_insns (rtx x)
2326 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2327 enum mips_symbol_type symbol_type;
2330 switch (GET_CODE (x))
2333 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2335 || !mips_split_p[symbol_type])
2338 /* This is simply an LUI for normal mode. It is an extended
2339 LI followed by an extended SLL for MIPS16. */
2340 return TARGET_MIPS16 ? 4 : 1;
2344 /* Unsigned 8-bit constants can be loaded using an unextended
2345 LI instruction. Unsigned 16-bit constants can be loaded
2346 using an extended LI. Negative constants must be loaded
2347 using LI and then negated. */
2348 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2349 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2350 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2351 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2354 return mips_build_integer (codes, INTVAL (x));
2358 /* Allow zeros for normal mode, where we can use $0. */
2359 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2365 /* See if we can refer to X directly. */
2366 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2367 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2369 /* Otherwise try splitting the constant into a base and offset.
2370 If the offset is a 16-bit value, we can load the base address
2371 into a register and then use (D)ADDIU to add in the offset.
2372 If the offset is larger, we can load the base and offset
2373 into separate registers and add them together with (D)ADDU.
2374 However, the latter is only possible before reload; during
2375 and after reload, we must have the option of forcing the
2376 constant into the pool instead. */
2377 split_const (x, &x, &offset);
2380 int n = mips_const_insns (x);
2383 if (SMALL_INT (offset))
2385 else if (!targetm.cannot_force_const_mem (x))
2386 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2393 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2401 /* X is a doubleword constant that can be handled by splitting it into
2402 two words and loading each word separately. Return the number of
2403 instructions required to do this. */
2406 mips_split_const_insns (rtx x)
2408 unsigned int low, high;
2410 low = mips_const_insns (mips_subword (x, false));
2411 high = mips_const_insns (mips_subword (x, true));
2412 gcc_assert (low > 0 && high > 0);
2416 /* Return the number of instructions needed to implement INSN,
2417 given that it loads from or stores to MEM. Count extended
2418 MIPS16 instructions as two instructions. */
2421 mips_load_store_insns (rtx mem, rtx insn)
2423 enum machine_mode mode;
2427 gcc_assert (MEM_P (mem));
2428 mode = GET_MODE (mem);
2430 /* Try to prove that INSN does not need to be split. */
2431 might_split_p = true;
2432 if (GET_MODE_BITSIZE (mode) == 64)
2434 set = single_set (insn);
2435 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2436 might_split_p = false;
2439 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2442 /* Return the number of instructions needed for an integer division. */
2445 mips_idiv_insns (void)
2450 if (TARGET_CHECK_ZERO_DIV)
2452 if (GENERATE_DIVIDE_TRAPS)
2458 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2463 /* Emit a move from SRC to DEST. Assume that the move expanders can
2464 handle all moves if !can_create_pseudo_p (). The distinction is
2465 important because, unlike emit_move_insn, the move expanders know
2466 how to force Pmode objects into the constant pool even when the
2467 constant pool address is not itself legitimate. */
2470 mips_emit_move (rtx dest, rtx src)
2472 return (can_create_pseudo_p ()
2473 ? emit_move_insn (dest, src)
2474 : emit_move_insn_1 (dest, src));
2477 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2480 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2482 emit_insn (gen_rtx_SET (VOIDmode, target,
2483 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2486 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2487 Return that new register. */
2490 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2494 reg = gen_reg_rtx (mode);
2495 mips_emit_unary (code, reg, op0);
2499 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2502 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2504 emit_insn (gen_rtx_SET (VOIDmode, target,
2505 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2508 /* Compute (CODE OP0 OP1) and store the result in a new register
2509 of mode MODE. Return that new register. */
2512 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2516 reg = gen_reg_rtx (mode);
2517 mips_emit_binary (code, reg, op0, op1);
2521 /* Copy VALUE to a register and return that register. If new pseudos
2522 are allowed, copy it into a new register, otherwise use DEST. */
2525 mips_force_temporary (rtx dest, rtx value)
2527 if (can_create_pseudo_p ())
2528 return force_reg (Pmode, value);
2531 mips_emit_move (dest, value);
2536 /* Emit a call sequence with call pattern PATTERN and return the call
2537 instruction itself (which is not necessarily the last instruction
2538 emitted). ORIG_ADDR is the original, unlegitimized address,
2539 ADDR is the legitimized form, and LAZY_P is true if the call
2540 address is lazily-bound. */
2543 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2547 insn = emit_call_insn (pattern);
2549 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2551 /* MIPS16 JALRs only take MIPS16 registers. If the target
2552 function requires $25 to be valid on entry, we must copy it
2553 there separately. The move instruction can be put in the
2554 call's delay slot. */
2555 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2556 emit_insn_before (gen_move_insn (reg, addr), insn);
2557 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2561 /* Lazy-binding stubs require $gp to be valid on entry. */
2562 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2566 /* See the comment above load_call<mode> for details. */
2567 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2568 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2569 emit_insn (gen_update_got_version ());
2574 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2575 then add CONST_INT OFFSET to the result. */
2578 mips_unspec_address_offset (rtx base, rtx offset,
2579 enum mips_symbol_type symbol_type)
2581 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2582 UNSPEC_ADDRESS_FIRST + symbol_type);
2583 if (offset != const0_rtx)
2584 base = gen_rtx_PLUS (Pmode, base, offset);
2585 return gen_rtx_CONST (Pmode, base);
2588 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2589 type SYMBOL_TYPE. */
2592 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2596 split_const (address, &base, &offset);
2597 return mips_unspec_address_offset (base, offset, symbol_type);
2600 /* If OP is an UNSPEC address, return the address to which it refers,
2601 otherwise return OP itself. */
2604 mips_strip_unspec_address (rtx op)
2608 split_const (op, &base, &offset);
2609 if (UNSPEC_ADDRESS_P (base))
2610 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2614 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2615 high part to BASE and return the result. Just return BASE otherwise.
2616 TEMP is as for mips_force_temporary.
2618 The returned expression can be used as the first operand to a LO_SUM. */
2621 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2622 enum mips_symbol_type symbol_type)
2624 if (mips_split_p[symbol_type])
2626 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2627 addr = mips_force_temporary (temp, addr);
2628 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2633 /* Return an instruction that copies $gp into register REG. We want
2634 GCC to treat the register's value as constant, so that its value
2635 can be rematerialized on demand. */
2638 gen_load_const_gp (rtx reg)
2640 return (Pmode == SImode
2641 ? gen_load_const_gp_si (reg)
2642 : gen_load_const_gp_di (reg));
2645 /* Return a pseudo register that contains the value of $gp throughout
2646 the current function. Such registers are needed by MIPS16 functions,
2647 for which $gp itself is not a valid base register or addition operand. */
2650 mips16_gp_pseudo_reg (void)
2652 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2656 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2658 push_topmost_sequence ();
2660 scan = get_insns ();
2661 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2662 scan = NEXT_INSN (scan);
2664 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2665 emit_insn_after (insn, scan);
2667 pop_topmost_sequence ();
2670 return cfun->machine->mips16_gp_pseudo_rtx;
2673 /* Return a base register that holds pic_offset_table_rtx.
2674 TEMP, if nonnull, is a scratch Pmode base register. */
2677 mips_pic_base_register (rtx temp)
2680 return pic_offset_table_rtx;
2682 if (currently_expanding_to_rtl)
2683 return mips16_gp_pseudo_reg ();
2685 if (can_create_pseudo_p ())
2686 temp = gen_reg_rtx (Pmode);
2689 /* The first post-reload split exposes all references to $gp
2690 (both uses and definitions). All references must remain
2691 explicit after that point.
2693 It is safe to introduce uses of $gp at any time, so for
2694 simplicity, we do that before the split too. */
2695 mips_emit_move (temp, pic_offset_table_rtx);
2697 emit_insn (gen_load_const_gp (temp));
2701 /* Return the RHS of a load_call<mode> insn. */
2704 mips_unspec_call (rtx reg, rtx symbol)
2708 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2709 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2712 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2713 reference. Return NULL_RTX otherwise. */
2716 mips_strip_unspec_call (rtx src)
2718 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2719 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2723 /* Create and return a GOT reference of type TYPE for address ADDR.
2724 TEMP, if nonnull, is a scratch Pmode base register. */
2727 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2729 rtx base, high, lo_sum_symbol;
2731 base = mips_pic_base_register (temp);
2733 /* If we used the temporary register to load $gp, we can't use
2734 it for the high part as well. */
2735 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2738 high = mips_unspec_offset_high (temp, base, addr, type);
2739 lo_sum_symbol = mips_unspec_address (addr, type);
2741 if (type == SYMBOL_GOTOFF_CALL)
2742 return mips_unspec_call (high, lo_sum_symbol);
2744 return (Pmode == SImode
2745 ? gen_unspec_gotsi (high, lo_sum_symbol)
2746 : gen_unspec_gotdi (high, lo_sum_symbol));
2749 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2750 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2751 constant in that context and can be split into high and low parts.
2752 If so, and if LOW_OUT is nonnull, emit the high part and store the
2753 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2755 TEMP is as for mips_force_temporary and is used to load the high
2756 part into a register.
2758 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2759 a legitimize SET_SRC for an .md pattern, otherwise the low part
2760 is guaranteed to be a legitimate address for mode MODE. */
2763 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2765 enum mips_symbol_context context;
2766 enum mips_symbol_type symbol_type;
2769 context = (mode == MAX_MACHINE_MODE
2770 ? SYMBOL_CONTEXT_LEA
2771 : SYMBOL_CONTEXT_MEM);
2772 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2774 addr = XEXP (addr, 0);
2775 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2776 && mips_symbol_insns (symbol_type, mode) > 0
2777 && mips_split_hi_p[symbol_type])
2780 switch (symbol_type)
2782 case SYMBOL_GOT_PAGE_OFST:
2783 /* The high part of a page/ofst pair is loaded from the GOT. */
2784 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2795 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2796 && mips_symbol_insns (symbol_type, mode) > 0
2797 && mips_split_p[symbol_type])
2800 switch (symbol_type)
2802 case SYMBOL_GOT_DISP:
2803 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2804 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2807 case SYMBOL_GP_RELATIVE:
2808 high = mips_pic_base_register (temp);
2809 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2813 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2814 high = mips_force_temporary (temp, high);
2815 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2824 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2825 mips_force_temporary; it is only needed when OFFSET is not a
2829 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2831 if (!SMALL_OPERAND (offset))
2837 /* Load the full offset into a register so that we can use
2838 an unextended instruction for the address itself. */
2839 high = GEN_INT (offset);
2844 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2845 The addition inside the macro CONST_HIGH_PART may cause an
2846 overflow, so we need to force a sign-extension check. */
2847 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2848 offset = CONST_LOW_PART (offset);
2850 high = mips_force_temporary (temp, high);
2851 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2853 return plus_constant (reg, offset);
2856 /* The __tls_get_attr symbol. */
2857 static GTY(()) rtx mips_tls_symbol;
2859 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2860 the TLS symbol we are referencing and TYPE is the symbol type to use
2861 (either global dynamic or local dynamic). V0 is an RTX for the
2862 return value location. */
2865 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2869 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2871 if (!mips_tls_symbol)
2872 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2874 loc = mips_unspec_address (sym, type);
2878 emit_insn (gen_rtx_SET (Pmode, a0,
2879 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2880 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2881 const0_rtx, NULL_RTX, false);
2882 RTL_CONST_CALL_P (insn) = 1;
2883 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2884 insn = get_insns ();
2891 /* Return a pseudo register that contains the current thread pointer. */
2898 tp = gen_reg_rtx (Pmode);
2899 if (Pmode == DImode)
2900 emit_insn (gen_tls_get_tp_di (tp));
2902 emit_insn (gen_tls_get_tp_si (tp));
2906 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2907 its address. The return value will be both a valid address and a valid
2908 SET_SRC (either a REG or a LO_SUM). */
2911 mips_legitimize_tls_address (rtx loc)
2913 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2914 enum tls_model model;
2918 sorry ("MIPS16 TLS");
2919 return gen_reg_rtx (Pmode);
2922 model = SYMBOL_REF_TLS_MODEL (loc);
2923 /* Only TARGET_ABICALLS code can have more than one module; other
2924 code must be be static and should not use a GOT. All TLS models
2925 reduce to local exec in this situation. */
2926 if (!TARGET_ABICALLS)
2927 model = TLS_MODEL_LOCAL_EXEC;
2931 case TLS_MODEL_GLOBAL_DYNAMIC:
2932 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2933 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2934 dest = gen_reg_rtx (Pmode);
2935 emit_libcall_block (insn, dest, v0, loc);
2938 case TLS_MODEL_LOCAL_DYNAMIC:
2939 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2940 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2941 tmp1 = gen_reg_rtx (Pmode);
2943 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2944 share the LDM result with other LD model accesses. */
2945 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2947 emit_libcall_block (insn, tmp1, v0, eqv);
2949 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2950 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2951 mips_unspec_address (loc, SYMBOL_DTPREL));
2954 case TLS_MODEL_INITIAL_EXEC:
2955 tp = mips_get_tp ();
2956 tmp1 = gen_reg_rtx (Pmode);
2957 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2958 if (Pmode == DImode)
2959 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2961 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2962 dest = gen_reg_rtx (Pmode);
2963 emit_insn (gen_add3_insn (dest, tmp1, tp));
2966 case TLS_MODEL_LOCAL_EXEC:
2967 tp = mips_get_tp ();
2968 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2969 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2970 mips_unspec_address (loc, SYMBOL_TPREL));
2979 /* If X is not a valid address for mode MODE, force it into a register. */
2982 mips_force_address (rtx x, enum machine_mode mode)
2984 if (!mips_legitimate_address_p (mode, x, false))
2985 x = force_reg (Pmode, x);
2989 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2990 be legitimized in a way that the generic machinery might not expect,
2991 return a new address, otherwise return NULL. MODE is the mode of
2992 the memory being accessed. */
2995 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2996 enum machine_mode mode)
2999 HOST_WIDE_INT offset;
3001 if (mips_tls_symbol_p (x))
3002 return mips_legitimize_tls_address (x);
3004 /* See if the address can split into a high part and a LO_SUM. */
3005 if (mips_split_symbol (NULL, x, mode, &addr))
3006 return mips_force_address (addr, mode);
3008 /* Handle BASE + OFFSET using mips_add_offset. */
3009 mips_split_plus (x, &base, &offset);
3012 if (!mips_valid_base_register_p (base, mode, false))
3013 base = copy_to_mode_reg (Pmode, base);
3014 addr = mips_add_offset (NULL, base, offset);
3015 return mips_force_address (addr, mode);
3021 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3024 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3026 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3027 enum machine_mode mode;
3028 unsigned int i, num_ops;
3031 mode = GET_MODE (dest);
3032 num_ops = mips_build_integer (codes, value);
3034 /* Apply each binary operation to X. Invariant: X is a legitimate
3035 source operand for a SET pattern. */
3036 x = GEN_INT (codes[0].value);
3037 for (i = 1; i < num_ops; i++)
3039 if (!can_create_pseudo_p ())
3041 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3045 x = force_reg (mode, x);
3046 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3049 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3052 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3053 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3057 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3061 /* Split moves of big integers into smaller pieces. */
3062 if (splittable_const_int_operand (src, mode))
3064 mips_move_integer (dest, dest, INTVAL (src));
3068 /* Split moves of symbolic constants into high/low pairs. */
3069 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3071 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3075 /* Generate the appropriate access sequences for TLS symbols. */
3076 if (mips_tls_symbol_p (src))
3078 mips_emit_move (dest, mips_legitimize_tls_address (src));
3082 /* If we have (const (plus symbol offset)), and that expression cannot
3083 be forced into memory, load the symbol first and add in the offset.
3084 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3085 forced into memory, as it usually produces better code. */
3086 split_const (src, &base, &offset);
3087 if (offset != const0_rtx
3088 && (targetm.cannot_force_const_mem (src)
3089 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3091 base = mips_force_temporary (dest, base);
3092 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3096 src = force_const_mem (mode, src);
3098 /* When using explicit relocs, constant pool references are sometimes
3099 not legitimate addresses. */
3100 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3101 mips_emit_move (dest, src);
3104 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3105 sequence that is valid. */
3108 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3110 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3112 mips_emit_move (dest, force_reg (mode, src));
3116 /* We need to deal with constants that would be legitimate
3117 immediate_operands but aren't legitimate move_operands. */
3118 if (CONSTANT_P (src) && !move_operand (src, mode))
3120 mips_legitimize_const_move (mode, dest, src);
3121 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3127 /* Return true if value X in context CONTEXT is a small-data address
3128 that can be rewritten as a LO_SUM. */
3131 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3133 enum mips_symbol_type symbol_type;
3135 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3136 && !mips_split_p[SYMBOL_GP_RELATIVE]
3137 && mips_symbolic_constant_p (x, context, &symbol_type)
3138 && symbol_type == SYMBOL_GP_RELATIVE);
3141 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3142 containing MEM, or null if none. */
3145 mips_small_data_pattern_1 (rtx *loc, void *data)
3147 enum mips_symbol_context context;
3149 if (GET_CODE (*loc) == LO_SUM)
3154 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3159 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3160 return mips_rewrite_small_data_p (*loc, context);
3163 /* Return true if OP refers to small data symbols directly, not through
3167 mips_small_data_pattern_p (rtx op)
3169 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3172 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3173 DATA is the containing MEM, or null if none. */
3176 mips_rewrite_small_data_1 (rtx *loc, void *data)
3178 enum mips_symbol_context context;
3182 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3186 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3187 if (mips_rewrite_small_data_p (*loc, context))
3188 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3190 if (GET_CODE (*loc) == LO_SUM)
3196 /* Rewrite instruction pattern PATTERN so that it refers to small data
3197 using explicit relocations. */
3200 mips_rewrite_small_data (rtx pattern)
3202 pattern = copy_insn (pattern);
3203 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3207 /* We need a lot of little routines to check the range of MIPS16 immediate
3211 m16_check_op (rtx op, int low, int high, int mask)
3213 return (CONST_INT_P (op)
3214 && IN_RANGE (INTVAL (op), low, high)
3215 && (INTVAL (op) & mask) == 0);
3219 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3221 return m16_check_op (op, 0x1, 0x8, 0);
3225 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3227 return m16_check_op (op, -0x8, 0x7, 0);
3231 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3233 return m16_check_op (op, -0x7, 0x8, 0);
3237 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3239 return m16_check_op (op, -0x10, 0xf, 0);
3243 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3245 return m16_check_op (op, -0xf, 0x10, 0);
3249 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3251 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3255 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3257 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3261 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3263 return m16_check_op (op, -0x80, 0x7f, 0);
3267 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3269 return m16_check_op (op, -0x7f, 0x80, 0);
3273 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3275 return m16_check_op (op, 0x0, 0xff, 0);
3279 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3281 return m16_check_op (op, -0xff, 0x0, 0);
3285 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3287 return m16_check_op (op, -0x1, 0xfe, 0);
3291 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3293 return m16_check_op (op, 0x0, 0xff << 2, 3);
3297 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3299 return m16_check_op (op, -0xff << 2, 0x0, 3);
3303 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3305 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3309 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3311 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3314 /* The cost of loading values from the constant pool. It should be
3315 larger than the cost of any constant we want to synthesize inline. */
3316 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3318 /* Return the cost of X when used as an operand to the MIPS16 instruction
3319 that implements CODE. Return -1 if there is no such instruction, or if
3320 X is not a valid immediate operand for it. */
3323 mips16_constant_cost (int code, HOST_WIDE_INT x)
3330 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3331 other shifts are extended. The shift patterns truncate the shift
3332 count to the right size, so there are no out-of-range values. */
3333 if (IN_RANGE (x, 1, 8))
3335 return COSTS_N_INSNS (1);
3338 if (IN_RANGE (x, -128, 127))
3340 if (SMALL_OPERAND (x))
3341 return COSTS_N_INSNS (1);
3345 /* Like LE, but reject the always-true case. */
3349 /* We add 1 to the immediate and use SLT. */
3352 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3355 if (IN_RANGE (x, 0, 255))
3357 if (SMALL_OPERAND_UNSIGNED (x))
3358 return COSTS_N_INSNS (1);
3363 /* Equality comparisons with 0 are cheap. */
3373 /* Return true if there is a non-MIPS16 instruction that implements CODE
3374 and if that instruction accepts X as an immediate operand. */
3377 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3384 /* All shift counts are truncated to a valid constant. */
3389 /* Likewise rotates, if the target supports rotates at all. */
3395 /* These instructions take 16-bit unsigned immediates. */
3396 return SMALL_OPERAND_UNSIGNED (x);
3401 /* These instructions take 16-bit signed immediates. */
3402 return SMALL_OPERAND (x);
3408 /* The "immediate" forms of these instructions are really
3409 implemented as comparisons with register 0. */
3414 /* Likewise, meaning that the only valid immediate operand is 1. */
3418 /* We add 1 to the immediate and use SLT. */
3419 return SMALL_OPERAND (x + 1);
3422 /* Likewise SLTU, but reject the always-true case. */
3423 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3427 /* The bit position and size are immediate operands. */
3428 return ISA_HAS_EXT_INS;
3431 /* By default assume that $0 can be used for 0. */
3436 /* Return the cost of binary operation X, given that the instruction
3437 sequence for a word-sized or smaller operation has cost SINGLE_COST
3438 and that the sequence of a double-word operation has cost DOUBLE_COST.
3439 If SPEED is true, optimize for speed otherwise optimize for size. */
3442 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3446 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3451 + rtx_cost (XEXP (x, 0), SET, speed)
3452 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3455 /* Return the cost of floating-point multiplications of mode MODE. */
3458 mips_fp_mult_cost (enum machine_mode mode)
3460 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3463 /* Return the cost of floating-point divisions of mode MODE. */
3466 mips_fp_div_cost (enum machine_mode mode)
3468 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3471 /* Return the cost of sign-extending OP to mode MODE, not including the
3472 cost of OP itself. */
3475 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3478 /* Extended loads are as cheap as unextended ones. */
3481 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3482 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3485 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3486 /* We can use SEB or SEH. */
3487 return COSTS_N_INSNS (1);
3489 /* We need to use a shift left and a shift right. */
3490 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3493 /* Return the cost of zero-extending OP to mode MODE, not including the
3494 cost of OP itself. */
3497 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3500 /* Extended loads are as cheap as unextended ones. */
3503 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3504 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3505 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3507 if (GENERATE_MIPS16E)
3508 /* We can use ZEB or ZEH. */
3509 return COSTS_N_INSNS (1);
3512 /* We need to load 0xff or 0xffff into a register and use AND. */
3513 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3515 /* We can use ANDI. */
3516 return COSTS_N_INSNS (1);
3519 /* Implement TARGET_RTX_COSTS. */
3522 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3524 enum machine_mode mode = GET_MODE (x);
3525 bool float_mode_p = FLOAT_MODE_P (mode);
3529 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3530 appear in the instruction stream, and the cost of a comparison is
3531 really the cost of the branch or scc condition. At the time of
3532 writing, GCC only uses an explicit outer COMPARE code when optabs
3533 is testing whether a constant is expensive enough to force into a
3534 register. We want optabs to pass such constants through the MIPS
3535 expanders instead, so make all constants very cheap here. */
3536 if (outer_code == COMPARE)
3538 gcc_assert (CONSTANT_P (x));
3546 /* Treat *clear_upper32-style ANDs as having zero cost in the
3547 second operand. The cost is entirely in the first operand.
3549 ??? This is needed because we would otherwise try to CSE
3550 the constant operand. Although that's the right thing for
3551 instructions that continue to be a register operation throughout
3552 compilation, it is disastrous for instructions that could
3553 later be converted into a memory operation. */
3555 && outer_code == AND
3556 && UINTVAL (x) == 0xffffffff)
3564 cost = mips16_constant_cost (outer_code, INTVAL (x));
3573 /* When not optimizing for size, we care more about the cost
3574 of hot code, and hot code is often in a loop. If a constant
3575 operand needs to be forced into a register, we will often be
3576 able to hoist the constant load out of the loop, so the load
3577 should not contribute to the cost. */
3578 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3590 if (force_to_mem_operand (x, VOIDmode))
3592 *total = COSTS_N_INSNS (1);
3595 cost = mips_const_insns (x);
3598 /* If the constant is likely to be stored in a GPR, SETs of
3599 single-insn constants are as cheap as register sets; we
3600 never want to CSE them.
3602 Don't reduce the cost of storing a floating-point zero in
3603 FPRs. If we have a zero in an FPR for other reasons, we
3604 can get better cfg-cleanup and delayed-branch results by
3605 using it consistently, rather than using $0 sometimes and
3606 an FPR at other times. Also, moves between floating-point
3607 registers are sometimes cheaper than (D)MTC1 $0. */
3609 && outer_code == SET
3610 && !(float_mode_p && TARGET_HARD_FLOAT))
3612 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3613 want to CSE the constant itself. It is usually better to
3614 have N copies of the last operation in the sequence and one
3615 shared copy of the other operations. (Note that this is
3616 not true for MIPS16 code, where the final operation in the
3617 sequence is often an extended instruction.)
3619 Also, if we have a CONST_INT, we don't know whether it is
3620 for a word or doubleword operation, so we cannot rely on
3621 the result of mips_build_integer. */
3622 else if (!TARGET_MIPS16
3623 && (outer_code == SET || mode == VOIDmode))
3625 *total = COSTS_N_INSNS (cost);
3628 /* The value will need to be fetched from the constant pool. */
3629 *total = CONSTANT_POOL_COST;
3633 /* If the address is legitimate, return the number of
3634 instructions it needs. */
3636 cost = mips_address_insns (addr, mode, true);
3639 *total = COSTS_N_INSNS (cost + 1);
3642 /* Check for a scaled indexed address. */
3643 if (mips_lwxs_address_p (addr))
3645 *total = COSTS_N_INSNS (2);
3648 /* Otherwise use the default handling. */
3652 *total = COSTS_N_INSNS (6);
3656 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3660 /* Check for a *clear_upper32 pattern and treat it like a zero
3661 extension. See the pattern's comment for details. */
3664 && CONST_INT_P (XEXP (x, 1))
3665 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3667 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3668 + rtx_cost (XEXP (x, 0), SET, speed));
3675 /* Double-word operations use two single-word operations. */
3676 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3685 if (CONSTANT_P (XEXP (x, 1)))
3686 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3689 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3695 *total = mips_cost->fp_add;
3697 *total = COSTS_N_INSNS (4);
3701 /* Low-part immediates need an extended MIPS16 instruction. */
3702 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3703 + rtx_cost (XEXP (x, 0), SET, speed));
3718 /* Branch comparisons have VOIDmode, so use the first operand's
3720 mode = GET_MODE (XEXP (x, 0));
3721 if (FLOAT_MODE_P (mode))
3723 *total = mips_cost->fp_add;
3726 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3732 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3733 && TARGET_FUSED_MADD
3734 && !HONOR_NANS (mode)
3735 && !HONOR_SIGNED_ZEROS (mode))
3737 /* See if we can use NMADD or NMSUB. See mips.md for the
3738 associated patterns. */
3739 rtx op0 = XEXP (x, 0);
3740 rtx op1 = XEXP (x, 1);
3741 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3743 *total = (mips_fp_mult_cost (mode)
3744 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3745 + rtx_cost (XEXP (op0, 1), SET, speed)
3746 + rtx_cost (op1, SET, speed));
3749 if (GET_CODE (op1) == MULT)
3751 *total = (mips_fp_mult_cost (mode)
3752 + rtx_cost (op0, SET, speed)
3753 + rtx_cost (XEXP (op1, 0), SET, speed)
3754 + rtx_cost (XEXP (op1, 1), SET, speed));
3763 /* If this is part of a MADD or MSUB, treat the PLUS as
3766 && TARGET_FUSED_MADD
3767 && GET_CODE (XEXP (x, 0)) == MULT)
3770 *total = mips_cost->fp_add;
3774 /* Double-word operations require three single-word operations and
3775 an SLTU. The MIPS16 version then needs to move the result of
3776 the SLTU from $24 to a MIPS16 register. */
3777 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3778 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3784 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3785 && TARGET_FUSED_MADD
3786 && !HONOR_NANS (mode)
3787 && HONOR_SIGNED_ZEROS (mode))
3789 /* See if we can use NMADD or NMSUB. See mips.md for the
3790 associated patterns. */
3791 rtx op = XEXP (x, 0);
3792 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3793 && GET_CODE (XEXP (op, 0)) == MULT)
3795 *total = (mips_fp_mult_cost (mode)
3796 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3797 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3798 + rtx_cost (XEXP (op, 1), SET, speed));
3804 *total = mips_cost->fp_add;
3806 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3811 *total = mips_fp_mult_cost (mode);
3812 else if (mode == DImode && !TARGET_64BIT)
3813 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3814 where the mulsidi3 always includes an MFHI and an MFLO. */
3816 ? mips_cost->int_mult_si * 3 + 6
3817 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3819 *total = (ISA_HAS_MUL3 ? 1 : 2);
3820 else if (mode == DImode)
3821 *total = mips_cost->int_mult_di;
3823 *total = mips_cost->int_mult_si;
3827 /* Check for a reciprocal. */
3830 && flag_unsafe_math_optimizations
3831 && XEXP (x, 0) == CONST1_RTX (mode))
3833 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3834 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3835 division as being free. */
3836 *total = rtx_cost (XEXP (x, 1), SET, speed);
3838 *total = (mips_fp_div_cost (mode)
3839 + rtx_cost (XEXP (x, 1), SET, speed));
3848 *total = mips_fp_div_cost (mode);
3857 /* It is our responsibility to make division by a power of 2
3858 as cheap as 2 register additions if we want the division
3859 expanders to be used for such operations; see the setting
3860 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3861 should always produce shorter code than using
3862 expand_sdiv2_pow2. */
3864 && CONST_INT_P (XEXP (x, 1))
3865 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3867 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3870 *total = COSTS_N_INSNS (mips_idiv_insns ());
3872 else if (mode == DImode)
3873 *total = mips_cost->int_div_di;
3875 *total = mips_cost->int_div_si;
3879 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3883 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3887 case UNSIGNED_FLOAT:
3890 case FLOAT_TRUNCATE:
3891 *total = mips_cost->fp_add;
3899 /* Implement TARGET_ADDRESS_COST. */
3902 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3904 return mips_address_insns (addr, SImode, false);
3907 /* Information about a single instruction in a multi-instruction
3909 struct mips_multi_member {
3910 /* True if this is a label, false if it is code. */
3913 /* The output_asm_insn format of the instruction. */
3916 /* The operands to the instruction. */
3917 rtx operands[MAX_RECOG_OPERANDS];
3919 typedef struct mips_multi_member mips_multi_member;
3921 /* Vector definitions for the above. */
3922 DEF_VEC_O(mips_multi_member);
3923 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3925 /* The instructions that make up the current multi-insn sequence. */
3926 static VEC (mips_multi_member, heap) *mips_multi_members;
3928 /* How many instructions (as opposed to labels) are in the current
3929 multi-insn sequence. */
3930 static unsigned int mips_multi_num_insns;
3932 /* Start a new multi-insn sequence. */
3935 mips_multi_start (void)
3937 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3938 mips_multi_num_insns = 0;
3941 /* Add a new, uninitialized member to the current multi-insn sequence. */
3943 static struct mips_multi_member *
3944 mips_multi_add (void)
3946 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3949 /* Add a normal insn with the given asm format to the current multi-insn
3950 sequence. The other arguments are a null-terminated list of operands. */
3953 mips_multi_add_insn (const char *format, ...)
3955 struct mips_multi_member *member;
3960 member = mips_multi_add ();
3961 member->is_label_p = false;
3962 member->format = format;
3963 va_start (ap, format);
3965 while ((op = va_arg (ap, rtx)))
3966 member->operands[i++] = op;
3968 mips_multi_num_insns++;
3971 /* Add the given label definition to the current multi-insn sequence.
3972 The definition should include the colon. */
3975 mips_multi_add_label (const char *label)
3977 struct mips_multi_member *member;
3979 member = mips_multi_add ();
3980 member->is_label_p = true;
3981 member->format = label;
3984 /* Return the index of the last member of the current multi-insn sequence. */
3987 mips_multi_last_index (void)
3989 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3992 /* Add a copy of an existing instruction to the current multi-insn
3993 sequence. I is the index of the instruction that should be copied. */
3996 mips_multi_copy_insn (unsigned int i)
3998 struct mips_multi_member *member;
4000 member = mips_multi_add ();
4001 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
4003 gcc_assert (!member->is_label_p);
4006 /* Change the operand of an existing instruction in the current
4007 multi-insn sequence. I is the index of the instruction,
4008 OP is the index of the operand, and X is the new value. */
4011 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4013 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
4016 /* Write out the asm code for the current multi-insn sequence. */
4019 mips_multi_write (void)
4021 struct mips_multi_member *member;
4024 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4025 if (member->is_label_p)
4026 fprintf (asm_out_file, "%s\n", member->format);
4028 output_asm_insn (member->format, member->operands);
4031 /* Return one word of double-word value OP, taking into account the fixed
4032 endianness of certain registers. HIGH_P is true to select the high part,
4033 false to select the low part. */
4036 mips_subword (rtx op, bool high_p)
4038 unsigned int byte, offset;
4039 enum machine_mode mode;
4041 mode = GET_MODE (op);
4042 if (mode == VOIDmode)
4043 mode = TARGET_64BIT ? TImode : DImode;
4045 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4046 byte = UNITS_PER_WORD;
4050 if (FP_REG_RTX_P (op))
4052 /* Paired FPRs are always ordered little-endian. */
4053 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4054 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4058 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4060 return simplify_gen_subreg (word_mode, op, mode, byte);
4063 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4066 mips_split_64bit_move_p (rtx dest, rtx src)
4071 /* FPR-to-FPR moves can be done in a single instruction, if they're
4073 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4076 /* Check for floating-point loads and stores. */
4077 if (ISA_HAS_LDC1_SDC1)
4079 if (FP_REG_RTX_P (dest) && MEM_P (src))
4081 if (FP_REG_RTX_P (src) && MEM_P (dest))
4087 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4088 this function handles 64-bit moves for which mips_split_64bit_move_p
4089 holds. For 64-bit targets, this function handles 128-bit moves. */
4092 mips_split_doubleword_move (rtx dest, rtx src)
4096 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4098 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4099 emit_insn (gen_move_doubleword_fprdi (dest, src));
4100 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4101 emit_insn (gen_move_doubleword_fprdf (dest, src));
4102 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4103 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4104 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4105 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4106 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4107 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4108 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4109 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4110 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4111 emit_insn (gen_move_doubleword_fprtf (dest, src));
4115 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4117 low_dest = mips_subword (dest, false);
4118 mips_emit_move (low_dest, mips_subword (src, false));
4120 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4122 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4124 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4126 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4128 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4130 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4134 /* The operation can be split into two normal moves. Decide in
4135 which order to do them. */
4136 low_dest = mips_subword (dest, false);
4137 if (REG_P (low_dest)
4138 && reg_overlap_mentioned_p (low_dest, src))
4140 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4141 mips_emit_move (low_dest, mips_subword (src, false));
4145 mips_emit_move (low_dest, mips_subword (src, false));
4146 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4151 /* Return the appropriate instructions to move SRC into DEST. Assume
4152 that SRC is operand 1 and DEST is operand 0. */
4155 mips_output_move (rtx dest, rtx src)
4157 enum rtx_code dest_code, src_code;
4158 enum machine_mode mode;
4159 enum mips_symbol_type symbol_type;
4162 dest_code = GET_CODE (dest);
4163 src_code = GET_CODE (src);
4164 mode = GET_MODE (dest);
4165 dbl_p = (GET_MODE_SIZE (mode) == 8);
4167 if (dbl_p && mips_split_64bit_move_p (dest, src))
4170 if ((src_code == REG && GP_REG_P (REGNO (src)))
4171 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4173 if (dest_code == REG)
4175 if (GP_REG_P (REGNO (dest)))
4176 return "move\t%0,%z1";
4178 /* Moves to HI are handled by special .md insns. */
4179 if (REGNO (dest) == LO_REGNUM)
4182 if (DSP_ACC_REG_P (REGNO (dest)))
4184 static char retval[] = "mt__\t%z1,%q0";
4186 retval[2] = reg_names[REGNO (dest)][4];
4187 retval[3] = reg_names[REGNO (dest)][5];
4191 if (FP_REG_P (REGNO (dest)))
4192 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4194 if (ALL_COP_REG_P (REGNO (dest)))
4196 static char retval[] = "dmtc_\t%z1,%0";
4198 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4199 return dbl_p ? retval : retval + 1;
4202 if (dest_code == MEM)
4203 switch (GET_MODE_SIZE (mode))
4205 case 1: return "sb\t%z1,%0";
4206 case 2: return "sh\t%z1,%0";
4207 case 4: return "sw\t%z1,%0";
4208 case 8: return "sd\t%z1,%0";
4211 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4213 if (src_code == REG)
4215 /* Moves from HI are handled by special .md insns. */
4216 if (REGNO (src) == LO_REGNUM)
4218 /* When generating VR4120 or VR4130 code, we use MACC and
4219 DMACC instead of MFLO. This avoids both the normal
4220 MIPS III HI/LO hazards and the errata related to
4223 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4227 if (DSP_ACC_REG_P (REGNO (src)))
4229 static char retval[] = "mf__\t%0,%q1";
4231 retval[2] = reg_names[REGNO (src)][4];
4232 retval[3] = reg_names[REGNO (src)][5];
4236 if (FP_REG_P (REGNO (src)))
4237 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4239 if (ALL_COP_REG_P (REGNO (src)))
4241 static char retval[] = "dmfc_\t%0,%1";
4243 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4244 return dbl_p ? retval : retval + 1;
4247 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4248 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4251 if (src_code == MEM)
4252 switch (GET_MODE_SIZE (mode))
4254 case 1: return "lbu\t%0,%1";
4255 case 2: return "lhu\t%0,%1";
4256 case 4: return "lw\t%0,%1";
4257 case 8: return "ld\t%0,%1";
4260 if (src_code == CONST_INT)
4262 /* Don't use the X format for the operand itself, because that
4263 will give out-of-range numbers for 64-bit hosts and 32-bit
4266 return "li\t%0,%1\t\t\t# %X1";
4268 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4271 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4275 if (src_code == HIGH)
4276 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4278 if (CONST_GP_P (src))
4279 return "move\t%0,%1";
4281 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4282 && mips_lo_relocs[symbol_type] != 0)
4284 /* A signed 16-bit constant formed by applying a relocation
4285 operator to a symbolic address. */
4286 gcc_assert (!mips_split_p[symbol_type]);
4287 return "li\t%0,%R1";
4290 if (symbolic_operand (src, VOIDmode))
4292 gcc_assert (TARGET_MIPS16
4293 ? TARGET_MIPS16_TEXT_LOADS
4294 : !TARGET_EXPLICIT_RELOCS);
4295 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4298 if (src_code == REG && FP_REG_P (REGNO (src)))
4300 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4302 if (GET_MODE (dest) == V2SFmode)
4303 return "mov.ps\t%0,%1";
4305 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4308 if (dest_code == MEM)
4309 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4311 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4313 if (src_code == MEM)
4314 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4316 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4318 static char retval[] = "l_c_\t%0,%1";
4320 retval[1] = (dbl_p ? 'd' : 'w');
4321 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4324 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4326 static char retval[] = "s_c_\t%1,%0";
4328 retval[1] = (dbl_p ? 'd' : 'w');
4329 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4335 /* Return true if CMP1 is a suitable second operand for integer ordering
4336 test CODE. See also the *sCC patterns in mips.md. */
4339 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4345 return reg_or_0_operand (cmp1, VOIDmode);
4349 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4353 return arith_operand (cmp1, VOIDmode);
4356 return sle_operand (cmp1, VOIDmode);
4359 return sleu_operand (cmp1, VOIDmode);
4366 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4367 integer ordering test *CODE, or if an equivalent combination can
4368 be formed by adjusting *CODE and *CMP1. When returning true, update
4369 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4373 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4374 enum machine_mode mode)
4376 HOST_WIDE_INT plus_one;
4378 if (mips_int_order_operand_ok_p (*code, *cmp1))
4381 if (CONST_INT_P (*cmp1))
4385 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4386 if (INTVAL (*cmp1) < plus_one)
4389 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4395 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4399 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4410 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4411 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4412 is nonnull, it's OK to set TARGET to the inverse of the result and
4413 flip *INVERT_PTR instead. */
4416 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4417 rtx target, rtx cmp0, rtx cmp1)
4419 enum machine_mode mode;
4421 /* First see if there is a MIPS instruction that can do this operation.
4422 If not, try doing the same for the inverse operation. If that also
4423 fails, force CMP1 into a register and try again. */
4424 mode = GET_MODE (cmp0);
4425 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4426 mips_emit_binary (code, target, cmp0, cmp1);
4429 enum rtx_code inv_code = reverse_condition (code);
4430 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4432 cmp1 = force_reg (mode, cmp1);
4433 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4435 else if (invert_ptr == 0)
4439 inv_target = mips_force_binary (GET_MODE (target),
4440 inv_code, cmp0, cmp1);
4441 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4445 *invert_ptr = !*invert_ptr;
4446 mips_emit_binary (inv_code, target, cmp0, cmp1);
4451 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4452 The register will have the same mode as CMP0. */
4455 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4457 if (cmp1 == const0_rtx)
4460 if (uns_arith_operand (cmp1, VOIDmode))
4461 return expand_binop (GET_MODE (cmp0), xor_optab,
4462 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4464 return expand_binop (GET_MODE (cmp0), sub_optab,
4465 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4468 /* Convert *CODE into a code that can be used in a floating-point
4469 scc instruction (C.cond.fmt). Return true if the values of
4470 the condition code registers will be inverted, with 0 indicating
4471 that the condition holds. */
4474 mips_reversed_fp_cond (enum rtx_code *code)
4481 *code = reverse_condition_maybe_unordered (*code);
4489 /* Convert a comparison into something that can be used in a branch or
4490 conditional move. On entry, *OP0 and *OP1 are the values being
4491 compared and *CODE is the code used to compare them.
4493 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4494 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4495 otherwise any standard branch condition can be used. The standard branch
4498 - EQ or NE between two registers.
4499 - any comparison between a register and zero. */
4502 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4507 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4509 if (!need_eq_ne_p && *op1 == const0_rtx)
4511 else if (*code == EQ || *code == NE)
4515 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4519 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4523 /* The comparison needs a separate scc instruction. Store the
4524 result of the scc in *OP0 and compare it against zero. */
4525 bool invert = false;
4526 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4527 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4528 *code = (invert ? EQ : NE);
4532 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4534 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4535 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4541 enum rtx_code cmp_code;
4543 /* Floating-point tests use a separate C.cond.fmt comparison to
4544 set a condition code register. The branch or conditional move
4545 will then compare that register against zero.
4547 Set CMP_CODE to the code of the comparison instruction and
4548 *CODE to the code that the branch or move should use. */
4550 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4552 ? gen_reg_rtx (CCmode)
4553 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4555 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4559 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4560 and OPERAND[3]. Store the result in OPERANDS[0].
4562 On 64-bit targets, the mode of the comparison and target will always be
4563 SImode, thus possibly narrower than that of the comparison's operands. */
4566 mips_expand_scc (rtx operands[])
4568 rtx target = operands[0];
4569 enum rtx_code code = GET_CODE (operands[1]);
4570 rtx op0 = operands[2];
4571 rtx op1 = operands[3];
4573 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4575 if (code == EQ || code == NE)
4578 && reg_imm10_operand (op1, GET_MODE (op1)))
4579 mips_emit_binary (code, target, op0, op1);
4582 rtx zie = mips_zero_if_equal (op0, op1);
4583 mips_emit_binary (code, target, zie, const0_rtx);
4587 mips_emit_int_order_test (code, 0, target, op0, op1);
4590 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4591 CODE and jump to OPERANDS[3] if the condition holds. */
4594 mips_expand_conditional_branch (rtx *operands)
4596 enum rtx_code code = GET_CODE (operands[0]);
4597 rtx op0 = operands[1];
4598 rtx op1 = operands[2];
4601 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4602 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4603 emit_jump_insn (gen_condjump (condition, operands[3]));
4608 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4609 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4612 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4613 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4618 reversed_p = mips_reversed_fp_cond (&cond);
4619 cmp_result = gen_reg_rtx (CCV2mode);
4620 emit_insn (gen_scc_ps (cmp_result,
4621 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4623 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4626 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4630 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4631 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4634 mips_expand_conditional_move (rtx *operands)
4637 enum rtx_code code = GET_CODE (operands[1]);
4638 rtx op0 = XEXP (operands[1], 0);
4639 rtx op1 = XEXP (operands[1], 1);
4641 mips_emit_compare (&code, &op0, &op1, true);
4642 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4643 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4644 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4645 operands[2], operands[3])));
4648 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4651 mips_expand_conditional_trap (rtx comparison)
4654 enum machine_mode mode;
4657 /* MIPS conditional trap instructions don't have GT or LE flavors,
4658 so we must swap the operands and convert to LT and GE respectively. */
4659 code = GET_CODE (comparison);
4666 code = swap_condition (code);
4667 op0 = XEXP (comparison, 1);
4668 op1 = XEXP (comparison, 0);
4672 op0 = XEXP (comparison, 0);
4673 op1 = XEXP (comparison, 1);
4677 mode = GET_MODE (XEXP (comparison, 0));
4678 op0 = force_reg (mode, op0);
4679 if (!arith_operand (op1, mode))
4680 op1 = force_reg (mode, op1);
4682 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4683 gen_rtx_fmt_ee (code, mode, op0, op1),
4687 /* Initialize *CUM for a call to a function of type FNTYPE. */
4690 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4692 memset (cum, 0, sizeof (*cum));
4693 cum->prototype = (fntype && prototype_p (fntype));
4694 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4697 /* Fill INFO with information about a single argument. CUM is the
4698 cumulative state for earlier arguments. MODE is the mode of this
4699 argument and TYPE is its type (if known). NAMED is true if this
4700 is a named (fixed) argument rather than a variable one. */
4703 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4704 enum machine_mode mode, const_tree type, bool named)
4706 bool doubleword_aligned_p;
4707 unsigned int num_bytes, num_words, max_regs;
4709 /* Work out the size of the argument. */
4710 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4711 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4713 /* Decide whether it should go in a floating-point register, assuming
4714 one is free. Later code checks for availability.
4716 The checks against UNITS_PER_FPVALUE handle the soft-float and
4717 single-float cases. */
4721 /* The EABI conventions have traditionally been defined in terms
4722 of TYPE_MODE, regardless of the actual type. */
4723 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4724 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4725 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4730 /* Only leading floating-point scalars are passed in
4731 floating-point registers. We also handle vector floats the same
4732 say, which is OK because they are not covered by the standard ABI. */
4733 info->fpr_p = (!cum->gp_reg_found
4734 && cum->arg_number < 2
4736 || SCALAR_FLOAT_TYPE_P (type)
4737 || VECTOR_FLOAT_TYPE_P (type))
4738 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4739 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4740 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4745 /* Scalar, complex and vector floating-point types are passed in
4746 floating-point registers, as long as this is a named rather
4747 than a variable argument. */
4748 info->fpr_p = (named
4749 && (type == 0 || FLOAT_TYPE_P (type))
4750 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4751 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4752 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4753 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4755 /* ??? According to the ABI documentation, the real and imaginary
4756 parts of complex floats should be passed in individual registers.
4757 The real and imaginary parts of stack arguments are supposed
4758 to be contiguous and there should be an extra word of padding
4761 This has two problems. First, it makes it impossible to use a
4762 single "void *" va_list type, since register and stack arguments
4763 are passed differently. (At the time of writing, MIPSpro cannot
4764 handle complex float varargs correctly.) Second, it's unclear
4765 what should happen when there is only one register free.
4767 For now, we assume that named complex floats should go into FPRs
4768 if there are two FPRs free, otherwise they should be passed in the
4769 same way as a struct containing two floats. */
4771 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4772 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4774 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4775 info->fpr_p = false;
4785 /* See whether the argument has doubleword alignment. */
4786 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4789 /* Set REG_OFFSET to the register count we're interested in.
4790 The EABI allocates the floating-point registers separately,
4791 but the other ABIs allocate them like integer registers. */
4792 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4796 /* Advance to an even register if the argument is doubleword-aligned. */
4797 if (doubleword_aligned_p)
4798 info->reg_offset += info->reg_offset & 1;
4800 /* Work out the offset of a stack argument. */
4801 info->stack_offset = cum->stack_words;
4802 if (doubleword_aligned_p)
4803 info->stack_offset += info->stack_offset & 1;
4805 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4807 /* Partition the argument between registers and stack. */
4808 info->reg_words = MIN (num_words, max_regs);
4809 info->stack_words = num_words - info->reg_words;
4812 /* INFO describes a register argument that has the normal format for the
4813 argument's mode. Return the register it uses, assuming that FPRs are
4814 available if HARD_FLOAT_P. */
4817 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4819 if (!info->fpr_p || !hard_float_p)
4820 return GP_ARG_FIRST + info->reg_offset;
4821 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4822 /* In o32, the second argument is always passed in $f14
4823 for TARGET_DOUBLE_FLOAT, regardless of whether the
4824 first argument was a word or doubleword. */
4825 return FP_ARG_FIRST + 2;
4827 return FP_ARG_FIRST + info->reg_offset;
4830 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4833 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4835 return !TARGET_OLDABI;
4838 /* Implement TARGET_FUNCTION_ARG. */
4841 mips_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4842 const_tree type, bool named)
4844 struct mips_arg_info info;
4846 /* We will be called with a mode of VOIDmode after the last argument
4847 has been seen. Whatever we return will be passed to the call expander.
4848 If we need a MIPS16 fp_code, return a REG with the code stored as
4850 if (mode == VOIDmode)
4852 if (TARGET_MIPS16 && cum->fp_code != 0)
4853 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4858 mips_get_arg_info (&info, cum, mode, type, named);
4860 /* Return straight away if the whole argument is passed on the stack. */
4861 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4864 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4865 contains a double in its entirety, then that 64-bit chunk is passed
4866 in a floating-point register. */
4868 && TARGET_HARD_FLOAT
4871 && TREE_CODE (type) == RECORD_TYPE
4872 && TYPE_SIZE_UNIT (type)
4873 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4877 /* First check to see if there is any such field. */
4878 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4879 if (TREE_CODE (field) == FIELD_DECL
4880 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4881 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4882 && host_integerp (bit_position (field), 0)
4883 && int_bit_position (field) % BITS_PER_WORD == 0)
4888 /* Now handle the special case by returning a PARALLEL
4889 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4890 chunks are passed in registers. */
4892 HOST_WIDE_INT bitpos;
4895 /* assign_parms checks the mode of ENTRY_PARM, so we must
4896 use the actual mode here. */
4897 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4900 field = TYPE_FIELDS (type);
4901 for (i = 0; i < info.reg_words; i++)
4905 for (; field; field = DECL_CHAIN (field))
4906 if (TREE_CODE (field) == FIELD_DECL
4907 && int_bit_position (field) >= bitpos)
4911 && int_bit_position (field) == bitpos
4912 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4913 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4914 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4916 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4919 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4920 GEN_INT (bitpos / BITS_PER_UNIT));
4922 bitpos += BITS_PER_WORD;
4928 /* Handle the n32/n64 conventions for passing complex floating-point
4929 arguments in FPR pairs. The real part goes in the lower register
4930 and the imaginary part goes in the upper register. */
4933 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4936 enum machine_mode inner;
4939 inner = GET_MODE_INNER (mode);
4940 regno = FP_ARG_FIRST + info.reg_offset;
4941 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4943 /* Real part in registers, imaginary part on stack. */
4944 gcc_assert (info.stack_words == info.reg_words);
4945 return gen_rtx_REG (inner, regno);
4949 gcc_assert (info.stack_words == 0);
4950 real = gen_rtx_EXPR_LIST (VOIDmode,
4951 gen_rtx_REG (inner, regno),
4953 imag = gen_rtx_EXPR_LIST (VOIDmode,
4955 regno + info.reg_words / 2),
4956 GEN_INT (GET_MODE_SIZE (inner)));
4957 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4961 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4964 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4967 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4968 const_tree type, bool named)
4970 struct mips_arg_info info;
4972 mips_get_arg_info (&info, cum, mode, type, named);
4975 cum->gp_reg_found = true;
4977 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4978 an explanation of what this code does. It assumes that we're using
4979 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4981 if (cum->arg_number < 2 && info.fpr_p)
4982 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4984 /* Advance the register count. This has the effect of setting
4985 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4986 argument required us to skip the final GPR and pass the whole
4987 argument on the stack. */
4988 if (mips_abi != ABI_EABI || !info.fpr_p)
4989 cum->num_gprs = info.reg_offset + info.reg_words;
4990 else if (info.reg_words > 0)
4991 cum->num_fprs += MAX_FPRS_PER_FMT;
4993 /* Advance the stack word count. */
4994 if (info.stack_words > 0)
4995 cum->stack_words = info.stack_offset + info.stack_words;
5000 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5003 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
5004 enum machine_mode mode, tree type, bool named)
5006 struct mips_arg_info info;
5008 mips_get_arg_info (&info, cum, mode, type, named);
5009 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5012 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5013 least PARM_BOUNDARY bits of alignment, but will be given anything up
5014 to STACK_BOUNDARY bits if the type requires it. */
5017 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5019 unsigned int alignment;
5021 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5022 if (alignment < PARM_BOUNDARY)
5023 alignment = PARM_BOUNDARY;
5024 if (alignment > STACK_BOUNDARY)
5025 alignment = STACK_BOUNDARY;
5029 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5030 upward rather than downward. In other words, return true if the
5031 first byte of the stack slot has useful data, false if the last
5035 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5037 /* On little-endian targets, the first byte of every stack argument
5038 is passed in the first byte of the stack slot. */
5039 if (!BYTES_BIG_ENDIAN)
5042 /* Otherwise, integral types are padded downward: the last byte of a
5043 stack argument is passed in the last byte of the stack slot. */
5045 ? (INTEGRAL_TYPE_P (type)
5046 || POINTER_TYPE_P (type)
5047 || FIXED_POINT_TYPE_P (type))
5048 : (SCALAR_INT_MODE_P (mode)
5049 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5052 /* Big-endian o64 pads floating-point arguments downward. */
5053 if (mips_abi == ABI_O64)
5054 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5057 /* Other types are padded upward for o32, o64, n32 and n64. */
5058 if (mips_abi != ABI_EABI)
5061 /* Arguments smaller than a stack slot are padded downward. */
5062 if (mode != BLKmode)
5063 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5065 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5068 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5069 if the least significant byte of the register has useful data. Return
5070 the opposite if the most significant byte does. */
5073 mips_pad_reg_upward (enum machine_mode mode, tree type)
5075 /* No shifting is required for floating-point arguments. */
5076 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5077 return !BYTES_BIG_ENDIAN;
5079 /* Otherwise, apply the same padding to register arguments as we do
5080 to stack arguments. */
5081 return mips_pad_arg_upward (mode, type);
5084 /* Return nonzero when an argument must be passed by reference. */
5087 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5088 enum machine_mode mode, const_tree type,
5089 bool named ATTRIBUTE_UNUSED)
5091 if (mips_abi == ABI_EABI)
5095 /* ??? How should SCmode be handled? */
5096 if (mode == DImode || mode == DFmode
5097 || mode == DQmode || mode == UDQmode
5098 || mode == DAmode || mode == UDAmode)
5101 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5102 return size == -1 || size > UNITS_PER_WORD;
5106 /* If we have a variable-sized parameter, we have no choice. */
5107 return targetm.calls.must_pass_in_stack (mode, type);
5111 /* Implement TARGET_CALLEE_COPIES. */
5114 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5115 enum machine_mode mode ATTRIBUTE_UNUSED,
5116 const_tree type ATTRIBUTE_UNUSED, bool named)
5118 return mips_abi == ABI_EABI && named;
5121 /* See whether VALTYPE is a record whose fields should be returned in
5122 floating-point registers. If so, return the number of fields and
5123 list them in FIELDS (which should have two elements). Return 0
5126 For n32 & n64, a structure with one or two fields is returned in
5127 floating-point registers as long as every field has a floating-point
5131 mips_fpr_return_fields (const_tree valtype, tree *fields)
5139 if (TREE_CODE (valtype) != RECORD_TYPE)
5143 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5145 if (TREE_CODE (field) != FIELD_DECL)
5148 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5154 fields[i++] = field;
5159 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5160 a value in the most significant part of $2/$3 if:
5162 - the target is big-endian;
5164 - the value has a structure or union type (we generalize this to
5165 cover aggregates from other languages too); and
5167 - the structure is not returned in floating-point registers. */
5170 mips_return_in_msb (const_tree valtype)
5174 return (TARGET_NEWABI
5175 && TARGET_BIG_ENDIAN
5176 && AGGREGATE_TYPE_P (valtype)
5177 && mips_fpr_return_fields (valtype, fields) == 0);
5180 /* Return true if the function return value MODE will get returned in a
5181 floating-point register. */
5184 mips_return_mode_in_fpr_p (enum machine_mode mode)
5186 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5187 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5188 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5189 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5192 /* Return the representation of an FPR return register when the
5193 value being returned in FP_RETURN has mode VALUE_MODE and the
5194 return type itself has mode TYPE_MODE. On NewABI targets,
5195 the two modes may be different for structures like:
5197 struct __attribute__((packed)) foo { float f; }
5199 where we return the SFmode value of "f" in FP_RETURN, but where
5200 the structure itself has mode BLKmode. */
5203 mips_return_fpr_single (enum machine_mode type_mode,
5204 enum machine_mode value_mode)
5208 x = gen_rtx_REG (value_mode, FP_RETURN);
5209 if (type_mode != value_mode)
5211 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5212 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5217 /* Return a composite value in a pair of floating-point registers.
5218 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5219 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5222 For n32 & n64, $f0 always holds the first value and $f2 the second.
5223 Otherwise the values are packed together as closely as possible. */
5226 mips_return_fpr_pair (enum machine_mode mode,
5227 enum machine_mode mode1, HOST_WIDE_INT offset1,
5228 enum machine_mode mode2, HOST_WIDE_INT offset2)
5232 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5233 return gen_rtx_PARALLEL
5236 gen_rtx_EXPR_LIST (VOIDmode,
5237 gen_rtx_REG (mode1, FP_RETURN),
5239 gen_rtx_EXPR_LIST (VOIDmode,
5240 gen_rtx_REG (mode2, FP_RETURN + inc),
5241 GEN_INT (offset2))));
5245 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5246 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5247 VALTYPE is null and MODE is the mode of the return value. */
5250 mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
5257 mode = TYPE_MODE (valtype);
5258 unsigned_p = TYPE_UNSIGNED (valtype);
5260 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5261 return values, promote the mode here too. */
5262 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5264 /* Handle structures whose fields are returned in $f0/$f2. */
5265 switch (mips_fpr_return_fields (valtype, fields))
5268 return mips_return_fpr_single (mode,
5269 TYPE_MODE (TREE_TYPE (fields[0])));
5272 return mips_return_fpr_pair (mode,
5273 TYPE_MODE (TREE_TYPE (fields[0])),
5274 int_byte_position (fields[0]),
5275 TYPE_MODE (TREE_TYPE (fields[1])),
5276 int_byte_position (fields[1]));
5279 /* If a value is passed in the most significant part of a register, see
5280 whether we have to round the mode up to a whole number of words. */
5281 if (mips_return_in_msb (valtype))
5283 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5284 if (size % UNITS_PER_WORD != 0)
5286 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5287 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5291 /* For EABI, the class of return register depends entirely on MODE.
5292 For example, "struct { some_type x; }" and "union { some_type x; }"
5293 are returned in the same way as a bare "some_type" would be.
5294 Other ABIs only use FPRs for scalar, complex or vector types. */
5295 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5296 return gen_rtx_REG (mode, GP_RETURN);
5301 /* Handle long doubles for n32 & n64. */
5303 return mips_return_fpr_pair (mode,
5305 DImode, GET_MODE_SIZE (mode) / 2);
5307 if (mips_return_mode_in_fpr_p (mode))
5309 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5310 return mips_return_fpr_pair (mode,
5311 GET_MODE_INNER (mode), 0,
5312 GET_MODE_INNER (mode),
5313 GET_MODE_SIZE (mode) / 2);
5315 return gen_rtx_REG (mode, FP_RETURN);
5319 return gen_rtx_REG (mode, GP_RETURN);
5322 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5323 all BLKmode objects are returned in memory. Under the n32, n64
5324 and embedded ABIs, small structures are returned in a register.
5325 Objects with varying size must still be returned in memory, of
5329 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5331 return (TARGET_OLDABI
5332 ? TYPE_MODE (type) == BLKmode
5333 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5336 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5339 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5340 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5343 CUMULATIVE_ARGS local_cum;
5344 int gp_saved, fp_saved;
5346 /* The caller has advanced CUM up to, but not beyond, the last named
5347 argument. Advance a local copy of CUM past the last "real" named
5348 argument, to find out how many registers are left over. */
5350 mips_function_arg_advance (&local_cum, mode, type, true);
5352 /* Found out how many registers we need to save. */
5353 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5354 fp_saved = (EABI_FLOAT_VARARGS_P
5355 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5364 ptr = plus_constant (virtual_incoming_args_rtx,
5365 REG_PARM_STACK_SPACE (cfun->decl)
5366 - gp_saved * UNITS_PER_WORD);
5367 mem = gen_frame_mem (BLKmode, ptr);
5368 set_mem_alias_set (mem, get_varargs_alias_set ());
5370 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5375 /* We can't use move_block_from_reg, because it will use
5377 enum machine_mode mode;
5380 /* Set OFF to the offset from virtual_incoming_args_rtx of
5381 the first float register. The FP save area lies below
5382 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5383 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5384 off -= fp_saved * UNITS_PER_FPREG;
5386 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5388 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5389 i += MAX_FPRS_PER_FMT)
5393 ptr = plus_constant (virtual_incoming_args_rtx, off);
5394 mem = gen_frame_mem (mode, ptr);
5395 set_mem_alias_set (mem, get_varargs_alias_set ());
5396 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5397 off += UNITS_PER_HWFPVALUE;
5401 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5402 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5403 + fp_saved * UNITS_PER_FPREG);
5406 /* Implement TARGET_BUILTIN_VA_LIST. */
5409 mips_build_builtin_va_list (void)
5411 if (EABI_FLOAT_VARARGS_P)
5413 /* We keep 3 pointers, and two offsets.
5415 Two pointers are to the overflow area, which starts at the CFA.
5416 One of these is constant, for addressing into the GPR save area
5417 below it. The other is advanced up the stack through the
5420 The third pointer is to the bottom of the GPR save area.
5421 Since the FPR save area is just below it, we can address
5422 FPR slots off this pointer.
5424 We also keep two one-byte offsets, which are to be subtracted
5425 from the constant pointers to yield addresses in the GPR and
5426 FPR save areas. These are downcounted as float or non-float
5427 arguments are used, and when they get to zero, the argument
5428 must be obtained from the overflow region. */
5429 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5432 record = lang_hooks.types.make_type (RECORD_TYPE);
5434 f_ovfl = build_decl (BUILTINS_LOCATION,
5435 FIELD_DECL, get_identifier ("__overflow_argptr"),
5437 f_gtop = build_decl (BUILTINS_LOCATION,
5438 FIELD_DECL, get_identifier ("__gpr_top"),
5440 f_ftop = build_decl (BUILTINS_LOCATION,
5441 FIELD_DECL, get_identifier ("__fpr_top"),
5443 f_goff = build_decl (BUILTINS_LOCATION,
5444 FIELD_DECL, get_identifier ("__gpr_offset"),
5445 unsigned_char_type_node);
5446 f_foff = build_decl (BUILTINS_LOCATION,
5447 FIELD_DECL, get_identifier ("__fpr_offset"),
5448 unsigned_char_type_node);
5449 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5450 warn on every user file. */
5451 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5452 array = build_array_type (unsigned_char_type_node,
5453 build_index_type (index));
5454 f_res = build_decl (BUILTINS_LOCATION,
5455 FIELD_DECL, get_identifier ("__reserved"), array);
5457 DECL_FIELD_CONTEXT (f_ovfl) = record;
5458 DECL_FIELD_CONTEXT (f_gtop) = record;
5459 DECL_FIELD_CONTEXT (f_ftop) = record;
5460 DECL_FIELD_CONTEXT (f_goff) = record;
5461 DECL_FIELD_CONTEXT (f_foff) = record;
5462 DECL_FIELD_CONTEXT (f_res) = record;
5464 TYPE_FIELDS (record) = f_ovfl;
5465 DECL_CHAIN (f_ovfl) = f_gtop;
5466 DECL_CHAIN (f_gtop) = f_ftop;
5467 DECL_CHAIN (f_ftop) = f_goff;
5468 DECL_CHAIN (f_goff) = f_foff;
5469 DECL_CHAIN (f_foff) = f_res;
5471 layout_type (record);
5474 else if (TARGET_IRIX6)
5475 /* On IRIX 6, this type is 'char *'. */
5476 return build_pointer_type (char_type_node);
5478 /* Otherwise, we use 'void *'. */
5479 return ptr_type_node;
5482 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5485 mips_va_start (tree valist, rtx nextarg)
5487 if (EABI_FLOAT_VARARGS_P)
5489 const CUMULATIVE_ARGS *cum;
5490 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5491 tree ovfl, gtop, ftop, goff, foff;
5493 int gpr_save_area_size;
5494 int fpr_save_area_size;
5497 cum = &crtl->args.info;
5499 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5501 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5503 f_ovfl = TYPE_FIELDS (va_list_type_node);
5504 f_gtop = DECL_CHAIN (f_ovfl);
5505 f_ftop = DECL_CHAIN (f_gtop);
5506 f_goff = DECL_CHAIN (f_ftop);
5507 f_foff = DECL_CHAIN (f_goff);
5509 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5511 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5513 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5515 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5517 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5520 /* Emit code to initialize OVFL, which points to the next varargs
5521 stack argument. CUM->STACK_WORDS gives the number of stack
5522 words used by named arguments. */
5523 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5524 if (cum->stack_words > 0)
5525 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5526 size_int (cum->stack_words * UNITS_PER_WORD));
5527 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5528 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5530 /* Emit code to initialize GTOP, the top of the GPR save area. */
5531 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5532 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5533 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5535 /* Emit code to initialize FTOP, the top of the FPR save area.
5536 This address is gpr_save_area_bytes below GTOP, rounded
5537 down to the next fp-aligned boundary. */
5538 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5539 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5540 fpr_offset &= -UNITS_PER_FPVALUE;
5542 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5543 size_int (-fpr_offset));
5544 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5545 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5547 /* Emit code to initialize GOFF, the offset from GTOP of the
5548 next GPR argument. */
5549 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5550 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5551 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5553 /* Likewise emit code to initialize FOFF, the offset from FTOP
5554 of the next FPR argument. */
5555 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5556 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5557 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5561 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5562 std_expand_builtin_va_start (valist, nextarg);
5566 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5569 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5575 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5577 type = build_pointer_type (type);
5579 if (!EABI_FLOAT_VARARGS_P)
5580 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5583 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5584 tree ovfl, top, off, align;
5585 HOST_WIDE_INT size, rsize, osize;
5588 f_ovfl = TYPE_FIELDS (va_list_type_node);
5589 f_gtop = DECL_CHAIN (f_ovfl);
5590 f_ftop = DECL_CHAIN (f_gtop);
5591 f_goff = DECL_CHAIN (f_ftop);
5592 f_foff = DECL_CHAIN (f_goff);
5596 TOP be the top of the GPR or FPR save area;
5597 OFF be the offset from TOP of the next register;
5598 ADDR_RTX be the address of the argument;
5599 SIZE be the number of bytes in the argument type;
5600 RSIZE be the number of bytes used to store the argument
5601 when it's in the register save area; and
5602 OSIZE be the number of bytes used to store it when it's
5603 in the stack overflow area.
5605 The code we want is:
5607 1: off &= -rsize; // round down
5610 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5615 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5616 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5620 [1] and [9] can sometimes be optimized away. */
5622 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5624 size = int_size_in_bytes (type);
5626 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5627 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5629 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5630 unshare_expr (valist), f_ftop, NULL_TREE);
5631 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5632 unshare_expr (valist), f_foff, NULL_TREE);
5634 /* When va_start saves FPR arguments to the stack, each slot
5635 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5636 argument's precision. */
5637 rsize = UNITS_PER_HWFPVALUE;
5639 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5640 (= PARM_BOUNDARY bits). This can be different from RSIZE
5643 (1) On 32-bit targets when TYPE is a structure such as:
5645 struct s { float f; };
5647 Such structures are passed in paired FPRs, so RSIZE
5648 will be 8 bytes. However, the structure only takes
5649 up 4 bytes of memory, so OSIZE will only be 4.
5651 (2) In combinations such as -mgp64 -msingle-float
5652 -fshort-double. Doubles passed in registers will then take
5653 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5654 stack take up UNITS_PER_WORD bytes. */
5655 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5659 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5660 unshare_expr (valist), f_gtop, NULL_TREE);
5661 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5662 unshare_expr (valist), f_goff, NULL_TREE);
5663 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5664 if (rsize > UNITS_PER_WORD)
5666 /* [1] Emit code for: off &= -rsize. */
5667 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5668 build_int_cst (TREE_TYPE (off), -rsize));
5669 gimplify_assign (unshare_expr (off), t, pre_p);
5674 /* [2] Emit code to branch if off == 0. */
5675 t = build2 (NE_EXPR, boolean_type_node, off,
5676 build_int_cst (TREE_TYPE (off), 0));
5677 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5679 /* [5] Emit code for: off -= rsize. We do this as a form of
5680 post-decrement not available to C. */
5681 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5682 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5684 /* [4] Emit code for:
5685 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5686 t = fold_convert (sizetype, t);
5687 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5688 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5689 if (BYTES_BIG_ENDIAN && rsize > size)
5691 u = size_int (rsize - size);
5692 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5694 COND_EXPR_THEN (addr) = t;
5696 if (osize > UNITS_PER_WORD)
5698 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5699 u = size_int (osize - 1);
5700 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5701 unshare_expr (ovfl), u);
5702 t = fold_convert (sizetype, t);
5703 u = size_int (-osize);
5704 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5705 t = fold_convert (TREE_TYPE (ovfl), t);
5706 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5707 unshare_expr (ovfl), t);
5712 /* [10, 11] Emit code for:
5713 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5715 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5716 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5717 if (BYTES_BIG_ENDIAN && osize > size)
5719 u = size_int (osize - size);
5720 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5723 /* String [9] and [10, 11] together. */
5725 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5726 COND_EXPR_ELSE (addr) = t;
5728 addr = fold_convert (build_pointer_type (type), addr);
5729 addr = build_va_arg_indirect_ref (addr);
5733 addr = build_va_arg_indirect_ref (addr);
5738 /* Start a definition of function NAME. MIPS16_P indicates whether the
5739 function contains MIPS16 code. */
5742 mips_start_function_definition (const char *name, bool mips16_p)
5745 fprintf (asm_out_file, "\t.set\tmips16\n");
5747 fprintf (asm_out_file, "\t.set\tnomips16\n");
5749 if (!flag_inhibit_size_directive)
5751 fputs ("\t.ent\t", asm_out_file);
5752 assemble_name (asm_out_file, name);
5753 fputs ("\n", asm_out_file);
5756 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5758 /* Start the definition proper. */
5759 assemble_name (asm_out_file, name);
5760 fputs (":\n", asm_out_file);
5763 /* End a function definition started by mips_start_function_definition. */
5766 mips_end_function_definition (const char *name)
5768 if (!flag_inhibit_size_directive)
5770 fputs ("\t.end\t", asm_out_file);
5771 assemble_name (asm_out_file, name);
5772 fputs ("\n", asm_out_file);
5776 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5779 mips_ok_for_lazy_binding_p (rtx x)
5781 return (TARGET_USE_GOT
5782 && GET_CODE (x) == SYMBOL_REF
5783 && !SYMBOL_REF_BIND_NOW_P (x)
5784 && !mips_symbol_binds_local_p (x));
5787 /* Load function address ADDR into register DEST. TYPE is as for
5788 mips_expand_call. Return true if we used an explicit lazy-binding
5792 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5794 /* If we're generating PIC, and this call is to a global function,
5795 try to allow its address to be resolved lazily. This isn't
5796 possible for sibcalls when $gp is call-saved because the value
5797 of $gp on entry to the stub would be our caller's gp, not ours. */
5798 if (TARGET_EXPLICIT_RELOCS
5799 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5800 && mips_ok_for_lazy_binding_p (addr))
5802 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5803 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5808 mips_emit_move (dest, addr);
5813 /* Each locally-defined hard-float MIPS16 function has a local symbol
5814 associated with it. This hash table maps the function symbol (FUNC)
5815 to the local symbol (LOCAL). */
5816 struct GTY(()) mips16_local_alias {
5820 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5822 /* Hash table callbacks for mips16_local_aliases. */
5825 mips16_local_aliases_hash (const void *entry)
5827 const struct mips16_local_alias *alias;
5829 alias = (const struct mips16_local_alias *) entry;
5830 return htab_hash_string (XSTR (alias->func, 0));
5834 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5836 const struct mips16_local_alias *alias1, *alias2;
5838 alias1 = (const struct mips16_local_alias *) entry1;
5839 alias2 = (const struct mips16_local_alias *) entry2;
5840 return rtx_equal_p (alias1->func, alias2->func);
5843 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5844 Return a local alias for it, creating a new one if necessary. */
5847 mips16_local_alias (rtx func)
5849 struct mips16_local_alias *alias, tmp_alias;
5852 /* Create the hash table if this is the first call. */
5853 if (mips16_local_aliases == NULL)
5854 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5855 mips16_local_aliases_eq, NULL);
5857 /* Look up the function symbol, creating a new entry if need be. */
5858 tmp_alias.func = func;
5859 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5860 gcc_assert (slot != NULL);
5862 alias = (struct mips16_local_alias *) *slot;
5865 const char *func_name, *local_name;
5868 /* Create a new SYMBOL_REF for the local symbol. The choice of
5869 __fn_local_* is based on the __fn_stub_* names that we've
5870 traditionally used for the non-MIPS16 stub. */
5871 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5872 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5873 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5874 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5876 /* Create a new structure to represent the mapping. */
5877 alias = ggc_alloc_mips16_local_alias ();
5879 alias->local = local;
5882 return alias->local;
5885 /* A chained list of functions for which mips16_build_call_stub has already
5886 generated a stub. NAME is the name of the function and FP_RET_P is true
5887 if the function returns a value in floating-point registers. */
5888 struct mips16_stub {
5889 struct mips16_stub *next;
5893 static struct mips16_stub *mips16_stubs;
5895 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5898 mips16_stub_function (const char *name)
5902 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5903 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5907 /* Return the two-character string that identifies floating-point
5908 return mode MODE in the name of a MIPS16 function stub. */
5911 mips16_call_stub_mode_suffix (enum machine_mode mode)
5915 else if (mode == DFmode)
5917 else if (mode == SCmode)
5919 else if (mode == DCmode)
5921 else if (mode == V2SFmode)
5927 /* Write instructions to move a 32-bit value between general register
5928 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5929 from GPREG to FPREG and 'f' to move in the opposite direction. */
5932 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5934 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5935 reg_names[gpreg], reg_names[fpreg]);
5938 /* Likewise for 64-bit values. */
5941 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5944 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5945 reg_names[gpreg], reg_names[fpreg]);
5946 else if (TARGET_FLOAT64)
5948 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5949 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5950 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5951 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5955 /* Move the least-significant word. */
5956 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5957 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5958 /* ...then the most significant word. */
5959 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5960 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5964 /* Write out code to move floating-point arguments into or out of
5965 general registers. FP_CODE is the code describing which arguments
5966 are present (see the comment above the definition of CUMULATIVE_ARGS
5967 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5970 mips_output_args_xfer (int fp_code, char direction)
5972 unsigned int gparg, fparg, f;
5973 CUMULATIVE_ARGS cum;
5975 /* This code only works for o32 and o64. */
5976 gcc_assert (TARGET_OLDABI);
5978 mips_init_cumulative_args (&cum, NULL);
5980 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5982 enum machine_mode mode;
5983 struct mips_arg_info info;
5987 else if ((f & 3) == 2)
5992 mips_get_arg_info (&info, &cum, mode, NULL, true);
5993 gparg = mips_arg_regno (&info, false);
5994 fparg = mips_arg_regno (&info, true);
5997 mips_output_32bit_xfer (direction, gparg, fparg);
5999 mips_output_64bit_xfer (direction, gparg, fparg);
6001 mips_function_arg_advance (&cum, mode, NULL, true);
6005 /* Write a MIPS16 stub for the current function. This stub is used
6006 for functions which take arguments in the floating-point registers.
6007 It is normal-mode code that moves the floating-point arguments
6008 into the general registers and then jumps to the MIPS16 code. */
6011 mips16_build_function_stub (void)
6013 const char *fnname, *alias_name, *separator;
6014 char *secname, *stubname;
6019 /* Create the name of the stub, and its unique section. */
6020 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6021 alias = mips16_local_alias (symbol);
6023 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6024 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6025 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6026 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6028 /* Build a decl for the stub. */
6029 stubdecl = build_decl (BUILTINS_LOCATION,
6030 FUNCTION_DECL, get_identifier (stubname),
6031 build_function_type (void_type_node, NULL_TREE));
6032 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6033 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6034 RESULT_DECL, NULL_TREE, void_type_node);
6036 /* Output a comment. */
6037 fprintf (asm_out_file, "\t# Stub function for %s (",
6038 current_function_name ());
6040 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6042 fprintf (asm_out_file, "%s%s", separator,
6043 (f & 3) == 1 ? "float" : "double");
6046 fprintf (asm_out_file, ")\n");
6048 /* Start the function definition. */
6049 assemble_start_function (stubdecl, stubname);
6050 mips_start_function_definition (stubname, false);
6052 /* If generating pic2 code, either set up the global pointer or
6054 if (TARGET_ABICALLS_PIC2)
6056 if (TARGET_ABSOLUTE_ABICALLS)
6057 fprintf (asm_out_file, "\t.option\tpic0\n");
6060 output_asm_insn ("%(.cpload\t%^%)", NULL);
6061 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6062 target function is. Use a local GOT access when loading the
6063 symbol, to cut down on the number of unnecessary GOT entries
6064 for stubs that aren't needed. */
6065 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6070 /* Load the address of the MIPS16 function into $25. Do this first so
6071 that targets with coprocessor interlocks can use an MFC1 to fill the
6073 output_asm_insn ("la\t%^,%0", &symbol);
6075 /* Move the arguments from floating-point registers to general registers. */
6076 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6078 /* Jump to the MIPS16 function. */
6079 output_asm_insn ("jr\t%^", NULL);
6081 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6082 fprintf (asm_out_file, "\t.option\tpic2\n");
6084 mips_end_function_definition (stubname);
6086 /* If the linker needs to create a dynamic symbol for the target
6087 function, it will associate the symbol with the stub (which,
6088 unlike the target function, follows the proper calling conventions).
6089 It is therefore useful to have a local alias for the target function,
6090 so that it can still be identified as MIPS16 code. As an optimization,
6091 this symbol can also be used for indirect MIPS16 references from
6092 within this file. */
6093 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6095 switch_to_section (function_section (current_function_decl));
6098 /* The current function is a MIPS16 function that returns a value in an FPR.
6099 Copy the return value from its soft-float to its hard-float location.
6100 libgcc2 has special non-MIPS16 helper functions for each case. */
6103 mips16_copy_fpr_return_value (void)
6105 rtx fn, insn, retval;
6107 enum machine_mode return_mode;
6110 return_type = DECL_RESULT (current_function_decl);
6111 return_mode = DECL_MODE (return_type);
6113 name = ACONCAT (("__mips16_ret_",
6114 mips16_call_stub_mode_suffix (return_mode),
6116 fn = mips16_stub_function (name);
6118 /* The function takes arguments in $2 (and possibly $3), so calls
6119 to it cannot be lazily bound. */
6120 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6122 /* Model the call as something that takes the GPR return value as
6123 argument and returns an "updated" value. */
6124 retval = gen_rtx_REG (return_mode, GP_RETURN);
6125 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6126 const0_rtx, NULL_RTX, false);
6127 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6130 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6131 RETVAL is the location of the return value, or null if this is
6132 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6133 arguments and FP_CODE is the code built by mips_function_arg;
6134 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6136 There are three alternatives:
6138 - If a stub was needed, emit the call and return the call insn itself.
6140 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6141 to the new target and return null.
6143 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6146 A stub is needed for calls to functions that, in normal mode,
6147 receive arguments in FPRs or return values in FPRs. The stub
6148 copies the arguments from their soft-float positions to their
6149 hard-float positions, calls the real function, then copies the
6150 return value from its hard-float position to its soft-float
6153 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6154 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6155 automatically redirects the JAL to the stub, otherwise the JAL
6156 continues to call FN directly. */
6159 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6163 struct mips16_stub *l;
6166 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6167 we were invoked with the -msoft-float option. */
6168 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6171 /* Figure out whether the value might come back in a floating-point
6173 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6175 /* We don't need to do anything if there were no floating-point
6176 arguments and the value will not be returned in a floating-point
6178 if (fp_code == 0 && !fp_ret_p)
6181 /* We don't need to do anything if this is a call to a special
6182 MIPS16 support function. */
6184 if (mips16_stub_function_p (fn))
6187 /* This code will only work for o32 and o64 abis. The other ABI's
6188 require more sophisticated support. */
6189 gcc_assert (TARGET_OLDABI);
6191 /* If we're calling via a function pointer, use one of the magic
6192 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6193 Each stub expects the function address to arrive in register $2. */
6194 if (GET_CODE (fn) != SYMBOL_REF
6195 || !call_insn_operand (fn, VOIDmode))
6198 rtx stub_fn, insn, addr;
6201 /* If this is a locally-defined and locally-binding function,
6202 avoid the stub by calling the local alias directly. */
6203 if (mips16_local_function_p (fn))
6205 *fn_ptr = mips16_local_alias (fn);
6209 /* Create a SYMBOL_REF for the libgcc.a function. */
6211 sprintf (buf, "__mips16_call_stub_%s_%d",
6212 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6215 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6216 stub_fn = mips16_stub_function (buf);
6218 /* The function uses $2 as an argument, so calls to it
6219 cannot be lazily bound. */
6220 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6222 /* Load the target function into $2. */
6223 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6224 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6226 /* Emit the call. */
6227 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6228 args_size, NULL_RTX, lazy_p);
6230 /* Tell GCC that this call does indeed use the value of $2. */
6231 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6233 /* If we are handling a floating-point return value, we need to
6234 save $18 in the function prologue. Putting a note on the
6235 call will mean that df_regs_ever_live_p ($18) will be true if the
6236 call is not eliminated, and we can check that in the prologue
6239 CALL_INSN_FUNCTION_USAGE (insn) =
6240 gen_rtx_EXPR_LIST (VOIDmode,
6241 gen_rtx_CLOBBER (VOIDmode,
6242 gen_rtx_REG (word_mode, 18)),
6243 CALL_INSN_FUNCTION_USAGE (insn));
6248 /* We know the function we are going to call. If we have already
6249 built a stub, we don't need to do anything further. */
6250 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6251 for (l = mips16_stubs; l != NULL; l = l->next)
6252 if (strcmp (l->name, fnname) == 0)
6257 const char *separator;
6258 char *secname, *stubname;
6259 tree stubid, stubdecl;
6262 /* If the function does not return in FPRs, the special stub
6266 If the function does return in FPRs, the stub section is named
6267 .mips16.call.fp.FNNAME
6269 Build a decl for the stub. */
6270 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6272 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6274 stubid = get_identifier (stubname);
6275 stubdecl = build_decl (BUILTINS_LOCATION,
6276 FUNCTION_DECL, stubid,
6277 build_function_type (void_type_node, NULL_TREE));
6278 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6279 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6280 RESULT_DECL, NULL_TREE,
6283 /* Output a comment. */
6284 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6286 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6290 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6292 fprintf (asm_out_file, "%s%s", separator,
6293 (f & 3) == 1 ? "float" : "double");
6296 fprintf (asm_out_file, ")\n");
6298 /* Start the function definition. */
6299 assemble_start_function (stubdecl, stubname);
6300 mips_start_function_definition (stubname, false);
6304 /* Load the address of the MIPS16 function into $25. Do this
6305 first so that targets with coprocessor interlocks can use
6306 an MFC1 to fill the delay slot. */
6307 if (TARGET_EXPLICIT_RELOCS)
6309 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6310 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6313 output_asm_insn ("la\t%^,%0", &fn);
6316 /* Move the arguments from general registers to floating-point
6318 mips_output_args_xfer (fp_code, 't');
6322 /* Jump to the previously-loaded address. */
6323 output_asm_insn ("jr\t%^", NULL);
6327 /* Save the return address in $18 and call the non-MIPS16 function.
6328 The stub's caller knows that $18 might be clobbered, even though
6329 $18 is usually a call-saved register. */
6330 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6331 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6332 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6334 /* Move the result from floating-point registers to
6335 general registers. */
6336 switch (GET_MODE (retval))
6339 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6341 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6343 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6344 TARGET_LITTLE_ENDIAN
6345 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6347 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6349 /* On 64-bit targets, complex floats are returned in
6350 a single GPR, such that "sd" on a suitably-aligned
6351 target would store the value correctly. */
6352 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6353 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6354 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6355 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6356 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6357 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6358 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6359 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6360 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6361 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6362 reg_names[GP_RETURN],
6363 reg_names[GP_RETURN],
6364 reg_names[GP_RETURN + 1]);
6369 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6373 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6374 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6378 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6384 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6387 #ifdef ASM_DECLARE_FUNCTION_SIZE
6388 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6391 mips_end_function_definition (stubname);
6393 /* Record this stub. */
6394 l = XNEW (struct mips16_stub);
6395 l->name = xstrdup (fnname);
6396 l->fp_ret_p = fp_ret_p;
6397 l->next = mips16_stubs;
6401 /* If we expect a floating-point return value, but we've built a
6402 stub which does not expect one, then we're in trouble. We can't
6403 use the existing stub, because it won't handle the floating-point
6404 value. We can't build a new stub, because the linker won't know
6405 which stub to use for the various calls in this object file.
6406 Fortunately, this case is illegal, since it means that a function
6407 was declared in two different ways in a single compilation. */
6408 if (fp_ret_p && !l->fp_ret_p)
6409 error ("cannot handle inconsistent calls to %qs", fnname);
6411 if (retval == NULL_RTX)
6412 insn = gen_call_internal_direct (fn, args_size);
6414 insn = gen_call_value_internal_direct (retval, fn, args_size);
6415 insn = mips_emit_call_insn (insn, fn, fn, false);
6417 /* If we are calling a stub which handles a floating-point return
6418 value, we need to arrange to save $18 in the prologue. We do this
6419 by marking the function call as using the register. The prologue
6420 will later see that it is used, and emit code to save it. */
6422 CALL_INSN_FUNCTION_USAGE (insn) =
6423 gen_rtx_EXPR_LIST (VOIDmode,
6424 gen_rtx_CLOBBER (VOIDmode,
6425 gen_rtx_REG (word_mode, 18)),
6426 CALL_INSN_FUNCTION_USAGE (insn));
6431 /* Expand a call of type TYPE. RESULT is where the result will go (null
6432 for "call"s and "sibcall"s), ADDR is the address of the function,
6433 ARGS_SIZE is the size of the arguments and AUX is the value passed
6434 to us by mips_function_arg. LAZY_P is true if this call already
6435 involves a lazily-bound function address (such as when calling
6436 functions through a MIPS16 hard-float stub).
6438 Return the call itself. */
6441 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6442 rtx args_size, rtx aux, bool lazy_p)
6444 rtx orig_addr, pattern, insn;
6447 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6448 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6451 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6456 if (!call_insn_operand (addr, VOIDmode))
6458 if (type == MIPS_CALL_EPILOGUE)
6459 addr = MIPS_EPILOGUE_TEMP (Pmode);
6461 addr = gen_reg_rtx (Pmode);
6462 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6467 rtx (*fn) (rtx, rtx);
6469 if (type == MIPS_CALL_SIBCALL)
6470 fn = gen_sibcall_internal;
6472 fn = gen_call_internal;
6474 pattern = fn (addr, args_size);
6476 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6478 /* Handle return values created by mips_return_fpr_pair. */
6479 rtx (*fn) (rtx, rtx, rtx, rtx);
6482 if (type == MIPS_CALL_SIBCALL)
6483 fn = gen_sibcall_value_multiple_internal;
6485 fn = gen_call_value_multiple_internal;
6487 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6488 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6489 pattern = fn (reg1, addr, args_size, reg2);
6493 rtx (*fn) (rtx, rtx, rtx);
6495 if (type == MIPS_CALL_SIBCALL)
6496 fn = gen_sibcall_value_internal;
6498 fn = gen_call_value_internal;
6500 /* Handle return values created by mips_return_fpr_single. */
6501 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6502 result = XEXP (XVECEXP (result, 0, 0), 0);
6503 pattern = fn (result, addr, args_size);
6506 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6509 /* Split call instruction INSN into a $gp-clobbering call and
6510 (where necessary) an instruction to restore $gp from its save slot.
6511 CALL_PATTERN is the pattern of the new call. */
6514 mips_split_call (rtx insn, rtx call_pattern)
6516 emit_call_insn (call_pattern);
6517 if (!find_reg_note (insn, REG_NORETURN, 0))
6518 /* Pick a temporary register that is suitable for both MIPS16 and
6519 non-MIPS16 code. $4 and $5 are used for returning complex double
6520 values in soft-float code, so $6 is the first suitable candidate. */
6521 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6524 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6527 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6529 if (!TARGET_SIBCALLS)
6532 /* Interrupt handlers need special epilogue code and therefore can't
6534 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6537 /* We can't do a sibcall if the called function is a MIPS16 function
6538 because there is no direct "jx" instruction equivalent to "jalx" to
6539 switch the ISA mode. We only care about cases where the sibling
6540 and normal calls would both be direct. */
6542 && mips_use_mips16_mode_p (decl)
6543 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6546 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6547 functions could be MIPS16 ones unless an attribute explicitly tells
6549 if (TARGET_INTERLINK_MIPS16
6551 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6552 && !mips_nomips16_decl_p (decl)
6553 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6560 /* Emit code to move general operand SRC into condition-code
6561 register DEST given that SCRATCH is a scratch TFmode FPR.
6568 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6571 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6575 /* Change the source to SFmode. */
6577 src = adjust_address (src, SFmode, 0);
6578 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6579 src = gen_rtx_REG (SFmode, true_regnum (src));
6581 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6582 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6584 mips_emit_move (copy_rtx (fp1), src);
6585 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6586 emit_insn (gen_slt_sf (dest, fp2, fp1));
6589 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6590 Assume that the areas do not overlap. */
6593 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6595 HOST_WIDE_INT offset, delta;
6596 unsigned HOST_WIDE_INT bits;
6598 enum machine_mode mode;
6601 /* Work out how many bits to move at a time. If both operands have
6602 half-word alignment, it is usually better to move in half words.
6603 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6604 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6605 Otherwise move word-sized chunks. */
6606 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6607 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6608 bits = BITS_PER_WORD / 2;
6610 bits = BITS_PER_WORD;
6612 mode = mode_for_size (bits, MODE_INT, 0);
6613 delta = bits / BITS_PER_UNIT;
6615 /* Allocate a buffer for the temporary registers. */
6616 regs = XALLOCAVEC (rtx, length / delta);
6618 /* Load as many BITS-sized chunks as possible. Use a normal load if
6619 the source has enough alignment, otherwise use left/right pairs. */
6620 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6622 regs[i] = gen_reg_rtx (mode);
6623 if (MEM_ALIGN (src) >= bits)
6624 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6627 rtx part = adjust_address (src, BLKmode, offset);
6628 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6633 /* Copy the chunks to the destination. */
6634 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6635 if (MEM_ALIGN (dest) >= bits)
6636 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6639 rtx part = adjust_address (dest, BLKmode, offset);
6640 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6644 /* Mop up any left-over bytes. */
6645 if (offset < length)
6647 src = adjust_address (src, BLKmode, offset);
6648 dest = adjust_address (dest, BLKmode, offset);
6649 move_by_pieces (dest, src, length - offset,
6650 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6654 /* Helper function for doing a loop-based block operation on memory
6655 reference MEM. Each iteration of the loop will operate on LENGTH
6658 Create a new base register for use within the loop and point it to
6659 the start of MEM. Create a new memory reference that uses this
6660 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6663 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6664 rtx *loop_reg, rtx *loop_mem)
6666 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6668 /* Although the new mem does not refer to a known location,
6669 it does keep up to LENGTH bytes of alignment. */
6670 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6671 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6674 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6675 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6676 the memory regions do not overlap. */
6679 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6680 HOST_WIDE_INT bytes_per_iter)
6682 rtx label, src_reg, dest_reg, final_src, test;
6683 HOST_WIDE_INT leftover;
6685 leftover = length % bytes_per_iter;
6688 /* Create registers and memory references for use within the loop. */
6689 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6690 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6692 /* Calculate the value that SRC_REG should have after the last iteration
6694 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6697 /* Emit the start of the loop. */
6698 label = gen_label_rtx ();
6701 /* Emit the loop body. */
6702 mips_block_move_straight (dest, src, bytes_per_iter);
6704 /* Move on to the next block. */
6705 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6706 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6708 /* Emit the loop condition. */
6709 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6710 if (Pmode == DImode)
6711 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6713 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6715 /* Mop up any left-over bytes. */
6717 mips_block_move_straight (dest, src, leftover);
6720 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6721 memory reference SRC to memory reference DEST. */
6724 mips_expand_block_move (rtx dest, rtx src, rtx length)
6726 if (CONST_INT_P (length))
6728 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6730 mips_block_move_straight (dest, src, INTVAL (length));
6735 mips_block_move_loop (dest, src, INTVAL (length),
6736 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6743 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6746 mips_expand_synci_loop (rtx begin, rtx end)
6748 rtx inc, label, end_label, cmp_result, mask, length;
6750 /* Create end_label. */
6751 end_label = gen_label_rtx ();
6753 /* Check if begin equals end. */
6754 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6755 emit_jump_insn (gen_condjump (cmp_result, end_label));
6757 /* Load INC with the cache line size (rdhwr INC,$1). */
6758 inc = gen_reg_rtx (Pmode);
6759 emit_insn (Pmode == SImode
6760 ? gen_rdhwr_synci_step_si (inc)
6761 : gen_rdhwr_synci_step_di (inc));
6763 /* Check if inc is 0. */
6764 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
6765 emit_jump_insn (gen_condjump (cmp_result, end_label));
6767 /* Calculate mask. */
6768 mask = mips_force_unary (Pmode, NEG, inc);
6770 /* Mask out begin by mask. */
6771 begin = mips_force_binary (Pmode, AND, begin, mask);
6773 /* Calculate length. */
6774 length = mips_force_binary (Pmode, MINUS, end, begin);
6776 /* Loop back to here. */
6777 label = gen_label_rtx ();
6780 emit_insn (gen_synci (begin));
6782 /* Update length. */
6783 mips_emit_binary (MINUS, length, length, inc);
6786 mips_emit_binary (PLUS, begin, begin, inc);
6788 /* Check if length is greater than 0. */
6789 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
6790 emit_jump_insn (gen_condjump (cmp_result, label));
6792 emit_label (end_label);
6795 /* Expand a QI or HI mode atomic memory operation.
6797 GENERATOR contains a pointer to the gen_* function that generates
6798 the SI mode underlying atomic operation using masks that we
6801 RESULT is the return register for the operation. Its value is NULL
6804 MEM is the location of the atomic access.
6806 OLDVAL is the first operand for the operation.
6808 NEWVAL is the optional second operand for the operation. Its value
6809 is NULL if unused. */
6812 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6813 rtx result, rtx mem, rtx oldval, rtx newval)
6815 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6816 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6818 enum machine_mode mode;
6820 mode = GET_MODE (mem);
6822 /* Compute the address of the containing SImode value. */
6823 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6824 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6825 force_reg (Pmode, GEN_INT (-4)));
6827 /* Create a memory reference for it. */
6828 memsi = gen_rtx_MEM (SImode, memsi_addr);
6829 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6830 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6832 /* Work out the byte offset of the QImode or HImode value,
6833 counting from the least significant byte. */
6834 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6835 if (TARGET_BIG_ENDIAN)
6836 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6838 /* Multiply by eight to convert the shift value from bytes to bits. */
6839 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6841 /* Make the final shift an SImode value, so that it can be used in
6842 SImode operations. */
6843 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6845 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6846 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6847 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6848 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6850 /* Compute the equivalent exclusive mask. */
6851 inverted_mask = gen_reg_rtx (SImode);
6852 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6853 gen_rtx_NOT (SImode, mask)));
6855 /* Shift the old value into place. */
6856 if (oldval != const0_rtx)
6858 oldval = convert_modes (SImode, mode, oldval, true);
6859 oldval = force_reg (SImode, oldval);
6860 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6863 /* Do the same for the new value. */
6864 if (newval && newval != const0_rtx)
6866 newval = convert_modes (SImode, mode, newval, true);
6867 newval = force_reg (SImode, newval);
6868 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6871 /* Do the SImode atomic access. */
6873 res = gen_reg_rtx (SImode);
6875 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6877 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6879 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6885 /* Shift and convert the result. */
6886 mips_emit_binary (AND, res, res, mask);
6887 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6888 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6892 /* Return true if it is possible to use left/right accesses for a
6893 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6894 returning true, update *OP, *LEFT and *RIGHT as follows:
6896 *OP is a BLKmode reference to the whole field.
6898 *LEFT is a QImode reference to the first byte if big endian or
6899 the last byte if little endian. This address can be used in the
6900 left-side instructions (LWL, SWL, LDL, SDL).
6902 *RIGHT is a QImode reference to the opposite end of the field and
6903 can be used in the patterning right-side instruction. */
6906 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6907 rtx *left, rtx *right)
6911 /* Check that the operand really is a MEM. Not all the extv and
6912 extzv predicates are checked. */
6916 /* Check that the size is valid. */
6917 if (width != 32 && (!TARGET_64BIT || width != 64))
6920 /* We can only access byte-aligned values. Since we are always passed
6921 a reference to the first byte of the field, it is not necessary to
6922 do anything with BITPOS after this check. */
6923 if (bitpos % BITS_PER_UNIT != 0)
6926 /* Reject aligned bitfields: we want to use a normal load or store
6927 instead of a left/right pair. */
6928 if (MEM_ALIGN (*op) >= width)
6931 /* Adjust *OP to refer to the whole field. This also has the effect
6932 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6933 *op = adjust_address (*op, BLKmode, 0);
6934 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6936 /* Get references to both ends of the field. We deliberately don't
6937 use the original QImode *OP for FIRST since the new BLKmode one
6938 might have a simpler address. */
6939 first = adjust_address (*op, QImode, 0);
6940 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6942 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6943 correspond to the MSB and RIGHT to the LSB. */
6944 if (TARGET_BIG_ENDIAN)
6945 *left = first, *right = last;
6947 *left = last, *right = first;
6952 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6953 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6954 the operation is the equivalent of:
6956 (set DEST (*_extract SRC WIDTH BITPOS))
6958 Return true on success. */
6961 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6962 HOST_WIDE_INT bitpos)
6964 rtx left, right, temp;
6966 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6967 be a paradoxical word_mode subreg. This is the only case in which
6968 we allow the destination to be larger than the source. */
6969 if (GET_CODE (dest) == SUBREG
6970 && GET_MODE (dest) == DImode
6971 && GET_MODE (SUBREG_REG (dest)) == SImode)
6972 dest = SUBREG_REG (dest);
6974 /* After the above adjustment, the destination must be the same
6975 width as the source. */
6976 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6979 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6982 temp = gen_reg_rtx (GET_MODE (dest));
6983 if (GET_MODE (dest) == DImode)
6985 emit_insn (gen_mov_ldl (temp, src, left));
6986 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6990 emit_insn (gen_mov_lwl (temp, src, left));
6991 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6996 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6997 BITPOS and SRC are the operands passed to the expander; the operation
6998 is the equivalent of:
7000 (set (zero_extract DEST WIDTH BITPOS) SRC)
7002 Return true on success. */
7005 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7006 HOST_WIDE_INT bitpos)
7009 enum machine_mode mode;
7011 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7014 mode = mode_for_size (width, MODE_INT, 0);
7015 src = gen_lowpart (mode, src);
7018 emit_insn (gen_mov_sdl (dest, src, left));
7019 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7023 emit_insn (gen_mov_swl (dest, src, left));
7024 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7029 /* Return true if X is a MEM with the same size as MODE. */
7032 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7039 size = MEM_SIZE (x);
7040 return size && INTVAL (size) == GET_MODE_SIZE (mode);
7043 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7044 source of an "ext" instruction or the destination of an "ins"
7045 instruction. OP must be a register operand and the following
7046 conditions must hold:
7048 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7049 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7050 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7052 Also reject lengths equal to a word as they are better handled
7053 by the move patterns. */
7056 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7058 if (!ISA_HAS_EXT_INS
7059 || !register_operand (op, VOIDmode)
7060 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7063 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7066 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7072 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7073 operation if MAXLEN is the maxium length of consecutive bits that
7074 can make up MASK. MODE is the mode of the operation. See
7075 mask_low_and_shift_len for the actual definition. */
7078 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7080 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7083 /* Return true iff OP1 and OP2 are valid operands together for the
7084 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7085 see the table in the comment before the pattern. */
7088 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7090 return (memory_operand (op1, mode)
7091 ? and_load_operand (op2, mode)
7092 : and_reg_operand (op2, mode));
7095 /* The canonical form of a mask-low-and-shift-left operation is
7096 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7097 cleared. Thus we need to shift MASK to the right before checking if it
7098 is a valid mask value. MODE is the mode of the operation. If true
7099 return the length of the mask, otherwise return -1. */
7102 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7104 HOST_WIDE_INT shval;
7106 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7107 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7110 /* Return true if -msplit-addresses is selected and should be honored.
7112 -msplit-addresses is a half-way house between explicit relocations
7113 and the traditional assembler macros. It can split absolute 32-bit
7114 symbolic constants into a high/lo_sum pair but uses macros for other
7117 Like explicit relocation support for REL targets, it relies
7118 on GNU extensions in the assembler and the linker.
7120 Although this code should work for -O0, it has traditionally
7121 been treated as an optimization. */
7124 mips_split_addresses_p (void)
7126 return (TARGET_SPLIT_ADDRESSES
7130 && !ABI_HAS_64BIT_SYMBOLS);
7133 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7136 mips_init_relocs (void)
7138 memset (mips_split_p, '\0', sizeof (mips_split_p));
7139 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7140 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7141 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7143 if (ABI_HAS_64BIT_SYMBOLS)
7145 if (TARGET_EXPLICIT_RELOCS)
7147 mips_split_p[SYMBOL_64_HIGH] = true;
7148 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7149 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7151 mips_split_p[SYMBOL_64_MID] = true;
7152 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7153 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7155 mips_split_p[SYMBOL_64_LOW] = true;
7156 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7157 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7159 mips_split_p[SYMBOL_ABSOLUTE] = true;
7160 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7165 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7167 mips_split_p[SYMBOL_ABSOLUTE] = true;
7168 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7169 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7171 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7177 /* The high part is provided by a pseudo copy of $gp. */
7178 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7179 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7181 else if (TARGET_EXPLICIT_RELOCS)
7182 /* Small data constants are kept whole until after reload,
7183 then lowered by mips_rewrite_small_data. */
7184 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7186 if (TARGET_EXPLICIT_RELOCS)
7188 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7191 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7192 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7196 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7197 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7200 /* Expose the use of $28 as soon as possible. */
7201 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7205 /* The HIGH and LO_SUM are matched by special .md patterns. */
7206 mips_split_p[SYMBOL_GOT_DISP] = true;
7208 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7209 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7210 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7212 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7213 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7214 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7219 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7221 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7222 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7224 /* Expose the use of $28 as soon as possible. */
7225 mips_split_p[SYMBOL_GOT_DISP] = true;
7231 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7232 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7233 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7236 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7237 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7239 mips_split_p[SYMBOL_DTPREL] = true;
7240 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7241 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7243 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7245 mips_split_p[SYMBOL_TPREL] = true;
7246 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7247 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7249 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7252 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7253 in context CONTEXT. RELOCS is the array of relocations to use. */
7256 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7257 const char **relocs)
7259 enum mips_symbol_type symbol_type;
7262 symbol_type = mips_classify_symbolic_expression (op, context);
7263 gcc_assert (relocs[symbol_type]);
7265 fputs (relocs[symbol_type], file);
7266 output_addr_const (file, mips_strip_unspec_address (op));
7267 for (p = relocs[symbol_type]; *p != 0; p++)
7272 /* Start a new block with the given asm switch enabled. If we need
7273 to print a directive, emit PREFIX before it and SUFFIX after it. */
7276 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7277 const char *prefix, const char *suffix)
7279 if (asm_switch->nesting_level == 0)
7280 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7281 asm_switch->nesting_level++;
7284 /* Likewise, but end a block. */
7287 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7288 const char *prefix, const char *suffix)
7290 gcc_assert (asm_switch->nesting_level);
7291 asm_switch->nesting_level--;
7292 if (asm_switch->nesting_level == 0)
7293 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7296 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7297 that either print a complete line or print nothing. */
7300 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7302 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7306 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7308 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7311 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7312 The punctuation characters are:
7314 '(' Start a nested ".set noreorder" block.
7315 ')' End a nested ".set noreorder" block.
7316 '[' Start a nested ".set noat" block.
7317 ']' End a nested ".set noat" block.
7318 '<' Start a nested ".set nomacro" block.
7319 '>' End a nested ".set nomacro" block.
7320 '*' Behave like %(%< if generating a delayed-branch sequence.
7321 '#' Print a nop if in a ".set noreorder" block.
7322 '/' Like '#', but do nothing within a delayed-branch sequence.
7323 '?' Print "l" if mips_branch_likely is true
7324 '~' Print a nop if mips_branch_likely is true
7325 '.' Print the name of the register with a hard-wired zero (zero or $0).
7326 '@' Print the name of the assembler temporary register (at or $1).
7327 '^' Print the name of the pic call-through register (t9 or $25).
7328 '+' Print the name of the gp register (usually gp or $28).
7329 '$' Print the name of the stack pointer register (sp or $29).
7331 See also mips_init_print_operand_pucnt. */
7334 mips_print_operand_punctuation (FILE *file, int ch)
7339 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7343 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7347 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7351 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7355 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7359 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7363 if (final_sequence != 0)
7365 mips_print_operand_punctuation (file, '(');
7366 mips_print_operand_punctuation (file, '<');
7371 if (mips_noreorder.nesting_level > 0)
7372 fputs ("\n\tnop", file);
7376 /* Print an extra newline so that the delayed insn is separated
7377 from the following ones. This looks neater and is consistent
7378 with non-nop delayed sequences. */
7379 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7380 fputs ("\n\tnop\n", file);
7384 if (mips_branch_likely)
7389 if (mips_branch_likely)
7390 fputs ("\n\tnop", file);
7394 fputs (reg_names[GP_REG_FIRST + 0], file);
7398 fputs (reg_names[AT_REGNUM], file);
7402 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7406 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7410 fputs (reg_names[STACK_POINTER_REGNUM], file);
7419 /* Initialize mips_print_operand_punct. */
7422 mips_init_print_operand_punct (void)
7426 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7427 mips_print_operand_punct[(unsigned char) *p] = true;
7430 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7431 associated with condition CODE. Print the condition part of the
7435 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7449 /* Conveniently, the MIPS names for these conditions are the same
7450 as their RTL equivalents. */
7451 fputs (GET_RTX_NAME (code), file);
7455 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7460 /* Likewise floating-point branches. */
7463 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7468 fputs ("c1f", file);
7472 fputs ("c1t", file);
7476 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7481 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7484 mips_print_operand_punct_valid_p (unsigned char code)
7486 return mips_print_operand_punct[code];
7489 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7491 'X' Print CONST_INT OP in hexadecimal format.
7492 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7493 'd' Print CONST_INT OP in decimal.
7494 'm' Print one less than CONST_INT OP in decimal.
7495 'h' Print the high-part relocation associated with OP, after stripping
7497 'R' Print the low-part relocation associated with OP.
7498 'C' Print the integer branch condition for comparison OP.
7499 'N' Print the inverse of the integer branch condition for comparison OP.
7500 'F' Print the FPU branch condition for comparison OP.
7501 'W' Print the inverse of the FPU branch condition for comparison OP.
7502 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7503 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7504 't' Like 'T', but with the EQ/NE cases reversed
7505 'Y' Print mips_fp_conditions[INTVAL (OP)]
7506 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7507 'q' Print a DSP accumulator register.
7508 'D' Print the second part of a double-word register or memory operand.
7509 'L' Print the low-order register in a double-word register operand.
7510 'M' Print high-order register in a double-word register operand.
7511 'z' Print $0 if OP is zero, otherwise print OP normally. */
7514 mips_print_operand (FILE *file, rtx op, int letter)
7518 if (mips_print_operand_punct_valid_p (letter))
7520 mips_print_operand_punctuation (file, letter);
7525 code = GET_CODE (op);
7530 if (CONST_INT_P (op))
7531 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7533 output_operand_lossage ("invalid use of '%%%c'", letter);
7537 if (CONST_INT_P (op))
7538 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7540 output_operand_lossage ("invalid use of '%%%c'", letter);
7544 if (CONST_INT_P (op))
7545 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7547 output_operand_lossage ("invalid use of '%%%c'", letter);
7551 if (CONST_INT_P (op))
7552 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7554 output_operand_lossage ("invalid use of '%%%c'", letter);
7560 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7564 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7568 mips_print_int_branch_condition (file, code, letter);
7572 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7576 mips_print_float_branch_condition (file, code, letter);
7580 mips_print_float_branch_condition (file, reverse_condition (code),
7587 int truth = (code == NE) == (letter == 'T');
7588 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7593 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7594 fputs (mips_fp_conditions[UINTVAL (op)], file);
7596 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7603 mips_print_operand (file, op, 0);
7609 if (code == REG && MD_REG_P (REGNO (op)))
7610 fprintf (file, "$ac0");
7611 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7612 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7614 output_operand_lossage ("invalid use of '%%%c'", letter);
7622 unsigned int regno = REGNO (op);
7623 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7624 || (letter == 'L' && TARGET_BIG_ENDIAN)
7627 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7628 output_operand_lossage ("invalid use of '%%%c'", letter);
7629 /* We need to print $0 .. $31 for COP0 registers. */
7630 if (COP0_REG_P (regno))
7631 fprintf (file, "$%s", ®_names[regno][4]);
7633 fprintf (file, "%s", reg_names[regno]);
7639 output_address (plus_constant (XEXP (op, 0), 4));
7640 else if (letter && letter != 'z')
7641 output_operand_lossage ("invalid use of '%%%c'", letter);
7643 output_address (XEXP (op, 0));
7647 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7648 fputs (reg_names[GP_REG_FIRST], file);
7649 else if (letter && letter != 'z')
7650 output_operand_lossage ("invalid use of '%%%c'", letter);
7651 else if (CONST_GP_P (op))
7652 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7654 output_addr_const (file, mips_strip_unspec_address (op));
7660 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7663 mips_print_operand_address (FILE *file, rtx x)
7665 struct mips_address_info addr;
7667 if (mips_classify_address (&addr, x, word_mode, true))
7671 mips_print_operand (file, addr.offset, 0);
7672 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7675 case ADDRESS_LO_SUM:
7676 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7678 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7681 case ADDRESS_CONST_INT:
7682 output_addr_const (file, x);
7683 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7686 case ADDRESS_SYMBOLIC:
7687 output_addr_const (file, mips_strip_unspec_address (x));
7693 /* Implement TARGET_ENCODE_SECTION_INFO. */
7696 mips_encode_section_info (tree decl, rtx rtl, int first)
7698 default_encode_section_info (decl, rtl, first);
7700 if (TREE_CODE (decl) == FUNCTION_DECL)
7702 rtx symbol = XEXP (rtl, 0);
7703 tree type = TREE_TYPE (decl);
7705 /* Encode whether the symbol is short or long. */
7706 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7707 || mips_far_type_p (type))
7708 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7712 /* Implement TARGET_SELECT_RTX_SECTION. */
7715 mips_select_rtx_section (enum machine_mode mode, rtx x,
7716 unsigned HOST_WIDE_INT align)
7718 /* ??? Consider using mergeable small data sections. */
7719 if (mips_rtx_constant_in_small_data_p (mode))
7720 return get_named_section (NULL, ".sdata", 0);
7722 return default_elf_select_rtx_section (mode, x, align);
7725 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7727 The complication here is that, with the combination TARGET_ABICALLS
7728 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7729 absolute addresses, and should therefore not be included in the
7730 read-only part of a DSO. Handle such cases by selecting a normal
7731 data section instead of a read-only one. The logic apes that in
7732 default_function_rodata_section. */
7735 mips_function_rodata_section (tree decl)
7737 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7738 return default_function_rodata_section (decl);
7740 if (decl && DECL_SECTION_NAME (decl))
7742 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7743 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7745 char *rname = ASTRDUP (name);
7747 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7749 else if (flag_function_sections
7750 && flag_data_sections
7751 && strncmp (name, ".text.", 6) == 0)
7753 char *rname = ASTRDUP (name);
7754 memcpy (rname + 1, "data", 4);
7755 return get_section (rname, SECTION_WRITE, decl);
7758 return data_section;
7761 /* Implement TARGET_IN_SMALL_DATA_P. */
7764 mips_in_small_data_p (const_tree decl)
7766 unsigned HOST_WIDE_INT size;
7768 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7771 /* We don't yet generate small-data references for -mabicalls
7772 or VxWorks RTP code. See the related -G handling in
7773 mips_option_override. */
7774 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7777 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7781 /* Reject anything that isn't in a known small-data section. */
7782 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7783 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7786 /* If a symbol is defined externally, the assembler will use the
7787 usual -G rules when deciding how to implement macros. */
7788 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7791 else if (TARGET_EMBEDDED_DATA)
7793 /* Don't put constants into the small data section: we want them
7794 to be in ROM rather than RAM. */
7795 if (TREE_CODE (decl) != VAR_DECL)
7798 if (TREE_READONLY (decl)
7799 && !TREE_SIDE_EFFECTS (decl)
7800 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7804 /* Enforce -mlocal-sdata. */
7805 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7808 /* Enforce -mextern-sdata. */
7809 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7811 if (DECL_EXTERNAL (decl))
7813 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7817 /* We have traditionally not treated zero-sized objects as small data,
7818 so this is now effectively part of the ABI. */
7819 size = int_size_in_bytes (TREE_TYPE (decl));
7820 return size > 0 && size <= mips_small_data_threshold;
7823 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7824 anchors for small data: the GP register acts as an anchor in that
7825 case. We also don't want to use them for PC-relative accesses,
7826 where the PC acts as an anchor. */
7829 mips_use_anchors_for_symbol_p (const_rtx symbol)
7831 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7833 case SYMBOL_PC_RELATIVE:
7834 case SYMBOL_GP_RELATIVE:
7838 return default_use_anchors_for_symbol_p (symbol);
7842 /* The MIPS debug format wants all automatic variables and arguments
7843 to be in terms of the virtual frame pointer (stack pointer before
7844 any adjustment in the function), while the MIPS 3.0 linker wants
7845 the frame pointer to be the stack pointer after the initial
7846 adjustment. So, we do the adjustment here. The arg pointer (which
7847 is eliminated) points to the virtual frame pointer, while the frame
7848 pointer (which may be eliminated) points to the stack pointer after
7849 the initial adjustments. */
7852 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7854 rtx offset2 = const0_rtx;
7855 rtx reg = eliminate_constant_term (addr, &offset2);
7858 offset = INTVAL (offset2);
7860 if (reg == stack_pointer_rtx
7861 || reg == frame_pointer_rtx
7862 || reg == hard_frame_pointer_rtx)
7864 offset -= cfun->machine->frame.total_size;
7865 if (reg == hard_frame_pointer_rtx)
7866 offset += cfun->machine->frame.hard_frame_pointer_offset;
7869 /* sdbout_parms does not want this to crash for unrecognized cases. */
7871 else if (reg != arg_pointer_rtx)
7872 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7879 /* Implement ASM_OUTPUT_EXTERNAL. */
7882 mips_output_external (FILE *file, tree decl, const char *name)
7884 default_elf_asm_output_external (file, decl, name);
7886 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7887 set in order to avoid putting out names that are never really
7889 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7891 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7893 /* When using assembler macros, emit .extern directives for
7894 all small-data externs so that the assembler knows how
7897 In most cases it would be safe (though pointless) to emit
7898 .externs for other symbols too. One exception is when an
7899 object is within the -G limit but declared by the user to
7900 be in a section other than .sbss or .sdata. */
7901 fputs ("\t.extern\t", file);
7902 assemble_name (file, name);
7903 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7904 int_size_in_bytes (TREE_TYPE (decl)));
7909 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7912 mips_output_filename (FILE *stream, const char *name)
7914 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7916 if (write_symbols == DWARF2_DEBUG)
7918 else if (mips_output_filename_first_time)
7920 mips_output_filename_first_time = 0;
7921 num_source_filenames += 1;
7922 current_function_file = name;
7923 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7924 output_quoted_string (stream, name);
7925 putc ('\n', stream);
7927 /* If we are emitting stabs, let dbxout.c handle this (except for
7928 the mips_output_filename_first_time case). */
7929 else if (write_symbols == DBX_DEBUG)
7931 else if (name != current_function_file
7932 && strcmp (name, current_function_file) != 0)
7934 num_source_filenames += 1;
7935 current_function_file = name;
7936 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7937 output_quoted_string (stream, name);
7938 putc ('\n', stream);
7942 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7944 static void ATTRIBUTE_UNUSED
7945 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7950 fputs ("\t.dtprelword\t", file);
7954 fputs ("\t.dtpreldword\t", file);
7960 output_addr_const (file, x);
7961 fputs ("+0x8000", file);
7964 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7967 mips_dwarf_register_span (rtx reg)
7970 enum machine_mode mode;
7972 /* By default, GCC maps increasing register numbers to increasing
7973 memory locations, but paired FPRs are always little-endian,
7974 regardless of the prevailing endianness. */
7975 mode = GET_MODE (reg);
7976 if (FP_REG_P (REGNO (reg))
7977 && TARGET_BIG_ENDIAN
7978 && MAX_FPRS_PER_FMT > 1
7979 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7981 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7982 high = mips_subword (reg, true);
7983 low = mips_subword (reg, false);
7984 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7990 /* Implement ASM_OUTPUT_ASCII. */
7993 mips_output_ascii (FILE *stream, const char *string, size_t len)
7999 fprintf (stream, "\t.ascii\t\"");
8000 for (i = 0; i < len; i++)
8004 c = (unsigned char) string[i];
8007 if (c == '\\' || c == '\"')
8009 putc ('\\', stream);
8017 fprintf (stream, "\\%03o", c);
8021 if (cur_pos > 72 && i+1 < len)
8024 fprintf (stream, "\"\n\t.ascii\t\"");
8027 fprintf (stream, "\"\n");
8030 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8031 macros, mark the symbol as written so that mips_asm_output_external
8032 won't emit an .extern for it. STREAM is the output file, NAME is the
8033 name of the symbol, INIT_STRING is the string that should be written
8034 before the symbol and FINAL_STRING is the string that should be
8035 written after it. FINAL_STRING is a printf format that consumes the
8036 remaining arguments. */
8039 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8040 const char *final_string, ...)
8044 fputs (init_string, stream);
8045 assemble_name (stream, name);
8046 va_start (ap, final_string);
8047 vfprintf (stream, final_string, ap);
8050 if (!TARGET_EXPLICIT_RELOCS)
8052 tree name_tree = get_identifier (name);
8053 TREE_ASM_WRITTEN (name_tree) = 1;
8057 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8058 NAME is the name of the object and ALIGN is the required alignment
8059 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8060 alignment argument. */
8063 mips_declare_common_object (FILE *stream, const char *name,
8064 const char *init_string,
8065 unsigned HOST_WIDE_INT size,
8066 unsigned int align, bool takes_alignment_p)
8068 if (!takes_alignment_p)
8070 size += (align / BITS_PER_UNIT) - 1;
8071 size -= size % (align / BITS_PER_UNIT);
8072 mips_declare_object (stream, name, init_string,
8073 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8076 mips_declare_object (stream, name, init_string,
8077 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8078 size, align / BITS_PER_UNIT);
8081 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8082 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8085 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8086 unsigned HOST_WIDE_INT size,
8089 /* If the target wants uninitialized const declarations in
8090 .rdata then don't put them in .comm. */
8091 if (TARGET_EMBEDDED_DATA
8092 && TARGET_UNINIT_CONST_IN_RODATA
8093 && TREE_CODE (decl) == VAR_DECL
8094 && TREE_READONLY (decl)
8095 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8097 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8098 targetm.asm_out.globalize_label (stream, name);
8100 switch_to_section (readonly_data_section);
8101 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8102 mips_declare_object (stream, name, "",
8103 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8107 mips_declare_common_object (stream, name, "\n\t.comm\t",
8111 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8112 extern int size_directive_output;
8114 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8115 definitions except that it uses mips_declare_object to emit the label. */
8118 mips_declare_object_name (FILE *stream, const char *name,
8119 tree decl ATTRIBUTE_UNUSED)
8121 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8122 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8125 size_directive_output = 0;
8126 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8130 size_directive_output = 1;
8131 size = int_size_in_bytes (TREE_TYPE (decl));
8132 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8135 mips_declare_object (stream, name, "", ":\n");
8138 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8141 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8145 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8146 if (!flag_inhibit_size_directive
8147 && DECL_SIZE (decl) != 0
8150 && DECL_INITIAL (decl) == error_mark_node
8151 && !size_directive_output)
8155 size_directive_output = 1;
8156 size = int_size_in_bytes (TREE_TYPE (decl));
8157 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8162 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8163 with the current ABI. */
8166 mips_mdebug_abi_name (void)
8179 return TARGET_64BIT ? "eabi64" : "eabi32";
8185 /* Implement TARGET_ASM_FILE_START. */
8188 mips_file_start (void)
8190 default_file_start ();
8192 /* Generate a special section to describe the ABI switches used to
8193 produce the resultant binary. This is unnecessary on IRIX and
8194 causes unwanted warnings from the native linker. */
8197 /* Record the ABI itself. Modern versions of binutils encode
8198 this information in the ELF header flags, but GDB needs the
8199 information in order to correctly debug binaries produced by
8200 older binutils. See the function mips_gdbarch_init in
8202 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8203 mips_mdebug_abi_name ());
8205 /* There is no ELF header flag to distinguish long32 forms of the
8206 EABI from long64 forms. Emit a special section to help tools
8207 such as GDB. Do the same for o64, which is sometimes used with
8209 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8210 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8211 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8213 #ifdef HAVE_AS_GNU_ATTRIBUTE
8217 /* No floating-point operations, -mno-float. */
8218 if (TARGET_NO_FLOAT)
8220 /* Soft-float code, -msoft-float. */
8221 else if (!TARGET_HARD_FLOAT_ABI)
8223 /* Single-float code, -msingle-float. */
8224 else if (!TARGET_DOUBLE_FLOAT)
8226 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8227 else if (!TARGET_64BIT && TARGET_FLOAT64)
8229 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8233 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8238 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8239 if (TARGET_ABICALLS)
8241 fprintf (asm_out_file, "\t.abicalls\n");
8242 if (TARGET_ABICALLS_PIC0)
8243 fprintf (asm_out_file, "\t.option\tpic0\n");
8246 if (flag_verbose_asm)
8247 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8249 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8252 /* Make the last instruction frame-related and note that it performs
8253 the operation described by FRAME_PATTERN. */
8256 mips_set_frame_expr (rtx frame_pattern)
8260 insn = get_last_insn ();
8261 RTX_FRAME_RELATED_P (insn) = 1;
8262 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8267 /* Return a frame-related rtx that stores REG at MEM.
8268 REG must be a single register. */
8271 mips_frame_set (rtx mem, rtx reg)
8275 /* If we're saving the return address register and the DWARF return
8276 address column differs from the hard register number, adjust the
8277 note reg to refer to the former. */
8278 if (REGNO (reg) == RETURN_ADDR_REGNUM
8279 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8280 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8282 set = gen_rtx_SET (VOIDmode, mem, reg);
8283 RTX_FRAME_RELATED_P (set) = 1;
8288 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8289 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8290 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8291 static const unsigned char mips16e_s2_s8_regs[] = {
8292 30, 23, 22, 21, 20, 19, 18
8294 static const unsigned char mips16e_a0_a3_regs[] = {
8298 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8299 ordered from the uppermost in memory to the lowest in memory. */
8300 static const unsigned char mips16e_save_restore_regs[] = {
8301 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8304 /* Return the index of the lowest X in the range [0, SIZE) for which
8305 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8308 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8313 for (i = 0; i < size; i++)
8314 if (BITSET_P (mask, regs[i]))
8320 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8321 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8322 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8323 is true for all indexes (X, SIZE). */
8326 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8327 unsigned int size, unsigned int *num_regs_ptr)
8331 i = mips16e_find_first_register (*mask_ptr, regs, size);
8332 for (i++; i < size; i++)
8333 if (!BITSET_P (*mask_ptr, regs[i]))
8336 *mask_ptr |= 1 << regs[i];
8340 /* Return a simplified form of X using the register values in REG_VALUES.
8341 REG_VALUES[R] is the last value assigned to hard register R, or null
8342 if R has not been modified.
8344 This function is rather limited, but is good enough for our purposes. */
8347 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8349 x = avoid_constant_pool_reference (x);
8353 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8354 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8355 x0, GET_MODE (XEXP (x, 0)));
8358 if (ARITHMETIC_P (x))
8360 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8361 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8362 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8366 && reg_values[REGNO (x)]
8367 && !rtx_unstable_p (reg_values[REGNO (x)]))
8368 return reg_values[REGNO (x)];
8373 /* Return true if (set DEST SRC) stores an argument register into its
8374 caller-allocated save slot, storing the number of that argument
8375 register in *REGNO_PTR if so. REG_VALUES is as for
8376 mips16e_collect_propagate_value. */
8379 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8380 unsigned int *regno_ptr)
8382 unsigned int argno, regno;
8383 HOST_WIDE_INT offset, required_offset;
8386 /* Check that this is a word-mode store. */
8387 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8390 /* Check that the register being saved is an unmodified argument
8392 regno = REGNO (src);
8393 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8395 argno = regno - GP_ARG_FIRST;
8397 /* Check whether the address is an appropriate stack-pointer or
8398 frame-pointer access. */
8399 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8400 mips_split_plus (addr, &base, &offset);
8401 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8402 if (base == hard_frame_pointer_rtx)
8403 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8404 else if (base != stack_pointer_rtx)
8406 if (offset != required_offset)
8413 /* A subroutine of mips_expand_prologue, called only when generating
8414 MIPS16e SAVE instructions. Search the start of the function for any
8415 instructions that save argument registers into their caller-allocated
8416 save slots. Delete such instructions and return a value N such that
8417 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8418 instructions redundant. */
8421 mips16e_collect_argument_saves (void)
8423 rtx reg_values[FIRST_PSEUDO_REGISTER];
8424 rtx insn, next, set, dest, src;
8425 unsigned int nargs, regno;
8427 push_topmost_sequence ();
8429 memset (reg_values, 0, sizeof (reg_values));
8430 for (insn = get_insns (); insn; insn = next)
8432 next = NEXT_INSN (insn);
8433 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8439 set = PATTERN (insn);
8440 if (GET_CODE (set) != SET)
8443 dest = SET_DEST (set);
8444 src = SET_SRC (set);
8445 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8447 if (!BITSET_P (cfun->machine->frame.mask, regno))
8450 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8453 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8454 reg_values[REGNO (dest)]
8455 = mips16e_collect_propagate_value (src, reg_values);
8459 pop_topmost_sequence ();
8464 /* Return a move between register REGNO and memory location SP + OFFSET.
8465 Make the move a load if RESTORE_P, otherwise make it a frame-related
8469 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8474 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8475 reg = gen_rtx_REG (SImode, regno);
8477 ? gen_rtx_SET (VOIDmode, reg, mem)
8478 : mips_frame_set (mem, reg));
8481 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8482 The instruction must:
8484 - Allocate or deallocate SIZE bytes in total; SIZE is known
8487 - Save or restore as many registers in *MASK_PTR as possible.
8488 The instruction saves the first registers at the top of the
8489 allocated area, with the other registers below it.
8491 - Save NARGS argument registers above the allocated area.
8493 (NARGS is always zero if RESTORE_P.)
8495 The SAVE and RESTORE instructions cannot save and restore all general
8496 registers, so there may be some registers left over for the caller to
8497 handle. Destructively modify *MASK_PTR so that it contains the registers
8498 that still need to be saved or restored. The caller can save these
8499 registers in the memory immediately below *OFFSET_PTR, which is a
8500 byte offset from the bottom of the allocated stack area. */
8503 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8504 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8508 HOST_WIDE_INT offset, top_offset;
8509 unsigned int i, regno;
8512 gcc_assert (cfun->machine->frame.num_fp == 0);
8514 /* Calculate the number of elements in the PARALLEL. We need one element
8515 for the stack adjustment, one for each argument register save, and one
8516 for each additional register move. */
8518 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8519 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8522 /* Create the final PARALLEL. */
8523 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8526 /* Add the stack pointer adjustment. */
8527 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8528 plus_constant (stack_pointer_rtx,
8529 restore_p ? size : -size));
8530 RTX_FRAME_RELATED_P (set) = 1;
8531 XVECEXP (pattern, 0, n++) = set;
8533 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8534 top_offset = restore_p ? size : 0;
8536 /* Save the arguments. */
8537 for (i = 0; i < nargs; i++)
8539 offset = top_offset + i * UNITS_PER_WORD;
8540 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8541 XVECEXP (pattern, 0, n++) = set;
8544 /* Then fill in the other register moves. */
8545 offset = top_offset;
8546 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8548 regno = mips16e_save_restore_regs[i];
8549 if (BITSET_P (*mask_ptr, regno))
8551 offset -= UNITS_PER_WORD;
8552 set = mips16e_save_restore_reg (restore_p, offset, regno);
8553 XVECEXP (pattern, 0, n++) = set;
8554 *mask_ptr &= ~(1 << regno);
8558 /* Tell the caller what offset it should use for the remaining registers. */
8559 *offset_ptr = size + (offset - top_offset);
8561 gcc_assert (n == XVECLEN (pattern, 0));
8566 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8567 pointer. Return true if PATTERN matches the kind of instruction
8568 generated by mips16e_build_save_restore. If INFO is nonnull,
8569 initialize it when returning true. */
8572 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8573 struct mips16e_save_restore_info *info)
8575 unsigned int i, nargs, mask, extra;
8576 HOST_WIDE_INT top_offset, save_offset, offset;
8577 rtx set, reg, mem, base;
8580 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8583 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8584 top_offset = adjust > 0 ? adjust : 0;
8586 /* Interpret all other members of the PARALLEL. */
8587 save_offset = top_offset - UNITS_PER_WORD;
8591 for (n = 1; n < XVECLEN (pattern, 0); n++)
8593 /* Check that we have a SET. */
8594 set = XVECEXP (pattern, 0, n);
8595 if (GET_CODE (set) != SET)
8598 /* Check that the SET is a load (if restoring) or a store
8600 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8604 /* Check that the address is the sum of the stack pointer and a
8605 possibly-zero constant offset. */
8606 mips_split_plus (XEXP (mem, 0), &base, &offset);
8607 if (base != stack_pointer_rtx)
8610 /* Check that SET's other operand is a register. */
8611 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8615 /* Check for argument saves. */
8616 if (offset == top_offset + nargs * UNITS_PER_WORD
8617 && REGNO (reg) == GP_ARG_FIRST + nargs)
8619 else if (offset == save_offset)
8621 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8622 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8625 mask |= 1 << REGNO (reg);
8626 save_offset -= UNITS_PER_WORD;
8632 /* Check that the restrictions on register ranges are met. */
8634 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8635 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8636 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8637 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8641 /* Make sure that the topmost argument register is not saved twice.
8642 The checks above ensure that the same is then true for the other
8643 argument registers. */
8644 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8647 /* Pass back information, if requested. */
8650 info->nargs = nargs;
8652 info->size = (adjust > 0 ? adjust : -adjust);
8658 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8659 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8660 the null terminator. */
8663 mips16e_add_register_range (char *s, unsigned int min_reg,
8664 unsigned int max_reg)
8666 if (min_reg != max_reg)
8667 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8669 s += sprintf (s, ",%s", reg_names[min_reg]);
8673 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8674 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8677 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8679 static char buffer[300];
8681 struct mips16e_save_restore_info info;
8682 unsigned int i, end;
8685 /* Parse the pattern. */
8686 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8689 /* Add the mnemonic. */
8690 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8693 /* Save the arguments. */
8695 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8696 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8697 else if (info.nargs == 1)
8698 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8700 /* Emit the amount of stack space to allocate or deallocate. */
8701 s += sprintf (s, "%d", (int) info.size);
8703 /* Save or restore $16. */
8704 if (BITSET_P (info.mask, 16))
8705 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8707 /* Save or restore $17. */
8708 if (BITSET_P (info.mask, 17))
8709 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8711 /* Save or restore registers in the range $s2...$s8, which
8712 mips16e_s2_s8_regs lists in decreasing order. Note that this
8713 is a software register range; the hardware registers are not
8714 numbered consecutively. */
8715 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8716 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8718 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8719 mips16e_s2_s8_regs[i]);
8721 /* Save or restore registers in the range $a0...$a3. */
8722 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8723 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8725 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8726 mips16e_a0_a3_regs[end - 1]);
8728 /* Save or restore $31. */
8729 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8730 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8735 /* Return true if the current function returns its value in a floating-point
8736 register in MIPS16 mode. */
8739 mips16_cfun_returns_in_fpr_p (void)
8741 tree return_type = DECL_RESULT (current_function_decl);
8742 return (TARGET_MIPS16
8743 && TARGET_HARD_FLOAT_ABI
8744 && !aggregate_value_p (return_type, current_function_decl)
8745 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8748 /* Return true if predicate PRED is true for at least one instruction.
8749 Cache the result in *CACHE, and assume that the result is true
8750 if *CACHE is already true. */
8753 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8759 push_topmost_sequence ();
8760 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8761 if (USEFUL_INSN_P (insn) && pred (insn))
8766 pop_topmost_sequence ();
8771 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8772 See mips_cfun_has_inflexible_gp_ref_p for details. */
8775 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8777 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8778 indicate that the target could be a traditional MIPS
8779 lazily-binding stub. */
8780 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8783 /* Return true if the current function refers to the global pointer
8784 in a way that forces $28 to be valid. This means that we can't
8785 change the choice of global pointer, even for NewABI code.
8787 One example of this (and one which needs several checks) is that
8788 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8789 (This restriction does not apply to PLTs.) */
8792 mips_cfun_has_inflexible_gp_ref_p (void)
8794 /* If the function has a nonlocal goto, $28 must hold the correct
8795 global pointer for the target function. That is, the target
8796 of the goto implicitly uses $28. */
8797 if (crtl->has_nonlocal_goto)
8800 if (TARGET_ABICALLS_PIC2)
8802 /* Symbolic accesses implicitly use the global pointer unless
8803 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8804 might go to traditional MIPS lazy-binding stubs. */
8805 if (!TARGET_EXPLICIT_RELOCS)
8808 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8809 can be lazily-bound. */
8813 /* MIPS16 functions that return in FPRs need to call an
8814 external libgcc routine. This call is only made explict
8815 during mips_expand_epilogue, and it too might be lazily bound. */
8816 if (mips16_cfun_returns_in_fpr_p ())
8820 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8821 mips_insn_has_inflexible_gp_ref_p);
8824 /* Return true if INSN refers to the global pointer in a "flexible" way.
8825 See mips_cfun_has_flexible_gp_ref_p for details. */
8828 mips_insn_has_flexible_gp_ref_p (rtx insn)
8830 return (get_attr_got (insn) != GOT_UNSET
8831 || mips_small_data_pattern_p (PATTERN (insn))
8832 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8835 /* Return true if the current function references the global pointer,
8836 but if those references do not inherently require the global pointer
8837 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8840 mips_cfun_has_flexible_gp_ref_p (void)
8842 /* Reload can sometimes introduce constant pool references
8843 into a function that otherwise didn't need them. For example,
8844 suppose we have an instruction like:
8846 (set (reg:DF R1) (float:DF (reg:SI R2)))
8848 If R2 turns out to be a constant such as 1, the instruction may
8849 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8850 the option of using this constant if R2 doesn't get allocated
8853 In cases like these, reload will have added the constant to the
8854 pool but no instruction will yet refer to it. */
8855 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8858 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8859 mips_insn_has_flexible_gp_ref_p);
8862 /* Return the register that should be used as the global pointer
8863 within this function. Return INVALID_REGNUM if the function
8864 doesn't need a global pointer. */
8867 mips_global_pointer (void)
8871 /* $gp is always available unless we're using a GOT. */
8872 if (!TARGET_USE_GOT)
8873 return GLOBAL_POINTER_REGNUM;
8875 /* If there are inflexible references to $gp, we must use the
8876 standard register. */
8877 if (mips_cfun_has_inflexible_gp_ref_p ())
8878 return GLOBAL_POINTER_REGNUM;
8880 /* If there are no current references to $gp, then the only uses
8881 we can introduce later are those involved in long branches. */
8882 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8883 return INVALID_REGNUM;
8885 /* If the global pointer is call-saved, try to use a call-clobbered
8887 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8888 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8889 if (!df_regs_ever_live_p (regno)
8890 && call_really_used_regs[regno]
8891 && !fixed_regs[regno]
8892 && regno != PIC_FUNCTION_ADDR_REGNUM)
8895 return GLOBAL_POINTER_REGNUM;
8898 /* Return true if the current function's prologue must load the global
8899 pointer value into pic_offset_table_rtx and store the same value in
8900 the function's cprestore slot (if any).
8902 One problem we have to deal with is that, when emitting GOT-based
8903 position independent code, long-branch sequences will need to load
8904 the address of the branch target from the GOT. We don't know until
8905 the very end of compilation whether (and where) the function needs
8906 long branches, so we must ensure that _any_ branch can access the
8907 global pointer in some form. However, we do not want to pessimize
8908 the usual case in which all branches are short.
8910 We handle this as follows:
8912 (1) During reload, we set cfun->machine->global_pointer to
8913 INVALID_REGNUM if we _know_ that the current function
8914 doesn't need a global pointer. This is only valid if
8915 long branches don't need the GOT.
8917 Otherwise, we assume that we might need a global pointer
8918 and pick an appropriate register.
8920 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8921 we ensure that the global pointer is available at every
8922 block boundary bar entry and exit. We do this in one of two ways:
8924 - If the function has a cprestore slot, we ensure that this
8925 slot is valid at every branch. However, as explained in
8926 point (6) below, there is no guarantee that pic_offset_table_rtx
8927 itself is valid if new uses of the global pointer are introduced
8928 after the first post-epilogue split.
8930 We guarantee that the cprestore slot is valid by loading it
8931 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8932 this register live at every block boundary bar function entry
8933 and exit. It is then invalid to move the load (and thus the
8934 preceding store) across a block boundary.
8936 - If the function has no cprestore slot, we guarantee that
8937 pic_offset_table_rtx itself is valid at every branch.
8939 See mips_eh_uses for the handling of the register liveness.
8941 (3) During prologue and epilogue generation, we emit "ghost"
8942 placeholder instructions to manipulate the global pointer.
8944 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8945 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8946 that the function needs a global pointer. (There is no need to set
8947 them earlier than this, and doing it as late as possible leads to
8948 fewer false positives.)
8950 (5) If cfun->machine->must_initialize_gp_p is true during a
8951 split_insns pass, we split the ghost instructions into real
8952 instructions. These split instructions can then be optimized in
8953 the usual way. Otherwise, we keep the ghost instructions intact,
8954 and optimize for the case where they aren't needed. We still
8955 have the option of splitting them later, if we need to introduce
8956 new uses of the global pointer.
8958 For example, the scheduler ignores a ghost instruction that
8959 stores $28 to the stack, but it handles the split form of
8960 the ghost instruction as an ordinary store.
8962 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8963 is true during the first post-epilogue split_insns pass, we split
8964 calls and restore_gp patterns into instructions that explicitly
8965 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8966 we split these patterns into instructions that _don't_ load from
8969 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8970 time of the split, then any instructions that exist at that time
8971 can make free use of pic_offset_table_rtx. However, if we want
8972 to introduce new uses of the global pointer after the split,
8973 we must explicitly load the value from the cprestore slot, since
8974 pic_offset_table_rtx itself might not be valid at a given point
8977 The idea is that we want to be able to delete redundant
8978 loads from the cprestore slot in the usual case where no
8979 long branches are needed.
8981 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8982 of md_reorg, we decide whether the global pointer is needed for
8983 long branches. If so, we set cfun->machine->must_initialize_gp_p
8984 to true and split the ghost instructions into real instructions
8987 Note that the ghost instructions must have a zero length for three reasons:
8989 - Giving the length of the underlying $gp sequence might cause
8990 us to use long branches in cases where they aren't really needed.
8992 - They would perturb things like alignment calculations.
8994 - More importantly, the hazard detection in md_reorg relies on
8995 empty instructions having a zero length.
8997 If we find a long branch and split the ghost instructions at the
8998 end of md_reorg, the split could introduce more long branches.
8999 That isn't a problem though, because we still do the split before
9000 the final shorten_branches pass.
9002 This is extremely ugly, but it seems like the best compromise between
9003 correctness and efficiency. */
9006 mips_must_initialize_gp_p (void)
9008 return cfun->machine->must_initialize_gp_p;
9011 /* Return true if REGNO is a register that is ordinarily call-clobbered
9012 but must nevertheless be preserved by an interrupt handler. */
9015 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9017 if (MD_REG_P (regno))
9020 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9023 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9025 /* $0 is hard-wired. */
9026 if (regno == GP_REG_FIRST)
9029 /* The interrupt handler can treat kernel registers as
9030 scratch registers. */
9031 if (KERNEL_REG_P (regno))
9034 /* The function will return the stack pointer to its original value
9036 if (regno == STACK_POINTER_REGNUM)
9039 /* Otherwise, return true for registers that aren't ordinarily
9041 return call_really_used_regs[regno];
9047 /* Return true if the current function should treat register REGNO
9051 mips_cfun_call_saved_reg_p (unsigned int regno)
9053 /* Interrupt handlers need to save extra registers. */
9054 if (cfun->machine->interrupt_handler_p
9055 && mips_interrupt_extra_call_saved_reg_p (regno))
9058 /* call_insns preserve $28 unless they explicitly say otherwise,
9059 so call_really_used_regs[] treats $28 as call-saved. However,
9060 we want the ABI property rather than the default call_insn
9062 return (regno == GLOBAL_POINTER_REGNUM
9063 ? TARGET_CALL_SAVED_GP
9064 : !call_really_used_regs[regno]);
9067 /* Return true if the function body might clobber register REGNO.
9068 We know that REGNO is call-saved. */
9071 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9073 /* Some functions should be treated as clobbering all call-saved
9075 if (crtl->saves_all_registers)
9078 /* DF handles cases where a register is explicitly referenced in
9079 the rtl. Incoming values are passed in call-clobbered registers,
9080 so we can assume that any live call-saved register is set within
9082 if (df_regs_ever_live_p (regno))
9085 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9086 These clobbers are not explicit in the rtl. */
9087 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9090 /* If we're using a call-saved global pointer, the function's
9091 prologue will need to set it up. */
9092 if (cfun->machine->global_pointer == regno)
9095 /* The function's prologue will need to set the frame pointer if
9096 frame_pointer_needed. */
9097 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9100 /* If a MIPS16 function returns a value in FPRs, its epilogue
9101 will need to call an external libgcc routine. This yet-to-be
9102 generated call_insn will clobber $31. */
9103 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9106 /* If REGNO is ordinarily call-clobbered, we must assume that any
9107 called function could modify it. */
9108 if (cfun->machine->interrupt_handler_p
9109 && !current_function_is_leaf
9110 && mips_interrupt_extra_call_saved_reg_p (regno))
9116 /* Return true if the current function must save register REGNO. */
9119 mips_save_reg_p (unsigned int regno)
9121 if (mips_cfun_call_saved_reg_p (regno))
9123 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9126 /* Save both registers in an FPR pair if either one is used. This is
9127 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9128 register to be used without the even register. */
9129 if (FP_REG_P (regno)
9130 && MAX_FPRS_PER_FMT == 2
9131 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9135 /* We need to save the incoming return address if __builtin_eh_return
9136 is being used to set a different return address. */
9137 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9143 /* Populate the current function's mips_frame_info structure.
9145 MIPS stack frames look like:
9147 +-------------------------------+
9149 | incoming stack arguments |
9151 +-------------------------------+
9153 | caller-allocated save area |
9154 A | for register arguments |
9156 +-------------------------------+ <-- incoming stack pointer
9158 | callee-allocated save area |
9159 B | for arguments that are |
9160 | split between registers and |
9163 +-------------------------------+ <-- arg_pointer_rtx
9165 C | callee-allocated save area |
9166 | for register varargs |
9168 +-------------------------------+ <-- frame_pointer_rtx
9169 | | + cop0_sp_offset
9170 | COP0 reg save area | + UNITS_PER_WORD
9172 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9173 | | + UNITS_PER_WORD
9174 | accumulator save area |
9176 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9177 | | + UNITS_PER_HWFPVALUE
9180 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9181 | | + UNITS_PER_WORD
9184 +-------------------------------+ <-- frame_pointer_rtx with
9185 | | \ -fstack-protector
9186 | local variables | | var_size
9188 +-------------------------------+
9190 | $gp save area | | cprestore_size
9192 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9194 | outgoing stack arguments | |
9196 +-------------------------------+ | args_size
9198 | caller-allocated save area | |
9199 | for register arguments | |
9201 +-------------------------------+ <-- stack_pointer_rtx
9202 frame_pointer_rtx without
9204 hard_frame_pointer_rtx for
9207 At least two of A, B and C will be empty.
9209 Dynamic stack allocations such as alloca insert data at point P.
9210 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9211 hard_frame_pointer_rtx unchanged. */
9214 mips_compute_frame_info (void)
9216 struct mips_frame_info *frame;
9217 HOST_WIDE_INT offset, size;
9218 unsigned int regno, i;
9220 /* Set this function's interrupt properties. */
9221 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9224 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9225 else if (TARGET_HARD_FLOAT)
9226 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9227 else if (TARGET_MIPS16)
9228 error ("interrupt handlers cannot be MIPS16 functions");
9231 cfun->machine->interrupt_handler_p = true;
9232 cfun->machine->use_shadow_register_set_p =
9233 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9234 cfun->machine->keep_interrupts_masked_p =
9235 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9236 cfun->machine->use_debug_exception_return_p =
9237 mips_use_debug_exception_return_p (TREE_TYPE
9238 (current_function_decl));
9242 frame = &cfun->machine->frame;
9243 memset (frame, 0, sizeof (*frame));
9244 size = get_frame_size ();
9246 cfun->machine->global_pointer = mips_global_pointer ();
9248 /* The first two blocks contain the outgoing argument area and the $gp save
9249 slot. This area isn't needed in leaf functions, but if the
9250 target-independent frame size is nonzero, we have already committed to
9251 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9252 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9254 /* The MIPS 3.0 linker does not like functions that dynamically
9255 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9256 looks like we are trying to create a second frame pointer to the
9257 function, so allocate some stack space to make it happy. */
9258 if (cfun->calls_alloca)
9259 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9261 frame->args_size = 0;
9262 frame->cprestore_size = 0;
9266 frame->args_size = crtl->outgoing_args_size;
9267 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9269 offset = frame->args_size + frame->cprestore_size;
9271 /* Move above the local variables. */
9272 frame->var_size = MIPS_STACK_ALIGN (size);
9273 offset += frame->var_size;
9275 /* Find out which GPRs we need to save. */
9276 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9277 if (mips_save_reg_p (regno))
9280 frame->mask |= 1 << (regno - GP_REG_FIRST);
9283 /* If this function calls eh_return, we must also save and restore the
9284 EH data registers. */
9285 if (crtl->calls_eh_return)
9286 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9289 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9292 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9293 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9294 save all later registers too. */
9295 if (GENERATE_MIPS16E_SAVE_RESTORE)
9297 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9298 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9299 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9300 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9303 /* Move above the GPR save area. */
9304 if (frame->num_gp > 0)
9306 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9307 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9310 /* Find out which FPRs we need to save. This loop must iterate over
9311 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9312 if (TARGET_HARD_FLOAT)
9313 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9314 if (mips_save_reg_p (regno))
9316 frame->num_fp += MAX_FPRS_PER_FMT;
9317 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9320 /* Move above the FPR save area. */
9321 if (frame->num_fp > 0)
9323 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9324 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9327 /* Add in space for the interrupt context information. */
9328 if (cfun->machine->interrupt_handler_p)
9331 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9334 frame->acc_mask |= (1 << 0);
9337 /* Check accumulators 1, 2, 3. */
9338 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9339 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9342 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9345 /* All interrupt context functions need space to preserve STATUS. */
9346 frame->num_cop0_regs++;
9348 /* If we don't keep interrupts masked, we need to save EPC. */
9349 if (!cfun->machine->keep_interrupts_masked_p)
9350 frame->num_cop0_regs++;
9353 /* Move above the accumulator save area. */
9354 if (frame->num_acc > 0)
9356 /* Each accumulator needs 2 words. */
9357 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9358 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9361 /* Move above the COP0 register save area. */
9362 if (frame->num_cop0_regs > 0)
9364 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9365 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9368 /* Move above the callee-allocated varargs save area. */
9369 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9370 frame->arg_pointer_offset = offset;
9372 /* Move above the callee-allocated area for pretend stack arguments. */
9373 offset += crtl->args.pretend_args_size;
9374 frame->total_size = offset;
9376 /* Work out the offsets of the save areas from the top of the frame. */
9377 if (frame->gp_sp_offset > 0)
9378 frame->gp_save_offset = frame->gp_sp_offset - offset;
9379 if (frame->fp_sp_offset > 0)
9380 frame->fp_save_offset = frame->fp_sp_offset - offset;
9381 if (frame->acc_sp_offset > 0)
9382 frame->acc_save_offset = frame->acc_sp_offset - offset;
9383 if (frame->num_cop0_regs > 0)
9384 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9386 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9387 arguments. This tends to increase the chances of using unextended
9388 instructions for local variables and incoming arguments. */
9390 frame->hard_frame_pointer_offset = frame->args_size;
9393 /* Return the style of GP load sequence that is being used for the
9394 current function. */
9396 enum mips_loadgp_style
9397 mips_current_loadgp_style (void)
9399 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9405 if (TARGET_ABSOLUTE_ABICALLS)
9406 return LOADGP_ABSOLUTE;
9408 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9411 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9414 mips_frame_pointer_required (void)
9416 /* If the function contains dynamic stack allocations, we need to
9417 use the frame pointer to access the static parts of the frame. */
9418 if (cfun->calls_alloca)
9421 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9422 reload may be unable to compute the address of a local variable,
9423 since there is no way to add a large constant to the stack pointer
9424 without using a second temporary register. */
9427 mips_compute_frame_info ();
9428 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9435 /* Make sure that we're not trying to eliminate to the wrong hard frame
9439 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9441 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9444 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9445 or argument pointer. TO is either the stack pointer or hard frame
9449 mips_initial_elimination_offset (int from, int to)
9451 HOST_WIDE_INT offset;
9453 mips_compute_frame_info ();
9455 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9458 case FRAME_POINTER_REGNUM:
9459 if (FRAME_GROWS_DOWNWARD)
9460 offset = (cfun->machine->frame.args_size
9461 + cfun->machine->frame.cprestore_size
9462 + cfun->machine->frame.var_size);
9467 case ARG_POINTER_REGNUM:
9468 offset = cfun->machine->frame.arg_pointer_offset;
9475 if (to == HARD_FRAME_POINTER_REGNUM)
9476 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9481 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9484 mips_extra_live_on_entry (bitmap regs)
9488 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9489 the global pointer. */
9490 if (!TARGET_ABSOLUTE_ABICALLS)
9491 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9493 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9494 the global pointer. */
9496 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9498 /* See the comment above load_call<mode> for details. */
9499 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9503 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9507 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9512 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9515 /* Emit code to change the current function's return address to
9516 ADDRESS. SCRATCH is available as a scratch register, if needed.
9517 ADDRESS and SCRATCH are both word-mode GPRs. */
9520 mips_set_return_address (rtx address, rtx scratch)
9524 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9525 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9526 cfun->machine->frame.gp_sp_offset);
9527 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9530 /* Return true if the current function has a cprestore slot. */
9533 mips_cfun_has_cprestore_slot_p (void)
9535 return (cfun->machine->global_pointer != INVALID_REGNUM
9536 && cfun->machine->frame.cprestore_size > 0);
9539 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9540 cprestore slot. LOAD_P is true if the caller wants to load from
9541 the cprestore slot; it is false if the caller wants to store to
9545 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9548 const struct mips_frame_info *frame;
9550 frame = &cfun->machine->frame;
9551 /* .cprestore always uses the stack pointer instead of the frame pointer.
9552 We have a free choice for direct stores for non-MIPS16 functions,
9553 and for MIPS16 functions whose cprestore slot is in range of the
9554 stack pointer. Using the stack pointer would sometimes give more
9555 (early) scheduling freedom, but using the frame pointer would
9556 sometimes give more (late) scheduling freedom. It's hard to
9557 predict which applies to a given function, so let's keep things
9560 Loads must always use the frame pointer in functions that call
9561 alloca, and there's little benefit to using the stack pointer
9563 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9565 *base = hard_frame_pointer_rtx;
9566 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9570 *base = stack_pointer_rtx;
9571 *offset = frame->args_size;
9575 /* Return true if X is the load or store address of the cprestore slot;
9576 LOAD_P says which. */
9579 mips_cprestore_address_p (rtx x, bool load_p)
9581 rtx given_base, required_base;
9582 HOST_WIDE_INT given_offset, required_offset;
9584 mips_split_plus (x, &given_base, &given_offset);
9585 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9586 return given_base == required_base && given_offset == required_offset;
9589 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9590 going to load from it, false if we are going to store to it.
9591 Use TEMP as a temporary register if need be. */
9594 mips_cprestore_slot (rtx temp, bool load_p)
9597 HOST_WIDE_INT offset;
9599 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9600 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9603 /* Emit instructions to save global pointer value GP into cprestore
9604 slot MEM. OFFSET is the offset that MEM applies to the base register.
9606 MEM may not be a legitimate address. If it isn't, TEMP is a
9607 temporary register that can be used, otherwise it is a SCRATCH. */
9610 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9612 if (TARGET_CPRESTORE_DIRECTIVE)
9614 gcc_assert (gp == pic_offset_table_rtx);
9615 emit_insn (gen_cprestore (mem, offset));
9618 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9621 /* Restore $gp from its save slot, using TEMP as a temporary base register
9622 if need be. This function is for o32 and o64 abicalls only.
9624 See mips_must_initialize_gp_p for details about how we manage the
9628 mips_restore_gp_from_cprestore_slot (rtx temp)
9630 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9632 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9634 emit_note (NOTE_INSN_DELETED);
9640 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9641 mips_emit_move (pic_offset_table_rtx, temp);
9644 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9645 if (!TARGET_EXPLICIT_RELOCS)
9646 emit_insn (gen_blockage ());
9649 /* A function to save or store a register. The first argument is the
9650 register and the second is the stack slot. */
9651 typedef void (*mips_save_restore_fn) (rtx, rtx);
9653 /* Use FN to save or restore register REGNO. MODE is the register's
9654 mode and OFFSET is the offset of its save slot from the current
9658 mips_save_restore_reg (enum machine_mode mode, int regno,
9659 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9663 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9664 fn (gen_rtx_REG (mode, regno), mem);
9667 /* Call FN for each accumlator that is saved by the current function.
9668 SP_OFFSET is the offset of the current stack pointer from the start
9672 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9674 HOST_WIDE_INT offset;
9677 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9678 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9680 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9681 offset -= UNITS_PER_WORD;
9682 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9683 offset -= UNITS_PER_WORD;
9686 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9687 if (BITSET_P (cfun->machine->frame.acc_mask,
9688 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9690 mips_save_restore_reg (word_mode, regno, offset, fn);
9691 offset -= UNITS_PER_WORD;
9695 /* Call FN for each register that is saved by the current function.
9696 SP_OFFSET is the offset of the current stack pointer from the start
9700 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9701 mips_save_restore_fn fn)
9703 enum machine_mode fpr_mode;
9704 HOST_WIDE_INT offset;
9707 /* Save registers starting from high to low. The debuggers prefer at least
9708 the return register be stored at func+4, and also it allows us not to
9709 need a nop in the epilogue if at least one register is reloaded in
9710 addition to return address. */
9711 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9712 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9713 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9715 /* Record the ra offset for use by mips_function_profiler. */
9716 if (regno == RETURN_ADDR_REGNUM)
9717 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
9718 mips_save_restore_reg (word_mode, regno, offset, fn);
9719 offset -= UNITS_PER_WORD;
9722 /* This loop must iterate over the same space as its companion in
9723 mips_compute_frame_info. */
9724 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9725 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9726 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9727 regno >= FP_REG_FIRST;
9728 regno -= MAX_FPRS_PER_FMT)
9729 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9731 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9732 offset -= GET_MODE_SIZE (fpr_mode);
9736 /* Return true if a move between register REGNO and its save slot (MEM)
9737 can be done in a single move. LOAD_P is true if we are loading
9738 from the slot, false if we are storing to it. */
9741 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9743 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9744 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9747 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9748 GET_MODE (mem), mem, load_p) == NO_REGS;
9751 /* Emit a move from SRC to DEST, given that one of them is a register
9752 save slot and that the other is a register. TEMP is a temporary
9753 GPR of the same mode that is available if need be. */
9756 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9763 regno = REGNO (src);
9768 regno = REGNO (dest);
9772 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9774 /* We don't yet know whether we'll need this instruction or not.
9775 Postpone the decision by emitting a ghost move. This move
9776 is specifically not frame-related; only the split version is. */
9778 emit_insn (gen_move_gpdi (dest, src));
9780 emit_insn (gen_move_gpsi (dest, src));
9784 if (regno == HI_REGNUM)
9788 mips_emit_move (temp, src);
9790 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9791 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9793 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9794 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9799 emit_insn (gen_mfhidi_ti (temp,
9800 gen_rtx_REG (TImode, MD_REG_FIRST)));
9802 emit_insn (gen_mfhisi_di (temp,
9803 gen_rtx_REG (DImode, MD_REG_FIRST)));
9804 mips_emit_move (dest, temp);
9807 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9808 mips_emit_move (dest, src);
9811 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9812 mips_emit_move (temp, src);
9813 mips_emit_move (dest, temp);
9816 mips_set_frame_expr (mips_frame_set (dest, src));
9819 /* If we're generating n32 or n64 abicalls, and the current function
9820 does not use $28 as its global pointer, emit a cplocal directive.
9821 Use pic_offset_table_rtx as the argument to the directive. */
9824 mips_output_cplocal (void)
9826 if (!TARGET_EXPLICIT_RELOCS
9827 && mips_must_initialize_gp_p ()
9828 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9829 output_asm_insn (".cplocal %+", 0);
9832 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9835 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9839 #ifdef SDB_DEBUGGING_INFO
9840 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9841 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9844 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9845 floating-point arguments. */
9847 && TARGET_HARD_FLOAT_ABI
9848 && crtl->args.info.fp_code != 0)
9849 mips16_build_function_stub ();
9851 /* Get the function name the same way that toplev.c does before calling
9852 assemble_start_function. This is needed so that the name used here
9853 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9854 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9855 mips_start_function_definition (fnname, TARGET_MIPS16);
9857 /* Output MIPS-specific frame information. */
9858 if (!flag_inhibit_size_directive)
9860 const struct mips_frame_info *frame;
9862 frame = &cfun->machine->frame;
9864 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9866 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9867 "# vars= " HOST_WIDE_INT_PRINT_DEC
9869 ", args= " HOST_WIDE_INT_PRINT_DEC
9870 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9871 reg_names[frame_pointer_needed
9872 ? HARD_FRAME_POINTER_REGNUM
9873 : STACK_POINTER_REGNUM],
9874 (frame_pointer_needed
9875 ? frame->total_size - frame->hard_frame_pointer_offset
9876 : frame->total_size),
9877 reg_names[RETURN_ADDR_REGNUM],
9879 frame->num_gp, frame->num_fp,
9881 frame->cprestore_size);
9883 /* .mask MASK, OFFSET. */
9884 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9885 frame->mask, frame->gp_save_offset);
9887 /* .fmask MASK, OFFSET. */
9888 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9889 frame->fmask, frame->fp_save_offset);
9892 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9893 Also emit the ".set noreorder; .set nomacro" sequence for functions
9895 if (mips_must_initialize_gp_p ()
9896 && mips_current_loadgp_style () == LOADGP_OLDABI)
9900 /* This is a fixed-form sequence. The position of the
9901 first two instructions is important because of the
9902 way _gp_disp is defined. */
9903 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9904 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9905 output_asm_insn ("sll\t$2,16", 0);
9906 output_asm_insn ("addu\t$2,$3", 0);
9910 /* .cpload must be in a .set noreorder but not a
9911 .set nomacro block. */
9912 mips_push_asm_switch (&mips_noreorder);
9913 output_asm_insn (".cpload\t%^", 0);
9914 if (!cfun->machine->all_noreorder_p)
9915 mips_pop_asm_switch (&mips_noreorder);
9917 mips_push_asm_switch (&mips_nomacro);
9920 else if (cfun->machine->all_noreorder_p)
9922 mips_push_asm_switch (&mips_noreorder);
9923 mips_push_asm_switch (&mips_nomacro);
9926 /* Tell the assembler which register we're using as the global
9927 pointer. This is needed for thunks, since they can use either
9928 explicit relocs or assembler macros. */
9929 mips_output_cplocal ();
9932 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9935 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9936 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9940 /* Reinstate the normal $gp. */
9941 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9942 mips_output_cplocal ();
9944 if (cfun->machine->all_noreorder_p)
9946 mips_pop_asm_switch (&mips_nomacro);
9947 mips_pop_asm_switch (&mips_noreorder);
9950 /* Get the function name the same way that toplev.c does before calling
9951 assemble_start_function. This is needed so that the name used here
9952 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9953 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9954 mips_end_function_definition (fnname);
9957 /* Save register REG to MEM. Make the instruction frame-related. */
9960 mips_save_reg (rtx reg, rtx mem)
9962 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9966 if (mips_split_64bit_move_p (mem, reg))
9967 mips_split_doubleword_move (mem, reg);
9969 mips_emit_move (mem, reg);
9971 x1 = mips_frame_set (mips_subword (mem, false),
9972 mips_subword (reg, false));
9973 x2 = mips_frame_set (mips_subword (mem, true),
9974 mips_subword (reg, true));
9975 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9978 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9981 /* The __gnu_local_gp symbol. */
9983 static GTY(()) rtx mips_gnu_local_gp;
9985 /* If we're generating n32 or n64 abicalls, emit instructions
9986 to set up the global pointer. */
9989 mips_emit_loadgp (void)
9991 rtx addr, offset, incoming_address, base, index, pic_reg;
9993 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9994 switch (mips_current_loadgp_style ())
9996 case LOADGP_ABSOLUTE:
9997 if (mips_gnu_local_gp == NULL)
9999 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10000 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10002 emit_insn (Pmode == SImode
10003 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
10004 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
10007 case LOADGP_OLDABI:
10008 /* Added by mips_output_function_prologue. */
10011 case LOADGP_NEWABI:
10012 addr = XEXP (DECL_RTL (current_function_decl), 0);
10013 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10014 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10015 emit_insn (Pmode == SImode
10016 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
10017 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
10021 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10022 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10023 emit_insn (Pmode == SImode
10024 ? gen_loadgp_rtp_si (pic_reg, base, index)
10025 : gen_loadgp_rtp_di (pic_reg, base, index));
10033 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
10035 /* Emit a blockage if there are implicit uses of the GP register.
10036 This includes profiled functions, because FUNCTION_PROFILE uses
10038 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10039 emit_insn (gen_loadgp_blockage ());
10042 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10045 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10047 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10050 /* Expand the "prologue" pattern. */
10053 mips_expand_prologue (void)
10055 const struct mips_frame_info *frame;
10056 HOST_WIDE_INT size;
10057 unsigned int nargs;
10060 if (cfun->machine->global_pointer != INVALID_REGNUM)
10062 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10063 or implicitly. If so, we can commit to using a global pointer
10064 straight away, otherwise we need to defer the decision. */
10065 if (mips_cfun_has_inflexible_gp_ref_p ()
10066 || mips_cfun_has_flexible_gp_ref_p ())
10068 cfun->machine->must_initialize_gp_p = true;
10069 cfun->machine->must_restore_gp_when_clobbered_p = true;
10072 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10075 frame = &cfun->machine->frame;
10076 size = frame->total_size;
10078 if (flag_stack_usage)
10079 current_function_static_stack_size = size;
10081 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10082 bytes beforehand; this is enough to cover the register save area
10083 without going out of range. */
10084 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10085 || frame->num_cop0_regs > 0)
10087 HOST_WIDE_INT step1;
10089 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10090 if (GENERATE_MIPS16E_SAVE_RESTORE)
10092 HOST_WIDE_INT offset;
10093 unsigned int mask, regno;
10095 /* Try to merge argument stores into the save instruction. */
10096 nargs = mips16e_collect_argument_saves ();
10098 /* Build the save instruction. */
10099 mask = frame->mask;
10100 insn = mips16e_build_save_restore (false, &mask, &offset,
10102 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10105 /* Check if we need to save other registers. */
10106 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10107 if (BITSET_P (mask, regno - GP_REG_FIRST))
10109 offset -= UNITS_PER_WORD;
10110 mips_save_restore_reg (word_mode, regno,
10111 offset, mips_save_reg);
10116 if (cfun->machine->interrupt_handler_p)
10118 HOST_WIDE_INT offset;
10121 /* If this interrupt is using a shadow register set, we need to
10122 get the stack pointer from the previous register set. */
10123 if (cfun->machine->use_shadow_register_set_p)
10124 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10125 stack_pointer_rtx));
10127 if (!cfun->machine->keep_interrupts_masked_p)
10129 /* Move from COP0 Cause to K0. */
10130 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10131 gen_rtx_REG (SImode,
10132 COP0_CAUSE_REG_NUM)));
10133 /* Move from COP0 EPC to K1. */
10134 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10135 gen_rtx_REG (SImode,
10136 COP0_EPC_REG_NUM)));
10139 /* Allocate the first part of the frame. */
10140 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10142 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10145 /* Start at the uppermost location for saving. */
10146 offset = frame->cop0_sp_offset - size;
10147 if (!cfun->machine->keep_interrupts_masked_p)
10149 /* Push EPC into its stack slot. */
10150 mem = gen_frame_mem (word_mode,
10151 plus_constant (stack_pointer_rtx,
10153 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10154 offset -= UNITS_PER_WORD;
10157 /* Move from COP0 Status to K1. */
10158 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10159 gen_rtx_REG (SImode,
10160 COP0_STATUS_REG_NUM)));
10162 /* Right justify the RIPL in k0. */
10163 if (!cfun->machine->keep_interrupts_masked_p)
10164 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10165 gen_rtx_REG (SImode, K0_REG_NUM),
10166 GEN_INT (CAUSE_IPL)));
10168 /* Push Status into its stack slot. */
10169 mem = gen_frame_mem (word_mode,
10170 plus_constant (stack_pointer_rtx, offset));
10171 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10172 offset -= UNITS_PER_WORD;
10174 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10175 if (!cfun->machine->keep_interrupts_masked_p)
10176 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10179 gen_rtx_REG (SImode, K0_REG_NUM)));
10181 if (!cfun->machine->keep_interrupts_masked_p)
10182 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10183 IE is already the correct value, so we don't have to do
10184 anything explicit. */
10185 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10188 gen_rtx_REG (SImode, GP_REG_FIRST)));
10190 /* Disable interrupts by clearing the KSU, ERL, EXL,
10192 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10195 gen_rtx_REG (SImode, GP_REG_FIRST)));
10199 insn = gen_add3_insn (stack_pointer_rtx,
10202 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10205 mips_for_each_saved_acc (size, mips_save_reg);
10206 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10210 /* Allocate the rest of the frame. */
10213 if (SMALL_OPERAND (-size))
10214 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10216 GEN_INT (-size)))) = 1;
10219 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10222 /* There are no instructions to add or subtract registers
10223 from the stack pointer, so use the frame pointer as a
10224 temporary. We should always be using a frame pointer
10225 in this case anyway. */
10226 gcc_assert (frame_pointer_needed);
10227 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10228 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10229 hard_frame_pointer_rtx,
10230 MIPS_PROLOGUE_TEMP (Pmode)));
10231 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10234 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10236 MIPS_PROLOGUE_TEMP (Pmode)));
10238 /* Describe the combined effect of the previous instructions. */
10239 mips_set_frame_expr
10240 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10241 plus_constant (stack_pointer_rtx, -size)));
10245 /* Set up the frame pointer, if we're using one. */
10246 if (frame_pointer_needed)
10248 HOST_WIDE_INT offset;
10250 offset = frame->hard_frame_pointer_offset;
10253 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10254 RTX_FRAME_RELATED_P (insn) = 1;
10256 else if (SMALL_OPERAND (offset))
10258 insn = gen_add3_insn (hard_frame_pointer_rtx,
10259 stack_pointer_rtx, GEN_INT (offset));
10260 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10264 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10265 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10266 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10267 hard_frame_pointer_rtx,
10268 MIPS_PROLOGUE_TEMP (Pmode)));
10269 mips_set_frame_expr
10270 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10271 plus_constant (stack_pointer_rtx, offset)));
10275 mips_emit_loadgp ();
10277 /* Initialize the $gp save slot. */
10278 if (mips_cfun_has_cprestore_slot_p ())
10280 rtx base, mem, gp, temp;
10281 HOST_WIDE_INT offset;
10283 mips_get_cprestore_base_and_offset (&base, &offset, false);
10284 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10285 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10286 temp = (SMALL_OPERAND (offset)
10287 ? gen_rtx_SCRATCH (Pmode)
10288 : MIPS_PROLOGUE_TEMP (Pmode));
10289 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10291 mips_get_cprestore_base_and_offset (&base, &offset, true);
10292 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10293 emit_insn (gen_use_cprestore (mem));
10296 /* We need to search back to the last use of K0 or K1. */
10297 if (cfun->machine->interrupt_handler_p)
10299 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10301 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10303 /* Emit a move from K1 to COP0 Status after insn. */
10304 gcc_assert (insn != NULL_RTX);
10305 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10306 gen_rtx_REG (SImode, K1_REG_NUM)),
10310 /* If we are profiling, make sure no instructions are scheduled before
10311 the call to mcount. */
10313 emit_insn (gen_blockage ());
10316 /* Emit instructions to restore register REG from slot MEM. */
10319 mips_restore_reg (rtx reg, rtx mem)
10321 /* There's no MIPS16 instruction to load $31 directly. Load into
10322 $7 instead and adjust the return insn appropriately. */
10323 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10324 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10326 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10329 /* Emit any instructions needed before a return. */
10332 mips_expand_before_return (void)
10334 /* When using a call-clobbered gp, we start out with unified call
10335 insns that include instructions to restore the gp. We then split
10336 these unified calls after reload. These split calls explicitly
10337 clobber gp, so there is no need to define
10338 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10340 For consistency, we should also insert an explicit clobber of $28
10341 before return insns, so that the post-reload optimizers know that
10342 the register is not live on exit. */
10343 if (TARGET_CALL_CLOBBERED_GP)
10344 emit_clobber (pic_offset_table_rtx);
10347 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10351 mips_expand_epilogue (bool sibcall_p)
10353 const struct mips_frame_info *frame;
10354 HOST_WIDE_INT step1, step2;
10355 rtx base, target, insn;
10357 if (!sibcall_p && mips_can_use_return_insn ())
10359 emit_jump_insn (gen_return ());
10363 /* In MIPS16 mode, if the return value should go into a floating-point
10364 register, we need to call a helper routine to copy it over. */
10365 if (mips16_cfun_returns_in_fpr_p ())
10366 mips16_copy_fpr_return_value ();
10368 /* Split the frame into two. STEP1 is the amount of stack we should
10369 deallocate before restoring the registers. STEP2 is the amount we
10370 should deallocate afterwards.
10372 Start off by assuming that no registers need to be restored. */
10373 frame = &cfun->machine->frame;
10374 step1 = frame->total_size;
10377 /* Work out which register holds the frame address. */
10378 if (!frame_pointer_needed)
10379 base = stack_pointer_rtx;
10382 base = hard_frame_pointer_rtx;
10383 step1 -= frame->hard_frame_pointer_offset;
10386 /* If we need to restore registers, deallocate as much stack as
10387 possible in the second step without going out of range. */
10388 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10389 || frame->num_cop0_regs > 0)
10391 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10395 /* Set TARGET to BASE + STEP1. */
10401 /* Get an rtx for STEP1 that we can add to BASE. */
10402 adjust = GEN_INT (step1);
10403 if (!SMALL_OPERAND (step1))
10405 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10406 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10409 /* Normal mode code can copy the result straight into $sp. */
10410 if (!TARGET_MIPS16)
10411 target = stack_pointer_rtx;
10413 emit_insn (gen_add3_insn (target, base, adjust));
10416 /* Copy TARGET into the stack pointer. */
10417 if (target != stack_pointer_rtx)
10418 mips_emit_move (stack_pointer_rtx, target);
10420 /* If we're using addressing macros, $gp is implicitly used by all
10421 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10423 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10424 emit_insn (gen_blockage ());
10426 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10428 unsigned int regno, mask;
10429 HOST_WIDE_INT offset;
10432 /* Generate the restore instruction. */
10433 mask = frame->mask;
10434 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10436 /* Restore any other registers manually. */
10437 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10438 if (BITSET_P (mask, regno - GP_REG_FIRST))
10440 offset -= UNITS_PER_WORD;
10441 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10444 /* Restore the remaining registers and deallocate the final bit
10446 emit_insn (restore);
10450 /* Restore the registers. */
10451 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10452 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10455 if (cfun->machine->interrupt_handler_p)
10457 HOST_WIDE_INT offset;
10460 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10461 if (!cfun->machine->keep_interrupts_masked_p)
10463 /* Restore the original EPC. */
10464 mem = gen_frame_mem (word_mode,
10465 plus_constant (stack_pointer_rtx, offset));
10466 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10467 offset -= UNITS_PER_WORD;
10469 /* Move to COP0 EPC. */
10470 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10471 gen_rtx_REG (SImode, K0_REG_NUM)));
10474 /* Restore the original Status. */
10475 mem = gen_frame_mem (word_mode,
10476 plus_constant (stack_pointer_rtx, offset));
10477 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10478 offset -= UNITS_PER_WORD;
10480 /* If we don't use shoadow register set, we need to update SP. */
10481 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10482 emit_insn (gen_add3_insn (stack_pointer_rtx,
10486 /* Move to COP0 Status. */
10487 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10488 gen_rtx_REG (SImode, K0_REG_NUM)));
10492 /* Deallocate the final bit of the frame. */
10494 emit_insn (gen_add3_insn (stack_pointer_rtx,
10500 /* Add in the __builtin_eh_return stack adjustment. We need to
10501 use a temporary in MIPS16 code. */
10502 if (crtl->calls_eh_return)
10506 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10507 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10508 MIPS_EPILOGUE_TEMP (Pmode),
10509 EH_RETURN_STACKADJ_RTX));
10510 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10513 emit_insn (gen_add3_insn (stack_pointer_rtx,
10515 EH_RETURN_STACKADJ_RTX));
10520 mips_expand_before_return ();
10521 if (cfun->machine->interrupt_handler_p)
10523 /* Interrupt handlers generate eret or deret. */
10524 if (cfun->machine->use_debug_exception_return_p)
10525 emit_jump_insn (gen_mips_deret ());
10527 emit_jump_insn (gen_mips_eret ());
10531 unsigned int regno;
10533 /* When generating MIPS16 code, the normal
10534 mips_for_each_saved_gpr_and_fpr path will restore the return
10535 address into $7 rather than $31. */
10537 && !GENERATE_MIPS16E_SAVE_RESTORE
10538 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10539 regno = GP_REG_FIRST + 7;
10541 regno = RETURN_ADDR_REGNUM;
10542 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10546 /* Search from the beginning to the first use of K0 or K1. */
10547 if (cfun->machine->interrupt_handler_p
10548 && !cfun->machine->keep_interrupts_masked_p)
10550 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10552 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10554 gcc_assert (insn != NULL_RTX);
10555 /* Insert disable interrupts before the first use of K0 or K1. */
10556 emit_insn_before (gen_mips_di (), insn);
10557 emit_insn_before (gen_mips_ehb (), insn);
10561 /* Return nonzero if this function is known to have a null epilogue.
10562 This allows the optimizer to omit jumps to jumps if no stack
10566 mips_can_use_return_insn (void)
10568 /* Interrupt handlers need to go through the epilogue. */
10569 if (cfun->machine->interrupt_handler_p)
10572 if (!reload_completed)
10578 /* In MIPS16 mode, a function that returns a floating-point value
10579 needs to arrange to copy the return value into the floating-point
10581 if (mips16_cfun_returns_in_fpr_p ())
10584 return cfun->machine->frame.total_size == 0;
10587 /* Return true if register REGNO can store a value of mode MODE.
10588 The result of this function is cached in mips_hard_regno_mode_ok. */
10591 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10594 enum mode_class mclass;
10596 if (mode == CCV2mode)
10597 return (ISA_HAS_8CC
10598 && ST_REG_P (regno)
10599 && (regno - ST_REG_FIRST) % 2 == 0);
10601 if (mode == CCV4mode)
10602 return (ISA_HAS_8CC
10603 && ST_REG_P (regno)
10604 && (regno - ST_REG_FIRST) % 4 == 0);
10606 if (mode == CCmode)
10609 return regno == FPSW_REGNUM;
10611 return (ST_REG_P (regno)
10612 || GP_REG_P (regno)
10613 || FP_REG_P (regno));
10616 size = GET_MODE_SIZE (mode);
10617 mclass = GET_MODE_CLASS (mode);
10619 if (GP_REG_P (regno))
10620 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10622 if (FP_REG_P (regno)
10623 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10624 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10626 /* Allow TFmode for CCmode reloads. */
10627 if (mode == TFmode && ISA_HAS_8CC)
10630 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10631 if (TARGET_LOONGSON_VECTORS
10632 && (mode == V2SImode
10633 || mode == V4HImode
10634 || mode == V8QImode
10635 || mode == DImode))
10638 if (mclass == MODE_FLOAT
10639 || mclass == MODE_COMPLEX_FLOAT
10640 || mclass == MODE_VECTOR_FLOAT)
10641 return size <= UNITS_PER_FPVALUE;
10643 /* Allow integer modes that fit into a single register. We need
10644 to put integers into FPRs when using instructions like CVT
10645 and TRUNC. There's no point allowing sizes smaller than a word,
10646 because the FPU has no appropriate load/store instructions. */
10647 if (mclass == MODE_INT)
10648 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10651 if (ACC_REG_P (regno)
10652 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10654 if (MD_REG_P (regno))
10656 /* After a multiplication or division, clobbering HI makes
10657 the value of LO unpredictable, and vice versa. This means
10658 that, for all interesting cases, HI and LO are effectively
10661 We model this by requiring that any value that uses HI
10663 if (size <= UNITS_PER_WORD * 2)
10664 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10668 /* DSP accumulators do not have the same restrictions as
10669 HI and LO, so we can treat them as normal doubleword
10671 if (size <= UNITS_PER_WORD)
10674 if (size <= UNITS_PER_WORD * 2
10675 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10680 if (ALL_COP_REG_P (regno))
10681 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10683 if (regno == GOT_VERSION_REGNUM)
10684 return mode == SImode;
10689 /* Implement HARD_REGNO_NREGS. */
10692 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10694 if (ST_REG_P (regno))
10695 /* The size of FP status registers is always 4, because they only hold
10696 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10697 return (GET_MODE_SIZE (mode) + 3) / 4;
10699 if (FP_REG_P (regno))
10700 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10702 /* All other registers are word-sized. */
10703 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10706 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10707 in mips_hard_regno_nregs. */
10710 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10716 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10717 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10719 size = MIN (size, 4);
10720 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10722 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10724 size = MIN (size, UNITS_PER_FPREG);
10725 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10727 if (!hard_reg_set_empty_p (left))
10728 size = MIN (size, UNITS_PER_WORD);
10729 return (GET_MODE_SIZE (mode) + size - 1) / size;
10732 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10735 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10736 enum machine_mode to ATTRIBUTE_UNUSED,
10737 enum reg_class rclass)
10739 /* There are several problems with changing the modes of values
10740 in floating-point registers:
10742 - When a multi-word value is stored in paired floating-point
10743 registers, the first register always holds the low word.
10744 We therefore can't allow FPRs to change between single-word
10745 and multi-word modes on big-endian targets.
10747 - GCC assumes that each word of a multiword register can be accessed
10748 individually using SUBREGs. This is not true for floating-point
10749 registers if they are bigger than a word.
10751 - Loading a 32-bit value into a 64-bit floating-point register
10752 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10753 We can't allow FPRs to change from SImode to to a wider mode on
10756 - If the FPU has already interpreted a value in one format, we must
10757 not ask it to treat the value as having a different format.
10759 We therefore disallow all mode changes involving FPRs. */
10760 return reg_classes_intersect_p (FP_REGS, rclass);
10763 /* Implement target hook small_register_classes_for_mode_p. */
10766 mips_small_register_classes_for_mode_p (enum machine_mode mode
10769 return TARGET_MIPS16;
10772 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10775 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10780 return TARGET_HARD_FLOAT;
10783 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10786 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10793 /* Implement MODES_TIEABLE_P. */
10796 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10798 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10799 prefer to put one of them in FPRs. */
10800 return (mode1 == mode2
10801 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10802 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10805 /* Implement PREFERRED_RELOAD_CLASS. */
10808 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10810 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10813 if (reg_class_subset_p (FP_REGS, rclass)
10814 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10817 if (reg_class_subset_p (GR_REGS, rclass))
10820 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10826 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10827 Return a "canonical" class to represent it in later calculations. */
10830 mips_canonicalize_move_class (reg_class_t rclass)
10832 /* All moves involving accumulator registers have the same cost. */
10833 if (reg_class_subset_p (rclass, ACC_REGS))
10836 /* Likewise promote subclasses of general registers to the most
10837 interesting containing class. */
10838 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10840 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10841 rclass = GENERAL_REGS;
10846 /* Return the cost of moving a value of mode MODE from a register of
10847 class FROM to a GPR. Return 0 for classes that are unions of other
10848 classes handled by this function. */
10851 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10857 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10861 /* MFLO and MFHI. */
10869 /* LUI followed by MOVF. */
10875 /* This choice of value is historical. */
10883 /* Return the cost of moving a value of mode MODE from a GPR to a
10884 register of class TO. Return 0 for classes that are unions of
10885 other classes handled by this function. */
10888 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
10893 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10897 /* MTLO and MTHI. */
10905 /* A secondary reload through an FPR scratch. */
10906 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10907 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10912 /* This choice of value is historical. */
10920 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10921 maximum of the move costs for subclasses; regclass will work out
10922 the maximum for us. */
10925 mips_register_move_cost (enum machine_mode mode,
10926 reg_class_t from, reg_class_t to)
10931 from = mips_canonicalize_move_class (from);
10932 to = mips_canonicalize_move_class (to);
10934 /* Handle moves that can be done without using general-purpose registers. */
10935 if (from == FP_REGS)
10937 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10941 /* The sequence generated by mips_expand_fcc_reload. */
10945 /* Handle cases in which only one class deviates from the ideal. */
10946 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10948 return mips_move_from_gpr_cost (mode, to);
10950 return mips_move_to_gpr_cost (mode, from);
10952 /* Handles cases that require a GPR temporary. */
10953 cost1 = mips_move_to_gpr_cost (mode, from);
10956 cost2 = mips_move_from_gpr_cost (mode, to);
10958 return cost1 + cost2;
10964 /* Implement TARGET_MEMORY_MOVE_COST. */
10967 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
10969 return (mips_cost->memory_latency
10970 + memory_move_secondary_cost (mode, rclass, in));
10973 /* Implement TARGET_IRA_COVER_CLASSES. */
10975 static const reg_class_t *
10976 mips_ira_cover_classes (void)
10978 static const reg_class_t acc_classes[] = {
10979 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10980 ST_REGS, LIM_REG_CLASSES
10982 static const reg_class_t no_acc_classes[] = {
10983 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10984 ST_REGS, LIM_REG_CLASSES
10987 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10988 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10989 as a cover class only works well when we keep per-register costs.
10990 Using it when not optimizing can cause us to think accumulators
10991 have the same cost as GPRs in cases where GPRs are actually much
10993 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10996 /* Return the register class required for a secondary register when
10997 copying between one of the registers in RCLASS and value X, which
10998 has mode MODE. X is the source of the move if IN_P, otherwise it
10999 is the destination. Return NO_REGS if no secondary register is
11003 mips_secondary_reload_class (enum reg_class rclass,
11004 enum machine_mode mode, rtx x, bool in_p)
11008 /* If X is a constant that cannot be loaded into $25, it must be loaded
11009 into some other GPR. No other register class allows a direct move. */
11010 if (mips_dangerous_for_la25_p (x))
11011 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11013 regno = true_regnum (x);
11016 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11017 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11023 /* Copying from accumulator registers to anywhere other than a general
11024 register requires a temporary general register. */
11025 if (reg_class_subset_p (rclass, ACC_REGS))
11026 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11027 if (ACC_REG_P (regno))
11028 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11030 /* We can only copy a value to a condition code register from a
11031 floating-point register, and even then we require a scratch
11032 floating-point register. We can only copy a value out of a
11033 condition-code register into a general register. */
11034 if (reg_class_subset_p (rclass, ST_REGS))
11038 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11040 if (ST_REG_P (regno))
11044 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11047 if (reg_class_subset_p (rclass, FP_REGS))
11050 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11051 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11052 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11055 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11056 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11059 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
11060 /* We can force the constant to memory and use lwc1
11061 and ldc1. As above, we will use pairs of lwc1s if
11062 ldc1 is not supported. */
11065 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11066 /* In this case we can use mov.fmt. */
11069 /* Otherwise, we need to reload through an integer register. */
11072 if (FP_REG_P (regno))
11073 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11078 /* Implement TARGET_MODE_REP_EXTENDED. */
11081 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11083 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11084 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11085 return SIGN_EXTEND;
11090 /* Implement TARGET_VALID_POINTER_MODE. */
11093 mips_valid_pointer_mode (enum machine_mode mode)
11095 return mode == SImode || (TARGET_64BIT && mode == DImode);
11098 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11101 mips_vector_mode_supported_p (enum machine_mode mode)
11106 return TARGET_PAIRED_SINGLE_FLOAT;
11121 return TARGET_LOONGSON_VECTORS;
11128 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11131 mips_scalar_mode_supported_p (enum machine_mode mode)
11133 if (ALL_FIXED_POINT_MODE_P (mode)
11134 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11137 return default_scalar_mode_supported_p (mode);
11140 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11142 static enum machine_mode
11143 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11145 if (TARGET_PAIRED_SINGLE_FLOAT
11151 /* Implement TARGET_INIT_LIBFUNCS. */
11153 #include "config/gofast.h"
11156 mips_init_libfuncs (void)
11158 if (TARGET_FIX_VR4120)
11160 /* Register the special divsi3 and modsi3 functions needed to work
11161 around VR4120 division errata. */
11162 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11163 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11166 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11168 /* Register the MIPS16 -mhard-float stubs. */
11169 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11170 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11171 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11172 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11174 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11175 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11176 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11177 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11178 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11179 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11180 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11182 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11183 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11184 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11186 if (TARGET_DOUBLE_FLOAT)
11188 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11189 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11190 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11191 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11193 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11194 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11195 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11196 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11197 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11198 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11199 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11201 set_conv_libfunc (sext_optab, DFmode, SFmode,
11202 "__mips16_extendsfdf2");
11203 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11204 "__mips16_truncdfsf2");
11205 set_conv_libfunc (sfix_optab, SImode, DFmode,
11206 "__mips16_fix_truncdfsi");
11207 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11208 "__mips16_floatsidf");
11209 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11210 "__mips16_floatunsidf");
11214 /* Register the gofast functions if selected using --enable-gofast. */
11215 gofast_maybe_init_libfuncs ();
11217 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11218 on an external non-MIPS16 routine to implement __sync_synchronize. */
11220 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11223 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11226 mips_process_load_label (rtx target)
11228 rtx base, gp, intop;
11229 HOST_WIDE_INT offset;
11231 mips_multi_start ();
11235 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11236 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11240 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11241 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11245 gp = pic_offset_table_rtx;
11246 if (mips_cfun_has_cprestore_slot_p ())
11248 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11249 mips_get_cprestore_base_and_offset (&base, &offset, true);
11250 if (!SMALL_OPERAND (offset))
11252 intop = GEN_INT (CONST_HIGH_PART (offset));
11253 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11254 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11257 offset = CONST_LOW_PART (offset);
11259 intop = GEN_INT (offset);
11260 if (ISA_HAS_LOAD_DELAY)
11261 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11263 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11265 if (ISA_HAS_LOAD_DELAY)
11266 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11268 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11269 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11274 /* Return the number of instructions needed to load a label into $AT. */
11276 static unsigned int
11277 mips_load_label_num_insns (void)
11279 if (cfun->machine->load_label_num_insns == 0)
11281 mips_process_load_label (pc_rtx);
11282 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11284 return cfun->machine->load_label_num_insns;
11287 /* Emit an asm sequence to start a noat block and load the address
11288 of a label into $1. */
11291 mips_output_load_label (rtx target)
11293 mips_push_asm_switch (&mips_noat);
11294 if (TARGET_EXPLICIT_RELOCS)
11296 mips_process_load_label (target);
11297 mips_multi_write ();
11301 if (Pmode == DImode)
11302 output_asm_insn ("dla\t%@,%0", &target);
11304 output_asm_insn ("la\t%@,%0", &target);
11308 /* Return the length of INSN. LENGTH is the initial length computed by
11309 attributes in the machine-description file. */
11312 mips_adjust_insn_length (rtx insn, int length)
11314 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11315 of a PIC long-branch sequence. Substitute the correct value. */
11316 if (length == MAX_PIC_BRANCH_LENGTH
11317 && INSN_CODE (insn) >= 0
11318 && get_attr_type (insn) == TYPE_BRANCH)
11320 /* Add the branch-over instruction and its delay slot, if this
11321 is a conditional branch. */
11322 length = simplejump_p (insn) ? 0 : 8;
11324 /* Load the label into $AT and jump to it. Ignore the delay
11325 slot of the jump. */
11326 length += 4 * mips_load_label_num_insns() + 4;
11329 /* A unconditional jump has an unfilled delay slot if it is not part
11330 of a sequence. A conditional jump normally has a delay slot, but
11331 does not on MIPS16. */
11332 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11335 /* See how many nops might be needed to avoid hardware hazards. */
11336 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11337 switch (get_attr_hazard (insn))
11351 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11352 the .md file length attributes are 4-based for both modes.
11353 Adjust the MIPS16 ones here. */
11360 /* Return the assembly code for INSN, which has the operands given by
11361 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11362 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11363 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11364 version of BRANCH_IF_TRUE. */
11367 mips_output_conditional_branch (rtx insn, rtx *operands,
11368 const char *branch_if_true,
11369 const char *branch_if_false)
11371 unsigned int length;
11372 rtx taken, not_taken;
11374 gcc_assert (LABEL_P (operands[0]));
11376 length = get_attr_length (insn);
11379 /* Just a simple conditional branch. */
11380 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11381 return branch_if_true;
11384 /* Generate a reversed branch around a direct jump. This fallback does
11385 not use branch-likely instructions. */
11386 mips_branch_likely = false;
11387 not_taken = gen_label_rtx ();
11388 taken = operands[0];
11390 /* Generate the reversed branch to NOT_TAKEN. */
11391 operands[0] = not_taken;
11392 output_asm_insn (branch_if_false, operands);
11394 /* If INSN has a delay slot, we must provide delay slots for both the
11395 branch to NOT_TAKEN and the conditional jump. We must also ensure
11396 that INSN's delay slot is executed in the appropriate cases. */
11397 if (final_sequence)
11399 /* This first delay slot will always be executed, so use INSN's
11400 delay slot if is not annulled. */
11401 if (!INSN_ANNULLED_BRANCH_P (insn))
11403 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11404 asm_out_file, optimize, 1, NULL);
11405 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11408 output_asm_insn ("nop", 0);
11409 fprintf (asm_out_file, "\n");
11412 /* Output the unconditional branch to TAKEN. */
11413 if (TARGET_ABSOLUTE_JUMPS)
11414 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11417 mips_output_load_label (taken);
11418 output_asm_insn ("jr\t%@%]%/", 0);
11421 /* Now deal with its delay slot; see above. */
11422 if (final_sequence)
11424 /* This delay slot will only be executed if the branch is taken.
11425 Use INSN's delay slot if is annulled. */
11426 if (INSN_ANNULLED_BRANCH_P (insn))
11428 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11429 asm_out_file, optimize, 1, NULL);
11430 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11433 output_asm_insn ("nop", 0);
11434 fprintf (asm_out_file, "\n");
11437 /* Output NOT_TAKEN. */
11438 targetm.asm_out.internal_label (asm_out_file, "L",
11439 CODE_LABEL_NUMBER (not_taken));
11443 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11444 if some ordering condition is true. The condition is given by
11445 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11446 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11447 its second is always zero. */
11450 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11452 const char *branch[2];
11454 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11455 Make BRANCH[0] branch on the inverse condition. */
11456 switch (GET_CODE (operands[1]))
11458 /* These cases are equivalent to comparisons against zero. */
11460 inverted_p = !inverted_p;
11461 /* Fall through. */
11463 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11464 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11467 /* These cases are always true or always false. */
11469 inverted_p = !inverted_p;
11470 /* Fall through. */
11472 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11473 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11477 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11478 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11481 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11484 /* Start a block of code that needs access to the LL, SC and SYNC
11488 mips_start_ll_sc_sync_block (void)
11490 if (!ISA_HAS_LL_SC)
11492 output_asm_insn (".set\tpush", 0);
11493 output_asm_insn (".set\tmips2", 0);
11497 /* End a block started by mips_start_ll_sc_sync_block. */
11500 mips_end_ll_sc_sync_block (void)
11502 if (!ISA_HAS_LL_SC)
11503 output_asm_insn (".set\tpop", 0);
11506 /* Output and/or return the asm template for a sync instruction. */
11509 mips_output_sync (void)
11511 mips_start_ll_sc_sync_block ();
11512 output_asm_insn ("sync", 0);
11513 mips_end_ll_sc_sync_block ();
11517 /* Return the asm template associated with sync_insn1 value TYPE.
11518 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11520 static const char *
11521 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11525 case SYNC_INSN1_MOVE:
11526 return "move\t%0,%z2";
11527 case SYNC_INSN1_LI:
11528 return "li\t%0,%2";
11529 case SYNC_INSN1_ADDU:
11530 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11531 case SYNC_INSN1_ADDIU:
11532 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11533 case SYNC_INSN1_SUBU:
11534 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11535 case SYNC_INSN1_AND:
11536 return "and\t%0,%1,%z2";
11537 case SYNC_INSN1_ANDI:
11538 return "andi\t%0,%1,%2";
11539 case SYNC_INSN1_OR:
11540 return "or\t%0,%1,%z2";
11541 case SYNC_INSN1_ORI:
11542 return "ori\t%0,%1,%2";
11543 case SYNC_INSN1_XOR:
11544 return "xor\t%0,%1,%z2";
11545 case SYNC_INSN1_XORI:
11546 return "xori\t%0,%1,%2";
11548 gcc_unreachable ();
11551 /* Return the asm template associated with sync_insn2 value TYPE. */
11553 static const char *
11554 mips_sync_insn2_template (enum attr_sync_insn2 type)
11558 case SYNC_INSN2_NOP:
11559 gcc_unreachable ();
11560 case SYNC_INSN2_AND:
11561 return "and\t%0,%1,%z2";
11562 case SYNC_INSN2_XOR:
11563 return "xor\t%0,%1,%z2";
11564 case SYNC_INSN2_NOT:
11565 return "nor\t%0,%1,%.";
11567 gcc_unreachable ();
11570 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11571 the value of the one of the sync_* attributes. Return the operand
11572 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11573 have the associated attribute. */
11576 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11579 default_value = operands[index - 1];
11580 return default_value;
11583 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11584 sequence for it. */
11587 mips_process_sync_loop (rtx insn, rtx *operands)
11589 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11590 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11591 unsigned int tmp3_insn;
11592 enum attr_sync_insn1 insn1;
11593 enum attr_sync_insn2 insn2;
11596 /* Read an operand from the sync_WHAT attribute and store it in
11597 variable WHAT. DEFAULT is the default value if no attribute
11599 #define READ_OPERAND(WHAT, DEFAULT) \
11600 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11603 /* Read the memory. */
11604 READ_OPERAND (mem, 0);
11606 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11608 /* Read the other attributes. */
11609 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11610 READ_OPERAND (oldval, at);
11611 READ_OPERAND (newval, at);
11612 READ_OPERAND (inclusive_mask, 0);
11613 READ_OPERAND (exclusive_mask, 0);
11614 READ_OPERAND (required_oldval, 0);
11615 READ_OPERAND (insn1_op2, 0);
11616 insn1 = get_attr_sync_insn1 (insn);
11617 insn2 = get_attr_sync_insn2 (insn);
11619 mips_multi_start ();
11621 /* Output the release side of the memory barrier. */
11622 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11624 if (required_oldval == 0 && TARGET_OCTEON)
11626 /* Octeon doesn't reorder reads, so a full barrier can be
11627 created by using SYNCW to order writes combined with the
11628 write from the following SC. When the SC successfully
11629 completes, we know that all preceding writes are also
11630 committed to the coherent memory system. It is possible
11631 for a single SYNCW to fail, but a pair of them will never
11632 fail, so we use two. */
11633 mips_multi_add_insn ("syncw", NULL);
11634 mips_multi_add_insn ("syncw", NULL);
11637 mips_multi_add_insn ("sync", NULL);
11640 /* Output the branch-back label. */
11641 mips_multi_add_label ("1:");
11643 /* OLDVAL = *MEM. */
11644 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11645 oldval, mem, NULL);
11647 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11648 if (required_oldval)
11650 if (inclusive_mask == 0)
11654 gcc_assert (oldval != at);
11655 mips_multi_add_insn ("and\t%0,%1,%2",
11656 at, oldval, inclusive_mask, NULL);
11659 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11662 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11663 if (exclusive_mask == 0)
11667 gcc_assert (oldval != at);
11668 mips_multi_add_insn ("and\t%0,%1,%z2",
11669 at, oldval, exclusive_mask, NULL);
11673 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11675 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11676 at least one instruction in that case. */
11677 if (insn1 == SYNC_INSN1_MOVE
11678 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11682 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11683 newval, oldval, insn1_op2, NULL);
11687 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11688 if (insn2 == SYNC_INSN2_NOP)
11692 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11693 newval, tmp2, inclusive_mask, NULL);
11696 tmp3_insn = mips_multi_last_index ();
11698 /* $AT = $TMP1 | $TMP3. */
11699 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11701 mips_multi_set_operand (tmp3_insn, 0, at);
11706 gcc_assert (tmp1 != tmp3);
11707 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11710 /* if (!commit (*MEM = $AT)) goto 1.
11712 This will sometimes be a delayed branch; see the write code below
11714 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11715 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11717 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11718 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11720 mips_multi_copy_insn (tmp3_insn);
11721 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11724 mips_multi_add_insn ("nop", NULL);
11726 /* Output the acquire side of the memory barrier. */
11727 if (TARGET_SYNC_AFTER_SC)
11728 mips_multi_add_insn ("sync", NULL);
11730 /* Output the exit label, if needed. */
11731 if (required_oldval)
11732 mips_multi_add_label ("2:");
11734 #undef READ_OPERAND
11737 /* Output and/or return the asm template for sync loop INSN, which has
11738 the operands given by OPERANDS. */
11741 mips_output_sync_loop (rtx insn, rtx *operands)
11743 mips_process_sync_loop (insn, operands);
11745 /* Use branch-likely instructions to work around the LL/SC R10000
11747 mips_branch_likely = TARGET_FIX_R10000;
11749 mips_push_asm_switch (&mips_noreorder);
11750 mips_push_asm_switch (&mips_nomacro);
11751 mips_push_asm_switch (&mips_noat);
11752 mips_start_ll_sc_sync_block ();
11754 mips_multi_write ();
11756 mips_end_ll_sc_sync_block ();
11757 mips_pop_asm_switch (&mips_noat);
11758 mips_pop_asm_switch (&mips_nomacro);
11759 mips_pop_asm_switch (&mips_noreorder);
11764 /* Return the number of individual instructions in sync loop INSN,
11765 which has the operands given by OPERANDS. */
11768 mips_sync_loop_insns (rtx insn, rtx *operands)
11770 mips_process_sync_loop (insn, operands);
11771 return mips_multi_num_insns;
11774 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11775 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11777 When working around R4000 and R4400 errata, we need to make sure that
11778 the division is not immediately followed by a shift[1][2]. We also
11779 need to stop the division from being put into a branch delay slot[3].
11780 The easiest way to avoid both problems is to add a nop after the
11781 division. When a divide-by-zero check is needed, this nop can be
11782 used to fill the branch delay slot.
11784 [1] If a double-word or a variable shift executes immediately
11785 after starting an integer division, the shift may give an
11786 incorrect result. See quotations of errata #16 and #28 from
11787 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11788 in mips.md for details.
11790 [2] A similar bug to [1] exists for all revisions of the
11791 R4000 and the R4400 when run in an MC configuration.
11792 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11794 "19. In this following sequence:
11796 ddiv (or ddivu or div or divu)
11797 dsll32 (or dsrl32, dsra32)
11799 if an MPT stall occurs, while the divide is slipping the cpu
11800 pipeline, then the following double shift would end up with an
11803 Workaround: The compiler needs to avoid generating any
11804 sequence with divide followed by extended double shift."
11806 This erratum is also present in "MIPS R4400MC Errata, Processor
11807 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11808 & 3.0" as errata #10 and #4, respectively.
11810 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11811 (also valid for MIPS R4000MC processors):
11813 "52. R4000SC: This bug does not apply for the R4000PC.
11815 There are two flavors of this bug:
11817 1) If the instruction just after divide takes an RF exception
11818 (tlb-refill, tlb-invalid) and gets an instruction cache
11819 miss (both primary and secondary) and the line which is
11820 currently in secondary cache at this index had the first
11821 data word, where the bits 5..2 are set, then R4000 would
11822 get a wrong result for the div.
11827 ------------------- # end-of page. -tlb-refill
11832 ------------------- # end-of page. -tlb-invalid
11835 2) If the divide is in the taken branch delay slot, where the
11836 target takes RF exception and gets an I-cache miss for the
11837 exception vector or where I-cache miss occurs for the
11838 target address, under the above mentioned scenarios, the
11839 div would get wrong results.
11842 j r2 # to next page mapped or unmapped
11843 div r8,r9 # this bug would be there as long
11844 # as there is an ICache miss and
11845 nop # the "data pattern" is present
11848 beq r0, r0, NextPage # to Next page
11852 This bug is present for div, divu, ddiv, and ddivu
11855 Workaround: For item 1), OS could make sure that the next page
11856 after the divide instruction is also mapped. For item 2), the
11857 compiler could make sure that the divide instruction is not in
11858 the branch delay slot."
11860 These processors have PRId values of 0x00004220 and 0x00004300 for
11861 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11864 mips_output_division (const char *division, rtx *operands)
11869 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11871 output_asm_insn (s, operands);
11874 if (TARGET_CHECK_ZERO_DIV)
11878 output_asm_insn (s, operands);
11879 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11881 else if (GENERATE_DIVIDE_TRAPS)
11883 /* Avoid long replay penalty on load miss by putting the trap before
11886 output_asm_insn ("teq\t%2,%.,7", operands);
11889 output_asm_insn (s, operands);
11890 s = "teq\t%2,%.,7";
11895 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11896 output_asm_insn (s, operands);
11897 s = "break\t7%)\n1:";
11903 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11904 instruction and if OUT_INSN assigns to the accumulator operand. */
11907 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11911 x = single_set (in_insn);
11917 if (GET_CODE (x) == PLUS
11918 && GET_CODE (XEXP (x, 0)) == MULT
11919 && reg_set_p (XEXP (x, 1), out_insn))
11922 if (GET_CODE (x) == MINUS
11923 && GET_CODE (XEXP (x, 1)) == MULT
11924 && reg_set_p (XEXP (x, 0), out_insn))
11930 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11931 data rather than the address. We need this because the cprestore
11932 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11933 which causes the default routine to abort. We just return false
11937 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11939 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11942 return !store_data_bypass_p (out_insn, in_insn);
11946 /* Variables and flags used in scheduler hooks when tuning for
11950 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11953 /* If true, then next ALU1/2 instruction will go to ALU1. */
11956 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11959 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11960 int alu1_core_unit_code;
11961 int alu2_core_unit_code;
11962 int falu1_core_unit_code;
11963 int falu2_core_unit_code;
11965 /* True if current cycle has a multi instruction.
11966 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11967 bool cycle_has_multi_p;
11969 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11970 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11972 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11973 instruction to go ALU1. */
11974 rtx alu1_turn_enabled_insn;
11975 rtx alu2_turn_enabled_insn;
11976 rtx falu1_turn_enabled_insn;
11977 rtx falu2_turn_enabled_insn;
11980 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11981 dependencies have no cost, except on the 20Kc where output-dependence
11982 is treated like input-dependence. */
11985 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11986 rtx dep ATTRIBUTE_UNUSED, int cost)
11988 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11991 if (REG_NOTE_KIND (link) != 0)
11996 /* Return the number of instructions that can be issued per cycle. */
11999 mips_issue_rate (void)
12003 case PROCESSOR_74KC:
12004 case PROCESSOR_74KF2_1:
12005 case PROCESSOR_74KF1_1:
12006 case PROCESSOR_74KF3_2:
12007 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12008 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12009 but in reality only a maximum of 3 insns can be issued as
12010 floating-point loads and stores also require a slot in the
12012 case PROCESSOR_R10000:
12013 /* All R10K Processors are quad-issue (being the first MIPS
12014 processors to support this feature). */
12017 case PROCESSOR_20KC:
12018 case PROCESSOR_R4130:
12019 case PROCESSOR_R5400:
12020 case PROCESSOR_R5500:
12021 case PROCESSOR_R7000:
12022 case PROCESSOR_R9000:
12023 case PROCESSOR_OCTEON:
12026 case PROCESSOR_SB1:
12027 case PROCESSOR_SB1A:
12028 /* This is actually 4, but we get better performance if we claim 3.
12029 This is partly because of unwanted speculative code motion with the
12030 larger number, and partly because in most common cases we can't
12031 reach the theoretical max of 4. */
12034 case PROCESSOR_LOONGSON_2E:
12035 case PROCESSOR_LOONGSON_2F:
12036 case PROCESSOR_LOONGSON_3A:
12044 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12047 mips_ls2_init_dfa_post_cycle_insn (void)
12050 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12051 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12055 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12056 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12060 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12061 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12065 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12066 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12069 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12070 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12071 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12072 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12075 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12076 Init data used in mips_dfa_post_advance_cycle. */
12079 mips_init_dfa_post_cycle_insn (void)
12081 if (TUNE_LOONGSON_2EF)
12082 mips_ls2_init_dfa_post_cycle_insn ();
12085 /* Initialize STATE when scheduling for Loongson 2E/2F.
12086 Support round-robin dispatch scheme by enabling only one of
12087 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12091 mips_ls2_dfa_post_advance_cycle (state_t state)
12093 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12095 /* Though there are no non-pipelined ALU1 insns,
12096 we can get an instruction of type 'multi' before reload. */
12097 gcc_assert (mips_ls2.cycle_has_multi_p);
12098 mips_ls2.alu1_turn_p = false;
12101 mips_ls2.cycle_has_multi_p = false;
12103 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12104 /* We have a non-pipelined alu instruction in the core,
12105 adjust round-robin counter. */
12106 mips_ls2.alu1_turn_p = true;
12108 if (mips_ls2.alu1_turn_p)
12110 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12111 gcc_unreachable ();
12115 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12116 gcc_unreachable ();
12119 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12121 /* There are no non-pipelined FALU1 insns. */
12122 gcc_unreachable ();
12123 mips_ls2.falu1_turn_p = false;
12126 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12127 /* We have a non-pipelined falu instruction in the core,
12128 adjust round-robin counter. */
12129 mips_ls2.falu1_turn_p = true;
12131 if (mips_ls2.falu1_turn_p)
12133 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12134 gcc_unreachable ();
12138 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12139 gcc_unreachable ();
12143 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12144 This hook is being called at the start of each cycle. */
12147 mips_dfa_post_advance_cycle (void)
12149 if (TUNE_LOONGSON_2EF)
12150 mips_ls2_dfa_post_advance_cycle (curr_state);
12153 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12154 be as wide as the scheduling freedom in the DFA. */
12157 mips_multipass_dfa_lookahead (void)
12159 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12163 if (TUNE_LOONGSON_2EF)
12172 /* Remove the instruction at index LOWER from ready queue READY and
12173 reinsert it in front of the instruction at index HIGHER. LOWER must
12177 mips_promote_ready (rtx *ready, int lower, int higher)
12182 new_head = ready[lower];
12183 for (i = lower; i < higher; i++)
12184 ready[i] = ready[i + 1];
12185 ready[i] = new_head;
12188 /* If the priority of the instruction at POS2 in the ready queue READY
12189 is within LIMIT units of that of the instruction at POS1, swap the
12190 instructions if POS2 is not already less than POS1. */
12193 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12196 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12200 temp = ready[pos1];
12201 ready[pos1] = ready[pos2];
12202 ready[pos2] = temp;
12206 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12207 that may clobber hi or lo. */
12208 static rtx mips_macc_chains_last_hilo;
12210 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12211 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12214 mips_macc_chains_record (rtx insn)
12216 if (get_attr_may_clobber_hilo (insn))
12217 mips_macc_chains_last_hilo = insn;
12220 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12221 has NREADY elements, looking for a multiply-add or multiply-subtract
12222 instruction that is cumulative with mips_macc_chains_last_hilo.
12223 If there is one, promote it ahead of anything else that might
12224 clobber hi or lo. */
12227 mips_macc_chains_reorder (rtx *ready, int nready)
12231 if (mips_macc_chains_last_hilo != 0)
12232 for (i = nready - 1; i >= 0; i--)
12233 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12235 for (j = nready - 1; j > i; j--)
12236 if (recog_memoized (ready[j]) >= 0
12237 && get_attr_may_clobber_hilo (ready[j]))
12239 mips_promote_ready (ready, i, j);
12246 /* The last instruction to be scheduled. */
12247 static rtx vr4130_last_insn;
12249 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12250 points to an rtx that is initially an instruction. Nullify the rtx
12251 if the instruction uses the value of register X. */
12254 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12259 insn_ptr = (rtx *) data;
12262 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12266 /* Return true if there is true register dependence between vr4130_last_insn
12270 vr4130_true_reg_dependence_p (rtx insn)
12272 note_stores (PATTERN (vr4130_last_insn),
12273 vr4130_true_reg_dependence_p_1, &insn);
12277 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12278 the ready queue and that INSN2 is the instruction after it, return
12279 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12280 in which INSN1 and INSN2 can probably issue in parallel, but for
12281 which (INSN2, INSN1) should be less sensitive to instruction
12282 alignment than (INSN1, INSN2). See 4130.md for more details. */
12285 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12287 sd_iterator_def sd_it;
12290 /* Check for the following case:
12292 1) there is some other instruction X with an anti dependence on INSN1;
12293 2) X has a higher priority than INSN2; and
12294 3) X is an arithmetic instruction (and thus has no unit restrictions).
12296 If INSN1 is the last instruction blocking X, it would better to
12297 choose (INSN1, X) over (INSN2, INSN1). */
12298 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12299 if (DEP_TYPE (dep) == REG_DEP_ANTI
12300 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12301 && recog_memoized (DEP_CON (dep)) >= 0
12302 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12305 if (vr4130_last_insn != 0
12306 && recog_memoized (insn1) >= 0
12307 && recog_memoized (insn2) >= 0)
12309 /* See whether INSN1 and INSN2 use different execution units,
12310 or if they are both ALU-type instructions. If so, they can
12311 probably execute in parallel. */
12312 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12313 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12314 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12316 /* If only one of the instructions has a dependence on
12317 vr4130_last_insn, prefer to schedule the other one first. */
12318 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12319 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12320 if (dep1_p != dep2_p)
12323 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12324 is not an ALU-type instruction and if INSN1 uses the same
12325 execution unit. (Note that if this condition holds, we already
12326 know that INSN2 uses a different execution unit.) */
12327 if (class1 != VR4130_CLASS_ALU
12328 && recog_memoized (vr4130_last_insn) >= 0
12329 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12336 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12337 queue with at least two instructions. Swap the first two if
12338 vr4130_swap_insns_p says that it could be worthwhile. */
12341 vr4130_reorder (rtx *ready, int nready)
12343 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12344 mips_promote_ready (ready, nready - 2, nready - 1);
12347 /* Record whether last 74k AGEN instruction was a load or store. */
12348 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12350 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12351 resets to TYPE_UNKNOWN state. */
12354 mips_74k_agen_init (rtx insn)
12356 if (!insn || CALL_P (insn) || JUMP_P (insn))
12357 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12360 enum attr_type type = get_attr_type (insn);
12361 if (type == TYPE_LOAD || type == TYPE_STORE)
12362 mips_last_74k_agen_insn = type;
12366 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12367 loads to be grouped together, and multiple stores to be grouped
12368 together. Swap things around in the ready queue to make this happen. */
12371 mips_74k_agen_reorder (rtx *ready, int nready)
12374 int store_pos, load_pos;
12379 for (i = nready - 1; i >= 0; i--)
12381 rtx insn = ready[i];
12382 if (USEFUL_INSN_P (insn))
12383 switch (get_attr_type (insn))
12386 if (store_pos == -1)
12391 if (load_pos == -1)
12400 if (load_pos == -1 || store_pos == -1)
12403 switch (mips_last_74k_agen_insn)
12406 /* Prefer to schedule loads since they have a higher latency. */
12408 /* Swap loads to the front of the queue. */
12409 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12412 /* Swap stores to the front of the queue. */
12413 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12420 /* Implement TARGET_SCHED_INIT. */
12423 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12424 int max_ready ATTRIBUTE_UNUSED)
12426 mips_macc_chains_last_hilo = 0;
12427 vr4130_last_insn = 0;
12428 mips_74k_agen_init (NULL_RTX);
12430 /* When scheduling for Loongson2, branch instructions go to ALU1,
12431 therefore basic block is most likely to start with round-robin counter
12432 pointed to ALU2. */
12433 mips_ls2.alu1_turn_p = false;
12434 mips_ls2.falu1_turn_p = true;
12437 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12440 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12441 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12443 if (!reload_completed
12444 && TUNE_MACC_CHAINS
12446 mips_macc_chains_reorder (ready, *nreadyp);
12448 if (reload_completed
12450 && !TARGET_VR4130_ALIGN
12452 vr4130_reorder (ready, *nreadyp);
12455 mips_74k_agen_reorder (ready, *nreadyp);
12458 /* Implement TARGET_SCHED_REORDER. */
12461 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12462 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12464 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12465 return mips_issue_rate ();
12468 /* Implement TARGET_SCHED_REORDER2. */
12471 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12472 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12474 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12475 return cached_can_issue_more;
12478 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12481 mips_ls2_variable_issue (rtx insn)
12483 if (mips_ls2.alu1_turn_p)
12485 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12486 mips_ls2.alu1_turn_p = false;
12490 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12491 mips_ls2.alu1_turn_p = true;
12494 if (mips_ls2.falu1_turn_p)
12496 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12497 mips_ls2.falu1_turn_p = false;
12501 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12502 mips_ls2.falu1_turn_p = true;
12505 if (recog_memoized (insn) >= 0)
12506 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12509 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12512 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12513 rtx insn, int more)
12515 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12516 if (USEFUL_INSN_P (insn))
12518 if (get_attr_type (insn) != TYPE_GHOST)
12520 if (!reload_completed && TUNE_MACC_CHAINS)
12521 mips_macc_chains_record (insn);
12522 vr4130_last_insn = insn;
12524 mips_74k_agen_init (insn);
12525 else if (TUNE_LOONGSON_2EF)
12526 mips_ls2_variable_issue (insn);
12529 /* Instructions of type 'multi' should all be split before
12530 the second scheduling pass. */
12531 gcc_assert (!reload_completed
12532 || recog_memoized (insn) < 0
12533 || get_attr_type (insn) != TYPE_MULTI);
12535 cached_can_issue_more = more;
12539 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12540 return the first operand of the associated PREF or PREFX insn. */
12543 mips_prefetch_cookie (rtx write, rtx locality)
12545 /* store_streamed / load_streamed. */
12546 if (INTVAL (locality) <= 0)
12547 return GEN_INT (INTVAL (write) + 4);
12549 /* store / load. */
12550 if (INTVAL (locality) <= 2)
12553 /* store_retained / load_retained. */
12554 return GEN_INT (INTVAL (write) + 6);
12557 /* Flags that indicate when a built-in function is available.
12559 BUILTIN_AVAIL_NON_MIPS16
12560 The function is available on the current target, but only
12561 in non-MIPS16 mode. */
12562 #define BUILTIN_AVAIL_NON_MIPS16 1
12564 /* Declare an availability predicate for built-in functions that
12565 require non-MIPS16 mode and also require COND to be true.
12566 NAME is the main part of the predicate's name. */
12567 #define AVAIL_NON_MIPS16(NAME, COND) \
12568 static unsigned int \
12569 mips_builtin_avail_##NAME (void) \
12571 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12574 /* This structure describes a single built-in function. */
12575 struct mips_builtin_description {
12576 /* The code of the main .md file instruction. See mips_builtin_type
12577 for more information. */
12578 enum insn_code icode;
12580 /* The floating-point comparison code to use with ICODE, if any. */
12581 enum mips_fp_condition cond;
12583 /* The name of the built-in function. */
12586 /* Specifies how the function should be expanded. */
12587 enum mips_builtin_type builtin_type;
12589 /* The function's prototype. */
12590 enum mips_function_type function_type;
12592 /* Whether the function is available. */
12593 unsigned int (*avail) (void);
12596 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12597 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12598 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12599 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12600 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12601 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12602 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12603 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12604 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12606 /* Construct a mips_builtin_description from the given arguments.
12608 INSN is the name of the associated instruction pattern, without the
12609 leading CODE_FOR_mips_.
12611 CODE is the floating-point condition code associated with the
12612 function. It can be 'f' if the field is not applicable.
12614 NAME is the name of the function itself, without the leading
12617 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12619 AVAIL is the name of the availability predicate, without the leading
12620 mips_builtin_avail_. */
12621 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12622 FUNCTION_TYPE, AVAIL) \
12623 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12624 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12625 mips_builtin_avail_ ## AVAIL }
12627 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12628 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12629 are as for MIPS_BUILTIN. */
12630 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12631 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12633 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12634 are subject to mips_builtin_avail_<AVAIL>. */
12635 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12636 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12637 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12638 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12639 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12641 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12642 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12643 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12644 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12645 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12646 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12648 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12649 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12651 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12652 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12654 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12655 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12658 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12659 are subject to mips_builtin_avail_mips3d. */
12660 #define CMP_4S_BUILTINS(INSN, COND) \
12661 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12662 MIPS_BUILTIN_CMP_ANY, \
12663 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12664 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12665 MIPS_BUILTIN_CMP_ALL, \
12666 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12668 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12669 instruction requires mips_builtin_avail_<AVAIL>. */
12670 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12671 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12672 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12674 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12675 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12678 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12679 #define CMP_BUILTINS(COND) \
12680 MOVTF_BUILTINS (c, COND, paired_single), \
12681 MOVTF_BUILTINS (cabs, COND, mips3d), \
12682 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12683 CMP_PS_BUILTINS (c, COND, paired_single), \
12684 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12685 CMP_4S_BUILTINS (c, COND), \
12686 CMP_4S_BUILTINS (cabs, COND)
12688 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12689 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12690 and AVAIL are as for MIPS_BUILTIN. */
12691 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12692 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12693 FUNCTION_TYPE, AVAIL)
12695 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12696 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12697 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12698 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12699 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12701 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12702 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12703 builtin_description field. */
12704 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12705 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12706 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12707 FUNCTION_TYPE, mips_builtin_avail_loongson }
12709 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12710 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12711 builtin_description field. */
12712 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12713 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12715 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12716 We use functions of this form when the same insn can be usefully applied
12717 to more than one datatype. */
12718 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12719 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12721 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12722 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12723 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12724 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12725 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12726 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12727 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
12728 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
12730 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12731 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12732 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12733 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12734 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12735 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12736 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12737 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12738 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12739 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12740 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12741 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12742 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12743 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12744 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12745 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12746 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12747 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
12748 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
12749 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
12750 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
12751 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
12752 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
12753 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12754 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12755 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12756 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12757 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12758 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12759 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12760 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12761 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12762 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12763 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12764 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12765 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12767 static const struct mips_builtin_description mips_builtins[] = {
12768 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12769 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12770 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12771 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12772 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12773 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12774 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12775 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12777 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12778 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12779 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12780 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12781 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12783 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12784 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12785 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12786 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12787 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12788 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12790 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12791 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12792 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12793 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12794 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12795 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12797 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12799 /* Built-in functions for the SB-1 processor. */
12800 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12802 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12803 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12804 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12805 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12806 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12807 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12808 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12809 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12810 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12811 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12812 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12813 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12814 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12815 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12816 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12817 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12818 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12819 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12820 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12821 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12822 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12823 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12824 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12825 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12826 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12827 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12828 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12829 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12830 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12831 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12832 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12833 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12834 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12835 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12836 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12837 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12838 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12839 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12840 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12841 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12842 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12843 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12844 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12845 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12846 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12847 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12848 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12849 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12850 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12851 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12852 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12853 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12854 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12855 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12856 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12857 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12858 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12859 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12860 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12861 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12862 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12863 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12864 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12865 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12866 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12867 BPOSGE_BUILTIN (32, dsp),
12869 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12870 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12871 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12872 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12873 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12874 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12875 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12876 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12877 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12878 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12879 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12880 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12881 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12882 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12883 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12884 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12885 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12886 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12887 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12888 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12889 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12890 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12891 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12892 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12893 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12894 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12895 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12896 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12897 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12898 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12899 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12900 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12901 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12902 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12903 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12905 /* Built-in functions for the DSP ASE (32-bit only). */
12906 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12907 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12908 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12909 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12910 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12911 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12912 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12913 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12914 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12915 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12916 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12917 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12918 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12919 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12920 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12921 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12922 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12923 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12924 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12925 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12926 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12927 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12928 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12929 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12930 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12931 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
12932 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
12934 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12935 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12936 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12937 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12938 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12939 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12940 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12941 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12942 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12943 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12945 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12946 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12947 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12948 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12949 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12950 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12951 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12952 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12953 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12954 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12955 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12956 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12957 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12958 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12959 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12960 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12961 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12962 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12963 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12964 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12965 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12966 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12967 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12968 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12969 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12970 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12971 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12972 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12973 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12974 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12975 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12976 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12977 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12978 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12979 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12980 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12981 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12982 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12983 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12984 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12985 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12986 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12987 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12988 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12989 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12990 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12991 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12992 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12993 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
12994 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12995 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12996 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12997 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12998 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
12999 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13000 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13001 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13002 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13003 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13004 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13005 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13006 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13007 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
13008 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
13009 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13010 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13011 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13012 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13013 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13014 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13015 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13016 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13017 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13018 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13019 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13020 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13021 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13022 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13023 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13024 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13025 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13026 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13027 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13028 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13029 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13030 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13031 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13032 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13033 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13034 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13035 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13036 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13037 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13038 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13039 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13040 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13041 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13042 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13043 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13044 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13046 /* Sundry other built-in functions. */
13047 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13050 /* Index I is the function declaration for mips_builtins[I], or null if the
13051 function isn't defined on this target. */
13052 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13054 /* MODE is a vector mode whose elements have type TYPE. Return the type
13055 of the vector itself. */
13058 mips_builtin_vector_type (tree type, enum machine_mode mode)
13060 static tree types[2 * (int) MAX_MACHINE_MODE];
13063 mode_index = (int) mode;
13065 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13066 mode_index += MAX_MACHINE_MODE;
13068 if (types[mode_index] == NULL_TREE)
13069 types[mode_index] = build_vector_type_for_mode (type, mode);
13070 return types[mode_index];
13073 /* Return a type for 'const volatile void *'. */
13076 mips_build_cvpointer_type (void)
13080 if (cache == NULL_TREE)
13081 cache = build_pointer_type (build_qualified_type
13083 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13087 /* Source-level argument types. */
13088 #define MIPS_ATYPE_VOID void_type_node
13089 #define MIPS_ATYPE_INT integer_type_node
13090 #define MIPS_ATYPE_POINTER ptr_type_node
13091 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13093 /* Standard mode-based argument types. */
13094 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13095 #define MIPS_ATYPE_SI intSI_type_node
13096 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13097 #define MIPS_ATYPE_DI intDI_type_node
13098 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13099 #define MIPS_ATYPE_SF float_type_node
13100 #define MIPS_ATYPE_DF double_type_node
13102 /* Vector argument types. */
13103 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13104 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13105 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13106 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13107 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13108 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13109 #define MIPS_ATYPE_UV2SI \
13110 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13111 #define MIPS_ATYPE_UV4HI \
13112 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13113 #define MIPS_ATYPE_UV8QI \
13114 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13116 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13117 their associated MIPS_ATYPEs. */
13118 #define MIPS_FTYPE_ATYPES1(A, B) \
13119 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13121 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13122 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13124 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13125 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13127 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13128 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13131 /* Return the function type associated with function prototype TYPE. */
13134 mips_build_function_type (enum mips_function_type type)
13136 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13138 if (types[(int) type] == NULL_TREE)
13141 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13142 case MIPS_FTYPE_NAME##NUM ARGS: \
13143 types[(int) type] \
13144 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13147 #include "config/mips/mips-ftypes.def"
13148 #undef DEF_MIPS_FTYPE
13150 gcc_unreachable ();
13153 return types[(int) type];
13156 /* Implement TARGET_INIT_BUILTINS. */
13159 mips_init_builtins (void)
13161 const struct mips_builtin_description *d;
13164 /* Iterate through all of the bdesc arrays, initializing all of the
13165 builtin functions. */
13166 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13168 d = &mips_builtins[i];
13170 mips_builtin_decls[i]
13171 = add_builtin_function (d->name,
13172 mips_build_function_type (d->function_type),
13173 i, BUILT_IN_MD, NULL, NULL);
13177 /* Implement TARGET_BUILTIN_DECL. */
13180 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13182 if (code >= ARRAY_SIZE (mips_builtins))
13183 return error_mark_node;
13184 return mips_builtin_decls[code];
13187 /* Take argument ARGNO from EXP's argument list and convert it into a
13188 form suitable for input operand OPNO of instruction ICODE. Return the
13192 mips_prepare_builtin_arg (enum insn_code icode,
13193 unsigned int opno, tree exp, unsigned int argno)
13197 enum machine_mode mode;
13199 arg = CALL_EXPR_ARG (exp, argno);
13200 value = expand_normal (arg);
13201 mode = insn_data[icode].operand[opno].mode;
13202 if (!insn_data[icode].operand[opno].predicate (value, mode))
13204 /* We need to get the mode from ARG for two reasons:
13206 - to cope with address operands, where MODE is the mode of the
13207 memory, rather than of VALUE itself.
13209 - to cope with special predicates like pmode_register_operand,
13210 where MODE is VOIDmode. */
13211 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
13213 /* Check the predicate again. */
13214 if (!insn_data[icode].operand[opno].predicate (value, mode))
13216 error ("invalid argument to built-in function");
13224 /* Return an rtx suitable for output operand OP of instruction ICODE.
13225 If TARGET is non-null, try to use it where possible. */
13228 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
13230 enum machine_mode mode;
13232 mode = insn_data[icode].operand[op].mode;
13233 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
13234 target = gen_reg_rtx (mode);
13239 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13240 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13241 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13242 suggests a good place to put the result. */
13245 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13248 rtx ops[MAX_RECOG_OPERANDS];
13251 /* Map any target to operand 0. */
13255 target = mips_prepare_builtin_target (icode, opno, target);
13256 ops[opno] = target;
13260 /* Map the arguments to the other operands. The n_operands value
13261 for an expander includes match_dups and match_scratches as well as
13262 match_operands, so n_operands is only an upper bound on the number
13263 of arguments to the expander function. */
13264 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
13265 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
13266 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
13271 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
13275 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
13279 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
13283 gcc_unreachable ();
13288 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13289 function; TYPE says which. EXP is the CALL_EXPR that calls the
13290 function, ICODE is the instruction that should be used to compare
13291 the first two arguments, and COND is the condition it should test.
13292 TARGET, if nonnull, suggests a good place to put the result. */
13295 mips_expand_builtin_movtf (enum mips_builtin_type type,
13296 enum insn_code icode, enum mips_fp_condition cond,
13297 rtx target, tree exp)
13299 rtx cmp_result, op0, op1;
13301 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13302 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
13303 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
13304 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
13306 icode = CODE_FOR_mips_cond_move_tf_ps;
13307 target = mips_prepare_builtin_target (icode, 0, target);
13308 if (type == MIPS_BUILTIN_MOVT)
13310 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
13311 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
13315 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
13316 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
13318 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
13322 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13323 into TARGET otherwise. Return TARGET. */
13326 mips_builtin_branch_and_move (rtx condition, rtx target,
13327 rtx value_if_true, rtx value_if_false)
13329 rtx true_label, done_label;
13331 true_label = gen_label_rtx ();
13332 done_label = gen_label_rtx ();
13334 /* First assume that CONDITION is false. */
13335 mips_emit_move (target, value_if_false);
13337 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13338 emit_jump_insn (gen_condjump (condition, true_label));
13339 emit_jump_insn (gen_jump (done_label));
13342 /* Fix TARGET if CONDITION is true. */
13343 emit_label (true_label);
13344 mips_emit_move (target, value_if_true);
13346 emit_label (done_label);
13350 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13351 the CALL_EXPR that calls the function, ICODE is the code of the
13352 comparison instruction, and COND is the condition it should test.
13353 TARGET, if nonnull, suggests a good place to put the boolean result. */
13356 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13357 enum insn_code icode, enum mips_fp_condition cond,
13358 rtx target, tree exp)
13360 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
13363 if (target == 0 || GET_MODE (target) != SImode)
13364 target = gen_reg_rtx (SImode);
13366 /* The instruction should have a target operand, an operand for each
13367 argument, and an operand for COND. */
13368 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
13370 /* Prepare the operands to the comparison. */
13371 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13372 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13373 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
13375 switch (insn_data[icode].n_operands)
13378 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13383 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13384 args[2], args[3], GEN_INT (cond)));
13388 gcc_unreachable ();
13391 /* If the comparison sets more than one register, we define the result
13392 to be 0 if all registers are false and -1 if all registers are true.
13393 The value of the complete result is indeterminate otherwise. */
13394 switch (builtin_type)
13396 case MIPS_BUILTIN_CMP_ALL:
13397 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13398 return mips_builtin_branch_and_move (condition, target,
13399 const0_rtx, const1_rtx);
13401 case MIPS_BUILTIN_CMP_UPPER:
13402 case MIPS_BUILTIN_CMP_LOWER:
13403 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13404 condition = gen_single_cc (cmp_result, offset);
13405 return mips_builtin_branch_and_move (condition, target,
13406 const1_rtx, const0_rtx);
13409 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13410 return mips_builtin_branch_and_move (condition, target,
13411 const1_rtx, const0_rtx);
13415 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13416 if nonnull, suggests a good place to put the boolean result. */
13419 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13421 rtx condition, cmp_result;
13424 if (target == 0 || GET_MODE (target) != SImode)
13425 target = gen_reg_rtx (SImode);
13427 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13429 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13434 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13435 return mips_builtin_branch_and_move (condition, target,
13436 const1_rtx, const0_rtx);
13439 /* Implement TARGET_EXPAND_BUILTIN. */
13442 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13443 enum machine_mode mode, int ignore)
13446 unsigned int fcode, avail;
13447 const struct mips_builtin_description *d;
13449 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13450 fcode = DECL_FUNCTION_CODE (fndecl);
13451 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13452 d = &mips_builtins[fcode];
13453 avail = d->avail ();
13454 gcc_assert (avail != 0);
13457 error ("built-in function %qE not supported for MIPS16",
13458 DECL_NAME (fndecl));
13459 return ignore ? const0_rtx : CONST0_RTX (mode);
13461 switch (d->builtin_type)
13463 case MIPS_BUILTIN_DIRECT:
13464 return mips_expand_builtin_direct (d->icode, target, exp, true);
13466 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13467 return mips_expand_builtin_direct (d->icode, target, exp, false);
13469 case MIPS_BUILTIN_MOVT:
13470 case MIPS_BUILTIN_MOVF:
13471 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13472 d->cond, target, exp);
13474 case MIPS_BUILTIN_CMP_ANY:
13475 case MIPS_BUILTIN_CMP_ALL:
13476 case MIPS_BUILTIN_CMP_UPPER:
13477 case MIPS_BUILTIN_CMP_LOWER:
13478 case MIPS_BUILTIN_CMP_SINGLE:
13479 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13480 d->cond, target, exp);
13482 case MIPS_BUILTIN_BPOSGE32:
13483 return mips_expand_builtin_bposge (d->builtin_type, target);
13485 gcc_unreachable ();
13488 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13489 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13490 struct mips16_constant {
13491 struct mips16_constant *next;
13494 enum machine_mode mode;
13497 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13498 first constant, HIGHEST_ADDRESS is the highest address that the first
13499 byte of the pool can have, and INSN_ADDRESS is the current instruction
13501 struct mips16_constant_pool {
13502 struct mips16_constant *first;
13503 int highest_address;
13507 /* Add constant VALUE to POOL and return its label. MODE is the
13508 value's mode (used for CONST_INTs, etc.). */
13511 mips16_add_constant (struct mips16_constant_pool *pool,
13512 rtx value, enum machine_mode mode)
13514 struct mips16_constant **p, *c;
13515 bool first_of_size_p;
13517 /* See whether the constant is already in the pool. If so, return the
13518 existing label, otherwise leave P pointing to the place where the
13519 constant should be added.
13521 Keep the pool sorted in increasing order of mode size so that we can
13522 reduce the number of alignments needed. */
13523 first_of_size_p = true;
13524 for (p = &pool->first; *p != 0; p = &(*p)->next)
13526 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13527 return (*p)->label;
13528 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13530 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13531 first_of_size_p = false;
13534 /* In the worst case, the constant needed by the earliest instruction
13535 will end up at the end of the pool. The entire pool must then be
13536 accessible from that instruction.
13538 When adding the first constant, set the pool's highest address to
13539 the address of the first out-of-range byte. Adjust this address
13540 downwards each time a new constant is added. */
13541 if (pool->first == 0)
13542 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13543 of the instruction with the lowest two bits clear. The base PC
13544 value for LDPC has the lowest three bits clear. Assume the worst
13545 case here; namely that the PC-relative instruction occupies the
13546 last 2 bytes in an aligned word. */
13547 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13548 pool->highest_address -= GET_MODE_SIZE (mode);
13549 if (first_of_size_p)
13550 /* Take into account the worst possible padding due to alignment. */
13551 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13553 /* Create a new entry. */
13554 c = XNEW (struct mips16_constant);
13557 c->label = gen_label_rtx ();
13564 /* Output constant VALUE after instruction INSN and return the last
13565 instruction emitted. MODE is the mode of the constant. */
13568 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13570 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13572 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13573 return emit_insn_after (gen_consttable_int (value, size), insn);
13576 if (SCALAR_FLOAT_MODE_P (mode))
13577 return emit_insn_after (gen_consttable_float (value), insn);
13579 if (VECTOR_MODE_P (mode))
13583 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13584 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13585 CONST_VECTOR_ELT (value, i), insn);
13589 gcc_unreachable ();
13592 /* Dump out the constants in CONSTANTS after INSN. */
13595 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13597 struct mips16_constant *c, *next;
13601 for (c = constants; c != NULL; c = next)
13603 /* If necessary, increase the alignment of PC. */
13604 if (align < GET_MODE_SIZE (c->mode))
13606 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13607 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13609 align = GET_MODE_SIZE (c->mode);
13611 insn = emit_label_after (c->label, insn);
13612 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13618 emit_barrier_after (insn);
13621 /* Return the length of instruction INSN. */
13624 mips16_insn_length (rtx insn)
13628 rtx body = PATTERN (insn);
13629 if (GET_CODE (body) == ADDR_VEC)
13630 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13631 if (GET_CODE (body) == ADDR_DIFF_VEC)
13632 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13634 return get_attr_length (insn);
13637 /* If *X is a symbolic constant that refers to the constant pool, add
13638 the constant to POOL and rewrite *X to use the constant's label. */
13641 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13643 rtx base, offset, label;
13645 split_const (*x, &base, &offset);
13646 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13648 label = mips16_add_constant (pool, get_pool_constant (base),
13649 get_pool_mode (base));
13650 base = gen_rtx_LABEL_REF (Pmode, label);
13651 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13655 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13656 INSN is the instruction we're rewriting and POOL points to the current
13658 struct mips16_rewrite_pool_refs_info {
13660 struct mips16_constant_pool *pool;
13663 /* Rewrite *X so that constant pool references refer to the constant's
13664 label instead. DATA points to a mips16_rewrite_pool_refs_info
13668 mips16_rewrite_pool_refs (rtx *x, void *data)
13670 struct mips16_rewrite_pool_refs_info *info =
13671 (struct mips16_rewrite_pool_refs_info *) data;
13673 if (force_to_mem_operand (*x, Pmode))
13675 rtx mem = force_const_mem (GET_MODE (*x), *x);
13676 validate_change (info->insn, x, mem, false);
13681 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13685 if (TARGET_MIPS16_TEXT_LOADS)
13686 mips16_rewrite_pool_constant (info->pool, x);
13688 return GET_CODE (*x) == CONST ? -1 : 0;
13691 /* Return whether CFG is used in mips_reorg. */
13694 mips_cfg_in_reorg (void)
13696 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13697 || TARGET_RELAX_PIC_CALLS);
13700 /* Build MIPS16 constant pools. */
13703 mips16_lay_out_constants (void)
13705 struct mips16_constant_pool pool;
13706 struct mips16_rewrite_pool_refs_info info;
13709 if (!TARGET_MIPS16_PCREL_LOADS)
13712 if (mips_cfg_in_reorg ())
13713 split_all_insns ();
13715 split_all_insns_noflow ();
13717 memset (&pool, 0, sizeof (pool));
13718 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13720 /* Rewrite constant pool references in INSN. */
13721 if (USEFUL_INSN_P (insn))
13725 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13728 pool.insn_address += mips16_insn_length (insn);
13730 if (pool.first != NULL)
13732 /* If there are no natural barriers between the first user of
13733 the pool and the highest acceptable address, we'll need to
13734 create a new instruction to jump around the constant pool.
13735 In the worst case, this instruction will be 4 bytes long.
13737 If it's too late to do this transformation after INSN,
13738 do it immediately before INSN. */
13739 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13743 label = gen_label_rtx ();
13745 jump = emit_jump_insn_before (gen_jump (label), insn);
13746 JUMP_LABEL (jump) = label;
13747 LABEL_NUSES (label) = 1;
13748 barrier = emit_barrier_after (jump);
13750 emit_label_after (label, barrier);
13751 pool.insn_address += 4;
13754 /* See whether the constant pool is now out of range of the first
13755 user. If so, output the constants after the previous barrier.
13756 Note that any instructions between BARRIER and INSN (inclusive)
13757 will use negative offsets to refer to the pool. */
13758 if (pool.insn_address > pool.highest_address)
13760 mips16_emit_constants (pool.first, barrier);
13764 else if (BARRIER_P (insn))
13768 mips16_emit_constants (pool.first, get_last_insn ());
13771 /* Return true if it is worth r10k_simplify_address's while replacing
13772 an address with X. We are looking for constants, and for addresses
13773 at a known offset from the incoming stack pointer. */
13776 r10k_simplified_address_p (rtx x)
13778 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13780 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13783 /* X is an expression that appears in INSN. Try to use the UD chains
13784 to simplify it, returning the simplified form on success and the
13785 original form otherwise. Replace the incoming value of $sp with
13786 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13789 r10k_simplify_address (rtx x, rtx insn)
13791 rtx newx, op0, op1, set, def_insn, note;
13793 struct df_link *defs;
13798 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13799 if (op0 != XEXP (x, 0))
13800 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13801 op0, GET_MODE (XEXP (x, 0)));
13803 else if (BINARY_P (x))
13805 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13806 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13807 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13808 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13810 else if (GET_CODE (x) == LO_SUM)
13812 /* LO_SUMs can be offset from HIGHs, if we know they won't
13813 overflow. See mips_classify_address for the rationale behind
13815 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13816 if (GET_CODE (op0) == HIGH)
13817 newx = XEXP (x, 1);
13819 else if (REG_P (x))
13821 /* Uses are recorded by regno_reg_rtx, not X itself. */
13822 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13824 defs = DF_REF_CHAIN (use);
13826 /* Require a single definition. */
13827 if (defs && defs->next == NULL)
13830 if (DF_REF_IS_ARTIFICIAL (def))
13832 /* Replace the incoming value of $sp with
13833 virtual_incoming_args_rtx. */
13834 if (x == stack_pointer_rtx
13835 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13836 newx = virtual_incoming_args_rtx;
13838 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13841 /* Make sure that DEF_INSN is a single set of REG. */
13842 def_insn = DF_REF_INSN (def);
13843 if (NONJUMP_INSN_P (def_insn))
13845 set = single_set (def_insn);
13846 if (set && rtx_equal_p (SET_DEST (set), x))
13848 /* Prefer to use notes, since the def-use chains
13849 are often shorter. */
13850 note = find_reg_equal_equiv_note (def_insn);
13852 newx = XEXP (note, 0);
13854 newx = SET_SRC (set);
13855 newx = r10k_simplify_address (newx, def_insn);
13861 if (newx && r10k_simplified_address_p (newx))
13866 /* Return true if ADDRESS is known to be an uncached address
13867 on R10K systems. */
13870 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13872 unsigned HOST_WIDE_INT upper;
13874 /* Check for KSEG1. */
13875 if (address + 0x60000000 < 0x20000000)
13878 /* Check for uncached XKPHYS addresses. */
13879 if (Pmode == DImode)
13881 upper = (address >> 40) & 0xf9ffff;
13882 if (upper == 0x900000 || upper == 0xb80000)
13888 /* Return true if we can prove that an access to address X in instruction
13889 INSN would be safe from R10K speculation. This X is a general
13890 expression; it might not be a legitimate address. */
13893 r10k_safe_address_p (rtx x, rtx insn)
13896 HOST_WIDE_INT offset_val;
13898 x = r10k_simplify_address (x, insn);
13900 /* Check for references to the stack frame. It doesn't really matter
13901 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13902 allows us to assume that accesses to any part of the eventual frame
13903 is safe from speculation at any point in the function. */
13904 mips_split_plus (x, &base, &offset_val);
13905 if (base == virtual_incoming_args_rtx
13906 && offset_val >= -cfun->machine->frame.total_size
13907 && offset_val < cfun->machine->frame.args_size)
13910 /* Check for uncached addresses. */
13911 if (CONST_INT_P (x))
13912 return r10k_uncached_address_p (INTVAL (x));
13914 /* Check for accesses to a static object. */
13915 split_const (x, &base, &offset);
13916 return offset_within_block_p (base, INTVAL (offset));
13919 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13920 an in-range access to an automatic variable, or to an object with
13921 a link-time-constant address. */
13924 r10k_safe_mem_expr_p (tree expr, rtx offset)
13926 if (expr == NULL_TREE
13927 || offset == NULL_RTX
13928 || !CONST_INT_P (offset)
13929 || INTVAL (offset) < 0
13930 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13933 while (TREE_CODE (expr) == COMPONENT_REF)
13935 expr = TREE_OPERAND (expr, 0);
13936 if (expr == NULL_TREE)
13940 return DECL_P (expr);
13943 /* A for_each_rtx callback for which DATA points to the instruction
13944 containing *X. Stop the search if we find a MEM that is not safe
13945 from R10K speculation. */
13948 r10k_needs_protection_p_1 (rtx *loc, void *data)
13956 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13959 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13965 /* A note_stores callback for which DATA points to an instruction pointer.
13966 If *DATA is nonnull, make it null if it X contains a MEM that is not
13967 safe from R10K speculation. */
13970 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13975 insn_ptr = (rtx *) data;
13976 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13977 *insn_ptr = NULL_RTX;
13980 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13981 Return nonzero if the call is not to a declared function. */
13984 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13993 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13999 /* Return true if instruction INSN needs to be protected by an R10K
14003 r10k_needs_protection_p (rtx insn)
14006 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
14008 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
14010 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
14011 return insn == NULL_RTX;
14014 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14017 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14018 edge is unconditional. */
14021 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14026 FOR_EACH_EDGE (e, ei, bb->preds)
14027 if (!single_succ_p (e->src)
14028 || !TEST_BIT (protected_bbs, e->src->index)
14029 || (e->flags & EDGE_COMPLEX) != 0)
14034 /* Implement -mr10k-cache-barrier= for the current function. */
14037 r10k_insert_cache_barriers (void)
14039 int *rev_post_order;
14042 sbitmap protected_bbs;
14043 rtx insn, end, unprotected_region;
14047 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14051 /* Calculate dominators. */
14052 calculate_dominance_info (CDI_DOMINATORS);
14054 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14055 X is protected by a cache barrier. */
14056 protected_bbs = sbitmap_alloc (last_basic_block);
14057 sbitmap_zero (protected_bbs);
14059 /* Iterate over the basic blocks in reverse post-order. */
14060 rev_post_order = XNEWVEC (int, last_basic_block);
14061 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14062 for (i = 0; i < n; i++)
14064 bb = BASIC_BLOCK (rev_post_order[i]);
14066 /* If this block is only reached by unconditional edges, and if the
14067 source of every edge is protected, the beginning of the block is
14069 if (r10k_protected_bb_p (bb, protected_bbs))
14070 unprotected_region = NULL_RTX;
14072 unprotected_region = pc_rtx;
14073 end = NEXT_INSN (BB_END (bb));
14075 /* UNPROTECTED_REGION is:
14077 - null if we are processing a protected region,
14078 - pc_rtx if we are processing an unprotected region but have
14079 not yet found the first instruction in it
14080 - the first instruction in an unprotected region otherwise. */
14081 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14083 if (unprotected_region && USEFUL_INSN_P (insn))
14085 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14086 /* This CACHE instruction protects the following code. */
14087 unprotected_region = NULL_RTX;
14090 /* See if INSN is the first instruction in this
14091 unprotected region. */
14092 if (unprotected_region == pc_rtx)
14093 unprotected_region = insn;
14095 /* See if INSN needs to be protected. If so,
14096 we must insert a cache barrier somewhere between
14097 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14098 clear which position is better performance-wise,
14099 but as a tie-breaker, we assume that it is better
14100 to allow delay slots to be back-filled where
14101 possible, and that it is better not to insert
14102 barriers in the middle of already-scheduled code.
14103 We therefore insert the barrier at the beginning
14105 if (r10k_needs_protection_p (insn))
14107 emit_insn_before (gen_r10k_cache_barrier (),
14108 unprotected_region);
14109 unprotected_region = NULL_RTX;
14115 /* The called function is not required to protect the exit path.
14116 The code that follows a call is therefore unprotected. */
14117 unprotected_region = pc_rtx;
14120 /* Record whether the end of this block is protected. */
14121 if (unprotected_region == NULL_RTX)
14122 SET_BIT (protected_bbs, bb->index);
14124 XDELETEVEC (rev_post_order);
14126 sbitmap_free (protected_bbs);
14128 free_dominance_info (CDI_DOMINATORS);
14131 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14132 otherwise. If INSN has two call rtx, then store the second one in
14136 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14141 if (!CALL_P (insn))
14144 x = PATTERN (insn);
14145 if (GET_CODE (x) == PARALLEL)
14147 /* Calls returning complex values have two CALL rtx. Look for the second
14148 one here, and return it via the SECOND_CALL arg. */
14149 x2 = XVECEXP (x, 0, 1);
14150 if (GET_CODE (x2) == SET)
14152 if (GET_CODE (x2) == CALL)
14155 x = XVECEXP (x, 0, 0);
14157 if (GET_CODE (x) == SET)
14159 gcc_assert (GET_CODE (x) == CALL);
14164 /* REG is set in DEF. See if the definition is one of the ways we load a
14165 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
14166 it is return the symbol reference of the function, otherwise return
14170 mips_pic_call_symbol_from_set (df_ref def, rtx reg)
14174 if (DF_REF_IS_ARTIFICIAL (def))
14177 def_insn = DF_REF_INSN (def);
14178 set = single_set (def_insn);
14179 if (set && rtx_equal_p (SET_DEST (set), reg))
14181 rtx note, src, symbol;
14183 /* First, look at REG_EQUAL/EQUIV notes. */
14184 note = find_reg_equal_equiv_note (def_insn);
14185 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14186 return XEXP (note, 0);
14188 /* For %call16 references we don't have REG_EQUAL. */
14189 src = SET_SRC (set);
14190 symbol = mips_strip_unspec_call (src);
14193 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14197 /* Follow simple register copies. */
14199 return mips_find_pic_call_symbol (def_insn, src);
14205 /* Find the definition of the use of REG in INSN. See if the definition is
14206 one of the ways we load a register with a symbol address for a
14207 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14208 the function, otherwise return NULL_RTX. */
14211 mips_find_pic_call_symbol (rtx insn, rtx reg)
14214 struct df_link *defs;
14217 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14220 defs = DF_REF_CHAIN (use);
14223 symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
14227 /* If we have more than one definition, they need to be identical. */
14228 for (defs = defs->next; defs; defs = defs->next)
14232 other = mips_pic_call_symbol_from_set (defs->ref, reg);
14233 if (!rtx_equal_p (symbol, other))
14240 /* Replace the args_size operand of the call expression CALL with the
14241 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14244 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14248 args_size = XEXP (call, 1);
14249 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14250 gen_rtvec (2, args_size, symbol),
14254 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14255 if instead of the arg_size argument it contains the call attributes. If
14256 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14257 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14261 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14263 rtx args_size, symbol;
14265 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14268 args_size = operands[args_size_opno];
14269 if (GET_CODE (args_size) != UNSPEC)
14271 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14273 symbol = XVECEXP (args_size, 0, 1);
14274 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14276 operands[args_size_opno] = symbol;
14280 /* Use DF to annotate PIC indirect calls with the function symbol they
14284 mips_annotate_pic_calls (void)
14290 FOR_BB_INSNS (bb, insn)
14292 rtx call, reg, symbol, second_call;
14295 call = mips_call_expr_from_insn (insn, &second_call);
14298 gcc_assert (MEM_P (XEXP (call, 0)));
14299 reg = XEXP (XEXP (call, 0), 0);
14303 symbol = mips_find_pic_call_symbol (insn, reg);
14306 mips_annotate_pic_call_expr (call, symbol);
14308 mips_annotate_pic_call_expr (second_call, symbol);
14313 /* A temporary variable used by for_each_rtx callbacks, etc. */
14314 static rtx mips_sim_insn;
14316 /* A structure representing the state of the processor pipeline.
14317 Used by the mips_sim_* family of functions. */
14319 /* The maximum number of instructions that can be issued in a cycle.
14320 (Caches mips_issue_rate.) */
14321 unsigned int issue_rate;
14323 /* The current simulation time. */
14326 /* How many more instructions can be issued in the current cycle. */
14327 unsigned int insns_left;
14329 /* LAST_SET[X].INSN is the last instruction to set register X.
14330 LAST_SET[X].TIME is the time at which that instruction was issued.
14331 INSN is null if no instruction has yet set register X. */
14335 } last_set[FIRST_PSEUDO_REGISTER];
14337 /* The pipeline's current DFA state. */
14341 /* Reset STATE to the initial simulation state. */
14344 mips_sim_reset (struct mips_sim *state)
14347 state->insns_left = state->issue_rate;
14348 memset (&state->last_set, 0, sizeof (state->last_set));
14349 state_reset (state->dfa_state);
14352 /* Initialize STATE before its first use. DFA_STATE points to an
14353 allocated but uninitialized DFA state. */
14356 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14358 state->issue_rate = mips_issue_rate ();
14359 state->dfa_state = dfa_state;
14360 mips_sim_reset (state);
14363 /* Advance STATE by one clock cycle. */
14366 mips_sim_next_cycle (struct mips_sim *state)
14369 state->insns_left = state->issue_rate;
14370 state_transition (state->dfa_state, 0);
14373 /* Advance simulation state STATE until instruction INSN can read
14377 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14379 unsigned int regno, end_regno;
14381 end_regno = END_REGNO (reg);
14382 for (regno = REGNO (reg); regno < end_regno; regno++)
14383 if (state->last_set[regno].insn != 0)
14387 t = (state->last_set[regno].time
14388 + insn_latency (state->last_set[regno].insn, insn));
14389 while (state->time < t)
14390 mips_sim_next_cycle (state);
14394 /* A for_each_rtx callback. If *X is a register, advance simulation state
14395 DATA until mips_sim_insn can read the register's value. */
14398 mips_sim_wait_regs_2 (rtx *x, void *data)
14401 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14405 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14408 mips_sim_wait_regs_1 (rtx *x, void *data)
14410 for_each_rtx (x, mips_sim_wait_regs_2, data);
14413 /* Advance simulation state STATE until all of INSN's register
14414 dependencies are satisfied. */
14417 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14419 mips_sim_insn = insn;
14420 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14423 /* Advance simulation state STATE until the units required by
14424 instruction INSN are available. */
14427 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14431 tmp_state = alloca (state_size ());
14432 while (state->insns_left == 0
14433 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14434 state_transition (tmp_state, insn) >= 0))
14435 mips_sim_next_cycle (state);
14438 /* Advance simulation state STATE until INSN is ready to issue. */
14441 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14443 mips_sim_wait_regs (state, insn);
14444 mips_sim_wait_units (state, insn);
14447 /* mips_sim_insn has just set X. Update the LAST_SET array
14448 in simulation state DATA. */
14451 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14453 struct mips_sim *state;
14455 state = (struct mips_sim *) data;
14458 unsigned int regno, end_regno;
14460 end_regno = END_REGNO (x);
14461 for (regno = REGNO (x); regno < end_regno; regno++)
14463 state->last_set[regno].insn = mips_sim_insn;
14464 state->last_set[regno].time = state->time;
14469 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14470 can issue immediately (i.e., that mips_sim_wait_insn has already
14474 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14476 state_transition (state->dfa_state, insn);
14477 state->insns_left--;
14479 mips_sim_insn = insn;
14480 note_stores (PATTERN (insn), mips_sim_record_set, state);
14483 /* Simulate issuing a NOP in state STATE. */
14486 mips_sim_issue_nop (struct mips_sim *state)
14488 if (state->insns_left == 0)
14489 mips_sim_next_cycle (state);
14490 state->insns_left--;
14493 /* Update simulation state STATE so that it's ready to accept the instruction
14494 after INSN. INSN should be part of the main rtl chain, not a member of a
14498 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14500 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14502 mips_sim_issue_nop (state);
14504 switch (GET_CODE (SEQ_BEGIN (insn)))
14508 /* We can't predict the processor state after a call or label. */
14509 mips_sim_reset (state);
14513 /* The delay slots of branch likely instructions are only executed
14514 when the branch is taken. Therefore, if the caller has simulated
14515 the delay slot instruction, STATE does not really reflect the state
14516 of the pipeline for the instruction after the delay slot. Also,
14517 branch likely instructions tend to incur a penalty when not taken,
14518 so there will probably be an extra delay between the branch and
14519 the instruction after the delay slot. */
14520 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14521 mips_sim_reset (state);
14529 /* The VR4130 pipeline issues aligned pairs of instructions together,
14530 but it stalls the second instruction if it depends on the first.
14531 In order to cut down the amount of logic required, this dependence
14532 check is not based on a full instruction decode. Instead, any non-SPECIAL
14533 instruction is assumed to modify the register specified by bits 20-16
14534 (which is usually the "rt" field).
14536 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14537 input, so we can end up with a false dependence between the branch
14538 and its delay slot. If this situation occurs in instruction INSN,
14539 try to avoid it by swapping rs and rt. */
14542 vr4130_avoid_branch_rt_conflict (rtx insn)
14546 first = SEQ_BEGIN (insn);
14547 second = SEQ_END (insn);
14549 && NONJUMP_INSN_P (second)
14550 && GET_CODE (PATTERN (first)) == SET
14551 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14552 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14554 /* Check for the right kind of condition. */
14555 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14556 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14557 && REG_P (XEXP (cond, 0))
14558 && REG_P (XEXP (cond, 1))
14559 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14560 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14562 /* SECOND mentions the rt register but not the rs register. */
14563 rtx tmp = XEXP (cond, 0);
14564 XEXP (cond, 0) = XEXP (cond, 1);
14565 XEXP (cond, 1) = tmp;
14570 /* Implement -mvr4130-align. Go through each basic block and simulate the
14571 processor pipeline. If we find that a pair of instructions could execute
14572 in parallel, and the first of those instructions is not 8-byte aligned,
14573 insert a nop to make it aligned. */
14576 vr4130_align_insns (void)
14578 struct mips_sim state;
14579 rtx insn, subinsn, last, last2, next;
14584 /* LAST is the last instruction before INSN to have a nonzero length.
14585 LAST2 is the last such instruction before LAST. */
14589 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14592 mips_sim_init (&state, alloca (state_size ()));
14593 for (insn = get_insns (); insn != 0; insn = next)
14595 unsigned int length;
14597 next = NEXT_INSN (insn);
14599 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14600 This isn't really related to the alignment pass, but we do it on
14601 the fly to avoid a separate instruction walk. */
14602 vr4130_avoid_branch_rt_conflict (insn);
14604 if (USEFUL_INSN_P (insn))
14605 FOR_EACH_SUBINSN (subinsn, insn)
14607 mips_sim_wait_insn (&state, subinsn);
14609 /* If we want this instruction to issue in parallel with the
14610 previous one, make sure that the previous instruction is
14611 aligned. There are several reasons why this isn't worthwhile
14612 when the second instruction is a call:
14614 - Calls are less likely to be performance critical,
14615 - There's a good chance that the delay slot can execute
14616 in parallel with the call.
14617 - The return address would then be unaligned.
14619 In general, if we're going to insert a nop between instructions
14620 X and Y, it's better to insert it immediately after X. That
14621 way, if the nop makes Y aligned, it will also align any labels
14622 between X and Y. */
14623 if (state.insns_left != state.issue_rate
14624 && !CALL_P (subinsn))
14626 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14628 /* SUBINSN is the first instruction in INSN and INSN is
14629 aligned. We want to align the previous instruction
14630 instead, so insert a nop between LAST2 and LAST.
14632 Note that LAST could be either a single instruction
14633 or a branch with a delay slot. In the latter case,
14634 LAST, like INSN, is already aligned, but the delay
14635 slot must have some extra delay that stops it from
14636 issuing at the same time as the branch. We therefore
14637 insert a nop before the branch in order to align its
14639 emit_insn_after (gen_nop (), last2);
14642 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14644 /* SUBINSN is the delay slot of INSN, but INSN is
14645 currently unaligned. Insert a nop between
14646 LAST and INSN to align it. */
14647 emit_insn_after (gen_nop (), last);
14651 mips_sim_issue_insn (&state, subinsn);
14653 mips_sim_finish_insn (&state, insn);
14655 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14656 length = get_attr_length (insn);
14659 /* If the instruction is an asm statement or multi-instruction
14660 mips.md patern, the length is only an estimate. Insert an
14661 8 byte alignment after it so that the following instructions
14662 can be handled correctly. */
14663 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14664 && (recog_memoized (insn) < 0 || length >= 8))
14666 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14667 next = NEXT_INSN (next);
14668 mips_sim_next_cycle (&state);
14671 else if (length & 4)
14672 aligned_p = !aligned_p;
14677 /* See whether INSN is an aligned label. */
14678 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14684 /* This structure records that the current function has a LO_SUM
14685 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14686 the largest offset applied to BASE by all such LO_SUMs. */
14687 struct mips_lo_sum_offset {
14689 HOST_WIDE_INT offset;
14692 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14695 mips_hash_base (rtx base)
14697 int do_not_record_p;
14699 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14702 /* Hash-table callbacks for mips_lo_sum_offsets. */
14705 mips_lo_sum_offset_hash (const void *entry)
14707 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14711 mips_lo_sum_offset_eq (const void *entry, const void *value)
14713 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14714 (const_rtx) value);
14717 /* Look up symbolic constant X in HTAB, which is a hash table of
14718 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14719 paired with a recorded LO_SUM, otherwise record X in the table. */
14722 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14726 struct mips_lo_sum_offset *entry;
14728 /* Split X into a base and offset. */
14729 split_const (x, &base, &offset);
14730 if (UNSPEC_ADDRESS_P (base))
14731 base = UNSPEC_ADDRESS (base);
14733 /* Look up the base in the hash table. */
14734 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14738 entry = (struct mips_lo_sum_offset *) *slot;
14739 if (option == INSERT)
14743 entry = XNEW (struct mips_lo_sum_offset);
14744 entry->base = base;
14745 entry->offset = INTVAL (offset);
14750 if (INTVAL (offset) > entry->offset)
14751 entry->offset = INTVAL (offset);
14754 return INTVAL (offset) <= entry->offset;
14757 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14758 Record every LO_SUM in *LOC. */
14761 mips_record_lo_sum (rtx *loc, void *data)
14763 if (GET_CODE (*loc) == LO_SUM)
14764 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14768 /* Return true if INSN is a SET of an orphaned high-part relocation.
14769 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14770 LO_SUMs in the current function. */
14773 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14775 enum mips_symbol_type type;
14778 set = single_set (insn);
14781 /* Check for %his. */
14783 if (GET_CODE (x) == HIGH
14784 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14785 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14787 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14788 if (GET_CODE (x) == UNSPEC
14789 && XINT (x, 1) == UNSPEC_LOAD_GOT
14790 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14791 SYMBOL_CONTEXT_LEA, &type)
14792 && type == SYMBOL_GOTOFF_PAGE)
14793 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14798 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14799 INSN and a previous instruction, avoid it by inserting nops after
14802 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14803 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14804 before using the value of that register. *HILO_DELAY counts the
14805 number of instructions since the last hilo hazard (that is,
14806 the number of instructions since the last MFLO or MFHI).
14808 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14809 for the next instruction.
14811 LO_REG is an rtx for the LO register, used in dependence checking. */
14814 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14815 rtx *delayed_reg, rtx lo_reg)
14820 pattern = PATTERN (insn);
14822 /* Do not put the whole function in .set noreorder if it contains
14823 an asm statement. We don't know whether there will be hazards
14824 between the asm statement and the gcc-generated code. */
14825 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14826 cfun->machine->all_noreorder_p = false;
14828 /* Ignore zero-length instructions (barriers and the like). */
14829 ninsns = get_attr_length (insn) / 4;
14833 /* Work out how many nops are needed. Note that we only care about
14834 registers that are explicitly mentioned in the instruction's pattern.
14835 It doesn't matter that calls use the argument registers or that they
14836 clobber hi and lo. */
14837 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14838 nops = 2 - *hilo_delay;
14839 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14844 /* Insert the nops between this instruction and the previous one.
14845 Each new nop takes us further from the last hilo hazard. */
14846 *hilo_delay += nops;
14848 emit_insn_after (gen_hazard_nop (), after);
14850 /* Set up the state for the next instruction. */
14851 *hilo_delay += ninsns;
14853 if (INSN_CODE (insn) >= 0)
14854 switch (get_attr_hazard (insn))
14864 set = single_set (insn);
14866 *delayed_reg = SET_DEST (set);
14871 /* Go through the instruction stream and insert nops where necessary.
14872 Also delete any high-part relocations whose partnering low parts
14873 are now all dead. See if the whole function can then be put into
14874 .set noreorder and .set nomacro. */
14877 mips_reorg_process_insns (void)
14879 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14883 /* Force all instructions to be split into their final form. */
14884 split_all_insns_noflow ();
14886 /* Recalculate instruction lengths without taking nops into account. */
14887 cfun->machine->ignore_hazard_length_p = true;
14888 shorten_branches (get_insns ());
14890 cfun->machine->all_noreorder_p = true;
14892 /* We don't track MIPS16 PC-relative offsets closely enough to make
14893 a good job of "set .noreorder" code in MIPS16 mode. */
14895 cfun->machine->all_noreorder_p = false;
14897 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14898 if (!TARGET_EXPLICIT_RELOCS)
14899 cfun->machine->all_noreorder_p = false;
14901 /* Profiled functions can't be all noreorder because the profiler
14902 support uses assembler macros. */
14904 cfun->machine->all_noreorder_p = false;
14906 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14907 we rely on the assembler to work around some errata. */
14908 if (TARGET_FIX_VR4120)
14909 cfun->machine->all_noreorder_p = false;
14911 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14912 MFHI instructions. Note that we avoid using MFLO and MFHI if
14913 the VR4130 MACC and DMACC instructions are available instead;
14914 see the *mfhilo_{si,di}_macc patterns. */
14915 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14916 cfun->machine->all_noreorder_p = false;
14918 htab = htab_create (37, mips_lo_sum_offset_hash,
14919 mips_lo_sum_offset_eq, free);
14921 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14922 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14923 FOR_EACH_SUBINSN (subinsn, insn)
14924 if (USEFUL_INSN_P (subinsn))
14925 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14930 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14932 /* Make a second pass over the instructions. Delete orphaned
14933 high-part relocations or turn them into NOPs. Avoid hazards
14934 by inserting NOPs. */
14935 for (insn = get_insns (); insn != 0; insn = next_insn)
14937 next_insn = NEXT_INSN (insn);
14938 if (USEFUL_INSN_P (insn))
14940 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14942 /* If we find an orphaned high-part relocation in a delay
14943 slot, it's easier to turn that instruction into a NOP than
14944 to delete it. The delay slot will be a NOP either way. */
14945 FOR_EACH_SUBINSN (subinsn, insn)
14946 if (INSN_P (subinsn))
14948 if (mips_orphaned_high_part_p (htab, subinsn))
14950 PATTERN (subinsn) = gen_nop ();
14951 INSN_CODE (subinsn) = CODE_FOR_nop;
14953 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14954 &delayed_reg, lo_reg);
14960 /* INSN is a single instruction. Delete it if it's an
14961 orphaned high-part relocation. */
14962 if (mips_orphaned_high_part_p (htab, insn))
14963 delete_insn (insn);
14964 /* Also delete cache barriers if the last instruction
14965 was an annulled branch. INSN will not be speculatively
14967 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14969 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14970 delete_insn (insn);
14973 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14974 &delayed_reg, lo_reg);
14981 htab_delete (htab);
14984 /* If we are using a GOT, but have not decided to use a global pointer yet,
14985 see whether we need one to implement long branches. Convert the ghost
14986 global-pointer instructions into real ones if so. */
14989 mips_expand_ghost_gp_insns (void)
14994 /* Quick exit if we already know that we will or won't need a
14996 if (!TARGET_USE_GOT
14997 || cfun->machine->global_pointer == INVALID_REGNUM
14998 || mips_must_initialize_gp_p ())
15001 shorten_branches (get_insns ());
15003 /* Look for a branch that is longer than normal. The normal length for
15004 non-MIPS16 branches is 8, because the length includes the delay slot.
15005 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15006 but they have no delay slot. */
15007 normal_length = (TARGET_MIPS16 ? 4 : 8);
15008 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15010 && USEFUL_INSN_P (insn)
15011 && get_attr_length (insn) > normal_length)
15014 if (insn == NULL_RTX)
15017 /* We've now established that we need $gp. */
15018 cfun->machine->must_initialize_gp_p = true;
15019 split_all_insns_noflow ();
15024 /* Subroutine of mips_reorg to manage passes that require DF. */
15027 mips_df_reorg (void)
15029 /* Create def-use chains. */
15030 df_set_flags (DF_EQ_NOTES);
15031 df_chain_add_problem (DF_UD_CHAIN);
15034 if (TARGET_RELAX_PIC_CALLS)
15035 mips_annotate_pic_calls ();
15037 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15038 r10k_insert_cache_barriers ();
15040 df_finish_pass (false);
15043 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15048 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15049 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15050 to date if the CFG is available. */
15051 if (mips_cfg_in_reorg ())
15052 compute_bb_for_insn ();
15053 mips16_lay_out_constants ();
15054 if (mips_cfg_in_reorg ())
15057 free_bb_for_insn ();
15060 if (optimize > 0 && flag_delayed_branch)
15061 dbr_schedule (get_insns ());
15062 mips_reorg_process_insns ();
15064 && TARGET_EXPLICIT_RELOCS
15066 && TARGET_VR4130_ALIGN)
15067 vr4130_align_insns ();
15068 if (mips_expand_ghost_gp_insns ())
15069 /* The expansion could invalidate some of the VR4130 alignment
15070 optimizations, but this should be an extremely rare case anyhow. */
15071 mips_reorg_process_insns ();
15074 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15075 in order to avoid duplicating too much logic from elsewhere. */
15078 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15079 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15082 rtx this_rtx, temp1, temp2, insn, fnaddr;
15083 bool use_sibcall_p;
15085 /* Pretend to be a post-reload pass while generating rtl. */
15086 reload_completed = 1;
15088 /* Mark the end of the (empty) prologue. */
15089 emit_note (NOTE_INSN_PROLOGUE_END);
15091 /* Determine if we can use a sibcall to call FUNCTION directly. */
15092 fnaddr = XEXP (DECL_RTL (function), 0);
15093 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15094 && const_call_insn_operand (fnaddr, Pmode));
15096 /* Determine if we need to load FNADDR from the GOT. */
15098 && (mips_got_symbol_type_p
15099 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15101 /* Pick a global pointer. Use a call-clobbered register if
15102 TARGET_CALL_SAVED_GP. */
15103 cfun->machine->global_pointer
15104 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15105 cfun->machine->must_initialize_gp_p = true;
15106 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15108 /* Set up the global pointer for n32 or n64 abicalls. */
15109 mips_emit_loadgp ();
15112 /* We need two temporary registers in some cases. */
15113 temp1 = gen_rtx_REG (Pmode, 2);
15114 temp2 = gen_rtx_REG (Pmode, 3);
15116 /* Find out which register contains the "this" pointer. */
15117 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15118 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15120 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15122 /* Add DELTA to THIS_RTX. */
15125 rtx offset = GEN_INT (delta);
15126 if (!SMALL_OPERAND (delta))
15128 mips_emit_move (temp1, offset);
15131 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15134 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15135 if (vcall_offset != 0)
15139 /* Set TEMP1 to *THIS_RTX. */
15140 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15142 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15143 addr = mips_add_offset (temp2, temp1, vcall_offset);
15145 /* Load the offset and add it to THIS_RTX. */
15146 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15147 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15150 /* Jump to the target function. Use a sibcall if direct jumps are
15151 allowed, otherwise load the address into a register first. */
15154 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15155 SIBLING_CALL_P (insn) = 1;
15159 /* This is messy. GAS treats "la $25,foo" as part of a call
15160 sequence and may allow a global "foo" to be lazily bound.
15161 The general move patterns therefore reject this combination.
15163 In this context, lazy binding would actually be OK
15164 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15165 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15166 We must therefore load the address via a temporary
15167 register if mips_dangerous_for_la25_p.
15169 If we jump to the temporary register rather than $25,
15170 the assembler can use the move insn to fill the jump's
15173 We can use the same technique for MIPS16 code, where $25
15174 is not a valid JR register. */
15175 if (TARGET_USE_PIC_FN_ADDR_REG
15177 && !mips_dangerous_for_la25_p (fnaddr))
15178 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15179 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15181 if (TARGET_USE_PIC_FN_ADDR_REG
15182 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15183 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15184 emit_jump_insn (gen_indirect_jump (temp1));
15187 /* Run just enough of rest_of_compilation. This sequence was
15188 "borrowed" from alpha.c. */
15189 insn = get_insns ();
15190 insn_locators_alloc ();
15191 split_all_insns_noflow ();
15192 mips16_lay_out_constants ();
15193 shorten_branches (insn);
15194 final_start_function (insn, file, 1);
15195 final (insn, file, 1);
15196 final_end_function ();
15198 /* Clean up the vars set above. Note that final_end_function resets
15199 the global pointer for us. */
15200 reload_completed = 0;
15203 /* The last argument passed to mips_set_mips16_mode, or negative if the
15204 function hasn't been called yet.
15206 There are two copies of this information. One is saved and restored
15207 by the PCH process while the other is specific to this compiler
15208 invocation. The information calculated by mips_set_mips16_mode
15209 is invalid unless the two variables are the same. */
15210 static int was_mips16_p = -1;
15211 static GTY(()) int was_mips16_pch_p = -1;
15213 /* Set up the target-dependent global state so that it matches the
15214 current function's ISA mode. */
15217 mips_set_mips16_mode (int mips16_p)
15219 if (mips16_p == was_mips16_p
15220 && mips16_p == was_mips16_pch_p)
15223 /* Restore base settings of various flags. */
15224 target_flags = mips_base_target_flags;
15225 flag_schedule_insns = mips_base_schedule_insns;
15226 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15227 flag_move_loop_invariants = mips_base_move_loop_invariants;
15228 align_loops = mips_base_align_loops;
15229 align_jumps = mips_base_align_jumps;
15230 align_functions = mips_base_align_functions;
15234 /* Switch to MIPS16 mode. */
15235 target_flags |= MASK_MIPS16;
15237 /* Don't run the scheduler before reload, since it tends to
15238 increase register pressure. */
15239 flag_schedule_insns = 0;
15241 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15242 the whole function to be in a single section. */
15243 flag_reorder_blocks_and_partition = 0;
15245 /* Don't move loop invariants, because it tends to increase
15246 register pressure. It also introduces an extra move in cases
15247 where the constant is the first operand in a two-operand binary
15248 instruction, or when it forms a register argument to a functon
15250 flag_move_loop_invariants = 0;
15252 target_flags |= MASK_EXPLICIT_RELOCS;
15254 /* Experiments suggest we get the best overall section-anchor
15255 results from using the range of an unextended LW or SW. Code
15256 that makes heavy use of byte or short accesses can do better
15257 with ranges of 0...31 and 0...63 respectively, but most code is
15258 sensitive to the range of LW and SW instead. */
15259 targetm.min_anchor_offset = 0;
15260 targetm.max_anchor_offset = 127;
15262 targetm.const_anchor = 0;
15264 /* MIPS16 has no BAL instruction. */
15265 target_flags &= ~MASK_RELAX_PIC_CALLS;
15267 if (flag_pic && !TARGET_OLDABI)
15268 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15271 sorry ("MIPS16 -mxgot code");
15273 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15274 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15278 /* Switch to normal (non-MIPS16) mode. */
15279 target_flags &= ~MASK_MIPS16;
15281 /* Provide default values for align_* for 64-bit targets. */
15284 if (align_loops == 0)
15286 if (align_jumps == 0)
15288 if (align_functions == 0)
15289 align_functions = 8;
15292 targetm.min_anchor_offset = -32768;
15293 targetm.max_anchor_offset = 32767;
15295 targetm.const_anchor = 0x8000;
15298 /* (Re)initialize MIPS target internals for new ISA. */
15299 mips_init_relocs ();
15303 if (!mips16_globals)
15304 mips16_globals = save_target_globals ();
15306 restore_target_globals (mips16_globals);
15309 restore_target_globals (&default_target_globals);
15311 was_mips16_p = mips16_p;
15312 was_mips16_pch_p = mips16_p;
15315 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15316 function should use the MIPS16 ISA and switch modes accordingly. */
15319 mips_set_current_function (tree fndecl)
15321 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15324 /* Allocate a chunk of memory for per-function machine-dependent data. */
15326 static struct machine_function *
15327 mips_init_machine_status (void)
15329 return ggc_alloc_cleared_machine_function ();
15332 /* Return the processor associated with the given ISA level, or null
15333 if the ISA isn't valid. */
15335 static const struct mips_cpu_info *
15336 mips_cpu_info_from_isa (int isa)
15340 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15341 if (mips_cpu_info_table[i].isa == isa)
15342 return mips_cpu_info_table + i;
15347 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15348 with a final "000" replaced by "k". Ignore case.
15350 Note: this function is shared between GCC and GAS. */
15353 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15355 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15356 given++, canonical++;
15358 return ((*given == 0 && *canonical == 0)
15359 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15362 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15363 CPU name. We've traditionally allowed a lot of variation here.
15365 Note: this function is shared between GCC and GAS. */
15368 mips_matching_cpu_name_p (const char *canonical, const char *given)
15370 /* First see if the name matches exactly, or with a final "000"
15371 turned into "k". */
15372 if (mips_strict_matching_cpu_name_p (canonical, given))
15375 /* If not, try comparing based on numerical designation alone.
15376 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15377 if (TOLOWER (*given) == 'r')
15379 if (!ISDIGIT (*given))
15382 /* Skip over some well-known prefixes in the canonical name,
15383 hoping to find a number there too. */
15384 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15386 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15388 else if (TOLOWER (canonical[0]) == 'r')
15391 return mips_strict_matching_cpu_name_p (canonical, given);
15394 /* Return the mips_cpu_info entry for the processor or ISA given
15395 by CPU_STRING. Return null if the string isn't recognized.
15397 A similar function exists in GAS. */
15399 static const struct mips_cpu_info *
15400 mips_parse_cpu (const char *cpu_string)
15405 /* In the past, we allowed upper-case CPU names, but it doesn't
15406 work well with the multilib machinery. */
15407 for (s = cpu_string; *s != 0; s++)
15410 warning (0, "CPU names must be lower case");
15414 /* 'from-abi' selects the most compatible architecture for the given
15415 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15416 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15418 if (strcasecmp (cpu_string, "from-abi") == 0)
15419 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15420 : ABI_NEEDS_64BIT_REGS ? 3
15421 : (TARGET_64BIT ? 3 : 1));
15423 /* 'default' has traditionally been a no-op. Probably not very useful. */
15424 if (strcasecmp (cpu_string, "default") == 0)
15427 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15428 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
15429 return mips_cpu_info_table + i;
15434 /* Set up globals to generate code for the ISA or processor
15435 described by INFO. */
15438 mips_set_architecture (const struct mips_cpu_info *info)
15442 mips_arch_info = info;
15443 mips_arch = info->cpu;
15444 mips_isa = info->isa;
15448 /* Likewise for tuning. */
15451 mips_set_tune (const struct mips_cpu_info *info)
15455 mips_tune_info = info;
15456 mips_tune = info->cpu;
15460 /* Implement TARGET_HANDLE_OPTION. */
15463 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
15468 if (strcmp (arg, "32") == 0)
15470 else if (strcmp (arg, "o64") == 0)
15471 mips_abi = ABI_O64;
15472 else if (strcmp (arg, "n32") == 0)
15473 mips_abi = ABI_N32;
15474 else if (strcmp (arg, "64") == 0)
15476 else if (strcmp (arg, "eabi") == 0)
15477 mips_abi = ABI_EABI;
15484 return mips_parse_cpu (arg) != 0;
15487 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
15488 return mips_isa_option_info != 0;
15490 case OPT_mno_flush_func:
15491 mips_cache_flush_func = NULL;
15494 case OPT_mcode_readable_:
15495 if (strcmp (arg, "yes") == 0)
15496 mips_code_readable = CODE_READABLE_YES;
15497 else if (strcmp (arg, "pcrel") == 0)
15498 mips_code_readable = CODE_READABLE_PCREL;
15499 else if (strcmp (arg, "no") == 0)
15500 mips_code_readable = CODE_READABLE_NO;
15505 case OPT_mr10k_cache_barrier_:
15506 if (strcmp (arg, "load-store") == 0)
15507 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
15508 else if (strcmp (arg, "store") == 0)
15509 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
15510 else if (strcmp (arg, "none") == 0)
15511 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15521 /* Implement TARGET_OPTION_OVERRIDE. */
15524 mips_option_override (void)
15526 int i, start, regno, mode;
15528 /* Process flags as though we were generating non-MIPS16 code. */
15529 mips_base_mips16 = TARGET_MIPS16;
15530 target_flags &= ~MASK_MIPS16;
15532 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15533 SUBTARGET_OVERRIDE_OPTIONS;
15536 /* -mno-float overrides -mhard-float and -msoft-float. */
15537 if (TARGET_NO_FLOAT)
15539 target_flags |= MASK_SOFT_FLOAT_ABI;
15540 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15543 if (TARGET_FLIP_MIPS16)
15544 TARGET_INTERLINK_MIPS16 = 1;
15546 /* Set the small data limit. */
15547 mips_small_data_threshold = (global_options_set.x_g_switch_value
15549 : MIPS_DEFAULT_GVALUE);
15551 /* The following code determines the architecture and register size.
15552 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15553 The GAS and GCC code should be kept in sync as much as possible. */
15555 if (mips_arch_string != 0)
15556 mips_set_architecture (mips_parse_cpu (mips_arch_string));
15558 if (mips_isa_option_info != 0)
15560 if (mips_arch_info == 0)
15561 mips_set_architecture (mips_isa_option_info);
15562 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15563 error ("%<-%s%> conflicts with the other architecture options, "
15564 "which specify a %s processor",
15565 mips_isa_option_info->name,
15566 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15569 if (mips_arch_info == 0)
15571 #ifdef MIPS_CPU_STRING_DEFAULT
15572 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
15574 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
15578 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15579 error ("%<-march=%s%> is not compatible with the selected ABI",
15580 mips_arch_info->name);
15582 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15583 if (mips_tune_string != 0)
15584 mips_set_tune (mips_parse_cpu (mips_tune_string));
15586 if (mips_tune_info == 0)
15587 mips_set_tune (mips_arch_info);
15589 if ((target_flags_explicit & MASK_64BIT) != 0)
15591 /* The user specified the size of the integer registers. Make sure
15592 it agrees with the ABI and ISA. */
15593 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15594 error ("%<-mgp64%> used with a 32-bit processor");
15595 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15596 error ("%<-mgp32%> used with a 64-bit ABI");
15597 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15598 error ("%<-mgp64%> used with a 32-bit ABI");
15602 /* Infer the integer register size from the ABI and processor.
15603 Restrict ourselves to 32-bit registers if that's all the
15604 processor has, or if the ABI cannot handle 64-bit registers. */
15605 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15606 target_flags &= ~MASK_64BIT;
15608 target_flags |= MASK_64BIT;
15611 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15613 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15614 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15615 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15616 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15617 else if (!TARGET_64BIT && TARGET_FLOAT64)
15619 if (!ISA_HAS_MXHC1)
15620 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15621 " the target supports the mfhc1 and mthc1 instructions");
15622 else if (mips_abi != ABI_32)
15623 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15629 /* -msingle-float selects 32-bit float registers. Otherwise the
15630 float registers should be the same size as the integer ones. */
15631 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15632 target_flags |= MASK_FLOAT64;
15634 target_flags &= ~MASK_FLOAT64;
15637 /* End of code shared with GAS. */
15639 /* If no -mlong* option was given, infer it from the other options. */
15640 if ((target_flags_explicit & MASK_LONG64) == 0)
15642 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15643 target_flags |= MASK_LONG64;
15645 target_flags &= ~MASK_LONG64;
15648 if (!TARGET_OLDABI)
15649 flag_pcc_struct_return = 0;
15651 /* Decide which rtx_costs structure to use. */
15653 mips_cost = &mips_rtx_cost_optimize_size;
15655 mips_cost = &mips_rtx_cost_data[mips_tune];
15657 /* If the user hasn't specified a branch cost, use the processor's
15659 if (mips_branch_cost == 0)
15660 mips_branch_cost = mips_cost->branch_cost;
15662 /* If neither -mbranch-likely nor -mno-branch-likely was given
15663 on the command line, set MASK_BRANCHLIKELY based on the target
15664 architecture and tuning flags. Annulled delay slots are a
15665 size win, so we only consider the processor-specific tuning
15666 for !optimize_size. */
15667 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15669 if (ISA_HAS_BRANCHLIKELY
15671 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15672 target_flags |= MASK_BRANCHLIKELY;
15674 target_flags &= ~MASK_BRANCHLIKELY;
15676 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15677 warning (0, "the %qs architecture does not support branch-likely"
15678 " instructions", mips_arch_info->name);
15680 /* The effect of -mabicalls isn't defined for the EABI. */
15681 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15683 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15684 target_flags &= ~MASK_ABICALLS;
15687 if (TARGET_ABICALLS_PIC2)
15688 /* We need to set flag_pic for executables as well as DSOs
15689 because we may reference symbols that are not defined in
15690 the final executable. (MIPS does not use things like
15691 copy relocs, for example.)
15693 There is a body of code that uses __PIC__ to distinguish
15694 between -mabicalls and -mno-abicalls code. The non-__PIC__
15695 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15696 long as any indirect jumps use $25. */
15699 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15700 faster code, but at the expense of more nops. Enable it at -O3 and
15702 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15703 target_flags |= MASK_VR4130_ALIGN;
15705 /* Prefer a call to memcpy over inline code when optimizing for size,
15706 though see MOVE_RATIO in mips.h. */
15707 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15708 target_flags |= MASK_MEMCPY;
15710 /* If we have a nonzero small-data limit, check that the -mgpopt
15711 setting is consistent with the other target flags. */
15712 if (mips_small_data_threshold > 0)
15716 if (!TARGET_EXPLICIT_RELOCS)
15717 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15719 TARGET_LOCAL_SDATA = false;
15720 TARGET_EXTERN_SDATA = false;
15724 if (TARGET_VXWORKS_RTP)
15725 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15727 if (TARGET_ABICALLS)
15728 warning (0, "cannot use small-data accesses for %qs",
15733 #ifdef MIPS_TFMODE_FORMAT
15734 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15737 /* Make sure that the user didn't turn off paired single support when
15738 MIPS-3D support is requested. */
15740 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15741 && !TARGET_PAIRED_SINGLE_FLOAT)
15742 error ("%<-mips3d%> requires %<-mpaired-single%>");
15744 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15746 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15748 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15749 and TARGET_HARD_FLOAT_ABI are both true. */
15750 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15751 error ("%qs must be used with %qs",
15752 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15753 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15755 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15757 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15758 warning (0, "the %qs architecture does not support paired-single"
15759 " instructions", mips_arch_info->name);
15761 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15762 && !TARGET_CACHE_BUILTIN)
15764 error ("%qs requires a target that provides the %qs instruction",
15765 "-mr10k-cache-barrier", "cache");
15766 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15769 /* If TARGET_DSPR2, enable MASK_DSP. */
15771 target_flags |= MASK_DSP;
15773 /* .eh_frame addresses should be the same width as a C pointer.
15774 Most MIPS ABIs support only one pointer size, so the assembler
15775 will usually know exactly how big an .eh_frame address is.
15777 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15778 originally defined to use 64-bit pointers (i.e. it is LP64), and
15779 this is still the default mode. However, we also support an n32-like
15780 ILP32 mode, which is selected by -mlong32. The problem is that the
15781 assembler has traditionally not had an -mlong option, so it has
15782 traditionally not known whether we're using the ILP32 or LP64 form.
15784 As it happens, gas versions up to and including 2.19 use _32-bit_
15785 addresses for EABI64 .cfi_* directives. This is wrong for the
15786 default LP64 mode, so we can't use the directives by default.
15787 Moreover, since gas's current behavior is at odds with gcc's
15788 default behavior, it seems unwise to rely on future versions
15789 of gas behaving the same way. We therefore avoid using .cfi
15790 directives for -mlong32 as well. */
15791 if (mips_abi == ABI_EABI && TARGET_64BIT)
15792 flag_dwarf2_cfi_asm = 0;
15794 /* .cfi_* directives generate a read-only section, so fall back on
15795 manual .eh_frame creation if we need the section to be writable. */
15796 if (TARGET_WRITABLE_EH_FRAME)
15797 flag_dwarf2_cfi_asm = 0;
15799 mips_init_print_operand_punct ();
15801 /* Set up array to map GCC register number to debug register number.
15802 Ignore the special purpose register numbers. */
15804 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15806 mips_dbx_regno[i] = INVALID_REGNUM;
15807 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15808 mips_dwarf_regno[i] = i;
15810 mips_dwarf_regno[i] = INVALID_REGNUM;
15813 start = GP_DBX_FIRST - GP_REG_FIRST;
15814 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15815 mips_dbx_regno[i] = i + start;
15817 start = FP_DBX_FIRST - FP_REG_FIRST;
15818 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15819 mips_dbx_regno[i] = i + start;
15821 /* Accumulator debug registers use big-endian ordering. */
15822 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15823 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15824 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15825 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15826 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15828 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15829 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15832 /* Set up mips_hard_regno_mode_ok. */
15833 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15834 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15835 mips_hard_regno_mode_ok[mode][regno]
15836 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15838 /* Function to allocate machine-dependent function status. */
15839 init_machine_status = &mips_init_machine_status;
15841 /* Default to working around R4000 errata only if the processor
15842 was selected explicitly. */
15843 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15844 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
15845 target_flags |= MASK_FIX_R4000;
15847 /* Default to working around R4400 errata only if the processor
15848 was selected explicitly. */
15849 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15850 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
15851 target_flags |= MASK_FIX_R4400;
15853 /* Default to working around R10000 errata only if the processor
15854 was selected explicitly. */
15855 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15856 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
15857 target_flags |= MASK_FIX_R10000;
15859 /* Make sure that branch-likely instructions available when using
15860 -mfix-r10000. The instructions are not available if either:
15862 1. -mno-branch-likely was passed.
15863 2. The selected ISA does not support branch-likely and
15864 the command line does not include -mbranch-likely. */
15865 if (TARGET_FIX_R10000
15866 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15867 ? !ISA_HAS_BRANCHLIKELY
15868 : !TARGET_BRANCHLIKELY))
15869 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15871 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15873 warning (0, "the %qs architecture does not support the synci "
15874 "instruction", mips_arch_info->name);
15875 target_flags &= ~MASK_SYNCI;
15878 /* Only optimize PIC indirect calls if they are actually required. */
15879 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15880 target_flags &= ~MASK_RELAX_PIC_CALLS;
15882 /* Save base state of options. */
15883 mips_base_target_flags = target_flags;
15884 mips_base_schedule_insns = flag_schedule_insns;
15885 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15886 mips_base_move_loop_invariants = flag_move_loop_invariants;
15887 mips_base_align_loops = align_loops;
15888 mips_base_align_jumps = align_jumps;
15889 mips_base_align_functions = align_functions;
15891 /* Now select the ISA mode.
15893 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15894 MIPS16 mode afterwards if need be. */
15895 mips_set_mips16_mode (false);
15898 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
15899 static const struct default_options mips_option_optimization_table[] =
15901 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
15902 { OPT_LEVELS_NONE, 0, NULL, 0 }
15905 /* Swap the register information for registers I and I + 1, which
15906 currently have the wrong endianness. Note that the registers'
15907 fixedness and call-clobberedness might have been set on the
15911 mips_swap_registers (unsigned int i)
15916 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15917 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15919 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15920 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15921 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15922 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15928 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
15931 mips_conditional_register_usage (void)
15936 /* These DSP control register fields are global. */
15937 global_regs[CCDSP_PO_REGNUM] = 1;
15938 global_regs[CCDSP_SC_REGNUM] = 1;
15944 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15945 fixed_regs[regno] = call_used_regs[regno] = 1;
15947 if (!TARGET_HARD_FLOAT)
15951 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15952 fixed_regs[regno] = call_used_regs[regno] = 1;
15953 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15954 fixed_regs[regno] = call_used_regs[regno] = 1;
15956 else if (! ISA_HAS_8CC)
15960 /* We only have a single condition-code register. We implement
15961 this by fixing all the condition-code registers and generating
15962 RTL that refers directly to ST_REG_FIRST. */
15963 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15964 fixed_regs[regno] = call_used_regs[regno] = 1;
15966 /* In MIPS16 mode, we permit the $t temporary registers to be used
15967 for reload. We prohibit the unused $s registers, since they
15968 are call-saved, and saving them via a MIPS16 register would
15969 probably waste more time than just reloading the value. */
15972 fixed_regs[18] = call_used_regs[18] = 1;
15973 fixed_regs[19] = call_used_regs[19] = 1;
15974 fixed_regs[20] = call_used_regs[20] = 1;
15975 fixed_regs[21] = call_used_regs[21] = 1;
15976 fixed_regs[22] = call_used_regs[22] = 1;
15977 fixed_regs[23] = call_used_regs[23] = 1;
15978 fixed_regs[26] = call_used_regs[26] = 1;
15979 fixed_regs[27] = call_used_regs[27] = 1;
15980 fixed_regs[30] = call_used_regs[30] = 1;
15982 /* $f20-$f23 are call-clobbered for n64. */
15983 if (mips_abi == ABI_64)
15986 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15987 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15989 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15991 if (mips_abi == ABI_N32)
15994 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15995 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15997 /* Make sure that double-register accumulator values are correctly
15998 ordered for the current endianness. */
15999 if (TARGET_LITTLE_ENDIAN)
16001 unsigned int regno;
16003 mips_swap_registers (MD_REG_FIRST);
16004 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
16005 mips_swap_registers (regno);
16009 /* Initialize vector TARGET to VALS. */
16012 mips_expand_vector_init (rtx target, rtx vals)
16014 enum machine_mode mode;
16015 enum machine_mode inner;
16016 unsigned int i, n_elts;
16019 mode = GET_MODE (target);
16020 inner = GET_MODE_INNER (mode);
16021 n_elts = GET_MODE_NUNITS (mode);
16023 gcc_assert (VECTOR_MODE_P (mode));
16025 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
16026 for (i = 0; i < n_elts; i++)
16027 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
16028 XVECEXP (vals, 0, i));
16030 emit_move_insn (target, mem);
16033 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16034 other registers for instructions for which it is possible. This
16035 encourages the compiler to use CMP in cases where an XOR would
16036 require some register shuffling. */
16039 mips_order_regs_for_local_alloc (void)
16043 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16044 reg_alloc_order[i] = i;
16048 /* It really doesn't matter where we put register 0, since it is
16049 a fixed register anyhow. */
16050 reg_alloc_order[0] = 24;
16051 reg_alloc_order[24] = 0;
16055 /* Implement EH_USES. */
16058 mips_eh_uses (unsigned int regno)
16060 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16062 /* We need to force certain registers to be live in order to handle
16063 PIC long branches correctly. See mips_must_initialize_gp_p for
16065 if (mips_cfun_has_cprestore_slot_p ())
16067 if (regno == CPRESTORE_SLOT_REGNUM)
16072 if (cfun->machine->global_pointer == regno)
16080 /* Implement EPILOGUE_USES. */
16083 mips_epilogue_uses (unsigned int regno)
16085 /* Say that the epilogue uses the return address register. Note that
16086 in the case of sibcalls, the values "used by the epilogue" are
16087 considered live at the start of the called function. */
16088 if (regno == RETURN_ADDR_REGNUM)
16091 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16092 See the comment above load_call<mode> for details. */
16093 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16096 /* An interrupt handler must preserve some registers that are
16097 ordinarily call-clobbered. */
16098 if (cfun->machine->interrupt_handler_p
16099 && mips_interrupt_extra_call_saved_reg_p (regno))
16105 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16108 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16110 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16113 /* Return true if INSN needs to be wrapped in ".set noat".
16114 INSN has NOPERANDS operands, stored in OPVEC. */
16117 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16121 if (recog_memoized (insn) >= 0)
16122 for (i = 0; i < noperands; i++)
16123 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16128 /* Implement FINAL_PRESCAN_INSN. */
16131 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16133 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16134 mips_push_asm_switch (&mips_noat);
16137 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16140 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16141 rtx *opvec, int noperands)
16143 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16144 mips_pop_asm_switch (&mips_noat);
16147 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16148 EXT_CODE is the code of the extension used. Return NULL if widening
16149 multiplication shouldn't be used. */
16152 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16156 signed_p = ext_code == SIGN_EXTEND;
16159 /* Don't use widening multiplication with MULT when we have DMUL. Even
16160 with the extension of its input operands DMUL is faster. Note that
16161 the extension is not needed for signed multiplication. In order to
16162 ensure that we always remove the redundant sign-extension in this
16163 case we still expand mulsidi3 for DMUL. */
16165 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16166 if (TARGET_FIX_R4000)
16168 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16172 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16173 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16174 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16178 /* Return the size in bytes of the trampoline code, padded to
16179 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16180 function address immediately follow. */
16183 mips_trampoline_code_size (void)
16185 if (TARGET_USE_PIC_FN_ADDR_REG)
16187 else if (ptr_mode == DImode)
16189 else if (ISA_HAS_LOAD_DELAY)
16195 /* Implement TARGET_TRAMPOLINE_INIT. */
16198 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16200 rtx addr, end_addr, high, low, opcode, mem;
16203 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16205 /* Work out the offsets of the pointers from the start of the
16206 trampoline code. */
16207 end_addr_offset = mips_trampoline_code_size ();
16208 static_chain_offset = end_addr_offset;
16209 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16211 /* Get pointers to the beginning and end of the code block. */
16212 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16213 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16215 #define OP(X) gen_int_mode (X, SImode)
16217 /* Build up the code in TRAMPOLINE. */
16219 if (TARGET_USE_PIC_FN_ADDR_REG)
16221 /* $25 contains the address of the trampoline. Emit code of the form:
16223 l[wd] $1, target_function_offset($25)
16224 l[wd] $static_chain, static_chain_offset($25)
16227 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16228 target_function_offset,
16229 PIC_FUNCTION_ADDR_REGNUM));
16230 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16231 static_chain_offset,
16232 PIC_FUNCTION_ADDR_REGNUM));
16233 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16234 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16236 else if (ptr_mode == DImode)
16238 /* It's too cumbersome to create the full 64-bit address, so let's
16244 1: l[wd] $25, target_function_offset - 12($31)
16245 l[wd] $static_chain, static_chain_offset - 12($31)
16249 where 12 is the offset of "1:" from the start of the code block. */
16250 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16251 trampoline[i++] = OP (MIPS_BAL (1));
16252 trampoline[i++] = OP (MIPS_NOP);
16253 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16254 target_function_offset - 12,
16255 RETURN_ADDR_REGNUM));
16256 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16257 static_chain_offset - 12,
16258 RETURN_ADDR_REGNUM));
16259 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16260 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16264 /* If the target has load delays, emit:
16266 lui $1, %hi(end_addr)
16267 lw $25, %lo(end_addr + ...)($1)
16268 lw $static_chain, %lo(end_addr + ...)($1)
16274 lui $1, %hi(end_addr)
16275 lw $25, %lo(end_addr + ...)($1)
16277 lw $static_chain, %lo(end_addr + ...)($1). */
16279 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16280 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16281 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16282 NULL, false, OPTAB_WIDEN);
16283 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16284 NULL, false, OPTAB_WIDEN);
16285 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16287 /* Emit the LUI. */
16288 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16289 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16290 NULL, false, OPTAB_WIDEN);
16292 /* Emit the load of the target function. */
16293 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16294 target_function_offset - end_addr_offset,
16296 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16297 NULL, false, OPTAB_WIDEN);
16299 /* Emit the JR here, if we can. */
16300 if (!ISA_HAS_LOAD_DELAY)
16301 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16303 /* Emit the load of the static chain register. */
16304 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16305 static_chain_offset - end_addr_offset,
16307 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16308 NULL, false, OPTAB_WIDEN);
16310 /* Emit the JR, if we couldn't above. */
16311 if (ISA_HAS_LOAD_DELAY)
16313 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16314 trampoline[i++] = OP (MIPS_NOP);
16320 /* Copy the trampoline code. Leave any padding uninitialized. */
16321 for (j = 0; j < i; j++)
16323 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16324 mips_emit_move (mem, trampoline[j]);
16327 /* Set up the static chain pointer field. */
16328 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16329 mips_emit_move (mem, chain_value);
16331 /* Set up the target function field. */
16332 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16333 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16335 /* Flush the code part of the trampoline. */
16336 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16337 emit_insn (gen_clear_cache (addr, end_addr));
16340 /* Implement FUNCTION_PROFILER. */
16342 void mips_function_profiler (FILE *file)
16345 sorry ("mips16 function profiling");
16346 if (TARGET_LONG_CALLS)
16348 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16349 if (Pmode == DImode)
16350 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16352 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16354 mips_push_asm_switch (&mips_noat);
16355 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16356 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16357 /* _mcount treats $2 as the static chain register. */
16358 if (cfun->static_chain_decl != NULL)
16359 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16360 reg_names[STATIC_CHAIN_REGNUM]);
16361 if (TARGET_MCOUNT_RA_ADDRESS)
16363 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16364 ra save location. */
16365 if (cfun->machine->frame.ra_fp_offset == 0)
16366 /* ra not saved, pass zero. */
16367 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16369 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16370 Pmode == DImode ? "dla" : "la", reg_names[12],
16371 cfun->machine->frame.ra_fp_offset,
16372 reg_names[STACK_POINTER_REGNUM]);
16374 if (!TARGET_NEWABI)
16376 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16377 TARGET_64BIT ? "dsubu" : "subu",
16378 reg_names[STACK_POINTER_REGNUM],
16379 reg_names[STACK_POINTER_REGNUM],
16380 Pmode == DImode ? 16 : 8);
16382 if (TARGET_LONG_CALLS)
16383 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16385 fprintf (file, "\tjal\t_mcount\n");
16386 mips_pop_asm_switch (&mips_noat);
16387 /* _mcount treats $2 as the static chain register. */
16388 if (cfun->static_chain_decl != NULL)
16389 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16393 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16394 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16395 when TARGET_LOONGSON_2EF is true. */
16397 static unsigned HOST_WIDE_INT
16398 mips_shift_truncation_mask (enum machine_mode mode)
16400 if (TARGET_LOONGSON_2EF && VECTOR_MODE_P (mode))
16403 return GET_MODE_BITSIZE (mode) - 1;
16407 /* Initialize the GCC target structure. */
16408 #undef TARGET_ASM_ALIGNED_HI_OP
16409 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16410 #undef TARGET_ASM_ALIGNED_SI_OP
16411 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16412 #undef TARGET_ASM_ALIGNED_DI_OP
16413 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16415 #undef TARGET_OPTION_OVERRIDE
16416 #define TARGET_OPTION_OVERRIDE mips_option_override
16417 #undef TARGET_OPTION_OPTIMIZATION_TABLE
16418 #define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table
16420 #undef TARGET_LEGITIMIZE_ADDRESS
16421 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16423 #undef TARGET_ASM_FUNCTION_PROLOGUE
16424 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16425 #undef TARGET_ASM_FUNCTION_EPILOGUE
16426 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16427 #undef TARGET_ASM_SELECT_RTX_SECTION
16428 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16429 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16430 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16432 #undef TARGET_SCHED_INIT
16433 #define TARGET_SCHED_INIT mips_sched_init
16434 #undef TARGET_SCHED_REORDER
16435 #define TARGET_SCHED_REORDER mips_sched_reorder
16436 #undef TARGET_SCHED_REORDER2
16437 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
16438 #undef TARGET_SCHED_VARIABLE_ISSUE
16439 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16440 #undef TARGET_SCHED_ADJUST_COST
16441 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16442 #undef TARGET_SCHED_ISSUE_RATE
16443 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16444 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16445 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16446 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16447 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16448 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16449 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16450 mips_multipass_dfa_lookahead
16451 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16452 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16453 mips_small_register_classes_for_mode_p
16455 #undef TARGET_DEFAULT_TARGET_FLAGS
16456 #define TARGET_DEFAULT_TARGET_FLAGS \
16458 | TARGET_CPU_DEFAULT \
16459 | TARGET_ENDIAN_DEFAULT \
16460 | TARGET_FP_EXCEPTIONS_DEFAULT \
16461 | MASK_CHECK_ZERO_DIV \
16463 #undef TARGET_HANDLE_OPTION
16464 #define TARGET_HANDLE_OPTION mips_handle_option
16466 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16467 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16469 #undef TARGET_INSERT_ATTRIBUTES
16470 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16471 #undef TARGET_MERGE_DECL_ATTRIBUTES
16472 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16473 #undef TARGET_SET_CURRENT_FUNCTION
16474 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16476 #undef TARGET_VALID_POINTER_MODE
16477 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16478 #undef TARGET_REGISTER_MOVE_COST
16479 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16480 #undef TARGET_MEMORY_MOVE_COST
16481 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16482 #undef TARGET_RTX_COSTS
16483 #define TARGET_RTX_COSTS mips_rtx_costs
16484 #undef TARGET_ADDRESS_COST
16485 #define TARGET_ADDRESS_COST mips_address_cost
16487 #undef TARGET_IN_SMALL_DATA_P
16488 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16490 #undef TARGET_MACHINE_DEPENDENT_REORG
16491 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16493 #undef TARGET_ASM_FILE_START
16494 #define TARGET_ASM_FILE_START mips_file_start
16495 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16496 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16498 #undef TARGET_INIT_LIBFUNCS
16499 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16501 #undef TARGET_BUILD_BUILTIN_VA_LIST
16502 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16503 #undef TARGET_EXPAND_BUILTIN_VA_START
16504 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16505 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16506 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16508 #undef TARGET_PROMOTE_FUNCTION_MODE
16509 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16510 #undef TARGET_PROMOTE_PROTOTYPES
16511 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16513 #undef TARGET_RETURN_IN_MEMORY
16514 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16515 #undef TARGET_RETURN_IN_MSB
16516 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16518 #undef TARGET_ASM_OUTPUT_MI_THUNK
16519 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16520 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16521 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16523 #undef TARGET_PRINT_OPERAND
16524 #define TARGET_PRINT_OPERAND mips_print_operand
16525 #undef TARGET_PRINT_OPERAND_ADDRESS
16526 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16527 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16528 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16530 #undef TARGET_SETUP_INCOMING_VARARGS
16531 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16532 #undef TARGET_STRICT_ARGUMENT_NAMING
16533 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16534 #undef TARGET_MUST_PASS_IN_STACK
16535 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16536 #undef TARGET_PASS_BY_REFERENCE
16537 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16538 #undef TARGET_CALLEE_COPIES
16539 #define TARGET_CALLEE_COPIES mips_callee_copies
16540 #undef TARGET_ARG_PARTIAL_BYTES
16541 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16542 #undef TARGET_FUNCTION_ARG
16543 #define TARGET_FUNCTION_ARG mips_function_arg
16544 #undef TARGET_FUNCTION_ARG_ADVANCE
16545 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16546 #undef TARGET_FUNCTION_ARG_BOUNDARY
16547 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
16549 #undef TARGET_MODE_REP_EXTENDED
16550 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16552 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16553 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16555 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16556 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16558 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16559 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
16561 #undef TARGET_INIT_BUILTINS
16562 #define TARGET_INIT_BUILTINS mips_init_builtins
16563 #undef TARGET_BUILTIN_DECL
16564 #define TARGET_BUILTIN_DECL mips_builtin_decl
16565 #undef TARGET_EXPAND_BUILTIN
16566 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16568 #undef TARGET_HAVE_TLS
16569 #define TARGET_HAVE_TLS HAVE_AS_TLS
16571 #undef TARGET_CANNOT_FORCE_CONST_MEM
16572 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16574 #undef TARGET_ENCODE_SECTION_INFO
16575 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16577 #undef TARGET_ATTRIBUTE_TABLE
16578 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16579 /* All our function attributes are related to how out-of-line copies should
16580 be compiled or called. They don't in themselves prevent inlining. */
16581 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16582 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16584 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16585 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16587 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16588 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16589 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16590 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16592 #undef TARGET_COMP_TYPE_ATTRIBUTES
16593 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16595 #ifdef HAVE_AS_DTPRELWORD
16596 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16597 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16599 #undef TARGET_DWARF_REGISTER_SPAN
16600 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16602 #undef TARGET_IRA_COVER_CLASSES
16603 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
16605 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16606 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16608 #undef TARGET_LEGITIMATE_ADDRESS_P
16609 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16611 #undef TARGET_FRAME_POINTER_REQUIRED
16612 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16614 #undef TARGET_CAN_ELIMINATE
16615 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16617 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16618 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
16620 #undef TARGET_TRAMPOLINE_INIT
16621 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16623 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16624 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16626 #undef TARGET_SHIFT_TRUNCATION_MASK
16627 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
16629 struct gcc_target targetm = TARGET_INITIALIZER;
16631 #include "gt-mips.h"