1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-attr.h"
51 #include "target-def.h"
52 #include "integrate.h"
53 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
58 #include "diagnostic.h"
59 #include "target-globals.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
83 up to 0x7f8 bytes and can usually save or restore all the registers
84 that we need to save or restore. (Note that we can only use these
85 instructions for o32, for which the stack alignment is 8 bytes.)
87 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
88 RESTORE are not available. We can then use unextended instructions
89 to save and restore registers, and to allocate and deallocate the top
91 #define MIPS_MAX_FIRST_STACK_STEP \
92 (!TARGET_MIPS16 ? 0x7ff0 \
93 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
94 : TARGET_64BIT ? 0x100 : 0x400)
96 /* True if INSN is a mips.md pattern or asm statement. */
97 #define USEFUL_INSN_P(INSN) \
98 (NONDEBUG_INSN_P (INSN) \
99 && GET_CODE (PATTERN (INSN)) != USE \
100 && GET_CODE (PATTERN (INSN)) != CLOBBER \
101 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
102 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104 /* If INSN is a delayed branch sequence, return the first instruction
105 in the sequence, otherwise return INSN itself. */
106 #define SEQ_BEGIN(INSN) \
107 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
108 ? XVECEXP (PATTERN (INSN), 0, 0) \
111 /* Likewise for the last instruction in a delayed branch sequence. */
112 #define SEQ_END(INSN) \
113 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
114 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
117 /* Execute the following loop body with SUBINSN set to each instruction
118 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
119 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
120 for ((SUBINSN) = SEQ_BEGIN (INSN); \
121 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
122 (SUBINSN) = NEXT_INSN (SUBINSN))
124 /* True if bit BIT is set in VALUE. */
125 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127 /* Return the opcode for a ptr_mode load of the form:
129 l[wd] DEST, OFFSET(BASE). */
130 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
131 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
136 /* Return the opcode to move register SRC into register DEST. */
137 #define MIPS_MOVE(DEST, SRC) \
138 ((TARGET_64BIT ? 0x2d : 0x21) \
142 /* Return the opcode for:
145 #define MIPS_LUI(DEST, VALUE) \
146 ((0xf << 26) | ((DEST) << 16) | (VALUE))
148 /* Return the opcode to jump to register DEST. */
149 #define MIPS_JR(DEST) \
150 (((DEST) << 21) | 0x8)
152 /* Return the opcode for:
154 bal . + (1 + OFFSET) * 4. */
155 #define MIPS_BAL(OFFSET) \
156 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
158 /* Return the usual opcode for a nop. */
161 /* Classifies an address.
164 A natural register + offset address. The register satisfies
165 mips_valid_base_register_p and the offset is a const_arith_operand.
168 A LO_SUM rtx. The first operand is a valid base register and
169 the second operand is a symbolic address.
172 A signed 16-bit constant address.
175 A constant symbolic address. */
176 enum mips_address_type {
183 /* Enumerates the setting of the -mr10k-cache-barrier option. */
184 enum mips_r10k_cache_barrier_setting {
185 R10K_CACHE_BARRIER_NONE,
186 R10K_CACHE_BARRIER_STORE,
187 R10K_CACHE_BARRIER_LOAD_STORE
190 /* Macros to create an enumeration identifier for a function prototype. */
191 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
192 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
193 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
194 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
196 /* Classifies the prototype of a built-in function. */
197 enum mips_function_type {
198 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
199 #include "config/mips/mips-ftypes.def"
200 #undef DEF_MIPS_FTYPE
204 /* Specifies how a built-in function should be converted into rtl. */
205 enum mips_builtin_type {
206 /* The function corresponds directly to an .md pattern. The return
207 value is mapped to operand 0 and the arguments are mapped to
208 operands 1 and above. */
211 /* The function corresponds directly to an .md pattern. There is no return
212 value and the arguments are mapped to operands 0 and above. */
213 MIPS_BUILTIN_DIRECT_NO_TARGET,
215 /* The function corresponds to a comparison instruction followed by
216 a mips_cond_move_tf_ps pattern. The first two arguments are the
217 values to compare and the second two arguments are the vector
218 operands for the movt.ps or movf.ps instruction (in assembly order). */
222 /* The function corresponds to a V2SF comparison instruction. Operand 0
223 of this instruction is the result of the comparison, which has mode
224 CCV2 or CCV4. The function arguments are mapped to operands 1 and
225 above. The function's return value is an SImode boolean that is
226 true under the following conditions:
228 MIPS_BUILTIN_CMP_ANY: one of the registers is true
229 MIPS_BUILTIN_CMP_ALL: all of the registers are true
230 MIPS_BUILTIN_CMP_LOWER: the first register is true
231 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
232 MIPS_BUILTIN_CMP_ANY,
233 MIPS_BUILTIN_CMP_ALL,
234 MIPS_BUILTIN_CMP_UPPER,
235 MIPS_BUILTIN_CMP_LOWER,
237 /* As above, but the instruction only sets a single $fcc register. */
238 MIPS_BUILTIN_CMP_SINGLE,
240 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
241 MIPS_BUILTIN_BPOSGE32
244 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
245 #define MIPS_FP_CONDITIONS(MACRO) \
263 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
264 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
265 enum mips_fp_condition {
266 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
269 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
270 #define STRINGIFY(X) #X
271 static const char *const mips_fp_conditions[] = {
272 MIPS_FP_CONDITIONS (STRINGIFY)
275 /* Information about a function's frame layout. */
276 struct GTY(()) mips_frame_info {
277 /* The size of the frame in bytes. */
278 HOST_WIDE_INT total_size;
280 /* The number of bytes allocated to variables. */
281 HOST_WIDE_INT var_size;
283 /* The number of bytes allocated to outgoing function arguments. */
284 HOST_WIDE_INT args_size;
286 /* The number of bytes allocated to the .cprestore slot, or 0 if there
288 HOST_WIDE_INT cprestore_size;
290 /* Bit X is set if the function saves or restores GPR X. */
293 /* Likewise FPR X. */
296 /* Likewise doubleword accumulator X ($acX). */
297 unsigned int acc_mask;
299 /* The number of GPRs, FPRs, doubleword accumulators and COP0
303 unsigned int num_acc;
304 unsigned int num_cop0_regs;
306 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
307 save slots from the top of the frame, or zero if no such slots are
309 HOST_WIDE_INT gp_save_offset;
310 HOST_WIDE_INT fp_save_offset;
311 HOST_WIDE_INT acc_save_offset;
312 HOST_WIDE_INT cop0_save_offset;
314 /* Likewise, but giving offsets from the bottom of the frame. */
315 HOST_WIDE_INT gp_sp_offset;
316 HOST_WIDE_INT fp_sp_offset;
317 HOST_WIDE_INT acc_sp_offset;
318 HOST_WIDE_INT cop0_sp_offset;
320 /* Similar, but the value passed to _mcount. */
321 HOST_WIDE_INT ra_fp_offset;
323 /* The offset of arg_pointer_rtx from the bottom of the frame. */
324 HOST_WIDE_INT arg_pointer_offset;
326 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
327 HOST_WIDE_INT hard_frame_pointer_offset;
330 struct GTY(()) machine_function {
331 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
332 rtx mips16_gp_pseudo_rtx;
334 /* The number of extra stack bytes taken up by register varargs.
335 This area is allocated by the callee at the very top of the frame. */
338 /* The current frame information, calculated by mips_compute_frame_info. */
339 struct mips_frame_info frame;
341 /* The register to use as the function's global pointer, or INVALID_REGNUM
342 if the function doesn't need one. */
343 unsigned int global_pointer;
345 /* How many instructions it takes to load a label into $AT, or 0 if
346 this property hasn't yet been calculated. */
347 unsigned int load_label_num_insns;
349 /* True if mips_adjust_insn_length should ignore an instruction's
351 bool ignore_hazard_length_p;
353 /* True if the whole function is suitable for .set noreorder and
355 bool all_noreorder_p;
357 /* True if the function has "inflexible" and "flexible" references
358 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
359 and mips_cfun_has_flexible_gp_ref_p for details. */
360 bool has_inflexible_gp_insn_p;
361 bool has_flexible_gp_insn_p;
363 /* True if the function's prologue must load the global pointer
364 value into pic_offset_table_rtx and store the same value in
365 the function's cprestore slot (if any). Even if this value
366 is currently false, we may decide to set it to true later;
367 see mips_must_initialize_gp_p () for details. */
368 bool must_initialize_gp_p;
370 /* True if the current function must restore $gp after any potential
371 clobber. This value is only meaningful during the first post-epilogue
372 split_insns pass; see mips_must_initialize_gp_p () for details. */
373 bool must_restore_gp_when_clobbered_p;
375 /* True if this is an interrupt handler. */
376 bool interrupt_handler_p;
378 /* True if this is an interrupt handler that uses shadow registers. */
379 bool use_shadow_register_set_p;
381 /* True if this is an interrupt handler that should keep interrupts
383 bool keep_interrupts_masked_p;
385 /* True if this is an interrupt handler that should use DERET
387 bool use_debug_exception_return_p;
390 /* Information about a single argument. */
391 struct mips_arg_info {
392 /* True if the argument is passed in a floating-point register, or
393 would have been if we hadn't run out of registers. */
396 /* The number of words passed in registers, rounded up. */
397 unsigned int reg_words;
399 /* For EABI, the offset of the first register from GP_ARG_FIRST or
400 FP_ARG_FIRST. For other ABIs, the offset of the first register from
401 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
402 comment for details).
404 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
406 unsigned int reg_offset;
408 /* The number of words that must be passed on the stack, rounded up. */
409 unsigned int stack_words;
411 /* The offset from the start of the stack overflow area of the argument's
412 first stack word. Only meaningful when STACK_WORDS is nonzero. */
413 unsigned int stack_offset;
416 /* Information about an address described by mips_address_type.
422 REG is the base register and OFFSET is the constant offset.
425 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
426 is the type of symbol it references.
429 SYMBOL_TYPE is the type of symbol that the address references. */
430 struct mips_address_info {
431 enum mips_address_type type;
434 enum mips_symbol_type symbol_type;
437 /* One stage in a constant building sequence. These sequences have
441 A = A CODE[1] VALUE[1]
442 A = A CODE[2] VALUE[2]
445 where A is an accumulator, each CODE[i] is a binary rtl operation
446 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
447 struct mips_integer_op {
449 unsigned HOST_WIDE_INT value;
452 /* The largest number of operations needed to load an integer constant.
453 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
454 When the lowest bit is clear, we can try, but reject a sequence with
455 an extra SLL at the end. */
456 #define MIPS_MAX_INTEGER_OPS 7
458 /* Information about a MIPS16e SAVE or RESTORE instruction. */
459 struct mips16e_save_restore_info {
460 /* The number of argument registers saved by a SAVE instruction.
461 0 for RESTORE instructions. */
464 /* Bit X is set if the instruction saves or restores GPR X. */
467 /* The total number of bytes to allocate. */
471 /* Costs of various operations on the different architectures. */
473 struct mips_rtx_cost_data
475 unsigned short fp_add;
476 unsigned short fp_mult_sf;
477 unsigned short fp_mult_df;
478 unsigned short fp_div_sf;
479 unsigned short fp_div_df;
480 unsigned short int_mult_si;
481 unsigned short int_mult_di;
482 unsigned short int_div_si;
483 unsigned short int_div_di;
484 unsigned short branch_cost;
485 unsigned short memory_latency;
488 /* Global variables for machine-dependent things. */
490 /* The -G setting, or the configuration's default small-data limit if
491 no -G option is given. */
492 static unsigned int mips_small_data_threshold;
494 /* The number of file directives written by mips_output_filename. */
495 int num_source_filenames;
497 /* The name that appeared in the last .file directive written by
498 mips_output_filename, or "" if mips_output_filename hasn't
499 written anything yet. */
500 const char *current_function_file = "";
502 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
505 /* Arrays that map GCC register numbers to debugger register numbers. */
506 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
507 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
509 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
510 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
511 struct mips_asm_switch mips_nomacro = { "macro", 0 };
512 struct mips_asm_switch mips_noat = { "at", 0 };
514 /* True if we're writing out a branch-likely instruction rather than a
516 static bool mips_branch_likely;
518 /* The current instruction-set architecture. */
519 enum processor mips_arch;
520 const struct mips_cpu_info *mips_arch_info;
522 /* The processor that we should tune the code for. */
523 enum processor mips_tune;
524 const struct mips_cpu_info *mips_tune_info;
526 /* The ISA level associated with mips_arch. */
529 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
530 static const struct mips_cpu_info *mips_isa_option_info;
532 /* Which ABI to use. */
533 int mips_abi = MIPS_ABI_DEFAULT;
535 /* Which cost information to use. */
536 static const struct mips_rtx_cost_data *mips_cost;
538 /* The ambient target flags, excluding MASK_MIPS16. */
539 static int mips_base_target_flags;
541 /* True if MIPS16 is the default mode. */
542 bool mips_base_mips16;
544 /* The ambient values of other global variables. */
545 static int mips_base_schedule_insns; /* flag_schedule_insns */
546 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
547 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
548 static int mips_base_align_loops; /* align_loops */
549 static int mips_base_align_jumps; /* align_jumps */
550 static int mips_base_align_functions; /* align_functions */
552 /* The -mcode-readable setting. */
553 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
555 /* The -mr10k-cache-barrier setting. */
556 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
558 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
559 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
561 /* Index C is true if character C is a valid PRINT_OPERAND punctation
563 static bool mips_print_operand_punct[256];
565 static GTY (()) int mips_output_filename_first_time = 1;
567 /* mips_split_p[X] is true if symbols of type X can be split by
568 mips_split_symbol. */
569 bool mips_split_p[NUM_SYMBOL_TYPES];
571 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
572 can be split by mips_split_symbol. */
573 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
575 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
576 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
577 if they are matched by a special .md file pattern. */
578 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
580 /* Likewise for HIGHs. */
581 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
583 /* Target state for MIPS16. */
584 struct target_globals *mips16_globals;
586 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
587 and returned from mips_sched_reorder2. */
588 static int cached_can_issue_more;
590 /* Index R is the smallest register class that contains register R. */
591 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
592 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
593 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
594 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
595 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
596 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
597 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
598 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
599 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
600 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
601 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
602 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
603 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
604 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
609 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
610 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
611 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
612 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
613 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
614 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
615 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
616 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
621 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
622 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
623 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
624 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
629 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
630 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
631 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
632 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
637 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
638 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
641 /* The value of TARGET_ATTRIBUTE_TABLE. */
642 static const struct attribute_spec mips_attribute_table[] = {
643 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
644 { "long_call", 0, 0, false, true, true, NULL },
645 { "far", 0, 0, false, true, true, NULL },
646 { "near", 0, 0, false, true, true, NULL },
647 /* We would really like to treat "mips16" and "nomips16" as type
648 attributes, but GCC doesn't provide the hooks we need to support
649 the right conversion rules. As declaration attributes, they affect
650 code generation but don't carry other semantics. */
651 { "mips16", 0, 0, true, false, false, NULL },
652 { "nomips16", 0, 0, true, false, false, NULL },
653 /* Allow functions to be specified as interrupt handlers */
654 { "interrupt", 0, 0, false, true, true, NULL },
655 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
656 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
657 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
658 { NULL, 0, 0, false, false, false, NULL }
661 /* A table describing all the processors GCC knows about. Names are
662 matched in the order listed. The first mention of an ISA level is
663 taken as the canonical name for that ISA.
665 To ease comparison, please keep this table in the same order
666 as GAS's mips_cpu_info_table. Please also make sure that
667 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
668 options correctly. */
669 static const struct mips_cpu_info mips_cpu_info_table[] = {
670 /* Entries for generic ISAs. */
671 { "mips1", PROCESSOR_R3000, 1, 0 },
672 { "mips2", PROCESSOR_R6000, 2, 0 },
673 { "mips3", PROCESSOR_R4000, 3, 0 },
674 { "mips4", PROCESSOR_R8000, 4, 0 },
675 /* Prefer not to use branch-likely instructions for generic MIPS32rX
676 and MIPS64rX code. The instructions were officially deprecated
677 in revisions 2 and earlier, but revision 3 is likely to downgrade
678 that to a recommendation to avoid the instructions in code that
679 isn't tuned to a specific processor. */
680 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
681 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
682 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
683 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
684 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
686 /* MIPS I processors. */
687 { "r3000", PROCESSOR_R3000, 1, 0 },
688 { "r2000", PROCESSOR_R3000, 1, 0 },
689 { "r3900", PROCESSOR_R3900, 1, 0 },
691 /* MIPS II processors. */
692 { "r6000", PROCESSOR_R6000, 2, 0 },
694 /* MIPS III processors. */
695 { "r4000", PROCESSOR_R4000, 3, 0 },
696 { "vr4100", PROCESSOR_R4100, 3, 0 },
697 { "vr4111", PROCESSOR_R4111, 3, 0 },
698 { "vr4120", PROCESSOR_R4120, 3, 0 },
699 { "vr4130", PROCESSOR_R4130, 3, 0 },
700 { "vr4300", PROCESSOR_R4300, 3, 0 },
701 { "r4400", PROCESSOR_R4000, 3, 0 },
702 { "r4600", PROCESSOR_R4600, 3, 0 },
703 { "orion", PROCESSOR_R4600, 3, 0 },
704 { "r4650", PROCESSOR_R4650, 3, 0 },
705 /* ST Loongson 2E/2F processors. */
706 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
707 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
709 /* MIPS IV processors. */
710 { "r8000", PROCESSOR_R8000, 4, 0 },
711 { "r10000", PROCESSOR_R10000, 4, 0 },
712 { "r12000", PROCESSOR_R10000, 4, 0 },
713 { "r14000", PROCESSOR_R10000, 4, 0 },
714 { "r16000", PROCESSOR_R10000, 4, 0 },
715 { "vr5000", PROCESSOR_R5000, 4, 0 },
716 { "vr5400", PROCESSOR_R5400, 4, 0 },
717 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
718 { "rm7000", PROCESSOR_R7000, 4, 0 },
719 { "rm9000", PROCESSOR_R9000, 4, 0 },
721 /* MIPS32 processors. */
722 { "4kc", PROCESSOR_4KC, 32, 0 },
723 { "4km", PROCESSOR_4KC, 32, 0 },
724 { "4kp", PROCESSOR_4KP, 32, 0 },
725 { "4ksc", PROCESSOR_4KC, 32, 0 },
727 /* MIPS32 Release 2 processors. */
728 { "m4k", PROCESSOR_M4K, 33, 0 },
729 { "4kec", PROCESSOR_4KC, 33, 0 },
730 { "4kem", PROCESSOR_4KC, 33, 0 },
731 { "4kep", PROCESSOR_4KP, 33, 0 },
732 { "4ksd", PROCESSOR_4KC, 33, 0 },
734 { "24kc", PROCESSOR_24KC, 33, 0 },
735 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
736 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
737 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
738 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
739 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
741 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
742 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
743 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
744 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
745 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
746 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
748 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
749 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
750 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
751 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
752 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
753 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
755 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
756 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
757 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
758 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
759 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
760 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
761 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
763 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
764 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
765 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
766 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
768 /* MIPS64 processors. */
769 { "5kc", PROCESSOR_5KC, 64, 0 },
770 { "5kf", PROCESSOR_5KF, 64, 0 },
771 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
772 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
773 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
774 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
775 { "xlr", PROCESSOR_XLR, 64, 0 },
776 { "loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY },
778 /* MIPS64 Release 2 processors. */
779 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
782 /* Default costs. If these are used for a processor we should look
783 up the actual costs. */
784 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
785 COSTS_N_INSNS (7), /* fp_mult_sf */ \
786 COSTS_N_INSNS (8), /* fp_mult_df */ \
787 COSTS_N_INSNS (23), /* fp_div_sf */ \
788 COSTS_N_INSNS (36), /* fp_div_df */ \
789 COSTS_N_INSNS (10), /* int_mult_si */ \
790 COSTS_N_INSNS (10), /* int_mult_di */ \
791 COSTS_N_INSNS (69), /* int_div_si */ \
792 COSTS_N_INSNS (69), /* int_div_di */ \
793 2, /* branch_cost */ \
794 4 /* memory_latency */
796 /* Floating-point costs for processors without an FPU. Just assume that
797 all floating-point libcalls are very expensive. */
798 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
799 COSTS_N_INSNS (256), /* fp_mult_sf */ \
800 COSTS_N_INSNS (256), /* fp_mult_df */ \
801 COSTS_N_INSNS (256), /* fp_div_sf */ \
802 COSTS_N_INSNS (256) /* fp_div_df */
804 /* Costs to use when optimizing for size. */
805 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
806 COSTS_N_INSNS (1), /* fp_add */
807 COSTS_N_INSNS (1), /* fp_mult_sf */
808 COSTS_N_INSNS (1), /* fp_mult_df */
809 COSTS_N_INSNS (1), /* fp_div_sf */
810 COSTS_N_INSNS (1), /* fp_div_df */
811 COSTS_N_INSNS (1), /* int_mult_si */
812 COSTS_N_INSNS (1), /* int_mult_di */
813 COSTS_N_INSNS (1), /* int_div_si */
814 COSTS_N_INSNS (1), /* int_div_di */
816 4 /* memory_latency */
819 /* Costs to use when optimizing for speed, indexed by processor. */
820 static const struct mips_rtx_cost_data
821 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
823 COSTS_N_INSNS (2), /* fp_add */
824 COSTS_N_INSNS (4), /* fp_mult_sf */
825 COSTS_N_INSNS (5), /* fp_mult_df */
826 COSTS_N_INSNS (12), /* fp_div_sf */
827 COSTS_N_INSNS (19), /* fp_div_df */
828 COSTS_N_INSNS (12), /* int_mult_si */
829 COSTS_N_INSNS (12), /* int_mult_di */
830 COSTS_N_INSNS (35), /* int_div_si */
831 COSTS_N_INSNS (35), /* int_div_di */
833 4 /* memory_latency */
837 COSTS_N_INSNS (6), /* int_mult_si */
838 COSTS_N_INSNS (6), /* int_mult_di */
839 COSTS_N_INSNS (36), /* int_div_si */
840 COSTS_N_INSNS (36), /* int_div_di */
842 4 /* memory_latency */
846 COSTS_N_INSNS (36), /* int_mult_si */
847 COSTS_N_INSNS (36), /* int_mult_di */
848 COSTS_N_INSNS (37), /* int_div_si */
849 COSTS_N_INSNS (37), /* int_div_di */
851 4 /* memory_latency */
855 COSTS_N_INSNS (4), /* int_mult_si */
856 COSTS_N_INSNS (11), /* int_mult_di */
857 COSTS_N_INSNS (36), /* int_div_si */
858 COSTS_N_INSNS (68), /* int_div_di */
860 4 /* memory_latency */
863 COSTS_N_INSNS (4), /* fp_add */
864 COSTS_N_INSNS (4), /* fp_mult_sf */
865 COSTS_N_INSNS (5), /* fp_mult_df */
866 COSTS_N_INSNS (17), /* fp_div_sf */
867 COSTS_N_INSNS (32), /* fp_div_df */
868 COSTS_N_INSNS (4), /* int_mult_si */
869 COSTS_N_INSNS (11), /* int_mult_di */
870 COSTS_N_INSNS (36), /* int_div_si */
871 COSTS_N_INSNS (68), /* int_div_di */
873 4 /* memory_latency */
876 COSTS_N_INSNS (4), /* fp_add */
877 COSTS_N_INSNS (4), /* fp_mult_sf */
878 COSTS_N_INSNS (5), /* fp_mult_df */
879 COSTS_N_INSNS (17), /* fp_div_sf */
880 COSTS_N_INSNS (32), /* fp_div_df */
881 COSTS_N_INSNS (4), /* int_mult_si */
882 COSTS_N_INSNS (7), /* int_mult_di */
883 COSTS_N_INSNS (42), /* int_div_si */
884 COSTS_N_INSNS (72), /* int_div_di */
886 4 /* memory_latency */
890 COSTS_N_INSNS (5), /* int_mult_si */
891 COSTS_N_INSNS (5), /* int_mult_di */
892 COSTS_N_INSNS (41), /* int_div_si */
893 COSTS_N_INSNS (41), /* int_div_di */
895 4 /* memory_latency */
898 COSTS_N_INSNS (8), /* fp_add */
899 COSTS_N_INSNS (8), /* fp_mult_sf */
900 COSTS_N_INSNS (10), /* fp_mult_df */
901 COSTS_N_INSNS (34), /* fp_div_sf */
902 COSTS_N_INSNS (64), /* fp_div_df */
903 COSTS_N_INSNS (5), /* int_mult_si */
904 COSTS_N_INSNS (5), /* int_mult_di */
905 COSTS_N_INSNS (41), /* int_div_si */
906 COSTS_N_INSNS (41), /* int_div_di */
908 4 /* memory_latency */
911 COSTS_N_INSNS (4), /* fp_add */
912 COSTS_N_INSNS (4), /* fp_mult_sf */
913 COSTS_N_INSNS (5), /* fp_mult_df */
914 COSTS_N_INSNS (17), /* fp_div_sf */
915 COSTS_N_INSNS (32), /* fp_div_df */
916 COSTS_N_INSNS (5), /* int_mult_si */
917 COSTS_N_INSNS (5), /* int_mult_di */
918 COSTS_N_INSNS (41), /* int_div_si */
919 COSTS_N_INSNS (41), /* int_div_di */
921 4 /* memory_latency */
925 COSTS_N_INSNS (5), /* int_mult_si */
926 COSTS_N_INSNS (5), /* int_mult_di */
927 COSTS_N_INSNS (41), /* int_div_si */
928 COSTS_N_INSNS (41), /* int_div_di */
930 4 /* memory_latency */
933 COSTS_N_INSNS (8), /* fp_add */
934 COSTS_N_INSNS (8), /* fp_mult_sf */
935 COSTS_N_INSNS (10), /* fp_mult_df */
936 COSTS_N_INSNS (34), /* fp_div_sf */
937 COSTS_N_INSNS (64), /* fp_div_df */
938 COSTS_N_INSNS (5), /* int_mult_si */
939 COSTS_N_INSNS (5), /* int_mult_di */
940 COSTS_N_INSNS (41), /* int_div_si */
941 COSTS_N_INSNS (41), /* int_div_di */
943 4 /* memory_latency */
946 COSTS_N_INSNS (4), /* fp_add */
947 COSTS_N_INSNS (4), /* fp_mult_sf */
948 COSTS_N_INSNS (5), /* fp_mult_df */
949 COSTS_N_INSNS (17), /* fp_div_sf */
950 COSTS_N_INSNS (32), /* fp_div_df */
951 COSTS_N_INSNS (5), /* int_mult_si */
952 COSTS_N_INSNS (5), /* int_mult_di */
953 COSTS_N_INSNS (41), /* int_div_si */
954 COSTS_N_INSNS (41), /* int_div_di */
956 4 /* memory_latency */
959 COSTS_N_INSNS (6), /* fp_add */
960 COSTS_N_INSNS (6), /* fp_mult_sf */
961 COSTS_N_INSNS (7), /* fp_mult_df */
962 COSTS_N_INSNS (25), /* fp_div_sf */
963 COSTS_N_INSNS (48), /* fp_div_df */
964 COSTS_N_INSNS (5), /* int_mult_si */
965 COSTS_N_INSNS (5), /* int_mult_di */
966 COSTS_N_INSNS (41), /* int_div_si */
967 COSTS_N_INSNS (41), /* int_div_di */
969 4 /* memory_latency */
986 COSTS_N_INSNS (5), /* int_mult_si */
987 COSTS_N_INSNS (5), /* int_mult_di */
988 COSTS_N_INSNS (72), /* int_div_si */
989 COSTS_N_INSNS (72), /* int_div_di */
991 4 /* memory_latency */
994 COSTS_N_INSNS (2), /* fp_add */
995 COSTS_N_INSNS (4), /* fp_mult_sf */
996 COSTS_N_INSNS (5), /* fp_mult_df */
997 COSTS_N_INSNS (12), /* fp_div_sf */
998 COSTS_N_INSNS (19), /* fp_div_df */
999 COSTS_N_INSNS (2), /* int_mult_si */
1000 COSTS_N_INSNS (2), /* int_mult_di */
1001 COSTS_N_INSNS (35), /* int_div_si */
1002 COSTS_N_INSNS (35), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1007 COSTS_N_INSNS (3), /* fp_add */
1008 COSTS_N_INSNS (5), /* fp_mult_sf */
1009 COSTS_N_INSNS (6), /* fp_mult_df */
1010 COSTS_N_INSNS (15), /* fp_div_sf */
1011 COSTS_N_INSNS (16), /* fp_div_df */
1012 COSTS_N_INSNS (17), /* int_mult_si */
1013 COSTS_N_INSNS (17), /* int_mult_di */
1014 COSTS_N_INSNS (38), /* int_div_si */
1015 COSTS_N_INSNS (38), /* int_div_di */
1016 2, /* branch_cost */
1017 6 /* memory_latency */
1020 COSTS_N_INSNS (6), /* fp_add */
1021 COSTS_N_INSNS (7), /* fp_mult_sf */
1022 COSTS_N_INSNS (8), /* fp_mult_df */
1023 COSTS_N_INSNS (23), /* fp_div_sf */
1024 COSTS_N_INSNS (36), /* fp_div_df */
1025 COSTS_N_INSNS (10), /* int_mult_si */
1026 COSTS_N_INSNS (10), /* int_mult_di */
1027 COSTS_N_INSNS (69), /* int_div_si */
1028 COSTS_N_INSNS (69), /* int_div_di */
1029 2, /* branch_cost */
1030 6 /* memory_latency */
1042 /* The only costs that appear to be updated here are
1043 integer multiplication. */
1045 COSTS_N_INSNS (4), /* int_mult_si */
1046 COSTS_N_INSNS (6), /* int_mult_di */
1047 COSTS_N_INSNS (69), /* int_div_si */
1048 COSTS_N_INSNS (69), /* int_div_di */
1049 1, /* branch_cost */
1050 4 /* memory_latency */
1062 COSTS_N_INSNS (6), /* fp_add */
1063 COSTS_N_INSNS (4), /* fp_mult_sf */
1064 COSTS_N_INSNS (5), /* fp_mult_df */
1065 COSTS_N_INSNS (23), /* fp_div_sf */
1066 COSTS_N_INSNS (36), /* fp_div_df */
1067 COSTS_N_INSNS (5), /* int_mult_si */
1068 COSTS_N_INSNS (5), /* int_mult_di */
1069 COSTS_N_INSNS (36), /* int_div_si */
1070 COSTS_N_INSNS (36), /* int_div_di */
1071 1, /* branch_cost */
1072 4 /* memory_latency */
1075 COSTS_N_INSNS (6), /* fp_add */
1076 COSTS_N_INSNS (5), /* fp_mult_sf */
1077 COSTS_N_INSNS (6), /* fp_mult_df */
1078 COSTS_N_INSNS (30), /* fp_div_sf */
1079 COSTS_N_INSNS (59), /* fp_div_df */
1080 COSTS_N_INSNS (3), /* int_mult_si */
1081 COSTS_N_INSNS (4), /* int_mult_di */
1082 COSTS_N_INSNS (42), /* int_div_si */
1083 COSTS_N_INSNS (74), /* int_div_di */
1084 1, /* branch_cost */
1085 4 /* memory_latency */
1088 COSTS_N_INSNS (6), /* fp_add */
1089 COSTS_N_INSNS (5), /* fp_mult_sf */
1090 COSTS_N_INSNS (6), /* fp_mult_df */
1091 COSTS_N_INSNS (30), /* fp_div_sf */
1092 COSTS_N_INSNS (59), /* fp_div_df */
1093 COSTS_N_INSNS (5), /* int_mult_si */
1094 COSTS_N_INSNS (9), /* int_mult_di */
1095 COSTS_N_INSNS (42), /* int_div_si */
1096 COSTS_N_INSNS (74), /* int_div_di */
1097 1, /* branch_cost */
1098 4 /* memory_latency */
1101 /* The only costs that are changed here are
1102 integer multiplication. */
1103 COSTS_N_INSNS (6), /* fp_add */
1104 COSTS_N_INSNS (7), /* fp_mult_sf */
1105 COSTS_N_INSNS (8), /* fp_mult_df */
1106 COSTS_N_INSNS (23), /* fp_div_sf */
1107 COSTS_N_INSNS (36), /* fp_div_df */
1108 COSTS_N_INSNS (5), /* int_mult_si */
1109 COSTS_N_INSNS (9), /* int_mult_di */
1110 COSTS_N_INSNS (69), /* int_div_si */
1111 COSTS_N_INSNS (69), /* int_div_di */
1112 1, /* branch_cost */
1113 4 /* memory_latency */
1119 /* The only costs that are changed here are
1120 integer multiplication. */
1121 COSTS_N_INSNS (6), /* fp_add */
1122 COSTS_N_INSNS (7), /* fp_mult_sf */
1123 COSTS_N_INSNS (8), /* fp_mult_df */
1124 COSTS_N_INSNS (23), /* fp_div_sf */
1125 COSTS_N_INSNS (36), /* fp_div_df */
1126 COSTS_N_INSNS (3), /* int_mult_si */
1127 COSTS_N_INSNS (8), /* int_mult_di */
1128 COSTS_N_INSNS (69), /* int_div_si */
1129 COSTS_N_INSNS (69), /* int_div_di */
1130 1, /* branch_cost */
1131 4 /* memory_latency */
1134 COSTS_N_INSNS (2), /* fp_add */
1135 COSTS_N_INSNS (2), /* fp_mult_sf */
1136 COSTS_N_INSNS (2), /* fp_mult_df */
1137 COSTS_N_INSNS (12), /* fp_div_sf */
1138 COSTS_N_INSNS (19), /* fp_div_df */
1139 COSTS_N_INSNS (5), /* int_mult_si */
1140 COSTS_N_INSNS (9), /* int_mult_di */
1141 COSTS_N_INSNS (34), /* int_div_si */
1142 COSTS_N_INSNS (66), /* int_div_di */
1143 1, /* branch_cost */
1144 4 /* memory_latency */
1147 /* These costs are the same as the SB-1A below. */
1148 COSTS_N_INSNS (4), /* fp_add */
1149 COSTS_N_INSNS (4), /* fp_mult_sf */
1150 COSTS_N_INSNS (4), /* fp_mult_df */
1151 COSTS_N_INSNS (24), /* fp_div_sf */
1152 COSTS_N_INSNS (32), /* fp_div_df */
1153 COSTS_N_INSNS (3), /* int_mult_si */
1154 COSTS_N_INSNS (4), /* int_mult_di */
1155 COSTS_N_INSNS (36), /* int_div_si */
1156 COSTS_N_INSNS (68), /* int_div_di */
1157 1, /* branch_cost */
1158 4 /* memory_latency */
1161 /* These costs are the same as the SB-1 above. */
1162 COSTS_N_INSNS (4), /* fp_add */
1163 COSTS_N_INSNS (4), /* fp_mult_sf */
1164 COSTS_N_INSNS (4), /* fp_mult_df */
1165 COSTS_N_INSNS (24), /* fp_div_sf */
1166 COSTS_N_INSNS (32), /* fp_div_df */
1167 COSTS_N_INSNS (3), /* int_mult_si */
1168 COSTS_N_INSNS (4), /* int_mult_di */
1169 COSTS_N_INSNS (36), /* int_div_si */
1170 COSTS_N_INSNS (68), /* int_div_di */
1171 1, /* branch_cost */
1172 4 /* memory_latency */
1179 COSTS_N_INSNS (8), /* int_mult_si */
1180 COSTS_N_INSNS (8), /* int_mult_di */
1181 COSTS_N_INSNS (72), /* int_div_si */
1182 COSTS_N_INSNS (72), /* int_div_di */
1183 1, /* branch_cost */
1184 4 /* memory_latency */
1188 static rtx mips_find_pic_call_symbol (rtx, rtx);
1189 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1191 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1193 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1194 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1195 struct GTY (()) mflip_mips16_entry {
1199 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1201 /* Hash table callbacks for mflip_mips16_htab. */
1204 mflip_mips16_htab_hash (const void *entry)
1206 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1210 mflip_mips16_htab_eq (const void *entry, const void *name)
1212 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1213 (const char *) name) == 0;
1216 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1217 mode, false if it should next add an attribute for the opposite mode. */
1218 static GTY(()) bool mips16_flipper;
1220 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1221 for -mflip-mips16. Return true if it should use "mips16" and false if
1222 it should use "nomips16". */
1225 mflip_mips16_use_mips16_p (tree decl)
1227 struct mflip_mips16_entry *entry;
1232 /* Use the opposite of the command-line setting for anonymous decls. */
1233 if (!DECL_NAME (decl))
1234 return !mips_base_mips16;
1236 if (!mflip_mips16_htab)
1237 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1238 mflip_mips16_htab_eq, NULL);
1240 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1241 hash = htab_hash_string (name);
1242 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1243 entry = (struct mflip_mips16_entry *) *slot;
1246 mips16_flipper = !mips16_flipper;
1247 entry = ggc_alloc_mflip_mips16_entry ();
1249 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1252 return entry->mips16_p;
1255 /* Predicates to test for presence of "near" and "far"/"long_call"
1256 attributes on the given TYPE. */
1259 mips_near_type_p (const_tree type)
1261 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1265 mips_far_type_p (const_tree type)
1267 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1268 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1271 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1274 mips_mips16_decl_p (const_tree decl)
1276 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1280 mips_nomips16_decl_p (const_tree decl)
1282 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1285 /* Check if the interrupt attribute is set for a function. */
1288 mips_interrupt_type_p (tree type)
1290 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1293 /* Check if the attribute to use shadow register set is set for a function. */
1296 mips_use_shadow_register_set_p (tree type)
1298 return lookup_attribute ("use_shadow_register_set",
1299 TYPE_ATTRIBUTES (type)) != NULL;
1302 /* Check if the attribute to keep interrupts masked is set for a function. */
1305 mips_keep_interrupts_masked_p (tree type)
1307 return lookup_attribute ("keep_interrupts_masked",
1308 TYPE_ATTRIBUTES (type)) != NULL;
1311 /* Check if the attribute to use debug exception return is set for
1315 mips_use_debug_exception_return_p (tree type)
1317 return lookup_attribute ("use_debug_exception_return",
1318 TYPE_ATTRIBUTES (type)) != NULL;
1321 /* Return true if function DECL is a MIPS16 function. Return the ambient
1322 setting if DECL is null. */
1325 mips_use_mips16_mode_p (tree decl)
1329 /* Nested functions must use the same frame pointer as their
1330 parent and must therefore use the same ISA mode. */
1331 tree parent = decl_function_context (decl);
1334 if (mips_mips16_decl_p (decl))
1336 if (mips_nomips16_decl_p (decl))
1339 return mips_base_mips16;
1342 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1345 mips_comp_type_attributes (const_tree type1, const_tree type2)
1347 /* Disallow mixed near/far attributes. */
1348 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1350 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1355 /* Implement TARGET_INSERT_ATTRIBUTES. */
1358 mips_insert_attributes (tree decl, tree *attributes)
1361 bool mips16_p, nomips16_p;
1363 /* Check for "mips16" and "nomips16" attributes. */
1364 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1365 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1366 if (TREE_CODE (decl) != FUNCTION_DECL)
1369 error ("%qs attribute only applies to functions", "mips16");
1371 error ("%qs attribute only applies to functions", "nomips16");
1375 mips16_p |= mips_mips16_decl_p (decl);
1376 nomips16_p |= mips_nomips16_decl_p (decl);
1377 if (mips16_p || nomips16_p)
1379 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1380 if (mips16_p && nomips16_p)
1381 error ("%qE cannot have both %<mips16%> and "
1382 "%<nomips16%> attributes",
1385 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1387 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1388 "mips16" attribute, arbitrarily pick one. We must pick the same
1389 setting for duplicate declarations of a function. */
1390 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1391 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1396 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1399 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1401 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1402 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1403 error ("%qE redeclared with conflicting %qs attributes",
1404 DECL_NAME (newdecl), "mips16");
1405 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1406 error ("%qE redeclared with conflicting %qs attributes",
1407 DECL_NAME (newdecl), "nomips16");
1409 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1410 DECL_ATTRIBUTES (newdecl));
1413 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1414 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1417 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1419 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1421 *base_ptr = XEXP (x, 0);
1422 *offset_ptr = INTVAL (XEXP (x, 1));
1431 static unsigned int mips_build_integer (struct mips_integer_op *,
1432 unsigned HOST_WIDE_INT);
1434 /* A subroutine of mips_build_integer, with the same interface.
1435 Assume that the final action in the sequence should be a left shift. */
1438 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1440 unsigned int i, shift;
1442 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1443 since signed numbers are easier to load than unsigned ones. */
1445 while ((value & 1) == 0)
1446 value /= 2, shift++;
1448 i = mips_build_integer (codes, value);
1449 codes[i].code = ASHIFT;
1450 codes[i].value = shift;
1454 /* As for mips_build_shift, but assume that the final action will be
1455 an IOR or PLUS operation. */
1458 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1460 unsigned HOST_WIDE_INT high;
1463 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1464 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1466 /* The constant is too complex to load with a simple LUI/ORI pair,
1467 so we want to give the recursive call as many trailing zeros as
1468 possible. In this case, we know bit 16 is set and that the
1469 low 16 bits form a negative number. If we subtract that number
1470 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1471 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1472 codes[i].code = PLUS;
1473 codes[i].value = CONST_LOW_PART (value);
1477 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1478 bits gives a value with at least 17 trailing zeros. */
1479 i = mips_build_integer (codes, high);
1480 codes[i].code = IOR;
1481 codes[i].value = value & 0xffff;
1486 /* Fill CODES with a sequence of rtl operations to load VALUE.
1487 Return the number of operations needed. */
1490 mips_build_integer (struct mips_integer_op *codes,
1491 unsigned HOST_WIDE_INT value)
1493 if (SMALL_OPERAND (value)
1494 || SMALL_OPERAND_UNSIGNED (value)
1495 || LUI_OPERAND (value))
1497 /* The value can be loaded with a single instruction. */
1498 codes[0].code = UNKNOWN;
1499 codes[0].value = value;
1502 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1504 /* Either the constant is a simple LUI/ORI combination or its
1505 lowest bit is set. We don't want to shift in this case. */
1506 return mips_build_lower (codes, value);
1508 else if ((value & 0xffff) == 0)
1510 /* The constant will need at least three actions. The lowest
1511 16 bits are clear, so the final action will be a shift. */
1512 return mips_build_shift (codes, value);
1516 /* The final action could be a shift, add or inclusive OR.
1517 Rather than use a complex condition to select the best
1518 approach, try both mips_build_shift and mips_build_lower
1519 and pick the one that gives the shortest sequence.
1520 Note that this case is only used once per constant. */
1521 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1522 unsigned int cost, alt_cost;
1524 cost = mips_build_shift (codes, value);
1525 alt_cost = mips_build_lower (alt_codes, value);
1526 if (alt_cost < cost)
1528 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1535 /* Return true if symbols of type TYPE require a GOT access. */
1538 mips_got_symbol_type_p (enum mips_symbol_type type)
1542 case SYMBOL_GOT_PAGE_OFST:
1543 case SYMBOL_GOT_DISP:
1551 /* Return true if X is a thread-local symbol. */
1554 mips_tls_symbol_p (rtx x)
1556 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1559 /* Return true if SYMBOL_REF X is associated with a global symbol
1560 (in the STB_GLOBAL sense). */
1563 mips_global_symbol_p (const_rtx x)
1565 const_tree decl = SYMBOL_REF_DECL (x);
1568 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1570 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1571 or weak symbols. Relocations in the object file will be against
1572 the target symbol, so it's that symbol's binding that matters here. */
1573 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1576 /* Return true if function X is a libgcc MIPS16 stub function. */
1579 mips16_stub_function_p (const_rtx x)
1581 return (GET_CODE (x) == SYMBOL_REF
1582 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1585 /* Return true if function X is a locally-defined and locally-binding
1589 mips16_local_function_p (const_rtx x)
1591 return (GET_CODE (x) == SYMBOL_REF
1592 && SYMBOL_REF_LOCAL_P (x)
1593 && !SYMBOL_REF_EXTERNAL_P (x)
1594 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1597 /* Return true if SYMBOL_REF X binds locally. */
1600 mips_symbol_binds_local_p (const_rtx x)
1602 return (SYMBOL_REF_DECL (x)
1603 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1604 : SYMBOL_REF_LOCAL_P (x));
1607 /* Return true if rtx constants of mode MODE should be put into a small
1611 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1613 return (!TARGET_EMBEDDED_DATA
1614 && TARGET_LOCAL_SDATA
1615 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1618 /* Return true if X should not be moved directly into register $25.
1619 We need this because many versions of GAS will treat "la $25,foo" as
1620 part of a call sequence and so allow a global "foo" to be lazily bound. */
1623 mips_dangerous_for_la25_p (rtx x)
1625 return (!TARGET_EXPLICIT_RELOCS
1627 && GET_CODE (x) == SYMBOL_REF
1628 && mips_global_symbol_p (x));
1631 /* Return true if calls to X might need $25 to be valid on entry. */
1634 mips_use_pic_fn_addr_reg_p (const_rtx x)
1636 if (!TARGET_USE_PIC_FN_ADDR_REG)
1639 /* MIPS16 stub functions are guaranteed not to use $25. */
1640 if (mips16_stub_function_p (x))
1643 if (GET_CODE (x) == SYMBOL_REF)
1645 /* If PLTs and copy relocations are available, the static linker
1646 will make sure that $25 is valid on entry to the target function. */
1647 if (TARGET_ABICALLS_PIC0)
1650 /* Locally-defined functions use absolute accesses to set up
1651 the global pointer. */
1652 if (TARGET_ABSOLUTE_ABICALLS
1653 && mips_symbol_binds_local_p (x)
1654 && !SYMBOL_REF_EXTERNAL_P (x))
1661 /* Return the method that should be used to access SYMBOL_REF or
1662 LABEL_REF X in context CONTEXT. */
1664 static enum mips_symbol_type
1665 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1668 return SYMBOL_GOT_DISP;
1670 if (GET_CODE (x) == LABEL_REF)
1672 /* LABEL_REFs are used for jump tables as well as text labels.
1673 Only return SYMBOL_PC_RELATIVE if we know the label is in
1674 the text section. */
1675 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1676 return SYMBOL_PC_RELATIVE;
1678 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1679 return SYMBOL_GOT_PAGE_OFST;
1681 return SYMBOL_ABSOLUTE;
1684 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1686 if (SYMBOL_REF_TLS_MODEL (x))
1689 if (CONSTANT_POOL_ADDRESS_P (x))
1691 if (TARGET_MIPS16_TEXT_LOADS)
1692 return SYMBOL_PC_RELATIVE;
1694 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1695 return SYMBOL_PC_RELATIVE;
1697 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1698 return SYMBOL_GP_RELATIVE;
1701 /* Do not use small-data accesses for weak symbols; they may end up
1703 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1704 return SYMBOL_GP_RELATIVE;
1706 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1708 if (TARGET_ABICALLS_PIC2
1709 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1711 /* There are three cases to consider:
1713 - o32 PIC (either with or without explicit relocs)
1714 - n32/n64 PIC without explicit relocs
1715 - n32/n64 PIC with explicit relocs
1717 In the first case, both local and global accesses will use an
1718 R_MIPS_GOT16 relocation. We must correctly predict which of
1719 the two semantics (local or global) the assembler and linker
1720 will apply. The choice depends on the symbol's binding rather
1721 than its visibility.
1723 In the second case, the assembler will not use R_MIPS_GOT16
1724 relocations, but it chooses between local and global accesses
1725 in the same way as for o32 PIC.
1727 In the third case we have more freedom since both forms of
1728 access will work for any kind of symbol. However, there seems
1729 little point in doing things differently. */
1730 if (mips_global_symbol_p (x))
1731 return SYMBOL_GOT_DISP;
1733 return SYMBOL_GOT_PAGE_OFST;
1736 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1737 return SYMBOL_FORCE_TO_MEM;
1739 return SYMBOL_ABSOLUTE;
1742 /* Classify the base of symbolic expression X, given that X appears in
1745 static enum mips_symbol_type
1746 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1750 split_const (x, &x, &offset);
1751 if (UNSPEC_ADDRESS_P (x))
1752 return UNSPEC_ADDRESS_TYPE (x);
1754 return mips_classify_symbol (x, context);
1757 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1758 is the alignment in bytes of SYMBOL_REF X. */
1761 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1763 HOST_WIDE_INT align;
1765 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1766 return IN_RANGE (offset, 0, align - 1);
1769 /* Return true if X is a symbolic constant that can be used in context
1770 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1773 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1774 enum mips_symbol_type *symbol_type)
1778 split_const (x, &x, &offset);
1779 if (UNSPEC_ADDRESS_P (x))
1781 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1782 x = UNSPEC_ADDRESS (x);
1784 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1786 *symbol_type = mips_classify_symbol (x, context);
1787 if (*symbol_type == SYMBOL_TLS)
1793 if (offset == const0_rtx)
1796 /* Check whether a nonzero offset is valid for the underlying
1798 switch (*symbol_type)
1800 case SYMBOL_ABSOLUTE:
1801 case SYMBOL_FORCE_TO_MEM:
1802 case SYMBOL_32_HIGH:
1803 case SYMBOL_64_HIGH:
1806 /* If the target has 64-bit pointers and the object file only
1807 supports 32-bit symbols, the values of those symbols will be
1808 sign-extended. In this case we can't allow an arbitrary offset
1809 in case the 32-bit value X + OFFSET has a different sign from X. */
1810 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1811 return offset_within_block_p (x, INTVAL (offset));
1813 /* In other cases the relocations can handle any offset. */
1816 case SYMBOL_PC_RELATIVE:
1817 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1818 In this case, we no longer have access to the underlying constant,
1819 but the original symbol-based access was known to be valid. */
1820 if (GET_CODE (x) == LABEL_REF)
1825 case SYMBOL_GP_RELATIVE:
1826 /* Make sure that the offset refers to something within the
1827 same object block. This should guarantee that the final
1828 PC- or GP-relative offset is within the 16-bit limit. */
1829 return offset_within_block_p (x, INTVAL (offset));
1831 case SYMBOL_GOT_PAGE_OFST:
1832 case SYMBOL_GOTOFF_PAGE:
1833 /* If the symbol is global, the GOT entry will contain the symbol's
1834 address, and we will apply a 16-bit offset after loading it.
1835 If the symbol is local, the linker should provide enough local
1836 GOT entries for a 16-bit offset, but larger offsets may lead
1838 return SMALL_INT (offset);
1842 /* There is no carry between the HI and LO REL relocations, so the
1843 offset is only valid if we know it won't lead to such a carry. */
1844 return mips_offset_within_alignment_p (x, INTVAL (offset));
1846 case SYMBOL_GOT_DISP:
1847 case SYMBOL_GOTOFF_DISP:
1848 case SYMBOL_GOTOFF_CALL:
1849 case SYMBOL_GOTOFF_LOADGP:
1852 case SYMBOL_GOTTPREL:
1860 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1861 single instruction. We rely on the fact that, in the worst case,
1862 all instructions involved in a MIPS16 address calculation are usually
1866 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1870 case SYMBOL_ABSOLUTE:
1871 /* When using 64-bit symbols, we need 5 preparatory instructions,
1874 lui $at,%highest(symbol)
1875 daddiu $at,$at,%higher(symbol)
1877 daddiu $at,$at,%hi(symbol)
1880 The final address is then $at + %lo(symbol). With 32-bit
1881 symbols we just need a preparatory LUI for normal mode and
1882 a preparatory LI and SLL for MIPS16. */
1883 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1885 case SYMBOL_GP_RELATIVE:
1886 /* Treat GP-relative accesses as taking a single instruction on
1887 MIPS16 too; the copy of $gp can often be shared. */
1890 case SYMBOL_PC_RELATIVE:
1891 /* PC-relative constants can be only be used with ADDIUPC,
1892 DADDIUPC, LWPC and LDPC. */
1893 if (mode == MAX_MACHINE_MODE
1894 || GET_MODE_SIZE (mode) == 4
1895 || GET_MODE_SIZE (mode) == 8)
1898 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1901 case SYMBOL_FORCE_TO_MEM:
1902 /* LEAs will be converted into constant-pool references by
1904 if (mode == MAX_MACHINE_MODE)
1907 /* The constant must be loaded and then dereferenced. */
1910 case SYMBOL_GOT_DISP:
1911 /* The constant will have to be loaded from the GOT before it
1912 is used in an address. */
1913 if (mode != MAX_MACHINE_MODE)
1918 case SYMBOL_GOT_PAGE_OFST:
1919 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1920 local/global classification is accurate. The worst cases are:
1922 (1) For local symbols when generating o32 or o64 code. The assembler
1928 ...and the final address will be $at + %lo(symbol).
1930 (2) For global symbols when -mxgot. The assembler will use:
1932 lui $at,%got_hi(symbol)
1935 ...and the final address will be $at + %got_lo(symbol). */
1938 case SYMBOL_GOTOFF_PAGE:
1939 case SYMBOL_GOTOFF_DISP:
1940 case SYMBOL_GOTOFF_CALL:
1941 case SYMBOL_GOTOFF_LOADGP:
1942 case SYMBOL_32_HIGH:
1943 case SYMBOL_64_HIGH:
1949 case SYMBOL_GOTTPREL:
1952 /* A 16-bit constant formed by a single relocation, or a 32-bit
1953 constant formed from a high 16-bit relocation and a low 16-bit
1954 relocation. Use mips_split_p to determine which. 32-bit
1955 constants need an "lui; addiu" sequence for normal mode and
1956 an "li; sll; addiu" sequence for MIPS16 mode. */
1957 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1960 /* We don't treat a bare TLS symbol as a constant. */
1966 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1967 to load symbols of type TYPE into a register. Return 0 if the given
1968 type of symbol cannot be used as an immediate operand.
1970 Otherwise, return the number of instructions needed to load or store
1971 values of mode MODE to or from addresses of type TYPE. Return 0 if
1972 the given type of symbol is not valid in addresses.
1974 In both cases, treat extended MIPS16 instructions as two instructions. */
1977 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1979 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1982 /* A for_each_rtx callback. Stop the search if *X references a
1983 thread-local symbol. */
1986 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1988 return mips_tls_symbol_p (*x);
1991 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1994 mips_cannot_force_const_mem (rtx x)
1996 enum mips_symbol_type type;
1999 /* There is no assembler syntax for expressing an address-sized
2001 if (GET_CODE (x) == HIGH)
2004 /* As an optimization, reject constants that mips_legitimize_move
2007 Suppose we have a multi-instruction sequence that loads constant C
2008 into register R. If R does not get allocated a hard register, and
2009 R is used in an operand that allows both registers and memory
2010 references, reload will consider forcing C into memory and using
2011 one of the instruction's memory alternatives. Returning false
2012 here will force it to use an input reload instead. */
2013 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
2016 split_const (x, &base, &offset);
2017 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
2018 && type != SYMBOL_FORCE_TO_MEM)
2020 /* The same optimization as for CONST_INT. */
2021 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2024 /* If MIPS16 constant pools live in the text section, they should
2025 not refer to anything that might need run-time relocation. */
2026 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2030 /* TLS symbols must be computed by mips_legitimize_move. */
2031 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2037 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2038 constants when we're using a per-function constant pool. */
2041 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2042 const_rtx x ATTRIBUTE_UNUSED)
2044 return !TARGET_MIPS16_PCREL_LOADS;
2047 /* Return true if register REGNO is a valid base register for mode MODE.
2048 STRICT_P is true if REG_OK_STRICT is in effect. */
2051 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2054 if (!HARD_REGISTER_NUM_P (regno))
2058 regno = reg_renumber[regno];
2061 /* These fake registers will be eliminated to either the stack or
2062 hard frame pointer, both of which are usually valid base registers.
2063 Reload deals with the cases where the eliminated form isn't valid. */
2064 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2067 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2068 values, nothing smaller. There are two problems here:
2070 (a) Instantiating virtual registers can introduce new uses of the
2071 stack pointer. If these virtual registers are valid addresses,
2072 the stack pointer should be too.
2074 (b) Most uses of the stack pointer are not made explicit until
2075 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2076 We don't know until that stage whether we'll be eliminating to the
2077 stack pointer (which needs the restriction) or the hard frame
2078 pointer (which doesn't).
2080 All in all, it seems more consistent to only enforce this restriction
2081 during and after reload. */
2082 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2083 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2085 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2088 /* Return true if X is a valid base register for mode MODE.
2089 STRICT_P is true if REG_OK_STRICT is in effect. */
2092 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2094 if (!strict_p && GET_CODE (x) == SUBREG)
2098 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2101 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2102 can address a value of mode MODE. */
2105 mips_valid_offset_p (rtx x, enum machine_mode mode)
2107 /* Check that X is a signed 16-bit number. */
2108 if (!const_arith_operand (x, Pmode))
2111 /* We may need to split multiword moves, so make sure that every word
2113 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2114 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2120 /* Return true if a LO_SUM can address a value of mode MODE when the
2121 LO_SUM symbol has type SYMBOL_TYPE. */
2124 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2126 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2128 if (mips_symbol_insns (symbol_type, mode) == 0)
2131 /* Check that there is a known low-part relocation. */
2132 if (mips_lo_relocs[symbol_type] == NULL)
2135 /* We may need to split multiword moves, so make sure that each word
2136 can be accessed without inducing a carry. This is mainly needed
2137 for o64, which has historically only guaranteed 64-bit alignment
2138 for 128-bit types. */
2139 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2140 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2146 /* Return true if X is a valid address for machine mode MODE. If it is,
2147 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2151 mips_classify_address (struct mips_address_info *info, rtx x,
2152 enum machine_mode mode, bool strict_p)
2154 switch (GET_CODE (x))
2158 info->type = ADDRESS_REG;
2160 info->offset = const0_rtx;
2161 return mips_valid_base_register_p (info->reg, mode, strict_p);
2164 info->type = ADDRESS_REG;
2165 info->reg = XEXP (x, 0);
2166 info->offset = XEXP (x, 1);
2167 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2168 && mips_valid_offset_p (info->offset, mode));
2171 info->type = ADDRESS_LO_SUM;
2172 info->reg = XEXP (x, 0);
2173 info->offset = XEXP (x, 1);
2174 /* We have to trust the creator of the LO_SUM to do something vaguely
2175 sane. Target-independent code that creates a LO_SUM should also
2176 create and verify the matching HIGH. Target-independent code that
2177 adds an offset to a LO_SUM must prove that the offset will not
2178 induce a carry. Failure to do either of these things would be
2179 a bug, and we are not required to check for it here. The MIPS
2180 backend itself should only create LO_SUMs for valid symbolic
2181 constants, with the high part being either a HIGH or a copy
2184 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2185 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2186 && mips_valid_lo_sum_p (info->symbol_type, mode));
2189 /* Small-integer addresses don't occur very often, but they
2190 are legitimate if $0 is a valid base register. */
2191 info->type = ADDRESS_CONST_INT;
2192 return !TARGET_MIPS16 && SMALL_INT (x);
2197 info->type = ADDRESS_SYMBOLIC;
2198 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2200 && mips_symbol_insns (info->symbol_type, mode) > 0
2201 && !mips_split_p[info->symbol_type]);
2208 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2211 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2213 struct mips_address_info addr;
2215 return mips_classify_address (&addr, x, mode, strict_p);
2218 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2221 mips_stack_address_p (rtx x, enum machine_mode mode)
2223 struct mips_address_info addr;
2225 return (mips_classify_address (&addr, x, mode, false)
2226 && addr.type == ADDRESS_REG
2227 && addr.reg == stack_pointer_rtx);
2230 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2231 address instruction. Note that such addresses are not considered
2232 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2233 is so restricted. */
2236 mips_lwxs_address_p (rtx addr)
2239 && GET_CODE (addr) == PLUS
2240 && REG_P (XEXP (addr, 1)))
2242 rtx offset = XEXP (addr, 0);
2243 if (GET_CODE (offset) == MULT
2244 && REG_P (XEXP (offset, 0))
2245 && CONST_INT_P (XEXP (offset, 1))
2246 && INTVAL (XEXP (offset, 1)) == 4)
2252 /* Return true if a value at OFFSET bytes from base register BASE can be
2253 accessed using an unextended MIPS16 instruction. MODE is the mode of
2256 Usually the offset in an unextended instruction is a 5-bit field.
2257 The offset is unsigned and shifted left once for LH and SH, twice
2258 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2259 an 8-bit immediate field that's shifted left twice. */
2262 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2263 unsigned HOST_WIDE_INT offset)
2265 if (offset % GET_MODE_SIZE (mode) == 0)
2267 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2268 return offset < 256U * GET_MODE_SIZE (mode);
2269 return offset < 32U * GET_MODE_SIZE (mode);
2274 /* Return the number of instructions needed to load or store a value
2275 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2276 Assume that multiword moves may need to be split into word moves
2277 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2280 For MIPS16 code, count extended instructions as two instructions. */
2283 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2285 struct mips_address_info addr;
2288 /* BLKmode is used for single unaligned loads and stores and should
2289 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2290 meaningless, so we have to single it out as a special case one way
2292 if (mode != BLKmode && might_split_p)
2293 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2297 if (mips_classify_address (&addr, x, mode, false))
2302 && !mips16_unextended_reference_p (mode, addr.reg,
2303 UINTVAL (addr.offset)))
2307 case ADDRESS_LO_SUM:
2308 return TARGET_MIPS16 ? factor * 2 : factor;
2310 case ADDRESS_CONST_INT:
2313 case ADDRESS_SYMBOLIC:
2314 return factor * mips_symbol_insns (addr.symbol_type, mode);
2319 /* Return the number of instructions needed to load constant X.
2320 Return 0 if X isn't a valid constant. */
2323 mips_const_insns (rtx x)
2325 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2326 enum mips_symbol_type symbol_type;
2329 switch (GET_CODE (x))
2332 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2334 || !mips_split_p[symbol_type])
2337 /* This is simply an LUI for normal mode. It is an extended
2338 LI followed by an extended SLL for MIPS16. */
2339 return TARGET_MIPS16 ? 4 : 1;
2343 /* Unsigned 8-bit constants can be loaded using an unextended
2344 LI instruction. Unsigned 16-bit constants can be loaded
2345 using an extended LI. Negative constants must be loaded
2346 using LI and then negated. */
2347 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2348 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2349 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2350 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2353 return mips_build_integer (codes, INTVAL (x));
2357 /* Allow zeros for normal mode, where we can use $0. */
2358 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2364 /* See if we can refer to X directly. */
2365 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2366 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2368 /* Otherwise try splitting the constant into a base and offset.
2369 If the offset is a 16-bit value, we can load the base address
2370 into a register and then use (D)ADDIU to add in the offset.
2371 If the offset is larger, we can load the base and offset
2372 into separate registers and add them together with (D)ADDU.
2373 However, the latter is only possible before reload; during
2374 and after reload, we must have the option of forcing the
2375 constant into the pool instead. */
2376 split_const (x, &x, &offset);
2379 int n = mips_const_insns (x);
2382 if (SMALL_INT (offset))
2384 else if (!targetm.cannot_force_const_mem (x))
2385 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2392 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2400 /* X is a doubleword constant that can be handled by splitting it into
2401 two words and loading each word separately. Return the number of
2402 instructions required to do this. */
2405 mips_split_const_insns (rtx x)
2407 unsigned int low, high;
2409 low = mips_const_insns (mips_subword (x, false));
2410 high = mips_const_insns (mips_subword (x, true));
2411 gcc_assert (low > 0 && high > 0);
2415 /* Return the number of instructions needed to implement INSN,
2416 given that it loads from or stores to MEM. Count extended
2417 MIPS16 instructions as two instructions. */
2420 mips_load_store_insns (rtx mem, rtx insn)
2422 enum machine_mode mode;
2426 gcc_assert (MEM_P (mem));
2427 mode = GET_MODE (mem);
2429 /* Try to prove that INSN does not need to be split. */
2430 might_split_p = true;
2431 if (GET_MODE_BITSIZE (mode) == 64)
2433 set = single_set (insn);
2434 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2435 might_split_p = false;
2438 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2441 /* Return the number of instructions needed for an integer division. */
2444 mips_idiv_insns (void)
2449 if (TARGET_CHECK_ZERO_DIV)
2451 if (GENERATE_DIVIDE_TRAPS)
2457 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2462 /* Emit a move from SRC to DEST. Assume that the move expanders can
2463 handle all moves if !can_create_pseudo_p (). The distinction is
2464 important because, unlike emit_move_insn, the move expanders know
2465 how to force Pmode objects into the constant pool even when the
2466 constant pool address is not itself legitimate. */
2469 mips_emit_move (rtx dest, rtx src)
2471 return (can_create_pseudo_p ()
2472 ? emit_move_insn (dest, src)
2473 : emit_move_insn_1 (dest, src));
2476 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2479 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2481 emit_insn (gen_rtx_SET (VOIDmode, target,
2482 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2485 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2486 Return that new register. */
2489 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2493 reg = gen_reg_rtx (mode);
2494 mips_emit_unary (code, reg, op0);
2498 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2501 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2503 emit_insn (gen_rtx_SET (VOIDmode, target,
2504 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2507 /* Compute (CODE OP0 OP1) and store the result in a new register
2508 of mode MODE. Return that new register. */
2511 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2515 reg = gen_reg_rtx (mode);
2516 mips_emit_binary (code, reg, op0, op1);
2520 /* Copy VALUE to a register and return that register. If new pseudos
2521 are allowed, copy it into a new register, otherwise use DEST. */
2524 mips_force_temporary (rtx dest, rtx value)
2526 if (can_create_pseudo_p ())
2527 return force_reg (Pmode, value);
2530 mips_emit_move (dest, value);
2535 /* Emit a call sequence with call pattern PATTERN and return the call
2536 instruction itself (which is not necessarily the last instruction
2537 emitted). ORIG_ADDR is the original, unlegitimized address,
2538 ADDR is the legitimized form, and LAZY_P is true if the call
2539 address is lazily-bound. */
2542 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2546 insn = emit_call_insn (pattern);
2548 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2550 /* MIPS16 JALRs only take MIPS16 registers. If the target
2551 function requires $25 to be valid on entry, we must copy it
2552 there separately. The move instruction can be put in the
2553 call's delay slot. */
2554 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2555 emit_insn_before (gen_move_insn (reg, addr), insn);
2556 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2560 /* Lazy-binding stubs require $gp to be valid on entry. */
2561 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2565 /* See the comment above load_call<mode> for details. */
2566 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2567 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2568 emit_insn (gen_update_got_version ());
2573 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2574 then add CONST_INT OFFSET to the result. */
2577 mips_unspec_address_offset (rtx base, rtx offset,
2578 enum mips_symbol_type symbol_type)
2580 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2581 UNSPEC_ADDRESS_FIRST + symbol_type);
2582 if (offset != const0_rtx)
2583 base = gen_rtx_PLUS (Pmode, base, offset);
2584 return gen_rtx_CONST (Pmode, base);
2587 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2588 type SYMBOL_TYPE. */
2591 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2595 split_const (address, &base, &offset);
2596 return mips_unspec_address_offset (base, offset, symbol_type);
2599 /* If OP is an UNSPEC address, return the address to which it refers,
2600 otherwise return OP itself. */
2603 mips_strip_unspec_address (rtx op)
2607 split_const (op, &base, &offset);
2608 if (UNSPEC_ADDRESS_P (base))
2609 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2613 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2614 high part to BASE and return the result. Just return BASE otherwise.
2615 TEMP is as for mips_force_temporary.
2617 The returned expression can be used as the first operand to a LO_SUM. */
2620 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2621 enum mips_symbol_type symbol_type)
2623 if (mips_split_p[symbol_type])
2625 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2626 addr = mips_force_temporary (temp, addr);
2627 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2632 /* Return an instruction that copies $gp into register REG. We want
2633 GCC to treat the register's value as constant, so that its value
2634 can be rematerialized on demand. */
2637 gen_load_const_gp (rtx reg)
2639 return (Pmode == SImode
2640 ? gen_load_const_gp_si (reg)
2641 : gen_load_const_gp_di (reg));
2644 /* Return a pseudo register that contains the value of $gp throughout
2645 the current function. Such registers are needed by MIPS16 functions,
2646 for which $gp itself is not a valid base register or addition operand. */
2649 mips16_gp_pseudo_reg (void)
2651 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2655 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2657 push_topmost_sequence ();
2659 scan = get_insns ();
2660 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2661 scan = NEXT_INSN (scan);
2663 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2664 emit_insn_after (insn, scan);
2666 pop_topmost_sequence ();
2669 return cfun->machine->mips16_gp_pseudo_rtx;
2672 /* Return a base register that holds pic_offset_table_rtx.
2673 TEMP, if nonnull, is a scratch Pmode base register. */
2676 mips_pic_base_register (rtx temp)
2679 return pic_offset_table_rtx;
2681 if (currently_expanding_to_rtl)
2682 return mips16_gp_pseudo_reg ();
2684 if (can_create_pseudo_p ())
2685 temp = gen_reg_rtx (Pmode);
2688 /* The first post-reload split exposes all references to $gp
2689 (both uses and definitions). All references must remain
2690 explicit after that point.
2692 It is safe to introduce uses of $gp at any time, so for
2693 simplicity, we do that before the split too. */
2694 mips_emit_move (temp, pic_offset_table_rtx);
2696 emit_insn (gen_load_const_gp (temp));
2700 /* Return the RHS of a load_call<mode> insn. */
2703 mips_unspec_call (rtx reg, rtx symbol)
2707 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2708 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2711 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2712 reference. Return NULL_RTX otherwise. */
2715 mips_strip_unspec_call (rtx src)
2717 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2718 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2722 /* Create and return a GOT reference of type TYPE for address ADDR.
2723 TEMP, if nonnull, is a scratch Pmode base register. */
2726 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2728 rtx base, high, lo_sum_symbol;
2730 base = mips_pic_base_register (temp);
2732 /* If we used the temporary register to load $gp, we can't use
2733 it for the high part as well. */
2734 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2737 high = mips_unspec_offset_high (temp, base, addr, type);
2738 lo_sum_symbol = mips_unspec_address (addr, type);
2740 if (type == SYMBOL_GOTOFF_CALL)
2741 return mips_unspec_call (high, lo_sum_symbol);
2743 return (Pmode == SImode
2744 ? gen_unspec_gotsi (high, lo_sum_symbol)
2745 : gen_unspec_gotdi (high, lo_sum_symbol));
2748 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2749 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2750 constant in that context and can be split into high and low parts.
2751 If so, and if LOW_OUT is nonnull, emit the high part and store the
2752 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2754 TEMP is as for mips_force_temporary and is used to load the high
2755 part into a register.
2757 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2758 a legitimize SET_SRC for an .md pattern, otherwise the low part
2759 is guaranteed to be a legitimate address for mode MODE. */
2762 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2764 enum mips_symbol_context context;
2765 enum mips_symbol_type symbol_type;
2768 context = (mode == MAX_MACHINE_MODE
2769 ? SYMBOL_CONTEXT_LEA
2770 : SYMBOL_CONTEXT_MEM);
2771 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2773 addr = XEXP (addr, 0);
2774 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2775 && mips_symbol_insns (symbol_type, mode) > 0
2776 && mips_split_hi_p[symbol_type])
2779 switch (symbol_type)
2781 case SYMBOL_GOT_PAGE_OFST:
2782 /* The high part of a page/ofst pair is loaded from the GOT. */
2783 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2794 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2795 && mips_symbol_insns (symbol_type, mode) > 0
2796 && mips_split_p[symbol_type])
2799 switch (symbol_type)
2801 case SYMBOL_GOT_DISP:
2802 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2803 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2806 case SYMBOL_GP_RELATIVE:
2807 high = mips_pic_base_register (temp);
2808 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2812 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2813 high = mips_force_temporary (temp, high);
2814 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2823 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2824 mips_force_temporary; it is only needed when OFFSET is not a
2828 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2830 if (!SMALL_OPERAND (offset))
2836 /* Load the full offset into a register so that we can use
2837 an unextended instruction for the address itself. */
2838 high = GEN_INT (offset);
2843 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2844 The addition inside the macro CONST_HIGH_PART may cause an
2845 overflow, so we need to force a sign-extension check. */
2846 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2847 offset = CONST_LOW_PART (offset);
2849 high = mips_force_temporary (temp, high);
2850 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2852 return plus_constant (reg, offset);
2855 /* The __tls_get_attr symbol. */
2856 static GTY(()) rtx mips_tls_symbol;
2858 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2859 the TLS symbol we are referencing and TYPE is the symbol type to use
2860 (either global dynamic or local dynamic). V0 is an RTX for the
2861 return value location. */
2864 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2868 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2870 if (!mips_tls_symbol)
2871 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2873 loc = mips_unspec_address (sym, type);
2877 emit_insn (gen_rtx_SET (Pmode, a0,
2878 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2879 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2880 const0_rtx, NULL_RTX, false);
2881 RTL_CONST_CALL_P (insn) = 1;
2882 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2883 insn = get_insns ();
2890 /* Return a pseudo register that contains the current thread pointer. */
2897 tp = gen_reg_rtx (Pmode);
2898 if (Pmode == DImode)
2899 emit_insn (gen_tls_get_tp_di (tp));
2901 emit_insn (gen_tls_get_tp_si (tp));
2905 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2906 its address. The return value will be both a valid address and a valid
2907 SET_SRC (either a REG or a LO_SUM). */
2910 mips_legitimize_tls_address (rtx loc)
2912 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2913 enum tls_model model;
2917 sorry ("MIPS16 TLS");
2918 return gen_reg_rtx (Pmode);
2921 model = SYMBOL_REF_TLS_MODEL (loc);
2922 /* Only TARGET_ABICALLS code can have more than one module; other
2923 code must be be static and should not use a GOT. All TLS models
2924 reduce to local exec in this situation. */
2925 if (!TARGET_ABICALLS)
2926 model = TLS_MODEL_LOCAL_EXEC;
2930 case TLS_MODEL_GLOBAL_DYNAMIC:
2931 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2932 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2933 dest = gen_reg_rtx (Pmode);
2934 emit_libcall_block (insn, dest, v0, loc);
2937 case TLS_MODEL_LOCAL_DYNAMIC:
2938 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2939 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2940 tmp1 = gen_reg_rtx (Pmode);
2942 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2943 share the LDM result with other LD model accesses. */
2944 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2946 emit_libcall_block (insn, tmp1, v0, eqv);
2948 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2949 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2950 mips_unspec_address (loc, SYMBOL_DTPREL));
2953 case TLS_MODEL_INITIAL_EXEC:
2954 tp = mips_get_tp ();
2955 tmp1 = gen_reg_rtx (Pmode);
2956 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2957 if (Pmode == DImode)
2958 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2960 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2961 dest = gen_reg_rtx (Pmode);
2962 emit_insn (gen_add3_insn (dest, tmp1, tp));
2965 case TLS_MODEL_LOCAL_EXEC:
2966 tp = mips_get_tp ();
2967 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2968 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2969 mips_unspec_address (loc, SYMBOL_TPREL));
2978 /* If X is not a valid address for mode MODE, force it into a register. */
2981 mips_force_address (rtx x, enum machine_mode mode)
2983 if (!mips_legitimate_address_p (mode, x, false))
2984 x = force_reg (Pmode, x);
2988 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2989 be legitimized in a way that the generic machinery might not expect,
2990 return a new address, otherwise return NULL. MODE is the mode of
2991 the memory being accessed. */
2994 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2995 enum machine_mode mode)
2998 HOST_WIDE_INT offset;
3000 if (mips_tls_symbol_p (x))
3001 return mips_legitimize_tls_address (x);
3003 /* See if the address can split into a high part and a LO_SUM. */
3004 if (mips_split_symbol (NULL, x, mode, &addr))
3005 return mips_force_address (addr, mode);
3007 /* Handle BASE + OFFSET using mips_add_offset. */
3008 mips_split_plus (x, &base, &offset);
3011 if (!mips_valid_base_register_p (base, mode, false))
3012 base = copy_to_mode_reg (Pmode, base);
3013 addr = mips_add_offset (NULL, base, offset);
3014 return mips_force_address (addr, mode);
3020 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3023 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3025 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3026 enum machine_mode mode;
3027 unsigned int i, num_ops;
3030 mode = GET_MODE (dest);
3031 num_ops = mips_build_integer (codes, value);
3033 /* Apply each binary operation to X. Invariant: X is a legitimate
3034 source operand for a SET pattern. */
3035 x = GEN_INT (codes[0].value);
3036 for (i = 1; i < num_ops; i++)
3038 if (!can_create_pseudo_p ())
3040 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3044 x = force_reg (mode, x);
3045 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3048 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3051 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3052 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3056 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3060 /* Split moves of big integers into smaller pieces. */
3061 if (splittable_const_int_operand (src, mode))
3063 mips_move_integer (dest, dest, INTVAL (src));
3067 /* Split moves of symbolic constants into high/low pairs. */
3068 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3070 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3074 /* Generate the appropriate access sequences for TLS symbols. */
3075 if (mips_tls_symbol_p (src))
3077 mips_emit_move (dest, mips_legitimize_tls_address (src));
3081 /* If we have (const (plus symbol offset)), and that expression cannot
3082 be forced into memory, load the symbol first and add in the offset.
3083 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3084 forced into memory, as it usually produces better code. */
3085 split_const (src, &base, &offset);
3086 if (offset != const0_rtx
3087 && (targetm.cannot_force_const_mem (src)
3088 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3090 base = mips_force_temporary (dest, base);
3091 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3095 src = force_const_mem (mode, src);
3097 /* When using explicit relocs, constant pool references are sometimes
3098 not legitimate addresses. */
3099 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3100 mips_emit_move (dest, src);
3103 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3104 sequence that is valid. */
3107 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3109 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3111 mips_emit_move (dest, force_reg (mode, src));
3115 /* We need to deal with constants that would be legitimate
3116 immediate_operands but aren't legitimate move_operands. */
3117 if (CONSTANT_P (src) && !move_operand (src, mode))
3119 mips_legitimize_const_move (mode, dest, src);
3120 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3126 /* Return true if value X in context CONTEXT is a small-data address
3127 that can be rewritten as a LO_SUM. */
3130 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3132 enum mips_symbol_type symbol_type;
3134 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3135 && !mips_split_p[SYMBOL_GP_RELATIVE]
3136 && mips_symbolic_constant_p (x, context, &symbol_type)
3137 && symbol_type == SYMBOL_GP_RELATIVE);
3140 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3141 containing MEM, or null if none. */
3144 mips_small_data_pattern_1 (rtx *loc, void *data)
3146 enum mips_symbol_context context;
3148 if (GET_CODE (*loc) == LO_SUM)
3153 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3158 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3159 return mips_rewrite_small_data_p (*loc, context);
3162 /* Return true if OP refers to small data symbols directly, not through
3166 mips_small_data_pattern_p (rtx op)
3168 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3171 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3172 DATA is the containing MEM, or null if none. */
3175 mips_rewrite_small_data_1 (rtx *loc, void *data)
3177 enum mips_symbol_context context;
3181 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3185 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3186 if (mips_rewrite_small_data_p (*loc, context))
3187 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3189 if (GET_CODE (*loc) == LO_SUM)
3195 /* Rewrite instruction pattern PATTERN so that it refers to small data
3196 using explicit relocations. */
3199 mips_rewrite_small_data (rtx pattern)
3201 pattern = copy_insn (pattern);
3202 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3206 /* We need a lot of little routines to check the range of MIPS16 immediate
3210 m16_check_op (rtx op, int low, int high, int mask)
3212 return (CONST_INT_P (op)
3213 && IN_RANGE (INTVAL (op), low, high)
3214 && (INTVAL (op) & mask) == 0);
3218 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3220 return m16_check_op (op, 0x1, 0x8, 0);
3224 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3226 return m16_check_op (op, -0x8, 0x7, 0);
3230 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3232 return m16_check_op (op, -0x7, 0x8, 0);
3236 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3238 return m16_check_op (op, -0x10, 0xf, 0);
3242 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3244 return m16_check_op (op, -0xf, 0x10, 0);
3248 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3250 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3254 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3256 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3260 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3262 return m16_check_op (op, -0x80, 0x7f, 0);
3266 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3268 return m16_check_op (op, -0x7f, 0x80, 0);
3272 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3274 return m16_check_op (op, 0x0, 0xff, 0);
3278 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3280 return m16_check_op (op, -0xff, 0x0, 0);
3284 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3286 return m16_check_op (op, -0x1, 0xfe, 0);
3290 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3292 return m16_check_op (op, 0x0, 0xff << 2, 3);
3296 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3298 return m16_check_op (op, -0xff << 2, 0x0, 3);
3302 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3304 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3308 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3310 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3313 /* The cost of loading values from the constant pool. It should be
3314 larger than the cost of any constant we want to synthesize inline. */
3315 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3317 /* Return the cost of X when used as an operand to the MIPS16 instruction
3318 that implements CODE. Return -1 if there is no such instruction, or if
3319 X is not a valid immediate operand for it. */
3322 mips16_constant_cost (int code, HOST_WIDE_INT x)
3329 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3330 other shifts are extended. The shift patterns truncate the shift
3331 count to the right size, so there are no out-of-range values. */
3332 if (IN_RANGE (x, 1, 8))
3334 return COSTS_N_INSNS (1);
3337 if (IN_RANGE (x, -128, 127))
3339 if (SMALL_OPERAND (x))
3340 return COSTS_N_INSNS (1);
3344 /* Like LE, but reject the always-true case. */
3348 /* We add 1 to the immediate and use SLT. */
3351 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3354 if (IN_RANGE (x, 0, 255))
3356 if (SMALL_OPERAND_UNSIGNED (x))
3357 return COSTS_N_INSNS (1);
3362 /* Equality comparisons with 0 are cheap. */
3372 /* Return true if there is a non-MIPS16 instruction that implements CODE
3373 and if that instruction accepts X as an immediate operand. */
3376 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3383 /* All shift counts are truncated to a valid constant. */
3388 /* Likewise rotates, if the target supports rotates at all. */
3394 /* These instructions take 16-bit unsigned immediates. */
3395 return SMALL_OPERAND_UNSIGNED (x);
3400 /* These instructions take 16-bit signed immediates. */
3401 return SMALL_OPERAND (x);
3407 /* The "immediate" forms of these instructions are really
3408 implemented as comparisons with register 0. */
3413 /* Likewise, meaning that the only valid immediate operand is 1. */
3417 /* We add 1 to the immediate and use SLT. */
3418 return SMALL_OPERAND (x + 1);
3421 /* Likewise SLTU, but reject the always-true case. */
3422 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3426 /* The bit position and size are immediate operands. */
3427 return ISA_HAS_EXT_INS;
3430 /* By default assume that $0 can be used for 0. */
3435 /* Return the cost of binary operation X, given that the instruction
3436 sequence for a word-sized or smaller operation has cost SINGLE_COST
3437 and that the sequence of a double-word operation has cost DOUBLE_COST.
3438 If SPEED is true, optimize for speed otherwise optimize for size. */
3441 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3445 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3450 + rtx_cost (XEXP (x, 0), SET, speed)
3451 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3454 /* Return the cost of floating-point multiplications of mode MODE. */
3457 mips_fp_mult_cost (enum machine_mode mode)
3459 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3462 /* Return the cost of floating-point divisions of mode MODE. */
3465 mips_fp_div_cost (enum machine_mode mode)
3467 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3470 /* Return the cost of sign-extending OP to mode MODE, not including the
3471 cost of OP itself. */
3474 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3477 /* Extended loads are as cheap as unextended ones. */
3480 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3481 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3484 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3485 /* We can use SEB or SEH. */
3486 return COSTS_N_INSNS (1);
3488 /* We need to use a shift left and a shift right. */
3489 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3492 /* Return the cost of zero-extending OP to mode MODE, not including the
3493 cost of OP itself. */
3496 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3499 /* Extended loads are as cheap as unextended ones. */
3502 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3503 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3504 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3506 if (GENERATE_MIPS16E)
3507 /* We can use ZEB or ZEH. */
3508 return COSTS_N_INSNS (1);
3511 /* We need to load 0xff or 0xffff into a register and use AND. */
3512 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3514 /* We can use ANDI. */
3515 return COSTS_N_INSNS (1);
3518 /* Implement TARGET_RTX_COSTS. */
3521 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3523 enum machine_mode mode = GET_MODE (x);
3524 bool float_mode_p = FLOAT_MODE_P (mode);
3528 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3529 appear in the instruction stream, and the cost of a comparison is
3530 really the cost of the branch or scc condition. At the time of
3531 writing, GCC only uses an explicit outer COMPARE code when optabs
3532 is testing whether a constant is expensive enough to force into a
3533 register. We want optabs to pass such constants through the MIPS
3534 expanders instead, so make all constants very cheap here. */
3535 if (outer_code == COMPARE)
3537 gcc_assert (CONSTANT_P (x));
3545 /* Treat *clear_upper32-style ANDs as having zero cost in the
3546 second operand. The cost is entirely in the first operand.
3548 ??? This is needed because we would otherwise try to CSE
3549 the constant operand. Although that's the right thing for
3550 instructions that continue to be a register operation throughout
3551 compilation, it is disastrous for instructions that could
3552 later be converted into a memory operation. */
3554 && outer_code == AND
3555 && UINTVAL (x) == 0xffffffff)
3563 cost = mips16_constant_cost (outer_code, INTVAL (x));
3572 /* When not optimizing for size, we care more about the cost
3573 of hot code, and hot code is often in a loop. If a constant
3574 operand needs to be forced into a register, we will often be
3575 able to hoist the constant load out of the loop, so the load
3576 should not contribute to the cost. */
3577 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3589 if (force_to_mem_operand (x, VOIDmode))
3591 *total = COSTS_N_INSNS (1);
3594 cost = mips_const_insns (x);
3597 /* If the constant is likely to be stored in a GPR, SETs of
3598 single-insn constants are as cheap as register sets; we
3599 never want to CSE them.
3601 Don't reduce the cost of storing a floating-point zero in
3602 FPRs. If we have a zero in an FPR for other reasons, we
3603 can get better cfg-cleanup and delayed-branch results by
3604 using it consistently, rather than using $0 sometimes and
3605 an FPR at other times. Also, moves between floating-point
3606 registers are sometimes cheaper than (D)MTC1 $0. */
3608 && outer_code == SET
3609 && !(float_mode_p && TARGET_HARD_FLOAT))
3611 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3612 want to CSE the constant itself. It is usually better to
3613 have N copies of the last operation in the sequence and one
3614 shared copy of the other operations. (Note that this is
3615 not true for MIPS16 code, where the final operation in the
3616 sequence is often an extended instruction.)
3618 Also, if we have a CONST_INT, we don't know whether it is
3619 for a word or doubleword operation, so we cannot rely on
3620 the result of mips_build_integer. */
3621 else if (!TARGET_MIPS16
3622 && (outer_code == SET || mode == VOIDmode))
3624 *total = COSTS_N_INSNS (cost);
3627 /* The value will need to be fetched from the constant pool. */
3628 *total = CONSTANT_POOL_COST;
3632 /* If the address is legitimate, return the number of
3633 instructions it needs. */
3635 cost = mips_address_insns (addr, mode, true);
3638 *total = COSTS_N_INSNS (cost + 1);
3641 /* Check for a scaled indexed address. */
3642 if (mips_lwxs_address_p (addr))
3644 *total = COSTS_N_INSNS (2);
3647 /* Otherwise use the default handling. */
3651 *total = COSTS_N_INSNS (6);
3655 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3659 /* Check for a *clear_upper32 pattern and treat it like a zero
3660 extension. See the pattern's comment for details. */
3663 && CONST_INT_P (XEXP (x, 1))
3664 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3666 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3667 + rtx_cost (XEXP (x, 0), SET, speed));
3674 /* Double-word operations use two single-word operations. */
3675 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3684 if (CONSTANT_P (XEXP (x, 1)))
3685 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3688 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3694 *total = mips_cost->fp_add;
3696 *total = COSTS_N_INSNS (4);
3700 /* Low-part immediates need an extended MIPS16 instruction. */
3701 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3702 + rtx_cost (XEXP (x, 0), SET, speed));
3717 /* Branch comparisons have VOIDmode, so use the first operand's
3719 mode = GET_MODE (XEXP (x, 0));
3720 if (FLOAT_MODE_P (mode))
3722 *total = mips_cost->fp_add;
3725 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3731 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3732 && TARGET_FUSED_MADD
3733 && !HONOR_NANS (mode)
3734 && !HONOR_SIGNED_ZEROS (mode))
3736 /* See if we can use NMADD or NMSUB. See mips.md for the
3737 associated patterns. */
3738 rtx op0 = XEXP (x, 0);
3739 rtx op1 = XEXP (x, 1);
3740 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3742 *total = (mips_fp_mult_cost (mode)
3743 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3744 + rtx_cost (XEXP (op0, 1), SET, speed)
3745 + rtx_cost (op1, SET, speed));
3748 if (GET_CODE (op1) == MULT)
3750 *total = (mips_fp_mult_cost (mode)
3751 + rtx_cost (op0, SET, speed)
3752 + rtx_cost (XEXP (op1, 0), SET, speed)
3753 + rtx_cost (XEXP (op1, 1), SET, speed));
3762 /* If this is part of a MADD or MSUB, treat the PLUS as
3765 && TARGET_FUSED_MADD
3766 && GET_CODE (XEXP (x, 0)) == MULT)
3769 *total = mips_cost->fp_add;
3773 /* Double-word operations require three single-word operations and
3774 an SLTU. The MIPS16 version then needs to move the result of
3775 the SLTU from $24 to a MIPS16 register. */
3776 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3777 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3783 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3784 && TARGET_FUSED_MADD
3785 && !HONOR_NANS (mode)
3786 && HONOR_SIGNED_ZEROS (mode))
3788 /* See if we can use NMADD or NMSUB. See mips.md for the
3789 associated patterns. */
3790 rtx op = XEXP (x, 0);
3791 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3792 && GET_CODE (XEXP (op, 0)) == MULT)
3794 *total = (mips_fp_mult_cost (mode)
3795 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3796 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3797 + rtx_cost (XEXP (op, 1), SET, speed));
3803 *total = mips_cost->fp_add;
3805 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3810 *total = mips_fp_mult_cost (mode);
3811 else if (mode == DImode && !TARGET_64BIT)
3812 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3813 where the mulsidi3 always includes an MFHI and an MFLO. */
3815 ? mips_cost->int_mult_si * 3 + 6
3816 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3818 *total = (ISA_HAS_MUL3 ? 1 : 2);
3819 else if (mode == DImode)
3820 *total = mips_cost->int_mult_di;
3822 *total = mips_cost->int_mult_si;
3826 /* Check for a reciprocal. */
3829 && flag_unsafe_math_optimizations
3830 && XEXP (x, 0) == CONST1_RTX (mode))
3832 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3833 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3834 division as being free. */
3835 *total = rtx_cost (XEXP (x, 1), SET, speed);
3837 *total = (mips_fp_div_cost (mode)
3838 + rtx_cost (XEXP (x, 1), SET, speed));
3847 *total = mips_fp_div_cost (mode);
3856 /* It is our responsibility to make division by a power of 2
3857 as cheap as 2 register additions if we want the division
3858 expanders to be used for such operations; see the setting
3859 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3860 should always produce shorter code than using
3861 expand_sdiv2_pow2. */
3863 && CONST_INT_P (XEXP (x, 1))
3864 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3866 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3869 *total = COSTS_N_INSNS (mips_idiv_insns ());
3871 else if (mode == DImode)
3872 *total = mips_cost->int_div_di;
3874 *total = mips_cost->int_div_si;
3878 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3882 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3886 case UNSIGNED_FLOAT:
3889 case FLOAT_TRUNCATE:
3890 *total = mips_cost->fp_add;
3898 /* Implement TARGET_ADDRESS_COST. */
3901 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3903 return mips_address_insns (addr, SImode, false);
3906 /* Information about a single instruction in a multi-instruction
3908 struct mips_multi_member {
3909 /* True if this is a label, false if it is code. */
3912 /* The output_asm_insn format of the instruction. */
3915 /* The operands to the instruction. */
3916 rtx operands[MAX_RECOG_OPERANDS];
3918 typedef struct mips_multi_member mips_multi_member;
3920 /* Vector definitions for the above. */
3921 DEF_VEC_O(mips_multi_member);
3922 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3924 /* The instructions that make up the current multi-insn sequence. */
3925 static VEC (mips_multi_member, heap) *mips_multi_members;
3927 /* How many instructions (as opposed to labels) are in the current
3928 multi-insn sequence. */
3929 static unsigned int mips_multi_num_insns;
3931 /* Start a new multi-insn sequence. */
3934 mips_multi_start (void)
3936 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3937 mips_multi_num_insns = 0;
3940 /* Add a new, uninitialized member to the current multi-insn sequence. */
3942 static struct mips_multi_member *
3943 mips_multi_add (void)
3945 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3948 /* Add a normal insn with the given asm format to the current multi-insn
3949 sequence. The other arguments are a null-terminated list of operands. */
3952 mips_multi_add_insn (const char *format, ...)
3954 struct mips_multi_member *member;
3959 member = mips_multi_add ();
3960 member->is_label_p = false;
3961 member->format = format;
3962 va_start (ap, format);
3964 while ((op = va_arg (ap, rtx)))
3965 member->operands[i++] = op;
3967 mips_multi_num_insns++;
3970 /* Add the given label definition to the current multi-insn sequence.
3971 The definition should include the colon. */
3974 mips_multi_add_label (const char *label)
3976 struct mips_multi_member *member;
3978 member = mips_multi_add ();
3979 member->is_label_p = true;
3980 member->format = label;
3983 /* Return the index of the last member of the current multi-insn sequence. */
3986 mips_multi_last_index (void)
3988 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3991 /* Add a copy of an existing instruction to the current multi-insn
3992 sequence. I is the index of the instruction that should be copied. */
3995 mips_multi_copy_insn (unsigned int i)
3997 struct mips_multi_member *member;
3999 member = mips_multi_add ();
4000 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
4002 gcc_assert (!member->is_label_p);
4005 /* Change the operand of an existing instruction in the current
4006 multi-insn sequence. I is the index of the instruction,
4007 OP is the index of the operand, and X is the new value. */
4010 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4012 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
4015 /* Write out the asm code for the current multi-insn sequence. */
4018 mips_multi_write (void)
4020 struct mips_multi_member *member;
4023 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4024 if (member->is_label_p)
4025 fprintf (asm_out_file, "%s\n", member->format);
4027 output_asm_insn (member->format, member->operands);
4030 /* Return one word of double-word value OP, taking into account the fixed
4031 endianness of certain registers. HIGH_P is true to select the high part,
4032 false to select the low part. */
4035 mips_subword (rtx op, bool high_p)
4037 unsigned int byte, offset;
4038 enum machine_mode mode;
4040 mode = GET_MODE (op);
4041 if (mode == VOIDmode)
4042 mode = TARGET_64BIT ? TImode : DImode;
4044 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4045 byte = UNITS_PER_WORD;
4049 if (FP_REG_RTX_P (op))
4051 /* Paired FPRs are always ordered little-endian. */
4052 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4053 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4057 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4059 return simplify_gen_subreg (word_mode, op, mode, byte);
4062 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4065 mips_split_64bit_move_p (rtx dest, rtx src)
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