1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
58 /* Enumeration for all of the relational tests, so that we can build
59 arrays indexed by the test type, and not worry about the order
76 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
77 #define UNSPEC_ADDRESS_P(X) \
78 (GET_CODE (X) == UNSPEC \
79 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
80 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
82 /* Extract the symbol or label from UNSPEC wrapper X. */
83 #define UNSPEC_ADDRESS(X) \
86 /* Extract the symbol type from UNSPEC wrapper X. */
87 #define UNSPEC_ADDRESS_TYPE(X) \
88 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
90 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
91 to initialize the mips16 gp pseudo register. */
92 #define CONST_GP_P(X) \
93 (GET_CODE (X) == CONST \
94 && GET_CODE (XEXP (X, 0)) == UNSPEC \
95 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
97 /* The maximum distance between the top of the stack frame and the
98 value $sp has when we save & restore registers.
100 Use a maximum gap of 0x100 in the mips16 case. We can then use
101 unextended instructions to save and restore registers, and to
102 allocate and deallocate the top part of the frame.
104 The value in the !mips16 case must be a SMALL_OPERAND and must
105 preserve the maximum stack alignment. It could really be 0x7ff0,
106 but SGI's assemblers implement daddiu $sp,$sp,-0x7ff0 as a
107 multi-instruction addu sequence. Use 0x7fe0 to work around this. */
108 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
111 /* Classifies an address.
114 A natural register + offset address. The register satisfies
115 mips_valid_base_register_p and the offset is a const_arith_operand.
118 A LO_SUM rtx. The first operand is a valid base register and
119 the second operand is a symbolic address.
122 A signed 16-bit constant address.
125 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
126 enum mips_address_type {
133 /* A function to save or store a register. The first argument is the
134 register and the second is the stack slot. */
135 typedef void (*mips_save_restore_fn) (rtx, rtx);
137 struct mips16_constant;
138 struct mips_arg_info;
139 struct mips_address_info;
140 struct mips_integer_op;
142 static enum mips_symbol_type mips_classify_symbol (rtx);
143 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
144 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
145 static bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
146 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
147 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
148 static bool mips_classify_address (struct mips_address_info *, rtx,
149 enum machine_mode, int);
150 static int mips_symbol_insns (enum mips_symbol_type);
151 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
152 static rtx mips_force_temporary (rtx, rtx);
153 static rtx mips_split_symbol (rtx, rtx);
154 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
155 static rtx mips_add_offset (rtx, HOST_WIDE_INT);
156 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
157 static unsigned int mips_build_lower (struct mips_integer_op *,
158 unsigned HOST_WIDE_INT);
159 static unsigned int mips_build_integer (struct mips_integer_op *,
160 unsigned HOST_WIDE_INT);
161 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
162 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
163 static int m16_check_op (rtx, int, int, int);
164 static bool mips_rtx_costs (rtx, int, int, int *);
165 static int mips_address_cost (rtx);
166 static enum internal_test map_test_to_internal_test (enum rtx_code);
167 static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
169 static void mips_load_call_address (rtx, rtx, int);
170 static bool mips_function_ok_for_sibcall (tree, tree);
171 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
172 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
173 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
174 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
175 tree, int, struct mips_arg_info *);
176 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
177 static void mips_set_architecture (const struct mips_cpu_info *);
178 static void mips_set_tune (const struct mips_cpu_info *);
179 static struct machine_function *mips_init_machine_status (void);
180 static void print_operand_reloc (FILE *, rtx, const char **);
181 static bool mips_assemble_integer (rtx, unsigned int, int);
182 static void mips_file_start (void);
183 static void mips_file_end (void);
184 static bool mips_rewrite_small_data_p (rtx);
185 static int small_data_pattern_1 (rtx *, void *);
186 static int mips_rewrite_small_data_1 (rtx *, void *);
187 static bool mips_function_has_gp_insn (void);
188 static unsigned int mips_global_pointer (void);
189 static bool mips_save_reg_p (unsigned int);
190 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
191 mips_save_restore_fn);
192 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
193 static void mips_output_cplocal (void);
194 static void mips_emit_loadgp (void);
195 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
196 static void mips_set_frame_expr (rtx);
197 static rtx mips_frame_set (rtx, rtx);
198 static void mips_save_reg (rtx, rtx);
199 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
200 static void mips_restore_reg (rtx, rtx);
201 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
202 HOST_WIDE_INT, tree);
203 static int symbolic_expression_p (rtx);
204 static void mips_select_rtx_section (enum machine_mode, rtx,
205 unsigned HOST_WIDE_INT);
206 static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
208 static bool mips_in_small_data_p (tree);
209 static void mips_encode_section_info (tree, rtx, int);
210 static int mips_fpr_return_fields (tree, tree *);
211 static bool mips_return_in_msb (tree);
212 static rtx mips_return_fpr_pair (enum machine_mode mode,
213 enum machine_mode mode1, HOST_WIDE_INT,
214 enum machine_mode mode2, HOST_WIDE_INT);
215 static rtx mips16_gp_pseudo_reg (void);
216 static void mips16_fp_args (FILE *, int, int);
217 static void build_mips16_function_stub (FILE *);
218 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
219 static void dump_constants (struct mips16_constant *, rtx);
220 static int mips16_insn_length (rtx);
221 static int mips16_rewrite_pool_refs (rtx *, void *);
222 static void mips16_lay_out_constants (void);
223 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
224 static void mips_avoid_hazards (void);
225 static void mips_reorg (void);
226 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
227 static bool mips_matching_cpu_name_p (const char *, const char *);
228 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
229 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
230 static int mips_adjust_cost (rtx, rtx, rtx, int);
231 static bool mips_return_in_memory (tree, tree);
232 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
233 static int mips_issue_rate (void);
234 static int mips_use_dfa_pipeline_interface (void);
235 static void mips_init_libfuncs (void);
236 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
238 static tree mips_build_builtin_va_list (void);
241 static void irix_asm_named_section_1 (const char *, unsigned int,
243 static void irix_asm_named_section (const char *, unsigned int);
244 static int irix_section_align_entry_eq (const void *, const void *);
245 static hashval_t irix_section_align_entry_hash (const void *);
246 static void irix_file_start (void);
247 static int irix_section_align_1 (void **, void *);
248 static void copy_file_data (FILE *, FILE *);
249 static void irix_file_end (void);
250 static unsigned int irix_section_type_flags (tree, const char *, int);
253 /* Structure to be filled in by compute_frame_size with register
254 save masks, and offsets for the current function. */
256 struct mips_frame_info GTY(())
258 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
259 HOST_WIDE_INT var_size; /* # bytes that variables take up */
260 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
261 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
262 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
263 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
264 unsigned int mask; /* mask of saved gp registers */
265 unsigned int fmask; /* mask of saved fp registers */
266 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
267 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
268 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
269 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
270 bool initialized; /* true if frame size already calculated */
271 int num_gp; /* number of gp registers saved */
272 int num_fp; /* number of fp registers saved */
275 struct machine_function GTY(()) {
276 /* Pseudo-reg holding the address of the current function when
277 generating embedded PIC code. */
278 rtx embedded_pic_fnaddr_rtx;
280 /* Pseudo-reg holding the value of $28 in a mips16 function which
281 refers to GP relative global variables. */
282 rtx mips16_gp_pseudo_rtx;
284 /* Current frame information, calculated by compute_frame_size. */
285 struct mips_frame_info frame;
287 /* The register to use as the global pointer within this function. */
288 unsigned int global_pointer;
290 /* True if mips_adjust_insn_length should ignore an instruction's
292 bool ignore_hazard_length_p;
294 /* True if the whole function is suitable for .set noreorder and
296 bool all_noreorder_p;
298 /* True if the function is known to have an instruction that needs $gp. */
302 /* Information about a single argument. */
305 /* True if the argument is passed in a floating-point register, or
306 would have been if we hadn't run out of registers. */
309 /* The argument's size, in bytes. */
310 unsigned int num_bytes;
312 /* The number of words passed in registers, rounded up. */
313 unsigned int reg_words;
315 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
316 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
318 unsigned int reg_offset;
320 /* The number of words that must be passed on the stack, rounded up. */
321 unsigned int stack_words;
323 /* The offset from the start of the stack overflow area of the argument's
324 first stack word. Only meaningful when STACK_WORDS is nonzero. */
325 unsigned int stack_offset;
329 /* Information about an address described by mips_address_type.
335 REG is the base register and OFFSET is the constant offset.
338 REG is the register that contains the high part of the address,
339 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
340 is the type of OFFSET's symbol.
343 SYMBOL_TYPE is the type of symbol being referenced. */
345 struct mips_address_info
347 enum mips_address_type type;
350 enum mips_symbol_type symbol_type;
354 /* One stage in a constant building sequence. These sequences have
358 A = A CODE[1] VALUE[1]
359 A = A CODE[2] VALUE[2]
362 where A is an accumulator, each CODE[i] is a binary rtl operation
363 and each VALUE[i] is a constant integer. */
364 struct mips_integer_op {
366 unsigned HOST_WIDE_INT value;
370 /* The largest number of operations needed to load an integer constant.
371 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
372 When the lowest bit is clear, we can try, but reject a sequence with
373 an extra SLL at the end. */
374 #define MIPS_MAX_INTEGER_OPS 7
377 /* Global variables for machine-dependent things. */
379 /* Threshold for data being put into the small data/bss area, instead
380 of the normal data area. */
381 int mips_section_threshold = -1;
383 /* Count the number of .file directives, so that .loc is up to date. */
384 int num_source_filenames = 0;
386 /* Count the number of sdb related labels are generated (to find block
387 start and end boundaries). */
388 int sdb_label_count = 0;
390 /* Next label # for each statement for Silicon Graphics IRIS systems. */
393 /* Linked list of all externals that are to be emitted when optimizing
394 for the global pointer if they haven't been declared by the end of
395 the program with an appropriate .comm or initialization. */
397 struct extern_list GTY (())
399 struct extern_list *next; /* next external */
400 const char *name; /* name of the external */
401 int size; /* size in bytes */
404 static GTY (()) struct extern_list *extern_head = 0;
406 /* Name of the file containing the current function. */
407 const char *current_function_file = "";
409 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
415 /* The next branch instruction is a branch likely, not branch normal. */
416 int mips_branch_likely;
418 /* Cached operands, and operator to compare for use in set/branch/trap
419 on condition codes. */
422 /* what type of branch to use */
423 enum cmp_type branch_type;
425 /* The target cpu for code generation. */
426 enum processor_type mips_arch;
427 const struct mips_cpu_info *mips_arch_info;
429 /* The target cpu for optimization and scheduling. */
430 enum processor_type mips_tune;
431 const struct mips_cpu_info *mips_tune_info;
433 /* Which instruction set architecture to use. */
436 /* Which ABI to use. */
439 /* Strings to hold which cpu and instruction set architecture to use. */
440 const char *mips_arch_string; /* for -march=<xxx> */
441 const char *mips_tune_string; /* for -mtune=<xxx> */
442 const char *mips_isa_string; /* for -mips{1,2,3,4} */
443 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
445 /* Whether we are generating mips16 hard float code. In mips16 mode
446 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
447 -msoft-float was not specified by the user, which means that we
448 should arrange to call mips32 hard floating point code. */
449 int mips16_hard_float;
451 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
453 /* If TRUE, we split addresses into their high and low parts in the RTL. */
454 int mips_split_addresses;
456 /* Mode used for saving/restoring general purpose registers. */
457 static enum machine_mode gpr_mode;
459 /* Array giving truth value on whether or not a given hard register
460 can support a given mode. */
461 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
463 /* List of all MIPS punctuation characters used by print_operand. */
464 char mips_print_operand_punct[256];
466 /* Map GCC register number to debugger register number. */
467 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
469 /* A copy of the original flag_delayed_branch: see override_options. */
470 static int mips_flag_delayed_branch;
472 static GTY (()) int mips_output_filename_first_time = 1;
474 /* mips_split_p[X] is true if symbols of type X can be split by
475 mips_split_symbol(). */
476 static bool mips_split_p[NUM_SYMBOL_TYPES];
478 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
479 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
480 if they are matched by a special .md file pattern. */
481 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
483 /* Likewise for HIGHs. */
484 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
486 /* Hardware names for the registers. If -mrnames is used, this
487 will be overwritten with mips_sw_reg_names. */
489 char mips_reg_names[][8] =
491 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
492 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
493 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
494 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
495 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
496 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
497 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
498 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
499 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
500 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec",
501 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
502 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
503 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
504 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
505 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
506 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
507 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
508 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
509 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
510 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
511 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
512 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
515 /* Mips software names for the registers, used to overwrite the
516 mips_reg_names array. */
518 char mips_sw_reg_names[][8] =
520 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
521 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
522 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
523 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
524 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
525 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
526 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
527 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
528 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
529 "$fcc5","$fcc6","$fcc7","$rap", "", "$arg", "$frame", "$fakec",
530 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
531 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
532 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
533 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
534 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
535 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
536 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
537 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
538 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
539 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
540 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
541 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
544 /* Map hard register number to register class */
545 const enum reg_class mips_regno_to_class[] =
547 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
548 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
549 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
550 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
551 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
552 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
553 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
554 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
555 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
556 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
557 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
558 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
559 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
560 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
561 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
562 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
563 HI_REG, LO_REG, NO_REGS, ST_REGS,
564 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
565 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
566 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
567 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
568 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
569 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
570 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
571 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
572 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
573 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
574 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
575 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
576 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
577 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
578 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
579 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
580 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
581 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
582 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
583 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
584 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
585 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
586 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
587 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
588 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
589 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
590 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
593 /* Map register constraint character to register class. */
594 enum reg_class mips_char_to_class[256];
596 /* A table describing all the processors gcc knows about. Names are
597 matched in the order listed. The first mention of an ISA level is
598 taken as the canonical name for that ISA.
600 To ease comparison, please keep this table in the same order as
601 gas's mips_cpu_info_table[]. */
602 const struct mips_cpu_info mips_cpu_info_table[] = {
603 /* Entries for generic ISAs */
604 { "mips1", PROCESSOR_R3000, 1 },
605 { "mips2", PROCESSOR_R6000, 2 },
606 { "mips3", PROCESSOR_R4000, 3 },
607 { "mips4", PROCESSOR_R8000, 4 },
608 { "mips32", PROCESSOR_4KC, 32 },
609 { "mips32r2", PROCESSOR_M4K, 33 },
610 { "mips64", PROCESSOR_5KC, 64 },
613 { "r3000", PROCESSOR_R3000, 1 },
614 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
615 { "r3900", PROCESSOR_R3900, 1 },
618 { "r6000", PROCESSOR_R6000, 2 },
621 { "r4000", PROCESSOR_R4000, 3 },
622 { "vr4100", PROCESSOR_R4100, 3 },
623 { "vr4111", PROCESSOR_R4111, 3 },
624 { "vr4120", PROCESSOR_R4120, 3 },
625 { "vr4130", PROCESSOR_R4130, 3 },
626 { "vr4300", PROCESSOR_R4300, 3 },
627 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
628 { "r4600", PROCESSOR_R4600, 3 },
629 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
630 { "r4650", PROCESSOR_R4650, 3 },
633 { "r8000", PROCESSOR_R8000, 4 },
634 { "vr5000", PROCESSOR_R5000, 4 },
635 { "vr5400", PROCESSOR_R5400, 4 },
636 { "vr5500", PROCESSOR_R5500, 4 },
637 { "rm7000", PROCESSOR_R7000, 4 },
638 { "rm9000", PROCESSOR_R9000, 4 },
641 { "4kc", PROCESSOR_4KC, 32 },
642 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
644 /* MIPS32 Release 2 */
645 { "m4k", PROCESSOR_M4K, 33 },
648 { "5kc", PROCESSOR_5KC, 64 },
649 { "20kc", PROCESSOR_20KC, 64 },
650 { "sb1", PROCESSOR_SB1, 64 },
651 { "sr71000", PROCESSOR_SR71000, 64 },
657 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
658 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
659 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
662 /* Initialize the GCC target structure. */
663 #undef TARGET_ASM_ALIGNED_HI_OP
664 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
665 #undef TARGET_ASM_ALIGNED_SI_OP
666 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
667 #undef TARGET_ASM_INTEGER
668 #define TARGET_ASM_INTEGER mips_assemble_integer
670 #undef TARGET_ASM_FUNCTION_PROLOGUE
671 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
672 #undef TARGET_ASM_FUNCTION_EPILOGUE
673 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
674 #undef TARGET_ASM_SELECT_RTX_SECTION
675 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
677 #undef TARGET_SCHED_ADJUST_COST
678 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
679 #undef TARGET_SCHED_ISSUE_RATE
680 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
681 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
682 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
684 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
685 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
687 #undef TARGET_VALID_POINTER_MODE
688 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
689 #undef TARGET_RTX_COSTS
690 #define TARGET_RTX_COSTS mips_rtx_costs
691 #undef TARGET_ADDRESS_COST
692 #define TARGET_ADDRESS_COST mips_address_cost
694 #undef TARGET_ENCODE_SECTION_INFO
695 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
696 #undef TARGET_IN_SMALL_DATA_P
697 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
699 #undef TARGET_MACHINE_DEPENDENT_REORG
700 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
702 #undef TARGET_ASM_FILE_START
703 #undef TARGET_ASM_FILE_END
705 #define TARGET_ASM_FILE_START irix_file_start
706 #define TARGET_ASM_FILE_END irix_file_end
708 #define TARGET_ASM_FILE_START mips_file_start
709 #define TARGET_ASM_FILE_END mips_file_end
711 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
712 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
715 #undef TARGET_SECTION_TYPE_FLAGS
716 #define TARGET_SECTION_TYPE_FLAGS irix_section_type_flags
719 #undef TARGET_INIT_LIBFUNCS
720 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
722 #undef TARGET_BUILD_BUILTIN_VA_LIST
723 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
725 #undef TARGET_PROMOTE_FUNCTION_ARGS
726 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
727 #undef TARGET_PROMOTE_FUNCTION_RETURN
728 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
729 #undef TARGET_PROMOTE_PROTOTYPES
730 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
732 #undef TARGET_RETURN_IN_MEMORY
733 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
734 #undef TARGET_RETURN_IN_MSB
735 #define TARGET_RETURN_IN_MSB mips_return_in_msb
737 #undef TARGET_ASM_OUTPUT_MI_THUNK
738 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
739 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
740 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
742 #undef TARGET_SETUP_INCOMING_VARARGS
743 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
744 #undef TARGET_STRICT_ARGUMENT_NAMING
745 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
747 struct gcc_target targetm = TARGET_INITIALIZER;
749 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
751 static enum mips_symbol_type
752 mips_classify_symbol (rtx x)
754 if (GET_CODE (x) == LABEL_REF)
757 return SYMBOL_CONSTANT_POOL;
759 return SYMBOL_GOT_LOCAL;
760 return SYMBOL_GENERAL;
763 if (GET_CODE (x) != SYMBOL_REF)
766 if (CONSTANT_POOL_ADDRESS_P (x))
769 return SYMBOL_CONSTANT_POOL;
772 return SYMBOL_GOT_LOCAL;
774 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
775 return SYMBOL_SMALL_DATA;
777 return SYMBOL_GENERAL;
780 if (SYMBOL_REF_SMALL_P (x))
781 return SYMBOL_SMALL_DATA;
785 if (SYMBOL_REF_DECL (x) == 0)
786 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
788 /* There are three cases to consider:
790 - o32 PIC (either with or without explicit relocs)
791 - n32/n64 PIC without explicit relocs
792 - n32/n64 PIC with explicit relocs
794 In the first case, both local and global accesses will use an
795 R_MIPS_GOT16 relocation. We must correctly predict which of
796 the two semantics (local or global) the assembler and linker
797 will apply. The choice doesn't depend on the symbol's
798 visibility, so we deliberately ignore decl_visibility and
801 In the second case, the assembler will not use R_MIPS_GOT16
802 relocations, but it chooses between local and global accesses
803 in the same way as for o32 PIC.
805 In the third case we have more freedom since both forms of
806 access will work for any kind of symbol. However, there seems
807 little point in doing things differently. */
808 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
809 return SYMBOL_GOT_GLOBAL;
811 return SYMBOL_GOT_LOCAL;
814 return SYMBOL_GENERAL;
818 /* Split X into a base and a constant offset, storing them in *BASE
819 and *OFFSET respectively. */
822 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
826 if (GET_CODE (x) == CONST)
829 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
831 *offset += INTVAL (XEXP (x, 1));
838 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
839 to the same object as SYMBOL. */
842 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
844 if (GET_CODE (symbol) != SYMBOL_REF)
847 if (CONSTANT_POOL_ADDRESS_P (symbol)
849 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
852 if (SYMBOL_REF_DECL (symbol) != 0
854 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
861 /* Return true if X is a symbolic constant that can be calculated in
862 the same way as a bare symbol. If it is, store the type of the
863 symbol in *SYMBOL_TYPE. */
866 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
868 HOST_WIDE_INT offset;
870 mips_split_const (x, &x, &offset);
871 if (UNSPEC_ADDRESS_P (x))
872 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
873 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
874 *symbol_type = mips_classify_symbol (x);
881 /* Check whether a nonzero offset is valid for the underlying
883 switch (*symbol_type)
889 /* If the target has 64-bit pointers and the object file only
890 supports 32-bit symbols, the values of those symbols will be
891 sign-extended. In this case we can't allow an arbitrary offset
892 in case the 32-bit value X + OFFSET has a different sign from X. */
893 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
894 return mips_offset_within_object_p (x, offset);
896 /* In other cases the relocations can handle any offset. */
899 case SYMBOL_CONSTANT_POOL:
900 /* Allow constant pool references to be converted to LABEL+CONSTANT.
901 In this case, we no longer have access to the underlying constant,
902 but the original symbol-based access was known to be valid. */
903 if (GET_CODE (x) == LABEL_REF)
908 case SYMBOL_SMALL_DATA:
909 /* Make sure that the offset refers to something within the
910 underlying object. This should guarantee that the final
911 PC- or GP-relative offset is within the 16-bit limit. */
912 return mips_offset_within_object_p (x, offset);
914 case SYMBOL_GOT_LOCAL:
915 case SYMBOL_GOTOFF_PAGE:
916 /* The linker should provide enough local GOT entries for a
917 16-bit offset. Larger offsets may lead to GOT overflow. */
918 return SMALL_OPERAND (offset);
920 case SYMBOL_GOT_GLOBAL:
921 case SYMBOL_GOTOFF_GLOBAL:
922 case SYMBOL_GOTOFF_CALL:
923 case SYMBOL_GOTOFF_LOADGP:
930 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
933 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
935 if (regno >= FIRST_PSEUDO_REGISTER)
939 regno = reg_renumber[regno];
942 /* These fake registers will be eliminated to either the stack or
943 hard frame pointer, both of which are usually valid base registers.
944 Reload deals with the cases where the eliminated form isn't valid. */
945 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
948 /* In mips16 mode, the stack pointer can only address word and doubleword
949 values, nothing smaller. There are two problems here:
951 (a) Instantiating virtual registers can introduce new uses of the
952 stack pointer. If these virtual registers are valid addresses,
953 the stack pointer should be too.
955 (b) Most uses of the stack pointer are not made explicit until
956 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
957 We don't know until that stage whether we'll be eliminating to the
958 stack pointer (which needs the restriction) or the hard frame
959 pointer (which doesn't).
961 All in all, it seems more consistent to only enforce this restriction
962 during and after reload. */
963 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
964 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
966 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
970 /* Return true if X is a valid base register for the given mode.
971 Allow only hard registers if STRICT. */
974 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
976 if (!strict && GET_CODE (x) == SUBREG)
979 return (GET_CODE (x) == REG
980 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
984 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
985 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
988 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
989 enum machine_mode mode)
994 return !TARGET_MIPS16;
996 case SYMBOL_SMALL_DATA:
999 case SYMBOL_CONSTANT_POOL:
1000 /* PC-relative addressing is only available for lw and ld. */
1001 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1003 case SYMBOL_GOT_LOCAL:
1006 case SYMBOL_GOT_GLOBAL:
1007 /* The address will have to be loaded from the GOT first. */
1010 case SYMBOL_GOTOFF_PAGE:
1011 case SYMBOL_GOTOFF_GLOBAL:
1012 case SYMBOL_GOTOFF_CALL:
1013 case SYMBOL_GOTOFF_LOADGP:
1014 case SYMBOL_64_HIGH:
1023 /* Return true if X is a valid address for machine mode MODE. If it is,
1024 fill in INFO appropriately. STRICT is true if we should only accept
1025 hard base registers. */
1028 mips_classify_address (struct mips_address_info *info, rtx x,
1029 enum machine_mode mode, int strict)
1031 switch (GET_CODE (x))
1035 info->type = ADDRESS_REG;
1037 info->offset = const0_rtx;
1038 return mips_valid_base_register_p (info->reg, mode, strict);
1041 info->type = ADDRESS_REG;
1042 info->reg = XEXP (x, 0);
1043 info->offset = XEXP (x, 1);
1044 return (mips_valid_base_register_p (info->reg, mode, strict)
1045 && const_arith_operand (info->offset, VOIDmode));
1048 info->type = ADDRESS_LO_SUM;
1049 info->reg = XEXP (x, 0);
1050 info->offset = XEXP (x, 1);
1051 return (mips_valid_base_register_p (info->reg, mode, strict)
1052 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1053 && mips_symbolic_address_p (info->symbol_type, mode)
1054 && mips_lo_relocs[info->symbol_type] != 0);
1057 /* Small-integer addresses don't occur very often, but they
1058 are legitimate if $0 is a valid base register. */
1059 info->type = ADDRESS_CONST_INT;
1060 return !TARGET_MIPS16 && SMALL_INT (x);
1065 info->type = ADDRESS_SYMBOLIC;
1066 return (mips_symbolic_constant_p (x, &info->symbol_type)
1067 && mips_symbolic_address_p (info->symbol_type, mode)
1068 && !mips_split_p[info->symbol_type]);
1075 /* Return the number of instructions needed to load a symbol of the
1076 given type into a register. If valid in an address, the same number
1077 of instructions are needed for loads and stores. Treat extended
1078 mips16 instructions as two instructions. */
1081 mips_symbol_insns (enum mips_symbol_type type)
1085 case SYMBOL_GENERAL:
1086 /* In mips16 code, general symbols must be fetched from the
1091 /* When using 64-bit symbols, we need 5 preparatory instructions,
1094 lui $at,%highest(symbol)
1095 daddiu $at,$at,%higher(symbol)
1097 daddiu $at,$at,%hi(symbol)
1100 The final address is then $at + %lo(symbol). With 32-bit
1101 symbols we just need a preparatory lui. */
1102 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1104 case SYMBOL_SMALL_DATA:
1107 case SYMBOL_CONSTANT_POOL:
1108 /* This case is for mips16 only. Assume we'll need an
1109 extended instruction. */
1112 case SYMBOL_GOT_LOCAL:
1113 case SYMBOL_GOT_GLOBAL:
1114 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1115 the local/global classification is accurate. See override_options
1118 The worst cases are:
1120 (1) For local symbols when generating o32 or o64 code. The assembler
1126 ...and the final address will be $at + %lo(symbol).
1128 (2) For global symbols when -mxgot. The assembler will use:
1130 lui $at,%got_hi(symbol)
1133 ...and the final address will be $at + %got_lo(symbol). */
1136 case SYMBOL_GOTOFF_PAGE:
1137 case SYMBOL_GOTOFF_GLOBAL:
1138 case SYMBOL_GOTOFF_CALL:
1139 case SYMBOL_GOTOFF_LOADGP:
1140 case SYMBOL_64_HIGH:
1143 /* Check whether the offset is a 16- or 32-bit value. */
1144 return mips_split_p[type] ? 2 : 1;
1150 /* Return true if a value at OFFSET bytes from BASE can be accessed
1151 using an unextended mips16 instruction. MODE is the mode of the
1154 Usually the offset in an unextended instruction is a 5-bit field.
1155 The offset is unsigned and shifted left once for HIs, twice
1156 for SIs, and so on. An exception is SImode accesses off the
1157 stack pointer, which have an 8-bit immediate field. */
1160 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1163 && GET_CODE (offset) == CONST_INT
1164 && INTVAL (offset) >= 0
1165 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1167 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1168 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1169 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1175 /* Return the number of instructions needed to load or store a value
1176 of mode MODE at X. Return 0 if X isn't valid for MODE.
1178 For mips16 code, count extended instructions as two instructions. */
1181 mips_address_insns (rtx x, enum machine_mode mode)
1183 struct mips_address_info addr;
1186 if (mode == BLKmode)
1187 /* BLKmode is used for single unaligned loads and stores. */
1190 /* Each word of a multi-word value will be accessed individually. */
1191 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1193 if (mips_classify_address (&addr, x, mode, false))
1198 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1202 case ADDRESS_LO_SUM:
1203 return (TARGET_MIPS16 ? factor * 2 : factor);
1205 case ADDRESS_CONST_INT:
1208 case ADDRESS_SYMBOLIC:
1209 return factor * mips_symbol_insns (addr.symbol_type);
1215 /* Likewise for constant X. */
1218 mips_const_insns (rtx x)
1220 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1221 enum mips_symbol_type symbol_type;
1222 HOST_WIDE_INT offset;
1224 switch (GET_CODE (x))
1226 case CONSTANT_P_RTX:
1231 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1232 || !mips_split_p[symbol_type])
1239 /* Unsigned 8-bit constants can be loaded using an unextended
1240 LI instruction. Unsigned 16-bit constants can be loaded
1241 using an extended LI. Negative constants must be loaded
1242 using LI and then negated. */
1243 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1244 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1245 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1246 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1249 return mips_build_integer (codes, INTVAL (x));
1252 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1258 /* See if we can refer to X directly. */
1259 if (mips_symbolic_constant_p (x, &symbol_type))
1260 return mips_symbol_insns (symbol_type);
1262 /* Otherwise try splitting the constant into a base and offset.
1263 16-bit offsets can be added using an extra addiu. Larger offsets
1264 must be calculated separately and then added to the base. */
1265 mips_split_const (x, &x, &offset);
1268 int n = mips_const_insns (x);
1271 if (SMALL_OPERAND (offset))
1274 return n + 1 + mips_build_integer (codes, offset);
1281 return mips_symbol_insns (mips_classify_symbol (x));
1289 /* Return the number of instructions needed for memory reference X.
1290 Count extended mips16 instructions as two instructions. */
1293 mips_fetch_insns (rtx x)
1295 if (GET_CODE (x) != MEM)
1298 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1302 /* Return the number of instructions needed for an integer division. */
1305 mips_idiv_insns (void)
1310 if (TARGET_CHECK_ZERO_DIV)
1312 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1318 /* Return truth value of whether OP can be used as an operands
1319 where a register or 16 bit unsigned integer is needed. */
1322 uns_arith_operand (rtx op, enum machine_mode mode)
1324 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1327 return register_operand (op, mode);
1331 /* True if OP can be treated as a signed 16-bit constant. */
1334 const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1336 return GET_CODE (op) == CONST_INT && SMALL_INT (op);
1340 /* Return true if OP is a register operand or a signed 16-bit constant. */
1343 arith_operand (rtx op, enum machine_mode mode)
1345 return const_arith_operand (op, mode) || register_operand (op, mode);
1348 /* Return truth value of whether OP is an integer which fits in 16 bits. */
1351 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1353 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1356 /* Return truth value of whether OP is a register or the constant 0.
1357 Do not accept 0 in mips16 mode since $0 is not one of the core 8
1361 reg_or_0_operand (rtx op, enum machine_mode mode)
1363 switch (GET_CODE (op))
1368 return INTVAL (op) == 0;
1373 return op == CONST0_RTX (mode);
1376 return register_operand (op, mode);
1380 /* Accept a register or the floating point constant 1 in the appropriate mode. */
1383 reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
1387 switch (GET_CODE (op))
1390 if (mode != GET_MODE (op)
1391 || (mode != DFmode && mode != SFmode))
1394 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1395 return REAL_VALUES_EQUAL (d, dconst1);
1398 return register_operand (op, mode);
1402 /* Accept the floating point constant 1 in the appropriate mode. */
1405 const_float_1_operand (rtx op, enum machine_mode mode)
1409 if (GET_CODE (op) != CONST_DOUBLE
1410 || mode != GET_MODE (op)
1411 || (mode != DFmode && mode != SFmode))
1414 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1416 return REAL_VALUES_EQUAL (d, dconst1);
1419 /* Return true if OP is either the HI or LO register. */
1422 hilo_operand (rtx op, enum machine_mode mode)
1424 return ((mode == VOIDmode || mode == GET_MODE (op))
1425 && REG_P (op) && MD_REG_P (REGNO (op)));
1428 /* Return true if OP is an extension operator. */
1431 extend_operator (rtx op, enum machine_mode mode)
1433 return ((mode == VOIDmode || mode == GET_MODE (op))
1434 && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
1437 /* Return true if X is the right hand side of a "macc" or "msac" instruction.
1438 This predicate is intended for use in peephole optimizations. */
1441 macc_msac_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1443 if (ISA_HAS_MACC && GET_CODE (x) == PLUS && REG_P (XEXP (x, 1)))
1445 else if (ISA_HAS_MSAC && GET_CODE (x) == MINUS && REG_P (XEXP (x, 0)))
1450 return GET_CODE (x) == MULT && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1));
1453 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1456 equality_op (rtx op, enum machine_mode mode)
1458 if (mode != GET_MODE (op))
1461 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1464 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1467 cmp_op (rtx op, enum machine_mode mode)
1469 if (mode != GET_MODE (op))
1472 return COMPARISON_P (op);
1475 /* Return nonzero if the code is a relational operation suitable for a
1476 conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
1477 We need this in the insn that expands `trap_if' in order to prevent
1478 combine from erroneously altering the condition. */
1481 trap_cmp_op (rtx op, enum machine_mode mode)
1483 if (mode != GET_MODE (op))
1486 switch (GET_CODE (op))
1501 /* Return nonzero if the operand is either the PC or a label_ref. */
1504 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1509 if (GET_CODE (op) == LABEL_REF)
1515 /* Test for a valid call address. */
1518 call_insn_operand (rtx op, enum machine_mode mode)
1520 enum mips_symbol_type symbol_type;
1522 if (mips_symbolic_constant_p (op, &symbol_type))
1523 switch (symbol_type)
1525 case SYMBOL_GENERAL:
1526 /* If -mlong-calls, force all calls to use register addressing. */
1527 return !TARGET_LONG_CALLS;
1529 case SYMBOL_GOT_GLOBAL:
1530 /* Without explicit relocs, there is no special syntax for
1531 loading the address of a call destination into a register.
1532 Using "la $25,foo; jal $25" would prevent the lazy binding
1533 of "foo", so keep the address of global symbols with the
1535 return !TARGET_EXPLICIT_RELOCS;
1540 return register_operand (op, mode);
1544 /* Return nonzero if OP is valid as a source operand for a move
1548 move_operand (rtx op, enum machine_mode mode)
1550 enum mips_symbol_type symbol_type;
1552 if (!general_operand (op, mode))
1555 switch (GET_CODE (op))
1558 /* When generating mips16 code, LEGITIMATE_CONSTANT_P rejects
1559 CONST_INTs that can't be loaded using simple insns. */
1563 /* When generating 32-bit code, allow DImode move_operands to
1564 match arbitrary constants. We split them after reload. */
1565 if (!TARGET_64BIT && mode == DImode)
1568 /* Otherwise check whether the constant can be loaded in a single
1570 return LUI_INT (op) || SMALL_INT (op) || SMALL_INT_UNSIGNED (op);
1575 if (CONST_GP_P (op))
1578 return (mips_symbolic_constant_p (op, &symbol_type)
1579 && !mips_split_p[symbol_type]);
1587 /* Accept any operand that can appear in a mips16 constant table
1588 instruction. We can't use any of the standard operand functions
1589 because for these instructions we accept values that are not
1590 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1593 consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1595 return CONSTANT_P (op);
1598 /* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1599 possibly with an offset. */
1602 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1604 enum mips_symbol_type symbol_type;
1606 return mips_symbolic_constant_p (op, &symbol_type);
1610 /* Return true if OP is a symbolic constant of type SYMBOL_GENERAL. */
1613 general_symbolic_operand (rtx op, enum machine_mode mode)
1615 enum mips_symbol_type symbol_type;
1617 return ((mode == VOIDmode || mode == GET_MODE (op))
1618 && mips_symbolic_constant_p (op, &symbol_type)
1619 && symbol_type == SYMBOL_GENERAL);
1623 /* Return true if we're generating PIC and OP is a global symbol. */
1626 global_got_operand (rtx op, enum machine_mode mode)
1628 enum mips_symbol_type symbol_type;
1630 return ((mode == VOIDmode || mode == GET_MODE (op))
1631 && mips_symbolic_constant_p (op, &symbol_type)
1632 && symbol_type == SYMBOL_GOT_GLOBAL);
1636 /* Likewise for local symbols. */
1639 local_got_operand (rtx op, enum machine_mode mode)
1641 enum mips_symbol_type symbol_type;
1643 return ((mode == VOIDmode || mode == GET_MODE (op))
1644 && mips_symbolic_constant_p (op, &symbol_type)
1645 && symbol_type == SYMBOL_GOT_LOCAL);
1649 /* Return true if OP is a memory reference that uses the stack pointer
1650 as a base register. */
1653 stack_operand (rtx op, enum machine_mode mode)
1655 struct mips_address_info addr;
1657 return ((mode == VOIDmode || mode == GET_MODE (op))
1658 && GET_CODE (op) == MEM
1659 && mips_classify_address (&addr, XEXP (op, 0), GET_MODE (op), false)
1660 && addr.type == ADDRESS_REG
1661 && addr.reg == stack_pointer_rtx);
1665 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1666 returns a nonzero value if X is a legitimate address for a memory
1667 operand of the indicated MODE. STRICT is nonzero if this function
1668 is called during reload. */
1671 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1673 struct mips_address_info addr;
1675 return mips_classify_address (&addr, x, mode, strict);
1679 /* Copy VALUE to a register and return that register. If new psuedos
1680 are allowed, copy it into a new register, otherwise use DEST. */
1683 mips_force_temporary (rtx dest, rtx value)
1685 if (!no_new_pseudos)
1686 return force_reg (Pmode, value);
1689 emit_move_insn (copy_rtx (dest), value);
1695 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1696 and is used to load the high part into a register. */
1699 mips_split_symbol (rtx temp, rtx addr)
1704 high = mips16_gp_pseudo_reg ();
1706 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1707 return gen_rtx_LO_SUM (Pmode, high, addr);
1711 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1712 type SYMBOL_TYPE. */
1715 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1718 HOST_WIDE_INT offset;
1720 mips_split_const (address, &base, &offset);
1721 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1722 UNSPEC_ADDRESS_FIRST + symbol_type);
1723 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1727 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1728 high part to BASE and return the result. Just return BASE otherwise.
1729 TEMP is available as a temporary register if needed.
1731 The returned expression can be used as the first operand to a LO_SUM. */
1734 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1735 enum mips_symbol_type symbol_type)
1737 if (mips_split_p[symbol_type])
1739 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1740 addr = mips_force_temporary (temp, addr);
1741 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1747 /* Return a legitimate address for REG + OFFSET. This function will
1748 create a temporary register if OFFSET is not a SMALL_OPERAND. */
1751 mips_add_offset (rtx reg, HOST_WIDE_INT offset)
1753 if (!SMALL_OPERAND (offset))
1754 reg = expand_simple_binop (GET_MODE (reg), PLUS,
1755 GEN_INT (CONST_HIGH_PART (offset)),
1756 reg, NULL, 0, OPTAB_WIDEN);
1758 return plus_constant (reg, CONST_LOW_PART (offset));
1762 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1763 be legitimized in a way that the generic machinery might not expect,
1764 put the new address in *XLOC and return true. MODE is the mode of
1765 the memory being accessed. */
1768 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1770 enum mips_symbol_type symbol_type;
1772 /* See if the address can split into a high part and a LO_SUM. */
1773 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1774 && mips_symbolic_address_p (symbol_type, mode)
1775 && mips_split_p[symbol_type])
1777 *xloc = mips_split_symbol (0, *xloc);
1781 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1783 /* Handle REG + CONSTANT using mips_add_offset. */
1786 reg = XEXP (*xloc, 0);
1787 if (!mips_valid_base_register_p (reg, mode, 0))
1788 reg = copy_to_mode_reg (Pmode, reg);
1789 *xloc = mips_add_offset (reg, INTVAL (XEXP (*xloc, 1)));
1797 /* Subroutine of mips_build_integer (with the same interface).
1798 Assume that the final action in the sequence should be a left shift. */
1801 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1803 unsigned int i, shift;
1805 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1806 since signed numbers are easier to load than unsigned ones. */
1808 while ((value & 1) == 0)
1809 value /= 2, shift++;
1811 i = mips_build_integer (codes, value);
1812 codes[i].code = ASHIFT;
1813 codes[i].value = shift;
1818 /* As for mips_build_shift, but assume that the final action will be
1819 an IOR or PLUS operation. */
1822 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1824 unsigned HOST_WIDE_INT high;
1827 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1828 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1830 /* The constant is too complex to load with a simple lui/ori pair
1831 so our goal is to clear as many trailing zeros as possible.
1832 In this case, we know bit 16 is set and that the low 16 bits
1833 form a negative number. If we subtract that number from VALUE,
1834 we will clear at least the lowest 17 bits, maybe more. */
1835 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1836 codes[i].code = PLUS;
1837 codes[i].value = CONST_LOW_PART (value);
1841 i = mips_build_integer (codes, high);
1842 codes[i].code = IOR;
1843 codes[i].value = value & 0xffff;
1849 /* Fill CODES with a sequence of rtl operations to load VALUE.
1850 Return the number of operations needed. */
1853 mips_build_integer (struct mips_integer_op *codes,
1854 unsigned HOST_WIDE_INT value)
1856 if (SMALL_OPERAND (value)
1857 || SMALL_OPERAND_UNSIGNED (value)
1858 || LUI_OPERAND (value))
1860 /* The value can be loaded with a single instruction. */
1861 codes[0].code = NIL;
1862 codes[0].value = value;
1865 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1867 /* Either the constant is a simple LUI/ORI combination or its
1868 lowest bit is set. We don't want to shift in this case. */
1869 return mips_build_lower (codes, value);
1871 else if ((value & 0xffff) == 0)
1873 /* The constant will need at least three actions. The lowest
1874 16 bits are clear, so the final action will be a shift. */
1875 return mips_build_shift (codes, value);
1879 /* The final action could be a shift, add or inclusive OR.
1880 Rather than use a complex condition to select the best
1881 approach, try both mips_build_shift and mips_build_lower
1882 and pick the one that gives the shortest sequence.
1883 Note that this case is only used once per constant. */
1884 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1885 unsigned int cost, alt_cost;
1887 cost = mips_build_shift (codes, value);
1888 alt_cost = mips_build_lower (alt_codes, value);
1889 if (alt_cost < cost)
1891 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1899 /* Move VALUE into register DEST. */
1902 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1904 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1905 enum machine_mode mode;
1906 unsigned int i, cost;
1909 mode = GET_MODE (dest);
1910 cost = mips_build_integer (codes, value);
1912 /* Apply each binary operation to X. Invariant: X is a legitimate
1913 source operand for a SET pattern. */
1914 x = GEN_INT (codes[0].value);
1915 for (i = 1; i < cost; i++)
1918 emit_move_insn (dest, x), x = dest;
1920 x = force_reg (mode, x);
1921 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1924 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1928 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1929 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1933 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1936 HOST_WIDE_INT offset;
1937 enum mips_symbol_type symbol_type;
1939 /* Split moves of big integers into smaller pieces. In mips16 code,
1940 it's better to force the constant into memory instead. */
1941 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1943 mips_move_integer (dest, INTVAL (src));
1947 /* See if the symbol can be split. For mips16, this is often worse than
1948 forcing it in the constant pool since it needs the single-register form
1949 of addiu or daddiu. */
1951 && mips_symbolic_constant_p (src, &symbol_type)
1952 && mips_split_p[symbol_type])
1954 emit_move_insn (dest, mips_split_symbol (dest, src));
1958 /* If we have (const (plus symbol offset)), load the symbol first
1959 and then add in the offset. This is usually better than forcing
1960 the constant into memory, at least in non-mips16 code. */
1961 mips_split_const (src, &base, &offset);
1964 && (!no_new_pseudos || SMALL_OPERAND (offset)))
1966 base = mips_force_temporary (dest, base);
1967 emit_move_insn (dest, mips_add_offset (base, offset));
1971 src = force_const_mem (mode, src);
1973 /* When using explicit relocs, constant pool references are sometimes
1974 not legitimate addresses. */
1975 if (!memory_operand (src, VOIDmode))
1976 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
1977 emit_move_insn (dest, src);
1981 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1982 sequence that is valid. */
1985 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
1987 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1989 emit_move_insn (dest, force_reg (mode, src));
1993 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
1994 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1995 && REG_P (src) && MD_REG_P (REGNO (src))
1996 && REG_P (dest) && GP_REG_P (REGNO (dest)))
1998 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
1999 if (GET_MODE_SIZE (mode) <= 4)
2000 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2001 gen_rtx_REG (SImode, REGNO (src)),
2002 gen_rtx_REG (SImode, other_regno)));
2004 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2005 gen_rtx_REG (DImode, REGNO (src)),
2006 gen_rtx_REG (DImode, other_regno)));
2010 /* We need to deal with constants that would be legitimate
2011 immediate_operands but not legitimate move_operands. */
2012 if (CONSTANT_P (src) && !move_operand (src, mode))
2014 mips_legitimize_const_move (mode, dest, src);
2015 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2021 /* We need a lot of little routines to check constant values on the
2022 mips16. These are used to figure out how long the instruction will
2023 be. It would be much better to do this using constraints, but
2024 there aren't nearly enough letters available. */
2027 m16_check_op (rtx op, int low, int high, int mask)
2029 return (GET_CODE (op) == CONST_INT
2030 && INTVAL (op) >= low
2031 && INTVAL (op) <= high
2032 && (INTVAL (op) & mask) == 0);
2036 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2038 return m16_check_op (op, 0x1, 0x8, 0);
2042 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2044 return m16_check_op (op, - 0x8, 0x7, 0);
2048 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2050 return m16_check_op (op, - 0x7, 0x8, 0);
2054 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2056 return m16_check_op (op, - 0x10, 0xf, 0);
2060 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2062 return m16_check_op (op, - 0xf, 0x10, 0);
2066 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2068 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2072 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2074 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2078 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2080 return m16_check_op (op, - 0x80, 0x7f, 0);
2084 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2086 return m16_check_op (op, - 0x7f, 0x80, 0);
2090 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2092 return m16_check_op (op, 0x0, 0xff, 0);
2096 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2098 return m16_check_op (op, - 0xff, 0x0, 0);
2102 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2104 return m16_check_op (op, - 0x1, 0xfe, 0);
2108 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2110 return m16_check_op (op, 0x0, 0xff << 2, 3);
2114 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2116 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2120 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2122 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2126 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2128 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2132 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2134 enum machine_mode mode = GET_MODE (x);
2141 /* Always return 0, since we don't have different sized
2142 instructions, hence different costs according to Richard
2148 /* A number between 1 and 8 inclusive is efficient for a shift.
2149 Otherwise, we will need an extended instruction. */
2150 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2151 || (outer_code) == LSHIFTRT)
2153 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2156 *total = COSTS_N_INSNS (1);
2160 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2161 if ((outer_code) == XOR
2162 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2168 /* We may be able to use slt or sltu for a comparison with a
2169 signed 16 bit value. (The boundary conditions aren't quite
2170 right, but this is just a heuristic anyhow.) */
2171 if (((outer_code) == LT || (outer_code) == LE
2172 || (outer_code) == GE || (outer_code) == GT
2173 || (outer_code) == LTU || (outer_code) == LEU
2174 || (outer_code) == GEU || (outer_code) == GTU)
2175 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2181 /* Equality comparisons with 0 are cheap. */
2182 if (((outer_code) == EQ || (outer_code) == NE)
2189 /* Otherwise fall through to the handling below. */
2195 if (LEGITIMATE_CONSTANT_P (x))
2197 *total = COSTS_N_INSNS (1);
2202 /* The value will need to be fetched from the constant pool. */
2203 *total = CONSTANT_POOL_COST;
2209 /* If the address is legitimate, return the number of
2210 instructions it needs, otherwise use the default handling. */
2211 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2214 *total = COSTS_N_INSNS (1 + n);
2221 *total = COSTS_N_INSNS (6);
2225 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2231 if (mode == DImode && !TARGET_64BIT)
2233 *total = COSTS_N_INSNS (2);
2241 if (mode == DImode && !TARGET_64BIT)
2243 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2250 if (mode == SFmode || mode == DFmode)
2251 *total = COSTS_N_INSNS (1);
2253 *total = COSTS_N_INSNS (4);
2257 *total = COSTS_N_INSNS (1);
2262 if (mode == SFmode || mode == DFmode)
2264 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2265 *total = COSTS_N_INSNS (2);
2266 else if (TUNE_MIPS6000)
2267 *total = COSTS_N_INSNS (3);
2269 *total = COSTS_N_INSNS (6);
2272 if (mode == DImode && !TARGET_64BIT)
2274 *total = COSTS_N_INSNS (4);
2280 if (mode == DImode && !TARGET_64BIT)
2293 *total = COSTS_N_INSNS (4);
2294 else if (TUNE_MIPS6000
2297 *total = COSTS_N_INSNS (5);
2299 *total = COSTS_N_INSNS (7);
2308 *total = COSTS_N_INSNS (5);
2309 else if (TUNE_MIPS6000
2312 *total = COSTS_N_INSNS (6);
2314 *total = COSTS_N_INSNS (8);
2319 *total = COSTS_N_INSNS (12);
2320 else if (TUNE_MIPS3900)
2321 *total = COSTS_N_INSNS (2);
2322 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2323 *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
2324 else if (TUNE_MIPS7000)
2325 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2326 else if (TUNE_MIPS9000)
2327 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2328 else if (TUNE_MIPS6000)
2329 *total = COSTS_N_INSNS (17);
2330 else if (TUNE_MIPS5000)
2331 *total = COSTS_N_INSNS (5);
2333 *total = COSTS_N_INSNS (10);
2342 *total = COSTS_N_INSNS (12);
2343 else if (TUNE_MIPS6000)
2344 *total = COSTS_N_INSNS (15);
2345 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2346 *total = COSTS_N_INSNS (30);
2348 *total = COSTS_N_INSNS (23);
2356 *total = COSTS_N_INSNS (19);
2357 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2358 *total = COSTS_N_INSNS (59);
2359 else if (TUNE_MIPS6000)
2360 *total = COSTS_N_INSNS (16);
2362 *total = COSTS_N_INSNS (36);
2371 *total = COSTS_N_INSNS (35);
2372 else if (TUNE_MIPS6000)
2373 *total = COSTS_N_INSNS (38);
2374 else if (TUNE_MIPS5000)
2375 *total = COSTS_N_INSNS (36);
2376 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2377 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2379 *total = COSTS_N_INSNS (69);
2383 /* A sign extend from SImode to DImode in 64 bit mode is often
2384 zero instructions, because the result can often be used
2385 directly by another instruction; we'll call it one. */
2386 if (TARGET_64BIT && mode == DImode
2387 && GET_MODE (XEXP (x, 0)) == SImode)
2388 *total = COSTS_N_INSNS (1);
2390 *total = COSTS_N_INSNS (2);
2394 if (TARGET_64BIT && mode == DImode
2395 && GET_MODE (XEXP (x, 0)) == SImode)
2396 *total = COSTS_N_INSNS (2);
2398 *total = COSTS_N_INSNS (1);
2406 /* Provide the costs of an addressing mode that contains ADDR.
2407 If ADDR is not a valid address, its cost is irrelevant. */
2410 mips_address_cost (rtx addr)
2412 return mips_address_insns (addr, SImode);
2415 /* Return a pseudo that points to the address of the current function.
2416 The first time it is called for a function, an initializer for the
2417 pseudo is emitted in the beginning of the function. */
2420 embedded_pic_fnaddr_reg (void)
2422 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
2426 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
2428 /* Output code at function start to initialize the pseudo-reg. */
2429 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2430 inline functions, because it is called after RTL for the function
2431 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2432 does not get copied, and ends up not matching the rest of the RTL.
2433 This solution works, but means that we get unnecessary code to
2434 initialize this value every time a function is inlined into another
2437 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
2438 XEXP (DECL_RTL (current_function_decl), 0)));
2441 push_topmost_sequence ();
2442 emit_insn_after (seq, get_insns ());
2443 pop_topmost_sequence ();
2446 return cfun->machine->embedded_pic_fnaddr_rtx;
2449 /* Return RTL for the offset from the current function to the argument.
2450 X is the symbol whose offset from the current function we want. */
2453 embedded_pic_offset (rtx x)
2455 /* Make sure it is emitted. */
2456 embedded_pic_fnaddr_reg ();
2459 gen_rtx_CONST (Pmode,
2460 gen_rtx_MINUS (Pmode, x,
2461 XEXP (DECL_RTL (current_function_decl), 0)));
2464 /* Return one word of double-word value OP, taking into account the fixed
2465 endianness of certain registers. HIGH_P is true to select the high part,
2466 false to select the low part. */
2469 mips_subword (rtx op, int high_p)
2472 enum machine_mode mode;
2474 mode = GET_MODE (op);
2475 if (mode == VOIDmode)
2478 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2479 byte = UNITS_PER_WORD;
2483 if (GET_CODE (op) == REG)
2485 if (FP_REG_P (REGNO (op)))
2486 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2487 if (REGNO (op) == HI_REGNUM)
2488 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2491 if (GET_CODE (op) == MEM)
2492 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2494 return simplify_gen_subreg (word_mode, op, mode, byte);
2498 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2501 mips_split_64bit_move_p (rtx dest, rtx src)
2506 /* FP->FP moves can be done in a single instruction. */
2507 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2510 /* Check for floating-point loads and stores. They can be done using
2511 ldc1 and sdc1 on MIPS II and above. */
2514 if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
2516 if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
2523 /* Split a 64-bit move from SRC to DEST assuming that
2524 mips_split_64bit_move_p holds.
2526 Moves into and out of FPRs cause some difficulty here. Such moves
2527 will always be DFmode, since paired FPRs are not allowed to store
2528 DImode values. The most natural representation would be two separate
2529 32-bit moves, such as:
2531 (set (reg:SI $f0) (mem:SI ...))
2532 (set (reg:SI $f1) (mem:SI ...))
2534 However, the second insn is invalid because odd-numbered FPRs are
2535 not allowed to store independent values. Use the patterns load_df_low,
2536 load_df_high and store_df_high instead. */
2539 mips_split_64bit_move (rtx dest, rtx src)
2541 if (FP_REG_RTX_P (dest))
2543 /* Loading an FPR from memory or from GPRs. */
2544 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2545 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2548 else if (FP_REG_RTX_P (src))
2550 /* Storing an FPR into memory or GPRs. */
2551 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2552 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2556 /* The operation can be split into two normal moves. Decide in
2557 which order to do them. */
2560 low_dest = mips_subword (dest, 0);
2561 if (GET_CODE (low_dest) == REG
2562 && reg_overlap_mentioned_p (low_dest, src))
2564 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2565 emit_move_insn (low_dest, mips_subword (src, 0));
2569 emit_move_insn (low_dest, mips_subword (src, 0));
2570 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2575 /* Return the appropriate instructions to move SRC into DEST. Assume
2576 that SRC is operand 1 and DEST is operand 0. */
2579 mips_output_move (rtx dest, rtx src)
2581 enum rtx_code dest_code, src_code;
2584 dest_code = GET_CODE (dest);
2585 src_code = GET_CODE (src);
2586 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2588 if (dbl_p && mips_split_64bit_move_p (dest, src))
2591 if ((src_code == REG && GP_REG_P (REGNO (src)))
2592 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2594 if (dest_code == REG)
2596 if (GP_REG_P (REGNO (dest)))
2597 return "move\t%0,%z1";
2599 if (MD_REG_P (REGNO (dest)))
2602 if (FP_REG_P (REGNO (dest)))
2603 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2605 if (ALL_COP_REG_P (REGNO (dest)))
2607 static char retval[] = "dmtc_\t%z1,%0";
2609 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2610 return (dbl_p ? retval : retval + 1);
2613 if (dest_code == MEM)
2614 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2616 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2618 if (src_code == REG)
2620 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2621 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2623 if (FP_REG_P (REGNO (src)))
2624 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2626 if (ALL_COP_REG_P (REGNO (src)))
2628 static char retval[] = "dmfc_\t%0,%1";
2630 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2631 return (dbl_p ? retval : retval + 1);
2635 if (src_code == MEM)
2636 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2638 if (src_code == CONST_INT)
2640 /* Don't use the X format, because that will give out of
2641 range numbers for 64 bit hosts and 32 bit targets. */
2643 return "li\t%0,%1\t\t\t# %X1";
2645 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2648 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2649 return "li\t%0,%n1\n\tneg\t%0";
2652 if (src_code == HIGH)
2653 return "lui\t%0,%h1";
2655 if (CONST_GP_P (src))
2656 return "move\t%0,%1";
2658 if (symbolic_operand (src, VOIDmode))
2659 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2661 if (src_code == REG && FP_REG_P (REGNO (src)))
2663 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2664 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2666 if (dest_code == MEM)
2667 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2669 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2671 if (src_code == MEM)
2672 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2674 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2676 static char retval[] = "l_c_\t%0,%1";
2678 retval[1] = (dbl_p ? 'd' : 'w');
2679 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2682 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2684 static char retval[] = "s_c_\t%1,%0";
2686 retval[1] = (dbl_p ? 'd' : 'w');
2687 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2693 /* Return an rtx for the gp save slot. Valid only when using o32 or
2697 mips_gp_save_slot (void)
2701 if (!TARGET_ABICALLS || TARGET_NEWABI)
2704 if (frame_pointer_needed)
2705 loc = hard_frame_pointer_rtx;
2707 loc = stack_pointer_rtx;
2708 loc = plus_constant (loc, current_function_outgoing_args_size);
2709 loc = gen_rtx_MEM (Pmode, loc);
2710 RTX_UNCHANGING_P (loc) = 1;
2714 /* Make normal rtx_code into something we can index from an array */
2716 static enum internal_test
2717 map_test_to_internal_test (enum rtx_code test_code)
2719 enum internal_test test = ITEST_MAX;
2723 case EQ: test = ITEST_EQ; break;
2724 case NE: test = ITEST_NE; break;
2725 case GT: test = ITEST_GT; break;
2726 case GE: test = ITEST_GE; break;
2727 case LT: test = ITEST_LT; break;
2728 case LE: test = ITEST_LE; break;
2729 case GTU: test = ITEST_GTU; break;
2730 case GEU: test = ITEST_GEU; break;
2731 case LTU: test = ITEST_LTU; break;
2732 case LEU: test = ITEST_LEU; break;
2740 /* Generate the code to compare two integer values. The return value is:
2741 (reg:SI xx) The pseudo register the comparison is in
2742 0 No register, generate a simple branch.
2744 ??? This is called with result nonzero by the Scond patterns in
2745 mips.md. These patterns are called with a target in the mode of
2746 the Scond instruction pattern. Since this must be a constant, we
2747 must use SImode. This means that if RESULT is nonzero, it will
2748 always be an SImode register, even if TARGET_64BIT is true. We
2749 cope with this by calling convert_move rather than emit_move_insn.
2750 This will sometimes lead to an unnecessary extension of the result;
2759 TEST_CODE is the rtx code for the comparison.
2760 CMP0 and CMP1 are the two operands to compare.
2761 RESULT is the register in which the result should be stored (null for
2763 For branches, P_INVERT points to an integer that is nonzero on return
2764 if the branch should be inverted. */
2767 gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
2768 rtx cmp1, int *p_invert)
2772 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2773 int const_low; /* low bound of constant we can accept */
2774 int const_high; /* high bound of constant we can accept */
2775 int const_add; /* constant to add (convert LE -> LT) */
2776 int reverse_regs; /* reverse registers in test */
2777 int invert_const; /* != 0 if invert value if cmp1 is constant */
2778 int invert_reg; /* != 0 if invert value if cmp1 is register */
2779 int unsignedp; /* != 0 for unsigned comparisons. */
2782 static const struct cmp_info info[ (int)ITEST_MAX ] = {
2784 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2785 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2786 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2787 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2788 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2789 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2790 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2791 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2792 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2793 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2796 enum internal_test test;
2797 enum machine_mode mode;
2798 const struct cmp_info *p_info;
2805 test = map_test_to_internal_test (test_code);
2806 if (test == ITEST_MAX)
2809 p_info = &info[(int) test];
2810 eqne_p = (p_info->test_code == XOR);
2812 mode = GET_MODE (cmp0);
2813 if (mode == VOIDmode)
2814 mode = GET_MODE (cmp1);
2816 /* Eliminate simple branches. */
2817 branch_p = (result == 0);
2820 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2822 /* Comparisons against zero are simple branches. */
2823 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2824 && (! TARGET_MIPS16 || eqne_p))
2827 /* Test for beq/bne. */
2828 if (eqne_p && ! TARGET_MIPS16)
2832 /* Allocate a pseudo to calculate the value in. */
2833 result = gen_reg_rtx (mode);
2836 /* Make sure we can handle any constants given to us. */
2837 if (GET_CODE (cmp0) == CONST_INT)
2838 cmp0 = force_reg (mode, cmp0);
2840 if (GET_CODE (cmp1) == CONST_INT)
2842 HOST_WIDE_INT value = INTVAL (cmp1);
2844 if (value < p_info->const_low
2845 || value > p_info->const_high
2846 /* ??? Why? And why wasn't the similar code below modified too? */
2848 && HOST_BITS_PER_WIDE_INT < 64
2849 && p_info->const_add != 0
2850 && ((p_info->unsignedp
2851 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2852 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2853 : (value + p_info->const_add) > INTVAL (cmp1))
2854 != (p_info->const_add > 0))))
2855 cmp1 = force_reg (mode, cmp1);
2858 /* See if we need to invert the result. */
2859 invert = (GET_CODE (cmp1) == CONST_INT
2860 ? p_info->invert_const : p_info->invert_reg);
2862 if (p_invert != (int *)0)
2868 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2869 Comparison between two registers, may involve switching operands. */
2870 if (GET_CODE (cmp1) == CONST_INT)
2872 if (p_info->const_add != 0)
2874 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2876 /* If modification of cmp1 caused overflow,
2877 we would get the wrong answer if we follow the usual path;
2878 thus, x > 0xffffffffU would turn into x > 0U. */
2879 if ((p_info->unsignedp
2880 ? (unsigned HOST_WIDE_INT) new >
2881 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2882 : new > INTVAL (cmp1))
2883 != (p_info->const_add > 0))
2885 /* This test is always true, but if INVERT is true then
2886 the result of the test needs to be inverted so 0 should
2887 be returned instead. */
2888 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2892 cmp1 = GEN_INT (new);
2896 else if (p_info->reverse_regs)
2903 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2907 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2908 convert_move (reg, gen_rtx_fmt_ee (p_info->test_code,
2909 mode, cmp0, cmp1), 0);
2912 if (test == ITEST_NE)
2914 if (! TARGET_MIPS16)
2916 convert_move (result, gen_rtx_GTU (mode, reg, const0_rtx), 0);
2917 if (p_invert != NULL)
2923 reg2 = invert ? gen_reg_rtx (mode) : result;
2924 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2929 else if (test == ITEST_EQ)
2931 reg2 = invert ? gen_reg_rtx (mode) : result;
2932 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2940 if (! TARGET_MIPS16)
2944 /* The value is in $24. Copy it to another register, so
2945 that reload doesn't think it needs to store the $24 and
2946 the input to the XOR in the same location. */
2947 reg2 = gen_reg_rtx (mode);
2948 emit_move_insn (reg2, reg);
2950 one = force_reg (mode, const1_rtx);
2952 convert_move (result, gen_rtx_XOR (mode, reg, one), 0);
2958 /* Work out how to check a floating-point condition. We need a
2959 separate comparison instruction (C.cond.fmt), followed by a
2960 branch or conditional move. Given that IN_CODE is the
2961 required condition, set *CMP_CODE to the C.cond.fmt code
2962 and *action_code to the branch or move code. */
2965 get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
2966 enum rtx_code *action_code)
2975 *cmp_code = reverse_condition_maybe_unordered (in_code);
2980 *cmp_code = in_code;
2986 /* Emit the common code for doing conditional branches.
2987 operand[0] is the label to jump to.
2988 The comparison operands are saved away by cmp{si,di,sf,df}. */
2991 gen_conditional_branch (rtx *operands, enum rtx_code test_code)
2993 enum cmp_type type = branch_type;
2994 rtx cmp0 = branch_cmp[0];
2995 rtx cmp1 = branch_cmp[1];
2996 enum machine_mode mode;
2997 enum rtx_code cmp_code;
3006 mode = type == CMP_SI ? SImode : DImode;
3008 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3016 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3017 /* We don't want to build a comparison against a nonzero
3019 cmp1 = force_reg (mode, cmp1);
3026 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3028 reg = gen_reg_rtx (CCmode);
3030 get_float_compare_codes (test_code, &cmp_code, &test_code);
3031 emit_insn (gen_rtx_SET (VOIDmode, reg,
3032 gen_rtx_fmt_ee (cmp_code, CCmode, cmp0, cmp1)));
3041 fatal_insn ("bad test",
3042 gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
3045 /* Generate the branch. */
3047 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3057 (gen_rtx_SET (VOIDmode, pc_rtx,
3058 gen_rtx_IF_THEN_ELSE (VOIDmode,
3059 gen_rtx_fmt_ee (test_code, mode,
3064 /* Emit the common code for conditional moves. OPERANDS is the array
3065 of operands passed to the conditional move define_expand. */
3068 gen_conditional_move (rtx *operands)
3070 rtx op0 = branch_cmp[0];
3071 rtx op1 = branch_cmp[1];
3072 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3073 enum rtx_code cmp_code = GET_CODE (operands[1]);
3074 enum rtx_code move_code = NE;
3075 enum machine_mode op_mode = GET_MODE (operands[0]);
3076 enum machine_mode cmp_mode;
3079 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3098 op0 = force_reg (mode, branch_cmp[1]);
3099 op1 = branch_cmp[0];
3103 op0 = force_reg (mode, branch_cmp[1]);
3104 op1 = branch_cmp[0];
3115 op0 = force_reg (mode, branch_cmp[1]);
3116 op1 = branch_cmp[0];
3120 op0 = force_reg (mode, branch_cmp[1]);
3121 op1 = branch_cmp[0];
3129 get_float_compare_codes (cmp_code, &cmp_code, &move_code);
3131 if (mode == SImode || mode == DImode)
3133 else if (mode == SFmode || mode == DFmode)
3138 cmp_reg = gen_reg_rtx (cmp_mode);
3139 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3140 gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)));
3142 emit_insn (gen_rtx_SET (op_mode, operands[0],
3143 gen_rtx_IF_THEN_ELSE (op_mode,
3144 gen_rtx_fmt_ee (move_code,
3148 operands[2], operands[3])));
3151 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3152 the conditional_trap expander. */
3155 mips_gen_conditional_trap (rtx *operands)
3158 enum rtx_code cmp_code = GET_CODE (operands[0]);
3159 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3161 /* MIPS conditional trap machine instructions don't have GT or LE
3162 flavors, so we must invert the comparison and convert to LT and
3163 GE, respectively. */
3166 case GT: cmp_code = LT; break;
3167 case LE: cmp_code = GE; break;
3168 case GTU: cmp_code = LTU; break;
3169 case LEU: cmp_code = GEU; break;
3172 if (cmp_code == GET_CODE (operands[0]))
3174 op0 = force_reg (mode, branch_cmp[0]);
3175 op1 = branch_cmp[1];
3179 op0 = force_reg (mode, branch_cmp[1]);
3180 op1 = branch_cmp[0];
3182 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3183 op1 = force_reg (mode, op1);
3185 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3186 gen_rtx_fmt_ee (cmp_code, GET_MODE (operands[0]),
3191 /* Load function address ADDR into register DEST. SIBCALL_P is true
3192 if the address is needed for a sibling call. */
3195 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3197 /* If we're generating PIC, and this call is to a global function,
3198 try to allow its address to be resolved lazily. This isn't
3199 possible for NewABI sibcalls since the value of $gp on entry
3200 to the stub would be our caller's gp, not ours. */
3201 if (TARGET_EXPLICIT_RELOCS
3202 && !(sibcall_p && TARGET_NEWABI)
3203 && global_got_operand (addr, VOIDmode))
3205 rtx high, lo_sum_symbol;
3207 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3208 addr, SYMBOL_GOTOFF_CALL);
3209 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3210 if (Pmode == SImode)
3211 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3213 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3216 emit_move_insn (dest, addr);
3220 /* Expand a call or call_value instruction. RESULT is where the
3221 result will go (null for calls), ADDR is the address of the
3222 function, ARGS_SIZE is the size of the arguments and AUX is
3223 the value passed to us by mips_function_arg. SIBCALL_P is true
3224 if we are expanding a sibling call, false if we're expanding
3228 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3230 rtx orig_addr, pattern, insn;
3233 if (!call_insn_operand (addr, VOIDmode))
3235 addr = gen_reg_rtx (Pmode);
3236 mips_load_call_address (addr, orig_addr, sibcall_p);
3240 && mips16_hard_float
3241 && build_mips16_call_stub (result, addr, args_size,
3242 aux == 0 ? 0 : (int) GET_MODE (aux)))
3246 pattern = (sibcall_p
3247 ? gen_sibcall_internal (addr, args_size)
3248 : gen_call_internal (addr, args_size));
3249 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3253 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3254 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3257 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3258 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3261 pattern = (sibcall_p
3262 ? gen_sibcall_value_internal (result, addr, args_size)
3263 : gen_call_value_internal (result, addr, args_size));
3265 insn = emit_call_insn (pattern);
3267 /* Lazy-binding stubs require $gp to be valid on entry. */
3268 if (global_got_operand (orig_addr, VOIDmode))
3269 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3273 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3276 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3277 tree exp ATTRIBUTE_UNUSED)
3279 return TARGET_SIBCALLS;
3282 /* Return true if operand OP is a condition code register.
3283 Only for use during or after reload. */
3286 fcc_register_operand (rtx op, enum machine_mode mode)
3288 return ((mode == VOIDmode || mode == GET_MODE (op))
3289 && (reload_in_progress || reload_completed)
3290 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3291 && ST_REG_P (true_regnum (op)));
3294 /* Emit code to move general operand SRC into condition-code
3295 register DEST. SCRATCH is a scratch TFmode float register.
3302 where FP1 and FP2 are single-precision float registers
3303 taken from SCRATCH. */
3306 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3310 /* Change the source to SFmode. */
3311 if (GET_CODE (src) == MEM)
3312 src = adjust_address (src, SFmode, 0);
3313 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3314 src = gen_rtx_REG (SFmode, true_regnum (src));
3316 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3317 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3319 emit_move_insn (copy_rtx (fp1), src);
3320 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3321 emit_insn (gen_slt_sf (dest, fp2, fp1));
3324 /* Emit code to change the current function's return address to
3325 ADDRESS. SCRATCH is available as a scratch register, if needed.
3326 ADDRESS and SCRATCH are both word-mode GPRs. */
3329 mips_set_return_address (rtx address, rtx scratch)
3331 HOST_WIDE_INT gp_offset;
3333 compute_frame_size (get_frame_size ());
3334 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3336 gp_offset = cfun->machine->frame.gp_sp_offset;
3338 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3339 if (gp_offset < 32768)
3340 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3343 emit_move_insn (scratch, GEN_INT (gp_offset));
3344 if (Pmode == DImode)
3345 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3347 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3350 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3353 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3354 Assume that the areas do not overlap. */
3357 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3359 HOST_WIDE_INT offset, delta;
3360 unsigned HOST_WIDE_INT bits;
3362 enum machine_mode mode;
3365 /* Work out how many bits to move at a time. If both operands have
3366 half-word alignment, it is usually better to move in half words.
3367 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3368 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3369 Otherwise move word-sized chunks. */
3370 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3371 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3372 bits = BITS_PER_WORD / 2;
3374 bits = BITS_PER_WORD;
3376 mode = mode_for_size (bits, MODE_INT, 0);
3377 delta = bits / BITS_PER_UNIT;
3379 /* Allocate a buffer for the temporary registers. */
3380 regs = alloca (sizeof (rtx) * length / delta);
3382 /* Load as many BITS-sized chunks as possible. Use a normal load if
3383 the source has enough alignment, otherwise use left/right pairs. */
3384 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3388 regs[i] = gen_reg_rtx (mode);
3389 part = adjust_address (src, mode, offset);
3390 if (MEM_ALIGN (part) >= bits)
3391 emit_move_insn (regs[i], part);
3392 else if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3396 /* Copy the chunks to the destination. */
3397 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3401 part = adjust_address (dest, mode, offset);
3402 if (MEM_ALIGN (part) >= bits)
3403 emit_move_insn (part, regs[i]);
3404 else if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3408 /* Mop up any left-over bytes. */
3409 if (offset < length)
3411 src = adjust_address (src, mode, offset);
3412 dest = adjust_address (dest, mode, offset);
3413 move_by_pieces (dest, src, length - offset,
3414 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3418 #define MAX_MOVE_REGS 4
3419 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3422 /* Helper function for doing a loop-based block operation on memory
3423 reference MEM. Each iteration of the loop will operate on LENGTH
3426 Create a new base register for use within the loop and point it to
3427 the start of MEM. Create a new memory reference that uses this
3428 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3431 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3432 rtx *loop_reg, rtx *loop_mem)
3434 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3436 /* Although the new mem does not refer to a known location,
3437 it does keep up to LENGTH bytes of alignment. */
3438 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3439 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3443 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3444 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3445 memory regions do not overlap. */
3448 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3450 rtx label, src_reg, dest_reg, final_src;
3451 HOST_WIDE_INT leftover;
3453 leftover = length % MAX_MOVE_BYTES;
3456 /* Create registers and memory references for use within the loop. */
3457 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3458 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3460 /* Calculate the value that SRC_REG should have after the last iteration
3462 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3465 /* Emit the start of the loop. */
3466 label = gen_label_rtx ();
3469 /* Emit the loop body. */
3470 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3472 /* Move on to the next block. */
3473 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3474 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3476 /* Emit the loop condition. */
3477 if (Pmode == DImode)
3478 emit_insn (gen_cmpdi (src_reg, final_src));
3480 emit_insn (gen_cmpsi (src_reg, final_src));
3481 emit_jump_insn (gen_bne (label));
3483 /* Mop up any left-over bytes. */
3485 mips_block_move_straight (dest, src, leftover);
3488 /* Expand a movstrsi instruction. */
3491 mips_expand_block_move (rtx dest, rtx src, rtx length)
3493 if (GET_CODE (length) == CONST_INT)
3495 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3497 mips_block_move_straight (dest, src, INTVAL (length));
3502 mips_block_move_loop (dest, src, INTVAL (length));
3509 /* Argument support functions. */
3511 /* Initialize CUMULATIVE_ARGS for a function. */
3514 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3515 rtx libname ATTRIBUTE_UNUSED)
3517 static CUMULATIVE_ARGS zero_cum;
3518 tree param, next_param;
3521 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3523 /* Determine if this function has variable arguments. This is
3524 indicated by the last argument being 'void_type_mode' if there
3525 are no variable arguments. The standard MIPS calling sequence
3526 passes all arguments in the general purpose registers in this case. */
3528 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3529 param != 0; param = next_param)
3531 next_param = TREE_CHAIN (param);
3532 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3533 cum->gp_reg_found = 1;
3538 /* Fill INFO with information about a single argument. CUM is the
3539 cumulative state for earlier arguments. MODE is the mode of this
3540 argument and TYPE is its type (if known). NAMED is true if this
3541 is a named (fixed) argument rather than a variable one. */
3544 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3545 tree type, int named, struct mips_arg_info *info)
3548 unsigned int num_words, max_regs;
3550 /* Decide whether this argument should go in a floating-point register,
3551 assuming one is free. Later code checks for availability. */
3553 info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
3554 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3561 info->fpr_p = (!cum->gp_reg_found
3562 && cum->arg_number < 2
3563 && (type == 0 || FLOAT_TYPE_P (type)));
3568 info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
3572 /* Now decide whether the argument must go in an even-numbered register. */
3577 /* Under the O64 ABI, the second float argument goes in $f13 if it
3578 is a double, but $f14 if it is a single. Otherwise, on a
3579 32-bit double-float machine, each FP argument must start in a
3580 new register pair. */
3581 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
3582 || (mips_abi == ABI_O64 && mode == SFmode)
3585 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
3587 if (GET_MODE_CLASS (mode) == MODE_INT
3588 || GET_MODE_CLASS (mode) == MODE_FLOAT)
3589 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
3591 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
3595 if (mips_abi != ABI_EABI && MUST_PASS_IN_STACK (mode, type))
3596 /* This argument must be passed on the stack. Eat up all the
3597 remaining registers. */
3598 info->reg_offset = MAX_ARGS_IN_REGISTERS;
3601 /* Set REG_OFFSET to the register count we're interested in.
3602 The EABI allocates the floating-point registers separately,
3603 but the other ABIs allocate them like integer registers. */
3604 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3609 info->reg_offset += info->reg_offset & 1;
3612 /* The alignment applied to registers is also applied to stack arguments. */
3613 info->stack_offset = cum->stack_words;
3615 info->stack_offset += info->stack_offset & 1;
3617 if (mode == BLKmode)
3618 info->num_bytes = int_size_in_bytes (type);
3620 info->num_bytes = GET_MODE_SIZE (mode);
3622 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3623 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3625 /* Partition the argument between registers and stack. */
3626 info->reg_words = MIN (num_words, max_regs);
3627 info->stack_words = num_words - info->reg_words;
3631 /* Implement FUNCTION_ARG_ADVANCE. */
3634 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3635 tree type, int named)
3637 struct mips_arg_info info;
3639 mips_arg_info (cum, mode, type, named, &info);
3642 cum->gp_reg_found = true;
3644 /* See the comment above the cumulative args structure in mips.h
3645 for an explanation of what this code does. It assumes the O32
3646 ABI, which passes at most 2 arguments in float registers. */
3647 if (cum->arg_number < 2 && info.fpr_p)
3648 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3650 if (mips_abi != ABI_EABI || !info.fpr_p)
3651 cum->num_gprs = info.reg_offset + info.reg_words;
3652 else if (info.reg_words > 0)
3653 cum->num_fprs += FP_INC;
3655 if (info.stack_words > 0)
3656 cum->stack_words = info.stack_offset + info.stack_words;
3661 /* Implement FUNCTION_ARG. */
3664 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3665 tree type, int named)
3667 struct mips_arg_info info;
3669 /* We will be called with a mode of VOIDmode after the last argument
3670 has been seen. Whatever we return will be passed to the call
3671 insn. If we need a mips16 fp_code, return a REG with the code
3672 stored as the mode. */
3673 if (mode == VOIDmode)
3675 if (TARGET_MIPS16 && cum->fp_code != 0)
3676 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3682 mips_arg_info (cum, mode, type, named, &info);
3684 /* Return straight away if the whole argument is passed on the stack. */
3685 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3689 && TREE_CODE (type) == RECORD_TYPE
3691 && TYPE_SIZE_UNIT (type)
3692 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3695 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3696 structure contains a double in its entirety, then that 64 bit
3697 chunk is passed in a floating point register. */
3700 /* First check to see if there is any such field. */
3701 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3702 if (TREE_CODE (field) == FIELD_DECL
3703 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3704 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3705 && host_integerp (bit_position (field), 0)
3706 && int_bit_position (field) % BITS_PER_WORD == 0)
3711 /* Now handle the special case by returning a PARALLEL
3712 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3713 chunks are passed in registers. */
3715 HOST_WIDE_INT bitpos;
3718 /* assign_parms checks the mode of ENTRY_PARM, so we must
3719 use the actual mode here. */
3720 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3723 field = TYPE_FIELDS (type);
3724 for (i = 0; i < info.reg_words; i++)
3728 for (; field; field = TREE_CHAIN (field))
3729 if (TREE_CODE (field) == FIELD_DECL
3730 && int_bit_position (field) >= bitpos)
3734 && int_bit_position (field) == bitpos
3735 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3736 && !TARGET_SOFT_FLOAT
3737 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3738 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3740 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3743 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3744 GEN_INT (bitpos / BITS_PER_UNIT));
3746 bitpos += BITS_PER_WORD;
3753 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3755 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3759 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3762 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3763 enum machine_mode mode, tree type, int named)
3765 struct mips_arg_info info;
3767 mips_arg_info (cum, mode, type, named, &info);
3768 return info.stack_words > 0 ? info.reg_words : 0;
3772 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3773 upward rather than downward. In other words, return true if the
3774 first byte of the stack slot has useful data, false if the last
3778 mips_pad_arg_upward (enum machine_mode mode, tree type)
3780 /* On little-endian targets, the first byte of every stack argument
3781 is passed in the first byte of the stack slot. */
3782 if (!BYTES_BIG_ENDIAN)
3785 /* Otherwise, integral types are padded downward: the last byte of a
3786 stack argument is passed in the last byte of the stack slot. */
3788 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3789 : GET_MODE_CLASS (mode) == MODE_INT)
3792 /* Big-endian o64 pads floating-point arguments downward. */
3793 if (mips_abi == ABI_O64)
3794 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3797 /* Other types are padded upward for o32, o64, n32 and n64. */
3798 if (mips_abi != ABI_EABI)
3801 /* Arguments smaller than a stack slot are padded downward. */
3802 if (mode != BLKmode)
3803 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3805 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3809 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3810 if the least significant byte of the register has useful data. Return
3811 the opposite if the most significant byte does. */
3814 mips_pad_reg_upward (enum machine_mode mode, tree type)
3816 /* No shifting is required for floating-point arguments. */
3817 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3818 return !BYTES_BIG_ENDIAN;
3820 /* Otherwise, apply the same padding to register arguments as we do
3821 to stack arguments. */
3822 return mips_pad_arg_upward (mode, type);
3826 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3827 tree type, int *pretend_size, int no_rtl)
3829 CUMULATIVE_ARGS local_cum;
3830 int gp_saved, fp_saved;
3832 /* The caller has advanced CUM up to, but not beyond, the last named
3833 argument. Advance a local copy of CUM past the last "real" named
3834 argument, to find out how many registers are left over. */
3837 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3839 /* Found out how many registers we need to save. */
3840 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3841 fp_saved = (EABI_FLOAT_VARARGS_P
3842 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3851 ptr = virtual_incoming_args_rtx;
3856 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3860 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3863 mem = gen_rtx_MEM (BLKmode, ptr);
3864 set_mem_alias_set (mem, get_varargs_alias_set ());
3866 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3871 /* We can't use move_block_from_reg, because it will use
3873 enum machine_mode mode;
3876 /* Set OFF to the offset from virtual_incoming_args_rtx of
3877 the first float register. The FP save area lies below
3878 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3879 off = -gp_saved * UNITS_PER_WORD;
3880 off &= ~(UNITS_PER_FPVALUE - 1);
3881 off -= fp_saved * UNITS_PER_FPREG;
3883 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3885 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3889 ptr = plus_constant (virtual_incoming_args_rtx, off);
3890 mem = gen_rtx_MEM (mode, ptr);
3891 set_mem_alias_set (mem, get_varargs_alias_set ());
3892 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3893 off += UNITS_PER_HWFPVALUE;
3899 /* No need for pretend arguments: the register parameter area was
3900 allocated by the caller. */
3904 *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3907 /* Create the va_list data type.
3908 We keep 3 pointers, and two offsets.
3909 Two pointers are to the overflow area, which starts at the CFA.
3910 One of these is constant, for addressing into the GPR save area below it.
3911 The other is advanced up the stack through the overflow region.
3912 The third pointer is to the GPR save area. Since the FPR save area
3913 is just below it, we can address FPR slots off this pointer.
3914 We also keep two one-byte offsets, which are to be subtracted from the
3915 constant pointers to yield addresses in the GPR and FPR save areas.
3916 These are downcounted as float or non-float arguments are used,
3917 and when they get to zero, the argument must be obtained from the
3919 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3920 pointer is enough. It's started at the GPR save area, and is
3922 Note that the GPR save area is not constant size, due to optimization
3923 in the prologue. Hence, we can't use a design with two pointers
3924 and two offsets, although we could have designed this with two pointers
3925 and three offsets. */
3928 mips_build_builtin_va_list (void)
3930 if (EABI_FLOAT_VARARGS_P)
3932 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3935 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3937 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
3939 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
3941 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
3943 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
3944 unsigned_char_type_node);
3945 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
3946 unsigned_char_type_node);
3947 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
3948 warn on every user file. */
3949 index = build_int_2 (GET_MODE_SIZE (ptr_mode) - 2 - 1, 0);
3950 array = build_array_type (unsigned_char_type_node,
3951 build_index_type (index));
3952 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
3954 DECL_FIELD_CONTEXT (f_ovfl) = record;
3955 DECL_FIELD_CONTEXT (f_gtop) = record;
3956 DECL_FIELD_CONTEXT (f_ftop) = record;
3957 DECL_FIELD_CONTEXT (f_goff) = record;
3958 DECL_FIELD_CONTEXT (f_foff) = record;
3959 DECL_FIELD_CONTEXT (f_res) = record;
3961 TYPE_FIELDS (record) = f_ovfl;
3962 TREE_CHAIN (f_ovfl) = f_gtop;
3963 TREE_CHAIN (f_gtop) = f_ftop;
3964 TREE_CHAIN (f_ftop) = f_goff;
3965 TREE_CHAIN (f_goff) = f_foff;
3966 TREE_CHAIN (f_foff) = f_res;
3968 layout_type (record);
3971 else if (TARGET_IRIX && !TARGET_IRIX5)
3972 /* On IRIX 6, this type is 'char *'. */
3973 return build_pointer_type (char_type_node);
3975 /* Otherwise, we use 'void *'. */
3976 return ptr_type_node;
3979 /* Implement va_start. */
3982 mips_va_start (tree valist, rtx nextarg)
3984 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
3986 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
3987 since the stack is aligned for a pair of argument-passing slots,
3988 and the beginning of a variable argument list may be an odd slot,
3989 we have to decrease its alignment. */
3990 if (cfun && cfun->emit->regno_pointer_align)
3991 while (((current_function_pretend_args_size * BITS_PER_UNIT)
3992 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
3993 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
3995 if (mips_abi == ABI_EABI)
3997 int gpr_save_area_size;
4000 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4002 if (EABI_FLOAT_VARARGS_P)
4004 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4005 tree ovfl, gtop, ftop, goff, foff;
4008 int fpr_save_area_size;
4010 f_ovfl = TYPE_FIELDS (va_list_type_node);
4011 f_gtop = TREE_CHAIN (f_ovfl);
4012 f_ftop = TREE_CHAIN (f_gtop);
4013 f_goff = TREE_CHAIN (f_ftop);
4014 f_foff = TREE_CHAIN (f_goff);
4016 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4017 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4018 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4019 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4020 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4022 /* Emit code to initialize OVFL, which points to the next varargs
4023 stack argument. CUM->STACK_WORDS gives the number of stack
4024 words used by named arguments. */
4025 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4026 if (cum->stack_words > 0)
4027 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4028 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4029 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4030 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4032 /* Emit code to initialize GTOP, the top of the GPR save area. */
4033 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4034 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4035 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4037 /* Emit code to initialize FTOP, the top of the FPR save area.
4038 This address is gpr_save_area_bytes below GTOP, rounded
4039 down to the next fp-aligned boundary. */
4040 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4041 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4042 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4044 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4045 build_int_2 (-fpr_offset, -1));
4046 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4047 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4049 /* Emit code to initialize GOFF, the offset from GTOP of the
4050 next GPR argument. */
4051 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4052 build_int_2 (gpr_save_area_size, 0));
4053 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4055 /* Likewise emit code to initialize FOFF, the offset from FTOP
4056 of the next FPR argument. */
4058 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4059 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4060 build_int_2 (fpr_save_area_size, 0));
4061 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4065 /* Everything is in the GPR save area, or in the overflow
4066 area which is contiguous with it. */
4067 nextarg = plus_constant (nextarg, -gpr_save_area_size);
4068 std_expand_builtin_va_start (valist, nextarg);
4072 std_expand_builtin_va_start (valist, nextarg);
4075 /* Implement va_arg. */
4078 mips_va_arg (tree valist, tree type)
4080 HOST_WIDE_INT size, rsize;
4084 size = int_size_in_bytes (type);
4085 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4087 if (mips_abi == ABI_EABI)
4093 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4097 size = POINTER_SIZE / BITS_PER_UNIT;
4098 rsize = UNITS_PER_WORD;
4101 addr_rtx = gen_reg_rtx (Pmode);
4103 if (!EABI_FLOAT_VARARGS_P)
4105 /* Case of all args in a merged stack. No need to check bounds,
4106 just advance valist along the stack. */
4111 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4113 /* Align the pointer using: ap = (ap + align - 1) & -align,
4114 where align is 2 * UNITS_PER_WORD. */
4115 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4116 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4117 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4118 build_int_2 (-2 * UNITS_PER_WORD, -1));
4119 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4120 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4123 /* Emit code to set addr_rtx to the valist, and postincrement
4124 the valist by the size of the argument, rounded up to the
4126 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4128 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4130 emit_move_insn (addr_rtx, r);
4132 /* Flush the POSTINCREMENT. */
4137 /* Not a simple merged stack. */
4139 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4140 tree ovfl, top, off;
4141 rtx lab_over = NULL_RTX, lab_false;
4142 HOST_WIDE_INT osize;
4144 f_ovfl = TYPE_FIELDS (va_list_type_node);
4145 f_gtop = TREE_CHAIN (f_ovfl);
4146 f_ftop = TREE_CHAIN (f_gtop);
4147 f_goff = TREE_CHAIN (f_ftop);
4148 f_foff = TREE_CHAIN (f_goff);
4150 /* We maintain separate pointers and offsets for floating-point
4151 and integer arguments, but we need similar code in both cases.
4154 TOP be the top of the register save area;
4155 OFF be the offset from TOP of the next register;
4156 ADDR_RTX be the address of the argument;
4157 RSIZE be the number of bytes used to store the argument
4158 when it's in the register save area;
4159 OSIZE be the number of bytes used to store it when it's
4160 in the stack overflow area; and
4161 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4163 The code we want is:
4165 1: off &= -rsize; // round down
4168 4: addr_rtx = top - off;
4173 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4174 10: addr_rtx = ovfl + PADDING;
4178 [1] and [9] can sometimes be optimized away. */
4180 lab_false = gen_label_rtx ();
4181 lab_over = gen_label_rtx ();
4183 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4184 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4185 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4187 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4188 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4190 /* When floating-point registers are saved to the stack,
4191 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4192 of the float's precision. */
4193 rsize = UNITS_PER_HWFPVALUE;
4197 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4198 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4199 if (rsize > UNITS_PER_WORD)
4201 /* [1] Emit code for: off &= -rsize. */
4202 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4203 build_int_2 (-rsize, -1));
4204 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4205 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4208 /* Every overflow argument must take up at least UNITS_PER_WORD
4209 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4210 than that, such as in the combination -mgp64 -msingle-float
4211 -fshort-double. Doubles passed in registers will then take
4212 up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
4213 take up UNITS_PER_WORD bytes. */
4214 osize = MAX (rsize, UNITS_PER_WORD);
4216 /* [2] Emit code to branch if off == 0. */
4217 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4219 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4222 /* [4] Emit code for: addr_rtx = top - off. */
4223 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4224 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4226 emit_move_insn (addr_rtx, r);
4228 /* [5] Emit code for: off -= rsize. */
4229 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4230 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4231 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4233 /* [7] Emit code to jump over the else clause, then the label
4236 emit_jump (lab_over);
4238 emit_label (lab_false);
4240 if (osize > UNITS_PER_WORD)
4242 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4243 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4244 build_int_2 (osize - 1, 0));
4245 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4246 build_int_2 (-osize, -1));
4247 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4248 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4251 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4252 post-increment ovfl by osize. On big-endian machines,
4253 the argument has OSIZE - RSIZE bytes of leading padding. */
4254 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4256 if (BYTES_BIG_ENDIAN && osize > rsize)
4257 t = build (PLUS_EXPR, TREE_TYPE (t), t,
4258 build_int_2 (osize - rsize, 0));
4259 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4261 emit_move_insn (addr_rtx, r);
4264 emit_label (lab_over);
4266 if (BYTES_BIG_ENDIAN && rsize != size)
4267 addr_rtx = plus_constant (addr_rtx, rsize - size);
4270 addr_rtx = force_reg (Pmode, addr_rtx);
4271 r = gen_rtx_MEM (Pmode, addr_rtx);
4272 set_mem_alias_set (r, get_varargs_alias_set ());
4273 emit_move_insn (addr_rtx, r);
4281 HOST_WIDE_INT min_offset;
4283 /* ??? The original va-mips.h did always align, despite the fact
4284 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4285 increment mechanism. */
4287 if (TARGET_NEWABI && TYPE_ALIGN (type) > 64)
4289 else if (TARGET_64BIT)
4291 else if (TYPE_ALIGN (type) > 32)
4296 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4297 build_int_2 (align - 1, 0));
4298 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4300 /* If arguments of type TYPE must be passed on the stack,
4301 set MIN_OFFSET to the offset of the first stack parameter. */
4302 if (!MUST_PASS_IN_STACK (TYPE_MODE (type), type))
4304 else if (TARGET_NEWABI)
4305 min_offset = current_function_pretend_args_size;
4307 min_offset = REG_PARM_STACK_SPACE (current_function_decl);
4309 /* Make sure the new address is at least MIN_OFFSET bytes from
4310 the incoming argument pointer. */
4312 t = build (MAX_EXPR, TREE_TYPE (valist), t,
4313 make_tree (TREE_TYPE (valist),
4314 plus_constant (virtual_incoming_args_rtx,
4317 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4318 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4320 /* Everything past the alignment is standard. */
4321 return std_expand_builtin_va_arg (valist, type);
4325 /* Return true if it is possible to use left/right accesses for a
4326 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4327 returning true, update *OP, *LEFT and *RIGHT as follows:
4329 *OP is a BLKmode reference to the whole field.
4331 *LEFT is a QImode reference to the first byte if big endian or
4332 the last byte if little endian. This address can be used in the
4333 left-side instructions (lwl, swl, ldl, sdl).
4335 *RIGHT is a QImode reference to the opposite end of the field and
4336 can be used in the parterning right-side instruction. */
4339 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4340 rtx *left, rtx *right)
4344 /* Check that the operand really is a MEM. Not all the extv and
4345 extzv predicates are checked. */
4346 if (GET_CODE (*op) != MEM)
4349 /* Check that the size is valid. */
4350 if (width != 32 && (!TARGET_64BIT || width != 64))
4353 /* We can only access byte-aligned values. Since we are always passed
4354 a reference to the first byte of the field, it is not necessary to
4355 do anything with BITPOS after this check. */
4356 if (bitpos % BITS_PER_UNIT != 0)
4359 /* Reject aligned bitfields: we want to use a normal load or store
4360 instead of a left/right pair. */
4361 if (MEM_ALIGN (*op) >= width)
4364 /* Adjust *OP to refer to the whole field. This also has the effect
4365 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4366 *op = adjust_address (*op, BLKmode, 0);
4367 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4369 /* Get references to both ends of the field. We deliberately don't
4370 use the original QImode *OP for FIRST since the new BLKmode one
4371 might have a simpler address. */
4372 first = adjust_address (*op, QImode, 0);
4373 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4375 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4376 be the upper word and RIGHT the lower word. */
4377 if (TARGET_BIG_ENDIAN)
4378 *left = first, *right = last;
4380 *left = last, *right = first;
4386 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4387 Return true on success. We only handle cases where zero_extract is
4388 equivalent to sign_extract. */
4391 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4395 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4396 paradoxical word_mode subreg. This is the only case in which
4397 we allow the destination to be larger than the source. */
4398 if (GET_CODE (dest) == SUBREG
4399 && GET_MODE (dest) == DImode
4400 && SUBREG_BYTE (dest) == 0
4401 && GET_MODE (SUBREG_REG (dest)) == SImode)
4402 dest = SUBREG_REG (dest);
4404 /* After the above adjustment, the destination must be the same
4405 width as the source. */
4406 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4409 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4412 if (GET_MODE (dest) == DImode)
4414 emit_insn (gen_mov_ldl (dest, src, left));
4415 emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
4416 right, copy_rtx (dest)));
4420 emit_insn (gen_mov_lwl (dest, src, left));
4421 emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
4422 right, copy_rtx (dest)));
4428 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4432 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4436 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4439 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4441 if (GET_MODE (src) == DImode)
4443 emit_insn (gen_mov_sdl (dest, src, left));
4444 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4448 emit_insn (gen_mov_swl (dest, src, left));
4449 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4454 /* Set up globals to generate code for the ISA or processor
4455 described by INFO. */
4458 mips_set_architecture (const struct mips_cpu_info *info)
4462 mips_arch_info = info;
4463 mips_arch = info->cpu;
4464 mips_isa = info->isa;
4469 /* Likewise for tuning. */
4472 mips_set_tune (const struct mips_cpu_info *info)
4476 mips_tune_info = info;
4477 mips_tune = info->cpu;
4482 /* Set up the threshold for data to go into the small data area, instead
4483 of the normal data area, and detect any conflicts in the switches. */
4486 override_options (void)
4488 int i, start, regno;
4489 enum machine_mode mode;
4491 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4493 /* Interpret -mabi. */
4494 mips_abi = MIPS_ABI_DEFAULT;
4495 if (mips_abi_string != 0)
4497 if (strcmp (mips_abi_string, "32") == 0)
4499 else if (strcmp (mips_abi_string, "o64") == 0)
4501 else if (strcmp (mips_abi_string, "n32") == 0)
4503 else if (strcmp (mips_abi_string, "64") == 0)
4505 else if (strcmp (mips_abi_string, "eabi") == 0)
4506 mips_abi = ABI_EABI;
4508 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4511 /* The following code determines the architecture and register size.
4512 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4513 The GAS and GCC code should be kept in sync as much as possible. */
4515 if (mips_arch_string != 0)
4516 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4518 if (mips_isa_string != 0)
4520 /* Handle -mipsN. */
4521 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4522 const struct mips_cpu_info *isa_info;
4524 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4525 free (whole_isa_str);
4527 /* -march takes precedence over -mipsN, since it is more descriptive.
4528 There's no harm in specifying both as long as the ISA levels
4530 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4531 error ("-mips%s conflicts with the other architecture options, "
4532 "which specify a MIPS%d processor",
4533 mips_isa_string, mips_isa);
4535 /* Set architecture based on the given option. */
4536 mips_set_architecture (isa_info);
4539 if (mips_arch_info == 0)
4541 #ifdef MIPS_CPU_STRING_DEFAULT
4542 mips_set_architecture (mips_parse_cpu ("default CPU",
4543 MIPS_CPU_STRING_DEFAULT));
4545 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4549 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4550 error ("-march=%s is not compatible with the selected ABI",
4551 mips_arch_info->name);
4553 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4554 if (mips_tune_string != 0)
4555 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4557 if (mips_tune_info == 0)
4558 mips_set_tune (mips_arch_info);
4560 if ((target_flags_explicit & MASK_64BIT) != 0)
4562 /* The user specified the size of the integer registers. Make sure
4563 it agrees with the ABI and ISA. */
4564 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4565 error ("-mgp64 used with a 32-bit processor");
4566 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4567 error ("-mgp32 used with a 64-bit ABI");
4568 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4569 error ("-mgp64 used with a 32-bit ABI");
4573 /* Infer the integer register size from the ABI and processor.
4574 Restrict ourselves to 32-bit registers if that's all the
4575 processor has, or if the ABI cannot handle 64-bit registers. */
4576 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4577 target_flags &= ~MASK_64BIT;
4579 target_flags |= MASK_64BIT;
4582 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4584 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4585 only one right answer here. */
4586 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4587 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4588 else if (!TARGET_64BIT && TARGET_FLOAT64)
4589 error ("unsupported combination: %s", "-mgp32 -mfp64");
4590 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4591 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4595 /* -msingle-float selects 32-bit float registers. Otherwise the
4596 float registers should be the same size as the integer ones. */
4597 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4598 target_flags |= MASK_FLOAT64;
4600 target_flags &= ~MASK_FLOAT64;
4603 /* End of code shared with GAS. */
4605 if ((target_flags_explicit & MASK_LONG64) == 0)
4607 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4608 were used, then set the type sizes. In the EABI in 64 bit mode,
4609 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4611 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4612 target_flags |= MASK_LONG64;
4614 target_flags &= ~MASK_LONG64;
4617 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4618 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4620 /* For some configurations, it is useful to have -march control
4621 the default setting of MASK_SOFT_FLOAT. */
4622 switch ((int) mips_arch)
4624 case PROCESSOR_R4100:
4625 case PROCESSOR_R4111:
4626 case PROCESSOR_R4120:
4627 case PROCESSOR_R4130:
4628 target_flags |= MASK_SOFT_FLOAT;
4632 target_flags &= ~MASK_SOFT_FLOAT;
4638 flag_pcc_struct_return = 0;
4640 #if defined(USE_COLLECT2)
4641 /* For IRIX 5 or IRIX 6 with integrated O32 ABI support, USE_COLLECT2 is
4642 always defined when GNU as is not in use, but collect2 is only used
4643 for the O32 ABI, so override the toplev.c and target-def.h defaults
4644 for flag_gnu_linker, TARGET_ASM_{CONSTRUCTOR, DESTRUCTOR} and
4645 TARGET_HAVE_CTORS_DTORS.
4647 Since the IRIX 5 and IRIX 6 O32 assemblers cannot handle named
4648 sections, constructor/destructor handling depends on the ABI in use.
4650 Since USE_COLLECT2 is defined, we only need to restore the non-collect2
4651 defaults for the N32/N64 ABIs. */
4652 if (TARGET_IRIX && !TARGET_SGI_O32_AS)
4654 targetm.have_ctors_dtors = true;
4655 targetm.asm_out.constructor = default_named_section_asm_out_constructor;
4656 targetm.asm_out.destructor = default_named_section_asm_out_destructor;
4660 /* Handle some quirks of the IRIX 5 and IRIX 6 O32 assemblers. */
4662 if (TARGET_SGI_O32_AS)
4664 /* They don't recognize `.[248]byte'. */
4665 targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
4666 targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
4667 /* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
4668 contrary to the documentation, so disable it. */
4669 targetm.asm_out.unaligned_op.di = NULL;
4671 /* They cannot handle named sections. */
4672 targetm.have_named_sections = false;
4673 /* Therefore, EH_FRAME_SECTION_NAME isn't defined and we must use
4675 targetm.terminate_dw2_eh_frame_info = true;
4676 targetm.asm_out.eh_frame_section = collect2_eh_frame_section;
4678 /* They cannot handle debug information. */
4679 if (write_symbols != NO_DEBUG)
4681 /* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
4682 so -mabi=32 isn't usually specified. */
4684 inform ("-g is only supported using GNU as,");
4686 inform ("-g is only supported using GNU as with -mabi=32,");
4687 inform ("-g option disabled");
4688 write_symbols = NO_DEBUG;
4692 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4694 /* If neither -mbranch-likely nor -mno-branch-likely was given
4695 on the command line, set MASK_BRANCHLIKELY based on the target
4698 By default, we enable use of Branch Likely instructions on
4699 all architectures which support them except for MIPS32 and MIPS64
4700 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
4703 The MIPS32 and MIPS64 architecture specifications say "Software
4704 is strongly encouraged to avoid use of Branch Likely
4705 instructions, as they will be removed from a future revision
4706 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4707 issue those instructions unless instructed to do so by
4709 if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
4710 target_flags |= MASK_BRANCHLIKELY;
4712 target_flags &= ~MASK_BRANCHLIKELY;
4714 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4715 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4717 /* The effect of -mabicalls isn't defined for the EABI. */
4718 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4720 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4721 target_flags &= ~MASK_ABICALLS;
4724 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4725 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4726 /* ??? -non_shared turns off pic code generation, but this is not
4728 if (TARGET_ABICALLS)
4731 if (mips_section_threshold > 0)
4732 warning ("-G is incompatible with PIC code which is the default");
4735 /* The MIPS and SGI o32 assemblers expect small-data variables to
4736 be declared before they are used. Although we once had code to
4737 do this, it was very invasive and fragile. It no longer seems
4738 worth the effort. */
4739 if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
4740 mips_section_threshold = 0;
4742 /* We switch to small data sections using ".section", which the native
4743 o32 irix assemblers don't understand. Disable -G accordingly.
4744 We must do this regardless of command-line options since otherwise
4745 the compiler would abort. */
4746 if (!targetm.have_named_sections)
4747 mips_section_threshold = 0;
4749 /* -membedded-pic is a form of PIC code suitable for embedded
4750 systems. All calls are made using PC relative addressing, and
4751 all data is addressed using the $gp register. This requires gas,
4752 which does most of the work, and GNU ld, which automatically
4753 expands PC relative calls which are out of range into a longer
4754 instruction sequence. All gcc really does differently is
4755 generate a different sequence for a switch. */
4756 if (TARGET_EMBEDDED_PIC)
4759 if (TARGET_ABICALLS)
4760 warning ("-membedded-pic and -mabicalls are incompatible");
4763 warning ("-G and -membedded-pic are incompatible");
4765 /* Setting mips_section_threshold is not required, because gas
4766 will force everything to be GP addressable anyhow, but
4767 setting it will cause gcc to make better estimates of the
4768 number of instructions required to access a particular data
4770 mips_section_threshold = 0x7fffffff;
4773 /* mips_split_addresses is a half-way house between explicit
4774 relocations and the traditional assembler macros. It can
4775 split absolute 32-bit symbolic constants into a high/lo_sum
4776 pair but uses macros for other sorts of access.
4778 Like explicit relocation support for REL targets, it relies
4779 on GNU extensions in the assembler and the linker.
4781 Although this code should work for -O0, it has traditionally
4782 been treated as an optimization. */
4783 if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4784 && optimize && !flag_pic
4785 && !ABI_HAS_64BIT_SYMBOLS)
4786 mips_split_addresses = 1;
4788 mips_split_addresses = 0;
4790 /* Explicit relocations for "old" ABIs are a GNU extension. Unless
4791 the user has said otherwise, assume that they are not available
4792 with assemblers other than gas. */
4793 if (!TARGET_NEWABI && !TARGET_GAS
4794 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4795 target_flags &= ~MASK_EXPLICIT_RELOCS;
4797 /* Make -mabicalls -fno-unit-at-a-time imply -mno-explicit-relocs
4798 unless the user says otherwise.
4800 There are two problems here:
4802 (1) The value of an R_MIPS_GOT16 relocation depends on whether
4803 the symbol is local or global. We therefore need to know
4804 a symbol's binding before refering to it using %got().
4806 (2) R_MIPS_CALL16 can only be applied to global symbols.
4808 When not using -funit-at-a-time, a symbol's binding may change
4809 after it has been used. For example, the C++ front-end will
4810 initially assume that the typeinfo for an incomplete type will be
4811 comdat, on the basis that the type could be completed later in the
4812 file. But if the type never is completed, the typeinfo will become
4814 if (!flag_unit_at_a_time
4816 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4817 target_flags &= ~MASK_EXPLICIT_RELOCS;
4819 /* -mrnames says to use the MIPS software convention for register
4820 names instead of the hardware names (ie, $a0 instead of $4).
4821 We do this by switching the names in mips_reg_names, which the
4822 reg_names points into via the REGISTER_NAMES macro. */
4824 if (TARGET_NAME_REGS)
4825 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
4827 /* When compiling for the mips16, we can not use floating point. We
4828 record the original hard float value in mips16_hard_float. */
4831 if (TARGET_SOFT_FLOAT)
4832 mips16_hard_float = 0;
4834 mips16_hard_float = 1;
4835 target_flags |= MASK_SOFT_FLOAT;
4837 /* Don't run the scheduler before reload, since it tends to
4838 increase register pressure. */
4839 flag_schedule_insns = 0;
4841 /* Silently disable -mexplicit-relocs since it doesn't apply
4842 to mips16 code. Even so, it would overly pedantic to warn
4843 about "-mips16 -mexplicit-relocs", especially given that
4844 we use a %gprel() operator. */
4845 target_flags &= ~MASK_EXPLICIT_RELOCS;
4848 /* When using explicit relocs, we call dbr_schedule from within
4850 if (TARGET_EXPLICIT_RELOCS)
4852 mips_flag_delayed_branch = flag_delayed_branch;
4853 flag_delayed_branch = 0;
4856 #ifdef MIPS_TFMODE_FORMAT
4857 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4860 mips_print_operand_punct['?'] = 1;
4861 mips_print_operand_punct['#'] = 1;
4862 mips_print_operand_punct['/'] = 1;
4863 mips_print_operand_punct['&'] = 1;
4864 mips_print_operand_punct['!'] = 1;
4865 mips_print_operand_punct['*'] = 1;
4866 mips_print_operand_punct['@'] = 1;
4867 mips_print_operand_punct['.'] = 1;
4868 mips_print_operand_punct['('] = 1;
4869 mips_print_operand_punct[')'] = 1;
4870 mips_print_operand_punct['['] = 1;
4871 mips_print_operand_punct[']'] = 1;
4872 mips_print_operand_punct['<'] = 1;
4873 mips_print_operand_punct['>'] = 1;
4874 mips_print_operand_punct['{'] = 1;
4875 mips_print_operand_punct['}'] = 1;
4876 mips_print_operand_punct['^'] = 1;
4877 mips_print_operand_punct['$'] = 1;
4878 mips_print_operand_punct['+'] = 1;
4879 mips_print_operand_punct['~'] = 1;
4881 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4882 mips_char_to_class['t'] = T_REG;
4883 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4884 mips_char_to_class['h'] = HI_REG;
4885 mips_char_to_class['l'] = LO_REG;
4886 mips_char_to_class['x'] = MD_REGS;
4887 mips_char_to_class['b'] = ALL_REGS;
4888 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4889 TARGET_MIPS16 ? M16_NA_REGS :
4891 mips_char_to_class['e'] = LEA_REGS;
4892 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4893 mips_char_to_class['y'] = GR_REGS;
4894 mips_char_to_class['z'] = ST_REGS;
4895 mips_char_to_class['B'] = COP0_REGS;
4896 mips_char_to_class['C'] = COP2_REGS;
4897 mips_char_to_class['D'] = COP3_REGS;
4899 /* Set up array to map GCC register number to debug register number.
4900 Ignore the special purpose register numbers. */
4902 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4903 mips_dbx_regno[i] = -1;
4905 start = GP_DBX_FIRST - GP_REG_FIRST;
4906 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4907 mips_dbx_regno[i] = i + start;
4909 start = FP_DBX_FIRST - FP_REG_FIRST;
4910 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4911 mips_dbx_regno[i] = i + start;
4913 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4914 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4916 /* Set up array giving whether a given register can hold a given mode. */
4918 for (mode = VOIDmode;
4919 mode != MAX_MACHINE_MODE;
4920 mode = (enum machine_mode) ((int)mode + 1))
4922 register int size = GET_MODE_SIZE (mode);
4923 register enum mode_class class = GET_MODE_CLASS (mode);
4925 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4932 temp = (regno == FPSW_REGNUM);
4934 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4935 || FP_REG_P (regno));
4938 else if (GP_REG_P (regno))
4939 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4941 else if (FP_REG_P (regno))
4942 temp = ((regno % FP_INC) == 0)
4943 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
4944 && size <= UNITS_PER_FPVALUE)
4945 /* Allow integer modes that fit into a single
4946 register. We need to put integers into FPRs
4947 when using instructions like cvt and trunc. */
4948 || (class == MODE_INT && size <= UNITS_PER_FPREG)
4949 /* Allow TFmode for CCmode reloads. */
4950 || (ISA_HAS_8CC && mode == TFmode));
4952 else if (MD_REG_P (regno))
4953 temp = (class == MODE_INT
4954 && (size <= UNITS_PER_WORD
4955 || (regno == MD_REG_FIRST
4956 && size == 2 * UNITS_PER_WORD)));
4958 else if (ALL_COP_REG_P (regno))
4959 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4963 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4967 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4968 initialized yet, so we can't use that here. */
4969 gpr_mode = TARGET_64BIT ? DImode : SImode;
4971 /* Provide default values for align_* for 64-bit targets. */
4972 if (TARGET_64BIT && !TARGET_MIPS16)
4974 if (align_loops == 0)
4976 if (align_jumps == 0)
4978 if (align_functions == 0)
4979 align_functions = 8;
4982 /* Function to allocate machine-dependent function status. */
4983 init_machine_status = &mips_init_machine_status;
4985 if (ABI_HAS_64BIT_SYMBOLS)
4987 if (TARGET_EXPLICIT_RELOCS)
4989 mips_split_p[SYMBOL_64_HIGH] = true;
4990 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4991 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4993 mips_split_p[SYMBOL_64_MID] = true;
4994 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4995 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4997 mips_split_p[SYMBOL_64_LOW] = true;
4998 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4999 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5001 mips_split_p[SYMBOL_GENERAL] = true;
5002 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5007 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5009 mips_split_p[SYMBOL_GENERAL] = true;
5010 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5011 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5017 /* The high part is provided by a pseudo copy of $gp. */
5018 mips_split_p[SYMBOL_SMALL_DATA] = true;
5019 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5022 if (TARGET_EXPLICIT_RELOCS)
5024 /* Small data constants are kept whole until after reload,
5025 then lowered by mips_rewrite_small_data. */
5026 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5028 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5031 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5032 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5036 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5037 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5042 /* The HIGH and LO_SUM are matched by special .md patterns. */
5043 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5045 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5046 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5047 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5049 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5050 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5051 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5056 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5058 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5059 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5065 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5066 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5067 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5070 /* Default to working around R4000 errata only if the processor
5071 was selected explicitly. */
5072 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5073 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5074 target_flags |= MASK_FIX_R4000;
5076 /* Default to working around R4400 errata only if the processor
5077 was selected explicitly. */
5078 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5079 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5080 target_flags |= MASK_FIX_R4400;
5083 /* Implement CONDITIONAL_REGISTER_USAGE. */
5086 mips_conditional_register_usage (void)
5088 if (!TARGET_HARD_FLOAT)
5092 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5093 fixed_regs[regno] = call_used_regs[regno] = 1;
5094 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5095 fixed_regs[regno] = call_used_regs[regno] = 1;
5097 else if (! ISA_HAS_8CC)
5101 /* We only have a single condition code register. We
5102 implement this by hiding all the condition code registers,
5103 and generating RTL that refers directly to ST_REG_FIRST. */
5104 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5105 fixed_regs[regno] = call_used_regs[regno] = 1;
5107 /* In mips16 mode, we permit the $t temporary registers to be used
5108 for reload. We prohibit the unused $s registers, since they
5109 are caller saved, and saving them via a mips16 register would
5110 probably waste more time than just reloading the value. */
5113 fixed_regs[18] = call_used_regs[18] = 1;
5114 fixed_regs[19] = call_used_regs[19] = 1;
5115 fixed_regs[20] = call_used_regs[20] = 1;
5116 fixed_regs[21] = call_used_regs[21] = 1;
5117 fixed_regs[22] = call_used_regs[22] = 1;
5118 fixed_regs[23] = call_used_regs[23] = 1;
5119 fixed_regs[26] = call_used_regs[26] = 1;
5120 fixed_regs[27] = call_used_regs[27] = 1;
5121 fixed_regs[30] = call_used_regs[30] = 1;
5123 /* fp20-23 are now caller saved. */
5124 if (mips_abi == ABI_64)
5127 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5128 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5130 /* Odd registers from fp21 to fp31 are now caller saved. */
5131 if (mips_abi == ABI_N32)
5134 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5135 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5139 /* Allocate a chunk of memory for per-function machine-dependent data. */
5140 static struct machine_function *
5141 mips_init_machine_status (void)
5143 return ((struct machine_function *)
5144 ggc_alloc_cleared (sizeof (struct machine_function)));
5147 /* On the mips16, we want to allocate $24 (T_REG) before other
5148 registers for instructions for which it is possible. This helps
5149 avoid shuffling registers around in order to set up for an xor,
5150 encouraging the compiler to use a cmp instead. */
5153 mips_order_regs_for_local_alloc (void)
5157 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5158 reg_alloc_order[i] = i;
5162 /* It really doesn't matter where we put register 0, since it is
5163 a fixed register anyhow. */
5164 reg_alloc_order[0] = 24;
5165 reg_alloc_order[24] = 0;
5170 /* The MIPS debug format wants all automatic variables and arguments
5171 to be in terms of the virtual frame pointer (stack pointer before
5172 any adjustment in the function), while the MIPS 3.0 linker wants
5173 the frame pointer to be the stack pointer after the initial
5174 adjustment. So, we do the adjustment here. The arg pointer (which
5175 is eliminated) points to the virtual frame pointer, while the frame
5176 pointer (which may be eliminated) points to the stack pointer after
5177 the initial adjustments. */
5180 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5182 rtx offset2 = const0_rtx;
5183 rtx reg = eliminate_constant_term (addr, &offset2);
5186 offset = INTVAL (offset2);
5188 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5189 || reg == hard_frame_pointer_rtx)
5191 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5192 ? compute_frame_size (get_frame_size ())
5193 : cfun->machine->frame.total_size;
5195 /* MIPS16 frame is smaller */
5196 if (frame_pointer_needed && TARGET_MIPS16)
5197 frame_size -= cfun->machine->frame.args_size;
5199 offset = offset - frame_size;
5202 /* sdbout_parms does not want this to crash for unrecognized cases. */
5204 else if (reg != arg_pointer_rtx)
5205 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5212 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5214 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5215 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5216 'h' OP is HIGH, prints %hi(X),
5217 'd' output integer constant in decimal,
5218 'z' if the operand is 0, use $0 instead of normal operand.
5219 'D' print second part of double-word register or memory operand.
5220 'L' print low-order register of double-word register operand.
5221 'M' print high-order register of double-word register operand.
5222 'C' print part of opcode for a branch condition.
5223 'F' print part of opcode for a floating-point branch condition.
5224 'N' print part of opcode for a branch condition, inverted.
5225 'W' print part of opcode for a floating-point branch condition, inverted.
5226 'S' OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5227 'B' print 'z' for EQ, 'n' for NE
5228 'b' print 'n' for EQ, 'z' for NE
5229 'T' print 'f' for EQ, 't' for NE
5230 't' print 't' for EQ, 'f' for NE
5231 'Z' print register and a comma, but print nothing for $fcc0
5232 'R' print the reloc associated with LO_SUM
5234 The punctuation characters are:
5236 '(' Turn on .set noreorder
5237 ')' Turn on .set reorder
5238 '[' Turn on .set noat
5240 '<' Turn on .set nomacro
5241 '>' Turn on .set macro
5242 '{' Turn on .set volatile (not GAS)
5243 '}' Turn on .set novolatile (not GAS)
5244 '&' Turn on .set noreorder if filling delay slots
5245 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5246 '!' Turn on .set nomacro if filling delay slots
5247 '#' Print nop if in a .set noreorder section.
5248 '/' Like '#', but does nothing within a delayed branch sequence
5249 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5250 '@' Print the name of the assembler temporary register (at or $1).
5251 '.' Print the name of the register with a hard-wired zero (zero or $0).
5252 '^' Print the name of the pic call-through register (t9 or $25).
5253 '$' Print the name of the stack pointer register (sp or $29).
5254 '+' Print the name of the gp register (usually gp or $28).
5255 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5258 print_operand (FILE *file, rtx op, int letter)
5260 register enum rtx_code code;
5262 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5267 if (mips_branch_likely)
5272 fputs (reg_names [GP_REG_FIRST + 1], file);
5276 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5280 fputs (reg_names [GP_REG_FIRST + 0], file);
5284 fputs (reg_names[STACK_POINTER_REGNUM], file);
5288 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5292 if (final_sequence != 0 && set_noreorder++ == 0)
5293 fputs (".set\tnoreorder\n\t", file);
5297 if (final_sequence != 0)
5299 if (set_noreorder++ == 0)
5300 fputs (".set\tnoreorder\n\t", file);
5302 if (set_nomacro++ == 0)
5303 fputs (".set\tnomacro\n\t", file);
5308 if (final_sequence != 0 && set_nomacro++ == 0)
5309 fputs ("\n\t.set\tnomacro", file);
5313 if (set_noreorder != 0)
5314 fputs ("\n\tnop", file);
5318 /* Print an extra newline so that the delayed insn is separated
5319 from the following ones. This looks neater and is consistent
5320 with non-nop delayed sequences. */
5321 if (set_noreorder != 0 && final_sequence == 0)
5322 fputs ("\n\tnop\n", file);
5326 if (set_noreorder++ == 0)
5327 fputs (".set\tnoreorder\n\t", file);
5331 if (set_noreorder == 0)
5332 error ("internal error: %%) found without a %%( in assembler pattern");
5334 else if (--set_noreorder == 0)
5335 fputs ("\n\t.set\treorder", file);
5340 if (set_noat++ == 0)
5341 fputs (".set\tnoat\n\t", file);
5346 error ("internal error: %%] found without a %%[ in assembler pattern");
5347 else if (--set_noat == 0)
5348 fputs ("\n\t.set\tat", file);
5353 if (set_nomacro++ == 0)
5354 fputs (".set\tnomacro\n\t", file);
5358 if (set_nomacro == 0)
5359 error ("internal error: %%> found without a %%< in assembler pattern");
5360 else if (--set_nomacro == 0)
5361 fputs ("\n\t.set\tmacro", file);
5366 if (set_volatile++ == 0)
5367 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5371 if (set_volatile == 0)
5372 error ("internal error: %%} found without a %%{ in assembler pattern");
5373 else if (--set_volatile == 0)
5374 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5380 if (align_labels_log > 0)
5381 ASM_OUTPUT_ALIGN (file, align_labels_log);
5386 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5395 error ("PRINT_OPERAND null pointer");
5399 code = GET_CODE (op);
5404 case EQ: fputs ("eq", file); break;
5405 case NE: fputs ("ne", file); break;
5406 case GT: fputs ("gt", file); break;
5407 case GE: fputs ("ge", file); break;
5408 case LT: fputs ("lt", file); break;
5409 case LE: fputs ("le", file); break;
5410 case GTU: fputs ("gtu", file); break;
5411 case GEU: fputs ("geu", file); break;
5412 case LTU: fputs ("ltu", file); break;
5413 case LEU: fputs ("leu", file); break;
5415 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5418 else if (letter == 'N')
5421 case EQ: fputs ("ne", file); break;
5422 case NE: fputs ("eq", file); break;
5423 case GT: fputs ("le", file); break;
5424 case GE: fputs ("lt", file); break;
5425 case LT: fputs ("ge", file); break;
5426 case LE: fputs ("gt", file); break;
5427 case GTU: fputs ("leu", file); break;
5428 case GEU: fputs ("ltu", file); break;
5429 case LTU: fputs ("geu", file); break;
5430 case LEU: fputs ("gtu", file); break;
5432 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5435 else if (letter == 'F')
5438 case EQ: fputs ("c1f", file); break;
5439 case NE: fputs ("c1t", file); break;
5441 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5444 else if (letter == 'W')
5447 case EQ: fputs ("c1t", file); break;
5448 case NE: fputs ("c1f", file); break;
5450 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5453 else if (letter == 'h')
5455 if (GET_CODE (op) == HIGH)
5458 print_operand_reloc (file, op, mips_hi_relocs);
5461 else if (letter == 'R')
5462 print_operand_reloc (file, op, mips_lo_relocs);
5464 else if (letter == 'S')
5468 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5469 assemble_name (file, buffer);
5472 else if (letter == 'Z')
5474 register int regnum;
5479 regnum = REGNO (op);
5480 if (! ST_REG_P (regnum))
5483 if (regnum != ST_REG_FIRST)
5484 fprintf (file, "%s,", reg_names[regnum]);
5487 else if (code == REG || code == SUBREG)
5489 register int regnum;
5492 regnum = REGNO (op);
5494 regnum = true_regnum (op);
5496 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5497 || (letter == 'L' && WORDS_BIG_ENDIAN)
5501 fprintf (file, "%s", reg_names[regnum]);
5504 else if (code == MEM)
5507 output_address (plus_constant (XEXP (op, 0), 4));
5509 output_address (XEXP (op, 0));
5512 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5513 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5515 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5516 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5518 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5519 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5521 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5522 fputs (reg_names[GP_REG_FIRST], file);
5524 else if (letter == 'd' || letter == 'x' || letter == 'X')
5525 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5527 else if (letter == 'B')
5528 fputs (code == EQ ? "z" : "n", file);
5529 else if (letter == 'b')
5530 fputs (code == EQ ? "n" : "z", file);
5531 else if (letter == 'T')
5532 fputs (code == EQ ? "f" : "t", file);
5533 else if (letter == 't')
5534 fputs (code == EQ ? "t" : "f", file);
5536 else if (CONST_GP_P (op))
5537 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5540 output_addr_const (file, op);
5544 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5545 RELOCS is the array of relocations to use. */
5548 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5550 enum mips_symbol_type symbol_type;
5553 HOST_WIDE_INT offset;
5555 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5556 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5558 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5559 mips_split_const (op, &base, &offset);
5560 if (UNSPEC_ADDRESS_P (base))
5561 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5563 fputs (relocs[symbol_type], file);
5564 output_addr_const (file, op);
5565 for (p = relocs[symbol_type]; *p != 0; p++)
5570 /* Output address operand X to FILE. */
5573 print_operand_address (FILE *file, rtx x)
5575 struct mips_address_info addr;
5577 if (mips_classify_address (&addr, x, word_mode, true))
5581 print_operand (file, addr.offset, 0);
5582 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5585 case ADDRESS_LO_SUM:
5586 print_operand (file, addr.offset, 'R');
5587 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5590 case ADDRESS_CONST_INT:
5591 case ADDRESS_SYMBOLIC:
5592 output_addr_const (file, x);
5598 /* Target hook for assembling integer objects. It appears that the Irix
5599 6 assembler can't handle 64-bit decimal integers, so avoid printing
5600 such an integer here. */
5603 mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
5605 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5607 fputs ("\t.dword\t", asm_out_file);
5608 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5609 output_addr_const (asm_out_file, x);
5611 print_operand (asm_out_file, x, 'X');
5612 fputc ('\n', asm_out_file);
5615 return default_assemble_integer (x, size, aligned_p);
5618 /* When using assembler macros, keep track of all of small-data externs
5619 so that mips_file_end can emit the appropriate declarations for them.
5621 In most cases it would be safe (though pointless) to emit .externs
5622 for other symbols too. One exception is when an object is within
5623 the -G limit but declared by the user to be in a section other
5624 than .sbss or .sdata. */
5627 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5629 register struct extern_list *p;
5631 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5633 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5634 p->next = extern_head;
5636 p->size = int_size_in_bytes (TREE_TYPE (decl));
5640 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5642 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5643 p->next = extern_head;
5654 irix_output_external_libcall (rtx fun)
5656 register struct extern_list *p;
5658 if (mips_abi == ABI_32)
5660 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5661 p->next = extern_head;
5662 p->name = XSTR (fun, 0);
5669 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5670 put out a MIPS ECOFF file and a stab. */
5673 mips_output_filename (FILE *stream, const char *name)
5675 char ltext_label_name[100];
5677 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5679 if (write_symbols == DWARF2_DEBUG)
5681 else if (mips_output_filename_first_time)
5683 mips_output_filename_first_time = 0;
5685 current_function_file = name;
5686 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5687 /* This tells mips-tfile that stabs will follow. */
5688 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5689 fprintf (stream, "\t#@stabs\n");
5692 else if (write_symbols == DBX_DEBUG)
5694 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5695 fprintf (stream, "%s", ASM_STABS_OP);
5696 output_quoted_string (stream, name);
5697 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5700 else if (name != current_function_file
5701 && strcmp (name, current_function_file) != 0)
5704 current_function_file = name;
5705 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5709 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5710 as well as a .loc, since it is possible that MIPS ECOFF might not be
5711 able to represent the location for inlines that come from a different
5715 mips_output_lineno (FILE *stream, int line)
5717 if (write_symbols == DBX_DEBUG)
5720 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5721 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5722 LOCAL_LABEL_PREFIX, sym_lineno);
5726 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
5727 LABEL_AFTER_LOC (stream);
5731 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5732 that should be written before the opening quote, such as "\t.ascii\t"
5733 for real string data or "\t# " for a comment. */
5736 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5741 register const unsigned char *string =
5742 (const unsigned char *)string_param;
5744 fprintf (stream, "%s\"", prefix);
5745 for (i = 0; i < len; i++)
5747 register int c = string[i];
5753 putc ('\\', stream);
5758 case TARGET_NEWLINE:
5759 fputs ("\\n", stream);
5761 && (((c = string[i+1]) >= '\040' && c <= '~')
5762 || c == TARGET_TAB))
5763 cur_pos = 32767; /* break right here */
5769 fputs ("\\t", stream);
5774 fputs ("\\f", stream);
5779 fputs ("\\b", stream);
5784 fputs ("\\r", stream);
5789 if (c >= ' ' && c < 0177)
5796 fprintf (stream, "\\%03o", c);
5801 if (cur_pos > 72 && i+1 < len)
5804 fprintf (stream, "\"\n%s\"", prefix);
5807 fprintf (stream, "\"\n");
5810 /* Implement TARGET_ASM_FILE_START. */
5813 mips_file_start (void)
5815 default_file_start ();
5817 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5818 inside of a .set noreorder section jumps to a label outside of the .set
5819 noreorder section. Revision 2.20 just set nobopt silently rather than
5822 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5823 fprintf (asm_out_file, "\t.set\tnobopt\n");
5827 #if defined(OBJECT_FORMAT_ELF) && !TARGET_IRIX
5828 /* Generate a special section to describe the ABI switches used to
5829 produce the resultant binary. This used to be done by the assembler
5830 setting bits in the ELF header's flags field, but we have run out of
5831 bits. GDB needs this information in order to be able to correctly
5832 debug these binaries. See the function mips_gdbarch_init() in
5833 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5834 causes unnecessary IRIX 6 ld warnings. */
5835 const char * abi_string = NULL;
5839 case ABI_32: abi_string = "abi32"; break;
5840 case ABI_N32: abi_string = "abiN32"; break;
5841 case ABI_64: abi_string = "abi64"; break;
5842 case ABI_O64: abi_string = "abiO64"; break;
5843 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5847 /* Note - we use fprintf directly rather than called named_section()
5848 because in this way we can avoid creating an allocated section. We
5849 do not want this section to take up any space in the running
5851 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5853 /* Restore the default section. */
5854 fprintf (asm_out_file, "\t.previous\n");
5858 /* Generate the pseudo ops that System V.4 wants. */
5859 #ifndef ABICALLS_ASM_OP
5860 #define ABICALLS_ASM_OP "\t.abicalls"
5862 if (TARGET_ABICALLS)
5863 /* ??? but do not want this (or want pic0) if -non-shared? */
5864 fprintf (asm_out_file, "%s\n", ABICALLS_ASM_OP);
5867 fprintf (asm_out_file, "\t.set\tmips16\n");
5869 if (flag_verbose_asm)
5870 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5872 mips_section_threshold, mips_arch_info->name, mips_isa);
5875 #ifdef BSS_SECTION_ASM_OP
5876 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5877 in the use of sbss. */
5880 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5881 unsigned HOST_WIDE_INT size, int align)
5883 extern tree last_assemble_variable_decl;
5885 if (mips_in_small_data_p (decl))
5886 named_section (0, ".sbss", 0);
5889 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5890 last_assemble_variable_decl = decl;
5891 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5892 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5896 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5897 .externs for any small-data variables that turned out to be external. */
5900 mips_file_end (void)
5903 struct extern_list *p;
5907 fputs ("\n", asm_out_file);
5909 for (p = extern_head; p != 0; p = p->next)
5911 name_tree = get_identifier (p->name);
5913 /* Positively ensure only one .extern for any given symbol. */
5914 if (!TREE_ASM_WRITTEN (name_tree)
5915 && TREE_SYMBOL_REFERENCED (name_tree))
5917 TREE_ASM_WRITTEN (name_tree) = 1;
5918 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5919 `.global name .text' directive for every used but
5920 undefined function. If we don't, the linker may perform
5921 an optimization (skipping over the insns that set $gp)
5922 when it is unsafe. */
5923 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5925 fputs ("\t.globl ", asm_out_file);
5926 assemble_name (asm_out_file, p->name);
5927 fputs (" .text\n", asm_out_file);
5931 fputs ("\t.extern\t", asm_out_file);
5932 assemble_name (asm_out_file, p->name);
5933 fprintf (asm_out_file, ", %d\n", p->size);
5940 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as
5941 the elfos.h version, but we also need to handle -muninit-const-in-rodata
5942 and the limitations of the SGI o32 assembler. */
5945 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5946 unsigned HOST_WIDE_INT size,
5949 /* If the target wants uninitialized const declarations in
5950 .rdata then don't put them in .comm. */
5951 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5952 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5953 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5955 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5956 targetm.asm_out.globalize_label (stream, name);
5958 readonly_data_section ();
5959 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5960 mips_declare_object (stream, name, "",
5961 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5964 else if (TARGET_SGI_O32_AS)
5966 /* The SGI o32 assembler doesn't accept an alignment, so round up
5967 the size instead. */
5968 size += (align / BITS_PER_UNIT) - 1;
5969 size -= size % (align / BITS_PER_UNIT);
5970 mips_declare_object (stream, name, "\n\t.comm\t",
5971 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5974 mips_declare_object (stream, name, "\n\t.comm\t",
5975 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5976 size, align / BITS_PER_UNIT);
5979 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5980 macros, mark the symbol as written so that mips_file_end won't emit an
5981 .extern for it. STREAM is the output file, NAME is the name of the
5982 symbol, INIT_STRING is the string that should be written before the
5983 symbol and FINAL_STRING is the string that should be written after it.
5984 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5987 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5988 const char *final_string, ...)
5992 fputs (init_string, stream);
5993 assemble_name (stream, name);
5994 va_start (ap, final_string);
5995 vfprintf (stream, final_string, ap);
5998 if (!TARGET_EXPLICIT_RELOCS)
6000 tree name_tree = get_identifier (name);
6001 TREE_ASM_WRITTEN (name_tree) = 1;
6005 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6006 extern int size_directive_output;
6008 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6009 definitions except that it uses mips_declare_object() to emit the label. */
6012 mips_declare_object_name (FILE *stream, const char *name,
6013 tree decl ATTRIBUTE_UNUSED)
6015 if (!TARGET_SGI_O32_AS)
6017 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6018 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6021 size_directive_output = 0;
6022 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6026 size_directive_output = 1;
6027 size = int_size_in_bytes (TREE_TYPE (decl));
6028 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6032 mips_declare_object (stream, name, "", ":\n", 0);
6035 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6038 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6042 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6043 if (!TARGET_SGI_O32_AS
6044 && !flag_inhibit_size_directive
6045 && DECL_SIZE (decl) != 0
6046 && !at_end && top_level
6047 && DECL_INITIAL (decl) == error_mark_node
6048 && !size_directive_output)
6052 size_directive_output = 1;
6053 size = int_size_in_bytes (TREE_TYPE (decl));
6054 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6059 /* Return true if X is a small data address that can be rewritten
6063 mips_rewrite_small_data_p (rtx x)
6065 enum mips_symbol_type symbol_type;
6067 return (TARGET_EXPLICIT_RELOCS
6068 && mips_symbolic_constant_p (x, &symbol_type)
6069 && symbol_type == SYMBOL_SMALL_DATA);
6073 /* A for_each_rtx callback for small_data_pattern. */
6076 small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6078 if (GET_CODE (*loc) == LO_SUM)
6081 return mips_rewrite_small_data_p (*loc);
6084 /* Return true if OP refers to small data symbols directly, not through
6088 small_data_pattern (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
6090 return (GET_CODE (op) != SEQUENCE
6091 && for_each_rtx (&op, small_data_pattern_1, 0));
6094 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6097 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6099 if (mips_rewrite_small_data_p (*loc))
6100 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6102 if (GET_CODE (*loc) == LO_SUM)
6108 /* If possible, rewrite OP so that it refers to small data using
6109 explicit relocations. */
6112 mips_rewrite_small_data (rtx op)
6114 op = copy_insn (op);
6115 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6119 /* Return true if the current function has an insn that implicitly
6123 mips_function_has_gp_insn (void)
6125 /* Don't bother rechecking if we found one last time. */
6126 if (!cfun->machine->has_gp_insn_p)
6130 push_topmost_sequence ();
6131 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6133 && GET_CODE (PATTERN (insn)) != USE
6134 && GET_CODE (PATTERN (insn)) != CLOBBER
6135 && (get_attr_got (insn) != GOT_UNSET
6136 || small_data_pattern (PATTERN (insn), VOIDmode)))
6138 pop_topmost_sequence ();
6140 cfun->machine->has_gp_insn_p = (insn != 0);
6142 return cfun->machine->has_gp_insn_p;
6146 /* Return the register that should be used as the global pointer
6147 within this function. Return 0 if the function doesn't need
6148 a global pointer. */
6151 mips_global_pointer (void)
6155 /* $gp is always available in non-abicalls code. */
6156 if (!TARGET_ABICALLS)
6157 return GLOBAL_POINTER_REGNUM;
6159 /* We must always provide $gp when it is used implicitly. */
6160 if (!TARGET_EXPLICIT_RELOCS)
6161 return GLOBAL_POINTER_REGNUM;
6163 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6165 if (current_function_profile)
6166 return GLOBAL_POINTER_REGNUM;
6168 /* If the function has a nonlocal goto, $gp must hold the correct
6169 global pointer for the target function. */
6170 if (current_function_has_nonlocal_goto)
6171 return GLOBAL_POINTER_REGNUM;
6173 /* If the gp is never referenced, there's no need to initialize it.
6174 Note that reload can sometimes introduce constant pool references
6175 into a function that otherwise didn't need them. For example,
6176 suppose we have an instruction like:
6178 (set (reg:DF R1) (float:DF (reg:SI R2)))
6180 If R2 turns out to be constant such as 1, the instruction may have a
6181 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6182 using this constant if R2 doesn't get allocated to a register.
6184 In cases like these, reload will have added the constant to the pool
6185 but no instruction will yet refer to it. */
6186 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6187 && !current_function_uses_const_pool
6188 && !mips_function_has_gp_insn ())
6191 /* We need a global pointer, but perhaps we can use a call-clobbered
6192 register instead of $gp. */
6193 if (TARGET_NEWABI && current_function_is_leaf)
6194 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6195 if (!regs_ever_live[regno]
6196 && call_used_regs[regno]
6197 && !fixed_regs[regno]
6198 && regno != PIC_FUNCTION_ADDR_REGNUM)
6201 return GLOBAL_POINTER_REGNUM;
6205 /* Return true if the current function must save REGNO. */
6208 mips_save_reg_p (unsigned int regno)
6210 /* We only need to save $gp for NewABI PIC. */
6211 if (regno == GLOBAL_POINTER_REGNUM)
6212 return (TARGET_ABICALLS && TARGET_NEWABI
6213 && cfun->machine->global_pointer == regno);
6215 /* Check call-saved registers. */
6216 if (regs_ever_live[regno] && !call_used_regs[regno])
6219 /* We need to save the old frame pointer before setting up a new one. */
6220 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6223 /* We need to save the incoming return address if it is ever clobbered
6224 within the function. */
6225 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6232 return_type = DECL_RESULT (current_function_decl);
6234 /* $18 is a special case in mips16 code. It may be used to call
6235 a function which returns a floating point value, but it is
6236 marked in call_used_regs. */
6237 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6240 /* $31 is also a special case. It will be used to copy a return
6241 value into the floating point registers if the return value is
6243 if (regno == GP_REG_FIRST + 31
6244 && mips16_hard_float
6245 && !aggregate_value_p (return_type, current_function_decl)
6246 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6247 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6255 /* Return the bytes needed to compute the frame pointer from the current
6256 stack pointer. SIZE is the size (in bytes) of the local variables.
6258 Mips stack frames look like:
6260 Before call After call
6261 +-----------------------+ +-----------------------+
6264 | caller's temps. | | caller's temps. |
6266 +-----------------------+ +-----------------------+
6268 | arguments on stack. | | arguments on stack. |
6270 +-----------------------+ +-----------------------+
6271 | 4 words to save | | 4 words to save |
6272 | arguments passed | | arguments passed |
6273 | in registers, even | | in registers, even |
6274 SP->| if not passed. | VFP->| if not passed. |
6275 +-----------------------+ +-----------------------+
6277 | fp register save |
6279 +-----------------------+
6281 | gp register save |
6283 +-----------------------+
6287 +-----------------------+
6289 | alloca allocations |
6291 +-----------------------+
6293 | GP save for V.4 abi |
6295 +-----------------------+
6297 | arguments on stack |
6299 +-----------------------+
6301 | arguments passed |
6302 | in registers, even |
6303 low SP->| if not passed. |
6304 memory +-----------------------+
6309 compute_frame_size (HOST_WIDE_INT size)
6312 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6313 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6314 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6315 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6316 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6317 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6318 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6319 unsigned int mask; /* mask of saved gp registers */
6320 unsigned int fmask; /* mask of saved fp registers */
6322 cfun->machine->global_pointer = mips_global_pointer ();
6328 var_size = MIPS_STACK_ALIGN (size);
6329 args_size = current_function_outgoing_args_size;
6330 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6332 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6333 functions. If the function has local variables, we're committed
6334 to allocating it anyway. Otherwise reclaim it here. */
6335 if (var_size == 0 && current_function_is_leaf)
6336 cprestore_size = args_size = 0;
6338 /* The MIPS 3.0 linker does not like functions that dynamically
6339 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6340 looks like we are trying to create a second frame pointer to the
6341 function, so allocate some stack space to make it happy. */
6343 if (args_size == 0 && current_function_calls_alloca)
6344 args_size = 4 * UNITS_PER_WORD;
6346 total_size = var_size + args_size + cprestore_size;
6348 /* Calculate space needed for gp registers. */
6349 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6350 if (mips_save_reg_p (regno))
6352 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6353 mask |= 1 << (regno - GP_REG_FIRST);
6356 /* We need to restore these for the handler. */
6357 if (current_function_calls_eh_return)
6362 regno = EH_RETURN_DATA_REGNO (i);
6363 if (regno == INVALID_REGNUM)
6365 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6366 mask |= 1 << (regno - GP_REG_FIRST);
6370 /* This loop must iterate over the same space as its companion in
6371 save_restore_insns. */
6372 for (regno = (FP_REG_LAST - FP_INC + 1);
6373 regno >= FP_REG_FIRST;
6376 if (mips_save_reg_p (regno))
6378 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6379 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6383 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6384 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6386 /* Add in space reserved on the stack by the callee for storing arguments
6387 passed in registers. */
6389 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6391 /* Save other computed information. */
6392 cfun->machine->frame.total_size = total_size;
6393 cfun->machine->frame.var_size = var_size;
6394 cfun->machine->frame.args_size = args_size;
6395 cfun->machine->frame.cprestore_size = cprestore_size;
6396 cfun->machine->frame.gp_reg_size = gp_reg_size;
6397 cfun->machine->frame.fp_reg_size = fp_reg_size;
6398 cfun->machine->frame.mask = mask;
6399 cfun->machine->frame.fmask = fmask;
6400 cfun->machine->frame.initialized = reload_completed;
6401 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6402 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6406 HOST_WIDE_INT offset;
6408 offset = (args_size + cprestore_size + var_size
6409 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6410 cfun->machine->frame.gp_sp_offset = offset;
6411 cfun->machine->frame.gp_save_offset = offset - total_size;
6415 cfun->machine->frame.gp_sp_offset = 0;
6416 cfun->machine->frame.gp_save_offset = 0;
6421 HOST_WIDE_INT offset;
6423 offset = (args_size + cprestore_size + var_size
6424 + gp_reg_rounded + fp_reg_size
6425 - FP_INC * UNITS_PER_FPREG);
6426 cfun->machine->frame.fp_sp_offset = offset;
6427 cfun->machine->frame.fp_save_offset = offset - total_size;
6431 cfun->machine->frame.fp_sp_offset = 0;
6432 cfun->machine->frame.fp_save_offset = 0;
6435 /* Ok, we're done. */
6439 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6440 pointer or argument pointer. TO is either the stack pointer or
6441 hard frame pointer. */
6444 mips_initial_elimination_offset (int from, int to)
6446 HOST_WIDE_INT offset;
6448 compute_frame_size (get_frame_size ());
6450 /* Set OFFSET to the offset from the stack pointer. */
6453 case FRAME_POINTER_REGNUM:
6457 case ARG_POINTER_REGNUM:
6458 offset = cfun->machine->frame.total_size;
6460 offset -= current_function_pretend_args_size;
6467 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6468 offset -= cfun->machine->frame.args_size;
6473 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6474 back to a previous frame. */
6476 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6481 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6484 /* Use FN to save or restore register REGNO. MODE is the register's
6485 mode and OFFSET is the offset of its save slot from the current
6489 mips_save_restore_reg (enum machine_mode mode, int regno,
6490 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6494 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6495 if (!current_function_calls_eh_return)
6496 RTX_UNCHANGING_P (mem) = 1;
6498 fn (gen_rtx_REG (mode, regno), mem);
6502 /* Call FN for each register that is saved by the current function.
6503 SP_OFFSET is the offset of the current stack pointer from the start
6507 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6509 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6511 enum machine_mode fpr_mode;
6512 HOST_WIDE_INT offset;
6515 /* Save registers starting from high to low. The debuggers prefer at least
6516 the return register be stored at func+4, and also it allows us not to
6517 need a nop in the epilog if at least one register is reloaded in
6518 addition to return address. */
6519 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6520 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6521 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6523 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6524 offset -= GET_MODE_SIZE (gpr_mode);
6527 /* This loop must iterate over the same space as its companion in
6528 compute_frame_size. */
6529 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6530 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6531 for (regno = (FP_REG_LAST - FP_INC + 1);
6532 regno >= FP_REG_FIRST;
6534 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6536 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6537 offset -= GET_MODE_SIZE (fpr_mode);
6542 /* If we're generating n32 or n64 abicalls, and the current function
6543 does not use $28 as its global pointer, emit a cplocal directive.
6544 Use pic_offset_table_rtx as the argument to the directive. */
6547 mips_output_cplocal (void)
6549 if (!TARGET_EXPLICIT_RELOCS
6550 && cfun->machine->global_pointer > 0
6551 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6552 output_asm_insn (".cplocal %+", 0);
6555 /* If we're generating n32 or n64 abicalls, emit instructions
6556 to set up the global pointer. */
6559 mips_emit_loadgp (void)
6561 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6563 rtx addr, offset, incoming_address;
6565 addr = XEXP (DECL_RTL (current_function_decl), 0);
6566 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6567 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6568 emit_insn (gen_loadgp (offset, incoming_address));
6569 if (!TARGET_EXPLICIT_RELOCS)
6570 emit_insn (gen_loadgp_blockage ());
6574 /* Set up the stack and frame (if desired) for the function. */
6577 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6580 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6582 /* ??? When is this really needed? At least the GNU assembler does not
6583 need the source filename more than once in the file, beyond what is
6584 emitted by the debug information. */
6586 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6588 #ifdef SDB_DEBUGGING_INFO
6589 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6590 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl), 0);
6593 /* In mips16 mode, we may need to generate a 32 bit to handle
6594 floating point arguments. The linker will arrange for any 32 bit
6595 functions to call this stub, which will then jump to the 16 bit
6597 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6598 && current_function_args_info.fp_code != 0)
6599 build_mips16_function_stub (file);
6601 if (!FUNCTION_NAME_ALREADY_DECLARED)
6603 /* Get the function name the same way that toplev.c does before calling
6604 assemble_start_function. This is needed so that the name used here
6605 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6606 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6608 if (!flag_inhibit_size_directive)
6610 fputs ("\t.ent\t", file);
6611 assemble_name (file, fnname);
6615 assemble_name (file, fnname);
6616 fputs (":\n", file);
6619 if (!flag_inhibit_size_directive)
6621 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6623 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6624 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6625 ", args= " HOST_WIDE_INT_PRINT_DEC
6626 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6627 (reg_names[(frame_pointer_needed)
6628 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6629 ((frame_pointer_needed && TARGET_MIPS16)
6630 ? tsize - cfun->machine->frame.args_size
6632 reg_names[GP_REG_FIRST + 31],
6633 cfun->machine->frame.var_size,
6634 cfun->machine->frame.num_gp,
6635 cfun->machine->frame.num_fp,
6636 cfun->machine->frame.args_size,
6637 cfun->machine->frame.cprestore_size);
6639 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6640 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6641 cfun->machine->frame.mask,
6642 cfun->machine->frame.gp_save_offset);
6643 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6644 cfun->machine->frame.fmask,
6645 cfun->machine->frame.fp_save_offset);
6648 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6649 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6652 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6654 /* Handle the initialization of $gp for SVR4 PIC. */
6655 if (!cfun->machine->all_noreorder_p)
6656 output_asm_insn ("%(.cpload\t%^%)", 0);
6658 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6660 else if (cfun->machine->all_noreorder_p)
6661 output_asm_insn ("%(%<", 0);
6663 /* Tell the assembler which register we're using as the global
6664 pointer. This is needed for thunks, since they can use either
6665 explicit relocs or assembler macros. */
6666 mips_output_cplocal ();
6669 /* Make the last instruction frame related and note that it performs
6670 the operation described by FRAME_PATTERN. */
6673 mips_set_frame_expr (rtx frame_pattern)
6677 insn = get_last_insn ();
6678 RTX_FRAME_RELATED_P (insn) = 1;
6679 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6685 /* Return a frame-related rtx that stores REG at MEM.
6686 REG must be a single register. */
6689 mips_frame_set (rtx mem, rtx reg)
6691 rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6692 RTX_FRAME_RELATED_P (set) = 1;
6697 /* Save register REG to MEM. Make the instruction frame-related. */
6700 mips_save_reg (rtx reg, rtx mem)
6702 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6706 if (mips_split_64bit_move_p (mem, reg))
6707 mips_split_64bit_move (mem, reg);
6709 emit_move_insn (mem, reg);
6711 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6712 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6713 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6718 && REGNO (reg) != GP_REG_FIRST + 31
6719 && !M16_REG_P (REGNO (reg)))
6721 /* Save a non-mips16 register by moving it through a temporary.
6722 We don't need to do this for $31 since there's a special
6723 instruction for it. */
6724 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6725 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6728 emit_move_insn (mem, reg);
6730 mips_set_frame_expr (mips_frame_set (mem, reg));
6735 /* Expand the prologue into a bunch of separate insns. */
6738 mips_expand_prologue (void)
6742 if (cfun->machine->global_pointer > 0)
6743 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6745 size = compute_frame_size (get_frame_size ());
6747 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6748 bytes beforehand; this is enough to cover the register save area
6749 without going out of range. */
6750 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6752 HOST_WIDE_INT step1;
6754 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6755 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6757 GEN_INT (-step1)))) = 1;
6759 mips_for_each_saved_reg (size, mips_save_reg);
6762 /* Allocate the rest of the frame. */
6765 if (SMALL_OPERAND (-size))
6766 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6768 GEN_INT (-size)))) = 1;
6771 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6774 /* There are no instructions to add or subtract registers
6775 from the stack pointer, so use the frame pointer as a
6776 temporary. We should always be using a frame pointer
6777 in this case anyway. */
6778 if (!frame_pointer_needed)
6781 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6782 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6783 hard_frame_pointer_rtx,
6784 MIPS_PROLOGUE_TEMP (Pmode)));
6785 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6788 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6790 MIPS_PROLOGUE_TEMP (Pmode)));
6792 /* Describe the combined effect of the previous instructions. */
6794 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6795 plus_constant (stack_pointer_rtx, -size)));
6799 /* Set up the frame pointer, if we're using one. In mips16 code,
6800 we point the frame pointer ahead of the outgoing argument area.
6801 This should allow more variables & incoming arguments to be
6802 accessed with unextended instructions. */
6803 if (frame_pointer_needed)
6805 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6807 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6809 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6814 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6815 stack_pointer_rtx)) = 1;
6818 /* If generating o32/o64 abicalls, save $gp on the stack. */
6819 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6820 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6822 mips_emit_loadgp ();
6824 /* If we are profiling, make sure no instructions are scheduled before
6825 the call to mcount. */
6827 if (current_function_profile)
6828 emit_insn (gen_blockage ());
6831 /* Do any necessary cleanup after a function to restore stack, frame,
6834 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6837 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6838 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6840 /* Reinstate the normal $gp. */
6841 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6842 mips_output_cplocal ();
6844 if (cfun->machine->all_noreorder_p)
6846 /* Avoid using %>%) since it adds excess whitespace. */
6847 output_asm_insn (".set\tmacro", 0);
6848 output_asm_insn (".set\treorder", 0);
6849 set_noreorder = set_nomacro = 0;
6852 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6856 /* Get the function name the same way that toplev.c does before calling
6857 assemble_start_function. This is needed so that the name used here
6858 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6859 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6860 fputs ("\t.end\t", file);
6861 assemble_name (file, fnname);
6866 /* Emit instructions to restore register REG from slot MEM. */
6869 mips_restore_reg (rtx reg, rtx mem)
6871 /* There's no mips16 instruction to load $31 directly. Load into
6872 $7 instead and adjust the return insn appropriately. */
6873 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6874 reg = gen_rtx_REG (GET_MODE (reg), 7);
6876 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6878 /* Can't restore directly; move through a temporary. */
6879 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6880 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6883 emit_move_insn (reg, mem);
6887 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6888 if this epilogue precedes a sibling call, false if it is for a normal
6889 "epilogue" pattern. */
6892 mips_expand_epilogue (int sibcall_p)
6894 HOST_WIDE_INT step1, step2;
6897 if (!sibcall_p && mips_can_use_return_insn ())
6899 emit_jump_insn (gen_return ());
6903 /* Split the frame into two. STEP1 is the amount of stack we should
6904 deallocate before restoring the registers. STEP2 is the amount we
6905 should deallocate afterwards.
6907 Start off by assuming that no registers need to be restored. */
6908 step1 = cfun->machine->frame.total_size;
6911 /* Work out which register holds the frame address. Account for the
6912 frame pointer offset used by mips16 code. */
6913 if (!frame_pointer_needed)
6914 base = stack_pointer_rtx;
6917 base = hard_frame_pointer_rtx;
6919 step1 -= cfun->machine->frame.args_size;
6922 /* If we need to restore registers, deallocate as much stack as
6923 possible in the second step without going out of range. */
6924 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6926 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6930 /* Set TARGET to BASE + STEP1. */
6936 /* Get an rtx for STEP1 that we can add to BASE. */
6937 adjust = GEN_INT (step1);
6938 if (!SMALL_OPERAND (step1))
6940 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6941 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6944 /* Normal mode code can copy the result straight into $sp. */
6946 target = stack_pointer_rtx;
6948 emit_insn (gen_add3_insn (target, base, adjust));
6951 /* Copy TARGET into the stack pointer. */
6952 if (target != stack_pointer_rtx)
6953 emit_move_insn (stack_pointer_rtx, target);
6955 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6956 implicitly used by all SYMBOL_REFs. We must emit a blockage
6957 insn before restoring it. */
6958 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6959 emit_insn (gen_blockage ());
6961 /* Restore the registers. */
6962 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6965 /* Deallocate the final bit of the frame. */
6967 emit_insn (gen_add3_insn (stack_pointer_rtx,
6971 /* Add in the __builtin_eh_return stack adjustment. We need to
6972 use a temporary in mips16 code. */
6973 if (current_function_calls_eh_return)
6977 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6978 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6979 MIPS_EPILOGUE_TEMP (Pmode),
6980 EH_RETURN_STACKADJ_RTX));
6981 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6984 emit_insn (gen_add3_insn (stack_pointer_rtx,
6986 EH_RETURN_STACKADJ_RTX));
6991 /* The mips16 loads the return address into $7, not $31. */
6992 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6993 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6994 GP_REG_FIRST + 7)));
6996 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6997 GP_REG_FIRST + 31)));
7001 /* Return nonzero if this function is known to have a null epilogue.
7002 This allows the optimizer to omit jumps to jumps if no stack
7006 mips_can_use_return_insn (void)
7010 if (! reload_completed)
7013 if (regs_ever_live[31] || current_function_profile)
7016 return_type = DECL_RESULT (current_function_decl);
7018 /* In mips16 mode, a function which returns a floating point value
7019 needs to arrange to copy the return value into the floating point
7022 && mips16_hard_float
7023 && ! aggregate_value_p (return_type, current_function_decl)
7024 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7025 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7028 if (cfun->machine->frame.initialized)
7029 return cfun->machine->frame.total_size == 0;
7031 return compute_frame_size (get_frame_size ()) == 0;
7034 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7035 in order to avoid duplicating too much logic from elsewhere. */
7038 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7039 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7042 rtx this, temp1, temp2, insn, fnaddr;
7044 /* Pretend to be a post-reload pass while generating rtl. */
7046 reload_completed = 1;
7048 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7049 for TARGET_NEWABI since the latter is a call-saved register. */
7050 if (TARGET_ABICALLS)
7051 cfun->machine->global_pointer
7052 = REGNO (pic_offset_table_rtx)
7053 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7055 /* Set up the global pointer for n32 or n64 abicalls. */
7056 mips_emit_loadgp ();
7058 /* We need two temporary registers in some cases. */
7059 temp1 = gen_rtx_REG (Pmode, 2);
7060 temp2 = gen_rtx_REG (Pmode, 3);
7062 /* Find out which register contains the "this" pointer. */
7063 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7064 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7066 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7068 /* Add DELTA to THIS. */
7071 rtx offset = GEN_INT (delta);
7072 if (!SMALL_OPERAND (delta))
7074 emit_move_insn (temp1, offset);
7077 emit_insn (gen_add3_insn (this, this, offset));
7080 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7081 if (vcall_offset != 0)
7085 /* Set TEMP1 to *THIS. */
7086 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7088 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7089 if (SMALL_OPERAND (vcall_offset))
7090 addr = gen_rtx_PLUS (Pmode, temp1, GEN_INT (vcall_offset));
7091 else if (TARGET_MIPS16)
7093 /* Load the full offset into a register so that we can use
7094 an unextended instruction for the load itself. */
7095 emit_move_insn (temp2, GEN_INT (vcall_offset));
7096 emit_insn (gen_add3_insn (temp1, temp1, temp2));
7101 /* Load the high part of the offset into a register and
7102 leave the low part for the address. */
7103 emit_move_insn (temp2, GEN_INT (CONST_HIGH_PART (vcall_offset)));
7104 emit_insn (gen_add3_insn (temp1, temp1, temp2));
7105 addr = gen_rtx_PLUS (Pmode, temp1,
7106 GEN_INT (CONST_LOW_PART (vcall_offset)));
7109 /* Load the offset and add it to THIS. */
7110 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7111 emit_insn (gen_add3_insn (this, this, temp1));
7114 /* Jump to the target function. Use a sibcall if direct jumps are
7115 allowed, otherwise load the address into a register first. */
7116 fnaddr = XEXP (DECL_RTL (function), 0);
7117 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7119 /* This is messy. gas treats "la $25,foo" as part of a call
7120 sequence and may allow a global "foo" to be lazily bound.
7121 The general move patterns therefore reject this combination.
7123 In this context, lazy binding would actually be OK for o32 and o64,
7124 but it's still wrong for n32 and n64; see mips_load_call_address.
7125 We must therefore load the address via a temporary register if
7126 mips_dangerous_for_la25_p.
7128 If we jump to the temporary register rather than $25, the assembler
7129 can use the move insn to fill the jump's delay slot. */
7130 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7131 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7132 mips_load_call_address (temp1, fnaddr, true);
7134 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7135 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7136 emit_jump_insn (gen_indirect_jump (temp1));
7140 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7141 SIBLING_CALL_P (insn) = 1;
7144 /* Run just enough of rest_of_compilation. This sequence was
7145 "borrowed" from alpha.c. */
7146 insn = get_insns ();
7147 insn_locators_initialize ();
7148 split_all_insns_noflow ();
7150 mips16_lay_out_constants ();
7151 shorten_branches (insn);
7152 final_start_function (insn, file, 1);
7153 final (insn, file, 1, 0);
7154 final_end_function ();
7156 /* Clean up the vars set above. Note that final_end_function resets
7157 the global pointer for us. */
7158 reload_completed = 0;
7162 /* Returns nonzero if X contains a SYMBOL_REF. */
7165 symbolic_expression_p (rtx x)
7167 if (GET_CODE (x) == SYMBOL_REF)
7170 if (GET_CODE (x) == CONST)
7171 return symbolic_expression_p (XEXP (x, 0));
7174 return symbolic_expression_p (XEXP (x, 0));
7176 if (ARITHMETIC_P (x))
7177 return (symbolic_expression_p (XEXP (x, 0))
7178 || symbolic_expression_p (XEXP (x, 1)));
7183 /* Choose the section to use for the constant rtx expression X that has
7187 mips_select_rtx_section (enum machine_mode mode, rtx x,
7188 unsigned HOST_WIDE_INT align)
7192 /* In mips16 mode, the constant table always goes in the same section
7193 as the function, so that constants can be loaded using PC relative
7195 function_section (current_function_decl);
7197 else if (TARGET_EMBEDDED_DATA)
7199 /* For embedded applications, always put constants in read-only data,
7200 in order to reduce RAM usage. */
7201 mergeable_constant_section (mode, align, 0);
7205 /* For hosted applications, always put constants in small data if
7206 possible, as this gives the best performance. */
7207 /* ??? Consider using mergeable small data sections. */
7209 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7210 && mips_section_threshold > 0)
7211 named_section (0, ".sdata", 0);
7212 else if (flag_pic && symbolic_expression_p (x))
7214 if (targetm.have_named_sections)
7215 named_section (0, ".data.rel.ro", 3);
7220 mergeable_constant_section (mode, align, 0);
7224 /* Choose the section to use for DECL. RELOC is true if its value contains
7225 any relocatable expression. */
7228 mips_select_section (tree decl, int reloc,
7229 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
7231 if (TARGET_EMBEDDED_PIC && TREE_CODE (decl) == STRING_CST)
7232 /* For embedded position independent code, put constant strings in the
7233 text section, because the data section is limited to 64K in size. */
7235 else if (targetm.have_named_sections)
7236 default_elf_select_section (decl, reloc, align);
7238 /* The native irix o32 assembler doesn't support named sections. */
7239 default_select_section (decl, reloc, align);
7243 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7244 access DECL using %gp_rel(...)($gp). */
7247 mips_in_small_data_p (tree decl)
7251 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7254 /* We don't yet generate small-data references for -mabicalls. See related
7255 -G handling in override_options. */
7256 if (TARGET_ABICALLS)
7259 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7263 /* Reject anything that isn't in a known small-data section. */
7264 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7265 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7268 /* If a symbol is defined externally, the assembler will use the
7269 usual -G rules when deciding how to implement macros. */
7270 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7273 else if (TARGET_EMBEDDED_DATA)
7275 /* Don't put constants into the small data section: we want them
7276 to be in ROM rather than RAM. */
7277 if (TREE_CODE (decl) != VAR_DECL)
7280 if (TREE_READONLY (decl)
7281 && !TREE_SIDE_EFFECTS (decl)
7282 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7286 size = int_size_in_bytes (TREE_TYPE (decl));
7287 return (size > 0 && size <= mips_section_threshold);
7291 /* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
7292 symbols which are not in the .text section. */
7295 mips_encode_section_info (tree decl, rtx rtl, int first)
7299 if (GET_CODE (rtl) != MEM)
7302 symbol = XEXP (rtl, 0);
7304 if (GET_CODE (symbol) != SYMBOL_REF)
7307 if (TARGET_EMBEDDED_PIC)
7309 if (TREE_CODE (decl) == VAR_DECL)
7310 SYMBOL_REF_FLAG (symbol) = 1;
7311 else if (TREE_CODE (decl) == FUNCTION_DECL)
7312 SYMBOL_REF_FLAG (symbol) = 0;
7313 else if (TREE_CODE (decl) == STRING_CST)
7314 SYMBOL_REF_FLAG (symbol) = 0;
7316 SYMBOL_REF_FLAG (symbol) = 1;
7319 default_encode_section_info (decl, rtl, first);
7322 /* See whether VALTYPE is a record whose fields should be returned in
7323 floating-point registers. If so, return the number of fields and
7324 list them in FIELDS (which should have two elements). Return 0
7327 For n32 & n64, a structure with one or two fields is returned in
7328 floating-point registers as long as every field has a floating-point
7332 mips_fpr_return_fields (tree valtype, tree *fields)
7340 if (TREE_CODE (valtype) != RECORD_TYPE)
7344 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7346 if (TREE_CODE (field) != FIELD_DECL)
7349 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7355 fields[i++] = field;
7361 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7362 a value in the most significant part of $2/$3 if:
7364 - the target is big-endian;
7366 - the value has a structure or union type (we generalize this to
7367 cover aggregates from other languages too); and
7369 - the structure is not returned in floating-point registers. */
7372 mips_return_in_msb (tree valtype)
7376 return (TARGET_NEWABI
7377 && TARGET_BIG_ENDIAN
7378 && AGGREGATE_TYPE_P (valtype)
7379 && mips_fpr_return_fields (valtype, fields) == 0);
7383 /* Return a composite value in a pair of floating-point registers.
7384 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7385 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7388 For n32 & n64, $f0 always holds the first value and $f2 the second.
7389 Otherwise the values are packed together as closely as possible. */
7392 mips_return_fpr_pair (enum machine_mode mode,
7393 enum machine_mode mode1, HOST_WIDE_INT offset1,
7394 enum machine_mode mode2, HOST_WIDE_INT offset2)
7398 inc = (TARGET_NEWABI ? 2 : FP_INC);
7399 return gen_rtx_PARALLEL
7402 gen_rtx_EXPR_LIST (VOIDmode,
7403 gen_rtx_REG (mode1, FP_RETURN),
7405 gen_rtx_EXPR_LIST (VOIDmode,
7406 gen_rtx_REG (mode2, FP_RETURN + inc),
7407 GEN_INT (offset2))));
7412 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7413 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7414 VALTYPE is null and MODE is the mode of the return value. */
7417 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7418 enum machine_mode mode)
7425 mode = TYPE_MODE (valtype);
7426 unsignedp = TYPE_UNSIGNED (valtype);
7428 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7429 true, we must promote the mode just as PROMOTE_MODE does. */
7430 mode = promote_mode (valtype, mode, &unsignedp, 1);
7432 /* Handle structures whose fields are returned in $f0/$f2. */
7433 switch (mips_fpr_return_fields (valtype, fields))
7436 return gen_rtx_REG (mode, FP_RETURN);
7439 return mips_return_fpr_pair (mode,
7440 TYPE_MODE (TREE_TYPE (fields[0])),
7441 int_byte_position (fields[0]),
7442 TYPE_MODE (TREE_TYPE (fields[1])),
7443 int_byte_position (fields[1]));
7446 /* If a value is passed in the most significant part of a register, see
7447 whether we have to round the mode up to a whole number of words. */
7448 if (mips_return_in_msb (valtype))
7450 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7451 if (size % UNITS_PER_WORD != 0)
7453 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7454 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7459 if (GET_MODE_CLASS (mode) == MODE_FLOAT
7460 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7461 return gen_rtx_REG (mode, FP_RETURN);
7463 /* Handle long doubles for n32 & n64. */
7465 return mips_return_fpr_pair (mode,
7467 DImode, GET_MODE_SIZE (mode) / 2);
7469 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7470 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7471 return mips_return_fpr_pair (mode,
7472 GET_MODE_INNER (mode), 0,
7473 GET_MODE_INNER (mode),
7474 GET_MODE_SIZE (mode) / 2);
7476 return gen_rtx_REG (mode, GP_RETURN);
7479 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7480 nonzero when an argument must be passed by reference. */
7483 function_arg_pass_by_reference (const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7484 enum machine_mode mode, tree type,
7485 int named ATTRIBUTE_UNUSED)
7489 /* The EABI is the only one to pass args by reference. */
7490 if (mips_abi != ABI_EABI)
7493 /* ??? How should SCmode be handled? */
7494 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7497 size = int_size_in_bytes (type);
7498 return size == -1 || size > UNITS_PER_WORD;
7501 /* Return the class of registers for which a mode change from FROM to TO
7504 In little-endian mode, the hi-lo registers are numbered backwards,
7505 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
7508 Similarly, when using paired floating-point registers, the first
7509 register holds the low word, regardless of endianness. So in big
7510 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
7513 Also, loading a 32-bit value into a 64-bit floating-point register
7514 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7515 We can't allow 64-bit float registers to change from a 32-bit
7516 mode to a 64-bit mode. */
7519 mips_cannot_change_mode_class (enum machine_mode from,
7520 enum machine_mode to, enum reg_class class)
7522 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7524 if (TARGET_BIG_ENDIAN)
7525 return reg_classes_intersect_p (FP_REGS, class);
7527 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
7528 return reg_classes_intersect_p (HI_REG, class);
7533 /* Return true if X should not be moved directly into register $25.
7534 We need this because many versions of GAS will treat "la $25,foo" as
7535 part of a call sequence and so allow a global "foo" to be lazily bound. */
7538 mips_dangerous_for_la25_p (rtx x)
7540 HOST_WIDE_INT offset;
7542 if (TARGET_EXPLICIT_RELOCS)
7545 mips_split_const (x, &x, &offset);
7546 return global_got_operand (x, VOIDmode);
7549 /* Implement PREFERRED_RELOAD_CLASS. */
7552 mips_preferred_reload_class (rtx x, enum reg_class class)
7554 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7557 if (TARGET_HARD_FLOAT
7558 && FLOAT_MODE_P (GET_MODE (x))
7559 && reg_class_subset_p (FP_REGS, class))
7562 if (reg_class_subset_p (GR_REGS, class))
7565 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7571 /* This function returns the register class required for a secondary
7572 register when copying between one of the registers in CLASS, and X,
7573 using MODE. If IN_P is nonzero, the copy is going from X to the
7574 register, otherwise the register is the source. A return value of
7575 NO_REGS means that no secondary register is required. */
7578 mips_secondary_reload_class (enum reg_class class,
7579 enum machine_mode mode, rtx x, int in_p)
7581 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7585 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7586 regno = true_regnum (x);
7588 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7590 if (mips_dangerous_for_la25_p (x))
7593 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7597 /* Copying from HI or LO to anywhere other than a general register
7598 requires a general register. */
7599 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7601 if (TARGET_MIPS16 && in_p)
7603 /* We can't really copy to HI or LO at all in mips16 mode. */
7606 return gp_reg_p ? NO_REGS : gr_regs;
7608 if (MD_REG_P (regno))
7610 if (TARGET_MIPS16 && ! in_p)
7612 /* We can't really copy to HI or LO at all in mips16 mode. */
7615 return class == gr_regs ? NO_REGS : gr_regs;
7618 /* We can only copy a value to a condition code register from a
7619 floating point register, and even then we require a scratch
7620 floating point register. We can only copy a value out of a
7621 condition code register into a general register. */
7622 if (class == ST_REGS)
7626 return gp_reg_p ? NO_REGS : gr_regs;
7628 if (ST_REG_P (regno))
7632 return class == gr_regs ? NO_REGS : gr_regs;
7635 if (class == FP_REGS)
7637 if (GET_CODE (x) == MEM)
7639 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7642 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7644 /* We can use the l.s and l.d macros to load floating-point
7645 constants. ??? For l.s, we could probably get better
7646 code by returning GR_REGS here. */
7649 else if (gp_reg_p || x == CONST0_RTX (mode))
7651 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7654 else if (FP_REG_P (regno))
7656 /* In this case we can use mov.s or mov.d. */
7661 /* Otherwise, we need to reload through an integer register. */
7666 /* In mips16 mode, going between memory and anything but M16_REGS
7667 requires an M16_REG. */
7670 if (class != M16_REGS && class != M16_NA_REGS)
7678 if (class == M16_REGS || class == M16_NA_REGS)
7687 /* Implement CLASS_MAX_NREGS.
7689 Usually all registers are word-sized. The only supported exception
7690 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7691 registers. A word-based calculation is correct even in that case,
7692 since -msingle-float disallows multi-FPR values. */
7695 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7696 enum machine_mode mode)
7698 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7702 mips_valid_pointer_mode (enum machine_mode mode)
7704 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7708 /* If we can access small data directly (using gp-relative relocation
7709 operators) return the small data pointer, otherwise return null.
7711 For each mips16 function which refers to GP relative symbols, we
7712 use a pseudo register, initialized at the start of the function, to
7713 hold the $gp value. */
7716 mips16_gp_pseudo_reg (void)
7718 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7723 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7724 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
7726 /* We want to initialize this to a value which gcc will believe
7729 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7730 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7731 gen_rtx_CONST (Pmode, unspec));
7732 insn = get_insns ();
7735 push_topmost_sequence ();
7736 /* We need to emit the initialization after the FUNCTION_BEG
7737 note, so that it will be integrated. */
7738 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7739 if (GET_CODE (scan) == NOTE
7740 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7742 if (scan == NULL_RTX)
7743 scan = get_insns ();
7744 insn = emit_insn_after (insn, scan);
7745 pop_topmost_sequence ();
7748 return cfun->machine->mips16_gp_pseudo_rtx;
7751 /* Write out code to move floating point arguments in or out of
7752 general registers. Output the instructions to FILE. FP_CODE is
7753 the code describing which arguments are present (see the comment at
7754 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7755 we are copying from the floating point registers. */
7758 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7764 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7772 gparg = GP_ARG_FIRST;
7773 fparg = FP_ARG_FIRST;
7774 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7778 if ((fparg & 1) != 0)
7780 fprintf (file, "\t%s\t%s,%s\n", s,
7781 reg_names[gparg], reg_names[fparg]);
7783 else if ((f & 3) == 2)
7786 fprintf (file, "\td%s\t%s,%s\n", s,
7787 reg_names[gparg], reg_names[fparg]);
7790 if ((fparg & 1) != 0)
7792 if (TARGET_BIG_ENDIAN)
7793 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7794 reg_names[gparg], reg_names[fparg + 1], s,
7795 reg_names[gparg + 1], reg_names[fparg]);
7797 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7798 reg_names[gparg], reg_names[fparg], s,
7799 reg_names[gparg + 1], reg_names[fparg + 1]);
7812 /* Build a mips16 function stub. This is used for functions which
7813 take arguments in the floating point registers. It is 32 bit code
7814 that moves the floating point args into the general registers, and
7815 then jumps to the 16 bit code. */
7818 build_mips16_function_stub (FILE *file)
7821 char *secname, *stubname;
7822 tree stubid, stubdecl;
7826 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7827 secname = (char *) alloca (strlen (fnname) + 20);
7828 sprintf (secname, ".mips16.fn.%s", fnname);
7829 stubname = (char *) alloca (strlen (fnname) + 20);
7830 sprintf (stubname, "__fn_stub_%s", fnname);
7831 stubid = get_identifier (stubname);
7832 stubdecl = build_decl (FUNCTION_DECL, stubid,
7833 build_function_type (void_type_node, NULL_TREE));
7834 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7836 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7838 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7840 fprintf (file, "%s%s",
7841 need_comma ? ", " : "",
7842 (f & 3) == 1 ? "float" : "double");
7845 fprintf (file, ")\n");
7847 fprintf (file, "\t.set\tnomips16\n");
7848 function_section (stubdecl);
7849 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7851 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7852 within a .ent, and we can not emit another .ent. */
7853 if (!FUNCTION_NAME_ALREADY_DECLARED)
7855 fputs ("\t.ent\t", file);
7856 assemble_name (file, stubname);
7860 assemble_name (file, stubname);
7861 fputs (":\n", file);
7863 /* We don't want the assembler to insert any nops here. */
7864 fprintf (file, "\t.set\tnoreorder\n");
7866 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7868 fprintf (asm_out_file, "\t.set\tnoat\n");
7869 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7870 assemble_name (file, fnname);
7871 fprintf (file, "\n");
7872 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7873 fprintf (asm_out_file, "\t.set\tat\n");
7875 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7876 with one of the mfc1 instructions, because the result is not
7877 available for one instruction, so if the very first instruction
7878 in the function refers to the register, it will see the wrong
7880 fprintf (file, "\tnop\n");
7882 fprintf (file, "\t.set\treorder\n");
7884 if (!FUNCTION_NAME_ALREADY_DECLARED)
7886 fputs ("\t.end\t", file);
7887 assemble_name (file, stubname);
7891 fprintf (file, "\t.set\tmips16\n");
7893 function_section (current_function_decl);
7896 /* We keep a list of functions for which we have already built stubs
7897 in build_mips16_call_stub. */
7901 struct mips16_stub *next;
7906 static struct mips16_stub *mips16_stubs;
7908 /* Build a call stub for a mips16 call. A stub is needed if we are
7909 passing any floating point values which should go into the floating
7910 point registers. If we are, and the call turns out to be to a 32
7911 bit function, the stub will be used to move the values into the
7912 floating point registers before calling the 32 bit function. The
7913 linker will magically adjust the function call to either the 16 bit
7914 function or the 32 bit stub, depending upon where the function call
7915 is actually defined.
7917 Similarly, we need a stub if the return value might come back in a
7918 floating point register.
7920 RETVAL is the location of the return value, or null if this is
7921 a call rather than a call_value. FN is the address of the
7922 function and ARG_SIZE is the size of the arguments. FP_CODE
7923 is the code built by function_arg. This function returns a nonzero
7924 value if it builds the call instruction itself. */
7927 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7931 char *secname, *stubname;
7932 struct mips16_stub *l;
7933 tree stubid, stubdecl;
7937 /* We don't need to do anything if we aren't in mips16 mode, or if
7938 we were invoked with the -msoft-float option. */
7939 if (! TARGET_MIPS16 || ! mips16_hard_float)
7942 /* Figure out whether the value might come back in a floating point
7944 fpret = (retval != 0
7945 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7946 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7948 /* We don't need to do anything if there were no floating point
7949 arguments and the value will not be returned in a floating point
7951 if (fp_code == 0 && ! fpret)
7954 /* We don't need to do anything if this is a call to a special
7955 mips16 support function. */
7956 if (GET_CODE (fn) == SYMBOL_REF
7957 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7960 /* This code will only work for o32 and o64 abis. The other ABI's
7961 require more sophisticated support. */
7965 /* We can only handle SFmode and DFmode floating point return
7967 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
7970 /* If we're calling via a function pointer, then we must always call
7971 via a stub. There are magic stubs provided in libgcc.a for each
7972 of the required cases. Each of them expects the function address
7973 to arrive in register $2. */
7975 if (GET_CODE (fn) != SYMBOL_REF)
7981 /* ??? If this code is modified to support other ABI's, we need
7982 to handle PARALLEL return values here. */
7984 sprintf (buf, "__mips16_call_stub_%s%d",
7986 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7989 id = get_identifier (buf);
7990 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7992 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7994 if (retval == NULL_RTX)
7995 insn = gen_call_internal (stub_fn, arg_size);
7997 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7998 insn = emit_call_insn (insn);
8000 /* Put the register usage information on the CALL. */
8001 if (GET_CODE (insn) != CALL_INSN)
8003 CALL_INSN_FUNCTION_USAGE (insn) =
8004 gen_rtx_EXPR_LIST (VOIDmode,
8005 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8006 CALL_INSN_FUNCTION_USAGE (insn));
8008 /* If we are handling a floating point return value, we need to
8009 save $18 in the function prologue. Putting a note on the
8010 call will mean that regs_ever_live[$18] will be true if the
8011 call is not eliminated, and we can check that in the prologue
8014 CALL_INSN_FUNCTION_USAGE (insn) =
8015 gen_rtx_EXPR_LIST (VOIDmode,
8016 gen_rtx_USE (VOIDmode,
8017 gen_rtx_REG (word_mode, 18)),
8018 CALL_INSN_FUNCTION_USAGE (insn));
8020 /* Return 1 to tell the caller that we've generated the call
8025 /* We know the function we are going to call. If we have already
8026 built a stub, we don't need to do anything further. */
8028 fnname = XSTR (fn, 0);
8029 for (l = mips16_stubs; l != NULL; l = l->next)
8030 if (strcmp (l->name, fnname) == 0)
8035 /* Build a special purpose stub. When the linker sees a
8036 function call in mips16 code, it will check where the target
8037 is defined. If the target is a 32 bit call, the linker will
8038 search for the section defined here. It can tell which
8039 symbol this section is associated with by looking at the
8040 relocation information (the name is unreliable, since this
8041 might be a static function). If such a section is found, the
8042 linker will redirect the call to the start of the magic
8045 If the function does not return a floating point value, the
8046 special stub section is named
8049 If the function does return a floating point value, the stub
8051 .mips16.call.fp.FNNAME
8054 secname = (char *) alloca (strlen (fnname) + 40);
8055 sprintf (secname, ".mips16.call.%s%s",
8058 stubname = (char *) alloca (strlen (fnname) + 20);
8059 sprintf (stubname, "__call_stub_%s%s",
8062 stubid = get_identifier (stubname);
8063 stubdecl = build_decl (FUNCTION_DECL, stubid,
8064 build_function_type (void_type_node, NULL_TREE));
8065 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8067 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8069 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8073 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8075 fprintf (asm_out_file, "%s%s",
8076 need_comma ? ", " : "",
8077 (f & 3) == 1 ? "float" : "double");
8080 fprintf (asm_out_file, ")\n");
8082 fprintf (asm_out_file, "\t.set\tnomips16\n");
8083 assemble_start_function (stubdecl, stubname);
8085 if (!FUNCTION_NAME_ALREADY_DECLARED)
8087 fputs ("\t.ent\t", asm_out_file);
8088 assemble_name (asm_out_file, stubname);
8089 fputs ("\n", asm_out_file);
8091 assemble_name (asm_out_file, stubname);
8092 fputs (":\n", asm_out_file);
8095 /* We build the stub code by hand. That's the only way we can
8096 do it, since we can't generate 32 bit code during a 16 bit
8099 /* We don't want the assembler to insert any nops here. */
8100 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8102 mips16_fp_args (asm_out_file, fp_code, 0);
8106 fprintf (asm_out_file, "\t.set\tnoat\n");
8107 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8109 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8110 fprintf (asm_out_file, "\t.set\tat\n");
8111 /* Unfortunately, we can't fill the jump delay slot. We
8112 can't fill with one of the mtc1 instructions, because the
8113 result is not available for one instruction, so if the
8114 very first instruction in the function refers to the
8115 register, it will see the wrong value. */
8116 fprintf (asm_out_file, "\tnop\n");
8120 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8121 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8122 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8123 /* As above, we can't fill the delay slot. */
8124 fprintf (asm_out_file, "\tnop\n");
8125 if (GET_MODE (retval) == SFmode)
8126 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8127 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8130 if (TARGET_BIG_ENDIAN)
8132 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8133 reg_names[GP_REG_FIRST + 2],
8134 reg_names[FP_REG_FIRST + 1]);
8135 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8136 reg_names[GP_REG_FIRST + 3],
8137 reg_names[FP_REG_FIRST + 0]);
8141 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8142 reg_names[GP_REG_FIRST + 2],
8143 reg_names[FP_REG_FIRST + 0]);
8144 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8145 reg_names[GP_REG_FIRST + 3],
8146 reg_names[FP_REG_FIRST + 1]);
8149 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8150 /* As above, we can't fill the delay slot. */
8151 fprintf (asm_out_file, "\tnop\n");
8154 fprintf (asm_out_file, "\t.set\treorder\n");
8156 #ifdef ASM_DECLARE_FUNCTION_SIZE
8157 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8160 if (!FUNCTION_NAME_ALREADY_DECLARED)
8162 fputs ("\t.end\t", asm_out_file);
8163 assemble_name (asm_out_file, stubname);
8164 fputs ("\n", asm_out_file);
8167 fprintf (asm_out_file, "\t.set\tmips16\n");
8169 /* Record this stub. */
8170 l = (struct mips16_stub *) xmalloc (sizeof *l);
8171 l->name = xstrdup (fnname);
8173 l->next = mips16_stubs;
8177 /* If we expect a floating point return value, but we've built a
8178 stub which does not expect one, then we're in trouble. We can't
8179 use the existing stub, because it won't handle the floating point
8180 value. We can't build a new stub, because the linker won't know
8181 which stub to use for the various calls in this object file.
8182 Fortunately, this case is illegal, since it means that a function
8183 was declared in two different ways in a single compilation. */
8184 if (fpret && ! l->fpret)
8185 error ("can not handle inconsistent calls to `%s'", fnname);
8187 /* If we are calling a stub which handles a floating point return
8188 value, we need to arrange to save $18 in the prologue. We do
8189 this by marking the function call as using the register. The
8190 prologue will later see that it is used, and emit code to save
8197 if (retval == NULL_RTX)
8198 insn = gen_call_internal (fn, arg_size);
8200 insn = gen_call_value_internal (retval, fn, arg_size);
8201 insn = emit_call_insn (insn);
8203 if (GET_CODE (insn) != CALL_INSN)
8206 CALL_INSN_FUNCTION_USAGE (insn) =
8207 gen_rtx_EXPR_LIST (VOIDmode,
8208 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8209 CALL_INSN_FUNCTION_USAGE (insn));
8211 /* Return 1 to tell the caller that we've generated the call
8216 /* Return 0 to let the caller generate the call insn. */
8220 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8221 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8223 struct mips16_constant {
8224 struct mips16_constant *next;
8227 enum machine_mode mode;
8230 /* Information about an incomplete mips16 constant pool. FIRST is the
8231 first constant, HIGHEST_ADDRESS is the highest address that the first
8232 byte of the pool can have, and INSN_ADDRESS is the current instruction
8235 struct mips16_constant_pool {
8236 struct mips16_constant *first;
8237 int highest_address;
8241 /* Add constant VALUE to POOL and return its label. MODE is the
8242 value's mode (used for CONST_INTs, etc.). */
8245 add_constant (struct mips16_constant_pool *pool,
8246 rtx value, enum machine_mode mode)
8248 struct mips16_constant **p, *c;
8249 bool first_of_size_p;
8251 /* See whether the constant is already in the pool. If so, return the
8252 existing label, otherwise leave P pointing to the place where the
8253 constant should be added.
8255 Keep the pool sorted in increasing order of mode size so that we can
8256 reduce the number of alignments needed. */
8257 first_of_size_p = true;
8258 for (p = &pool->first; *p != 0; p = &(*p)->next)
8260 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8262 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8264 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8265 first_of_size_p = false;
8268 /* In the worst case, the constant needed by the earliest instruction
8269 will end up at the end of the pool. The entire pool must then be
8270 accessible from that instruction.
8272 When adding the first constant, set the pool's highest address to
8273 the address of the first out-of-range byte. Adjust this address
8274 downwards each time a new constant is added. */
8275 if (pool->first == 0)
8276 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8277 is the address of the instruction with the lowest two bits clear.
8278 The base PC value for ld has the lowest three bits clear. Assume
8279 the worst case here. */
8280 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8281 pool->highest_address -= GET_MODE_SIZE (mode);
8282 if (first_of_size_p)
8283 /* Take into account the worst possible padding due to alignment. */
8284 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8286 /* Create a new entry. */
8287 c = (struct mips16_constant *) xmalloc (sizeof *c);
8290 c->label = gen_label_rtx ();
8297 /* Output constant VALUE after instruction INSN and return the last
8298 instruction emitted. MODE is the mode of the constant. */
8301 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8303 switch (GET_MODE_CLASS (mode))
8307 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8308 return emit_insn_after (gen_consttable_int (value, size), insn);
8312 return emit_insn_after (gen_consttable_float (value), insn);
8314 case MODE_VECTOR_FLOAT:
8315 case MODE_VECTOR_INT:
8318 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8319 insn = dump_constants_1 (GET_MODE_INNER (mode),
8320 CONST_VECTOR_ELT (value, i), insn);
8330 /* Dump out the constants in CONSTANTS after INSN. */
8333 dump_constants (struct mips16_constant *constants, rtx insn)
8335 struct mips16_constant *c, *next;
8339 for (c = constants; c != NULL; c = next)
8341 /* If necessary, increase the alignment of PC. */
8342 if (align < GET_MODE_SIZE (c->mode))
8344 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8345 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8347 align = GET_MODE_SIZE (c->mode);
8349 insn = emit_label_after (c->label, insn);
8350 insn = dump_constants_1 (c->mode, c->value, insn);
8356 emit_barrier_after (insn);
8359 /* Return the length of instruction INSN.
8361 ??? MIPS16 switch tables go in .text, but we don't define
8362 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8363 compute their lengths correctly. */
8366 mips16_insn_length (rtx insn)
8368 if (GET_CODE (insn) == JUMP_INSN)
8370 rtx body = PATTERN (insn);
8371 if (GET_CODE (body) == ADDR_VEC)
8372 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8373 if (GET_CODE (body) == ADDR_DIFF_VEC)
8374 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8376 return get_attr_length (insn);
8379 /* Rewrite *X so that constant pool references refer to the constant's
8380 label instead. DATA points to the constant pool structure. */
8383 mips16_rewrite_pool_refs (rtx *x, void *data)
8385 struct mips16_constant_pool *pool = data;
8386 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8387 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8388 get_pool_constant (*x),
8389 get_pool_mode (*x)));
8393 /* Build MIPS16 constant pools. */
8396 mips16_lay_out_constants (void)
8398 struct mips16_constant_pool pool;
8402 memset (&pool, 0, sizeof (pool));
8403 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8405 /* Rewrite constant pool references in INSN. */
8407 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8409 pool.insn_address += mips16_insn_length (insn);
8411 if (pool.first != NULL)
8413 /* If there are no natural barriers between the first user of
8414 the pool and the highest acceptable address, we'll need to
8415 create a new instruction to jump around the constant pool.
8416 In the worst case, this instruction will be 4 bytes long.
8418 If it's too late to do this transformation after INSN,
8419 do it immediately before INSN. */
8420 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8424 label = gen_label_rtx ();
8426 jump = emit_jump_insn_before (gen_jump (label), insn);
8427 JUMP_LABEL (jump) = label;
8428 LABEL_NUSES (label) = 1;
8429 barrier = emit_barrier_after (jump);
8431 emit_label_after (label, barrier);
8432 pool.insn_address += 4;
8435 /* See whether the constant pool is now out of range of the first
8436 user. If so, output the constants after the previous barrier.
8437 Note that any instructions between BARRIER and INSN (inclusive)
8438 will use negative offsets to refer to the pool. */
8439 if (pool.insn_address > pool.highest_address)
8441 dump_constants (pool.first, barrier);
8445 else if (BARRIER_P (insn))
8449 dump_constants (pool.first, get_last_insn ());
8453 /* Subroutine of mips_reorg. If there is a hazard between INSN
8454 and a previous instruction, avoid it by inserting nops after
8457 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8458 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8459 before using the value of that register. *HILO_DELAY counts the
8460 number of instructions since the last hilo hazard (that is,
8461 the number of instructions since the last mflo or mfhi).
8463 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8464 for the next instruction.
8466 LO_REG is an rtx for the LO register, used in dependence checking. */
8469 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8470 rtx *delayed_reg, rtx lo_reg)
8478 pattern = PATTERN (insn);
8480 /* Do not put the whole function in .set noreorder if it contains
8481 an asm statement. We don't know whether there will be hazards
8482 between the asm statement and the gcc-generated code. */
8483 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8484 cfun->machine->all_noreorder_p = false;
8486 /* Ignore zero-length instructions (barriers and the like). */
8487 ninsns = get_attr_length (insn) / 4;
8491 /* Work out how many nops are needed. Note that we only care about
8492 registers that are explicitly mentioned in the instruction's pattern.
8493 It doesn't matter that calls use the argument registers or that they
8494 clobber hi and lo. */
8495 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8496 nops = 2 - *hilo_delay;
8497 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8502 /* Insert the nops between this instruction and the previous one.
8503 Each new nop takes us further from the last hilo hazard. */
8504 *hilo_delay += nops;
8506 emit_insn_after (gen_hazard_nop (), after);
8508 /* Set up the state for the next instruction. */
8509 *hilo_delay += ninsns;
8511 if (INSN_CODE (insn) >= 0)
8512 switch (get_attr_hazard (insn))
8522 set = single_set (insn);
8525 *delayed_reg = SET_DEST (set);
8531 /* Go through the instruction stream and insert nops where necessary.
8532 See if the whole function can then be put into .set noreorder &
8536 mips_avoid_hazards (void)
8538 rtx insn, last_insn, lo_reg, delayed_reg;
8541 /* Recalculate instruction lengths without taking nops into account. */
8542 cfun->machine->ignore_hazard_length_p = true;
8543 shorten_branches (get_insns ());
8545 /* The profiler code uses assembler macros. -mfix-vr4120 relies on
8546 assembler nop insertion. */
8547 cfun->machine->all_noreorder_p = (!current_function_profile
8548 && !TARGET_FIX_VR4120);
8553 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8555 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8558 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8559 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8560 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8561 &hilo_delay, &delayed_reg, lo_reg);
8563 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8564 &delayed_reg, lo_reg);
8571 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8577 mips16_lay_out_constants ();
8578 else if (TARGET_EXPLICIT_RELOCS)
8580 if (mips_flag_delayed_branch)
8581 dbr_schedule (get_insns (), dump_file);
8582 mips_avoid_hazards ();
8586 /* This function does three things:
8588 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8589 - Register the mips16 hardware floating point stubs.
8590 - Register the gofast functions if selected using --enable-gofast. */
8592 #include "config/gofast.h"
8595 mips_init_libfuncs (void)
8597 if (TARGET_FIX_VR4120)
8599 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8600 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8603 if (TARGET_MIPS16 && mips16_hard_float)
8605 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8606 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8607 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8608 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8610 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8611 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8612 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8613 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8614 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8615 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8617 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8618 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8620 if (TARGET_DOUBLE_FLOAT)
8622 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8623 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8624 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8625 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8627 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8628 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8629 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8630 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8631 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8632 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8634 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8635 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8637 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8638 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8642 gofast_maybe_init_libfuncs ();
8645 /* Return a number assessing the cost of moving a register in class
8646 FROM to class TO. The classes are expressed using the enumeration
8647 values such as `GENERAL_REGS'. A value of 2 is the default; other
8648 values are interpreted relative to that.
8650 It is not required that the cost always equal 2 when FROM is the
8651 same as TO; on some machines it is expensive to move between
8652 registers if they are not general registers.
8654 If reload sees an insn consisting of a single `set' between two
8655 hard registers, and if `REGISTER_MOVE_COST' applied to their
8656 classes returns a value of 2, reload does not check to ensure that
8657 the constraints of the insn are met. Setting a cost of other than
8658 2 will allow reload to verify that the constraints are met. You
8659 should do this if the `movM' pattern's constraints do not allow
8662 ??? We make the cost of moving from HI/LO into general
8663 registers the same as for one of moving general registers to
8664 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8665 pseudo to HI/LO. This might hurt optimizations though, it
8666 isn't clear if it is wise. And it might not work in all cases. We
8667 could solve the DImode LO reg problem by using a multiply, just
8668 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8669 problem by using divide instructions. divu puts the remainder in
8670 the HI reg, so doing a divide by -1 will move the value in the HI
8671 reg for all values except -1. We could handle that case by using a
8672 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8673 a compare/branch to test the input value to see which instruction
8674 we need to use. This gets pretty messy, but it is feasible. */
8677 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8678 enum reg_class to, enum reg_class from)
8680 if (from == M16_REGS && GR_REG_CLASS_P (to))
8682 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8684 else if (GR_REG_CLASS_P (from))
8688 else if (to == M16_NA_REGS)
8690 else if (GR_REG_CLASS_P (to))
8697 else if (to == FP_REGS)
8699 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8706 else if (COP_REG_CLASS_P (to))
8710 } /* GR_REG_CLASS_P (from) */
8711 else if (from == FP_REGS)
8713 if (GR_REG_CLASS_P (to))
8715 else if (to == FP_REGS)
8717 else if (to == ST_REGS)
8719 } /* from == FP_REGS */
8720 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8722 if (GR_REG_CLASS_P (to))
8729 } /* from == HI_REG, etc. */
8730 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8732 else if (COP_REG_CLASS_P (from))
8735 } /* COP_REG_CLASS_P (from) */
8742 /* Return the length of INSN. LENGTH is the initial length computed by
8743 attributes in the machine-description file. */
8746 mips_adjust_insn_length (rtx insn, int length)
8748 /* A unconditional jump has an unfilled delay slot if it is not part
8749 of a sequence. A conditional jump normally has a delay slot, but
8750 does not on MIPS16. */
8751 if (simplejump_p (insn)
8752 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8753 || GET_CODE (insn) == CALL_INSN)))
8756 /* See how many nops might be needed to avoid hardware hazards. */
8757 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8758 switch (get_attr_hazard (insn))
8772 /* All MIPS16 instructions are a measly two bytes. */
8780 /* Return an asm sequence to start a noat block and load the address
8781 of a label into $1. */
8784 mips_output_load_label (void)
8786 if (TARGET_EXPLICIT_RELOCS)
8790 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8793 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8796 if (ISA_HAS_LOAD_DELAY)
8797 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8798 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8802 if (Pmode == DImode)
8803 return "%[dla\t%@,%0";
8805 return "%[la\t%@,%0";
8810 /* Output assembly instructions to peform a conditional branch.
8812 INSN is the branch instruction. OPERANDS[0] is the condition.
8813 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8814 of the first operand to the condition. If TWO_OPERANDS_P is
8815 nonzero the comparison takes two operands; OPERANDS[3] will be the
8818 If INVERTED_P is nonzero we are to branch if the condition does
8819 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
8821 LENGTH is the length (in bytes) of the sequence we are to generate.
8822 That tells us whether to generate a simple conditional branch, or a
8823 reversed conditional branch around a `jr' instruction. */
8825 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
8826 int float_p, int inverted_p, int length)
8828 static char buffer[200];
8829 /* The kind of comparison we are doing. */
8830 enum rtx_code code = GET_CODE (operands[0]);
8831 /* Nonzero if the opcode for the comparison needs a `z' indicating
8832 that it is a comparison against zero. */
8834 /* A string to use in the assembly output to represent the first
8836 const char *op1 = "%z2";
8837 /* A string to use in the assembly output to represent the second
8838 operand. Use the hard-wired zero register if there's no second
8840 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
8841 /* The operand-printing string for the comparison. */
8842 const char *const comp = (float_p ? "%F0" : "%C0");
8843 /* The operand-printing string for the inverted comparison. */
8844 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
8846 /* The MIPS processors (for levels of the ISA at least two), have
8847 "likely" variants of each branch instruction. These instructions
8848 annul the instruction in the delay slot if the branch is not
8850 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8852 if (!two_operands_p)
8854 /* To compute whether than A > B, for example, we normally
8855 subtract B from A and then look at the sign bit. But, if we
8856 are doing an unsigned comparison, and B is zero, we don't
8857 have to do the subtraction. Instead, we can just check to
8858 see if A is nonzero. Thus, we change the CODE here to
8859 reflect the simpler comparison operation. */
8871 /* A condition which will always be true. */
8877 /* A condition which will always be false. */
8883 /* Not a special case. */
8888 /* Relative comparisons are always done against zero. But
8889 equality comparisons are done between two operands, and therefore
8890 do not require a `z' in the assembly language output. */
8891 need_z_p = (!float_p && code != EQ && code != NE);
8892 /* For comparisons against zero, the zero is not provided
8897 /* Begin by terminating the buffer. That way we can always use
8898 strcat to add to it. */
8905 /* Just a simple conditional branch. */
8907 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
8908 inverted_p ? inverted_comp : comp);
8910 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
8911 inverted_p ? inverted_comp : comp,
8912 need_z_p ? "z" : "",
8922 /* Generate a reversed conditional branch around ` j'
8935 If the original branch was a likely branch, the delay slot
8936 must be executed only if the branch is taken, so generate:
8948 When generating non-embedded PIC, instead of:
8961 rtx target = gen_label_rtx ();
8963 orig_target = operands[1];
8964 operands[1] = target;
8965 /* Generate the reversed comparison. This takes four
8968 sprintf (buffer, "%%*b%s\t%%Z2%%1",
8969 inverted_p ? comp : inverted_comp);
8971 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
8972 inverted_p ? comp : inverted_comp,
8973 need_z_p ? "z" : "",
8976 output_asm_insn (buffer, operands);
8978 if (length != 16 && length != 28 && ! mips_branch_likely)
8980 /* Output delay slot instruction. */
8981 rtx insn = final_sequence;
8982 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
8983 optimize, 0, 1, NULL);
8984 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
8987 output_asm_insn ("%#", 0);
8990 output_asm_insn ("j\t%0", &orig_target);
8993 output_asm_insn (mips_output_load_label (), &orig_target);
8994 output_asm_insn ("jr\t%@%]", 0);
8997 if (length != 16 && length != 28 && mips_branch_likely)
8999 /* Output delay slot instruction. */
9000 rtx insn = final_sequence;
9001 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9002 optimize, 0, 1, NULL);
9003 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9006 output_asm_insn ("%#", 0);
9008 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9009 CODE_LABEL_NUMBER (target));
9022 /* Used to output div or ddiv instruction DIVISION, which has the operands
9023 given by OPERANDS. Add in a divide-by-zero check if needed.
9025 When working around R4000 and R4400 errata, we need to make sure that
9026 the division is not immediately followed by a shift[1][2]. We also
9027 need to stop the division from being put into a branch delay slot[3].
9028 The easiest way to avoid both problems is to add a nop after the
9029 division. When a divide-by-zero check is needed, this nop can be
9030 used to fill the branch delay slot.
9032 [1] If a double-word or a variable shift executes immediately
9033 after starting an integer division, the shift may give an
9034 incorrect result. See quotations of errata #16 and #28 from
9035 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9036 in mips.md for details.
9038 [2] A similar bug to [1] exists for all revisions of the
9039 R4000 and the R4400 when run in an MC configuration.
9040 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9042 "19. In this following sequence:
9044 ddiv (or ddivu or div or divu)
9045 dsll32 (or dsrl32, dsra32)
9047 if an MPT stall occurs, while the divide is slipping the cpu
9048 pipeline, then the following double shift would end up with an
9051 Workaround: The compiler needs to avoid generating any
9052 sequence with divide followed by extended double shift."
9054 This erratum is also present in "MIPS R4400MC Errata, Processor
9055 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9056 & 3.0" as errata #10 and #4, respectively.
9058 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9059 (also valid for MIPS R4000MC processors):
9061 "52. R4000SC: This bug does not apply for the R4000PC.
9063 There are two flavors of this bug:
9065 1) If the instruction just after divide takes an RF exception
9066 (tlb-refill, tlb-invalid) and gets an instruction cache
9067 miss (both primary and secondary) and the line which is
9068 currently in secondary cache at this index had the first
9069 data word, where the bits 5..2 are set, then R4000 would
9070 get a wrong result for the div.
9075 ------------------- # end-of page. -tlb-refill
9080 ------------------- # end-of page. -tlb-invalid
9083 2) If the divide is in the taken branch delay slot, where the
9084 target takes RF exception and gets an I-cache miss for the
9085 exception vector or where I-cache miss occurs for the
9086 target address, under the above mentioned scenarios, the
9087 div would get wrong results.
9090 j r2 # to next page mapped or unmapped
9091 div r8,r9 # this bug would be there as long
9092 # as there is an ICache miss and
9093 nop # the "data pattern" is present
9096 beq r0, r0, NextPage # to Next page
9100 This bug is present for div, divu, ddiv, and ddivu
9103 Workaround: For item 1), OS could make sure that the next page
9104 after the divide instruction is also mapped. For item 2), the
9105 compiler could make sure that the divide instruction is not in
9106 the branch delay slot."
9108 These processors have PRId values of 0x00004220 and 0x00004300 for
9109 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9112 mips_output_division (const char *division, rtx *operands)
9117 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9119 output_asm_insn (s, operands);
9122 if (TARGET_CHECK_ZERO_DIV)
9126 output_asm_insn (s, operands);
9127 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9131 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9132 output_asm_insn (s, operands);
9133 s = "break\t7%)\n1:";
9139 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9140 with a final "000" replaced by "k". Ignore case.
9142 Note: this function is shared between GCC and GAS. */
9145 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9147 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9148 given++, canonical++;
9150 return ((*given == 0 && *canonical == 0)
9151 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9155 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9156 CPU name. We've traditionally allowed a lot of variation here.
9158 Note: this function is shared between GCC and GAS. */
9161 mips_matching_cpu_name_p (const char *canonical, const char *given)
9163 /* First see if the name matches exactly, or with a final "000"
9165 if (mips_strict_matching_cpu_name_p (canonical, given))
9168 /* If not, try comparing based on numerical designation alone.
9169 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9170 if (TOLOWER (*given) == 'r')
9172 if (!ISDIGIT (*given))
9175 /* Skip over some well-known prefixes in the canonical name,
9176 hoping to find a number there too. */
9177 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9179 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9181 else if (TOLOWER (canonical[0]) == 'r')
9184 return mips_strict_matching_cpu_name_p (canonical, given);
9188 /* Parse an option that takes the name of a processor as its argument.
9189 OPTION is the name of the option and CPU_STRING is the argument.
9190 Return the corresponding processor enumeration if the CPU_STRING is
9191 recognized, otherwise report an error and return null.
9193 A similar function exists in GAS. */
9195 static const struct mips_cpu_info *
9196 mips_parse_cpu (const char *option, const char *cpu_string)
9198 const struct mips_cpu_info *p;
9201 /* In the past, we allowed upper-case CPU names, but it doesn't
9202 work well with the multilib machinery. */
9203 for (s = cpu_string; *s != 0; s++)
9206 warning ("the cpu name must be lower case");
9210 /* 'from-abi' selects the most compatible architecture for the given
9211 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9212 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9213 version. Look first at the -mgp options, if given, otherwise base
9214 the choice on MASK_64BIT in TARGET_DEFAULT. */
9215 if (strcasecmp (cpu_string, "from-abi") == 0)
9216 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9217 : ABI_NEEDS_64BIT_REGS ? 3
9218 : (TARGET_64BIT ? 3 : 1));
9220 /* 'default' has traditionally been a no-op. Probably not very useful. */
9221 if (strcasecmp (cpu_string, "default") == 0)
9224 for (p = mips_cpu_info_table; p->name != 0; p++)
9225 if (mips_matching_cpu_name_p (p->name, cpu_string))
9228 error ("bad value (%s) for %s", cpu_string, option);
9233 /* Return the processor associated with the given ISA level, or null
9234 if the ISA isn't valid. */
9236 static const struct mips_cpu_info *
9237 mips_cpu_info_from_isa (int isa)
9239 const struct mips_cpu_info *p;
9241 for (p = mips_cpu_info_table; p->name != 0; p++)
9248 /* Adjust the cost of INSN based on the relationship between INSN that
9249 is dependent on DEP_INSN through the dependence LINK. The default
9250 is to make no adjustment to COST.
9252 On the MIPS, ignore the cost of anti- and output-dependencies. */
9254 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9255 rtx dep ATTRIBUTE_UNUSED, int cost)
9257 if (REG_NOTE_KIND (link) != 0)
9258 return 0; /* Anti or output dependence. */
9262 /* Implement HARD_REGNO_NREGS. The size of FP registers are controlled
9263 by UNITS_PER_FPREG. All other registers are word sized. */
9266 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9268 if (! FP_REG_P (regno))
9269 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9271 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9274 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9275 all BLKmode objects are returned in memory. Under the new (N32 and
9276 64-bit MIPS ABIs) small structures are returned in a register.
9277 Objects with varying size must still be returned in memory, of
9281 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9284 return (TYPE_MODE (type) == BLKmode);
9286 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9287 || (int_size_in_bytes (type) == -1));
9291 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9293 return !TARGET_OLDABI;
9297 mips_issue_rate (void)
9301 case PROCESSOR_R5400:
9302 case PROCESSOR_R5500:
9303 case PROCESSOR_R7000:
9304 case PROCESSOR_R9000:
9315 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
9316 processors that have a DFA pipeline description. */
9319 mips_use_dfa_pipeline_interface (void)
9323 case PROCESSOR_R5400:
9324 case PROCESSOR_R5500:
9325 case PROCESSOR_R7000:
9326 case PROCESSOR_R9000:
9327 case PROCESSOR_SR71000:
9337 mips_emit_prefetch (rtx *operands)
9339 int write = INTVAL (operands[1]);
9340 int locality = INTVAL (operands[2]);
9341 int indexed = GET_CODE (operands[3]) == REG;
9346 code = (write ? 5 : 4); /* store_streamed / load_streamed. */
9347 else if (locality <= 2)
9348 code = (write ? 1 : 0); /* store / load. */
9350 code = (write ? 7 : 6); /* store_retained / load_retained. */
9352 sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
9353 output_asm_insn (buffer, operands);
9360 /* Output assembly to switch to section NAME with attribute FLAGS. */
9363 irix_asm_named_section_1 (const char *name, unsigned int flags,
9366 unsigned int sh_type, sh_flags, sh_entsize;
9369 if (!(flags & SECTION_DEBUG))
9370 sh_flags |= 2; /* SHF_ALLOC */
9371 if (flags & SECTION_WRITE)
9372 sh_flags |= 1; /* SHF_WRITE */
9373 if (flags & SECTION_CODE)
9374 sh_flags |= 4; /* SHF_EXECINSTR */
9375 if (flags & SECTION_SMALL)
9376 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9377 if (strcmp (name, ".debug_frame") == 0)
9378 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9379 if (flags & SECTION_DEBUG)
9380 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9381 else if (flags & SECTION_BSS)
9382 sh_type = 8; /* SHT_NOBITS */
9384 sh_type = 1; /* SHT_PROGBITS */
9386 if (flags & SECTION_CODE)
9391 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9392 name, sh_type, sh_flags, sh_entsize, align);
9396 irix_asm_named_section (const char *name, unsigned int flags)
9398 if (TARGET_SGI_O32_AS)
9399 default_no_named_section (name, flags);
9400 else if (mips_abi == ABI_32 && TARGET_GAS)
9401 default_elf_asm_named_section (name, flags);
9403 irix_asm_named_section_1 (name, flags, 0);
9406 /* In addition to emitting a .align directive, record the maximum
9407 alignment requested for the current section. */
9409 struct GTY (()) irix_section_align_entry
9416 static htab_t irix_section_align_htab;
9417 static FILE *irix_orig_asm_out_file;
9420 irix_section_align_entry_eq (const void *p1, const void *p2)
9422 const struct irix_section_align_entry *old = p1;
9423 const char *new = p2;
9425 return strcmp (old->name, new) == 0;
9429 irix_section_align_entry_hash (const void *p)
9431 const struct irix_section_align_entry *old = p;
9432 return htab_hash_string (old->name);
9436 irix_asm_output_align (FILE *file, unsigned int log)
9438 const char *section = current_section_name ();
9439 struct irix_section_align_entry **slot, *entry;
9441 if (mips_abi != ABI_32)
9446 slot = (struct irix_section_align_entry **)
9447 htab_find_slot_with_hash (irix_section_align_htab, section,
9448 htab_hash_string (section), INSERT);
9452 entry = (struct irix_section_align_entry *)
9453 xmalloc (sizeof (struct irix_section_align_entry));
9455 entry->name = section;
9457 entry->flags = current_section_flags ();
9459 else if (entry->log < log)
9463 fprintf (file, "\t.align\t%u\n", log);
9466 /* The IRIX assembler does not record alignment from .align directives,
9467 but takes it from the first .section directive seen. Play file
9468 switching games so that we can emit a .section directive at the
9469 beginning of the file with the proper alignment attached. */
9472 irix_file_start (void)
9476 if (mips_abi == ABI_32)
9479 irix_orig_asm_out_file = asm_out_file;
9480 asm_out_file = tmpfile ();
9482 irix_section_align_htab = htab_create (31, irix_section_align_entry_hash,
9483 irix_section_align_entry_eq, NULL);
9487 irix_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
9489 const struct irix_section_align_entry *entry
9490 = *(const struct irix_section_align_entry **) slot;
9492 irix_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
9497 copy_file_data (FILE *to, FILE *from)
9503 fatal_error ("can't rewind temp file: %m");
9505 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
9506 if (fwrite (buffer, 1, len, to) != len)
9507 fatal_error ("can't write to output file: %m");
9510 fatal_error ("can't read from temp file: %m");
9513 fatal_error ("can't close temp file: %m");
9517 irix_file_end (void)
9519 if (mips_abi != ABI_32)
9521 /* Emit section directives with the proper alignment at the top of the
9522 real output file. */
9523 FILE *temp = asm_out_file;
9524 asm_out_file = irix_orig_asm_out_file;
9525 htab_traverse (irix_section_align_htab, irix_section_align_1, NULL);
9527 /* Copy the data emitted to the temp file to the real output file. */
9528 copy_file_data (asm_out_file, temp);
9535 /* Implement TARGET_SECTION_TYPE_FLAGS. Make sure that .sdata and
9536 .sbss sections get the SECTION_SMALL flag: this isn't set by the
9540 irix_section_type_flags (tree decl, const char *section, int relocs_p)
9544 flags = default_section_type_flags (decl, section, relocs_p);
9546 if (strcmp (section, ".sdata") == 0
9547 || strcmp (section, ".sbss") == 0
9548 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9549 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9550 flags |= SECTION_SMALL;
9555 #endif /* TARGET_IRIX */
9557 #include "gt-mips.h"