1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type {
185 /* Enumerates the setting of the -mr10k-cache-barrier option. */
186 enum mips_r10k_cache_barrier_setting {
187 R10K_CACHE_BARRIER_NONE,
188 R10K_CACHE_BARRIER_STORE,
189 R10K_CACHE_BARRIER_LOAD_STORE
192 /* Macros to create an enumeration identifier for a function prototype. */
193 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
194 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
195 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
196 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
198 /* Classifies the prototype of a built-in function. */
199 enum mips_function_type {
200 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
201 #include "config/mips/mips-ftypes.def"
202 #undef DEF_MIPS_FTYPE
206 /* Specifies how a built-in function should be converted into rtl. */
207 enum mips_builtin_type {
208 /* The function corresponds directly to an .md pattern. The return
209 value is mapped to operand 0 and the arguments are mapped to
210 operands 1 and above. */
213 /* The function corresponds directly to an .md pattern. There is no return
214 value and the arguments are mapped to operands 0 and above. */
215 MIPS_BUILTIN_DIRECT_NO_TARGET,
217 /* The function corresponds to a comparison instruction followed by
218 a mips_cond_move_tf_ps pattern. The first two arguments are the
219 values to compare and the second two arguments are the vector
220 operands for the movt.ps or movf.ps instruction (in assembly order). */
224 /* The function corresponds to a V2SF comparison instruction. Operand 0
225 of this instruction is the result of the comparison, which has mode
226 CCV2 or CCV4. The function arguments are mapped to operands 1 and
227 above. The function's return value is an SImode boolean that is
228 true under the following conditions:
230 MIPS_BUILTIN_CMP_ANY: one of the registers is true
231 MIPS_BUILTIN_CMP_ALL: all of the registers are true
232 MIPS_BUILTIN_CMP_LOWER: the first register is true
233 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
234 MIPS_BUILTIN_CMP_ANY,
235 MIPS_BUILTIN_CMP_ALL,
236 MIPS_BUILTIN_CMP_UPPER,
237 MIPS_BUILTIN_CMP_LOWER,
239 /* As above, but the instruction only sets a single $fcc register. */
240 MIPS_BUILTIN_CMP_SINGLE,
242 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
243 MIPS_BUILTIN_BPOSGE32
246 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
247 #define MIPS_FP_CONDITIONS(MACRO) \
265 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
266 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
267 enum mips_fp_condition {
268 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
271 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
272 #define STRINGIFY(X) #X
273 static const char *const mips_fp_conditions[] = {
274 MIPS_FP_CONDITIONS (STRINGIFY)
277 /* Information about a function's frame layout. */
278 struct GTY(()) mips_frame_info {
279 /* The size of the frame in bytes. */
280 HOST_WIDE_INT total_size;
282 /* The number of bytes allocated to variables. */
283 HOST_WIDE_INT var_size;
285 /* The number of bytes allocated to outgoing function arguments. */
286 HOST_WIDE_INT args_size;
288 /* The number of bytes allocated to the .cprestore slot, or 0 if there
290 HOST_WIDE_INT cprestore_size;
292 /* Bit X is set if the function saves or restores GPR X. */
295 /* Likewise FPR X. */
298 /* Likewise doubleword accumulator X ($acX). */
299 unsigned int acc_mask;
301 /* The number of GPRs, FPRs, doubleword accumulators and COP0
305 unsigned int num_acc;
306 unsigned int num_cop0_regs;
308 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
309 save slots from the top of the frame, or zero if no such slots are
311 HOST_WIDE_INT gp_save_offset;
312 HOST_WIDE_INT fp_save_offset;
313 HOST_WIDE_INT acc_save_offset;
314 HOST_WIDE_INT cop0_save_offset;
316 /* Likewise, but giving offsets from the bottom of the frame. */
317 HOST_WIDE_INT gp_sp_offset;
318 HOST_WIDE_INT fp_sp_offset;
319 HOST_WIDE_INT acc_sp_offset;
320 HOST_WIDE_INT cop0_sp_offset;
322 /* Similar, but the value passed to _mcount. */
323 HOST_WIDE_INT ra_fp_offset;
325 /* The offset of arg_pointer_rtx from the bottom of the frame. */
326 HOST_WIDE_INT arg_pointer_offset;
328 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
329 HOST_WIDE_INT hard_frame_pointer_offset;
332 struct GTY(()) machine_function {
333 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
334 rtx mips16_gp_pseudo_rtx;
336 /* The number of extra stack bytes taken up by register varargs.
337 This area is allocated by the callee at the very top of the frame. */
340 /* The current frame information, calculated by mips_compute_frame_info. */
341 struct mips_frame_info frame;
343 /* The register to use as the function's global pointer, or INVALID_REGNUM
344 if the function doesn't need one. */
345 unsigned int global_pointer;
347 /* How many instructions it takes to load a label into $AT, or 0 if
348 this property hasn't yet been calculated. */
349 unsigned int load_label_length;
351 /* True if mips_adjust_insn_length should ignore an instruction's
353 bool ignore_hazard_length_p;
355 /* True if the whole function is suitable for .set noreorder and
357 bool all_noreorder_p;
359 /* True if the function has "inflexible" and "flexible" references
360 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
361 and mips_cfun_has_flexible_gp_ref_p for details. */
362 bool has_inflexible_gp_insn_p;
363 bool has_flexible_gp_insn_p;
365 /* True if the function's prologue must load the global pointer
366 value into pic_offset_table_rtx and store the same value in
367 the function's cprestore slot (if any). Even if this value
368 is currently false, we may decide to set it to true later;
369 see mips_must_initialize_gp_p () for details. */
370 bool must_initialize_gp_p;
372 /* True if the current function must restore $gp after any potential
373 clobber. This value is only meaningful during the first post-epilogue
374 split_insns pass; see mips_must_initialize_gp_p () for details. */
375 bool must_restore_gp_when_clobbered_p;
377 /* True if we have emitted an instruction to initialize
378 mips16_gp_pseudo_rtx. */
379 bool initialized_mips16_gp_pseudo_p;
381 /* True if this is an interrupt handler. */
382 bool interrupt_handler_p;
384 /* True if this is an interrupt handler that uses shadow registers. */
385 bool use_shadow_register_set_p;
387 /* True if this is an interrupt handler that should keep interrupts
389 bool keep_interrupts_masked_p;
391 /* True if this is an interrupt handler that should use DERET
393 bool use_debug_exception_return_p;
396 /* Information about a single argument. */
397 struct mips_arg_info {
398 /* True if the argument is passed in a floating-point register, or
399 would have been if we hadn't run out of registers. */
402 /* The number of words passed in registers, rounded up. */
403 unsigned int reg_words;
405 /* For EABI, the offset of the first register from GP_ARG_FIRST or
406 FP_ARG_FIRST. For other ABIs, the offset of the first register from
407 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
408 comment for details).
410 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
412 unsigned int reg_offset;
414 /* The number of words that must be passed on the stack, rounded up. */
415 unsigned int stack_words;
417 /* The offset from the start of the stack overflow area of the argument's
418 first stack word. Only meaningful when STACK_WORDS is nonzero. */
419 unsigned int stack_offset;
422 /* Information about an address described by mips_address_type.
428 REG is the base register and OFFSET is the constant offset.
431 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
432 is the type of symbol it references.
435 SYMBOL_TYPE is the type of symbol that the address references. */
436 struct mips_address_info {
437 enum mips_address_type type;
440 enum mips_symbol_type symbol_type;
443 /* One stage in a constant building sequence. These sequences have
447 A = A CODE[1] VALUE[1]
448 A = A CODE[2] VALUE[2]
451 where A is an accumulator, each CODE[i] is a binary rtl operation
452 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
453 struct mips_integer_op {
455 unsigned HOST_WIDE_INT value;
458 /* The largest number of operations needed to load an integer constant.
459 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
460 When the lowest bit is clear, we can try, but reject a sequence with
461 an extra SLL at the end. */
462 #define MIPS_MAX_INTEGER_OPS 7
464 /* Information about a MIPS16e SAVE or RESTORE instruction. */
465 struct mips16e_save_restore_info {
466 /* The number of argument registers saved by a SAVE instruction.
467 0 for RESTORE instructions. */
470 /* Bit X is set if the instruction saves or restores GPR X. */
473 /* The total number of bytes to allocate. */
477 /* Global variables for machine-dependent things. */
479 /* The -G setting, or the configuration's default small-data limit if
480 no -G option is given. */
481 static unsigned int mips_small_data_threshold;
483 /* The number of file directives written by mips_output_filename. */
484 int num_source_filenames;
486 /* The name that appeared in the last .file directive written by
487 mips_output_filename, or "" if mips_output_filename hasn't
488 written anything yet. */
489 const char *current_function_file = "";
491 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
494 /* Arrays that map GCC register numbers to debugger register numbers. */
495 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
496 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
498 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
499 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
500 struct mips_asm_switch mips_nomacro = { "macro", 0 };
501 struct mips_asm_switch mips_noat = { "at", 0 };
503 /* True if we're writing out a branch-likely instruction rather than a
505 static bool mips_branch_likely;
507 /* The current instruction-set architecture. */
508 enum processor_type mips_arch;
509 const struct mips_cpu_info *mips_arch_info;
511 /* The processor that we should tune the code for. */
512 enum processor_type mips_tune;
513 const struct mips_cpu_info *mips_tune_info;
515 /* The ISA level associated with mips_arch. */
518 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
519 static const struct mips_cpu_info *mips_isa_option_info;
521 /* Which ABI to use. */
522 int mips_abi = MIPS_ABI_DEFAULT;
524 /* Which cost information to use. */
525 const struct mips_rtx_cost_data *mips_cost;
527 /* The ambient target flags, excluding MASK_MIPS16. */
528 static int mips_base_target_flags;
530 /* True if MIPS16 is the default mode. */
531 bool mips_base_mips16;
533 /* The ambient values of other global variables. */
534 static int mips_base_schedule_insns; /* flag_schedule_insns */
535 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
536 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
537 static int mips_base_align_loops; /* align_loops */
538 static int mips_base_align_jumps; /* align_jumps */
539 static int mips_base_align_functions; /* align_functions */
541 /* The -mcode-readable setting. */
542 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
544 /* The -mr10k-cache-barrier setting. */
545 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
547 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
548 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
550 /* Index C is true if character C is a valid PRINT_OPERAND punctation
552 bool mips_print_operand_punct[256];
554 static GTY (()) int mips_output_filename_first_time = 1;
556 /* mips_split_p[X] is true if symbols of type X can be split by
557 mips_split_symbol. */
558 bool mips_split_p[NUM_SYMBOL_TYPES];
560 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
561 can be split by mips_split_symbol. */
562 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
564 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
565 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
566 if they are matched by a special .md file pattern. */
567 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
569 /* Likewise for HIGHs. */
570 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
572 /* Index R is the smallest register class that contains register R. */
573 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
574 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
575 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
576 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
577 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
578 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
579 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
580 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
581 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
582 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
583 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
584 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
585 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
586 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
587 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
588 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
589 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
590 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
591 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
592 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
593 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
594 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
595 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
596 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
597 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
598 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
599 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
600 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
601 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
602 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
603 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
604 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
605 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
606 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
607 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
608 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
609 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
610 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
611 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
612 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
613 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
614 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
615 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
616 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
617 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
618 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
619 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
620 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
623 /* The value of TARGET_ATTRIBUTE_TABLE. */
624 static const struct attribute_spec mips_attribute_table[] = {
625 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
626 { "long_call", 0, 0, false, true, true, NULL },
627 { "far", 0, 0, false, true, true, NULL },
628 { "near", 0, 0, false, true, true, NULL },
629 /* We would really like to treat "mips16" and "nomips16" as type
630 attributes, but GCC doesn't provide the hooks we need to support
631 the right conversion rules. As declaration attributes, they affect
632 code generation but don't carry other semantics. */
633 { "mips16", 0, 0, true, false, false, NULL },
634 { "nomips16", 0, 0, true, false, false, NULL },
635 /* Allow functions to be specified as interrupt handlers */
636 { "interrupt", 0, 0, false, true, true, NULL },
637 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
638 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
639 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
640 { NULL, 0, 0, false, false, false, NULL }
643 /* A table describing all the processors GCC knows about. Names are
644 matched in the order listed. The first mention of an ISA level is
645 taken as the canonical name for that ISA.
647 To ease comparison, please keep this table in the same order
648 as GAS's mips_cpu_info_table. Please also make sure that
649 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
650 options correctly. */
651 static const struct mips_cpu_info mips_cpu_info_table[] = {
652 /* Entries for generic ISAs. */
653 { "mips1", PROCESSOR_R3000, 1, 0 },
654 { "mips2", PROCESSOR_R6000, 2, 0 },
655 { "mips3", PROCESSOR_R4000, 3, 0 },
656 { "mips4", PROCESSOR_R8000, 4, 0 },
657 /* Prefer not to use branch-likely instructions for generic MIPS32rX
658 and MIPS64rX code. The instructions were officially deprecated
659 in revisions 2 and earlier, but revision 3 is likely to downgrade
660 that to a recommendation to avoid the instructions in code that
661 isn't tuned to a specific processor. */
662 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
663 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
664 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
665 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
666 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
668 /* MIPS I processors. */
669 { "r3000", PROCESSOR_R3000, 1, 0 },
670 { "r2000", PROCESSOR_R3000, 1, 0 },
671 { "r3900", PROCESSOR_R3900, 1, 0 },
673 /* MIPS II processors. */
674 { "r6000", PROCESSOR_R6000, 2, 0 },
676 /* MIPS III processors. */
677 { "r4000", PROCESSOR_R4000, 3, 0 },
678 { "vr4100", PROCESSOR_R4100, 3, 0 },
679 { "vr4111", PROCESSOR_R4111, 3, 0 },
680 { "vr4120", PROCESSOR_R4120, 3, 0 },
681 { "vr4130", PROCESSOR_R4130, 3, 0 },
682 { "vr4300", PROCESSOR_R4300, 3, 0 },
683 { "r4400", PROCESSOR_R4000, 3, 0 },
684 { "r4600", PROCESSOR_R4600, 3, 0 },
685 { "orion", PROCESSOR_R4600, 3, 0 },
686 { "r4650", PROCESSOR_R4650, 3, 0 },
687 /* ST Loongson 2E/2F processors. */
688 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
689 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
691 /* MIPS IV processors. */
692 { "r8000", PROCESSOR_R8000, 4, 0 },
693 { "r10000", PROCESSOR_R10000, 4, 0 },
694 { "r12000", PROCESSOR_R10000, 4, 0 },
695 { "r14000", PROCESSOR_R10000, 4, 0 },
696 { "r16000", PROCESSOR_R10000, 4, 0 },
697 { "vr5000", PROCESSOR_R5000, 4, 0 },
698 { "vr5400", PROCESSOR_R5400, 4, 0 },
699 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
700 { "rm7000", PROCESSOR_R7000, 4, 0 },
701 { "rm9000", PROCESSOR_R9000, 4, 0 },
703 /* MIPS32 processors. */
704 { "4kc", PROCESSOR_4KC, 32, 0 },
705 { "4km", PROCESSOR_4KC, 32, 0 },
706 { "4kp", PROCESSOR_4KP, 32, 0 },
707 { "4ksc", PROCESSOR_4KC, 32, 0 },
709 /* MIPS32 Release 2 processors. */
710 { "m4k", PROCESSOR_M4K, 33, 0 },
711 { "4kec", PROCESSOR_4KC, 33, 0 },
712 { "4kem", PROCESSOR_4KC, 33, 0 },
713 { "4kep", PROCESSOR_4KP, 33, 0 },
714 { "4ksd", PROCESSOR_4KC, 33, 0 },
716 { "24kc", PROCESSOR_24KC, 33, 0 },
717 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
718 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
719 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
720 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
721 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
723 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
724 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
725 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
726 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
727 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
728 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
730 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
731 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
732 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
733 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
734 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
735 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
737 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
738 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
739 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
740 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
741 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
742 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
743 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
745 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
746 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
747 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
748 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
750 /* MIPS64 processors. */
751 { "5kc", PROCESSOR_5KC, 64, 0 },
752 { "5kf", PROCESSOR_5KF, 64, 0 },
753 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
754 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
755 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
756 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
757 { "xlr", PROCESSOR_XLR, 64, 0 },
759 /* MIPS64 Release 2 processors. */
760 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
763 /* Default costs. If these are used for a processor we should look
764 up the actual costs. */
765 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
766 COSTS_N_INSNS (7), /* fp_mult_sf */ \
767 COSTS_N_INSNS (8), /* fp_mult_df */ \
768 COSTS_N_INSNS (23), /* fp_div_sf */ \
769 COSTS_N_INSNS (36), /* fp_div_df */ \
770 COSTS_N_INSNS (10), /* int_mult_si */ \
771 COSTS_N_INSNS (10), /* int_mult_di */ \
772 COSTS_N_INSNS (69), /* int_div_si */ \
773 COSTS_N_INSNS (69), /* int_div_di */ \
774 2, /* branch_cost */ \
775 4 /* memory_latency */
777 /* Floating-point costs for processors without an FPU. Just assume that
778 all floating-point libcalls are very expensive. */
779 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
780 COSTS_N_INSNS (256), /* fp_mult_sf */ \
781 COSTS_N_INSNS (256), /* fp_mult_df */ \
782 COSTS_N_INSNS (256), /* fp_div_sf */ \
783 COSTS_N_INSNS (256) /* fp_div_df */
785 /* Costs to use when optimizing for size. */
786 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
787 COSTS_N_INSNS (1), /* fp_add */
788 COSTS_N_INSNS (1), /* fp_mult_sf */
789 COSTS_N_INSNS (1), /* fp_mult_df */
790 COSTS_N_INSNS (1), /* fp_div_sf */
791 COSTS_N_INSNS (1), /* fp_div_df */
792 COSTS_N_INSNS (1), /* int_mult_si */
793 COSTS_N_INSNS (1), /* int_mult_di */
794 COSTS_N_INSNS (1), /* int_div_si */
795 COSTS_N_INSNS (1), /* int_div_di */
797 4 /* memory_latency */
800 /* Costs to use when optimizing for speed, indexed by processor. */
801 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
803 COSTS_N_INSNS (2), /* fp_add */
804 COSTS_N_INSNS (4), /* fp_mult_sf */
805 COSTS_N_INSNS (5), /* fp_mult_df */
806 COSTS_N_INSNS (12), /* fp_div_sf */
807 COSTS_N_INSNS (19), /* fp_div_df */
808 COSTS_N_INSNS (12), /* int_mult_si */
809 COSTS_N_INSNS (12), /* int_mult_di */
810 COSTS_N_INSNS (35), /* int_div_si */
811 COSTS_N_INSNS (35), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (6), /* int_mult_si */
818 COSTS_N_INSNS (6), /* int_mult_di */
819 COSTS_N_INSNS (36), /* int_div_si */
820 COSTS_N_INSNS (36), /* int_div_di */
822 4 /* memory_latency */
826 COSTS_N_INSNS (36), /* int_mult_si */
827 COSTS_N_INSNS (36), /* int_mult_di */
828 COSTS_N_INSNS (37), /* int_div_si */
829 COSTS_N_INSNS (37), /* int_div_di */
831 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* int_mult_si */
836 COSTS_N_INSNS (11), /* int_mult_di */
837 COSTS_N_INSNS (36), /* int_div_si */
838 COSTS_N_INSNS (68), /* int_div_di */
840 4 /* memory_latency */
843 COSTS_N_INSNS (4), /* fp_add */
844 COSTS_N_INSNS (4), /* fp_mult_sf */
845 COSTS_N_INSNS (5), /* fp_mult_df */
846 COSTS_N_INSNS (17), /* fp_div_sf */
847 COSTS_N_INSNS (32), /* fp_div_df */
848 COSTS_N_INSNS (4), /* int_mult_si */
849 COSTS_N_INSNS (11), /* int_mult_di */
850 COSTS_N_INSNS (36), /* int_div_si */
851 COSTS_N_INSNS (68), /* int_div_di */
853 4 /* memory_latency */
856 COSTS_N_INSNS (4), /* fp_add */
857 COSTS_N_INSNS (4), /* fp_mult_sf */
858 COSTS_N_INSNS (5), /* fp_mult_df */
859 COSTS_N_INSNS (17), /* fp_div_sf */
860 COSTS_N_INSNS (32), /* fp_div_df */
861 COSTS_N_INSNS (4), /* int_mult_si */
862 COSTS_N_INSNS (7), /* int_mult_di */
863 COSTS_N_INSNS (42), /* int_div_si */
864 COSTS_N_INSNS (72), /* int_div_di */
866 4 /* memory_latency */
870 COSTS_N_INSNS (5), /* int_mult_si */
871 COSTS_N_INSNS (5), /* int_mult_di */
872 COSTS_N_INSNS (41), /* int_div_si */
873 COSTS_N_INSNS (41), /* int_div_di */
875 4 /* memory_latency */
878 COSTS_N_INSNS (8), /* fp_add */
879 COSTS_N_INSNS (8), /* fp_mult_sf */
880 COSTS_N_INSNS (10), /* fp_mult_df */
881 COSTS_N_INSNS (34), /* fp_div_sf */
882 COSTS_N_INSNS (64), /* fp_div_df */
883 COSTS_N_INSNS (5), /* int_mult_si */
884 COSTS_N_INSNS (5), /* int_mult_di */
885 COSTS_N_INSNS (41), /* int_div_si */
886 COSTS_N_INSNS (41), /* int_div_di */
888 4 /* memory_latency */
891 COSTS_N_INSNS (4), /* fp_add */
892 COSTS_N_INSNS (4), /* fp_mult_sf */
893 COSTS_N_INSNS (5), /* fp_mult_df */
894 COSTS_N_INSNS (17), /* fp_div_sf */
895 COSTS_N_INSNS (32), /* fp_div_df */
896 COSTS_N_INSNS (5), /* int_mult_si */
897 COSTS_N_INSNS (5), /* int_mult_di */
898 COSTS_N_INSNS (41), /* int_div_si */
899 COSTS_N_INSNS (41), /* int_div_di */
901 4 /* memory_latency */
905 COSTS_N_INSNS (5), /* int_mult_si */
906 COSTS_N_INSNS (5), /* int_mult_di */
907 COSTS_N_INSNS (41), /* int_div_si */
908 COSTS_N_INSNS (41), /* int_div_di */
910 4 /* memory_latency */
913 COSTS_N_INSNS (8), /* fp_add */
914 COSTS_N_INSNS (8), /* fp_mult_sf */
915 COSTS_N_INSNS (10), /* fp_mult_df */
916 COSTS_N_INSNS (34), /* fp_div_sf */
917 COSTS_N_INSNS (64), /* fp_div_df */
918 COSTS_N_INSNS (5), /* int_mult_si */
919 COSTS_N_INSNS (5), /* int_mult_di */
920 COSTS_N_INSNS (41), /* int_div_si */
921 COSTS_N_INSNS (41), /* int_div_di */
923 4 /* memory_latency */
926 COSTS_N_INSNS (4), /* fp_add */
927 COSTS_N_INSNS (4), /* fp_mult_sf */
928 COSTS_N_INSNS (5), /* fp_mult_df */
929 COSTS_N_INSNS (17), /* fp_div_sf */
930 COSTS_N_INSNS (32), /* fp_div_df */
931 COSTS_N_INSNS (5), /* int_mult_si */
932 COSTS_N_INSNS (5), /* int_mult_di */
933 COSTS_N_INSNS (41), /* int_div_si */
934 COSTS_N_INSNS (41), /* int_div_di */
936 4 /* memory_latency */
939 COSTS_N_INSNS (6), /* fp_add */
940 COSTS_N_INSNS (6), /* fp_mult_sf */
941 COSTS_N_INSNS (7), /* fp_mult_df */
942 COSTS_N_INSNS (25), /* fp_div_sf */
943 COSTS_N_INSNS (48), /* fp_div_df */
944 COSTS_N_INSNS (5), /* int_mult_si */
945 COSTS_N_INSNS (5), /* int_mult_di */
946 COSTS_N_INSNS (41), /* int_div_si */
947 COSTS_N_INSNS (41), /* int_div_di */
949 4 /* memory_latency */
963 COSTS_N_INSNS (5), /* int_mult_si */
964 COSTS_N_INSNS (5), /* int_mult_di */
965 COSTS_N_INSNS (72), /* int_div_si */
966 COSTS_N_INSNS (72), /* int_div_di */
968 4 /* memory_latency */
971 COSTS_N_INSNS (2), /* fp_add */
972 COSTS_N_INSNS (4), /* fp_mult_sf */
973 COSTS_N_INSNS (5), /* fp_mult_df */
974 COSTS_N_INSNS (12), /* fp_div_sf */
975 COSTS_N_INSNS (19), /* fp_div_df */
976 COSTS_N_INSNS (2), /* int_mult_si */
977 COSTS_N_INSNS (2), /* int_mult_di */
978 COSTS_N_INSNS (35), /* int_div_si */
979 COSTS_N_INSNS (35), /* int_div_di */
981 4 /* memory_latency */
984 COSTS_N_INSNS (3), /* fp_add */
985 COSTS_N_INSNS (5), /* fp_mult_sf */
986 COSTS_N_INSNS (6), /* fp_mult_df */
987 COSTS_N_INSNS (15), /* fp_div_sf */
988 COSTS_N_INSNS (16), /* fp_div_df */
989 COSTS_N_INSNS (17), /* int_mult_si */
990 COSTS_N_INSNS (17), /* int_mult_di */
991 COSTS_N_INSNS (38), /* int_div_si */
992 COSTS_N_INSNS (38), /* int_div_di */
994 6 /* memory_latency */
997 COSTS_N_INSNS (6), /* fp_add */
998 COSTS_N_INSNS (7), /* fp_mult_sf */
999 COSTS_N_INSNS (8), /* fp_mult_df */
1000 COSTS_N_INSNS (23), /* fp_div_sf */
1001 COSTS_N_INSNS (36), /* fp_div_df */
1002 COSTS_N_INSNS (10), /* int_mult_si */
1003 COSTS_N_INSNS (10), /* int_mult_di */
1004 COSTS_N_INSNS (69), /* int_div_si */
1005 COSTS_N_INSNS (69), /* int_div_di */
1006 2, /* branch_cost */
1007 6 /* memory_latency */
1019 /* The only costs that appear to be updated here are
1020 integer multiplication. */
1022 COSTS_N_INSNS (4), /* int_mult_si */
1023 COSTS_N_INSNS (6), /* int_mult_di */
1024 COSTS_N_INSNS (69), /* int_div_si */
1025 COSTS_N_INSNS (69), /* int_div_di */
1026 1, /* branch_cost */
1027 4 /* memory_latency */
1039 COSTS_N_INSNS (6), /* fp_add */
1040 COSTS_N_INSNS (4), /* fp_mult_sf */
1041 COSTS_N_INSNS (5), /* fp_mult_df */
1042 COSTS_N_INSNS (23), /* fp_div_sf */
1043 COSTS_N_INSNS (36), /* fp_div_df */
1044 COSTS_N_INSNS (5), /* int_mult_si */
1045 COSTS_N_INSNS (5), /* int_mult_di */
1046 COSTS_N_INSNS (36), /* int_div_si */
1047 COSTS_N_INSNS (36), /* int_div_di */
1048 1, /* branch_cost */
1049 4 /* memory_latency */
1052 COSTS_N_INSNS (6), /* fp_add */
1053 COSTS_N_INSNS (5), /* fp_mult_sf */
1054 COSTS_N_INSNS (6), /* fp_mult_df */
1055 COSTS_N_INSNS (30), /* fp_div_sf */
1056 COSTS_N_INSNS (59), /* fp_div_df */
1057 COSTS_N_INSNS (3), /* int_mult_si */
1058 COSTS_N_INSNS (4), /* int_mult_di */
1059 COSTS_N_INSNS (42), /* int_div_si */
1060 COSTS_N_INSNS (74), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1065 COSTS_N_INSNS (6), /* fp_add */
1066 COSTS_N_INSNS (5), /* fp_mult_sf */
1067 COSTS_N_INSNS (6), /* fp_mult_df */
1068 COSTS_N_INSNS (30), /* fp_div_sf */
1069 COSTS_N_INSNS (59), /* fp_div_df */
1070 COSTS_N_INSNS (5), /* int_mult_si */
1071 COSTS_N_INSNS (9), /* int_mult_di */
1072 COSTS_N_INSNS (42), /* int_div_si */
1073 COSTS_N_INSNS (74), /* int_div_di */
1074 1, /* branch_cost */
1075 4 /* memory_latency */
1078 /* The only costs that are changed here are
1079 integer multiplication. */
1080 COSTS_N_INSNS (6), /* fp_add */
1081 COSTS_N_INSNS (7), /* fp_mult_sf */
1082 COSTS_N_INSNS (8), /* fp_mult_df */
1083 COSTS_N_INSNS (23), /* fp_div_sf */
1084 COSTS_N_INSNS (36), /* fp_div_df */
1085 COSTS_N_INSNS (5), /* int_mult_si */
1086 COSTS_N_INSNS (9), /* int_mult_di */
1087 COSTS_N_INSNS (69), /* int_div_si */
1088 COSTS_N_INSNS (69), /* int_div_di */
1089 1, /* branch_cost */
1090 4 /* memory_latency */
1096 /* The only costs that are changed here are
1097 integer multiplication. */
1098 COSTS_N_INSNS (6), /* fp_add */
1099 COSTS_N_INSNS (7), /* fp_mult_sf */
1100 COSTS_N_INSNS (8), /* fp_mult_df */
1101 COSTS_N_INSNS (23), /* fp_div_sf */
1102 COSTS_N_INSNS (36), /* fp_div_df */
1103 COSTS_N_INSNS (3), /* int_mult_si */
1104 COSTS_N_INSNS (8), /* int_mult_di */
1105 COSTS_N_INSNS (69), /* int_div_si */
1106 COSTS_N_INSNS (69), /* int_div_di */
1107 1, /* branch_cost */
1108 4 /* memory_latency */
1111 COSTS_N_INSNS (2), /* fp_add */
1112 COSTS_N_INSNS (2), /* fp_mult_sf */
1113 COSTS_N_INSNS (2), /* fp_mult_df */
1114 COSTS_N_INSNS (12), /* fp_div_sf */
1115 COSTS_N_INSNS (19), /* fp_div_df */
1116 COSTS_N_INSNS (5), /* int_mult_si */
1117 COSTS_N_INSNS (9), /* int_mult_di */
1118 COSTS_N_INSNS (34), /* int_div_si */
1119 COSTS_N_INSNS (66), /* int_div_di */
1120 1, /* branch_cost */
1121 4 /* memory_latency */
1124 /* These costs are the same as the SB-1A below. */
1125 COSTS_N_INSNS (4), /* fp_add */
1126 COSTS_N_INSNS (4), /* fp_mult_sf */
1127 COSTS_N_INSNS (4), /* fp_mult_df */
1128 COSTS_N_INSNS (24), /* fp_div_sf */
1129 COSTS_N_INSNS (32), /* fp_div_df */
1130 COSTS_N_INSNS (3), /* int_mult_si */
1131 COSTS_N_INSNS (4), /* int_mult_di */
1132 COSTS_N_INSNS (36), /* int_div_si */
1133 COSTS_N_INSNS (68), /* int_div_di */
1134 1, /* branch_cost */
1135 4 /* memory_latency */
1138 /* These costs are the same as the SB-1 above. */
1139 COSTS_N_INSNS (4), /* fp_add */
1140 COSTS_N_INSNS (4), /* fp_mult_sf */
1141 COSTS_N_INSNS (4), /* fp_mult_df */
1142 COSTS_N_INSNS (24), /* fp_div_sf */
1143 COSTS_N_INSNS (32), /* fp_div_df */
1144 COSTS_N_INSNS (3), /* int_mult_si */
1145 COSTS_N_INSNS (4), /* int_mult_di */
1146 COSTS_N_INSNS (36), /* int_div_si */
1147 COSTS_N_INSNS (68), /* int_div_di */
1148 1, /* branch_cost */
1149 4 /* memory_latency */
1156 COSTS_N_INSNS (8), /* int_mult_si */
1157 COSTS_N_INSNS (8), /* int_mult_di */
1158 COSTS_N_INSNS (72), /* int_div_si */
1159 COSTS_N_INSNS (72), /* int_div_di */
1160 1, /* branch_cost */
1161 4 /* memory_latency */
1165 static rtx mips_find_pic_call_symbol (rtx, rtx);
1167 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1168 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1169 struct GTY (()) mflip_mips16_entry {
1173 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1175 /* Hash table callbacks for mflip_mips16_htab. */
1178 mflip_mips16_htab_hash (const void *entry)
1180 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1184 mflip_mips16_htab_eq (const void *entry, const void *name)
1186 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1187 (const char *) name) == 0;
1190 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1191 mode, false if it should next add an attribute for the opposite mode. */
1192 static GTY(()) bool mips16_flipper;
1194 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1195 for -mflip-mips16. Return true if it should use "mips16" and false if
1196 it should use "nomips16". */
1199 mflip_mips16_use_mips16_p (tree decl)
1201 struct mflip_mips16_entry *entry;
1206 /* Use the opposite of the command-line setting for anonymous decls. */
1207 if (!DECL_NAME (decl))
1208 return !mips_base_mips16;
1210 if (!mflip_mips16_htab)
1211 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1212 mflip_mips16_htab_eq, NULL);
1214 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1215 hash = htab_hash_string (name);
1216 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1217 entry = (struct mflip_mips16_entry *) *slot;
1220 mips16_flipper = !mips16_flipper;
1221 entry = GGC_NEW (struct mflip_mips16_entry);
1223 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1226 return entry->mips16_p;
1229 /* Predicates to test for presence of "near" and "far"/"long_call"
1230 attributes on the given TYPE. */
1233 mips_near_type_p (const_tree type)
1235 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1239 mips_far_type_p (const_tree type)
1241 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1242 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1245 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1248 mips_mips16_decl_p (const_tree decl)
1250 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1254 mips_nomips16_decl_p (const_tree decl)
1256 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1259 /* Check if the interrupt attribute is set for a function. */
1262 mips_interrupt_type_p (tree type)
1264 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1267 /* Check if the attribute to use shadow register set is set for a function. */
1270 mips_use_shadow_register_set_p (tree type)
1272 return lookup_attribute ("use_shadow_register_set",
1273 TYPE_ATTRIBUTES (type)) != NULL;
1276 /* Check if the attribute to keep interrupts masked is set for a function. */
1279 mips_keep_interrupts_masked_p (tree type)
1281 return lookup_attribute ("keep_interrupts_masked",
1282 TYPE_ATTRIBUTES (type)) != NULL;
1285 /* Check if the attribute to use debug exception return is set for
1289 mips_use_debug_exception_return_p (tree type)
1291 return lookup_attribute ("use_debug_exception_return",
1292 TYPE_ATTRIBUTES (type)) != NULL;
1295 /* Return true if function DECL is a MIPS16 function. Return the ambient
1296 setting if DECL is null. */
1299 mips_use_mips16_mode_p (tree decl)
1303 /* Nested functions must use the same frame pointer as their
1304 parent and must therefore use the same ISA mode. */
1305 tree parent = decl_function_context (decl);
1308 if (mips_mips16_decl_p (decl))
1310 if (mips_nomips16_decl_p (decl))
1313 return mips_base_mips16;
1316 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1319 mips_comp_type_attributes (const_tree type1, const_tree type2)
1321 /* Disallow mixed near/far attributes. */
1322 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1324 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1329 /* Implement TARGET_INSERT_ATTRIBUTES. */
1332 mips_insert_attributes (tree decl, tree *attributes)
1335 bool mips16_p, nomips16_p;
1337 /* Check for "mips16" and "nomips16" attributes. */
1338 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1339 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1340 if (TREE_CODE (decl) != FUNCTION_DECL)
1343 error ("%qs attribute only applies to functions", "mips16");
1345 error ("%qs attribute only applies to functions", "nomips16");
1349 mips16_p |= mips_mips16_decl_p (decl);
1350 nomips16_p |= mips_nomips16_decl_p (decl);
1351 if (mips16_p || nomips16_p)
1353 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1354 if (mips16_p && nomips16_p)
1355 error ("%qE cannot have both %<mips16%> and "
1356 "%<nomips16%> attributes",
1359 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1361 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1362 "mips16" attribute, arbitrarily pick one. We must pick the same
1363 setting for duplicate declarations of a function. */
1364 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1365 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1370 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1373 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1375 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1376 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1377 error ("%qE redeclared with conflicting %qs attributes",
1378 DECL_NAME (newdecl), "mips16");
1379 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1380 error ("%qE redeclared with conflicting %qs attributes",
1381 DECL_NAME (newdecl), "nomips16");
1383 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1384 DECL_ATTRIBUTES (newdecl));
1387 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1388 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1391 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1393 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1395 *base_ptr = XEXP (x, 0);
1396 *offset_ptr = INTVAL (XEXP (x, 1));
1405 static unsigned int mips_build_integer (struct mips_integer_op *,
1406 unsigned HOST_WIDE_INT);
1408 /* A subroutine of mips_build_integer, with the same interface.
1409 Assume that the final action in the sequence should be a left shift. */
1412 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1414 unsigned int i, shift;
1416 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1417 since signed numbers are easier to load than unsigned ones. */
1419 while ((value & 1) == 0)
1420 value /= 2, shift++;
1422 i = mips_build_integer (codes, value);
1423 codes[i].code = ASHIFT;
1424 codes[i].value = shift;
1428 /* As for mips_build_shift, but assume that the final action will be
1429 an IOR or PLUS operation. */
1432 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1434 unsigned HOST_WIDE_INT high;
1437 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1438 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1440 /* The constant is too complex to load with a simple LUI/ORI pair,
1441 so we want to give the recursive call as many trailing zeros as
1442 possible. In this case, we know bit 16 is set and that the
1443 low 16 bits form a negative number. If we subtract that number
1444 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1445 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1446 codes[i].code = PLUS;
1447 codes[i].value = CONST_LOW_PART (value);
1451 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1452 bits gives a value with at least 17 trailing zeros. */
1453 i = mips_build_integer (codes, high);
1454 codes[i].code = IOR;
1455 codes[i].value = value & 0xffff;
1460 /* Fill CODES with a sequence of rtl operations to load VALUE.
1461 Return the number of operations needed. */
1464 mips_build_integer (struct mips_integer_op *codes,
1465 unsigned HOST_WIDE_INT value)
1467 if (SMALL_OPERAND (value)
1468 || SMALL_OPERAND_UNSIGNED (value)
1469 || LUI_OPERAND (value))
1471 /* The value can be loaded with a single instruction. */
1472 codes[0].code = UNKNOWN;
1473 codes[0].value = value;
1476 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1478 /* Either the constant is a simple LUI/ORI combination or its
1479 lowest bit is set. We don't want to shift in this case. */
1480 return mips_build_lower (codes, value);
1482 else if ((value & 0xffff) == 0)
1484 /* The constant will need at least three actions. The lowest
1485 16 bits are clear, so the final action will be a shift. */
1486 return mips_build_shift (codes, value);
1490 /* The final action could be a shift, add or inclusive OR.
1491 Rather than use a complex condition to select the best
1492 approach, try both mips_build_shift and mips_build_lower
1493 and pick the one that gives the shortest sequence.
1494 Note that this case is only used once per constant. */
1495 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1496 unsigned int cost, alt_cost;
1498 cost = mips_build_shift (codes, value);
1499 alt_cost = mips_build_lower (alt_codes, value);
1500 if (alt_cost < cost)
1502 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1509 /* Return true if symbols of type TYPE require a GOT access. */
1512 mips_got_symbol_type_p (enum mips_symbol_type type)
1516 case SYMBOL_GOT_PAGE_OFST:
1517 case SYMBOL_GOT_DISP:
1525 /* Return true if X is a thread-local symbol. */
1528 mips_tls_symbol_p (rtx x)
1530 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1533 /* Return true if SYMBOL_REF X is associated with a global symbol
1534 (in the STB_GLOBAL sense). */
1537 mips_global_symbol_p (const_rtx x)
1539 const_tree decl = SYMBOL_REF_DECL (x);
1542 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1544 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1545 or weak symbols. Relocations in the object file will be against
1546 the target symbol, so it's that symbol's binding that matters here. */
1547 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1550 /* Return true if function X is a libgcc MIPS16 stub function. */
1553 mips16_stub_function_p (const_rtx x)
1555 return (GET_CODE (x) == SYMBOL_REF
1556 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1559 /* Return true if function X is a locally-defined and locally-binding
1563 mips16_local_function_p (const_rtx x)
1565 return (GET_CODE (x) == SYMBOL_REF
1566 && SYMBOL_REF_LOCAL_P (x)
1567 && !SYMBOL_REF_EXTERNAL_P (x)
1568 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1571 /* Return true if SYMBOL_REF X binds locally. */
1574 mips_symbol_binds_local_p (const_rtx x)
1576 return (SYMBOL_REF_DECL (x)
1577 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1578 : SYMBOL_REF_LOCAL_P (x));
1581 /* Return true if rtx constants of mode MODE should be put into a small
1585 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1587 return (!TARGET_EMBEDDED_DATA
1588 && TARGET_LOCAL_SDATA
1589 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1592 /* Return true if X should not be moved directly into register $25.
1593 We need this because many versions of GAS will treat "la $25,foo" as
1594 part of a call sequence and so allow a global "foo" to be lazily bound. */
1597 mips_dangerous_for_la25_p (rtx x)
1599 return (!TARGET_EXPLICIT_RELOCS
1601 && GET_CODE (x) == SYMBOL_REF
1602 && mips_global_symbol_p (x));
1605 /* Return true if calls to X might need $25 to be valid on entry. */
1608 mips_use_pic_fn_addr_reg_p (const_rtx x)
1610 if (!TARGET_USE_PIC_FN_ADDR_REG)
1613 /* MIPS16 stub functions are guaranteed not to use $25. */
1614 if (mips16_stub_function_p (x))
1617 if (GET_CODE (x) == SYMBOL_REF)
1619 /* If PLTs and copy relocations are available, the static linker
1620 will make sure that $25 is valid on entry to the target function. */
1621 if (TARGET_ABICALLS_PIC0)
1624 /* Locally-defined functions use absolute accesses to set up
1625 the global pointer. */
1626 if (TARGET_ABSOLUTE_ABICALLS
1627 && mips_symbol_binds_local_p (x)
1628 && !SYMBOL_REF_EXTERNAL_P (x))
1635 /* Return the method that should be used to access SYMBOL_REF or
1636 LABEL_REF X in context CONTEXT. */
1638 static enum mips_symbol_type
1639 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1642 return SYMBOL_GOT_DISP;
1644 if (GET_CODE (x) == LABEL_REF)
1646 /* LABEL_REFs are used for jump tables as well as text labels.
1647 Only return SYMBOL_PC_RELATIVE if we know the label is in
1648 the text section. */
1649 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1650 return SYMBOL_PC_RELATIVE;
1652 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1653 return SYMBOL_GOT_PAGE_OFST;
1655 return SYMBOL_ABSOLUTE;
1658 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1660 if (SYMBOL_REF_TLS_MODEL (x))
1663 if (CONSTANT_POOL_ADDRESS_P (x))
1665 if (TARGET_MIPS16_TEXT_LOADS)
1666 return SYMBOL_PC_RELATIVE;
1668 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1669 return SYMBOL_PC_RELATIVE;
1671 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1672 return SYMBOL_GP_RELATIVE;
1675 /* Do not use small-data accesses for weak symbols; they may end up
1677 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1678 return SYMBOL_GP_RELATIVE;
1680 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1682 if (TARGET_ABICALLS_PIC2
1683 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1685 /* There are three cases to consider:
1687 - o32 PIC (either with or without explicit relocs)
1688 - n32/n64 PIC without explicit relocs
1689 - n32/n64 PIC with explicit relocs
1691 In the first case, both local and global accesses will use an
1692 R_MIPS_GOT16 relocation. We must correctly predict which of
1693 the two semantics (local or global) the assembler and linker
1694 will apply. The choice depends on the symbol's binding rather
1695 than its visibility.
1697 In the second case, the assembler will not use R_MIPS_GOT16
1698 relocations, but it chooses between local and global accesses
1699 in the same way as for o32 PIC.
1701 In the third case we have more freedom since both forms of
1702 access will work for any kind of symbol. However, there seems
1703 little point in doing things differently. */
1704 if (mips_global_symbol_p (x))
1705 return SYMBOL_GOT_DISP;
1707 return SYMBOL_GOT_PAGE_OFST;
1710 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1711 return SYMBOL_FORCE_TO_MEM;
1713 return SYMBOL_ABSOLUTE;
1716 /* Classify the base of symbolic expression X, given that X appears in
1719 static enum mips_symbol_type
1720 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1724 split_const (x, &x, &offset);
1725 if (UNSPEC_ADDRESS_P (x))
1726 return UNSPEC_ADDRESS_TYPE (x);
1728 return mips_classify_symbol (x, context);
1731 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1732 is the alignment in bytes of SYMBOL_REF X. */
1735 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1737 HOST_WIDE_INT align;
1739 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1740 return IN_RANGE (offset, 0, align - 1);
1743 /* Return true if X is a symbolic constant that can be used in context
1744 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1747 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1748 enum mips_symbol_type *symbol_type)
1752 split_const (x, &x, &offset);
1753 if (UNSPEC_ADDRESS_P (x))
1755 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1756 x = UNSPEC_ADDRESS (x);
1758 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1760 *symbol_type = mips_classify_symbol (x, context);
1761 if (*symbol_type == SYMBOL_TLS)
1767 if (offset == const0_rtx)
1770 /* Check whether a nonzero offset is valid for the underlying
1772 switch (*symbol_type)
1774 case SYMBOL_ABSOLUTE:
1775 case SYMBOL_FORCE_TO_MEM:
1776 case SYMBOL_32_HIGH:
1777 case SYMBOL_64_HIGH:
1780 /* If the target has 64-bit pointers and the object file only
1781 supports 32-bit symbols, the values of those symbols will be
1782 sign-extended. In this case we can't allow an arbitrary offset
1783 in case the 32-bit value X + OFFSET has a different sign from X. */
1784 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1785 return offset_within_block_p (x, INTVAL (offset));
1787 /* In other cases the relocations can handle any offset. */
1790 case SYMBOL_PC_RELATIVE:
1791 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1792 In this case, we no longer have access to the underlying constant,
1793 but the original symbol-based access was known to be valid. */
1794 if (GET_CODE (x) == LABEL_REF)
1799 case SYMBOL_GP_RELATIVE:
1800 /* Make sure that the offset refers to something within the
1801 same object block. This should guarantee that the final
1802 PC- or GP-relative offset is within the 16-bit limit. */
1803 return offset_within_block_p (x, INTVAL (offset));
1805 case SYMBOL_GOT_PAGE_OFST:
1806 case SYMBOL_GOTOFF_PAGE:
1807 /* If the symbol is global, the GOT entry will contain the symbol's
1808 address, and we will apply a 16-bit offset after loading it.
1809 If the symbol is local, the linker should provide enough local
1810 GOT entries for a 16-bit offset, but larger offsets may lead
1812 return SMALL_INT (offset);
1816 /* There is no carry between the HI and LO REL relocations, so the
1817 offset is only valid if we know it won't lead to such a carry. */
1818 return mips_offset_within_alignment_p (x, INTVAL (offset));
1820 case SYMBOL_GOT_DISP:
1821 case SYMBOL_GOTOFF_DISP:
1822 case SYMBOL_GOTOFF_CALL:
1823 case SYMBOL_GOTOFF_LOADGP:
1826 case SYMBOL_GOTTPREL:
1834 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1835 single instruction. We rely on the fact that, in the worst case,
1836 all instructions involved in a MIPS16 address calculation are usually
1840 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1844 case SYMBOL_ABSOLUTE:
1845 /* When using 64-bit symbols, we need 5 preparatory instructions,
1848 lui $at,%highest(symbol)
1849 daddiu $at,$at,%higher(symbol)
1851 daddiu $at,$at,%hi(symbol)
1854 The final address is then $at + %lo(symbol). With 32-bit
1855 symbols we just need a preparatory LUI for normal mode and
1856 a preparatory LI and SLL for MIPS16. */
1857 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1859 case SYMBOL_GP_RELATIVE:
1860 /* Treat GP-relative accesses as taking a single instruction on
1861 MIPS16 too; the copy of $gp can often be shared. */
1864 case SYMBOL_PC_RELATIVE:
1865 /* PC-relative constants can be only be used with ADDIUPC,
1866 DADDIUPC, LWPC and LDPC. */
1867 if (mode == MAX_MACHINE_MODE
1868 || GET_MODE_SIZE (mode) == 4
1869 || GET_MODE_SIZE (mode) == 8)
1872 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1875 case SYMBOL_FORCE_TO_MEM:
1876 /* LEAs will be converted into constant-pool references by
1878 if (mode == MAX_MACHINE_MODE)
1881 /* The constant must be loaded and then dereferenced. */
1884 case SYMBOL_GOT_DISP:
1885 /* The constant will have to be loaded from the GOT before it
1886 is used in an address. */
1887 if (mode != MAX_MACHINE_MODE)
1892 case SYMBOL_GOT_PAGE_OFST:
1893 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1894 local/global classification is accurate. The worst cases are:
1896 (1) For local symbols when generating o32 or o64 code. The assembler
1902 ...and the final address will be $at + %lo(symbol).
1904 (2) For global symbols when -mxgot. The assembler will use:
1906 lui $at,%got_hi(symbol)
1909 ...and the final address will be $at + %got_lo(symbol). */
1912 case SYMBOL_GOTOFF_PAGE:
1913 case SYMBOL_GOTOFF_DISP:
1914 case SYMBOL_GOTOFF_CALL:
1915 case SYMBOL_GOTOFF_LOADGP:
1916 case SYMBOL_32_HIGH:
1917 case SYMBOL_64_HIGH:
1923 case SYMBOL_GOTTPREL:
1926 /* A 16-bit constant formed by a single relocation, or a 32-bit
1927 constant formed from a high 16-bit relocation and a low 16-bit
1928 relocation. Use mips_split_p to determine which. 32-bit
1929 constants need an "lui; addiu" sequence for normal mode and
1930 an "li; sll; addiu" sequence for MIPS16 mode. */
1931 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1934 /* We don't treat a bare TLS symbol as a constant. */
1940 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1941 to load symbols of type TYPE into a register. Return 0 if the given
1942 type of symbol cannot be used as an immediate operand.
1944 Otherwise, return the number of instructions needed to load or store
1945 values of mode MODE to or from addresses of type TYPE. Return 0 if
1946 the given type of symbol is not valid in addresses.
1948 In both cases, treat extended MIPS16 instructions as two instructions. */
1951 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1953 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1956 /* A for_each_rtx callback. Stop the search if *X references a
1957 thread-local symbol. */
1960 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1962 return mips_tls_symbol_p (*x);
1965 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1968 mips_cannot_force_const_mem (rtx x)
1970 enum mips_symbol_type type;
1973 /* There is no assembler syntax for expressing an address-sized
1975 if (GET_CODE (x) == HIGH)
1978 /* As an optimization, reject constants that mips_legitimize_move
1981 Suppose we have a multi-instruction sequence that loads constant C
1982 into register R. If R does not get allocated a hard register, and
1983 R is used in an operand that allows both registers and memory
1984 references, reload will consider forcing C into memory and using
1985 one of the instruction's memory alternatives. Returning false
1986 here will force it to use an input reload instead. */
1987 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
1990 split_const (x, &base, &offset);
1991 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1992 && type != SYMBOL_FORCE_TO_MEM)
1994 /* The same optimization as for CONST_INT. */
1995 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1998 /* If MIPS16 constant pools live in the text section, they should
1999 not refer to anything that might need run-time relocation. */
2000 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2004 /* TLS symbols must be computed by mips_legitimize_move. */
2005 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2011 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2012 constants when we're using a per-function constant pool. */
2015 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2016 const_rtx x ATTRIBUTE_UNUSED)
2018 return !TARGET_MIPS16_PCREL_LOADS;
2021 /* Return true if register REGNO is a valid base register for mode MODE.
2022 STRICT_P is true if REG_OK_STRICT is in effect. */
2025 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2028 if (!HARD_REGISTER_NUM_P (regno))
2032 regno = reg_renumber[regno];
2035 /* These fake registers will be eliminated to either the stack or
2036 hard frame pointer, both of which are usually valid base registers.
2037 Reload deals with the cases where the eliminated form isn't valid. */
2038 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2041 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2042 values, nothing smaller. There are two problems here:
2044 (a) Instantiating virtual registers can introduce new uses of the
2045 stack pointer. If these virtual registers are valid addresses,
2046 the stack pointer should be too.
2048 (b) Most uses of the stack pointer are not made explicit until
2049 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2050 We don't know until that stage whether we'll be eliminating to the
2051 stack pointer (which needs the restriction) or the hard frame
2052 pointer (which doesn't).
2054 All in all, it seems more consistent to only enforce this restriction
2055 during and after reload. */
2056 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2057 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2059 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2062 /* Return true if X is a valid base register for mode MODE.
2063 STRICT_P is true if REG_OK_STRICT is in effect. */
2066 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2068 if (!strict_p && GET_CODE (x) == SUBREG)
2072 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2075 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2076 can address a value of mode MODE. */
2079 mips_valid_offset_p (rtx x, enum machine_mode mode)
2081 /* Check that X is a signed 16-bit number. */
2082 if (!const_arith_operand (x, Pmode))
2085 /* We may need to split multiword moves, so make sure that every word
2087 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2088 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2094 /* Return true if a LO_SUM can address a value of mode MODE when the
2095 LO_SUM symbol has type SYMBOL_TYPE. */
2098 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2100 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2102 if (mips_symbol_insns (symbol_type, mode) == 0)
2105 /* Check that there is a known low-part relocation. */
2106 if (mips_lo_relocs[symbol_type] == NULL)
2109 /* We may need to split multiword moves, so make sure that each word
2110 can be accessed without inducing a carry. This is mainly needed
2111 for o64, which has historically only guaranteed 64-bit alignment
2112 for 128-bit types. */
2113 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2114 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2120 /* Return true if X is a valid address for machine mode MODE. If it is,
2121 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2125 mips_classify_address (struct mips_address_info *info, rtx x,
2126 enum machine_mode mode, bool strict_p)
2128 switch (GET_CODE (x))
2132 info->type = ADDRESS_REG;
2134 info->offset = const0_rtx;
2135 return mips_valid_base_register_p (info->reg, mode, strict_p);
2138 info->type = ADDRESS_REG;
2139 info->reg = XEXP (x, 0);
2140 info->offset = XEXP (x, 1);
2141 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2142 && mips_valid_offset_p (info->offset, mode));
2145 info->type = ADDRESS_LO_SUM;
2146 info->reg = XEXP (x, 0);
2147 info->offset = XEXP (x, 1);
2148 /* We have to trust the creator of the LO_SUM to do something vaguely
2149 sane. Target-independent code that creates a LO_SUM should also
2150 create and verify the matching HIGH. Target-independent code that
2151 adds an offset to a LO_SUM must prove that the offset will not
2152 induce a carry. Failure to do either of these things would be
2153 a bug, and we are not required to check for it here. The MIPS
2154 backend itself should only create LO_SUMs for valid symbolic
2155 constants, with the high part being either a HIGH or a copy
2158 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2159 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2160 && mips_valid_lo_sum_p (info->symbol_type, mode));
2163 /* Small-integer addresses don't occur very often, but they
2164 are legitimate if $0 is a valid base register. */
2165 info->type = ADDRESS_CONST_INT;
2166 return !TARGET_MIPS16 && SMALL_INT (x);
2171 info->type = ADDRESS_SYMBOLIC;
2172 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2174 && mips_symbol_insns (info->symbol_type, mode) > 0
2175 && !mips_split_p[info->symbol_type]);
2182 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2185 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2187 struct mips_address_info addr;
2189 return mips_classify_address (&addr, x, mode, strict_p);
2192 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2195 mips_stack_address_p (rtx x, enum machine_mode mode)
2197 struct mips_address_info addr;
2199 return (mips_classify_address (&addr, x, mode, false)
2200 && addr.type == ADDRESS_REG
2201 && addr.reg == stack_pointer_rtx);
2204 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2205 address instruction. Note that such addresses are not considered
2206 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2207 is so restricted. */
2210 mips_lwxs_address_p (rtx addr)
2213 && GET_CODE (addr) == PLUS
2214 && REG_P (XEXP (addr, 1)))
2216 rtx offset = XEXP (addr, 0);
2217 if (GET_CODE (offset) == MULT
2218 && REG_P (XEXP (offset, 0))
2219 && CONST_INT_P (XEXP (offset, 1))
2220 && INTVAL (XEXP (offset, 1)) == 4)
2226 /* Return true if a value at OFFSET bytes from base register BASE can be
2227 accessed using an unextended MIPS16 instruction. MODE is the mode of
2230 Usually the offset in an unextended instruction is a 5-bit field.
2231 The offset is unsigned and shifted left once for LH and SH, twice
2232 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2233 an 8-bit immediate field that's shifted left twice. */
2236 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2237 unsigned HOST_WIDE_INT offset)
2239 if (offset % GET_MODE_SIZE (mode) == 0)
2241 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2242 return offset < 256U * GET_MODE_SIZE (mode);
2243 return offset < 32U * GET_MODE_SIZE (mode);
2248 /* Return the number of instructions needed to load or store a value
2249 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2250 Assume that multiword moves may need to be split into word moves
2251 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2254 For MIPS16 code, count extended instructions as two instructions. */
2257 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2259 struct mips_address_info addr;
2262 /* BLKmode is used for single unaligned loads and stores and should
2263 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2264 meaningless, so we have to single it out as a special case one way
2266 if (mode != BLKmode && might_split_p)
2267 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2271 if (mips_classify_address (&addr, x, mode, false))
2276 && !mips16_unextended_reference_p (mode, addr.reg,
2277 UINTVAL (addr.offset)))
2281 case ADDRESS_LO_SUM:
2282 return TARGET_MIPS16 ? factor * 2 : factor;
2284 case ADDRESS_CONST_INT:
2287 case ADDRESS_SYMBOLIC:
2288 return factor * mips_symbol_insns (addr.symbol_type, mode);
2293 /* Return the number of instructions needed to load constant X.
2294 Return 0 if X isn't a valid constant. */
2297 mips_const_insns (rtx x)
2299 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2300 enum mips_symbol_type symbol_type;
2303 switch (GET_CODE (x))
2306 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2308 || !mips_split_p[symbol_type])
2311 /* This is simply an LUI for normal mode. It is an extended
2312 LI followed by an extended SLL for MIPS16. */
2313 return TARGET_MIPS16 ? 4 : 1;
2317 /* Unsigned 8-bit constants can be loaded using an unextended
2318 LI instruction. Unsigned 16-bit constants can be loaded
2319 using an extended LI. Negative constants must be loaded
2320 using LI and then negated. */
2321 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2322 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2323 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2324 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2327 return mips_build_integer (codes, INTVAL (x));
2331 /* Allow zeros for normal mode, where we can use $0. */
2332 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2338 /* See if we can refer to X directly. */
2339 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2340 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2342 /* Otherwise try splitting the constant into a base and offset.
2343 If the offset is a 16-bit value, we can load the base address
2344 into a register and then use (D)ADDIU to add in the offset.
2345 If the offset is larger, we can load the base and offset
2346 into separate registers and add them together with (D)ADDU.
2347 However, the latter is only possible before reload; during
2348 and after reload, we must have the option of forcing the
2349 constant into the pool instead. */
2350 split_const (x, &x, &offset);
2353 int n = mips_const_insns (x);
2356 if (SMALL_INT (offset))
2358 else if (!targetm.cannot_force_const_mem (x))
2359 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2366 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2374 /* X is a doubleword constant that can be handled by splitting it into
2375 two words and loading each word separately. Return the number of
2376 instructions required to do this. */
2379 mips_split_const_insns (rtx x)
2381 unsigned int low, high;
2383 low = mips_const_insns (mips_subword (x, false));
2384 high = mips_const_insns (mips_subword (x, true));
2385 gcc_assert (low > 0 && high > 0);
2389 /* Return the number of instructions needed to implement INSN,
2390 given that it loads from or stores to MEM. Count extended
2391 MIPS16 instructions as two instructions. */
2394 mips_load_store_insns (rtx mem, rtx insn)
2396 enum machine_mode mode;
2400 gcc_assert (MEM_P (mem));
2401 mode = GET_MODE (mem);
2403 /* Try to prove that INSN does not need to be split. */
2404 might_split_p = true;
2405 if (GET_MODE_BITSIZE (mode) == 64)
2407 set = single_set (insn);
2408 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2409 might_split_p = false;
2412 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2415 /* Return the number of instructions needed for an integer division. */
2418 mips_idiv_insns (void)
2423 if (TARGET_CHECK_ZERO_DIV)
2425 if (GENERATE_DIVIDE_TRAPS)
2431 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2436 /* Emit a move from SRC to DEST. Assume that the move expanders can
2437 handle all moves if !can_create_pseudo_p (). The distinction is
2438 important because, unlike emit_move_insn, the move expanders know
2439 how to force Pmode objects into the constant pool even when the
2440 constant pool address is not itself legitimate. */
2443 mips_emit_move (rtx dest, rtx src)
2445 return (can_create_pseudo_p ()
2446 ? emit_move_insn (dest, src)
2447 : emit_move_insn_1 (dest, src));
2450 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2453 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2455 emit_insn (gen_rtx_SET (VOIDmode, target,
2456 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2459 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2460 Return that new register. */
2463 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2467 reg = gen_reg_rtx (mode);
2468 mips_emit_unary (code, reg, op0);
2472 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2475 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2477 emit_insn (gen_rtx_SET (VOIDmode, target,
2478 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2481 /* Compute (CODE OP0 OP1) and store the result in a new register
2482 of mode MODE. Return that new register. */
2485 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2489 reg = gen_reg_rtx (mode);
2490 mips_emit_binary (code, reg, op0, op1);
2494 /* Copy VALUE to a register and return that register. If new pseudos
2495 are allowed, copy it into a new register, otherwise use DEST. */
2498 mips_force_temporary (rtx dest, rtx value)
2500 if (can_create_pseudo_p ())
2501 return force_reg (Pmode, value);
2504 mips_emit_move (dest, value);
2509 /* Emit a call sequence with call pattern PATTERN and return the call
2510 instruction itself (which is not necessarily the last instruction
2511 emitted). ORIG_ADDR is the original, unlegitimized address,
2512 ADDR is the legitimized form, and LAZY_P is true if the call
2513 address is lazily-bound. */
2516 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2520 insn = emit_call_insn (pattern);
2522 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2524 /* MIPS16 JALRs only take MIPS16 registers. If the target
2525 function requires $25 to be valid on entry, we must copy it
2526 there separately. The move instruction can be put in the
2527 call's delay slot. */
2528 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2529 emit_insn_before (gen_move_insn (reg, addr), insn);
2530 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2534 /* Lazy-binding stubs require $gp to be valid on entry. */
2535 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2539 /* See the comment above load_call<mode> for details. */
2540 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2541 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2542 emit_insn (gen_update_got_version ());
2547 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2548 then add CONST_INT OFFSET to the result. */
2551 mips_unspec_address_offset (rtx base, rtx offset,
2552 enum mips_symbol_type symbol_type)
2554 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2555 UNSPEC_ADDRESS_FIRST + symbol_type);
2556 if (offset != const0_rtx)
2557 base = gen_rtx_PLUS (Pmode, base, offset);
2558 return gen_rtx_CONST (Pmode, base);
2561 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2562 type SYMBOL_TYPE. */
2565 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2569 split_const (address, &base, &offset);
2570 return mips_unspec_address_offset (base, offset, symbol_type);
2573 /* If OP is an UNSPEC address, return the address to which it refers,
2574 otherwise return OP itself. */
2577 mips_strip_unspec_address (rtx op)
2581 split_const (op, &base, &offset);
2582 if (UNSPEC_ADDRESS_P (base))
2583 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2587 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2588 high part to BASE and return the result. Just return BASE otherwise.
2589 TEMP is as for mips_force_temporary.
2591 The returned expression can be used as the first operand to a LO_SUM. */
2594 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2595 enum mips_symbol_type symbol_type)
2597 if (mips_split_p[symbol_type])
2599 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2600 addr = mips_force_temporary (temp, addr);
2601 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2606 /* Return an instruction that copies $gp into register REG. We want
2607 GCC to treat the register's value as constant, so that its value
2608 can be rematerialized on demand. */
2611 gen_load_const_gp (rtx reg)
2613 return (Pmode == SImode
2614 ? gen_load_const_gp_si (reg)
2615 : gen_load_const_gp_di (reg));
2618 /* Return a pseudo register that contains the value of $gp throughout
2619 the current function. Such registers are needed by MIPS16 functions,
2620 for which $gp itself is not a valid base register or addition operand. */
2623 mips16_gp_pseudo_reg (void)
2625 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2626 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2628 /* Don't emit an instruction to initialize the pseudo register if
2629 we are being called from the tree optimizers' cost-calculation
2631 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2632 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2636 push_topmost_sequence ();
2638 scan = get_insns ();
2639 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2640 scan = NEXT_INSN (scan);
2642 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2643 emit_insn_after (insn, scan);
2645 pop_topmost_sequence ();
2647 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2650 return cfun->machine->mips16_gp_pseudo_rtx;
2653 /* Return a base register that holds pic_offset_table_rtx.
2654 TEMP, if nonnull, is a scratch Pmode base register. */
2657 mips_pic_base_register (rtx temp)
2660 return pic_offset_table_rtx;
2662 if (can_create_pseudo_p ())
2663 return mips16_gp_pseudo_reg ();
2666 /* The first post-reload split exposes all references to $gp
2667 (both uses and definitions). All references must remain
2668 explicit after that point.
2670 It is safe to introduce uses of $gp at any time, so for
2671 simplicity, we do that before the split too. */
2672 mips_emit_move (temp, pic_offset_table_rtx);
2674 emit_insn (gen_load_const_gp (temp));
2678 /* Return the RHS of a load_call<mode> insn. */
2681 mips_unspec_call (rtx reg, rtx symbol)
2685 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2686 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2689 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2690 reference. Return NULL_RTX otherwise. */
2693 mips_strip_unspec_call (rtx src)
2695 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2696 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2700 /* Create and return a GOT reference of type TYPE for address ADDR.
2701 TEMP, if nonnull, is a scratch Pmode base register. */
2704 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2706 rtx base, high, lo_sum_symbol;
2708 base = mips_pic_base_register (temp);
2710 /* If we used the temporary register to load $gp, we can't use
2711 it for the high part as well. */
2712 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2715 high = mips_unspec_offset_high (temp, base, addr, type);
2716 lo_sum_symbol = mips_unspec_address (addr, type);
2718 if (type == SYMBOL_GOTOFF_CALL)
2719 return mips_unspec_call (high, lo_sum_symbol);
2721 return (Pmode == SImode
2722 ? gen_unspec_gotsi (high, lo_sum_symbol)
2723 : gen_unspec_gotdi (high, lo_sum_symbol));
2726 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2727 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2728 constant in that context and can be split into high and low parts.
2729 If so, and if LOW_OUT is nonnull, emit the high part and store the
2730 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2732 TEMP is as for mips_force_temporary and is used to load the high
2733 part into a register.
2735 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2736 a legitimize SET_SRC for an .md pattern, otherwise the low part
2737 is guaranteed to be a legitimate address for mode MODE. */
2740 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2742 enum mips_symbol_context context;
2743 enum mips_symbol_type symbol_type;
2746 context = (mode == MAX_MACHINE_MODE
2747 ? SYMBOL_CONTEXT_LEA
2748 : SYMBOL_CONTEXT_MEM);
2749 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2751 addr = XEXP (addr, 0);
2752 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2753 && mips_symbol_insns (symbol_type, mode) > 0
2754 && mips_split_hi_p[symbol_type])
2757 switch (symbol_type)
2759 case SYMBOL_GOT_PAGE_OFST:
2760 /* The high part of a page/ofst pair is loaded from the GOT. */
2761 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2772 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2773 && mips_symbol_insns (symbol_type, mode) > 0
2774 && mips_split_p[symbol_type])
2777 switch (symbol_type)
2779 case SYMBOL_GOT_DISP:
2780 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2781 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2784 case SYMBOL_GP_RELATIVE:
2785 high = mips_pic_base_register (temp);
2786 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2790 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2791 high = mips_force_temporary (temp, high);
2792 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2801 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2802 mips_force_temporary; it is only needed when OFFSET is not a
2806 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2808 if (!SMALL_OPERAND (offset))
2814 /* Load the full offset into a register so that we can use
2815 an unextended instruction for the address itself. */
2816 high = GEN_INT (offset);
2821 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2822 The addition inside the macro CONST_HIGH_PART may cause an
2823 overflow, so we need to force a sign-extension check. */
2824 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2825 offset = CONST_LOW_PART (offset);
2827 high = mips_force_temporary (temp, high);
2828 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2830 return plus_constant (reg, offset);
2833 /* The __tls_get_attr symbol. */
2834 static GTY(()) rtx mips_tls_symbol;
2836 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2837 the TLS symbol we are referencing and TYPE is the symbol type to use
2838 (either global dynamic or local dynamic). V0 is an RTX for the
2839 return value location. */
2842 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2846 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2848 if (!mips_tls_symbol)
2849 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2851 loc = mips_unspec_address (sym, type);
2855 emit_insn (gen_rtx_SET (Pmode, a0,
2856 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2857 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2858 const0_rtx, NULL_RTX, false);
2859 RTL_CONST_CALL_P (insn) = 1;
2860 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2861 insn = get_insns ();
2868 /* Return a pseudo register that contains the current thread pointer. */
2875 tp = gen_reg_rtx (Pmode);
2876 if (Pmode == DImode)
2877 emit_insn (gen_tls_get_tp_di (tp));
2879 emit_insn (gen_tls_get_tp_si (tp));
2883 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2884 its address. The return value will be both a valid address and a valid
2885 SET_SRC (either a REG or a LO_SUM). */
2888 mips_legitimize_tls_address (rtx loc)
2890 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2891 enum tls_model model;
2895 sorry ("MIPS16 TLS");
2896 return gen_reg_rtx (Pmode);
2899 model = SYMBOL_REF_TLS_MODEL (loc);
2900 /* Only TARGET_ABICALLS code can have more than one module; other
2901 code must be be static and should not use a GOT. All TLS models
2902 reduce to local exec in this situation. */
2903 if (!TARGET_ABICALLS)
2904 model = TLS_MODEL_LOCAL_EXEC;
2908 case TLS_MODEL_GLOBAL_DYNAMIC:
2909 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2910 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2911 dest = gen_reg_rtx (Pmode);
2912 emit_libcall_block (insn, dest, v0, loc);
2915 case TLS_MODEL_LOCAL_DYNAMIC:
2916 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2917 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2918 tmp1 = gen_reg_rtx (Pmode);
2920 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2921 share the LDM result with other LD model accesses. */
2922 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2924 emit_libcall_block (insn, tmp1, v0, eqv);
2926 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2927 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2928 mips_unspec_address (loc, SYMBOL_DTPREL));
2931 case TLS_MODEL_INITIAL_EXEC:
2932 tp = mips_get_tp ();
2933 tmp1 = gen_reg_rtx (Pmode);
2934 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2935 if (Pmode == DImode)
2936 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2938 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2939 dest = gen_reg_rtx (Pmode);
2940 emit_insn (gen_add3_insn (dest, tmp1, tp));
2943 case TLS_MODEL_LOCAL_EXEC:
2944 tp = mips_get_tp ();
2945 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2946 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2947 mips_unspec_address (loc, SYMBOL_TPREL));
2956 /* If X is not a valid address for mode MODE, force it into a register. */
2959 mips_force_address (rtx x, enum machine_mode mode)
2961 if (!mips_legitimate_address_p (mode, x, false))
2962 x = force_reg (Pmode, x);
2966 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2967 be legitimized in a way that the generic machinery might not expect,
2968 return a new address, otherwise return NULL. MODE is the mode of
2969 the memory being accessed. */
2972 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2973 enum machine_mode mode)
2976 HOST_WIDE_INT offset;
2978 if (mips_tls_symbol_p (x))
2979 return mips_legitimize_tls_address (x);
2981 /* See if the address can split into a high part and a LO_SUM. */
2982 if (mips_split_symbol (NULL, x, mode, &addr))
2983 return mips_force_address (addr, mode);
2985 /* Handle BASE + OFFSET using mips_add_offset. */
2986 mips_split_plus (x, &base, &offset);
2989 if (!mips_valid_base_register_p (base, mode, false))
2990 base = copy_to_mode_reg (Pmode, base);
2991 addr = mips_add_offset (NULL, base, offset);
2992 return mips_force_address (addr, mode);
2998 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3001 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3003 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3004 enum machine_mode mode;
3005 unsigned int i, num_ops;
3008 mode = GET_MODE (dest);
3009 num_ops = mips_build_integer (codes, value);
3011 /* Apply each binary operation to X. Invariant: X is a legitimate
3012 source operand for a SET pattern. */
3013 x = GEN_INT (codes[0].value);
3014 for (i = 1; i < num_ops; i++)
3016 if (!can_create_pseudo_p ())
3018 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3022 x = force_reg (mode, x);
3023 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3026 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3029 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3030 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3034 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3038 /* Split moves of big integers into smaller pieces. */
3039 if (splittable_const_int_operand (src, mode))
3041 mips_move_integer (dest, dest, INTVAL (src));
3045 /* Split moves of symbolic constants into high/low pairs. */
3046 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3048 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3052 /* Generate the appropriate access sequences for TLS symbols. */
3053 if (mips_tls_symbol_p (src))
3055 mips_emit_move (dest, mips_legitimize_tls_address (src));
3059 /* If we have (const (plus symbol offset)), and that expression cannot
3060 be forced into memory, load the symbol first and add in the offset.
3061 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3062 forced into memory, as it usually produces better code. */
3063 split_const (src, &base, &offset);
3064 if (offset != const0_rtx
3065 && (targetm.cannot_force_const_mem (src)
3066 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3068 base = mips_force_temporary (dest, base);
3069 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3073 src = force_const_mem (mode, src);
3075 /* When using explicit relocs, constant pool references are sometimes
3076 not legitimate addresses. */
3077 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3078 mips_emit_move (dest, src);
3081 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3082 sequence that is valid. */
3085 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3087 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3089 mips_emit_move (dest, force_reg (mode, src));
3093 /* We need to deal with constants that would be legitimate
3094 immediate_operands but aren't legitimate move_operands. */
3095 if (CONSTANT_P (src) && !move_operand (src, mode))
3097 mips_legitimize_const_move (mode, dest, src);
3098 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3104 /* Return true if value X in context CONTEXT is a small-data address
3105 that can be rewritten as a LO_SUM. */
3108 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3110 enum mips_symbol_type symbol_type;
3112 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3113 && !mips_split_p[SYMBOL_GP_RELATIVE]
3114 && mips_symbolic_constant_p (x, context, &symbol_type)
3115 && symbol_type == SYMBOL_GP_RELATIVE);
3118 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3119 containing MEM, or null if none. */
3122 mips_small_data_pattern_1 (rtx *loc, void *data)
3124 enum mips_symbol_context context;
3126 if (GET_CODE (*loc) == LO_SUM)
3131 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3136 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3137 return mips_rewrite_small_data_p (*loc, context);
3140 /* Return true if OP refers to small data symbols directly, not through
3144 mips_small_data_pattern_p (rtx op)
3146 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3149 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3150 DATA is the containing MEM, or null if none. */
3153 mips_rewrite_small_data_1 (rtx *loc, void *data)
3155 enum mips_symbol_context context;
3159 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3163 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3164 if (mips_rewrite_small_data_p (*loc, context))
3165 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3167 if (GET_CODE (*loc) == LO_SUM)
3173 /* Rewrite instruction pattern PATTERN so that it refers to small data
3174 using explicit relocations. */
3177 mips_rewrite_small_data (rtx pattern)
3179 pattern = copy_insn (pattern);
3180 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3184 /* We need a lot of little routines to check the range of MIPS16 immediate
3188 m16_check_op (rtx op, int low, int high, int mask)
3190 return (CONST_INT_P (op)
3191 && IN_RANGE (INTVAL (op), low, high)
3192 && (INTVAL (op) & mask) == 0);
3196 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3198 return m16_check_op (op, 0x1, 0x8, 0);
3202 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3204 return m16_check_op (op, -0x8, 0x7, 0);
3208 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3210 return m16_check_op (op, -0x7, 0x8, 0);
3214 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3216 return m16_check_op (op, -0x10, 0xf, 0);
3220 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3222 return m16_check_op (op, -0xf, 0x10, 0);
3226 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3228 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3232 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3234 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3238 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3240 return m16_check_op (op, -0x80, 0x7f, 0);
3244 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3246 return m16_check_op (op, -0x7f, 0x80, 0);
3250 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3252 return m16_check_op (op, 0x0, 0xff, 0);
3256 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3258 return m16_check_op (op, -0xff, 0x0, 0);
3262 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3264 return m16_check_op (op, -0x1, 0xfe, 0);
3268 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3270 return m16_check_op (op, 0x0, 0xff << 2, 3);
3274 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3276 return m16_check_op (op, -0xff << 2, 0x0, 3);
3280 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3282 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3286 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3288 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3291 /* The cost of loading values from the constant pool. It should be
3292 larger than the cost of any constant we want to synthesize inline. */
3293 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3295 /* Return the cost of X when used as an operand to the MIPS16 instruction
3296 that implements CODE. Return -1 if there is no such instruction, or if
3297 X is not a valid immediate operand for it. */
3300 mips16_constant_cost (int code, HOST_WIDE_INT x)
3307 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3308 other shifts are extended. The shift patterns truncate the shift
3309 count to the right size, so there are no out-of-range values. */
3310 if (IN_RANGE (x, 1, 8))
3312 return COSTS_N_INSNS (1);
3315 if (IN_RANGE (x, -128, 127))
3317 if (SMALL_OPERAND (x))
3318 return COSTS_N_INSNS (1);
3322 /* Like LE, but reject the always-true case. */
3326 /* We add 1 to the immediate and use SLT. */
3329 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3332 if (IN_RANGE (x, 0, 255))
3334 if (SMALL_OPERAND_UNSIGNED (x))
3335 return COSTS_N_INSNS (1);
3340 /* Equality comparisons with 0 are cheap. */
3350 /* Return true if there is a non-MIPS16 instruction that implements CODE
3351 and if that instruction accepts X as an immediate operand. */
3354 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3361 /* All shift counts are truncated to a valid constant. */
3366 /* Likewise rotates, if the target supports rotates at all. */
3372 /* These instructions take 16-bit unsigned immediates. */
3373 return SMALL_OPERAND_UNSIGNED (x);
3378 /* These instructions take 16-bit signed immediates. */
3379 return SMALL_OPERAND (x);
3385 /* The "immediate" forms of these instructions are really
3386 implemented as comparisons with register 0. */
3391 /* Likewise, meaning that the only valid immediate operand is 1. */
3395 /* We add 1 to the immediate and use SLT. */
3396 return SMALL_OPERAND (x + 1);
3399 /* Likewise SLTU, but reject the always-true case. */
3400 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3404 /* The bit position and size are immediate operands. */
3405 return ISA_HAS_EXT_INS;
3408 /* By default assume that $0 can be used for 0. */
3413 /* Return the cost of binary operation X, given that the instruction
3414 sequence for a word-sized or smaller operation has cost SINGLE_COST
3415 and that the sequence of a double-word operation has cost DOUBLE_COST.
3416 If SPEED is true, optimize for speed otherwise optimize for size. */
3419 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3423 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3428 + rtx_cost (XEXP (x, 0), SET, speed)
3429 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3432 /* Return the cost of floating-point multiplications of mode MODE. */
3435 mips_fp_mult_cost (enum machine_mode mode)
3437 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3440 /* Return the cost of floating-point divisions of mode MODE. */
3443 mips_fp_div_cost (enum machine_mode mode)
3445 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3448 /* Return the cost of sign-extending OP to mode MODE, not including the
3449 cost of OP itself. */
3452 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3455 /* Extended loads are as cheap as unextended ones. */
3458 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3459 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3462 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3463 /* We can use SEB or SEH. */
3464 return COSTS_N_INSNS (1);
3466 /* We need to use a shift left and a shift right. */
3467 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3470 /* Return the cost of zero-extending OP to mode MODE, not including the
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