1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
62 #define STAB_CODE_TYPE enum __stab_debug_code
64 #define STAB_CODE_TYPE int
67 extern tree lookup_name PARAMS ((tree));
69 /* Enumeration for all of the relational tests, so that we can build
70 arrays indexed by the test type, and not worry about the order
90 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
91 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
93 int coprocessor_operand PARAMS ((rtx,
95 int coprocessor2_operand PARAMS ((rtx,
97 static int m16_check_op PARAMS ((rtx, int, int, int));
98 static void block_move_loop PARAMS ((rtx, rtx,
102 static void block_move_call PARAMS ((rtx, rtx, rtx));
103 static void mips_arg_info PARAMS ((const CUMULATIVE_ARGS *,
106 struct mips_arg_info *));
107 static rtx mips_add_large_offset_to_sp PARAMS ((HOST_WIDE_INT));
108 static void mips_annotate_frame_insn PARAMS ((rtx, rtx));
109 static rtx mips_frame_set PARAMS ((enum machine_mode,
111 static void mips_emit_frame_related_store PARAMS ((rtx, rtx,
113 static void save_restore_insns PARAMS ((int, rtx, long));
114 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
115 static void mips16_fp_args PARAMS ((FILE *, int, int));
116 static void build_mips16_function_stub PARAMS ((FILE *));
117 static void mips16_optimize_gp PARAMS ((rtx));
118 static rtx add_constant PARAMS ((struct constant **,
121 static void dump_constants PARAMS ((struct constant *,
123 static rtx mips_find_symbol PARAMS ((rtx));
124 static void abort_with_insn PARAMS ((rtx, const char *))
126 static int symbolic_expression_p PARAMS ((rtx));
127 static void mips_add_gc_roots PARAMS ((void));
128 static bool mips_assemble_integer PARAMS ((rtx, unsigned int, int));
129 static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
130 static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
131 static enum processor_type mips_parse_cpu PARAMS ((const char *));
132 static void copy_file_data PARAMS ((FILE *, FILE *));
134 static void iris6_asm_named_section_1 PARAMS ((const char *,
137 static void iris6_asm_named_section PARAMS ((const char *,
139 static int iris_section_align_entry_eq PARAMS ((const PTR, const PTR));
140 static hashval_t iris_section_align_entry_hash PARAMS ((const PTR));
141 static int iris6_section_align_1 PARAMS ((void **, void *));
143 static int mips_adjust_cost PARAMS ((rtx, rtx, rtx, int));
144 static int mips_issue_rate PARAMS ((void));
146 static void mips_init_machine_status PARAMS ((struct function *));
147 static void mips_free_machine_status PARAMS ((struct function *));
148 static void mips_mark_machine_status PARAMS ((struct function *));
149 static void mips_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
151 static void mips_unique_section PARAMS ((tree, int))
153 static void mips_select_rtx_section PARAMS ((enum machine_mode, rtx,
154 unsigned HOST_WIDE_INT));
157 struct machine_function {
158 /* Pseudo-reg holding the address of the current function when
159 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS,
160 used by mips_finalize_pic if it was created. */
161 rtx embedded_pic_fnaddr_rtx;
163 /* Pseudo-reg holding the value of $28 in a mips16 function which
164 refers to GP relative global variables. */
165 rtx mips16_gp_pseudo_rtx;
168 /* Information about a single argument. */
171 /* True if the argument is a record or union type. */
174 /* True if the argument is passed in a floating-point register, or
175 would have been if we hadn't run out of registers. */
178 /* The argument's size, in bytes. */
179 unsigned int num_bytes;
181 /* The number of words passed in registers, rounded up. */
182 unsigned int reg_words;
184 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
185 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
187 unsigned int reg_offset;
189 /* The number of words that must be passed on the stack, rounded up. */
190 unsigned int stack_words;
192 /* The offset from the start of the stack overflow area of the argument's
193 first stack word. Only meaningful when STACK_WORDS is non-zero. */
194 unsigned int stack_offset;
197 /* Global variables for machine-dependent things. */
199 /* Threshold for data being put into the small data/bss area, instead
200 of the normal data area (references to the small data/bss area take
201 1 instruction, and use the global pointer, references to the normal
202 data area takes 2 instructions). */
203 int mips_section_threshold = -1;
205 /* Count the number of .file directives, so that .loc is up to date. */
206 int num_source_filenames = 0;
208 /* Count the number of sdb related labels are generated (to find block
209 start and end boundaries). */
210 int sdb_label_count = 0;
212 /* Next label # for each statement for Silicon Graphics IRIS systems. */
215 /* Non-zero if inside of a function, because the stupid MIPS asm can't
216 handle .files inside of functions. */
217 int inside_function = 0;
219 /* Files to separate the text and the data output, so that all of the data
220 can be emitted before the text, which will mean that the assembler will
221 generate smaller code, based on the global pointer. */
222 FILE *asm_out_data_file;
223 FILE *asm_out_text_file;
225 /* Linked list of all externals that are to be emitted when optimizing
226 for the global pointer if they haven't been declared by the end of
227 the program with an appropriate .comm or initialization. */
231 struct extern_list *next; /* next external */
232 const char *name; /* name of the external */
233 int size; /* size in bytes */
236 /* Name of the file containing the current function. */
237 const char *current_function_file = "";
239 /* Warning given that Mips ECOFF can't support changing files
240 within a function. */
241 int file_in_function_warning = FALSE;
243 /* Whether to suppress issuing .loc's because the user attempted
244 to change the filename within a function. */
245 int ignore_line_number = FALSE;
247 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
253 /* The next branch instruction is a branch likely, not branch normal. */
254 int mips_branch_likely;
256 /* Count of delay slots and how many are filled. */
257 int dslots_load_total;
258 int dslots_load_filled;
259 int dslots_jump_total;
260 int dslots_jump_filled;
262 /* # of nops needed by previous insn */
263 int dslots_number_nops;
265 /* Number of 1/2/3 word references to data items (ie, not jal's). */
268 /* registers to check for load delay */
269 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
271 /* Cached operands, and operator to compare for use in set/branch/trap
272 on condition codes. */
275 /* what type of branch to use */
276 enum cmp_type branch_type;
278 /* Number of previously seen half-pic pointers and references. */
279 static int prev_half_pic_ptrs = 0;
280 static int prev_half_pic_refs = 0;
282 /* The target cpu for code generation. */
283 enum processor_type mips_arch;
285 /* The target cpu for optimization and scheduling. */
286 enum processor_type mips_tune;
288 /* which instruction set architecture to use. */
291 /* which abi to use. */
294 /* Strings to hold which cpu and instruction set architecture to use. */
295 const char *mips_cpu_string; /* for -mcpu=<xxx> */
296 const char *mips_arch_string; /* for -march=<xxx> */
297 const char *mips_tune_string; /* for -mtune=<xxx> */
298 const char *mips_isa_string; /* for -mips{1,2,3,4} */
299 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
301 /* Whether we are generating mips16 code. This is a synonym for
302 TARGET_MIPS16, and exists for use as an attribute. */
305 /* This variable is set by -mno-mips16. We only care whether
306 -mno-mips16 appears or not, and using a string in this fashion is
307 just a way to avoid using up another bit in target_flags. */
308 const char *mips_no_mips16_string;
310 /* This is only used to determine if an type size setting option was
311 explicitly specified (-mlong64, -mint64, -mlong32). The specs
312 set this option if such an option is used. */
313 const char *mips_explicit_type_size_string;
315 /* Whether we are generating mips16 hard float code. In mips16 mode
316 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
317 -msoft-float was not specified by the user, which means that we
318 should arrange to call mips32 hard floating point code. */
319 int mips16_hard_float;
321 /* This variable is set by -mentry. We only care whether -mentry
322 appears or not, and using a string in this fashion is just a way to
323 avoid using up another bit in target_flags. */
324 const char *mips_entry_string;
326 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
328 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
331 /* If TRUE, we split addresses into their high and low parts in the RTL. */
332 int mips_split_addresses;
334 /* Generating calls to position independent functions? */
335 enum mips_abicalls_type mips_abicalls;
337 /* High and low marks for floating point values which we will accept
338 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
339 initialized in override_options. */
340 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
342 /* Mode used for saving/restoring general purpose registers. */
343 static enum machine_mode gpr_mode;
345 /* Array giving truth value on whether or not a given hard register
346 can support a given mode. */
347 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
349 /* Current frame information calculated by compute_frame_size. */
350 struct mips_frame_info current_frame_info;
352 /* Zero structure to initialize current_frame_info. */
353 struct mips_frame_info zero_frame_info;
355 /* The length of all strings seen when compiling for the mips16. This
356 is used to tell how many strings are in the constant pool, so that
357 we can see if we may have an overflow. This is reset each time the
358 constant pool is output. */
359 int mips_string_length;
361 /* In mips16 mode, we build a list of all the string constants we see
362 in a particular function. */
364 struct string_constant
366 struct string_constant *next;
370 static struct string_constant *string_constants;
372 /* List of all MIPS punctuation characters used by print_operand. */
373 char mips_print_operand_punct[256];
375 /* Map GCC register number to debugger register number. */
376 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
378 /* Buffer to use to enclose a load/store operation with %{ %} to
379 turn on .set volatile. */
380 static char volatile_buffer[60];
382 /* Hardware names for the registers. If -mrnames is used, this
383 will be overwritten with mips_sw_reg_names. */
385 char mips_reg_names[][8] =
387 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
388 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
389 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
390 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
391 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
392 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
393 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
394 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
395 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
396 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
397 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
398 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
399 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
400 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
401 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
402 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
403 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
404 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
405 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
406 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
407 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
408 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
411 /* Mips software names for the registers, used to overwrite the
412 mips_reg_names array. */
414 char mips_sw_reg_names[][8] =
416 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
417 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
418 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
419 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
420 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
421 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
422 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
423 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
424 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
425 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
426 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
427 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
428 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
429 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
430 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
431 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
432 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
433 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
434 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
435 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
436 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
437 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
440 /* Map hard register number to register class */
441 const enum reg_class mips_regno_to_class[] =
443 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
444 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
445 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
446 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
447 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
448 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
449 T_REG, GR_REGS, GR_REGS, GR_REGS,
450 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
451 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
452 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
453 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
454 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
455 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
456 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
457 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
458 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
459 HI_REG, LO_REG, HILO_REG, ST_REGS,
460 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
461 ST_REGS, ST_REGS, ST_REGS, GR_REGS,
462 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
463 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
464 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
465 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
466 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
467 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
468 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
469 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
470 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
471 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
472 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
473 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
474 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
475 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
476 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
477 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
478 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
479 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
480 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
481 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
482 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
483 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
484 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
485 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
486 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
489 /* Map register constraint character to register class. */
490 enum reg_class mips_char_to_class[256] =
492 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
493 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
494 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
495 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
496 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
497 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
498 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
499 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
500 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
501 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
502 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
503 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
504 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
505 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
506 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
507 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
508 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
509 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
510 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
511 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
512 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
513 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
514 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
515 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
516 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
517 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
518 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
519 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
520 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
521 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
522 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
523 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
524 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
525 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
526 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
527 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
528 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
529 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
530 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
531 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
532 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
533 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
534 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
535 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
536 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
537 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
538 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
539 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
540 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
541 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
542 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
543 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
544 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
545 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
546 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
547 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
548 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
549 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
550 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
551 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
552 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
553 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
554 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
555 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
558 /* Initialize the GCC target structure. */
559 #undef TARGET_ASM_ALIGNED_HI_OP
560 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
561 #undef TARGET_ASM_ALIGNED_SI_OP
562 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
563 #undef TARGET_ASM_INTEGER
564 #define TARGET_ASM_INTEGER mips_assemble_integer
566 #if TARGET_IRIX5 && !TARGET_IRIX6
567 #undef TARGET_ASM_UNALIGNED_HI_OP
568 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
569 #undef TARGET_ASM_UNALIGNED_SI_OP
570 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
573 #undef TARGET_ASM_FUNCTION_PROLOGUE
574 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
575 #undef TARGET_ASM_FUNCTION_EPILOGUE
576 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
577 #undef TARGET_ASM_SELECT_RTX_SECTION
578 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
580 #undef TARGET_SCHED_ADJUST_COST
581 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
583 #undef TARGET_SCHED_ISSUE_RATE
584 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
586 struct gcc_target targetm = TARGET_INITIALIZER;
588 /* Return truth value of whether OP can be used as an operands
589 where a register or 16 bit unsigned integer is needed. */
592 uns_arith_operand (op, mode)
594 enum machine_mode mode;
596 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
599 return register_operand (op, mode);
602 /* Return truth value of whether OP can be used as an operands
603 where a 16 bit integer is needed */
606 arith_operand (op, mode)
608 enum machine_mode mode;
610 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
613 /* On the mips16, a GP relative value is a signed 16 bit offset. */
614 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
617 return register_operand (op, mode);
620 /* Return truth value of whether OP can be used as an operand in a two
621 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
624 arith32_operand (op, mode)
626 enum machine_mode mode;
628 if (GET_CODE (op) == CONST_INT)
631 return register_operand (op, mode);
634 /* Return truth value of whether OP is an integer which fits in 16 bits. */
639 enum machine_mode mode ATTRIBUTE_UNUSED;
641 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
644 /* Return truth value of whether OP is a 32 bit integer which is too big to
645 be loaded with one instruction. */
650 enum machine_mode mode ATTRIBUTE_UNUSED;
654 if (GET_CODE (op) != CONST_INT)
659 /* ior reg,$r0,value */
660 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
663 /* subu reg,$r0,value */
664 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
667 /* lui reg,value>>16 */
668 if ((value & 0x0000ffff) == 0)
674 /* Return truth value of whether OP is a register or the constant 0.
675 In mips16 mode, we only accept a register, since the mips16 does
679 reg_or_0_operand (op, mode)
681 enum machine_mode mode;
683 switch (GET_CODE (op))
688 return INTVAL (op) == 0;
693 return op == CONST0_RTX (mode);
697 return register_operand (op, mode);
706 /* Return truth value of whether OP is a register or the constant 0,
707 even in mips16 mode. */
710 true_reg_or_0_operand (op, mode)
712 enum machine_mode mode;
714 switch (GET_CODE (op))
717 return INTVAL (op) == 0;
720 return op == CONST0_RTX (mode);
724 return register_operand (op, mode);
733 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
736 mips_const_double_ok (op, mode)
738 enum machine_mode mode;
742 if (GET_CODE (op) != CONST_DOUBLE)
745 if (mode == VOIDmode)
748 if (mode != SFmode && mode != DFmode)
751 if (op == CONST0_RTX (mode))
754 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
755 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
758 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
760 if (REAL_VALUE_ISNAN (d))
763 if (REAL_VALUE_NEGATIVE (d))
764 d = REAL_VALUE_NEGATE (d);
768 if (REAL_VALUES_LESS (d, dfhigh)
769 && REAL_VALUES_LESS (dflow, d))
774 if (REAL_VALUES_LESS (d, sfhigh)
775 && REAL_VALUES_LESS (sflow, d))
782 /* Accept the floating point constant 1 in the appropriate mode. */
785 const_float_1_operand (op, mode)
787 enum machine_mode mode;
790 static REAL_VALUE_TYPE onedf;
791 static REAL_VALUE_TYPE onesf;
792 static int one_initialized;
794 if (GET_CODE (op) != CONST_DOUBLE
795 || mode != GET_MODE (op)
796 || (mode != DFmode && mode != SFmode))
799 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
801 /* We only initialize these values if we need them, since we will
802 never get called unless mips_isa >= 4. */
803 if (! one_initialized)
805 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
806 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
811 return REAL_VALUES_EQUAL (d, onedf);
813 return REAL_VALUES_EQUAL (d, onesf);
816 /* Return true if a memory load or store of REG plus OFFSET in MODE
817 can be represented in a single word on the mips16. */
820 mips16_simple_memory_operand (reg, offset, mode)
823 enum machine_mode mode;
830 /* We can't tell, because we don't know how the value will
831 eventually be accessed. Returning 0 here does no great
832 harm; it just prevents some possible instruction scheduling. */
836 size = GET_MODE_SIZE (mode);
838 if (INTVAL (offset) % size != 0)
840 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
844 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
849 /* Return truth value if a memory operand fits in a single instruction
850 (ie, register + small offset). */
853 simple_memory_operand (op, mode)
855 enum machine_mode mode;
857 rtx addr, plus0, plus1;
859 /* Eliminate non-memory operations */
860 if (GET_CODE (op) != MEM)
863 /* dword operations really put out 2 instructions, so eliminate them. */
864 /* ??? This isn't strictly correct. It is OK to accept multiword modes
865 here, since the length attributes are being set correctly, but only
866 if the address is offsettable. LO_SUM is not offsettable. */
867 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
870 /* Decode the address now. */
872 switch (GET_CODE (addr))
881 return SMALL_INT (addr);
884 plus0 = XEXP (addr, 0);
885 plus1 = XEXP (addr, 1);
886 if (GET_CODE (plus0) == REG
887 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
889 || mips16_simple_memory_operand (plus0, plus1, mode)))
892 else if (GET_CODE (plus1) == REG
893 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
895 || mips16_simple_memory_operand (plus1, plus0, mode)))
902 /* We used to allow small symbol refs here (ie, stuff in .sdata
903 or .sbss), but this causes some bugs in G++. Also, it won't
904 interfere if the MIPS linker rewrites the store instruction
905 because the function is PIC. */
907 case LABEL_REF: /* never gp relative */
911 /* If -G 0, we can never have a GP relative memory operation.
912 Also, save some time if not optimizing. */
917 rtx offset = const0_rtx;
918 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
919 if (GET_CODE (op) != SYMBOL_REF)
922 /* let's be paranoid.... */
923 if (! SMALL_INT (offset))
930 return SYMBOL_REF_FLAG (addr);
933 /* This SYMBOL_REF case is for the mips16. If the above case is
934 reenabled, this one should be merged in. */
936 /* References to the constant pool on the mips16 use a small
937 offset if the function is small. The only time we care about
938 getting this right is during delayed branch scheduling, so
939 don't need to check until then. The machine_dependent_reorg
940 function will set the total length of the instructions used
941 in the function in current_frame_info. If that is small
942 enough, we know for sure that this is a small offset. It
943 would be better if we could take into account the location of
944 the instruction within the function, but we can't, because we
945 don't know where we are. */
947 && CONSTANT_POOL_ADDRESS_P (addr)
948 && current_frame_info.insns_len > 0)
952 size = current_frame_info.insns_len + get_pool_size ();
953 if (GET_MODE_SIZE (mode) == 4)
954 return size < 4 * 0x100;
955 else if (GET_MODE_SIZE (mode) == 8)
956 return size < 8 * 0x20;
970 /* Return nonzero for a memory address that can be used to load or store
974 double_memory_operand (op, mode)
976 enum machine_mode mode;
978 if (GET_CODE (op) != MEM
979 || ! memory_operand (op, mode))
981 /* During reload, we accept a pseudo register if it has an
982 appropriate memory address. If we don't do this, we will
983 wind up reloading into a register, and then reloading that
984 register from memory, when we could just reload directly from
986 if (reload_in_progress
987 && GET_CODE (op) == REG
988 && REGNO (op) >= FIRST_PSEUDO_REGISTER
989 && reg_renumber[REGNO (op)] < 0
990 && reg_equiv_mem[REGNO (op)] != 0
991 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
994 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
995 the same test performed for 'm' in find_reloads. */
997 if (reload_in_progress
999 && (GET_CODE (op) == MEM
1000 || (GET_CODE (op) == REG
1001 && REGNO (op) >= FIRST_PSEUDO_REGISTER
1002 && reg_renumber[REGNO (op)] < 0)))
1005 if (reload_in_progress
1007 && GET_CODE (op) == MEM)
1011 addr = XEXP (op, 0);
1013 /* During reload on the mips16, we accept a large offset
1014 from the frame pointer or the stack pointer. This large
1015 address will get reloaded anyhow. */
1016 if (GET_CODE (addr) == PLUS
1017 && GET_CODE (XEXP (addr, 0)) == REG
1018 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1019 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
1020 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
1021 && ! SMALL_INT (XEXP (addr, 1)))
1022 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
1023 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
1026 /* Similarly, we accept a case where the memory address is
1027 itself on the stack, and will be reloaded. */
1028 if (GET_CODE (addr) == MEM)
1032 maddr = XEXP (addr, 0);
1033 if (GET_CODE (maddr) == PLUS
1034 && GET_CODE (XEXP (maddr, 0)) == REG
1035 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1036 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
1037 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
1038 && ! SMALL_INT (XEXP (maddr, 1)))
1039 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
1040 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
1044 /* We also accept the same case when we have a 16 bit signed
1045 offset mixed in as well. The large address will get
1046 reloaded, and the 16 bit offset will be OK. */
1047 if (GET_CODE (addr) == PLUS
1048 && GET_CODE (XEXP (addr, 0)) == MEM
1049 && GET_CODE (XEXP (addr, 1)) == CONST_INT
1050 && SMALL_INT (XEXP (addr, 1)))
1052 addr = XEXP (XEXP (addr, 0), 0);
1053 if (GET_CODE (addr) == PLUS
1054 && GET_CODE (XEXP (addr, 0)) == REG
1055 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1056 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
1057 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
1058 && ! SMALL_INT (XEXP (addr, 1)))
1059 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
1060 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
1070 /* In this case we can use an instruction like sd. */
1074 /* Make sure that 4 added to the address is a valid memory address.
1075 This essentially just checks for overflow in an added constant. */
1077 if (CONSTANT_ADDRESS_P (XEXP (op, 0)))
1080 op = adjust_address_nv (op, GET_MODE_CLASS (mode) == MODE_INT
1081 ? SImode : SFmode, 4);
1082 return memory_address_p (GET_MODE (op), XEXP (op, 0));
1085 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1088 equality_op (op, mode)
1090 enum machine_mode mode;
1092 if (mode != GET_MODE (op))
1095 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1098 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1103 enum machine_mode mode;
1105 if (mode != GET_MODE (op))
1108 return GET_RTX_CLASS (GET_CODE (op)) == '<';
1111 /* Return nonzero if the code is a relational operation suitable for a
1112 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1113 We need this in the insn that expands `trap_if' in order to prevent
1114 combine from erroneously altering the condition. */
1117 trap_cmp_op (op, mode)
1119 enum machine_mode mode;
1121 if (mode != GET_MODE (op))
1124 switch (GET_CODE (op))
1139 /* Return nonzero if the operand is either the PC or a label_ref. */
1142 pc_or_label_operand (op, mode)
1144 enum machine_mode mode ATTRIBUTE_UNUSED;
1149 if (GET_CODE (op) == LABEL_REF)
1155 /* Test for a valid operand for a call instruction.
1156 Don't allow the arg pointer register or virtual regs
1157 since they may change into reg + const, which the patterns
1158 can't handle yet. */
1161 call_insn_operand (op, mode)
1163 enum machine_mode mode ATTRIBUTE_UNUSED;
1165 return (CONSTANT_ADDRESS_P (op)
1166 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1167 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1168 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1171 /* Return nonzero if OPERAND is valid as a source operand for a move
1175 move_operand (op, mode)
1177 enum machine_mode mode;
1179 /* Accept any general operand after reload has started; doing so
1180 avoids losing if reload does an in-place replacement of a register
1181 with a SYMBOL_REF or CONST. */
1182 return (general_operand (op, mode)
1183 && (! (mips_split_addresses && mips_check_split (op, mode))
1184 || reload_in_progress || reload_completed)
1186 && GET_CODE (op) == SYMBOL_REF
1187 && ! mips16_constant (op, mode, 1, 0)));
1190 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1191 This accepts not only general_operand, but also sign extended
1192 constants and registers. We need to accept sign extended constants
1193 in case a sign extended register which is used in an expression,
1194 and is equivalent to a constant, is spilled. */
1197 movdi_operand (op, mode)
1199 enum machine_mode mode;
1203 && GET_CODE (op) == SIGN_EXTEND
1204 && GET_MODE (op) == DImode
1205 && (GET_MODE (XEXP (op, 0)) == SImode
1206 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1207 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1208 && (register_operand (XEXP (op, 0), SImode)
1209 || immediate_operand (XEXP (op, 0), SImode)))
1212 return (general_operand (op, mode)
1214 && GET_CODE (op) == SYMBOL_REF
1215 && ! mips16_constant (op, mode, 1, 0)));
1218 /* Like register_operand, but when in 64 bit mode also accept a sign
1219 extend of a 32 bit register, since the value is known to be already
1223 se_register_operand (op, mode)
1225 enum machine_mode mode;
1229 && GET_CODE (op) == SIGN_EXTEND
1230 && GET_MODE (op) == DImode
1231 && GET_MODE (XEXP (op, 0)) == SImode
1232 && register_operand (XEXP (op, 0), SImode))
1235 return register_operand (op, mode);
1238 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1239 extend of a 32 bit register, since the value is known to be already
1243 se_reg_or_0_operand (op, mode)
1245 enum machine_mode mode;
1249 && GET_CODE (op) == SIGN_EXTEND
1250 && GET_MODE (op) == DImode
1251 && GET_MODE (XEXP (op, 0)) == SImode
1252 && register_operand (XEXP (op, 0), SImode))
1255 return reg_or_0_operand (op, mode);
1258 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1259 extend of a 32 bit register, since the value is known to be already
1263 se_uns_arith_operand (op, mode)
1265 enum machine_mode mode;
1269 && GET_CODE (op) == SIGN_EXTEND
1270 && GET_MODE (op) == DImode
1271 && GET_MODE (XEXP (op, 0)) == SImode
1272 && register_operand (XEXP (op, 0), SImode))
1275 return uns_arith_operand (op, mode);
1278 /* Like arith_operand, but when in 64 bit mode also accept a sign
1279 extend of a 32 bit register, since the value is known to be already
1283 se_arith_operand (op, mode)
1285 enum machine_mode mode;
1289 && GET_CODE (op) == SIGN_EXTEND
1290 && GET_MODE (op) == DImode
1291 && GET_MODE (XEXP (op, 0)) == SImode
1292 && register_operand (XEXP (op, 0), SImode))
1295 return arith_operand (op, mode);
1298 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1299 extend of a 32 bit register, since the value is known to be already
1303 se_nonmemory_operand (op, mode)
1305 enum machine_mode mode;
1309 && GET_CODE (op) == SIGN_EXTEND
1310 && GET_MODE (op) == DImode
1311 && GET_MODE (XEXP (op, 0)) == SImode
1312 && register_operand (XEXP (op, 0), SImode))
1315 return nonmemory_operand (op, mode);
1318 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1319 sign extend of a 32 bit register, since the value is known to be
1320 already sign extended. */
1323 se_nonimmediate_operand (op, mode)
1325 enum machine_mode mode;
1329 && GET_CODE (op) == SIGN_EXTEND
1330 && GET_MODE (op) == DImode
1331 && GET_MODE (XEXP (op, 0)) == SImode
1332 && register_operand (XEXP (op, 0), SImode))
1335 return nonimmediate_operand (op, mode);
1338 /* Accept any operand that can appear in a mips16 constant table
1339 instruction. We can't use any of the standard operand functions
1340 because for these instructions we accept values that are not
1341 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1344 consttable_operand (op, mode)
1346 enum machine_mode mode ATTRIBUTE_UNUSED;
1348 return CONSTANT_P (op);
1351 /* Coprocessor operand; return true if rtx is a REG and refers to a
1355 coprocessor_operand (op, mode)
1357 enum machine_mode mode ATTRIBUTE_UNUSED;
1359 return (GET_CODE (op) == REG
1360 && COP0_REG_FIRST <= REGNO (op)
1361 && REGNO (op) <= COP3_REG_LAST);
1365 coprocessor2_operand (op, mode)
1367 enum machine_mode mode ATTRIBUTE_UNUSED;
1369 return (GET_CODE (op) == REG
1370 && COP2_REG_FIRST <= REGNO (op)
1371 && REGNO (op) <= COP2_REG_LAST);
1374 /* Return nonzero if we split the address into high and low parts. */
1376 /* ??? We should also handle reg+array somewhere. We get four
1377 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1378 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1379 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1380 out of the address, then we have 4 instructions to combine. Perhaps
1381 add a 3->2 define_split for combine. */
1383 /* ??? We could also split a CONST_INT here if it is a large_int().
1384 However, it doesn't seem to be very useful to have %hi(constant).
1385 We would be better off by doing the masking ourselves and then putting
1386 the explicit high part of the constant in the RTL. This will give better
1387 optimization. Also, %hi(constant) needs assembler changes to work.
1388 There is already a define_split that does this. */
1391 mips_check_split (address, mode)
1393 enum machine_mode mode;
1395 /* ??? This is the same check used in simple_memory_operand.
1396 We use it here because LO_SUM is not offsettable. */
1397 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1400 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1401 || (GET_CODE (address) == CONST
1402 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1403 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1404 || GET_CODE (address) == LABEL_REF)
1410 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1413 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1415 enum machine_mode mode;
1419 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1420 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1423 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1424 returns a nonzero value if XINSN is a legitimate address for a
1425 memory operand of the indicated MODE. STRICT is non-zero if this
1426 function is called during reload. */
1429 mips_legitimate_address_p (mode, xinsn, strict)
1430 enum machine_mode mode;
1434 if (TARGET_DEBUG_B_MODE)
1436 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1437 strict ? "" : "not ");
1438 GO_DEBUG_RTX (xinsn);
1441 /* Check for constant before stripping off SUBREG, so that we don't
1442 accept (subreg (const_int)) which will fail to reload. */
1443 if (CONSTANT_ADDRESS_P (xinsn)
1444 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1445 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1448 while (GET_CODE (xinsn) == SUBREG)
1449 xinsn = SUBREG_REG (xinsn);
1451 /* The mips16 can only use the stack pointer as a base register when
1452 loading SImode or DImode values. */
1453 if (GET_CODE (xinsn) == REG
1454 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1457 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1459 register rtx xlow0 = XEXP (xinsn, 0);
1460 register rtx xlow1 = XEXP (xinsn, 1);
1462 while (GET_CODE (xlow0) == SUBREG)
1463 xlow0 = SUBREG_REG (xlow0);
1464 if (GET_CODE (xlow0) == REG
1465 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1466 && mips_check_split (xlow1, mode))
1470 if (GET_CODE (xinsn) == PLUS)
1472 register rtx xplus0 = XEXP (xinsn, 0);
1473 register rtx xplus1 = XEXP (xinsn, 1);
1474 register enum rtx_code code0;
1475 register enum rtx_code code1;
1477 while (GET_CODE (xplus0) == SUBREG)
1478 xplus0 = SUBREG_REG (xplus0);
1479 code0 = GET_CODE (xplus0);
1481 while (GET_CODE (xplus1) == SUBREG)
1482 xplus1 = SUBREG_REG (xplus1);
1483 code1 = GET_CODE (xplus1);
1485 /* The mips16 can only use the stack pointer as a base register
1486 when loading SImode or DImode values. */
1488 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1490 if (code1 == CONST_INT && SMALL_INT (xplus1))
1493 /* On the mips16, we represent GP relative offsets in RTL.
1494 These are 16 bit signed values, and can serve as register
1497 && mips16_gp_offset_p (xplus1))
1500 /* For some code sequences, you actually get better code by
1501 pretending that the MIPS supports an address mode of a
1502 constant address + a register, even though the real
1503 machine doesn't support it. This is because the
1504 assembler can use $r1 to load just the high 16 bits, add
1505 in the register, and fold the low 16 bits into the memory
1506 reference, whereas the compiler generates a 4 instruction
1507 sequence. On the other hand, CSE is not as effective.
1508 It would be a win to generate the lui directly, but the
1509 MIPS assembler does not have syntax to generate the
1510 appropriate relocation. */
1512 /* Also accept CONST_INT addresses here, so no else. */
1513 /* Reject combining an embedded PIC text segment reference
1514 with a register. That requires an additional
1516 /* ??? Reject combining an address with a register for the MIPS
1517 64 bit ABI, because the SGI assembler can not handle this. */
1518 if (!TARGET_DEBUG_A_MODE
1519 && (mips_abi == ABI_32
1520 || mips_abi == ABI_O64
1521 || mips_abi == ABI_EABI)
1522 && CONSTANT_ADDRESS_P (xplus1)
1523 && ! mips_split_addresses
1524 && (!TARGET_EMBEDDED_PIC
1526 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1527 /* When assembling for machines with 64 bit registers,
1528 the assembler will sign-extend the constant "foo"
1529 in "la x, foo(x)" yielding the wrong result for:
1530 (set (blah:DI) (plus x y)). */
1532 || (code1 == CONST_INT
1533 && trunc_int_for_mode (INTVAL (xplus1),
1534 SImode) == INTVAL (xplus1)))
1540 if (TARGET_DEBUG_B_MODE)
1541 GO_PRINTF ("Not a legitimate address\n");
1543 /* The address was not legitimate. */
1548 /* We need a lot of little routines to check constant values on the
1549 mips16. These are used to figure out how long the instruction will
1550 be. It would be much better to do this using constraints, but
1551 there aren't nearly enough letters available. */
1554 m16_check_op (op, low, high, mask)
1560 return (GET_CODE (op) == CONST_INT
1561 && INTVAL (op) >= low
1562 && INTVAL (op) <= high
1563 && (INTVAL (op) & mask) == 0);
1567 m16_uimm3_b (op, mode)
1569 enum machine_mode mode ATTRIBUTE_UNUSED;
1571 return m16_check_op (op, 0x1, 0x8, 0);
1575 m16_simm4_1 (op, mode)
1577 enum machine_mode mode ATTRIBUTE_UNUSED;
1579 return m16_check_op (op, - 0x8, 0x7, 0);
1583 m16_nsimm4_1 (op, mode)
1585 enum machine_mode mode ATTRIBUTE_UNUSED;
1587 return m16_check_op (op, - 0x7, 0x8, 0);
1591 m16_simm5_1 (op, mode)
1593 enum machine_mode mode ATTRIBUTE_UNUSED;
1595 return m16_check_op (op, - 0x10, 0xf, 0);
1599 m16_nsimm5_1 (op, mode)
1601 enum machine_mode mode ATTRIBUTE_UNUSED;
1603 return m16_check_op (op, - 0xf, 0x10, 0);
1607 m16_uimm5_4 (op, mode)
1609 enum machine_mode mode ATTRIBUTE_UNUSED;
1611 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1615 m16_nuimm5_4 (op, mode)
1617 enum machine_mode mode ATTRIBUTE_UNUSED;
1619 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1623 m16_simm8_1 (op, mode)
1625 enum machine_mode mode ATTRIBUTE_UNUSED;
1627 return m16_check_op (op, - 0x80, 0x7f, 0);
1631 m16_nsimm8_1 (op, mode)
1633 enum machine_mode mode ATTRIBUTE_UNUSED;
1635 return m16_check_op (op, - 0x7f, 0x80, 0);
1639 m16_uimm8_1 (op, mode)
1641 enum machine_mode mode ATTRIBUTE_UNUSED;
1643 return m16_check_op (op, 0x0, 0xff, 0);
1647 m16_nuimm8_1 (op, mode)
1649 enum machine_mode mode ATTRIBUTE_UNUSED;
1651 return m16_check_op (op, - 0xff, 0x0, 0);
1655 m16_uimm8_m1_1 (op, mode)
1657 enum machine_mode mode ATTRIBUTE_UNUSED;
1659 return m16_check_op (op, - 0x1, 0xfe, 0);
1663 m16_uimm8_4 (op, mode)
1665 enum machine_mode mode ATTRIBUTE_UNUSED;
1667 return m16_check_op (op, 0x0, 0xff << 2, 3);
1671 m16_nuimm8_4 (op, mode)
1673 enum machine_mode mode ATTRIBUTE_UNUSED;
1675 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1679 m16_simm8_8 (op, mode)
1681 enum machine_mode mode ATTRIBUTE_UNUSED;
1683 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1687 m16_nsimm8_8 (op, mode)
1689 enum machine_mode mode ATTRIBUTE_UNUSED;
1691 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1694 /* References to the string table on the mips16 only use a small
1695 offset if the function is small. See the comment in the SYMBOL_REF
1696 case in simple_memory_operand. We can't check for LABEL_REF here,
1697 because the offset is always large if the label is before the
1698 referencing instruction. */
1701 m16_usym8_4 (op, mode)
1703 enum machine_mode mode ATTRIBUTE_UNUSED;
1705 if (GET_CODE (op) == SYMBOL_REF
1706 && SYMBOL_REF_FLAG (op)
1707 && current_frame_info.insns_len > 0
1708 && XSTR (op, 0)[0] == '*'
1709 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1710 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1711 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1714 struct string_constant *l;
1716 /* Make sure this symbol is on thelist of string constants to be
1717 output for this function. It is possible that it has already
1718 been output, in which case this requires a large offset. */
1719 for (l = string_constants; l != NULL; l = l->next)
1720 if (strcmp (l->label, XSTR (op, 0)) == 0)
1728 m16_usym5_4 (op, mode)
1730 enum machine_mode mode ATTRIBUTE_UNUSED;
1732 if (GET_CODE (op) == SYMBOL_REF
1733 && SYMBOL_REF_FLAG (op)
1734 && current_frame_info.insns_len > 0
1735 && XSTR (op, 0)[0] == '*'
1736 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1737 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1738 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1741 struct string_constant *l;
1743 /* Make sure this symbol is on thelist of string constants to be
1744 output for this function. It is possible that it has already
1745 been output, in which case this requires a large offset. */
1746 for (l = string_constants; l != NULL; l = l->next)
1747 if (strcmp (l->label, XSTR (op, 0)) == 0)
1754 /* Returns an operand string for the given instruction's delay slot,
1755 after updating filled delay slot statistics.
1757 We assume that operands[0] is the target register that is set.
1759 In order to check the next insn, most of this functionality is moved
1760 to FINAL_PRESCAN_INSN, and we just set the global variables that
1763 /* ??? This function no longer does anything useful, because final_prescan_insn
1764 now will never emit a nop. */
1767 mips_fill_delay_slot (ret, type, operands, cur_insn)
1768 const char *ret; /* normal string to return */
1769 enum delay_type type; /* type of delay */
1770 rtx operands[]; /* operands to use */
1771 rtx cur_insn; /* current insn */
1773 register rtx set_reg;
1774 register enum machine_mode mode;
1775 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1776 register int num_nops;
1778 if (type == DELAY_LOAD || type == DELAY_FCMP)
1781 else if (type == DELAY_HILO)
1787 /* Make sure that we don't put nop's after labels. */
1788 next_insn = NEXT_INSN (cur_insn);
1789 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1790 next_insn = NEXT_INSN (next_insn);
1792 dslots_load_total += num_nops;
1793 if (TARGET_DEBUG_F_MODE
1795 || type == DELAY_NONE
1799 || GET_CODE (next_insn) == CODE_LABEL
1800 || (set_reg = operands[0]) == 0)
1802 dslots_number_nops = 0;
1810 set_reg = operands[0];
1814 while (GET_CODE (set_reg) == SUBREG)
1815 set_reg = SUBREG_REG (set_reg);
1817 mode = GET_MODE (set_reg);
1818 dslots_number_nops = num_nops;
1819 mips_load_reg = set_reg;
1820 if (GET_MODE_SIZE (mode)
1821 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1822 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1826 if (type == DELAY_HILO)
1828 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1829 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1841 /* Determine whether a memory reference takes one (based off of the GP
1842 pointer), two (normal), or three (label + reg) instructions, and bump the
1843 appropriate counter for -mstats. */
1846 mips_count_memory_refs (op, num)
1852 rtx addr, plus0, plus1;
1853 enum rtx_code code0, code1;
1856 if (TARGET_DEBUG_B_MODE)
1858 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1862 /* Skip MEM if passed, otherwise handle movsi of address. */
1863 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1865 /* Loop, going through the address RTL. */
1869 switch (GET_CODE (addr))
1877 plus0 = XEXP (addr, 0);
1878 plus1 = XEXP (addr, 1);
1879 code0 = GET_CODE (plus0);
1880 code1 = GET_CODE (plus1);
1890 if (code0 == CONST_INT)
1905 if (code1 == CONST_INT)
1912 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1919 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1929 n_words = 2; /* always 2 words */
1933 addr = XEXP (addr, 0);
1938 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1950 n_words += additional;
1954 num_refs[n_words-1] += num;
1958 /* Return a pseudo that points to the address of the current function.
1959 The first time it is called for a function, an initializer for the
1960 pseudo is emitted in the beginning of the function. */
1963 embedded_pic_fnaddr_reg ()
1965 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
1969 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1971 /* Output code at function start to initialize the pseudo-reg. */
1972 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1973 inline functions, because it is called after RTL for the function
1974 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1975 does not get copied, and ends up not matching the rest of the RTL.
1976 This solution works, but means that we get unnecessary code to
1977 initialize this value every time a function is inlined into another
1980 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
1981 XEXP (DECL_RTL (current_function_decl), 0)));
1982 seq = gen_sequence ();
1984 push_topmost_sequence ();
1985 emit_insn_after (seq, get_insns ());
1986 pop_topmost_sequence ();
1989 return cfun->machine->embedded_pic_fnaddr_rtx;
1992 /* Return RTL for the offset from the current function to the argument.
1993 X is the symbol whose offset from the current function we want. */
1996 embedded_pic_offset (x)
1999 /* Make sure it is emitted. */
2000 embedded_pic_fnaddr_reg ();
2003 gen_rtx_CONST (Pmode,
2004 gen_rtx_MINUS (Pmode, x,
2005 XEXP (DECL_RTL (current_function_decl), 0)));
2008 /* Return the appropriate instructions to move one operand to another. */
2011 mips_move_1word (operands, insn, unsignedp)
2016 const char *ret = 0;
2017 rtx op0 = operands[0];
2018 rtx op1 = operands[1];
2019 enum rtx_code code0 = GET_CODE (op0);
2020 enum rtx_code code1 = GET_CODE (op1);
2021 enum machine_mode mode = GET_MODE (op0);
2022 int subreg_offset0 = 0;
2023 int subreg_offset1 = 0;
2024 enum delay_type delay = DELAY_NONE;
2026 while (code0 == SUBREG)
2028 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2029 GET_MODE (SUBREG_REG (op0)),
2032 op0 = SUBREG_REG (op0);
2033 code0 = GET_CODE (op0);
2036 while (code1 == SUBREG)
2038 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2039 GET_MODE (SUBREG_REG (op1)),
2042 op1 = SUBREG_REG (op1);
2043 code1 = GET_CODE (op1);
2046 /* For our purposes, a condition code mode is the same as SImode. */
2052 int regno0 = REGNO (op0) + subreg_offset0;
2056 int regno1 = REGNO (op1) + subreg_offset1;
2058 /* Just in case, don't do anything for assigning a register
2059 to itself, unless we are filling a delay slot. */
2060 if (regno0 == regno1 && set_nomacro == 0)
2063 else if (GP_REG_P (regno0))
2065 if (GP_REG_P (regno1))
2066 ret = "move\t%0,%1";
2068 else if (MD_REG_P (regno1))
2071 if (regno1 != HILO_REGNUM)
2077 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
2078 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
2083 if (FP_REG_P (regno1))
2084 ret = "mfc1\t%0,%1";
2085 else if (ALL_COP_REG_P (regno1))
2087 static char retval[] = "mfc_\t%0,%1";
2089 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2092 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
2093 ret = "cfc1\t%0,$31";
2097 else if (FP_REG_P (regno0))
2099 if (GP_REG_P (regno1))
2102 ret = "mtc1\t%1,%0";
2105 if (FP_REG_P (regno1))
2106 ret = "mov.s\t%0,%1";
2109 else if (MD_REG_P (regno0))
2111 if (GP_REG_P (regno1))
2114 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
2119 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
2121 if (GP_REG_P (regno1))
2124 ret = "ctc1\t%0,$31";
2127 else if (ALL_COP_REG_P (regno0))
2129 if (GP_REG_P (regno1))
2131 static char retval[] = "mtc_\t%1,%0";
2132 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2135 abort_with_insn (insn,
2136 "mtc0 not supported; it disturbs virtual address translation");
2144 else if (code1 == MEM)
2149 mips_count_memory_refs (op1, 1);
2151 if (GP_REG_P (regno0))
2153 /* For loads, use the mode of the memory item, instead of the
2154 target, so zero/sign extend can use this code as well. */
2155 switch (GET_MODE (op1))
2164 ret = ((unsignedp && TARGET_64BIT)
2169 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
2172 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
2177 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
2180 else if (ALL_COP_REG_P (regno0))
2182 static char retval[] = "lwc_\t%0,%1";
2183 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2186 abort_with_insn (insn,
2187 "loads from memory to COP0 are illegal");
2193 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
2195 size_t i = strlen (ret);
2196 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2199 sprintf (volatile_buffer, "%%{%s%%}", ret);
2200 ret = volatile_buffer;
2204 else if (code1 == CONST_INT
2205 || (code1 == CONST_DOUBLE
2206 && GET_MODE (op1) == VOIDmode))
2208 if (code1 == CONST_DOUBLE)
2210 /* This can happen when storing constants into long long
2211 bitfields. Just store the least significant word of
2213 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2216 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
2218 if (GP_REG_P (regno0))
2219 ret = "move\t%0,%z1";
2221 else if (FP_REG_P (regno0))
2224 ret = "mtc1\t%z1,%0";
2227 else if (MD_REG_P (regno0))
2234 else if (GP_REG_P (regno0))
2236 /* Don't use X format, because that will give out of
2237 range numbers for 64 bit host and 32 bit target. */
2238 if (! TARGET_MIPS16)
2239 ret = "li\t%0,%1\t\t\t# %X1";
2242 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2244 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2245 ret = "li\t%0,%n1\n\tneg\t%0";
2250 else if (code1 == CONST_DOUBLE && mode == SFmode)
2252 if (op1 == CONST0_RTX (SFmode))
2254 if (GP_REG_P (regno0))
2255 ret = "move\t%0,%.";
2257 else if (FP_REG_P (regno0))
2260 ret = "mtc1\t%.,%0";
2267 ret = "li.s\t%0,%1";
2271 else if (code1 == LABEL_REF)
2274 mips_count_memory_refs (op1, 1);
2279 else if (code1 == SYMBOL_REF || code1 == CONST)
2281 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
2283 rtx offset = const0_rtx;
2285 if (GET_CODE (op1) == CONST)
2286 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2288 if (GET_CODE (op1) == SYMBOL_REF)
2290 operands[2] = HALF_PIC_PTR (op1);
2293 mips_count_memory_refs (operands[2], 1);
2295 if (INTVAL (offset) == 0)
2298 ret = (unsignedp && TARGET_64BIT
2304 dslots_load_total++;
2305 operands[3] = offset;
2306 if (unsignedp && TARGET_64BIT)
2307 ret = (SMALL_INT (offset)
2308 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2309 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2311 ret = (SMALL_INT (offset)
2312 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2313 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2317 else if (TARGET_MIPS16
2319 && GET_CODE (XEXP (op1, 0)) == REG
2320 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2322 /* This case arises on the mips16; see
2323 mips16_gp_pseudo_reg. */
2324 ret = "move\t%0,%+";
2326 else if (TARGET_MIPS16
2327 && code1 == SYMBOL_REF
2328 && SYMBOL_REF_FLAG (op1)
2329 && (XSTR (op1, 0)[0] != '*'
2330 || strncmp (XSTR (op1, 0) + 1,
2332 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2334 /* This can occur when reloading the address of a GP
2335 relative symbol on the mips16. */
2336 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2341 mips_count_memory_refs (op1, 1);
2347 else if (code1 == PLUS)
2349 rtx add_op0 = XEXP (op1, 0);
2350 rtx add_op1 = XEXP (op1, 1);
2352 if (GET_CODE (XEXP (op1, 1)) == REG
2353 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2354 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2356 operands[2] = add_op0;
2357 operands[3] = add_op1;
2358 ret = "add%:\t%0,%2,%3";
2361 else if (code1 == HIGH)
2363 operands[1] = XEXP (op1, 0);
2364 ret = "lui\t%0,%%hi(%1)";
2368 else if (code0 == MEM)
2371 mips_count_memory_refs (op0, 1);
2375 int regno1 = REGNO (op1) + subreg_offset1;
2377 if (GP_REG_P (regno1))
2381 case SFmode: ret = "sw\t%1,%0"; break;
2382 case SImode: ret = "sw\t%1,%0"; break;
2383 case HImode: ret = "sh\t%1,%0"; break;
2384 case QImode: ret = "sb\t%1,%0"; break;
2389 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2391 else if (ALL_COP_REG_P (regno1))
2393 static char retval[] = "swc_\t%1,%0";
2395 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2400 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2404 case SFmode: ret = "sw\t%z1,%0"; break;
2405 case SImode: ret = "sw\t%z1,%0"; break;
2406 case HImode: ret = "sh\t%z1,%0"; break;
2407 case QImode: ret = "sb\t%z1,%0"; break;
2412 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2416 case SFmode: ret = "sw\t%.,%0"; break;
2417 case SImode: ret = "sw\t%.,%0"; break;
2418 case HImode: ret = "sh\t%.,%0"; break;
2419 case QImode: ret = "sb\t%.,%0"; break;
2424 if (ret != 0 && MEM_VOLATILE_P (op0))
2426 size_t i = strlen (ret);
2428 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2431 sprintf (volatile_buffer, "%%{%s%%}", ret);
2432 ret = volatile_buffer;
2438 abort_with_insn (insn, "bad move");
2442 if (delay != DELAY_NONE)
2443 return mips_fill_delay_slot (ret, delay, operands, insn);
2449 /* Return the appropriate instructions to move 2 words */
2452 mips_move_2words (operands, insn)
2456 const char *ret = 0;
2457 rtx op0 = operands[0];
2458 rtx op1 = operands[1];
2459 enum rtx_code code0 = GET_CODE (operands[0]);
2460 enum rtx_code code1 = GET_CODE (operands[1]);
2461 int subreg_offset0 = 0;
2462 int subreg_offset1 = 0;
2463 enum delay_type delay = DELAY_NONE;
2465 while (code0 == SUBREG)
2467 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2468 GET_MODE (SUBREG_REG (op0)),
2471 op0 = SUBREG_REG (op0);
2472 code0 = GET_CODE (op0);
2475 if (code1 == SIGN_EXTEND)
2477 op1 = XEXP (op1, 0);
2478 code1 = GET_CODE (op1);
2481 while (code1 == SUBREG)
2483 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2484 GET_MODE (SUBREG_REG (op1)),
2487 op1 = SUBREG_REG (op1);
2488 code1 = GET_CODE (op1);
2492 if (GET_CODE (operands[1]) == SIGN_EXTEND
2494 && code1 != CONST_INT
2495 /* The following three can happen as the result of a questionable
2497 && code1 != LABEL_REF
2498 && code1 != SYMBOL_REF
2504 int regno0 = REGNO (op0) + subreg_offset0;
2508 int regno1 = REGNO (op1) + subreg_offset1;
2510 /* Just in case, don't do anything for assigning a register
2511 to itself, unless we are filling a delay slot. */
2512 if (regno0 == regno1 && set_nomacro == 0)
2515 else if (FP_REG_P (regno0))
2517 if (FP_REG_P (regno1))
2518 ret = "mov.d\t%0,%1";
2526 abort_with_insn (insn, "bad move");
2528 #ifdef TARGET_FP_CALL_32
2529 if (FP_CALL_GP_REG_P (regno1))
2530 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2533 ret = "dmtc1\t%1,%0";
2536 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2540 else if (FP_REG_P (regno1))
2546 abort_with_insn (insn, "bad move");
2548 #ifdef TARGET_FP_CALL_32
2549 if (FP_CALL_GP_REG_P (regno0))
2550 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2553 ret = "dmfc1\t%0,%1";
2556 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2559 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2564 if (regno0 != HILO_REGNUM)
2566 else if (regno1 == 0)
2567 ret = "mtlo\t%.\n\tmthi\t%.";
2570 ret = "mthi\t%M1\n\tmtlo\t%L1";
2573 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2578 if (regno1 != HILO_REGNUM)
2582 ret = "mfhi\t%M0\n\tmflo\t%L0";
2584 else if (GP_REG_P (regno0) && ALL_COP_REG_P (regno1)
2587 static char retval[] = "dmfc_\t%0,%1";
2590 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2593 else if (ALL_COP_REG_P (regno0) && GP_REG_P (regno1)
2596 static char retval[] = "dmtc_\t%1,%0";
2597 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2600 abort_with_insn (insn,
2601 "dmtc0 not supported; it disturbs virtual address translation");
2606 else if (TARGET_64BIT)
2607 ret = "move\t%0,%1";
2609 else if (regno0 != (regno1+1))
2610 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2613 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2616 else if (code1 == CONST_DOUBLE)
2618 /* Move zero from $0 unless !TARGET_64BIT and recipient
2619 is 64-bit fp reg, in which case generate a constant. */
2620 if (op1 != CONST0_RTX (GET_MODE (op1))
2621 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2623 if (GET_MODE (op1) == DFmode)
2627 #ifdef TARGET_FP_CALL_32
2628 if (FP_CALL_GP_REG_P (regno0))
2630 if (TARGET_FLOAT64 && !TARGET_64BIT)
2632 split_double (op1, operands + 2, operands + 3);
2633 ret = "li\t%0,%2\n\tli\t%D0,%3";
2636 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2640 /* GNU as emits 64-bit code for li.d if the ISA is 3
2641 or higher. For !TARGET_64BIT && gp registers we
2642 need to avoid this by using two li instructions
2644 if (ISA_HAS_64BIT_REGS
2646 && ! FP_REG_P (regno0))
2648 split_double (op1, operands + 2, operands + 3);
2649 ret = "li\t%0,%2\n\tli\t%D0,%3";
2652 ret = "li.d\t%0,%1";
2655 else if (TARGET_64BIT)
2657 if (! TARGET_MIPS16)
2663 split_double (op1, operands + 2, operands + 3);
2664 ret = "li\t%0,%2\n\tli\t%D0,%3";
2670 if (GP_REG_P (regno0))
2672 #ifdef TARGET_FP_CALL_32
2673 && ! FP_CALL_GP_REG_P (regno0)
2676 : "move\t%0,%.\n\tmove\t%D0,%.");
2678 else if (FP_REG_P (regno0))
2683 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2688 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2690 if (GP_REG_P (regno0))
2693 : "move\t%0,%.\n\tmove\t%D0,%.");
2695 else if (FP_REG_P (regno0))
2702 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2704 else if (MD_REG_P (regno0))
2707 ret = (regno0 == HILO_REGNUM
2708 ? "mtlo\t%.\n\tmthi\t%."
2713 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2714 && GP_REG_P (regno0))
2720 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2722 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2723 ret = "li\t%0,%n1\n\tneg\t%0";
2725 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2726 ret = "li\t%0,%1\t\t# %X1";
2727 else if (HOST_BITS_PER_WIDE_INT < 64)
2728 /* We can't use 'X' for negative numbers, because then we won't
2729 get the right value for the upper 32 bits. */
2730 ret = (INTVAL (op1) < 0
2731 ? "dli\t%0,%1\t\t\t# %X1"
2732 : "dli\t%0,%X1\t\t# %1");
2734 /* We must use 'X', because otherwise LONG_MIN will print as
2735 a number that the assembler won't accept. */
2736 ret = "dli\t%0,%X1\t\t# %1";
2738 else if (HOST_BITS_PER_WIDE_INT < 64)
2740 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2743 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2744 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2745 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2747 operands[2] = GEN_INT (1);
2748 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2752 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2756 /* We use multiple shifts here, to avoid warnings about out
2757 of range shifts on 32 bit hosts. */
2758 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2760 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2763 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2764 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2765 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2767 operands[2] = GEN_INT (1);
2768 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2772 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2776 else if (code1 == MEM)
2781 mips_count_memory_refs (op1, 2);
2783 if (FP_REG_P (regno0))
2786 else if (ALL_COP_REG_P (regno0) && TARGET_64BIT)
2788 static char retval[] = "ldc_\t%0,%1";
2789 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2792 abort_with_insn (insn,
2793 "loads from memory to COP0 are illegal");
2799 else if (TARGET_64BIT)
2802 #ifdef TARGET_FP_CALL_32
2803 if (FP_CALL_GP_REG_P (regno0))
2804 ret = (double_memory_operand (op1, GET_MODE (op1))
2805 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2806 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2812 else if (double_memory_operand (op1, GET_MODE (op1)))
2813 ret = (reg_mentioned_p (op0, op1)
2814 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2815 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2817 if (ret != 0 && MEM_VOLATILE_P (op1))
2819 size_t i = strlen (ret);
2821 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2824 sprintf (volatile_buffer, "%%{%s%%}", ret);
2825 ret = volatile_buffer;
2829 else if (code1 == LABEL_REF)
2832 mips_count_memory_refs (op1, 2);
2834 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2835 /* We deliberately remove the 'a' from '%1', so that we don't
2836 have to add SIGN_EXTEND support to print_operand_address.
2837 print_operand will just call print_operand_address in this
2838 case, so there is no problem. */
2841 ret = "dla\t%0,%a1";
2843 else if (code1 == SYMBOL_REF || code1 == CONST)
2847 && GET_CODE (XEXP (op1, 0)) == REG
2848 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2850 /* This case arises on the mips16; see
2851 mips16_gp_pseudo_reg. */
2852 ret = "move\t%0,%+";
2854 else if (TARGET_MIPS16
2855 && code1 == SYMBOL_REF
2856 && SYMBOL_REF_FLAG (op1)
2857 && (XSTR (op1, 0)[0] != '*'
2858 || strncmp (XSTR (op1, 0) + 1,
2860 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2862 /* This can occur when reloading the address of a GP
2863 relative symbol on the mips16. */
2864 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2869 mips_count_memory_refs (op1, 2);
2871 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2872 /* We deliberately remove the 'a' from '%1', so that we don't
2873 have to add SIGN_EXTEND support to print_operand_address.
2874 print_operand will just call print_operand_address in this
2875 case, so there is no problem. */
2878 ret = "dla\t%0,%a1";
2883 else if (code0 == MEM)
2887 int regno1 = REGNO (op1) + subreg_offset1;
2889 if (FP_REG_P (regno1))
2892 else if (ALL_COP_REG_P (regno1) && TARGET_64BIT)
2894 static char retval[] = "sdc_\t%1,%0";
2896 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2899 else if (TARGET_64BIT)
2902 #ifdef TARGET_FP_CALL_32
2903 if (FP_CALL_GP_REG_P (regno1))
2904 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2910 else if (double_memory_operand (op0, GET_MODE (op0)))
2911 ret = "sw\t%1,%0\n\tsw\t%D1,%D0";
2914 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2915 || (code1 == CONST_DOUBLE
2916 && op1 == CONST0_RTX (GET_MODE (op1))))
2918 || double_memory_operand (op0, GET_MODE (op0))))
2923 ret = "sw\t%.,%0\n\tsw\t%.,%D0";
2927 mips_count_memory_refs (op0, 2);
2929 if (ret != 0 && MEM_VOLATILE_P (op0))
2931 size_t i = strlen (ret);
2933 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2936 sprintf (volatile_buffer, "%%{%s%%}", ret);
2937 ret = volatile_buffer;
2943 abort_with_insn (insn, "bad move");
2947 if (delay != DELAY_NONE)
2948 return mips_fill_delay_slot (ret, delay, operands, insn);
2953 /* Provide the costs of an addressing mode that contains ADDR.
2954 If ADDR is not a valid address, its cost is irrelevant. */
2957 mips_address_cost (addr)
2960 switch (GET_CODE (addr))
2970 rtx offset = const0_rtx;
2971 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2972 if (GET_CODE (addr) == LABEL_REF)
2975 if (GET_CODE (addr) != SYMBOL_REF)
2978 if (! SMALL_INT (offset))
2982 /* ... fall through ... */
2985 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2989 register rtx plus0 = XEXP (addr, 0);
2990 register rtx plus1 = XEXP (addr, 1);
2992 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2993 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2995 if (GET_CODE (plus0) != REG)
2998 switch (GET_CODE (plus1))
3001 return SMALL_INT (plus1) ? 1 : 2;
3008 return mips_address_cost (plus1) + 1;
3022 /* Return nonzero if X is an address which needs a temporary register when
3023 reloaded while generating PIC code. */
3026 pic_address_needs_scratch (x)
3029 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3030 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3031 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3032 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3033 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3039 /* Make normal rtx_code into something we can index from an array */
3041 static enum internal_test
3042 map_test_to_internal_test (test_code)
3043 enum rtx_code test_code;
3045 enum internal_test test = ITEST_MAX;
3049 case EQ: test = ITEST_EQ; break;
3050 case NE: test = ITEST_NE; break;
3051 case GT: test = ITEST_GT; break;
3052 case GE: test = ITEST_GE; break;
3053 case LT: test = ITEST_LT; break;
3054 case LE: test = ITEST_LE; break;
3055 case GTU: test = ITEST_GTU; break;
3056 case GEU: test = ITEST_GEU; break;
3057 case LTU: test = ITEST_LTU; break;
3058 case LEU: test = ITEST_LEU; break;
3066 /* Generate the code to compare two integer values. The return value is:
3067 (reg:SI xx) The pseudo register the comparison is in
3068 0 No register, generate a simple branch.
3070 ??? This is called with result nonzero by the Scond patterns in
3071 mips.md. These patterns are called with a target in the mode of
3072 the Scond instruction pattern. Since this must be a constant, we
3073 must use SImode. This means that if RESULT is non-zero, it will
3074 always be an SImode register, even if TARGET_64BIT is true. We
3075 cope with this by calling convert_move rather than emit_move_insn.
3076 This will sometimes lead to an unnecessary extension of the result;
3088 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
3089 enum rtx_code test_code; /* relational test (EQ, etc) */
3090 rtx result; /* result to store comp. or 0 if branch */
3091 rtx cmp0; /* first operand to compare */
3092 rtx cmp1; /* second operand to compare */
3093 int *p_invert; /* NULL or ptr to hold whether branch needs */
3094 /* to reverse its test */
3098 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
3099 int const_low; /* low bound of constant we can accept */
3100 int const_high; /* high bound of constant we can accept */
3101 int const_add; /* constant to add (convert LE -> LT) */
3102 int reverse_regs; /* reverse registers in test */
3103 int invert_const; /* != 0 if invert value if cmp1 is constant */
3104 int invert_reg; /* != 0 if invert value if cmp1 is register */
3105 int unsignedp; /* != 0 for unsigned comparisons. */
3108 static const struct cmp_info info[ (int)ITEST_MAX ] = {
3110 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
3111 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
3112 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
3113 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
3114 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
3115 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
3116 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
3117 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
3118 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
3119 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
3122 enum internal_test test;
3123 enum machine_mode mode;
3124 const struct cmp_info *p_info;
3131 test = map_test_to_internal_test (test_code);
3132 if (test == ITEST_MAX)
3135 p_info = &info[(int) test];
3136 eqne_p = (p_info->test_code == XOR);
3138 mode = GET_MODE (cmp0);
3139 if (mode == VOIDmode)
3140 mode = GET_MODE (cmp1);
3142 /* Eliminate simple branches */
3143 branch_p = (result == 0);
3146 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
3148 /* Comparisons against zero are simple branches */
3149 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
3150 && (! TARGET_MIPS16 || eqne_p))
3153 /* Test for beq/bne. */
3154 if (eqne_p && ! TARGET_MIPS16)
3158 /* allocate a pseudo to calculate the value in. */
3159 result = gen_reg_rtx (mode);
3162 /* Make sure we can handle any constants given to us. */
3163 if (GET_CODE (cmp0) == CONST_INT)
3164 cmp0 = force_reg (mode, cmp0);
3166 if (GET_CODE (cmp1) == CONST_INT)
3168 HOST_WIDE_INT value = INTVAL (cmp1);
3170 if (value < p_info->const_low
3171 || value > p_info->const_high
3172 /* ??? Why? And why wasn't the similar code below modified too? */
3174 && HOST_BITS_PER_WIDE_INT < 64
3175 && p_info->const_add != 0
3176 && ((p_info->unsignedp
3177 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
3178 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
3179 : (value + p_info->const_add) > INTVAL (cmp1))
3180 != (p_info->const_add > 0))))
3181 cmp1 = force_reg (mode, cmp1);
3184 /* See if we need to invert the result. */
3185 invert = (GET_CODE (cmp1) == CONST_INT
3186 ? p_info->invert_const : p_info->invert_reg);
3188 if (p_invert != (int *)0)
3194 /* Comparison to constants, may involve adding 1 to change a LT into LE.
3195 Comparison between two registers, may involve switching operands. */
3196 if (GET_CODE (cmp1) == CONST_INT)
3198 if (p_info->const_add != 0)
3200 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
3202 /* If modification of cmp1 caused overflow,
3203 we would get the wrong answer if we follow the usual path;
3204 thus, x > 0xffffffffU would turn into x > 0U. */
3205 if ((p_info->unsignedp
3206 ? (unsigned HOST_WIDE_INT) new >
3207 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
3208 : new > INTVAL (cmp1))
3209 != (p_info->const_add > 0))
3211 /* This test is always true, but if INVERT is true then
3212 the result of the test needs to be inverted so 0 should
3213 be returned instead. */
3214 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
3218 cmp1 = GEN_INT (new);
3222 else if (p_info->reverse_regs)
3229 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
3233 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
3234 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
3237 if (test == ITEST_NE)
3239 if (! TARGET_MIPS16)
3241 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
3242 if (p_invert != NULL)
3248 reg2 = invert ? gen_reg_rtx (mode) : result;
3249 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3254 else if (test == ITEST_EQ)
3256 reg2 = invert ? gen_reg_rtx (mode) : result;
3257 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3265 if (! TARGET_MIPS16)
3269 /* The value is in $24. Copy it to another register, so
3270 that reload doesn't think it needs to store the $24 and
3271 the input to the XOR in the same location. */
3272 reg2 = gen_reg_rtx (mode);
3273 emit_move_insn (reg2, reg);
3275 one = force_reg (mode, const1_rtx);
3277 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3283 /* Emit the common code for doing conditional branches.
3284 operand[0] is the label to jump to.
3285 The comparison operands are saved away by cmp{si,di,sf,df}. */
3288 gen_conditional_branch (operands, test_code)
3290 enum rtx_code test_code;
3292 enum cmp_type type = branch_type;
3293 rtx cmp0 = branch_cmp[0];
3294 rtx cmp1 = branch_cmp[1];
3295 enum machine_mode mode;
3304 mode = type == CMP_SI ? SImode : DImode;
3306 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3314 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3315 /* We don't want to build a comparison against a non-zero
3317 cmp1 = force_reg (mode, cmp1);
3324 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3326 reg = gen_reg_rtx (CCmode);
3328 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3329 0 in the instruction built below. The MIPS FPU handles
3330 inequality testing by testing for equality and looking for a
3332 emit_insn (gen_rtx_SET (VOIDmode, reg,
3333 gen_rtx (test_code == NE ? EQ : test_code,
3334 CCmode, cmp0, cmp1)));
3336 test_code = test_code == NE ? EQ : NE;
3344 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3347 /* Generate the branch. */
3349 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3358 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3359 gen_rtx_IF_THEN_ELSE (VOIDmode,
3360 gen_rtx (test_code, mode,
3365 /* Emit the common code for conditional moves. OPERANDS is the array
3366 of operands passed to the conditional move defined_expand. */
3369 gen_conditional_move (operands)
3372 rtx op0 = branch_cmp[0];
3373 rtx op1 = branch_cmp[1];
3374 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3375 enum rtx_code cmp_code = GET_CODE (operands[1]);
3376 enum rtx_code move_code = NE;
3377 enum machine_mode op_mode = GET_MODE (operands[0]);
3378 enum machine_mode cmp_mode;
3381 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3400 op0 = force_reg (mode, branch_cmp[1]);
3401 op1 = branch_cmp[0];
3405 op0 = force_reg (mode, branch_cmp[1]);
3406 op1 = branch_cmp[0];
3417 op0 = force_reg (mode, branch_cmp[1]);
3418 op1 = branch_cmp[0];
3422 op0 = force_reg (mode, branch_cmp[1]);
3423 op1 = branch_cmp[0];
3430 else if (cmp_code == NE)
3431 cmp_code = EQ, move_code = EQ;
3433 if (mode == SImode || mode == DImode)
3435 else if (mode == SFmode || mode == DFmode)
3440 cmp_reg = gen_reg_rtx (cmp_mode);
3441 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3442 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3444 emit_insn (gen_rtx_SET (op_mode, operands[0],
3445 gen_rtx_IF_THEN_ELSE (op_mode,
3446 gen_rtx (move_code, VOIDmode,
3448 CONST0_RTX (SImode)),
3449 operands[2], operands[3])));
3452 /* Emit the common code for conditional moves. OPERANDS is the array
3453 of operands passed to the conditional move defined_expand. */
3456 mips_gen_conditional_trap (operands)
3460 enum rtx_code cmp_code = GET_CODE (operands[0]);
3461 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3463 /* MIPS conditional trap machine instructions don't have GT or LE
3464 flavors, so we must invert the comparison and convert to LT and
3465 GE, respectively. */
3468 case GT: cmp_code = LT; break;
3469 case LE: cmp_code = GE; break;
3470 case GTU: cmp_code = LTU; break;
3471 case LEU: cmp_code = GEU; break;
3474 if (cmp_code == GET_CODE (operands[0]))
3476 op0 = force_reg (mode, branch_cmp[0]);
3477 op1 = branch_cmp[1];
3481 op0 = force_reg (mode, branch_cmp[1]);
3482 op1 = branch_cmp[0];
3484 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3485 op1 = force_reg (mode, op1);
3487 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3488 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3492 /* Write a loop to move a constant number of bytes.
3493 Generate load/stores as follows:
3499 temp<last> = src[MAX_MOVE_REGS-1];
3503 dest[MAX_MOVE_REGS-1] = temp<last>;
3504 src += MAX_MOVE_REGS;
3505 dest += MAX_MOVE_REGS;
3506 } while (src != final);
3508 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3509 registers are needed.
3511 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3512 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3513 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3515 #define MAX_MOVE_REGS 4
3516 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3519 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3520 rtx dest_reg; /* register holding destination address */
3521 rtx src_reg; /* register holding source address */
3522 unsigned int bytes; /* # bytes to move */
3523 int align; /* alignment */
3524 rtx orig_dest; /* original dest */
3525 rtx orig_src; /* original source for making a reg note */
3527 rtx dest_mem = replace_equiv_address (orig_dest, dest_reg);
3528 rtx src_mem = replace_equiv_address (orig_src, src_reg);
3529 rtx align_rtx = GEN_INT (align);
3535 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3538 leftover = bytes % MAX_MOVE_BYTES;
3541 label = gen_label_rtx ();
3542 final_src = gen_reg_rtx (Pmode);
3543 bytes_rtx = GEN_INT (bytes);
3547 if (Pmode == DImode)
3549 emit_insn (gen_movdi (final_src, bytes_rtx));
3550 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3554 emit_insn (gen_movsi (final_src, bytes_rtx));
3555 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3560 if (Pmode == DImode)
3561 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3563 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3568 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3569 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3571 if (Pmode == DImode)
3573 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3574 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3575 emit_insn (gen_cmpdi (src_reg, final_src));
3579 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3580 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3581 emit_insn (gen_cmpsi (src_reg, final_src));
3584 emit_jump_insn (gen_bne (label));
3587 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3591 /* Use a library function to move some bytes. */
3594 block_move_call (dest_reg, src_reg, bytes_rtx)
3599 /* We want to pass the size as Pmode, which will normally be SImode
3600 but will be DImode if we are using 64 bit longs and pointers. */
3601 if (GET_MODE (bytes_rtx) != VOIDmode
3602 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3603 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3605 #ifdef TARGET_MEM_FUNCTIONS
3606 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3607 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3608 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3609 TREE_UNSIGNED (sizetype)),
3610 TYPE_MODE (sizetype));
3612 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3613 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3614 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3615 TREE_UNSIGNED (integer_type_node)),
3616 TYPE_MODE (integer_type_node));
3620 /* Expand string/block move operations.
3622 operands[0] is the pointer to the destination.
3623 operands[1] is the pointer to the source.
3624 operands[2] is the number of bytes to move.
3625 operands[3] is the alignment. */
3628 expand_block_move (operands)
3631 rtx bytes_rtx = operands[2];
3632 rtx align_rtx = operands[3];
3633 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3634 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3635 unsigned int align = INTVAL (align_rtx);
3636 rtx orig_src = operands[1];
3637 rtx orig_dest = operands[0];
3641 if (constp && bytes == 0)
3644 if (align > (unsigned) UNITS_PER_WORD)
3645 align = UNITS_PER_WORD;
3647 /* Move the address into scratch registers. */
3648 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3649 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3652 block_move_call (dest_reg, src_reg, bytes_rtx);
3654 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3655 && align == (unsigned) UNITS_PER_WORD)
3656 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3658 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3659 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3661 replace_equiv_address (orig_src,
3663 bytes_rtx, align_rtx));
3665 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3666 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3668 else if (constp && optimize)
3670 /* If the alignment is not word aligned, generate a test at
3671 runtime, to see whether things wound up aligned, and we
3672 can use the faster lw/sw instead ulw/usw. */
3674 rtx temp = gen_reg_rtx (Pmode);
3675 rtx aligned_label = gen_label_rtx ();
3676 rtx join_label = gen_label_rtx ();
3677 int leftover = bytes % MAX_MOVE_BYTES;
3681 if (Pmode == DImode)
3683 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3684 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3685 emit_insn (gen_cmpdi (temp, const0_rtx));
3689 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3690 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3691 emit_insn (gen_cmpsi (temp, const0_rtx));
3694 emit_jump_insn (gen_beq (aligned_label));
3696 /* Unaligned loop. */
3697 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3698 emit_jump_insn (gen_jump (join_label));
3702 emit_label (aligned_label);
3703 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3705 emit_label (join_label);
3707 /* Bytes at the end of the loop. */
3709 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3711 replace_equiv_address (orig_src,
3718 block_move_call (dest_reg, src_reg, bytes_rtx);
3721 /* Emit load/stores for a small constant block_move.
3723 operands[0] is the memory address of the destination.
3724 operands[1] is the memory address of the source.
3725 operands[2] is the number of bytes to move.
3726 operands[3] is the alignment.
3727 operands[4] is a temp register.
3728 operands[5] is a temp register.
3730 operands[3+num_regs] is the last temp register.
3732 The block move type can be one of the following:
3733 BLOCK_MOVE_NORMAL Do all of the block move.
3734 BLOCK_MOVE_NOT_LAST Do all but the last store.
3735 BLOCK_MOVE_LAST Do just the last store. */
3738 output_block_move (insn, operands, num_regs, move_type)
3742 enum block_move_type move_type;
3744 rtx dest_reg = XEXP (operands[0], 0);
3745 rtx src_reg = XEXP (operands[1], 0);
3746 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3747 int align = INTVAL (operands[3]);
3750 int use_lwl_lwr = 0;
3751 int last_operand = num_regs + 4;
3757 const char *load; /* load insn without nop */
3758 const char *load_nop; /* load insn with trailing nop */
3759 const char *store; /* store insn */
3760 const char *final; /* if last_store used: NULL or swr */
3761 const char *last_store; /* last store instruction */
3762 int offset; /* current offset */
3763 enum machine_mode mode; /* mode to use on (MEM) */
3766 /* ??? Detect a bug in GCC, where it can give us a register
3767 the same as one of the addressing registers and reduce
3768 the number of registers available. */
3769 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3770 if (! reg_mentioned_p (operands[i], operands[0])
3771 && ! reg_mentioned_p (operands[i], operands[1]))
3772 xoperands[safe_regs++] = operands[i];
3774 if (safe_regs < last_operand)
3776 xoperands[0] = operands[0];
3777 xoperands[1] = operands[1];
3778 xoperands[2] = operands[2];
3779 xoperands[3] = operands[3];
3780 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3783 /* If we are given global or static addresses, and we would be
3784 emitting a few instructions, try to save time by using a
3785 temporary register for the pointer. */
3786 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3787 an ldl/ldr instruction pair. We play it safe, and always move
3788 constant addresses into registers when generating N32/N64 code, just
3789 in case we might emit an unaligned load instruction. */
3790 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3791 || mips_abi == ABI_MEABI
3792 || mips_abi == ABI_N32
3793 || mips_abi == ABI_64))
3795 if (CONSTANT_P (src_reg))
3798 mips_count_memory_refs (operands[1], 1);
3800 src_reg = operands[3 + num_regs--];
3801 if (move_type != BLOCK_MOVE_LAST)
3803 xoperands[1] = operands[1];
3804 xoperands[0] = src_reg;
3805 if (Pmode == DImode)
3806 output_asm_insn ("dla\t%0,%1", xoperands);
3808 output_asm_insn ("la\t%0,%1", xoperands);
3812 if (CONSTANT_P (dest_reg))
3815 mips_count_memory_refs (operands[0], 1);
3817 dest_reg = operands[3 + num_regs--];
3818 if (move_type != BLOCK_MOVE_LAST)
3820 xoperands[1] = operands[0];
3821 xoperands[0] = dest_reg;
3822 if (Pmode == DImode)
3823 output_asm_insn ("dla\t%0,%1", xoperands);
3825 output_asm_insn ("la\t%0,%1", xoperands);
3830 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3831 are not offsettable, however, offsettable_address_p says they are
3832 offsettable. I think this is a bug in offsettable_address_p.
3833 For expediency, we fix this by just loading the address into a register
3834 if we happen to get one. */
3836 if (GET_CODE (src_reg) == LO_SUM)
3838 src_reg = operands[3 + num_regs--];
3839 if (move_type != BLOCK_MOVE_LAST)
3841 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3842 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3843 xoperands[0] = src_reg;
3844 if (Pmode == DImode)
3845 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3847 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3851 if (GET_CODE (dest_reg) == LO_SUM)
3853 dest_reg = operands[3 + num_regs--];
3854 if (move_type != BLOCK_MOVE_LAST)
3856 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3857 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3858 xoperands[0] = dest_reg;
3859 if (Pmode == DImode)
3860 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3862 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3866 if (num_regs > (int) ARRAY_SIZE (load_store))
3867 num_regs = ARRAY_SIZE (load_store);
3869 else if (num_regs < 1)
3870 abort_with_insn (insn,
3871 "cannot do block move, not enough scratch registers");
3875 load_store[num].offset = offset;
3877 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3879 load_store[num].load = "ld\t%0,%1";
3880 load_store[num].load_nop = "ld\t%0,%1%#";
3881 load_store[num].store = "sd\t%0,%1";
3882 load_store[num].last_store = "sd\t%0,%1";
3883 load_store[num].final = 0;
3884 load_store[num].mode = DImode;
3889 /* ??? Fails because of a MIPS assembler bug? */
3890 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3892 if (BYTES_BIG_ENDIAN)
3894 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3895 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3896 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3897 load_store[num].last_store = "sdr\t%0,%2";
3898 load_store[num].final = "sdl\t%0,%1";
3902 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3903 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3904 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3905 load_store[num].last_store = "sdr\t%0,%1";
3906 load_store[num].final = "sdl\t%0,%2";
3909 load_store[num].mode = DImode;
3915 else if (bytes >= 4 && align >= 4)
3917 load_store[num].load = "lw\t%0,%1";
3918 load_store[num].load_nop = "lw\t%0,%1%#";
3919 load_store[num].store = "sw\t%0,%1";
3920 load_store[num].last_store = "sw\t%0,%1";
3921 load_store[num].final = 0;
3922 load_store[num].mode = SImode;
3927 else if (bytes >= 4 && ! TARGET_MIPS16)
3929 if (BYTES_BIG_ENDIAN)
3931 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3932 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3933 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3934 load_store[num].last_store = "swr\t%0,%2";
3935 load_store[num].final = "swl\t%0,%1";
3939 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3940 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3941 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3942 load_store[num].last_store = "swr\t%0,%1";
3943 load_store[num].final = "swl\t%0,%2";
3946 load_store[num].mode = SImode;
3952 else if (bytes >= 2 && align >= 2)
3954 load_store[num].load = "lh\t%0,%1";
3955 load_store[num].load_nop = "lh\t%0,%1%#";
3956 load_store[num].store = "sh\t%0,%1";
3957 load_store[num].last_store = "sh\t%0,%1";
3958 load_store[num].final = 0;
3959 load_store[num].mode = HImode;
3965 load_store[num].load = "lb\t%0,%1";
3966 load_store[num].load_nop = "lb\t%0,%1%#";
3967 load_store[num].store = "sb\t%0,%1";
3968 load_store[num].last_store = "sb\t%0,%1";
3969 load_store[num].final = 0;
3970 load_store[num].mode = QImode;
3975 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3977 dslots_load_total++;
3978 dslots_load_filled++;
3980 if (CONSTANT_P (src_reg))
3981 mips_count_memory_refs (src_reg, 1);
3983 if (CONSTANT_P (dest_reg))
3984 mips_count_memory_refs (dest_reg, 1);
3987 /* Emit load/stores now if we have run out of registers or are
3988 at the end of the move. */
3990 if (++num == num_regs || bytes == 0)
3992 /* If only load/store, we need a NOP after the load. */
3995 load_store[0].load = load_store[0].load_nop;
3996 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3997 dslots_load_filled--;
4000 if (move_type != BLOCK_MOVE_LAST)
4002 for (i = 0; i < num; i++)
4006 if (!operands[i + 4])
4009 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
4010 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
4011 REGNO (operands[i + 4]));
4013 offset = load_store[i].offset;
4014 xoperands[0] = operands[i + 4];
4015 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
4016 plus_constant (src_reg, offset));
4021 = GET_MODE_SIZE (load_store[i].mode) - 1;
4023 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
4024 plus_constant (src_reg,
4029 output_asm_insn (load_store[i].load, xoperands);
4033 for (i = 0; i < num; i++)
4035 int last_p = (i == num-1 && bytes == 0);
4036 int offset = load_store[i].offset;
4038 xoperands[0] = operands[i + 4];
4039 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
4040 plus_constant (dest_reg, offset));
4045 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
4046 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
4047 plus_constant (dest_reg,
4052 if (move_type == BLOCK_MOVE_NORMAL)
4053 output_asm_insn (load_store[i].store, xoperands);
4055 else if (move_type == BLOCK_MOVE_NOT_LAST)
4058 output_asm_insn (load_store[i].store, xoperands);
4060 else if (load_store[i].final != 0)
4061 output_asm_insn (load_store[i].final, xoperands);
4065 output_asm_insn (load_store[i].last_store, xoperands);
4068 num = 0; /* reset load_store */
4076 /* Argument support functions. */
4078 /* Initialize CUMULATIVE_ARGS for a function. */
4081 init_cumulative_args (cum, fntype, libname)
4082 CUMULATIVE_ARGS *cum; /* argument info to initialize */
4083 tree fntype; /* tree ptr for function decl */
4084 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
4086 static CUMULATIVE_ARGS zero_cum;
4087 tree param, next_param;
4089 if (TARGET_DEBUG_E_MODE)
4092 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
4095 fputc ('\n', stderr);
4099 tree ret_type = TREE_TYPE (fntype);
4100 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
4101 tree_code_name[(int)TREE_CODE (fntype)],
4102 tree_code_name[(int)TREE_CODE (ret_type)]);
4107 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4109 /* Determine if this function has variable arguments. This is
4110 indicated by the last argument being 'void_type_mode' if there
4111 are no variable arguments. The standard MIPS calling sequence
4112 passes all arguments in the general purpose registers in this case. */
4114 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
4115 param != 0; param = next_param)
4117 next_param = TREE_CHAIN (param);
4118 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
4119 cum->gp_reg_found = 1;
4124 mips_arg_info (cum, mode, type, named, info)
4125 const CUMULATIVE_ARGS *cum;
4126 enum machine_mode mode;
4129 struct mips_arg_info *info;
4132 unsigned int num_words, max_regs;
4134 info->struct_p = (type != 0
4135 && (TREE_CODE (type) == RECORD_TYPE
4136 || TREE_CODE (type) == UNION_TYPE
4137 || TREE_CODE (type) == QUAL_UNION_TYPE));
4139 /* Decide whether this argument should go in a floating-point register,
4140 assuming one is free. Later code checks for availablity. */
4142 info->fpr_p = false;
4143 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4144 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
4150 info->fpr_p = (!cum->gp_reg_found && cum->arg_number < 2);
4158 /* The MIPS eabi says only structures containing doubles get
4159 passed in a fp register, so force a structure containing
4160 a float to be passed in the integer registers. */
4161 info->fpr_p = (named && !(mode == SFmode && info->struct_p));
4165 info->fpr_p = named;
4170 /* Now decide whether the argument must go in an even-numbered register. */
4175 /* Under the O64 ABI, the second float argument goes in $f13 if it
4176 is a double, but $f14 if it is a single. Otherwise, on a
4177 32-bit double-float machine, each FP argument must start in a
4178 new register pair. */
4179 even_reg_p = ((mips_abi == ABI_O64 && mode == SFmode) || FP_INC > 1);
4181 else if (!TARGET_64BIT)
4183 if (GET_MODE_CLASS (mode) == MODE_INT
4184 || GET_MODE_CLASS (mode) == MODE_FLOAT)
4185 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
4187 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
4191 /* Set REG_OFFSET to the register count we're interested in.
4192 The EABI allocates the floating-point registers separately,
4193 but the other ABIs allocate them like integer registers. */
4194 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4199 info->reg_offset += info->reg_offset & 1;
4201 /* The alignment applied to registers is also applied to stack arguments. */
4202 info->stack_offset = cum->stack_words;
4204 info->stack_offset += info->stack_offset & 1;
4206 if (mode == BLKmode)
4207 info->num_bytes = int_size_in_bytes (type);
4209 info->num_bytes = GET_MODE_SIZE (mode);
4211 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4212 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4214 /* Partition the argument between registers and stack. */
4215 info->reg_words = MIN (num_words, max_regs);
4216 info->stack_words = num_words - info->reg_words;
4220 /* Advance the argument to the next argument position. */
4223 function_arg_advance (cum, mode, type, named)
4224 CUMULATIVE_ARGS *cum; /* current arg information */
4225 enum machine_mode mode; /* current arg mode */
4226 tree type; /* type of the argument or 0 if lib support */
4227 int named; /* whether or not the argument was named */
4229 struct mips_arg_info info;
4231 mips_arg_info (cum, mode, type, named, &info);
4233 /* The following is a hack in order to pass 1 byte structures
4234 the same way that the MIPS compiler does (namely by passing
4235 the structure in the high byte or half word of the register).
4236 This also makes varargs work. If we have such a structure,
4237 we save the adjustment RTL, and the call define expands will
4238 emit them. For the VOIDmode argument (argument after the
4239 last real argument), pass back a parallel vector holding each
4240 of the adjustments. */
4242 /* ??? This scheme requires everything smaller than the word size to
4243 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4244 that would mean every int needs to be shifted left, which is very
4245 inefficient. Let's not carry this compatibility to the 64 bit
4246 calling convention for now. */
4249 && info.reg_words == 1
4250 && info.num_bytes < UNITS_PER_WORD
4252 && mips_abi != ABI_EABI
4253 && mips_abi != ABI_MEABI)
4255 rtx amount = GEN_INT (BITS_PER_WORD - info.num_bytes * BITS_PER_UNIT);
4256 rtx reg = gen_rtx_REG (word_mode, GP_ARG_FIRST + info.reg_offset);
4259 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
4261 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
4265 cum->gp_reg_found = true;
4267 /* See the comment above the cumulative args structure in mips.h
4268 for an explanation of what this code does. It assumes the O32
4269 ABI, which passes at most 2 arguments in float registers. */
4270 if (cum->arg_number < 2 && info.fpr_p)
4271 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
4273 if (mips_abi != ABI_EABI || !info.fpr_p)
4274 cum->num_gprs = info.reg_offset + info.reg_words;
4275 else if (info.reg_words > 0)
4276 cum->num_fprs += FP_INC;
4278 if (info.stack_words > 0)
4279 cum->stack_words = info.stack_offset + info.stack_words;
4284 /* Return an RTL expression containing the register for the given mode,
4285 or 0 if the argument is to be passed on the stack. */
4288 function_arg (cum, mode, type, named)
4289 const CUMULATIVE_ARGS *cum; /* current arg information */
4290 enum machine_mode mode; /* current arg mode */
4291 tree type; /* type of the argument or 0 if lib support */
4292 int named; /* != 0 for normal args, == 0 for ... args */
4294 struct mips_arg_info info;
4296 /* We will be called with a mode of VOIDmode after the last argument
4297 has been seen. Whatever we return will be passed to the call
4298 insn. If we need any shifts for small structures, return them in
4299 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4300 mode. Otherwise, if we need a mips16 fp_code, return a REG
4301 with the code stored as the mode. */
4302 if (mode == VOIDmode)
4304 if (cum->num_adjusts > 0)
4305 return gen_rtx_PARALLEL ((enum machine_mode) cum->fp_code,
4306 gen_rtvec_v (cum->num_adjusts,
4307 (rtx *) cum->adjust));
4309 else if (TARGET_MIPS16 && cum->fp_code != 0)
4310 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4316 mips_arg_info (cum, mode, type, named, &info);
4318 /* Return straight away if the whole argument is passed on the stack. */
4319 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4323 && TREE_CODE (type) == RECORD_TYPE
4324 && (mips_abi == ABI_N32 || mips_abi == ABI_64)
4325 && TYPE_SIZE_UNIT (type)
4326 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4330 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4331 structure contains a double in its entirety, then that 64 bit
4332 chunk is passed in a floating point register. */
4335 /* First check to see if there is any such field. */
4336 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4337 if (TREE_CODE (field) == FIELD_DECL
4338 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4339 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4340 && host_integerp (bit_position (field), 0)
4341 && int_bit_position (field) % BITS_PER_WORD == 0)
4346 /* Now handle the special case by returning a PARALLEL
4347 indicating where each 64 bit chunk goes. INFO.REG_WORDS
4348 chunks are passed in registers. */
4350 HOST_WIDE_INT bitpos;
4353 /* assign_parms checks the mode of ENTRY_PARM, so we must
4354 use the actual mode here. */
4355 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4358 field = TYPE_FIELDS (type);
4359 for (i = 0; i < info.reg_words; i++)
4363 for (; field; field = TREE_CHAIN (field))
4364 if (TREE_CODE (field) == FIELD_DECL
4365 && int_bit_position (field) >= bitpos)
4369 && int_bit_position (field) == bitpos
4370 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4371 && !TARGET_SOFT_FLOAT
4372 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4373 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4375 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4378 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4379 GEN_INT (bitpos / BITS_PER_UNIT));
4381 bitpos += BITS_PER_WORD;
4387 if (mips_abi == ABI_MEABI && info.fpr_p && !cum->prototype)
4389 /* To make K&R varargs work we need to pass floating
4390 point arguments in both integer and FP registers. */
4391 return gen_rtx_PARALLEL
4394 gen_rtx_EXPR_LIST (VOIDmode,
4399 gen_rtx_EXPR_LIST (VOIDmode,
4407 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
4409 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
4413 function_arg_partial_nregs (cum, mode, type, named)
4414 const CUMULATIVE_ARGS *cum; /* current arg information */
4415 enum machine_mode mode; /* current arg mode */
4416 tree type; /* type of the argument or 0 if lib support */
4417 int named; /* != 0 for normal args, == 0 for ... args */
4419 struct mips_arg_info info;
4421 mips_arg_info (cum, mode, type, named, &info);
4422 return info.stack_words > 0 ? info.reg_words : 0;
4426 mips_setup_incoming_varargs (cum, mode, type, no_rtl)
4427 const CUMULATIVE_ARGS *cum;
4428 enum machine_mode mode;
4432 CUMULATIVE_ARGS local_cum;
4433 int gp_saved, fp_saved;
4435 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4438 /* The caller has advanced CUM up to, but not beyond, the last named
4439 argument. Advance a local copy of CUM past the last "real" named
4440 argument, to find out how many registers are left over.
4442 For K&R varargs, the last named argument is a dummy word-sized one,
4443 so CUM already contains the information we need. For stdarg, it is
4444 a real argument (such as the format in printf()) and we need to
4447 if (!current_function_varargs)
4448 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4450 /* Found out how many registers we need to save. */
4451 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4452 fp_saved = (EABI_FLOAT_VARARGS_P
4453 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4462 ptr = virtual_incoming_args_rtx;
4463 if (mips_abi == ABI_EABI)
4464 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
4465 mem = gen_rtx_MEM (BLKmode, ptr);
4467 /* va_arg is an array access in this case, which causes
4468 it to get MEM_IN_STRUCT_P set. We must set it here
4469 so that the insn scheduler won't assume that these
4470 stores can't possibly overlap with the va_arg loads. */
4471 if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN)
4472 MEM_SET_IN_STRUCT_P (mem, 1);
4474 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, mem,
4475 gp_saved, gp_saved * UNITS_PER_WORD);
4479 /* We can't use move_block_from_reg, because it will use
4481 enum machine_mode mode;
4484 /* Set OFF to the offset from virtual_incoming_args_rtx of
4485 the first float register. The FP save area lies below
4486 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4487 off = -gp_saved * UNITS_PER_WORD;
4488 off &= ~(UNITS_PER_FPVALUE - 1);
4489 off -= fp_saved * UNITS_PER_FPREG;
4491 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4493 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4495 rtx ptr = plus_constant (virtual_incoming_args_rtx, off);
4496 emit_move_insn (gen_rtx_MEM (mode, ptr),
4497 gen_rtx_REG (mode, FP_ARG_FIRST + i));
4498 off += UNITS_PER_FPVALUE;
4502 return (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
4505 /* Create the va_list data type.
4506 We keep 3 pointers, and two offsets.
4507 Two pointers are to the overflow area, which starts at the CFA.
4508 One of these is constant, for addressing into the GPR save area below it.
4509 The other is advanced up the stack through the overflow region.
4510 The third pointer is to the GPR save area. Since the FPR save area
4511 is just below it, we can address FPR slots off this pointer.
4512 We also keep two one-byte offsets, which are to be subtracted from the
4513 constant pointers to yield addresses in the GPR and FPR save areas.
4514 These are downcounted as float or non-float arguments are used,
4515 and when they get to zero, the argument must be obtained from the
4517 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4518 pointer is enough. It's started at the GPR save area, and is
4520 Note that the GPR save area is not constant size, due to optimization
4521 in the prologue. Hence, we can't use a design with two pointers
4522 and two offsets, although we could have designed this with two pointers
4523 and three offsets. */
4527 mips_build_va_list ()
4529 if (EABI_FLOAT_VARARGS_P)
4531 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4533 record = make_node (RECORD_TYPE);
4535 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4537 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4539 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4541 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4542 unsigned_char_type_node);
4543 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4544 unsigned_char_type_node);
4547 DECL_FIELD_CONTEXT (f_ovfl) = record;
4548 DECL_FIELD_CONTEXT (f_gtop) = record;
4549 DECL_FIELD_CONTEXT (f_ftop) = record;
4550 DECL_FIELD_CONTEXT (f_goff) = record;
4551 DECL_FIELD_CONTEXT (f_foff) = record;
4553 TYPE_FIELDS (record) = f_ovfl;
4554 TREE_CHAIN (f_ovfl) = f_gtop;
4555 TREE_CHAIN (f_gtop) = f_ftop;
4556 TREE_CHAIN (f_ftop) = f_goff;
4557 TREE_CHAIN (f_goff) = f_foff;
4559 layout_type (record);
4563 return ptr_type_node;
4566 /* Implement va_start. stdarg_p is 0 if implementing
4567 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4568 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4569 (It doesn't have "...", so it inherits the pointers of its caller.) */
4572 mips_va_start (stdarg_p, valist, nextarg)
4577 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
4579 if (mips_abi == ABI_EABI)
4581 int gpr_save_area_size;
4584 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4586 if (EABI_FLOAT_VARARGS_P)
4588 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4589 tree ovfl, gtop, ftop, goff, foff;
4592 int fpr_save_area_size;
4594 f_ovfl = TYPE_FIELDS (va_list_type_node);
4595 f_gtop = TREE_CHAIN (f_ovfl);
4596 f_ftop = TREE_CHAIN (f_gtop);
4597 f_goff = TREE_CHAIN (f_ftop);
4598 f_foff = TREE_CHAIN (f_goff);
4600 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4601 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4602 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4603 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4604 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4606 /* Emit code to initialize OVFL, which points to the next varargs
4607 stack argument. CUM->STACK_WORDS gives the number of stack
4608 words used by named arguments. */
4609 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4610 if (cum->stack_words > 0)
4611 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4612 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4613 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4614 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4616 /* Emit code to initialize GTOP, the top of the GPR save area. */
4617 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4618 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4619 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4621 /* Emit code to initialize FTOP, the top of the FPR save area.
4622 This address is gpr_save_area_bytes below GTOP, rounded
4623 down to the next fp-aligned boundary. */
4624 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4625 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4626 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4628 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4629 build_int_2 (-fpr_offset, -1));
4630 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4631 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4633 /* Emit code to initialize GOFF, the offset from GTOP of the
4634 next GPR argument. */
4635 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4636 build_int_2 (gpr_save_area_size, 0));
4637 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4639 /* Likewise emit code to initialize FOFF, the offset from FTOP
4640 of the next FPR argument. */
4642 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4643 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4644 build_int_2 (fpr_save_area_size, 0));
4645 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4649 /* Everything is in the GPR save area, or in the overflow
4650 area which is contiguous with it. */
4652 int offset = -gpr_save_area_size;
4653 if (gpr_save_area_size == 0)
4654 offset = (stdarg_p ? 0 : -UNITS_PER_WORD);
4655 nextarg = plus_constant (nextarg, offset);
4656 std_expand_builtin_va_start (1, valist, nextarg);
4668 /* ??? This had been conditional on
4669 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4670 and both iris5.h and iris6.h define _MIPS_SIM. */
4671 if (mips_abi == ABI_N32
4672 || mips_abi == ABI_64
4673 || mips_abi == ABI_MEABI)
4674 ofs = (cum->num_gprs < MAX_ARGS_IN_REGISTERS
4678 ofs = -UNITS_PER_WORD;
4681 nextarg = plus_constant (nextarg, ofs);
4682 std_expand_builtin_va_start (1, valist, nextarg);
4686 /* Implement va_arg. */
4689 mips_va_arg (valist, type)
4692 HOST_WIDE_INT size, rsize;
4696 size = int_size_in_bytes (type);
4697 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4699 if (mips_abi == ABI_EABI)
4705 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4709 size = POINTER_SIZE / BITS_PER_UNIT;
4710 rsize = UNITS_PER_WORD;
4713 addr_rtx = gen_reg_rtx (Pmode);
4715 if (!EABI_FLOAT_VARARGS_P)
4717 /* Case of all args in a merged stack. No need to check bounds,
4718 just advance valist along the stack. */
4723 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4725 /* Align the pointer using: ap = (ap + align - 1) & -align,
4726 where align is 2 * UNITS_PER_WORD. */
4727 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4728 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4729 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4730 build_int_2 (-2 * UNITS_PER_WORD, -1));
4731 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4732 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4735 /* Emit code to set addr_rtx to the valist, and postincrement
4736 the valist by the size of the argument, rounded up to the
4738 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4740 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4742 emit_move_insn (addr_rtx, r);
4744 /* Flush the POSTINCREMENT. */
4749 /* Not a simple merged stack. */
4751 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4752 tree ovfl, top, off;
4753 rtx lab_over = NULL_RTX, lab_false;
4754 HOST_WIDE_INT osize;
4756 f_ovfl = TYPE_FIELDS (va_list_type_node);
4757 f_gtop = TREE_CHAIN (f_ovfl);
4758 f_ftop = TREE_CHAIN (f_gtop);
4759 f_goff = TREE_CHAIN (f_ftop);
4760 f_foff = TREE_CHAIN (f_goff);
4762 /* We maintain separate pointers and offsets for floating-point
4763 and integer arguments, but we need similar code in both cases.
4766 TOP be the top of the register save area;
4767 OFF be the offset from TOP of the next register;
4768 ADDR_RTX be the address of the argument; and
4769 RSIZE be the number of bytes used to store the argument
4770 when it's in the register save area
4771 OSIZE be the number of bytes used to store it when it's
4772 in the stack overflow area
4773 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4775 The code we want is:
4777 1: off &= -rsize; // round down
4780 4: addr_rtx = top - off;
4785 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4786 10: addr_rtx = ovfl + PADDING;
4790 [1] and [9] can sometimes be optimized away. */
4792 lab_false = gen_label_rtx ();
4793 lab_over = gen_label_rtx ();
4795 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4797 if (TREE_CODE (type) == REAL_TYPE)
4799 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4800 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4802 /* When floating-point registers are saved to the stack,
4803 each one will take up UNITS_PER_FPVALUE bytes, regardless
4804 of the float's precision. */
4805 rsize = UNITS_PER_FPVALUE;
4809 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4810 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4811 if (rsize > UNITS_PER_WORD)
4813 /* [1] Emit code for: off &= -rsize. */
4814 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4815 build_int_2 (-rsize, -1));
4816 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4817 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4820 /* Every overflow argument must take up at least UNITS_PER_WORD
4821 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4822 than that, such as in the combination -mgp64 -msingle-float
4823 -fshort-double. Doubles passed in registers will then take
4824 up UNITS_PER_FPVALUE bytes, but those passed on the stack
4825 take up UNITS_PER_WORD bytes. */
4826 osize = MAX (rsize, UNITS_PER_WORD);
4828 /* [2] Emit code to branch if off == 0. */
4829 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4831 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4834 /* [4] Emit code for: addr_rtx = top - off. */
4835 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4836 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4838 emit_move_insn (addr_rtx, r);
4840 /* [5] Emit code for: off -= rsize. */
4841 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4842 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4843 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4845 /* [7] Emit code to jump over the else clause, then the label
4848 emit_jump (lab_over);
4850 emit_label (lab_false);
4852 if (osize > UNITS_PER_WORD)
4854 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4855 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4856 build_int_2 (osize - 1, 0));
4857 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4858 build_int_2 (-osize, -1));
4859 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4860 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4863 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4864 post-increment ovfl by osize. On big-endian machines,
4865 the argument has OSIZE - RSIZE bytes of leading padding. */
4866 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4868 if (BYTES_BIG_ENDIAN && osize > rsize)
4869 t = build (PLUS_EXPR, TREE_TYPE (t), t,
4870 build_int_2 (osize - rsize, 0));
4871 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4873 emit_move_insn (addr_rtx, r);
4876 emit_label (lab_over);
4880 addr_rtx = force_reg (Pmode, addr_rtx);
4881 r = gen_rtx_MEM (Pmode, addr_rtx);
4882 set_mem_alias_set (r, get_varargs_alias_set ());
4883 emit_move_insn (addr_rtx, r);
4887 if (BYTES_BIG_ENDIAN && rsize != size)
4888 addr_rtx = plus_constant (addr_rtx, rsize - size);
4897 /* ??? The original va-mips.h did always align, despite the fact
4898 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4899 increment mechanism. */
4903 else if (TYPE_ALIGN (type) > 32)
4908 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4909 build_int_2 (align - 1, 0));
4910 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4911 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4912 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4914 /* Everything past the alignment is standard. */
4915 return std_expand_builtin_va_arg (valist, type);
4919 /* Abort after printing out a specific insn. */
4922 abort_with_insn (insn, reason)
4931 /* Set up the threshold for data to go into the small data area, instead
4932 of the normal data area, and detect any conflicts in the switches. */
4937 register int i, start;
4939 register enum machine_mode mode;
4940 register enum processor_type mips_cpu;
4942 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4944 if (mips_section_threshold <= 0)
4945 target_flags &= ~MASK_GPOPT;
4947 target_flags |= MASK_GPOPT;
4949 /* If both single-float and soft-float are set, then clear the one that
4950 was set by TARGET_DEFAULT, leaving the one that was set by the
4951 user. We assume here that the specs prevent both being set by the
4953 #ifdef TARGET_DEFAULT
4954 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4955 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
4958 /* Get the architectural level. */
4959 if (mips_isa_string == 0)
4960 mips_isa = MIPS_ISA_DEFAULT;
4962 else if (mips_isa_string != 0
4963 && mips_arch_string != 0)
4964 warning ("The -march option is incompatible to -mipsN and therefore ignored.");
4966 else if (ISDIGIT (*mips_isa_string))
4968 mips_isa = atoi (mips_isa_string);
4971 /* -mno-mips16 overrides -mips16. */
4972 if (mips_no_mips16_string == NULL)
4974 target_flags |= MASK_MIPS16;
4978 mips_isa = MIPS_ISA_DEFAULT;
4982 mips_isa = MIPS_ISA_DEFAULT;
4985 else if (mips_isa < 1
4990 error ("-mips%d not supported", mips_isa);
4997 error ("bad value (%s) for -mips switch", mips_isa_string);
5001 #ifdef MIPS_ABI_DEFAULT
5002 /* Get the ABI to use. */
5003 if (mips_abi_string == (char *) 0)
5004 mips_abi = MIPS_ABI_DEFAULT;
5005 else if (! strcmp (mips_abi_string, "32"))
5007 else if (! strcmp (mips_abi_string, "o64"))
5009 else if (! strcmp (mips_abi_string, "n32"))
5011 else if (! strcmp (mips_abi_string, "64"))
5013 else if (! strcmp (mips_abi_string, "eabi"))
5014 mips_abi = ABI_EABI;
5015 else if (! strcmp (mips_abi_string, "meabi"))
5016 mips_abi = ABI_MEABI;
5018 error ("bad value (%s) for -mabi= switch", mips_abi_string);
5020 /* A specified ISA defaults the ABI if it was not specified. */
5021 if (mips_abi_string == 0 && mips_isa_string
5022 && mips_abi != ABI_EABI
5023 && mips_abi != ABI_O64
5024 && mips_abi != ABI_MEABI)
5030 if (! ISA_HAS_64BIT_REGS)
5032 else if (mips_abi != ABI_N32)
5037 #ifdef MIPS_CPU_STRING_DEFAULT
5038 /* A specified ABI defaults the ISA if it was not specified. */
5039 else if (mips_isa_string == 0 && mips_abi_string
5040 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
5042 if (mips_abi == ABI_32)
5044 else if (mips_abi == ABI_N32)
5051 /* If both ABI and ISA were specified, check for conflicts. */
5052 else if (mips_isa_string && mips_abi_string)
5054 if (! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
5055 || mips_abi == ABI_O64))
5056 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
5059 /* Override TARGET_DEFAULT if necessary. */
5060 if (mips_abi == ABI_32)
5061 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
5063 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
5064 then set the type sizes. In the EABI in 64 bit mode, longs and
5065 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
5066 if (mips_explicit_type_size_string == NULL
5067 && ((mips_abi == ABI_EABI && TARGET_64BIT)
5068 || mips_abi == ABI_64))
5069 target_flags |= MASK_LONG64;
5072 if (mips_abi_string)
5073 error ("this target does not support the -mabi switch");
5076 #ifdef MIPS_CPU_STRING_DEFAULT
5077 /* ??? There is a minor inconsistency here. If the user specifies an ISA
5078 greater than that supported by the default processor, then the user gets
5079 an error. Normally, the compiler will just default to the base level cpu
5080 for the indicated isa. */
5081 if (mips_arch_string == 0)
5082 mips_arch_string = MIPS_CPU_STRING_DEFAULT;
5083 if (mips_tune_string == 0)
5084 mips_tune_string = MIPS_CPU_STRING_DEFAULT;
5087 /* Identify the processor type. */
5089 if (mips_cpu_string != 0)
5091 mips_cpu = mips_parse_cpu (mips_cpu_string);
5092 if (mips_cpu == PROCESSOR_DEFAULT)
5094 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
5095 mips_cpu_string = "default";
5097 mips_arch = mips_cpu;
5098 mips_tune = mips_cpu;
5101 if (mips_arch_string == 0
5102 || ! strcmp (mips_arch_string, "default")
5103 || ! strcmp (mips_arch_string, "DEFAULT"))
5108 mips_arch_string = "3000";
5109 mips_arch = PROCESSOR_R3000;
5112 mips_arch_string = "6000";
5113 mips_arch = PROCESSOR_R6000;
5116 mips_arch_string = "4000";
5117 mips_arch = PROCESSOR_R4000;
5120 mips_arch_string = "8000";
5121 mips_arch = PROCESSOR_R8000;
5124 mips_arch_string = "4kc";
5125 mips_arch = PROCESSOR_R4KC;
5128 mips_arch_string = "5kc";
5129 mips_arch = PROCESSOR_R5KC;
5135 mips_arch = mips_parse_cpu (mips_arch_string);
5136 if (mips_arch == PROCESSOR_DEFAULT)
5138 error ("bad value (%s) for -march= switch", mips_arch_string);
5139 mips_arch_string = "default";
5142 if (mips_tune_string == 0
5143 || ! strcmp (mips_tune_string, "default")
5144 || ! strcmp (mips_tune_string, "DEFAULT"))
5146 if (mips_arch != PROCESSOR_DEFAULT)
5147 mips_tune = mips_arch;
5152 mips_tune_string = "3000";
5153 mips_tune = PROCESSOR_R3000;
5156 mips_tune_string = "6000";
5157 mips_tune = PROCESSOR_R6000;
5160 mips_tune_string = "4000";
5161 mips_tune = PROCESSOR_R4000;
5164 mips_tune_string = "8000";
5165 mips_tune = PROCESSOR_R8000;
5168 mips_tune_string = "4kc";
5169 mips_tune = PROCESSOR_R4KC;
5172 mips_tune_string = "5kc";
5173 mips_tune = PROCESSOR_R5KC;
5180 mips_tune = mips_parse_cpu (mips_tune_string);
5181 if (mips_tune == PROCESSOR_DEFAULT)
5183 error ("bad value (%s) for -mtune= switch", mips_tune_string);
5184 mips_tune_string = "default";
5188 /* make sure sizes of ints/longs/etc. are ok */
5189 if (! ISA_HAS_64BIT_REGS)
5193 error ("-mips%d does not support 64 bit fp registers", mips_isa);
5194 target_flags &= ~ MASK_FLOAT64;
5197 else if (TARGET_64BIT)
5199 error ("-mips%d does not support 64 bit gp registers", mips_isa);
5200 target_flags &= ~MASK_64BIT;
5204 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
5205 flag_pcc_struct_return = 0;
5207 /* Tell halfpic.c that we have half-pic code if we do. */
5208 if (TARGET_HALF_PIC)
5211 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5212 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5213 /* ??? -non_shared turns off pic code generation, but this is not
5215 if (TARGET_ABICALLS)
5217 mips_abicalls = MIPS_ABICALLS_YES;
5219 if (mips_section_threshold > 0)
5220 warning ("-G is incompatible with PIC code which is the default");
5223 mips_abicalls = MIPS_ABICALLS_NO;
5225 /* -membedded-pic is a form of PIC code suitable for embedded
5226 systems. All calls are made using PC relative addressing, and
5227 all data is addressed using the $gp register. This requires gas,
5228 which does most of the work, and GNU ld, which automatically
5229 expands PC relative calls which are out of range into a longer
5230 instruction sequence. All gcc really does differently is
5231 generate a different sequence for a switch. */
5232 if (TARGET_EMBEDDED_PIC)
5235 if (TARGET_ABICALLS)
5236 warning ("-membedded-pic and -mabicalls are incompatible");
5239 warning ("-G and -membedded-pic are incompatible");
5241 /* Setting mips_section_threshold is not required, because gas
5242 will force everything to be GP addressable anyhow, but
5243 setting it will cause gcc to make better estimates of the
5244 number of instructions required to access a particular data
5246 mips_section_threshold = 0x7fffffff;
5249 /* This optimization requires a linker that can support a R_MIPS_LO16
5250 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5251 GNU ld has this support, but not all other MIPS linkers do, so we enable
5252 this optimization only if the user requests it, or if GNU ld is the
5253 standard linker for this configuration. */
5254 /* ??? This does not work when target addresses are DImode.
5255 This is because we are missing DImode high/lo_sum patterns. */
5256 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5258 mips_split_addresses = 1;
5260 mips_split_addresses = 0;
5262 /* -mrnames says to use the MIPS software convention for register
5263 names instead of the hardware names (ie, $a0 instead of $4).
5264 We do this by switching the names in mips_reg_names, which the
5265 reg_names points into via the REGISTER_NAMES macro. */
5267 if (TARGET_NAME_REGS)
5268 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
5270 /* When compiling for the mips16, we can not use floating point. We
5271 record the original hard float value in mips16_hard_float. */
5274 if (TARGET_SOFT_FLOAT)
5275 mips16_hard_float = 0;
5277 mips16_hard_float = 1;
5278 target_flags |= MASK_SOFT_FLOAT;
5280 /* Don't run the scheduler before reload, since it tends to
5281 increase register pressure. */
5282 flag_schedule_insns = 0;
5285 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5286 to avoid using up another bit in target_flags. */
5287 if (mips_entry_string != NULL)
5289 if (*mips_entry_string != '\0')
5290 error ("invalid option `entry%s'", mips_entry_string);
5292 if (! TARGET_MIPS16)
5293 warning ("-mentry is only meaningful with -mips-16");
5298 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5299 attributes can access it. */
5305 /* Initialize the high and low values for legitimate floating point
5306 constants. Rather than trying to get the accuracy down to the
5307 last bit, just use approximate ranges. */
5308 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5309 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5310 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5311 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5313 mips_print_operand_punct['?'] = 1;
5314 mips_print_operand_punct['#'] = 1;
5315 mips_print_operand_punct['&'] = 1;
5316 mips_print_operand_punct['!'] = 1;
5317 mips_print_operand_punct['*'] = 1;
5318 mips_print_operand_punct['@'] = 1;
5319 mips_print_operand_punct['.'] = 1;
5320 mips_print_operand_punct['('] = 1;
5321 mips_print_operand_punct[')'] = 1;
5322 mips_print_operand_punct['['] = 1;
5323 mips_print_operand_punct[']'] = 1;
5324 mips_print_operand_punct['<'] = 1;
5325 mips_print_operand_punct['>'] = 1;
5326 mips_print_operand_punct['{'] = 1;
5327 mips_print_operand_punct['}'] = 1;
5328 mips_print_operand_punct['^'] = 1;
5329 mips_print_operand_punct['$'] = 1;
5330 mips_print_operand_punct['+'] = 1;
5331 mips_print_operand_punct['~'] = 1;
5333 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5334 mips_char_to_class['e'] = M16_NA_REGS;
5335 mips_char_to_class['t'] = T_REG;
5336 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5337 mips_char_to_class['h'] = HI_REG;
5338 mips_char_to_class['l'] = LO_REG;
5339 mips_char_to_class['a'] = HILO_REG;
5340 mips_char_to_class['x'] = MD_REGS;
5341 mips_char_to_class['b'] = ALL_REGS;
5342 mips_char_to_class['y'] = GR_REGS;
5343 mips_char_to_class['z'] = ST_REGS;
5344 mips_char_to_class['B'] = COP0_REGS;
5345 mips_char_to_class['C'] = COP2_REGS;
5346 mips_char_to_class['D'] = COP3_REGS;
5348 /* Set up array to map GCC register number to debug register number.
5349 Ignore the special purpose register numbers. */
5351 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5352 mips_dbx_regno[i] = -1;
5354 start = GP_DBX_FIRST - GP_REG_FIRST;
5355 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5356 mips_dbx_regno[i] = i + start;
5358 start = FP_DBX_FIRST - FP_REG_FIRST;
5359 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5360 mips_dbx_regno[i] = i + start;
5362 /* Set up array giving whether a given register can hold a given mode.
5363 At present, restrict ints from being in FP registers, because reload
5364 is a little enthusiastic about storing extra values in FP registers,
5365 and this is not good for things like OS kernels. Also, due to the
5366 mandatory delay, it is as fast to load from cached memory as to move
5367 from the FP register. */
5369 for (mode = VOIDmode;
5370 mode != MAX_MACHINE_MODE;
5371 mode = (enum machine_mode) ((int)mode + 1))
5373 register int size = GET_MODE_SIZE (mode);
5374 register enum mode_class class = GET_MODE_CLASS (mode);
5376 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5383 temp = (regno == FPSW_REGNUM);
5385 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5386 || FP_REG_P (regno));
5389 else if (GP_REG_P (regno))
5390 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5392 else if (FP_REG_P (regno))
5393 temp = (((regno % FP_INC) == 0
5394 /* I think this change is OK regardless of abi, but
5395 I'm being cautions untill I can test this more.
5396 HARD_REGNO_MODE_OK is about whether or not you
5397 can move to and from a register without changing
5398 the value, not about whether math works on the
5400 || (mips_abi == ABI_MEABI && size <= 4))
5401 && (class == MODE_FLOAT
5402 || class == MODE_COMPLEX_FLOAT
5403 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
5404 && size <= UNITS_PER_FPVALUE);
5406 else if (MD_REG_P (regno))
5407 temp = (class == MODE_INT
5408 && (size <= UNITS_PER_WORD
5409 || (regno == MD_REG_FIRST
5410 && size == 2 * UNITS_PER_WORD)));
5412 else if (ALL_COP_REG_P (regno))
5413 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5417 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5421 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5422 initialized yet, so we can't use that here. */
5423 gpr_mode = TARGET_64BIT ? DImode : SImode;
5425 /* Provide default values for align_* for 64-bit targets. */
5426 if (TARGET_64BIT && !TARGET_MIPS16)
5428 if (align_loops == 0)
5430 if (align_jumps == 0)
5432 if (align_functions == 0)
5433 align_functions = 8;
5436 /* Register global variables with the garbage collector. */
5437 mips_add_gc_roots ();
5439 /* Functions to allocate, mark and deallocate machine-dependent
5441 init_machine_status = &mips_init_machine_status;
5442 free_machine_status = &mips_free_machine_status;
5443 mark_machine_status = &mips_mark_machine_status;
5446 /* Allocate a chunk of memory for per-function machine-dependent data. */
5448 mips_init_machine_status (fn)
5449 struct function *fn;
5451 fn->machine = ((struct machine_function *)
5452 xcalloc (1, sizeof (struct machine_function)));
5455 /* Release the chunk of memory for per-function machine-dependent data. */
5457 mips_free_machine_status (fn)
5458 struct function *fn;
5464 /* Mark per-function machine-dependent data. */
5466 mips_mark_machine_status (fn)
5467 struct function *fn;
5471 ggc_mark_rtx (fn->machine->embedded_pic_fnaddr_rtx);
5472 ggc_mark_rtx (fn->machine->mips16_gp_pseudo_rtx);
5476 /* On the mips16, we want to allocate $24 (T_REG) before other
5477 registers for instructions for which it is possible. This helps
5478 avoid shuffling registers around in order to set up for an xor,
5479 encouraging the compiler to use a cmp instead. */
5482 mips_order_regs_for_local_alloc ()
5486 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5487 reg_alloc_order[i] = i;
5491 /* It really doesn't matter where we put register 0, since it is
5492 a fixed register anyhow. */
5493 reg_alloc_order[0] = 24;
5494 reg_alloc_order[24] = 0;
5499 /* The MIPS debug format wants all automatic variables and arguments
5500 to be in terms of the virtual frame pointer (stack pointer before
5501 any adjustment in the function), while the MIPS 3.0 linker wants
5502 the frame pointer to be the stack pointer after the initial
5503 adjustment. So, we do the adjustment here. The arg pointer (which
5504 is eliminated) points to the virtual frame pointer, while the frame
5505 pointer (which may be eliminated) points to the stack pointer after
5506 the initial adjustments. */
5509 mips_debugger_offset (addr, offset)
5511 HOST_WIDE_INT offset;
5513 rtx offset2 = const0_rtx;
5514 rtx reg = eliminate_constant_term (addr, &offset2);
5517 offset = INTVAL (offset2);
5519 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5520 || reg == hard_frame_pointer_rtx)
5522 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
5523 ? compute_frame_size (get_frame_size ())
5524 : current_frame_info.total_size;
5526 /* MIPS16 frame is smaller */
5527 if (frame_pointer_needed && TARGET_MIPS16)
5528 frame_size -= current_function_outgoing_args_size;
5530 offset = offset - frame_size;
5533 /* sdbout_parms does not want this to crash for unrecognized cases. */
5535 else if (reg != arg_pointer_rtx)
5536 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer");
5542 /* A C compound statement to output to stdio stream STREAM the
5543 assembler syntax for an instruction operand X. X is an RTL
5546 CODE is a value that can be used to specify one of several ways
5547 of printing the operand. It is used when identical operands
5548 must be printed differently depending on the context. CODE
5549 comes from the `%' specification that was used to request
5550 printing of the operand. If the specification was just `%DIGIT'
5551 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5552 is the ASCII code for LTR.
5554 If X is a register, this macro should print the register's name.
5555 The names can be found in an array `reg_names' whose type is
5556 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5558 When the machine description has a specification `%PUNCT' (a `%'
5559 followed by a punctuation character), this macro is called with
5560 a null pointer for X and the punctuation character for CODE.
5562 The MIPS specific codes are:
5564 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5565 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5566 'd' output integer constant in decimal,
5567 'z' if the operand is 0, use $0 instead of normal operand.
5568 'D' print second part of double-word register or memory operand.
5569 'L' print low-order register of double-word register operand.
5570 'M' print high-order register of double-word register operand.
5571 'C' print part of opcode for a branch condition.
5572 'F' print part of opcode for a floating-point branch condition.
5573 'N' print part of opcode for a branch condition, inverted.
5574 'W' print part of opcode for a floating-point branch condition, inverted.
5575 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5576 'B' print 'z' for EQ, 'n' for NE
5577 'b' print 'n' for EQ, 'z' for NE
5578 'T' print 'f' for EQ, 't' for NE
5579 't' print 't' for EQ, 'f' for NE
5580 'Z' print register and a comma, but print nothing for $fcc0
5581 '(' Turn on .set noreorder
5582 ')' Turn on .set reorder
5583 '[' Turn on .set noat
5585 '<' Turn on .set nomacro
5586 '>' Turn on .set macro
5587 '{' Turn on .set volatile (not GAS)
5588 '}' Turn on .set novolatile (not GAS)
5589 '&' Turn on .set noreorder if filling delay slots
5590 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5591 '!' Turn on .set nomacro if filling delay slots
5592 '#' Print nop if in a .set noreorder section.
5593 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5594 '@' Print the name of the assembler temporary register (at or $1).
5595 '.' Print the name of the register with a hard-wired zero (zero or $0).
5596 '^' Print the name of the pic call-through register (t9 or $25).
5597 '$' Print the name of the stack pointer register (sp or $29).
5598 '+' Print the name of the gp register (gp or $28).
5599 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5602 print_operand (file, op, letter)
5603 FILE *file; /* file to write to */
5604 rtx op; /* operand to print */
5605 int letter; /* %<letter> or 0 */
5607 register enum rtx_code code;
5609 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5614 if (mips_branch_likely)
5619 fputs (reg_names [GP_REG_FIRST + 1], file);
5623 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5627 fputs (reg_names [GP_REG_FIRST + 0], file);
5631 fputs (reg_names[STACK_POINTER_REGNUM], file);
5635 fputs (reg_names[GP_REG_FIRST + 28], file);
5639 if (final_sequence != 0 && set_noreorder++ == 0)
5640 fputs (".set\tnoreorder\n\t", file);
5644 if (final_sequence != 0)
5646 if (set_noreorder++ == 0)
5647 fputs (".set\tnoreorder\n\t", file);
5649 if (set_nomacro++ == 0)
5650 fputs (".set\tnomacro\n\t", file);
5655 if (final_sequence != 0 && set_nomacro++ == 0)
5656 fputs ("\n\t.set\tnomacro", file);
5660 if (set_noreorder != 0)
5661 fputs ("\n\tnop", file);
5662 else if (TARGET_STATS)
5663 fputs ("\n\t#nop", file);
5668 if (set_noreorder++ == 0)
5669 fputs (".set\tnoreorder\n\t", file);
5673 if (set_noreorder == 0)
5674 error ("internal error: %%) found without a %%( in assembler pattern");
5676 else if (--set_noreorder == 0)
5677 fputs ("\n\t.set\treorder", file);
5682 if (set_noat++ == 0)
5683 fputs (".set\tnoat\n\t", file);
5688 error ("internal error: %%] found without a %%[ in assembler pattern");
5689 else if (--set_noat == 0)
5690 fputs ("\n\t.set\tat", file);
5695 if (set_nomacro++ == 0)
5696 fputs (".set\tnomacro\n\t", file);
5700 if (set_nomacro == 0)
5701 error ("internal error: %%> found without a %%< in assembler pattern");
5702 else if (--set_nomacro == 0)
5703 fputs ("\n\t.set\tmacro", file);
5708 if (set_volatile++ == 0)
5709 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5713 if (set_volatile == 0)
5714 error ("internal error: %%} found without a %%{ in assembler pattern");
5715 else if (--set_volatile == 0)
5716 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5722 if (align_labels_log > 0)
5723 ASM_OUTPUT_ALIGN (file, align_labels_log);
5728 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5737 error ("PRINT_OPERAND null pointer");
5741 code = GET_CODE (op);
5743 if (code == SIGN_EXTEND)
5744 op = XEXP (op, 0), code = GET_CODE (op);
5749 case EQ: fputs ("eq", file); break;
5750 case NE: fputs ("ne", file); break;
5751 case GT: fputs ("gt", file); break;
5752 case GE: fputs ("ge", file); break;
5753 case LT: fputs ("lt", file); break;
5754 case LE: fputs ("le", file); break;
5755 case GTU: fputs ("gtu", file); break;
5756 case GEU: fputs ("geu", file); break;
5757 case LTU: fputs ("ltu", file); break;
5758 case LEU: fputs ("leu", file); break;
5760 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5763 else if (letter == 'N')
5766 case EQ: fputs ("ne", file); break;
5767 case NE: fputs ("eq", file); break;
5768 case GT: fputs ("le", file); break;
5769 case GE: fputs ("lt", file); break;
5770 case LT: fputs ("ge", file); break;
5771 case LE: fputs ("gt", file); break;
5772 case GTU: fputs ("leu", file); break;
5773 case GEU: fputs ("ltu", file); break;
5774 case LTU: fputs ("geu", file); break;
5775 case LEU: fputs ("gtu", file); break;
5777 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5780 else if (letter == 'F')
5783 case EQ: fputs ("c1f", file); break;
5784 case NE: fputs ("c1t", file); break;
5786 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5789 else if (letter == 'W')
5792 case EQ: fputs ("c1t", file); break;
5793 case NE: fputs ("c1f", file); break;
5795 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5798 else if (letter == 'S')
5802 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5803 assemble_name (file, buffer);
5806 else if (letter == 'Z')
5808 register int regnum;
5813 regnum = REGNO (op);
5814 if (! ST_REG_P (regnum))
5817 if (regnum != ST_REG_FIRST)
5818 fprintf (file, "%s,", reg_names[regnum]);
5821 else if (code == REG || code == SUBREG)
5823 register int regnum;
5826 regnum = REGNO (op);
5828 regnum = true_regnum (op);
5830 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5831 || (letter == 'L' && WORDS_BIG_ENDIAN)
5835 fprintf (file, "%s", reg_names[regnum]);
5838 else if (code == MEM)
5841 output_address (plus_constant (XEXP (op, 0), 4));
5843 output_address (XEXP (op, 0));
5846 else if (code == CONST_DOUBLE
5847 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5852 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5853 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5857 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5858 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5860 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5861 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5863 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5864 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5866 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5867 fputs (reg_names[GP_REG_FIRST], file);
5869 else if (letter == 'd' || letter == 'x' || letter == 'X')
5870 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5872 else if (letter == 'B')
5873 fputs (code == EQ ? "z" : "n", file);
5874 else if (letter == 'b')
5875 fputs (code == EQ ? "n" : "z", file);
5876 else if (letter == 'T')
5877 fputs (code == EQ ? "f" : "t", file);
5878 else if (letter == 't')
5879 fputs (code == EQ ? "t" : "f", file);
5881 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5883 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5884 print_operand (file, XEXP (op, 0), letter);
5887 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5889 fputs ("%gprel(", file);
5890 mips16_output_gp_offset (file, op);
5895 output_addr_const (file, op);
5898 /* A C compound statement to output to stdio stream STREAM the
5899 assembler syntax for an instruction operand that is a memory
5900 reference whose address is ADDR. ADDR is an RTL expression.
5902 On some machines, the syntax for a symbolic address depends on
5903 the section that the address refers to. On these machines,
5904 define the macro `ENCODE_SECTION_INFO' to store the information
5905 into the `symbol_ref', and then check for it here. */
5908 print_operand_address (file, addr)
5913 error ("PRINT_OPERAND_ADDRESS, null pointer");
5916 switch (GET_CODE (addr))
5919 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5920 abort_with_insn (addr, "arg pointer not eliminated");
5922 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5927 register rtx arg0 = XEXP (addr, 0);
5928 register rtx arg1 = XEXP (addr, 1);
5930 if (! mips_split_addresses)
5931 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
5933 if (GET_CODE (arg0) != REG)
5934 abort_with_insn (addr,
5935 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
5937 fprintf (file, "%%lo(");
5938 print_operand_address (file, arg1);
5939 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5945 register rtx reg = 0;
5946 register rtx offset = 0;
5947 register rtx arg0 = XEXP (addr, 0);
5948 register rtx arg1 = XEXP (addr, 1);
5950 if (GET_CODE (arg0) == REG)
5954 if (GET_CODE (offset) == REG)
5955 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5958 else if (GET_CODE (arg1) == REG)
5959 reg = arg1, offset = arg0;
5960 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5962 output_addr_const (file, addr);
5966 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5968 if (! CONSTANT_P (offset))
5969 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5971 if (REGNO (reg) == ARG_POINTER_REGNUM)
5972 abort_with_insn (addr, "arg pointer not eliminated");
5975 && GET_CODE (offset) == CONST
5976 && mips16_gp_offset_p (offset))
5978 fputs ("%gprel(", file);
5979 mips16_output_gp_offset (file, offset);
5983 output_addr_const (file, offset);
5984 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5992 output_addr_const (file, addr);
5996 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
6001 /* Target hook for assembling integer objects. It appears that the Irix
6002 6 assembler can't handle 64-bit decimal integers, so avoid printing
6003 such an integer here. */
6006 mips_assemble_integer (x, size, aligned_p)
6011 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
6013 fputs ("\t.dword\t", asm_out_file);
6014 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
6015 output_addr_const (asm_out_file, x);
6017 print_operand (asm_out_file, x, 'X');
6018 fputc ('\n', asm_out_file);
6021 return default_assemble_integer (x, size, aligned_p);
6024 /* If optimizing for the global pointer, keep track of all of the externs, so
6025 that at the end of the file, we can emit the appropriate .extern
6026 declaration for them, before writing out the text section. We assume all
6027 names passed to us are in the permanent obstack, so they will be valid at
6028 the end of the compilation.
6030 If we have -G 0, or the extern size is unknown, or the object is in a user
6031 specified section that is not .sbss/.sdata, don't bother emitting the
6032 .externs. In the case of user specified sections this behaviour is
6033 required as otherwise GAS will think the object lives in .sbss/.sdata. */
6036 mips_output_external (file, decl, name)
6037 FILE *file ATTRIBUTE_UNUSED;
6041 register struct extern_list *p;
6046 && TREE_CODE (decl) != FUNCTION_DECL
6047 && !DECL_COMDAT (decl)
6048 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
6049 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
6050 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
6051 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
6053 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
6054 p->next = extern_head;
6060 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6061 if (TREE_CODE (decl) == FUNCTION_DECL
6062 /* ??? Don't include alloca, since gcc will always expand it
6063 inline. If we don't do this, the C++ library fails to build. */
6064 && strcmp (name, "alloca")
6065 /* ??? Don't include __builtin_next_arg, because then gcc will not
6066 bootstrap under Irix 5.1. */
6067 && strcmp (name, "__builtin_next_arg"))
6069 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
6070 p->next = extern_head;
6080 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6082 mips_output_external_libcall (file, name)
6083 FILE *file ATTRIBUTE_UNUSED;
6086 register struct extern_list *p;
6088 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
6089 p->next = extern_head;
6098 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
6099 for .file's that start within a function. If we are smuggling stabs, try to
6100 put out a MIPS ECOFF file and a stab. */
6103 mips_output_filename (stream, name)
6107 static int first_time = 1;
6108 char ltext_label_name[100];
6114 current_function_file = name;
6115 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
6116 /* This tells mips-tfile that stabs will follow. */
6117 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
6118 fprintf (stream, "\t#@stabs\n");
6121 else if (write_symbols == DBX_DEBUG)
6123 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
6124 fprintf (stream, "%s", ASM_STABS_OP);
6125 output_quoted_string (stream, name);
6126 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
6129 else if (name != current_function_file
6130 && strcmp (name, current_function_file) != 0)
6132 if (inside_function && !TARGET_GAS)
6134 if (!file_in_function_warning)
6136 file_in_function_warning = 1;
6137 ignore_line_number = 1;
6138 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
6144 current_function_file = name;
6145 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
6150 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
6151 as well as a .loc, since it is possible that MIPS ECOFF might not be
6152 able to represent the location for inlines that come from a different
6156 mips_output_lineno (stream, line)
6160 if (write_symbols == DBX_DEBUG)
6163 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
6164 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
6165 LOCAL_LABEL_PREFIX, sym_lineno);
6169 fprintf (stream, "\n\t%s.loc\t%d %d\n",
6170 (ignore_line_number) ? "#" : "",
6171 num_source_filenames, line);
6173 LABEL_AFTER_LOC (stream);
6177 /* Output an ASCII string, in a space-saving way. */
6180 mips_output_ascii (stream, string_param, len)
6182 const char *string_param;
6187 register const unsigned char *string =
6188 (const unsigned char *)string_param;
6190 fprintf (stream, "\t.ascii\t\"");
6191 for (i = 0; i < len; i++)
6193 register int c = string[i];
6199 putc ('\\', stream);
6204 case TARGET_NEWLINE:
6205 fputs ("\\n", stream);
6207 && (((c = string[i+1]) >= '\040' && c <= '~')
6208 || c == TARGET_TAB))
6209 cur_pos = 32767; /* break right here */
6215 fputs ("\\t", stream);
6220 fputs ("\\f", stream);
6225 fputs ("\\b", stream);
6230 fputs ("\\r", stream);
6235 if (c >= ' ' && c < 0177)
6242 fprintf (stream, "\\%03o", c);
6247 if (cur_pos > 72 && i+1 < len)
6250 fprintf (stream, "\"\n\t.ascii\t\"");
6253 fprintf (stream, "\"\n");
6256 /* If defined, a C statement to be executed just prior to the output of
6257 assembler code for INSN, to modify the extracted operands so they will be
6260 Here the argument OPVEC is the vector containing the operands extracted
6261 from INSN, and NOPERANDS is the number of elements of the vector which
6262 contain meaningful data for this insn. The contents of this vector are
6263 what will be used to convert the insn template into assembler code, so you
6264 can change the assembler output by changing the contents of the vector.
6266 We use it to check if the current insn needs a nop in front of it because
6267 of load delays, and also to update the delay slot statistics. */
6269 /* ??? There is no real need for this function, because it never actually
6270 emits a NOP anymore. */
6273 final_prescan_insn (insn, opvec, noperands)
6275 rtx opvec[] ATTRIBUTE_UNUSED;
6276 int noperands ATTRIBUTE_UNUSED;
6278 if (dslots_number_nops > 0)
6280 rtx pattern = PATTERN (insn);
6281 int length = get_attr_length (insn);
6283 /* Do we need to emit a NOP? */
6285 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
6286 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
6287 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
6288 || (mips_load_reg4 != 0
6289 && reg_mentioned_p (mips_load_reg4, pattern)))
6290 fputs ("\t#nop\n", asm_out_file);
6293 dslots_load_filled++;
6295 while (--dslots_number_nops > 0)
6296 fputs ("\t#nop\n", asm_out_file);
6305 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6306 dslots_jump_total++;
6309 /* Output at beginning of assembler file.
6311 If we are optimizing to use the global pointer, create a temporary file to
6312 hold all of the text stuff, and write it out to the end. This is needed
6313 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6314 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6315 processed, it generates a two instruction sequence. */
6318 mips_asm_file_start (stream)
6321 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6323 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6324 inside of a .set noreorder section jumps to a label outside of the .set
6325 noreorder section. Revision 2.20 just set nobopt silently rather than
6328 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6329 fprintf (stream, "\t.set\tnobopt\n");
6333 #if defined(OBJECT_FORMAT_ELF)
6334 /* Generate a special section to describe the ABI switches used to
6335 produce the resultant binary. This used to be done by the assembler
6336 setting bits in the ELF header's flags field, but we have run out of
6337 bits. GDB needs this information in order to be able to correctly
6338 debug these binaries. See the function mips_gdbarch_init() in
6340 const char * abi_string = NULL;
6344 case ABI_32: abi_string = "abi32"; break;
6345 case ABI_N32: abi_string = "abiN32"; break;
6346 case ABI_64: abi_string = "abi64"; break;
6347 case ABI_O64: abi_string = "abiO64"; break;
6348 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6349 case ABI_MEABI:abi_string = TARGET_64BIT ? "meabi64" : "meabi32"; break;
6353 /* Note - we use fprintf directly rather than called named_section()
6354 because in this way we can avoid creating an allocated section. We
6355 do not want this section to take up any space in the running
6357 fprintf (stream, "\t.section .mdebug.%s\n", abi_string);
6359 /* Restore the default section. */
6360 fprintf (stream, "\t.previous\n");
6366 /* Generate the pseudo ops that System V.4 wants. */
6367 #ifndef ABICALLS_ASM_OP
6368 #define ABICALLS_ASM_OP "\t.abicalls"
6370 if (TARGET_ABICALLS)
6371 /* ??? but do not want this (or want pic0) if -non-shared? */
6372 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
6375 fprintf (stream, "\t.set\tmips16\n");
6377 /* This code exists so that we can put all externs before all symbol
6378 references. This is necessary for the MIPS assembler's global pointer
6379 optimizations to work. */
6380 if (TARGET_FILE_SWITCHING)
6382 asm_out_data_file = stream;
6383 asm_out_text_file = tmpfile ();
6386 asm_out_data_file = asm_out_text_file = stream;
6388 if (flag_verbose_asm)
6389 fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6391 mips_section_threshold, mips_arch_string, mips_isa);
6394 /* If we are optimizing the global pointer, emit the text section now and any
6395 small externs which did not have .comm, etc that are needed. Also, give a
6396 warning if the data area is more than 32K and -pic because 3 instructions
6397 are needed to reference the data pointers. */
6400 mips_asm_file_end (file)
6404 struct extern_list *p;
6408 HALF_PIC_FINISH (file);
6415 for (p = extern_head; p != 0; p = p->next)
6417 name_tree = get_identifier (p->name);
6419 /* Positively ensure only one .extern for any given symbol. */
6420 if (! TREE_ASM_WRITTEN (name_tree))
6422 TREE_ASM_WRITTEN (name_tree) = 1;
6423 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6425 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6429 fputs ("\t.extern\t", file);
6430 assemble_name (file, p->name);
6431 fprintf (file, ", %d\n", p->size);
6437 if (TARGET_FILE_SWITCHING)
6439 fprintf (file, "\n\t.text\n");
6440 copy_file_data (file, asm_out_text_file);
6445 copy_file_data (to, from)
6452 fatal_io_error ("can't rewind temp file");
6454 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
6455 if (fwrite (buffer, 1, len, to) != len)
6456 fatal_io_error ("can't write to output file");
6459 fatal_io_error ("can't read from temp file");
6462 fatal_io_error ("can't close temp file");
6465 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6466 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6469 mips_declare_object (stream, name, init_string, final_string, size)
6472 const char *init_string;
6473 const char *final_string;
6476 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6477 assemble_name (stream, name);
6478 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6482 tree name_tree = get_identifier (name);
6483 TREE_ASM_WRITTEN (name_tree) = 1;
6487 /* Return the bytes needed to compute the frame pointer from the current
6490 Mips stack frames look like:
6492 Before call After call
6493 +-----------------------+ +-----------------------+
6496 | caller's temps. | | caller's temps. |
6498 +-----------------------+ +-----------------------+
6500 | arguments on stack. | | arguments on stack. |
6502 +-----------------------+ +-----------------------+
6503 | 4 words to save | | 4 words to save |
6504 | arguments passed | | arguments passed |
6505 | in registers, even | | in registers, even |
6506 SP->| if not passed. | VFP->| if not passed. |
6507 +-----------------------+ +-----------------------+
6509 | fp register save |
6511 +-----------------------+
6513 | gp register save |
6515 +-----------------------+
6519 +-----------------------+
6521 | alloca allocations |
6523 +-----------------------+
6525 | GP save for V.4 abi |
6527 +-----------------------+
6529 | arguments on stack |
6531 +-----------------------+
6533 | arguments passed |
6534 | in registers, even |
6535 low SP->| if not passed. |
6536 memory +-----------------------+
6541 compute_frame_size (size)
6542 HOST_WIDE_INT size; /* # of var. bytes allocated */
6545 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6546 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6547 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6548 HOST_WIDE_INT extra_size; /* # extra bytes */
6549 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6550 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6551 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6552 long mask; /* mask of saved gp registers */
6553 long fmask; /* mask of saved fp registers */
6560 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6561 var_size = MIPS_STACK_ALIGN (size);
6562 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6564 /* The MIPS 3.0 linker does not like functions that dynamically
6565 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6566 looks like we are trying to create a second frame pointer to the
6567 function, so allocate some stack space to make it happy. */
6569 if (args_size == 0 && current_function_calls_alloca)
6570 args_size = 4 * UNITS_PER_WORD;
6572 total_size = var_size + args_size + extra_size;
6573 return_type = DECL_RESULT (current_function_decl);
6575 /* Calculate space needed for gp registers. */
6576 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6578 /* $18 is a special case on the mips16. It may be used to call
6579 a function which returns a floating point value, but it is
6580 marked in call_used_regs. $31 is also a special case. When
6581 not using -mentry, it will be used to copy a return value
6582 into the floating point registers if the return value is
6584 if (MUST_SAVE_REGISTER (regno)
6586 && regno == GP_REG_FIRST + 18
6587 && regs_ever_live[regno])
6589 && regno == GP_REG_FIRST + 31
6590 && mips16_hard_float
6592 && ! aggregate_value_p (return_type)
6593 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6594 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE))
6596 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6597 mask |= 1L << (regno - GP_REG_FIRST);
6599 /* The entry and exit pseudo instructions can not save $17
6600 without also saving $16. */
6602 && regno == GP_REG_FIRST + 17
6603 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6605 gp_reg_size += UNITS_PER_WORD;
6611 /* We need to restore these for the handler. */
6612 if (current_function_calls_eh_return)
6617 regno = EH_RETURN_DATA_REGNO (i);
6618 if (regno == INVALID_REGNUM)
6620 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6621 mask |= 1L << (regno - GP_REG_FIRST);
6625 /* This loop must iterate over the same space as its companion in
6626 save_restore_insns. */
6627 for (regno = (FP_REG_LAST - FP_INC + 1);
6628 regno >= FP_REG_FIRST;
6631 if (regs_ever_live[regno] && !call_used_regs[regno])
6633 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6634 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6638 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6639 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6641 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6642 for leaf routines (total_size == extra_size) to save the gp reg.
6643 The gp reg is callee saved in the 64 bit ABI, so all routines must
6644 save the gp reg. This is not a leaf routine if -p, because of the
6646 if (total_size == extra_size
6647 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6648 && ! current_function_profile)
6649 total_size = extra_size = 0;
6650 else if (TARGET_ABICALLS)
6652 /* Add the context-pointer to the saved registers. */
6653 gp_reg_size += UNITS_PER_WORD;
6654 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6655 total_size -= gp_reg_rounded;
6656 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6657 total_size += gp_reg_rounded;
6660 /* Add in space reserved on the stack by the callee for storing arguments
6661 passed in registers. */
6662 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6663 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6665 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6666 if (mips_entry && total_size > 0 && total_size < 32)
6669 /* Save other computed information. */
6670 current_frame_info.total_size = total_size;
6671 current_frame_info.var_size = var_size;
6672 current_frame_info.args_size = args_size;
6673 current_frame_info.extra_size = extra_size;
6674 current_frame_info.gp_reg_size = gp_reg_size;
6675 current_frame_info.fp_reg_size = fp_reg_size;
6676 current_frame_info.mask = mask;
6677 current_frame_info.fmask = fmask;
6678 current_frame_info.initialized = reload_completed;
6679 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6680 current_frame_info.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6684 unsigned long offset;
6686 /* When using mips_entry, the registers are always saved at the
6687 top of the stack. */
6689 offset = (args_size + extra_size + var_size
6690 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6692 offset = total_size - GET_MODE_SIZE (gpr_mode);
6694 current_frame_info.gp_sp_offset = offset;
6695 current_frame_info.gp_save_offset = offset - total_size;
6699 current_frame_info.gp_sp_offset = 0;
6700 current_frame_info.gp_save_offset = 0;
6705 unsigned long offset = (args_size + extra_size + var_size
6706 + gp_reg_rounded + fp_reg_size
6707 - FP_INC * UNITS_PER_FPREG);
6708 current_frame_info.fp_sp_offset = offset;
6709 current_frame_info.fp_save_offset = offset - total_size;
6713 current_frame_info.fp_sp_offset = 0;
6714 current_frame_info.fp_save_offset = 0;
6717 /* Ok, we're done. */
6721 /* Common code to emit the insns (or to write the instructions to a file)
6722 to save/restore registers.
6724 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6725 is not modified within save_restore_insns. */
6727 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6729 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6730 and return an rtl expression for the register.
6732 This function is a subroutine of save_restore_insns. It is used when
6733 OFFSET is too large to add in a single instruction. */
6736 mips_add_large_offset_to_sp (offset)
6737 HOST_WIDE_INT offset;
6739 rtx reg = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6740 rtx offset_rtx = GEN_INT (offset);
6742 emit_move_insn (reg, offset_rtx);
6743 if (Pmode == DImode)
6744 emit_insn (gen_adddi3 (reg, reg, stack_pointer_rtx));
6746 emit_insn (gen_addsi3 (reg, reg, stack_pointer_rtx));
6750 /* Make INSN frame related and note that it performs the frame-related
6751 operation DWARF_PATTERN. */
6754 mips_annotate_frame_insn (insn, dwarf_pattern)
6755 rtx insn, dwarf_pattern;
6757 RTX_FRAME_RELATED_P (insn) = 1;
6758 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6763 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6764 The expression should only be used to store single registers. */
6767 mips_frame_set (mode, regno, offset)
6768 enum machine_mode mode;
6772 rtx address = plus_constant (stack_pointer_rtx, offset);
6773 rtx set = gen_rtx_SET (mode,
6774 gen_rtx_MEM (mode, address),
6775 gen_rtx_REG (mode, regno));
6776 RTX_FRAME_RELATED_P (set) = 1;
6781 /* Emit a move instruction that stores REG in MEM. Make the instruction
6782 frame related and note that it stores REG at (SP + OFFSET). This
6783 function may be asked to store an FPR pair. */
6786 mips_emit_frame_related_store (mem, reg, offset)
6789 HOST_WIDE_INT offset;
6793 if (GET_MODE (reg) == DFmode && ! TARGET_FLOAT64)
6795 /* Two registers are being stored, so the frame-related expression
6796 must be a PARALLEL rtx with one SET for each register. The
6797 higher numbered register is stored in the lower address on
6798 big-endian targets. */
6799 int regno1 = TARGET_BIG_ENDIAN ? REGNO (reg) + 1 : REGNO (reg);
6800 int regno2 = TARGET_BIG_ENDIAN ? REGNO (reg) : REGNO (reg) + 1;
6801 rtx set1 = mips_frame_set (SFmode, regno1, offset);
6802 rtx set2 = mips_frame_set (SFmode, regno2, offset + UNITS_PER_FPREG);
6803 dwarf_expr = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2));
6806 dwarf_expr = mips_frame_set (GET_MODE (reg), REGNO (reg), offset);
6808 mips_annotate_frame_insn (emit_move_insn (mem, reg), dwarf_expr);
6812 save_restore_insns (store_p, large_reg, large_offset)
6813 int store_p; /* true if this is prologue */
6814 rtx large_reg; /* register holding large offset constant or NULL */
6815 long large_offset; /* large constant offset value */
6817 long mask = current_frame_info.mask;
6818 long fmask = current_frame_info.fmask;
6819 long real_mask = mask;
6822 HOST_WIDE_INT base_offset;
6823 HOST_WIDE_INT gp_offset;
6824 HOST_WIDE_INT fp_offset;
6825 HOST_WIDE_INT end_offset;
6828 if (frame_pointer_needed
6829 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6832 /* Do not restore GP under certain conditions. */
6835 && (mips_abi == ABI_32 || mips_abi == ABI_O64))
6836 mask &= ~(1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST));
6838 if (mask == 0 && fmask == 0)
6841 /* Save registers starting from high to low. The debuggers prefer at least
6842 the return register be stored at func+4, and also it allows us not to
6843 need a nop in the epilog if at least one register is reloaded in
6844 addition to return address. */
6846 /* Save GP registers if needed. */
6849 /* Pick which pointer to use as a base register. For small frames, just
6850 use the stack pointer. Otherwise, use a temporary register. Save 2
6851 cycles if the save area is near the end of a large frame, by reusing
6852 the constant created in the prologue/epilogue to adjust the stack
6855 gp_offset = current_frame_info.gp_sp_offset;
6857 = gp_offset - (current_frame_info.gp_reg_size
6858 - GET_MODE_SIZE (gpr_mode));
6860 if (gp_offset < 0 || end_offset < 0)
6862 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
6863 (long) gp_offset, (long) end_offset);
6865 /* If we see a large frame in mips16 mode, we save the registers
6866 before adjusting the stack pointer, and load them afterward. */
6867 else if (TARGET_MIPS16 && large_offset > 32767)
6868 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6870 else if (gp_offset < 32768)
6871 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6873 else if (large_reg != 0
6874 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6875 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6877 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6878 base_offset = large_offset;
6879 if (Pmode == DImode)
6880 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6881 stack_pointer_rtx));
6883 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6884 stack_pointer_rtx));
6888 base_offset = gp_offset;
6889 base_reg_rtx = mips_add_large_offset_to_sp (base_offset);
6892 /* When we restore the registers in MIPS16 mode, then if we are
6893 using a frame pointer, and this is not a large frame, the
6894 current stack pointer will be offset by
6895 current_function_outgoing_args_size. Doing it this way lets
6896 us avoid offsetting the frame pointer before copying it into
6897 the stack pointer; there is no instruction to set the stack
6898 pointer to the sum of a register and a constant. */
6901 && frame_pointer_needed
6902 && large_offset <= 32767)
6903 base_offset += current_function_outgoing_args_size;
6905 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6907 if (BITSET_P (mask, regno - GP_REG_FIRST))
6911 = gen_rtx (MEM, gpr_mode,
6912 gen_rtx (PLUS, Pmode, base_reg_rtx,
6913 GEN_INT (gp_offset - base_offset)));
6915 if (! current_function_calls_eh_return)
6916 RTX_UNCHANGING_P (mem_rtx) = 1;
6918 /* The mips16 does not have an instruction to load
6919 $31, so we load $7 instead, and work things out
6920 in mips_expand_epilogue. */
6921 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6922 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6923 /* The mips16 sometimes needs to save $18. */
6924 else if (TARGET_MIPS16
6925 && regno != GP_REG_FIRST + 31
6926 && ! M16_REG_P (regno))
6929 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6932 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6933 emit_move_insn (reg_rtx,
6934 gen_rtx (REG, gpr_mode, regno));
6938 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6941 mips_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
6944 emit_move_insn (reg_rtx, mem_rtx);
6946 && regno != GP_REG_FIRST + 31
6947 && ! M16_REG_P (regno))
6948 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6952 /* If the restore is being supressed, still take into account
6953 the offset at which it is stored. */
6954 if (BITSET_P (real_mask, regno - GP_REG_FIRST))
6955 gp_offset -= GET_MODE_SIZE (gpr_mode);
6959 base_reg_rtx = 0, base_offset = 0;
6961 /* Save floating point registers if needed. */
6964 /* Pick which pointer to use as a base register. */
6965 fp_offset = current_frame_info.fp_sp_offset;
6966 end_offset = fp_offset - (current_frame_info.fp_reg_size
6967 - UNITS_PER_FPVALUE);
6969 if (fp_offset < 0 || end_offset < 0)
6971 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
6972 (long) fp_offset, (long) end_offset);
6974 else if (fp_offset < 32768)
6975 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6977 else if (base_reg_rtx != 0
6978 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6979 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6980 ; /* already set up for gp registers above */
6982 else if (large_reg != 0
6983 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6984 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6986 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6987 base_offset = large_offset;
6988 if (Pmode == DImode)
6989 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6990 stack_pointer_rtx));
6992 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6993 stack_pointer_rtx));
6997 base_offset = fp_offset;
6998 base_reg_rtx = mips_add_large_offset_to_sp (fp_offset);
7001 /* This loop must iterate over the same space as its companion in
7002 compute_frame_size. */
7003 for (regno = (FP_REG_LAST - FP_INC + 1);
7004 regno >= FP_REG_FIRST;
7006 if (BITSET_P (fmask, regno - FP_REG_FIRST))
7008 enum machine_mode sz = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
7009 rtx reg_rtx = gen_rtx (REG, sz, regno);
7010 rtx mem_rtx = gen_rtx (MEM, sz,
7011 gen_rtx (PLUS, Pmode, base_reg_rtx,
7014 if (! current_function_calls_eh_return)
7015 RTX_UNCHANGING_P (mem_rtx) = 1;
7018 mips_emit_frame_related_store (mem_rtx, reg_rtx, fp_offset);
7020 emit_move_insn (reg_rtx, mem_rtx);
7022 fp_offset -= UNITS_PER_FPVALUE;
7027 /* Set up the stack and frame (if desired) for the function. */
7030 mips_output_function_prologue (file, size)
7032 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7034 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7037 HOST_WIDE_INT tsize = current_frame_info.total_size;
7039 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
7041 #ifdef SDB_DEBUGGING_INFO
7042 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
7043 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
7046 /* In mips16 mode, we may need to generate a 32 bit to handle
7047 floating point arguments. The linker will arrange for any 32 bit
7048 functions to call this stub, which will then jump to the 16 bit
7050 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
7051 && current_function_args_info.fp_code != 0)
7052 build_mips16_function_stub (file);
7054 inside_function = 1;
7056 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7057 /* Get the function name the same way that toplev.c does before calling
7058 assemble_start_function. This is needed so that the name used here
7059 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7060 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7062 if (!flag_inhibit_size_directive)
7064 fputs ("\t.ent\t", file);
7065 assemble_name (file, fnname);
7069 assemble_name (file, fnname);
7070 fputs (":\n", file);
7073 if (!flag_inhibit_size_directive)
7075 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7077 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7078 (reg_names[(frame_pointer_needed)
7079 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
7080 ((frame_pointer_needed && TARGET_MIPS16)
7081 ? ((long) tsize - current_function_outgoing_args_size)
7083 reg_names[GP_REG_FIRST + 31],
7084 current_frame_info.var_size,
7085 current_frame_info.num_gp,
7086 current_frame_info.num_fp,
7087 current_function_outgoing_args_size,
7088 current_frame_info.extra_size);
7090 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7091 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7092 current_frame_info.mask,
7093 current_frame_info.gp_save_offset,
7094 current_frame_info.fmask,
7095 current_frame_info.fp_save_offset);
7098 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7099 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7102 if (mips_entry && ! mips_can_use_return_insn ())
7104 int save16 = BITSET_P (current_frame_info.mask, 16);
7105 int save17 = BITSET_P (current_frame_info.mask, 17);
7106 int save31 = BITSET_P (current_frame_info.mask, 31);
7110 /* Look through the initial insns to see if any of them store
7111 the function parameters into the incoming parameter storage
7112 area. If they do, we delete the insn, and save the register
7113 using the entry pseudo-instruction instead. We don't try to
7114 look past a label, jump, or call. */
7115 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
7117 rtx note, set, src, dest, base, offset;
7120 if (GET_CODE (insn) == CODE_LABEL
7121 || GET_CODE (insn) == JUMP_INSN
7122 || GET_CODE (insn) == CALL_INSN)
7124 if (GET_CODE (insn) != INSN)
7126 set = PATTERN (insn);
7127 if (GET_CODE (set) != SET)
7130 /* An insn storing a function parameter will still have a
7131 REG_EQUIV note on it mentioning the argument pointer. */
7132 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
7133 if (note == NULL_RTX)
7135 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
7138 src = SET_SRC (set);
7139 if (GET_CODE (src) != REG
7140 || REGNO (src) < GP_REG_FIRST + 4
7141 || REGNO (src) > GP_REG_FIRST + 7)
7144 dest = SET_DEST (set);
7145 if (GET_CODE (dest) != MEM)
7147 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
7149 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
7150 && REGNO (src) < GP_REG_FIRST + 7)
7154 offset = const0_rtx;
7155 base = eliminate_constant_term (XEXP (dest, 0), &offset);
7156 if (GET_CODE (base) != REG
7157 || GET_CODE (offset) != CONST_INT)
7159 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
7160 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
7162 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
7165 + (REGNO (src) - 4) * UNITS_PER_WORD
7166 - current_function_outgoing_args_size)))
7171 /* This insn stores a parameter onto the stack, in the same
7172 location where the entry pseudo-instruction will put it.
7173 Delete the insn, and arrange to tell the entry
7174 instruction to save the register. */
7175 PUT_CODE (insn, NOTE);
7176 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7177 NOTE_SOURCE_FILE (insn) = 0;
7179 hireg = (REGNO (src)
7180 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
7182 if (hireg > savearg)
7186 /* If this is a varargs function, we need to save all the
7187 registers onto the stack anyhow. */
7188 if (current_function_stdarg || current_function_varargs)
7189 savearg = GP_REG_FIRST + 7;
7191 fprintf (file, "\tentry\t");
7194 if (savearg == GP_REG_FIRST + 4)
7195 fprintf (file, "%s", reg_names[savearg]);
7197 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
7198 reg_names[savearg]);
7200 if (save16 || save17)
7203 fprintf (file, ",");
7204 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
7206 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
7210 if (savearg > 0 || save16 || save17)
7211 fprintf (file, ",");
7212 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
7214 fprintf (file, "\n");
7217 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
7219 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7221 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7222 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7225 fprintf (file, "\t%s\t%s,%s,%ld\n",
7226 (Pmode == DImode ? "dsubu" : "subu"),
7227 sp_str, sp_str, (long) tsize);
7228 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
7231 if (dwarf2out_do_frame ())
7232 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
7236 /* Expand the prologue into a bunch of separate insns. */
7239 mips_expand_prologue ()
7242 HOST_WIDE_INT tsize;
7244 int last_arg_is_vararg_marker = 0;
7245 tree fndecl = current_function_decl;
7246 tree fntype = TREE_TYPE (fndecl);
7247 tree fnargs = DECL_ARGUMENTS (fndecl);
7252 CUMULATIVE_ARGS args_so_far;
7253 rtx reg_18_save = NULL_RTX;
7254 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7255 && (! mips_entry || mips_can_use_return_insn ());
7257 /* If struct value address is treated as the first argument, make it so. */
7258 if (aggregate_value_p (DECL_RESULT (fndecl))
7259 && ! current_function_returns_pcc_struct
7260 && struct_value_incoming_rtx == 0)
7262 tree type = build_pointer_type (fntype);
7263 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7265 DECL_ARG_TYPE (function_result_decl) = type;
7266 TREE_CHAIN (function_result_decl) = fnargs;
7267 fnargs = function_result_decl;
7270 /* For arguments passed in registers, find the register number
7271 of the first argument in the variable part of the argument list,
7272 otherwise GP_ARG_LAST+1. Note also if the last argument is
7273 the varargs special argument, and treat it as part of the
7276 This is only needed if store_args_on_stack is true. */
7278 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7279 regno = GP_ARG_FIRST;
7281 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7283 tree passed_type = DECL_ARG_TYPE (cur_arg);
7284 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7287 if (TREE_ADDRESSABLE (passed_type))
7289 passed_type = build_pointer_type (passed_type);
7290 passed_mode = Pmode;
7293 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7295 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7296 next_arg = TREE_CHAIN (cur_arg);
7298 if (entry_parm && store_args_on_stack)
7301 && DECL_NAME (cur_arg)
7302 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7303 "__builtin_va_alist"))
7304 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7307 last_arg_is_vararg_marker = 1;
7308 if (GET_CODE (entry_parm) == REG)
7309 regno = REGNO (entry_parm);
7311 regno = GP_ARG_LAST + 1;
7318 if (GET_CODE (entry_parm) != REG)
7321 /* passed in a register, so will get homed automatically */
7322 if (GET_MODE (entry_parm) == BLKmode)
7323 words = (int_size_in_bytes (passed_type) + 3) / 4;
7325 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
7327 regno = REGNO (entry_parm) + words - 1;
7332 regno = GP_ARG_LAST+1;
7337 /* In order to pass small structures by value in registers compatibly with
7338 the MIPS compiler, we need to shift the value into the high part of the
7339 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7340 adjustments to be made as the next_arg_reg variable, so we split up the
7341 insns, and emit them separately. */
7343 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7344 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7346 rtvec adjust = XVEC (next_arg_reg, 0);
7347 int num = GET_NUM_ELEM (adjust);
7349 for (i = 0; i < num; i++)
7353 pattern = RTVEC_ELT (adjust, i);
7354 if (GET_CODE (pattern) != SET
7355 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7356 abort_with_insn (pattern, "insn is not a shift");
7357 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7359 insn = emit_insn (pattern);
7361 /* Global life information isn't valid at this point, so we
7362 can't check whether these shifts are actually used. Mark
7363 them MAYBE_DEAD so that flow2 will remove them, and not
7364 complain about dead code in the prologue. */
7365 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7370 tsize = compute_frame_size (get_frame_size ());
7372 /* If this function is a varargs function, store any registers that
7373 would normally hold arguments ($4 - $7) on the stack. */
7374 if (store_args_on_stack
7375 && ((TYPE_ARG_TYPES (fntype) != 0
7376 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7378 || last_arg_is_vararg_marker))
7380 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7381 rtx ptr = stack_pointer_rtx;
7383 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7384 if (TARGET_ABICALLS)
7387 for (; regno <= GP_ARG_LAST; regno++)
7390 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7391 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7392 gen_rtx (REG, gpr_mode, regno));
7394 offset += GET_MODE_SIZE (gpr_mode);
7398 /* If we are using the entry pseudo instruction, it will
7399 automatically subtract 32 from the stack pointer, so we don't
7400 need to. The entry pseudo instruction is emitted by
7401 function_prologue. */
7402 if (mips_entry && ! mips_can_use_return_insn ())
7404 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7408 /* If we are using a frame pointer with a small stack frame,
7409 we need to initialize it here since it won't be done
7411 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7413 rtx incr = GEN_INT (current_function_outgoing_args_size);
7414 if (Pmode == DImode)
7415 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7419 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7423 else if (Pmode == DImode)
7424 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7425 stack_pointer_rtx));
7427 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7428 stack_pointer_rtx));
7430 RTX_FRAME_RELATED_P (insn) = 1;
7433 /* We may need to save $18, if it is used to call a function
7434 which may return a floating point value. Set up a sequence
7435 of instructions to do so. Later on we emit them at the right
7437 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
7439 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7440 long gp_offset, base_offset;
7442 gp_offset = current_frame_info.gp_sp_offset;
7443 if (BITSET_P (current_frame_info.mask, 16))
7444 gp_offset -= UNITS_PER_WORD;
7445 if (BITSET_P (current_frame_info.mask, 17))
7446 gp_offset -= UNITS_PER_WORD;
7447 if (BITSET_P (current_frame_info.mask, 31))
7448 gp_offset -= UNITS_PER_WORD;
7450 base_offset = tsize;
7454 emit_move_insn (reg_rtx,
7455 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7456 emit_move_insn (gen_rtx (MEM, gpr_mode,
7457 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7461 reg_18_save = gen_sequence ();
7470 if (reg_18_save != NULL_RTX)
7471 emit_insn (reg_18_save);
7477 rtx tsize_rtx = GEN_INT (tsize);
7479 /* If we are doing svr4-abi, sp move is done by
7480 function_prologue. In mips16 mode with a large frame, we
7481 save the registers before adjusting the stack. */
7482 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7483 && (!TARGET_MIPS16 || tsize <= 32767))
7485 rtx adjustment_rtx, insn, dwarf_pattern;
7489 adjustment_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7490 emit_move_insn (adjustment_rtx, tsize_rtx);
7493 adjustment_rtx = tsize_rtx;
7495 if (Pmode == DImode)
7496 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7499 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7502 dwarf_pattern = gen_rtx_SET (Pmode, stack_pointer_rtx,
7503 plus_constant (stack_pointer_rtx,
7506 mips_annotate_frame_insn (insn, dwarf_pattern);
7510 save_restore_insns (1, tmp_rtx, tsize);
7511 else if (reg_18_save != NULL_RTX)
7512 emit_insn (reg_18_save);
7514 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7520 if (!frame_pointer_needed)
7523 reg_rtx = gen_rtx (REG, Pmode, 3);
7524 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7525 emit_move_insn (reg_rtx, tsize_rtx);
7526 if (Pmode == DImode)
7527 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7528 hard_frame_pointer_rtx,
7531 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7532 hard_frame_pointer_rtx,
7534 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7537 if (frame_pointer_needed)
7541 /* On the mips16, we encourage the use of unextended
7542 instructions when using the frame pointer by pointing the
7543 frame pointer ahead of the argument space allocated on
7545 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7549 /* In this case, we have already copied the stack
7550 pointer into the frame pointer, above. We need only
7551 adjust for the outgoing argument size. */
7552 if (current_function_outgoing_args_size != 0)
7554 rtx incr = GEN_INT (current_function_outgoing_args_size);
7555 if (Pmode == DImode)
7556 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7557 hard_frame_pointer_rtx,
7560 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7561 hard_frame_pointer_rtx,
7565 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7567 rtx incr = GEN_INT (current_function_outgoing_args_size);
7568 if (Pmode == DImode)
7569 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7573 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7577 else if (Pmode == DImode)
7578 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7579 stack_pointer_rtx));
7581 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7582 stack_pointer_rtx));
7585 RTX_FRAME_RELATED_P (insn) = 1;
7588 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7589 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7590 gen_rtx_REG (DImode, 25)));
7593 /* If we are profiling, make sure no instructions are scheduled before
7594 the call to mcount. */
7596 if (current_function_profile)
7597 emit_insn (gen_blockage ());
7600 /* Do any necessary cleanup after a function to restore stack, frame,
7603 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7604 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7607 mips_output_function_epilogue (file, size)
7608 FILE *file ATTRIBUTE_UNUSED;
7609 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7611 const char *fnname = ""; /* FIXME: Correct initialisation? */
7613 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7614 /* Get the function name the same way that toplev.c does before calling
7615 assemble_start_function. This is needed so that the name used here
7616 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7617 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7619 if (!flag_inhibit_size_directive)
7621 fputs ("\t.end\t", file);
7622 assemble_name (file, fnname);
7629 int num_gp_regs = current_frame_info.gp_reg_size / 4;
7630 int num_fp_regs = current_frame_info.fp_reg_size / 8;
7631 int num_regs = num_gp_regs + num_fp_regs;
7632 const char *name = fnname;
7637 dslots_load_total += num_regs;
7640 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7641 name, frame_pointer_needed ? 'y' : 'n',
7642 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7643 current_function_calls_alloca ? 'y' : 'n',
7644 current_function_calls_setjmp ? 'y' : 'n',
7645 current_frame_info.total_size,
7646 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7647 dslots_load_total, dslots_load_filled,
7648 dslots_jump_total, dslots_jump_filled,
7649 num_refs[0], num_refs[1], num_refs[2]);
7651 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7654 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7655 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7658 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7661 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7662 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7665 fputc ('\n', stderr);
7668 /* Reset state info for each function. */
7669 inside_function = 0;
7670 ignore_line_number = 0;
7671 dslots_load_total = 0;
7672 dslots_jump_total = 0;
7673 dslots_load_filled = 0;
7674 dslots_jump_filled = 0;
7680 current_frame_info = zero_frame_info;
7682 while (string_constants != NULL)
7684 struct string_constant *next;
7686 next = string_constants->next;
7687 free (string_constants);
7688 string_constants = next;
7691 /* Restore the output file if optimizing the GP (optimizing the GP causes
7692 the text to be diverted to a tempfile, so that data decls come before
7693 references to the data). */
7694 if (TARGET_FILE_SWITCHING)
7696 asm_out_file = asm_out_data_file;
7701 /* Expand the epilogue into a bunch of separate insns. */
7704 mips_expand_epilogue ()
7706 HOST_WIDE_INT tsize = current_frame_info.total_size;
7707 rtx tsize_rtx = GEN_INT (tsize);
7708 rtx tmp_rtx = (rtx)0;
7710 if (mips_can_use_return_insn ())
7712 emit_insn (gen_return ());
7716 if (mips_entry && ! mips_can_use_return_insn ())
7719 if (tsize > 32767 && ! TARGET_MIPS16)
7721 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7722 emit_move_insn (tmp_rtx, tsize_rtx);
7723 tsize_rtx = tmp_rtx;
7728 long orig_tsize = tsize;
7730 if (frame_pointer_needed)
7732 emit_insn (gen_blockage ());
7734 /* On the mips16, the frame pointer is offset from the stack
7735 pointer by current_function_outgoing_args_size. We
7736 account for that by changing tsize. Note that this can
7737 actually make tsize negative. */
7740 tsize -= current_function_outgoing_args_size;
7742 /* If we have a large frame, it's easier to add to $6
7743 than to $sp, since the mips16 has no instruction to
7744 add a register to $sp. */
7745 if (orig_tsize > 32767)
7747 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7749 emit_move_insn (g6_rtx, GEN_INT (tsize));
7750 if (Pmode == DImode)
7751 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7752 hard_frame_pointer_rtx,
7755 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7756 hard_frame_pointer_rtx,
7761 if (tsize && tsize != orig_tsize)
7762 tsize_rtx = GEN_INT (tsize);
7765 if (Pmode == DImode)
7766 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7768 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7771 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7772 are going to restore it, then we must emit a blockage insn to
7773 prevent the scheduler from moving the restore out of the epilogue. */
7774 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7775 && (current_frame_info.mask
7776 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7777 emit_insn (gen_blockage ());
7779 save_restore_insns (0, tmp_rtx, orig_tsize);
7781 /* In mips16 mode with a large frame, we adjust the stack
7782 pointer before restoring the registers. In this case, we
7783 should always be using a frame pointer, so everything should
7784 have been handled above. */
7785 if (tsize > 32767 && TARGET_MIPS16)
7788 if (current_function_calls_eh_return)
7790 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
7791 if (Pmode == DImode)
7792 emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
7794 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
7798 emit_insn (gen_blockage ());
7800 if (tsize != 0 || current_function_calls_eh_return)
7804 if (Pmode == DImode)
7805 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7808 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7813 /* We need to work around not being able to add a register
7814 to the stack pointer directly. Use register $6 as an
7815 intermediate step. */
7817 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7819 if (Pmode == DImode)
7821 emit_insn (gen_movdi (g6_rtx, stack_pointer_rtx));
7822 emit_insn (gen_adddi3 (g6_rtx, g6_rtx, tsize_rtx));
7823 emit_insn (gen_movdi (stack_pointer_rtx, g6_rtx));
7827 emit_insn (gen_movsi (g6_rtx, stack_pointer_rtx));
7828 emit_insn (gen_addsi3 (g6_rtx, g6_rtx, tsize_rtx));
7829 emit_insn (gen_movsi (stack_pointer_rtx, g6_rtx));
7836 /* The mips16 loads the return address into $7, not $31. */
7837 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7838 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7839 GP_REG_FIRST + 7)));
7841 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7842 GP_REG_FIRST + 31)));
7845 /* Return nonzero if this function is known to have a null epilogue.
7846 This allows the optimizer to omit jumps to jumps if no stack
7850 mips_can_use_return_insn ()
7854 if (! reload_completed)
7857 if (regs_ever_live[31] || current_function_profile)
7860 return_type = DECL_RESULT (current_function_decl);
7862 /* In mips16 mode, a function which returns a floating point value
7863 needs to arrange to copy the return value into the floating point
7866 && mips16_hard_float
7867 && ! aggregate_value_p (return_type)
7868 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7869 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7872 if (current_frame_info.initialized)
7873 return current_frame_info.total_size == 0;
7875 return compute_frame_size (get_frame_size ()) == 0;
7878 /* Returns non-zero if X contains a SYMBOL_REF. */
7881 symbolic_expression_p (x)
7884 if (GET_CODE (x) == SYMBOL_REF)
7887 if (GET_CODE (x) == CONST)
7888 return symbolic_expression_p (XEXP (x, 0));
7890 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7891 return symbolic_expression_p (XEXP (x, 0));
7893 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7894 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7895 return (symbolic_expression_p (XEXP (x, 0))
7896 || symbolic_expression_p (XEXP (x, 1)));
7901 /* Choose the section to use for the constant rtx expression X that has
7905 mips_select_rtx_section (mode, x, align)
7906 enum machine_mode mode;
7908 unsigned HOST_WIDE_INT align;
7912 /* In mips16 mode, the constant table always goes in the same section
7913 as the function, so that constants can be loaded using PC relative
7915 function_section (current_function_decl);
7917 else if (TARGET_EMBEDDED_DATA)
7919 /* For embedded applications, always put constants in read-only data,
7920 in order to reduce RAM usage. */
7921 mergeable_constant_section (mode, align, 0);
7925 /* For hosted applications, always put constants in small data if
7926 possible, as this gives the best performance. */
7927 /* ??? Consider using mergable small data sections. */
7929 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7930 && mips_section_threshold > 0)
7931 SMALL_DATA_SECTION ();
7932 else if (flag_pic && symbolic_expression_p (x))
7934 if (targetm.have_named_sections)
7935 named_section (NULL_TREE, ".data.rel.ro", 3);
7940 mergeable_constant_section (mode, align, 0);
7944 /* Choose the section to use for DECL. RELOC is true if its value contains
7945 any relocatable expression.
7947 Some of the logic used here needs to be replicated in
7948 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7949 are done correctly. Specifically, at least all symbols assigned
7950 here to rom (.text and/or .rodata) must not be referenced via
7951 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7953 If you need to make a change here, you probably should check
7954 ENCODE_SECTION_INFO to see if it needs a similar change. */
7957 mips_select_section (decl, reloc, align)
7960 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
7962 int size = int_size_in_bytes (TREE_TYPE (decl));
7964 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7965 && TREE_CODE (decl) == STRING_CST
7966 && !flag_writable_strings)
7967 /* For embedded position independent code, put constant strings in the
7968 text section, because the data section is limited to 64K in size.
7969 For mips16 code, put strings in the text section so that a PC
7970 relative load instruction can be used to get their address. */
7972 else if (TARGET_EMBEDDED_DATA)
7974 /* For embedded applications, always put an object in read-only data
7975 if possible, in order to reduce RAM usage. */
7977 if (((TREE_CODE (decl) == VAR_DECL
7978 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7979 && DECL_INITIAL (decl)
7980 && (DECL_INITIAL (decl) == error_mark_node
7981 || TREE_CONSTANT (DECL_INITIAL (decl))))
7982 /* Deal with calls from output_constant_def_contents. */
7983 || (TREE_CODE (decl) != VAR_DECL
7984 && (TREE_CODE (decl) != STRING_CST
7985 || !flag_writable_strings)))
7986 && ! (flag_pic && reloc))
7987 readonly_data_section ();
7988 else if (size > 0 && size <= mips_section_threshold)
7989 SMALL_DATA_SECTION ();
7995 /* For hosted applications, always put an object in small data if
7996 possible, as this gives the best performance. */
7998 if (size > 0 && size <= mips_section_threshold)
7999 SMALL_DATA_SECTION ();
8000 else if (((TREE_CODE (decl) == VAR_DECL
8001 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
8002 && DECL_INITIAL (decl)
8003 && (DECL_INITIAL (decl) == error_mark_node
8004 || TREE_CONSTANT (DECL_INITIAL (decl))))
8005 /* Deal with calls from output_constant_def_contents. */
8006 || (TREE_CODE (decl) != VAR_DECL
8007 && (TREE_CODE (decl) != STRING_CST
8008 || !flag_writable_strings)))
8009 && ! (flag_pic && reloc))
8010 readonly_data_section ();
8016 /* Return register to use for a function return value with VALTYPE for
8017 function FUNC. MODE is used instead of VALTYPE for LIBCALLs. */
8020 mips_function_value (valtype, func, mode)
8022 tree func ATTRIBUTE_UNUSED;
8023 enum machine_mode mode;
8025 int reg = GP_RETURN;
8026 enum mode_class mclass;
8031 mode = TYPE_MODE (valtype);
8032 unsignedp = TREE_UNSIGNED (valtype);
8034 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
8035 the mode just as PROMOTE_MODE does. */
8036 mode = promote_mode (valtype, mode, &unsignedp, 1);
8038 mclass = GET_MODE_CLASS (mode);
8040 if (mclass == MODE_FLOAT && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
8043 else if (mclass == MODE_COMPLEX_FLOAT
8044 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE * 2)
8046 enum machine_mode cmode = GET_MODE_INNER (mode);
8048 return gen_rtx_PARALLEL
8051 gen_rtx_EXPR_LIST (VOIDmode,
8052 gen_rtx_REG (cmode, FP_RETURN),
8054 gen_rtx_EXPR_LIST (VOIDmode,
8055 gen_rtx_REG (cmode, FP_RETURN + FP_INC),
8056 GEN_INT (GET_MODE_SIZE (cmode)))));
8059 else if (valtype && TREE_CODE (valtype) == RECORD_TYPE
8060 && mips_abi != ABI_32
8061 && mips_abi != ABI_O64
8062 && mips_abi != ABI_EABI)
8064 /* A struct with only one or two floating point fields is returned in
8065 the floating point registers. */
8066 tree field, fields[2];
8069 for (i = 0, field = TYPE_FIELDS (valtype); field;
8070 field = TREE_CHAIN (field))
8072 if (TREE_CODE (field) != FIELD_DECL)
8075 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
8078 fields[i++] = field;
8081 /* Must check i, so that we reject structures with no elements. */
8086 /* The structure has DImode, but we don't allow DImode values
8087 in FP registers, so we use a PARALLEL even though it isn't
8088 strictly necessary. */
8089 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
8091 return gen_rtx_PARALLEL
8094 gen_rtx_EXPR_LIST (VOIDmode,
8095 gen_rtx_REG (field_mode,
8102 enum machine_mode first_mode
8103 = TYPE_MODE (TREE_TYPE (fields[0]));
8104 enum machine_mode second_mode
8105 = TYPE_MODE (TREE_TYPE (fields[1]));
8106 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
8107 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
8109 return gen_rtx_PARALLEL
8112 gen_rtx_EXPR_LIST (VOIDmode,
8113 gen_rtx_REG (first_mode,
8115 GEN_INT (first_offset)),
8116 gen_rtx_EXPR_LIST (VOIDmode,
8117 gen_rtx_REG (second_mode,
8119 GEN_INT (second_offset))));
8124 return gen_rtx_REG (mode, reg);
8127 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8128 nonzero when an argument must be passed by reference. */
8131 function_arg_pass_by_reference (cum, mode, type, named)
8132 const CUMULATIVE_ARGS *cum;
8133 enum machine_mode mode;
8135 int named ATTRIBUTE_UNUSED;
8139 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
8142 /* We must pass by reference if we would be both passing in registers
8143 and the stack. This is because any subsequent partial arg would be
8144 handled incorrectly in this case.
8146 ??? This is really a kludge. We should either fix GCC so that such
8147 a situation causes an abort and then do something in the MIPS port
8148 to prevent it, or add code to function.c to properly handle the case. */
8149 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8150 here hopefully is not relevant to mips_va_arg. */
8151 if (cum && MUST_PASS_IN_STACK (mode, type)
8152 && mips_abi != ABI_MEABI
8153 && FUNCTION_ARG (*cum, mode, type, named) != 0)
8156 /* Otherwise, we only do this if EABI is selected. */
8157 if (mips_abi != ABI_EABI)
8160 /* ??? How should SCmode be handled? */
8161 if (type == NULL_TREE || mode == DImode || mode == DFmode)
8164 size = int_size_in_bytes (type);
8165 return size == -1 || size > UNITS_PER_WORD;
8168 /* This function returns the register class required for a secondary
8169 register when copying between one of the registers in CLASS, and X,
8170 using MODE. If IN_P is nonzero, the copy is going from X to the
8171 register, otherwise the register is the source. A return value of
8172 NO_REGS means that no secondary register is required. */
8175 mips_secondary_reload_class (class, mode, x, in_p)
8176 enum reg_class class;
8177 enum machine_mode mode;
8181 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8185 if (GET_CODE (x) == SIGN_EXTEND)
8191 /* We may be called with reg_renumber NULL from regclass.
8192 ??? This is probably a bug. */
8194 regno = true_regnum (x);
8197 while (GET_CODE (x) == SUBREG)
8199 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
8200 GET_MODE (SUBREG_REG (x)),
8206 if (GET_CODE (x) == REG)
8207 regno = REGNO (x) + off;
8211 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
8212 regno = true_regnum (x);
8214 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8216 /* We always require a general register when copying anything to
8217 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8218 to a general register, or when copying from register 0. */
8219 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
8222 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8223 ? NO_REGS : gr_regs);
8224 else if (regno == HILO_REGNUM)
8227 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8228 ? NO_REGS : gr_regs);
8230 /* Copying from HI or LO to anywhere other than a general register
8231 requires a general register. */
8232 if (class == HI_REG || class == LO_REG || class == MD_REGS)
8234 if (TARGET_MIPS16 && in_p)
8236 /* We can't really copy to HI or LO at all in mips16 mode. */
8239 return gp_reg_p ? NO_REGS : gr_regs;
8241 if (MD_REG_P (regno))
8243 if (TARGET_MIPS16 && ! in_p)
8245 /* We can't really copy to HI or LO at all in mips16 mode. */
8248 return class == gr_regs ? NO_REGS : gr_regs;
8251 /* We can only copy a value to a condition code register from a
8252 floating point register, and even then we require a scratch
8253 floating point register. We can only copy a value out of a
8254 condition code register into a general register. */
8255 if (class == ST_REGS)
8259 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8261 if (ST_REG_P (regno))
8265 return class == GR_REGS ? NO_REGS : GR_REGS;
8268 /* In mips16 mode, going between memory and anything but M16_REGS
8269 requires an M16_REG. */
8272 if (class != M16_REGS && class != M16_NA_REGS)
8280 /* The stack pointer isn't a valid operand to an add instruction,
8281 so we need to load it into M16_REGS first. This can happen as
8282 a result of register elimination and form_sum converting
8283 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8284 need an extra register if the dest is the same as the other
8285 register. In that case, we can't fix the problem by loading SP
8286 into the dest first. */
8287 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8288 && GET_CODE (XEXP (x, 1)) == REG
8289 && (XEXP (x, 0) == stack_pointer_rtx
8290 || XEXP (x, 1) == stack_pointer_rtx))
8291 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8293 if (class == M16_REGS || class == M16_NA_REGS)
8302 /* This function returns the maximum number of consecutive registers
8303 needed to represent mode MODE in registers of class CLASS. */
8306 mips_class_max_nregs (class, mode)
8307 enum reg_class class;
8308 enum machine_mode mode;
8310 if (class == FP_REGS)
8313 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8316 /* For each mips16 function which refers to GP relative symbols, we
8317 use a pseudo register, initialized at the start of the function, to
8318 hold the $gp value. */
8321 mips16_gp_pseudo_reg ()
8323 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
8328 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8329 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
8331 /* We want to initialize this to a value which gcc will believe
8333 const_gp = gen_rtx (CONST, Pmode,
8334 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8337 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
8339 insn = gen_sequence ();
8342 push_topmost_sequence ();
8343 /* We need to emit the initialization after the FUNCTION_BEG
8344 note, so that it will be integrated. */
8345 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8346 if (GET_CODE (scan) == NOTE
8347 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8349 if (scan == NULL_RTX)
8350 scan = get_insns ();
8351 insn = emit_insn_after (insn, scan);
8352 pop_topmost_sequence ();
8355 return cfun->machine->mips16_gp_pseudo_rtx;
8358 /* Return an RTX which represents the signed 16 bit offset from the
8359 $gp register for the given symbol. This is only used on the
8363 mips16_gp_offset (sym)
8368 if (GET_CODE (sym) != SYMBOL_REF
8369 || ! SYMBOL_REF_FLAG (sym))
8372 /* We use a special identifier to represent the value of the gp
8374 gp = get_identifier ("__mips16_gp_value");
8376 return gen_rtx (CONST, Pmode,
8377 gen_rtx (MINUS, Pmode, sym,
8378 gen_rtx (SYMBOL_REF, Pmode,
8379 IDENTIFIER_POINTER (gp))));
8382 /* Return nonzero if the given RTX represents a signed 16 bit offset
8383 from the $gp register. */
8386 mips16_gp_offset_p (x)
8389 if (GET_CODE (x) == CONST)
8392 /* It's OK to add a small integer value to a gp offset. */
8393 if (GET_CODE (x) == PLUS)
8395 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8396 && SMALL_INT (XEXP (x, 1)))
8397 return mips16_gp_offset_p (XEXP (x, 0));
8398 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8399 && SMALL_INT (XEXP (x, 0)))
8400 return mips16_gp_offset_p (XEXP (x, 1));
8404 /* Make sure it is in the form SYM - __mips16_gp_value. */
8405 return (GET_CODE (x) == MINUS
8406 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8407 && SYMBOL_REF_FLAG (XEXP (x, 0))
8408 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8409 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8412 /* Output a GP offset. We don't want to print the subtraction of
8413 __mips16_gp_value; it is implicitly represented by the %gprel which
8414 should have been printed by the caller. */
8417 mips16_output_gp_offset (file, x)
8421 if (GET_CODE (x) == CONST)
8424 if (GET_CODE (x) == PLUS)
8426 mips16_output_gp_offset (file, XEXP (x, 0));
8428 mips16_output_gp_offset (file, XEXP (x, 1));
8432 if (GET_CODE (x) == MINUS
8433 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8434 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8436 mips16_output_gp_offset (file, XEXP (x, 0));
8440 output_addr_const (file, x);
8443 /* Return nonzero if a constant should not be output until after the
8444 function. This is true of most string constants, so that we can
8445 use a more efficient PC relative reference. However, a static
8446 inline function may never call assemble_function_end to write out
8447 the constant pool, so don't try to postpone the constant in that
8450 ??? It's really a bug that a static inline function can put stuff
8451 in the constant pool even if the function itself is not output.
8453 We record which string constants we've seen, so that we know which
8454 ones might use the more efficient reference. */
8457 mips16_constant_after_function_p (x)
8460 if (TREE_CODE (x) == STRING_CST
8461 && ! flag_writable_strings
8462 && current_function_decl != 0
8463 && ! DECL_DEFER_OUTPUT (current_function_decl)
8464 && ! (DECL_INLINE (current_function_decl)
8465 && ((! TREE_PUBLIC (current_function_decl)
8466 && ! TREE_ADDRESSABLE (current_function_decl)
8467 && ! flag_keep_inline_functions)
8468 || DECL_EXTERNAL (current_function_decl))))
8470 struct string_constant *n;
8472 n = (struct string_constant *) xmalloc (sizeof *n);
8473 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8474 n->next = string_constants;
8475 string_constants = n;
8483 /* Validate a constant for the mips16. This rejects general symbolic
8484 addresses, which must be loaded from memory. If ADDR is nonzero,
8485 this should reject anything which is not a legal address. If
8486 ADDEND is nonzero, this is being added to something else. */
8489 mips16_constant (x, mode, addr, addend)
8491 enum machine_mode mode;
8495 while (GET_CODE (x) == CONST)
8498 switch (GET_CODE (x))
8504 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8505 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8508 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8510 if (CONSTANT_POOL_ADDRESS_P (x))
8513 /* If we aren't looking for a memory address, we can accept a GP
8514 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8515 knows how to handle this. We can always accept a string
8516 constant, which is the other case in which SYMBOL_REF_FLAG
8520 && SYMBOL_REF_FLAG (x)
8521 && mode == (enum machine_mode) Pmode)
8524 /* We can accept a string constant, which will have
8525 SYMBOL_REF_FLAG set but must be recognized by name to
8526 distinguish from a GP accessible symbol. The name of a
8527 string constant will have been generated by
8528 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8529 if (SYMBOL_REF_FLAG (x))
8531 const char *name = XSTR (x, 0);
8533 return (name[0] == '*'
8534 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8535 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8541 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8546 if (addr && ! addend)
8548 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8551 /* We need to treat $gp as a legitimate constant, because
8552 mips16_gp_pseudo_reg assumes that. */
8553 return REGNO (x) == GP_REG_FIRST + 28;
8557 /* Write out code to move floating point arguments in or out of
8558 general registers. Output the instructions to FILE. FP_CODE is
8559 the code describing which arguments are present (see the comment at
8560 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8561 we are copying from the floating point registers. */
8564 mips16_fp_args (file, fp_code, from_fp_p)
8573 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8574 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8581 gparg = GP_ARG_FIRST;
8582 fparg = FP_ARG_FIRST;
8583 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8587 if ((fparg & 1) != 0)
8589 fprintf (file, "\t%s\t%s,%s\n", s,
8590 reg_names[gparg], reg_names[fparg]);
8592 else if ((f & 3) == 2)
8595 fprintf (file, "\td%s\t%s,%s\n", s,
8596 reg_names[gparg], reg_names[fparg]);
8599 if ((fparg & 1) != 0)
8601 if (TARGET_BIG_ENDIAN)
8602 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8603 reg_names[gparg], reg_names[fparg + 1], s,
8604 reg_names[gparg + 1], reg_names[fparg]);
8606 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8607 reg_names[gparg], reg_names[fparg], s,
8608 reg_names[gparg + 1], reg_names[fparg + 1]);
8621 /* Build a mips16 function stub. This is used for functions which
8622 take aruments in the floating point registers. It is 32 bit code
8623 that moves the floating point args into the general registers, and
8624 then jumps to the 16 bit code. */
8627 build_mips16_function_stub (file)
8631 char *secname, *stubname;
8632 tree stubid, stubdecl;
8636 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8637 secname = (char *) alloca (strlen (fnname) + 20);
8638 sprintf (secname, ".mips16.fn.%s", fnname);
8639 stubname = (char *) alloca (strlen (fnname) + 20);
8640 sprintf (stubname, "__fn_stub_%s", fnname);
8641 stubid = get_identifier (stubname);
8642 stubdecl = build_decl (FUNCTION_DECL, stubid,
8643 build_function_type (void_type_node, NULL_TREE));
8644 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8646 fprintf (file, "\t# Stub function for %s (", current_function_name);
8648 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8650 fprintf (file, "%s%s",
8651 need_comma ? ", " : "",
8652 (f & 3) == 1 ? "float" : "double");
8655 fprintf (file, ")\n");
8657 fprintf (file, "\t.set\tnomips16\n");
8658 function_section (stubdecl);
8659 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8661 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8662 within a .ent, and we can not emit another .ent. */
8663 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8664 fputs ("\t.ent\t", file);
8665 assemble_name (file, stubname);
8669 assemble_name (file, stubname);
8670 fputs (":\n", file);
8672 /* We don't want the assembler to insert any nops here. */
8673 fprintf (file, "\t.set\tnoreorder\n");
8675 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8677 fprintf (asm_out_file, "\t.set\tnoat\n");
8678 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8679 assemble_name (file, fnname);
8680 fprintf (file, "\n");
8681 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8682 fprintf (asm_out_file, "\t.set\tat\n");
8684 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8685 with one of the mfc1 instructions, because the result is not
8686 available for one instruction, so if the very first instruction
8687 in the function refers to the register, it will see the wrong
8689 fprintf (file, "\tnop\n");
8691 fprintf (file, "\t.set\treorder\n");
8693 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8694 fputs ("\t.end\t", file);
8695 assemble_name (file, stubname);
8699 fprintf (file, "\t.set\tmips16\n");
8701 function_section (current_function_decl);
8704 /* We keep a list of functions for which we have already built stubs
8705 in build_mips16_call_stub. */
8709 struct mips16_stub *next;
8714 static struct mips16_stub *mips16_stubs;
8716 /* Build a call stub for a mips16 call. A stub is needed if we are
8717 passing any floating point values which should go into the floating
8718 point registers. If we are, and the call turns out to be to a 32
8719 bit function, the stub will be used to move the values into the
8720 floating point registers before calling the 32 bit function. The
8721 linker will magically adjust the function call to either the 16 bit
8722 function or the 32 bit stub, depending upon where the function call
8723 is actually defined.
8725 Similarly, we need a stub if the return value might come back in a
8726 floating point register.
8728 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8729 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8730 is the code built by function_arg. This function returns a nonzero
8731 value if it builds the call instruction itself. */
8734 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8743 char *secname, *stubname;
8744 struct mips16_stub *l;
8745 tree stubid, stubdecl;
8749 /* We don't need to do anything if we aren't in mips16 mode, or if
8750 we were invoked with the -msoft-float option. */
8751 if (! TARGET_MIPS16 || ! mips16_hard_float)
8754 /* Figure out whether the value might come back in a floating point
8756 fpret = (retval != 0
8757 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8758 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8760 /* We don't need to do anything if there were no floating point
8761 arguments and the value will not be returned in a floating point
8763 if (fp_code == 0 && ! fpret)
8766 if (GET_CODE (fnmem) != MEM)
8768 fn = XEXP (fnmem, 0);
8770 /* We don't need to do anything if this is a call to a special
8771 mips16 support function. */
8772 if (GET_CODE (fn) == SYMBOL_REF
8773 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8776 /* This code will only work for o32 and o64 abis. The other ABI's
8777 require more sophisticated support. */
8778 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8781 /* We can only handle SFmode and DFmode floating point return
8783 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8786 /* If we're calling via a function pointer, then we must always call
8787 via a stub. There are magic stubs provided in libgcc.a for each
8788 of the required cases. Each of them expects the function address
8789 to arrive in register $2. */
8791 if (GET_CODE (fn) != SYMBOL_REF)
8795 rtx stub_fn, stub_mem, insn;
8797 /* ??? If this code is modified to support other ABI's, we need
8798 to handle PARALLEL return values here. */
8800 sprintf (buf, "__mips16_call_stub_%s%d",
8802 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8805 id = get_identifier (buf);
8806 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8807 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8809 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8811 if (retval == NULL_RTX)
8812 insn = gen_call_internal0 (stub_mem, arg_size,
8813 gen_rtx (REG, SImode,
8814 GP_REG_FIRST + 31));
8816 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8817 gen_rtx (REG, SImode,
8818 GP_REG_FIRST + 31));
8819 insn = emit_call_insn (insn);
8821 /* Put the register usage information on the CALL. */
8822 if (GET_CODE (insn) != CALL_INSN)
8824 CALL_INSN_FUNCTION_USAGE (insn) =
8825 gen_rtx (EXPR_LIST, VOIDmode,
8826 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8827 CALL_INSN_FUNCTION_USAGE (insn));
8829 /* If we are handling a floating point return value, we need to
8830 save $18 in the function prologue. Putting a note on the
8831 call will mean that regs_ever_live[$18] will be true if the
8832 call is not eliminated, and we can check that in the prologue
8835 CALL_INSN_FUNCTION_USAGE (insn) =
8836 gen_rtx (EXPR_LIST, VOIDmode,
8837 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8838 CALL_INSN_FUNCTION_USAGE (insn));
8840 /* Return 1 to tell the caller that we've generated the call
8845 /* We know the function we are going to call. If we have already
8846 built a stub, we don't need to do anything further. */
8848 fnname = XSTR (fn, 0);
8849 for (l = mips16_stubs; l != NULL; l = l->next)
8850 if (strcmp (l->name, fnname) == 0)
8855 /* Build a special purpose stub. When the linker sees a
8856 function call in mips16 code, it will check where the target
8857 is defined. If the target is a 32 bit call, the linker will
8858 search for the section defined here. It can tell which
8859 symbol this section is associated with by looking at the
8860 relocation information (the name is unreliable, since this
8861 might be a static function). If such a section is found, the
8862 linker will redirect the call to the start of the magic
8865 If the function does not return a floating point value, the
8866 special stub section is named
8869 If the function does return a floating point value, the stub
8871 .mips16.call.fp.FNNAME
8874 secname = (char *) alloca (strlen (fnname) + 40);
8875 sprintf (secname, ".mips16.call.%s%s",
8878 stubname = (char *) alloca (strlen (fnname) + 20);
8879 sprintf (stubname, "__call_stub_%s%s",
8882 stubid = get_identifier (stubname);
8883 stubdecl = build_decl (FUNCTION_DECL, stubid,
8884 build_function_type (void_type_node, NULL_TREE));
8885 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8887 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8889 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8893 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8895 fprintf (asm_out_file, "%s%s",
8896 need_comma ? ", " : "",
8897 (f & 3) == 1 ? "float" : "double");
8900 fprintf (asm_out_file, ")\n");
8902 fprintf (asm_out_file, "\t.set\tnomips16\n");
8903 assemble_start_function (stubdecl, stubname);
8905 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8906 fputs ("\t.ent\t", asm_out_file);
8907 assemble_name (asm_out_file, stubname);
8908 fputs ("\n", asm_out_file);
8910 assemble_name (asm_out_file, stubname);
8911 fputs (":\n", asm_out_file);
8914 /* We build the stub code by hand. That's the only way we can
8915 do it, since we can't generate 32 bit code during a 16 bit
8918 /* We don't want the assembler to insert any nops here. */
8919 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8921 mips16_fp_args (asm_out_file, fp_code, 0);
8925 fprintf (asm_out_file, "\t.set\tnoat\n");
8926 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8928 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8929 fprintf (asm_out_file, "\t.set\tat\n");
8930 /* Unfortunately, we can't fill the jump delay slot. We
8931 can't fill with one of the mtc1 instructions, because the
8932 result is not available for one instruction, so if the
8933 very first instruction in the function refers to the
8934 register, it will see the wrong value. */
8935 fprintf (asm_out_file, "\tnop\n");
8939 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8940 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8941 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8942 /* As above, we can't fill the delay slot. */
8943 fprintf (asm_out_file, "\tnop\n");
8944 if (GET_MODE (retval) == SFmode)
8945 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8946 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8949 if (TARGET_BIG_ENDIAN)
8951 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8952 reg_names[GP_REG_FIRST + 2],
8953 reg_names[FP_REG_FIRST + 1]);
8954 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8955 reg_names[GP_REG_FIRST + 3],
8956 reg_names[FP_REG_FIRST + 0]);
8960 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8961 reg_names[GP_REG_FIRST + 2],
8962 reg_names[FP_REG_FIRST + 0]);
8963 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8964 reg_names[GP_REG_FIRST + 3],
8965 reg_names[FP_REG_FIRST + 1]);
8968 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8969 /* As above, we can't fill the delay slot. */
8970 fprintf (asm_out_file, "\tnop\n");
8973 fprintf (asm_out_file, "\t.set\treorder\n");
8975 #ifdef ASM_DECLARE_FUNCTION_SIZE
8976 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8979 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8980 fputs ("\t.end\t", asm_out_file);
8981 assemble_name (asm_out_file, stubname);
8982 fputs ("\n", asm_out_file);
8985 fprintf (asm_out_file, "\t.set\tmips16\n");
8987 /* Record this stub. */
8988 l = (struct mips16_stub *) xmalloc (sizeof *l);
8989 l->name = xstrdup (fnname);
8991 l->next = mips16_stubs;
8995 /* If we expect a floating point return value, but we've built a
8996 stub which does not expect one, then we're in trouble. We can't
8997 use the existing stub, because it won't handle the floating point
8998 value. We can't build a new stub, because the linker won't know
8999 which stub to use for the various calls in this object file.
9000 Fortunately, this case is illegal, since it means that a function
9001 was declared in two different ways in a single compilation. */
9002 if (fpret && ! l->fpret)
9003 error ("can not handle inconsistent calls to `%s'", fnname);
9005 /* If we are calling a stub which handles a floating point return
9006 value, we need to arrange to save $18 in the prologue. We do
9007 this by marking the function call as using the register. The
9008 prologue will later see that it is used, and emit code to save
9015 if (retval == NULL_RTX)
9016 insn = gen_call_internal0 (fnmem, arg_size,
9017 gen_rtx (REG, SImode,
9018 GP_REG_FIRST + 31));
9020 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
9021 gen_rtx (REG, SImode,
9022 GP_REG_FIRST + 31));
9023 insn = emit_call_insn (insn);
9025 if (GET_CODE (insn) != CALL_INSN)
9028 CALL_INSN_FUNCTION_USAGE (insn) =
9029 gen_rtx (EXPR_LIST, VOIDmode,
9030 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
9031 CALL_INSN_FUNCTION_USAGE (insn));
9033 /* Return 1 to tell the caller that we've generated the call
9038 /* Return 0 to let the caller generate the call insn. */
9042 /* This function looks through the code for a function, and tries to
9043 optimize the usage of the $gp register. We arrange to copy $gp
9044 into a pseudo-register, and then let gcc's normal reload handling
9045 deal with the pseudo-register. Unfortunately, if reload choose to
9046 put the pseudo-register into a call-clobbered register, it will
9047 emit saves and restores for that register around any function
9048 calls. We don't need the saves, and it's faster to copy $gp than
9049 to do an actual restore. ??? This still means that we waste a
9052 This is an optimization, and the code which gcc has actually
9053 generated is correct, so we do not need to catch all cases. */
9056 mips16_optimize_gp (first)
9059 rtx gpcopy, slot, insn;
9061 /* Look through the instructions. Set GPCOPY to the register which
9062 holds a copy of $gp. Set SLOT to the stack slot where it is
9063 saved. If we find an instruction which sets GPCOPY to anything
9064 other than $gp or SLOT, then we can't use it. If we find an
9065 instruction which sets SLOT to anything other than GPCOPY, we
9070 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9074 if (! INSN_P (insn))
9077 set = PATTERN (insn);
9079 /* We know that all references to memory will be inside a SET,
9080 because there is no other way to access memory on the mips16.
9081 We don't have to worry about a PARALLEL here, because the
9082 mips.md file will never generate them for memory references. */
9083 if (GET_CODE (set) != SET)
9086 if (gpcopy == NULL_RTX
9087 && GET_CODE (SET_SRC (set)) == CONST
9088 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
9089 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
9090 && GET_CODE (SET_DEST (set)) == REG
9091 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
9092 gpcopy = SET_DEST (set);
9093 else if (slot == NULL_RTX
9094 && gpcopy != NULL_RTX
9095 && GET_CODE (SET_DEST (set)) == MEM
9096 && GET_CODE (SET_SRC (set)) == REG
9097 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
9098 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
9102 offset = const0_rtx;
9103 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9104 if (GET_CODE (base) == REG
9105 && (REGNO (base) == STACK_POINTER_REGNUM
9106 || REGNO (base) == FRAME_POINTER_REGNUM))
9107 slot = SET_DEST (set);
9109 else if (gpcopy != NULL_RTX
9110 && (GET_CODE (SET_DEST (set)) == REG
9111 || GET_CODE (SET_DEST (set)) == SUBREG)
9112 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
9113 && (GET_CODE (SET_DEST (set)) != REG
9114 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
9115 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
9116 || ((GET_CODE (SET_SRC (set)) != CONST
9117 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
9118 || (REGNO (XEXP (SET_SRC (set), 0))
9119 != GP_REG_FIRST + 28))
9120 && ! rtx_equal_p (SET_SRC (set), slot))))
9122 else if (slot != NULL_RTX
9123 && GET_CODE (SET_DEST (set)) == MEM
9124 && rtx_equal_p (SET_DEST (set), slot)
9125 && (GET_CODE (SET_SRC (set)) != REG
9126 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
9130 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9131 different optimization. Any time we find a copy of $28 into a
9132 register, followed by an add of a symbol_ref to that register, we
9133 convert it to load the value from the constant table instead.
9134 The copy and add will take six bytes, just as the load and
9135 constant table entry will take six bytes. However, it is
9136 possible that the constant table entry will be shared.
9138 This could be a peephole optimization, but I don't know if the
9139 peephole code can call force_const_mem.
9141 Using the same register for the copy of $28 and the add of the
9142 symbol_ref is actually pretty likely, since the add instruction
9143 requires the destination and the first addend to be the same
9146 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
9150 /* This optimization is only reasonable if the constant table
9151 entries are only 4 bytes. */
9152 if (Pmode != SImode)
9155 for (insn = first; insn != NULL_RTX; insn = next)
9162 next = NEXT_INSN (next);
9164 while (next != NULL_RTX
9165 && (GET_CODE (next) == NOTE
9166 || (GET_CODE (next) == INSN
9167 && (GET_CODE (PATTERN (next)) == USE
9168 || GET_CODE (PATTERN (next)) == CLOBBER))));
9170 if (next == NULL_RTX)
9173 if (! INSN_P (insn))
9176 if (! INSN_P (next))
9179 set1 = PATTERN (insn);
9180 if (GET_CODE (set1) != SET)
9182 set2 = PATTERN (next);
9183 if (GET_CODE (set2) != SET)
9186 if (GET_CODE (SET_DEST (set1)) == REG
9187 && GET_CODE (SET_SRC (set1)) == CONST
9188 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
9189 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
9190 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
9191 && GET_CODE (SET_SRC (set2)) == PLUS
9192 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
9193 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
9194 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
9198 /* We've found a case we can change to load from the
9201 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
9202 if (GET_CODE (sym) != SYMBOL_REF)
9204 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
9205 force_const_mem (Pmode, sym)),
9208 PUT_CODE (insn, NOTE);
9209 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9210 NOTE_SOURCE_FILE (insn) = 0;
9212 PUT_CODE (next, NOTE);
9213 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
9214 NOTE_SOURCE_FILE (next) = 0;
9221 /* We can safely remove all assignments to SLOT from GPCOPY, and
9222 replace all assignments from SLOT to GPCOPY with assignments from
9225 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9229 if (! INSN_P (insn))
9232 set = PATTERN (insn);
9233 if (GET_CODE (set) != SET
9234 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
9237 if (GET_CODE (SET_DEST (set)) == MEM
9238 && rtx_equal_p (SET_DEST (set), slot)
9239 && GET_CODE (SET_SRC (set)) == REG
9240 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
9242 PUT_CODE (insn, NOTE);
9243 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9244 NOTE_SOURCE_FILE (insn) = 0;
9246 else if (GET_CODE (SET_DEST (set)) == REG
9247 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9248 && GET_CODE (SET_SRC (set)) == MEM
9249 && rtx_equal_p (SET_SRC (set), slot))
9251 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
9252 gen_rtx (CONST, Pmode,
9253 gen_rtx (REG, Pmode,
9254 GP_REG_FIRST + 28))),
9256 PUT_CODE (insn, NOTE);
9257 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9258 NOTE_SOURCE_FILE (insn) = 0;
9263 /* We keep a list of constants we which we have to add to internal
9264 constant tables in the middle of large functions. */
9268 struct constant *next;
9271 enum machine_mode mode;
9274 /* Add a constant to the list in *PCONSTANTS. */
9277 add_constant (pconstants, val, mode)
9278 struct constant **pconstants;
9280 enum machine_mode mode;
9284 for (c = *pconstants; c != NULL; c = c->next)
9285 if (mode == c->mode && rtx_equal_p (val, c->value))
9288 c = (struct constant *) xmalloc (sizeof *c);
9291 c->label = gen_label_rtx ();
9292 c->next = *pconstants;
9297 /* Dump out the constants in CONSTANTS after INSN. */
9300 dump_constants (constants, insn)
9301 struct constant *constants;
9312 struct constant *next;
9314 switch (GET_MODE_SIZE (c->mode))
9321 insn = emit_insn_after (gen_align_2 (), insn);
9326 insn = emit_insn_after (gen_align_4 (), insn);
9331 insn = emit_insn_after (gen_align_8 (), insn);
9336 insn = emit_label_after (c->label, insn);
9341 r = gen_consttable_qi (c->value);
9344 r = gen_consttable_hi (c->value);
9347 r = gen_consttable_si (c->value);
9350 r = gen_consttable_sf (c->value);
9353 r = gen_consttable_di (c->value);
9356 r = gen_consttable_df (c->value);
9362 insn = emit_insn_after (r, insn);
9369 emit_barrier_after (insn);
9372 /* Find the symbol in an address expression. */
9375 mips_find_symbol (addr)
9378 if (GET_CODE (addr) == MEM)
9379 addr = XEXP (addr, 0);
9380 while (GET_CODE (addr) == CONST)
9381 addr = XEXP (addr, 0);
9382 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9384 if (GET_CODE (addr) == PLUS)
9388 l1 = mips_find_symbol (XEXP (addr, 0));
9389 l2 = mips_find_symbol (XEXP (addr, 1));
9390 if (l1 != NULL_RTX && l2 == NULL_RTX)
9392 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9398 /* Exported to toplev.c.
9400 Do a final pass over the function, just before delayed branch
9404 machine_dependent_reorg (first)
9407 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9409 struct constant *constants;
9411 if (! TARGET_MIPS16)
9414 /* If $gp is used, try to remove stores, and replace loads with
9417 mips16_optimize_gp (first);
9419 /* Scan the function looking for PC relative loads which may be out
9420 of range. All such loads will either be from the constant table,
9421 or be getting the address of a constant string. If the size of
9422 the function plus the size of the constant table is less than
9423 0x8000, then all loads are in range. */
9426 for (insn = first; insn; insn = NEXT_INSN (insn))
9428 insns_len += get_attr_length (insn);
9430 /* ??? We put switch tables in .text, but we don't define
9431 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9432 compute their lengths correctly. */
9433 if (GET_CODE (insn) == JUMP_INSN)
9437 body = PATTERN (insn);
9438 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9439 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9440 * GET_MODE_SIZE (GET_MODE (body)));
9441 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9445 /* Store the original value of insns_len in current_frame_info, so
9446 that simple_memory_operand can look at it. */
9447 current_frame_info.insns_len = insns_len;
9449 pool_size = get_pool_size ();
9450 if (insns_len + pool_size + mips_string_length < 0x8000)
9453 /* Loop over the insns and figure out what the maximum internal pool
9455 max_internal_pool_size = 0;
9456 for (insn = first; insn; insn = NEXT_INSN (insn))
9458 if (GET_CODE (insn) == INSN
9459 && GET_CODE (PATTERN (insn)) == SET)
9463 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9464 if (src == NULL_RTX)
9466 if (CONSTANT_POOL_ADDRESS_P (src))
9467 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9468 else if (SYMBOL_REF_FLAG (src))
9469 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9475 first_constant_ref = -1;
9477 for (insn = first; insn; insn = NEXT_INSN (insn))
9479 if (GET_CODE (insn) == INSN
9480 && GET_CODE (PATTERN (insn)) == SET)
9483 enum machine_mode mode = VOIDmode;
9486 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9487 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9489 /* ??? This is very conservative, which means that we
9490 will generate too many copies of the constant table.
9491 The only solution would seem to be some form of
9493 if (((insns_len - addr)
9494 + max_internal_pool_size
9495 + get_pool_offset (src))
9498 val = get_pool_constant (src);
9499 mode = get_pool_mode (src);
9501 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9503 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9505 /* Including all of mips_string_length is conservative,
9506 and so is including all of max_internal_pool_size. */
9507 if (((insns_len - addr)
9508 + max_internal_pool_size
9510 + mips_string_length)
9516 max_internal_pool_size -= Pmode;
9519 if (val != NULL_RTX)
9523 /* This PC relative load is out of range. ??? In the
9524 case of a string constant, we are only guessing that
9525 it is range, since we don't know the offset of a
9526 particular string constant. */
9528 lab = add_constant (&constants, val, mode);
9529 newsrc = gen_rtx (MEM, mode,
9530 gen_rtx (LABEL_REF, VOIDmode, lab));
9531 RTX_UNCHANGING_P (newsrc) = 1;
9532 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9533 SET_DEST (PATTERN (insn)),
9535 INSN_CODE (insn) = -1;
9537 if (first_constant_ref < 0)
9538 first_constant_ref = addr;
9542 addr += get_attr_length (insn);
9544 /* ??? We put switch tables in .text, but we don't define
9545 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9546 compute their lengths correctly. */
9547 if (GET_CODE (insn) == JUMP_INSN)
9551 body = PATTERN (insn);
9552 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9553 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9554 * GET_MODE_SIZE (GET_MODE (body)));
9555 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9558 if (GET_CODE (insn) == BARRIER)
9560 /* Output any constants we have accumulated. Note that we
9561 don't need to change ADDR, since its only use is
9562 subtraction from INSNS_LEN, and both would be changed by
9564 ??? If the instructions up to the next barrier reuse a
9565 constant, it would often be better to continue
9567 if (constants != NULL)
9568 dump_constants (constants, insn);
9570 first_constant_ref = -1;
9573 if (constants != NULL
9574 && (NEXT_INSN (insn) == NULL
9575 || (first_constant_ref >= 0
9576 && (((addr - first_constant_ref)
9577 + 2 /* for alignment */
9578 + 2 /* for a short jump insn */
9582 /* If we haven't had a barrier within 0x8000 bytes of a
9583 constant reference or we are at the end of the function,
9584 emit a barrier now. */
9586 rtx label, jump, barrier;
9588 label = gen_label_rtx ();
9589 jump = emit_jump_insn_after (gen_jump (label), insn);
9590 JUMP_LABEL (jump) = label;
9591 LABEL_NUSES (label) = 1;
9592 barrier = emit_barrier_after (jump);
9593 emit_label_after (label, barrier);
9594 first_constant_ref = -1;
9598 /* ??? If we output all references to a constant in internal
9599 constants table, we don't need to output the constant in the real
9600 constant table, but we have no way to prevent that. */
9603 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9605 extend_operator (x, mode)
9607 enum machine_mode mode ATTRIBUTE_UNUSED;
9609 enum rtx_code code = GET_CODE (x);
9610 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9613 /* Accept any operator that can be used to shift the high half of the
9614 input value to the lower half, suitable for truncation. The
9615 remainder (the lower half of the input, and the upper half of the
9616 output) will be discarded. */
9618 highpart_shift_operator (x, mode)
9620 enum machine_mode mode ATTRIBUTE_UNUSED;
9622 enum rtx_code code = GET_CODE (x);
9623 return (code == LSHIFTRT
9629 /* Return a number assessing the cost of moving a register in class
9630 FROM to class TO. The classes are expressed using the enumeration
9631 values such as `GENERAL_REGS'. A value of 2 is the default; other
9632 values are interpreted relative to that.
9634 It is not required that the cost always equal 2 when FROM is the
9635 same as TO; on some machines it is expensive to move between
9636 registers if they are not general registers.
9638 If reload sees an insn consisting of a single `set' between two
9639 hard registers, and if `REGISTER_MOVE_COST' applied to their
9640 classes returns a value of 2, reload does not check to ensure that
9641 the constraints of the insn are met. Setting a cost of other than
9642 2 will allow reload to verify that the constraints are met. You
9643 should do this if the `movM' pattern's constraints do not allow
9646 ??? We make make the cost of moving from HI/LO/HILO/MD into general
9647 registers the same as for one of moving general registers to
9648 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
9649 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
9650 isn't clear if it is wise. And it might not work in all cases. We
9651 could solve the DImode LO reg problem by using a multiply, just
9652 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9653 problem by using divide instructions. divu puts the remainder in
9654 the HI reg, so doing a divide by -1 will move the value in the HI
9655 reg for all values except -1. We could handle that case by using a
9656 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9657 a compare/branch to test the input value to see which instruction
9658 we need to use. This gets pretty messy, but it is feasible. */
9661 mips_register_move_cost (mode, to, from)
9662 enum machine_mode mode ATTRIBUTE_UNUSED;
9663 enum reg_class to, from;
9665 if (from == M16_REGS && GR_REG_CLASS_P (to))
9667 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9669 else if (GR_REG_CLASS_P (from))
9673 else if (to == M16_NA_REGS)
9675 else if (GR_REG_CLASS_P (to))
9682 else if (to == FP_REGS)
9684 else if (to == HI_REG || to == LO_REG || to == MD_REGS
9692 else if (COP_REG_CLASS_P (to))
9696 } /* GR_REG_CLASS_P (from) */
9697 else if (from == FP_REGS)
9699 if (GR_REG_CLASS_P (to))
9701 else if (to == FP_REGS)
9703 else if (to == ST_REGS)
9705 } /* from == FP_REGS */
9706 else if (from == HI_REG || from == LO_REG || from == MD_REGS
9707 || from == HILO_REG)
9709 if (GR_REG_CLASS_P (to))
9716 } /* from == HI_REG, etc. */
9717 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9719 else if (COP_REG_CLASS_P (from))
9722 } /* COP_REG_CLASS_P (from) */
9729 /* Return the length of INSN. LENGTH is the initial length computed by
9730 attributes in the machine-description file. */
9733 mips_adjust_insn_length (insn, length)
9737 /* A unconditional jump has an unfilled delay slot if it is not part
9738 of a sequence. A conditional jump normally has a delay slot, but
9739 does not on MIPS16. */
9740 if (simplejump_p (insn)
9741 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9742 || GET_CODE (insn) == CALL_INSN)))
9745 /* All MIPS16 instructions are a measly two bytes. */
9752 /* Output assembly instructions to peform a conditional branch.
9754 INSN is the branch instruction. OPERANDS[0] is the condition.
9755 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9756 of the first operand to the condition. If TWO_OPERANDS_P is
9757 non-zero the comparison takes two operands; OPERANDS[3] will be the
9760 If INVERTED_P is non-zero we are to branch if the condition does
9761 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9763 LENGTH is the length (in bytes) of the sequence we are to generate.
9764 That tells us whether to generate a simple conditional branch, or a
9765 reversed conditional branch around a `jr' instruction. */
9767 mips_output_conditional_branch (insn,
9780 static char buffer[200];
9781 /* The kind of comparison we are doing. */
9782 enum rtx_code code = GET_CODE (operands[0]);
9783 /* Non-zero if the opcode for the comparison needs a `z' indicating
9784 that it is a comparision against zero. */
9786 /* A string to use in the assembly output to represent the first
9788 const char *op1 = "%z2";
9789 /* A string to use in the assembly output to represent the second
9790 operand. Use the hard-wired zero register if there's no second
9792 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9793 /* The operand-printing string for the comparison. */
9794 const char *const comp = (float_p ? "%F0" : "%C0");
9795 /* The operand-printing string for the inverted comparison. */
9796 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9798 /* The MIPS processors (for levels of the ISA at least two), have
9799 "likely" variants of each branch instruction. These instructions
9800 annul the instruction in the delay slot if the branch is not
9802 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9804 if (!two_operands_p)
9806 /* To compute whether than A > B, for example, we normally
9807 subtract B from A and then look at the sign bit. But, if we
9808 are doing an unsigned comparison, and B is zero, we don't
9809 have to do the subtraction. Instead, we can just check to
9810 see if A is non-zero. Thus, we change the CODE here to
9811 reflect the simpler comparison operation. */
9823 /* A condition which will always be true. */
9829 /* A condition which will always be false. */
9835 /* Not a special case. */
9840 /* Relative comparisons are always done against zero. But
9841 equality comparisons are done between two operands, and therefore
9842 do not require a `z' in the assembly language output. */
9843 need_z_p = (!float_p && code != EQ && code != NE);
9844 /* For comparisons against zero, the zero is not provided
9849 /* Begin by terminating the buffer. That way we can always use
9850 strcat to add to it. */
9857 /* Just a simple conditional branch. */
9859 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9860 inverted_p ? inverted_comp : comp);
9862 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9863 inverted_p ? inverted_comp : comp,
9864 need_z_p ? "z" : "",
9872 /* Generate a reversed conditional branch around ` j'
9887 rtx target = gen_label_rtx ();
9889 output_asm_insn ("%(%<", 0);
9890 orig_target = operands[1];
9891 operands[1] = target;
9892 /* Generate the reversed comparison. This takes four
9895 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9896 inverted_p ? comp : inverted_comp);
9898 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9899 inverted_p ? comp : inverted_comp,
9900 need_z_p ? "z" : "",
9903 output_asm_insn (buffer, operands);
9904 operands[1] = orig_target;
9906 output_asm_insn ("nop\n\tj\t%1", operands);
9909 output_asm_insn ("nop", 0);
9912 /* Output delay slot instruction. */
9913 rtx insn = final_sequence;
9914 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9916 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9918 output_asm_insn ("%>%)", 0);
9919 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
9920 CODE_LABEL_NUMBER (target));
9924 /* We do not currently use this code. It handles jumps to
9925 arbitrary locations, using `jr', even across a 256MB boundary.
9926 We could add a -mhuge switch, and then use this code instead of
9927 the `j' alternative above when -mhuge was used. */
9932 /* Generate a reversed conditional branch around a `jr'
9946 Not pretty, but allows a conditional branch anywhere in the
9947 32-bit address space. If the original branch is annulled,
9948 then the instruction in the delay slot should be executed
9949 only if the branch is taken. The la instruction is really
9950 a macro which will usually take eight bytes, but sometimes
9951 takes only four, if the instruction to which we're jumping
9952 gets its own entry in the global pointer table, which will
9953 happen if its a case label. The assembler will then
9954 generate only a four-byte sequence, rather than eight, and
9955 there seems to be no way to tell it not to. Thus, we can't
9956 just use a `.+x' addressing form; we don't know what value
9959 So, we resort to using the explicit relocation syntax
9960 available in the assembler and do:
9962 lw $at,%got_page(target)($gp)
9963 daddiu $at,$at,%got_ofst(target)
9965 That way, this always takes up eight bytes, and we can use
9966 the `.+x' form. Of course, these explicit machinations
9967 with relocation will not work with old assemblers. Then
9968 again, neither do out-of-range branches, so we haven't lost
9971 /* The target of the reversed branch. */
9972 const char *const target
9973 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9974 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9975 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9978 strcpy (buffer, "%(%<%[");
9979 c = strchr (buffer, '\0');
9980 /* Generate the reversed comparision. This takes four
9983 sprintf (c, "%%*b%s\t%%Z2%s",
9984 inverted_p ? comp : inverted_comp,
9987 sprintf (c, "%%*b%s%s\t%s%s,%s",
9988 inverted_p ? comp : inverted_comp,
9989 need_z_p ? "z" : "",
9993 c = strchr (buffer, '\0');
9994 /* Generate the load-address, and jump. This takes twelve
9995 bytes, for a total of 16. */
9997 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
10004 /* The delay slot was unfilled. Since we're inside
10005 .noreorder, the assembler will not fill in the NOP for
10006 us, so we must do it ourselves. */
10007 strcat (buffer, "\n\tnop");
10008 strcat (buffer, "%]%>%)");
10021 /* Called to register all of our global variables with the garbage
10025 mips_add_gc_roots ()
10027 ggc_add_rtx_root (&mips_load_reg, 1);
10028 ggc_add_rtx_root (&mips_load_reg2, 1);
10029 ggc_add_rtx_root (&mips_load_reg3, 1);
10030 ggc_add_rtx_root (&mips_load_reg4, 1);
10031 ggc_add_rtx_root (branch_cmp, ARRAY_SIZE (branch_cmp));
10034 static enum processor_type
10035 mips_parse_cpu (cpu_string)
10036 const char *cpu_string;
10038 const char *p = cpu_string;
10040 enum processor_type cpu;
10041 int warn_upper_case = 0;
10043 /* We need to cope with the various "vr" prefixes for the NEC 4300
10044 and 4100 processors. */
10045 if (*p == 'v' || *p == 'V')
10048 warn_upper_case = 1;
10052 if (*p == 'r' || *p == 'R')
10055 warn_upper_case = 1;
10059 if (warn_upper_case)
10060 warning ("the cpu name must be lower case");
10062 /* Since there is no difference between a R2000 and R3000 in
10063 terms of the scheduler, we collapse them into just an R3000. */
10065 cpu = PROCESSOR_DEFAULT;
10069 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
10070 cpu = PROCESSOR_R3000;
10071 else if (!strcmp (p, "20kc") || !strcmp (p, "20Kc") )
10072 cpu = PROCESSOR_R20KC;
10076 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
10077 cpu = PROCESSOR_R3000;
10078 else if (!strcmp (p, "3900"))
10079 cpu = PROCESSOR_R3900;
10083 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
10084 cpu = PROCESSOR_R4000;
10085 /* The vr4100 is a non-FP ISA III processor with some extra
10087 else if (!strcmp (p, "4100"))
10088 cpu = PROCESSOR_R4100;
10089 /* The vr4300 is a standard ISA III processor, but with a different
10091 else if (!strcmp (p, "4300"))
10092 cpu = PROCESSOR_R4300;
10093 /* The r4400 is exactly the same as the r4000 from the compiler's
10095 else if (!strcmp (p, "4400"))
10096 cpu = PROCESSOR_R4000;
10097 else if (!strcmp (p, "4600"))
10098 cpu = PROCESSOR_R4600;
10099 else if (!strcmp (p, "4650"))
10100 cpu = PROCESSOR_R4650;
10101 /* The 4kc and 4kp processor cores are the same for
10102 scheduling purposes; they both implement the MIPS32
10103 ISA and only differ in their memory management
10105 else if (!strcmp (p, "4kc") || !strcmp (p, "4Kc")
10106 || !strcmp (p, "4kp") || !strcmp (p, "4Kp") )
10107 cpu = PROCESSOR_R4KC;
10111 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
10112 cpu = PROCESSOR_R5000;
10113 else if (!strcmp (p, "5kc") || !strcmp (p, "5Kc") )
10114 cpu = PROCESSOR_R5KC;
10118 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
10119 cpu = PROCESSOR_R6000;
10123 if (!strcmp (p, "8000"))
10124 cpu = PROCESSOR_R8000;
10128 if (!strcmp (p, "orion"))
10129 cpu = PROCESSOR_R4600;
10134 && cpu != PROCESSOR_R4300
10135 && cpu != PROCESSOR_R4100
10136 && cpu != PROCESSOR_R5000)
10137 cpu = PROCESSOR_DEFAULT;
10142 /* Adjust the cost of INSN based on the relationship between INSN that
10143 is dependent on DEP_INSN through the dependence LINK. The default
10144 is to make no adjustment to COST.
10146 On the MIPS, ignore the cost of anti- and output-dependencies. */
10148 mips_adjust_cost (insn, link, dep, cost)
10149 rtx insn ATTRIBUTE_UNUSED;
10151 rtx dep ATTRIBUTE_UNUSED;
10154 if (REG_NOTE_KIND (link) != 0)
10155 return 0; /* Anti or output dependence. */
10159 /* ??? This could be replaced with the default elf version if
10160 TARGET_IS_SMALL_DATA_P is set properly. */
10163 mips_unique_section (decl, reloc)
10167 int len, size, sec;
10168 const char *name, *prefix;
10170 static const char *const prefixes[4][2] = {
10171 { ".text.", ".gnu.linkonce.t." },
10172 { ".rodata.", ".gnu.linkonce.r." },
10173 { ".data.", ".gnu.linkonce.d." },
10174 { ".sdata.", ".gnu.linkonce.s." }
10177 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10178 size = int_size_in_bytes (TREE_TYPE (decl));
10179 STRIP_NAME_ENCODING (name, name);
10181 /* Determine the base section we are interested in:
10182 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
10183 if (TREE_CODE (decl) == FUNCTION_DECL)
10185 else if (DECL_INITIAL (decl) == 0
10186 || DECL_INITIAL (decl) == error_mark_node)
10188 else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
10189 && TREE_CODE (decl) == STRING_CST
10190 && !flag_writable_strings)
10192 /* For embedded position independent code, put constant
10193 strings in the text section, because the data section
10194 is limited to 64K in size. For mips16 code, put
10195 strings in the text section so that a PC relative load
10196 instruction can be used to get their address. */
10199 else if (TARGET_EMBEDDED_DATA)
10201 /* For embedded applications, always put an object in
10202 read-only data if possible, in order to reduce RAM
10205 if (DECL_READONLY_SECTION (decl, reloc))
10207 else if (size > 0 && size <= mips_section_threshold)
10214 /* For hosted applications, always put an object in
10215 small data if possible, as this gives the best
10218 if (size > 0 && size <= mips_section_threshold)
10220 else if (DECL_READONLY_SECTION (decl, reloc))
10226 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
10227 len = strlen (name) + strlen (prefix);
10228 string = alloca (len + 1);
10229 sprintf (string, "%s%s", prefix, name);
10231 DECL_SECTION_NAME (decl) = build_string (len, string);
10235 mips_hard_regno_nregs (regno, mode)
10237 enum machine_mode mode;
10239 if (! FP_REG_P (regno))
10240 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10242 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10246 mips_return_in_memory (type)
10249 /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
10250 returned in memory. Under the new (N32 and 64-bit MIPS ABIs) small
10251 structures are returned in a register. Objects with varying size
10252 must still be returned in memory, of course. */
10254 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
10255 return (TYPE_MODE (type) == BLKmode);
10257 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
10258 || (int_size_in_bytes (type) == -1));
10268 case PROCESSOR_R3000:
10281 #ifdef TARGET_IRIX6
10282 /* Output assembly to switch to section NAME with attribute FLAGS. */
10285 iris6_asm_named_section_1 (name, flags, align)
10287 unsigned int flags;
10288 unsigned int align;
10290 unsigned int sh_type, sh_flags, sh_entsize;
10293 if (!(flags & SECTION_DEBUG))
10294 sh_flags |= 2; /* SHF_ALLOC */
10295 if (flags & SECTION_WRITE)
10296 sh_flags |= 1; /* SHF_WRITE */
10297 if (flags & SECTION_CODE)
10298 sh_flags |= 4; /* SHF_EXECINSTR */
10299 if (flags & SECTION_SMALL)
10300 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
10301 if (strcmp (name, ".debug_frame") == 0)
10302 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
10303 if (flags & SECTION_DEBUG)
10304 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
10305 else if (flags & SECTION_BSS)
10306 sh_type = 8; /* SHT_NOBITS */
10308 sh_type = 1; /* SHT_PROGBITS */
10310 if (flags & SECTION_CODE)
10315 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
10316 name, sh_type, sh_flags, sh_entsize, align);
10320 iris6_asm_named_section (name, flags)
10322 unsigned int flags;
10324 if (TARGET_FILE_SWITCHING && (flags & SECTION_CODE))
10325 asm_out_file = asm_out_text_file;
10326 iris6_asm_named_section_1 (name, flags, 0);
10329 /* In addition to emitting a .align directive, record the maximum
10330 alignment requested for the current section. */
10332 struct iris_section_align_entry
10336 unsigned int flags;
10339 static htab_t iris_section_align_htab;
10340 static FILE *iris_orig_asm_out_file;
10343 iris_section_align_entry_eq (p1, p2)
10347 const struct iris_section_align_entry *old = p1;
10348 const char *new = p2;
10350 return strcmp (old->name, new) == 0;
10354 iris_section_align_entry_hash (p)
10357 const struct iris_section_align_entry *old = p;
10358 return htab_hash_string (old->name);
10362 iris6_asm_output_align (file, log)
10366 const char *section = current_section_name ();
10367 struct iris_section_align_entry **slot, *entry;
10372 slot = (struct iris_section_align_entry **)
10373 htab_find_slot_with_hash (iris_section_align_htab, section,
10374 htab_hash_string (section), INSERT);
10378 entry = (struct iris_section_align_entry *)
10379 xmalloc (sizeof (struct iris_section_align_entry));
10381 entry->name = section;
10383 entry->flags = current_section_flags ();
10385 else if (entry->log < log)
10388 fprintf (file, "\t.align\t%u\n", log);
10391 /* The Iris assembler does not record alignment from .align directives,
10392 but takes it from the first .section directive seen. Play yet more
10393 file switching games so that we can emit a .section directive at the
10394 beginning of the file with the proper alignment attached. */
10397 iris6_asm_file_start (stream)
10400 mips_asm_file_start (stream);
10402 iris_orig_asm_out_file = asm_out_file;
10403 stream = tmpfile ();
10404 asm_out_file = stream;
10405 asm_out_data_file = stream;
10406 if (! TARGET_FILE_SWITCHING)
10407 asm_out_text_file = stream;
10409 iris_section_align_htab = htab_create (31, iris_section_align_entry_hash,
10410 iris_section_align_entry_eq, NULL);
10414 iris6_section_align_1 (slot, data)
10416 void *data ATTRIBUTE_UNUSED;
10418 const struct iris_section_align_entry *entry
10419 = *(const struct iris_section_align_entry **) slot;
10421 iris6_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
10426 iris6_asm_file_end (stream)
10429 /* Emit section directives with the proper alignment at the top of the
10430 real output file. */
10431 asm_out_file = iris_orig_asm_out_file;
10432 htab_traverse (iris_section_align_htab, iris6_section_align_1, NULL);
10434 /* Copy the data emitted to the temp file to the real output file. */
10435 copy_file_data (asm_out_file, stream);
10437 mips_asm_file_end (stream);
10439 #endif /* TARGET_IRIX6 */