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* doc/extend.texi (MIPS DSP Built-in Functions): Document the DSP
[pf3gnuchains/gcc-fork.git] / gcc / config / mips / mips-dspr2.md
1 ; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
2
3 (define_insn "mips_absq_s_qb"
4   [(parallel
5     [(set (match_operand:V4QI 0 "register_operand" "=d")
6           (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
7                        UNSPEC_ABSQ_S_QB))
8      (set (reg:CCDSP CCDSP_OU_REGNUM)
9           (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
10   "TARGET_DSPR2"
11   "absq_s.qb\t%0,%z1"
12   [(set_attr "type"     "arith")
13    (set_attr "mode"     "SI")])
14
15 (define_insn "mips_addu_ph"
16   [(parallel
17     [(set (match_operand:V2HI 0 "register_operand" "=d")
18           (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
19                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
20      (set (reg:CCDSP CCDSP_OU_REGNUM)
21           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
22   "TARGET_DSPR2"
23   "addu.ph\t%0,%z1,%z2"
24   [(set_attr "type"     "arith")
25    (set_attr "mode"     "SI")])
26
27 (define_insn "mips_addu_s_ph"
28   [(parallel
29     [(set (match_operand:V2HI 0 "register_operand" "=d")
30           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
31                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
32                        UNSPEC_ADDU_S_PH))
33      (set (reg:CCDSP CCDSP_OU_REGNUM)
34           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
35   "TARGET_DSPR2"
36   "addu_s.ph\t%0,%z1,%z2"
37   [(set_attr "type"     "arith")
38    (set_attr "mode"     "SI")])
39
40 (define_insn "mips_adduh_qb"
41   [(set (match_operand:V4QI 0 "register_operand" "=d")
42         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
43                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
44                      UNSPEC_ADDUH_QB))]
45   "TARGET_DSPR2"
46   "adduh.qb\t%0,%z1,%z2"
47   [(set_attr "type"     "arith")
48    (set_attr "mode"     "SI")])
49
50 (define_insn "mips_adduh_r_qb"
51   [(set (match_operand:V4QI 0 "register_operand" "=d")
52         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
53                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
54                      UNSPEC_ADDUH_R_QB))]
55   "TARGET_DSPR2"
56   "adduh_r.qb\t%0,%z1,%z2"
57   [(set_attr "type"     "arith")
58    (set_attr "mode"     "SI")])
59
60 (define_insn "mips_append"
61   [(set (match_operand:SI 0 "register_operand" "=d")
62         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
63                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
64                     (match_operand:SI 3 "const_int_operand" "n")]
65                    UNSPEC_APPEND))]
66   "TARGET_DSPR2"
67 {
68   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
69     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
70   return "append\t%0,%z2,%3";
71 }
72   [(set_attr "type"     "arith")
73    (set_attr "mode"     "SI")])
74
75 (define_insn "mips_balign"
76   [(set (match_operand:SI 0 "register_operand" "=d")
77         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
78                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
79                     (match_operand:SI 3 "const_int_operand" "n")]
80                    UNSPEC_BALIGN))]
81   "TARGET_DSPR2"
82 {
83   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
84     operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
85   return "balign\t%0,%z2,%3";
86 }
87   [(set_attr "type"     "arith")
88    (set_attr "mode"     "SI")])
89
90 (define_insn "mips_cmpgdu_eq_qb"
91   [(parallel
92     [(set (match_operand:SI 0 "register_operand" "=d")
93           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
94                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
95                      UNSPEC_CMPGDU_EQ_QB))
96      (set (reg:CCDSP CCDSP_CC_REGNUM)
97           (unspec:CCDSP [(match_dup 1) (match_dup 2)
98                          (reg:CCDSP CCDSP_CC_REGNUM)]
99                         UNSPEC_CMPGDU_EQ_QB))])]
100   "TARGET_DSPR2"
101   "cmpgdu.eq.qb\t%0,%z1,%z2"
102   [(set_attr "type"     "arith")
103    (set_attr "mode"     "SI")])
104
105 (define_insn "mips_cmpgdu_lt_qb"
106   [(parallel
107     [(set (match_operand:SI 0 "register_operand" "=d")
108           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
109                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
110                      UNSPEC_CMPGDU_LT_QB))
111      (set (reg:CCDSP CCDSP_CC_REGNUM)
112           (unspec:CCDSP [(match_dup 1) (match_dup 2)
113                          (reg:CCDSP CCDSP_CC_REGNUM)]
114                         UNSPEC_CMPGDU_LT_QB))])]
115   "TARGET_DSPR2"
116   "cmpgdu.lt.qb\t%0,%z1,%z2"
117   [(set_attr "type"     "arith")
118    (set_attr "mode"     "SI")])
119
120 (define_insn "mips_cmpgdu_le_qb"
121   [(parallel
122     [(set (match_operand:SI 0 "register_operand" "=d")
123           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
124                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
125                      UNSPEC_CMPGDU_LE_QB))
126      (set (reg:CCDSP CCDSP_CC_REGNUM)
127           (unspec:CCDSP [(match_dup 1) (match_dup 2)
128                          (reg:CCDSP CCDSP_CC_REGNUM)]
129                         UNSPEC_CMPGDU_LE_QB))])]
130   "TARGET_DSPR2"
131   "cmpgdu.le.qb\t%0,%z1,%z2"
132   [(set_attr "type"     "arith")
133    (set_attr "mode"     "SI")])
134
135 (define_insn "mips_dpa_w_ph"
136   [(set (match_operand:DI 0 "register_operand" "=a")
137         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
138                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
139                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
140                    UNSPEC_DPA_W_PH))]
141   "TARGET_DSPR2 && !TARGET_64BIT"
142   "dpa.w.ph\t%q0,%z2,%z3"
143   [(set_attr "type"     "imadd")
144    (set_attr "mode"     "SI")])
145
146 (define_insn "mips_dps_w_ph"
147   [(set (match_operand:DI 0 "register_operand" "=a")
148         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
149                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
150                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
151                    UNSPEC_DPS_W_PH))]
152   "TARGET_DSPR2 && !TARGET_64BIT"
153   "dps.w.ph\t%q0,%z2,%z3"
154   [(set_attr "type"     "imadd")
155    (set_attr "mode"     "SI")])
156
157 (define_insn "mips_madd"
158   [(set (match_operand:DI 0 "register_operand" "=a")
159         (plus:DI
160          (mult:DI (sign_extend:DI
161                    (match_operand:SI 2 "register_operand" "d"))
162                   (sign_extend:DI
163                    (match_operand:SI 3 "register_operand" "d")))
164          (match_operand:DI 1 "register_operand" "0")))]
165   "TARGET_DSPR2 && !TARGET_64BIT"
166   "madd\t%q0,%2,%3"
167   [(set_attr "type"     "imadd")
168    (set_attr "mode"     "SI")])
169
170 (define_insn "mips_maddu"
171   [(set (match_operand:DI 0 "register_operand" "=a")
172         (plus:DI
173          (mult:DI (zero_extend:DI
174                    (match_operand:SI 2 "register_operand" "d"))
175                   (zero_extend:DI
176                    (match_operand:SI 3 "register_operand" "d")))
177          (match_operand:DI 1 "register_operand" "0")))]
178   "TARGET_DSPR2 && !TARGET_64BIT"
179   "maddu\t%q0,%2,%3"
180   [(set_attr "type"     "imadd")
181    (set_attr "mode"     "SI")])
182
183 (define_insn "mips_msub"
184   [(set (match_operand:DI 0 "register_operand" "=a")
185         (minus:DI
186          (match_operand:DI 1 "register_operand" "0")
187          (mult:DI (sign_extend:DI
188                    (match_operand:SI 2 "register_operand" "d"))
189                   (sign_extend:DI
190                    (match_operand:SI 3 "register_operand" "d")))))]
191   "TARGET_DSPR2 && !TARGET_64BIT"
192   "msub\t%q0,%2,%3"
193   [(set_attr "type"     "imadd")
194    (set_attr "mode"     "SI")])
195
196 (define_insn "mips_msubu"
197   [(set (match_operand:DI 0 "register_operand" "=a")
198         (minus:DI
199          (match_operand:DI 1 "register_operand" "0")
200          (mult:DI (zero_extend:DI
201                    (match_operand:SI 2 "register_operand" "d"))
202                   (zero_extend:DI
203                    (match_operand:SI 3 "register_operand" "d")))))]
204   "TARGET_DSPR2 && !TARGET_64BIT"
205   "msubu\t%q0,%2,%3"
206   [(set_attr "type"     "imadd")
207    (set_attr "mode"     "SI")])
208
209 (define_insn "mulv2hi3"
210   [(parallel
211     [(set (match_operand:V2HI 0 "register_operand" "=d")
212           (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
213                      (match_operand:V2HI 2 "register_operand" "d")))
214      (set (reg:CCDSP CCDSP_OU_REGNUM)
215           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
216      (clobber (match_scratch:DI 3 "=x"))])]
217   "TARGET_DSPR2"
218   "mul.ph\t%0,%1,%2"
219   [(set_attr "type"     "imul3")
220    (set_attr "mode"     "SI")])
221
222 (define_insn "mips_mul_s_ph"
223   [(parallel
224     [(set (match_operand:V2HI 0 "register_operand" "=d")
225           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
226                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
227                        UNSPEC_MUL_S_PH))
228      (set (reg:CCDSP CCDSP_OU_REGNUM)
229           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
230      (clobber (match_scratch:DI 3 "=x"))])]
231   "TARGET_DSPR2"
232   "mul_s.ph\t%0,%z1,%z2"
233   [(set_attr "type"     "imul3")
234    (set_attr "mode"     "SI")])
235
236 (define_insn "mips_mulq_rs_w"
237   [(parallel
238     [(set (match_operand:SI 0 "register_operand" "=d")
239           (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
240                       (match_operand:SI 2 "reg_or_0_operand" "dJ")]
241                      UNSPEC_MULQ_RS_W))
242      (set (reg:CCDSP CCDSP_OU_REGNUM)
243           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
244      (clobber (match_scratch:DI 3 "=x"))])]
245   "TARGET_DSPR2"
246   "mulq_rs.w\t%0,%z1,%z2"
247   [(set_attr "type"     "imul3")
248    (set_attr "mode"     "SI")])
249
250 (define_insn "mips_mulq_s_ph"
251   [(parallel
252     [(set (match_operand:V2HI 0 "register_operand" "=d")
253           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
254                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
255                        UNSPEC_MULQ_S_PH))
256      (set (reg:CCDSP CCDSP_OU_REGNUM)
257           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
258      (clobber (match_scratch:DI 3 "=x"))])]
259   "TARGET_DSPR2"
260   "mulq_s.ph\t%0,%z1,%z2"
261   [(set_attr "type"     "imul3")
262    (set_attr "mode"     "SI")])
263
264 (define_insn "mips_mulq_s_w"
265   [(parallel
266     [(set (match_operand:SI 0 "register_operand" "=d")
267           (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
268                       (match_operand:SI 2 "reg_or_0_operand" "dJ")]
269                      UNSPEC_MULQ_S_W))
270      (set (reg:CCDSP CCDSP_OU_REGNUM)
271           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
272      (clobber (match_scratch:DI 3 "=x"))])]
273   "TARGET_DSPR2"
274   "mulq_s.w\t%0,%z1,%z2"
275   [(set_attr "type"     "imul3")
276    (set_attr "mode"     "SI")])
277
278 (define_insn "mips_mulsa_w_ph"
279   [(set (match_operand:DI 0 "register_operand" "=a")
280         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
281                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
282                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
283                    UNSPEC_MULSA_W_PH))]
284   "TARGET_DSPR2 && !TARGET_64BIT"
285   "mulsa.w.ph\t%q0,%z2,%z3"
286   [(set_attr "type"     "imadd")
287    (set_attr "mode"     "SI")])
288
289 (define_insn "mips_mult"
290   [(set (match_operand:DI 0 "register_operand" "=a")
291         (mult:DI
292          (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
293          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
294   "TARGET_DSPR2 && !TARGET_64BIT"
295   "mult\t%q0,%1,%2"
296   [(set_attr "type"     "imul")
297    (set_attr "mode"     "SI")])
298
299 (define_insn "mips_multu"
300   [(set (match_operand:DI 0 "register_operand" "=a")
301         (mult:DI
302          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
303          (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
304   "TARGET_DSPR2 && !TARGET_64BIT"
305   "multu\t%q0,%1,%2"
306   [(set_attr "type"     "imul")
307    (set_attr "mode"     "SI")])
308
309 (define_insn "mips_precr_qb_ph"
310   [(set (match_operand:V4QI 0 "register_operand" "=d")
311         (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
312                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
313                      UNSPEC_PRECR_QB_PH))]
314   "TARGET_DSPR2"
315   "precr.qb.ph\t%0,%z1,%z2"
316   [(set_attr "type"     "arith")
317    (set_attr "mode"     "SI")])
318
319 (define_insn "mips_precr_sra_ph_w"
320   [(set (match_operand:V2HI 0 "register_operand" "=d")
321         (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
322                       (match_operand:SI 2 "reg_or_0_operand" "dJ")
323                       (match_operand:SI 3 "const_int_operand" "n")]
324                      UNSPEC_PRECR_SRA_PH_W))]
325   "TARGET_DSPR2"
326 {
327   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
328     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
329   return "precr_sra.ph.w\t%0,%z2,%3";
330 }
331   [(set_attr "type"     "arith")
332    (set_attr "mode"     "SI")])
333
334 (define_insn "mips_precr_sra_r_ph_w"
335   [(set (match_operand:V2HI 0 "register_operand" "=d")
336         (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
337                       (match_operand:SI 2 "reg_or_0_operand" "dJ")
338                       (match_operand:SI 3 "const_int_operand" "n")]
339                      UNSPEC_PRECR_SRA_R_PH_W))]
340   "TARGET_DSPR2"
341 {
342   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
343     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
344   return "precr_sra_r.ph.w\t%0,%z2,%3";
345 }
346   [(set_attr "type"     "arith")
347    (set_attr "mode"     "SI")])
348
349 (define_insn "mips_prepend"
350   [(set (match_operand:SI 0 "register_operand" "=d")
351         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
352                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
353                     (match_operand:SI 3 "const_int_operand" "n")]
354                    UNSPEC_PREPEND))]
355   "TARGET_DSPR2"
356 {
357   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
358     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
359   return "prepend\t%0,%z2,%3";
360 }
361   [(set_attr "type"     "arith")
362    (set_attr "mode"     "SI")])
363
364 (define_insn "mips_shra_qb"
365   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
366         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
367                       (match_operand:SI 2 "arith_operand" "I,d")]
368                      UNSPEC_SHRA_QB))]
369   "TARGET_DSPR2"
370 {
371   if (which_alternative == 0)
372     {
373       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
374         operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
375       return "shra.qb\t%0,%z1,%2";
376     }
377   return "shrav.qb\t%0,%z1,%2";
378 }
379   [(set_attr "type"     "shift")
380    (set_attr "mode"     "SI")])
381
382
383 (define_insn "mips_shra_r_qb"
384   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
385         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
386                       (match_operand:SI 2 "arith_operand" "I,d")]
387                      UNSPEC_SHRA_R_QB))]
388   "TARGET_DSPR2"
389 {
390   if (which_alternative == 0)
391     {
392       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
393         operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
394       return "shra_r.qb\t%0,%z1,%2";
395     }
396   return "shrav_r.qb\t%0,%z1,%2";
397 }
398   [(set_attr "type"     "shift")
399    (set_attr "mode"     "SI")])
400
401 (define_insn "mips_shrl_ph"
402   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
403         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
404                       (match_operand:SI 2 "arith_operand" "I,d")]
405                      UNSPEC_SHRL_PH))]
406   "TARGET_DSPR2"
407 {
408   if (which_alternative == 0)
409     {
410       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
411         operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
412       return "shrl.ph\t%0,%z1,%2";
413     }
414   return "shrlv.ph\t%0,%z1,%2";
415 }
416   [(set_attr "type"     "shift")
417    (set_attr "mode"     "SI")])
418
419 (define_insn "mips_subu_ph"
420   [(parallel
421     [(set (match_operand:V2HI 0 "register_operand" "=d")
422           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
423                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
424                        UNSPEC_SUBU_PH))
425      (set (reg:CCDSP CCDSP_OU_REGNUM)
426           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
427   "TARGET_DSPR2"
428   "subu.ph\t%0,%z1,%z2"
429   [(set_attr "type"     "arith")
430    (set_attr "mode"     "SI")])
431
432 (define_insn "mips_subu_s_ph"
433   [(parallel
434     [(set (match_operand:V2HI 0 "register_operand" "=d")
435           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
436                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
437                        UNSPEC_SUBU_S_PH))
438      (set (reg:CCDSP CCDSP_OU_REGNUM)
439           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
440   "TARGET_DSPR2"
441   "subu_s.ph\t%0,%z1,%z2"
442   [(set_attr "type"     "arith")
443    (set_attr "mode"     "SI")])
444
445 (define_insn "mips_subuh_qb"
446   [(set (match_operand:V4QI 0 "register_operand" "=d")
447         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
448                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
449                      UNSPEC_SUBUH_QB))]
450   "TARGET_DSPR2"
451   "subuh.qb\t%0,%z1,%z2"
452   [(set_attr "type"     "arith")
453    (set_attr "mode"     "SI")])
454
455 (define_insn "mips_subuh_r_qb"
456   [(set (match_operand:V4QI 0 "register_operand" "=d")
457         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
458                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
459                      UNSPEC_SUBUH_R_QB))]
460   "TARGET_DSPR2"
461   "subuh_r.qb\t%0,%z1,%z2"
462   [(set_attr "type"     "arith")
463    (set_attr "mode"     "SI")])
464
465 (define_insn "mips_addqh_ph"
466   [(set (match_operand:V2HI 0 "register_operand" "=d")
467         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
468                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
469                      UNSPEC_ADDQH_PH))]
470   "TARGET_DSPR2"
471   "addqh.ph\t%0,%z1,%z2"
472   [(set_attr "type"     "arith")
473    (set_attr "mode"     "SI")])
474
475 (define_insn "mips_addqh_r_ph"
476   [(set (match_operand:V2HI 0 "register_operand" "=d")
477         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
478                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
479                      UNSPEC_ADDQH_R_PH))]
480   "TARGET_DSPR2"
481   "addqh_r.ph\t%0,%z1,%z2"
482   [(set_attr "type"     "arith")
483    (set_attr "mode"     "SI")])
484
485 (define_insn "mips_addqh_w"
486   [(set (match_operand:SI 0 "register_operand" "=d")
487         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
488                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
489                    UNSPEC_ADDQH_W))]
490   "TARGET_DSPR2"
491   "addqh.w\t%0,%z1,%z2"
492   [(set_attr "type"     "arith")
493    (set_attr "mode"     "SI")])
494
495 (define_insn "mips_addqh_r_w"
496   [(set (match_operand:SI 0 "register_operand" "=d")
497         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
498                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
499                    UNSPEC_ADDQH_R_W))]
500   "TARGET_DSPR2"
501   "addqh_r.w\t%0,%z1,%z2"
502   [(set_attr "type"     "arith")
503    (set_attr "mode"     "SI")])
504
505 (define_insn "mips_subqh_ph"
506   [(set (match_operand:V2HI 0 "register_operand" "=d")
507         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
508                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
509                      UNSPEC_SUBQH_PH))]
510   "TARGET_DSPR2"
511   "subqh.ph\t%0,%z1,%z2"
512   [(set_attr "type"     "arith")
513    (set_attr "mode"     "SI")])
514
515 (define_insn "mips_subqh_r_ph"
516   [(set (match_operand:V2HI 0 "register_operand" "=d")
517         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
518                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
519                      UNSPEC_SUBQH_R_PH))]
520   "TARGET_DSPR2"
521   "subqh_r.ph\t%0,%z1,%z2"
522   [(set_attr "type"     "arith")
523    (set_attr "mode"     "SI")])
524
525 (define_insn "mips_subqh_w"
526   [(set (match_operand:SI 0 "register_operand" "=d")
527         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
528                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
529                    UNSPEC_SUBQH_W))]
530   "TARGET_DSPR2"
531   "subqh.w\t%0,%z1,%z2"
532   [(set_attr "type"     "arith")
533    (set_attr "mode"     "SI")])
534
535 (define_insn "mips_subqh_r_w"
536   [(set (match_operand:SI 0 "register_operand" "=d")
537         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
538                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
539                    UNSPEC_SUBQH_R_W))]
540   "TARGET_DSPR2"
541   "subqh_r.w\t%0,%z1,%z2"
542   [(set_attr "type"     "arith")
543    (set_attr "mode"     "SI")])
544
545 (define_insn "mips_dpax_w_ph"
546   [(set (match_operand:DI 0 "register_operand" "=a")
547         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
548                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
549                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
550                    UNSPEC_DPAX_W_PH))]
551   "TARGET_DSPR2 && !TARGET_64BIT"
552   "dpax.w.ph\t%q0,%z2,%z3"
553   [(set_attr "type"     "imadd")
554    (set_attr "mode"     "SI")])
555
556 (define_insn "mips_dpsx_w_ph"
557   [(set (match_operand:DI 0 "register_operand" "=a")
558         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
559                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
560                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
561                    UNSPEC_DPSX_W_PH))]
562   "TARGET_DSPR2 && !TARGET_64BIT"
563   "dpsx.w.ph\t%q0,%z2,%z3"
564   [(set_attr "type"     "imadd")
565    (set_attr "mode"     "SI")])
566
567 (define_insn "mips_dpaqx_s_w_ph"
568   [(parallel
569     [(set (match_operand:DI 0 "register_operand" "=a")
570           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
571                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
572                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
573                      UNSPEC_DPAQX_S_W_PH))
574      (set (reg:CCDSP CCDSP_OU_REGNUM)
575           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
576                         UNSPEC_DPAQX_S_W_PH))])]
577   "TARGET_DSPR2 && !TARGET_64BIT"
578   "dpaqx_s.w.ph\t%q0,%z2,%z3"
579   [(set_attr "type"     "imadd")
580    (set_attr "mode"     "SI")])
581
582 (define_insn "mips_dpaqx_sa_w_ph"
583   [(parallel
584     [(set (match_operand:DI 0 "register_operand" "=a")
585           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
586                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
587                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
588                      UNSPEC_DPAQX_SA_W_PH))
589      (set (reg:CCDSP CCDSP_OU_REGNUM)
590           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
591                         UNSPEC_DPAQX_SA_W_PH))])]
592   "TARGET_DSPR2 && !TARGET_64BIT"
593   "dpaqx_sa.w.ph\t%q0,%z2,%z3"
594   [(set_attr "type"     "imadd")
595    (set_attr "mode"     "SI")])
596
597 (define_insn "mips_dpsqx_s_w_ph"
598   [(parallel
599     [(set (match_operand:DI 0 "register_operand" "=a")
600           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
601                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
602                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
603                      UNSPEC_DPSQX_S_W_PH))
604      (set (reg:CCDSP CCDSP_OU_REGNUM)
605           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
606                         UNSPEC_DPSQX_S_W_PH))])]
607   "TARGET_DSPR2 && !TARGET_64BIT"
608   "dpsqx_s.w.ph\t%q0,%z2,%z3"
609   [(set_attr "type"     "imadd")
610    (set_attr "mode"     "SI")])
611
612 (define_insn "mips_dpsqx_sa_w_ph"
613   [(parallel
614     [(set (match_operand:DI 0 "register_operand" "=a")
615           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
616                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
617                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
618                      UNSPEC_DPSQX_SA_W_PH))
619      (set (reg:CCDSP CCDSP_OU_REGNUM)
620           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
621                         UNSPEC_DPSQX_SA_W_PH))])]
622   "TARGET_DSPR2 && !TARGET_64BIT"
623   "dpsqx_sa.w.ph\t%q0,%z2,%z3"
624   [(set_attr "type"     "imadd")
625    (set_attr "mode"     "SI")])
626