gcc/config/mips/mips-dspr2.md

   1 ; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
   2
   3 (define_insn "mips_absq_s_qb"
   4   [(parallel
   5     [(set (match_operand:V4QI 0 "register_operand" "=d")
   6           (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
   7                        UNSPEC_ABSQ_S_QB))
   8      (set (reg:CCDSP CCDSP_OU_REGNUM)
   9           (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
  10   "TARGET_DSPR2"
  11   "absq_s.qb\t%0,%z1"
  12   [(set_attr "type"     "arith")
  13    (set_attr "mode"     "SI")])
  14
  15 (define_insn "mips_addu_ph"
  16   [(parallel
  17     [(set (match_operand:V2HI 0 "register_operand" "=d")
  18           (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
  19                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
  20      (set (reg:CCDSP CCDSP_OU_REGNUM)
  21           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
  22   "TARGET_DSPR2"
  23   "addu.ph\t%0,%z1,%z2"
  24   [(set_attr "type"     "arith")
  25    (set_attr "mode"     "SI")])
  26
  27 (define_insn "mips_addu_s_ph"
  28   [(parallel
  29     [(set (match_operand:V2HI 0 "register_operand" "=d")
  30           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
  31                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
  32                        UNSPEC_ADDU_S_PH))
  33      (set (reg:CCDSP CCDSP_OU_REGNUM)
  34           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
  35   "TARGET_DSPR2"
  36   "addu_s.ph\t%0,%z1,%z2"
  37   [(set_attr "type"     "arith")
  38    (set_attr "mode"     "SI")])
  39
  40 (define_insn "mips_adduh_qb"
  41   [(set (match_operand:V4QI 0 "register_operand" "=d")
  42         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
  43                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
  44                      UNSPEC_ADDUH_QB))]
  45   "TARGET_DSPR2"
  46   "adduh.qb\t%0,%z1,%z2"
  47   [(set_attr "type"     "arith")
  48    (set_attr "mode"     "SI")])
  49
  50 (define_insn "mips_adduh_r_qb"
  51   [(set (match_operand:V4QI 0 "register_operand" "=d")
  52         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
  53                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
  54                      UNSPEC_ADDUH_R_QB))]
  55   "TARGET_DSPR2"
  56   "adduh_r.qb\t%0,%z1,%z2"
  57   [(set_attr "type"     "arith")
  58    (set_attr "mode"     "SI")])
  59
  60 (define_insn "mips_append"
  61   [(set (match_operand:SI 0 "register_operand" "=d")
  62         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
  63                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
  64                     (match_operand:SI 3 "const_int_operand" "n")]
  65                    UNSPEC_APPEND))]
  66   "TARGET_DSPR2"
  67 {
  68   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
  69     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
  70   return "append\t%0,%z2,%3";
  71 }
  72   [(set_attr "type"     "arith")
  73    (set_attr "mode"     "SI")])
  74
  75 (define_insn "mips_balign"
  76   [(set (match_operand:SI 0 "register_operand" "=d")
  77         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
  78                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
  79                     (match_operand:SI 3 "const_int_operand" "n")]
  80                    UNSPEC_BALIGN))]
  81   "TARGET_DSPR2"
  82 {
  83   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
  84     operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
  85   return "balign\t%0,%z2,%3";
  86 }
  87   [(set_attr "type"     "arith")
  88    (set_attr "mode"     "SI")])
  89
  90 (define_insn "mips_cmpgdu_eq_qb"
  91   [(parallel
  92     [(set (match_operand:SI 0 "register_operand" "=d")
  93           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
  94                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
  95                      UNSPEC_CMPGDU_EQ_QB))
  96      (set (reg:CCDSP CCDSP_CC_REGNUM)
  97           (unspec:CCDSP [(match_dup 1) (match_dup 2)
  98                          (reg:CCDSP CCDSP_CC_REGNUM)]
  99                         UNSPEC_CMPGDU_EQ_QB))])]
 100   "TARGET_DSPR2"
 101   "cmpgdu.eq.qb\t%0,%z1,%z2"
 102   [(set_attr "type"     "arith")
 103    (set_attr "mode"     "SI")])
 104
 105 (define_insn "mips_cmpgdu_lt_qb"
 106   [(parallel
 107     [(set (match_operand:SI 0 "register_operand" "=d")
 108           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 109                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 110                      UNSPEC_CMPGDU_LT_QB))
 111      (set (reg:CCDSP CCDSP_CC_REGNUM)
 112           (unspec:CCDSP [(match_dup 1) (match_dup 2)
 113                          (reg:CCDSP CCDSP_CC_REGNUM)]
 114                         UNSPEC_CMPGDU_LT_QB))])]
 115   "TARGET_DSPR2"
 116   "cmpgdu.lt.qb\t%0,%z1,%z2"
 117   [(set_attr "type"     "arith")
 118    (set_attr "mode"     "SI")])
 119
 120 (define_insn "mips_cmpgdu_le_qb"
 121   [(parallel
 122     [(set (match_operand:SI 0 "register_operand" "=d")
 123           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 124                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 125                      UNSPEC_CMPGDU_LE_QB))
 126      (set (reg:CCDSP CCDSP_CC_REGNUM)
 127           (unspec:CCDSP [(match_dup 1) (match_dup 2)
 128                          (reg:CCDSP CCDSP_CC_REGNUM)]
 129                         UNSPEC_CMPGDU_LE_QB))])]
 130   "TARGET_DSPR2"
 131   "cmpgdu.le.qb\t%0,%z1,%z2"
 132   [(set_attr "type"     "arith")
 133    (set_attr "mode"     "SI")])
 134
 135 (define_insn "mips_dpa_w_ph"
 136   [(set (match_operand:DI 0 "register_operand" "=a")
 137         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 138                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 139                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 140                    UNSPEC_DPA_W_PH))]
 141   "TARGET_DSPR2 && !TARGET_64BIT"
 142   "dpa.w.ph\t%q0,%z2,%z3"
 143   [(set_attr "type"     "imadd")
 144    (set_attr "mode"     "SI")])
 145
 146 (define_insn "mips_dps_w_ph"
 147   [(set (match_operand:DI 0 "register_operand" "=a")
 148         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 149                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 150                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 151                    UNSPEC_DPS_W_PH))]
 152   "TARGET_DSPR2 && !TARGET_64BIT"
 153   "dps.w.ph\t%q0,%z2,%z3"
 154   [(set_attr "type"     "imadd")
 155    (set_attr "mode"     "SI")])
 156
 157 (define_expand "mips_madd<u>"
 158   [(set (match_operand:DI 0 "register_operand")
 159         (plus:DI
 160          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
 161                   (any_extend:DI (match_operand:SI 3 "register_operand")))
 162          (match_operand:DI 1 "register_operand")))]
 163   "TARGET_DSPR2 && !TARGET_64BIT")
 164
 165 (define_expand "mips_msub<u>"
 166   [(set (match_operand:DI 0 "register_operand")
 167         (minus:DI
 168          (match_operand:DI 1 "register_operand")
 169          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
 170                   (any_extend:DI (match_operand:SI 3 "register_operand")))))]
 171   "TARGET_DSPR2 && !TARGET_64BIT")
 172
 173 (define_insn "mulv2hi3"
 174   [(parallel
 175     [(set (match_operand:V2HI 0 "register_operand" "=d")
 176           (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
 177                      (match_operand:V2HI 2 "register_operand" "d")))
 178      (set (reg:CCDSP CCDSP_OU_REGNUM)
 179           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
 180      (clobber (match_scratch:DI 3 "=x"))])]
 181   "TARGET_DSPR2"
 182   "mul.ph\t%0,%1,%2"
 183   [(set_attr "type"     "imul3")
 184    (set_attr "mode"     "SI")])
 185
 186 (define_insn "mips_mul_s_ph"
 187   [(parallel
 188     [(set (match_operand:V2HI 0 "register_operand" "=d")
 189           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 190                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 191                        UNSPEC_MUL_S_PH))
 192      (set (reg:CCDSP CCDSP_OU_REGNUM)
 193           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
 194      (clobber (match_scratch:DI 3 "=x"))])]
 195   "TARGET_DSPR2"
 196   "mul_s.ph\t%0,%z1,%z2"
 197   [(set_attr "type"     "imul3")
 198    (set_attr "mode"     "SI")])
 199
 200 (define_insn "mips_mulq_rs_w"
 201   [(parallel
 202     [(set (match_operand:SI 0 "register_operand" "=d")
 203           (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 204                       (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 205                      UNSPEC_MULQ_RS_W))
 206      (set (reg:CCDSP CCDSP_OU_REGNUM)
 207           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
 208      (clobber (match_scratch:DI 3 "=x"))])]
 209   "TARGET_DSPR2"
 210   "mulq_rs.w\t%0,%z1,%z2"
 211   [(set_attr "type"     "imul3")
 212    (set_attr "mode"     "SI")])
 213
 214 (define_insn "mips_mulq_s_ph"
 215   [(parallel
 216     [(set (match_operand:V2HI 0 "register_operand" "=d")
 217           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 218                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 219                        UNSPEC_MULQ_S_PH))
 220      (set (reg:CCDSP CCDSP_OU_REGNUM)
 221           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
 222      (clobber (match_scratch:DI 3 "=x"))])]
 223   "TARGET_DSPR2"
 224   "mulq_s.ph\t%0,%z1,%z2"
 225   [(set_attr "type"     "imul3")
 226    (set_attr "mode"     "SI")])
 227
 228 (define_insn "mips_mulq_s_w"
 229   [(parallel
 230     [(set (match_operand:SI 0 "register_operand" "=d")
 231           (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 232                       (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 233                      UNSPEC_MULQ_S_W))
 234      (set (reg:CCDSP CCDSP_OU_REGNUM)
 235           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
 236      (clobber (match_scratch:DI 3 "=x"))])]
 237   "TARGET_DSPR2"
 238   "mulq_s.w\t%0,%z1,%z2"
 239   [(set_attr "type"     "imul3")
 240    (set_attr "mode"     "SI")])
 241
 242 (define_insn "mips_mulsa_w_ph"
 243   [(set (match_operand:DI 0 "register_operand" "=a")
 244         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 245                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 246                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 247                    UNSPEC_MULSA_W_PH))]
 248   "TARGET_DSPR2 && !TARGET_64BIT"
 249   "mulsa.w.ph\t%q0,%z2,%z3"
 250   [(set_attr "type"     "imadd")
 251    (set_attr "mode"     "SI")])
 252
 253 (define_insn "mips_mult"
 254   [(set (match_operand:DI 0 "register_operand" "=a")
 255         (mult:DI
 256          (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
 257          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
 258   "TARGET_DSPR2 && !TARGET_64BIT"
 259   "mult\t%q0,%1,%2"
 260   [(set_attr "type"     "imul")
 261    (set_attr "mode"     "SI")])
 262
 263 (define_insn "mips_multu"
 264   [(set (match_operand:DI 0 "register_operand" "=a")
 265         (mult:DI
 266          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
 267          (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
 268   "TARGET_DSPR2 && !TARGET_64BIT"
 269   "multu\t%q0,%1,%2"
 270   [(set_attr "type"     "imul")
 271    (set_attr "mode"     "SI")])
 272
 273 (define_insn "mips_precr_qb_ph"
 274   [(set (match_operand:V4QI 0 "register_operand" "=d")
 275         (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 276                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 277                      UNSPEC_PRECR_QB_PH))]
 278   "TARGET_DSPR2"
 279   "precr.qb.ph\t%0,%z1,%z2"
 280   [(set_attr "type"     "arith")
 281    (set_attr "mode"     "SI")])
 282
 283 (define_insn "mips_precr_sra_ph_w"
 284   [(set (match_operand:V2HI 0 "register_operand" "=d")
 285         (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
 286                       (match_operand:SI 2 "reg_or_0_operand" "dJ")
 287                       (match_operand:SI 3 "const_int_operand" "n")]
 288                      UNSPEC_PRECR_SRA_PH_W))]
 289   "TARGET_DSPR2"
 290 {
 291   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 292     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 293   return "precr_sra.ph.w\t%0,%z2,%3";
 294 }
 295   [(set_attr "type"     "arith")
 296    (set_attr "mode"     "SI")])
 297
 298 (define_insn "mips_precr_sra_r_ph_w"
 299   [(set (match_operand:V2HI 0 "register_operand" "=d")
 300         (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
 301                       (match_operand:SI 2 "reg_or_0_operand" "dJ")
 302                       (match_operand:SI 3 "const_int_operand" "n")]
 303                      UNSPEC_PRECR_SRA_R_PH_W))]
 304   "TARGET_DSPR2"
 305 {
 306   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 307     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 308   return "precr_sra_r.ph.w\t%0,%z2,%3";
 309 }
 310   [(set_attr "type"     "arith")
 311    (set_attr "mode"     "SI")])
 312
 313 (define_insn "mips_prepend"
 314   [(set (match_operand:SI 0 "register_operand" "=d")
 315         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
 316                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
 317                     (match_operand:SI 3 "const_int_operand" "n")]
 318                    UNSPEC_PREPEND))]
 319   "TARGET_DSPR2"
 320 {
 321   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 322     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 323   return "prepend\t%0,%z2,%3";
 324 }
 325   [(set_attr "type"     "arith")
 326    (set_attr "mode"     "SI")])
 327
 328 (define_insn "mips_shra_qb"
 329   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 330         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
 331                       (match_operand:SI 2 "arith_operand" "I,d")]
 332                      UNSPEC_SHRA_QB))]
 333   "TARGET_DSPR2"
 334 {
 335   if (which_alternative == 0)
 336     {
 337       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
 338         operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
 339       return "shra.qb\t%0,%z1,%2";
 340     }
 341   return "shrav.qb\t%0,%z1,%2";
 342 }
 343   [(set_attr "type"     "shift")
 344    (set_attr "mode"     "SI")])
 345
 346
 347 (define_insn "mips_shra_r_qb"
 348   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 349         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
 350                       (match_operand:SI 2 "arith_operand" "I,d")]
 351                      UNSPEC_SHRA_R_QB))]
 352   "TARGET_DSPR2"
 353 {
 354   if (which_alternative == 0)
 355     {
 356       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
 357         operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
 358       return "shra_r.qb\t%0,%z1,%2";
 359     }
 360   return "shrav_r.qb\t%0,%z1,%2";
 361 }
 362   [(set_attr "type"     "shift")
 363    (set_attr "mode"     "SI")])
 364
 365 (define_insn "mips_shrl_ph"
 366   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 367         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
 368                       (match_operand:SI 2 "arith_operand" "I,d")]
 369                      UNSPEC_SHRL_PH))]
 370   "TARGET_DSPR2"
 371 {
 372   if (which_alternative == 0)
 373     {
 374       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
 375         operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
 376       return "shrl.ph\t%0,%z1,%2";
 377     }
 378   return "shrlv.ph\t%0,%z1,%2";
 379 }
 380   [(set_attr "type"     "shift")
 381    (set_attr "mode"     "SI")])
 382
 383 (define_insn "mips_subu_ph"
 384   [(parallel
 385     [(set (match_operand:V2HI 0 "register_operand" "=d")
 386           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 387                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 388                        UNSPEC_SUBU_PH))
 389      (set (reg:CCDSP CCDSP_OU_REGNUM)
 390           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
 391   "TARGET_DSPR2"
 392   "subu.ph\t%0,%z1,%z2"
 393   [(set_attr "type"     "arith")
 394    (set_attr "mode"     "SI")])
 395
 396 (define_insn "mips_subu_s_ph"
 397   [(parallel
 398     [(set (match_operand:V2HI 0 "register_operand" "=d")
 399           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 400                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 401                        UNSPEC_SUBU_S_PH))
 402      (set (reg:CCDSP CCDSP_OU_REGNUM)
 403           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
 404   "TARGET_DSPR2"
 405   "subu_s.ph\t%0,%z1,%z2"
 406   [(set_attr "type"     "arith")
 407    (set_attr "mode"     "SI")])
 408
 409 (define_insn "mips_subuh_qb"
 410   [(set (match_operand:V4QI 0 "register_operand" "=d")
 411         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 412                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 413                      UNSPEC_SUBUH_QB))]
 414   "TARGET_DSPR2"
 415   "subuh.qb\t%0,%z1,%z2"
 416   [(set_attr "type"     "arith")
 417    (set_attr "mode"     "SI")])
 418
 419 (define_insn "mips_subuh_r_qb"
 420   [(set (match_operand:V4QI 0 "register_operand" "=d")
 421         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 422                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 423                      UNSPEC_SUBUH_R_QB))]
 424   "TARGET_DSPR2"
 425   "subuh_r.qb\t%0,%z1,%z2"
 426   [(set_attr "type"     "arith")
 427    (set_attr "mode"     "SI")])
 428
 429 (define_insn "mips_addqh_ph"
 430   [(set (match_operand:V2HI 0 "register_operand" "=d")
 431         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 432                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 433                      UNSPEC_ADDQH_PH))]
 434   "TARGET_DSPR2"
 435   "addqh.ph\t%0,%z1,%z2"
 436   [(set_attr "type"     "arith")
 437    (set_attr "mode"     "SI")])
 438
 439 (define_insn "mips_addqh_r_ph"
 440   [(set (match_operand:V2HI 0 "register_operand" "=d")
 441         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 442                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 443                      UNSPEC_ADDQH_R_PH))]
 444   "TARGET_DSPR2"
 445   "addqh_r.ph\t%0,%z1,%z2"
 446   [(set_attr "type"     "arith")
 447    (set_attr "mode"     "SI")])
 448
 449 (define_insn "mips_addqh_w"
 450   [(set (match_operand:SI 0 "register_operand" "=d")
 451         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 452                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 453                    UNSPEC_ADDQH_W))]
 454   "TARGET_DSPR2"
 455   "addqh.w\t%0,%z1,%z2"
 456   [(set_attr "type"     "arith")
 457    (set_attr "mode"     "SI")])
 458
 459 (define_insn "mips_addqh_r_w"
 460   [(set (match_operand:SI 0 "register_operand" "=d")
 461         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 462                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 463                    UNSPEC_ADDQH_R_W))]
 464   "TARGET_DSPR2"
 465   "addqh_r.w\t%0,%z1,%z2"
 466   [(set_attr "type"     "arith")
 467    (set_attr "mode"     "SI")])
 468
 469 (define_insn "mips_subqh_ph"
 470   [(set (match_operand:V2HI 0 "register_operand" "=d")
 471         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 472                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 473                      UNSPEC_SUBQH_PH))]
 474   "TARGET_DSPR2"
 475   "subqh.ph\t%0,%z1,%z2"
 476   [(set_attr "type"     "arith")
 477    (set_attr "mode"     "SI")])
 478
 479 (define_insn "mips_subqh_r_ph"
 480   [(set (match_operand:V2HI 0 "register_operand" "=d")
 481         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 482                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 483                      UNSPEC_SUBQH_R_PH))]
 484   "TARGET_DSPR2"
 485   "subqh_r.ph\t%0,%z1,%z2"
 486   [(set_attr "type"     "arith")
 487    (set_attr "mode"     "SI")])
 488
 489 (define_insn "mips_subqh_w"
 490   [(set (match_operand:SI 0 "register_operand" "=d")
 491         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 492                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 493                    UNSPEC_SUBQH_W))]
 494   "TARGET_DSPR2"
 495   "subqh.w\t%0,%z1,%z2"
 496   [(set_attr "type"     "arith")
 497    (set_attr "mode"     "SI")])
 498
 499 (define_insn "mips_subqh_r_w"
 500   [(set (match_operand:SI 0 "register_operand" "=d")
 501         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 502                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 503                    UNSPEC_SUBQH_R_W))]
 504   "TARGET_DSPR2"
 505   "subqh_r.w\t%0,%z1,%z2"
 506   [(set_attr "type"     "arith")
 507    (set_attr "mode"     "SI")])
 508
 509 (define_insn "mips_dpax_w_ph"
 510   [(set (match_operand:DI 0 "register_operand" "=a")
 511         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 512                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 513                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 514                    UNSPEC_DPAX_W_PH))]
 515   "TARGET_DSPR2 && !TARGET_64BIT"
 516   "dpax.w.ph\t%q0,%z2,%z3"
 517   [(set_attr "type"     "imadd")
 518    (set_attr "mode"     "SI")])
 519
 520 (define_insn "mips_dpsx_w_ph"
 521   [(set (match_operand:DI 0 "register_operand" "=a")
 522         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 523                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 524                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 525                    UNSPEC_DPSX_W_PH))]
 526   "TARGET_DSPR2 && !TARGET_64BIT"
 527   "dpsx.w.ph\t%q0,%z2,%z3"
 528   [(set_attr "type"     "imadd")
 529    (set_attr "mode"     "SI")])
 530
 531 (define_insn "mips_dpaqx_s_w_ph"
 532   [(parallel
 533     [(set (match_operand:DI 0 "register_operand" "=a")
 534           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 535                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 536                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 537                      UNSPEC_DPAQX_S_W_PH))
 538      (set (reg:CCDSP CCDSP_OU_REGNUM)
 539           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 540                         UNSPEC_DPAQX_S_W_PH))])]
 541   "TARGET_DSPR2 && !TARGET_64BIT"
 542   "dpaqx_s.w.ph\t%q0,%z2,%z3"
 543   [(set_attr "type"     "imadd")
 544    (set_attr "mode"     "SI")])
 545
 546 (define_insn "mips_dpaqx_sa_w_ph"
 547   [(parallel
 548     [(set (match_operand:DI 0 "register_operand" "=a")
 549           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 550                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 551                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 552                      UNSPEC_DPAQX_SA_W_PH))
 553      (set (reg:CCDSP CCDSP_OU_REGNUM)
 554           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 555                         UNSPEC_DPAQX_SA_W_PH))])]
 556   "TARGET_DSPR2 && !TARGET_64BIT"
 557   "dpaqx_sa.w.ph\t%q0,%z2,%z3"
 558   [(set_attr "type"     "imadd")
 559    (set_attr "mode"     "SI")])
 560
 561 (define_insn "mips_dpsqx_s_w_ph"
 562   [(parallel
 563     [(set (match_operand:DI 0 "register_operand" "=a")
 564           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 565                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 566                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 567                      UNSPEC_DPSQX_S_W_PH))
 568      (set (reg:CCDSP CCDSP_OU_REGNUM)
 569           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 570                         UNSPEC_DPSQX_S_W_PH))])]
 571   "TARGET_DSPR2 && !TARGET_64BIT"
 572   "dpsqx_s.w.ph\t%q0,%z2,%z3"
 573   [(set_attr "type"     "imadd")
 574    (set_attr "mode"     "SI")])
 575
 576 (define_insn "mips_dpsqx_sa_w_ph"
 577   [(parallel
 578     [(set (match_operand:DI 0 "register_operand" "=a")
 579           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 580                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 581                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 582                      UNSPEC_DPSQX_SA_W_PH))
 583      (set (reg:CCDSP CCDSP_OU_REGNUM)
 584           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 585                         UNSPEC_DPSQX_SA_W_PH))])]
 586   "TARGET_DSPR2 && !TARGET_64BIT"
 587   "dpsqx_sa.w.ph\t%q0,%z2,%z3"
 588   [(set_attr "type"     "imadd")
 589    (set_attr "mode"     "SI")])