gcc/config/mips/mips-dsp.md

   1 ;; Copyright (C) 2005, 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18
  19 ;; MIPS DSP ASE Revision 0.98 3/24/2005
  20 (define_c_enum "unspec" [
  21   UNSPEC_ADDQ
  22   UNSPEC_ADDQ_S
  23   UNSPEC_SUBQ
  24   UNSPEC_SUBQ_S
  25   UNSPEC_ADDSC
  26   UNSPEC_ADDWC
  27   UNSPEC_MODSUB
  28   UNSPEC_RADDU_W_QB
  29   UNSPEC_ABSQ_S
  30   UNSPEC_PRECRQ_QB_PH
  31   UNSPEC_PRECRQ_PH_W
  32   UNSPEC_PRECRQ_RS_PH_W
  33   UNSPEC_PRECRQU_S_QB_PH
  34   UNSPEC_PRECEQ_W_PHL
  35   UNSPEC_PRECEQ_W_PHR
  36   UNSPEC_PRECEQU_PH_QBL
  37   UNSPEC_PRECEQU_PH_QBR
  38   UNSPEC_PRECEQU_PH_QBLA
  39   UNSPEC_PRECEQU_PH_QBRA
  40   UNSPEC_PRECEU_PH_QBL
  41   UNSPEC_PRECEU_PH_QBR
  42   UNSPEC_PRECEU_PH_QBLA
  43   UNSPEC_PRECEU_PH_QBRA
  44   UNSPEC_SHLL
  45   UNSPEC_SHLL_S
  46   UNSPEC_SHRL_QB
  47   UNSPEC_SHRA_PH
  48   UNSPEC_SHRA_R
  49   UNSPEC_MULEU_S_PH_QBL
  50   UNSPEC_MULEU_S_PH_QBR
  51   UNSPEC_MULQ_RS_PH
  52   UNSPEC_MULEQ_S_W_PHL
  53   UNSPEC_MULEQ_S_W_PHR
  54   UNSPEC_DPAU_H_QBL
  55   UNSPEC_DPAU_H_QBR
  56   UNSPEC_DPSU_H_QBL
  57   UNSPEC_DPSU_H_QBR
  58   UNSPEC_DPAQ_S_W_PH
  59   UNSPEC_DPSQ_S_W_PH
  60   UNSPEC_MULSAQ_S_W_PH
  61   UNSPEC_DPAQ_SA_L_W
  62   UNSPEC_DPSQ_SA_L_W
  63   UNSPEC_MAQ_S_W_PHL
  64   UNSPEC_MAQ_S_W_PHR
  65   UNSPEC_MAQ_SA_W_PHL
  66   UNSPEC_MAQ_SA_W_PHR
  67   UNSPEC_BITREV
  68   UNSPEC_INSV
  69   UNSPEC_REPL_QB
  70   UNSPEC_REPL_PH
  71   UNSPEC_CMP_EQ
  72   UNSPEC_CMP_LT
  73   UNSPEC_CMP_LE
  74   UNSPEC_CMPGU_EQ_QB
  75   UNSPEC_CMPGU_LT_QB
  76   UNSPEC_CMPGU_LE_QB
  77   UNSPEC_PICK
  78   UNSPEC_PACKRL_PH
  79   UNSPEC_EXTR_W
  80   UNSPEC_EXTR_R_W
  81   UNSPEC_EXTR_RS_W
  82   UNSPEC_EXTR_S_H
  83   UNSPEC_EXTP
  84   UNSPEC_EXTPDP
  85   UNSPEC_SHILO
  86   UNSPEC_MTHLIP
  87   UNSPEC_WRDSP
  88   UNSPEC_RDDSP
  89 ])
  90
  91 (define_constants
  92   [(CCDSP_PO_REGNUM     182)
  93    (CCDSP_SC_REGNUM     183)
  94    (CCDSP_CA_REGNUM     184)
  95    (CCDSP_OU_REGNUM     185)
  96    (CCDSP_CC_REGNUM     186)
  97    (CCDSP_EF_REGNUM     187)])
  98
  99 ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE.
 100 (define_mode_iterator DSP [(SI "ISA_HAS_DSP")
 101                            (V2HI "ISA_HAS_DSP")
 102                            (V4QI "ISA_HAS_DSP")])
 103
 104 ;; This mode iterator allows v2hi, v4qi for vector/SIMD data.
 105 (define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP")
 106                             (V4QI "ISA_HAS_DSP")])
 107
 108 ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data.
 109 (define_mode_iterator DSPQ [(SI "ISA_HAS_DSP")
 110                             (V2HI "ISA_HAS_DSP")])
 111
 112 ;; DSP instructions use q for fixed-point data, and u for integer in the infix.
 113 (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
 114
 115 ;; DSP instructions use nothing for fixed-point data, and u for integer in
 116 ;; the infix.
 117 (define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")])
 118
 119 ;; DSP instructions use w, ph, qb in the postfix.
 120 (define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")])
 121
 122 ;; DSP shift masks for SI, V2HI, V4QI.
 123 (define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")])
 124
 125 ;; MIPS DSP ASE Revision 0.98 3/24/2005
 126 ;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic
 127 ;; ADDQ*
 128 (define_insn "add<DSPV:mode>3"
 129   [(parallel
 130     [(set (match_operand:DSPV 0 "register_operand" "=d")
 131           (plus:DSPV (match_operand:DSPV 1 "register_operand" "d")
 132                      (match_operand:DSPV 2 "register_operand" "d")))
 133      (set (reg:CCDSP CCDSP_OU_REGNUM)
 134           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])]
 135   "ISA_HAS_DSP"
 136   "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
 137   [(set_attr "type"     "arith")
 138    (set_attr "mode"     "SI")])
 139
 140 (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>"
 141   [(parallel
 142     [(set (match_operand:DSP 0 "register_operand" "=d")
 143           (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
 144                        (match_operand:DSP 2 "register_operand" "d")]
 145                       UNSPEC_ADDQ_S))
 146      (set (reg:CCDSP CCDSP_OU_REGNUM)
 147           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
 148   "ISA_HAS_DSP"
 149   "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
 150   [(set_attr "type"     "arith")
 151    (set_attr "mode"     "SI")])
 152
 153 ;; SUBQ*
 154 (define_insn "sub<DSPV:mode>3"
 155   [(parallel
 156     [(set (match_operand:DSPV 0 "register_operand" "=d")
 157           (minus:DSPV (match_operand:DSPV 1 "register_operand" "d")
 158                       (match_operand:DSPV 2 "register_operand" "d")))
 159      (set (reg:CCDSP CCDSP_OU_REGNUM)
 160           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
 161   "ISA_HAS_DSP"
 162   "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
 163   [(set_attr "type"     "arith")
 164    (set_attr "mode"     "SI")])
 165
 166 (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>"
 167   [(parallel
 168     [(set (match_operand:DSP 0 "register_operand" "=d")
 169           (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
 170                        (match_operand:DSP 2 "register_operand" "d")]
 171                       UNSPEC_SUBQ_S))
 172      (set (reg:CCDSP CCDSP_OU_REGNUM)
 173           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
 174   "ISA_HAS_DSP"
 175   "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
 176   [(set_attr "type"     "arith")
 177    (set_attr "mode"     "SI")])
 178
 179 ;; ADDSC
 180 (define_insn "mips_addsc"
 181   [(parallel
 182     [(set (match_operand:SI 0 "register_operand" "=d")
 183           (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 184                       (match_operand:SI 2 "register_operand" "d")]
 185                      UNSPEC_ADDSC))
 186      (set (reg:CCDSP CCDSP_CA_REGNUM)
 187           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
 188   "ISA_HAS_DSP"
 189   "addsc\t%0,%1,%2"
 190   [(set_attr "type"     "arith")
 191    (set_attr "mode"     "SI")])
 192
 193 ;; ADDWC
 194 (define_insn "mips_addwc"
 195   [(parallel
 196     [(set (match_operand:SI 0 "register_operand" "=d")
 197           (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 198                       (match_operand:SI 2 "register_operand" "d")
 199                     (reg:CCDSP CCDSP_CA_REGNUM)]
 200                      UNSPEC_ADDWC))
 201      (set (reg:CCDSP CCDSP_OU_REGNUM)
 202           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
 203   "ISA_HAS_DSP"
 204   "addwc\t%0,%1,%2"
 205   [(set_attr "type"     "arith")
 206    (set_attr "mode"     "SI")])
 207
 208 ;; MODSUB
 209 (define_insn "mips_modsub"
 210   [(set (match_operand:SI 0 "register_operand" "=d")
 211         (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 212                     (match_operand:SI 2 "register_operand" "d")]
 213                    UNSPEC_MODSUB))]
 214   "ISA_HAS_DSP"
 215   "modsub\t%0,%1,%2"
 216   [(set_attr "type"     "arith")
 217    (set_attr "mode"     "SI")])
 218
 219 ;; RADDU*
 220 (define_insn "mips_raddu_w_qb"
 221   [(set (match_operand:SI 0 "register_operand" "=d")
 222         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
 223                    UNSPEC_RADDU_W_QB))]
 224   "ISA_HAS_DSP"
 225   "raddu.w.qb\t%0,%1"
 226   [(set_attr "type"     "arith")
 227    (set_attr "mode"     "SI")])
 228
 229 ;; ABSQ*
 230 (define_insn "mips_absq_s_<DSPQ:dspfmt2>"
 231   [(parallel
 232     [(set (match_operand:DSPQ 0 "register_operand" "=d")
 233           (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")]
 234                        UNSPEC_ABSQ_S))
 235      (set (reg:CCDSP CCDSP_OU_REGNUM)
 236           (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
 237   "ISA_HAS_DSP"
 238   "absq_s.<DSPQ:dspfmt2>\t%0,%1"
 239   [(set_attr "type"     "arith")
 240    (set_attr "mode"     "SI")])
 241
 242 ;; PRECRQ*
 243 (define_insn "mips_precrq_qb_ph"
 244   [(set (match_operand:V4QI 0 "register_operand" "=d")
 245         (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
 246                       (match_operand:V2HI 2 "register_operand" "d")]
 247                      UNSPEC_PRECRQ_QB_PH))]
 248   "ISA_HAS_DSP"
 249   "precrq.qb.ph\t%0,%1,%2"
 250   [(set_attr "type"     "arith")
 251    (set_attr "mode"     "SI")])
 252
 253 (define_insn "mips_precrq_ph_w"
 254   [(set (match_operand:V2HI 0 "register_operand" "=d")
 255         (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
 256                       (match_operand:SI 2 "register_operand" "d")]
 257                      UNSPEC_PRECRQ_PH_W))]
 258   "ISA_HAS_DSP"
 259   "precrq.ph.w\t%0,%1,%2"
 260   [(set_attr "type"     "arith")
 261    (set_attr "mode"     "SI")])
 262
 263 (define_insn "mips_precrq_rs_ph_w"
 264   [(parallel
 265     [(set (match_operand:V2HI 0 "register_operand" "=d")
 266           (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
 267                         (match_operand:SI 2 "register_operand" "d")]
 268                        UNSPEC_PRECRQ_RS_PH_W))
 269      (set (reg:CCDSP CCDSP_OU_REGNUM)
 270           (unspec:CCDSP [(match_dup 1) (match_dup 2)]
 271                         UNSPEC_PRECRQ_RS_PH_W))])]
 272   "ISA_HAS_DSP"
 273   "precrq_rs.ph.w\t%0,%1,%2"
 274   [(set_attr "type"     "arith")
 275    (set_attr "mode"     "SI")])
 276
 277 ;; PRECRQU*
 278 (define_insn "mips_precrqu_s_qb_ph"
 279   [(parallel
 280     [(set (match_operand:V4QI 0 "register_operand" "=d")
 281           (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
 282                         (match_operand:V2HI 2 "register_operand" "d")]
 283                        UNSPEC_PRECRQU_S_QB_PH))
 284      (set (reg:CCDSP CCDSP_OU_REGNUM)
 285           (unspec:CCDSP [(match_dup 1) (match_dup 2)]
 286                         UNSPEC_PRECRQU_S_QB_PH))])]
 287   "ISA_HAS_DSP"
 288   "precrqu_s.qb.ph\t%0,%1,%2"
 289   [(set_attr "type"     "arith")
 290    (set_attr "mode"     "SI")])
 291
 292 ;; PRECEQ*
 293 (define_insn "mips_preceq_w_phl"
 294   [(set (match_operand:SI 0 "register_operand" "=d")
 295         (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
 296                    UNSPEC_PRECEQ_W_PHL))]
 297   "ISA_HAS_DSP"
 298   "preceq.w.phl\t%0,%1"
 299   [(set_attr "type"     "arith")
 300    (set_attr "mode"     "SI")])
 301
 302 (define_insn "mips_preceq_w_phr"
 303   [(set (match_operand:SI 0 "register_operand" "=d")
 304         (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
 305                    UNSPEC_PRECEQ_W_PHR))]
 306   "ISA_HAS_DSP"
 307   "preceq.w.phr\t%0,%1"
 308   [(set_attr "type"     "arith")
 309    (set_attr "mode"     "SI")])
 310
 311 ;; PRECEQU*
 312 (define_insn "mips_precequ_ph_qbl"
 313   [(set (match_operand:V2HI 0 "register_operand" "=d")
 314         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 315                      UNSPEC_PRECEQU_PH_QBL))]
 316   "ISA_HAS_DSP"
 317   "precequ.ph.qbl\t%0,%1"
 318   [(set_attr "type"     "arith")
 319    (set_attr "mode"     "SI")])
 320
 321 (define_insn "mips_precequ_ph_qbr"
 322   [(set (match_operand:V2HI 0 "register_operand" "=d")
 323         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 324                      UNSPEC_PRECEQU_PH_QBR))]
 325   "ISA_HAS_DSP"
 326   "precequ.ph.qbr\t%0,%1"
 327   [(set_attr "type"     "arith")
 328    (set_attr "mode"     "SI")])
 329
 330 (define_insn "mips_precequ_ph_qbla"
 331   [(set (match_operand:V2HI 0 "register_operand" "=d")
 332         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 333                      UNSPEC_PRECEQU_PH_QBLA))]
 334   "ISA_HAS_DSP"
 335   "precequ.ph.qbla\t%0,%1"
 336   [(set_attr "type"     "arith")
 337    (set_attr "mode"     "SI")])
 338
 339 (define_insn "mips_precequ_ph_qbra"
 340   [(set (match_operand:V2HI 0 "register_operand" "=d")
 341         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 342                      UNSPEC_PRECEQU_PH_QBRA))]
 343   "ISA_HAS_DSP"
 344   "precequ.ph.qbra\t%0,%1"
 345   [(set_attr "type"     "arith")
 346    (set_attr "mode"     "SI")])
 347
 348 ;; PRECEU*
 349 (define_insn "mips_preceu_ph_qbl"
 350   [(set (match_operand:V2HI 0 "register_operand" "=d")
 351         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 352                      UNSPEC_PRECEU_PH_QBL))]
 353   "ISA_HAS_DSP"
 354   "preceu.ph.qbl\t%0,%1"
 355   [(set_attr "type"     "arith")
 356    (set_attr "mode"     "SI")])
 357
 358 (define_insn "mips_preceu_ph_qbr"
 359   [(set (match_operand:V2HI 0 "register_operand" "=d")
 360         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 361                      UNSPEC_PRECEU_PH_QBR))]
 362   "ISA_HAS_DSP"
 363   "preceu.ph.qbr\t%0,%1"
 364   [(set_attr "type"     "arith")
 365    (set_attr "mode"     "SI")])
 366
 367 (define_insn "mips_preceu_ph_qbla"
 368   [(set (match_operand:V2HI 0 "register_operand" "=d")
 369         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 370                      UNSPEC_PRECEU_PH_QBLA))]
 371   "ISA_HAS_DSP"
 372   "preceu.ph.qbla\t%0,%1"
 373   [(set_attr "type"     "arith")
 374    (set_attr "mode"     "SI")])
 375
 376 (define_insn "mips_preceu_ph_qbra"
 377   [(set (match_operand:V2HI 0 "register_operand" "=d")
 378         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 379                      UNSPEC_PRECEU_PH_QBRA))]
 380   "ISA_HAS_DSP"
 381   "preceu.ph.qbra\t%0,%1"
 382   [(set_attr "type"     "arith")
 383    (set_attr "mode"     "SI")])
 384
 385 ;; Table 2-2. MIPS DSP ASE Instructions: Shift
 386 ;; SHLL*
 387 (define_insn "mips_shll_<DSPV:dspfmt2>"
 388   [(parallel
 389     [(set (match_operand:DSPV 0 "register_operand" "=d,d")
 390           (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d")
 391                         (match_operand:SI 2 "arith_operand" "I,d")]
 392                        UNSPEC_SHLL))
 393      (set (reg:CCDSP CCDSP_OU_REGNUM)
 394           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
 395   "ISA_HAS_DSP"
 396 {
 397   if (which_alternative == 0)
 398     {
 399       if (INTVAL (operands[2])
 400           & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>)
 401         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>);
 402       return "shll.<DSPV:dspfmt2>\t%0,%1,%2";
 403     }
 404   return "shllv.<DSPV:dspfmt2>\t%0,%1,%2";
 405 }
 406   [(set_attr "type"     "shift")
 407    (set_attr "mode"     "SI")])
 408
 409 (define_insn "mips_shll_s_<DSPQ:dspfmt2>"
 410   [(parallel
 411     [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
 412           (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
 413                         (match_operand:SI 2 "arith_operand" "I,d")]
 414                        UNSPEC_SHLL_S))
 415      (set (reg:CCDSP CCDSP_OU_REGNUM)
 416           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
 417   "ISA_HAS_DSP"
 418 {
 419   if (which_alternative == 0)
 420     {
 421       if (INTVAL (operands[2])
 422           & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
 423         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
 424       return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2";
 425     }
 426   return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2";
 427 }
 428   [(set_attr "type"     "shift")
 429    (set_attr "mode"     "SI")])
 430
 431 ;; SHRL*
 432 (define_insn "mips_shrl_qb"
 433   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 434         (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
 435                       (match_operand:SI 2 "arith_operand" "I,d")]
 436                      UNSPEC_SHRL_QB))]
 437   "ISA_HAS_DSP"
 438 {
 439   if (which_alternative == 0)
 440     {
 441       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7)
 442         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7);
 443       return "shrl.qb\t%0,%1,%2";
 444     }
 445   return "shrlv.qb\t%0,%1,%2";
 446 }
 447   [(set_attr "type"     "shift")
 448    (set_attr "mode"     "SI")])
 449
 450 ;; SHRA*
 451 (define_insn "mips_shra_ph"
 452   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 453         (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
 454                       (match_operand:SI 2 "arith_operand" "I,d")]
 455                      UNSPEC_SHRA_PH))]
 456   "ISA_HAS_DSP"
 457 {
 458   if (which_alternative == 0)
 459     {
 460       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf)
 461         operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf);
 462       return "shra.ph\t%0,%1,%2";
 463     }
 464   return "shrav.ph\t%0,%1,%2";
 465 }
 466   [(set_attr "type"     "shift")
 467    (set_attr "mode"     "SI")])
 468
 469 (define_insn "mips_shra_r_<DSPQ:dspfmt2>"
 470   [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
 471         (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
 472                       (match_operand:SI 2 "arith_operand" "I,d")]
 473                      UNSPEC_SHRA_R))]
 474   "ISA_HAS_DSP"
 475 {
 476   if (which_alternative == 0)
 477     {
 478       if (INTVAL (operands[2])
 479           & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
 480         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
 481       return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2";
 482     }
 483   return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2";
 484 }
 485   [(set_attr "type"     "shift")
 486    (set_attr "mode"     "SI")])
 487
 488 ;; Table 2-3. MIPS DSP ASE Instructions: Multiply
 489 ;; MULEU*
 490 (define_insn "mips_muleu_s_ph_qbl"
 491   [(parallel
 492     [(set (match_operand:V2HI 0 "register_operand" "=d")
 493           (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
 494                         (match_operand:V2HI 2 "register_operand" "d")]
 495                        UNSPEC_MULEU_S_PH_QBL))
 496      (set (reg:CCDSP CCDSP_OU_REGNUM)
 497           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
 498      (clobber (match_scratch:DI 3 "=x"))])]
 499   "ISA_HAS_DSP"
 500   "muleu_s.ph.qbl\t%0,%1,%2"
 501   [(set_attr "type"     "imul3")
 502    (set_attr "mode"     "SI")])
 503
 504 (define_insn "mips_muleu_s_ph_qbr"
 505   [(parallel
 506     [(set (match_operand:V2HI 0 "register_operand" "=d")
 507           (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
 508                         (match_operand:V2HI 2 "register_operand" "d")]
 509                        UNSPEC_MULEU_S_PH_QBR))
 510      (set (reg:CCDSP CCDSP_OU_REGNUM)
 511           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
 512      (clobber (match_scratch:DI 3 "=x"))])]
 513   "ISA_HAS_DSP"
 514   "muleu_s.ph.qbr\t%0,%1,%2"
 515   [(set_attr "type"     "imul3")
 516    (set_attr "mode"     "SI")])
 517
 518 ;; MULQ*
 519 (define_insn "mips_mulq_rs_ph"
 520   [(parallel
 521     [(set (match_operand:V2HI 0 "register_operand" "=d")
 522           (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
 523                         (match_operand:V2HI 2 "register_operand" "d")]
 524                        UNSPEC_MULQ_RS_PH))
 525      (set (reg:CCDSP CCDSP_OU_REGNUM)
 526           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
 527      (clobber (match_scratch:DI 3 "=x"))])]
 528   "ISA_HAS_DSP"
 529   "mulq_rs.ph\t%0,%1,%2"
 530   [(set_attr "type"     "imul3")
 531    (set_attr "mode"     "SI")])
 532
 533 ;; MULEQ*
 534 (define_insn "mips_muleq_s_w_phl"
 535   [(parallel
 536     [(set (match_operand:SI 0 "register_operand" "=d")
 537           (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
 538                       (match_operand:V2HI 2 "register_operand" "d")]
 539                      UNSPEC_MULEQ_S_W_PHL))
 540      (set (reg:CCDSP CCDSP_OU_REGNUM)
 541           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
 542      (clobber (match_scratch:DI 3 "=x"))])]
 543   "ISA_HAS_DSP"
 544   "muleq_s.w.phl\t%0,%1,%2"
 545   [(set_attr "type"     "imul3")
 546    (set_attr "mode"     "SI")])
 547
 548 (define_insn "mips_muleq_s_w_phr"
 549   [(parallel
 550     [(set (match_operand:SI 0 "register_operand" "=d")
 551           (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
 552                       (match_operand:V2HI 2 "register_operand" "d")]
 553                      UNSPEC_MULEQ_S_W_PHR))
 554      (set (reg:CCDSP CCDSP_OU_REGNUM)
 555           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
 556      (clobber (match_scratch:DI 3 "=x"))])]
 557   "ISA_HAS_DSP"
 558   "muleq_s.w.phr\t%0,%1,%2"
 559   [(set_attr "type"     "imul3")
 560    (set_attr "mode"     "SI")])
 561
 562 ;; DPAU*
 563 (define_insn "mips_dpau_h_qbl"
 564   [(set (match_operand:DI 0 "register_operand" "=a")
 565         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 566                     (match_operand:V4QI 2 "register_operand" "d")
 567                     (match_operand:V4QI 3 "register_operand" "d")]
 568                    UNSPEC_DPAU_H_QBL))]
 569   "ISA_HAS_DSP && !TARGET_64BIT"
 570   "dpau.h.qbl\t%q0,%2,%3"
 571   [(set_attr "type"     "imadd")
 572    (set_attr "mode"     "SI")])
 573
 574 (define_insn "mips_dpau_h_qbr"
 575   [(set (match_operand:DI 0 "register_operand" "=a")
 576         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 577                     (match_operand:V4QI 2 "register_operand" "d")
 578                     (match_operand:V4QI 3 "register_operand" "d")]
 579                    UNSPEC_DPAU_H_QBR))]
 580   "ISA_HAS_DSP && !TARGET_64BIT"
 581   "dpau.h.qbr\t%q0,%2,%3"
 582   [(set_attr "type"     "imadd")
 583    (set_attr "mode"     "SI")])
 584
 585 ;; DPSU*
 586 (define_insn "mips_dpsu_h_qbl"
 587   [(set (match_operand:DI 0 "register_operand" "=a")
 588         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 589                     (match_operand:V4QI 2 "register_operand" "d")
 590                     (match_operand:V4QI 3 "register_operand" "d")]
 591                    UNSPEC_DPSU_H_QBL))]
 592   "ISA_HAS_DSP && !TARGET_64BIT"
 593   "dpsu.h.qbl\t%q0,%2,%3"
 594   [(set_attr "type"     "imadd")
 595    (set_attr "mode"     "SI")])
 596
 597 (define_insn "mips_dpsu_h_qbr"
 598   [(set (match_operand:DI 0 "register_operand" "=a")
 599         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 600                     (match_operand:V4QI 2 "register_operand" "d")
 601                     (match_operand:V4QI 3 "register_operand" "d")]
 602                    UNSPEC_DPSU_H_QBR))]
 603   "ISA_HAS_DSP && !TARGET_64BIT"
 604   "dpsu.h.qbr\t%q0,%2,%3"
 605   [(set_attr "type"     "imadd")
 606    (set_attr "mode"     "SI")])
 607
 608 ;; DPAQ*
 609 (define_insn "mips_dpaq_s_w_ph"
 610   [(parallel
 611     [(set (match_operand:DI 0 "register_operand" "=a")
 612           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 613                       (match_operand:V2HI 2 "register_operand" "d")
 614                       (match_operand:V2HI 3 "register_operand" "d")]
 615                      UNSPEC_DPAQ_S_W_PH))
 616      (set (reg:CCDSP CCDSP_OU_REGNUM)
 617           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 618                         UNSPEC_DPAQ_S_W_PH))])]
 619   "ISA_HAS_DSP && !TARGET_64BIT"
 620   "dpaq_s.w.ph\t%q0,%2,%3"
 621   [(set_attr "type"     "imadd")
 622    (set_attr "mode"     "SI")])
 623
 624 ;; DPSQ*
 625 (define_insn "mips_dpsq_s_w_ph"
 626   [(parallel
 627     [(set (match_operand:DI 0 "register_operand" "=a")
 628           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 629                       (match_operand:V2HI 2 "register_operand" "d")
 630                       (match_operand:V2HI 3 "register_operand" "d")]
 631                      UNSPEC_DPSQ_S_W_PH))
 632      (set (reg:CCDSP CCDSP_OU_REGNUM)
 633           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 634                         UNSPEC_DPSQ_S_W_PH))])]
 635   "ISA_HAS_DSP && !TARGET_64BIT"
 636   "dpsq_s.w.ph\t%q0,%2,%3"
 637   [(set_attr "type"     "imadd")
 638    (set_attr "mode"     "SI")])
 639
 640 ;; MULSAQ*
 641 (define_insn "mips_mulsaq_s_w_ph"
 642   [(parallel
 643     [(set (match_operand:DI 0 "register_operand" "=a")
 644           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 645                       (match_operand:V2HI 2 "register_operand" "d")
 646                       (match_operand:V2HI 3 "register_operand" "d")]
 647                      UNSPEC_MULSAQ_S_W_PH))
 648      (set (reg:CCDSP CCDSP_OU_REGNUM)
 649           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 650                         UNSPEC_MULSAQ_S_W_PH))])]
 651   "ISA_HAS_DSP && !TARGET_64BIT"
 652   "mulsaq_s.w.ph\t%q0,%2,%3"
 653   [(set_attr "type"     "imadd")
 654    (set_attr "mode"     "SI")])
 655
 656 ;; DPAQ*
 657 (define_insn "mips_dpaq_sa_l_w"
 658   [(parallel
 659     [(set (match_operand:DI 0 "register_operand" "=a")
 660           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 661                       (match_operand:SI 2 "register_operand" "d")
 662                       (match_operand:SI 3 "register_operand" "d")]
 663                      UNSPEC_DPAQ_SA_L_W))
 664      (set (reg:CCDSP CCDSP_OU_REGNUM)
 665           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 666                         UNSPEC_DPAQ_SA_L_W))])]
 667   "ISA_HAS_DSP && !TARGET_64BIT"
 668   "dpaq_sa.l.w\t%q0,%2,%3"
 669   [(set_attr "type"     "imadd")
 670    (set_attr "mode"     "SI")])
 671
 672 ;; DPSQ*
 673 (define_insn "mips_dpsq_sa_l_w"
 674   [(parallel
 675     [(set (match_operand:DI 0 "register_operand" "=a")
 676           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 677                       (match_operand:SI 2 "register_operand" "d")
 678                       (match_operand:SI 3 "register_operand" "d")]
 679                      UNSPEC_DPSQ_SA_L_W))
 680      (set (reg:CCDSP CCDSP_OU_REGNUM)
 681           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 682                         UNSPEC_DPSQ_SA_L_W))])]
 683   "ISA_HAS_DSP && !TARGET_64BIT"
 684   "dpsq_sa.l.w\t%q0,%2,%3"
 685   [(set_attr "type"     "imadd")
 686    (set_attr "mode"     "SI")])
 687
 688 ;; MAQ*
 689 (define_insn "mips_maq_s_w_phl"
 690   [(parallel
 691     [(set (match_operand:DI 0 "register_operand" "=a")
 692           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 693                       (match_operand:V2HI 2 "register_operand" "d")
 694                       (match_operand:V2HI 3 "register_operand" "d")]
 695                      UNSPEC_MAQ_S_W_PHL))
 696      (set (reg:CCDSP CCDSP_OU_REGNUM)
 697           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 698                         UNSPEC_MAQ_S_W_PHL))])]
 699   "ISA_HAS_DSP && !TARGET_64BIT"
 700   "maq_s.w.phl\t%q0,%2,%3"
 701   [(set_attr "type"     "imadd")
 702    (set_attr "mode"     "SI")])
 703
 704 (define_insn "mips_maq_s_w_phr"
 705   [(parallel
 706     [(set (match_operand:DI 0 "register_operand" "=a")
 707           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 708                       (match_operand:V2HI 2 "register_operand" "d")
 709                       (match_operand:V2HI 3 "register_operand" "d")]
 710                      UNSPEC_MAQ_S_W_PHR))
 711      (set (reg:CCDSP CCDSP_OU_REGNUM)
 712           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 713                         UNSPEC_MAQ_S_W_PHR))])]
 714   "ISA_HAS_DSP && !TARGET_64BIT"
 715   "maq_s.w.phr\t%q0,%2,%3"
 716   [(set_attr "type"     "imadd")
 717    (set_attr "mode"     "SI")])
 718
 719 ;; MAQ_SA*
 720 (define_insn "mips_maq_sa_w_phl"
 721   [(parallel
 722     [(set (match_operand:DI 0 "register_operand" "=a")
 723           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 724                       (match_operand:V2HI 2 "register_operand" "d")
 725                       (match_operand:V2HI 3 "register_operand" "d")]
 726                      UNSPEC_MAQ_SA_W_PHL))
 727      (set (reg:CCDSP CCDSP_OU_REGNUM)
 728           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 729                         UNSPEC_MAQ_SA_W_PHL))])]
 730   "ISA_HAS_DSP && !TARGET_64BIT"
 731   "maq_sa.w.phl\t%q0,%2,%3"
 732   [(set_attr "type"     "imadd")
 733    (set_attr "mode"     "SI")])
 734
 735 (define_insn "mips_maq_sa_w_phr"
 736   [(parallel
 737     [(set (match_operand:DI 0 "register_operand" "=a")
 738           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 739                       (match_operand:V2HI 2 "register_operand" "d")
 740                       (match_operand:V2HI 3 "register_operand" "d")]
 741                      UNSPEC_MAQ_SA_W_PHR))
 742      (set (reg:CCDSP CCDSP_OU_REGNUM)
 743           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 744                         UNSPEC_MAQ_SA_W_PHR))])]
 745   "ISA_HAS_DSP && !TARGET_64BIT"
 746   "maq_sa.w.phr\t%q0,%2,%3"
 747   [(set_attr "type"     "imadd")
 748    (set_attr "mode"     "SI")])
 749
 750 ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation
 751 ;; BITREV
 752 (define_insn "mips_bitrev"
 753   [(set (match_operand:SI 0 "register_operand" "=d")
 754         (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
 755                    UNSPEC_BITREV))]
 756   "ISA_HAS_DSP"
 757   "bitrev\t%0,%1"
 758   [(set_attr "type"     "arith")
 759    (set_attr "mode"     "SI")])
 760
 761 ;; INSV
 762 (define_insn "mips_insv"
 763   [(set (match_operand:SI 0 "register_operand" "=d")
 764         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
 765                     (match_operand:SI 2 "register_operand" "d")
 766                     (reg:CCDSP CCDSP_SC_REGNUM)
 767                     (reg:CCDSP CCDSP_PO_REGNUM)]
 768                    UNSPEC_INSV))]
 769   "ISA_HAS_DSP"
 770   "insv\t%0,%2"
 771   [(set_attr "type"     "arith")
 772    (set_attr "mode"     "SI")])
 773
 774 ;; REPL*
 775 (define_insn "mips_repl_qb"
 776   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 777         (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
 778                      UNSPEC_REPL_QB))]
 779   "ISA_HAS_DSP"
 780 {
 781   if (which_alternative == 0)
 782     {
 783       if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff)
 784         operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
 785       return "repl.qb\t%0,%1";
 786     }
 787   return "replv.qb\t%0,%1";
 788 }
 789   [(set_attr "type"     "arith")
 790    (set_attr "mode"     "SI")])
 791
 792 (define_insn "mips_repl_ph"
 793   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 794         (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
 795                      UNSPEC_REPL_PH))]
 796   "ISA_HAS_DSP"
 797   "@
 798    repl.ph\t%0,%1
 799    replv.ph\t%0,%1"
 800   [(set_attr "type"     "arith")
 801    (set_attr "mode"     "SI")])
 802
 803 ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick
 804 ;; CMPU.* CMP.*
 805 (define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>"
 806   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 807         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 808                        (match_operand:DSPV 1 "register_operand" "d")
 809                        (reg:CCDSP CCDSP_CC_REGNUM)]
 810                       UNSPEC_CMP_EQ))]
 811   "ISA_HAS_DSP"
 812   "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1"
 813   [(set_attr "type"     "arith")
 814    (set_attr "mode"     "SI")])
 815
 816 (define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>"
 817   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 818         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 819                        (match_operand:DSPV 1 "register_operand" "d")
 820                        (reg:CCDSP CCDSP_CC_REGNUM)]
 821                       UNSPEC_CMP_LT))]
 822   "ISA_HAS_DSP"
 823   "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1"
 824   [(set_attr "type"     "arith")
 825    (set_attr "mode"     "SI")])
 826
 827 (define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>"
 828   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 829         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 830                        (match_operand:DSPV 1 "register_operand" "d")
 831                        (reg:CCDSP CCDSP_CC_REGNUM)]
 832                       UNSPEC_CMP_LE))]
 833   "ISA_HAS_DSP"
 834   "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1"
 835   [(set_attr "type"     "arith")
 836    (set_attr "mode"     "SI")])
 837
 838 (define_insn "mips_cmpgu_eq_qb"
 839   [(set (match_operand:SI 0 "register_operand" "=d")
 840         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 841                     (match_operand:V4QI 2 "register_operand" "d")]
 842                    UNSPEC_CMPGU_EQ_QB))]
 843   "ISA_HAS_DSP"
 844   "cmpgu.eq.qb\t%0,%1,%2"
 845   [(set_attr "type"     "arith")
 846    (set_attr "mode"     "SI")])
 847
 848 (define_insn "mips_cmpgu_lt_qb"
 849   [(set (match_operand:SI 0 "register_operand" "=d")
 850         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 851                     (match_operand:V4QI 2 "register_operand" "d")]
 852                    UNSPEC_CMPGU_LT_QB))]
 853   "ISA_HAS_DSP"
 854   "cmpgu.lt.qb\t%0,%1,%2"
 855   [(set_attr "type"     "arith")
 856    (set_attr "mode"     "SI")])
 857
 858 (define_insn "mips_cmpgu_le_qb"
 859   [(set (match_operand:SI 0 "register_operand" "=d")
 860         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 861                     (match_operand:V4QI 2 "register_operand" "d")]
 862                    UNSPEC_CMPGU_LE_QB))]
 863   "ISA_HAS_DSP"
 864   "cmpgu.le.qb\t%0,%1,%2"
 865   [(set_attr "type"     "arith")
 866    (set_attr "mode"     "SI")])
 867
 868 ;; PICK*
 869 (define_insn "mips_pick_<DSPV:dspfmt2>"
 870   [(set (match_operand:DSPV 0 "register_operand" "=d")
 871         (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d")
 872                       (match_operand:DSPV 2 "register_operand" "d")
 873                       (reg:CCDSP CCDSP_CC_REGNUM)]
 874                      UNSPEC_PICK))]
 875   "ISA_HAS_DSP"
 876   "pick.<DSPV:dspfmt2>\t%0,%1,%2"
 877   [(set_attr "type"     "arith")
 878    (set_attr "mode"     "SI")])
 879
 880 ;; PACKRL*
 881 (define_insn "mips_packrl_ph"
 882   [(set (match_operand:V2HI 0 "register_operand" "=d")
 883         (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
 884                       (match_operand:V2HI 2 "register_operand" "d")]
 885                      UNSPEC_PACKRL_PH))]
 886   "ISA_HAS_DSP"
 887   "packrl.ph\t%0,%1,%2"
 888   [(set_attr "type"     "arith")
 889    (set_attr "mode"     "SI")])
 890
 891 ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
 892 ;; EXTR*
 893 (define_insn "mips_extr_w"
 894   [(parallel
 895     [(set (match_operand:SI 0 "register_operand" "=d,d")
 896           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 897                       (match_operand:SI 2 "arith_operand" "I,d")]
 898                      UNSPEC_EXTR_W))
 899      (set (reg:CCDSP CCDSP_OU_REGNUM)
 900           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
 901   "ISA_HAS_DSP && !TARGET_64BIT"
 902 {
 903   if (which_alternative == 0)
 904     {
 905       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 906         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 907       return "extr.w\t%0,%q1,%2";
 908     }
 909   return "extrv.w\t%0,%q1,%2";
 910 }
 911   [(set_attr "type"     "mfhilo")
 912    (set_attr "mode"     "SI")])
 913
 914 (define_insn "mips_extr_r_w"
 915   [(parallel
 916     [(set (match_operand:SI 0 "register_operand" "=d,d")
 917           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 918                       (match_operand:SI 2 "arith_operand" "I,d")]
 919                      UNSPEC_EXTR_R_W))
 920      (set (reg:CCDSP CCDSP_OU_REGNUM)
 921           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
 922   "ISA_HAS_DSP && !TARGET_64BIT"
 923 {
 924   if (which_alternative == 0)
 925     {
 926       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 927         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 928       return "extr_r.w\t%0,%q1,%2";
 929     }
 930   return "extrv_r.w\t%0,%q1,%2";
 931 }
 932   [(set_attr "type"     "mfhilo")
 933    (set_attr "mode"     "SI")])
 934
 935 (define_insn "mips_extr_rs_w"
 936   [(parallel
 937     [(set (match_operand:SI 0 "register_operand" "=d,d")
 938           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 939                       (match_operand:SI 2 "arith_operand" "I,d")]
 940                      UNSPEC_EXTR_RS_W))
 941      (set (reg:CCDSP CCDSP_OU_REGNUM)
 942           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
 943   "ISA_HAS_DSP && !TARGET_64BIT"
 944 {
 945   if (which_alternative == 0)
 946     {
 947       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 948         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 949       return "extr_rs.w\t%0,%q1,%2";
 950     }
 951   return "extrv_rs.w\t%0,%q1,%2";
 952 }
 953   [(set_attr "type"     "mfhilo")
 954    (set_attr "mode"     "SI")])
 955
 956 ;; EXTR*_S.H
 957 (define_insn "mips_extr_s_h"
 958   [(parallel
 959     [(set (match_operand:SI 0 "register_operand" "=d,d")
 960           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 961                       (match_operand:SI 2 "arith_operand" "I,d")]
 962                      UNSPEC_EXTR_S_H))
 963      (set (reg:CCDSP CCDSP_OU_REGNUM)
 964           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
 965   "ISA_HAS_DSP && !TARGET_64BIT"
 966 {
 967   if (which_alternative == 0)
 968     {
 969       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 970         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 971       return "extr_s.h\t%0,%q1,%2";
 972     }
 973   return "extrv_s.h\t%0,%q1,%2";
 974 }
 975   [(set_attr "type"     "mfhilo")
 976    (set_attr "mode"     "SI")])
 977
 978 ;; EXTP*
 979 (define_insn "mips_extp"
 980   [(parallel
 981     [(set (match_operand:SI 0 "register_operand" "=d,d")
 982           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 983                       (match_operand:SI 2 "arith_operand" "I,d")
 984                       (reg:CCDSP CCDSP_PO_REGNUM)]
 985                      UNSPEC_EXTP))
 986      (set (reg:CCDSP CCDSP_EF_REGNUM)
 987           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
 988   "ISA_HAS_DSP && !TARGET_64BIT"
 989 {
 990   if (which_alternative == 0)
 991     {
 992       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 993         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 994       return "extp\t%0,%q1,%2";
 995     }
 996   return "extpv\t%0,%q1,%2";
 997 }
 998   [(set_attr "type"     "mfhilo")
 999    (set_attr "mode"     "SI")])
1000
1001 (define_insn "mips_extpdp"
1002   [(parallel
1003     [(set (match_operand:SI 0 "register_operand" "=d,d")
1004           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
1005                       (match_operand:SI 2 "arith_operand" "I,d")
1006                       (reg:CCDSP CCDSP_PO_REGNUM)]
1007                      UNSPEC_EXTPDP))
1008      (set (reg:CCDSP CCDSP_PO_REGNUM)
1009           (unspec:CCDSP [(match_dup 1) (match_dup 2)
1010                          (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
1011      (set (reg:CCDSP CCDSP_EF_REGNUM)
1012           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
1013   "ISA_HAS_DSP && !TARGET_64BIT"
1014 {
1015   if (which_alternative == 0)
1016     {
1017       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
1018         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
1019       return "extpdp\t%0,%q1,%2";
1020     }
1021   return "extpdpv\t%0,%q1,%2";
1022 }
1023   [(set_attr "type"     "mfhilo")
1024    (set_attr "mode"     "SI")])
1025
1026 ;; SHILO*
1027 (define_insn "mips_shilo"
1028   [(set (match_operand:DI 0 "register_operand" "=a,a")
1029         (unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
1030                     (match_operand:SI 2 "arith_operand" "I,d")]
1031                    UNSPEC_SHILO))]
1032   "ISA_HAS_DSP && !TARGET_64BIT"
1033 {
1034   if (which_alternative == 0)
1035     {
1036       if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31)
1037         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
1038       return "shilo\t%q0,%2";
1039     }
1040   return "shilov\t%q0,%2";
1041 }
1042   [(set_attr "type"     "mfhilo")
1043    (set_attr "mode"     "SI")])
1044
1045 ;; MTHLIP*
1046 (define_insn "mips_mthlip"
1047   [(parallel
1048     [(set (match_operand:DI 0 "register_operand" "=a")
1049           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1050                       (match_operand:SI 2 "register_operand" "d")
1051                       (reg:CCDSP CCDSP_PO_REGNUM)]
1052                      UNSPEC_MTHLIP))
1053      (set (reg:CCDSP CCDSP_PO_REGNUM)
1054           (unspec:CCDSP [(match_dup 1) (match_dup 2)
1055                          (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
1056   "ISA_HAS_DSP && !TARGET_64BIT"
1057   "mthlip\t%2,%q0"
1058   [(set_attr "type"     "mfhilo")
1059    (set_attr "mode"     "SI")])
1060
1061 ;; WRDSP
1062 (define_insn "mips_wrdsp"
1063   [(parallel
1064     [(set (reg:CCDSP CCDSP_PO_REGNUM)
1065           (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d")
1066                          (match_operand:SI 1 "const_uimm6_operand" "YA")]
1067                          UNSPEC_WRDSP))
1068      (set (reg:CCDSP CCDSP_SC_REGNUM)
1069           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1070      (set (reg:CCDSP CCDSP_CA_REGNUM)
1071           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1072      (set (reg:CCDSP CCDSP_OU_REGNUM)
1073           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1074      (set (reg:CCDSP CCDSP_CC_REGNUM)
1075           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1076      (set (reg:CCDSP CCDSP_EF_REGNUM)
1077           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
1078   "ISA_HAS_DSP"
1079   "wrdsp\t%0,%1"
1080   [(set_attr "type"     "arith")
1081    (set_attr "mode"     "SI")])
1082
1083 ;; RDDSP
1084 (define_insn "mips_rddsp"
1085   [(set (match_operand:SI 0 "register_operand" "=d")
1086         (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA")
1087                     (reg:CCDSP CCDSP_PO_REGNUM)
1088                     (reg:CCDSP CCDSP_SC_REGNUM)
1089                     (reg:CCDSP CCDSP_CA_REGNUM)
1090                     (reg:CCDSP CCDSP_OU_REGNUM)
1091                     (reg:CCDSP CCDSP_CC_REGNUM)
1092                     (reg:CCDSP CCDSP_EF_REGNUM)]
1093                    UNSPEC_RDDSP))]
1094   "ISA_HAS_DSP"
1095   "rddsp\t%0,%1"
1096   [(set_attr "type"     "arith")
1097    (set_attr "mode"     "SI")])
1098
1099 ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load
1100 ;; L*X
1101 (define_expand "mips_lbux"
1102   [(match_operand:SI 0 "register_operand")
1103    (match_operand 1 "pmode_register_operand")
1104    (match_operand:SI 2 "register_operand")]
1105   "ISA_HAS_DSP"
1106 {
1107   operands[2] = convert_to_mode (Pmode, operands[2], false);
1108   if (Pmode == SImode)
1109     emit_insn (gen_mips_lbux_si (operands[0], operands[1], operands[2]));
1110   else
1111     emit_insn (gen_mips_lbux_di (operands[0], operands[1], operands[2]));
1112   DONE;
1113 })
1114
1115 (define_insn "mips_lbux_<mode>"
1116   [(set (match_operand:SI 0 "register_operand" "=d")
1117         (zero_extend:SI
1118           (mem:QI (plus:P (match_operand:P 1 "register_operand" "d")
1119                           (match_operand:P 2 "register_operand" "d")))))]
1120   "ISA_HAS_DSP"
1121   "lbux\t%0,%2(%1)"
1122   [(set_attr "type"     "load")
1123    (set_attr "mode"     "SI")])
1124
1125 (define_expand "mips_lhx"
1126   [(match_operand:SI 0 "register_operand")
1127    (match_operand 1 "pmode_register_operand")
1128    (match_operand:SI 2 "register_operand")]
1129   "ISA_HAS_DSP"
1130 {
1131   operands[2] = convert_to_mode (Pmode, operands[2], false);
1132   if (Pmode == SImode)
1133     emit_insn (gen_mips_lhx_si (operands[0], operands[1], operands[2]));
1134   else
1135     emit_insn (gen_mips_lhx_di (operands[0], operands[1], operands[2]));
1136   DONE;
1137 })
1138
1139 (define_insn "mips_lhx_<mode>"
1140   [(set (match_operand:SI 0 "register_operand" "=d")
1141         (sign_extend:SI
1142           (mem:HI (plus:P (match_operand:P 1 "register_operand" "d")
1143                           (match_operand:P 2 "register_operand" "d")))))]
1144   "ISA_HAS_DSP"
1145   "lhx\t%0,%2(%1)"
1146   [(set_attr "type"     "load")
1147    (set_attr "mode"     "SI")])
1148
1149 (define_expand "mips_lwx"
1150   [(match_operand:SI 0 "register_operand")
1151    (match_operand 1 "pmode_register_operand")
1152    (match_operand:SI 2 "register_operand")]
1153   "ISA_HAS_DSP"
1154 {
1155   operands[2] = convert_to_mode (Pmode, operands[2], false);
1156   if (Pmode == SImode)
1157     emit_insn (gen_mips_lwx_si (operands[0], operands[1], operands[2]));
1158   else
1159     emit_insn (gen_mips_lwx_di (operands[0], operands[1], operands[2]));
1160   DONE;
1161 })
1162
1163 (define_insn "mips_lwx_<mode>"
1164   [(set (match_operand:SI 0 "register_operand" "=d")
1165         (mem:SI (plus:P (match_operand:P 1 "register_operand" "d")
1166                         (match_operand:P 2 "register_operand" "d"))))]
1167   "ISA_HAS_DSP"
1168   "lwx\t%0,%2(%1)"
1169   [(set_attr "type"     "load")
1170    (set_attr "mode"     "SI")])
1171
1172 ;; Table 2-8. MIPS DSP ASE Instructions: Branch
1173 ;; BPOSGE32
1174 (define_insn "mips_bposge"
1175   [(set (pc)
1176         (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM)
1177                           (match_operand:SI 1 "immediate_operand" "I"))
1178                       (label_ref (match_operand 0 "" ""))
1179                       (pc)))]
1180   "ISA_HAS_DSP"
1181   "%*bposge%1\t%0%/"
1182   [(set_attr "type"     "branch")])
1183
1184 (define_expand "mips_madd<u>"
1185   [(set (match_operand:DI 0 "register_operand")
1186         (plus:DI
1187          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1188                   (any_extend:DI (match_operand:SI 3 "register_operand")))
1189          (match_operand:DI 1 "register_operand")))]
1190   "ISA_HAS_DSP && !TARGET_64BIT")
1191
1192 (define_expand "mips_msub<u>"
1193   [(set (match_operand:DI 0 "register_operand")
1194         (minus:DI
1195          (match_operand:DI 1 "register_operand")
1196          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1197                   (any_extend:DI (match_operand:SI 3 "register_operand")))))]
1198   "ISA_HAS_DSP && !TARGET_64BIT")