1 ;; Constraint definitions for MIPS.
2 ;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Register constraints
22 (define_register_constraint "d" "BASE_REG_CLASS"
23 "An address register. This is equivalent to @code{r} unless
24 generating MIPS16 code.")
26 (define_register_constraint "t" "T_REG"
29 (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
30 "A floating-point register (if available).")
32 (define_register_constraint "h" "TARGET_BIG_ENDIAN ? MD0_REG : MD1_REG"
33 "The @code{hi} register.")
35 (define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
36 "The @code{lo} register.")
38 (define_register_constraint "x" "MD_REGS"
39 "The @code{hi} and @code{lo} registers.")
41 (define_register_constraint "b" "ALL_REGS"
44 (define_register_constraint "c" "TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
45 : TARGET_MIPS16 ? M16_NA_REGS
47 "A register suitable for use in an indirect jump. This will always be
48 @code{$25} for @option{-mabicalls}.")
50 (define_register_constraint "e" "LEA_REGS"
53 (define_register_constraint "j" "PIC_FN_ADDR_REG"
56 (define_register_constraint "v" "V1_REG"
59 (define_register_constraint "y" "GR_REGS"
60 "Equivalent to @code{r}; retained for backwards compatibility.")
62 (define_register_constraint "z" "ST_REGS"
63 "A floating-point condition code register.")
65 (define_register_constraint "A" "DSP_ACC_REGS"
68 (define_register_constraint "a" "ACC_REGS"
71 (define_register_constraint "B" "COP0_REGS"
74 (define_register_constraint "C" "COP2_REGS"
77 (define_register_constraint "D" "COP3_REGS"
80 ;; Registers that can be used as the target of multiply-accumulate
81 ;; instructions. The core MIPS32 ISA provides a hi/lo madd,
82 ;; but the DSPr2 version allows any accumulator target.
83 (define_register_constraint "ka" "TARGET_DSPR2 ? ACC_REGS : MD_REGS")
85 ;; This is a normal rather than a register constraint because we can
86 ;; never use the stack pointer as a reload register.
87 (define_constraint "ks"
89 (and (match_code "reg")
90 (match_test "REGNO (op) == STACK_POINTER_REGNUM")))
92 ;; Integer constraints
94 (define_constraint "I"
95 "A signed 16-bit constant (for arithmetic instructions)."
96 (and (match_code "const_int")
97 (match_test "SMALL_OPERAND (ival)")))
99 (define_constraint "J"
101 (and (match_code "const_int")
102 (match_test "ival == 0")))
104 (define_constraint "K"
105 "An unsigned 16-bit constant (for logic instructions)."
106 (and (match_code "const_int")
107 (match_test "SMALL_OPERAND_UNSIGNED (ival)")))
109 (define_constraint "L"
110 "A signed 32-bit constant in which the lower 16 bits are zero.
111 Such constants can be loaded using @code{lui}."
112 (and (match_code "const_int")
113 (match_test "LUI_OPERAND (ival)")))
115 (define_constraint "M"
116 "A constant that cannot be loaded using @code{lui}, @code{addiu}
118 (and (match_code "const_int")
119 (match_test "!SMALL_OPERAND (ival)")
120 (match_test "!SMALL_OPERAND_UNSIGNED (ival)")
121 (match_test "!LUI_OPERAND (ival)")))
123 (define_constraint "N"
124 "A constant in the range -65535 to -1 (inclusive)."
125 (and (match_code "const_int")
126 (match_test "ival >= -0xffff && ival < 0")))
128 (define_constraint "O"
129 "A signed 15-bit constant."
130 (and (match_code "const_int")
131 (match_test "ival >= -0x4000 && ival < 0x4000")))
133 (define_constraint "P"
134 "A constant in the range 1 to 65535 (inclusive)."
135 (and (match_code "const_int")
136 (match_test "ival > 0 && ival < 0x10000")))
138 ;; Floating-point constraints
140 (define_constraint "G"
141 "Floating-point zero."
142 (and (match_code "const_double")
143 (match_test "op == CONST0_RTX (mode)")))
145 ;; General constraints
147 (define_constraint "Q"
149 (match_operand 0 "const_arith_operand"))
151 (define_memory_constraint "R"
152 "An address that can be used in a non-macro load or store."
153 (and (match_code "mem")
154 (match_test "mips_fetch_insns (op) == 1")))
156 (define_constraint "S"
158 A constant call address."
159 (and (match_operand 0 "call_insn_operand")
160 (match_test "CONSTANT_P (op)")))
162 (define_constraint "T"
164 A constant @code{move_operand} that cannot be safely loaded into @code{$25}
166 (and (match_operand 0 "move_operand")
167 (match_test "CONSTANT_P (op)")
168 (match_test "mips_dangerous_for_la25_p (op)")))
170 (define_constraint "U"
172 A constant @code{move_operand} that can be safely loaded into @code{$25}
174 (and (match_operand 0 "move_operand")
175 (match_test "CONSTANT_P (op)")
176 (match_test "!mips_dangerous_for_la25_p (op)")))
178 (define_memory_constraint "W"
180 A memory address based on a member of @code{BASE_REG_CLASS}. This is
181 true for all non-mips16 references (although it can sometimes be implicit
182 if @samp{!TARGET_EXPLICIT_RELOCS}). For MIPS16, it excludes stack and
183 constant-pool references."
184 (and (match_code "mem")
185 (match_operand 0 "memory_operand")
186 (ior (match_test "!TARGET_MIPS16")
187 (and (not (match_operand 0 "stack_operand"))
188 (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
190 (define_constraint "YG"
193 (and (match_code "const_vector")
194 (match_test "op == CONST0_RTX (mode)")))
196 (define_constraint "YA"
198 An unsigned 6-bit constant."
199 (and (match_code "const_int")
200 (match_test "UIMM6_OPERAND (ival)")))
202 (define_constraint "YB"
204 A signed 10-bit constant."
205 (and (match_code "const_int")
206 (match_test "IMM10_OPERAND (ival)")))