1 /* Definitions of target machine for GNU compiler for Xilinx MicroBlaze.
2 Copyright 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Michael Eager <eager@eagercon.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Standard GCC variables that we reference. */
24 /* MicroBlaze external variables defined in microblaze.c. */
26 /* Which pipeline to schedule for. */
29 MICROBLAZE_PIPE_3 = 0,
33 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
35 /* print_operand punctuation chars */
36 extern char microblaze_print_operand_punct[];
38 /* # bytes of data/sdata cutoff */
39 extern int microblaze_section_threshold;
41 /* Map register # to debug register # */
42 extern int microblaze_dbx_regno[];
44 extern int microblaze_no_unsafe_delay;
45 extern enum pipeline_type microblaze_pipe;
47 #define OBJECT_FORMAT_ELF
49 /* Default target_flags if no switches are specified */
50 #define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT)
52 /* What is the default setting for -mcpu= . We set it to v4.00.a even though
53 we are actually ahead. This is safest version that has generate code
54 compatible for the original ISA */
55 #define MICROBLAZE_DEFAULT_CPU "v4.00.a"
57 /* Macros to decide whether certain features are available or not,
58 depending on the instruction set architecture level. */
60 #define DRIVER_SELF_SPECS \
61 "%{mxl-soft-mul:%<mno-xl-soft-mul}", \
62 "%{mno-xl-barrel-shift:%<mxl-barrel-shift}", \
63 "%{mno-xl-pattern-compare:%<mxl-pattern-compare}", \
64 "%{mxl-soft-div:%<mno-xl-soft-div}", \
65 "%{msoft-float:%<mhard-float}"
67 /* Tell collect what flags to pass to nm. */
69 #define NM_FLAGS "-Bn"
72 /* Names to predefine in the preprocessor for this target machine. */
73 #define TARGET_CPU_CPP_BUILTINS() microblaze_cpp_define (pfile)
75 /* Assembler specs. */
77 #define TARGET_ASM_SPEC "%{v}"
83 /* Extra switches sometimes passed to the linker. */
84 /* -xl-mode-xmdstub translated to -Zxl-mode-xmdstub -- deprecated. */
86 #define LINK_SPEC "%{shared:-shared} -N -relax \
87 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
88 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
89 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
90 %{!T*: -dT xilinx.ld%s}"
92 /* Specs for the compiler proper */
96 %{G*} %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
98 %(subtarget_cc1_spec) \
99 %{mxl-multiply-high:-mcpu=v6.00.a} \
103 #define EXTRA_SPECS \
104 { "target_asm_spec", TARGET_ASM_SPEC }, \
105 SUBTARGET_EXTRA_SPECS
107 /* Print subsidiary information on the compiler version in use. */
108 #define MICROBLAZE_VERSION MICROBLAZE_DEFAULT_CPU
111 #define MACHINE_TYPE "MicroBlaze/ELF"
114 #ifndef TARGET_VERSION_INTERNAL
115 #define TARGET_VERSION_INTERNAL(STREAM) \
116 fprintf (STREAM, " %s %s", MACHINE_TYPE, MICROBLAZE_VERSION)
119 #ifndef TARGET_VERSION
120 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
123 /* Local compiler-generated symbols must have a prefix that the assembler
126 #ifndef LOCAL_LABEL_PREFIX
127 #define LOCAL_LABEL_PREFIX "$"
130 /* fixed registers. */
131 #define MB_ABI_BASE_REGNUM 0
132 #define MB_ABI_STACK_POINTER_REGNUM 1
133 #define MB_ABI_GPRO_REGNUM 2
134 #define MB_ABI_GPRW_REGNUM 13
135 #define MB_ABI_INTR_RETURN_ADDR_REGNUM 14
136 #define MB_ABI_SUB_RETURN_ADDR_REGNUM 15
137 #define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16
138 #define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17
139 #define MB_ABI_ASM_TEMP_REGNUM 18
140 /* This is our temp register. */
141 #define MB_ABI_FRAME_POINTER_REGNUM 19
142 #define MB_ABI_PIC_ADDR_REGNUM 20
143 #define MB_ABI_PIC_FUNC_REGNUM 21
144 /* Volatile registers. */
145 #define MB_ABI_INT_RETURN_VAL_REGNUM 3
146 #define MB_ABI_INT_RETURN_VAL2_REGNUM 4
147 #define MB_ABI_FIRST_ARG_REGNUM 5
148 #define MB_ABI_LAST_ARG_REGNUM 10
149 #define MB_ABI_MAX_ARG_REGS (MB_ABI_LAST_ARG_REGNUM \
150 - MB_ABI_FIRST_ARG_REGNUM + 1)
151 #define MB_ABI_STATIC_CHAIN_REGNUM 3
152 #define MB_ABI_TEMP1_REGNUM 11
153 #define MB_ABI_TEMP2_REGNUM 12
154 #define MB_ABI_MSR_SAVE_REG 11
155 /* Volatile register used to save MSR in interrupt handlers. */
160 /* How to renumber registers for dbx and gdb. */
161 #define DBX_REGISTER_NUMBER(REGNO) microblaze_dbx_regno[(REGNO)]
163 /* Generate DWARF exception handling info. */
164 #define DWARF2_UNWIND_INFO 1
166 /* Don't generate .loc operations. */
167 #define DWARF2_ASM_LINE_DEBUG_INFO 0
169 /* The DWARF 2 CFA column which tracks the return address. */
170 #define DWARF_FRAME_RETURN_COLUMN \
171 (GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
173 /* Initial state of return address on entry to func = R15.
174 Actually, the RA is at R15+8, but gcc doesn't know how
176 NOTE: GDB has a workaround and expects this incorrect value.
177 If this is fixed, a corresponding fix to GDB is needed. */
178 #define INCOMING_RETURN_ADDR_RTX \
179 gen_rtx_REG (VOIDmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
181 /* Use DWARF 2 debugging information by default. */
182 #define DWARF2_DEBUGGING_INFO
183 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
185 /* Target machine storage layout */
187 #define BITS_BIG_ENDIAN 0
188 #define BYTES_BIG_ENDIAN 1
189 #define WORDS_BIG_ENDIAN 1
190 #define BITS_PER_UNIT 8
191 #define BITS_PER_WORD 32
192 #define UNITS_PER_WORD 4
193 #define MIN_UNITS_PER_WORD 4
194 #define INT_TYPE_SIZE 32
195 #define SHORT_TYPE_SIZE 16
196 #define LONG_TYPE_SIZE 32
197 #define LONG_LONG_TYPE_SIZE 64
198 #define FLOAT_TYPE_SIZE 32
199 #define DOUBLE_TYPE_SIZE 64
200 #define LONG_DOUBLE_TYPE_SIZE 64
201 #define POINTER_SIZE 32
202 #define PARM_BOUNDARY 32
203 #define FUNCTION_BOUNDARY 32
204 #define EMPTY_FIELD_BOUNDARY 32
205 #define STRUCTURE_SIZE_BOUNDARY 8
206 #define BIGGEST_ALIGNMENT 32
207 #define STRICT_ALIGNMENT 1
208 #define PCC_BITFIELD_TYPE_MATTERS 1
210 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
211 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
212 && (ALIGN) < BITS_PER_WORD \
216 #define DATA_ALIGNMENT(TYPE, ALIGN) \
217 ((((ALIGN) < BITS_PER_WORD) \
218 && (TREE_CODE (TYPE) == ARRAY_TYPE \
219 || TREE_CODE (TYPE) == UNION_TYPE \
220 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
222 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
223 (((TREE_CODE (TYPE) == ARRAY_TYPE \
224 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
225 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
227 #define WORD_REGISTER_OPERATIONS
229 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
231 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
232 if (GET_MODE_CLASS (MODE) == MODE_INT \
233 && GET_MODE_SIZE (MODE) < 4) \
236 /* Standard register usage. */
238 /* On the MicroBlaze, we have 32 integer registers */
240 #define FIRST_PSEUDO_REGISTER 36
242 #define FIXED_REGISTERS \
244 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
245 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
249 #define CALL_USED_REGISTERS \
251 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
252 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
256 #define GP_REG_FIRST 0
257 #define GP_REG_LAST 31
258 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
259 #define GP_DBX_FIRST 0
262 #define AP_REG_NUM 33
263 #define RAP_REG_NUM 34
264 #define FRP_REG_NUM 35
266 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
267 #define ST_REG_P(REGNO) ((REGNO) == ST_REG)
269 #define HARD_REGNO_NREGS(REGNO, MODE) \
270 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
272 /* Value is 1 if hard register REGNO can hold a value of machine-mode
273 MODE. In 32 bit mode, require that DImode and DFmode be in even
274 registers. For DImode, this makes some of the insns easier to
275 write, since you don't have to worry about a DImode value in
276 registers 3 & 4, producing a result in 4 & 5.
278 To make the code simpler HARD_REGNO_MODE_OK now just references an
279 array built in override_options. Because machmodes.h is not yet
280 included before this file is processed, the MODE bound can't be
282 extern char microblaze_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
283 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
284 microblaze_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO)]
286 #define MODES_TIEABLE_P(MODE1, MODE2) \
287 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
288 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
289 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
290 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
292 #define STACK_POINTER_REGNUM (GP_REG_FIRST + MB_ABI_STACK_POINTER_REGNUM)
294 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(FNDECL)
296 /* Base register for access to local variables of the function. We
297 pretend that the frame pointer is
298 MB_ABI_INTR_RETURN_ADDR_REGNUM, and then eliminate it
299 to HARD_FRAME_POINTER_REGNUM. We can get away with this because
300 rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed
301 register(return address for interrupt), and will not be used for
304 #define FRAME_POINTER_REGNUM FRP_REG_NUM
305 #define HARD_FRAME_POINTER_REGNUM \
306 (GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM)
307 #define ARG_POINTER_REGNUM AP_REG_NUM
308 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
309 #define STATIC_CHAIN_REGNUM \
310 (GP_REG_FIRST + MB_ABI_STATIC_CHAIN_REGNUM)
312 /* registers used in prologue/epilogue code when the stack frame
313 is larger than 32K bytes. These registers must come from the
314 scratch register set, and not used for passing and returning
315 arguments and any other information used in the calling sequence
318 #define MICROBLAZE_TEMP1_REGNUM \
319 (GP_REG_FIRST + MB_ABI_TEMP1_REGNUM)
321 #define MICROBLAZE_TEMP2_REGNUM \
322 (GP_REG_FIRST + MB_ABI_TEMP2_REGNUM)
324 #define NO_FUNCTION_CSE 1
326 #define PIC_OFFSET_TABLE_REGNUM \
327 (flag_pic ? (GP_REG_FIRST + MB_ABI_PIC_ADDR_REGNUM) : \
332 NO_REGS, /* no registers in set. */
333 GR_REGS, /* integer registers. */
334 ST_REGS, /* status register. */
335 ALL_REGS, /* all registers. */
336 LIM_REG_CLASSES /* max value + 1. */
339 #define N_REG_CLASSES (int) LIM_REG_CLASSES
341 #define GENERAL_REGS GR_REGS
343 #define REG_CLASS_NAMES \
351 #define REG_CLASS_CONTENTS \
353 { 0x00000000, 0x00000000 }, /* no registers. */ \
354 { 0xffffffff, 0x00000000 }, /* integer registers. */ \
355 { 0x00000000, 0x00000001 }, /* status registers. */ \
356 { 0xffffffff, 0x0000000f } /* all registers. */ \
359 extern enum reg_class microblaze_regno_to_class[];
361 #define REGNO_REG_CLASS(REGNO) microblaze_regno_to_class[ (REGNO) ]
363 #define BASE_REG_CLASS GR_REGS
365 #define INDEX_REG_CLASS GR_REGS
367 #define GR_REG_CLASS_P(CLASS) ((CLASS) == GR_REGS)
369 /* REGISTER AND CONSTANT CLASSES */
371 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
372 #define LARGE_INT(X) \
373 (INTVAL (X) > 0 && UINTVAL (X) >= 0x80000000 && UINTVAL (X) <= 0xffffffff)
374 #define PLT_ADDR_P(X) (GET_CODE (X) == UNSPEC && XINT (X,1) == UNSPEC_PLT)
375 /* Test for a valid operand for a call instruction.
376 Don't allow the arg pointer register or virtual regs
377 since they may change into reg + const, which the patterns
379 #define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \
380 || (GET_CODE (X) == REG && X != arg_pointer_rtx\
381 && ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \
382 && REGNO (X) <= LAST_VIRTUAL_REGISTER)))
384 /* True if VALUE is a signed 16-bit number. */
385 #define SMALL_OPERAND(VALUE) \
386 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
388 /* Constant which cannot be loaded in one instruction. */
389 #define LARGE_OPERAND(VALUE) \
390 ((((VALUE) & ~0x0000ffff) != 0) \
391 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
392 && (((VALUE) & 0x0000ffff) != 0 \
393 || (((VALUE) & ~2147483647) != 0 \
394 && ((VALUE) & ~2147483647) != ~2147483647)))
396 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
397 ((CLASS) != ALL_REGS \
399 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
400 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
402 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
403 || GET_MODE (X) == VOIDmode) \
404 ? (GR_REGS) : (CLASS))))
406 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
407 (GET_MODE_CLASS (MODE) == MODE_INT)
409 #define CLASS_MAX_NREGS(CLASS, MODE) \
410 ((GET_MODE_SIZE (MODE) + (UNITS_PER_WORD) - 1) / (UNITS_PER_WORD))
412 /* Stack layout; function entry, exit and calling. */
414 #define STACK_GROWS_DOWNWARD
416 /* Changed the starting frame offset to including the new link stuff */
417 #define STARTING_FRAME_OFFSET \
418 (crtl->outgoing_args_size + FIRST_PARM_OFFSET(FNDECL))
420 /* The return address for the current frame is in r31 if this is a leaf
421 function. Otherwise, it is on the stack. It is at a variable offset
422 from sp/fp/ap, so we define a fake hard register rap which is a
423 poiner to the return address on the stack. This always gets eliminated
424 during reload to be either the frame pointer or the stack pointer plus
427 #define RETURN_ADDR_RTX(count, frame) \
428 microblaze_return_addr(count,frame)
430 extern struct microblaze_frame_info current_frame_info;
432 #define ELIMINABLE_REGS \
433 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
434 { ARG_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
435 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
436 { RETURN_ADDRESS_POINTER_REGNUM, \
437 GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
438 { RETURN_ADDRESS_POINTER_REGNUM, \
439 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM}, \
440 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
441 { FRAME_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}}
443 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
444 (OFFSET) = microblaze_initial_elimination_offset ((FROM), (TO))
446 #define ACCUMULATE_OUTGOING_ARGS 1
448 #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
450 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
452 #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
454 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
456 #define STACK_BOUNDARY 32
458 #define NUM_OF_ARGS 6
460 #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
462 #define GP_ARG_FIRST (GP_REG_FIRST + MB_ABI_FIRST_ARG_REGNUM)
463 #define GP_ARG_LAST (GP_REG_FIRST + MB_ABI_LAST_ARG_REGNUM)
465 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
467 #define LIBCALL_VALUE(MODE) \
469 ((GET_MODE_CLASS (MODE) != MODE_INT \
470 || GET_MODE_SIZE (MODE) >= 4) \
472 : SImode), GP_RETURN)
474 /* 1 if N is a possible register number for a function value.
475 On the MicroBlaze, R2 R3 are the only register thus used.
476 Currently, R2 are only implemented here (C has no complex type) */
478 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
480 #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
482 typedef struct microblaze_args
484 int gp_reg_found; /* whether a gp register was found yet */
485 int arg_number; /* argument number */
486 int arg_words; /* # total words the arguments take */
487 int fp_arg_words; /* # words for FP args */
488 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
489 int fp_code; /* Mode of FP arguments */
490 int num_adjusts; /* number of adjustments made */
491 /* Adjustments made to args pass in regs. */
492 /* ??? The size is doubled to work around a bug in the code that sets the
493 adjustments in function_arg. */
494 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS * 2];
497 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
498 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
500 #define NO_PROFILE_COUNTERS 1
502 #define FUNCTION_PROFILER(FILE, LABELNO) { \
504 fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
508 #define EXIT_IGNORE_STACK 1
510 #define TRAMPOLINE_SIZE (32 + 8)
512 #define TRAMPOLINE_ALIGNMENT 32
514 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
516 #define REGNO_OK_FOR_INDEX_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
518 #ifndef REG_OK_STRICT
519 #define REG_STRICT_FLAG 0
521 #define REG_STRICT_FLAG 1
524 #define REG_OK_FOR_BASE_P(X) \
525 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
527 #define REG_OK_FOR_INDEX_P(X) \
528 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
530 #define MAX_REGS_PER_ADDRESS 2
533 /* Identify valid constant addresses. Exclude if PIC addr which
534 needs scratch register. */
535 #define CONSTANT_ADDRESS_P(X) \
536 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
537 || GET_CODE (X) == CONST_INT \
538 || (GET_CODE (X) == CONST \
539 && ! (flag_pic && pic_address_needs_scratch (X))))
541 /* Define this, so that when PIC, reload won't try to reload invalid
542 addresses which require two reload registers. */
543 #define LEGITIMATE_PIC_OPERAND_P(X) (!pic_address_needs_scratch (X))
545 /* At present, GAS doesn't understand li.[sd], so don't allow it
546 to be generated at present. */
547 #define LEGITIMATE_CONSTANT_P(X) \
548 (GET_CODE (X) != CONST_DOUBLE \
549 || microblaze_const_double_ok (X, GET_MODE (X)))
551 #define CASE_VECTOR_MODE (SImode)
553 #ifndef DEFAULT_SIGNED_CHAR
554 #define DEFAULT_SIGNED_CHAR 1
558 #define MAX_MOVE_MAX 8
560 #define SLOW_BYTE_ACCESS 1
562 /* sCOND operations return 1. */
563 #define STORE_FLAG_VALUE 1
565 #define SHIFT_COUNT_TRUNCATED 1
567 /* This results in inefficient code for 64 bit to 32 conversions.
568 Something needs to be done about this. Perhaps not use any 32 bit
569 instructions? Perhaps use PROMOTE_MODE? */
570 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
574 #define FUNCTION_MODE SImode
576 /* Mode should alwasy be SImode */
577 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
578 ( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \
579 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
582 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
583 (4 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
585 #define BRANCH_COST(speed_p, predictable_p) 2
587 /* Control the assembler format that we output. */
588 #define ASM_APP_ON " #APP\n"
589 #define ASM_APP_OFF " #NO_APP\n"
591 #define REGISTER_NAMES { \
592 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
593 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
594 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
595 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
596 "rmsr", "$ap", "$rap", "$frp" }
598 #define ADDITIONAL_REGISTER_NAMES \
600 { "r0", 0 + GP_REG_FIRST }, \
601 { "r1", 1 + GP_REG_FIRST }, \
602 { "r2", 2 + GP_REG_FIRST }, \
603 { "r3", 3 + GP_REG_FIRST }, \
604 { "r4", 4 + GP_REG_FIRST }, \
605 { "r5", 5 + GP_REG_FIRST }, \
606 { "r6", 6 + GP_REG_FIRST }, \
607 { "r7", 7 + GP_REG_FIRST }, \
608 { "r8", 8 + GP_REG_FIRST }, \
609 { "r9", 9 + GP_REG_FIRST }, \
610 { "r10", 10 + GP_REG_FIRST }, \
611 { "r11", 11 + GP_REG_FIRST }, \
612 { "r12", 12 + GP_REG_FIRST }, \
613 { "r13", 13 + GP_REG_FIRST }, \
614 { "r14", 14 + GP_REG_FIRST }, \
615 { "r15", 15 + GP_REG_FIRST }, \
616 { "r16", 16 + GP_REG_FIRST }, \
617 { "r17", 17 + GP_REG_FIRST }, \
618 { "r18", 18 + GP_REG_FIRST }, \
619 { "r19", 19 + GP_REG_FIRST }, \
620 { "r20", 20 + GP_REG_FIRST }, \
621 { "r21", 21 + GP_REG_FIRST }, \
622 { "r22", 22 + GP_REG_FIRST }, \
623 { "r23", 23 + GP_REG_FIRST }, \
624 { "r24", 24 + GP_REG_FIRST }, \
625 { "r25", 25 + GP_REG_FIRST }, \
626 { "r26", 26 + GP_REG_FIRST }, \
627 { "r27", 27 + GP_REG_FIRST }, \
628 { "r28", 28 + GP_REG_FIRST }, \
629 { "r29", 29 + GP_REG_FIRST }, \
630 { "r30", 30 + GP_REG_FIRST }, \
631 { "r31", 31 + GP_REG_FIRST }, \
635 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
637 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) microblaze_print_operand_punct[CODE]
639 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
641 /* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL
643 Unfortunately, we still need to set the section explicitly. Somehow,
644 our binutils assign .comm and .lcomm variables to the "current" section
645 in the assembly file, rather than where they implicitly belong. We need to
646 remove this explicit setting in GCC when binutils can understand sections
648 #undef ASM_OUTPUT_ALIGNED_COMMON
649 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
651 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
652 && (int) (SIZE) <= microblaze_section_threshold \
655 switch_to_section (sbss_section); \
659 switch_to_section (bss_section); \
661 fprintf (FILE, "%s", COMMON_ASM_OP); \
662 assemble_name ((FILE), (NAME)); \
663 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
664 (SIZE), (ALIGN) / BITS_PER_UNIT); \
665 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
668 #undef ASM_OUTPUT_ALIGNED_LOCAL
669 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
671 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
672 && (int) (SIZE) <= microblaze_section_threshold \
675 switch_to_section (sbss_section); \
679 switch_to_section (bss_section); \
681 fprintf (FILE, "%s", LCOMMON_ASM_OP); \
682 assemble_name ((FILE), (NAME)); \
683 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
684 (SIZE), (ALIGN) / BITS_PER_UNIT); \
685 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
688 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
690 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
693 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
697 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
698 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
700 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
701 fprintf (STREAM, "\t%s\t%sL%d\n", \
703 LOCAL_LABEL_PREFIX, VALUE)
705 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
708 fprintf (STREAM, "\t%s\t%sL%d@GOTOFF\n", \
710 LOCAL_LABEL_PREFIX, VALUE); \
712 fprintf (STREAM, "\t%s\t%sL%d\n", \
714 LOCAL_LABEL_PREFIX, VALUE); \
717 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
718 fprintf (STREAM, "\t.align\t%d\n", (LOG))
720 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
721 fprintf (STREAM, "\t.space\t%lu\n", (SIZE))
723 #define ASCII_DATA_ASM_OP "\t.ascii\t"
724 #define STRING_ASM_OP "\t.asciz\t"
726 #define ASM_OUTPUT_IDENT(FILE, STRING) \
727 microblaze_asm_output_ident (FILE, STRING)
729 /* Default to -G 8 */
730 #ifndef MICROBLAZE_DEFAULT_GVALUE
731 #define MICROBLAZE_DEFAULT_GVALUE 8
734 /* Given a decl node or constant node, choose the section to output it in
735 and select that section. */
737 /* Store in OUTPUT a string (made with alloca) containing
738 an assembler-name for a local static variable named NAME.
739 LABELNO is an integer which is different for each call. */
740 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
741 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
742 sprintf ((OUTPUT), "%s.%lu", (NAME), (unsigned long)(LABELNO)))
744 /* How to start an assembler comment.
745 The leading space is important (the microblaze assembler requires it). */
746 #ifndef ASM_COMMENT_START
747 #define ASM_COMMENT_START " #"
757 /* These definitions are used in with the shift_type flag in the rtl. */
758 #define SHIFT_CONST 1
762 /* Handle interrupt attribute. */
763 extern int interrupt_handler;
764 extern int save_volatiles;
766 #define INTERRUPT_HANDLER_NAME "_interrupt_handler"
768 /* These #define added for C++. */
769 #define UNALIGNED_SHORT_ASM_OP ".data16"
770 #define UNALIGNED_INT_ASM_OP ".data32"
771 #define UNALIGNED_DOUBLE_INT_ASM_OP ".data8"
773 #define ASM_BYTE_OP ".data8"
775 /* The following #defines are used in the headers files. Always retain these. */
777 /* Added for declaring size at the end of the function. */
778 #undef ASM_DECLARE_FUNCTION_SIZE
779 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
781 if (!flag_inhibit_size_directive) \
784 static int labelno; \
786 ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \
787 (*targetm.asm_out.internal_label) (FILE, "Lfe", labelno); \
788 fprintf (FILE, "%s", SIZE_ASM_OP); \
789 assemble_name (FILE, (FNAME)); \
790 fprintf (FILE, ","); \
791 assemble_name (FILE, label); \
792 fprintf (FILE, "-"); \
793 assemble_name (FILE, (FNAME)); \
798 #define GLOBAL_ASM_OP "\t.globl\t"
799 #define TYPE_ASM_OP "\t.type\t"
800 #define SIZE_ASM_OP "\t.size\t"
801 #define COMMON_ASM_OP "\t.comm\t"
802 #define LCOMMON_ASM_OP "\t.lcomm\t"
804 #define MAX_OFILE_ALIGNMENT (32768*8)
806 #define TYPE_OPERAND_FMT "@%s"
808 /* Write the extra assembler code needed to declare an object properly. */
809 #undef ASM_DECLARE_OBJECT_NAME
810 #define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \
812 fprintf (FILE, "%s", TYPE_ASM_OP); \
813 assemble_name (FILE, NAME); \
815 fprintf (FILE, TYPE_OPERAND_FMT, "object"); \
817 size_directive_output = 0; \
818 if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \
820 size_directive_output = 1; \
821 fprintf (FILE, "%s", SIZE_ASM_OP); \
822 assemble_name (FILE, NAME); \
823 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
824 int_size_in_bytes (TREE_TYPE (DECL))); \
826 microblaze_declare_object (FILE, NAME, "", ":\n", 0); \
829 #undef ASM_FINISH_DECLARE_OBJECT
830 #define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \
832 const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
833 if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \
834 && ! AT_END && TOP_LEVEL \
835 && DECL_INITIAL (DECL) == error_mark_node \
836 && !size_directive_output) \
838 size_directive_output = 1; \
839 fprintf (FILE, "%s", SIZE_ASM_OP); \
840 assemble_name (FILE, name); \
841 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
842 int_size_in_bytes (TREE_TYPE (DECL))); \
846 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \
847 do { fputc ( '\t', FILE); \
848 assemble_name (FILE, LABEL1); \
849 fputs ( " = ", FILE); \
850 assemble_name (FILE, LABEL2); \
851 fputc ( '\n', FILE); \
854 #define ASM_WEAKEN_LABEL(FILE,NAME) \
855 do { fputs ("\t.weakext\t", FILE); \
856 assemble_name (FILE, NAME); \
857 fputc ('\n', FILE); \
860 #define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
861 #undef UNIQUE_SECTION_P
862 #define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
864 #undef TARGET_ASM_NAMED_SECTION
865 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
867 /* Define the strings to put out for each section in the object file.
869 Note: For ctors/dtors, we want to give these sections the SHF_WRITE
870 attribute to allow shared libraries to patch/resolve addresses into
871 these locations. On Microblaze, there is no concept of shared libraries
872 yet, so this is for future use. */
873 #define TEXT_SECTION_ASM_OP "\t.text"
874 #define DATA_SECTION_ASM_OP "\t.data"
875 #define READONLY_DATA_SECTION_ASM_OP \
877 #define BSS_SECTION_ASM_OP "\t.bss"
878 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
879 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
880 #define INIT_SECTION_ASM_OP "\t.section\t.init,\"ax\""
881 #define FINI_SECTION_ASM_OP "\t.section\t.fini,\"ax\""
883 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small RW initialized data */
884 #define SDATA2_SECTION_ASM_OP "\t.sdata2" /* Small RO initialized data */
885 #define SBSS_SECTION_ASM_OP "\t.sbss" /* Small RW uninitialized data */
886 #define SBSS2_SECTION_ASM_OP "\t.sbss2" /* Small RO uninitialized data */
888 /* We do this to save a few 10s of code space that would be taken up
889 by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
890 definition in crtstuff.c. */
891 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
892 asm ( SECTION_OP "\n" \
893 "\tbrlid r15, " #FUNC "\n\t nop\n" \
894 TEXT_SECTION_ASM_OP);
896 /* We need to group -lm as well, since some Newlib math functions
897 reference __errno! */
901 %{pg:-start-group -lxilprofile -lgloss -lxil -lc -lm -end-group } \
902 %{!pg:-start-group -lgloss -lxil -lc -lm -end-group }} "
905 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
907 #define STARTFILE_EXECUTABLE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
908 #define STARTFILE_XMDSTUB_SPEC "crt1.o%s crti.o%s crtbegin.o%s"
909 #define STARTFILE_BOOTSTRAP_SPEC "crt2.o%s crti.o%s crtbegin.o%s"
910 #define STARTFILE_NOVECTORS_SPEC "crt3.o%s crti.o%s crtbegin.o%s"
911 #define STARTFILE_CRTINIT_SPEC "%{!pg: %{!mno-clearbss: crtinit.o%s} \
912 %{mno-clearbss: sim-crtinit.o%s}} \
913 %{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}"
915 #define STARTFILE_DEFAULT_SPEC STARTFILE_EXECUTABLE_SPEC
917 #undef SUBTARGET_EXTRA_SPECS
918 #define SUBTARGET_EXTRA_SPECS \
919 { "startfile_executable", STARTFILE_EXECUTABLE_SPEC }, \
920 { "startfile_xmdstub", STARTFILE_XMDSTUB_SPEC }, \
921 { "startfile_bootstrap", STARTFILE_BOOTSTRAP_SPEC }, \
922 { "startfile_novectors", STARTFILE_NOVECTORS_SPEC }, \
923 { "startfile_crtinit", STARTFILE_CRTINIT_SPEC }, \
924 { "startfile_default", STARTFILE_DEFAULT_SPEC },
926 #undef STARTFILE_SPEC
927 #define STARTFILE_SPEC "\
928 %{Zxl-mode-executable : %(startfile_executable) ; \
929 mxl-mode-executable : %(startfile_executable) ; \
930 Zxl-mode-xmdstub : %(startfile_xmdstub) ; \
931 mxl-mode-xmdstub : %(startfile_xmdstub) ; \
932 Zxl-mode-bootstrap : %(startfile_bootstrap) ; \
933 mxl-mode-bootstrap : %(startfile_bootstrap) ; \
934 Zxl-mode-novectors : %(startfile_novectors) ; \
935 mxl-mode-novectors : %(startfile_novectors) ; \
936 Zxl-mode-xilkernel : %(startfile_xilkernel) ; \
937 mxl-mode-xilkernel : %(startfile_xilkernel) ; \
938 : %(startfile_default) \
940 %(startfile_crtinit)"