3 ;; DO NOT EDIT: This file is automatically generated by CGEN.
4 ;; Any changes you make will be discarded when it is next regenerated.
7 (define_predicate "cgen_h_sint_12a1_immediate"
8 (and (match_code "const_int")
9 (match_test "(INTVAL (op) & 0) == 0
10 && INTVAL (op) >= -2048
11 && INTVAL (op) < 2048")))
13 (define_predicate "cgen_h_uint_20a1_immediate"
14 (and (match_code "const_int")
15 (match_test "(INTVAL (op) & 0) == 0
17 && INTVAL (op) < 1048576")))
19 (define_predicate "cgen_h_uint_7a1_immediate"
20 (and (match_code "const_int")
21 (match_test "(INTVAL (op) & 0) == 0
23 && INTVAL (op) < 128")))
25 (define_predicate "cgen_h_uint_6a2_immediate"
26 (and (match_code "const_int")
27 (match_test "(INTVAL (op) & 1) == 0
29 && INTVAL (op) < 128")))
31 (define_predicate "cgen_h_uint_22a4_immediate"
32 (and (match_code "const_int")
33 (match_test "(INTVAL (op) & 3) == 0
35 && INTVAL (op) < 33554432")))
37 (define_predicate "cgen_h_sint_2a1_immediate"
38 (and (match_code "const_int")
39 (match_test "(INTVAL (op) & 0) == 0
41 && INTVAL (op) < 2")))
43 (define_predicate "cgen_h_uint_24a1_immediate"
44 (and (match_code "const_int")
45 (match_test "(INTVAL (op) & 0) == 0
47 && INTVAL (op) < 16777216")))
49 (define_predicate "cgen_h_sint_6a1_immediate"
50 (and (match_code "const_int")
51 (match_test "(INTVAL (op) & 0) == 0
53 && INTVAL (op) < 32")))
55 (define_predicate "cgen_h_uint_5a4_immediate"
56 (and (match_code "const_int")
57 (match_test "(INTVAL (op) & 3) == 0
59 && INTVAL (op) < 256")))
61 (define_predicate "cgen_h_uint_2a1_immediate"
62 (and (match_code "const_int")
63 (match_test "(INTVAL (op) & 0) == 0
65 && INTVAL (op) < 4")))
67 (define_predicate "cgen_h_sint_10a1_immediate"
68 (and (match_code "const_int")
69 (match_test "(INTVAL (op) & 0) == 0
70 && INTVAL (op) >= -512
71 && INTVAL (op) < 512")))
73 (define_predicate "cgen_h_uint_4a1_immediate"
74 (and (match_code "const_int")
75 (match_test "(INTVAL (op) & 0) == 0
77 && INTVAL (op) < 16")))
79 (define_predicate "cgen_h_uint_6a1_immediate"
80 (and (match_code "const_int")
81 (match_test "(INTVAL (op) & 0) == 0
83 && INTVAL (op) < 64")))
85 (define_predicate "cgen_h_uint_16a1_immediate"
86 (and (match_code "const_int")
87 (match_test "(INTVAL (op) & 0) == 0
89 && INTVAL (op) < 65536")))
91 (define_predicate "cgen_h_uint_8a1_immediate"
92 (and (match_code "const_int")
93 (match_test "(INTVAL (op) & 0) == 0
95 && INTVAL (op) < 256")))
97 (define_predicate "cgen_h_sint_16a1_immediate"
98 (and (match_code "const_int")
99 (match_test "(INTVAL (op) & 0) == 0
100 && INTVAL (op) >= -32768
101 && INTVAL (op) < 32768")))
103 (define_predicate "cgen_h_uint_5a1_immediate"
104 (and (match_code "const_int")
105 (match_test "(INTVAL (op) & 0) == 0
107 && INTVAL (op) < 32")))
109 (define_predicate "cgen_h_sint_8a1_immediate"
110 (and (match_code "const_int")
111 (match_test "(INTVAL (op) & 0) == 0
112 && INTVAL (op) >= -128
113 && INTVAL (op) < 128")))
115 (define_predicate "cgen_h_uint_3a1_immediate"
116 (and (match_code "const_int")
117 (match_test "(INTVAL (op) & 0) == 0
119 && INTVAL (op) < 8")))
123 (define_insn "cgen_intrinsic_cpsmsbslla1_w_C3"
125 (unspec_volatile:SI [
126 (match_operand:DI 0 "general_operand" "x")
127 (match_operand:DI 1 "general_operand" "x")
130 (unspec_volatile:SI [
135 (unspec_volatile:SI [
140 (unspec_volatile:SI [
145 (unspec_volatile:SI [
149 "CGEN_ENABLE_INSN_P (0)"
150 "cpsmsbslla1.w\\t%0,%1"
151 [(set_attr "may_trap" "no")
152 (set_attr "latency" "0")
153 (set_attr "length" "4")
154 (set_attr "slot" "cop")
155 (set_attr "slots" "c3")
156 (set_attr "stall" "none")])
159 (define_insn "cgen_intrinsic_cpsmsbslla1_w_P1"
161 (unspec_volatile:SI [
162 (match_operand:DI 0 "general_operand" "x")
163 (match_operand:DI 1 "general_operand" "x")
166 (unspec_volatile:SI [
171 (unspec_volatile:SI [
176 (unspec_volatile:SI [
181 (unspec_volatile:SI [
185 "CGEN_ENABLE_INSN_P (1)"
186 "cpsmsbslla1.w\\t%0,%1"
187 [(set_attr "may_trap" "no")
188 (set_attr "latency" "0")
189 (set_attr "length" "4")
190 (set_attr "slot" "cop")
191 (set_attr "slots" "p1")
192 (set_attr "stall" "none")])
195 (define_insn "cgen_intrinsic_cpsmsbslua1_w_C3"
197 (unspec_volatile:SI [
198 (match_operand:DI 0 "general_operand" "x")
199 (match_operand:DI 1 "general_operand" "x")
202 (unspec_volatile:SI [
207 (unspec_volatile:SI [
212 (unspec_volatile:SI [
217 (unspec_volatile:SI [
221 "CGEN_ENABLE_INSN_P (2)"
222 "cpsmsbslua1.w\\t%0,%1"
223 [(set_attr "may_trap" "no")
224 (set_attr "latency" "0")
225 (set_attr "length" "4")
226 (set_attr "slot" "cop")
227 (set_attr "slots" "c3")
228 (set_attr "stall" "none")])
231 (define_insn "cgen_intrinsic_cpsmsbslua1_w_P1"
233 (unspec_volatile:SI [
234 (match_operand:DI 0 "general_operand" "x")
235 (match_operand:DI 1 "general_operand" "x")
238 (unspec_volatile:SI [
243 (unspec_volatile:SI [
248 (unspec_volatile:SI [
253 (unspec_volatile:SI [
257 "CGEN_ENABLE_INSN_P (3)"
258 "cpsmsbslua1.w\\t%0,%1"
259 [(set_attr "may_trap" "no")
260 (set_attr "latency" "0")
261 (set_attr "length" "4")
262 (set_attr "slot" "cop")
263 (set_attr "slots" "p1")
264 (set_attr "stall" "none")])
267 (define_insn "cgen_intrinsic_cpsmsbslla1_h_C3"
269 (unspec_volatile:SI [
270 (match_operand:DI 0 "general_operand" "x")
271 (match_operand:DI 1 "general_operand" "x")
274 (unspec_volatile:SI [
279 (unspec_volatile:SI [
284 (unspec_volatile:SI [
289 (unspec_volatile:SI [
293 "CGEN_ENABLE_INSN_P (4)"
294 "cpsmsbslla1.h\\t%0,%1"
295 [(set_attr "may_trap" "no")
296 (set_attr "latency" "0")
297 (set_attr "length" "4")
298 (set_attr "slot" "cop")
299 (set_attr "slots" "c3")
300 (set_attr "stall" "none")])
303 (define_insn "cgen_intrinsic_cpsmsbslla1_h_P1"
305 (unspec_volatile:SI [
306 (match_operand:DI 0 "general_operand" "x")
307 (match_operand:DI 1 "general_operand" "x")
310 (unspec_volatile:SI [
315 (unspec_volatile:SI [
320 (unspec_volatile:SI [
325 (unspec_volatile:SI [
329 "CGEN_ENABLE_INSN_P (5)"
330 "cpsmsbslla1.h\\t%0,%1"
331 [(set_attr "may_trap" "no")
332 (set_attr "latency" "0")
333 (set_attr "length" "4")
334 (set_attr "slot" "cop")
335 (set_attr "slots" "p1")
336 (set_attr "stall" "none")])
339 (define_insn "cgen_intrinsic_cpsmsbslua1_h_C3"
341 (unspec_volatile:SI [
342 (match_operand:DI 0 "general_operand" "x")
343 (match_operand:DI 1 "general_operand" "x")
346 (unspec_volatile:SI [
351 (unspec_volatile:SI [
356 (unspec_volatile:SI [
361 (unspec_volatile:SI [
365 "CGEN_ENABLE_INSN_P (6)"
366 "cpsmsbslua1.h\\t%0,%1"
367 [(set_attr "may_trap" "no")
368 (set_attr "latency" "0")
369 (set_attr "length" "4")
370 (set_attr "slot" "cop")
371 (set_attr "slots" "c3")
372 (set_attr "stall" "none")])
375 (define_insn "cgen_intrinsic_cpsmsbslua1_h_P1"
377 (unspec_volatile:SI [
378 (match_operand:DI 0 "general_operand" "x")
379 (match_operand:DI 1 "general_operand" "x")
382 (unspec_volatile:SI [
387 (unspec_volatile:SI [
392 (unspec_volatile:SI [
397 (unspec_volatile:SI [
401 "CGEN_ENABLE_INSN_P (7)"
402 "cpsmsbslua1.h\\t%0,%1"
403 [(set_attr "may_trap" "no")
404 (set_attr "latency" "0")
405 (set_attr "length" "4")
406 (set_attr "slot" "cop")
407 (set_attr "slots" "p1")
408 (set_attr "stall" "none")])
411 (define_insn "cgen_intrinsic_cpsmadslla1_w_C3"
413 (unspec_volatile:SI [
414 (match_operand:DI 0 "general_operand" "x")
415 (match_operand:DI 1 "general_operand" "x")
418 (unspec_volatile:SI [
423 (unspec_volatile:SI [
428 (unspec_volatile:SI [
433 (unspec_volatile:SI [
437 "CGEN_ENABLE_INSN_P (8)"
438 "cpsmadslla1.w\\t%0,%1"
439 [(set_attr "may_trap" "no")
440 (set_attr "latency" "0")
441 (set_attr "length" "4")
442 (set_attr "slot" "cop")
443 (set_attr "slots" "c3")
444 (set_attr "stall" "none")])
447 (define_insn "cgen_intrinsic_cpsmadslla1_w_P1"
449 (unspec_volatile:SI [
450 (match_operand:DI 0 "general_operand" "x")
451 (match_operand:DI 1 "general_operand" "x")
454 (unspec_volatile:SI [
459 (unspec_volatile:SI [
464 (unspec_volatile:SI [
469 (unspec_volatile:SI [
473 "CGEN_ENABLE_INSN_P (9)"
474 "cpsmadslla1.w\\t%0,%1"
475 [(set_attr "may_trap" "no")
476 (set_attr "latency" "0")
477 (set_attr "length" "4")
478 (set_attr "slot" "cop")
479 (set_attr "slots" "p1")
480 (set_attr "stall" "none")])
483 (define_insn "cgen_intrinsic_cpsmadslua1_w_C3"
485 (unspec_volatile:SI [
486 (match_operand:DI 0 "general_operand" "x")
487 (match_operand:DI 1 "general_operand" "x")
490 (unspec_volatile:SI [
495 (unspec_volatile:SI [
500 (unspec_volatile:SI [
505 (unspec_volatile:SI [
509 "CGEN_ENABLE_INSN_P (10)"
510 "cpsmadslua1.w\\t%0,%1"
511 [(set_attr "may_trap" "no")
512 (set_attr "latency" "0")
513 (set_attr "length" "4")
514 (set_attr "slot" "cop")
515 (set_attr "slots" "c3")
516 (set_attr "stall" "none")])
519 (define_insn "cgen_intrinsic_cpsmadslua1_w_P1"
521 (unspec_volatile:SI [
522 (match_operand:DI 0 "general_operand" "x")
523 (match_operand:DI 1 "general_operand" "x")
526 (unspec_volatile:SI [
531 (unspec_volatile:SI [
536 (unspec_volatile:SI [
541 (unspec_volatile:SI [
545 "CGEN_ENABLE_INSN_P (11)"
546 "cpsmadslua1.w\\t%0,%1"
547 [(set_attr "may_trap" "no")
548 (set_attr "latency" "0")
549 (set_attr "length" "4")
550 (set_attr "slot" "cop")
551 (set_attr "slots" "p1")
552 (set_attr "stall" "none")])
555 (define_insn "cgen_intrinsic_cpsmadslla1_h_C3"
557 (unspec_volatile:SI [
558 (match_operand:DI 0 "general_operand" "x")
559 (match_operand:DI 1 "general_operand" "x")
562 (unspec_volatile:SI [
567 (unspec_volatile:SI [
572 (unspec_volatile:SI [
577 (unspec_volatile:SI [
581 "CGEN_ENABLE_INSN_P (12)"
582 "cpsmadslla1.h\\t%0,%1"
583 [(set_attr "may_trap" "no")
584 (set_attr "latency" "0")
585 (set_attr "length" "4")
586 (set_attr "slot" "cop")
587 (set_attr "slots" "c3")
588 (set_attr "stall" "none")])
591 (define_insn "cgen_intrinsic_cpsmadslla1_h_P1"
593 (unspec_volatile:SI [
594 (match_operand:DI 0 "general_operand" "x")
595 (match_operand:DI 1 "general_operand" "x")
598 (unspec_volatile:SI [
603 (unspec_volatile:SI [
608 (unspec_volatile:SI [
613 (unspec_volatile:SI [
617 "CGEN_ENABLE_INSN_P (13)"
618 "cpsmadslla1.h\\t%0,%1"
619 [(set_attr "may_trap" "no")
620 (set_attr "latency" "0")
621 (set_attr "length" "4")
622 (set_attr "slot" "cop")
623 (set_attr "slots" "p1")
624 (set_attr "stall" "none")])
627 (define_insn "cgen_intrinsic_cpsmadslua1_h_C3"
629 (unspec_volatile:SI [
630 (match_operand:DI 0 "general_operand" "x")
631 (match_operand:DI 1 "general_operand" "x")
634 (unspec_volatile:SI [
639 (unspec_volatile:SI [
644 (unspec_volatile:SI [
649 (unspec_volatile:SI [
653 "CGEN_ENABLE_INSN_P (14)"
654 "cpsmadslua1.h\\t%0,%1"
655 [(set_attr "may_trap" "no")
656 (set_attr "latency" "0")
657 (set_attr "length" "4")
658 (set_attr "slot" "cop")
659 (set_attr "slots" "c3")
660 (set_attr "stall" "none")])
663 (define_insn "cgen_intrinsic_cpsmadslua1_h_P1"
665 (unspec_volatile:SI [
666 (match_operand:DI 0 "general_operand" "x")
667 (match_operand:DI 1 "general_operand" "x")
670 (unspec_volatile:SI [
675 (unspec_volatile:SI [
680 (unspec_volatile:SI [
685 (unspec_volatile:SI [
689 "CGEN_ENABLE_INSN_P (15)"
690 "cpsmadslua1.h\\t%0,%1"
691 [(set_attr "may_trap" "no")
692 (set_attr "latency" "0")
693 (set_attr "length" "4")
694 (set_attr "slot" "cop")
695 (set_attr "slots" "p1")
696 (set_attr "stall" "none")])
699 (define_insn "cgen_intrinsic_cpmulslla1_w_C3"
701 (unspec_volatile:SI [
702 (match_operand:DI 0 "general_operand" "x")
703 (match_operand:DI 1 "general_operand" "x")
706 (unspec_volatile:SI [
711 (unspec_volatile:SI [
716 (unspec_volatile:SI [
721 (unspec_volatile:SI [
725 "CGEN_ENABLE_INSN_P (16)"
726 "cpmulslla1.w\\t%0,%1"
727 [(set_attr "may_trap" "no")
728 (set_attr "latency" "0")
729 (set_attr "length" "4")
730 (set_attr "slot" "cop")
731 (set_attr "slots" "c3")
732 (set_attr "stall" "none")])
735 (define_insn "cgen_intrinsic_cpmulslla1_w_P1"
737 (unspec_volatile:SI [
738 (match_operand:DI 0 "general_operand" "x")
739 (match_operand:DI 1 "general_operand" "x")
742 (unspec_volatile:SI [
747 (unspec_volatile:SI [
752 (unspec_volatile:SI [
757 (unspec_volatile:SI [
761 "CGEN_ENABLE_INSN_P (17)"
762 "cpmulslla1.w\\t%0,%1"
763 [(set_attr "may_trap" "no")
764 (set_attr "latency" "0")
765 (set_attr "length" "4")
766 (set_attr "slot" "cop")
767 (set_attr "slots" "p1")
768 (set_attr "stall" "none")])
771 (define_insn "cgen_intrinsic_cpmulslua1_w_C3"
773 (unspec_volatile:SI [
774 (match_operand:DI 0 "general_operand" "x")
775 (match_operand:DI 1 "general_operand" "x")
778 (unspec_volatile:SI [
783 (unspec_volatile:SI [
788 (unspec_volatile:SI [
793 (unspec_volatile:SI [
797 "CGEN_ENABLE_INSN_P (18)"
798 "cpmulslua1.w\\t%0,%1"
799 [(set_attr "may_trap" "no")
800 (set_attr "latency" "0")
801 (set_attr "length" "4")
802 (set_attr "slot" "cop")
803 (set_attr "slots" "c3")
804 (set_attr "stall" "none")])
807 (define_insn "cgen_intrinsic_cpmulslua1_w_P1"
809 (unspec_volatile:SI [
810 (match_operand:DI 0 "general_operand" "x")
811 (match_operand:DI 1 "general_operand" "x")
814 (unspec_volatile:SI [
819 (unspec_volatile:SI [
824 (unspec_volatile:SI [
829 (unspec_volatile:SI [
833 "CGEN_ENABLE_INSN_P (19)"
834 "cpmulslua1.w\\t%0,%1"
835 [(set_attr "may_trap" "no")
836 (set_attr "latency" "0")
837 (set_attr "length" "4")
838 (set_attr "slot" "cop")
839 (set_attr "slots" "p1")
840 (set_attr "stall" "none")])
843 (define_insn "cgen_intrinsic_cpmulslla1_h_C3"
845 (unspec_volatile:SI [
846 (match_operand:DI 0 "general_operand" "x")
847 (match_operand:DI 1 "general_operand" "x")
850 (unspec_volatile:SI [
855 (unspec_volatile:SI [
860 (unspec_volatile:SI [
865 (unspec_volatile:SI [
869 "CGEN_ENABLE_INSN_P (20)"
870 "cpmulslla1.h\\t%0,%1"
871 [(set_attr "may_trap" "no")
872 (set_attr "latency" "0")
873 (set_attr "length" "4")
874 (set_attr "slot" "cop")
875 (set_attr "slots" "c3")
876 (set_attr "stall" "none")])
879 (define_insn "cgen_intrinsic_cpmulslla1_h_P1"
881 (unspec_volatile:SI [
882 (match_operand:DI 0 "general_operand" "x")
883 (match_operand:DI 1 "general_operand" "x")
886 (unspec_volatile:SI [
891 (unspec_volatile:SI [
896 (unspec_volatile:SI [
901 (unspec_volatile:SI [
905 "CGEN_ENABLE_INSN_P (21)"
906 "cpmulslla1.h\\t%0,%1"
907 [(set_attr "may_trap" "no")
908 (set_attr "latency" "0")
909 (set_attr "length" "4")
910 (set_attr "slot" "cop")
911 (set_attr "slots" "p1")
912 (set_attr "stall" "none")])
915 (define_insn "cgen_intrinsic_cpmulslua1_h_C3"
917 (unspec_volatile:SI [
918 (match_operand:DI 0 "general_operand" "x")
919 (match_operand:DI 1 "general_operand" "x")
922 (unspec_volatile:SI [
927 (unspec_volatile:SI [
932 (unspec_volatile:SI [
937 (unspec_volatile:SI [
941 "CGEN_ENABLE_INSN_P (22)"
942 "cpmulslua1.h\\t%0,%1"
943 [(set_attr "may_trap" "no")
944 (set_attr "latency" "0")
945 (set_attr "length" "4")
946 (set_attr "slot" "cop")
947 (set_attr "slots" "c3")
948 (set_attr "stall" "none")])
951 (define_insn "cgen_intrinsic_cpmulslua1_h_P1"
953 (unspec_volatile:SI [
954 (match_operand:DI 0 "general_operand" "x")
955 (match_operand:DI 1 "general_operand" "x")
958 (unspec_volatile:SI [
963 (unspec_volatile:SI [
968 (unspec_volatile:SI [
973 (unspec_volatile:SI [
977 "CGEN_ENABLE_INSN_P (23)"
978 "cpmulslua1.h\\t%0,%1"
979 [(set_attr "may_trap" "no")
980 (set_attr "latency" "0")
981 (set_attr "length" "4")
982 (set_attr "slot" "cop")
983 (set_attr "slots" "p1")
984 (set_attr "stall" "none")])
987 (define_insn "cgen_intrinsic_cpsmsbla1_w_C3"
989 (unspec_volatile:SI [
990 (match_operand:DI 0 "general_operand" "x")
991 (match_operand:DI 1 "general_operand" "x")
994 (unspec_volatile:SI [
999 (unspec_volatile:SI [
1004 (unspec_volatile:SI [
1009 (unspec_volatile:SI [
1013 "CGEN_ENABLE_INSN_P (24)"
1014 "cpsmsbla1.w\\t%0,%1"
1015 [(set_attr "may_trap" "no")
1016 (set_attr "latency" "0")
1017 (set_attr "length" "4")
1018 (set_attr "slot" "cop")
1019 (set_attr "slots" "c3")
1020 (set_attr "stall" "none")])
1023 (define_insn "cgen_intrinsic_cpsmsbla1_w_P1"
1025 (unspec_volatile:SI [
1026 (match_operand:DI 0 "general_operand" "x")
1027 (match_operand:DI 1 "general_operand" "x")
1030 (unspec_volatile:SI [
1035 (unspec_volatile:SI [
1040 (unspec_volatile:SI [
1045 (unspec_volatile:SI [
1049 "CGEN_ENABLE_INSN_P (25)"
1050 "cpsmsbla1.w\\t%0,%1"
1051 [(set_attr "may_trap" "no")
1052 (set_attr "latency" "0")
1053 (set_attr "length" "4")
1054 (set_attr "slot" "cop")
1055 (set_attr "slots" "p1")
1056 (set_attr "stall" "none")])
1059 (define_insn "cgen_intrinsic_cpsmsbua1_w_C3"
1061 (unspec_volatile:SI [
1062 (match_operand:DI 0 "general_operand" "x")
1063 (match_operand:DI 1 "general_operand" "x")
1066 (unspec_volatile:SI [
1071 (unspec_volatile:SI [
1076 (unspec_volatile:SI [
1081 (unspec_volatile:SI [
1085 "CGEN_ENABLE_INSN_P (26)"
1086 "cpsmsbua1.w\\t%0,%1"
1087 [(set_attr "may_trap" "no")
1088 (set_attr "latency" "0")
1089 (set_attr "length" "4")
1090 (set_attr "slot" "cop")
1091 (set_attr "slots" "c3")
1092 (set_attr "stall" "none")])
1095 (define_insn "cgen_intrinsic_cpsmsbua1_w_P1"
1097 (unspec_volatile:SI [
1098 (match_operand:DI 0 "general_operand" "x")
1099 (match_operand:DI 1 "general_operand" "x")
1102 (unspec_volatile:SI [
1107 (unspec_volatile:SI [
1112 (unspec_volatile:SI [
1117 (unspec_volatile:SI [
1121 "CGEN_ENABLE_INSN_P (27)"
1122 "cpsmsbua1.w\\t%0,%1"
1123 [(set_attr "may_trap" "no")
1124 (set_attr "latency" "0")
1125 (set_attr "length" "4")
1126 (set_attr "slot" "cop")
1127 (set_attr "slots" "p1")
1128 (set_attr "stall" "none")])
1131 (define_insn "cgen_intrinsic_cpsmsbla1_h_C3"
1133 (unspec_volatile:SI [
1134 (match_operand:DI 0 "general_operand" "x")
1135 (match_operand:DI 1 "general_operand" "x")
1138 (unspec_volatile:SI [
1143 (unspec_volatile:SI [
1148 (unspec_volatile:SI [
1153 (unspec_volatile:SI [
1157 "CGEN_ENABLE_INSN_P (28)"
1158 "cpsmsbla1.h\\t%0,%1"
1159 [(set_attr "may_trap" "no")
1160 (set_attr "latency" "0")
1161 (set_attr "length" "4")
1162 (set_attr "slot" "cop")
1163 (set_attr "slots" "c3")
1164 (set_attr "stall" "none")])
1167 (define_insn "cgen_intrinsic_cpsmsbla1_h_P1"
1169 (unspec_volatile:SI [
1170 (match_operand:DI 0 "general_operand" "x")
1171 (match_operand:DI 1 "general_operand" "x")
1174 (unspec_volatile:SI [
1179 (unspec_volatile:SI [
1184 (unspec_volatile:SI [
1189 (unspec_volatile:SI [
1193 "CGEN_ENABLE_INSN_P (29)"
1194 "cpsmsbla1.h\\t%0,%1"
1195 [(set_attr "may_trap" "no")
1196 (set_attr "latency" "0")
1197 (set_attr "length" "4")
1198 (set_attr "slot" "cop")
1199 (set_attr "slots" "p1")
1200 (set_attr "stall" "none")])
1203 (define_insn "cgen_intrinsic_cpsmsbua1_h_C3"
1205 (unspec_volatile:SI [
1206 (match_operand:DI 0 "general_operand" "x")
1207 (match_operand:DI 1 "general_operand" "x")
1210 (unspec_volatile:SI [
1215 (unspec_volatile:SI [
1220 (unspec_volatile:SI [
1225 (unspec_volatile:SI [
1229 "CGEN_ENABLE_INSN_P (30)"
1230 "cpsmsbua1.h\\t%0,%1"
1231 [(set_attr "may_trap" "no")
1232 (set_attr "latency" "0")
1233 (set_attr "length" "4")
1234 (set_attr "slot" "cop")
1235 (set_attr "slots" "c3")
1236 (set_attr "stall" "none")])
1239 (define_insn "cgen_intrinsic_cpsmsbua1_h_P1"
1241 (unspec_volatile:SI [
1242 (match_operand:DI 0 "general_operand" "x")
1243 (match_operand:DI 1 "general_operand" "x")
1246 (unspec_volatile:SI [
1251 (unspec_volatile:SI [
1256 (unspec_volatile:SI [
1261 (unspec_volatile:SI [
1265 "CGEN_ENABLE_INSN_P (31)"
1266 "cpsmsbua1.h\\t%0,%1"
1267 [(set_attr "may_trap" "no")
1268 (set_attr "latency" "0")
1269 (set_attr "length" "4")
1270 (set_attr "slot" "cop")
1271 (set_attr "slots" "p1")
1272 (set_attr "stall" "none")])
1275 (define_insn "cgen_intrinsic_cpsmadla1_w_C3"
1277 (unspec_volatile:SI [
1278 (match_operand:DI 0 "general_operand" "x")
1279 (match_operand:DI 1 "general_operand" "x")
1282 (unspec_volatile:SI [
1287 (unspec_volatile:SI [
1292 (unspec_volatile:SI [
1297 (unspec_volatile:SI [
1301 "CGEN_ENABLE_INSN_P (32)"
1302 "cpsmadla1.w\\t%0,%1"
1303 [(set_attr "may_trap" "no")
1304 (set_attr "latency" "0")
1305 (set_attr "length" "4")
1306 (set_attr "slot" "cop")
1307 (set_attr "slots" "c3")
1308 (set_attr "stall" "none")])
1311 (define_insn "cgen_intrinsic_cpsmadla1_w_P1"
1313 (unspec_volatile:SI [
1314 (match_operand:DI 0 "general_operand" "x")
1315 (match_operand:DI 1 "general_operand" "x")
1318 (unspec_volatile:SI [
1323 (unspec_volatile:SI [
1328 (unspec_volatile:SI [
1333 (unspec_volatile:SI [
1337 "CGEN_ENABLE_INSN_P (33)"
1338 "cpsmadla1.w\\t%0,%1"
1339 [(set_attr "may_trap" "no")
1340 (set_attr "latency" "0")
1341 (set_attr "length" "4")
1342 (set_attr "slot" "cop")
1343 (set_attr "slots" "p1")
1344 (set_attr "stall" "none")])
1347 (define_insn "cgen_intrinsic_cpsmadua1_w_C3"
1349 (unspec_volatile:SI [
1350 (match_operand:DI 0 "general_operand" "x")
1351 (match_operand:DI 1 "general_operand" "x")
1354 (unspec_volatile:SI [
1359 (unspec_volatile:SI [
1364 (unspec_volatile:SI [
1369 (unspec_volatile:SI [
1373 "CGEN_ENABLE_INSN_P (34)"
1374 "cpsmadua1.w\\t%0,%1"
1375 [(set_attr "may_trap" "no")
1376 (set_attr "latency" "0")
1377 (set_attr "length" "4")
1378 (set_attr "slot" "cop")
1379 (set_attr "slots" "c3")
1380 (set_attr "stall" "none")])
1383 (define_insn "cgen_intrinsic_cpsmadua1_w_P1"
1385 (unspec_volatile:SI [
1386 (match_operand:DI 0 "general_operand" "x")
1387 (match_operand:DI 1 "general_operand" "x")
1390 (unspec_volatile:SI [
1395 (unspec_volatile:SI [
1400 (unspec_volatile:SI [
1405 (unspec_volatile:SI [
1409 "CGEN_ENABLE_INSN_P (35)"
1410 "cpsmadua1.w\\t%0,%1"
1411 [(set_attr "may_trap" "no")
1412 (set_attr "latency" "0")
1413 (set_attr "length" "4")
1414 (set_attr "slot" "cop")
1415 (set_attr "slots" "p1")
1416 (set_attr "stall" "none")])
1419 (define_insn "cgen_intrinsic_cpsmadla1_h_C3"
1421 (unspec_volatile:SI [
1422 (match_operand:DI 0 "general_operand" "x")
1423 (match_operand:DI 1 "general_operand" "x")
1426 (unspec_volatile:SI [
1431 (unspec_volatile:SI [
1436 (unspec_volatile:SI [
1441 (unspec_volatile:SI [
1445 "CGEN_ENABLE_INSN_P (36)"
1446 "cpsmadla1.h\\t%0,%1"
1447 [(set_attr "may_trap" "no")
1448 (set_attr "latency" "0")
1449 (set_attr "length" "4")
1450 (set_attr "slot" "cop")
1451 (set_attr "slots" "c3")
1452 (set_attr "stall" "none")])
1455 (define_insn "cgen_intrinsic_cpsmadla1_h_P1"
1457 (unspec_volatile:SI [
1458 (match_operand:DI 0 "general_operand" "x")
1459 (match_operand:DI 1 "general_operand" "x")
1462 (unspec_volatile:SI [
1467 (unspec_volatile:SI [
1472 (unspec_volatile:SI [
1477 (unspec_volatile:SI [
1481 "CGEN_ENABLE_INSN_P (37)"
1482 "cpsmadla1.h\\t%0,%1"
1483 [(set_attr "may_trap" "no")
1484 (set_attr "latency" "0")
1485 (set_attr "length" "4")
1486 (set_attr "slot" "cop")
1487 (set_attr "slots" "p1")
1488 (set_attr "stall" "none")])
1491 (define_insn "cgen_intrinsic_cpsmadua1_h_C3"
1493 (unspec_volatile:SI [
1494 (match_operand:DI 0 "general_operand" "x")
1495 (match_operand:DI 1 "general_operand" "x")
1498 (unspec_volatile:SI [
1503 (unspec_volatile:SI [
1508 (unspec_volatile:SI [
1513 (unspec_volatile:SI [
1517 "CGEN_ENABLE_INSN_P (38)"
1518 "cpsmadua1.h\\t%0,%1"
1519 [(set_attr "may_trap" "no")
1520 (set_attr "latency" "0")
1521 (set_attr "length" "4")
1522 (set_attr "slot" "cop")
1523 (set_attr "slots" "c3")
1524 (set_attr "stall" "none")])
1527 (define_insn "cgen_intrinsic_cpsmadua1_h_P1"
1529 (unspec_volatile:SI [
1530 (match_operand:DI 0 "general_operand" "x")
1531 (match_operand:DI 1 "general_operand" "x")
1534 (unspec_volatile:SI [
1539 (unspec_volatile:SI [
1544 (unspec_volatile:SI [
1549 (unspec_volatile:SI [
1553 "CGEN_ENABLE_INSN_P (39)"
1554 "cpsmadua1.h\\t%0,%1"
1555 [(set_attr "may_trap" "no")
1556 (set_attr "latency" "0")
1557 (set_attr "length" "4")
1558 (set_attr "slot" "cop")
1559 (set_attr "slots" "p1")
1560 (set_attr "stall" "none")])
1563 (define_insn "cgen_intrinsic_cpmsbla1_w_C3"
1565 (unspec_volatile:SI [
1566 (match_operand:DI 0 "general_operand" "x")
1567 (match_operand:DI 1 "general_operand" "x")
1570 (unspec_volatile:SI [
1575 (unspec_volatile:SI [
1580 (unspec_volatile:SI [
1585 (unspec_volatile:SI [
1589 "CGEN_ENABLE_INSN_P (40)"
1590 "cpmsbla1.w\\t%0,%1"
1591 [(set_attr "may_trap" "no")
1592 (set_attr "latency" "0")
1593 (set_attr "length" "4")
1594 (set_attr "slot" "cop")
1595 (set_attr "slots" "c3")
1596 (set_attr "stall" "none")])
1599 (define_insn "cgen_intrinsic_cpmsbla1_w_P1"
1601 (unspec_volatile:SI [
1602 (match_operand:DI 0 "general_operand" "x")
1603 (match_operand:DI 1 "general_operand" "x")
1606 (unspec_volatile:SI [
1611 (unspec_volatile:SI [
1616 (unspec_volatile:SI [
1621 (unspec_volatile:SI [
1625 "CGEN_ENABLE_INSN_P (41)"
1626 "cpmsbla1.w\\t%0,%1"
1627 [(set_attr "may_trap" "no")
1628 (set_attr "latency" "0")
1629 (set_attr "length" "4")
1630 (set_attr "slot" "cop")
1631 (set_attr "slots" "p1")
1632 (set_attr "stall" "none")])
1635 (define_insn "cgen_intrinsic_cpmsbua1_w_C3"
1637 (unspec_volatile:SI [
1638 (match_operand:DI 0 "general_operand" "x")
1639 (match_operand:DI 1 "general_operand" "x")
1642 (unspec_volatile:SI [
1647 (unspec_volatile:SI [
1652 (unspec_volatile:SI [
1657 (unspec_volatile:SI [
1661 "CGEN_ENABLE_INSN_P (42)"
1662 "cpmsbua1.w\\t%0,%1"
1663 [(set_attr "may_trap" "no")
1664 (set_attr "latency" "0")
1665 (set_attr "length" "4")
1666 (set_attr "slot" "cop")
1667 (set_attr "slots" "c3")
1668 (set_attr "stall" "none")])
1671 (define_insn "cgen_intrinsic_cpmsbua1_w_P1"
1673 (unspec_volatile:SI [
1674 (match_operand:DI 0 "general_operand" "x")
1675 (match_operand:DI 1 "general_operand" "x")
1678 (unspec_volatile:SI [
1683 (unspec_volatile:SI [
1688 (unspec_volatile:SI [
1693 (unspec_volatile:SI [
1697 "CGEN_ENABLE_INSN_P (43)"
1698 "cpmsbua1.w\\t%0,%1"
1699 [(set_attr "may_trap" "no")
1700 (set_attr "latency" "0")
1701 (set_attr "length" "4")
1702 (set_attr "slot" "cop")
1703 (set_attr "slots" "p1")
1704 (set_attr "stall" "none")])
1707 (define_insn "cgen_intrinsic_cpmsbla1u_w_C3"
1709 (unspec_volatile:SI [
1710 (match_operand:DI 0 "general_operand" "x")
1711 (match_operand:DI 1 "general_operand" "x")
1714 (unspec_volatile:SI [
1719 (unspec_volatile:SI [
1724 (unspec_volatile:SI [
1729 (unspec_volatile:SI [
1733 "CGEN_ENABLE_INSN_P (44)"
1734 "cpmsbla1u.w\\t%0,%1"
1735 [(set_attr "may_trap" "no")
1736 (set_attr "latency" "0")
1737 (set_attr "length" "4")
1738 (set_attr "slot" "cop")
1739 (set_attr "slots" "c3")
1740 (set_attr "stall" "none")])
1743 (define_insn "cgen_intrinsic_cpmsbla1u_w_P1"
1745 (unspec_volatile:SI [
1746 (match_operand:DI 0 "general_operand" "x")
1747 (match_operand:DI 1 "general_operand" "x")
1750 (unspec_volatile:SI [
1755 (unspec_volatile:SI [
1760 (unspec_volatile:SI [
1765 (unspec_volatile:SI [
1769 "CGEN_ENABLE_INSN_P (45)"
1770 "cpmsbla1u.w\\t%0,%1"
1771 [(set_attr "may_trap" "no")
1772 (set_attr "latency" "0")
1773 (set_attr "length" "4")
1774 (set_attr "slot" "cop")
1775 (set_attr "slots" "p1")
1776 (set_attr "stall" "none")])
1779 (define_insn "cgen_intrinsic_cpmsbua1u_w_C3"
1781 (unspec_volatile:SI [
1782 (match_operand:DI 0 "general_operand" "x")
1783 (match_operand:DI 1 "general_operand" "x")
1786 (unspec_volatile:SI [
1791 (unspec_volatile:SI [
1796 (unspec_volatile:SI [
1801 (unspec_volatile:SI [
1805 "CGEN_ENABLE_INSN_P (46)"
1806 "cpmsbua1u.w\\t%0,%1"
1807 [(set_attr "may_trap" "no")
1808 (set_attr "latency" "0")
1809 (set_attr "length" "4")
1810 (set_attr "slot" "cop")
1811 (set_attr "slots" "c3")
1812 (set_attr "stall" "none")])
1815 (define_insn "cgen_intrinsic_cpmsbua1u_w_P1"
1817 (unspec_volatile:SI [
1818 (match_operand:DI 0 "general_operand" "x")
1819 (match_operand:DI 1 "general_operand" "x")
1822 (unspec_volatile:SI [
1827 (unspec_volatile:SI [
1832 (unspec_volatile:SI [
1837 (unspec_volatile:SI [
1841 "CGEN_ENABLE_INSN_P (47)"
1842 "cpmsbua1u.w\\t%0,%1"
1843 [(set_attr "may_trap" "no")
1844 (set_attr "latency" "0")
1845 (set_attr "length" "4")
1846 (set_attr "slot" "cop")
1847 (set_attr "slots" "p1")
1848 (set_attr "stall" "none")])
1851 (define_insn "cgen_intrinsic_cpmsbla1_h_C3"
1853 (unspec_volatile:SI [
1854 (match_operand:DI 0 "general_operand" "x")
1855 (match_operand:DI 1 "general_operand" "x")
1858 (unspec_volatile:SI [
1863 (unspec_volatile:SI [
1868 (unspec_volatile:SI [
1873 (unspec_volatile:SI [
1877 "CGEN_ENABLE_INSN_P (48)"
1878 "cpmsbla1.h\\t%0,%1"
1879 [(set_attr "may_trap" "no")
1880 (set_attr "latency" "0")
1881 (set_attr "length" "4")
1882 (set_attr "slot" "cop")
1883 (set_attr "slots" "c3")
1884 (set_attr "stall" "none")])
1887 (define_insn "cgen_intrinsic_cpmsbla1_h_P1"
1889 (unspec_volatile:SI [
1890 (match_operand:DI 0 "general_operand" "x")
1891 (match_operand:DI 1 "general_operand" "x")
1894 (unspec_volatile:SI [
1899 (unspec_volatile:SI [
1904 (unspec_volatile:SI [
1909 (unspec_volatile:SI [
1913 "CGEN_ENABLE_INSN_P (49)"
1914 "cpmsbla1.h\\t%0,%1"
1915 [(set_attr "may_trap" "no")
1916 (set_attr "latency" "0")
1917 (set_attr "length" "4")
1918 (set_attr "slot" "cop")
1919 (set_attr "slots" "p1")
1920 (set_attr "stall" "none")])
1923 (define_insn "cgen_intrinsic_cpmsbua1_h_C3"
1925 (unspec_volatile:SI [
1926 (match_operand:DI 0 "general_operand" "x")
1927 (match_operand:DI 1 "general_operand" "x")
1930 (unspec_volatile:SI [
1935 (unspec_volatile:SI [
1940 (unspec_volatile:SI [
1945 (unspec_volatile:SI [
1949 "CGEN_ENABLE_INSN_P (50)"
1950 "cpmsbua1.h\\t%0,%1"
1951 [(set_attr "may_trap" "no")
1952 (set_attr "latency" "0")
1953 (set_attr "length" "4")
1954 (set_attr "slot" "cop")
1955 (set_attr "slots" "c3")
1956 (set_attr "stall" "none")])
1959 (define_insn "cgen_intrinsic_cpmsbua1_h_P1"
1961 (unspec_volatile:SI [
1962 (match_operand:DI 0 "general_operand" "x")
1963 (match_operand:DI 1 "general_operand" "x")
1966 (unspec_volatile:SI [
1971 (unspec_volatile:SI [
1976 (unspec_volatile:SI [
1981 (unspec_volatile:SI [
1985 "CGEN_ENABLE_INSN_P (51)"
1986 "cpmsbua1.h\\t%0,%1"
1987 [(set_attr "may_trap" "no")
1988 (set_attr "latency" "0")
1989 (set_attr "length" "4")
1990 (set_attr "slot" "cop")
1991 (set_attr "slots" "p1")
1992 (set_attr "stall" "none")])
1995 (define_insn "cgen_intrinsic_cpmadla1_w_C3"
1997 (unspec_volatile:SI [
1998 (match_operand:DI 0 "general_operand" "x")
1999 (match_operand:DI 1 "general_operand" "x")
2002 (unspec_volatile:SI [
2007 (unspec_volatile:SI [
2012 (unspec_volatile:SI [
2017 (unspec_volatile:SI [
2021 "CGEN_ENABLE_INSN_P (52)"
2022 "cpmadla1.w\\t%0,%1"
2023 [(set_attr "may_trap" "no")
2024 (set_attr "latency" "0")
2025 (set_attr "length" "4")
2026 (set_attr "slot" "cop")
2027 (set_attr "slots" "c3")
2028 (set_attr "stall" "none")])
2031 (define_insn "cgen_intrinsic_cpmadla1_w_P1"
2033 (unspec_volatile:SI [
2034 (match_operand:DI 0 "general_operand" "x")
2035 (match_operand:DI 1 "general_operand" "x")
2038 (unspec_volatile:SI [
2043 (unspec_volatile:SI [
2048 (unspec_volatile:SI [
2053 (unspec_volatile:SI [
2057 "CGEN_ENABLE_INSN_P (53)"
2058 "cpmadla1.w\\t%0,%1"
2059 [(set_attr "may_trap" "no")
2060 (set_attr "latency" "0")
2061 (set_attr "length" "4")
2062 (set_attr "slot" "cop")
2063 (set_attr "slots" "p1")
2064 (set_attr "stall" "none")])
2067 (define_insn "cgen_intrinsic_cpmadua1_w_C3"
2069 (unspec_volatile:SI [
2070 (match_operand:DI 0 "general_operand" "x")
2071 (match_operand:DI 1 "general_operand" "x")
2074 (unspec_volatile:SI [
2079 (unspec_volatile:SI [
2084 (unspec_volatile:SI [
2089 (unspec_volatile:SI [
2093 "CGEN_ENABLE_INSN_P (54)"
2094 "cpmadua1.w\\t%0,%1"
2095 [(set_attr "may_trap" "no")
2096 (set_attr "latency" "0")
2097 (set_attr "length" "4")
2098 (set_attr "slot" "cop")
2099 (set_attr "slots" "c3")
2100 (set_attr "stall" "none")])
2103 (define_insn "cgen_intrinsic_cpmadua1_w_P1"
2105 (unspec_volatile:SI [
2106 (match_operand:DI 0 "general_operand" "x")
2107 (match_operand:DI 1 "general_operand" "x")
2110 (unspec_volatile:SI [
2115 (unspec_volatile:SI [
2120 (unspec_volatile:SI [
2125 (unspec_volatile:SI [
2129 "CGEN_ENABLE_INSN_P (55)"
2130 "cpmadua1.w\\t%0,%1"
2131 [(set_attr "may_trap" "no")
2132 (set_attr "latency" "0")
2133 (set_attr "length" "4")
2134 (set_attr "slot" "cop")
2135 (set_attr "slots" "p1")
2136 (set_attr "stall" "none")])
2139 (define_insn "cgen_intrinsic_cpmadla1u_w_C3"
2141 (unspec_volatile:SI [
2142 (match_operand:DI 0 "general_operand" "x")
2143 (match_operand:DI 1 "general_operand" "x")
2146 (unspec_volatile:SI [
2151 (unspec_volatile:SI [
2156 (unspec_volatile:SI [
2161 (unspec_volatile:SI [
2165 "CGEN_ENABLE_INSN_P (56)"
2166 "cpmadla1u.w\\t%0,%1"
2167 [(set_attr "may_trap" "no")
2168 (set_attr "latency" "0")
2169 (set_attr "length" "4")
2170 (set_attr "slot" "cop")
2171 (set_attr "slots" "c3")
2172 (set_attr "stall" "none")])
2175 (define_insn "cgen_intrinsic_cpmadla1u_w_P1"
2177 (unspec_volatile:SI [
2178 (match_operand:DI 0 "general_operand" "x")
2179 (match_operand:DI 1 "general_operand" "x")
2182 (unspec_volatile:SI [
2187 (unspec_volatile:SI [
2192 (unspec_volatile:SI [
2197 (unspec_volatile:SI [
2201 "CGEN_ENABLE_INSN_P (57)"
2202 "cpmadla1u.w\\t%0,%1"
2203 [(set_attr "may_trap" "no")
2204 (set_attr "latency" "0")
2205 (set_attr "length" "4")
2206 (set_attr "slot" "cop")
2207 (set_attr "slots" "p1")
2208 (set_attr "stall" "none")])
2211 (define_insn "cgen_intrinsic_cpmadua1u_w_C3"
2213 (unspec_volatile:SI [
2214 (match_operand:DI 0 "general_operand" "x")
2215 (match_operand:DI 1 "general_operand" "x")
2218 (unspec_volatile:SI [
2223 (unspec_volatile:SI [
2228 (unspec_volatile:SI [
2233 (unspec_volatile:SI [
2237 "CGEN_ENABLE_INSN_P (58)"
2238 "cpmadua1u.w\\t%0,%1"
2239 [(set_attr "may_trap" "no")
2240 (set_attr "latency" "0")
2241 (set_attr "length" "4")
2242 (set_attr "slot" "cop")
2243 (set_attr "slots" "c3")
2244 (set_attr "stall" "none")])
2247 (define_insn "cgen_intrinsic_cpmadua1u_w_P1"
2249 (unspec_volatile:SI [
2250 (match_operand:DI 0 "general_operand" "x")
2251 (match_operand:DI 1 "general_operand" "x")
2254 (unspec_volatile:SI [
2259 (unspec_volatile:SI [
2264 (unspec_volatile:SI [
2269 (unspec_volatile:SI [
2273 "CGEN_ENABLE_INSN_P (59)"
2274 "cpmadua1u.w\\t%0,%1"
2275 [(set_attr "may_trap" "no")
2276 (set_attr "latency" "0")
2277 (set_attr "length" "4")
2278 (set_attr "slot" "cop")
2279 (set_attr "slots" "p1")
2280 (set_attr "stall" "none")])
2283 (define_insn "cgen_intrinsic_cpmadla1_h_C3"
2285 (unspec_volatile:SI [
2286 (match_operand:DI 0 "general_operand" "x")
2287 (match_operand:DI 1 "general_operand" "x")
2290 (unspec_volatile:SI [
2295 (unspec_volatile:SI [
2300 (unspec_volatile:SI [
2305 (unspec_volatile:SI [
2309 "CGEN_ENABLE_INSN_P (60)"
2310 "cpmadla1.h\\t%0,%1"
2311 [(set_attr "may_trap" "no")
2312 (set_attr "latency" "0")
2313 (set_attr "length" "4")
2314 (set_attr "slot" "cop")
2315 (set_attr "slots" "c3")
2316 (set_attr "stall" "none")])
2319 (define_insn "cgen_intrinsic_cpmadla1_h_P1"
2321 (unspec_volatile:SI [
2322 (match_operand:DI 0 "general_operand" "x")
2323 (match_operand:DI 1 "general_operand" "x")
2326 (unspec_volatile:SI [
2331 (unspec_volatile:SI [
2336 (unspec_volatile:SI [
2341 (unspec_volatile:SI [
2345 "CGEN_ENABLE_INSN_P (61)"
2346 "cpmadla1.h\\t%0,%1"
2347 [(set_attr "may_trap" "no")
2348 (set_attr "latency" "0")
2349 (set_attr "length" "4")
2350 (set_attr "slot" "cop")
2351 (set_attr "slots" "p1")
2352 (set_attr "stall" "none")])
2355 (define_insn "cgen_intrinsic_cpmadua1_h_C3"
2357 (unspec_volatile:SI [
2358 (match_operand:DI 0 "general_operand" "x")
2359 (match_operand:DI 1 "general_operand" "x")
2362 (unspec_volatile:SI [
2367 (unspec_volatile:SI [
2372 (unspec_volatile:SI [
2377 (unspec_volatile:SI [
2381 "CGEN_ENABLE_INSN_P (62)"
2382 "cpmadua1.h\\t%0,%1"
2383 [(set_attr "may_trap" "no")
2384 (set_attr "latency" "0")
2385 (set_attr "length" "4")
2386 (set_attr "slot" "cop")
2387 (set_attr "slots" "c3")
2388 (set_attr "stall" "none")])
2391 (define_insn "cgen_intrinsic_cpmadua1_h_P1"
2393 (unspec_volatile:SI [
2394 (match_operand:DI 0 "general_operand" "x")
2395 (match_operand:DI 1 "general_operand" "x")
2398 (unspec_volatile:SI [
2403 (unspec_volatile:SI [
2408 (unspec_volatile:SI [
2413 (unspec_volatile:SI [
2417 "CGEN_ENABLE_INSN_P (63)"
2418 "cpmadua1.h\\t%0,%1"
2419 [(set_attr "may_trap" "no")
2420 (set_attr "latency" "0")
2421 (set_attr "length" "4")
2422 (set_attr "slot" "cop")
2423 (set_attr "slots" "p1")
2424 (set_attr "stall" "none")])
2427 (define_insn "cgen_intrinsic_cpmada1_b_C3"
2429 (unspec_volatile:SI [
2430 (match_operand:DI 0 "general_operand" "x")
2431 (match_operand:DI 1 "general_operand" "x")
2434 (unspec_volatile:SI [
2439 (unspec_volatile:SI [
2444 (unspec_volatile:SI [
2449 (unspec_volatile:SI [
2454 (unspec_volatile:SI [
2459 (unspec_volatile:SI [
2464 (unspec_volatile:SI [
2469 (unspec_volatile:SI [
2473 "CGEN_ENABLE_INSN_P (64)"
2475 [(set_attr "may_trap" "no")
2476 (set_attr "latency" "0")
2477 (set_attr "length" "4")
2478 (set_attr "slot" "cop")
2479 (set_attr "slots" "c3")
2480 (set_attr "stall" "none")])
2483 (define_insn "cgen_intrinsic_cpmada1_b_P1"
2485 (unspec_volatile:SI [
2486 (match_operand:DI 0 "general_operand" "x")
2487 (match_operand:DI 1 "general_operand" "x")
2490 (unspec_volatile:SI [
2495 (unspec_volatile:SI [
2500 (unspec_volatile:SI [
2505 (unspec_volatile:SI [
2510 (unspec_volatile:SI [
2515 (unspec_volatile:SI [
2520 (unspec_volatile:SI [
2525 (unspec_volatile:SI [
2529 "CGEN_ENABLE_INSN_P (65)"
2531 [(set_attr "may_trap" "no")
2532 (set_attr "latency" "0")
2533 (set_attr "length" "4")
2534 (set_attr "slot" "cop")
2535 (set_attr "slots" "p1")
2536 (set_attr "stall" "none")])
2539 (define_insn "cgen_intrinsic_cpmada1u_b_C3"
2541 (unspec_volatile:SI [
2542 (match_operand:DI 0 "general_operand" "x")
2543 (match_operand:DI 1 "general_operand" "x")
2546 (unspec_volatile:SI [
2551 (unspec_volatile:SI [
2556 (unspec_volatile:SI [
2561 (unspec_volatile:SI [
2566 (unspec_volatile:SI [
2571 (unspec_volatile:SI [
2576 (unspec_volatile:SI [
2581 (unspec_volatile:SI [
2585 "CGEN_ENABLE_INSN_P (66)"
2586 "cpmada1u.b\\t%0,%1"
2587 [(set_attr "may_trap" "no")
2588 (set_attr "latency" "0")
2589 (set_attr "length" "4")
2590 (set_attr "slot" "cop")
2591 (set_attr "slots" "c3")
2592 (set_attr "stall" "none")])
2595 (define_insn "cgen_intrinsic_cpmada1u_b_P1"
2597 (unspec_volatile:SI [
2598 (match_operand:DI 0 "general_operand" "x")
2599 (match_operand:DI 1 "general_operand" "x")
2602 (unspec_volatile:SI [
2607 (unspec_volatile:SI [
2612 (unspec_volatile:SI [
2617 (unspec_volatile:SI [
2622 (unspec_volatile:SI [
2627 (unspec_volatile:SI [
2632 (unspec_volatile:SI [
2637 (unspec_volatile:SI [
2641 "CGEN_ENABLE_INSN_P (67)"
2642 "cpmada1u.b\\t%0,%1"
2643 [(set_attr "may_trap" "no")
2644 (set_attr "latency" "0")
2645 (set_attr "length" "4")
2646 (set_attr "slot" "cop")
2647 (set_attr "slots" "p1")
2648 (set_attr "stall" "none")])
2651 (define_insn "cgen_intrinsic_cpmulla1_w_C3"
2653 (unspec_volatile:SI [
2654 (match_operand:DI 0 "general_operand" "x")
2655 (match_operand:DI 1 "general_operand" "x")
2658 (unspec_volatile:SI [
2663 (unspec_volatile:SI [
2668 (unspec_volatile:SI [
2672 "CGEN_ENABLE_INSN_P (68)"
2673 "cpmulla1.w\\t%0,%1"
2674 [(set_attr "may_trap" "no")
2675 (set_attr "latency" "0")
2676 (set_attr "length" "4")
2677 (set_attr "slot" "cop")
2678 (set_attr "slots" "c3")
2679 (set_attr "stall" "none")])
2682 (define_insn "cgen_intrinsic_cpmulla1_w_P1"
2684 (unspec_volatile:SI [
2685 (match_operand:DI 0 "general_operand" "x")
2686 (match_operand:DI 1 "general_operand" "x")
2689 (unspec_volatile:SI [
2694 (unspec_volatile:SI [
2699 (unspec_volatile:SI [
2703 "CGEN_ENABLE_INSN_P (69)"
2704 "cpmulla1.w\\t%0,%1"
2705 [(set_attr "may_trap" "no")
2706 (set_attr "latency" "0")
2707 (set_attr "length" "4")
2708 (set_attr "slot" "cop")
2709 (set_attr "slots" "p1")
2710 (set_attr "stall" "none")])
2713 (define_insn "cgen_intrinsic_cpmulua1_w_C3"
2715 (unspec_volatile:SI [
2716 (match_operand:DI 0 "general_operand" "x")
2717 (match_operand:DI 1 "general_operand" "x")
2720 (unspec_volatile:SI [
2725 (unspec_volatile:SI [
2730 (unspec_volatile:SI [
2734 "CGEN_ENABLE_INSN_P (70)"
2735 "cpmulua1.w\\t%0,%1"
2736 [(set_attr "may_trap" "no")
2737 (set_attr "latency" "0")
2738 (set_attr "length" "4")
2739 (set_attr "slot" "cop")
2740 (set_attr "slots" "c3")
2741 (set_attr "stall" "none")])
2744 (define_insn "cgen_intrinsic_cpmulua1_w_P1"
2746 (unspec_volatile:SI [
2747 (match_operand:DI 0 "general_operand" "x")
2748 (match_operand:DI 1 "general_operand" "x")
2751 (unspec_volatile:SI [
2756 (unspec_volatile:SI [
2761 (unspec_volatile:SI [
2765 "CGEN_ENABLE_INSN_P (71)"
2766 "cpmulua1.w\\t%0,%1"
2767 [(set_attr "may_trap" "no")
2768 (set_attr "latency" "0")
2769 (set_attr "length" "4")
2770 (set_attr "slot" "cop")
2771 (set_attr "slots" "p1")
2772 (set_attr "stall" "none")])
2775 (define_insn "cgen_intrinsic_cpmulla1u_w_C3"
2777 (unspec_volatile:SI [
2778 (match_operand:DI 0 "general_operand" "x")
2779 (match_operand:DI 1 "general_operand" "x")
2782 (unspec_volatile:SI [
2787 (unspec_volatile:SI [
2792 (unspec_volatile:SI [
2796 "CGEN_ENABLE_INSN_P (72)"
2797 "cpmulla1u.w\\t%0,%1"
2798 [(set_attr "may_trap" "no")
2799 (set_attr "latency" "0")
2800 (set_attr "length" "4")
2801 (set_attr "slot" "cop")
2802 (set_attr "slots" "c3")
2803 (set_attr "stall" "none")])
2806 (define_insn "cgen_intrinsic_cpmulla1u_w_P1"
2808 (unspec_volatile:SI [
2809 (match_operand:DI 0 "general_operand" "x")
2810 (match_operand:DI 1 "general_operand" "x")
2813 (unspec_volatile:SI [
2818 (unspec_volatile:SI [
2823 (unspec_volatile:SI [
2827 "CGEN_ENABLE_INSN_P (73)"
2828 "cpmulla1u.w\\t%0,%1"
2829 [(set_attr "may_trap" "no")
2830 (set_attr "latency" "0")
2831 (set_attr "length" "4")
2832 (set_attr "slot" "cop")
2833 (set_attr "slots" "p1")
2834 (set_attr "stall" "none")])
2837 (define_insn "cgen_intrinsic_cpmulua1u_w_C3"
2839 (unspec_volatile:SI [
2840 (match_operand:DI 0 "general_operand" "x")
2841 (match_operand:DI 1 "general_operand" "x")
2844 (unspec_volatile:SI [
2849 (unspec_volatile:SI [
2854 (unspec_volatile:SI [
2858 "CGEN_ENABLE_INSN_P (74)"
2859 "cpmulua1u.w\\t%0,%1"
2860 [(set_attr "may_trap" "no")
2861 (set_attr "latency" "0")
2862 (set_attr "length" "4")
2863 (set_attr "slot" "cop")
2864 (set_attr "slots" "c3")
2865 (set_attr "stall" "none")])
2868 (define_insn "cgen_intrinsic_cpmulua1u_w_P1"
2870 (unspec_volatile:SI [
2871 (match_operand:DI 0 "general_operand" "x")
2872 (match_operand:DI 1 "general_operand" "x")
2875 (unspec_volatile:SI [
2880 (unspec_volatile:SI [
2885 (unspec_volatile:SI [
2889 "CGEN_ENABLE_INSN_P (75)"
2890 "cpmulua1u.w\\t%0,%1"
2891 [(set_attr "may_trap" "no")
2892 (set_attr "latency" "0")
2893 (set_attr "length" "4")
2894 (set_attr "slot" "cop")
2895 (set_attr "slots" "p1")
2896 (set_attr "stall" "none")])
2899 (define_insn "cgen_intrinsic_cpmulla1_h_C3"
2901 (unspec_volatile:SI [
2902 (match_operand:DI 0 "general_operand" "x")
2903 (match_operand:DI 1 "general_operand" "x")
2906 (unspec_volatile:SI [
2911 (unspec_volatile:SI [
2916 (unspec_volatile:SI [
2920 "CGEN_ENABLE_INSN_P (76)"
2921 "cpmulla1.h\\t%0,%1"
2922 [(set_attr "may_trap" "no")
2923 (set_attr "latency" "0")
2924 (set_attr "length" "4")
2925 (set_attr "slot" "cop")
2926 (set_attr "slots" "c3")
2927 (set_attr "stall" "none")])
2930 (define_insn "cgen_intrinsic_cpmulla1_h_P1"
2932 (unspec_volatile:SI [
2933 (match_operand:DI 0 "general_operand" "x")
2934 (match_operand:DI 1 "general_operand" "x")
2937 (unspec_volatile:SI [
2942 (unspec_volatile:SI [
2947 (unspec_volatile:SI [
2951 "CGEN_ENABLE_INSN_P (77)"
2952 "cpmulla1.h\\t%0,%1"
2953 [(set_attr "may_trap" "no")
2954 (set_attr "latency" "0")
2955 (set_attr "length" "4")
2956 (set_attr "slot" "cop")
2957 (set_attr "slots" "p1")
2958 (set_attr "stall" "none")])
2961 (define_insn "cgen_intrinsic_cpmulua1_h_C3"
2963 (unspec_volatile:SI [
2964 (match_operand:DI 0 "general_operand" "x")
2965 (match_operand:DI 1 "general_operand" "x")
2968 (unspec_volatile:SI [
2973 (unspec_volatile:SI [
2978 (unspec_volatile:SI [
2982 "CGEN_ENABLE_INSN_P (78)"
2983 "cpmulua1.h\\t%0,%1"
2984 [(set_attr "may_trap" "no")
2985 (set_attr "latency" "0")
2986 (set_attr "length" "4")
2987 (set_attr "slot" "cop")
2988 (set_attr "slots" "c3")
2989 (set_attr "stall" "none")])
2992 (define_insn "cgen_intrinsic_cpmulua1_h_P1"
2994 (unspec_volatile:SI [
2995 (match_operand:DI 0 "general_operand" "x")
2996 (match_operand:DI 1 "general_operand" "x")
2999 (unspec_volatile:SI [
3004 (unspec_volatile:SI [
3009 (unspec_volatile:SI [
3013 "CGEN_ENABLE_INSN_P (79)"
3014 "cpmulua1.h\\t%0,%1"
3015 [(set_attr "may_trap" "no")
3016 (set_attr "latency" "0")
3017 (set_attr "length" "4")
3018 (set_attr "slot" "cop")
3019 (set_attr "slots" "p1")
3020 (set_attr "stall" "none")])
3023 (define_insn "cgen_intrinsic_cpmula1_b_C3"
3025 (unspec_volatile:SI [
3026 (match_operand:DI 0 "general_operand" "x")
3027 (match_operand:DI 1 "general_operand" "x")
3030 (unspec_volatile:SI [
3035 (unspec_volatile:SI [
3040 (unspec_volatile:SI [
3045 (unspec_volatile:SI [
3050 (unspec_volatile:SI [
3055 (unspec_volatile:SI [
3060 (unspec_volatile:SI [
3064 "CGEN_ENABLE_INSN_P (80)"
3066 [(set_attr "may_trap" "no")
3067 (set_attr "latency" "0")
3068 (set_attr "length" "4")
3069 (set_attr "slot" "cop")
3070 (set_attr "slots" "c3")
3071 (set_attr "stall" "none")])
3074 (define_insn "cgen_intrinsic_cpmula1_b_P1"
3076 (unspec_volatile:SI [
3077 (match_operand:DI 0 "general_operand" "x")
3078 (match_operand:DI 1 "general_operand" "x")
3081 (unspec_volatile:SI [
3086 (unspec_volatile:SI [
3091 (unspec_volatile:SI [
3096 (unspec_volatile:SI [
3101 (unspec_volatile:SI [
3106 (unspec_volatile:SI [
3111 (unspec_volatile:SI [
3115 "CGEN_ENABLE_INSN_P (81)"
3117 [(set_attr "may_trap" "no")
3118 (set_attr "latency" "0")
3119 (set_attr "length" "4")
3120 (set_attr "slot" "cop")
3121 (set_attr "slots" "p1")
3122 (set_attr "stall" "none")])
3125 (define_insn "cgen_intrinsic_cpmula1u_b_C3"
3127 (unspec_volatile:SI [
3128 (match_operand:DI 0 "general_operand" "x")
3129 (match_operand:DI 1 "general_operand" "x")
3132 (unspec_volatile:SI [
3137 (unspec_volatile:SI [
3142 (unspec_volatile:SI [
3147 (unspec_volatile:SI [
3152 (unspec_volatile:SI [
3157 (unspec_volatile:SI [
3162 (unspec_volatile:SI [
3166 "CGEN_ENABLE_INSN_P (82)"
3167 "cpmula1u.b\\t%0,%1"
3168 [(set_attr "may_trap" "no")
3169 (set_attr "latency" "0")
3170 (set_attr "length" "4")
3171 (set_attr "slot" "cop")
3172 (set_attr "slots" "c3")
3173 (set_attr "stall" "none")])
3176 (define_insn "cgen_intrinsic_cpmula1u_b_P1"
3178 (unspec_volatile:SI [
3179 (match_operand:DI 0 "general_operand" "x")
3180 (match_operand:DI 1 "general_operand" "x")
3183 (unspec_volatile:SI [
3188 (unspec_volatile:SI [
3193 (unspec_volatile:SI [
3198 (unspec_volatile:SI [
3203 (unspec_volatile:SI [
3208 (unspec_volatile:SI [
3213 (unspec_volatile:SI [
3217 "CGEN_ENABLE_INSN_P (83)"
3218 "cpmula1u.b\\t%0,%1"
3219 [(set_attr "may_trap" "no")
3220 (set_attr "latency" "0")
3221 (set_attr "length" "4")
3222 (set_attr "slot" "cop")
3223 (set_attr "slots" "p1")
3224 (set_attr "stall" "none")])
3227 (define_insn "cgen_intrinsic_cpssda1_b_C3"
3229 (unspec_volatile:SI [
3230 (match_operand:DI 0 "general_operand" "x")
3231 (match_operand:DI 1 "general_operand" "x")
3234 (unspec_volatile:SI [
3239 (unspec_volatile:SI [
3244 (unspec_volatile:SI [
3249 (unspec_volatile:SI [
3254 (unspec_volatile:SI [
3259 (unspec_volatile:SI [
3264 (unspec_volatile:SI [
3269 (unspec_volatile:SI [
3273 "CGEN_ENABLE_INSN_P (84)"
3275 [(set_attr "may_trap" "no")
3276 (set_attr "latency" "0")
3277 (set_attr "length" "4")
3278 (set_attr "slot" "cop")
3279 (set_attr "slots" "c3")
3280 (set_attr "stall" "none")])
3283 (define_insn "cgen_intrinsic_cpssda1_b_P1"
3285 (unspec_volatile:SI [
3286 (match_operand:DI 0 "general_operand" "x")
3287 (match_operand:DI 1 "general_operand" "x")
3290 (unspec_volatile:SI [
3295 (unspec_volatile:SI [
3300 (unspec_volatile:SI [
3305 (unspec_volatile:SI [
3310 (unspec_volatile:SI [
3315 (unspec_volatile:SI [
3320 (unspec_volatile:SI [
3324 "CGEN_ENABLE_INSN_P (85)"
3326 [(set_attr "may_trap" "no")
3327 (set_attr "latency" "0")
3328 (set_attr "length" "4")
3329 (set_attr "slot" "cop")
3330 (set_attr "slots" "p1")
3331 (set_attr "stall" "none")])
3334 (define_insn "cgen_intrinsic_cpssda1u_b_C3"
3336 (unspec_volatile:SI [
3337 (match_operand:DI 0 "general_operand" "x")
3338 (match_operand:DI 1 "general_operand" "x")
3341 (unspec_volatile:SI [
3346 (unspec_volatile:SI [
3351 (unspec_volatile:SI [
3356 (unspec_volatile:SI [
3361 (unspec_volatile:SI [
3366 (unspec_volatile:SI [
3371 (unspec_volatile:SI [
3376 (unspec_volatile:SI [
3380 "CGEN_ENABLE_INSN_P (86)"
3381 "cpssda1u.b\\t%0,%1"
3382 [(set_attr "may_trap" "no")
3383 (set_attr "latency" "0")
3384 (set_attr "length" "4")
3385 (set_attr "slot" "cop")
3386 (set_attr "slots" "c3")
3387 (set_attr "stall" "none")])
3390 (define_insn "cgen_intrinsic_cpssda1u_b_P1"
3392 (unspec_volatile:SI [
3393 (match_operand:DI 0 "general_operand" "x")
3394 (match_operand:DI 1 "general_operand" "x")
3397 (unspec_volatile:SI [
3402 (unspec_volatile:SI [
3407 (unspec_volatile:SI [
3412 (unspec_volatile:SI [
3417 (unspec_volatile:SI [
3422 (unspec_volatile:SI [
3427 (unspec_volatile:SI [
3431 "CGEN_ENABLE_INSN_P (87)"
3432 "cpssda1u.b\\t%0,%1"
3433 [(set_attr "may_trap" "no")
3434 (set_attr "latency" "0")
3435 (set_attr "length" "4")
3436 (set_attr "slot" "cop")
3437 (set_attr "slots" "p1")
3438 (set_attr "stall" "none")])
3441 (define_insn "cgen_intrinsic_cpssqa1_b_C3"
3443 (unspec_volatile:SI [
3444 (match_operand:DI 0 "general_operand" "x")
3445 (match_operand:DI 1 "general_operand" "x")
3448 (unspec_volatile:SI [
3453 (unspec_volatile:SI [
3458 (unspec_volatile:SI [
3463 (unspec_volatile:SI [
3468 (unspec_volatile:SI [
3473 (unspec_volatile:SI [
3478 (unspec_volatile:SI [
3482 "CGEN_ENABLE_INSN_P (88)"
3484 [(set_attr "may_trap" "no")
3485 (set_attr "latency" "0")
3486 (set_attr "length" "4")
3487 (set_attr "slot" "cop")
3488 (set_attr "slots" "c3")
3489 (set_attr "stall" "none")])
3492 (define_insn "cgen_intrinsic_cpssqa1_b_P1"
3494 (unspec_volatile:SI [
3495 (match_operand:DI 0 "general_operand" "x")
3496 (match_operand:DI 1 "general_operand" "x")
3499 (unspec_volatile:SI [
3504 (unspec_volatile:SI [
3509 (unspec_volatile:SI [
3514 (unspec_volatile:SI [
3519 (unspec_volatile:SI [
3524 (unspec_volatile:SI [
3529 (unspec_volatile:SI [
3533 "CGEN_ENABLE_INSN_P (89)"
3535 [(set_attr "may_trap" "no")
3536 (set_attr "latency" "0")
3537 (set_attr "length" "4")
3538 (set_attr "slot" "cop")
3539 (set_attr "slots" "p1")
3540 (set_attr "stall" "none")])
3543 (define_insn "cgen_intrinsic_cpssqa1u_b_C3"
3545 (unspec_volatile:SI [
3546 (match_operand:DI 0 "general_operand" "x")
3547 (match_operand:DI 1 "general_operand" "x")
3550 (unspec_volatile:SI [
3555 (unspec_volatile:SI [
3560 (unspec_volatile:SI [
3565 (unspec_volatile:SI [
3570 (unspec_volatile:SI [
3575 (unspec_volatile:SI [
3580 (unspec_volatile:SI [
3584 "CGEN_ENABLE_INSN_P (90)"
3585 "cpssqa1u.b\\t%0,%1"
3586 [(set_attr "may_trap" "no")
3587 (set_attr "latency" "0")
3588 (set_attr "length" "4")
3589 (set_attr "slot" "cop")
3590 (set_attr "slots" "c3")
3591 (set_attr "stall" "none")])
3594 (define_insn "cgen_intrinsic_cpssqa1u_b_P1"
3596 (unspec_volatile:SI [
3597 (match_operand:DI 0 "general_operand" "x")
3598 (match_operand:DI 1 "general_operand" "x")
3601 (unspec_volatile:SI [
3606 (unspec_volatile:SI [
3611 (unspec_volatile:SI [
3616 (unspec_volatile:SI [
3621 (unspec_volatile:SI [
3626 (unspec_volatile:SI [
3631 (unspec_volatile:SI [
3635 "CGEN_ENABLE_INSN_P (91)"
3636 "cpssqa1u.b\\t%0,%1"
3637 [(set_attr "may_trap" "no")
3638 (set_attr "latency" "0")
3639 (set_attr "length" "4")
3640 (set_attr "slot" "cop")
3641 (set_attr "slots" "p1")
3642 (set_attr "stall" "none")])
3645 (define_insn "cgen_intrinsic_cpfmadila1_h_P1"
3647 (unspec_volatile:SI [
3648 (match_operand:DI 0 "general_operand" "x")
3649 (match_operand:DI 1 "general_operand" "x")
3650 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3651 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3654 (unspec_volatile:SI [
3661 (unspec_volatile:SI [
3668 (unspec_volatile:SI [
3675 (unspec_volatile:SI [
3681 "CGEN_ENABLE_INSN_P (92)"
3682 "cpfmadila1.h\\t%0,%1,%2,%3"
3683 [(set_attr "may_trap" "no")
3684 (set_attr "latency" "0")
3685 (set_attr "length" "4")
3686 (set_attr "slot" "cop")
3687 (set_attr "slots" "p1")
3688 (set_attr "stall" "none")])
3691 (define_insn "cgen_intrinsic_cpfmadiua1_h_P1"
3693 (unspec_volatile:SI [
3694 (match_operand:DI 0 "general_operand" "x")
3695 (match_operand:DI 1 "general_operand" "x")
3696 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3697 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3700 (unspec_volatile:SI [
3707 (unspec_volatile:SI [
3714 (unspec_volatile:SI [
3721 (unspec_volatile:SI [
3727 "CGEN_ENABLE_INSN_P (93)"
3728 "cpfmadiua1.h\\t%0,%1,%2,%3"
3729 [(set_attr "may_trap" "no")
3730 (set_attr "latency" "0")
3731 (set_attr "length" "4")
3732 (set_attr "slot" "cop")
3733 (set_attr "slots" "p1")
3734 (set_attr "stall" "none")])
3737 (define_insn "cgen_intrinsic_cpfmadia1_b_P1"
3739 (unspec_volatile:SI [
3740 (match_operand:DI 0 "general_operand" "x")
3741 (match_operand:DI 1 "general_operand" "x")
3742 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3743 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3746 (unspec_volatile:SI [
3753 (unspec_volatile:SI [
3760 (unspec_volatile:SI [
3767 (unspec_volatile:SI [
3774 (unspec_volatile:SI [
3781 (unspec_volatile:SI [
3788 (unspec_volatile:SI [
3795 (unspec_volatile:SI [
3801 "CGEN_ENABLE_INSN_P (94)"
3802 "cpfmadia1.b\\t%0,%1,%2,%3"
3803 [(set_attr "may_trap" "no")
3804 (set_attr "latency" "0")
3805 (set_attr "length" "4")
3806 (set_attr "slot" "cop")
3807 (set_attr "slots" "p1")
3808 (set_attr "stall" "none")])
3811 (define_insn "cgen_intrinsic_cpfmadia1u_b_P1"
3813 (unspec_volatile:SI [
3814 (match_operand:DI 0 "general_operand" "x")
3815 (match_operand:DI 1 "general_operand" "x")
3816 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3817 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3820 (unspec_volatile:SI [
3827 (unspec_volatile:SI [
3834 (unspec_volatile:SI [
3841 (unspec_volatile:SI [
3848 (unspec_volatile:SI [
3855 (unspec_volatile:SI [
3862 (unspec_volatile:SI [
3869 (unspec_volatile:SI [
3875 "CGEN_ENABLE_INSN_P (95)"
3876 "cpfmadia1u.b\\t%0,%1,%2,%3"
3877 [(set_attr "may_trap" "no")
3878 (set_attr "latency" "0")
3879 (set_attr "length" "4")
3880 (set_attr "slot" "cop")
3881 (set_attr "slots" "p1")
3882 (set_attr "stall" "none")])
3885 (define_insn "cgen_intrinsic_cpfmulila1_h_P1"
3887 (unspec_volatile:SI [
3888 (match_operand:DI 0 "general_operand" "x")
3889 (match_operand:DI 1 "general_operand" "x")
3890 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3891 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3894 (unspec_volatile:SI [
3901 (unspec_volatile:SI [
3908 (unspec_volatile:SI [
3914 "CGEN_ENABLE_INSN_P (96)"
3915 "cpfmulila1.h\\t%0,%1,%2,%3"
3916 [(set_attr "may_trap" "no")
3917 (set_attr "latency" "0")
3918 (set_attr "length" "4")
3919 (set_attr "slot" "cop")
3920 (set_attr "slots" "p1")
3921 (set_attr "stall" "none")])
3924 (define_insn "cgen_intrinsic_cpfmuliua1_h_P1"
3926 (unspec_volatile:SI [
3927 (match_operand:DI 0 "general_operand" "x")
3928 (match_operand:DI 1 "general_operand" "x")
3929 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3930 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3933 (unspec_volatile:SI [
3940 (unspec_volatile:SI [
3947 (unspec_volatile:SI [
3953 "CGEN_ENABLE_INSN_P (97)"
3954 "cpfmuliua1.h\\t%0,%1,%2,%3"
3955 [(set_attr "may_trap" "no")
3956 (set_attr "latency" "0")
3957 (set_attr "length" "4")
3958 (set_attr "slot" "cop")
3959 (set_attr "slots" "p1")
3960 (set_attr "stall" "none")])
3963 (define_insn "cgen_intrinsic_cpfmulia1_b_P1"
3965 (unspec_volatile:SI [
3966 (match_operand:DI 0 "general_operand" "x")
3967 (match_operand:DI 1 "general_operand" "x")
3968 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
3969 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
3972 (unspec_volatile:SI [
3979 (unspec_volatile:SI [
3986 (unspec_volatile:SI [
3993 (unspec_volatile:SI [
4000 (unspec_volatile:SI [
4007 (unspec_volatile:SI [
4014 (unspec_volatile:SI [
4020 "CGEN_ENABLE_INSN_P (98)"
4021 "cpfmulia1.b\\t%0,%1,%2,%3"
4022 [(set_attr "may_trap" "no")
4023 (set_attr "latency" "0")
4024 (set_attr "length" "4")
4025 (set_attr "slot" "cop")
4026 (set_attr "slots" "p1")
4027 (set_attr "stall" "none")])
4030 (define_insn "cgen_intrinsic_cpfmulia1u_b_P1"
4032 (unspec_volatile:SI [
4033 (match_operand:DI 0 "general_operand" "x")
4034 (match_operand:DI 1 "general_operand" "x")
4035 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
4036 (match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
4039 (unspec_volatile:SI [
4046 (unspec_volatile:SI [
4053 (unspec_volatile:SI [
4060 (unspec_volatile:SI [
4067 (unspec_volatile:SI [
4074 (unspec_volatile:SI [
4081 (unspec_volatile:SI [
4087 "CGEN_ENABLE_INSN_P (99)"
4088 "cpfmulia1u.b\\t%0,%1,%2,%3"
4089 [(set_attr "may_trap" "no")
4090 (set_attr "latency" "0")
4091 (set_attr "length" "4")
4092 (set_attr "slot" "cop")
4093 (set_attr "slots" "p1")
4094 (set_attr "stall" "none")])
4097 (define_insn "cgen_intrinsic_cpamadila1_h_P1"
4099 (unspec_volatile:SI [
4100 (match_operand:DI 0 "general_operand" "x")
4101 (match_operand:DI 1 "general_operand" "x")
4102 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4105 (unspec_volatile:SI [
4111 (unspec_volatile:SI [
4117 (unspec_volatile:SI [
4123 (unspec_volatile:SI [
4128 "CGEN_ENABLE_INSN_P (100)"
4129 "cpamadila1.h\\t%0,%1,%2"
4130 [(set_attr "may_trap" "no")
4131 (set_attr "latency" "0")
4132 (set_attr "length" "4")
4133 (set_attr "slot" "cop")
4134 (set_attr "slots" "p1")
4135 (set_attr "stall" "none")])
4138 (define_insn "cgen_intrinsic_cpamadiua1_h_P1"
4140 (unspec_volatile:SI [
4141 (match_operand:DI 0 "general_operand" "x")
4142 (match_operand:DI 1 "general_operand" "x")
4143 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4146 (unspec_volatile:SI [
4152 (unspec_volatile:SI [
4158 (unspec_volatile:SI [
4164 (unspec_volatile:SI [
4169 "CGEN_ENABLE_INSN_P (101)"
4170 "cpamadiua1.h\\t%0,%1,%2"
4171 [(set_attr "may_trap" "no")
4172 (set_attr "latency" "0")
4173 (set_attr "length" "4")
4174 (set_attr "slot" "cop")
4175 (set_attr "slots" "p1")
4176 (set_attr "stall" "none")])
4179 (define_insn "cgen_intrinsic_cpamadia1_b_P1"
4181 (unspec_volatile:SI [
4182 (match_operand:DI 0 "general_operand" "x")
4183 (match_operand:DI 1 "general_operand" "x")
4184 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4187 (unspec_volatile:SI [
4193 (unspec_volatile:SI [
4199 (unspec_volatile:SI [
4205 (unspec_volatile:SI [
4211 (unspec_volatile:SI [
4217 (unspec_volatile:SI [
4223 (unspec_volatile:SI [
4229 (unspec_volatile:SI [
4234 "CGEN_ENABLE_INSN_P (102)"
4235 "cpamadia1.b\\t%0,%1,%2"
4236 [(set_attr "may_trap" "no")
4237 (set_attr "latency" "0")
4238 (set_attr "length" "4")
4239 (set_attr "slot" "cop")
4240 (set_attr "slots" "p1")
4241 (set_attr "stall" "none")])
4244 (define_insn "cgen_intrinsic_cpamadia1u_b_P1"
4246 (unspec_volatile:SI [
4247 (match_operand:DI 0 "general_operand" "x")
4248 (match_operand:DI 1 "general_operand" "x")
4249 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4252 (unspec_volatile:SI [
4258 (unspec_volatile:SI [
4264 (unspec_volatile:SI [
4270 (unspec_volatile:SI [
4276 (unspec_volatile:SI [
4282 (unspec_volatile:SI [
4288 (unspec_volatile:SI [
4294 (unspec_volatile:SI [
4299 "CGEN_ENABLE_INSN_P (103)"
4300 "cpamadia1u.b\\t%0,%1,%2"
4301 [(set_attr "may_trap" "no")
4302 (set_attr "latency" "0")
4303 (set_attr "length" "4")
4304 (set_attr "slot" "cop")
4305 (set_attr "slots" "p1")
4306 (set_attr "stall" "none")])
4309 (define_insn "cgen_intrinsic_cpamulila1_h_P1"
4311 (unspec_volatile:SI [
4312 (match_operand:DI 0 "general_operand" "x")
4313 (match_operand:DI 1 "general_operand" "x")
4314 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4317 (unspec_volatile:SI [
4323 (unspec_volatile:SI [
4329 (unspec_volatile:SI [
4334 "CGEN_ENABLE_INSN_P (104)"
4335 "cpamulila1.h\\t%0,%1,%2"
4336 [(set_attr "may_trap" "no")
4337 (set_attr "latency" "0")
4338 (set_attr "length" "4")
4339 (set_attr "slot" "cop")
4340 (set_attr "slots" "p1")
4341 (set_attr "stall" "none")])
4344 (define_insn "cgen_intrinsic_cpamuliua1_h_P1"
4346 (unspec_volatile:SI [
4347 (match_operand:DI 0 "general_operand" "x")
4348 (match_operand:DI 1 "general_operand" "x")
4349 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4352 (unspec_volatile:SI [
4358 (unspec_volatile:SI [
4364 (unspec_volatile:SI [
4369 "CGEN_ENABLE_INSN_P (105)"
4370 "cpamuliua1.h\\t%0,%1,%2"
4371 [(set_attr "may_trap" "no")
4372 (set_attr "latency" "0")
4373 (set_attr "length" "4")
4374 (set_attr "slot" "cop")
4375 (set_attr "slots" "p1")
4376 (set_attr "stall" "none")])
4379 (define_insn "cgen_intrinsic_cpamulia1_b_P1"
4381 (unspec_volatile:SI [
4382 (match_operand:DI 0 "general_operand" "x")
4383 (match_operand:DI 1 "general_operand" "x")
4384 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4387 (unspec_volatile:SI [
4393 (unspec_volatile:SI [
4399 (unspec_volatile:SI [
4405 (unspec_volatile:SI [
4411 (unspec_volatile:SI [
4417 (unspec_volatile:SI [
4423 (unspec_volatile:SI [
4428 "CGEN_ENABLE_INSN_P (106)"
4429 "cpamulia1.b\\t%0,%1,%2"
4430 [(set_attr "may_trap" "no")
4431 (set_attr "latency" "0")
4432 (set_attr "length" "4")
4433 (set_attr "slot" "cop")
4434 (set_attr "slots" "p1")
4435 (set_attr "stall" "none")])
4438 (define_insn "cgen_intrinsic_cpamulia1u_b_P1"
4440 (unspec_volatile:SI [
4441 (match_operand:DI 0 "general_operand" "x")
4442 (match_operand:DI 1 "general_operand" "x")
4443 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4446 (unspec_volatile:SI [
4452 (unspec_volatile:SI [
4458 (unspec_volatile:SI [
4464 (unspec_volatile:SI [
4470 (unspec_volatile:SI [
4476 (unspec_volatile:SI [
4482 (unspec_volatile:SI [
4487 "CGEN_ENABLE_INSN_P (107)"
4488 "cpamulia1u.b\\t%0,%1,%2"
4489 [(set_attr "may_trap" "no")
4490 (set_attr "latency" "0")
4491 (set_attr "length" "4")
4492 (set_attr "slot" "cop")
4493 (set_attr "slots" "p1")
4494 (set_attr "stall" "none")])
4497 (define_insn "cgen_intrinsic_cpfmadila1s1_h_P1"
4499 (unspec_volatile:SI [
4500 (match_operand:DI 0 "general_operand" "x")
4501 (match_operand:DI 1 "general_operand" "x")
4502 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4505 (unspec_volatile:SI [
4511 (unspec_volatile:SI [
4517 (unspec_volatile:SI [
4523 (unspec_volatile:SI [
4528 "CGEN_ENABLE_INSN_P (108)"
4529 "cpfmadila1s1.h\\t%0,%1,%2"
4530 [(set_attr "may_trap" "no")
4531 (set_attr "latency" "0")
4532 (set_attr "length" "4")
4533 (set_attr "slot" "cop")
4534 (set_attr "slots" "p1")
4535 (set_attr "stall" "none")])
4538 (define_insn "cgen_intrinsic_cpfmadiua1s1_h_P1"
4540 (unspec_volatile:SI [
4541 (match_operand:DI 0 "general_operand" "x")
4542 (match_operand:DI 1 "general_operand" "x")
4543 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4546 (unspec_volatile:SI [
4552 (unspec_volatile:SI [
4558 (unspec_volatile:SI [
4564 (unspec_volatile:SI [
4569 "CGEN_ENABLE_INSN_P (109)"
4570 "cpfmadiua1s1.h\\t%0,%1,%2"
4571 [(set_attr "may_trap" "no")
4572 (set_attr "latency" "0")
4573 (set_attr "length" "4")
4574 (set_attr "slot" "cop")
4575 (set_attr "slots" "p1")
4576 (set_attr "stall" "none")])
4579 (define_insn "cgen_intrinsic_cpfmadia1s1_b_P1"
4581 (unspec_volatile:SI [
4582 (match_operand:DI 0 "general_operand" "x")
4583 (match_operand:DI 1 "general_operand" "x")
4584 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4587 (unspec_volatile:SI [
4593 (unspec_volatile:SI [
4599 (unspec_volatile:SI [
4605 (unspec_volatile:SI [
4611 (unspec_volatile:SI [
4617 (unspec_volatile:SI [
4623 (unspec_volatile:SI [
4629 (unspec_volatile:SI [
4634 "CGEN_ENABLE_INSN_P (110)"
4635 "cpfmadia1s1.b\\t%0,%1,%2"
4636 [(set_attr "may_trap" "no")
4637 (set_attr "latency" "0")
4638 (set_attr "length" "4")
4639 (set_attr "slot" "cop")
4640 (set_attr "slots" "p1")
4641 (set_attr "stall" "none")])
4644 (define_insn "cgen_intrinsic_cpfmadia1s1u_b_P1"
4646 (unspec_volatile:SI [
4647 (match_operand:DI 0 "general_operand" "x")
4648 (match_operand:DI 1 "general_operand" "x")
4649 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4652 (unspec_volatile:SI [
4658 (unspec_volatile:SI [
4664 (unspec_volatile:SI [
4670 (unspec_volatile:SI [
4676 (unspec_volatile:SI [
4682 (unspec_volatile:SI [
4688 (unspec_volatile:SI [
4694 (unspec_volatile:SI [
4699 "CGEN_ENABLE_INSN_P (111)"
4700 "cpfmadia1s1u.b\\t%0,%1,%2"
4701 [(set_attr "may_trap" "no")
4702 (set_attr "latency" "0")
4703 (set_attr "length" "4")
4704 (set_attr "slot" "cop")
4705 (set_attr "slots" "p1")
4706 (set_attr "stall" "none")])
4709 (define_insn "cgen_intrinsic_cpfmulila1s1_h_P1"
4711 (unspec_volatile:SI [
4712 (match_operand:DI 0 "general_operand" "x")
4713 (match_operand:DI 1 "general_operand" "x")
4714 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4717 (unspec_volatile:SI [
4723 (unspec_volatile:SI [
4729 (unspec_volatile:SI [
4734 "CGEN_ENABLE_INSN_P (112)"
4735 "cpfmulila1s1.h\\t%0,%1,%2"
4736 [(set_attr "may_trap" "no")
4737 (set_attr "latency" "0")
4738 (set_attr "length" "4")
4739 (set_attr "slot" "cop")
4740 (set_attr "slots" "p1")
4741 (set_attr "stall" "none")])
4744 (define_insn "cgen_intrinsic_cpfmuliua1s1_h_P1"
4746 (unspec_volatile:SI [
4747 (match_operand:DI 0 "general_operand" "x")
4748 (match_operand:DI 1 "general_operand" "x")
4749 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4752 (unspec_volatile:SI [
4758 (unspec_volatile:SI [
4764 (unspec_volatile:SI [
4769 "CGEN_ENABLE_INSN_P (113)"
4770 "cpfmuliua1s1.h\\t%0,%1,%2"
4771 [(set_attr "may_trap" "no")
4772 (set_attr "latency" "0")
4773 (set_attr "length" "4")
4774 (set_attr "slot" "cop")
4775 (set_attr "slots" "p1")
4776 (set_attr "stall" "none")])
4779 (define_insn "cgen_intrinsic_cpfmulia1s1_b_P1"
4781 (unspec_volatile:SI [
4782 (match_operand:DI 0 "general_operand" "x")
4783 (match_operand:DI 1 "general_operand" "x")
4784 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4787 (unspec_volatile:SI [
4793 (unspec_volatile:SI [
4799 (unspec_volatile:SI [
4805 (unspec_volatile:SI [
4811 (unspec_volatile:SI [
4817 (unspec_volatile:SI [
4823 (unspec_volatile:SI [
4828 "CGEN_ENABLE_INSN_P (114)"
4829 "cpfmulia1s1.b\\t%0,%1,%2"
4830 [(set_attr "may_trap" "no")
4831 (set_attr "latency" "0")
4832 (set_attr "length" "4")
4833 (set_attr "slot" "cop")
4834 (set_attr "slots" "p1")
4835 (set_attr "stall" "none")])
4838 (define_insn "cgen_intrinsic_cpfmulia1s1u_b_P1"
4840 (unspec_volatile:SI [
4841 (match_operand:DI 0 "general_operand" "x")
4842 (match_operand:DI 1 "general_operand" "x")
4843 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4846 (unspec_volatile:SI [
4852 (unspec_volatile:SI [
4858 (unspec_volatile:SI [
4864 (unspec_volatile:SI [
4870 (unspec_volatile:SI [
4876 (unspec_volatile:SI [
4882 (unspec_volatile:SI [
4887 "CGEN_ENABLE_INSN_P (115)"
4888 "cpfmulia1s1u.b\\t%0,%1,%2"
4889 [(set_attr "may_trap" "no")
4890 (set_attr "latency" "0")
4891 (set_attr "length" "4")
4892 (set_attr "slot" "cop")
4893 (set_attr "slots" "p1")
4894 (set_attr "stall" "none")])
4897 (define_insn "cgen_intrinsic_cpfmadila1s0_h_P1"
4899 (unspec_volatile:SI [
4900 (match_operand:DI 0 "general_operand" "x")
4901 (match_operand:DI 1 "general_operand" "x")
4902 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4905 (unspec_volatile:SI [
4911 (unspec_volatile:SI [
4917 (unspec_volatile:SI [
4923 (unspec_volatile:SI [
4928 "CGEN_ENABLE_INSN_P (116)"
4929 "cpfmadila1s0.h\\t%0,%1,%2"
4930 [(set_attr "may_trap" "no")
4931 (set_attr "latency" "0")
4932 (set_attr "length" "4")
4933 (set_attr "slot" "cop")
4934 (set_attr "slots" "p1")
4935 (set_attr "stall" "none")])
4938 (define_insn "cgen_intrinsic_cpfmadiua1s0_h_P1"
4940 (unspec_volatile:SI [
4941 (match_operand:DI 0 "general_operand" "x")
4942 (match_operand:DI 1 "general_operand" "x")
4943 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4946 (unspec_volatile:SI [
4952 (unspec_volatile:SI [
4958 (unspec_volatile:SI [
4964 (unspec_volatile:SI [
4969 "CGEN_ENABLE_INSN_P (117)"
4970 "cpfmadiua1s0.h\\t%0,%1,%2"
4971 [(set_attr "may_trap" "no")
4972 (set_attr "latency" "0")
4973 (set_attr "length" "4")
4974 (set_attr "slot" "cop")
4975 (set_attr "slots" "p1")
4976 (set_attr "stall" "none")])
4979 (define_insn "cgen_intrinsic_cpfmadia1s0_b_P1"
4981 (unspec_volatile:SI [
4982 (match_operand:DI 0 "general_operand" "x")
4983 (match_operand:DI 1 "general_operand" "x")
4984 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
4987 (unspec_volatile:SI [
4993 (unspec_volatile:SI [
4999 (unspec_volatile:SI [
5005 (unspec_volatile:SI [
5011 (unspec_volatile:SI [
5017 (unspec_volatile:SI [
5023 (unspec_volatile:SI [
5029 (unspec_volatile:SI [
5034 "CGEN_ENABLE_INSN_P (118)"
5035 "cpfmadia1s0.b\\t%0,%1,%2"
5036 [(set_attr "may_trap" "no")
5037 (set_attr "latency" "0")
5038 (set_attr "length" "4")
5039 (set_attr "slot" "cop")
5040 (set_attr "slots" "p1")
5041 (set_attr "stall" "none")])
5044 (define_insn "cgen_intrinsic_cpfmadia1s0u_b_P1"
5046 (unspec_volatile:SI [
5047 (match_operand:DI 0 "general_operand" "x")
5048 (match_operand:DI 1 "general_operand" "x")
5049 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5052 (unspec_volatile:SI [
5058 (unspec_volatile:SI [
5064 (unspec_volatile:SI [
5070 (unspec_volatile:SI [
5076 (unspec_volatile:SI [
5082 (unspec_volatile:SI [
5088 (unspec_volatile:SI [
5094 (unspec_volatile:SI [
5099 "CGEN_ENABLE_INSN_P (119)"
5100 "cpfmadia1s0u.b\\t%0,%1,%2"
5101 [(set_attr "may_trap" "no")
5102 (set_attr "latency" "0")
5103 (set_attr "length" "4")
5104 (set_attr "slot" "cop")
5105 (set_attr "slots" "p1")
5106 (set_attr "stall" "none")])
5109 (define_insn "cgen_intrinsic_cpfmulila1s0_h_P1"
5111 (unspec_volatile:SI [
5112 (match_operand:DI 0 "general_operand" "x")
5113 (match_operand:DI 1 "general_operand" "x")
5114 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5117 (unspec_volatile:SI [
5123 (unspec_volatile:SI [
5129 (unspec_volatile:SI [
5134 "CGEN_ENABLE_INSN_P (120)"
5135 "cpfmulila1s0.h\\t%0,%1,%2"
5136 [(set_attr "may_trap" "no")
5137 (set_attr "latency" "0")
5138 (set_attr "length" "4")
5139 (set_attr "slot" "cop")
5140 (set_attr "slots" "p1")
5141 (set_attr "stall" "none")])
5144 (define_insn "cgen_intrinsic_cpfmuliua1s0_h_P1"
5146 (unspec_volatile:SI [
5147 (match_operand:DI 0 "general_operand" "x")
5148 (match_operand:DI 1 "general_operand" "x")
5149 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5152 (unspec_volatile:SI [
5158 (unspec_volatile:SI [
5164 (unspec_volatile:SI [
5169 "CGEN_ENABLE_INSN_P (121)"
5170 "cpfmuliua1s0.h\\t%0,%1,%2"
5171 [(set_attr "may_trap" "no")
5172 (set_attr "latency" "0")
5173 (set_attr "length" "4")
5174 (set_attr "slot" "cop")
5175 (set_attr "slots" "p1")
5176 (set_attr "stall" "none")])
5179 (define_insn "cgen_intrinsic_cpfmulia1s0_b_P1"
5181 (unspec_volatile:SI [
5182 (match_operand:DI 0 "general_operand" "x")
5183 (match_operand:DI 1 "general_operand" "x")
5184 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5187 (unspec_volatile:SI [
5193 (unspec_volatile:SI [
5199 (unspec_volatile:SI [
5205 (unspec_volatile:SI [
5211 (unspec_volatile:SI [
5217 (unspec_volatile:SI [
5223 (unspec_volatile:SI [
5228 "CGEN_ENABLE_INSN_P (122)"
5229 "cpfmulia1s0.b\\t%0,%1,%2"
5230 [(set_attr "may_trap" "no")
5231 (set_attr "latency" "0")
5232 (set_attr "length" "4")
5233 (set_attr "slot" "cop")
5234 (set_attr "slots" "p1")
5235 (set_attr "stall" "none")])
5238 (define_insn "cgen_intrinsic_cpfmulia1s0u_b_P1"
5240 (unspec_volatile:SI [
5241 (match_operand:DI 0 "general_operand" "x")
5242 (match_operand:DI 1 "general_operand" "x")
5243 (match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
5246 (unspec_volatile:SI [
5252 (unspec_volatile:SI [
5258 (unspec_volatile:SI [
5264 (unspec_volatile:SI [
5270 (unspec_volatile:SI [
5276 (unspec_volatile:SI [
5282 (unspec_volatile:SI [
5287 "CGEN_ENABLE_INSN_P (123)"
5288 "cpfmulia1s0u.b\\t%0,%1,%2"
5289 [(set_attr "may_trap" "no")
5290 (set_attr "latency" "0")
5291 (set_attr "length" "4")
5292 (set_attr "slot" "cop")
5293 (set_attr "slots" "p1")
5294 (set_attr "stall" "none")])
5297 (define_insn "cgen_intrinsic_cpsllia1_P1"
5299 (unspec_volatile:SI [
5300 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5303 (unspec_volatile:SI [
5307 (unspec_volatile:SI [
5311 (unspec_volatile:SI [
5315 (unspec_volatile:SI [
5319 (unspec_volatile:SI [
5323 (unspec_volatile:SI [
5327 (unspec_volatile:SI [
5330 "CGEN_ENABLE_INSN_P (124)"
5332 [(set_attr "may_trap" "no")
5333 (set_attr "latency" "0")
5334 (set_attr "length" "4")
5335 (set_attr "slot" "cop")
5336 (set_attr "slots" "c3")
5337 (set_attr "stall" "none")])
5340 (define_insn "cgen_intrinsic_cpsllia1_1_p1"
5342 (unspec_volatile:SI [
5343 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5346 (unspec_volatile:SI [
5350 (unspec_volatile:SI [
5354 (unspec_volatile:SI [
5358 (unspec_volatile:SI [
5362 (unspec_volatile:SI [
5366 (unspec_volatile:SI [
5370 (unspec_volatile:SI [
5373 "CGEN_ENABLE_INSN_P (125)"
5375 [(set_attr "may_trap" "no")
5376 (set_attr "latency" "0")
5377 (set_attr "length" "4")
5378 (set_attr "slot" "cop")
5379 (set_attr "slots" "p1")
5380 (set_attr "stall" "none")])
5383 (define_insn "cgen_intrinsic_cpsraia1_P1"
5385 (unspec_volatile:SI [
5386 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5389 (unspec_volatile:SI [
5393 (unspec_volatile:SI [
5397 (unspec_volatile:SI [
5401 (unspec_volatile:SI [
5405 (unspec_volatile:SI [
5409 (unspec_volatile:SI [
5413 (unspec_volatile:SI [
5416 "CGEN_ENABLE_INSN_P (126)"
5418 [(set_attr "may_trap" "no")
5419 (set_attr "latency" "0")
5420 (set_attr "length" "4")
5421 (set_attr "slot" "cop")
5422 (set_attr "slots" "c3")
5423 (set_attr "stall" "none")])
5426 (define_insn "cgen_intrinsic_cpsraia1_1_p1"
5428 (unspec_volatile:SI [
5429 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5432 (unspec_volatile:SI [
5436 (unspec_volatile:SI [
5440 (unspec_volatile:SI [
5444 (unspec_volatile:SI [
5448 (unspec_volatile:SI [
5452 (unspec_volatile:SI [
5456 (unspec_volatile:SI [
5459 "CGEN_ENABLE_INSN_P (127)"
5461 [(set_attr "may_trap" "no")
5462 (set_attr "latency" "0")
5463 (set_attr "length" "4")
5464 (set_attr "slot" "cop")
5465 (set_attr "slots" "p1")
5466 (set_attr "stall" "none")])
5469 (define_insn "cgen_intrinsic_cpsrlia1_P1"
5471 (unspec_volatile:SI [
5472 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5475 (unspec_volatile:SI [
5479 (unspec_volatile:SI [
5483 (unspec_volatile:SI [
5487 (unspec_volatile:SI [
5491 (unspec_volatile:SI [
5495 (unspec_volatile:SI [
5499 (unspec_volatile:SI [
5502 "CGEN_ENABLE_INSN_P (128)"
5504 [(set_attr "may_trap" "no")
5505 (set_attr "latency" "0")
5506 (set_attr "length" "4")
5507 (set_attr "slot" "cop")
5508 (set_attr "slots" "c3")
5509 (set_attr "stall" "none")])
5512 (define_insn "cgen_intrinsic_cpsrlia1_1_p1"
5514 (unspec_volatile:SI [
5515 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
5518 (unspec_volatile:SI [
5522 (unspec_volatile:SI [
5526 (unspec_volatile:SI [
5530 (unspec_volatile:SI [
5534 (unspec_volatile:SI [
5538 (unspec_volatile:SI [
5542 (unspec_volatile:SI [
5545 "CGEN_ENABLE_INSN_P (129)"
5547 [(set_attr "may_trap" "no")
5548 (set_attr "latency" "0")
5549 (set_attr "length" "4")
5550 (set_attr "slot" "cop")
5551 (set_attr "slots" "p1")
5552 (set_attr "stall" "none")])
5555 (define_insn "cgen_intrinsic_cpslla1_C3"
5557 (unspec_volatile:SI [
5558 (match_operand:DI 0 "general_operand" "x")
5561 (unspec_volatile:SI [
5565 (unspec_volatile:SI [
5569 (unspec_volatile:SI [
5573 (unspec_volatile:SI [
5577 (unspec_volatile:SI [
5581 (unspec_volatile:SI [
5585 (unspec_volatile:SI [
5588 "CGEN_ENABLE_INSN_P (130)"
5590 [(set_attr "may_trap" "no")
5591 (set_attr "latency" "0")
5592 (set_attr "length" "4")
5593 (set_attr "slot" "cop")
5594 (set_attr "slots" "c3")
5595 (set_attr "stall" "none")])
5598 (define_insn "cgen_intrinsic_cpslla1_P1"
5600 (unspec_volatile:SI [
5601 (match_operand:DI 0 "general_operand" "x")
5604 (unspec_volatile:SI [
5608 (unspec_volatile:SI [
5612 (unspec_volatile:SI [
5616 (unspec_volatile:SI [
5620 (unspec_volatile:SI [
5624 (unspec_volatile:SI [
5628 (unspec_volatile:SI [
5631 "CGEN_ENABLE_INSN_P (131)"
5633 [(set_attr "may_trap" "no")
5634 (set_attr "latency" "0")
5635 (set_attr "length" "4")
5636 (set_attr "slot" "cop")
5637 (set_attr "slots" "p1")
5638 (set_attr "stall" "none")])
5641 (define_insn "cgen_intrinsic_cpsraa1_C3"
5643 (unspec_volatile:SI [
5644 (match_operand:DI 0 "general_operand" "x")
5647 (unspec_volatile:SI [
5651 (unspec_volatile:SI [
5655 (unspec_volatile:SI [
5659 (unspec_volatile:SI [
5663 (unspec_volatile:SI [
5667 (unspec_volatile:SI [
5671 (unspec_volatile:SI [
5674 "CGEN_ENABLE_INSN_P (132)"
5676 [(set_attr "may_trap" "no")
5677 (set_attr "latency" "0")
5678 (set_attr "length" "4")
5679 (set_attr "slot" "cop")
5680 (set_attr "slots" "c3")
5681 (set_attr "stall" "none")])
5684 (define_insn "cgen_intrinsic_cpsraa1_P1"
5686 (unspec_volatile:SI [
5687 (match_operand:DI 0 "general_operand" "x")
5690 (unspec_volatile:SI [
5694 (unspec_volatile:SI [
5698 (unspec_volatile:SI [
5702 (unspec_volatile:SI [
5706 (unspec_volatile:SI [
5710 (unspec_volatile:SI [
5714 (unspec_volatile:SI [
5717 "CGEN_ENABLE_INSN_P (133)"
5719 [(set_attr "may_trap" "no")
5720 (set_attr "latency" "0")
5721 (set_attr "length" "4")
5722 (set_attr "slot" "cop")
5723 (set_attr "slots" "p1")
5724 (set_attr "stall" "none")])
5727 (define_insn "cgen_intrinsic_cpsrla1_C3"
5729 (unspec_volatile:SI [
5730 (match_operand:DI 0 "general_operand" "x")
5733 (unspec_volatile:SI [
5737 (unspec_volatile:SI [
5741 (unspec_volatile:SI [
5745 (unspec_volatile:SI [
5749 (unspec_volatile:SI [
5753 (unspec_volatile:SI [
5757 (unspec_volatile:SI [
5760 "CGEN_ENABLE_INSN_P (134)"
5762 [(set_attr "may_trap" "no")
5763 (set_attr "latency" "0")
5764 (set_attr "length" "4")
5765 (set_attr "slot" "cop")
5766 (set_attr "slots" "c3")
5767 (set_attr "stall" "none")])
5770 (define_insn "cgen_intrinsic_cpsrla1_P1"
5772 (unspec_volatile:SI [
5773 (match_operand:DI 0 "general_operand" "x")
5776 (unspec_volatile:SI [
5780 (unspec_volatile:SI [
5784 (unspec_volatile:SI [
5788 (unspec_volatile:SI [
5792 (unspec_volatile:SI [
5796 (unspec_volatile:SI [
5800 (unspec_volatile:SI [
5803 "CGEN_ENABLE_INSN_P (135)"
5805 [(set_attr "may_trap" "no")
5806 (set_attr "latency" "0")
5807 (set_attr "length" "4")
5808 (set_attr "slot" "cop")
5809 (set_attr "slots" "p1")
5810 (set_attr "stall" "none")])
5813 (define_insn "cgen_intrinsic_cpacswp_P1"
5815 (unspec_volatile:SI [
5819 (unspec_volatile:SI [
5823 (unspec_volatile:SI [
5827 (unspec_volatile:SI [
5831 (unspec_volatile:SI [
5835 (unspec_volatile:SI [
5839 (unspec_volatile:SI [
5843 (unspec_volatile:SI [
5847 (unspec_volatile:SI [
5851 (unspec_volatile:SI [
5855 (unspec_volatile:SI [
5859 (unspec_volatile:SI [
5863 (unspec_volatile:SI [
5867 (unspec_volatile:SI [
5871 (unspec_volatile:SI [
5875 (unspec_volatile:SI [
5878 "CGEN_ENABLE_INSN_P (136)"
5880 [(set_attr "may_trap" "no")
5881 (set_attr "latency" "0")
5882 (set_attr "length" "4")
5883 (set_attr "slot" "cop")
5884 (set_attr "slots" "p1")
5885 (set_attr "stall" "none")])
5888 (define_insn "cgen_intrinsic_cpaccpa1_P1"
5890 (unspec_volatile:SI [
5894 (unspec_volatile:SI [
5898 (unspec_volatile:SI [
5902 (unspec_volatile:SI [
5906 (unspec_volatile:SI [
5910 (unspec_volatile:SI [
5914 (unspec_volatile:SI [
5918 (unspec_volatile:SI [
5921 "CGEN_ENABLE_INSN_P (137)"
5923 [(set_attr "may_trap" "no")
5924 (set_attr "latency" "0")
5925 (set_attr "length" "4")
5926 (set_attr "slot" "cop")
5927 (set_attr "slots" "p1")
5928 (set_attr "stall" "none")])
5931 (define_insn "cgen_intrinsic_cpacsuma1_P1"
5933 (unspec_volatile:SI [
5937 (unspec_volatile:SI [
5941 (unspec_volatile:SI [
5945 (unspec_volatile:SI [
5949 (unspec_volatile:SI [
5953 (unspec_volatile:SI [
5957 (unspec_volatile:SI [
5961 (unspec_volatile:SI [
5965 (unspec_volatile:SI [
5968 "CGEN_ENABLE_INSN_P (138)"
5970 [(set_attr "may_trap" "no")
5971 (set_attr "latency" "0")
5972 (set_attr "length" "4")
5973 (set_attr "slot" "cop")
5974 (set_attr "slots" "p1")
5975 (set_attr "stall" "none")])
5978 (define_insn "cgen_intrinsic_cpmovhla1_w_C3"
5979 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
5980 (unspec_volatile:DI [
5983 "CGEN_ENABLE_INSN_P (139)"
5985 [(set_attr "may_trap" "no")
5986 (set_attr "latency" "0")
5987 (set_attr "length" "4")
5988 (set_attr "slot" "cop")
5989 (set_attr "slots" "c3")
5990 (set_attr "stall" "none")])
5993 (define_insn "cgen_intrinsic_cpmovhla1_w_P1"
5994 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
5995 (unspec_volatile:DI [
5998 "CGEN_ENABLE_INSN_P (140)"
6000 [(set_attr "may_trap" "no")
6001 (set_attr "latency" "0")
6002 (set_attr "length" "4")
6003 (set_attr "slot" "cop")
6004 (set_attr "slots" "p1")
6005 (set_attr "stall" "none")])
6008 (define_insn "cgen_intrinsic_cpmovhua1_w_C3"
6009 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6010 (unspec_volatile:DI [
6013 "CGEN_ENABLE_INSN_P (141)"
6015 [(set_attr "may_trap" "no")
6016 (set_attr "latency" "0")
6017 (set_attr "length" "4")
6018 (set_attr "slot" "cop")
6019 (set_attr "slots" "c3")
6020 (set_attr "stall" "none")])
6023 (define_insn "cgen_intrinsic_cpmovhua1_w_P1"
6024 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6025 (unspec_volatile:DI [
6028 "CGEN_ENABLE_INSN_P (142)"
6030 [(set_attr "may_trap" "no")
6031 (set_attr "latency" "0")
6032 (set_attr "length" "4")
6033 (set_attr "slot" "cop")
6034 (set_attr "slots" "p1")
6035 (set_attr "stall" "none")])
6038 (define_insn "cgen_intrinsic_cppackla1_w_C3"
6039 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6040 (unspec_volatile:DI [
6043 "CGEN_ENABLE_INSN_P (143)"
6045 [(set_attr "may_trap" "no")
6046 (set_attr "latency" "0")
6047 (set_attr "length" "4")
6048 (set_attr "slot" "cop")
6049 (set_attr "slots" "c3")
6050 (set_attr "stall" "none")])
6053 (define_insn "cgen_intrinsic_cppackla1_w_P1"
6054 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6055 (unspec_volatile:DI [
6058 "CGEN_ENABLE_INSN_P (144)"
6060 [(set_attr "may_trap" "no")
6061 (set_attr "latency" "0")
6062 (set_attr "length" "4")
6063 (set_attr "slot" "cop")
6064 (set_attr "slots" "p1")
6065 (set_attr "stall" "none")])
6068 (define_insn "cgen_intrinsic_cppackua1_w_C3"
6069 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6070 (unspec_volatile:DI [
6073 "CGEN_ENABLE_INSN_P (145)"
6075 [(set_attr "may_trap" "no")
6076 (set_attr "latency" "0")
6077 (set_attr "length" "4")
6078 (set_attr "slot" "cop")
6079 (set_attr "slots" "c3")
6080 (set_attr "stall" "none")])
6083 (define_insn "cgen_intrinsic_cppackua1_w_P1"
6084 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6085 (unspec_volatile:DI [
6088 "CGEN_ENABLE_INSN_P (146)"
6090 [(set_attr "may_trap" "no")
6091 (set_attr "latency" "0")
6092 (set_attr "length" "4")
6093 (set_attr "slot" "cop")
6094 (set_attr "slots" "p1")
6095 (set_attr "stall" "none")])
6098 (define_insn "cgen_intrinsic_cppackla1_h_C3"
6099 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6100 (unspec_volatile:DI [
6103 "CGEN_ENABLE_INSN_P (147)"
6105 [(set_attr "may_trap" "no")
6106 (set_attr "latency" "0")
6107 (set_attr "length" "4")
6108 (set_attr "slot" "cop")
6109 (set_attr "slots" "c3")
6110 (set_attr "stall" "none")])
6113 (define_insn "cgen_intrinsic_cppackla1_h_P1"
6114 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6115 (unspec_volatile:DI [
6118 "CGEN_ENABLE_INSN_P (148)"
6120 [(set_attr "may_trap" "no")
6121 (set_attr "latency" "0")
6122 (set_attr "length" "4")
6123 (set_attr "slot" "cop")
6124 (set_attr "slots" "p1")
6125 (set_attr "stall" "none")])
6128 (define_insn "cgen_intrinsic_cppackua1_h_C3"
6129 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6130 (unspec_volatile:DI [
6133 "CGEN_ENABLE_INSN_P (149)"
6135 [(set_attr "may_trap" "no")
6136 (set_attr "latency" "0")
6137 (set_attr "length" "4")
6138 (set_attr "slot" "cop")
6139 (set_attr "slots" "c3")
6140 (set_attr "stall" "none")])
6143 (define_insn "cgen_intrinsic_cppackua1_h_P1"
6144 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6145 (unspec_volatile:DI [
6148 "CGEN_ENABLE_INSN_P (150)"
6150 [(set_attr "may_trap" "no")
6151 (set_attr "latency" "0")
6152 (set_attr "length" "4")
6153 (set_attr "slot" "cop")
6154 (set_attr "slots" "p1")
6155 (set_attr "stall" "none")])
6158 (define_insn "cgen_intrinsic_cppacka1_b_C3"
6159 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6160 (unspec_volatile:DI [
6163 "CGEN_ENABLE_INSN_P (151)"
6165 [(set_attr "may_trap" "no")
6166 (set_attr "latency" "0")
6167 (set_attr "length" "4")
6168 (set_attr "slot" "cop")
6169 (set_attr "slots" "c3")
6170 (set_attr "stall" "none")])
6173 (define_insn "cgen_intrinsic_cppacka1_b_P1"
6174 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6175 (unspec_volatile:DI [
6178 "CGEN_ENABLE_INSN_P (152)"
6180 [(set_attr "may_trap" "no")
6181 (set_attr "latency" "0")
6182 (set_attr "length" "4")
6183 (set_attr "slot" "cop")
6184 (set_attr "slots" "p1")
6185 (set_attr "stall" "none")])
6188 (define_insn "cgen_intrinsic_cppacka1u_b_C3"
6189 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6190 (unspec_volatile:DI [
6193 "CGEN_ENABLE_INSN_P (153)"
6195 [(set_attr "may_trap" "no")
6196 (set_attr "latency" "0")
6197 (set_attr "length" "4")
6198 (set_attr "slot" "cop")
6199 (set_attr "slots" "c3")
6200 (set_attr "stall" "none")])
6203 (define_insn "cgen_intrinsic_cppacka1u_b_P1"
6204 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6205 (unspec_volatile:DI [
6208 "CGEN_ENABLE_INSN_P (154)"
6210 [(set_attr "may_trap" "no")
6211 (set_attr "latency" "0")
6212 (set_attr "length" "4")
6213 (set_attr "slot" "cop")
6214 (set_attr "slots" "p1")
6215 (set_attr "stall" "none")])
6218 (define_insn "cgen_intrinsic_cpmovlla1_w_C3"
6219 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6220 (unspec_volatile:DI [
6223 "CGEN_ENABLE_INSN_P (155)"
6225 [(set_attr "may_trap" "no")
6226 (set_attr "latency" "0")
6227 (set_attr "length" "4")
6228 (set_attr "slot" "cop")
6229 (set_attr "slots" "c3")
6230 (set_attr "stall" "none")])
6233 (define_insn "cgen_intrinsic_cpmovlla1_w_P1"
6234 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6235 (unspec_volatile:DI [
6238 "CGEN_ENABLE_INSN_P (156)"
6240 [(set_attr "may_trap" "no")
6241 (set_attr "latency" "0")
6242 (set_attr "length" "4")
6243 (set_attr "slot" "cop")
6244 (set_attr "slots" "p1")
6245 (set_attr "stall" "none")])
6248 (define_insn "cgen_intrinsic_cpmovlua1_w_C3"
6249 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6250 (unspec_volatile:DI [
6253 "CGEN_ENABLE_INSN_P (157)"
6255 [(set_attr "may_trap" "no")
6256 (set_attr "latency" "0")
6257 (set_attr "length" "4")
6258 (set_attr "slot" "cop")
6259 (set_attr "slots" "c3")
6260 (set_attr "stall" "none")])
6263 (define_insn "cgen_intrinsic_cpmovlua1_w_P1"
6264 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6265 (unspec_volatile:DI [
6268 "CGEN_ENABLE_INSN_P (158)"
6270 [(set_attr "may_trap" "no")
6271 (set_attr "latency" "0")
6272 (set_attr "length" "4")
6273 (set_attr "slot" "cop")
6274 (set_attr "slots" "p1")
6275 (set_attr "stall" "none")])
6278 (define_insn "cgen_intrinsic_cpmovula1_w_C3"
6279 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6280 (unspec_volatile:DI [
6283 "CGEN_ENABLE_INSN_P (159)"
6285 [(set_attr "may_trap" "no")
6286 (set_attr "latency" "0")
6287 (set_attr "length" "4")
6288 (set_attr "slot" "cop")
6289 (set_attr "slots" "c3")
6290 (set_attr "stall" "none")])
6293 (define_insn "cgen_intrinsic_cpmovula1_w_P1"
6294 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6295 (unspec_volatile:DI [
6298 "CGEN_ENABLE_INSN_P (160)"
6300 [(set_attr "may_trap" "no")
6301 (set_attr "latency" "0")
6302 (set_attr "length" "4")
6303 (set_attr "slot" "cop")
6304 (set_attr "slots" "p1")
6305 (set_attr "stall" "none")])
6308 (define_insn "cgen_intrinsic_cpmovuua1_w_C3"
6309 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6310 (unspec_volatile:DI [
6313 "CGEN_ENABLE_INSN_P (161)"
6315 [(set_attr "may_trap" "no")
6316 (set_attr "latency" "0")
6317 (set_attr "length" "4")
6318 (set_attr "slot" "cop")
6319 (set_attr "slots" "c3")
6320 (set_attr "stall" "none")])
6323 (define_insn "cgen_intrinsic_cpmovuua1_w_P1"
6324 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6325 (unspec_volatile:DI [
6328 "CGEN_ENABLE_INSN_P (162)"
6330 [(set_attr "may_trap" "no")
6331 (set_attr "latency" "0")
6332 (set_attr "length" "4")
6333 (set_attr "slot" "cop")
6334 (set_attr "slots" "p1")
6335 (set_attr "stall" "none")])
6338 (define_insn "cgen_intrinsic_cpmovla1_h_C3"
6339 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6340 (unspec_volatile:DI [
6343 "CGEN_ENABLE_INSN_P (163)"
6345 [(set_attr "may_trap" "no")
6346 (set_attr "latency" "0")
6347 (set_attr "length" "4")
6348 (set_attr "slot" "cop")
6349 (set_attr "slots" "c3")
6350 (set_attr "stall" "none")])
6353 (define_insn "cgen_intrinsic_cpmovla1_h_P1"
6354 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6355 (unspec_volatile:DI [
6358 "CGEN_ENABLE_INSN_P (164)"
6360 [(set_attr "may_trap" "no")
6361 (set_attr "latency" "0")
6362 (set_attr "length" "4")
6363 (set_attr "slot" "cop")
6364 (set_attr "slots" "p1")
6365 (set_attr "stall" "none")])
6368 (define_insn "cgen_intrinsic_cpmovua1_h_C3"
6369 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6370 (unspec_volatile:DI [
6373 "CGEN_ENABLE_INSN_P (165)"
6375 [(set_attr "may_trap" "no")
6376 (set_attr "latency" "0")
6377 (set_attr "length" "4")
6378 (set_attr "slot" "cop")
6379 (set_attr "slots" "c3")
6380 (set_attr "stall" "none")])
6383 (define_insn "cgen_intrinsic_cpmovua1_h_P1"
6384 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6385 (unspec_volatile:DI [
6388 "CGEN_ENABLE_INSN_P (166)"
6390 [(set_attr "may_trap" "no")
6391 (set_attr "latency" "0")
6392 (set_attr "length" "4")
6393 (set_attr "slot" "cop")
6394 (set_attr "slots" "p1")
6395 (set_attr "stall" "none")])
6398 (define_insn "cgen_intrinsic_cpmova1_b_C3"
6399 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6400 (unspec_volatile:DI [
6403 "CGEN_ENABLE_INSN_P (167)"
6405 [(set_attr "may_trap" "no")
6406 (set_attr "latency" "0")
6407 (set_attr "length" "4")
6408 (set_attr "slot" "cop")
6409 (set_attr "slots" "c3")
6410 (set_attr "stall" "none")])
6413 (define_insn "cgen_intrinsic_cpmova1_b_P1"
6414 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
6415 (unspec_volatile:DI [
6418 "CGEN_ENABLE_INSN_P (168)"
6420 [(set_attr "may_trap" "no")
6421 (set_attr "latency" "0")
6422 (set_attr "length" "4")
6423 (set_attr "slot" "cop")
6424 (set_attr "slots" "p1")
6425 (set_attr "stall" "none")])
6428 (define_insn "cgen_intrinsic_cpsetla1_w_C3"
6430 (unspec_volatile:SI [
6431 (match_operand:DI 0 "general_operand" "x")
6432 (match_operand:DI 1 "general_operand" "x")
6435 (unspec_volatile:SI [
6440 (unspec_volatile:SI [
6445 (unspec_volatile:SI [
6449 "CGEN_ENABLE_INSN_P (169)"
6450 "cpsetla1.w\\t%0,%1"
6451 [(set_attr "may_trap" "no")
6452 (set_attr "latency" "0")
6453 (set_attr "length" "4")
6454 (set_attr "slot" "cop")
6455 (set_attr "slots" "c3")
6456 (set_attr "stall" "none")])
6459 (define_insn "cgen_intrinsic_cpsetla1_w_P1"
6461 (unspec_volatile:SI [
6462 (match_operand:DI 0 "general_operand" "x")
6463 (match_operand:DI 1 "general_operand" "x")
6466 (unspec_volatile:SI [
6471 (unspec_volatile:SI [
6476 (unspec_volatile:SI [
6480 "CGEN_ENABLE_INSN_P (170)"
6481 "cpsetla1.w\\t%0,%1"
6482 [(set_attr "may_trap" "no")
6483 (set_attr "latency" "0")
6484 (set_attr "length" "4")
6485 (set_attr "slot" "cop")
6486 (set_attr "slots" "p1")
6487 (set_attr "stall" "none")])
6490 (define_insn "cgen_intrinsic_cpsetua1_w_C3"
6492 (unspec_volatile:SI [
6493 (match_operand:DI 0 "general_operand" "x")
6494 (match_operand:DI 1 "general_operand" "x")
6497 (unspec_volatile:SI [
6502 (unspec_volatile:SI [
6507 (unspec_volatile:SI [
6511 "CGEN_ENABLE_INSN_P (171)"
6512 "cpsetua1.w\\t%0,%1"
6513 [(set_attr "may_trap" "no")
6514 (set_attr "latency" "0")
6515 (set_attr "length" "4")
6516 (set_attr "slot" "cop")
6517 (set_attr "slots" "c3")
6518 (set_attr "stall" "none")])
6521 (define_insn "cgen_intrinsic_cpsetua1_w_P1"
6523 (unspec_volatile:SI [
6524 (match_operand:DI 0 "general_operand" "x")
6525 (match_operand:DI 1 "general_operand" "x")
6528 (unspec_volatile:SI [
6533 (unspec_volatile:SI [
6538 (unspec_volatile:SI [
6542 "CGEN_ENABLE_INSN_P (172)"
6543 "cpsetua1.w\\t%0,%1"
6544 [(set_attr "may_trap" "no")
6545 (set_attr "latency" "0")
6546 (set_attr "length" "4")
6547 (set_attr "slot" "cop")
6548 (set_attr "slots" "p1")
6549 (set_attr "stall" "none")])
6552 (define_insn "cgen_intrinsic_cpseta1_h_C3"
6554 (unspec_volatile:SI [
6555 (match_operand:DI 0 "general_operand" "x")
6556 (match_operand:DI 1 "general_operand" "x")
6559 (unspec_volatile:SI [
6564 (unspec_volatile:SI [
6569 (unspec_volatile:SI [
6574 (unspec_volatile:SI [
6579 (unspec_volatile:SI [
6584 (unspec_volatile:SI [
6589 (unspec_volatile:SI [
6593 "CGEN_ENABLE_INSN_P (173)"
6595 [(set_attr "may_trap" "no")
6596 (set_attr "latency" "0")
6597 (set_attr "length" "4")
6598 (set_attr "slot" "cop")
6599 (set_attr "slots" "c3")
6600 (set_attr "stall" "none")])
6603 (define_insn "cgen_intrinsic_cpseta1_h_P1"
6605 (unspec_volatile:SI [
6606 (match_operand:DI 0 "general_operand" "x")
6607 (match_operand:DI 1 "general_operand" "x")
6610 (unspec_volatile:SI [
6615 (unspec_volatile:SI [
6620 (unspec_volatile:SI [
6625 (unspec_volatile:SI [
6630 (unspec_volatile:SI [
6635 (unspec_volatile:SI [
6640 (unspec_volatile:SI [
6644 "CGEN_ENABLE_INSN_P (174)"
6646 [(set_attr "may_trap" "no")
6647 (set_attr "latency" "0")
6648 (set_attr "length" "4")
6649 (set_attr "slot" "cop")
6650 (set_attr "slots" "p1")
6651 (set_attr "stall" "none")])
6654 (define_insn "cgen_intrinsic_cpsadla1_h_C3"
6656 (unspec_volatile:SI [
6657 (match_operand:DI 0 "general_operand" "x")
6658 (match_operand:DI 1 "general_operand" "x")
6661 (unspec_volatile:SI [
6666 (unspec_volatile:SI [
6671 (unspec_volatile:SI [
6676 (unspec_volatile:SI [
6680 "CGEN_ENABLE_INSN_P (175)"
6681 "cpsadla1.h\\t%0,%1"
6682 [(set_attr "may_trap" "no")
6683 (set_attr "latency" "0")
6684 (set_attr "length" "4")
6685 (set_attr "slot" "cop")
6686 (set_attr "slots" "c3")
6687 (set_attr "stall" "none")])
6690 (define_insn "cgen_intrinsic_cpsadla1_h_P1"
6692 (unspec_volatile:SI [
6693 (match_operand:DI 0 "general_operand" "x")
6694 (match_operand:DI 1 "general_operand" "x")
6697 (unspec_volatile:SI [
6702 (unspec_volatile:SI [
6707 (unspec_volatile:SI [
6712 (unspec_volatile:SI [
6716 "CGEN_ENABLE_INSN_P (176)"
6717 "cpsadla1.h\\t%0,%1"
6718 [(set_attr "may_trap" "no")
6719 (set_attr "latency" "0")
6720 (set_attr "length" "4")
6721 (set_attr "slot" "cop")
6722 (set_attr "slots" "p1")
6723 (set_attr "stall" "none")])
6726 (define_insn "cgen_intrinsic_cpsadua1_h_C3"
6728 (unspec_volatile:SI [
6729 (match_operand:DI 0 "general_operand" "x")
6730 (match_operand:DI 1 "general_operand" "x")
6733 (unspec_volatile:SI [
6738 (unspec_volatile:SI [
6743 (unspec_volatile:SI [
6748 (unspec_volatile:SI [
6752 "CGEN_ENABLE_INSN_P (177)"
6753 "cpsadua1.h\\t%0,%1"
6754 [(set_attr "may_trap" "no")
6755 (set_attr "latency" "0")
6756 (set_attr "length" "4")
6757 (set_attr "slot" "cop")
6758 (set_attr "slots" "c3")
6759 (set_attr "stall" "none")])
6762 (define_insn "cgen_intrinsic_cpsadua1_h_P1"
6764 (unspec_volatile:SI [
6765 (match_operand:DI 0 "general_operand" "x")
6766 (match_operand:DI 1 "general_operand" "x")
6769 (unspec_volatile:SI [
6774 (unspec_volatile:SI [
6779 (unspec_volatile:SI [
6784 (unspec_volatile:SI [
6788 "CGEN_ENABLE_INSN_P (178)"
6789 "cpsadua1.h\\t%0,%1"
6790 [(set_attr "may_trap" "no")
6791 (set_attr "latency" "0")
6792 (set_attr "length" "4")
6793 (set_attr "slot" "cop")
6794 (set_attr "slots" "p1")
6795 (set_attr "stall" "none")])
6798 (define_insn "cgen_intrinsic_cpsada1_b_C3"
6800 (unspec_volatile:SI [
6801 (match_operand:DI 0 "general_operand" "x")
6802 (match_operand:DI 1 "general_operand" "x")
6805 (unspec_volatile:SI [
6810 (unspec_volatile:SI [
6815 (unspec_volatile:SI [
6820 (unspec_volatile:SI [
6825 (unspec_volatile:SI [
6830 (unspec_volatile:SI [
6835 (unspec_volatile:SI [
6840 (unspec_volatile:SI [
6844 "CGEN_ENABLE_INSN_P (179)"
6846 [(set_attr "may_trap" "no")
6847 (set_attr "latency" "0")
6848 (set_attr "length" "4")
6849 (set_attr "slot" "cop")
6850 (set_attr "slots" "c3")
6851 (set_attr "stall" "none")])
6854 (define_insn "cgen_intrinsic_cpsada1_b_P1"
6856 (unspec_volatile:SI [
6857 (match_operand:DI 0 "general_operand" "x")
6858 (match_operand:DI 1 "general_operand" "x")
6861 (unspec_volatile:SI [
6866 (unspec_volatile:SI [
6871 (unspec_volatile:SI [
6876 (unspec_volatile:SI [
6881 (unspec_volatile:SI [
6886 (unspec_volatile:SI [
6891 (unspec_volatile:SI [
6896 (unspec_volatile:SI [
6900 "CGEN_ENABLE_INSN_P (180)"
6902 [(set_attr "may_trap" "no")
6903 (set_attr "latency" "0")
6904 (set_attr "length" "4")
6905 (set_attr "slot" "cop")
6906 (set_attr "slots" "p1")
6907 (set_attr "stall" "none")])
6910 (define_insn "cgen_intrinsic_cpsada1u_b_C3"
6912 (unspec_volatile:SI [
6913 (match_operand:DI 0 "general_operand" "x")
6914 (match_operand:DI 1 "general_operand" "x")
6917 (unspec_volatile:SI [
6922 (unspec_volatile:SI [
6927 (unspec_volatile:SI [
6932 (unspec_volatile:SI [
6937 (unspec_volatile:SI [
6942 (unspec_volatile:SI [
6947 (unspec_volatile:SI [
6952 (unspec_volatile:SI [
6956 "CGEN_ENABLE_INSN_P (181)"
6957 "cpsada1u.b\\t%0,%1"
6958 [(set_attr "may_trap" "no")
6959 (set_attr "latency" "0")
6960 (set_attr "length" "4")
6961 (set_attr "slot" "cop")
6962 (set_attr "slots" "c3")
6963 (set_attr "stall" "none")])
6966 (define_insn "cgen_intrinsic_cpsada1u_b_P1"
6968 (unspec_volatile:SI [
6969 (match_operand:DI 0 "general_operand" "x")
6970 (match_operand:DI 1 "general_operand" "x")
6973 (unspec_volatile:SI [
6978 (unspec_volatile:SI [
6983 (unspec_volatile:SI [
6988 (unspec_volatile:SI [
6993 (unspec_volatile:SI [
6998 (unspec_volatile:SI [
7003 (unspec_volatile:SI [
7008 (unspec_volatile:SI [
7012 "CGEN_ENABLE_INSN_P (182)"
7013 "cpsada1u.b\\t%0,%1"
7014 [(set_attr "may_trap" "no")
7015 (set_attr "latency" "0")
7016 (set_attr "length" "4")
7017 (set_attr "slot" "cop")
7018 (set_attr "slots" "p1")
7019 (set_attr "stall" "none")])
7022 (define_insn "cgen_intrinsic_cpabsla1_h_C3"
7024 (unspec_volatile:SI [
7025 (match_operand:DI 0 "general_operand" "x")
7026 (match_operand:DI 1 "general_operand" "x")
7029 (unspec_volatile:SI [
7034 (unspec_volatile:SI [
7039 (unspec_volatile:SI [
7043 "CGEN_ENABLE_INSN_P (183)"
7044 "cpabsla1.h\\t%0,%1"
7045 [(set_attr "may_trap" "no")
7046 (set_attr "latency" "0")
7047 (set_attr "length" "4")
7048 (set_attr "slot" "cop")
7049 (set_attr "slots" "c3")
7050 (set_attr "stall" "none")])
7053 (define_insn "cgen_intrinsic_cpabsla1_h_P1"
7055 (unspec_volatile:SI [
7056 (match_operand:DI 0 "general_operand" "x")
7057 (match_operand:DI 1 "general_operand" "x")
7060 (unspec_volatile:SI [
7065 (unspec_volatile:SI [
7070 (unspec_volatile:SI [
7074 "CGEN_ENABLE_INSN_P (184)"
7075 "cpabsla1.h\\t%0,%1"
7076 [(set_attr "may_trap" "no")
7077 (set_attr "latency" "0")
7078 (set_attr "length" "4")
7079 (set_attr "slot" "cop")
7080 (set_attr "slots" "p1")
7081 (set_attr "stall" "none")])
7084 (define_insn "cgen_intrinsic_cpabsua1_h_C3"
7086 (unspec_volatile:SI [
7087 (match_operand:DI 0 "general_operand" "x")
7088 (match_operand:DI 1 "general_operand" "x")
7091 (unspec_volatile:SI [
7096 (unspec_volatile:SI [
7101 (unspec_volatile:SI [
7105 "CGEN_ENABLE_INSN_P (185)"
7106 "cpabsua1.h\\t%0,%1"
7107 [(set_attr "may_trap" "no")
7108 (set_attr "latency" "0")
7109 (set_attr "length" "4")
7110 (set_attr "slot" "cop")
7111 (set_attr "slots" "c3")
7112 (set_attr "stall" "none")])
7115 (define_insn "cgen_intrinsic_cpabsua1_h_P1"
7117 (unspec_volatile:SI [
7118 (match_operand:DI 0 "general_operand" "x")
7119 (match_operand:DI 1 "general_operand" "x")
7122 (unspec_volatile:SI [
7127 (unspec_volatile:SI [
7132 (unspec_volatile:SI [
7136 "CGEN_ENABLE_INSN_P (186)"
7137 "cpabsua1.h\\t%0,%1"
7138 [(set_attr "may_trap" "no")
7139 (set_attr "latency" "0")
7140 (set_attr "length" "4")
7141 (set_attr "slot" "cop")
7142 (set_attr "slots" "p1")
7143 (set_attr "stall" "none")])
7146 (define_insn "cgen_intrinsic_cpabsa1_b_C3"
7148 (unspec_volatile:SI [
7149 (match_operand:DI 0 "general_operand" "x")
7150 (match_operand:DI 1 "general_operand" "x")
7153 (unspec_volatile:SI [
7158 (unspec_volatile:SI [
7163 (unspec_volatile:SI [
7168 (unspec_volatile:SI [
7173 (unspec_volatile:SI [
7178 (unspec_volatile:SI [
7183 (unspec_volatile:SI [
7187 "CGEN_ENABLE_INSN_P (187)"
7189 [(set_attr "may_trap" "no")
7190 (set_attr "latency" "0")
7191 (set_attr "length" "4")
7192 (set_attr "slot" "cop")
7193 (set_attr "slots" "c3")
7194 (set_attr "stall" "none")])
7197 (define_insn "cgen_intrinsic_cpabsa1_b_P1"
7199 (unspec_volatile:SI [
7200 (match_operand:DI 0 "general_operand" "x")
7201 (match_operand:DI 1 "general_operand" "x")
7204 (unspec_volatile:SI [
7209 (unspec_volatile:SI [
7214 (unspec_volatile:SI [
7219 (unspec_volatile:SI [
7224 (unspec_volatile:SI [
7229 (unspec_volatile:SI [
7234 (unspec_volatile:SI [
7238 "CGEN_ENABLE_INSN_P (188)"
7240 [(set_attr "may_trap" "no")
7241 (set_attr "latency" "0")
7242 (set_attr "length" "4")
7243 (set_attr "slot" "cop")
7244 (set_attr "slots" "p1")
7245 (set_attr "stall" "none")])
7248 (define_insn "cgen_intrinsic_cpabsa1u_b_C3"
7250 (unspec_volatile:SI [
7251 (match_operand:DI 0 "general_operand" "x")
7252 (match_operand:DI 1 "general_operand" "x")
7255 (unspec_volatile:SI [
7260 (unspec_volatile:SI [
7265 (unspec_volatile:SI [
7270 (unspec_volatile:SI [
7275 (unspec_volatile:SI [
7280 (unspec_volatile:SI [
7285 (unspec_volatile:SI [
7289 "CGEN_ENABLE_INSN_P (189)"
7290 "cpabsa1u.b\\t%0,%1"
7291 [(set_attr "may_trap" "no")
7292 (set_attr "latency" "0")
7293 (set_attr "length" "4")
7294 (set_attr "slot" "cop")
7295 (set_attr "slots" "c3")
7296 (set_attr "stall" "none")])
7299 (define_insn "cgen_intrinsic_cpabsa1u_b_P1"
7301 (unspec_volatile:SI [
7302 (match_operand:DI 0 "general_operand" "x")
7303 (match_operand:DI 1 "general_operand" "x")
7306 (unspec_volatile:SI [
7311 (unspec_volatile:SI [
7316 (unspec_volatile:SI [
7321 (unspec_volatile:SI [
7326 (unspec_volatile:SI [
7331 (unspec_volatile:SI [
7336 (unspec_volatile:SI [
7340 "CGEN_ENABLE_INSN_P (190)"
7341 "cpabsa1u.b\\t%0,%1"
7342 [(set_attr "may_trap" "no")
7343 (set_attr "latency" "0")
7344 (set_attr "length" "4")
7345 (set_attr "slot" "cop")
7346 (set_attr "slots" "p1")
7347 (set_attr "stall" "none")])
7350 (define_insn "cgen_intrinsic_cpsubacla1_h_C3"
7352 (unspec_volatile:SI [
7353 (match_operand:DI 0 "general_operand" "x")
7354 (match_operand:DI 1 "general_operand" "x")
7357 (unspec_volatile:SI [
7362 (unspec_volatile:SI [
7367 (unspec_volatile:SI [
7372 (unspec_volatile:SI [
7376 "CGEN_ENABLE_INSN_P (191)"
7377 "cpsubacla1.h\\t%0,%1"
7378 [(set_attr "may_trap" "no")
7379 (set_attr "latency" "0")
7380 (set_attr "length" "4")
7381 (set_attr "slot" "cop")
7382 (set_attr "slots" "c3")
7383 (set_attr "stall" "none")])
7386 (define_insn "cgen_intrinsic_cpsubacla1_h_P1"
7388 (unspec_volatile:SI [
7389 (match_operand:DI 0 "general_operand" "x")
7390 (match_operand:DI 1 "general_operand" "x")
7393 (unspec_volatile:SI [
7398 (unspec_volatile:SI [
7403 (unspec_volatile:SI [
7408 (unspec_volatile:SI [
7412 "CGEN_ENABLE_INSN_P (192)"
7413 "cpsubacla1.h\\t%0,%1"
7414 [(set_attr "may_trap" "no")
7415 (set_attr "latency" "0")
7416 (set_attr "length" "4")
7417 (set_attr "slot" "cop")
7418 (set_attr "slots" "p1")
7419 (set_attr "stall" "none")])
7422 (define_insn "cgen_intrinsic_cpsubacua1_h_C3"
7424 (unspec_volatile:SI [
7425 (match_operand:DI 0 "general_operand" "x")
7426 (match_operand:DI 1 "general_operand" "x")
7429 (unspec_volatile:SI [
7434 (unspec_volatile:SI [
7439 (unspec_volatile:SI [
7444 (unspec_volatile:SI [
7448 "CGEN_ENABLE_INSN_P (193)"
7449 "cpsubacua1.h\\t%0,%1"
7450 [(set_attr "may_trap" "no")
7451 (set_attr "latency" "0")
7452 (set_attr "length" "4")
7453 (set_attr "slot" "cop")
7454 (set_attr "slots" "c3")
7455 (set_attr "stall" "none")])
7458 (define_insn "cgen_intrinsic_cpsubacua1_h_P1"
7460 (unspec_volatile:SI [
7461 (match_operand:DI 0 "general_operand" "x")
7462 (match_operand:DI 1 "general_operand" "x")
7465 (unspec_volatile:SI [
7470 (unspec_volatile:SI [
7475 (unspec_volatile:SI [
7480 (unspec_volatile:SI [
7484 "CGEN_ENABLE_INSN_P (194)"
7485 "cpsubacua1.h\\t%0,%1"
7486 [(set_attr "may_trap" "no")
7487 (set_attr "latency" "0")
7488 (set_attr "length" "4")
7489 (set_attr "slot" "cop")
7490 (set_attr "slots" "p1")
7491 (set_attr "stall" "none")])
7494 (define_insn "cgen_intrinsic_cpsubaca1_b_C3"
7496 (unspec_volatile:SI [
7497 (match_operand:DI 0 "general_operand" "x")
7498 (match_operand:DI 1 "general_operand" "x")
7501 (unspec_volatile:SI [
7506 (unspec_volatile:SI [
7511 (unspec_volatile:SI [
7516 (unspec_volatile:SI [
7521 (unspec_volatile:SI [
7526 (unspec_volatile:SI [
7531 (unspec_volatile:SI [
7536 (unspec_volatile:SI [
7540 "CGEN_ENABLE_INSN_P (195)"
7541 "cpsubaca1.b\\t%0,%1"
7542 [(set_attr "may_trap" "no")
7543 (set_attr "latency" "0")
7544 (set_attr "length" "4")
7545 (set_attr "slot" "cop")
7546 (set_attr "slots" "c3")
7547 (set_attr "stall" "none")])
7550 (define_insn "cgen_intrinsic_cpsubaca1_b_P1"
7552 (unspec_volatile:SI [
7553 (match_operand:DI 0 "general_operand" "x")
7554 (match_operand:DI 1 "general_operand" "x")
7557 (unspec_volatile:SI [
7562 (unspec_volatile:SI [
7567 (unspec_volatile:SI [
7572 (unspec_volatile:SI [
7577 (unspec_volatile:SI [
7582 (unspec_volatile:SI [
7587 (unspec_volatile:SI [
7592 (unspec_volatile:SI [
7596 "CGEN_ENABLE_INSN_P (196)"
7597 "cpsubaca1.b\\t%0,%1"
7598 [(set_attr "may_trap" "no")
7599 (set_attr "latency" "0")
7600 (set_attr "length" "4")
7601 (set_attr "slot" "cop")
7602 (set_attr "slots" "p1")
7603 (set_attr "stall" "none")])
7606 (define_insn "cgen_intrinsic_cpsubaca1u_b_C3"
7608 (unspec_volatile:SI [
7609 (match_operand:DI 0 "general_operand" "x")
7610 (match_operand:DI 1 "general_operand" "x")
7613 (unspec_volatile:SI [
7618 (unspec_volatile:SI [
7623 (unspec_volatile:SI [
7628 (unspec_volatile:SI [
7633 (unspec_volatile:SI [
7638 (unspec_volatile:SI [
7643 (unspec_volatile:SI [
7648 (unspec_volatile:SI [
7652 "CGEN_ENABLE_INSN_P (197)"
7653 "cpsubaca1u.b\\t%0,%1"
7654 [(set_attr "may_trap" "no")
7655 (set_attr "latency" "0")
7656 (set_attr "length" "4")
7657 (set_attr "slot" "cop")
7658 (set_attr "slots" "c3")
7659 (set_attr "stall" "none")])
7662 (define_insn "cgen_intrinsic_cpsubaca1u_b_P1"
7664 (unspec_volatile:SI [
7665 (match_operand:DI 0 "general_operand" "x")
7666 (match_operand:DI 1 "general_operand" "x")
7669 (unspec_volatile:SI [
7674 (unspec_volatile:SI [
7679 (unspec_volatile:SI [
7684 (unspec_volatile:SI [
7689 (unspec_volatile:SI [
7694 (unspec_volatile:SI [
7699 (unspec_volatile:SI [
7704 (unspec_volatile:SI [
7708 "CGEN_ENABLE_INSN_P (198)"
7709 "cpsubaca1u.b\\t%0,%1"
7710 [(set_attr "may_trap" "no")
7711 (set_attr "latency" "0")
7712 (set_attr "length" "4")
7713 (set_attr "slot" "cop")
7714 (set_attr "slots" "p1")
7715 (set_attr "stall" "none")])
7718 (define_insn "cgen_intrinsic_cpsubla1_h_C3"
7720 (unspec_volatile:SI [
7721 (match_operand:DI 0 "general_operand" "x")
7722 (match_operand:DI 1 "general_operand" "x")
7725 (unspec_volatile:SI [
7730 (unspec_volatile:SI [
7735 (unspec_volatile:SI [
7739 "CGEN_ENABLE_INSN_P (199)"
7740 "cpsubla1.h\\t%0,%1"
7741 [(set_attr "may_trap" "no")
7742 (set_attr "latency" "0")
7743 (set_attr "length" "4")
7744 (set_attr "slot" "cop")
7745 (set_attr "slots" "c3")
7746 (set_attr "stall" "none")])
7749 (define_insn "cgen_intrinsic_cpsubla1_h_P1"
7751 (unspec_volatile:SI [
7752 (match_operand:DI 0 "general_operand" "x")
7753 (match_operand:DI 1 "general_operand" "x")
7756 (unspec_volatile:SI [
7761 (unspec_volatile:SI [
7766 (unspec_volatile:SI [
7770 "CGEN_ENABLE_INSN_P (200)"
7771 "cpsubla1.h\\t%0,%1"
7772 [(set_attr "may_trap" "no")
7773 (set_attr "latency" "0")
7774 (set_attr "length" "4")
7775 (set_attr "slot" "cop")
7776 (set_attr "slots" "p1")
7777 (set_attr "stall" "none")])
7780 (define_insn "cgen_intrinsic_cpsubua1_h_C3"
7782 (unspec_volatile:SI [
7783 (match_operand:DI 0 "general_operand" "x")
7784 (match_operand:DI 1 "general_operand" "x")
7787 (unspec_volatile:SI [
7792 (unspec_volatile:SI [
7797 (unspec_volatile:SI [
7801 "CGEN_ENABLE_INSN_P (201)"
7802 "cpsubua1.h\\t%0,%1"
7803 [(set_attr "may_trap" "no")
7804 (set_attr "latency" "0")
7805 (set_attr "length" "4")
7806 (set_attr "slot" "cop")
7807 (set_attr "slots" "c3")
7808 (set_attr "stall" "none")])
7811 (define_insn "cgen_intrinsic_cpsubua1_h_P1"
7813 (unspec_volatile:SI [
7814 (match_operand:DI 0 "general_operand" "x")
7815 (match_operand:DI 1 "general_operand" "x")
7818 (unspec_volatile:SI [
7823 (unspec_volatile:SI [
7828 (unspec_volatile:SI [
7832 "CGEN_ENABLE_INSN_P (202)"
7833 "cpsubua1.h\\t%0,%1"
7834 [(set_attr "may_trap" "no")
7835 (set_attr "latency" "0")
7836 (set_attr "length" "4")
7837 (set_attr "slot" "cop")
7838 (set_attr "slots" "p1")
7839 (set_attr "stall" "none")])
7842 (define_insn "cgen_intrinsic_cpsuba1_b_C3"
7844 (unspec_volatile:SI [
7845 (match_operand:DI 0 "general_operand" "x")
7846 (match_operand:DI 1 "general_operand" "x")
7849 (unspec_volatile:SI [
7854 (unspec_volatile:SI [
7859 (unspec_volatile:SI [
7864 (unspec_volatile:SI [
7869 (unspec_volatile:SI [
7874 (unspec_volatile:SI [
7879 (unspec_volatile:SI [
7883 "CGEN_ENABLE_INSN_P (203)"
7885 [(set_attr "may_trap" "no")
7886 (set_attr "latency" "0")
7887 (set_attr "length" "4")
7888 (set_attr "slot" "cop")
7889 (set_attr "slots" "c3")
7890 (set_attr "stall" "none")])
7893 (define_insn "cgen_intrinsic_cpsuba1_b_P1"
7895 (unspec_volatile:SI [
7896 (match_operand:DI 0 "general_operand" "x")
7897 (match_operand:DI 1 "general_operand" "x")
7900 (unspec_volatile:SI [
7905 (unspec_volatile:SI [
7910 (unspec_volatile:SI [
7915 (unspec_volatile:SI [
7920 (unspec_volatile:SI [
7925 (unspec_volatile:SI [
7930 (unspec_volatile:SI [
7934 "CGEN_ENABLE_INSN_P (204)"
7936 [(set_attr "may_trap" "no")
7937 (set_attr "latency" "0")
7938 (set_attr "length" "4")
7939 (set_attr "slot" "cop")
7940 (set_attr "slots" "p1")
7941 (set_attr "stall" "none")])
7944 (define_insn "cgen_intrinsic_cpsuba1u_b_C3"
7946 (unspec_volatile:SI [
7947 (match_operand:DI 0 "general_operand" "x")
7948 (match_operand:DI 1 "general_operand" "x")
7951 (unspec_volatile:SI [
7956 (unspec_volatile:SI [
7961 (unspec_volatile:SI [
7966 (unspec_volatile:SI [
7971 (unspec_volatile:SI [
7976 (unspec_volatile:SI [
7981 (unspec_volatile:SI [
7985 "CGEN_ENABLE_INSN_P (205)"
7986 "cpsuba1u.b\\t%0,%1"
7987 [(set_attr "may_trap" "no")
7988 (set_attr "latency" "0")
7989 (set_attr "length" "4")
7990 (set_attr "slot" "cop")
7991 (set_attr "slots" "c3")
7992 (set_attr "stall" "none")])
7995 (define_insn "cgen_intrinsic_cpsuba1u_b_P1"
7997 (unspec_volatile:SI [
7998 (match_operand:DI 0 "general_operand" "x")
7999 (match_operand:DI 1 "general_operand" "x")
8002 (unspec_volatile:SI [
8007 (unspec_volatile:SI [
8012 (unspec_volatile:SI [
8017 (unspec_volatile:SI [
8022 (unspec_volatile:SI [
8027 (unspec_volatile:SI [
8032 (unspec_volatile:SI [
8036 "CGEN_ENABLE_INSN_P (206)"
8037 "cpsuba1u.b\\t%0,%1"
8038 [(set_attr "may_trap" "no")
8039 (set_attr "latency" "0")
8040 (set_attr "length" "4")
8041 (set_attr "slot" "cop")
8042 (set_attr "slots" "p1")
8043 (set_attr "stall" "none")])
8046 (define_insn "cgen_intrinsic_cpaddacla1_h_C3"
8048 (unspec_volatile:SI [
8049 (match_operand:DI 0 "general_operand" "x")
8050 (match_operand:DI 1 "general_operand" "x")
8053 (unspec_volatile:SI [
8058 (unspec_volatile:SI [
8063 (unspec_volatile:SI [
8068 (unspec_volatile:SI [
8072 "CGEN_ENABLE_INSN_P (207)"
8073 "cpaddacla1.h\\t%0,%1"
8074 [(set_attr "may_trap" "no")
8075 (set_attr "latency" "0")
8076 (set_attr "length" "4")
8077 (set_attr "slot" "cop")
8078 (set_attr "slots" "c3")
8079 (set_attr "stall" "none")])
8082 (define_insn "cgen_intrinsic_cpaddacla1_h_P1"
8084 (unspec_volatile:SI [
8085 (match_operand:DI 0 "general_operand" "x")
8086 (match_operand:DI 1 "general_operand" "x")
8089 (unspec_volatile:SI [
8094 (unspec_volatile:SI [
8099 (unspec_volatile:SI [
8104 (unspec_volatile:SI [
8108 "CGEN_ENABLE_INSN_P (208)"
8109 "cpaddacla1.h\\t%0,%1"
8110 [(set_attr "may_trap" "no")
8111 (set_attr "latency" "0")
8112 (set_attr "length" "4")
8113 (set_attr "slot" "cop")
8114 (set_attr "slots" "p1")
8115 (set_attr "stall" "none")])
8118 (define_insn "cgen_intrinsic_cpaddacua1_h_C3"
8120 (unspec_volatile:SI [
8121 (match_operand:DI 0 "general_operand" "x")
8122 (match_operand:DI 1 "general_operand" "x")
8125 (unspec_volatile:SI [
8130 (unspec_volatile:SI [
8135 (unspec_volatile:SI [
8140 (unspec_volatile:SI [
8144 "CGEN_ENABLE_INSN_P (209)"
8145 "cpaddacua1.h\\t%0,%1"
8146 [(set_attr "may_trap" "no")
8147 (set_attr "latency" "0")
8148 (set_attr "length" "4")
8149 (set_attr "slot" "cop")
8150 (set_attr "slots" "c3")
8151 (set_attr "stall" "none")])
8154 (define_insn "cgen_intrinsic_cpaddacua1_h_P1"
8156 (unspec_volatile:SI [
8157 (match_operand:DI 0 "general_operand" "x")
8158 (match_operand:DI 1 "general_operand" "x")
8161 (unspec_volatile:SI [
8166 (unspec_volatile:SI [
8171 (unspec_volatile:SI [
8176 (unspec_volatile:SI [
8180 "CGEN_ENABLE_INSN_P (210)"
8181 "cpaddacua1.h\\t%0,%1"
8182 [(set_attr "may_trap" "no")
8183 (set_attr "latency" "0")
8184 (set_attr "length" "4")
8185 (set_attr "slot" "cop")
8186 (set_attr "slots" "p1")
8187 (set_attr "stall" "none")])
8190 (define_insn "cgen_intrinsic_cpaddaca1_b_C3"
8192 (unspec_volatile:SI [
8193 (match_operand:DI 0 "general_operand" "x")
8194 (match_operand:DI 1 "general_operand" "x")
8197 (unspec_volatile:SI [
8202 (unspec_volatile:SI [
8207 (unspec_volatile:SI [
8212 (unspec_volatile:SI [
8217 (unspec_volatile:SI [
8222 (unspec_volatile:SI [
8227 (unspec_volatile:SI [
8232 (unspec_volatile:SI [
8236 "CGEN_ENABLE_INSN_P (211)"
8237 "cpaddaca1.b\\t%0,%1"
8238 [(set_attr "may_trap" "no")
8239 (set_attr "latency" "0")
8240 (set_attr "length" "4")
8241 (set_attr "slot" "cop")
8242 (set_attr "slots" "c3")
8243 (set_attr "stall" "none")])
8246 (define_insn "cgen_intrinsic_cpaddaca1_b_P1"
8248 (unspec_volatile:SI [
8249 (match_operand:DI 0 "general_operand" "x")
8250 (match_operand:DI 1 "general_operand" "x")
8253 (unspec_volatile:SI [
8258 (unspec_volatile:SI [
8263 (unspec_volatile:SI [
8268 (unspec_volatile:SI [
8273 (unspec_volatile:SI [
8278 (unspec_volatile:SI [
8283 (unspec_volatile:SI [
8288 (unspec_volatile:SI [
8292 "CGEN_ENABLE_INSN_P (212)"
8293 "cpaddaca1.b\\t%0,%1"
8294 [(set_attr "may_trap" "no")
8295 (set_attr "latency" "0")
8296 (set_attr "length" "4")
8297 (set_attr "slot" "cop")
8298 (set_attr "slots" "p1")
8299 (set_attr "stall" "none")])
8302 (define_insn "cgen_intrinsic_cpaddaca1u_b_C3"
8304 (unspec_volatile:SI [
8305 (match_operand:DI 0 "general_operand" "x")
8306 (match_operand:DI 1 "general_operand" "x")
8309 (unspec_volatile:SI [
8314 (unspec_volatile:SI [
8319 (unspec_volatile:SI [
8324 (unspec_volatile:SI [
8329 (unspec_volatile:SI [
8334 (unspec_volatile:SI [
8339 (unspec_volatile:SI [
8344 (unspec_volatile:SI [
8348 "CGEN_ENABLE_INSN_P (213)"
8349 "cpaddaca1u.b\\t%0,%1"
8350 [(set_attr "may_trap" "no")
8351 (set_attr "latency" "0")
8352 (set_attr "length" "4")
8353 (set_attr "slot" "cop")
8354 (set_attr "slots" "c3")
8355 (set_attr "stall" "none")])
8358 (define_insn "cgen_intrinsic_cpaddaca1u_b_P1"
8360 (unspec_volatile:SI [
8361 (match_operand:DI 0 "general_operand" "x")
8362 (match_operand:DI 1 "general_operand" "x")
8365 (unspec_volatile:SI [
8370 (unspec_volatile:SI [
8375 (unspec_volatile:SI [
8380 (unspec_volatile:SI [
8385 (unspec_volatile:SI [
8390 (unspec_volatile:SI [
8395 (unspec_volatile:SI [
8400 (unspec_volatile:SI [
8404 "CGEN_ENABLE_INSN_P (214)"
8405 "cpaddaca1u.b\\t%0,%1"
8406 [(set_attr "may_trap" "no")
8407 (set_attr "latency" "0")
8408 (set_attr "length" "4")
8409 (set_attr "slot" "cop")
8410 (set_attr "slots" "p1")
8411 (set_attr "stall" "none")])
8414 (define_insn "cgen_intrinsic_cpaddla1_h_C3"
8416 (unspec_volatile:SI [
8417 (match_operand:DI 0 "general_operand" "x")
8418 (match_operand:DI 1 "general_operand" "x")
8421 (unspec_volatile:SI [
8426 (unspec_volatile:SI [
8431 (unspec_volatile:SI [
8435 "CGEN_ENABLE_INSN_P (215)"
8436 "cpaddla1.h\\t%0,%1"
8437 [(set_attr "may_trap" "no")
8438 (set_attr "latency" "0")
8439 (set_attr "length" "4")
8440 (set_attr "slot" "cop")
8441 (set_attr "slots" "c3")
8442 (set_attr "stall" "none")])
8445 (define_insn "cgen_intrinsic_cpaddla1_h_P1"
8447 (unspec_volatile:SI [
8448 (match_operand:DI 0 "general_operand" "x")
8449 (match_operand:DI 1 "general_operand" "x")
8452 (unspec_volatile:SI [
8457 (unspec_volatile:SI [
8462 (unspec_volatile:SI [
8466 "CGEN_ENABLE_INSN_P (216)"
8467 "cpaddla1.h\\t%0,%1"
8468 [(set_attr "may_trap" "no")
8469 (set_attr "latency" "0")
8470 (set_attr "length" "4")
8471 (set_attr "slot" "cop")
8472 (set_attr "slots" "p1")
8473 (set_attr "stall" "none")])
8476 (define_insn "cgen_intrinsic_cpaddua1_h_C3"
8478 (unspec_volatile:SI [
8479 (match_operand:DI 0 "general_operand" "x")
8480 (match_operand:DI 1 "general_operand" "x")
8483 (unspec_volatile:SI [
8488 (unspec_volatile:SI [
8493 (unspec_volatile:SI [
8497 "CGEN_ENABLE_INSN_P (217)"
8498 "cpaddua1.h\\t%0,%1"
8499 [(set_attr "may_trap" "no")
8500 (set_attr "latency" "0")
8501 (set_attr "length" "4")
8502 (set_attr "slot" "cop")
8503 (set_attr "slots" "c3")
8504 (set_attr "stall" "none")])
8507 (define_insn "cgen_intrinsic_cpaddua1_h_P1"
8509 (unspec_volatile:SI [
8510 (match_operand:DI 0 "general_operand" "x")
8511 (match_operand:DI 1 "general_operand" "x")
8514 (unspec_volatile:SI [
8519 (unspec_volatile:SI [
8524 (unspec_volatile:SI [
8528 "CGEN_ENABLE_INSN_P (218)"
8529 "cpaddua1.h\\t%0,%1"
8530 [(set_attr "may_trap" "no")
8531 (set_attr "latency" "0")
8532 (set_attr "length" "4")
8533 (set_attr "slot" "cop")
8534 (set_attr "slots" "p1")
8535 (set_attr "stall" "none")])
8538 (define_insn "cgen_intrinsic_cpadda1_b_C3"
8540 (unspec_volatile:SI [
8541 (match_operand:DI 0 "general_operand" "x")
8542 (match_operand:DI 1 "general_operand" "x")
8545 (unspec_volatile:SI [
8550 (unspec_volatile:SI [
8555 (unspec_volatile:SI [
8560 (unspec_volatile:SI [
8565 (unspec_volatile:SI [
8570 (unspec_volatile:SI [
8575 (unspec_volatile:SI [
8579 "CGEN_ENABLE_INSN_P (219)"
8581 [(set_attr "may_trap" "no")
8582 (set_attr "latency" "0")
8583 (set_attr "length" "4")
8584 (set_attr "slot" "cop")
8585 (set_attr "slots" "c3")
8586 (set_attr "stall" "none")])
8589 (define_insn "cgen_intrinsic_cpadda1_b_P1"
8591 (unspec_volatile:SI [
8592 (match_operand:DI 0 "general_operand" "x")
8593 (match_operand:DI 1 "general_operand" "x")
8596 (unspec_volatile:SI [
8601 (unspec_volatile:SI [
8606 (unspec_volatile:SI [
8611 (unspec_volatile:SI [
8616 (unspec_volatile:SI [
8621 (unspec_volatile:SI [
8626 (unspec_volatile:SI [
8630 "CGEN_ENABLE_INSN_P (220)"
8632 [(set_attr "may_trap" "no")
8633 (set_attr "latency" "0")
8634 (set_attr "length" "4")
8635 (set_attr "slot" "cop")
8636 (set_attr "slots" "p1")
8637 (set_attr "stall" "none")])
8640 (define_insn "cgen_intrinsic_cpadda1u_b_C3"
8642 (unspec_volatile:SI [
8643 (match_operand:DI 0 "general_operand" "x")
8644 (match_operand:DI 1 "general_operand" "x")
8647 (unspec_volatile:SI [
8652 (unspec_volatile:SI [
8657 (unspec_volatile:SI [
8662 (unspec_volatile:SI [
8667 (unspec_volatile:SI [
8672 (unspec_volatile:SI [
8677 (unspec_volatile:SI [
8681 "CGEN_ENABLE_INSN_P (221)"
8682 "cpadda1u.b\\t%0,%1"
8683 [(set_attr "may_trap" "no")
8684 (set_attr "latency" "0")
8685 (set_attr "length" "4")
8686 (set_attr "slot" "cop")
8687 (set_attr "slots" "c3")
8688 (set_attr "stall" "none")])
8691 (define_insn "cgen_intrinsic_cpadda1u_b_P1"
8693 (unspec_volatile:SI [
8694 (match_operand:DI 0 "general_operand" "x")
8695 (match_operand:DI 1 "general_operand" "x")
8698 (unspec_volatile:SI [
8703 (unspec_volatile:SI [
8708 (unspec_volatile:SI [
8713 (unspec_volatile:SI [
8718 (unspec_volatile:SI [
8723 (unspec_volatile:SI [
8728 (unspec_volatile:SI [
8732 "CGEN_ENABLE_INSN_P (222)"
8733 "cpadda1u.b\\t%0,%1"
8734 [(set_attr "may_trap" "no")
8735 (set_attr "latency" "0")
8736 (set_attr "length" "4")
8737 (set_attr "slot" "cop")
8738 (set_attr "slots" "p1")
8739 (set_attr "stall" "none")])
8742 (define_insn "cgen_intrinsic_cpmovi_b_C3"
8743 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8745 (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8747 "CGEN_ENABLE_INSN_P (223)"
8749 [(set_attr "may_trap" "no")
8750 (set_attr "latency" "0")
8751 (set_attr "length" "4")
8752 (set_attr "slot" "cop")
8753 (set_attr "slots" "c3")
8754 (set_attr "stall" "none")])
8757 (define_insn "cgen_intrinsic_cpmovi_b_P0S_P1"
8758 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8760 (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8762 "CGEN_ENABLE_INSN_P (224)"
8764 [(set_attr "may_trap" "no")
8765 (set_attr "latency" "0")
8766 (set_attr "length" "4")
8767 (set_attr "slot" "cop")
8768 (set_attr "slots" "p0s_p1")
8769 (set_attr "stall" "none")])
8772 (define_insn "cgen_intrinsic_c1nop_P1"
8776 "CGEN_ENABLE_INSN_P (225)"
8778 [(set_attr "may_trap" "no")
8779 (set_attr "latency" "0")
8780 (set_attr "length" "4")
8781 (set_attr "slot" "cop")
8782 (set_attr "slots" "p1")
8783 (set_attr "stall" "none")])
8786 (define_insn "cgen_intrinsic_cdmovi_C3"
8787 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8789 (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8791 "CGEN_ENABLE_INSN_P (226)"
8793 [(set_attr "may_trap" "no")
8794 (set_attr "latency" "0")
8795 (set_attr "length" "4")
8796 (set_attr "slot" "cop")
8797 (set_attr "slots" "c3")
8798 (set_attr "stall" "none")])
8801 (define_insn "cgen_intrinsic_cdmovi_P0_P1"
8802 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8804 (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
8806 "CGEN_ENABLE_INSN_P (227)"
8808 [(set_attr "may_trap" "no")
8809 (set_attr "latency" "0")
8810 (set_attr "length" "4")
8811 (set_attr "slot" "cop")
8812 (set_attr "slots" "p0_p1")
8813 (set_attr "stall" "none")])
8816 (define_insn "cgen_intrinsic_cdmoviu_C3"
8817 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8819 (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
8821 "CGEN_ENABLE_INSN_P (228)"
8823 [(set_attr "may_trap" "no")
8824 (set_attr "latency" "0")
8825 (set_attr "length" "4")
8826 (set_attr "slot" "cop")
8827 (set_attr "slots" "c3")
8828 (set_attr "stall" "none")])
8831 (define_insn "cgen_intrinsic_cdmoviu_P0_P1"
8832 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8834 (match_operand:DI 1 "cgen_h_uint_16a1_immediate" "")
8836 "CGEN_ENABLE_INSN_P (229)"
8838 [(set_attr "may_trap" "no")
8839 (set_attr "latency" "0")
8840 (set_attr "length" "4")
8841 (set_attr "slot" "cop")
8842 (set_attr "slots" "p0_p1")
8843 (set_attr "stall" "none")])
8846 (define_insn "cgen_intrinsic_cpmovi_w_C3"
8847 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8849 (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8851 "CGEN_ENABLE_INSN_P (230)"
8853 [(set_attr "may_trap" "no")
8854 (set_attr "latency" "0")
8855 (set_attr "length" "4")
8856 (set_attr "slot" "cop")
8857 (set_attr "slots" "c3")
8858 (set_attr "stall" "none")])
8861 (define_insn "cgen_intrinsic_cpmovi_w_P0_P1"
8862 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8864 (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
8866 "CGEN_ENABLE_INSN_P (231)"
8868 [(set_attr "may_trap" "no")
8869 (set_attr "latency" "0")
8870 (set_attr "length" "4")
8871 (set_attr "slot" "cop")
8872 (set_attr "slots" "p0_p1")
8873 (set_attr "stall" "none")])
8876 (define_insn "cgen_intrinsic_cpmoviu_w_C3"
8877 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8879 (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
8881 "CGEN_ENABLE_INSN_P (232)"
8883 [(set_attr "may_trap" "no")
8884 (set_attr "latency" "0")
8885 (set_attr "length" "4")
8886 (set_attr "slot" "cop")
8887 (set_attr "slots" "c3")
8888 (set_attr "stall" "none")])
8891 (define_insn "cgen_intrinsic_cpmoviu_w_P0_P1"
8892 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8894 (match_operand:DI 1 "cgen_h_uint_16a1_immediate" "")
8896 "CGEN_ENABLE_INSN_P (233)"
8898 [(set_attr "may_trap" "no")
8899 (set_attr "latency" "0")
8900 (set_attr "length" "4")
8901 (set_attr "slot" "cop")
8902 (set_attr "slots" "p0_p1")
8903 (set_attr "stall" "none")])
8906 (define_insn "cgen_intrinsic_cpmovi_h_C3"
8907 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8909 (match_operand:DI 1 "cgen_h_sint_8a1_immediate" "")
8911 "CGEN_ENABLE_INSN_P (234)"
8913 [(set_attr "may_trap" "no")
8914 (set_attr "latency" "0")
8915 (set_attr "length" "4")
8916 (set_attr "slot" "cop")
8917 (set_attr "slots" "c3")
8918 (set_attr "stall" "none")])
8921 (define_insn "cgen_intrinsic_cpmovi_h_P0_P1"
8922 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8924 (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
8926 "CGEN_ENABLE_INSN_P (235)"
8928 [(set_attr "may_trap" "no")
8929 (set_attr "latency" "0")
8930 (set_attr "length" "4")
8931 (set_attr "slot" "cop")
8932 (set_attr "slots" "p0_p1")
8933 (set_attr "stall" "none")])
8936 (define_insn "cgen_intrinsic_cdclipi3_C3"
8937 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8939 (match_operand:DI 1 "general_operand" "x")
8940 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
8942 "CGEN_ENABLE_INSN_P (236)"
8943 "cdclipi3\\t%0,%1,%2"
8944 [(set_attr "may_trap" "no")
8945 (set_attr "latency" "0")
8946 (set_attr "length" "4")
8947 (set_attr "slot" "cop")
8948 (set_attr "slots" "c3")
8949 (set_attr "stall" "none")])
8952 (define_insn "cgen_intrinsic_cdclipi3_P0_P1"
8953 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8955 (match_operand:DI 1 "general_operand" "x")
8956 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
8958 "CGEN_ENABLE_INSN_P (237)"
8959 "cdclipi3\\t%0,%1,%2"
8960 [(set_attr "may_trap" "no")
8961 (set_attr "latency" "0")
8962 (set_attr "length" "4")
8963 (set_attr "slot" "cop")
8964 (set_attr "slots" "p0_p1")
8965 (set_attr "stall" "none")])
8968 (define_insn "cgen_intrinsic_cdclipiu3_C3"
8969 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8971 (match_operand:DI 1 "general_operand" "x")
8972 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
8974 "CGEN_ENABLE_INSN_P (238)"
8975 "cdclipiu3\\t%0,%1,%2"
8976 [(set_attr "may_trap" "no")
8977 (set_attr "latency" "0")
8978 (set_attr "length" "4")
8979 (set_attr "slot" "cop")
8980 (set_attr "slots" "c3")
8981 (set_attr "stall" "none")])
8984 (define_insn "cgen_intrinsic_cdclipiu3_P0_P1"
8985 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
8987 (match_operand:DI 1 "general_operand" "x")
8988 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
8990 "CGEN_ENABLE_INSN_P (239)"
8991 "cdclipiu3\\t%0,%1,%2"
8992 [(set_attr "may_trap" "no")
8993 (set_attr "latency" "0")
8994 (set_attr "length" "4")
8995 (set_attr "slot" "cop")
8996 (set_attr "slots" "p0_p1")
8997 (set_attr "stall" "none")])
9000 (define_insn "cgen_intrinsic_cpclipi3_w_C3"
9001 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9003 (match_operand:DI 1 "general_operand" "x")
9004 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9006 "CGEN_ENABLE_INSN_P (240)"
9007 "cpclipi3.w\\t%0,%1,%2"
9008 [(set_attr "may_trap" "no")
9009 (set_attr "latency" "0")
9010 (set_attr "length" "4")
9011 (set_attr "slot" "cop")
9012 (set_attr "slots" "c3")
9013 (set_attr "stall" "none")])
9016 (define_insn "cgen_intrinsic_cpclipi3_w_P0_P1"
9017 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9019 (match_operand:DI 1 "general_operand" "x")
9020 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9022 "CGEN_ENABLE_INSN_P (241)"
9023 "cpclipi3.w\\t%0,%1,%2"
9024 [(set_attr "may_trap" "no")
9025 (set_attr "latency" "0")
9026 (set_attr "length" "4")
9027 (set_attr "slot" "cop")
9028 (set_attr "slots" "p0_p1")
9029 (set_attr "stall" "none")])
9032 (define_insn "cgen_intrinsic_cpclipiu3_w_C3"
9033 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9035 (match_operand:DI 1 "general_operand" "x")
9036 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9038 "CGEN_ENABLE_INSN_P (242)"
9039 "cpclipiu3.w\\t%0,%1,%2"
9040 [(set_attr "may_trap" "no")
9041 (set_attr "latency" "0")
9042 (set_attr "length" "4")
9043 (set_attr "slot" "cop")
9044 (set_attr "slots" "c3")
9045 (set_attr "stall" "none")])
9048 (define_insn "cgen_intrinsic_cpclipiu3_w_P0_P1"
9049 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9051 (match_operand:DI 1 "general_operand" "x")
9052 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9054 "CGEN_ENABLE_INSN_P (243)"
9055 "cpclipiu3.w\\t%0,%1,%2"
9056 [(set_attr "may_trap" "no")
9057 (set_attr "latency" "0")
9058 (set_attr "length" "4")
9059 (set_attr "slot" "cop")
9060 (set_attr "slots" "p0_p1")
9061 (set_attr "stall" "none")])
9064 (define_insn "cgen_intrinsic_cpslai3_w_C3"
9065 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9066 (unspec_volatile:DI [
9067 (match_operand:DI 1 "general_operand" "x")
9068 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9070 "CGEN_ENABLE_INSN_P (244)"
9071 "cpslai3.w\\t%0,%1,%2"
9072 [(set_attr "may_trap" "no")
9073 (set_attr "latency" "0")
9074 (set_attr "length" "4")
9075 (set_attr "slot" "cop")
9076 (set_attr "slots" "c3")
9077 (set_attr "stall" "none")])
9080 (define_insn "cgen_intrinsic_cpslai3_w_P0_P1"
9081 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9082 (unspec_volatile:DI [
9083 (match_operand:DI 1 "general_operand" "x")
9084 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9086 "CGEN_ENABLE_INSN_P (245)"
9087 "cpslai3.w\\t%0,%1,%2"
9088 [(set_attr "may_trap" "no")
9089 (set_attr "latency" "0")
9090 (set_attr "length" "4")
9091 (set_attr "slot" "cop")
9092 (set_attr "slots" "p0_p1")
9093 (set_attr "stall" "none")])
9096 (define_insn "cgen_intrinsic_cpslai3_h_C3"
9097 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9098 (unspec_volatile:DI [
9099 (match_operand:DI 1 "general_operand" "x")
9100 (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9102 "CGEN_ENABLE_INSN_P (246)"
9103 "cpslai3.h\\t%0,%1,%2"
9104 [(set_attr "may_trap" "no")
9105 (set_attr "latency" "0")
9106 (set_attr "length" "4")
9107 (set_attr "slot" "cop")
9108 (set_attr "slots" "c3")
9109 (set_attr "stall" "none")])
9112 (define_insn "cgen_intrinsic_cpslai3_h_P0_P1"
9113 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9114 (unspec_volatile:DI [
9115 (match_operand:DI 1 "general_operand" "x")
9116 (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9118 "CGEN_ENABLE_INSN_P (247)"
9119 "cpslai3.h\\t%0,%1,%2"
9120 [(set_attr "may_trap" "no")
9121 (set_attr "latency" "0")
9122 (set_attr "length" "4")
9123 (set_attr "slot" "cop")
9124 (set_attr "slots" "p0_p1")
9125 (set_attr "stall" "none")])
9128 (define_insn "cgen_intrinsic_cdslli3_C3"
9129 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9131 (match_operand:DI 1 "general_operand" "x")
9132 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9134 "CGEN_ENABLE_INSN_P (248)"
9135 "cdslli3\\t%0,%1,%2"
9136 [(set_attr "may_trap" "no")
9137 (set_attr "latency" "0")
9138 (set_attr "length" "4")
9139 (set_attr "slot" "cop")
9140 (set_attr "slots" "c3")
9141 (set_attr "stall" "none")])
9144 (define_insn "cgen_intrinsic_cdslli3_P0_P1"
9145 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9147 (match_operand:DI 1 "general_operand" "x")
9148 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9150 "CGEN_ENABLE_INSN_P (249)"
9151 "cdslli3\\t%0,%1,%2"
9152 [(set_attr "may_trap" "no")
9153 (set_attr "latency" "0")
9154 (set_attr "length" "4")
9155 (set_attr "slot" "cop")
9156 (set_attr "slots" "p0_p1")
9157 (set_attr "stall" "none")])
9160 (define_insn "cgen_intrinsic_cpslli3_w_C3"
9161 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9163 (match_operand:DI 1 "general_operand" "x")
9164 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9166 "CGEN_ENABLE_INSN_P (250)"
9167 "cpslli3.w\\t%0,%1,%2"
9168 [(set_attr "may_trap" "no")
9169 (set_attr "latency" "0")
9170 (set_attr "length" "4")
9171 (set_attr "slot" "cop")
9172 (set_attr "slots" "c3")
9173 (set_attr "stall" "none")])
9176 (define_insn "cgen_intrinsic_cpslli3_w_P0_P1"
9177 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9179 (match_operand:DI 1 "general_operand" "x")
9180 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9182 "CGEN_ENABLE_INSN_P (251)"
9183 "cpslli3.w\\t%0,%1,%2"
9184 [(set_attr "may_trap" "no")
9185 (set_attr "latency" "0")
9186 (set_attr "length" "4")
9187 (set_attr "slot" "cop")
9188 (set_attr "slots" "p0_p1")
9189 (set_attr "stall" "none")])
9192 (define_insn "cgen_intrinsic_cpslli3_h_C3"
9193 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9195 (match_operand:DI 1 "general_operand" "x")
9196 (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9198 "CGEN_ENABLE_INSN_P (252)"
9199 "cpslli3.h\\t%0,%1,%2"
9200 [(set_attr "may_trap" "no")
9201 (set_attr "latency" "0")
9202 (set_attr "length" "4")
9203 (set_attr "slot" "cop")
9204 (set_attr "slots" "c3")
9205 (set_attr "stall" "none")])
9208 (define_insn "cgen_intrinsic_cpslli3_h_P0_P1"
9209 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9211 (match_operand:DI 1 "general_operand" "x")
9212 (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9214 "CGEN_ENABLE_INSN_P (253)"
9215 "cpslli3.h\\t%0,%1,%2"
9216 [(set_attr "may_trap" "no")
9217 (set_attr "latency" "0")
9218 (set_attr "length" "4")
9219 (set_attr "slot" "cop")
9220 (set_attr "slots" "p0_p1")
9221 (set_attr "stall" "none")])
9224 (define_insn "cgen_intrinsic_cpslli3_b_C3"
9225 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9227 (match_operand:DI 1 "general_operand" "x")
9228 (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9230 "CGEN_ENABLE_INSN_P (254)"
9231 "cpslli3.b\\t%0,%1,%2"
9232 [(set_attr "may_trap" "no")
9233 (set_attr "latency" "0")
9234 (set_attr "length" "4")
9235 (set_attr "slot" "cop")
9236 (set_attr "slots" "c3")
9237 (set_attr "stall" "none")])
9240 (define_insn "cgen_intrinsic_cpslli3_b_P0_P1"
9241 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9243 (match_operand:DI 1 "general_operand" "x")
9244 (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9246 "CGEN_ENABLE_INSN_P (255)"
9247 "cpslli3.b\\t%0,%1,%2"
9248 [(set_attr "may_trap" "no")
9249 (set_attr "latency" "0")
9250 (set_attr "length" "4")
9251 (set_attr "slot" "cop")
9252 (set_attr "slots" "p0_p1")
9253 (set_attr "stall" "none")])
9256 (define_insn "cgen_intrinsic_cdsrai3_C3"
9257 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9259 (match_operand:DI 1 "general_operand" "x")
9260 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9262 "CGEN_ENABLE_INSN_P (256)"
9263 "cdsrai3\\t%0,%1,%2"
9264 [(set_attr "may_trap" "no")
9265 (set_attr "latency" "0")
9266 (set_attr "length" "4")
9267 (set_attr "slot" "cop")
9268 (set_attr "slots" "c3")
9269 (set_attr "stall" "none")])
9272 (define_insn "cgen_intrinsic_cdsrai3_P0_P1"
9273 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9275 (match_operand:DI 1 "general_operand" "x")
9276 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9278 "CGEN_ENABLE_INSN_P (257)"
9279 "cdsrai3\\t%0,%1,%2"
9280 [(set_attr "may_trap" "no")
9281 (set_attr "latency" "0")
9282 (set_attr "length" "4")
9283 (set_attr "slot" "cop")
9284 (set_attr "slots" "p0_p1")
9285 (set_attr "stall" "none")])
9288 (define_insn "cgen_intrinsic_cpsrai3_w_C3"
9289 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9291 (match_operand:DI 1 "general_operand" "x")
9292 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9294 "CGEN_ENABLE_INSN_P (258)"
9295 "cpsrai3.w\\t%0,%1,%2"
9296 [(set_attr "may_trap" "no")
9297 (set_attr "latency" "0")
9298 (set_attr "length" "4")
9299 (set_attr "slot" "cop")
9300 (set_attr "slots" "c3")
9301 (set_attr "stall" "none")])
9304 (define_insn "cgen_intrinsic_cpsrai3_w_P0_P1"
9305 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9307 (match_operand:DI 1 "general_operand" "x")
9308 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9310 "CGEN_ENABLE_INSN_P (259)"
9311 "cpsrai3.w\\t%0,%1,%2"
9312 [(set_attr "may_trap" "no")
9313 (set_attr "latency" "0")
9314 (set_attr "length" "4")
9315 (set_attr "slot" "cop")
9316 (set_attr "slots" "p0_p1")
9317 (set_attr "stall" "none")])
9320 (define_insn "cgen_intrinsic_cpsrai3_h_C3"
9321 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9323 (match_operand:DI 1 "general_operand" "x")
9324 (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9326 "CGEN_ENABLE_INSN_P (260)"
9327 "cpsrai3.h\\t%0,%1,%2"
9328 [(set_attr "may_trap" "no")
9329 (set_attr "latency" "0")
9330 (set_attr "length" "4")
9331 (set_attr "slot" "cop")
9332 (set_attr "slots" "c3")
9333 (set_attr "stall" "none")])
9336 (define_insn "cgen_intrinsic_cpsrai3_h_P0_P1"
9337 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9339 (match_operand:DI 1 "general_operand" "x")
9340 (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9342 "CGEN_ENABLE_INSN_P (261)"
9343 "cpsrai3.h\\t%0,%1,%2"
9344 [(set_attr "may_trap" "no")
9345 (set_attr "latency" "0")
9346 (set_attr "length" "4")
9347 (set_attr "slot" "cop")
9348 (set_attr "slots" "p0_p1")
9349 (set_attr "stall" "none")])
9352 (define_insn "cgen_intrinsic_cpsrai3_b_C3"
9353 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9355 (match_operand:DI 1 "general_operand" "x")
9356 (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9358 "CGEN_ENABLE_INSN_P (262)"
9359 "cpsrai3.b\\t%0,%1,%2"
9360 [(set_attr "may_trap" "no")
9361 (set_attr "latency" "0")
9362 (set_attr "length" "4")
9363 (set_attr "slot" "cop")
9364 (set_attr "slots" "c3")
9365 (set_attr "stall" "none")])
9368 (define_insn "cgen_intrinsic_cpsrai3_b_P0_P1"
9369 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9371 (match_operand:DI 1 "general_operand" "x")
9372 (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9374 "CGEN_ENABLE_INSN_P (263)"
9375 "cpsrai3.b\\t%0,%1,%2"
9376 [(set_attr "may_trap" "no")
9377 (set_attr "latency" "0")
9378 (set_attr "length" "4")
9379 (set_attr "slot" "cop")
9380 (set_attr "slots" "p0_p1")
9381 (set_attr "stall" "none")])
9384 (define_insn "cgen_intrinsic_cdsrli3_C3"
9385 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9387 (match_operand:DI 1 "general_operand" "x")
9388 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9390 "CGEN_ENABLE_INSN_P (264)"
9391 "cdsrli3\\t%0,%1,%2"
9392 [(set_attr "may_trap" "no")
9393 (set_attr "latency" "0")
9394 (set_attr "length" "4")
9395 (set_attr "slot" "cop")
9396 (set_attr "slots" "c3")
9397 (set_attr "stall" "none")])
9400 (define_insn "cgen_intrinsic_cdsrli3_P0_P1"
9401 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9403 (match_operand:DI 1 "general_operand" "x")
9404 (match_operand:DI 2 "cgen_h_uint_6a1_immediate" "")
9406 "CGEN_ENABLE_INSN_P (265)"
9407 "cdsrli3\\t%0,%1,%2"
9408 [(set_attr "may_trap" "no")
9409 (set_attr "latency" "0")
9410 (set_attr "length" "4")
9411 (set_attr "slot" "cop")
9412 (set_attr "slots" "p0_p1")
9413 (set_attr "stall" "none")])
9416 (define_insn "cgen_intrinsic_cpsrli3_w_C3"
9417 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9419 (match_operand:DI 1 "general_operand" "x")
9420 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9422 "CGEN_ENABLE_INSN_P (266)"
9423 "cpsrli3.w\\t%0,%1,%2"
9424 [(set_attr "may_trap" "no")
9425 (set_attr "latency" "0")
9426 (set_attr "length" "4")
9427 (set_attr "slot" "cop")
9428 (set_attr "slots" "c3")
9429 (set_attr "stall" "none")])
9432 (define_insn "cgen_intrinsic_cpsrli3_w_P0_P1"
9433 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9435 (match_operand:DI 1 "general_operand" "x")
9436 (match_operand:DI 2 "cgen_h_uint_5a1_immediate" "")
9438 "CGEN_ENABLE_INSN_P (267)"
9439 "cpsrli3.w\\t%0,%1,%2"
9440 [(set_attr "may_trap" "no")
9441 (set_attr "latency" "0")
9442 (set_attr "length" "4")
9443 (set_attr "slot" "cop")
9444 (set_attr "slots" "p0_p1")
9445 (set_attr "stall" "none")])
9448 (define_insn "cgen_intrinsic_cpsrli3_h_C3"
9449 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9451 (match_operand:DI 1 "general_operand" "x")
9452 (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9454 "CGEN_ENABLE_INSN_P (268)"
9455 "cpsrli3.h\\t%0,%1,%2"
9456 [(set_attr "may_trap" "no")
9457 (set_attr "latency" "0")
9458 (set_attr "length" "4")
9459 (set_attr "slot" "cop")
9460 (set_attr "slots" "c3")
9461 (set_attr "stall" "none")])
9464 (define_insn "cgen_intrinsic_cpsrli3_h_P0_P1"
9465 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9467 (match_operand:DI 1 "general_operand" "x")
9468 (match_operand:DI 2 "cgen_h_uint_4a1_immediate" "")
9470 "CGEN_ENABLE_INSN_P (269)"
9471 "cpsrli3.h\\t%0,%1,%2"
9472 [(set_attr "may_trap" "no")
9473 (set_attr "latency" "0")
9474 (set_attr "length" "4")
9475 (set_attr "slot" "cop")
9476 (set_attr "slots" "p0_p1")
9477 (set_attr "stall" "none")])
9480 (define_insn "cgen_intrinsic_cpsrli3_b_C3"
9481 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9483 (match_operand:DI 1 "general_operand" "x")
9484 (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9486 "CGEN_ENABLE_INSN_P (270)"
9487 "cpsrli3.b\\t%0,%1,%2"
9488 [(set_attr "may_trap" "no")
9489 (set_attr "latency" "0")
9490 (set_attr "length" "4")
9491 (set_attr "slot" "cop")
9492 (set_attr "slots" "c3")
9493 (set_attr "stall" "none")])
9496 (define_insn "cgen_intrinsic_cpsrli3_b_P0_P1"
9497 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9499 (match_operand:DI 1 "general_operand" "x")
9500 (match_operand:DI 2 "cgen_h_uint_3a1_immediate" "")
9502 "CGEN_ENABLE_INSN_P (271)"
9503 "cpsrli3.b\\t%0,%1,%2"
9504 [(set_attr "may_trap" "no")
9505 (set_attr "latency" "0")
9506 (set_attr "length" "4")
9507 (set_attr "slot" "cop")
9508 (set_attr "slots" "p0_p1")
9509 (set_attr "stall" "none")])
9512 (define_insn "cgen_intrinsic_cpsla3_w_C3"
9513 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9514 (unspec_volatile:DI [
9515 (match_operand:DI 1 "general_operand" "x")
9516 (match_operand:DI 2 "general_operand" "x")
9518 "CGEN_ENABLE_INSN_P (272)"
9519 "cpsla3.w\\t%0,%1,%2"
9520 [(set_attr "may_trap" "no")
9521 (set_attr "latency" "0")
9522 (set_attr "length" "4")
9523 (set_attr "slot" "cop")
9524 (set_attr "slots" "c3")
9525 (set_attr "stall" "none")])
9528 (define_insn "cgen_intrinsic_cpsla3_w_P0_P1"
9529 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9530 (unspec_volatile:DI [
9531 (match_operand:DI 1 "general_operand" "x")
9532 (match_operand:DI 2 "general_operand" "x")
9534 "CGEN_ENABLE_INSN_P (273)"
9535 "cpsla3.w\\t%0,%1,%2"
9536 [(set_attr "may_trap" "no")
9537 (set_attr "latency" "0")
9538 (set_attr "length" "4")
9539 (set_attr "slot" "cop")
9540 (set_attr "slots" "p0_p1")
9541 (set_attr "stall" "none")])
9544 (define_insn "cgen_intrinsic_cpsla3_h_C3"
9545 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9546 (unspec_volatile:DI [
9547 (match_operand:DI 1 "general_operand" "x")
9548 (match_operand:DI 2 "general_operand" "x")
9550 "CGEN_ENABLE_INSN_P (274)"
9551 "cpsla3.h\\t%0,%1,%2"
9552 [(set_attr "may_trap" "no")
9553 (set_attr "latency" "0")
9554 (set_attr "length" "4")
9555 (set_attr "slot" "cop")
9556 (set_attr "slots" "c3")
9557 (set_attr "stall" "none")])
9560 (define_insn "cgen_intrinsic_cpsla3_h_P0_P1"
9561 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9562 (unspec_volatile:DI [
9563 (match_operand:DI 1 "general_operand" "x")
9564 (match_operand:DI 2 "general_operand" "x")
9566 "CGEN_ENABLE_INSN_P (275)"
9567 "cpsla3.h\\t%0,%1,%2"
9568 [(set_attr "may_trap" "no")
9569 (set_attr "latency" "0")
9570 (set_attr "length" "4")
9571 (set_attr "slot" "cop")
9572 (set_attr "slots" "p0_p1")
9573 (set_attr "stall" "none")])
9576 (define_insn "cgen_intrinsic_cdsll3_C3"
9577 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9579 (match_operand:DI 1 "general_operand" "x")
9580 (match_operand:DI 2 "general_operand" "x")
9582 "CGEN_ENABLE_INSN_P (276)"
9584 [(set_attr "may_trap" "no")
9585 (set_attr "latency" "0")
9586 (set_attr "length" "4")
9587 (set_attr "slot" "cop")
9588 (set_attr "slots" "c3")
9589 (set_attr "stall" "none")])
9592 (define_insn "cgen_intrinsic_cdsll3_P0_P1"
9593 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9595 (match_operand:DI 1 "general_operand" "x")
9596 (match_operand:DI 2 "general_operand" "x")
9598 "CGEN_ENABLE_INSN_P (277)"
9600 [(set_attr "may_trap" "no")
9601 (set_attr "latency" "0")
9602 (set_attr "length" "4")
9603 (set_attr "slot" "cop")
9604 (set_attr "slots" "p0_p1")
9605 (set_attr "stall" "none")])
9608 (define_insn "cgen_intrinsic_cpssll3_w_C3"
9609 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9611 (match_operand:DI 1 "general_operand" "x")
9612 (match_operand:DI 2 "general_operand" "x")
9614 "CGEN_ENABLE_INSN_P (278)"
9615 "cpssll3.w\\t%0,%1,%2"
9616 [(set_attr "may_trap" "no")
9617 (set_attr "latency" "0")
9618 (set_attr "length" "4")
9619 (set_attr "slot" "cop")
9620 (set_attr "slots" "c3")
9621 (set_attr "stall" "none")])
9624 (define_insn "cgen_intrinsic_cpssll3_w_P0_P1"
9625 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9627 (match_operand:DI 1 "general_operand" "x")
9628 (match_operand:DI 2 "general_operand" "x")
9630 "CGEN_ENABLE_INSN_P (279)"
9631 "cpssll3.w\\t%0,%1,%2"
9632 [(set_attr "may_trap" "no")
9633 (set_attr "latency" "0")
9634 (set_attr "length" "4")
9635 (set_attr "slot" "cop")
9636 (set_attr "slots" "p0_p1")
9637 (set_attr "stall" "none")])
9640 (define_insn "cgen_intrinsic_cpsll3_w_C3"
9641 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9643 (match_operand:DI 1 "general_operand" "x")
9644 (match_operand:DI 2 "general_operand" "x")
9646 "CGEN_ENABLE_INSN_P (280)"
9647 "cpsll3.w\\t%0,%1,%2"
9648 [(set_attr "may_trap" "no")
9649 (set_attr "latency" "0")
9650 (set_attr "length" "4")
9651 (set_attr "slot" "cop")
9652 (set_attr "slots" "c3")
9653 (set_attr "stall" "none")])
9656 (define_insn "cgen_intrinsic_cpsll3_w_P0_P1"
9657 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9659 (match_operand:DI 1 "general_operand" "x")
9660 (match_operand:DI 2 "general_operand" "x")
9662 "CGEN_ENABLE_INSN_P (281)"
9663 "cpsll3.w\\t%0,%1,%2"
9664 [(set_attr "may_trap" "no")
9665 (set_attr "latency" "0")
9666 (set_attr "length" "4")
9667 (set_attr "slot" "cop")
9668 (set_attr "slots" "p0_p1")
9669 (set_attr "stall" "none")])
9672 (define_insn "cgen_intrinsic_cpssll3_h_C3"
9673 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9675 (match_operand:DI 1 "general_operand" "x")
9676 (match_operand:DI 2 "general_operand" "x")
9678 "CGEN_ENABLE_INSN_P (282)"
9679 "cpssll3.h\\t%0,%1,%2"
9680 [(set_attr "may_trap" "no")
9681 (set_attr "latency" "0")
9682 (set_attr "length" "4")
9683 (set_attr "slot" "cop")
9684 (set_attr "slots" "c3")
9685 (set_attr "stall" "none")])
9688 (define_insn "cgen_intrinsic_cpssll3_h_P0_P1"
9689 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9691 (match_operand:DI 1 "general_operand" "x")
9692 (match_operand:DI 2 "general_operand" "x")
9694 "CGEN_ENABLE_INSN_P (283)"
9695 "cpssll3.h\\t%0,%1,%2"
9696 [(set_attr "may_trap" "no")
9697 (set_attr "latency" "0")
9698 (set_attr "length" "4")
9699 (set_attr "slot" "cop")
9700 (set_attr "slots" "p0_p1")
9701 (set_attr "stall" "none")])
9704 (define_insn "cgen_intrinsic_cpsll3_h_C3"
9705 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9707 (match_operand:DI 1 "general_operand" "x")
9708 (match_operand:DI 2 "general_operand" "x")
9710 "CGEN_ENABLE_INSN_P (284)"
9711 "cpsll3.h\\t%0,%1,%2"
9712 [(set_attr "may_trap" "no")
9713 (set_attr "latency" "0")
9714 (set_attr "length" "4")
9715 (set_attr "slot" "cop")
9716 (set_attr "slots" "c3")
9717 (set_attr "stall" "none")])
9720 (define_insn "cgen_intrinsic_cpsll3_h_P0_P1"
9721 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9723 (match_operand:DI 1 "general_operand" "x")
9724 (match_operand:DI 2 "general_operand" "x")
9726 "CGEN_ENABLE_INSN_P (285)"
9727 "cpsll3.h\\t%0,%1,%2"
9728 [(set_attr "may_trap" "no")
9729 (set_attr "latency" "0")
9730 (set_attr "length" "4")
9731 (set_attr "slot" "cop")
9732 (set_attr "slots" "p0_p1")
9733 (set_attr "stall" "none")])
9736 (define_insn "cgen_intrinsic_cpssll3_b_C3"
9737 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9739 (match_operand:DI 1 "general_operand" "x")
9740 (match_operand:DI 2 "general_operand" "x")
9742 "CGEN_ENABLE_INSN_P (286)"
9743 "cpssll3.b\\t%0,%1,%2"
9744 [(set_attr "may_trap" "no")
9745 (set_attr "latency" "0")
9746 (set_attr "length" "4")
9747 (set_attr "slot" "cop")
9748 (set_attr "slots" "c3")
9749 (set_attr "stall" "none")])
9752 (define_insn "cgen_intrinsic_cpssll3_b_P0_P1"
9753 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9755 (match_operand:DI 1 "general_operand" "x")
9756 (match_operand:DI 2 "general_operand" "x")
9758 "CGEN_ENABLE_INSN_P (287)"
9759 "cpssll3.b\\t%0,%1,%2"
9760 [(set_attr "may_trap" "no")
9761 (set_attr "latency" "0")
9762 (set_attr "length" "4")
9763 (set_attr "slot" "cop")
9764 (set_attr "slots" "p0_p1")
9765 (set_attr "stall" "none")])
9768 (define_insn "cgen_intrinsic_cpsll3_b_C3"
9769 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9771 (match_operand:DI 1 "general_operand" "x")
9772 (match_operand:DI 2 "general_operand" "x")
9774 "CGEN_ENABLE_INSN_P (288)"
9775 "cpsll3.b\\t%0,%1,%2"
9776 [(set_attr "may_trap" "no")
9777 (set_attr "latency" "0")
9778 (set_attr "length" "4")
9779 (set_attr "slot" "cop")
9780 (set_attr "slots" "c3")
9781 (set_attr "stall" "none")])
9784 (define_insn "cgen_intrinsic_cpsll3_b_P0_P1"
9785 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9787 (match_operand:DI 1 "general_operand" "x")
9788 (match_operand:DI 2 "general_operand" "x")
9790 "CGEN_ENABLE_INSN_P (289)"
9791 "cpsll3.b\\t%0,%1,%2"
9792 [(set_attr "may_trap" "no")
9793 (set_attr "latency" "0")
9794 (set_attr "length" "4")
9795 (set_attr "slot" "cop")
9796 (set_attr "slots" "p0_p1")
9797 (set_attr "stall" "none")])
9800 (define_insn "cgen_intrinsic_cdsra3_C3"
9801 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9803 (match_operand:DI 1 "general_operand" "x")
9804 (match_operand:DI 2 "general_operand" "x")
9806 "CGEN_ENABLE_INSN_P (290)"
9808 [(set_attr "may_trap" "no")
9809 (set_attr "latency" "0")
9810 (set_attr "length" "4")
9811 (set_attr "slot" "cop")
9812 (set_attr "slots" "c3")
9813 (set_attr "stall" "none")])
9816 (define_insn "cgen_intrinsic_cdsra3_P0_P1"
9817 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9819 (match_operand:DI 1 "general_operand" "x")
9820 (match_operand:DI 2 "general_operand" "x")
9822 "CGEN_ENABLE_INSN_P (291)"
9824 [(set_attr "may_trap" "no")
9825 (set_attr "latency" "0")
9826 (set_attr "length" "4")
9827 (set_attr "slot" "cop")
9828 (set_attr "slots" "p0_p1")
9829 (set_attr "stall" "none")])
9832 (define_insn "cgen_intrinsic_cpssra3_w_C3"
9833 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9835 (match_operand:DI 1 "general_operand" "x")
9836 (match_operand:DI 2 "general_operand" "x")
9838 "CGEN_ENABLE_INSN_P (292)"
9839 "cpssra3.w\\t%0,%1,%2"
9840 [(set_attr "may_trap" "no")
9841 (set_attr "latency" "0")
9842 (set_attr "length" "4")
9843 (set_attr "slot" "cop")
9844 (set_attr "slots" "c3")
9845 (set_attr "stall" "none")])
9848 (define_insn "cgen_intrinsic_cpssra3_w_P0_P1"
9849 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9851 (match_operand:DI 1 "general_operand" "x")
9852 (match_operand:DI 2 "general_operand" "x")
9854 "CGEN_ENABLE_INSN_P (293)"
9855 "cpssra3.w\\t%0,%1,%2"
9856 [(set_attr "may_trap" "no")
9857 (set_attr "latency" "0")
9858 (set_attr "length" "4")
9859 (set_attr "slot" "cop")
9860 (set_attr "slots" "p0_p1")
9861 (set_attr "stall" "none")])
9864 (define_insn "cgen_intrinsic_cpsra3_w_C3"
9865 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9867 (match_operand:DI 1 "general_operand" "x")
9868 (match_operand:DI 2 "general_operand" "x")
9870 "CGEN_ENABLE_INSN_P (294)"
9871 "cpsra3.w\\t%0,%1,%2"
9872 [(set_attr "may_trap" "no")
9873 (set_attr "latency" "0")
9874 (set_attr "length" "4")
9875 (set_attr "slot" "cop")
9876 (set_attr "slots" "c3")
9877 (set_attr "stall" "none")])
9880 (define_insn "cgen_intrinsic_cpsra3_w_P0_P1"
9881 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9883 (match_operand:DI 1 "general_operand" "x")
9884 (match_operand:DI 2 "general_operand" "x")
9886 "CGEN_ENABLE_INSN_P (295)"
9887 "cpsra3.w\\t%0,%1,%2"
9888 [(set_attr "may_trap" "no")
9889 (set_attr "latency" "0")
9890 (set_attr "length" "4")
9891 (set_attr "slot" "cop")
9892 (set_attr "slots" "p0_p1")
9893 (set_attr "stall" "none")])
9896 (define_insn "cgen_intrinsic_cpssra3_h_C3"
9897 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9899 (match_operand:DI 1 "general_operand" "x")
9900 (match_operand:DI 2 "general_operand" "x")
9902 "CGEN_ENABLE_INSN_P (296)"
9903 "cpssra3.h\\t%0,%1,%2"
9904 [(set_attr "may_trap" "no")
9905 (set_attr "latency" "0")
9906 (set_attr "length" "4")
9907 (set_attr "slot" "cop")
9908 (set_attr "slots" "c3")
9909 (set_attr "stall" "none")])
9912 (define_insn "cgen_intrinsic_cpssra3_h_P0_P1"
9913 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9915 (match_operand:DI 1 "general_operand" "x")
9916 (match_operand:DI 2 "general_operand" "x")
9918 "CGEN_ENABLE_INSN_P (297)"
9919 "cpssra3.h\\t%0,%1,%2"
9920 [(set_attr "may_trap" "no")
9921 (set_attr "latency" "0")
9922 (set_attr "length" "4")
9923 (set_attr "slot" "cop")
9924 (set_attr "slots" "p0_p1")
9925 (set_attr "stall" "none")])
9928 (define_insn "cgen_intrinsic_cpsra3_h_C3"
9929 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9931 (match_operand:DI 1 "general_operand" "x")
9932 (match_operand:DI 2 "general_operand" "x")
9934 "CGEN_ENABLE_INSN_P (298)"
9935 "cpsra3.h\\t%0,%1,%2"
9936 [(set_attr "may_trap" "no")
9937 (set_attr "latency" "0")
9938 (set_attr "length" "4")
9939 (set_attr "slot" "cop")
9940 (set_attr "slots" "c3")
9941 (set_attr "stall" "none")])
9944 (define_insn "cgen_intrinsic_cpsra3_h_P0_P1"
9945 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9947 (match_operand:DI 1 "general_operand" "x")
9948 (match_operand:DI 2 "general_operand" "x")
9950 "CGEN_ENABLE_INSN_P (299)"
9951 "cpsra3.h\\t%0,%1,%2"
9952 [(set_attr "may_trap" "no")
9953 (set_attr "latency" "0")
9954 (set_attr "length" "4")
9955 (set_attr "slot" "cop")
9956 (set_attr "slots" "p0_p1")
9957 (set_attr "stall" "none")])
9960 (define_insn "cgen_intrinsic_cpssra3_b_C3"
9961 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9963 (match_operand:DI 1 "general_operand" "x")
9964 (match_operand:DI 2 "general_operand" "x")
9966 "CGEN_ENABLE_INSN_P (300)"
9967 "cpssra3.b\\t%0,%1,%2"
9968 [(set_attr "may_trap" "no")
9969 (set_attr "latency" "0")
9970 (set_attr "length" "4")
9971 (set_attr "slot" "cop")
9972 (set_attr "slots" "c3")
9973 (set_attr "stall" "none")])
9976 (define_insn "cgen_intrinsic_cpssra3_b_P0_P1"
9977 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9979 (match_operand:DI 1 "general_operand" "x")
9980 (match_operand:DI 2 "general_operand" "x")
9982 "CGEN_ENABLE_INSN_P (301)"
9983 "cpssra3.b\\t%0,%1,%2"
9984 [(set_attr "may_trap" "no")
9985 (set_attr "latency" "0")
9986 (set_attr "length" "4")
9987 (set_attr "slot" "cop")
9988 (set_attr "slots" "p0_p1")
9989 (set_attr "stall" "none")])
9992 (define_insn "cgen_intrinsic_cpsra3_b_C3"
9993 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
9995 (match_operand:DI 1 "general_operand" "x")
9996 (match_operand:DI 2 "general_operand" "x")
9998 "CGEN_ENABLE_INSN_P (302)"
9999 "cpsra3.b\\t%0,%1,%2"
10000 [(set_attr "may_trap" "no")
10001 (set_attr "latency" "0")
10002 (set_attr "length" "4")
10003 (set_attr "slot" "cop")
10004 (set_attr "slots" "c3")
10005 (set_attr "stall" "none")])
10008 (define_insn "cgen_intrinsic_cpsra3_b_P0_P1"
10009 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10011 (match_operand:DI 1 "general_operand" "x")
10012 (match_operand:DI 2 "general_operand" "x")
10014 "CGEN_ENABLE_INSN_P (303)"
10015 "cpsra3.b\\t%0,%1,%2"
10016 [(set_attr "may_trap" "no")
10017 (set_attr "latency" "0")
10018 (set_attr "length" "4")
10019 (set_attr "slot" "cop")
10020 (set_attr "slots" "p0_p1")
10021 (set_attr "stall" "none")])
10024 (define_insn "cgen_intrinsic_cdsrl3_C3"
10025 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10027 (match_operand:DI 1 "general_operand" "x")
10028 (match_operand:DI 2 "general_operand" "x")
10030 "CGEN_ENABLE_INSN_P (304)"
10031 "cdsrl3\\t%0,%1,%2"
10032 [(set_attr "may_trap" "no")
10033 (set_attr "latency" "0")
10034 (set_attr "length" "4")
10035 (set_attr "slot" "cop")
10036 (set_attr "slots" "c3")
10037 (set_attr "stall" "none")])
10040 (define_insn "cgen_intrinsic_cdsrl3_P0_P1"
10041 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10043 (match_operand:DI 1 "general_operand" "x")
10044 (match_operand:DI 2 "general_operand" "x")
10046 "CGEN_ENABLE_INSN_P (305)"
10047 "cdsrl3\\t%0,%1,%2"
10048 [(set_attr "may_trap" "no")
10049 (set_attr "latency" "0")
10050 (set_attr "length" "4")
10051 (set_attr "slot" "cop")
10052 (set_attr "slots" "p0_p1")
10053 (set_attr "stall" "none")])
10056 (define_insn "cgen_intrinsic_cpssrl3_w_C3"
10057 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10059 (match_operand:DI 1 "general_operand" "x")
10060 (match_operand:DI 2 "general_operand" "x")
10062 "CGEN_ENABLE_INSN_P (306)"
10063 "cpssrl3.w\\t%0,%1,%2"
10064 [(set_attr "may_trap" "no")
10065 (set_attr "latency" "0")
10066 (set_attr "length" "4")
10067 (set_attr "slot" "cop")
10068 (set_attr "slots" "c3")
10069 (set_attr "stall" "none")])
10072 (define_insn "cgen_intrinsic_cpssrl3_w_P0_P1"
10073 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10075 (match_operand:DI 1 "general_operand" "x")
10076 (match_operand:DI 2 "general_operand" "x")
10078 "CGEN_ENABLE_INSN_P (307)"
10079 "cpssrl3.w\\t%0,%1,%2"
10080 [(set_attr "may_trap" "no")
10081 (set_attr "latency" "0")
10082 (set_attr "length" "4")
10083 (set_attr "slot" "cop")
10084 (set_attr "slots" "p0_p1")
10085 (set_attr "stall" "none")])
10088 (define_insn "cgen_intrinsic_cpsrl3_w_C3"
10089 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10091 (match_operand:DI 1 "general_operand" "x")
10092 (match_operand:DI 2 "general_operand" "x")
10094 "CGEN_ENABLE_INSN_P (308)"
10095 "cpsrl3.w\\t%0,%1,%2"
10096 [(set_attr "may_trap" "no")
10097 (set_attr "latency" "0")
10098 (set_attr "length" "4")
10099 (set_attr "slot" "cop")
10100 (set_attr "slots" "c3")
10101 (set_attr "stall" "none")])
10104 (define_insn "cgen_intrinsic_cpsrl3_w_P0_P1"
10105 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10107 (match_operand:DI 1 "general_operand" "x")
10108 (match_operand:DI 2 "general_operand" "x")
10110 "CGEN_ENABLE_INSN_P (309)"
10111 "cpsrl3.w\\t%0,%1,%2"
10112 [(set_attr "may_trap" "no")
10113 (set_attr "latency" "0")
10114 (set_attr "length" "4")
10115 (set_attr "slot" "cop")
10116 (set_attr "slots" "p0_p1")
10117 (set_attr "stall" "none")])
10120 (define_insn "cgen_intrinsic_cpssrl3_h_C3"
10121 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10123 (match_operand:DI 1 "general_operand" "x")
10124 (match_operand:DI 2 "general_operand" "x")
10126 "CGEN_ENABLE_INSN_P (310)"
10127 "cpssrl3.h\\t%0,%1,%2"
10128 [(set_attr "may_trap" "no")
10129 (set_attr "latency" "0")
10130 (set_attr "length" "4")
10131 (set_attr "slot" "cop")
10132 (set_attr "slots" "c3")
10133 (set_attr "stall" "none")])
10136 (define_insn "cgen_intrinsic_cpssrl3_h_P0_P1"
10137 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10139 (match_operand:DI 1 "general_operand" "x")
10140 (match_operand:DI 2 "general_operand" "x")
10142 "CGEN_ENABLE_INSN_P (311)"
10143 "cpssrl3.h\\t%0,%1,%2"
10144 [(set_attr "may_trap" "no")
10145 (set_attr "latency" "0")
10146 (set_attr "length" "4")
10147 (set_attr "slot" "cop")
10148 (set_attr "slots" "p0_p1")
10149 (set_attr "stall" "none")])
10152 (define_insn "cgen_intrinsic_cpsrl3_h_C3"
10153 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10155 (match_operand:DI 1 "general_operand" "x")
10156 (match_operand:DI 2 "general_operand" "x")
10158 "CGEN_ENABLE_INSN_P (312)"
10159 "cpsrl3.h\\t%0,%1,%2"
10160 [(set_attr "may_trap" "no")
10161 (set_attr "latency" "0")
10162 (set_attr "length" "4")
10163 (set_attr "slot" "cop")
10164 (set_attr "slots" "c3")
10165 (set_attr "stall" "none")])
10168 (define_insn "cgen_intrinsic_cpsrl3_h_P0_P1"
10169 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10171 (match_operand:DI 1 "general_operand" "x")
10172 (match_operand:DI 2 "general_operand" "x")
10174 "CGEN_ENABLE_INSN_P (313)"
10175 "cpsrl3.h\\t%0,%1,%2"
10176 [(set_attr "may_trap" "no")
10177 (set_attr "latency" "0")
10178 (set_attr "length" "4")
10179 (set_attr "slot" "cop")
10180 (set_attr "slots" "p0_p1")
10181 (set_attr "stall" "none")])
10184 (define_insn "cgen_intrinsic_cpssrl3_b_C3"
10185 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10187 (match_operand:DI 1 "general_operand" "x")
10188 (match_operand:DI 2 "general_operand" "x")
10190 "CGEN_ENABLE_INSN_P (314)"
10191 "cpssrl3.b\\t%0,%1,%2"
10192 [(set_attr "may_trap" "no")
10193 (set_attr "latency" "0")
10194 (set_attr "length" "4")
10195 (set_attr "slot" "cop")
10196 (set_attr "slots" "c3")
10197 (set_attr "stall" "none")])
10200 (define_insn "cgen_intrinsic_cpssrl3_b_P0_P1"
10201 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10203 (match_operand:DI 1 "general_operand" "x")
10204 (match_operand:DI 2 "general_operand" "x")
10206 "CGEN_ENABLE_INSN_P (315)"
10207 "cpssrl3.b\\t%0,%1,%2"
10208 [(set_attr "may_trap" "no")
10209 (set_attr "latency" "0")
10210 (set_attr "length" "4")
10211 (set_attr "slot" "cop")
10212 (set_attr "slots" "p0_p1")
10213 (set_attr "stall" "none")])
10216 (define_insn "cgen_intrinsic_cpsrl3_b_C3"
10217 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10219 (match_operand:DI 1 "general_operand" "x")
10220 (match_operand:DI 2 "general_operand" "x")
10222 "CGEN_ENABLE_INSN_P (316)"
10223 "cpsrl3.b\\t%0,%1,%2"
10224 [(set_attr "may_trap" "no")
10225 (set_attr "latency" "0")
10226 (set_attr "length" "4")
10227 (set_attr "slot" "cop")
10228 (set_attr "slots" "c3")
10229 (set_attr "stall" "none")])
10232 (define_insn "cgen_intrinsic_cpsrl3_b_P0_P1"
10233 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10235 (match_operand:DI 1 "general_operand" "x")
10236 (match_operand:DI 2 "general_operand" "x")
10238 "CGEN_ENABLE_INSN_P (317)"
10239 "cpsrl3.b\\t%0,%1,%2"
10240 [(set_attr "may_trap" "no")
10241 (set_attr "latency" "0")
10242 (set_attr "length" "4")
10243 (set_attr "slot" "cop")
10244 (set_attr "slots" "p0_p1")
10245 (set_attr "stall" "none")])
10248 (define_insn "cgen_intrinsic_cpmin3_w_C3"
10249 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10251 (match_operand:DI 1 "general_operand" "x")
10252 (match_operand:DI 2 "general_operand" "x")
10254 "CGEN_ENABLE_INSN_P (318)"
10255 "cpmin3.w\\t%0,%1,%2"
10256 [(set_attr "may_trap" "no")
10257 (set_attr "latency" "0")
10258 (set_attr "length" "4")
10259 (set_attr "slot" "cop")
10260 (set_attr "slots" "c3")
10261 (set_attr "stall" "none")])
10264 (define_insn "cgen_intrinsic_cpmin3_w_P0_P1"
10265 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10267 (match_operand:DI 1 "general_operand" "x")
10268 (match_operand:DI 2 "general_operand" "x")
10270 "CGEN_ENABLE_INSN_P (319)"
10271 "cpmin3.w\\t%0,%1,%2"
10272 [(set_attr "may_trap" "no")
10273 (set_attr "latency" "0")
10274 (set_attr "length" "4")
10275 (set_attr "slot" "cop")
10276 (set_attr "slots" "p0_p1")
10277 (set_attr "stall" "none")])
10280 (define_insn "cgen_intrinsic_cpminu3_w_C3"
10281 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10283 (match_operand:DI 1 "general_operand" "x")
10284 (match_operand:DI 2 "general_operand" "x")
10286 "CGEN_ENABLE_INSN_P (320)"
10287 "cpminu3.w\\t%0,%1,%2"
10288 [(set_attr "may_trap" "no")
10289 (set_attr "latency" "0")
10290 (set_attr "length" "4")
10291 (set_attr "slot" "cop")
10292 (set_attr "slots" "c3")
10293 (set_attr "stall" "none")])
10296 (define_insn "cgen_intrinsic_cpminu3_w_P0_P1"
10297 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10299 (match_operand:DI 1 "general_operand" "x")
10300 (match_operand:DI 2 "general_operand" "x")
10302 "CGEN_ENABLE_INSN_P (321)"
10303 "cpminu3.w\\t%0,%1,%2"
10304 [(set_attr "may_trap" "no")
10305 (set_attr "latency" "0")
10306 (set_attr "length" "4")
10307 (set_attr "slot" "cop")
10308 (set_attr "slots" "p0_p1")
10309 (set_attr "stall" "none")])
10312 (define_insn "cgen_intrinsic_cpmin3_h_C3"
10313 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10315 (match_operand:DI 1 "general_operand" "x")
10316 (match_operand:DI 2 "general_operand" "x")
10318 "CGEN_ENABLE_INSN_P (322)"
10319 "cpmin3.h\\t%0,%1,%2"
10320 [(set_attr "may_trap" "no")
10321 (set_attr "latency" "0")
10322 (set_attr "length" "4")
10323 (set_attr "slot" "cop")
10324 (set_attr "slots" "c3")
10325 (set_attr "stall" "none")])
10328 (define_insn "cgen_intrinsic_cpmin3_h_P0_P1"
10329 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10331 (match_operand:DI 1 "general_operand" "x")
10332 (match_operand:DI 2 "general_operand" "x")
10334 "CGEN_ENABLE_INSN_P (323)"
10335 "cpmin3.h\\t%0,%1,%2"
10336 [(set_attr "may_trap" "no")
10337 (set_attr "latency" "0")
10338 (set_attr "length" "4")
10339 (set_attr "slot" "cop")
10340 (set_attr "slots" "p0_p1")
10341 (set_attr "stall" "none")])
10344 (define_insn "cgen_intrinsic_cpmin3_b_C3"
10345 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10347 (match_operand:DI 1 "general_operand" "x")
10348 (match_operand:DI 2 "general_operand" "x")
10350 "CGEN_ENABLE_INSN_P (324)"
10351 "cpmin3.b\\t%0,%1,%2"
10352 [(set_attr "may_trap" "no")
10353 (set_attr "latency" "0")
10354 (set_attr "length" "4")
10355 (set_attr "slot" "cop")
10356 (set_attr "slots" "c3")
10357 (set_attr "stall" "none")])
10360 (define_insn "cgen_intrinsic_cpmin3_b_P0_P1"
10361 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10363 (match_operand:DI 1 "general_operand" "x")
10364 (match_operand:DI 2 "general_operand" "x")
10366 "CGEN_ENABLE_INSN_P (325)"
10367 "cpmin3.b\\t%0,%1,%2"
10368 [(set_attr "may_trap" "no")
10369 (set_attr "latency" "0")
10370 (set_attr "length" "4")
10371 (set_attr "slot" "cop")
10372 (set_attr "slots" "p0_p1")
10373 (set_attr "stall" "none")])
10376 (define_insn "cgen_intrinsic_cpminu3_b_C3"
10377 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10379 (match_operand:DI 1 "general_operand" "x")
10380 (match_operand:DI 2 "general_operand" "x")
10382 "CGEN_ENABLE_INSN_P (326)"
10383 "cpminu3.b\\t%0,%1,%2"
10384 [(set_attr "may_trap" "no")
10385 (set_attr "latency" "0")
10386 (set_attr "length" "4")
10387 (set_attr "slot" "cop")
10388 (set_attr "slots" "c3")
10389 (set_attr "stall" "none")])
10392 (define_insn "cgen_intrinsic_cpminu3_b_P0_P1"
10393 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10395 (match_operand:DI 1 "general_operand" "x")
10396 (match_operand:DI 2 "general_operand" "x")
10398 "CGEN_ENABLE_INSN_P (327)"
10399 "cpminu3.b\\t%0,%1,%2"
10400 [(set_attr "may_trap" "no")
10401 (set_attr "latency" "0")
10402 (set_attr "length" "4")
10403 (set_attr "slot" "cop")
10404 (set_attr "slots" "p0_p1")
10405 (set_attr "stall" "none")])
10408 (define_insn "cgen_intrinsic_cpmax3_w_C3"
10409 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10411 (match_operand:DI 1 "general_operand" "x")
10412 (match_operand:DI 2 "general_operand" "x")
10414 "CGEN_ENABLE_INSN_P (328)"
10415 "cpmax3.w\\t%0,%1,%2"
10416 [(set_attr "may_trap" "no")
10417 (set_attr "latency" "0")
10418 (set_attr "length" "4")
10419 (set_attr "slot" "cop")
10420 (set_attr "slots" "c3")
10421 (set_attr "stall" "none")])
10424 (define_insn "cgen_intrinsic_cpmax3_w_P0_P1"
10425 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10427 (match_operand:DI 1 "general_operand" "x")
10428 (match_operand:DI 2 "general_operand" "x")
10430 "CGEN_ENABLE_INSN_P (329)"
10431 "cpmax3.w\\t%0,%1,%2"
10432 [(set_attr "may_trap" "no")
10433 (set_attr "latency" "0")
10434 (set_attr "length" "4")
10435 (set_attr "slot" "cop")
10436 (set_attr "slots" "p0_p1")
10437 (set_attr "stall" "none")])
10440 (define_insn "cgen_intrinsic_cpmaxu3_w_C3"
10441 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10443 (match_operand:DI 1 "general_operand" "x")
10444 (match_operand:DI 2 "general_operand" "x")
10446 "CGEN_ENABLE_INSN_P (330)"
10447 "cpmaxu3.w\\t%0,%1,%2"
10448 [(set_attr "may_trap" "no")
10449 (set_attr "latency" "0")
10450 (set_attr "length" "4")
10451 (set_attr "slot" "cop")
10452 (set_attr "slots" "c3")
10453 (set_attr "stall" "none")])
10456 (define_insn "cgen_intrinsic_cpmaxu3_w_P0_P1"
10457 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10459 (match_operand:DI 1 "general_operand" "x")
10460 (match_operand:DI 2 "general_operand" "x")
10462 "CGEN_ENABLE_INSN_P (331)"
10463 "cpmaxu3.w\\t%0,%1,%2"
10464 [(set_attr "may_trap" "no")
10465 (set_attr "latency" "0")
10466 (set_attr "length" "4")
10467 (set_attr "slot" "cop")
10468 (set_attr "slots" "p0_p1")
10469 (set_attr "stall" "none")])
10472 (define_insn "cgen_intrinsic_cpmax3_h_C3"
10473 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10475 (match_operand:DI 1 "general_operand" "x")
10476 (match_operand:DI 2 "general_operand" "x")
10478 "CGEN_ENABLE_INSN_P (332)"
10479 "cpmax3.h\\t%0,%1,%2"
10480 [(set_attr "may_trap" "no")
10481 (set_attr "latency" "0")
10482 (set_attr "length" "4")
10483 (set_attr "slot" "cop")
10484 (set_attr "slots" "c3")
10485 (set_attr "stall" "none")])
10488 (define_insn "cgen_intrinsic_cpmax3_h_P0_P1"
10489 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10491 (match_operand:DI 1 "general_operand" "x")
10492 (match_operand:DI 2 "general_operand" "x")
10494 "CGEN_ENABLE_INSN_P (333)"
10495 "cpmax3.h\\t%0,%1,%2"
10496 [(set_attr "may_trap" "no")
10497 (set_attr "latency" "0")
10498 (set_attr "length" "4")
10499 (set_attr "slot" "cop")
10500 (set_attr "slots" "p0_p1")
10501 (set_attr "stall" "none")])
10504 (define_insn "cgen_intrinsic_cpmax3_b_C3"
10505 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10507 (match_operand:DI 1 "general_operand" "x")
10508 (match_operand:DI 2 "general_operand" "x")
10510 "CGEN_ENABLE_INSN_P (334)"
10511 "cpmax3.b\\t%0,%1,%2"
10512 [(set_attr "may_trap" "no")
10513 (set_attr "latency" "0")
10514 (set_attr "length" "4")
10515 (set_attr "slot" "cop")
10516 (set_attr "slots" "c3")
10517 (set_attr "stall" "none")])
10520 (define_insn "cgen_intrinsic_cpmax3_b_P0_P1"
10521 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10523 (match_operand:DI 1 "general_operand" "x")
10524 (match_operand:DI 2 "general_operand" "x")
10526 "CGEN_ENABLE_INSN_P (335)"
10527 "cpmax3.b\\t%0,%1,%2"
10528 [(set_attr "may_trap" "no")
10529 (set_attr "latency" "0")
10530 (set_attr "length" "4")
10531 (set_attr "slot" "cop")
10532 (set_attr "slots" "p0_p1")
10533 (set_attr "stall" "none")])
10536 (define_insn "cgen_intrinsic_cpmaxu3_b_C3"
10537 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10539 (match_operand:DI 1 "general_operand" "x")
10540 (match_operand:DI 2 "general_operand" "x")
10542 "CGEN_ENABLE_INSN_P (336)"
10543 "cpmaxu3.b\\t%0,%1,%2"
10544 [(set_attr "may_trap" "no")
10545 (set_attr "latency" "0")
10546 (set_attr "length" "4")
10547 (set_attr "slot" "cop")
10548 (set_attr "slots" "c3")
10549 (set_attr "stall" "none")])
10552 (define_insn "cgen_intrinsic_cpmaxu3_b_P0_P1"
10553 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10555 (match_operand:DI 1 "general_operand" "x")
10556 (match_operand:DI 2 "general_operand" "x")
10558 "CGEN_ENABLE_INSN_P (337)"
10559 "cpmaxu3.b\\t%0,%1,%2"
10560 [(set_attr "may_trap" "no")
10561 (set_attr "latency" "0")
10562 (set_attr "length" "4")
10563 (set_attr "slot" "cop")
10564 (set_attr "slots" "p0_p1")
10565 (set_attr "stall" "none")])
10568 (define_insn "cgen_intrinsic_cppack_h_C3"
10569 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10571 (match_operand:DI 1 "general_operand" "x")
10572 (match_operand:DI 2 "general_operand" "x")
10574 "CGEN_ENABLE_INSN_P (338)"
10575 "cppack.h\\t%0,%1,%2"
10576 [(set_attr "may_trap" "no")
10577 (set_attr "latency" "0")
10578 (set_attr "length" "4")
10579 (set_attr "slot" "cop")
10580 (set_attr "slots" "c3")
10581 (set_attr "stall" "none")])
10584 (define_insn "cgen_intrinsic_cppack_h_P0_P1"
10585 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10587 (match_operand:DI 1 "general_operand" "x")
10588 (match_operand:DI 2 "general_operand" "x")
10590 "CGEN_ENABLE_INSN_P (339)"
10591 "cppack.h\\t%0,%1,%2"
10592 [(set_attr "may_trap" "no")
10593 (set_attr "latency" "0")
10594 (set_attr "length" "4")
10595 (set_attr "slot" "cop")
10596 (set_attr "slots" "p0_p1")
10597 (set_attr "stall" "none")])
10600 (define_insn "cgen_intrinsic_cppack_b_C3"
10601 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10603 (match_operand:DI 1 "general_operand" "x")
10604 (match_operand:DI 2 "general_operand" "x")
10606 "CGEN_ENABLE_INSN_P (340)"
10607 "cppack.b\\t%0,%1,%2"
10608 [(set_attr "may_trap" "no")
10609 (set_attr "latency" "0")
10610 (set_attr "length" "4")
10611 (set_attr "slot" "cop")
10612 (set_attr "slots" "c3")
10613 (set_attr "stall" "none")])
10616 (define_insn "cgen_intrinsic_cppack_b_P0_P1"
10617 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10619 (match_operand:DI 1 "general_operand" "x")
10620 (match_operand:DI 2 "general_operand" "x")
10622 "CGEN_ENABLE_INSN_P (341)"
10623 "cppack.b\\t%0,%1,%2"
10624 [(set_attr "may_trap" "no")
10625 (set_attr "latency" "0")
10626 (set_attr "length" "4")
10627 (set_attr "slot" "cop")
10628 (set_attr "slots" "p0_p1")
10629 (set_attr "stall" "none")])
10632 (define_insn "cgen_intrinsic_cppacku_b_C3"
10633 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10635 (match_operand:DI 1 "general_operand" "x")
10636 (match_operand:DI 2 "general_operand" "x")
10638 "CGEN_ENABLE_INSN_P (342)"
10639 "cppacku.b\\t%0,%1,%2"
10640 [(set_attr "may_trap" "no")
10641 (set_attr "latency" "0")
10642 (set_attr "length" "4")
10643 (set_attr "slot" "cop")
10644 (set_attr "slots" "c3")
10645 (set_attr "stall" "none")])
10648 (define_insn "cgen_intrinsic_cppacku_b_P0_P1"
10649 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10651 (match_operand:DI 1 "general_operand" "x")
10652 (match_operand:DI 2 "general_operand" "x")
10654 "CGEN_ENABLE_INSN_P (343)"
10655 "cppacku.b\\t%0,%1,%2"
10656 [(set_attr "may_trap" "no")
10657 (set_attr "latency" "0")
10658 (set_attr "length" "4")
10659 (set_attr "slot" "cop")
10660 (set_attr "slots" "p0_p1")
10661 (set_attr "stall" "none")])
10664 (define_insn "cgen_intrinsic_cpxor3_C3"
10665 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10667 (match_operand:DI 1 "general_operand" "x")
10668 (match_operand:DI 2 "general_operand" "x")
10670 "CGEN_ENABLE_INSN_P (344)"
10671 "cpxor3\\t%0,%1,%2"
10672 [(set_attr "may_trap" "no")
10673 (set_attr "latency" "0")
10674 (set_attr "length" "4")
10675 (set_attr "slot" "cop")
10676 (set_attr "slots" "c3")
10677 (set_attr "stall" "none")])
10680 (define_insn "cgen_intrinsic_cpxor3_P0_P1"
10681 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10683 (match_operand:DI 1 "general_operand" "x")
10684 (match_operand:DI 2 "general_operand" "x")
10686 "CGEN_ENABLE_INSN_P (345)"
10687 "cpxor3\\t%0,%1,%2"
10688 [(set_attr "may_trap" "no")
10689 (set_attr "latency" "0")
10690 (set_attr "length" "4")
10691 (set_attr "slot" "cop")
10692 (set_attr "slots" "p0_p1")
10693 (set_attr "stall" "none")])
10696 (define_insn "cgen_intrinsic_cpnor3_C3"
10697 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10699 (match_operand:DI 1 "general_operand" "x")
10700 (match_operand:DI 2 "general_operand" "x")
10702 "CGEN_ENABLE_INSN_P (346)"
10703 "cpnor3\\t%0,%1,%2"
10704 [(set_attr "may_trap" "no")
10705 (set_attr "latency" "0")
10706 (set_attr "length" "4")
10707 (set_attr "slot" "cop")
10708 (set_attr "slots" "c3")
10709 (set_attr "stall" "none")])
10712 (define_insn "cgen_intrinsic_cpnor3_P0_P1"
10713 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10715 (match_operand:DI 1 "general_operand" "x")
10716 (match_operand:DI 2 "general_operand" "x")
10718 "CGEN_ENABLE_INSN_P (347)"
10719 "cpnor3\\t%0,%1,%2"
10720 [(set_attr "may_trap" "no")
10721 (set_attr "latency" "0")
10722 (set_attr "length" "4")
10723 (set_attr "slot" "cop")
10724 (set_attr "slots" "p0_p1")
10725 (set_attr "stall" "none")])
10728 (define_insn "cgen_intrinsic_cpor3_C3"
10729 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10731 (match_operand:DI 1 "general_operand" "x")
10732 (match_operand:DI 2 "general_operand" "x")
10734 "CGEN_ENABLE_INSN_P (348)"
10736 [(set_attr "may_trap" "no")
10737 (set_attr "latency" "0")
10738 (set_attr "length" "4")
10739 (set_attr "slot" "cop")
10740 (set_attr "slots" "c3")
10741 (set_attr "stall" "none")])
10744 (define_insn "cgen_intrinsic_cpor3_P0_P1"
10745 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10747 (match_operand:DI 1 "general_operand" "x")
10748 (match_operand:DI 2 "general_operand" "x")
10750 "CGEN_ENABLE_INSN_P (349)"
10752 [(set_attr "may_trap" "no")
10753 (set_attr "latency" "0")
10754 (set_attr "length" "4")
10755 (set_attr "slot" "cop")
10756 (set_attr "slots" "p0_p1")
10757 (set_attr "stall" "none")])
10760 (define_insn "cgen_intrinsic_cpand3_C3"
10761 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10763 (match_operand:DI 1 "general_operand" "x")
10764 (match_operand:DI 2 "general_operand" "x")
10766 "CGEN_ENABLE_INSN_P (350)"
10767 "cpand3\\t%0,%1,%2"
10768 [(set_attr "may_trap" "no")
10769 (set_attr "latency" "0")
10770 (set_attr "length" "4")
10771 (set_attr "slot" "cop")
10772 (set_attr "slots" "c3")
10773 (set_attr "stall" "none")])
10776 (define_insn "cgen_intrinsic_cpand3_P0_P1"
10777 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10779 (match_operand:DI 1 "general_operand" "x")
10780 (match_operand:DI 2 "general_operand" "x")
10782 "CGEN_ENABLE_INSN_P (351)"
10783 "cpand3\\t%0,%1,%2"
10784 [(set_attr "may_trap" "no")
10785 (set_attr "latency" "0")
10786 (set_attr "length" "4")
10787 (set_attr "slot" "cop")
10788 (set_attr "slots" "p0_p1")
10789 (set_attr "stall" "none")])
10792 (define_insn "cgen_intrinsic_cpabs3_h_C3"
10793 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10795 (match_operand:DI 1 "general_operand" "x")
10796 (match_operand:DI 2 "general_operand" "x")
10798 "CGEN_ENABLE_INSN_P (352)"
10799 "cpabs3.h\\t%0,%1,%2"
10800 [(set_attr "may_trap" "no")
10801 (set_attr "latency" "0")
10802 (set_attr "length" "4")
10803 (set_attr "slot" "cop")
10804 (set_attr "slots" "c3")
10805 (set_attr "stall" "none")])
10808 (define_insn "cgen_intrinsic_cpabs3_h_P0_P1"
10809 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10811 (match_operand:DI 1 "general_operand" "x")
10812 (match_operand:DI 2 "general_operand" "x")
10814 "CGEN_ENABLE_INSN_P (353)"
10815 "cpabs3.h\\t%0,%1,%2"
10816 [(set_attr "may_trap" "no")
10817 (set_attr "latency" "0")
10818 (set_attr "length" "4")
10819 (set_attr "slot" "cop")
10820 (set_attr "slots" "p0_p1")
10821 (set_attr "stall" "none")])
10824 (define_insn "cgen_intrinsic_cpabs3_b_C3"
10825 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10827 (match_operand:DI 1 "general_operand" "x")
10828 (match_operand:DI 2 "general_operand" "x")
10830 "CGEN_ENABLE_INSN_P (354)"
10831 "cpabs3.b\\t%0,%1,%2"
10832 [(set_attr "may_trap" "no")
10833 (set_attr "latency" "0")
10834 (set_attr "length" "4")
10835 (set_attr "slot" "cop")
10836 (set_attr "slots" "c3")
10837 (set_attr "stall" "none")])
10840 (define_insn "cgen_intrinsic_cpabs3_b_P0_P1"
10841 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10843 (match_operand:DI 1 "general_operand" "x")
10844 (match_operand:DI 2 "general_operand" "x")
10846 "CGEN_ENABLE_INSN_P (355)"
10847 "cpabs3.b\\t%0,%1,%2"
10848 [(set_attr "may_trap" "no")
10849 (set_attr "latency" "0")
10850 (set_attr "length" "4")
10851 (set_attr "slot" "cop")
10852 (set_attr "slots" "p0_p1")
10853 (set_attr "stall" "none")])
10856 (define_insn "cgen_intrinsic_cpabsu3_b_C3"
10857 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10859 (match_operand:DI 1 "general_operand" "x")
10860 (match_operand:DI 2 "general_operand" "x")
10862 "CGEN_ENABLE_INSN_P (356)"
10863 "cpabsu3.b\\t%0,%1,%2"
10864 [(set_attr "may_trap" "no")
10865 (set_attr "latency" "0")
10866 (set_attr "length" "4")
10867 (set_attr "slot" "cop")
10868 (set_attr "slots" "c3")
10869 (set_attr "stall" "none")])
10872 (define_insn "cgen_intrinsic_cpabsu3_b_P0_P1"
10873 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10875 (match_operand:DI 1 "general_operand" "x")
10876 (match_operand:DI 2 "general_operand" "x")
10878 "CGEN_ENABLE_INSN_P (357)"
10879 "cpabsu3.b\\t%0,%1,%2"
10880 [(set_attr "may_trap" "no")
10881 (set_attr "latency" "0")
10882 (set_attr "length" "4")
10883 (set_attr "slot" "cop")
10884 (set_attr "slots" "p0_p1")
10885 (set_attr "stall" "none")])
10888 (define_insn "cgen_intrinsic_cpaddsr3_w_C3"
10889 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10891 (match_operand:DI 1 "general_operand" "x")
10892 (match_operand:DI 2 "general_operand" "x")
10894 "CGEN_ENABLE_INSN_P (358)"
10895 "cpaddsr3.w\\t%0,%1,%2"
10896 [(set_attr "may_trap" "no")
10897 (set_attr "latency" "0")
10898 (set_attr "length" "4")
10899 (set_attr "slot" "cop")
10900 (set_attr "slots" "c3")
10901 (set_attr "stall" "none")])
10904 (define_insn "cgen_intrinsic_cpaddsr3_w_P0_P1"
10905 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10907 (match_operand:DI 1 "general_operand" "x")
10908 (match_operand:DI 2 "general_operand" "x")
10910 "CGEN_ENABLE_INSN_P (359)"
10911 "cpaddsr3.w\\t%0,%1,%2"
10912 [(set_attr "may_trap" "no")
10913 (set_attr "latency" "0")
10914 (set_attr "length" "4")
10915 (set_attr "slot" "cop")
10916 (set_attr "slots" "p0_p1")
10917 (set_attr "stall" "none")])
10920 (define_insn "cgen_intrinsic_cpaddsr3_h_C3"
10921 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10923 (match_operand:DI 1 "general_operand" "x")
10924 (match_operand:DI 2 "general_operand" "x")
10926 "CGEN_ENABLE_INSN_P (360)"
10927 "cpaddsr3.h\\t%0,%1,%2"
10928 [(set_attr "may_trap" "no")
10929 (set_attr "latency" "0")
10930 (set_attr "length" "4")
10931 (set_attr "slot" "cop")
10932 (set_attr "slots" "c3")
10933 (set_attr "stall" "none")])
10936 (define_insn "cgen_intrinsic_cpaddsr3_h_P0_P1"
10937 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10939 (match_operand:DI 1 "general_operand" "x")
10940 (match_operand:DI 2 "general_operand" "x")
10942 "CGEN_ENABLE_INSN_P (361)"
10943 "cpaddsr3.h\\t%0,%1,%2"
10944 [(set_attr "may_trap" "no")
10945 (set_attr "latency" "0")
10946 (set_attr "length" "4")
10947 (set_attr "slot" "cop")
10948 (set_attr "slots" "p0_p1")
10949 (set_attr "stall" "none")])
10952 (define_insn "cgen_intrinsic_cpaddsr3_b_C3"
10953 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10955 (match_operand:DI 1 "general_operand" "x")
10956 (match_operand:DI 2 "general_operand" "x")
10958 "CGEN_ENABLE_INSN_P (362)"
10959 "cpaddsr3.b\\t%0,%1,%2"
10960 [(set_attr "may_trap" "no")
10961 (set_attr "latency" "0")
10962 (set_attr "length" "4")
10963 (set_attr "slot" "cop")
10964 (set_attr "slots" "c3")
10965 (set_attr "stall" "none")])
10968 (define_insn "cgen_intrinsic_cpaddsr3_b_P0_P1"
10969 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10971 (match_operand:DI 1 "general_operand" "x")
10972 (match_operand:DI 2 "general_operand" "x")
10974 "CGEN_ENABLE_INSN_P (363)"
10975 "cpaddsr3.b\\t%0,%1,%2"
10976 [(set_attr "may_trap" "no")
10977 (set_attr "latency" "0")
10978 (set_attr "length" "4")
10979 (set_attr "slot" "cop")
10980 (set_attr "slots" "p0_p1")
10981 (set_attr "stall" "none")])
10984 (define_insn "cgen_intrinsic_cpaddsru3_b_C3"
10985 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
10987 (match_operand:DI 1 "general_operand" "x")
10988 (match_operand:DI 2 "general_operand" "x")
10990 "CGEN_ENABLE_INSN_P (364)"
10991 "cpaddsru3.b\\t%0,%1,%2"
10992 [(set_attr "may_trap" "no")
10993 (set_attr "latency" "0")
10994 (set_attr "length" "4")
10995 (set_attr "slot" "cop")
10996 (set_attr "slots" "c3")
10997 (set_attr "stall" "none")])
11000 (define_insn "cgen_intrinsic_cpaddsru3_b_P0_P1"
11001 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11003 (match_operand:DI 1 "general_operand" "x")
11004 (match_operand:DI 2 "general_operand" "x")
11006 "CGEN_ENABLE_INSN_P (365)"
11007 "cpaddsru3.b\\t%0,%1,%2"
11008 [(set_attr "may_trap" "no")
11009 (set_attr "latency" "0")
11010 (set_attr "length" "4")
11011 (set_attr "slot" "cop")
11012 (set_attr "slots" "p0_p1")
11013 (set_attr "stall" "none")])
11016 (define_insn "cgen_intrinsic_cpave3_w_C3"
11017 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11019 (match_operand:DI 1 "general_operand" "x")
11020 (match_operand:DI 2 "general_operand" "x")
11022 "CGEN_ENABLE_INSN_P (366)"
11023 "cpave3.w\\t%0,%1,%2"
11024 [(set_attr "may_trap" "no")
11025 (set_attr "latency" "0")
11026 (set_attr "length" "4")
11027 (set_attr "slot" "cop")
11028 (set_attr "slots" "c3")
11029 (set_attr "stall" "none")])
11032 (define_insn "cgen_intrinsic_cpave3_w_P0_P1"
11033 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11035 (match_operand:DI 1 "general_operand" "x")
11036 (match_operand:DI 2 "general_operand" "x")
11038 "CGEN_ENABLE_INSN_P (367)"
11039 "cpave3.w\\t%0,%1,%2"
11040 [(set_attr "may_trap" "no")
11041 (set_attr "latency" "0")
11042 (set_attr "length" "4")
11043 (set_attr "slot" "cop")
11044 (set_attr "slots" "p0_p1")
11045 (set_attr "stall" "none")])
11048 (define_insn "cgen_intrinsic_cpave3_h_C3"
11049 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11051 (match_operand:DI 1 "general_operand" "x")
11052 (match_operand:DI 2 "general_operand" "x")
11054 "CGEN_ENABLE_INSN_P (368)"
11055 "cpave3.h\\t%0,%1,%2"
11056 [(set_attr "may_trap" "no")
11057 (set_attr "latency" "0")
11058 (set_attr "length" "4")
11059 (set_attr "slot" "cop")
11060 (set_attr "slots" "c3")
11061 (set_attr "stall" "none")])
11064 (define_insn "cgen_intrinsic_cpave3_h_P0_P1"
11065 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11067 (match_operand:DI 1 "general_operand" "x")
11068 (match_operand:DI 2 "general_operand" "x")
11070 "CGEN_ENABLE_INSN_P (369)"
11071 "cpave3.h\\t%0,%1,%2"
11072 [(set_attr "may_trap" "no")
11073 (set_attr "latency" "0")
11074 (set_attr "length" "4")
11075 (set_attr "slot" "cop")
11076 (set_attr "slots" "p0_p1")
11077 (set_attr "stall" "none")])
11080 (define_insn "cgen_intrinsic_cpave3_b_C3"
11081 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11083 (match_operand:DI 1 "general_operand" "x")
11084 (match_operand:DI 2 "general_operand" "x")
11086 "CGEN_ENABLE_INSN_P (370)"
11087 "cpave3.b\\t%0,%1,%2"
11088 [(set_attr "may_trap" "no")
11089 (set_attr "latency" "0")
11090 (set_attr "length" "4")
11091 (set_attr "slot" "cop")
11092 (set_attr "slots" "c3")
11093 (set_attr "stall" "none")])
11096 (define_insn "cgen_intrinsic_cpave3_b_P0_P1"
11097 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11099 (match_operand:DI 1 "general_operand" "x")
11100 (match_operand:DI 2 "general_operand" "x")
11102 "CGEN_ENABLE_INSN_P (371)"
11103 "cpave3.b\\t%0,%1,%2"
11104 [(set_attr "may_trap" "no")
11105 (set_attr "latency" "0")
11106 (set_attr "length" "4")
11107 (set_attr "slot" "cop")
11108 (set_attr "slots" "p0_p1")
11109 (set_attr "stall" "none")])
11112 (define_insn "cgen_intrinsic_cpaveu3_b_C3"
11113 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11115 (match_operand:DI 1 "general_operand" "x")
11116 (match_operand:DI 2 "general_operand" "x")
11118 "CGEN_ENABLE_INSN_P (372)"
11119 "cpaveu3.b\\t%0,%1,%2"
11120 [(set_attr "may_trap" "no")
11121 (set_attr "latency" "0")
11122 (set_attr "length" "4")
11123 (set_attr "slot" "cop")
11124 (set_attr "slots" "c3")
11125 (set_attr "stall" "none")])
11128 (define_insn "cgen_intrinsic_cpaveu3_b_P0_P1"
11129 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11131 (match_operand:DI 1 "general_operand" "x")
11132 (match_operand:DI 2 "general_operand" "x")
11134 "CGEN_ENABLE_INSN_P (373)"
11135 "cpaveu3.b\\t%0,%1,%2"
11136 [(set_attr "may_trap" "no")
11137 (set_attr "latency" "0")
11138 (set_attr "length" "4")
11139 (set_attr "slot" "cop")
11140 (set_attr "slots" "p0_p1")
11141 (set_attr "stall" "none")])
11144 (define_insn "cgen_intrinsic_cpextlsub3_b_C3"
11145 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11147 (match_operand:DI 1 "general_operand" "x")
11148 (match_operand:DI 2 "general_operand" "x")
11150 "CGEN_ENABLE_INSN_P (374)"
11151 "cpextlsub3.b\\t%0,%1,%2"
11152 [(set_attr "may_trap" "no")
11153 (set_attr "latency" "0")
11154 (set_attr "length" "4")
11155 (set_attr "slot" "cop")
11156 (set_attr "slots" "c3")
11157 (set_attr "stall" "none")])
11160 (define_insn "cgen_intrinsic_cpextlsub3_b_P0_P1"
11161 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11163 (match_operand:DI 1 "general_operand" "x")
11164 (match_operand:DI 2 "general_operand" "x")
11166 "CGEN_ENABLE_INSN_P (375)"
11167 "cpextlsub3.b\\t%0,%1,%2"
11168 [(set_attr "may_trap" "no")
11169 (set_attr "latency" "0")
11170 (set_attr "length" "4")
11171 (set_attr "slot" "cop")
11172 (set_attr "slots" "p0_p1")
11173 (set_attr "stall" "none")])
11176 (define_insn "cgen_intrinsic_cpextlsubu3_b_C3"
11177 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11179 (match_operand:DI 1 "general_operand" "x")
11180 (match_operand:DI 2 "general_operand" "x")
11182 "CGEN_ENABLE_INSN_P (376)"
11183 "cpextlsubu3.b\\t%0,%1,%2"
11184 [(set_attr "may_trap" "no")
11185 (set_attr "latency" "0")
11186 (set_attr "length" "4")
11187 (set_attr "slot" "cop")
11188 (set_attr "slots" "c3")
11189 (set_attr "stall" "none")])
11192 (define_insn "cgen_intrinsic_cpextlsubu3_b_P0_P1"
11193 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11195 (match_operand:DI 1 "general_operand" "x")
11196 (match_operand:DI 2 "general_operand" "x")
11198 "CGEN_ENABLE_INSN_P (377)"
11199 "cpextlsubu3.b\\t%0,%1,%2"
11200 [(set_attr "may_trap" "no")
11201 (set_attr "latency" "0")
11202 (set_attr "length" "4")
11203 (set_attr "slot" "cop")
11204 (set_attr "slots" "p0_p1")
11205 (set_attr "stall" "none")])
11208 (define_insn "cgen_intrinsic_cpextusub3_b_C3"
11209 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11211 (match_operand:DI 1 "general_operand" "x")
11212 (match_operand:DI 2 "general_operand" "x")
11214 "CGEN_ENABLE_INSN_P (378)"
11215 "cpextusub3.b\\t%0,%1,%2"
11216 [(set_attr "may_trap" "no")
11217 (set_attr "latency" "0")
11218 (set_attr "length" "4")
11219 (set_attr "slot" "cop")
11220 (set_attr "slots" "c3")
11221 (set_attr "stall" "none")])
11224 (define_insn "cgen_intrinsic_cpextusub3_b_P0_P1"
11225 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11227 (match_operand:DI 1 "general_operand" "x")
11228 (match_operand:DI 2 "general_operand" "x")
11230 "CGEN_ENABLE_INSN_P (379)"
11231 "cpextusub3.b\\t%0,%1,%2"
11232 [(set_attr "may_trap" "no")
11233 (set_attr "latency" "0")
11234 (set_attr "length" "4")
11235 (set_attr "slot" "cop")
11236 (set_attr "slots" "p0_p1")
11237 (set_attr "stall" "none")])
11240 (define_insn "cgen_intrinsic_cpextusubu3_b_C3"
11241 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11243 (match_operand:DI 1 "general_operand" "x")
11244 (match_operand:DI 2 "general_operand" "x")
11246 "CGEN_ENABLE_INSN_P (380)"
11247 "cpextusubu3.b\\t%0,%1,%2"
11248 [(set_attr "may_trap" "no")
11249 (set_attr "latency" "0")
11250 (set_attr "length" "4")
11251 (set_attr "slot" "cop")
11252 (set_attr "slots" "c3")
11253 (set_attr "stall" "none")])
11256 (define_insn "cgen_intrinsic_cpextusubu3_b_P0_P1"
11257 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11259 (match_operand:DI 1 "general_operand" "x")
11260 (match_operand:DI 2 "general_operand" "x")
11262 "CGEN_ENABLE_INSN_P (381)"
11263 "cpextusubu3.b\\t%0,%1,%2"
11264 [(set_attr "may_trap" "no")
11265 (set_attr "latency" "0")
11266 (set_attr "length" "4")
11267 (set_attr "slot" "cop")
11268 (set_attr "slots" "p0_p1")
11269 (set_attr "stall" "none")])
11272 (define_insn "cgen_intrinsic_cpextladd3_b_C3"
11273 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11275 (match_operand:DI 1 "general_operand" "x")
11276 (match_operand:DI 2 "general_operand" "x")
11278 "CGEN_ENABLE_INSN_P (382)"
11279 "cpextladd3.b\\t%0,%1,%2"
11280 [(set_attr "may_trap" "no")
11281 (set_attr "latency" "0")
11282 (set_attr "length" "4")
11283 (set_attr "slot" "cop")
11284 (set_attr "slots" "c3")
11285 (set_attr "stall" "none")])
11288 (define_insn "cgen_intrinsic_cpextladd3_b_P0_P1"
11289 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11291 (match_operand:DI 1 "general_operand" "x")
11292 (match_operand:DI 2 "general_operand" "x")
11294 "CGEN_ENABLE_INSN_P (383)"
11295 "cpextladd3.b\\t%0,%1,%2"
11296 [(set_attr "may_trap" "no")
11297 (set_attr "latency" "0")
11298 (set_attr "length" "4")
11299 (set_attr "slot" "cop")
11300 (set_attr "slots" "p0_p1")
11301 (set_attr "stall" "none")])
11304 (define_insn "cgen_intrinsic_cpextladdu3_b_C3"
11305 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11307 (match_operand:DI 1 "general_operand" "x")
11308 (match_operand:DI 2 "general_operand" "x")
11310 "CGEN_ENABLE_INSN_P (384)"
11311 "cpextladdu3.b\\t%0,%1,%2"
11312 [(set_attr "may_trap" "no")
11313 (set_attr "latency" "0")
11314 (set_attr "length" "4")
11315 (set_attr "slot" "cop")
11316 (set_attr "slots" "c3")
11317 (set_attr "stall" "none")])
11320 (define_insn "cgen_intrinsic_cpextladdu3_b_P0_P1"
11321 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11323 (match_operand:DI 1 "general_operand" "x")
11324 (match_operand:DI 2 "general_operand" "x")
11326 "CGEN_ENABLE_INSN_P (385)"
11327 "cpextladdu3.b\\t%0,%1,%2"
11328 [(set_attr "may_trap" "no")
11329 (set_attr "latency" "0")
11330 (set_attr "length" "4")
11331 (set_attr "slot" "cop")
11332 (set_attr "slots" "p0_p1")
11333 (set_attr "stall" "none")])
11336 (define_insn "cgen_intrinsic_cpextuadd3_b_C3"
11337 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11339 (match_operand:DI 1 "general_operand" "x")
11340 (match_operand:DI 2 "general_operand" "x")
11342 "CGEN_ENABLE_INSN_P (386)"
11343 "cpextuadd3.b\\t%0,%1,%2"
11344 [(set_attr "may_trap" "no")
11345 (set_attr "latency" "0")
11346 (set_attr "length" "4")
11347 (set_attr "slot" "cop")
11348 (set_attr "slots" "c3")
11349 (set_attr "stall" "none")])
11352 (define_insn "cgen_intrinsic_cpextuadd3_b_P0_P1"
11353 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11355 (match_operand:DI 1 "general_operand" "x")
11356 (match_operand:DI 2 "general_operand" "x")
11358 "CGEN_ENABLE_INSN_P (387)"
11359 "cpextuadd3.b\\t%0,%1,%2"
11360 [(set_attr "may_trap" "no")
11361 (set_attr "latency" "0")
11362 (set_attr "length" "4")
11363 (set_attr "slot" "cop")
11364 (set_attr "slots" "p0_p1")
11365 (set_attr "stall" "none")])
11368 (define_insn "cgen_intrinsic_cpextuaddu3_b_C3"
11369 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11371 (match_operand:DI 1 "general_operand" "x")
11372 (match_operand:DI 2 "general_operand" "x")
11374 "CGEN_ENABLE_INSN_P (388)"
11375 "cpextuaddu3.b\\t%0,%1,%2"
11376 [(set_attr "may_trap" "no")
11377 (set_attr "latency" "0")
11378 (set_attr "length" "4")
11379 (set_attr "slot" "cop")
11380 (set_attr "slots" "c3")
11381 (set_attr "stall" "none")])
11384 (define_insn "cgen_intrinsic_cpextuaddu3_b_P0_P1"
11385 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11387 (match_operand:DI 1 "general_operand" "x")
11388 (match_operand:DI 2 "general_operand" "x")
11390 "CGEN_ENABLE_INSN_P (389)"
11391 "cpextuaddu3.b\\t%0,%1,%2"
11392 [(set_attr "may_trap" "no")
11393 (set_attr "latency" "0")
11394 (set_attr "length" "4")
11395 (set_attr "slot" "cop")
11396 (set_attr "slots" "p0_p1")
11397 (set_attr "stall" "none")])
11400 (define_insn "cgen_intrinsic_cpssub3_w_C3"
11401 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11402 (unspec_volatile:DI [
11403 (match_operand:DI 1 "general_operand" "x")
11404 (match_operand:DI 2 "general_operand" "x")
11407 (unspec_volatile:SI [
11411 "CGEN_ENABLE_INSN_P (390)"
11412 "cpssub3.w\\t%0,%1,%2"
11413 [(set_attr "may_trap" "no")
11414 (set_attr "latency" "0")
11415 (set_attr "length" "4")
11416 (set_attr "slot" "cop")
11417 (set_attr "slots" "c3")
11418 (set_attr "stall" "none")])
11421 (define_insn "cgen_intrinsic_cpssub3_w_P0_P1"
11422 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11423 (unspec_volatile:DI [
11424 (match_operand:DI 1 "general_operand" "x")
11425 (match_operand:DI 2 "general_operand" "x")
11428 (unspec_volatile:SI [
11432 "CGEN_ENABLE_INSN_P (391)"
11433 "cpssub3.w\\t%0,%1,%2"
11434 [(set_attr "may_trap" "no")
11435 (set_attr "latency" "0")
11436 (set_attr "length" "4")
11437 (set_attr "slot" "cop")
11438 (set_attr "slots" "p0_p1")
11439 (set_attr "stall" "none")])
11442 (define_insn "cgen_intrinsic_cpssub3_h_C3"
11443 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11444 (unspec_volatile:DI [
11445 (match_operand:DI 1 "general_operand" "x")
11446 (match_operand:DI 2 "general_operand" "x")
11449 (unspec_volatile:SI [
11453 "CGEN_ENABLE_INSN_P (392)"
11454 "cpssub3.h\\t%0,%1,%2"
11455 [(set_attr "may_trap" "no")
11456 (set_attr "latency" "0")
11457 (set_attr "length" "4")
11458 (set_attr "slot" "cop")
11459 (set_attr "slots" "c3")
11460 (set_attr "stall" "none")])
11463 (define_insn "cgen_intrinsic_cpssub3_h_P0_P1"
11464 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11465 (unspec_volatile:DI [
11466 (match_operand:DI 1 "general_operand" "x")
11467 (match_operand:DI 2 "general_operand" "x")
11470 (unspec_volatile:SI [
11474 "CGEN_ENABLE_INSN_P (393)"
11475 "cpssub3.h\\t%0,%1,%2"
11476 [(set_attr "may_trap" "no")
11477 (set_attr "latency" "0")
11478 (set_attr "length" "4")
11479 (set_attr "slot" "cop")
11480 (set_attr "slots" "p0_p1")
11481 (set_attr "stall" "none")])
11484 (define_insn "cgen_intrinsic_cpsadd3_w_C3"
11485 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11486 (unspec_volatile:DI [
11487 (match_operand:DI 1 "general_operand" "x")
11488 (match_operand:DI 2 "general_operand" "x")
11490 "CGEN_ENABLE_INSN_P (394)"
11491 "cpsadd3.w\\t%0,%1,%2"
11492 [(set_attr "may_trap" "no")
11493 (set_attr "latency" "0")
11494 (set_attr "length" "4")
11495 (set_attr "slot" "cop")
11496 (set_attr "slots" "c3")
11497 (set_attr "stall" "none")])
11500 (define_insn "cgen_intrinsic_cpsadd3_w_P0_P1"
11501 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11502 (unspec_volatile:DI [
11503 (match_operand:DI 1 "general_operand" "x")
11504 (match_operand:DI 2 "general_operand" "x")
11506 "CGEN_ENABLE_INSN_P (395)"
11507 "cpsadd3.w\\t%0,%1,%2"
11508 [(set_attr "may_trap" "no")
11509 (set_attr "latency" "0")
11510 (set_attr "length" "4")
11511 (set_attr "slot" "cop")
11512 (set_attr "slots" "p0_p1")
11513 (set_attr "stall" "none")])
11516 (define_insn "cgen_intrinsic_cpsadd3_h_C3"
11517 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11518 (unspec_volatile:DI [
11519 (match_operand:DI 1 "general_operand" "x")
11520 (match_operand:DI 2 "general_operand" "x")
11522 "CGEN_ENABLE_INSN_P (396)"
11523 "cpsadd3.h\\t%0,%1,%2"
11524 [(set_attr "may_trap" "no")
11525 (set_attr "latency" "0")
11526 (set_attr "length" "4")
11527 (set_attr "slot" "cop")
11528 (set_attr "slots" "c3")
11529 (set_attr "stall" "none")])
11532 (define_insn "cgen_intrinsic_cpsadd3_h_P0_P1"
11533 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11534 (unspec_volatile:DI [
11535 (match_operand:DI 1 "general_operand" "x")
11536 (match_operand:DI 2 "general_operand" "x")
11538 "CGEN_ENABLE_INSN_P (397)"
11539 "cpsadd3.h\\t%0,%1,%2"
11540 [(set_attr "may_trap" "no")
11541 (set_attr "latency" "0")
11542 (set_attr "length" "4")
11543 (set_attr "slot" "cop")
11544 (set_attr "slots" "p0_p1")
11545 (set_attr "stall" "none")])
11548 (define_insn "cgen_intrinsic_cdsub3_C3"
11549 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11551 (match_operand:DI 1 "general_operand" "x")
11552 (match_operand:DI 2 "general_operand" "x")
11554 "CGEN_ENABLE_INSN_P (398)"
11555 "cdsub3\\t%0,%1,%2"
11556 [(set_attr "may_trap" "no")
11557 (set_attr "latency" "0")
11558 (set_attr "length" "4")
11559 (set_attr "slot" "cop")
11560 (set_attr "slots" "c3")
11561 (set_attr "stall" "none")])
11564 (define_insn "cgen_intrinsic_cdsub3_P0_P1"
11565 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11567 (match_operand:DI 1 "general_operand" "x")
11568 (match_operand:DI 2 "general_operand" "x")
11570 "CGEN_ENABLE_INSN_P (399)"
11571 "cdsub3\\t%0,%1,%2"
11572 [(set_attr "may_trap" "no")
11573 (set_attr "latency" "0")
11574 (set_attr "length" "4")
11575 (set_attr "slot" "cop")
11576 (set_attr "slots" "p0_p1")
11577 (set_attr "stall" "none")])
11580 (define_insn "cgen_intrinsic_cpsub3_w_C3"
11581 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11583 (match_operand:DI 1 "general_operand" "x")
11584 (match_operand:DI 2 "general_operand" "x")
11586 "CGEN_ENABLE_INSN_P (400)"
11587 "cpsub3.w\\t%0,%1,%2"
11588 [(set_attr "may_trap" "no")
11589 (set_attr "latency" "0")
11590 (set_attr "length" "4")
11591 (set_attr "slot" "cop")
11592 (set_attr "slots" "c3")
11593 (set_attr "stall" "none")])
11596 (define_insn "cgen_intrinsic_cpsub3_w_P0_P1"
11597 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11599 (match_operand:DI 1 "general_operand" "x")
11600 (match_operand:DI 2 "general_operand" "x")
11602 "CGEN_ENABLE_INSN_P (401)"
11603 "cpsub3.w\\t%0,%1,%2"
11604 [(set_attr "may_trap" "no")
11605 (set_attr "latency" "0")
11606 (set_attr "length" "4")
11607 (set_attr "slot" "cop")
11608 (set_attr "slots" "p0_p1")
11609 (set_attr "stall" "none")])
11612 (define_insn "cgen_intrinsic_cpsub3_h_C3"
11613 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11615 (match_operand:DI 1 "general_operand" "x")
11616 (match_operand:DI 2 "general_operand" "x")
11618 "CGEN_ENABLE_INSN_P (402)"
11619 "cpsub3.h\\t%0,%1,%2"
11620 [(set_attr "may_trap" "no")
11621 (set_attr "latency" "0")
11622 (set_attr "length" "4")
11623 (set_attr "slot" "cop")
11624 (set_attr "slots" "c3")
11625 (set_attr "stall" "none")])
11628 (define_insn "cgen_intrinsic_cpsub3_h_P0_P1"
11629 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11631 (match_operand:DI 1 "general_operand" "x")
11632 (match_operand:DI 2 "general_operand" "x")
11634 "CGEN_ENABLE_INSN_P (403)"
11635 "cpsub3.h\\t%0,%1,%2"
11636 [(set_attr "may_trap" "no")
11637 (set_attr "latency" "0")
11638 (set_attr "length" "4")
11639 (set_attr "slot" "cop")
11640 (set_attr "slots" "p0_p1")
11641 (set_attr "stall" "none")])
11644 (define_insn "cgen_intrinsic_cpsub3_b_C3"
11645 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11647 (match_operand:DI 1 "general_operand" "x")
11648 (match_operand:DI 2 "general_operand" "x")
11650 "CGEN_ENABLE_INSN_P (404)"
11651 "cpsub3.b\\t%0,%1,%2"
11652 [(set_attr "may_trap" "no")
11653 (set_attr "latency" "0")
11654 (set_attr "length" "4")
11655 (set_attr "slot" "cop")
11656 (set_attr "slots" "c3")
11657 (set_attr "stall" "none")])
11660 (define_insn "cgen_intrinsic_cpsub3_b_P0_P1"
11661 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11663 (match_operand:DI 1 "general_operand" "x")
11664 (match_operand:DI 2 "general_operand" "x")
11666 "CGEN_ENABLE_INSN_P (405)"
11667 "cpsub3.b\\t%0,%1,%2"
11668 [(set_attr "may_trap" "no")
11669 (set_attr "latency" "0")
11670 (set_attr "length" "4")
11671 (set_attr "slot" "cop")
11672 (set_attr "slots" "p0_p1")
11673 (set_attr "stall" "none")])
11676 (define_insn "cgen_intrinsic_cdadd3_C3"
11677 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11679 (match_operand:DI 1 "general_operand" "x")
11680 (match_operand:DI 2 "general_operand" "x")
11682 "CGEN_ENABLE_INSN_P (406)"
11683 "cdadd3\\t%0,%1,%2"
11684 [(set_attr "may_trap" "no")
11685 (set_attr "latency" "0")
11686 (set_attr "length" "4")
11687 (set_attr "slot" "cop")
11688 (set_attr "slots" "c3")
11689 (set_attr "stall" "none")])
11692 (define_insn "cgen_intrinsic_cdadd3_P0_P1"
11693 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
11695 (match_operand:DI 1 "general_operand" "x")
11696 (match_operand:DI 2 "general_operand" "x")
11698 "CGEN_ENABLE_INSN_P (407)"
11699 "cdadd3\\t%0,%1,%2"
11700 [(set_attr "may_trap" "no")
11701 (set_attr "latency" "0")
11702 (set_attr "length" "4")
11703 (set_attr "slot" "cop")
11704 (set_attr "slots" "p0_p1")
11705 (set_attr "stall" "none")])
11708 (define_insn "cgen_intrinsic_cpocmpge_w_C3"
11711 (match_operand:DI 0 "general_operand" "x")
11712 (match_operand:DI 1 "general_operand" "x")
11719 "CGEN_ENABLE_INSN_P (408)"
11720 "cpocmpge.w\\t%0,%1"
11721 [(set_attr "may_trap" "no")
11722 (set_attr "latency" "0")
11723 (set_attr "length" "4")
11724 (set_attr "slot" "cop")
11725 (set_attr "slots" "c3")
11726 (set_attr "stall" "none")])
11729 (define_insn "cgen_intrinsic_cpocmpge_w_P0_P1"
11730 [(unspec_volatile [
11731 (match_operand:DI 0 "general_operand" "x")
11732 (match_operand:DI 1 "general_operand" "x")
11734 "CGEN_ENABLE_INSN_P (409)"
11735 "cpocmpge.w\\t%0,%1"
11736 [(set_attr "may_trap" "no")
11737 (set_attr "latency" "0")
11738 (set_attr "length" "4")
11739 (set_attr "slot" "cop")
11740 (set_attr "slots" "p0_p1")
11741 (set_attr "stall" "none")])
11744 (define_insn "cgen_intrinsic_cpocmpgeu_w_C3"
11747 (match_operand:DI 0 "general_operand" "x")
11748 (match_operand:DI 1 "general_operand" "x")
11755 "CGEN_ENABLE_INSN_P (410)"
11756 "cpocmpgeu.w\\t%0,%1"
11757 [(set_attr "may_trap" "no")
11758 (set_attr "latency" "0")
11759 (set_attr "length" "4")
11760 (set_attr "slot" "cop")
11761 (set_attr "slots" "c3")
11762 (set_attr "stall" "none")])
11765 (define_insn "cgen_intrinsic_cpocmpgeu_w_P0_P1"
11766 [(unspec_volatile [
11767 (match_operand:DI 0 "general_operand" "x")
11768 (match_operand:DI 1 "general_operand" "x")
11770 "CGEN_ENABLE_INSN_P (411)"
11771 "cpocmpgeu.w\\t%0,%1"
11772 [(set_attr "may_trap" "no")
11773 (set_attr "latency" "0")
11774 (set_attr "length" "4")
11775 (set_attr "slot" "cop")
11776 (set_attr "slots" "p0_p1")
11777 (set_attr "stall" "none")])
11780 (define_insn "cgen_intrinsic_cpocmpge_h_C3"
11783 (match_operand:DI 0 "general_operand" "x")
11784 (match_operand:DI 1 "general_operand" "x")
11791 "CGEN_ENABLE_INSN_P (412)"
11792 "cpocmpge.h\\t%0,%1"
11793 [(set_attr "may_trap" "no")
11794 (set_attr "latency" "0")
11795 (set_attr "length" "4")
11796 (set_attr "slot" "cop")
11797 (set_attr "slots" "c3")
11798 (set_attr "stall" "none")])
11801 (define_insn "cgen_intrinsic_cpocmpge_h_P0_P1"
11802 [(unspec_volatile [
11803 (match_operand:DI 0 "general_operand" "x")
11804 (match_operand:DI 1 "general_operand" "x")
11806 "CGEN_ENABLE_INSN_P (413)"
11807 "cpocmpge.h\\t%0,%1"
11808 [(set_attr "may_trap" "no")
11809 (set_attr "latency" "0")
11810 (set_attr "length" "4")
11811 (set_attr "slot" "cop")
11812 (set_attr "slots" "p0_p1")
11813 (set_attr "stall" "none")])
11816 (define_insn "cgen_intrinsic_cpocmpge_b_C3"
11819 (match_operand:DI 0 "general_operand" "x")
11820 (match_operand:DI 1 "general_operand" "x")
11827 "CGEN_ENABLE_INSN_P (414)"
11828 "cpocmpge.b\\t%0,%1"
11829 [(set_attr "may_trap" "no")
11830 (set_attr "latency" "0")
11831 (set_attr "length" "4")
11832 (set_attr "slot" "cop")
11833 (set_attr "slots" "c3")
11834 (set_attr "stall" "none")])
11837 (define_insn "cgen_intrinsic_cpocmpge_b_P0_P1"
11838 [(unspec_volatile [
11839 (match_operand:DI 0 "general_operand" "x")
11840 (match_operand:DI 1 "general_operand" "x")
11842 "CGEN_ENABLE_INSN_P (415)"
11843 "cpocmpge.b\\t%0,%1"
11844 [(set_attr "may_trap" "no")
11845 (set_attr "latency" "0")
11846 (set_attr "length" "4")
11847 (set_attr "slot" "cop")
11848 (set_attr "slots" "p0_p1")
11849 (set_attr "stall" "none")])
11852 (define_insn "cgen_intrinsic_cpocmpgeu_b_C3"
11855 (match_operand:DI 0 "general_operand" "x")
11856 (match_operand:DI 1 "general_operand" "x")
11863 "CGEN_ENABLE_INSN_P (416)"
11864 "cpocmpgeu.b\\t%0,%1"
11865 [(set_attr "may_trap" "no")
11866 (set_attr "latency" "0")
11867 (set_attr "length" "4")
11868 (set_attr "slot" "cop")
11869 (set_attr "slots" "c3")
11870 (set_attr "stall" "none")])
11873 (define_insn "cgen_intrinsic_cpocmpgeu_b_P0_P1"
11874 [(unspec_volatile [
11875 (match_operand:DI 0 "general_operand" "x")
11876 (match_operand:DI 1 "general_operand" "x")
11878 "CGEN_ENABLE_INSN_P (417)"
11879 "cpocmpgeu.b\\t%0,%1"
11880 [(set_attr "may_trap" "no")
11881 (set_attr "latency" "0")
11882 (set_attr "length" "4")
11883 (set_attr "slot" "cop")
11884 (set_attr "slots" "p0_p1")
11885 (set_attr "stall" "none")])
11888 (define_insn "cgen_intrinsic_cpocmpgt_w_C3"
11891 (match_operand:DI 0 "general_operand" "x")
11892 (match_operand:DI 1 "general_operand" "x")
11899 "CGEN_ENABLE_INSN_P (418)"
11900 "cpocmpgt.w\\t%0,%1"
11901 [(set_attr "may_trap" "no")
11902 (set_attr "latency" "0")
11903 (set_attr "length" "4")
11904 (set_attr "slot" "cop")
11905 (set_attr "slots" "c3")
11906 (set_attr "stall" "none")])
11909 (define_insn "cgen_intrinsic_cpocmpgt_w_P0_P1"
11910 [(unspec_volatile [
11911 (match_operand:DI 0 "general_operand" "x")
11912 (match_operand:DI 1 "general_operand" "x")
11914 "CGEN_ENABLE_INSN_P (419)"
11915 "cpocmpgt.w\\t%0,%1"
11916 [(set_attr "may_trap" "no")
11917 (set_attr "latency" "0")
11918 (set_attr "length" "4")
11919 (set_attr "slot" "cop")
11920 (set_attr "slots" "p0_p1")
11921 (set_attr "stall" "none")])
11924 (define_insn "cgen_intrinsic_cpocmpgtu_w_C3"
11927 (match_operand:DI 0 "general_operand" "x")
11928 (match_operand:DI 1 "general_operand" "x")
11935 "CGEN_ENABLE_INSN_P (420)"
11936 "cpocmpgtu.w\\t%0,%1"
11937 [(set_attr "may_trap" "no")
11938 (set_attr "latency" "0")
11939 (set_attr "length" "4")
11940 (set_attr "slot" "cop")
11941 (set_attr "slots" "c3")
11942 (set_attr "stall" "none")])
11945 (define_insn "cgen_intrinsic_cpocmpgtu_w_P0_P1"
11946 [(unspec_volatile [
11947 (match_operand:DI 0 "general_operand" "x")
11948 (match_operand:DI 1 "general_operand" "x")
11950 "CGEN_ENABLE_INSN_P (421)"
11951 "cpocmpgtu.w\\t%0,%1"
11952 [(set_attr "may_trap" "no")
11953 (set_attr "latency" "0")
11954 (set_attr "length" "4")
11955 (set_attr "slot" "cop")
11956 (set_attr "slots" "p0_p1")
11957 (set_attr "stall" "none")])
11960 (define_insn "cgen_intrinsic_cpocmpgt_h_C3"
11963 (match_operand:DI 0 "general_operand" "x")
11964 (match_operand:DI 1 "general_operand" "x")
11971 "CGEN_ENABLE_INSN_P (422)"
11972 "cpocmpgt.h\\t%0,%1"
11973 [(set_attr "may_trap" "no")
11974 (set_attr "latency" "0")
11975 (set_attr "length" "4")
11976 (set_attr "slot" "cop")
11977 (set_attr "slots" "c3")
11978 (set_attr "stall" "none")])
11981 (define_insn "cgen_intrinsic_cpocmpgt_h_P0_P1"
11982 [(unspec_volatile [
11983 (match_operand:DI 0 "general_operand" "x")
11984 (match_operand:DI 1 "general_operand" "x")
11986 "CGEN_ENABLE_INSN_P (423)"
11987 "cpocmpgt.h\\t%0,%1"
11988 [(set_attr "may_trap" "no")
11989 (set_attr "latency" "0")
11990 (set_attr "length" "4")
11991 (set_attr "slot" "cop")
11992 (set_attr "slots" "p0_p1")
11993 (set_attr "stall" "none")])
11996 (define_insn "cgen_intrinsic_cpocmpgt_b_C3"
11999 (match_operand:DI 0 "general_operand" "x")
12000 (match_operand:DI 1 "general_operand" "x")
12007 "CGEN_ENABLE_INSN_P (424)"
12008 "cpocmpgt.b\\t%0,%1"
12009 [(set_attr "may_trap" "no")
12010 (set_attr "latency" "0")
12011 (set_attr "length" "4")
12012 (set_attr "slot" "cop")
12013 (set_attr "slots" "c3")
12014 (set_attr "stall" "none")])
12017 (define_insn "cgen_intrinsic_cpocmpgt_b_P0_P1"
12018 [(unspec_volatile [
12019 (match_operand:DI 0 "general_operand" "x")
12020 (match_operand:DI 1 "general_operand" "x")
12022 "CGEN_ENABLE_INSN_P (425)"
12023 "cpocmpgt.b\\t%0,%1"
12024 [(set_attr "may_trap" "no")
12025 (set_attr "latency" "0")
12026 (set_attr "length" "4")
12027 (set_attr "slot" "cop")
12028 (set_attr "slots" "p0_p1")
12029 (set_attr "stall" "none")])
12032 (define_insn "cgen_intrinsic_cpocmpgtu_b_C3"
12035 (match_operand:DI 0 "general_operand" "x")
12036 (match_operand:DI 1 "general_operand" "x")
12043 "CGEN_ENABLE_INSN_P (426)"
12044 "cpocmpgtu.b\\t%0,%1"
12045 [(set_attr "may_trap" "no")
12046 (set_attr "latency" "0")
12047 (set_attr "length" "4")
12048 (set_attr "slot" "cop")
12049 (set_attr "slots" "c3")
12050 (set_attr "stall" "none")])
12053 (define_insn "cgen_intrinsic_cpocmpgtu_b_P0_P1"
12054 [(unspec_volatile [
12055 (match_operand:DI 0 "general_operand" "x")
12056 (match_operand:DI 1 "general_operand" "x")
12058 "CGEN_ENABLE_INSN_P (427)"
12059 "cpocmpgtu.b\\t%0,%1"
12060 [(set_attr "may_trap" "no")
12061 (set_attr "latency" "0")
12062 (set_attr "length" "4")
12063 (set_attr "slot" "cop")
12064 (set_attr "slots" "p0_p1")
12065 (set_attr "stall" "none")])
12068 (define_insn "cgen_intrinsic_cpocmpne_w_C3"
12071 (match_operand:DI 0 "general_operand" "x")
12072 (match_operand:DI 1 "general_operand" "x")
12079 "CGEN_ENABLE_INSN_P (428)"
12080 "cpocmpne.w\\t%0,%1"
12081 [(set_attr "may_trap" "no")
12082 (set_attr "latency" "0")
12083 (set_attr "length" "4")
12084 (set_attr "slot" "cop")
12085 (set_attr "slots" "c3")
12086 (set_attr "stall" "none")])
12089 (define_insn "cgen_intrinsic_cpocmpne_w_P0_P1"
12090 [(unspec_volatile [
12091 (match_operand:DI 0 "general_operand" "x")
12092 (match_operand:DI 1 "general_operand" "x")
12094 "CGEN_ENABLE_INSN_P (429)"
12095 "cpocmpne.w\\t%0,%1"
12096 [(set_attr "may_trap" "no")
12097 (set_attr "latency" "0")
12098 (set_attr "length" "4")
12099 (set_attr "slot" "cop")
12100 (set_attr "slots" "p0_p1")
12101 (set_attr "stall" "none")])
12104 (define_insn "cgen_intrinsic_cpocmpne_h_C3"
12107 (match_operand:DI 0 "general_operand" "x")
12108 (match_operand:DI 1 "general_operand" "x")
12115 "CGEN_ENABLE_INSN_P (430)"
12116 "cpocmpne.h\\t%0,%1"
12117 [(set_attr "may_trap" "no")
12118 (set_attr "latency" "0")
12119 (set_attr "length" "4")
12120 (set_attr "slot" "cop")
12121 (set_attr "slots" "c3")
12122 (set_attr "stall" "none")])
12125 (define_insn "cgen_intrinsic_cpocmpne_h_P0_P1"
12126 [(unspec_volatile [
12127 (match_operand:DI 0 "general_operand" "x")
12128 (match_operand:DI 1 "general_operand" "x")
12130 "CGEN_ENABLE_INSN_P (431)"
12131 "cpocmpne.h\\t%0,%1"
12132 [(set_attr "may_trap" "no")
12133 (set_attr "latency" "0")
12134 (set_attr "length" "4")
12135 (set_attr "slot" "cop")
12136 (set_attr "slots" "p0_p1")
12137 (set_attr "stall" "none")])
12140 (define_insn "cgen_intrinsic_cpocmpne_b_C3"
12143 (match_operand:DI 0 "general_operand" "x")
12144 (match_operand:DI 1 "general_operand" "x")
12151 "CGEN_ENABLE_INSN_P (432)"
12152 "cpocmpne.b\\t%0,%1"
12153 [(set_attr "may_trap" "no")
12154 (set_attr "latency" "0")
12155 (set_attr "length" "4")
12156 (set_attr "slot" "cop")
12157 (set_attr "slots" "c3")
12158 (set_attr "stall" "none")])
12161 (define_insn "cgen_intrinsic_cpocmpne_b_P0_P1"
12162 [(unspec_volatile [
12163 (match_operand:DI 0 "general_operand" "x")
12164 (match_operand:DI 1 "general_operand" "x")
12166 "CGEN_ENABLE_INSN_P (433)"
12167 "cpocmpne.b\\t%0,%1"
12168 [(set_attr "may_trap" "no")
12169 (set_attr "latency" "0")
12170 (set_attr "length" "4")
12171 (set_attr "slot" "cop")
12172 (set_attr "slots" "p0_p1")
12173 (set_attr "stall" "none")])
12176 (define_insn "cgen_intrinsic_cpocmpeq_w_C3"
12179 (match_operand:DI 0 "general_operand" "x")
12180 (match_operand:DI 1 "general_operand" "x")
12187 "CGEN_ENABLE_INSN_P (434)"
12188 "cpocmpeq.w\\t%0,%1"
12189 [(set_attr "may_trap" "no")
12190 (set_attr "latency" "0")
12191 (set_attr "length" "4")
12192 (set_attr "slot" "cop")
12193 (set_attr "slots" "c3")
12194 (set_attr "stall" "none")])
12197 (define_insn "cgen_intrinsic_cpocmpeq_w_P0_P1"
12198 [(unspec_volatile [
12199 (match_operand:DI 0 "general_operand" "x")
12200 (match_operand:DI 1 "general_operand" "x")
12202 "CGEN_ENABLE_INSN_P (435)"
12203 "cpocmpeq.w\\t%0,%1"
12204 [(set_attr "may_trap" "no")
12205 (set_attr "latency" "0")
12206 (set_attr "length" "4")
12207 (set_attr "slot" "cop")
12208 (set_attr "slots" "p0_p1")
12209 (set_attr "stall" "none")])
12212 (define_insn "cgen_intrinsic_cpocmpeq_h_C3"
12215 (match_operand:DI 0 "general_operand" "x")
12216 (match_operand:DI 1 "general_operand" "x")
12223 "CGEN_ENABLE_INSN_P (436)"
12224 "cpocmpeq.h\\t%0,%1"
12225 [(set_attr "may_trap" "no")
12226 (set_attr "latency" "0")
12227 (set_attr "length" "4")
12228 (set_attr "slot" "cop")
12229 (set_attr "slots" "c3")
12230 (set_attr "stall" "none")])
12233 (define_insn "cgen_intrinsic_cpocmpeq_h_P0_P1"
12234 [(unspec_volatile [
12235 (match_operand:DI 0 "general_operand" "x")
12236 (match_operand:DI 1 "general_operand" "x")
12238 "CGEN_ENABLE_INSN_P (437)"
12239 "cpocmpeq.h\\t%0,%1"
12240 [(set_attr "may_trap" "no")
12241 (set_attr "latency" "0")
12242 (set_attr "length" "4")
12243 (set_attr "slot" "cop")
12244 (set_attr "slots" "p0_p1")
12245 (set_attr "stall" "none")])
12248 (define_insn "cgen_intrinsic_cpocmpeq_b_C3"
12251 (match_operand:DI 0 "general_operand" "x")
12252 (match_operand:DI 1 "general_operand" "x")
12259 "CGEN_ENABLE_INSN_P (438)"
12260 "cpocmpeq.b\\t%0,%1"
12261 [(set_attr "may_trap" "no")
12262 (set_attr "latency" "0")
12263 (set_attr "length" "4")
12264 (set_attr "slot" "cop")
12265 (set_attr "slots" "c3")
12266 (set_attr "stall" "none")])
12269 (define_insn "cgen_intrinsic_cpocmpeq_b_P0_P1"
12270 [(unspec_volatile [
12271 (match_operand:DI 0 "general_operand" "x")
12272 (match_operand:DI 1 "general_operand" "x")
12274 "CGEN_ENABLE_INSN_P (439)"
12275 "cpocmpeq.b\\t%0,%1"
12276 [(set_attr "may_trap" "no")
12277 (set_attr "latency" "0")
12278 (set_attr "length" "4")
12279 (set_attr "slot" "cop")
12280 (set_attr "slots" "p0_p1")
12281 (set_attr "stall" "none")])
12284 (define_insn "cgen_intrinsic_cpacmpge_w_C3"
12287 (match_operand:DI 0 "general_operand" "x")
12288 (match_operand:DI 1 "general_operand" "x")
12295 "CGEN_ENABLE_INSN_P (440)"
12296 "cpacmpge.w\\t%0,%1"
12297 [(set_attr "may_trap" "no")
12298 (set_attr "latency" "0")
12299 (set_attr "length" "4")
12300 (set_attr "slot" "cop")
12301 (set_attr "slots" "c3")
12302 (set_attr "stall" "none")])
12305 (define_insn "cgen_intrinsic_cpacmpge_w_P0_P1"
12306 [(unspec_volatile [
12307 (match_operand:DI 0 "general_operand" "x")
12308 (match_operand:DI 1 "general_operand" "x")
12310 "CGEN_ENABLE_INSN_P (441)"
12311 "cpacmpge.w\\t%0,%1"
12312 [(set_attr "may_trap" "no")
12313 (set_attr "latency" "0")
12314 (set_attr "length" "4")
12315 (set_attr "slot" "cop")
12316 (set_attr "slots" "p0_p1")
12317 (set_attr "stall" "none")])
12320 (define_insn "cgen_intrinsic_cpacmpgeu_w_C3"
12323 (match_operand:DI 0 "general_operand" "x")
12324 (match_operand:DI 1 "general_operand" "x")
12331 "CGEN_ENABLE_INSN_P (442)"
12332 "cpacmpgeu.w\\t%0,%1"
12333 [(set_attr "may_trap" "no")
12334 (set_attr "latency" "0")
12335 (set_attr "length" "4")
12336 (set_attr "slot" "cop")
12337 (set_attr "slots" "c3")
12338 (set_attr "stall" "none")])
12341 (define_insn "cgen_intrinsic_cpacmpgeu_w_P0_P1"
12342 [(unspec_volatile [
12343 (match_operand:DI 0 "general_operand" "x")
12344 (match_operand:DI 1 "general_operand" "x")
12346 "CGEN_ENABLE_INSN_P (443)"
12347 "cpacmpgeu.w\\t%0,%1"
12348 [(set_attr "may_trap" "no")
12349 (set_attr "latency" "0")
12350 (set_attr "length" "4")
12351 (set_attr "slot" "cop")
12352 (set_attr "slots" "p0_p1")
12353 (set_attr "stall" "none")])
12356 (define_insn "cgen_intrinsic_cpacmpge_h_C3"
12359 (match_operand:DI 0 "general_operand" "x")
12360 (match_operand:DI 1 "general_operand" "x")
12367 "CGEN_ENABLE_INSN_P (444)"
12368 "cpacmpge.h\\t%0,%1"
12369 [(set_attr "may_trap" "no")
12370 (set_attr "latency" "0")
12371 (set_attr "length" "4")
12372 (set_attr "slot" "cop")
12373 (set_attr "slots" "c3")
12374 (set_attr "stall" "none")])
12377 (define_insn "cgen_intrinsic_cpacmpge_h_P0_P1"
12378 [(unspec_volatile [
12379 (match_operand:DI 0 "general_operand" "x")
12380 (match_operand:DI 1 "general_operand" "x")
12382 "CGEN_ENABLE_INSN_P (445)"
12383 "cpacmpge.h\\t%0,%1"
12384 [(set_attr "may_trap" "no")
12385 (set_attr "latency" "0")
12386 (set_attr "length" "4")
12387 (set_attr "slot" "cop")
12388 (set_attr "slots" "p0_p1")
12389 (set_attr "stall" "none")])
12392 (define_insn "cgen_intrinsic_cpacmpge_b_C3"
12395 (match_operand:DI 0 "general_operand" "x")
12396 (match_operand:DI 1 "general_operand" "x")
12403 "CGEN_ENABLE_INSN_P (446)"
12404 "cpacmpge.b\\t%0,%1"
12405 [(set_attr "may_trap" "no")
12406 (set_attr "latency" "0")
12407 (set_attr "length" "4")
12408 (set_attr "slot" "cop")
12409 (set_attr "slots" "c3")
12410 (set_attr "stall" "none")])
12413 (define_insn "cgen_intrinsic_cpacmpge_b_P0_P1"
12414 [(unspec_volatile [
12415 (match_operand:DI 0 "general_operand" "x")
12416 (match_operand:DI 1 "general_operand" "x")
12418 "CGEN_ENABLE_INSN_P (447)"
12419 "cpacmpge.b\\t%0,%1"
12420 [(set_attr "may_trap" "no")
12421 (set_attr "latency" "0")
12422 (set_attr "length" "4")
12423 (set_attr "slot" "cop")
12424 (set_attr "slots" "p0_p1")
12425 (set_attr "stall" "none")])
12428 (define_insn "cgen_intrinsic_cpacmpgeu_b_C3"
12431 (match_operand:DI 0 "general_operand" "x")
12432 (match_operand:DI 1 "general_operand" "x")
12439 "CGEN_ENABLE_INSN_P (448)"
12440 "cpacmpgeu.b\\t%0,%1"
12441 [(set_attr "may_trap" "no")
12442 (set_attr "latency" "0")
12443 (set_attr "length" "4")
12444 (set_attr "slot" "cop")
12445 (set_attr "slots" "c3")
12446 (set_attr "stall" "none")])
12449 (define_insn "cgen_intrinsic_cpacmpgeu_b_P0_P1"
12450 [(unspec_volatile [
12451 (match_operand:DI 0 "general_operand" "x")
12452 (match_operand:DI 1 "general_operand" "x")
12454 "CGEN_ENABLE_INSN_P (449)"
12455 "cpacmpgeu.b\\t%0,%1"
12456 [(set_attr "may_trap" "no")
12457 (set_attr "latency" "0")
12458 (set_attr "length" "4")
12459 (set_attr "slot" "cop")
12460 (set_attr "slots" "p0_p1")
12461 (set_attr "stall" "none")])
12464 (define_insn "cgen_intrinsic_cpacmpgt_w_C3"
12467 (match_operand:DI 0 "general_operand" "x")
12468 (match_operand:DI 1 "general_operand" "x")
12475 "CGEN_ENABLE_INSN_P (450)"
12476 "cpacmpgt.w\\t%0,%1"
12477 [(set_attr "may_trap" "no")
12478 (set_attr "latency" "0")
12479 (set_attr "length" "4")
12480 (set_attr "slot" "cop")
12481 (set_attr "slots" "c3")
12482 (set_attr "stall" "none")])
12485 (define_insn "cgen_intrinsic_cpacmpgt_w_P0_P1"
12486 [(unspec_volatile [
12487 (match_operand:DI 0 "general_operand" "x")
12488 (match_operand:DI 1 "general_operand" "x")
12490 "CGEN_ENABLE_INSN_P (451)"
12491 "cpacmpgt.w\\t%0,%1"
12492 [(set_attr "may_trap" "no")
12493 (set_attr "latency" "0")
12494 (set_attr "length" "4")
12495 (set_attr "slot" "cop")
12496 (set_attr "slots" "p0_p1")
12497 (set_attr "stall" "none")])
12500 (define_insn "cgen_intrinsic_cpacmpgtu_w_C3"
12503 (match_operand:DI 0 "general_operand" "x")
12504 (match_operand:DI 1 "general_operand" "x")
12511 "CGEN_ENABLE_INSN_P (452)"
12512 "cpacmpgtu.w\\t%0,%1"
12513 [(set_attr "may_trap" "no")
12514 (set_attr "latency" "0")
12515 (set_attr "length" "4")
12516 (set_attr "slot" "cop")
12517 (set_attr "slots" "c3")
12518 (set_attr "stall" "none")])
12521 (define_insn "cgen_intrinsic_cpacmpgtu_w_P0_P1"
12522 [(unspec_volatile [
12523 (match_operand:DI 0 "general_operand" "x")
12524 (match_operand:DI 1 "general_operand" "x")
12526 "CGEN_ENABLE_INSN_P (453)"
12527 "cpacmpgtu.w\\t%0,%1"
12528 [(set_attr "may_trap" "no")
12529 (set_attr "latency" "0")
12530 (set_attr "length" "4")
12531 (set_attr "slot" "cop")
12532 (set_attr "slots" "p0_p1")
12533 (set_attr "stall" "none")])
12536 (define_insn "cgen_intrinsic_cpacmpgt_h_C3"
12539 (match_operand:DI 0 "general_operand" "x")
12540 (match_operand:DI 1 "general_operand" "x")
12547 "CGEN_ENABLE_INSN_P (454)"
12548 "cpacmpgt.h\\t%0,%1"
12549 [(set_attr "may_trap" "no")
12550 (set_attr "latency" "0")
12551 (set_attr "length" "4")
12552 (set_attr "slot" "cop")
12553 (set_attr "slots" "c3")
12554 (set_attr "stall" "none")])
12557 (define_insn "cgen_intrinsic_cpacmpgt_h_P0_P1"
12558 [(unspec_volatile [
12559 (match_operand:DI 0 "general_operand" "x")
12560 (match_operand:DI 1 "general_operand" "x")
12562 "CGEN_ENABLE_INSN_P (455)"
12563 "cpacmpgt.h\\t%0,%1"
12564 [(set_attr "may_trap" "no")
12565 (set_attr "latency" "0")
12566 (set_attr "length" "4")
12567 (set_attr "slot" "cop")
12568 (set_attr "slots" "p0_p1")
12569 (set_attr "stall" "none")])
12572 (define_insn "cgen_intrinsic_cpacmpgt_b_C3"
12575 (match_operand:DI 0 "general_operand" "x")
12576 (match_operand:DI 1 "general_operand" "x")
12583 "CGEN_ENABLE_INSN_P (456)"
12584 "cpacmpgt.b\\t%0,%1"
12585 [(set_attr "may_trap" "no")
12586 (set_attr "latency" "0")
12587 (set_attr "length" "4")
12588 (set_attr "slot" "cop")
12589 (set_attr "slots" "c3")
12590 (set_attr "stall" "none")])
12593 (define_insn "cgen_intrinsic_cpacmpgt_b_P0_P1"
12594 [(unspec_volatile [
12595 (match_operand:DI 0 "general_operand" "x")
12596 (match_operand:DI 1 "general_operand" "x")
12598 "CGEN_ENABLE_INSN_P (457)"
12599 "cpacmpgt.b\\t%0,%1"
12600 [(set_attr "may_trap" "no")
12601 (set_attr "latency" "0")
12602 (set_attr "length" "4")
12603 (set_attr "slot" "cop")
12604 (set_attr "slots" "p0_p1")
12605 (set_attr "stall" "none")])
12608 (define_insn "cgen_intrinsic_cpacmpgtu_b_C3"
12611 (match_operand:DI 0 "general_operand" "x")
12612 (match_operand:DI 1 "general_operand" "x")
12619 "CGEN_ENABLE_INSN_P (458)"
12620 "cpacmpgtu.b\\t%0,%1"
12621 [(set_attr "may_trap" "no")
12622 (set_attr "latency" "0")
12623 (set_attr "length" "4")
12624 (set_attr "slot" "cop")
12625 (set_attr "slots" "c3")
12626 (set_attr "stall" "none")])
12629 (define_insn "cgen_intrinsic_cpacmpgtu_b_P0_P1"
12630 [(unspec_volatile [
12631 (match_operand:DI 0 "general_operand" "x")
12632 (match_operand:DI 1 "general_operand" "x")
12634 "CGEN_ENABLE_INSN_P (459)"
12635 "cpacmpgtu.b\\t%0,%1"
12636 [(set_attr "may_trap" "no")
12637 (set_attr "latency" "0")
12638 (set_attr "length" "4")
12639 (set_attr "slot" "cop")
12640 (set_attr "slots" "p0_p1")
12641 (set_attr "stall" "none")])
12644 (define_insn "cgen_intrinsic_cpacmpne_w_C3"
12647 (match_operand:DI 0 "general_operand" "x")
12648 (match_operand:DI 1 "general_operand" "x")
12655 "CGEN_ENABLE_INSN_P (460)"
12656 "cpacmpne.w\\t%0,%1"
12657 [(set_attr "may_trap" "no")
12658 (set_attr "latency" "0")
12659 (set_attr "length" "4")
12660 (set_attr "slot" "cop")
12661 (set_attr "slots" "c3")
12662 (set_attr "stall" "none")])
12665 (define_insn "cgen_intrinsic_cpacmpne_w_P0_P1"
12666 [(unspec_volatile [
12667 (match_operand:DI 0 "general_operand" "x")
12668 (match_operand:DI 1 "general_operand" "x")
12670 "CGEN_ENABLE_INSN_P (461)"
12671 "cpacmpne.w\\t%0,%1"
12672 [(set_attr "may_trap" "no")
12673 (set_attr "latency" "0")
12674 (set_attr "length" "4")
12675 (set_attr "slot" "cop")
12676 (set_attr "slots" "p0_p1")
12677 (set_attr "stall" "none")])
12680 (define_insn "cgen_intrinsic_cpacmpne_h_C3"
12683 (match_operand:DI 0 "general_operand" "x")
12684 (match_operand:DI 1 "general_operand" "x")
12691 "CGEN_ENABLE_INSN_P (462)"
12692 "cpacmpne.h\\t%0,%1"
12693 [(set_attr "may_trap" "no")
12694 (set_attr "latency" "0")
12695 (set_attr "length" "4")
12696 (set_attr "slot" "cop")
12697 (set_attr "slots" "c3")
12698 (set_attr "stall" "none")])
12701 (define_insn "cgen_intrinsic_cpacmpne_h_P0_P1"
12702 [(unspec_volatile [
12703 (match_operand:DI 0 "general_operand" "x")
12704 (match_operand:DI 1 "general_operand" "x")
12706 "CGEN_ENABLE_INSN_P (463)"
12707 "cpacmpne.h\\t%0,%1"
12708 [(set_attr "may_trap" "no")
12709 (set_attr "latency" "0")
12710 (set_attr "length" "4")
12711 (set_attr "slot" "cop")
12712 (set_attr "slots" "p0_p1")
12713 (set_attr "stall" "none")])
12716 (define_insn "cgen_intrinsic_cpacmpne_b_C3"
12719 (match_operand:DI 0 "general_operand" "x")
12720 (match_operand:DI 1 "general_operand" "x")
12727 "CGEN_ENABLE_INSN_P (464)"
12728 "cpacmpne.b\\t%0,%1"
12729 [(set_attr "may_trap" "no")
12730 (set_attr "latency" "0")
12731 (set_attr "length" "4")
12732 (set_attr "slot" "cop")
12733 (set_attr "slots" "c3")
12734 (set_attr "stall" "none")])
12737 (define_insn "cgen_intrinsic_cpacmpne_b_P0_P1"
12738 [(unspec_volatile [
12739 (match_operand:DI 0 "general_operand" "x")
12740 (match_operand:DI 1 "general_operand" "x")
12742 "CGEN_ENABLE_INSN_P (465)"
12743 "cpacmpne.b\\t%0,%1"
12744 [(set_attr "may_trap" "no")
12745 (set_attr "latency" "0")
12746 (set_attr "length" "4")
12747 (set_attr "slot" "cop")
12748 (set_attr "slots" "p0_p1")
12749 (set_attr "stall" "none")])
12752 (define_insn "cgen_intrinsic_cpacmpeq_w_C3"
12755 (match_operand:DI 0 "general_operand" "x")
12756 (match_operand:DI 1 "general_operand" "x")
12763 "CGEN_ENABLE_INSN_P (466)"
12764 "cpacmpeq.w\\t%0,%1"
12765 [(set_attr "may_trap" "no")
12766 (set_attr "latency" "0")
12767 (set_attr "length" "4")
12768 (set_attr "slot" "cop")
12769 (set_attr "slots" "c3")
12770 (set_attr "stall" "none")])
12773 (define_insn "cgen_intrinsic_cpacmpeq_w_P0_P1"
12774 [(unspec_volatile [
12775 (match_operand:DI 0 "general_operand" "x")
12776 (match_operand:DI 1 "general_operand" "x")
12778 "CGEN_ENABLE_INSN_P (467)"
12779 "cpacmpeq.w\\t%0,%1"
12780 [(set_attr "may_trap" "no")
12781 (set_attr "latency" "0")
12782 (set_attr "length" "4")
12783 (set_attr "slot" "cop")
12784 (set_attr "slots" "p0_p1")
12785 (set_attr "stall" "none")])
12788 (define_insn "cgen_intrinsic_cpacmpeq_h_C3"
12791 (match_operand:DI 0 "general_operand" "x")
12792 (match_operand:DI 1 "general_operand" "x")
12799 "CGEN_ENABLE_INSN_P (468)"
12800 "cpacmpeq.h\\t%0,%1"
12801 [(set_attr "may_trap" "no")
12802 (set_attr "latency" "0")
12803 (set_attr "length" "4")
12804 (set_attr "slot" "cop")
12805 (set_attr "slots" "c3")
12806 (set_attr "stall" "none")])
12809 (define_insn "cgen_intrinsic_cpacmpeq_h_P0_P1"
12810 [(unspec_volatile [
12811 (match_operand:DI 0 "general_operand" "x")
12812 (match_operand:DI 1 "general_operand" "x")
12814 "CGEN_ENABLE_INSN_P (469)"
12815 "cpacmpeq.h\\t%0,%1"
12816 [(set_attr "may_trap" "no")
12817 (set_attr "latency" "0")
12818 (set_attr "length" "4")
12819 (set_attr "slot" "cop")
12820 (set_attr "slots" "p0_p1")
12821 (set_attr "stall" "none")])
12824 (define_insn "cgen_intrinsic_cpacmpeq_b_C3"
12827 (match_operand:DI 0 "general_operand" "x")
12828 (match_operand:DI 1 "general_operand" "x")
12835 "CGEN_ENABLE_INSN_P (470)"
12836 "cpacmpeq.b\\t%0,%1"
12837 [(set_attr "may_trap" "no")
12838 (set_attr "latency" "0")
12839 (set_attr "length" "4")
12840 (set_attr "slot" "cop")
12841 (set_attr "slots" "c3")
12842 (set_attr "stall" "none")])
12845 (define_insn "cgen_intrinsic_cpacmpeq_b_P0_P1"
12846 [(unspec_volatile [
12847 (match_operand:DI 0 "general_operand" "x")
12848 (match_operand:DI 1 "general_operand" "x")
12850 "CGEN_ENABLE_INSN_P (471)"
12851 "cpacmpeq.b\\t%0,%1"
12852 [(set_attr "may_trap" "no")
12853 (set_attr "latency" "0")
12854 (set_attr "length" "4")
12855 (set_attr "slot" "cop")
12856 (set_attr "slots" "p0_p1")
12857 (set_attr "stall" "none")])
12860 (define_insn "cgen_intrinsic_cpfsftbi_C3"
12861 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
12863 (match_operand:DI 1 "general_operand" "x")
12864 (match_operand:DI 2 "general_operand" "x")
12865 (match_operand:DI 3 "cgen_h_uint_3a1_immediate" "")
12867 "CGEN_ENABLE_INSN_P (472)"
12868 "cpfsftbi\\t%0,%1,%2,%3"
12869 [(set_attr "may_trap" "no")
12870 (set_attr "latency" "0")
12871 (set_attr "length" "4")
12872 (set_attr "slot" "cop")
12873 (set_attr "slots" "c3")
12874 (set_attr "stall" "none")])
12877 (define_insn "cgen_intrinsic_cpfsftbi_P0_P1"
12878 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
12880 (match_operand:DI 1 "general_operand" "x")
12881 (match_operand:DI 2 "general_operand" "x")
12882 (match_operand:DI 3 "cgen_h_uint_3a1_immediate" "")
12884 "CGEN_ENABLE_INSN_P (473)"
12885 "cpfsftbi\\t%0,%1,%2,%3"
12886 [(set_attr "may_trap" "no")
12887 (set_attr "latency" "0")
12888 (set_attr "length" "4")
12889 (set_attr "slot" "cop")
12890 (set_attr "slots" "p0_p1")
12891 (set_attr "stall" "none")])
12894 (define_insn "cgen_intrinsic_cpfacla0s1_h_P0S"
12896 (unspec_volatile:SI [
12897 (match_operand:DI 0 "general_operand" "x")
12898 (match_operand:DI 1 "general_operand" "x")
12901 (unspec_volatile:SI [
12906 (unspec_volatile:SI [
12911 (unspec_volatile:SI [
12916 (unspec_volatile:SI [
12920 "CGEN_ENABLE_INSN_P (474)"
12921 "cpfacla0s1.h\\t%0,%1"
12922 [(set_attr "may_trap" "no")
12923 (set_attr "latency" "0")
12924 (set_attr "length" "4")
12925 (set_attr "slot" "cop")
12926 (set_attr "slots" "p0s")
12927 (set_attr "stall" "none")])
12930 (define_insn "cgen_intrinsic_cpfacua0s1_h_P0S"
12932 (unspec_volatile:SI [
12933 (match_operand:DI 0 "general_operand" "x")
12934 (match_operand:DI 1 "general_operand" "x")
12937 (unspec_volatile:SI [
12942 (unspec_volatile:SI [
12947 (unspec_volatile:SI [
12952 (unspec_volatile:SI [
12956 "CGEN_ENABLE_INSN_P (475)"
12957 "cpfacua0s1.h\\t%0,%1"
12958 [(set_attr "may_trap" "no")
12959 (set_attr "latency" "0")
12960 (set_attr "length" "4")
12961 (set_attr "slot" "cop")
12962 (set_attr "slots" "p0s")
12963 (set_attr "stall" "none")])
12966 (define_insn "cgen_intrinsic_cpfaca0s1_b_P0S"
12968 (unspec_volatile:SI [
12969 (match_operand:DI 0 "general_operand" "x")
12970 (match_operand:DI 1 "general_operand" "x")
12973 (unspec_volatile:SI [
12978 (unspec_volatile:SI [
12983 (unspec_volatile:SI [
12988 (unspec_volatile:SI [
12993 (unspec_volatile:SI [
12998 (unspec_volatile:SI [
13003 (unspec_volatile:SI [
13008 (unspec_volatile:SI [
13012 "CGEN_ENABLE_INSN_P (476)"
13013 "cpfaca0s1.b\\t%0,%1"
13014 [(set_attr "may_trap" "no")
13015 (set_attr "latency" "0")
13016 (set_attr "length" "4")
13017 (set_attr "slot" "cop")
13018 (set_attr "slots" "p0s")
13019 (set_attr "stall" "none")])
13022 (define_insn "cgen_intrinsic_cpfaca0s1u_b_P0S"
13024 (unspec_volatile:SI [
13025 (match_operand:DI 0 "general_operand" "x")
13026 (match_operand:DI 1 "general_operand" "x")
13029 (unspec_volatile:SI [
13034 (unspec_volatile:SI [
13039 (unspec_volatile:SI [
13044 (unspec_volatile:SI [
13049 (unspec_volatile:SI [
13054 (unspec_volatile:SI [
13059 (unspec_volatile:SI [
13064 (unspec_volatile:SI [
13068 "CGEN_ENABLE_INSN_P (477)"
13069 "cpfaca0s1u.b\\t%0,%1"
13070 [(set_attr "may_trap" "no")
13071 (set_attr "latency" "0")
13072 (set_attr "length" "4")
13073 (set_attr "slot" "cop")
13074 (set_attr "slots" "p0s")
13075 (set_attr "stall" "none")])
13078 (define_insn "cgen_intrinsic_cpfsftbla0s1_h_P0S"
13080 (unspec_volatile:SI [
13081 (match_operand:DI 0 "general_operand" "x")
13082 (match_operand:DI 1 "general_operand" "x")
13085 (unspec_volatile:SI [
13090 (unspec_volatile:SI [
13095 (unspec_volatile:SI [
13099 "CGEN_ENABLE_INSN_P (478)"
13100 "cpfsftbla0s1.h\\t%0,%1"
13101 [(set_attr "may_trap" "no")
13102 (set_attr "latency" "0")
13103 (set_attr "length" "4")
13104 (set_attr "slot" "cop")
13105 (set_attr "slots" "p0s")
13106 (set_attr "stall" "none")])
13109 (define_insn "cgen_intrinsic_cpfsftbua0s1_h_P0S"
13111 (unspec_volatile:SI [
13112 (match_operand:DI 0 "general_operand" "x")
13113 (match_operand:DI 1 "general_operand" "x")
13116 (unspec_volatile:SI [
13121 (unspec_volatile:SI [
13126 (unspec_volatile:SI [
13130 "CGEN_ENABLE_INSN_P (479)"
13131 "cpfsftbua0s1.h\\t%0,%1"
13132 [(set_attr "may_trap" "no")
13133 (set_attr "latency" "0")
13134 (set_attr "length" "4")
13135 (set_attr "slot" "cop")
13136 (set_attr "slots" "p0s")
13137 (set_attr "stall" "none")])
13140 (define_insn "cgen_intrinsic_cpfsftba0s1_b_P0S"
13142 (unspec_volatile:SI [
13143 (match_operand:DI 0 "general_operand" "x")
13144 (match_operand:DI 1 "general_operand" "x")
13147 (unspec_volatile:SI [
13152 (unspec_volatile:SI [
13157 (unspec_volatile:SI [
13162 (unspec_volatile:SI [
13167 (unspec_volatile:SI [
13172 (unspec_volatile:SI [
13177 (unspec_volatile:SI [
13181 "CGEN_ENABLE_INSN_P (480)"
13182 "cpfsftba0s1.b\\t%0,%1"
13183 [(set_attr "may_trap" "no")
13184 (set_attr "latency" "0")
13185 (set_attr "length" "4")
13186 (set_attr "slot" "cop")
13187 (set_attr "slots" "p0s")
13188 (set_attr "stall" "none")])
13191 (define_insn "cgen_intrinsic_cpfsftba0s1u_b_P0S"
13193 (unspec_volatile:SI [
13194 (match_operand:DI 0 "general_operand" "x")
13195 (match_operand:DI 1 "general_operand" "x")
13198 (unspec_volatile:SI [
13203 (unspec_volatile:SI [
13208 (unspec_volatile:SI [
13213 (unspec_volatile:SI [
13218 (unspec_volatile:SI [
13223 (unspec_volatile:SI [
13228 (unspec_volatile:SI [
13232 "CGEN_ENABLE_INSN_P (481)"
13233 "cpfsftba0s1u.b\\t%0,%1"
13234 [(set_attr "may_trap" "no")
13235 (set_attr "latency" "0")
13236 (set_attr "length" "4")
13237 (set_attr "slot" "cop")
13238 (set_attr "slots" "p0s")
13239 (set_attr "stall" "none")])
13242 (define_insn "cgen_intrinsic_cpfacla0s0_h_P0S"
13244 (unspec_volatile:SI [
13245 (match_operand:DI 0 "general_operand" "x")
13246 (match_operand:DI 1 "general_operand" "x")
13249 (unspec_volatile:SI [
13254 (unspec_volatile:SI [
13259 (unspec_volatile:SI [
13264 (unspec_volatile:SI [
13268 "CGEN_ENABLE_INSN_P (482)"
13269 "cpfacla0s0.h\\t%0,%1"
13270 [(set_attr "may_trap" "no")
13271 (set_attr "latency" "0")
13272 (set_attr "length" "4")
13273 (set_attr "slot" "cop")
13274 (set_attr "slots" "p0s")
13275 (set_attr "stall" "none")])
13278 (define_insn "cgen_intrinsic_cpfacua0s0_h_P0S"
13280 (unspec_volatile:SI [
13281 (match_operand:DI 0 "general_operand" "x")
13282 (match_operand:DI 1 "general_operand" "x")
13285 (unspec_volatile:SI [
13290 (unspec_volatile:SI [
13295 (unspec_volatile:SI [
13300 (unspec_volatile:SI [
13304 "CGEN_ENABLE_INSN_P (483)"
13305 "cpfacua0s0.h\\t%0,%1"
13306 [(set_attr "may_trap" "no")
13307 (set_attr "latency" "0")
13308 (set_attr "length" "4")
13309 (set_attr "slot" "cop")
13310 (set_attr "slots" "p0s")
13311 (set_attr "stall" "none")])
13314 (define_insn "cgen_intrinsic_cpfaca0s0_b_P0S"
13316 (unspec_volatile:SI [
13317 (match_operand:DI 0 "general_operand" "x")
13318 (match_operand:DI 1 "general_operand" "x")
13321 (unspec_volatile:SI [
13326 (unspec_volatile:SI [
13331 (unspec_volatile:SI [
13336 (unspec_volatile:SI [
13341 (unspec_volatile:SI [
13346 (unspec_volatile:SI [
13351 (unspec_volatile:SI [
13356 (unspec_volatile:SI [
13360 "CGEN_ENABLE_INSN_P (484)"
13361 "cpfaca0s0.b\\t%0,%1"
13362 [(set_attr "may_trap" "no")
13363 (set_attr "latency" "0")
13364 (set_attr "length" "4")
13365 (set_attr "slot" "cop")
13366 (set_attr "slots" "p0s")
13367 (set_attr "stall" "none")])
13370 (define_insn "cgen_intrinsic_cpfaca0s0u_b_P0S"
13372 (unspec_volatile:SI [
13373 (match_operand:DI 0 "general_operand" "x")
13374 (match_operand:DI 1 "general_operand" "x")
13377 (unspec_volatile:SI [
13382 (unspec_volatile:SI [
13387 (unspec_volatile:SI [
13392 (unspec_volatile:SI [
13397 (unspec_volatile:SI [
13402 (unspec_volatile:SI [
13407 (unspec_volatile:SI [
13412 (unspec_volatile:SI [
13416 "CGEN_ENABLE_INSN_P (485)"
13417 "cpfaca0s0u.b\\t%0,%1"
13418 [(set_attr "may_trap" "no")
13419 (set_attr "latency" "0")
13420 (set_attr "length" "4")
13421 (set_attr "slot" "cop")
13422 (set_attr "slots" "p0s")
13423 (set_attr "stall" "none")])
13426 (define_insn "cgen_intrinsic_cpfsftbla0s0_h_P0S"
13428 (unspec_volatile:SI [
13429 (match_operand:DI 0 "general_operand" "x")
13430 (match_operand:DI 1 "general_operand" "x")
13433 (unspec_volatile:SI [
13438 (unspec_volatile:SI [
13443 (unspec_volatile:SI [
13447 "CGEN_ENABLE_INSN_P (486)"
13448 "cpfsftbla0s0.h\\t%0,%1"
13449 [(set_attr "may_trap" "no")
13450 (set_attr "latency" "0")
13451 (set_attr "length" "4")
13452 (set_attr "slot" "cop")
13453 (set_attr "slots" "p0s")
13454 (set_attr "stall" "none")])
13457 (define_insn "cgen_intrinsic_cpfsftbua0s0_h_P0S"
13459 (unspec_volatile:SI [
13460 (match_operand:DI 0 "general_operand" "x")
13461 (match_operand:DI 1 "general_operand" "x")
13464 (unspec_volatile:SI [
13469 (unspec_volatile:SI [
13474 (unspec_volatile:SI [
13478 "CGEN_ENABLE_INSN_P (487)"
13479 "cpfsftbua0s0.h\\t%0,%1"
13480 [(set_attr "may_trap" "no")
13481 (set_attr "latency" "0")
13482 (set_attr "length" "4")
13483 (set_attr "slot" "cop")
13484 (set_attr "slots" "p0s")
13485 (set_attr "stall" "none")])
13488 (define_insn "cgen_intrinsic_cpfsftba0s0_b_P0S"
13490 (unspec_volatile:SI [
13491 (match_operand:DI 0 "general_operand" "x")
13492 (match_operand:DI 1 "general_operand" "x")
13495 (unspec_volatile:SI [
13500 (unspec_volatile:SI [
13505 (unspec_volatile:SI [
13510 (unspec_volatile:SI [
13515 (unspec_volatile:SI [
13520 (unspec_volatile:SI [
13525 (unspec_volatile:SI [
13529 "CGEN_ENABLE_INSN_P (488)"
13530 "cpfsftba0s0.b\\t%0,%1"
13531 [(set_attr "may_trap" "no")
13532 (set_attr "latency" "0")
13533 (set_attr "length" "4")
13534 (set_attr "slot" "cop")
13535 (set_attr "slots" "p0s")
13536 (set_attr "stall" "none")])
13539 (define_insn "cgen_intrinsic_cpfsftba0s0u_b_P0S"
13541 (unspec_volatile:SI [
13542 (match_operand:DI 0 "general_operand" "x")
13543 (match_operand:DI 1 "general_operand" "x")
13546 (unspec_volatile:SI [
13551 (unspec_volatile:SI [
13556 (unspec_volatile:SI [
13561 (unspec_volatile:SI [
13566 (unspec_volatile:SI [
13571 (unspec_volatile:SI [
13576 (unspec_volatile:SI [
13580 "CGEN_ENABLE_INSN_P (489)"
13581 "cpfsftba0s0u.b\\t%0,%1"
13582 [(set_attr "may_trap" "no")
13583 (set_attr "latency" "0")
13584 (set_attr "length" "4")
13585 (set_attr "slot" "cop")
13586 (set_attr "slots" "p0s")
13587 (set_attr "stall" "none")])
13590 (define_insn "cgen_intrinsic_cpsllia0_P0S"
13592 (unspec_volatile:SI [
13593 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
13596 (unspec_volatile:SI [
13600 (unspec_volatile:SI [
13604 (unspec_volatile:SI [
13608 (unspec_volatile:SI [
13612 (unspec_volatile:SI [
13616 (unspec_volatile:SI [
13620 (unspec_volatile:SI [
13623 "CGEN_ENABLE_INSN_P (490)"
13625 [(set_attr "may_trap" "no")
13626 (set_attr "latency" "0")
13627 (set_attr "length" "4")
13628 (set_attr "slot" "cop")
13629 (set_attr "slots" "p0s")
13630 (set_attr "stall" "none")])
13633 (define_insn "cgen_intrinsic_cpsraia0_P0S"
13635 (unspec_volatile:SI [
13636 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
13639 (unspec_volatile:SI [
13643 (unspec_volatile:SI [
13647 (unspec_volatile:SI [
13651 (unspec_volatile:SI [
13655 (unspec_volatile:SI [
13659 (unspec_volatile:SI [
13663 (unspec_volatile:SI [
13666 "CGEN_ENABLE_INSN_P (491)"
13668 [(set_attr "may_trap" "no")
13669 (set_attr "latency" "0")
13670 (set_attr "length" "4")
13671 (set_attr "slot" "cop")
13672 (set_attr "slots" "p0s")
13673 (set_attr "stall" "none")])
13676 (define_insn "cgen_intrinsic_cpsrlia0_P0S"
13678 (unspec_volatile:SI [
13679 (match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
13682 (unspec_volatile:SI [
13686 (unspec_volatile:SI [
13690 (unspec_volatile:SI [
13694 (unspec_volatile:SI [
13698 (unspec_volatile:SI [
13702 (unspec_volatile:SI [
13706 (unspec_volatile:SI [
13709 "CGEN_ENABLE_INSN_P (492)"
13711 [(set_attr "may_trap" "no")
13712 (set_attr "latency" "0")
13713 (set_attr "length" "4")
13714 (set_attr "slot" "cop")
13715 (set_attr "slots" "p0s")
13716 (set_attr "stall" "none")])
13719 (define_insn "cgen_intrinsic_cpslla0_P0S"
13721 (unspec_volatile:SI [
13722 (match_operand:DI 0 "general_operand" "x")
13725 (unspec_volatile:SI [
13729 (unspec_volatile:SI [
13733 (unspec_volatile:SI [
13737 (unspec_volatile:SI [
13741 (unspec_volatile:SI [
13745 (unspec_volatile:SI [
13749 (unspec_volatile:SI [
13752 "CGEN_ENABLE_INSN_P (493)"
13754 [(set_attr "may_trap" "no")
13755 (set_attr "latency" "0")
13756 (set_attr "length" "4")
13757 (set_attr "slot" "cop")
13758 (set_attr "slots" "p0s")
13759 (set_attr "stall" "none")])
13762 (define_insn "cgen_intrinsic_cpsraa0_P0S"
13764 (unspec_volatile:SI [
13765 (match_operand:DI 0 "general_operand" "x")
13768 (unspec_volatile:SI [
13772 (unspec_volatile:SI [
13776 (unspec_volatile:SI [
13780 (unspec_volatile:SI [
13784 (unspec_volatile:SI [
13788 (unspec_volatile:SI [
13792 (unspec_volatile:SI [
13795 "CGEN_ENABLE_INSN_P (494)"
13797 [(set_attr "may_trap" "no")
13798 (set_attr "latency" "0")
13799 (set_attr "length" "4")
13800 (set_attr "slot" "cop")
13801 (set_attr "slots" "p0s")
13802 (set_attr "stall" "none")])
13805 (define_insn "cgen_intrinsic_cpsrla0_P0S"
13807 (unspec_volatile:SI [
13808 (match_operand:DI 0 "general_operand" "x")
13811 (unspec_volatile:SI [
13815 (unspec_volatile:SI [
13819 (unspec_volatile:SI [
13823 (unspec_volatile:SI [
13827 (unspec_volatile:SI [
13831 (unspec_volatile:SI [
13835 (unspec_volatile:SI [
13838 "CGEN_ENABLE_INSN_P (495)"
13840 [(set_attr "may_trap" "no")
13841 (set_attr "latency" "0")
13842 (set_attr "length" "4")
13843 (set_attr "slot" "cop")
13844 (set_attr "slots" "p0s")
13845 (set_attr "stall" "none")])
13848 (define_insn "cgen_intrinsic_cpaccpa0_P0S"
13850 (unspec_volatile:SI [
13854 (unspec_volatile:SI [
13858 (unspec_volatile:SI [
13862 (unspec_volatile:SI [
13866 (unspec_volatile:SI [
13870 (unspec_volatile:SI [
13874 (unspec_volatile:SI [
13878 (unspec_volatile:SI [
13881 "CGEN_ENABLE_INSN_P (496)"
13883 [(set_attr "may_trap" "no")
13884 (set_attr "latency" "0")
13885 (set_attr "length" "4")
13886 (set_attr "slot" "cop")
13887 (set_attr "slots" "p0s")
13888 (set_attr "stall" "none")])
13891 (define_insn "cgen_intrinsic_cpacsuma0_P0S"
13893 (unspec_volatile:SI [
13897 (unspec_volatile:SI [
13901 (unspec_volatile:SI [
13905 (unspec_volatile:SI [
13909 (unspec_volatile:SI [
13913 (unspec_volatile:SI [
13917 (unspec_volatile:SI [
13921 (unspec_volatile:SI [
13925 (unspec_volatile:SI [
13928 "CGEN_ENABLE_INSN_P (497)"
13930 [(set_attr "may_trap" "no")
13931 (set_attr "latency" "0")
13932 (set_attr "length" "4")
13933 (set_attr "slot" "cop")
13934 (set_attr "slots" "p0s")
13935 (set_attr "stall" "none")])
13938 (define_insn "cgen_intrinsic_cpmovhla0_w_P0S"
13939 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
13940 (unspec_volatile:DI [
13943 "CGEN_ENABLE_INSN_P (498)"
13945 [(set_attr "may_trap" "no")
13946 (set_attr "latency" "0")
13947 (set_attr "length" "4")
13948 (set_attr "slot" "cop")
13949 (set_attr "slots" "p0s")
13950 (set_attr "stall" "none")])
13953 (define_insn "cgen_intrinsic_cpmovhua0_w_P0S"
13954 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
13955 (unspec_volatile:DI [
13958 "CGEN_ENABLE_INSN_P (499)"
13960 [(set_attr "may_trap" "no")
13961 (set_attr "latency" "0")
13962 (set_attr "length" "4")
13963 (set_attr "slot" "cop")
13964 (set_attr "slots" "p0s")
13965 (set_attr "stall" "none")])
13968 (define_insn "cgen_intrinsic_cppackla0_w_P0S"
13969 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
13970 (unspec_volatile:DI [
13973 "CGEN_ENABLE_INSN_P (500)"
13975 [(set_attr "may_trap" "no")
13976 (set_attr "latency" "0")
13977 (set_attr "length" "4")
13978 (set_attr "slot" "cop")
13979 (set_attr "slots" "p0s")
13980 (set_attr "stall" "none")])
13983 (define_insn "cgen_intrinsic_cppackua0_w_P0S"
13984 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
13985 (unspec_volatile:DI [
13988 "CGEN_ENABLE_INSN_P (501)"
13990 [(set_attr "may_trap" "no")
13991 (set_attr "latency" "0")
13992 (set_attr "length" "4")
13993 (set_attr "slot" "cop")
13994 (set_attr "slots" "p0s")
13995 (set_attr "stall" "none")])
13998 (define_insn "cgen_intrinsic_cppackla0_h_P0S"
13999 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14000 (unspec_volatile:DI [
14003 "CGEN_ENABLE_INSN_P (502)"
14005 [(set_attr "may_trap" "no")
14006 (set_attr "latency" "0")
14007 (set_attr "length" "4")
14008 (set_attr "slot" "cop")
14009 (set_attr "slots" "p0s")
14010 (set_attr "stall" "none")])
14013 (define_insn "cgen_intrinsic_cppackua0_h_P0S"
14014 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14015 (unspec_volatile:DI [
14018 "CGEN_ENABLE_INSN_P (503)"
14020 [(set_attr "may_trap" "no")
14021 (set_attr "latency" "0")
14022 (set_attr "length" "4")
14023 (set_attr "slot" "cop")
14024 (set_attr "slots" "p0s")
14025 (set_attr "stall" "none")])
14028 (define_insn "cgen_intrinsic_cppacka0_b_P0S"
14029 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14030 (unspec_volatile:DI [
14033 "CGEN_ENABLE_INSN_P (504)"
14035 [(set_attr "may_trap" "no")
14036 (set_attr "latency" "0")
14037 (set_attr "length" "4")
14038 (set_attr "slot" "cop")
14039 (set_attr "slots" "p0s")
14040 (set_attr "stall" "none")])
14043 (define_insn "cgen_intrinsic_cppacka0u_b_P0S"
14044 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14045 (unspec_volatile:DI [
14048 "CGEN_ENABLE_INSN_P (505)"
14050 [(set_attr "may_trap" "no")
14051 (set_attr "latency" "0")
14052 (set_attr "length" "4")
14053 (set_attr "slot" "cop")
14054 (set_attr "slots" "p0s")
14055 (set_attr "stall" "none")])
14058 (define_insn "cgen_intrinsic_cpmovlla0_w_P0S"
14059 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14060 (unspec_volatile:DI [
14063 "CGEN_ENABLE_INSN_P (506)"
14065 [(set_attr "may_trap" "no")
14066 (set_attr "latency" "0")
14067 (set_attr "length" "4")
14068 (set_attr "slot" "cop")
14069 (set_attr "slots" "p0s")
14070 (set_attr "stall" "none")])
14073 (define_insn "cgen_intrinsic_cpmovlua0_w_P0S"
14074 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14075 (unspec_volatile:DI [
14078 "CGEN_ENABLE_INSN_P (507)"
14080 [(set_attr "may_trap" "no")
14081 (set_attr "latency" "0")
14082 (set_attr "length" "4")
14083 (set_attr "slot" "cop")
14084 (set_attr "slots" "p0s")
14085 (set_attr "stall" "none")])
14088 (define_insn "cgen_intrinsic_cpmovula0_w_P0S"
14089 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14090 (unspec_volatile:DI [
14093 "CGEN_ENABLE_INSN_P (508)"
14095 [(set_attr "may_trap" "no")
14096 (set_attr "latency" "0")
14097 (set_attr "length" "4")
14098 (set_attr "slot" "cop")
14099 (set_attr "slots" "p0s")
14100 (set_attr "stall" "none")])
14103 (define_insn "cgen_intrinsic_cpmovuua0_w_P0S"
14104 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14105 (unspec_volatile:DI [
14108 "CGEN_ENABLE_INSN_P (509)"
14110 [(set_attr "may_trap" "no")
14111 (set_attr "latency" "0")
14112 (set_attr "length" "4")
14113 (set_attr "slot" "cop")
14114 (set_attr "slots" "p0s")
14115 (set_attr "stall" "none")])
14118 (define_insn "cgen_intrinsic_cpmovla0_h_P0S"
14119 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14120 (unspec_volatile:DI [
14123 "CGEN_ENABLE_INSN_P (510)"
14125 [(set_attr "may_trap" "no")
14126 (set_attr "latency" "0")
14127 (set_attr "length" "4")
14128 (set_attr "slot" "cop")
14129 (set_attr "slots" "p0s")
14130 (set_attr "stall" "none")])
14133 (define_insn "cgen_intrinsic_cpmovua0_h_P0S"
14134 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14135 (unspec_volatile:DI [
14138 "CGEN_ENABLE_INSN_P (511)"
14140 [(set_attr "may_trap" "no")
14141 (set_attr "latency" "0")
14142 (set_attr "length" "4")
14143 (set_attr "slot" "cop")
14144 (set_attr "slots" "p0s")
14145 (set_attr "stall" "none")])
14148 (define_insn "cgen_intrinsic_cpmova0_b_P0S"
14149 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
14150 (unspec_volatile:DI [
14153 "CGEN_ENABLE_INSN_P (512)"
14155 [(set_attr "may_trap" "no")
14156 (set_attr "latency" "0")
14157 (set_attr "length" "4")
14158 (set_attr "slot" "cop")
14159 (set_attr "slots" "p0s")
14160 (set_attr "stall" "none")])
14163 (define_insn "cgen_intrinsic_cpsetla0_w_P0S"
14165 (unspec_volatile:SI [
14166 (match_operand:DI 0 "general_operand" "x")
14167 (match_operand:DI 1 "general_operand" "x")
14170 (unspec_volatile:SI [
14175 (unspec_volatile:SI [
14180 (unspec_volatile:SI [
14184 "CGEN_ENABLE_INSN_P (513)"
14185 "cpsetla0.w\\t%0,%1"
14186 [(set_attr "may_trap" "no")
14187 (set_attr "latency" "0")
14188 (set_attr "length" "4")
14189 (set_attr "slot" "cop")
14190 (set_attr "slots" "p0s")
14191 (set_attr "stall" "none")])
14194 (define_insn "cgen_intrinsic_cpsetua0_w_P0S"
14196 (unspec_volatile:SI [
14197 (match_operand:DI 0 "general_operand" "x")
14198 (match_operand:DI 1 "general_operand" "x")
14201 (unspec_volatile:SI [
14206 (unspec_volatile:SI [
14211 (unspec_volatile:SI [
14215 "CGEN_ENABLE_INSN_P (514)"
14216 "cpsetua0.w\\t%0,%1"
14217 [(set_attr "may_trap" "no")
14218 (set_attr "latency" "0")
14219 (set_attr "length" "4")
14220 (set_attr "slot" "cop")
14221 (set_attr "slots" "p0s")
14222 (set_attr "stall" "none")])
14225 (define_insn "cgen_intrinsic_cpseta0_h_P0S"
14227 (unspec_volatile:SI [
14228 (match_operand:DI 0 "general_operand" "x")
14229 (match_operand:DI 1 "general_operand" "x")
14232 (unspec_volatile:SI [
14237 (unspec_volatile:SI [
14242 (unspec_volatile:SI [
14247 (unspec_volatile:SI [
14252 (unspec_volatile:SI [
14257 (unspec_volatile:SI [
14262 (unspec_volatile:SI [
14266 "CGEN_ENABLE_INSN_P (515)"
14267 "cpseta0.h\\t%0,%1"
14268 [(set_attr "may_trap" "no")
14269 (set_attr "latency" "0")
14270 (set_attr "length" "4")
14271 (set_attr "slot" "cop")
14272 (set_attr "slots" "p0s")
14273 (set_attr "stall" "none")])
14276 (define_insn "cgen_intrinsic_cpsadla0_h_P0S"
14278 (unspec_volatile:SI [
14279 (match_operand:DI 0 "general_operand" "x")
14280 (match_operand:DI 1 "general_operand" "x")
14283 (unspec_volatile:SI [
14288 (unspec_volatile:SI [
14293 (unspec_volatile:SI [
14298 (unspec_volatile:SI [
14302 "CGEN_ENABLE_INSN_P (516)"
14303 "cpsadla0.h\\t%0,%1"
14304 [(set_attr "may_trap" "no")
14305 (set_attr "latency" "0")
14306 (set_attr "length" "4")
14307 (set_attr "slot" "cop")
14308 (set_attr "slots" "p0s")
14309 (set_attr "stall" "none")])
14312 (define_insn "cgen_intrinsic_cpsadua0_h_P0S"
14314 (unspec_volatile:SI [
14315 (match_operand:DI 0 "general_operand" "x")
14316 (match_operand:DI 1 "general_operand" "x")
14319 (unspec_volatile:SI [
14324 (unspec_volatile:SI [
14329 (unspec_volatile:SI [
14334 (unspec_volatile:SI [
14338 "CGEN_ENABLE_INSN_P (517)"
14339 "cpsadua0.h\\t%0,%1"
14340 [(set_attr "may_trap" "no")
14341 (set_attr "latency" "0")
14342 (set_attr "length" "4")
14343 (set_attr "slot" "cop")
14344 (set_attr "slots" "p0s")
14345 (set_attr "stall" "none")])
14348 (define_insn "cgen_intrinsic_cpsada0_b_P0S"
14350 (unspec_volatile:SI [
14351 (match_operand:DI 0 "general_operand" "x")
14352 (match_operand:DI 1 "general_operand" "x")
14355 (unspec_volatile:SI [
14360 (unspec_volatile:SI [
14365 (unspec_volatile:SI [
14370 (unspec_volatile:SI [
14375 (unspec_volatile:SI [
14380 (unspec_volatile:SI [
14385 (unspec_volatile:SI [
14390 (unspec_volatile:SI [
14394 "CGEN_ENABLE_INSN_P (518)"
14395 "cpsada0.b\\t%0,%1"
14396 [(set_attr "may_trap" "no")
14397 (set_attr "latency" "0")
14398 (set_attr "length" "4")
14399 (set_attr "slot" "cop")
14400 (set_attr "slots" "p0s")
14401 (set_attr "stall" "none")])
14404 (define_insn "cgen_intrinsic_cpsada0u_b_P0S"
14406 (unspec_volatile:SI [
14407 (match_operand:DI 0 "general_operand" "x")
14408 (match_operand:DI 1 "general_operand" "x")
14411 (unspec_volatile:SI [
14416 (unspec_volatile:SI [
14421 (unspec_volatile:SI [
14426 (unspec_volatile:SI [
14431 (unspec_volatile:SI [
14436 (unspec_volatile:SI [
14441 (unspec_volatile:SI [
14446 (unspec_volatile:SI [
14450 "CGEN_ENABLE_INSN_P (519)"
14451 "cpsada0u.b\\t%0,%1"
14452 [(set_attr "may_trap" "no")
14453 (set_attr "latency" "0")
14454 (set_attr "length" "4")
14455 (set_attr "slot" "cop")
14456 (set_attr "slots" "p0s")
14457 (set_attr "stall" "none")])
14460 (define_insn "cgen_intrinsic_cpabsla0_h_P0S"
14462 (unspec_volatile:SI [
14463 (match_operand:DI 0 "general_operand" "x")
14464 (match_operand:DI 1 "general_operand" "x")
14467 (unspec_volatile:SI [
14472 (unspec_volatile:SI [
14477 (unspec_volatile:SI [
14481 "CGEN_ENABLE_INSN_P (520)"
14482 "cpabsla0.h\\t%0,%1"
14483 [(set_attr "may_trap" "no")
14484 (set_attr "latency" "0")
14485 (set_attr "length" "4")
14486 (set_attr "slot" "cop")
14487 (set_attr "slots" "p0s")
14488 (set_attr "stall" "none")])
14491 (define_insn "cgen_intrinsic_cpabsua0_h_P0S"
14493 (unspec_volatile:SI [
14494 (match_operand:DI 0 "general_operand" "x")
14495 (match_operand:DI 1 "general_operand" "x")
14498 (unspec_volatile:SI [
14503 (unspec_volatile:SI [
14508 (unspec_volatile:SI [
14512 "CGEN_ENABLE_INSN_P (521)"
14513 "cpabsua0.h\\t%0,%1"
14514 [(set_attr "may_trap" "no")
14515 (set_attr "latency" "0")
14516 (set_attr "length" "4")
14517 (set_attr "slot" "cop")
14518 (set_attr "slots" "p0s")
14519 (set_attr "stall" "none")])
14522 (define_insn "cgen_intrinsic_cpabsa0_b_P0S"
14524 (unspec_volatile:SI [
14525 (match_operand:DI 0 "general_operand" "x")
14526 (match_operand:DI 1 "general_operand" "x")
14529 (unspec_volatile:SI [
14534 (unspec_volatile:SI [
14539 (unspec_volatile:SI [
14544 (unspec_volatile:SI [
14549 (unspec_volatile:SI [
14554 (unspec_volatile:SI [
14559 (unspec_volatile:SI [
14563 "CGEN_ENABLE_INSN_P (522)"
14564 "cpabsa0.b\\t%0,%1"
14565 [(set_attr "may_trap" "no")
14566 (set_attr "latency" "0")
14567 (set_attr "length" "4")
14568 (set_attr "slot" "cop")
14569 (set_attr "slots" "p0s")
14570 (set_attr "stall" "none")])
14573 (define_insn "cgen_intrinsic_cpabsa0u_b_P0S"
14575 (unspec_volatile:SI [
14576 (match_operand:DI 0 "general_operand" "x")
14577 (match_operand:DI 1 "general_operand" "x")
14580 (unspec_volatile:SI [
14585 (unspec_volatile:SI [
14590 (unspec_volatile:SI [
14595 (unspec_volatile:SI [
14600 (unspec_volatile:SI [
14605 (unspec_volatile:SI [
14610 (unspec_volatile:SI [
14614 "CGEN_ENABLE_INSN_P (523)"
14615 "cpabsa0u.b\\t%0,%1"
14616 [(set_attr "may_trap" "no")
14617 (set_attr "latency" "0")
14618 (set_attr "length" "4")
14619 (set_attr "slot" "cop")
14620 (set_attr "slots" "p0s")
14621 (set_attr "stall" "none")])
14624 (define_insn "cgen_intrinsic_cpsubacla0_h_P0S"
14626 (unspec_volatile:SI [
14627 (match_operand:DI 0 "general_operand" "x")
14628 (match_operand:DI 1 "general_operand" "x")
14631 (unspec_volatile:SI [
14636 (unspec_volatile:SI [
14641 (unspec_volatile:SI [
14646 (unspec_volatile:SI [
14650 "CGEN_ENABLE_INSN_P (524)"
14651 "cpsubacla0.h\\t%0,%1"
14652 [(set_attr "may_trap" "no")
14653 (set_attr "latency" "0")
14654 (set_attr "length" "4")
14655 (set_attr "slot" "cop")
14656 (set_attr "slots" "p0s")
14657 (set_attr "stall" "none")])
14660 (define_insn "cgen_intrinsic_cpsubacua0_h_P0S"
14662 (unspec_volatile:SI [
14663 (match_operand:DI 0 "general_operand" "x")
14664 (match_operand:DI 1 "general_operand" "x")
14667 (unspec_volatile:SI [
14672 (unspec_volatile:SI [
14677 (unspec_volatile:SI [
14682 (unspec_volatile:SI [
14686 "CGEN_ENABLE_INSN_P (525)"
14687 "cpsubacua0.h\\t%0,%1"
14688 [(set_attr "may_trap" "no")
14689 (set_attr "latency" "0")
14690 (set_attr "length" "4")
14691 (set_attr "slot" "cop")
14692 (set_attr "slots" "p0s")
14693 (set_attr "stall" "none")])
14696 (define_insn "cgen_intrinsic_cpsubaca0_b_P0S"
14698 (unspec_volatile:SI [
14699 (match_operand:DI 0 "general_operand" "x")
14700 (match_operand:DI 1 "general_operand" "x")
14703 (unspec_volatile:SI [
14708 (unspec_volatile:SI [
14713 (unspec_volatile:SI [
14718 (unspec_volatile:SI [
14723 (unspec_volatile:SI [
14728 (unspec_volatile:SI [
14733 (unspec_volatile:SI [
14738 (unspec_volatile:SI [
14742 "CGEN_ENABLE_INSN_P (526)"
14743 "cpsubaca0.b\\t%0,%1"
14744 [(set_attr "may_trap" "no")
14745 (set_attr "latency" "0")
14746 (set_attr "length" "4")
14747 (set_attr "slot" "cop")
14748 (set_attr "slots" "p0s")
14749 (set_attr "stall" "none")])
14752 (define_insn "cgen_intrinsic_cpsubaca0u_b_P0S"
14754 (unspec_volatile:SI [
14755 (match_operand:DI 0 "general_operand" "x")
14756 (match_operand:DI 1 "general_operand" "x")
14759 (unspec_volatile:SI [
14764 (unspec_volatile:SI [
14769 (unspec_volatile:SI [
14774 (unspec_volatile:SI [
14779 (unspec_volatile:SI [
14784 (unspec_volatile:SI [
14789 (unspec_volatile:SI [
14794 (unspec_volatile:SI [
14798 "CGEN_ENABLE_INSN_P (527)"
14799 "cpsubaca0u.b\\t%0,%1"
14800 [(set_attr "may_trap" "no")
14801 (set_attr "latency" "0")
14802 (set_attr "length" "4")
14803 (set_attr "slot" "cop")
14804 (set_attr "slots" "p0s")
14805 (set_attr "stall" "none")])
14808 (define_insn "cgen_intrinsic_cpsubla0_h_P0S"
14810 (unspec_volatile:SI [
14811 (match_operand:DI 0 "general_operand" "x")
14812 (match_operand:DI 1 "general_operand" "x")
14815 (unspec_volatile:SI [
14820 (unspec_volatile:SI [
14825 (unspec_volatile:SI [
14829 "CGEN_ENABLE_INSN_P (528)"
14830 "cpsubla0.h\\t%0,%1"
14831 [(set_attr "may_trap" "no")
14832 (set_attr "latency" "0")
14833 (set_attr "length" "4")
14834 (set_attr "slot" "cop")
14835 (set_attr "slots" "p0s")
14836 (set_attr "stall" "none")])
14839 (define_insn "cgen_intrinsic_cpsubua0_h_P0S"
14841 (unspec_volatile:SI [
14842 (match_operand:DI 0 "general_operand" "x")
14843 (match_operand:DI 1 "general_operand" "x")
14846 (unspec_volatile:SI [
14851 (unspec_volatile:SI [
14856 (unspec_volatile:SI [
14860 "CGEN_ENABLE_INSN_P (529)"
14861 "cpsubua0.h\\t%0,%1"
14862 [(set_attr "may_trap" "no")
14863 (set_attr "latency" "0")
14864 (set_attr "length" "4")
14865 (set_attr "slot" "cop")
14866 (set_attr "slots" "p0s")
14867 (set_attr "stall" "none")])
14870 (define_insn "cgen_intrinsic_cpsuba0_b_P0S"
14872 (unspec_volatile:SI [
14873 (match_operand:DI 0 "general_operand" "x")
14874 (match_operand:DI 1 "general_operand" "x")
14877 (unspec_volatile:SI [
14882 (unspec_volatile:SI [
14887 (unspec_volatile:SI [
14892 (unspec_volatile:SI [
14897 (unspec_volatile:SI [
14902 (unspec_volatile:SI [
14907 (unspec_volatile:SI [
14911 "CGEN_ENABLE_INSN_P (530)"
14912 "cpsuba0.b\\t%0,%1"
14913 [(set_attr "may_trap" "no")
14914 (set_attr "latency" "0")
14915 (set_attr "length" "4")
14916 (set_attr "slot" "cop")
14917 (set_attr "slots" "p0s")
14918 (set_attr "stall" "none")])
14921 (define_insn "cgen_intrinsic_cpsuba0u_b_P0S"
14923 (unspec_volatile:SI [
14924 (match_operand:DI 0 "general_operand" "x")
14925 (match_operand:DI 1 "general_operand" "x")
14928 (unspec_volatile:SI [
14933 (unspec_volatile:SI [
14938 (unspec_volatile:SI [
14943 (unspec_volatile:SI [
14948 (unspec_volatile:SI [
14953 (unspec_volatile:SI [
14958 (unspec_volatile:SI [
14962 "CGEN_ENABLE_INSN_P (531)"
14963 "cpsuba0u.b\\t%0,%1"
14964 [(set_attr "may_trap" "no")
14965 (set_attr "latency" "0")
14966 (set_attr "length" "4")
14967 (set_attr "slot" "cop")
14968 (set_attr "slots" "p0s")
14969 (set_attr "stall" "none")])
14972 (define_insn "cgen_intrinsic_cpaddacla0_h_P0S"
14974 (unspec_volatile:SI [
14975 (match_operand:DI 0 "general_operand" "x")
14976 (match_operand:DI 1 "general_operand" "x")
14979 (unspec_volatile:SI [
14984 (unspec_volatile:SI [
14989 (unspec_volatile:SI [
14994 (unspec_volatile:SI [
14998 "CGEN_ENABLE_INSN_P (532)"
14999 "cpaddacla0.h\\t%0,%1"
15000 [(set_attr "may_trap" "no")
15001 (set_attr "latency" "0")
15002 (set_attr "length" "4")
15003 (set_attr "slot" "cop")
15004 (set_attr "slots" "p0s")
15005 (set_attr "stall" "none")])
15008 (define_insn "cgen_intrinsic_cpaddacua0_h_P0S"
15010 (unspec_volatile:SI [
15011 (match_operand:DI 0 "general_operand" "x")
15012 (match_operand:DI 1 "general_operand" "x")
15015 (unspec_volatile:SI [
15020 (unspec_volatile:SI [
15025 (unspec_volatile:SI [
15030 (unspec_volatile:SI [
15034 "CGEN_ENABLE_INSN_P (533)"
15035 "cpaddacua0.h\\t%0,%1"
15036 [(set_attr "may_trap" "no")
15037 (set_attr "latency" "0")
15038 (set_attr "length" "4")
15039 (set_attr "slot" "cop")
15040 (set_attr "slots" "p0s")
15041 (set_attr "stall" "none")])
15044 (define_insn "cgen_intrinsic_cpaddaca0_b_P0S"
15046 (unspec_volatile:SI [
15047 (match_operand:DI 0 "general_operand" "x")
15048 (match_operand:DI 1 "general_operand" "x")
15051 (unspec_volatile:SI [
15056 (unspec_volatile:SI [
15061 (unspec_volatile:SI [
15066 (unspec_volatile:SI [
15071 (unspec_volatile:SI [
15076 (unspec_volatile:SI [
15081 (unspec_volatile:SI [
15086 (unspec_volatile:SI [
15090 "CGEN_ENABLE_INSN_P (534)"
15091 "cpaddaca0.b\\t%0,%1"
15092 [(set_attr "may_trap" "no")
15093 (set_attr "latency" "0")
15094 (set_attr "length" "4")
15095 (set_attr "slot" "cop")
15096 (set_attr "slots" "p0s")
15097 (set_attr "stall" "none")])
15100 (define_insn "cgen_intrinsic_cpaddaca0u_b_P0S"
15102 (unspec_volatile:SI [
15103 (match_operand:DI 0 "general_operand" "x")
15104 (match_operand:DI 1 "general_operand" "x")
15107 (unspec_volatile:SI [
15112 (unspec_volatile:SI [
15117 (unspec_volatile:SI [
15122 (unspec_volatile:SI [
15127 (unspec_volatile:SI [
15132 (unspec_volatile:SI [
15137 (unspec_volatile:SI [
15142 (unspec_volatile:SI [
15146 "CGEN_ENABLE_INSN_P (535)"
15147 "cpaddaca0u.b\\t%0,%1"
15148 [(set_attr "may_trap" "no")
15149 (set_attr "latency" "0")
15150 (set_attr "length" "4")
15151 (set_attr "slot" "cop")
15152 (set_attr "slots" "p0s")
15153 (set_attr "stall" "none")])
15156 (define_insn "cgen_intrinsic_cpaddla0_h_P0S"
15158 (unspec_volatile:SI [
15159 (match_operand:DI 0 "general_operand" "x")
15160 (match_operand:DI 1 "general_operand" "x")
15163 (unspec_volatile:SI [
15168 (unspec_volatile:SI [
15173 (unspec_volatile:SI [
15177 "CGEN_ENABLE_INSN_P (536)"
15178 "cpaddla0.h\\t%0,%1"
15179 [(set_attr "may_trap" "no")
15180 (set_attr "latency" "0")
15181 (set_attr "length" "4")
15182 (set_attr "slot" "cop")
15183 (set_attr "slots" "p0s")
15184 (set_attr "stall" "none")])
15187 (define_insn "cgen_intrinsic_cpaddua0_h_P0S"
15189 (unspec_volatile:SI [
15190 (match_operand:DI 0 "general_operand" "x")
15191 (match_operand:DI 1 "general_operand" "x")
15194 (unspec_volatile:SI [
15199 (unspec_volatile:SI [
15204 (unspec_volatile:SI [
15208 "CGEN_ENABLE_INSN_P (537)"
15209 "cpaddua0.h\\t%0,%1"
15210 [(set_attr "may_trap" "no")
15211 (set_attr "latency" "0")
15212 (set_attr "length" "4")
15213 (set_attr "slot" "cop")
15214 (set_attr "slots" "p0s")
15215 (set_attr "stall" "none")])
15218 (define_insn "cgen_intrinsic_cpadda0_b_P0S"
15220 (unspec_volatile:SI [
15221 (match_operand:DI 0 "general_operand" "x")
15222 (match_operand:DI 1 "general_operand" "x")
15225 (unspec_volatile:SI [
15230 (unspec_volatile:SI [
15235 (unspec_volatile:SI [
15240 (unspec_volatile:SI [
15245 (unspec_volatile:SI [
15250 (unspec_volatile:SI [
15255 (unspec_volatile:SI [
15259 "CGEN_ENABLE_INSN_P (538)"
15260 "cpadda0.b\\t%0,%1"
15261 [(set_attr "may_trap" "no")
15262 (set_attr "latency" "0")
15263 (set_attr "length" "4")
15264 (set_attr "slot" "cop")
15265 (set_attr "slots" "p0s")
15266 (set_attr "stall" "none")])
15269 (define_insn "cgen_intrinsic_cpadda0u_b_P0S"
15271 (unspec_volatile:SI [
15272 (match_operand:DI 0 "general_operand" "x")
15273 (match_operand:DI 1 "general_operand" "x")
15276 (unspec_volatile:SI [
15281 (unspec_volatile:SI [
15286 (unspec_volatile:SI [
15291 (unspec_volatile:SI [
15296 (unspec_volatile:SI [
15301 (unspec_volatile:SI [
15306 (unspec_volatile:SI [
15310 "CGEN_ENABLE_INSN_P (539)"
15311 "cpadda0u.b\\t%0,%1"
15312 [(set_attr "may_trap" "no")
15313 (set_attr "latency" "0")
15314 (set_attr "length" "4")
15315 (set_attr "slot" "cop")
15316 (set_attr "slots" "p0s")
15317 (set_attr "stall" "none")])
15320 (define_insn "cgen_intrinsic_cpcmpge_w_C3"
15322 (unspec_volatile:SI [
15323 (match_operand:DI 0 "general_operand" "x")
15324 (match_operand:DI 1 "general_operand" "x")
15326 "CGEN_ENABLE_INSN_P (540)"
15327 "cpcmpge.w\\t%0,%1"
15328 [(set_attr "may_trap" "no")
15329 (set_attr "latency" "0")
15330 (set_attr "length" "4")
15331 (set_attr "slot" "cop")
15332 (set_attr "slots" "c3")
15333 (set_attr "stall" "none")])
15336 (define_insn "cgen_intrinsic_cpcmpge_w_P0S_P1"
15338 (unspec_volatile:SI [
15339 (match_operand:DI 0 "general_operand" "x")
15340 (match_operand:DI 1 "general_operand" "x")
15342 "CGEN_ENABLE_INSN_P (541)"
15343 "cpcmpge.w\\t%0,%1"
15344 [(set_attr "may_trap" "no")
15345 (set_attr "latency" "0")
15346 (set_attr "length" "4")
15347 (set_attr "slot" "cop")
15348 (set_attr "slots" "p0s_p1")
15349 (set_attr "stall" "none")])
15352 (define_insn "cgen_intrinsic_cpcmpgeu_w_C3"
15354 (unspec_volatile:SI [
15355 (match_operand:DI 0 "general_operand" "x")
15356 (match_operand:DI 1 "general_operand" "x")
15358 "CGEN_ENABLE_INSN_P (542)"
15359 "cpcmpgeu.w\\t%0,%1"
15360 [(set_attr "may_trap" "no")
15361 (set_attr "latency" "0")
15362 (set_attr "length" "4")
15363 (set_attr "slot" "cop")
15364 (set_attr "slots" "c3")
15365 (set_attr "stall" "none")])
15368 (define_insn "cgen_intrinsic_cpcmpgeu_w_P0S_P1"
15370 (unspec_volatile:SI [
15371 (match_operand:DI 0 "general_operand" "x")
15372 (match_operand:DI 1 "general_operand" "x")
15374 "CGEN_ENABLE_INSN_P (543)"
15375 "cpcmpgeu.w\\t%0,%1"
15376 [(set_attr "may_trap" "no")
15377 (set_attr "latency" "0")
15378 (set_attr "length" "4")
15379 (set_attr "slot" "cop")
15380 (set_attr "slots" "p0s_p1")
15381 (set_attr "stall" "none")])
15384 (define_insn "cgen_intrinsic_cpcmpge_h_C3"
15386 (unspec_volatile:SI [
15387 (match_operand:DI 0 "general_operand" "x")
15388 (match_operand:DI 1 "general_operand" "x")
15390 "CGEN_ENABLE_INSN_P (544)"
15391 "cpcmpge.h\\t%0,%1"
15392 [(set_attr "may_trap" "no")
15393 (set_attr "latency" "0")
15394 (set_attr "length" "4")
15395 (set_attr "slot" "cop")
15396 (set_attr "slots" "c3")
15397 (set_attr "stall" "none")])
15400 (define_insn "cgen_intrinsic_cpcmpge_h_P0S_P1"
15402 (unspec_volatile:SI [
15403 (match_operand:DI 0 "general_operand" "x")
15404 (match_operand:DI 1 "general_operand" "x")
15406 "CGEN_ENABLE_INSN_P (545)"
15407 "cpcmpge.h\\t%0,%1"
15408 [(set_attr "may_trap" "no")
15409 (set_attr "latency" "0")
15410 (set_attr "length" "4")
15411 (set_attr "slot" "cop")
15412 (set_attr "slots" "p0s_p1")
15413 (set_attr "stall" "none")])
15416 (define_insn "cgen_intrinsic_cpcmpge_b_C3"
15418 (unspec_volatile:SI [
15419 (match_operand:DI 0 "general_operand" "x")
15420 (match_operand:DI 1 "general_operand" "x")
15422 "CGEN_ENABLE_INSN_P (546)"
15423 "cpcmpge.b\\t%0,%1"
15424 [(set_attr "may_trap" "no")
15425 (set_attr "latency" "0")
15426 (set_attr "length" "4")
15427 (set_attr "slot" "cop")
15428 (set_attr "slots" "c3")
15429 (set_attr "stall" "none")])
15432 (define_insn "cgen_intrinsic_cpcmpge_b_P0S_P1"
15434 (unspec_volatile:SI [
15435 (match_operand:DI 0 "general_operand" "x")
15436 (match_operand:DI 1 "general_operand" "x")
15438 "CGEN_ENABLE_INSN_P (547)"
15439 "cpcmpge.b\\t%0,%1"
15440 [(set_attr "may_trap" "no")
15441 (set_attr "latency" "0")
15442 (set_attr "length" "4")
15443 (set_attr "slot" "cop")
15444 (set_attr "slots" "p0s_p1")
15445 (set_attr "stall" "none")])
15448 (define_insn "cgen_intrinsic_cpcmpgeu_b_C3"
15450 (unspec_volatile:SI [
15451 (match_operand:DI 0 "general_operand" "x")
15452 (match_operand:DI 1 "general_operand" "x")
15454 "CGEN_ENABLE_INSN_P (548)"
15455 "cpcmpgeu.b\\t%0,%1"
15456 [(set_attr "may_trap" "no")
15457 (set_attr "latency" "0")
15458 (set_attr "length" "4")
15459 (set_attr "slot" "cop")
15460 (set_attr "slots" "c3")
15461 (set_attr "stall" "none")])
15464 (define_insn "cgen_intrinsic_cpcmpgeu_b_P0S_P1"
15466 (unspec_volatile:SI [
15467 (match_operand:DI 0 "general_operand" "x")
15468 (match_operand:DI 1 "general_operand" "x")
15470 "CGEN_ENABLE_INSN_P (549)"
15471 "cpcmpgeu.b\\t%0,%1"
15472 [(set_attr "may_trap" "no")
15473 (set_attr "latency" "0")
15474 (set_attr "length" "4")
15475 (set_attr "slot" "cop")
15476 (set_attr "slots" "p0s_p1")
15477 (set_attr "stall" "none")])
15480 (define_insn "cgen_intrinsic_cpcmpgt_w_C3"
15482 (unspec_volatile:SI [
15483 (match_operand:DI 0 "general_operand" "x")
15484 (match_operand:DI 1 "general_operand" "x")
15486 "CGEN_ENABLE_INSN_P (550)"
15487 "cpcmpgt.w\\t%0,%1"
15488 [(set_attr "may_trap" "no")
15489 (set_attr "latency" "0")
15490 (set_attr "length" "4")
15491 (set_attr "slot" "cop")
15492 (set_attr "slots" "c3")
15493 (set_attr "stall" "none")])
15496 (define_insn "cgen_intrinsic_cpcmpgt_w_P0S_P1"
15498 (unspec_volatile:SI [
15499 (match_operand:DI 0 "general_operand" "x")
15500 (match_operand:DI 1 "general_operand" "x")
15502 "CGEN_ENABLE_INSN_P (551)"
15503 "cpcmpgt.w\\t%0,%1"
15504 [(set_attr "may_trap" "no")
15505 (set_attr "latency" "0")
15506 (set_attr "length" "4")
15507 (set_attr "slot" "cop")
15508 (set_attr "slots" "p0s_p1")
15509 (set_attr "stall" "none")])
15512 (define_insn "cgen_intrinsic_cpcmpgtu_w_C3"
15514 (unspec_volatile:SI [
15515 (match_operand:DI 0 "general_operand" "x")
15516 (match_operand:DI 1 "general_operand" "x")
15518 "CGEN_ENABLE_INSN_P (552)"
15519 "cpcmpgtu.w\\t%0,%1"
15520 [(set_attr "may_trap" "no")
15521 (set_attr "latency" "0")
15522 (set_attr "length" "4")
15523 (set_attr "slot" "cop")
15524 (set_attr "slots" "c3")
15525 (set_attr "stall" "none")])
15528 (define_insn "cgen_intrinsic_cpcmpgtu_w_P0S_P1"
15530 (unspec_volatile:SI [
15531 (match_operand:DI 0 "general_operand" "x")
15532 (match_operand:DI 1 "general_operand" "x")
15534 "CGEN_ENABLE_INSN_P (553)"
15535 "cpcmpgtu.w\\t%0,%1"
15536 [(set_attr "may_trap" "no")
15537 (set_attr "latency" "0")
15538 (set_attr "length" "4")
15539 (set_attr "slot" "cop")
15540 (set_attr "slots" "p0s_p1")
15541 (set_attr "stall" "none")])
15544 (define_insn "cgen_intrinsic_cpcmpgt_h_C3"
15546 (unspec_volatile:SI [
15547 (match_operand:DI 0 "general_operand" "x")
15548 (match_operand:DI 1 "general_operand" "x")
15550 "CGEN_ENABLE_INSN_P (554)"
15551 "cpcmpgt.h\\t%0,%1"
15552 [(set_attr "may_trap" "no")
15553 (set_attr "latency" "0")
15554 (set_attr "length" "4")
15555 (set_attr "slot" "cop")
15556 (set_attr "slots" "c3")
15557 (set_attr "stall" "none")])
15560 (define_insn "cgen_intrinsic_cpcmpgt_h_P0S_P1"
15562 (unspec_volatile:SI [
15563 (match_operand:DI 0 "general_operand" "x")
15564 (match_operand:DI 1 "general_operand" "x")
15566 "CGEN_ENABLE_INSN_P (555)"
15567 "cpcmpgt.h\\t%0,%1"
15568 [(set_attr "may_trap" "no")
15569 (set_attr "latency" "0")
15570 (set_attr "length" "4")
15571 (set_attr "slot" "cop")
15572 (set_attr "slots" "p0s_p1")
15573 (set_attr "stall" "none")])
15576 (define_insn "cgen_intrinsic_cpcmpgt_b_C3"
15578 (unspec_volatile:SI [
15579 (match_operand:DI 0 "general_operand" "x")
15580 (match_operand:DI 1 "general_operand" "x")
15582 "CGEN_ENABLE_INSN_P (556)"
15583 "cpcmpgt.b\\t%0,%1"
15584 [(set_attr "may_trap" "no")
15585 (set_attr "latency" "0")
15586 (set_attr "length" "4")
15587 (set_attr "slot" "cop")
15588 (set_attr "slots" "c3")
15589 (set_attr "stall" "none")])
15592 (define_insn "cgen_intrinsic_cpcmpgt_b_P0S_P1"
15594 (unspec_volatile:SI [
15595 (match_operand:DI 0 "general_operand" "x")
15596 (match_operand:DI 1 "general_operand" "x")
15598 "CGEN_ENABLE_INSN_P (557)"
15599 "cpcmpgt.b\\t%0,%1"
15600 [(set_attr "may_trap" "no")
15601 (set_attr "latency" "0")
15602 (set_attr "length" "4")
15603 (set_attr "slot" "cop")
15604 (set_attr "slots" "p0s_p1")
15605 (set_attr "stall" "none")])
15608 (define_insn "cgen_intrinsic_cpcmpgtu_b_C3"
15610 (unspec_volatile:SI [
15611 (match_operand:DI 0 "general_operand" "x")
15612 (match_operand:DI 1 "general_operand" "x")
15614 "CGEN_ENABLE_INSN_P (558)"
15615 "cpcmpgtu.b\\t%0,%1"
15616 [(set_attr "may_trap" "no")
15617 (set_attr "latency" "0")
15618 (set_attr "length" "4")
15619 (set_attr "slot" "cop")
15620 (set_attr "slots" "c3")
15621 (set_attr "stall" "none")])
15624 (define_insn "cgen_intrinsic_cpcmpgtu_b_P0S_P1"
15626 (unspec_volatile:SI [
15627 (match_operand:DI 0 "general_operand" "x")
15628 (match_operand:DI 1 "general_operand" "x")
15630 "CGEN_ENABLE_INSN_P (559)"
15631 "cpcmpgtu.b\\t%0,%1"
15632 [(set_attr "may_trap" "no")
15633 (set_attr "latency" "0")
15634 (set_attr "length" "4")
15635 (set_attr "slot" "cop")
15636 (set_attr "slots" "p0s_p1")
15637 (set_attr "stall" "none")])
15640 (define_insn "cgen_intrinsic_cpcmpne_w_C3"
15642 (unspec_volatile:SI [
15643 (match_operand:DI 0 "general_operand" "x")
15644 (match_operand:DI 1 "general_operand" "x")
15646 "CGEN_ENABLE_INSN_P (560)"
15647 "cpcmpne.w\\t%0,%1"
15648 [(set_attr "may_trap" "no")
15649 (set_attr "latency" "0")
15650 (set_attr "length" "4")
15651 (set_attr "slot" "cop")
15652 (set_attr "slots" "c3")
15653 (set_attr "stall" "none")])
15656 (define_insn "cgen_intrinsic_cpcmpne_w_P0S_P1"
15658 (unspec_volatile:SI [
15659 (match_operand:DI 0 "general_operand" "x")
15660 (match_operand:DI 1 "general_operand" "x")
15662 "CGEN_ENABLE_INSN_P (561)"
15663 "cpcmpne.w\\t%0,%1"
15664 [(set_attr "may_trap" "no")
15665 (set_attr "latency" "0")
15666 (set_attr "length" "4")
15667 (set_attr "slot" "cop")
15668 (set_attr "slots" "p0s_p1")
15669 (set_attr "stall" "none")])
15672 (define_insn "cgen_intrinsic_cpcmpne_h_C3"
15674 (unspec_volatile:SI [
15675 (match_operand:DI 0 "general_operand" "x")
15676 (match_operand:DI 1 "general_operand" "x")
15678 "CGEN_ENABLE_INSN_P (562)"
15679 "cpcmpne.h\\t%0,%1"
15680 [(set_attr "may_trap" "no")
15681 (set_attr "latency" "0")
15682 (set_attr "length" "4")
15683 (set_attr "slot" "cop")
15684 (set_attr "slots" "c3")
15685 (set_attr "stall" "none")])
15688 (define_insn "cgen_intrinsic_cpcmpne_h_P0S_P1"
15690 (unspec_volatile:SI [
15691 (match_operand:DI 0 "general_operand" "x")
15692 (match_operand:DI 1 "general_operand" "x")
15694 "CGEN_ENABLE_INSN_P (563)"
15695 "cpcmpne.h\\t%0,%1"
15696 [(set_attr "may_trap" "no")
15697 (set_attr "latency" "0")
15698 (set_attr "length" "4")
15699 (set_attr "slot" "cop")
15700 (set_attr "slots" "p0s_p1")
15701 (set_attr "stall" "none")])
15704 (define_insn "cgen_intrinsic_cpcmpne_b_C3"
15706 (unspec_volatile:SI [
15707 (match_operand:DI 0 "general_operand" "x")
15708 (match_operand:DI 1 "general_operand" "x")
15710 "CGEN_ENABLE_INSN_P (564)"
15711 "cpcmpne.b\\t%0,%1"
15712 [(set_attr "may_trap" "no")
15713 (set_attr "latency" "0")
15714 (set_attr "length" "4")
15715 (set_attr "slot" "cop")
15716 (set_attr "slots" "c3")
15717 (set_attr "stall" "none")])
15720 (define_insn "cgen_intrinsic_cpcmpne_b_P0S_P1"
15722 (unspec_volatile:SI [
15723 (match_operand:DI 0 "general_operand" "x")
15724 (match_operand:DI 1 "general_operand" "x")
15726 "CGEN_ENABLE_INSN_P (565)"
15727 "cpcmpne.b\\t%0,%1"
15728 [(set_attr "may_trap" "no")
15729 (set_attr "latency" "0")
15730 (set_attr "length" "4")
15731 (set_attr "slot" "cop")
15732 (set_attr "slots" "p0s_p1")
15733 (set_attr "stall" "none")])
15736 (define_insn "cgen_intrinsic_cpcmpeq_w_C3"
15738 (unspec_volatile:SI [
15739 (match_operand:DI 0 "general_operand" "x")
15740 (match_operand:DI 1 "general_operand" "x")
15742 "CGEN_ENABLE_INSN_P (566)"
15743 "cpcmpeq.w\\t%0,%1"
15744 [(set_attr "may_trap" "no")
15745 (set_attr "latency" "0")
15746 (set_attr "length" "4")
15747 (set_attr "slot" "cop")
15748 (set_attr "slots" "c3")
15749 (set_attr "stall" "none")])
15752 (define_insn "cgen_intrinsic_cpcmpeq_w_P0S_P1"
15754 (unspec_volatile:SI [
15755 (match_operand:DI 0 "general_operand" "x")
15756 (match_operand:DI 1 "general_operand" "x")
15758 "CGEN_ENABLE_INSN_P (567)"
15759 "cpcmpeq.w\\t%0,%1"
15760 [(set_attr "may_trap" "no")
15761 (set_attr "latency" "0")
15762 (set_attr "length" "4")
15763 (set_attr "slot" "cop")
15764 (set_attr "slots" "p0s_p1")
15765 (set_attr "stall" "none")])
15768 (define_insn "cgen_intrinsic_cpcmpeq_h_C3"
15770 (unspec_volatile:SI [
15771 (match_operand:DI 0 "general_operand" "x")
15772 (match_operand:DI 1 "general_operand" "x")
15774 "CGEN_ENABLE_INSN_P (568)"
15775 "cpcmpeq.h\\t%0,%1"
15776 [(set_attr "may_trap" "no")
15777 (set_attr "latency" "0")
15778 (set_attr "length" "4")
15779 (set_attr "slot" "cop")
15780 (set_attr "slots" "c3")
15781 (set_attr "stall" "none")])
15784 (define_insn "cgen_intrinsic_cpcmpeq_h_P0S_P1"
15786 (unspec_volatile:SI [
15787 (match_operand:DI 0 "general_operand" "x")
15788 (match_operand:DI 1 "general_operand" "x")
15790 "CGEN_ENABLE_INSN_P (569)"
15791 "cpcmpeq.h\\t%0,%1"
15792 [(set_attr "may_trap" "no")
15793 (set_attr "latency" "0")
15794 (set_attr "length" "4")
15795 (set_attr "slot" "cop")
15796 (set_attr "slots" "p0s_p1")
15797 (set_attr "stall" "none")])
15800 (define_insn "cgen_intrinsic_cpcmpeq_b_C3"
15802 (unspec_volatile:SI [
15803 (match_operand:DI 0 "general_operand" "x")
15804 (match_operand:DI 1 "general_operand" "x")
15806 "CGEN_ENABLE_INSN_P (570)"
15807 "cpcmpeq.b\\t%0,%1"
15808 [(set_attr "may_trap" "no")
15809 (set_attr "latency" "0")
15810 (set_attr "length" "4")
15811 (set_attr "slot" "cop")
15812 (set_attr "slots" "c3")
15813 (set_attr "stall" "none")])
15816 (define_insn "cgen_intrinsic_cpcmpeq_b_P0S_P1"
15818 (unspec_volatile:SI [
15819 (match_operand:DI 0 "general_operand" "x")
15820 (match_operand:DI 1 "general_operand" "x")
15822 "CGEN_ENABLE_INSN_P (571)"
15823 "cpcmpeq.b\\t%0,%1"
15824 [(set_attr "may_trap" "no")
15825 (set_attr "latency" "0")
15826 (set_attr "length" "4")
15827 (set_attr "slot" "cop")
15828 (set_attr "slots" "p0s_p1")
15829 (set_attr "stall" "none")])
15832 (define_insn "cgen_intrinsic_cpcmpeqz_b_C3"
15834 (unspec_volatile:SI [
15835 (match_operand:DI 0 "general_operand" "x")
15836 (match_operand:DI 1 "general_operand" "x")
15838 "CGEN_ENABLE_INSN_P (572)"
15839 "cpcmpeqz.b\\t%0,%1"
15840 [(set_attr "may_trap" "no")
15841 (set_attr "latency" "0")
15842 (set_attr "length" "4")
15843 (set_attr "slot" "cop")
15844 (set_attr "slots" "c3")
15845 (set_attr "stall" "none")])
15848 (define_insn "cgen_intrinsic_cpcmpeqz_b_P0S_P1"
15850 (unspec_volatile:SI [
15851 (match_operand:DI 0 "general_operand" "x")
15852 (match_operand:DI 1 "general_operand" "x")
15854 "CGEN_ENABLE_INSN_P (573)"
15855 "cpcmpeqz.b\\t%0,%1"
15856 [(set_attr "may_trap" "no")
15857 (set_attr "latency" "0")
15858 (set_attr "length" "4")
15859 (set_attr "slot" "cop")
15860 (set_attr "slots" "p0s_p1")
15861 (set_attr "stall" "none")])
15864 (define_insn "cgen_intrinsic_cpmovtocc_C3"
15866 (unspec_volatile:SI [
15867 (match_operand:DI 0 "general_operand" "x")
15869 "CGEN_ENABLE_INSN_P (574)"
15871 [(set_attr "may_trap" "no")
15872 (set_attr "latency" "0")
15873 (set_attr "length" "4")
15874 (set_attr "slot" "cop")
15875 (set_attr "slots" "c3")
15876 (set_attr "stall" "none")])
15879 (define_insn "cgen_intrinsic_cpmovtocc_P0S_P1"
15881 (unspec_volatile:SI [
15882 (match_operand:DI 0 "general_operand" "x")
15884 "CGEN_ENABLE_INSN_P (575)"
15886 [(set_attr "may_trap" "no")
15887 (set_attr "latency" "0")
15888 (set_attr "length" "4")
15889 (set_attr "slot" "cop")
15890 (set_attr "slots" "p0s_p1")
15891 (set_attr "stall" "none")])
15894 (define_insn "cgen_intrinsic_cpmovtocsar1_C3"
15896 (unspec_volatile:SI [
15897 (match_operand:DI 0 "general_operand" "x")
15899 "CGEN_ENABLE_INSN_P (576)"
15900 "cpmovtocsar1\\t%0"
15901 [(set_attr "may_trap" "no")
15902 (set_attr "latency" "0")
15903 (set_attr "length" "4")
15904 (set_attr "slot" "cop")
15905 (set_attr "slots" "c3")
15906 (set_attr "stall" "none")])
15909 (define_insn "cgen_intrinsic_cpmovtocsar1_P0S_P1"
15911 (unspec_volatile:SI [
15912 (match_operand:DI 0 "general_operand" "x")
15914 "CGEN_ENABLE_INSN_P (577)"
15915 "cpmovtocsar1\\t%0"
15916 [(set_attr "may_trap" "no")
15917 (set_attr "latency" "0")
15918 (set_attr "length" "4")
15919 (set_attr "slot" "cop")
15920 (set_attr "slots" "p0s_p1")
15921 (set_attr "stall" "none")])
15924 (define_insn "cgen_intrinsic_cpmovtocsar0_C3"
15926 (unspec_volatile:SI [
15927 (match_operand:DI 0 "general_operand" "x")
15929 "CGEN_ENABLE_INSN_P (578)"
15930 "cpmovtocsar0\\t%0"
15931 [(set_attr "may_trap" "no")
15932 (set_attr "latency" "0")
15933 (set_attr "length" "4")
15934 (set_attr "slot" "cop")
15935 (set_attr "slots" "c3")
15936 (set_attr "stall" "none")])
15939 (define_insn "cgen_intrinsic_cpmovtocsar0_P0S_P1"
15941 (unspec_volatile:SI [
15942 (match_operand:DI 0 "general_operand" "x")
15944 "CGEN_ENABLE_INSN_P (579)"
15945 "cpmovtocsar0\\t%0"
15946 [(set_attr "may_trap" "no")
15947 (set_attr "latency" "0")
15948 (set_attr "length" "4")
15949 (set_attr "slot" "cop")
15950 (set_attr "slots" "p0s_p1")
15951 (set_attr "stall" "none")])
15954 (define_insn "cgen_intrinsic_cpmovfrcc_C3"
15955 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
15956 (unspec_volatile:DI [
15959 "CGEN_ENABLE_INSN_P (580)"
15961 [(set_attr "may_trap" "no")
15962 (set_attr "latency" "0")
15963 (set_attr "length" "4")
15964 (set_attr "slot" "cop")
15965 (set_attr "slots" "c3")
15966 (set_attr "stall" "none")])
15969 (define_insn "cgen_intrinsic_cpmovfrcc_P0S_P1"
15970 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
15971 (unspec_volatile:DI [
15974 "CGEN_ENABLE_INSN_P (581)"
15976 [(set_attr "may_trap" "no")
15977 (set_attr "latency" "0")
15978 (set_attr "length" "4")
15979 (set_attr "slot" "cop")
15980 (set_attr "slots" "p0s_p1")
15981 (set_attr "stall" "none")])
15984 (define_insn "cgen_intrinsic_cpmovfrcsar1_C3"
15985 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
15986 (unspec_volatile:DI [
15989 "CGEN_ENABLE_INSN_P (582)"
15990 "cpmovfrcsar1\\t%0"
15991 [(set_attr "may_trap" "no")
15992 (set_attr "latency" "0")
15993 (set_attr "length" "4")
15994 (set_attr "slot" "cop")
15995 (set_attr "slots" "c3")
15996 (set_attr "stall" "none")])
15999 (define_insn "cgen_intrinsic_cpmovfrcsar1_P0S_P1"
16000 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16001 (unspec_volatile:DI [
16004 "CGEN_ENABLE_INSN_P (583)"
16005 "cpmovfrcsar1\\t%0"
16006 [(set_attr "may_trap" "no")
16007 (set_attr "latency" "0")
16008 (set_attr "length" "4")
16009 (set_attr "slot" "cop")
16010 (set_attr "slots" "p0s_p1")
16011 (set_attr "stall" "none")])
16014 (define_insn "cgen_intrinsic_cpmovfrcsar0_C3"
16015 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16016 (unspec_volatile:DI [
16019 "CGEN_ENABLE_INSN_P (584)"
16020 "cpmovfrcsar0\\t%0"
16021 [(set_attr "may_trap" "no")
16022 (set_attr "latency" "0")
16023 (set_attr "length" "4")
16024 (set_attr "slot" "cop")
16025 (set_attr "slots" "c3")
16026 (set_attr "stall" "none")])
16029 (define_insn "cgen_intrinsic_cpmovfrcsar0_P0S_P1"
16030 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16031 (unspec_volatile:DI [
16034 "CGEN_ENABLE_INSN_P (585)"
16035 "cpmovfrcsar0\\t%0"
16036 [(set_attr "may_trap" "no")
16037 (set_attr "latency" "0")
16038 (set_attr "length" "4")
16039 (set_attr "slot" "cop")
16040 (set_attr "slots" "p0s_p1")
16041 (set_attr "stall" "none")])
16044 (define_insn "cgen_intrinsic_cdcastw_C3"
16045 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16047 (match_operand:DI 1 "general_operand" "x")
16049 "CGEN_ENABLE_INSN_P (586)"
16051 [(set_attr "may_trap" "no")
16052 (set_attr "latency" "0")
16053 (set_attr "length" "4")
16054 (set_attr "slot" "cop")
16055 (set_attr "slots" "c3")
16056 (set_attr "stall" "none")])
16059 (define_insn "cgen_intrinsic_cdcastw_P0S_P1"
16060 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16062 (match_operand:DI 1 "general_operand" "x")
16064 "CGEN_ENABLE_INSN_P (587)"
16066 [(set_attr "may_trap" "no")
16067 (set_attr "latency" "0")
16068 (set_attr "length" "4")
16069 (set_attr "slot" "cop")
16070 (set_attr "slots" "p0s_p1")
16071 (set_attr "stall" "none")])
16074 (define_insn "cgen_intrinsic_cdcastuw_C3"
16075 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16077 (match_operand:DI 1 "general_operand" "x")
16079 "CGEN_ENABLE_INSN_P (588)"
16081 [(set_attr "may_trap" "no")
16082 (set_attr "latency" "0")
16083 (set_attr "length" "4")
16084 (set_attr "slot" "cop")
16085 (set_attr "slots" "c3")
16086 (set_attr "stall" "none")])
16089 (define_insn "cgen_intrinsic_cdcastuw_P0S_P1"
16090 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16092 (match_operand:DI 1 "general_operand" "x")
16094 "CGEN_ENABLE_INSN_P (589)"
16096 [(set_attr "may_trap" "no")
16097 (set_attr "latency" "0")
16098 (set_attr "length" "4")
16099 (set_attr "slot" "cop")
16100 (set_attr "slots" "p0s_p1")
16101 (set_attr "stall" "none")])
16104 (define_insn "cgen_intrinsic_cpcasth_w_C3"
16105 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16107 (match_operand:DI 1 "general_operand" "x")
16109 "CGEN_ENABLE_INSN_P (590)"
16110 "cpcasth.w\\t%0,%1"
16111 [(set_attr "may_trap" "no")
16112 (set_attr "latency" "0")
16113 (set_attr "length" "4")
16114 (set_attr "slot" "cop")
16115 (set_attr "slots" "c3")
16116 (set_attr "stall" "none")])
16119 (define_insn "cgen_intrinsic_cpcasth_w_P0S_P1"
16120 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16122 (match_operand:DI 1 "general_operand" "x")
16124 "CGEN_ENABLE_INSN_P (591)"
16125 "cpcasth.w\\t%0,%1"
16126 [(set_attr "may_trap" "no")
16127 (set_attr "latency" "0")
16128 (set_attr "length" "4")
16129 (set_attr "slot" "cop")
16130 (set_attr "slots" "p0s_p1")
16131 (set_attr "stall" "none")])
16134 (define_insn "cgen_intrinsic_cpcastuh_w_C3"
16135 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16137 (match_operand:DI 1 "general_operand" "x")
16139 "CGEN_ENABLE_INSN_P (592)"
16140 "cpcastuh.w\\t%0,%1"
16141 [(set_attr "may_trap" "no")
16142 (set_attr "latency" "0")
16143 (set_attr "length" "4")
16144 (set_attr "slot" "cop")
16145 (set_attr "slots" "c3")
16146 (set_attr "stall" "none")])
16149 (define_insn "cgen_intrinsic_cpcastuh_w_P0S_P1"
16150 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16152 (match_operand:DI 1 "general_operand" "x")
16154 "CGEN_ENABLE_INSN_P (593)"
16155 "cpcastuh.w\\t%0,%1"
16156 [(set_attr "may_trap" "no")
16157 (set_attr "latency" "0")
16158 (set_attr "length" "4")
16159 (set_attr "slot" "cop")
16160 (set_attr "slots" "p0s_p1")
16161 (set_attr "stall" "none")])
16164 (define_insn "cgen_intrinsic_cpcastb_w_C3"
16165 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16167 (match_operand:DI 1 "general_operand" "x")
16169 "CGEN_ENABLE_INSN_P (594)"
16170 "cpcastb.w\\t%0,%1"
16171 [(set_attr "may_trap" "no")
16172 (set_attr "latency" "0")
16173 (set_attr "length" "4")
16174 (set_attr "slot" "cop")
16175 (set_attr "slots" "c3")
16176 (set_attr "stall" "none")])
16179 (define_insn "cgen_intrinsic_cpcastb_w_P0S_P1"
16180 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16182 (match_operand:DI 1 "general_operand" "x")
16184 "CGEN_ENABLE_INSN_P (595)"
16185 "cpcastb.w\\t%0,%1"
16186 [(set_attr "may_trap" "no")
16187 (set_attr "latency" "0")
16188 (set_attr "length" "4")
16189 (set_attr "slot" "cop")
16190 (set_attr "slots" "p0s_p1")
16191 (set_attr "stall" "none")])
16194 (define_insn "cgen_intrinsic_cpcastub_w_C3"
16195 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16197 (match_operand:DI 1 "general_operand" "x")
16199 "CGEN_ENABLE_INSN_P (596)"
16200 "cpcastub.w\\t%0,%1"
16201 [(set_attr "may_trap" "no")
16202 (set_attr "latency" "0")
16203 (set_attr "length" "4")
16204 (set_attr "slot" "cop")
16205 (set_attr "slots" "c3")
16206 (set_attr "stall" "none")])
16209 (define_insn "cgen_intrinsic_cpcastub_w_P0S_P1"
16210 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16212 (match_operand:DI 1 "general_operand" "x")
16214 "CGEN_ENABLE_INSN_P (597)"
16215 "cpcastub.w\\t%0,%1"
16216 [(set_attr "may_trap" "no")
16217 (set_attr "latency" "0")
16218 (set_attr "length" "4")
16219 (set_attr "slot" "cop")
16220 (set_attr "slots" "p0s_p1")
16221 (set_attr "stall" "none")])
16224 (define_insn "cgen_intrinsic_cpcastb_h_C3"
16225 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16227 (match_operand:DI 1 "general_operand" "x")
16229 "CGEN_ENABLE_INSN_P (598)"
16230 "cpcastb.h\\t%0,%1"
16231 [(set_attr "may_trap" "no")
16232 (set_attr "latency" "0")
16233 (set_attr "length" "4")
16234 (set_attr "slot" "cop")
16235 (set_attr "slots" "c3")
16236 (set_attr "stall" "none")])
16239 (define_insn "cgen_intrinsic_cpcastb_h_P0S_P1"
16240 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16242 (match_operand:DI 1 "general_operand" "x")
16244 "CGEN_ENABLE_INSN_P (599)"
16245 "cpcastb.h\\t%0,%1"
16246 [(set_attr "may_trap" "no")
16247 (set_attr "latency" "0")
16248 (set_attr "length" "4")
16249 (set_attr "slot" "cop")
16250 (set_attr "slots" "p0s_p1")
16251 (set_attr "stall" "none")])
16254 (define_insn "cgen_intrinsic_cpcastub_h_C3"
16255 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16257 (match_operand:DI 1 "general_operand" "x")
16259 "CGEN_ENABLE_INSN_P (600)"
16260 "cpcastub.h\\t%0,%1"
16261 [(set_attr "may_trap" "no")
16262 (set_attr "latency" "0")
16263 (set_attr "length" "4")
16264 (set_attr "slot" "cop")
16265 (set_attr "slots" "c3")
16266 (set_attr "stall" "none")])
16269 (define_insn "cgen_intrinsic_cpcastub_h_P0S_P1"
16270 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16272 (match_operand:DI 1 "general_operand" "x")
16274 "CGEN_ENABLE_INSN_P (601)"
16275 "cpcastub.h\\t%0,%1"
16276 [(set_attr "may_trap" "no")
16277 (set_attr "latency" "0")
16278 (set_attr "length" "4")
16279 (set_attr "slot" "cop")
16280 (set_attr "slots" "p0s_p1")
16281 (set_attr "stall" "none")])
16284 (define_insn "cgen_intrinsic_cpextl_h_C3"
16285 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16287 (match_operand:DI 1 "general_operand" "x")
16289 "CGEN_ENABLE_INSN_P (602)"
16291 [(set_attr "may_trap" "no")
16292 (set_attr "latency" "0")
16293 (set_attr "length" "4")
16294 (set_attr "slot" "cop")
16295 (set_attr "slots" "c3")
16296 (set_attr "stall" "none")])
16299 (define_insn "cgen_intrinsic_cpextl_h_P0S_P1"
16300 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16302 (match_operand:DI 1 "general_operand" "x")
16304 "CGEN_ENABLE_INSN_P (603)"
16306 [(set_attr "may_trap" "no")
16307 (set_attr "latency" "0")
16308 (set_attr "length" "4")
16309 (set_attr "slot" "cop")
16310 (set_attr "slots" "p0s_p1")
16311 (set_attr "stall" "none")])
16314 (define_insn "cgen_intrinsic_cpextlu_h_C3"
16315 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16317 (match_operand:DI 1 "general_operand" "x")
16319 "CGEN_ENABLE_INSN_P (604)"
16320 "cpextlu.h\\t%0,%1"
16321 [(set_attr "may_trap" "no")
16322 (set_attr "latency" "0")
16323 (set_attr "length" "4")
16324 (set_attr "slot" "cop")
16325 (set_attr "slots" "c3")
16326 (set_attr "stall" "none")])
16329 (define_insn "cgen_intrinsic_cpextlu_h_P0S_P1"
16330 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16332 (match_operand:DI 1 "general_operand" "x")
16334 "CGEN_ENABLE_INSN_P (605)"
16335 "cpextlu.h\\t%0,%1"
16336 [(set_attr "may_trap" "no")
16337 (set_attr "latency" "0")
16338 (set_attr "length" "4")
16339 (set_attr "slot" "cop")
16340 (set_attr "slots" "p0s_p1")
16341 (set_attr "stall" "none")])
16344 (define_insn "cgen_intrinsic_cpextl_b_C3"
16345 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16347 (match_operand:DI 1 "general_operand" "x")
16349 "CGEN_ENABLE_INSN_P (606)"
16351 [(set_attr "may_trap" "no")
16352 (set_attr "latency" "0")
16353 (set_attr "length" "4")
16354 (set_attr "slot" "cop")
16355 (set_attr "slots" "c3")
16356 (set_attr "stall" "none")])
16359 (define_insn "cgen_intrinsic_cpextl_b_P0S_P1"
16360 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16362 (match_operand:DI 1 "general_operand" "x")
16364 "CGEN_ENABLE_INSN_P (607)"
16366 [(set_attr "may_trap" "no")
16367 (set_attr "latency" "0")
16368 (set_attr "length" "4")
16369 (set_attr "slot" "cop")
16370 (set_attr "slots" "p0s_p1")
16371 (set_attr "stall" "none")])
16374 (define_insn "cgen_intrinsic_cpextlu_b_C3"
16375 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16377 (match_operand:DI 1 "general_operand" "x")
16379 "CGEN_ENABLE_INSN_P (608)"
16380 "cpextlu.b\\t%0,%1"
16381 [(set_attr "may_trap" "no")
16382 (set_attr "latency" "0")
16383 (set_attr "length" "4")
16384 (set_attr "slot" "cop")
16385 (set_attr "slots" "c3")
16386 (set_attr "stall" "none")])
16389 (define_insn "cgen_intrinsic_cpextlu_b_P0S_P1"
16390 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16392 (match_operand:DI 1 "general_operand" "x")
16394 "CGEN_ENABLE_INSN_P (609)"
16395 "cpextlu.b\\t%0,%1"
16396 [(set_attr "may_trap" "no")
16397 (set_attr "latency" "0")
16398 (set_attr "length" "4")
16399 (set_attr "slot" "cop")
16400 (set_attr "slots" "p0s_p1")
16401 (set_attr "stall" "none")])
16404 (define_insn "cgen_intrinsic_cpextu_h_C3"
16405 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16407 (match_operand:DI 1 "general_operand" "x")
16409 "CGEN_ENABLE_INSN_P (610)"
16411 [(set_attr "may_trap" "no")
16412 (set_attr "latency" "0")
16413 (set_attr "length" "4")
16414 (set_attr "slot" "cop")
16415 (set_attr "slots" "c3")
16416 (set_attr "stall" "none")])
16419 (define_insn "cgen_intrinsic_cpextu_h_P0S_P1"
16420 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16422 (match_operand:DI 1 "general_operand" "x")
16424 "CGEN_ENABLE_INSN_P (611)"
16426 [(set_attr "may_trap" "no")
16427 (set_attr "latency" "0")
16428 (set_attr "length" "4")
16429 (set_attr "slot" "cop")
16430 (set_attr "slots" "p0s_p1")
16431 (set_attr "stall" "none")])
16434 (define_insn "cgen_intrinsic_cpextuu_h_C3"
16435 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16437 (match_operand:DI 1 "general_operand" "x")
16439 "CGEN_ENABLE_INSN_P (612)"
16440 "cpextuu.h\\t%0,%1"
16441 [(set_attr "may_trap" "no")
16442 (set_attr "latency" "0")
16443 (set_attr "length" "4")
16444 (set_attr "slot" "cop")
16445 (set_attr "slots" "c3")
16446 (set_attr "stall" "none")])
16449 (define_insn "cgen_intrinsic_cpextuu_h_P0S_P1"
16450 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16452 (match_operand:DI 1 "general_operand" "x")
16454 "CGEN_ENABLE_INSN_P (613)"
16455 "cpextuu.h\\t%0,%1"
16456 [(set_attr "may_trap" "no")
16457 (set_attr "latency" "0")
16458 (set_attr "length" "4")
16459 (set_attr "slot" "cop")
16460 (set_attr "slots" "p0s_p1")
16461 (set_attr "stall" "none")])
16464 (define_insn "cgen_intrinsic_cpextu_b_C3"
16465 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16467 (match_operand:DI 1 "general_operand" "x")
16469 "CGEN_ENABLE_INSN_P (614)"
16471 [(set_attr "may_trap" "no")
16472 (set_attr "latency" "0")
16473 (set_attr "length" "4")
16474 (set_attr "slot" "cop")
16475 (set_attr "slots" "c3")
16476 (set_attr "stall" "none")])
16479 (define_insn "cgen_intrinsic_cpextu_b_P0S_P1"
16480 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16482 (match_operand:DI 1 "general_operand" "x")
16484 "CGEN_ENABLE_INSN_P (615)"
16486 [(set_attr "may_trap" "no")
16487 (set_attr "latency" "0")
16488 (set_attr "length" "4")
16489 (set_attr "slot" "cop")
16490 (set_attr "slots" "p0s_p1")
16491 (set_attr "stall" "none")])
16494 (define_insn "cgen_intrinsic_cpextuu_b_C3"
16495 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16497 (match_operand:DI 1 "general_operand" "x")
16499 "CGEN_ENABLE_INSN_P (616)"
16500 "cpextuu.b\\t%0,%1"
16501 [(set_attr "may_trap" "no")
16502 (set_attr "latency" "0")
16503 (set_attr "length" "4")
16504 (set_attr "slot" "cop")
16505 (set_attr "slots" "c3")
16506 (set_attr "stall" "none")])
16509 (define_insn "cgen_intrinsic_cpextuu_b_P0S_P1"
16510 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16512 (match_operand:DI 1 "general_operand" "x")
16514 "CGEN_ENABLE_INSN_P (617)"
16515 "cpextuu.b\\t%0,%1"
16516 [(set_attr "may_trap" "no")
16517 (set_attr "latency" "0")
16518 (set_attr "length" "4")
16519 (set_attr "slot" "cop")
16520 (set_attr "slots" "p0s_p1")
16521 (set_attr "stall" "none")])
16524 (define_insn "cgen_intrinsic_cpbcast_w_C3"
16525 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16527 (match_operand:DI 1 "general_operand" "x")
16529 "CGEN_ENABLE_INSN_P (618)"
16530 "cpbcast.w\\t%0,%1"
16531 [(set_attr "may_trap" "no")
16532 (set_attr "latency" "0")
16533 (set_attr "length" "4")
16534 (set_attr "slot" "cop")
16535 (set_attr "slots" "c3")
16536 (set_attr "stall" "none")])
16539 (define_insn "cgen_intrinsic_cpbcast_w_P0S_P1"
16540 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16542 (match_operand:DI 1 "general_operand" "x")
16544 "CGEN_ENABLE_INSN_P (619)"
16545 "cpbcast.w\\t%0,%1"
16546 [(set_attr "may_trap" "no")
16547 (set_attr "latency" "0")
16548 (set_attr "length" "4")
16549 (set_attr "slot" "cop")
16550 (set_attr "slots" "p0s_p1")
16551 (set_attr "stall" "none")])
16554 (define_insn "cgen_intrinsic_cpbcast_h_C3"
16555 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16557 (match_operand:DI 1 "general_operand" "x")
16559 "CGEN_ENABLE_INSN_P (620)"
16560 "cpbcast.h\\t%0,%1"
16561 [(set_attr "may_trap" "no")
16562 (set_attr "latency" "0")
16563 (set_attr "length" "4")
16564 (set_attr "slot" "cop")
16565 (set_attr "slots" "c3")
16566 (set_attr "stall" "none")])
16569 (define_insn "cgen_intrinsic_cpbcast_h_P0S_P1"
16570 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16572 (match_operand:DI 1 "general_operand" "x")
16574 "CGEN_ENABLE_INSN_P (621)"
16575 "cpbcast.h\\t%0,%1"
16576 [(set_attr "may_trap" "no")
16577 (set_attr "latency" "0")
16578 (set_attr "length" "4")
16579 (set_attr "slot" "cop")
16580 (set_attr "slots" "p0s_p1")
16581 (set_attr "stall" "none")])
16584 (define_insn "cgen_intrinsic_cpbcast_b_C3"
16585 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16587 (match_operand:DI 1 "general_operand" "x")
16589 "CGEN_ENABLE_INSN_P (622)"
16590 "cpbcast.b\\t%0,%1"
16591 [(set_attr "may_trap" "no")
16592 (set_attr "latency" "0")
16593 (set_attr "length" "4")
16594 (set_attr "slot" "cop")
16595 (set_attr "slots" "c3")
16596 (set_attr "stall" "none")])
16599 (define_insn "cgen_intrinsic_cpbcast_b_P0S_P1"
16600 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16602 (match_operand:DI 1 "general_operand" "x")
16604 "CGEN_ENABLE_INSN_P (623)"
16605 "cpbcast.b\\t%0,%1"
16606 [(set_attr "may_trap" "no")
16607 (set_attr "latency" "0")
16608 (set_attr "length" "4")
16609 (set_attr "slot" "cop")
16610 (set_attr "slots" "p0s_p1")
16611 (set_attr "stall" "none")])
16614 (define_insn "cgen_intrinsic_cpccadd_b_C3"
16615 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16616 (unspec_volatile:DI [
16617 (match_operand:DI 1 "general_operand" "0")
16619 "CGEN_ENABLE_INSN_P (624)"
16621 [(set_attr "may_trap" "no")
16622 (set_attr "latency" "0")
16623 (set_attr "length" "4")
16624 (set_attr "slot" "cop")
16625 (set_attr "slots" "c3")
16626 (set_attr "stall" "none")])
16629 (define_insn "cgen_intrinsic_cpccadd_b_P0S_P1"
16630 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16631 (unspec_volatile:DI [
16632 (match_operand:DI 1 "general_operand" "0")
16634 "CGEN_ENABLE_INSN_P (625)"
16636 [(set_attr "may_trap" "no")
16637 (set_attr "latency" "0")
16638 (set_attr "length" "4")
16639 (set_attr "slot" "cop")
16640 (set_attr "slots" "p0s_p1")
16641 (set_attr "stall" "none")])
16644 (define_insn "cgen_intrinsic_cphadd_w_C3"
16645 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16647 (match_operand:DI 1 "general_operand" "x")
16649 "CGEN_ENABLE_INSN_P (626)"
16651 [(set_attr "may_trap" "no")
16652 (set_attr "latency" "0")
16653 (set_attr "length" "4")
16654 (set_attr "slot" "cop")
16655 (set_attr "slots" "c3")
16656 (set_attr "stall" "none")])
16659 (define_insn "cgen_intrinsic_cphadd_w_P0S_P1"
16660 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16662 (match_operand:DI 1 "general_operand" "x")
16664 "CGEN_ENABLE_INSN_P (627)"
16666 [(set_attr "may_trap" "no")
16667 (set_attr "latency" "0")
16668 (set_attr "length" "4")
16669 (set_attr "slot" "cop")
16670 (set_attr "slots" "p0s_p1")
16671 (set_attr "stall" "none")])
16674 (define_insn "cgen_intrinsic_cphadd_h_C3"
16675 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16677 (match_operand:DI 1 "general_operand" "x")
16679 "CGEN_ENABLE_INSN_P (628)"
16681 [(set_attr "may_trap" "no")
16682 (set_attr "latency" "0")
16683 (set_attr "length" "4")
16684 (set_attr "slot" "cop")
16685 (set_attr "slots" "c3")
16686 (set_attr "stall" "none")])
16689 (define_insn "cgen_intrinsic_cphadd_h_P0S_P1"
16690 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16692 (match_operand:DI 1 "general_operand" "x")
16694 "CGEN_ENABLE_INSN_P (629)"
16696 [(set_attr "may_trap" "no")
16697 (set_attr "latency" "0")
16698 (set_attr "length" "4")
16699 (set_attr "slot" "cop")
16700 (set_attr "slots" "p0s_p1")
16701 (set_attr "stall" "none")])
16704 (define_insn "cgen_intrinsic_cphadd_b_C3"
16705 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16707 (match_operand:DI 1 "general_operand" "x")
16709 "CGEN_ENABLE_INSN_P (630)"
16711 [(set_attr "may_trap" "no")
16712 (set_attr "latency" "0")
16713 (set_attr "length" "4")
16714 (set_attr "slot" "cop")
16715 (set_attr "slots" "c3")
16716 (set_attr "stall" "none")])
16719 (define_insn "cgen_intrinsic_cphadd_b_P0S_P1"
16720 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16722 (match_operand:DI 1 "general_operand" "x")
16724 "CGEN_ENABLE_INSN_P (631)"
16726 [(set_attr "may_trap" "no")
16727 (set_attr "latency" "0")
16728 (set_attr "length" "4")
16729 (set_attr "slot" "cop")
16730 (set_attr "slots" "p0s_p1")
16731 (set_attr "stall" "none")])
16734 (define_insn "cgen_intrinsic_cphaddu_b_C3"
16735 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16737 (match_operand:DI 1 "general_operand" "x")
16739 "CGEN_ENABLE_INSN_P (632)"
16740 "cphaddu.b\\t%0,%1"
16741 [(set_attr "may_trap" "no")
16742 (set_attr "latency" "0")
16743 (set_attr "length" "4")
16744 (set_attr "slot" "cop")
16745 (set_attr "slots" "c3")
16746 (set_attr "stall" "none")])
16749 (define_insn "cgen_intrinsic_cphaddu_b_P0S_P1"
16750 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16752 (match_operand:DI 1 "general_operand" "x")
16754 "CGEN_ENABLE_INSN_P (633)"
16755 "cphaddu.b\\t%0,%1"
16756 [(set_attr "may_trap" "no")
16757 (set_attr "latency" "0")
16758 (set_attr "length" "4")
16759 (set_attr "slot" "cop")
16760 (set_attr "slots" "p0s_p1")
16761 (set_attr "stall" "none")])
16764 (define_insn "cgen_intrinsic_cpnorm_w_C3"
16765 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16767 (match_operand:DI 1 "general_operand" "x")
16769 "CGEN_ENABLE_INSN_P (634)"
16771 [(set_attr "may_trap" "no")
16772 (set_attr "latency" "0")
16773 (set_attr "length" "4")
16774 (set_attr "slot" "cop")
16775 (set_attr "slots" "c3")
16776 (set_attr "stall" "none")])
16779 (define_insn "cgen_intrinsic_cpnorm_w_P0S_P1"
16780 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16782 (match_operand:DI 1 "general_operand" "x")
16784 "CGEN_ENABLE_INSN_P (635)"
16786 [(set_attr "may_trap" "no")
16787 (set_attr "latency" "0")
16788 (set_attr "length" "4")
16789 (set_attr "slot" "cop")
16790 (set_attr "slots" "p0s_p1")
16791 (set_attr "stall" "none")])
16794 (define_insn "cgen_intrinsic_cpnorm_h_C3"
16795 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16797 (match_operand:DI 1 "general_operand" "x")
16799 "CGEN_ENABLE_INSN_P (636)"
16801 [(set_attr "may_trap" "no")
16802 (set_attr "latency" "0")
16803 (set_attr "length" "4")
16804 (set_attr "slot" "cop")
16805 (set_attr "slots" "c3")
16806 (set_attr "stall" "none")])
16809 (define_insn "cgen_intrinsic_cpnorm_h_P0S_P1"
16810 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16812 (match_operand:DI 1 "general_operand" "x")
16814 "CGEN_ENABLE_INSN_P (637)"
16816 [(set_attr "may_trap" "no")
16817 (set_attr "latency" "0")
16818 (set_attr "length" "4")
16819 (set_attr "slot" "cop")
16820 (set_attr "slots" "p0s_p1")
16821 (set_attr "stall" "none")])
16824 (define_insn "cgen_intrinsic_cpldz_w_C3"
16825 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16827 (match_operand:DI 1 "general_operand" "x")
16829 "CGEN_ENABLE_INSN_P (638)"
16831 [(set_attr "may_trap" "no")
16832 (set_attr "latency" "0")
16833 (set_attr "length" "4")
16834 (set_attr "slot" "cop")
16835 (set_attr "slots" "c3")
16836 (set_attr "stall" "none")])
16839 (define_insn "cgen_intrinsic_cpldz_w_P0S_P1"
16840 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16842 (match_operand:DI 1 "general_operand" "x")
16844 "CGEN_ENABLE_INSN_P (639)"
16846 [(set_attr "may_trap" "no")
16847 (set_attr "latency" "0")
16848 (set_attr "length" "4")
16849 (set_attr "slot" "cop")
16850 (set_attr "slots" "p0s_p1")
16851 (set_attr "stall" "none")])
16854 (define_insn "cgen_intrinsic_cpldz_h_C3"
16855 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16857 (match_operand:DI 1 "general_operand" "x")
16859 "CGEN_ENABLE_INSN_P (640)"
16861 [(set_attr "may_trap" "no")
16862 (set_attr "latency" "0")
16863 (set_attr "length" "4")
16864 (set_attr "slot" "cop")
16865 (set_attr "slots" "c3")
16866 (set_attr "stall" "none")])
16869 (define_insn "cgen_intrinsic_cpldz_h_P0S_P1"
16870 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16872 (match_operand:DI 1 "general_operand" "x")
16874 "CGEN_ENABLE_INSN_P (641)"
16876 [(set_attr "may_trap" "no")
16877 (set_attr "latency" "0")
16878 (set_attr "length" "4")
16879 (set_attr "slot" "cop")
16880 (set_attr "slots" "p0s_p1")
16881 (set_attr "stall" "none")])
16884 (define_insn "cgen_intrinsic_cpabsz_w_C3"
16885 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16887 (match_operand:DI 1 "general_operand" "x")
16889 "CGEN_ENABLE_INSN_P (642)"
16891 [(set_attr "may_trap" "no")
16892 (set_attr "latency" "0")
16893 (set_attr "length" "4")
16894 (set_attr "slot" "cop")
16895 (set_attr "slots" "c3")
16896 (set_attr "stall" "none")])
16899 (define_insn "cgen_intrinsic_cpabsz_w_P0S_P1"
16900 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16902 (match_operand:DI 1 "general_operand" "x")
16904 "CGEN_ENABLE_INSN_P (643)"
16906 [(set_attr "may_trap" "no")
16907 (set_attr "latency" "0")
16908 (set_attr "length" "4")
16909 (set_attr "slot" "cop")
16910 (set_attr "slots" "p0s_p1")
16911 (set_attr "stall" "none")])
16914 (define_insn "cgen_intrinsic_cpabsz_h_C3"
16915 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16917 (match_operand:DI 1 "general_operand" "x")
16919 "CGEN_ENABLE_INSN_P (644)"
16921 [(set_attr "may_trap" "no")
16922 (set_attr "latency" "0")
16923 (set_attr "length" "4")
16924 (set_attr "slot" "cop")
16925 (set_attr "slots" "c3")
16926 (set_attr "stall" "none")])
16929 (define_insn "cgen_intrinsic_cpabsz_h_P0S_P1"
16930 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16932 (match_operand:DI 1 "general_operand" "x")
16934 "CGEN_ENABLE_INSN_P (645)"
16936 [(set_attr "may_trap" "no")
16937 (set_attr "latency" "0")
16938 (set_attr "length" "4")
16939 (set_attr "slot" "cop")
16940 (set_attr "slots" "p0s_p1")
16941 (set_attr "stall" "none")])
16944 (define_insn "cgen_intrinsic_cpabsz_b_C3"
16945 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16947 (match_operand:DI 1 "general_operand" "x")
16949 "CGEN_ENABLE_INSN_P (646)"
16951 [(set_attr "may_trap" "no")
16952 (set_attr "latency" "0")
16953 (set_attr "length" "4")
16954 (set_attr "slot" "cop")
16955 (set_attr "slots" "c3")
16956 (set_attr "stall" "none")])
16959 (define_insn "cgen_intrinsic_cpabsz_b_P0S_P1"
16960 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16962 (match_operand:DI 1 "general_operand" "x")
16964 "CGEN_ENABLE_INSN_P (647)"
16966 [(set_attr "may_trap" "no")
16967 (set_attr "latency" "0")
16968 (set_attr "length" "4")
16969 (set_attr "slot" "cop")
16970 (set_attr "slots" "p0s_p1")
16971 (set_attr "stall" "none")])
16974 (define_insn "cgen_intrinsic_cpmov_C3"
16975 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16977 (match_operand:DI 1 "general_operand" "x")
16979 "CGEN_ENABLE_INSN_P (648)"
16981 [(set_attr "may_trap" "no")
16982 (set_attr "latency" "0")
16983 (set_attr "length" "4")
16984 (set_attr "slot" "cop")
16985 (set_attr "slots" "c3")
16986 (set_attr "stall" "none")])
16989 (define_insn "cgen_intrinsic_cpmov_P0S_P1"
16990 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
16992 (match_operand:DI 1 "general_operand" "x")
16994 "CGEN_ENABLE_INSN_P (649)"
16996 [(set_attr "may_trap" "no")
16997 (set_attr "latency" "0")
16998 (set_attr "length" "4")
16999 (set_attr "slot" "cop")
17000 (set_attr "slots" "p0s_p1")
17001 (set_attr "stall" "none")])
17004 (define_insn "cgen_intrinsic_cpfsftbs1_C3"
17005 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17006 (unspec_volatile:DI [
17007 (match_operand:DI 1 "general_operand" "x")
17008 (match_operand:DI 2 "general_operand" "x")
17010 "CGEN_ENABLE_INSN_P (650)"
17011 "cpfsftbs1\\t%0,%1,%2"
17012 [(set_attr "may_trap" "no")
17013 (set_attr "latency" "0")
17014 (set_attr "length" "4")
17015 (set_attr "slot" "cop")
17016 (set_attr "slots" "c3")
17017 (set_attr "stall" "none")])
17020 (define_insn "cgen_intrinsic_cpfsftbs1_P0S_P1"
17021 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17022 (unspec_volatile:DI [
17023 (match_operand:DI 1 "general_operand" "x")
17024 (match_operand:DI 2 "general_operand" "x")
17026 "CGEN_ENABLE_INSN_P (651)"
17027 "cpfsftbs1\\t%0,%1,%2"
17028 [(set_attr "may_trap" "no")
17029 (set_attr "latency" "0")
17030 (set_attr "length" "4")
17031 (set_attr "slot" "cop")
17032 (set_attr "slots" "p0s_p1")
17033 (set_attr "stall" "none")])
17036 (define_insn "cgen_intrinsic_cpfsftbs0_C3"
17037 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17038 (unspec_volatile:DI [
17039 (match_operand:DI 1 "general_operand" "x")
17040 (match_operand:DI 2 "general_operand" "x")
17042 "CGEN_ENABLE_INSN_P (652)"
17043 "cpfsftbs0\\t%0,%1,%2"
17044 [(set_attr "may_trap" "no")
17045 (set_attr "latency" "0")
17046 (set_attr "length" "4")
17047 (set_attr "slot" "cop")
17048 (set_attr "slots" "c3")
17049 (set_attr "stall" "none")])
17052 (define_insn "cgen_intrinsic_cpfsftbs0_P0S_P1"
17053 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17054 (unspec_volatile:DI [
17055 (match_operand:DI 1 "general_operand" "x")
17056 (match_operand:DI 2 "general_operand" "x")
17058 "CGEN_ENABLE_INSN_P (653)"
17059 "cpfsftbs0\\t%0,%1,%2"
17060 [(set_attr "may_trap" "no")
17061 (set_attr "latency" "0")
17062 (set_attr "length" "4")
17063 (set_attr "slot" "cop")
17064 (set_attr "slots" "p0s_p1")
17065 (set_attr "stall" "none")])
17068 (define_insn "cgen_intrinsic_cpsel_C3"
17069 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17070 (unspec_volatile:DI [
17071 (match_operand:DI 1 "general_operand" "x")
17072 (match_operand:DI 2 "general_operand" "x")
17074 "CGEN_ENABLE_INSN_P (654)"
17076 [(set_attr "may_trap" "no")
17077 (set_attr "latency" "0")
17078 (set_attr "length" "4")
17079 (set_attr "slot" "cop")
17080 (set_attr "slots" "c3")
17081 (set_attr "stall" "none")])
17084 (define_insn "cgen_intrinsic_cpsel_P0S_P1"
17085 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17086 (unspec_volatile:DI [
17087 (match_operand:DI 1 "general_operand" "x")
17088 (match_operand:DI 2 "general_operand" "x")
17090 "CGEN_ENABLE_INSN_P (655)"
17092 [(set_attr "may_trap" "no")
17093 (set_attr "latency" "0")
17094 (set_attr "length" "4")
17095 (set_attr "slot" "cop")
17096 (set_attr "slots" "p0s_p1")
17097 (set_attr "stall" "none")])
17100 (define_insn "cgen_intrinsic_cpunpackl_w_C3"
17101 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17103 (match_operand:DI 1 "general_operand" "x")
17104 (match_operand:DI 2 "general_operand" "x")
17106 "CGEN_ENABLE_INSN_P (656)"
17107 "cpunpackl.w\\t%0,%1,%2"
17108 [(set_attr "may_trap" "no")
17109 (set_attr "latency" "0")
17110 (set_attr "length" "4")
17111 (set_attr "slot" "cop")
17112 (set_attr "slots" "c3")
17113 (set_attr "stall" "none")])
17116 (define_insn "cgen_intrinsic_cpunpackl_w_P0S_P1"
17117 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17119 (match_operand:DI 1 "general_operand" "x")
17120 (match_operand:DI 2 "general_operand" "x")
17122 "CGEN_ENABLE_INSN_P (657)"
17123 "cpunpackl.w\\t%0,%1,%2"
17124 [(set_attr "may_trap" "no")
17125 (set_attr "latency" "0")
17126 (set_attr "length" "4")
17127 (set_attr "slot" "cop")
17128 (set_attr "slots" "p0s_p1")
17129 (set_attr "stall" "none")])
17132 (define_insn "cgen_intrinsic_cpunpackl_h_C3"
17133 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17135 (match_operand:DI 1 "general_operand" "x")
17136 (match_operand:DI 2 "general_operand" "x")
17138 "CGEN_ENABLE_INSN_P (658)"
17139 "cpunpackl.h\\t%0,%1,%2"
17140 [(set_attr "may_trap" "no")
17141 (set_attr "latency" "0")
17142 (set_attr "length" "4")
17143 (set_attr "slot" "cop")
17144 (set_attr "slots" "c3")
17145 (set_attr "stall" "none")])
17148 (define_insn "cgen_intrinsic_cpunpackl_h_P0S_P1"
17149 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17151 (match_operand:DI 1 "general_operand" "x")
17152 (match_operand:DI 2 "general_operand" "x")
17154 "CGEN_ENABLE_INSN_P (659)"
17155 "cpunpackl.h\\t%0,%1,%2"
17156 [(set_attr "may_trap" "no")
17157 (set_attr "latency" "0")
17158 (set_attr "length" "4")
17159 (set_attr "slot" "cop")
17160 (set_attr "slots" "p0s_p1")
17161 (set_attr "stall" "none")])
17164 (define_insn "cgen_intrinsic_cpunpackl_b_C3"
17165 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17167 (match_operand:DI 1 "general_operand" "x")
17168 (match_operand:DI 2 "general_operand" "x")
17170 "CGEN_ENABLE_INSN_P (660)"
17171 "cpunpackl.b\\t%0,%1,%2"
17172 [(set_attr "may_trap" "no")
17173 (set_attr "latency" "0")
17174 (set_attr "length" "4")
17175 (set_attr "slot" "cop")
17176 (set_attr "slots" "c3")
17177 (set_attr "stall" "none")])
17180 (define_insn "cgen_intrinsic_cpunpackl_b_P0S_P1"
17181 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17183 (match_operand:DI 1 "general_operand" "x")
17184 (match_operand:DI 2 "general_operand" "x")
17186 "CGEN_ENABLE_INSN_P (661)"
17187 "cpunpackl.b\\t%0,%1,%2"
17188 [(set_attr "may_trap" "no")
17189 (set_attr "latency" "0")
17190 (set_attr "length" "4")
17191 (set_attr "slot" "cop")
17192 (set_attr "slots" "p0s_p1")
17193 (set_attr "stall" "none")])
17196 (define_insn "cgen_intrinsic_cpunpacku_w_C3"
17197 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17199 (match_operand:DI 1 "general_operand" "x")
17200 (match_operand:DI 2 "general_operand" "x")
17202 "CGEN_ENABLE_INSN_P (662)"
17203 "cpunpacku.w\\t%0,%1,%2"
17204 [(set_attr "may_trap" "no")
17205 (set_attr "latency" "0")
17206 (set_attr "length" "4")
17207 (set_attr "slot" "cop")
17208 (set_attr "slots" "c3")
17209 (set_attr "stall" "none")])
17212 (define_insn "cgen_intrinsic_cpunpacku_w_P0S_P1"
17213 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17215 (match_operand:DI 1 "general_operand" "x")
17216 (match_operand:DI 2 "general_operand" "x")
17218 "CGEN_ENABLE_INSN_P (663)"
17219 "cpunpacku.w\\t%0,%1,%2"
17220 [(set_attr "may_trap" "no")
17221 (set_attr "latency" "0")
17222 (set_attr "length" "4")
17223 (set_attr "slot" "cop")
17224 (set_attr "slots" "p0s_p1")
17225 (set_attr "stall" "none")])
17228 (define_insn "cgen_intrinsic_cpunpacku_h_C3"
17229 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17231 (match_operand:DI 1 "general_operand" "x")
17232 (match_operand:DI 2 "general_operand" "x")
17234 "CGEN_ENABLE_INSN_P (664)"
17235 "cpunpacku.h\\t%0,%1,%2"
17236 [(set_attr "may_trap" "no")
17237 (set_attr "latency" "0")
17238 (set_attr "length" "4")
17239 (set_attr "slot" "cop")
17240 (set_attr "slots" "c3")
17241 (set_attr "stall" "none")])
17244 (define_insn "cgen_intrinsic_cpunpacku_h_P0S_P1"
17245 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17247 (match_operand:DI 1 "general_operand" "x")
17248 (match_operand:DI 2 "general_operand" "x")
17250 "CGEN_ENABLE_INSN_P (665)"
17251 "cpunpacku.h\\t%0,%1,%2"
17252 [(set_attr "may_trap" "no")
17253 (set_attr "latency" "0")
17254 (set_attr "length" "4")
17255 (set_attr "slot" "cop")
17256 (set_attr "slots" "p0s_p1")
17257 (set_attr "stall" "none")])
17260 (define_insn "cgen_intrinsic_cpunpacku_b_C3"
17261 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17263 (match_operand:DI 1 "general_operand" "x")
17264 (match_operand:DI 2 "general_operand" "x")
17266 "CGEN_ENABLE_INSN_P (666)"
17267 "cpunpacku.b\\t%0,%1,%2"
17268 [(set_attr "may_trap" "no")
17269 (set_attr "latency" "0")
17270 (set_attr "length" "4")
17271 (set_attr "slot" "cop")
17272 (set_attr "slots" "c3")
17273 (set_attr "stall" "none")])
17276 (define_insn "cgen_intrinsic_cpunpacku_b_P0S_P1"
17277 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17279 (match_operand:DI 1 "general_operand" "x")
17280 (match_operand:DI 2 "general_operand" "x")
17282 "CGEN_ENABLE_INSN_P (667)"
17283 "cpunpacku.b\\t%0,%1,%2"
17284 [(set_attr "may_trap" "no")
17285 (set_attr "latency" "0")
17286 (set_attr "length" "4")
17287 (set_attr "slot" "cop")
17288 (set_attr "slots" "p0s_p1")
17289 (set_attr "stall" "none")])
17292 (define_insn "cgen_intrinsic_cpadd3_w_C3"
17293 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17295 (match_operand:DI 1 "general_operand" "x")
17296 (match_operand:DI 2 "general_operand" "x")
17298 "CGEN_ENABLE_INSN_P (668)"
17299 "cpadd3.w\\t%0,%1,%2"
17300 [(set_attr "may_trap" "no")
17301 (set_attr "latency" "0")
17302 (set_attr "length" "4")
17303 (set_attr "slot" "cop")
17304 (set_attr "slots" "c3")
17305 (set_attr "stall" "none")])
17308 (define_insn "cgen_intrinsic_cpadd3_w_P0S_P1"
17309 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17311 (match_operand:DI 1 "general_operand" "x")
17312 (match_operand:DI 2 "general_operand" "x")
17314 "CGEN_ENABLE_INSN_P (669)"
17315 "cpadd3.w\\t%0,%1,%2"
17316 [(set_attr "may_trap" "no")
17317 (set_attr "latency" "0")
17318 (set_attr "length" "4")
17319 (set_attr "slot" "cop")
17320 (set_attr "slots" "p0s_p1")
17321 (set_attr "stall" "none")])
17324 (define_insn "cgen_intrinsic_cpadd3_h_C3"
17325 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17327 (match_operand:DI 1 "general_operand" "x")
17328 (match_operand:DI 2 "general_operand" "x")
17330 "CGEN_ENABLE_INSN_P (670)"
17331 "cpadd3.h\\t%0,%1,%2"
17332 [(set_attr "may_trap" "no")
17333 (set_attr "latency" "0")
17334 (set_attr "length" "4")
17335 (set_attr "slot" "cop")
17336 (set_attr "slots" "c3")
17337 (set_attr "stall" "none")])
17340 (define_insn "cgen_intrinsic_cpadd3_h_P0S_P1"
17341 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17343 (match_operand:DI 1 "general_operand" "x")
17344 (match_operand:DI 2 "general_operand" "x")
17346 "CGEN_ENABLE_INSN_P (671)"
17347 "cpadd3.h\\t%0,%1,%2"
17348 [(set_attr "may_trap" "no")
17349 (set_attr "latency" "0")
17350 (set_attr "length" "4")
17351 (set_attr "slot" "cop")
17352 (set_attr "slots" "p0s_p1")
17353 (set_attr "stall" "none")])
17356 (define_insn "cgen_intrinsic_cpadd3_b_C3"
17357 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17359 (match_operand:DI 1 "general_operand" "x")
17360 (match_operand:DI 2 "general_operand" "x")
17362 "CGEN_ENABLE_INSN_P (672)"
17363 "cpadd3.b\\t%0,%1,%2"
17364 [(set_attr "may_trap" "no")
17365 (set_attr "latency" "0")
17366 (set_attr "length" "4")
17367 (set_attr "slot" "cop")
17368 (set_attr "slots" "c3")
17369 (set_attr "stall" "none")])
17372 (define_insn "cgen_intrinsic_cpadd3_b_P0S_P1"
17373 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17375 (match_operand:DI 1 "general_operand" "x")
17376 (match_operand:DI 2 "general_operand" "x")
17378 "CGEN_ENABLE_INSN_P (673)"
17379 "cpadd3.b\\t%0,%1,%2"
17380 [(set_attr "may_trap" "no")
17381 (set_attr "latency" "0")
17382 (set_attr "length" "4")
17383 (set_attr "slot" "cop")
17384 (set_attr "slots" "p0s_p1")
17385 (set_attr "stall" "none")])
17388 (define_insn "cgen_intrinsic_c0nop_P0_P0S"
17389 [(unspec_volatile [
17392 "CGEN_ENABLE_INSN_P (674)"
17394 [(set_attr "may_trap" "no")
17395 (set_attr "latency" "0")
17396 (set_attr "length" "4")
17397 (set_attr "slot" "cop")
17398 (set_attr "slots" "p0_p0s")
17399 (set_attr "stall" "none")])
17402 (define_insn "cgen_intrinsic_cpmoviu_h_C3"
17403 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17405 (match_operand:DI 1 "cgen_h_uint_8a1_immediate" "")
17407 "CGEN_ENABLE_INSN_P (675)"
17408 "cpmoviu.h\\t%0,%1"
17409 [(set_attr "may_trap" "no")
17410 (set_attr "latency" "0")
17411 (set_attr "length" "4")
17412 (set_attr "slot" "cop")
17413 (set_attr "slots" "c3")
17414 (set_attr "stall" "none")])
17417 (define_insn "cgen_intrinsic_cmovh_rn_crm"
17418 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17420 (match_operand:DI 1 "general_operand" "x")
17422 "CGEN_ENABLE_INSN_P (676)"
17424 [(set_attr "may_trap" "no")
17425 (set_attr "latency" "0")
17426 (set_attr "length" "4")
17427 (set_attr "slot" "cop")
17428 (set_attr "slots" "c3")
17429 (set_attr "stall" "none")])
17432 (define_insn "cgen_intrinsic_cmovh_rn_crm_p0"
17433 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17435 (match_operand:DI 1 "general_operand" "x")
17437 "CGEN_ENABLE_INSN_P (677)"
17439 [(set_attr "may_trap" "no")
17440 (set_attr "latency" "0")
17441 (set_attr "length" "4")
17442 (set_attr "slot" "cop")
17443 (set_attr "slots" "p0")
17444 (set_attr "stall" "none")])
17447 (define_insn "cgen_intrinsic_cmovh_crn_rm"
17448 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17450 (match_operand:DI 1 "general_operand" "0")
17451 (match_operand:SI 2 "general_operand" "r")
17453 "CGEN_ENABLE_INSN_P (678)"
17455 [(set_attr "may_trap" "no")
17456 (set_attr "latency" "0")
17457 (set_attr "length" "4")
17458 (set_attr "slot" "cop")
17459 (set_attr "slots" "c3")
17460 (set_attr "stall" "none")])
17463 (define_insn "cgen_intrinsic_cmovh_crn_rm_p0"
17464 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17466 (match_operand:DI 1 "general_operand" "0")
17467 (match_operand:SI 2 "general_operand" "r")
17469 "CGEN_ENABLE_INSN_P (679)"
17471 [(set_attr "may_trap" "no")
17472 (set_attr "latency" "0")
17473 (set_attr "length" "4")
17474 (set_attr "slot" "cop")
17475 (set_attr "slots" "p0")
17476 (set_attr "stall" "none")])
17479 (define_insn "cgen_intrinsic_cmovc_rn_ccrm"
17480 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17481 (unspec_volatile:SI [
17482 (match_operand:SI 1 "general_operand" "y")
17484 "CGEN_ENABLE_INSN_P (680)"
17486 [(set_attr "may_trap" "no")
17487 (set_attr "latency" "0")
17488 (set_attr "length" "4")
17489 (set_attr "slot" "cop")
17490 (set_attr "slots" "c3")
17491 (set_attr "stall" "none")])
17494 (define_insn "cgen_intrinsic_cmovc_rn_ccrm_p0"
17495 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17496 (unspec_volatile:SI [
17497 (match_operand:SI 1 "general_operand" "y")
17499 "CGEN_ENABLE_INSN_P (681)"
17501 [(set_attr "may_trap" "no")
17502 (set_attr "latency" "0")
17503 (set_attr "length" "4")
17504 (set_attr "slot" "cop")
17505 (set_attr "slots" "p0")
17506 (set_attr "stall" "none")])
17509 (define_insn "cgen_intrinsic_cmovc_ccrn_rm"
17510 [(set (match_operand:SI 0 "nonimmediate_operand" "=y")
17511 (unspec_volatile:SI [
17512 (match_operand:SI 1 "general_operand" "r")
17514 "CGEN_ENABLE_INSN_P (682)"
17516 [(set_attr "may_trap" "no")
17517 (set_attr "latency" "0")
17518 (set_attr "length" "4")
17519 (set_attr "slot" "cop")
17520 (set_attr "slots" "c3")
17521 (set_attr "stall" "none")])
17524 (define_insn "cgen_intrinsic_cmovc_ccrn_rm_p0"
17525 [(set (match_operand:SI 0 "nonimmediate_operand" "=y")
17526 (unspec_volatile:SI [
17527 (match_operand:SI 1 "general_operand" "r")
17529 "CGEN_ENABLE_INSN_P (683)"
17531 [(set_attr "may_trap" "no")
17532 (set_attr "latency" "0")
17533 (set_attr "length" "4")
17534 (set_attr "slot" "cop")
17535 (set_attr "slots" "p0")
17536 (set_attr "stall" "none")])
17539 (define_insn "cgen_intrinsic_cmov_rn_crm"
17540 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17542 (match_operand:DI 1 "general_operand" "x")
17544 "CGEN_ENABLE_INSN_P (684)"
17546 [(set_attr "may_trap" "no")
17547 (set_attr "latency" "0")
17548 (set_attr "length" "4")
17549 (set_attr "slot" "cop")
17550 (set_attr "slots" "c3")
17551 (set_attr "stall" "none")])
17554 (define_insn "cgen_intrinsic_cmov_rn_crm_p0"
17555 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17557 (match_operand:DI 1 "general_operand" "x")
17559 "CGEN_ENABLE_INSN_P (685)"
17561 [(set_attr "may_trap" "no")
17562 (set_attr "latency" "0")
17563 (set_attr "length" "4")
17564 (set_attr "slot" "cop")
17565 (set_attr "slots" "p0")
17566 (set_attr "stall" "none")])
17569 (define_insn "cgen_intrinsic_cmov_crn_rm"
17570 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17572 (match_operand:DI 1 "general_operand" "0")
17573 (match_operand:SI 2 "general_operand" "r")
17575 "CGEN_ENABLE_INSN_P (686)"
17577 [(set_attr "may_trap" "no")
17578 (set_attr "latency" "0")
17579 (set_attr "length" "4")
17580 (set_attr "slot" "cop")
17581 (set_attr "slots" "c3")
17582 (set_attr "stall" "none")])
17585 (define_insn "cgen_intrinsic_cmov_crn_rm_p0"
17586 [(set (match_operand:DI 0 "nonimmediate_operand" "=x")
17588 (match_operand:SI 1 "general_operand" "r")
17590 "CGEN_ENABLE_INSN_P (687)"
17592 [(set_attr "may_trap" "no")
17593 (set_attr "latency" "0")
17594 (set_attr "length" "4")
17595 (set_attr "slot" "cop")
17596 (set_attr "slots" "p0")
17597 (set_attr "stall" "none")])
17600 (define_insn "cgen_intrinsic_bsrv"
17602 (if_then_else (eq (unspec [
17603 (match_operand:SI 0 "immediate_operand" "")
17622 "CGEN_ENABLE_INSN_P (688)"
17624 [(set_attr "may_trap" "no")
17625 (set_attr "latency" "0")
17626 (set_attr "length" "4")
17627 (set_attr "slot" "core")
17628 (set_attr "slots" "core")
17629 (set_attr "stall" "none")])
17632 (define_insn "cgen_intrinsic_jsrv"
17635 (match_operand:SI 0 "general_operand" "r")
17651 "CGEN_ENABLE_INSN_P (689)"
17653 [(set_attr "may_trap" "no")
17654 (set_attr "latency" "0")
17655 (set_attr "length" "2")
17656 (set_attr "slot" "core")
17657 (set_attr "slots" "core")
17658 (set_attr "stall" "none")])
17661 (define_insn "cgen_intrinsic_synccp"
17662 [(unspec_volatile [
17665 "CGEN_ENABLE_INSN_P (690)"
17667 [(set_attr "may_trap" "no")
17668 (set_attr "latency" "0")
17669 (set_attr "length" "2")
17670 (set_attr "slot" "core")
17671 (set_attr "slots" "core")
17672 (set_attr "stall" "none")])
17675 (define_insn "cgen_intrinsic_bcpaf"
17677 (if_then_else (eq (unspec [
17678 (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
17679 (match_operand:SI 1 "immediate_operand" "")
17687 "CGEN_ENABLE_INSN_P (691)"
17689 [(set_attr "may_trap" "no")
17690 (set_attr "latency" "0")
17691 (set_attr "length" "4")
17692 (set_attr "slot" "core")
17693 (set_attr "slots" "core")
17694 (set_attr "stall" "none")])
17697 (define_insn "cgen_intrinsic_bcpat"
17699 (if_then_else (eq (unspec [
17700 (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
17701 (match_operand:SI 1 "immediate_operand" "")
17709 "CGEN_ENABLE_INSN_P (692)"
17711 [(set_attr "may_trap" "no")
17712 (set_attr "latency" "0")
17713 (set_attr "length" "4")
17714 (set_attr "slot" "core")
17715 (set_attr "slots" "core")
17716 (set_attr "stall" "none")])
17719 (define_insn "cgen_intrinsic_bcpne"
17721 (if_then_else (eq (unspec [
17722 (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
17723 (match_operand:SI 1 "immediate_operand" "")
17731 "CGEN_ENABLE_INSN_P (693)"
17733 [(set_attr "may_trap" "no")
17734 (set_attr "latency" "0")
17735 (set_attr "length" "4")
17736 (set_attr "slot" "core")
17737 (set_attr "slots" "core")
17738 (set_attr "stall" "none")])
17741 (define_insn "cgen_intrinsic_bcpeq"
17743 (if_then_else (eq (unspec [
17744 (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
17745 (match_operand:SI 1 "immediate_operand" "")
17753 "CGEN_ENABLE_INSN_P (694)"
17755 [(set_attr "may_trap" "no")
17756 (set_attr "latency" "0")
17757 (set_attr "length" "4")
17758 (set_attr "slot" "core")
17759 (set_attr "slots" "core")
17760 (set_attr "stall" "none")])
17763 (define_insn "cgen_intrinsic_lmcpm1"
17764 [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
17766 (match_operand:SI 2 "general_operand" "1")
17767 (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
17771 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17778 "CGEN_ENABLE_INSN_P (695)"
17779 "lmcpm1\\t%0,(%2+),%3"
17780 [(set_attr "may_trap" "no")
17781 (set_attr "latency" "0")
17782 (set_attr "length" "4")
17783 (set_attr "slot" "core")
17784 (set_attr "slots" "core")
17785 (set_attr "stall" "none")])
17788 (define_insn "cgen_intrinsic_smcpm1"
17789 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17791 (match_operand:DI 1 "general_operand" "em")
17792 (match_operand:SI 2 "general_operand" "0")
17793 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17797 "CGEN_ENABLE_INSN_P (696)"
17798 "smcpm1\\t%1,(%2+),%3"
17799 [(set_attr "may_trap" "no")
17800 (set_attr "latency" "0")
17801 (set_attr "length" "4")
17802 (set_attr "slot" "core")
17803 (set_attr "slots" "core")
17804 (set_attr "stall" "none")])
17807 (define_insn "cgen_intrinsic_lwcpm1"
17808 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
17810 (match_operand:SI 2 "general_operand" "1")
17811 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17814 (mem:SI (scratch:SI))
17816 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17822 (mem:SI (scratch:SI))
17824 "CGEN_ENABLE_INSN_P (697)"
17825 "lwcpm1\\t%0,(%2+),%3"
17826 [(set_attr "may_trap" "no")
17827 (set_attr "latency" "0")
17828 (set_attr "length" "4")
17829 (set_attr "slot" "core")
17830 (set_attr "slots" "core")
17831 (set_attr "stall" "none")])
17834 (define_insn "cgen_intrinsic_swcpm1"
17835 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17837 (match_operand:SI 1 "general_operand" "em")
17838 (match_operand:SI 2 "general_operand" "0")
17839 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17843 (set (mem:SI (scratch:SI))
17851 "CGEN_ENABLE_INSN_P (698)"
17852 "swcpm1\\t%1,(%2+),%3"
17853 [(set_attr "may_trap" "no")
17854 (set_attr "latency" "0")
17855 (set_attr "length" "4")
17856 (set_attr "slot" "core")
17857 (set_attr "slots" "core")
17858 (set_attr "stall" "none")])
17861 (define_insn "cgen_intrinsic_lhcpm1"
17862 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
17864 (match_operand:SI 2 "general_operand" "1")
17865 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17868 (mem:SI (scratch:SI))
17870 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17876 (mem:SI (scratch:SI))
17878 "CGEN_ENABLE_INSN_P (699)"
17879 "lhcpm1\\t%0,(%2+),%3"
17880 [(set_attr "may_trap" "no")
17881 (set_attr "latency" "0")
17882 (set_attr "length" "4")
17883 (set_attr "slot" "core")
17884 (set_attr "slots" "core")
17885 (set_attr "stall" "none")])
17888 (define_insn "cgen_intrinsic_shcpm1"
17889 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17891 (match_operand:SI 1 "general_operand" "em")
17892 (match_operand:SI 2 "general_operand" "0")
17893 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17897 (set (mem:SI (scratch:SI))
17905 "CGEN_ENABLE_INSN_P (700)"
17906 "shcpm1\\t%1,(%2+),%3"
17907 [(set_attr "may_trap" "no")
17908 (set_attr "latency" "0")
17909 (set_attr "length" "4")
17910 (set_attr "slot" "core")
17911 (set_attr "slots" "core")
17912 (set_attr "stall" "none")])
17915 (define_insn "cgen_intrinsic_lbcpm1"
17916 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
17918 (match_operand:SI 2 "general_operand" "1")
17919 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17922 (mem:SI (scratch:SI))
17924 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17930 (mem:SI (scratch:SI))
17932 "CGEN_ENABLE_INSN_P (701)"
17933 "lbcpm1\\t%0,(%2+),%3"
17934 [(set_attr "may_trap" "no")
17935 (set_attr "latency" "0")
17936 (set_attr "length" "4")
17937 (set_attr "slot" "core")
17938 (set_attr "slots" "core")
17939 (set_attr "stall" "none")])
17942 (define_insn "cgen_intrinsic_sbcpm1"
17943 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17945 (match_operand:SI 1 "general_operand" "em")
17946 (match_operand:SI 2 "general_operand" "0")
17947 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
17951 (set (mem:SI (scratch:SI))
17959 "CGEN_ENABLE_INSN_P (702)"
17960 "sbcpm1\\t%1,(%2+),%3"
17961 [(set_attr "may_trap" "no")
17962 (set_attr "latency" "0")
17963 (set_attr "length" "4")
17964 (set_attr "slot" "core")
17965 (set_attr "slots" "core")
17966 (set_attr "stall" "none")])
17969 (define_insn "cgen_intrinsic_lmcpm0"
17970 [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
17972 (match_operand:SI 2 "general_operand" "1")
17973 (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
17977 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
17984 "CGEN_ENABLE_INSN_P (703)"
17985 "lmcpm0\\t%0,(%2+),%3"
17986 [(set_attr "may_trap" "no")
17987 (set_attr "latency" "0")
17988 (set_attr "length" "4")
17989 (set_attr "slot" "core")
17990 (set_attr "slots" "core")
17991 (set_attr "stall" "none")])
17994 (define_insn "cgen_intrinsic_smcpm0"
17995 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
17997 (match_operand:DI 1 "general_operand" "em")
17998 (match_operand:SI 2 "general_operand" "0")
17999 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18003 "CGEN_ENABLE_INSN_P (704)"
18004 "smcpm0\\t%1,(%2+),%3"
18005 [(set_attr "may_trap" "no")
18006 (set_attr "latency" "0")
18007 (set_attr "length" "4")
18008 (set_attr "slot" "core")
18009 (set_attr "slots" "core")
18010 (set_attr "stall" "none")])
18013 (define_insn "cgen_intrinsic_lwcpm0"
18014 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18016 (match_operand:SI 2 "general_operand" "1")
18017 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18020 (mem:SI (scratch:SI))
18022 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18028 (mem:SI (scratch:SI))
18030 "CGEN_ENABLE_INSN_P (705)"
18031 "lwcpm0\\t%0,(%2+),%3"
18032 [(set_attr "may_trap" "no")
18033 (set_attr "latency" "0")
18034 (set_attr "length" "4")
18035 (set_attr "slot" "core")
18036 (set_attr "slots" "core")
18037 (set_attr "stall" "none")])
18040 (define_insn "cgen_intrinsic_swcpm0"
18041 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18043 (match_operand:SI 1 "general_operand" "em")
18044 (match_operand:SI 2 "general_operand" "0")
18045 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18049 (set (mem:SI (scratch:SI))
18057 "CGEN_ENABLE_INSN_P (706)"
18058 "swcpm0\\t%1,(%2+),%3"
18059 [(set_attr "may_trap" "no")
18060 (set_attr "latency" "0")
18061 (set_attr "length" "4")
18062 (set_attr "slot" "core")
18063 (set_attr "slots" "core")
18064 (set_attr "stall" "none")])
18067 (define_insn "cgen_intrinsic_lhcpm0"
18068 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18070 (match_operand:SI 2 "general_operand" "1")
18071 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18074 (mem:SI (scratch:SI))
18076 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18082 (mem:SI (scratch:SI))
18084 "CGEN_ENABLE_INSN_P (707)"
18085 "lhcpm0\\t%0,(%2+),%3"
18086 [(set_attr "may_trap" "no")
18087 (set_attr "latency" "0")
18088 (set_attr "length" "4")
18089 (set_attr "slot" "core")
18090 (set_attr "slots" "core")
18091 (set_attr "stall" "none")])
18094 (define_insn "cgen_intrinsic_shcpm0"
18095 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18097 (match_operand:SI 1 "general_operand" "em")
18098 (match_operand:SI 2 "general_operand" "0")
18099 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18103 (set (mem:SI (scratch:SI))
18111 "CGEN_ENABLE_INSN_P (708)"
18112 "shcpm0\\t%1,(%2+),%3"
18113 [(set_attr "may_trap" "no")
18114 (set_attr "latency" "0")
18115 (set_attr "length" "4")
18116 (set_attr "slot" "core")
18117 (set_attr "slots" "core")
18118 (set_attr "stall" "none")])
18121 (define_insn "cgen_intrinsic_lbcpm0"
18122 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18124 (match_operand:SI 2 "general_operand" "1")
18125 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18128 (mem:SI (scratch:SI))
18130 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18136 (mem:SI (scratch:SI))
18138 "CGEN_ENABLE_INSN_P (709)"
18139 "lbcpm0\\t%0,(%2+),%3"
18140 [(set_attr "may_trap" "no")
18141 (set_attr "latency" "0")
18142 (set_attr "length" "4")
18143 (set_attr "slot" "core")
18144 (set_attr "slots" "core")
18145 (set_attr "stall" "none")])
18148 (define_insn "cgen_intrinsic_sbcpm0"
18149 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18151 (match_operand:SI 1 "general_operand" "em")
18152 (match_operand:SI 2 "general_operand" "0")
18153 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18157 (set (mem:SI (scratch:SI))
18165 "CGEN_ENABLE_INSN_P (710)"
18166 "sbcpm0\\t%1,(%2+),%3"
18167 [(set_attr "may_trap" "no")
18168 (set_attr "latency" "0")
18169 (set_attr "length" "4")
18170 (set_attr "slot" "core")
18171 (set_attr "slots" "core")
18172 (set_attr "stall" "none")])
18175 (define_insn "cgen_intrinsic_lmcpa"
18176 [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
18178 (match_operand:SI 2 "general_operand" "1")
18179 (match_operand:DI 3 "cgen_h_sint_10a1_immediate" "")
18181 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18186 "CGEN_ENABLE_INSN_P (711)"
18187 "lmcpa\\t%0,(%2+),%3"
18188 [(set_attr "may_trap" "no")
18189 (set_attr "latency" "0")
18190 (set_attr "length" "4")
18191 (set_attr "slot" "core")
18192 (set_attr "slots" "core")
18193 (set_attr "stall" "load")])
18196 (define_insn "cgen_intrinsic_smcpa"
18197 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18199 (match_operand:DI 1 "general_operand" "em")
18200 (match_operand:SI 2 "general_operand" "0")
18201 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18203 "CGEN_ENABLE_INSN_P (712)"
18204 "smcpa\\t%1,(%2+),%3"
18205 [(set_attr "may_trap" "no")
18206 (set_attr "latency" "0")
18207 (set_attr "length" "4")
18208 (set_attr "slot" "core")
18209 (set_attr "slots" "core")
18210 (set_attr "stall" "store")])
18213 (define_insn "cgen_intrinsic_lwcpa"
18214 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18216 (match_operand:SI 2 "general_operand" "1")
18217 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18218 (mem:SI (scratch:SI))
18220 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18224 (mem:SI (scratch:SI))
18226 "CGEN_ENABLE_INSN_P (713)"
18227 "lwcpa\\t%0,(%2+),%3"
18228 [(set_attr "may_trap" "no")
18229 (set_attr "latency" "0")
18230 (set_attr "length" "4")
18231 (set_attr "slot" "core")
18232 (set_attr "slots" "core")
18233 (set_attr "stall" "load")])
18236 (define_insn "cgen_intrinsic_swcpa"
18237 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18239 (match_operand:SI 1 "general_operand" "em")
18240 (match_operand:SI 2 "general_operand" "0")
18241 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18243 (set (mem:SI (scratch:SI))
18249 "CGEN_ENABLE_INSN_P (714)"
18250 "swcpa\\t%1,(%2+),%3"
18251 [(set_attr "may_trap" "no")
18252 (set_attr "latency" "0")
18253 (set_attr "length" "4")
18254 (set_attr "slot" "core")
18255 (set_attr "slots" "core")
18256 (set_attr "stall" "store")])
18259 (define_insn "cgen_intrinsic_lhcpa"
18260 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18262 (match_operand:SI 2 "general_operand" "1")
18263 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18264 (mem:SI (scratch:SI))
18266 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18270 (mem:SI (scratch:SI))
18272 "CGEN_ENABLE_INSN_P (715)"
18273 "lhcpa\\t%0,(%2+),%3"
18274 [(set_attr "may_trap" "no")
18275 (set_attr "latency" "0")
18276 (set_attr "length" "4")
18277 (set_attr "slot" "core")
18278 (set_attr "slots" "core")
18279 (set_attr "stall" "load")])
18282 (define_insn "cgen_intrinsic_shcpa"
18283 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18285 (match_operand:SI 1 "general_operand" "em")
18286 (match_operand:SI 2 "general_operand" "0")
18287 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18289 (set (mem:SI (scratch:SI))
18295 "CGEN_ENABLE_INSN_P (716)"
18296 "shcpa\\t%1,(%2+),%3"
18297 [(set_attr "may_trap" "no")
18298 (set_attr "latency" "0")
18299 (set_attr "length" "4")
18300 (set_attr "slot" "core")
18301 (set_attr "slots" "core")
18302 (set_attr "stall" "store")])
18305 (define_insn "cgen_intrinsic_lbcpa"
18306 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18308 (match_operand:SI 2 "general_operand" "1")
18309 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18310 (mem:SI (scratch:SI))
18312 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18316 (mem:SI (scratch:SI))
18318 "CGEN_ENABLE_INSN_P (717)"
18319 "lbcpa\\t%0,(%2+),%3"
18320 [(set_attr "may_trap" "no")
18321 (set_attr "latency" "0")
18322 (set_attr "length" "4")
18323 (set_attr "slot" "core")
18324 (set_attr "slots" "core")
18325 (set_attr "stall" "load")])
18328 (define_insn "cgen_intrinsic_sbcpa"
18329 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18331 (match_operand:SI 1 "general_operand" "em")
18332 (match_operand:SI 2 "general_operand" "0")
18333 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
18335 (set (mem:SI (scratch:SI))
18341 "CGEN_ENABLE_INSN_P (718)"
18342 "sbcpa\\t%1,(%2+),%3"
18343 [(set_attr "may_trap" "no")
18344 (set_attr "latency" "0")
18345 (set_attr "length" "4")
18346 (set_attr "slot" "core")
18347 (set_attr "slots" "core")
18348 (set_attr "stall" "store")])
18351 (define_insn "cgen_intrinsic_lmcp16"
18352 [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
18354 (match_operand:DI 1 "cgen_h_sint_16a1_immediate" "")
18355 (match_operand:SI 2 "general_operand" "r")
18357 "CGEN_ENABLE_INSN_P (719)"
18359 [(set_attr "may_trap" "no")
18360 (set_attr "latency" "0")
18361 (set_attr "length" "4")
18362 (set_attr "slot" "core")
18363 (set_attr "slots" "core")
18364 (set_attr "stall" "load")])
18367 (define_insn "cgen_intrinsic_smcp16"
18368 [(unspec_volatile [
18369 (match_operand:DI 0 "general_operand" "em")
18370 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
18371 (match_operand:SI 2 "general_operand" "r")
18373 "CGEN_ENABLE_INSN_P (720)"
18375 [(set_attr "may_trap" "no")
18376 (set_attr "latency" "0")
18377 (set_attr "length" "4")
18378 (set_attr "slot" "core")
18379 (set_attr "slots" "core")
18380 (set_attr "stall" "store")])
18383 (define_insn "cgen_intrinsic_lwcp16"
18384 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18386 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
18387 (match_operand:SI 2 "general_operand" "r")
18388 (mem:SI (scratch:SI))
18390 "CGEN_ENABLE_INSN_P (721)"
18392 [(set_attr "may_trap" "no")
18393 (set_attr "latency" "0")
18394 (set_attr "length" "4")
18395 (set_attr "slot" "core")
18396 (set_attr "slots" "core")
18397 (set_attr "stall" "load")])
18400 (define_insn "cgen_intrinsic_swcp16"
18401 [(set (mem:SI (scratch:SI))
18403 (match_operand:SI 0 "general_operand" "em")
18404 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
18405 (match_operand:SI 2 "general_operand" "r")
18407 "CGEN_ENABLE_INSN_P (722)"
18409 [(set_attr "may_trap" "no")
18410 (set_attr "latency" "0")
18411 (set_attr "length" "4")
18412 (set_attr "slot" "core")
18413 (set_attr "slots" "core")
18414 (set_attr "stall" "store")])
18417 (define_insn "cgen_intrinsic_lmcpi"
18418 [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
18420 (match_operand:SI 2 "general_operand" "1")
18422 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18426 "CGEN_ENABLE_INSN_P (723)"
18428 [(set_attr "may_trap" "no")
18429 (set_attr "latency" "0")
18430 (set_attr "length" "2")
18431 (set_attr "slot" "core")
18432 (set_attr "slots" "core")
18433 (set_attr "stall" "load")])
18436 (define_insn "cgen_intrinsic_smcpi"
18437 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18439 (match_operand:DI 1 "general_operand" "em")
18440 (match_operand:SI 2 "general_operand" "0")
18442 "CGEN_ENABLE_INSN_P (724)"
18444 [(set_attr "may_trap" "no")
18445 (set_attr "latency" "0")
18446 (set_attr "length" "2")
18447 (set_attr "slot" "core")
18448 (set_attr "slots" "core")
18449 (set_attr "stall" "store")])
18452 (define_insn "cgen_intrinsic_lwcpi"
18453 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18455 (match_operand:SI 2 "general_operand" "1")
18456 (mem:SI (scratch:SI))
18458 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
18461 (mem:SI (scratch:SI))
18463 "CGEN_ENABLE_INSN_P (725)"
18465 [(set_attr "may_trap" "no")
18466 (set_attr "latency" "0")
18467 (set_attr "length" "2")
18468 (set_attr "slot" "core")
18469 (set_attr "slots" "core")
18470 (set_attr "stall" "load")])
18473 (define_insn "cgen_intrinsic_swcpi"
18474 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18476 (match_operand:SI 1 "general_operand" "em")
18477 (match_operand:SI 2 "general_operand" "0")
18479 (set (mem:SI (scratch:SI))
18484 "CGEN_ENABLE_INSN_P (726)"
18486 [(set_attr "may_trap" "no")
18487 (set_attr "latency" "0")
18488 (set_attr "length" "2")
18489 (set_attr "slot" "core")
18490 (set_attr "slots" "core")
18491 (set_attr "stall" "store")])
18494 (define_insn "cgen_intrinsic_lmcp"
18495 [(set (match_operand:DI 0 "nonimmediate_operand" "=em")
18497 (match_operand:SI 1 "general_operand" "r")
18499 "CGEN_ENABLE_INSN_P (727)"
18501 [(set_attr "may_trap" "no")
18502 (set_attr "latency" "0")
18503 (set_attr "length" "2")
18504 (set_attr "slot" "core")
18505 (set_attr "slots" "core")
18506 (set_attr "stall" "load")])
18509 (define_insn "cgen_intrinsic_smcp"
18510 [(unspec_volatile [
18511 (match_operand:DI 0 "general_operand" "em")
18512 (match_operand:SI 1 "general_operand" "r")
18514 "CGEN_ENABLE_INSN_P (728)"
18516 [(set_attr "may_trap" "no")
18517 (set_attr "latency" "0")
18518 (set_attr "length" "2")
18519 (set_attr "slot" "core")
18520 (set_attr "slots" "core")
18521 (set_attr "stall" "store")])
18524 (define_insn "cgen_intrinsic_lwcp"
18525 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
18527 (match_operand:SI 1 "general_operand" "r")
18528 (mem:SI (scratch:SI))
18530 "CGEN_ENABLE_INSN_P (729)"
18532 [(set_attr "may_trap" "no")
18533 (set_attr "latency" "0")
18534 (set_attr "length" "2")
18535 (set_attr "slot" "core")
18536 (set_attr "slots" "core")
18537 (set_attr "stall" "load")])
18540 (define_insn "cgen_intrinsic_swcp"
18541 [(set (mem:SI (scratch:SI))
18543 (match_operand:SI 0 "general_operand" "em")
18544 (match_operand:SI 1 "general_operand" "r")
18546 "CGEN_ENABLE_INSN_P (730)"
18548 [(set_attr "may_trap" "no")
18549 (set_attr "latency" "0")
18550 (set_attr "length" "2")
18551 (set_attr "slot" "core")
18552 (set_attr "slots" "core")
18553 (set_attr "stall" "store")])
18556 (define_insn "cgen_intrinsic_ssubu"
18557 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18559 (match_operand:SI 1 "general_operand" "0")
18560 (match_operand:SI 2 "general_operand" "r")
18562 "CGEN_ENABLE_INSN_P (731)"
18564 [(set_attr "may_trap" "no")
18565 (set_attr "latency" "0")
18566 (set_attr "length" "4")
18567 (set_attr "slot" "core")
18568 (set_attr "slots" "core")
18569 (set_attr "stall" "int2")])
18572 (define_insn "cgen_intrinsic_saddu"
18573 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18575 (match_operand:SI 1 "general_operand" "0")
18576 (match_operand:SI 2 "general_operand" "r")
18578 "CGEN_ENABLE_INSN_P (732)"
18580 [(set_attr "may_trap" "no")
18581 (set_attr "latency" "0")
18582 (set_attr "length" "4")
18583 (set_attr "slot" "core")
18584 (set_attr "slots" "core")
18585 (set_attr "stall" "int2")])
18588 (define_insn "cgen_intrinsic_ssub"
18589 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18591 (match_operand:SI 1 "general_operand" "0")
18592 (match_operand:SI 2 "general_operand" "r")
18594 "CGEN_ENABLE_INSN_P (733)"
18596 [(set_attr "may_trap" "no")
18597 (set_attr "latency" "0")
18598 (set_attr "length" "4")
18599 (set_attr "slot" "core")
18600 (set_attr "slots" "core")
18601 (set_attr "stall" "int2")])
18604 (define_insn "cgen_intrinsic_sadd"
18605 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18607 (match_operand:SI 1 "general_operand" "0")
18608 (match_operand:SI 2 "general_operand" "r")
18610 "CGEN_ENABLE_INSN_P (734)"
18612 [(set_attr "may_trap" "no")
18613 (set_attr "latency" "0")
18614 (set_attr "length" "4")
18615 (set_attr "slot" "core")
18616 (set_attr "slots" "core")
18617 (set_attr "stall" "int2")])
18620 (define_insn "cgen_intrinsic_clipu"
18621 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18623 (match_operand:SI 1 "general_operand" "0")
18624 (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
18626 "CGEN_ENABLE_INSN_P (735)"
18628 [(set_attr "may_trap" "no")
18629 (set_attr "latency" "0")
18630 (set_attr "length" "4")
18631 (set_attr "slot" "core")
18632 (set_attr "slots" "core")
18633 (set_attr "stall" "int2")])
18636 (define_insn "cgen_intrinsic_clip"
18637 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18639 (match_operand:SI 1 "general_operand" "0")
18640 (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
18642 "CGEN_ENABLE_INSN_P (736)"
18644 [(set_attr "may_trap" "no")
18645 (set_attr "latency" "0")
18646 (set_attr "length" "4")
18647 (set_attr "slot" "core")
18648 (set_attr "slots" "core")
18649 (set_attr "stall" "int2")])
18652 (define_insn "cgen_intrinsic_maxu"
18653 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18655 (match_operand:SI 1 "general_operand" "0")
18656 (match_operand:SI 2 "general_operand" "r")
18658 "CGEN_ENABLE_INSN_P (737)"
18660 [(set_attr "may_trap" "no")
18661 (set_attr "latency" "0")
18662 (set_attr "length" "4")
18663 (set_attr "slot" "core")
18664 (set_attr "slots" "core")
18665 (set_attr "stall" "int2")])
18668 (define_insn "cgen_intrinsic_minu"
18669 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18671 (match_operand:SI 1 "general_operand" "0")
18672 (match_operand:SI 2 "general_operand" "r")
18674 "CGEN_ENABLE_INSN_P (738)"
18676 [(set_attr "may_trap" "no")
18677 (set_attr "latency" "0")
18678 (set_attr "length" "4")
18679 (set_attr "slot" "core")
18680 (set_attr "slots" "core")
18681 (set_attr "stall" "int2")])
18684 (define_insn "cgen_intrinsic_max"
18685 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18687 (match_operand:SI 1 "general_operand" "0")
18688 (match_operand:SI 2 "general_operand" "r")
18690 "CGEN_ENABLE_INSN_P (739)"
18692 [(set_attr "may_trap" "no")
18693 (set_attr "latency" "0")
18694 (set_attr "length" "4")
18695 (set_attr "slot" "core")
18696 (set_attr "slots" "core")
18697 (set_attr "stall" "int2")])
18700 (define_insn "cgen_intrinsic_min"
18701 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18703 (match_operand:SI 1 "general_operand" "0")
18704 (match_operand:SI 2 "general_operand" "r")
18706 "CGEN_ENABLE_INSN_P (740)"
18708 [(set_attr "may_trap" "no")
18709 (set_attr "latency" "0")
18710 (set_attr "length" "4")
18711 (set_attr "slot" "core")
18712 (set_attr "slots" "core")
18713 (set_attr "stall" "int2")])
18716 (define_insn "cgen_intrinsic_ave"
18717 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18719 (match_operand:SI 1 "general_operand" "0")
18720 (match_operand:SI 2 "general_operand" "r")
18722 "CGEN_ENABLE_INSN_P (741)"
18724 [(set_attr "may_trap" "no")
18725 (set_attr "latency" "0")
18726 (set_attr "length" "4")
18727 (set_attr "slot" "core")
18728 (set_attr "slots" "core")
18729 (set_attr "stall" "int2")])
18732 (define_insn "cgen_intrinsic_abs"
18733 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18735 (match_operand:SI 1 "general_operand" "0")
18736 (match_operand:SI 2 "general_operand" "r")
18738 "CGEN_ENABLE_INSN_P (742)"
18740 [(set_attr "may_trap" "no")
18741 (set_attr "latency" "0")
18742 (set_attr "length" "4")
18743 (set_attr "slot" "core")
18744 (set_attr "slots" "core")
18745 (set_attr "stall" "int2")])
18748 (define_insn "cgen_intrinsic_ldz"
18749 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18751 (match_operand:SI 1 "general_operand" "r")
18753 "CGEN_ENABLE_INSN_P (743)"
18755 [(set_attr "may_trap" "no")
18756 (set_attr "latency" "0")
18757 (set_attr "length" "4")
18758 (set_attr "slot" "core")
18759 (set_attr "slots" "core")
18760 (set_attr "stall" "int2")])
18763 (define_insn "cgen_intrinsic_dbreak"
18765 (unspec_volatile:SI [
18768 "CGEN_ENABLE_INSN_P (744)"
18770 [(set_attr "may_trap" "yes")
18771 (set_attr "latency" "0")
18772 (set_attr "length" "2")
18773 (set_attr "slot" "core")
18774 (set_attr "slots" "core")
18775 (set_attr "stall" "none")])
18778 (define_insn "cgen_intrinsic_dret"
18794 "CGEN_ENABLE_INSN_P (745)"
18796 [(set_attr "may_trap" "no")
18797 (set_attr "latency" "0")
18798 (set_attr "length" "2")
18799 (set_attr "slot" "core")
18800 (set_attr "slots" "core")
18801 (set_attr "stall" "none")])
18804 (define_insn "cgen_intrinsic_divu"
18807 (match_operand:SI 0 "general_operand" "r")
18808 (match_operand:SI 1 "general_operand" "r")
18830 "CGEN_ENABLE_INSN_P (746)"
18832 [(set_attr "may_trap" "yes")
18833 (set_attr "latency" "34")
18834 (set_attr "length" "2")
18835 (set_attr "slot" "core")
18836 (set_attr "slots" "core")
18837 (set_attr "stall" "div")])
18840 (define_insn "cgen_intrinsic_div"
18843 (match_operand:SI 0 "general_operand" "r")
18844 (match_operand:SI 1 "general_operand" "r")
18866 "CGEN_ENABLE_INSN_P (747)"
18868 [(set_attr "may_trap" "yes")
18869 (set_attr "latency" "34")
18870 (set_attr "length" "2")
18871 (set_attr "slot" "core")
18872 (set_attr "slots" "core")
18873 (set_attr "stall" "div")])
18876 (define_insn "cgen_intrinsic_maddru"
18877 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18879 (match_operand:SI 1 "general_operand" "0")
18880 (match_operand:SI 2 "general_operand" "r")
18912 "CGEN_ENABLE_INSN_P (748)"
18914 [(set_attr "may_trap" "no")
18915 (set_attr "latency" "3")
18916 (set_attr "length" "4")
18917 (set_attr "slot" "core")
18918 (set_attr "slots" "core")
18919 (set_attr "stall" "mulr")])
18922 (define_insn "cgen_intrinsic_maddr"
18923 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
18925 (match_operand:SI 1 "general_operand" "0")
18926 (match_operand:SI 2 "general_operand" "r")
18958 "CGEN_ENABLE_INSN_P (749)"
18960 [(set_attr "may_trap" "no")
18961 (set_attr "latency" "3")
18962 (set_attr "length" "4")
18963 (set_attr "slot" "core")
18964 (set_attr "slots" "core")
18965 (set_attr "stall" "mulr")])
18968 (define_insn "cgen_intrinsic_maddu"
18971 (match_operand:SI 0 "general_operand" "r")
18972 (match_operand:SI 1 "general_operand" "r")
18997 "CGEN_ENABLE_INSN_P (750)"
18999 [(set_attr "may_trap" "no")
19000 (set_attr "latency" "0")
19001 (set_attr "length" "4")
19002 (set_attr "slot" "core")
19003 (set_attr "slots" "core")
19004 (set_attr "stall" "mul")])
19007 (define_insn "cgen_intrinsic_madd"
19010 (match_operand:SI 0 "general_operand" "r")
19011 (match_operand:SI 1 "general_operand" "r")
19036 "CGEN_ENABLE_INSN_P (751)"
19038 [(set_attr "may_trap" "no")
19039 (set_attr "latency" "0")
19040 (set_attr "length" "4")
19041 (set_attr "slot" "core")
19042 (set_attr "slots" "core")
19043 (set_attr "stall" "mul")])
19046 (define_insn "cgen_intrinsic_mulru"
19047 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19049 (match_operand:SI 1 "general_operand" "0")
19050 (match_operand:SI 2 "general_operand" "r")
19072 "CGEN_ENABLE_INSN_P (752)"
19074 [(set_attr "may_trap" "no")
19075 (set_attr "latency" "3")
19076 (set_attr "length" "2")
19077 (set_attr "slot" "core")
19078 (set_attr "slots" "core")
19079 (set_attr "stall" "mulr")])
19082 (define_insn "cgen_intrinsic_mulr"
19083 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19085 (match_operand:SI 1 "general_operand" "0")
19086 (match_operand:SI 2 "general_operand" "r")
19108 "CGEN_ENABLE_INSN_P (753)"
19110 [(set_attr "may_trap" "no")
19111 (set_attr "latency" "3")
19112 (set_attr "length" "2")
19113 (set_attr "slot" "core")
19114 (set_attr "slots" "core")
19115 (set_attr "stall" "mulr")])
19118 (define_insn "cgen_intrinsic_mulu"
19121 (match_operand:SI 0 "general_operand" "r")
19122 (match_operand:SI 1 "general_operand" "r")
19139 "CGEN_ENABLE_INSN_P (754)"
19141 [(set_attr "may_trap" "no")
19142 (set_attr "latency" "0")
19143 (set_attr "length" "2")
19144 (set_attr "slot" "core")
19145 (set_attr "slots" "core")
19146 (set_attr "stall" "mul")])
19149 (define_insn "cgen_intrinsic_mul"
19152 (match_operand:SI 0 "general_operand" "r")
19153 (match_operand:SI 1 "general_operand" "r")
19170 "CGEN_ENABLE_INSN_P (755)"
19172 [(set_attr "may_trap" "no")
19173 (set_attr "latency" "0")
19174 (set_attr "length" "2")
19175 (set_attr "slot" "core")
19176 (set_attr "slots" "core")
19177 (set_attr "stall" "mul")])
19180 (define_insn "cgen_intrinsic_cache"
19181 [(unspec_volatile [
19182 (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
19183 (match_operand:SI 1 "general_operand" "r")
19185 "CGEN_ENABLE_INSN_P (756)"
19187 [(set_attr "may_trap" "no")
19188 (set_attr "latency" "0")
19189 (set_attr "length" "2")
19190 (set_attr "slot" "core")
19191 (set_attr "slots" "core")
19192 (set_attr "stall" "none")])
19195 (define_insn "cgen_intrinsic_tas"
19196 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19198 (match_operand:SI 1 "general_operand" "r")
19199 (mem:SI (scratch:SI))
19201 (set (mem:SI (scratch:SI))
19204 (mem:SI (scratch:SI))
19206 "CGEN_ENABLE_INSN_P (757)"
19208 [(set_attr "may_trap" "no")
19209 (set_attr "latency" "0")
19210 (set_attr "length" "2")
19211 (set_attr "slot" "core")
19212 (set_attr "slots" "core")
19213 (set_attr "stall" "none")])
19216 (define_insn "cgen_intrinsic_btstm"
19217 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
19219 (match_operand:SI 1 "general_operand" "r")
19220 (match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
19221 (mem:SI (scratch:SI))
19223 "CGEN_ENABLE_INSN_P (758)"
19224 "btstm\\t$0,(%1),%2"
19225 [(set_attr "may_trap" "no")
19226 (set_attr "latency" "0")
19227 (set_attr "length" "2")
19228 (set_attr "slot" "core")
19229 (set_attr "slots" "core")
19230 (set_attr "stall" "none")])
19233 (define_insn "cgen_intrinsic_bnotm"
19234 [(set (mem:SI (scratch:SI))
19236 (match_operand:SI 0 "general_operand" "r")
19237 (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
19238 (mem:SI (scratch:SI))
19240 "CGEN_ENABLE_INSN_P (759)"
19242 [(set_attr "may_trap" "no")
19243 (set_attr "latency" "0")
19244 (set_attr "length" "2")
19245 (set_attr "slot" "core")
19246 (set_attr "slots" "core")
19247 (set_attr "stall" "none")])
19250 (define_insn "cgen_intrinsic_bclrm"
19251 [(set (mem:SI (scratch:SI))
19253 (match_operand:SI 0 "general_operand" "r")
19254 (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
19255 (mem:SI (scratch:SI))
19257 "CGEN_ENABLE_INSN_P (760)"
19259 [(set_attr "may_trap" "no")
19260 (set_attr "latency" "0")
19261 (set_attr "length" "2")
19262 (set_attr "slot" "core")
19263 (set_attr "slots" "core")
19264 (set_attr "stall" "none")])
19267 (define_insn "cgen_intrinsic_bsetm"
19268 [(set (mem:SI (scratch:SI))
19270 (match_operand:SI 0 "general_operand" "r")
19271 (match_operand:SI 1 "cgen_h_uint_3a1_immediate" "")
19272 (mem:SI (scratch:SI))
19274 "CGEN_ENABLE_INSN_P (761)"
19276 [(set_attr "may_trap" "no")
19277 (set_attr "latency" "0")
19278 (set_attr "length" "2")
19279 (set_attr "slot" "core")
19280 (set_attr "slots" "core")
19281 (set_attr "stall" "none")])
19284 (define_insn "cgen_intrinsic_ldcb"
19285 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19286 (unspec_volatile:SI [
19287 (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
19289 "CGEN_ENABLE_INSN_P (762)"
19291 [(set_attr "may_trap" "no")
19292 (set_attr "latency" "3")
19293 (set_attr "length" "4")
19294 (set_attr "slot" "core")
19295 (set_attr "slots" "core")
19296 (set_attr "stall" "ldcb")])
19299 (define_insn "cgen_intrinsic_stcb"
19300 [(unspec_volatile [
19301 (match_operand:SI 0 "general_operand" "r")
19302 (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
19304 "CGEN_ENABLE_INSN_P (763)"
19306 [(set_attr "may_trap" "no")
19307 (set_attr "latency" "0")
19308 (set_attr "length" "4")
19309 (set_attr "slot" "core")
19310 (set_attr "slots" "core")
19311 (set_attr "stall" "stcb")])
19314 (define_insn "cgen_intrinsic_syncm"
19315 [(unspec_volatile [
19318 "CGEN_ENABLE_INSN_P (764)"
19320 [(set_attr "may_trap" "no")
19321 (set_attr "latency" "0")
19322 (set_attr "length" "2")
19323 (set_attr "slot" "core")
19324 (set_attr "slots" "core")
19325 (set_attr "stall" "none")])
19328 (define_insn "cgen_intrinsic_break"
19330 (unspec_volatile:SI [
19333 "CGEN_ENABLE_INSN_P (765)"
19335 [(set_attr "may_trap" "yes")
19336 (set_attr "latency" "0")
19337 (set_attr "length" "2")
19338 (set_attr "slot" "core")
19339 (set_attr "slots" "core")
19340 (set_attr "stall" "none")])
19343 (define_insn "cgen_intrinsic_swi"
19345 (unspec_volatile:SI [
19346 (match_operand:SI 0 "cgen_h_uint_2a1_immediate" "")
19349 "CGEN_ENABLE_INSN_P (766)"
19351 [(set_attr "may_trap" "yes")
19352 (set_attr "latency" "0")
19353 (set_attr "length" "2")
19354 (set_attr "slot" "core")
19355 (set_attr "slots" "core")
19356 (set_attr "stall" "none")])
19359 (define_insn "cgen_intrinsic_sleep"
19360 [(unspec_volatile [
19363 "CGEN_ENABLE_INSN_P (767)"
19365 [(set_attr "may_trap" "no")
19366 (set_attr "latency" "0")
19367 (set_attr "length" "2")
19368 (set_attr "slot" "core")
19369 (set_attr "slots" "core")
19370 (set_attr "stall" "none")])
19373 (define_insn "cgen_intrinsic_halt"
19374 [(unspec_volatile [
19377 "CGEN_ENABLE_INSN_P (768)"
19379 [(set_attr "may_trap" "no")
19380 (set_attr "latency" "0")
19381 (set_attr "length" "2")
19382 (set_attr "slot" "core")
19383 (set_attr "slots" "core")
19384 (set_attr "stall" "none")])
19387 (define_insn "cgen_intrinsic_reti"
19395 "CGEN_ENABLE_INSN_P (769)"
19397 [(set_attr "may_trap" "no")
19398 (set_attr "latency" "0")
19399 (set_attr "length" "2")
19400 (set_attr "slot" "core")
19401 (set_attr "slots" "core")
19402 (set_attr "stall" "ret")])
19405 (define_insn "cgen_intrinsic_ei"
19407 (unspec_volatile:SI [
19410 "CGEN_ENABLE_INSN_P (770)"
19412 [(set_attr "may_trap" "no")
19413 (set_attr "latency" "0")
19414 (set_attr "length" "2")
19415 (set_attr "slot" "core")
19416 (set_attr "slots" "core")
19417 (set_attr "stall" "none")])
19420 (define_insn "cgen_intrinsic_di"
19422 (unspec_volatile:SI [
19425 "CGEN_ENABLE_INSN_P (771)"
19427 [(set_attr "may_trap" "no")
19428 (set_attr "latency" "0")
19429 (set_attr "length" "2")
19430 (set_attr "slot" "core")
19431 (set_attr "slots" "core")
19432 (set_attr "stall" "none")])
19435 (define_insn "cgen_intrinsic_ldc"
19436 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19437 (unspec_volatile:SI [
19438 (match_operand:SI 1 "general_operand" "c")
19442 "CGEN_ENABLE_INSN_P (772)"
19444 [(set_attr "may_trap" "no")
19445 (set_attr "latency" "2")
19446 (set_attr "length" "2")
19447 (set_attr "slot" "core")
19448 (set_attr "slots" "core")
19449 (set_attr "stall" "ldc")])
19452 (define_insn "cgen_intrinsic_ldc_lo"
19453 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19457 "CGEN_ENABLE_INSN_P (773)"
19459 [(set_attr "may_trap" "no")
19460 (set_attr "latency" "0")
19461 (set_attr "length" "2")
19462 (set_attr "slot" "core")
19463 (set_attr "slots" "core")
19464 (set_attr "stall" "ldc")])
19467 (define_insn "cgen_intrinsic_ldc_hi"
19468 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19472 "CGEN_ENABLE_INSN_P (774)"
19474 [(set_attr "may_trap" "no")
19475 (set_attr "latency" "0")
19476 (set_attr "length" "2")
19477 (set_attr "slot" "core")
19478 (set_attr "slots" "core")
19479 (set_attr "stall" "ldc")])
19482 (define_insn "cgen_intrinsic_ldc_lp"
19483 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
19487 "CGEN_ENABLE_INSN_P (775)"
19489 [(set_attr "may_trap" "no")
19490 (set_attr "latency" "0")
19491 (set_attr "length" "2")
19492 (set_attr "slot" "core")
19493 (set_attr "slots" "core")
19494 (set_attr "stall" "ldc")])
19497 (define_insn "cgen_intrinsic_stc"
19498 [(set (match_operand:SI 0 "nonimmediate_operand" "=c")
19499 (unspec_volatile:SI [
19500 (match_operand:SI 1 "general_operand" "r")
19502 "CGEN_ENABLE_INSN_P (776)"
19504 [(set_attr "may_trap" "no")
19505 (set_attr "latency" "0")
19506 (set_attr "length" "2")
19507 (set_attr "slot" "core")
19508 (set_attr "slots" "core")
19509 (set_attr "stall" "stc")])
19512 (define_insn "cgen_intrinsic_stc_lo"
19515 (match_operand:SI 0 "general_operand" "r")
19521 "CGEN_ENABLE_INSN_P (777)"
19523 [(set_attr "may_trap" "no")
19524 (set_attr "latency" "0")
19525 (set_attr "length" "2")
19526 (set_attr "slot" "core")
19527 (set_attr "slots" "core")
19528 (set_attr "stall" "stc")])
19531 (define_insn "cgen_intrinsic_stc_hi"
19534 (match_operand:SI 0 "general_operand" "r")
19540 "CGEN_ENABLE_INSN_P (778)"
19542 [(set_attr "may_trap" "no")
19543 (set_attr "latency" "0")
19544 (set_attr "length" "2")
19545 (set_attr "slot" "core")
19546 (set_attr "slots" "core")
19547 (set_attr "stall" "stc")])
19550 (define_insn "cgen_intrinsic_stc_lp"
19553 (match_operand:SI 0 "general_operand" "r")
19559 "CGEN_ENABLE_INSN_P (779)"
19561 [(set_attr "may_trap" "no")
19562 (set_attr "latency" "0")
19563 (set_attr "length" "2")
19564 (set_attr "slot" "core")
19565 (set_attr "slots" "core")
19566 (set_attr "stall" "stc")])
19569 (define_insn "cgen_intrinsic_erepeat"
19572 (match_operand:SI 0 "immediate_operand" "")
19606 "CGEN_ENABLE_INSN_P (780)"
19608 [(set_attr "may_trap" "no")
19609 (set_attr "latency" "0")
19610 (set_attr "length" "4")
19611 (set_attr "slot" "core")
19612 (set_attr "slots" "core")
19613 (set_attr "stall" "none")])
19616 (define_insn "cgen_intrinsic_repeat"
19619 (match_operand:SI 0 "general_operand" "r")
19620 (match_operand:SI 1 "immediate_operand" "")
19659 "CGEN_ENABLE_INSN_P (781)"
19661 [(set_attr "may_trap" "no")
19662 (set_attr "latency" "0")
19663 (set_attr "length" "4")
19664 (set_attr "slot" "core")
19665 (set_attr "slots" "core")
19666 (set_attr "stall" "none")])
19669 (define_insn "cgen_intrinsic_ret"
19676 "CGEN_ENABLE_INSN_P (782)"
19678 [(set_attr "may_trap" "no")
19679 (set_attr "latency" "0")
19680 (set_attr "length" "2")
19681 (set_attr "slot" "core")
19682 (set_attr "slots" "core")
19683 (set_attr "stall" "ret")])
19686 (define_insn "cgen_intrinsic_jsr"
19689 (match_operand:SI 0 "general_operand" "r")
19705 "CGEN_ENABLE_INSN_P (783)"
19707 [(set_attr "may_trap" "no")
19708 (set_attr "latency" "0")
19709 (set_attr "length" "2")
19710 (set_attr "slot" "core")
19711 (set_attr "slots" "core")
19712 (set_attr "stall" "none")])
19715 (define_insn "cgen_intrinsic_jmp24"
19717 (if_then_else (eq (unspec [
19718 (match_operand:SI 0 "immediate_operand" "")
19725 "CGEN_ENABLE_INSN_P (784)"
19727 [(set_attr "may_trap" "no")
19728 (set_attr "latency" "0")
19729 (set_attr "length" "4")
19730 (set_attr "slot" "core")
19731 (set_attr "slots" "core")
19732 (set_attr "stall" "none")])
19735 (define_insn "cgen_intrinsic_jmp"
19738 (match_operand:SI 0 "general_operand" "r")
19742 "CGEN_ENABLE_INSN_P (785)"
19744 [(set_attr "may_trap" "no")
19745 (set_attr "latency" "0")
19746 (set_attr "length" "2")
19747 (set_attr "slot" "core")
19748 (set_attr "slots" "core")
19749 (set_attr "stall" "none")])
19752 (define_insn "cgen_intrinsic_bsr12"
19754 (if_then_else (eq (unspec [
19755 (match_operand:SI 0 "immediate_operand" "")
19774 "CGEN_ENABLE_INSN_P (786)"
19776 [(set_attr "may_trap" "no")
19777 (set_attr "latency" "0")
19778 (set_attr "length" "2")
19779 (set_attr "slot" "core")
19780 (set_attr "slots" "core")
19781 (set_attr "stall" "none")])
19784 (define_insn "cgen_intrinsic_bsr24"
19786 (if_then_else (eq (unspec [
19787 (match_operand:SI 0 "immediate_operand" "")
19806 "CGEN_ENABLE_INSN_P (787)"
19808 [(set_attr "may_trap" "no")
19809 (set_attr "latency" "0")
19810 (set_attr "length" "4")
19811 (set_attr "slot" "core")
19812 (set_attr "slots" "core")
19813 (set_attr "stall" "none")])
19816 (define_insn "cgen_intrinsic_bne"
19818 (if_then_else (eq (unspec [
19819 (match_operand:SI 0 "general_operand" "r")
19820 (match_operand:SI 1 "general_operand" "r")
19821 (match_operand:SI 2 "immediate_operand" "")
19828 "CGEN_ENABLE_INSN_P (788)"
19830 [(set_attr "may_trap" "no")
19831 (set_attr "latency" "0")
19832 (set_attr "length" "4")
19833 (set_attr "slot" "core")
19834 (set_attr "slots" "core")
19835 (set_attr "stall" "none")])
19838 (define_insn "cgen_intrinsic_beq"
19840 (if_then_else (eq (unspec [
19841 (match_operand:SI 0 "general_operand" "r")
19842 (match_operand:SI 1 "general_operand" "r")
19843 (match_operand:SI 2 "immediate_operand" "")
19850 "CGEN_ENABLE_INSN_P (789)"
19852 [(set_attr "may_trap" "no")
19853 (set_attr "latency" "0")
19854 (set_attr "length" "4")
19855 (set_attr "slot" "core")
19856 (set_attr "slots" "core")
19857 (set_attr "stall" "none")])
19860 (define_insn "cgen_intrinsic_bgei"
19862 (if_then_else (eq (unspec [
19863 (match_operand:SI 0 "general_operand" "r")
19864 (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
19865 (match_operand:SI 2 "immediate_operand" "")
19872 "CGEN_ENABLE_INSN_P (790)"
19874 [(set_attr "may_trap" "no")
19875 (set_attr "latency" "0")
19876 (set_attr "length" "4")
19877 (set_attr "slot" "core")
19878 (set_attr "slots" "core")
19879 (set_attr "stall" "none")])
19882 (define_insn "cgen_intrinsic_blti"
19884 (if_then_else (eq (unspec [
19885 (match_operand:SI 0 "general_operand" "r")
19886 (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
19887 (match_operand:SI 2 "immediate_operand" "")
19894 "CGEN_ENABLE_INSN_P (791)"
19896 [(set_attr "may_trap" "no")
19897 (set_attr "latency" "0")
19898 (set_attr "length" "4")
19899 (set_attr "slot" "core")
19900 (set_attr "slots" "core")
19901 (set_attr "stall" "none")])
19904 (define_insn "cgen_intrinsic_bnei"
19906 (if_then_else (eq (unspec [
19907 (match_operand:SI 0 "general_operand" "r")
19908 (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
19909 (match_operand:SI 2 "immediate_operand" "")
19916 "CGEN_ENABLE_INSN_P (792)"
19918 [(set_attr "may_trap" "no")
19919 (set_attr "latency" "0")
19920 (set_attr "length" "4")
19921 (set_attr "slot" "core")
19922 (set_attr "slots" "core")
19923 (set_attr "stall" "none")])
19926 (define_insn "cgen_intrinsic_beqi"
19928 (if_then_else (eq (unspec [
19929 (match_operand:SI 0 "general_operand" "r")
19930 (match_operand:SI 1 "cgen_h_uint_4a1_immediate" "")
19931 (match_operand:SI 2 "immediate_operand" "")
19938 "CGEN_ENABLE_INSN_P (793)"
19940 [(set_attr "may_trap" "no")
19941 (set_attr "latency" "0")
19942 (set_attr "length" "4")
19943 (set_attr "slot" "core")
19944 (set_attr "slots" "core")
19945 (set_attr "stall" "none")])
19948 (define_insn "cgen_intrinsic_bnez"
19950 (if_then_else (eq (unspec [
19951 (match_operand:SI 0 "general_operand" "r")
19952 (match_operand:SI 1 "immediate_operand" "")
19959 "CGEN_ENABLE_INSN_P (794)"
19961 [(set_attr "may_trap" "no")
19962 (set_attr "latency" "0")
19963 (set_attr "length" "2")
19964 (set_attr "slot" "core")
19965 (set_attr "slots" "core")
19966 (set_attr "stall" "none")])
19969 (define_insn "cgen_intrinsic_beqz"
19971 (if_then_else (eq (unspec [
19972 (match_operand:SI 0 "general_operand" "r")
19973 (match_operand:SI 1 "immediate_operand" "")
19980 "CGEN_ENABLE_INSN_P (795)"
19982 [(set_attr "may_trap" "no")
19983 (set_attr "latency" "0")
19984 (set_attr "length" "2")
19985 (set_attr "slot" "core")
19986 (set_attr "slots" "core")
19987 (set_attr "stall" "none")])
19990 (define_insn "cgen_intrinsic_bra"
19992 (if_then_else (eq (unspec [
19993 (match_operand:SI 0 "immediate_operand" "")
20000 "CGEN_ENABLE_INSN_P (796)"
20002 [(set_attr "may_trap" "no")
20003 (set_attr "latency" "0")
20004 (set_attr "length" "2")
20005 (set_attr "slot" "core")
20006 (set_attr "slots" "core")
20007 (set_attr "stall" "none")])
20010 (define_insn "cgen_intrinsic_fsft"
20011 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20012 (unspec_volatile:SI [
20013 (match_operand:SI 1 "general_operand" "0")
20014 (match_operand:SI 2 "general_operand" "r")
20017 "CGEN_ENABLE_INSN_P (797)"
20019 [(set_attr "may_trap" "no")
20020 (set_attr "latency" "0")
20021 (set_attr "length" "2")
20022 (set_attr "slot" "core")
20023 (set_attr "slots" "core")
20024 (set_attr "stall" "fsft")])
20027 (define_insn "cgen_intrinsic_sll3"
20028 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20030 (match_operand:SI 1 "general_operand" "r")
20031 (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20033 "CGEN_ENABLE_INSN_P (798)"
20035 [(set_attr "may_trap" "no")
20036 (set_attr "latency" "0")
20037 (set_attr "length" "2")
20038 (set_attr "slot" "core")
20039 (set_attr "slots" "core")
20040 (set_attr "stall" "int2")])
20043 (define_insn "cgen_intrinsic_slli"
20044 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20046 (match_operand:SI 1 "general_operand" "0")
20047 (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20049 "CGEN_ENABLE_INSN_P (799)"
20051 [(set_attr "may_trap" "no")
20052 (set_attr "latency" "0")
20053 (set_attr "length" "2")
20054 (set_attr "slot" "core")
20055 (set_attr "slots" "core")
20056 (set_attr "shiftop" "operand2")])
20059 (define_insn "cgen_intrinsic_srli"
20060 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20062 (match_operand:SI 1 "general_operand" "0")
20063 (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20065 "CGEN_ENABLE_INSN_P (800)"
20067 [(set_attr "may_trap" "no")
20068 (set_attr "latency" "0")
20069 (set_attr "length" "2")
20070 (set_attr "slot" "core")
20071 (set_attr "slots" "core")
20072 (set_attr "shiftop" "operand2")])
20075 (define_insn "cgen_intrinsic_srai"
20076 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20078 (match_operand:SI 1 "general_operand" "0")
20079 (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20081 "CGEN_ENABLE_INSN_P (801)"
20083 [(set_attr "may_trap" "no")
20084 (set_attr "latency" "0")
20085 (set_attr "length" "2")
20086 (set_attr "slot" "core")
20087 (set_attr "slots" "core")
20088 (set_attr "shiftop" "operand2")])
20091 (define_insn "cgen_intrinsic_sll"
20092 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20094 (match_operand:SI 1 "general_operand" "0")
20095 (match_operand:SI 2 "general_operand" "r")
20097 "CGEN_ENABLE_INSN_P (802)"
20099 [(set_attr "may_trap" "no")
20100 (set_attr "latency" "0")
20101 (set_attr "length" "2")
20102 (set_attr "slot" "core")
20103 (set_attr "slots" "core")
20104 (set_attr "stall" "int2")])
20107 (define_insn "cgen_intrinsic_srl"
20108 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20110 (match_operand:SI 1 "general_operand" "0")
20111 (match_operand:SI 2 "general_operand" "r")
20113 "CGEN_ENABLE_INSN_P (803)"
20115 [(set_attr "may_trap" "no")
20116 (set_attr "latency" "0")
20117 (set_attr "length" "2")
20118 (set_attr "slot" "core")
20119 (set_attr "slots" "core")
20120 (set_attr "stall" "int2")])
20123 (define_insn "cgen_intrinsic_sra"
20124 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20126 (match_operand:SI 1 "general_operand" "0")
20127 (match_operand:SI 2 "general_operand" "r")
20129 "CGEN_ENABLE_INSN_P (804)"
20131 [(set_attr "may_trap" "no")
20132 (set_attr "latency" "0")
20133 (set_attr "length" "2")
20134 (set_attr "slot" "core")
20135 (set_attr "slots" "core")
20136 (set_attr "stall" "int2")])
20139 (define_insn "cgen_intrinsic_xor3"
20140 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20142 (match_operand:SI 1 "general_operand" "r")
20143 (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
20145 "CGEN_ENABLE_INSN_P (805)"
20147 [(set_attr "may_trap" "no")
20148 (set_attr "latency" "0")
20149 (set_attr "length" "4")
20150 (set_attr "slot" "core")
20151 (set_attr "slots" "core")
20152 (set_attr "stall" "none")])
20155 (define_insn "cgen_intrinsic_and3"
20156 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20158 (match_operand:SI 1 "general_operand" "r")
20159 (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
20161 "CGEN_ENABLE_INSN_P (806)"
20163 [(set_attr "may_trap" "no")
20164 (set_attr "latency" "0")
20165 (set_attr "length" "4")
20166 (set_attr "slot" "core")
20167 (set_attr "slots" "core")
20168 (set_attr "stall" "none")])
20171 (define_insn "cgen_intrinsic_or3"
20172 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20174 (match_operand:SI 1 "general_operand" "r")
20175 (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
20177 "CGEN_ENABLE_INSN_P (807)"
20179 [(set_attr "may_trap" "no")
20180 (set_attr "latency" "0")
20181 (set_attr "length" "4")
20182 (set_attr "slot" "core")
20183 (set_attr "slots" "core")
20184 (set_attr "stall" "none")])
20187 (define_insn "cgen_intrinsic_nor"
20188 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20190 (match_operand:SI 1 "general_operand" "0")
20191 (match_operand:SI 2 "general_operand" "r")
20193 "CGEN_ENABLE_INSN_P (808)"
20195 [(set_attr "may_trap" "no")
20196 (set_attr "latency" "0")
20197 (set_attr "length" "2")
20198 (set_attr "slot" "core")
20199 (set_attr "slots" "core")
20200 (set_attr "stall" "none")])
20203 (define_insn "cgen_intrinsic_xor"
20204 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20206 (match_operand:SI 1 "general_operand" "0")
20207 (match_operand:SI 2 "general_operand" "r")
20209 "CGEN_ENABLE_INSN_P (809)"
20211 [(set_attr "may_trap" "no")
20212 (set_attr "latency" "0")
20213 (set_attr "length" "2")
20214 (set_attr "slot" "core")
20215 (set_attr "slots" "core")
20216 (set_attr "stall" "none")])
20219 (define_insn "cgen_intrinsic_and"
20220 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20222 (match_operand:SI 1 "general_operand" "0")
20223 (match_operand:SI 2 "general_operand" "r")
20225 "CGEN_ENABLE_INSN_P (810)"
20227 [(set_attr "may_trap" "no")
20228 (set_attr "latency" "0")
20229 (set_attr "length" "2")
20230 (set_attr "slot" "core")
20231 (set_attr "slots" "core")
20232 (set_attr "stall" "none")])
20235 (define_insn "cgen_intrinsic_or"
20236 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20238 (match_operand:SI 1 "general_operand" "0")
20239 (match_operand:SI 2 "general_operand" "r")
20241 "CGEN_ENABLE_INSN_P (811)"
20243 [(set_attr "may_trap" "no")
20244 (set_attr "latency" "0")
20245 (set_attr "length" "2")
20246 (set_attr "slot" "core")
20247 (set_attr "slots" "core")
20248 (set_attr "stall" "none")])
20251 (define_insn "cgen_intrinsic_sltu3x"
20252 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20254 (match_operand:SI 1 "general_operand" "r")
20255 (match_operand:SI 2 "cgen_h_uint_16a1_immediate" "")
20257 "CGEN_ENABLE_INSN_P (812)"
20259 [(set_attr "may_trap" "no")
20260 (set_attr "latency" "0")
20261 (set_attr "length" "4")
20262 (set_attr "slot" "core")
20263 (set_attr "slots" "core")
20264 (set_attr "stall" "none")])
20267 (define_insn "cgen_intrinsic_slt3x"
20268 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20270 (match_operand:SI 1 "general_operand" "r")
20271 (match_operand:SI 2 "cgen_h_sint_16a1_immediate" "")
20273 "CGEN_ENABLE_INSN_P (813)"
20275 [(set_attr "may_trap" "no")
20276 (set_attr "latency" "0")
20277 (set_attr "length" "4")
20278 (set_attr "slot" "core")
20279 (set_attr "slots" "core")
20280 (set_attr "stall" "none")])
20283 (define_insn "cgen_intrinsic_add3x"
20284 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20286 (match_operand:SI 1 "general_operand" "r")
20287 (match_operand:SI 2 "cgen_h_sint_16a1_immediate" "")
20289 "CGEN_ENABLE_INSN_P (814)"
20291 [(set_attr "may_trap" "no")
20292 (set_attr "latency" "0")
20293 (set_attr "length" "4")
20294 (set_attr "slot" "core")
20295 (set_attr "slots" "core")
20296 (set_attr "stall" "none")])
20299 (define_insn "cgen_intrinsic_sl2ad3"
20300 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20302 (match_operand:SI 1 "general_operand" "r")
20303 (match_operand:SI 2 "general_operand" "r")
20305 "CGEN_ENABLE_INSN_P (815)"
20306 "sl2ad3\\t$0,%1,%2"
20307 [(set_attr "may_trap" "no")
20308 (set_attr "latency" "0")
20309 (set_attr "length" "2")
20310 (set_attr "slot" "core")
20311 (set_attr "slots" "core")
20312 (set_attr "stall" "int2")])
20315 (define_insn "cgen_intrinsic_sl1ad3"
20316 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20318 (match_operand:SI 1 "general_operand" "r")
20319 (match_operand:SI 2 "general_operand" "r")
20321 "CGEN_ENABLE_INSN_P (816)"
20322 "sl1ad3\\t$0,%1,%2"
20323 [(set_attr "may_trap" "no")
20324 (set_attr "latency" "0")
20325 (set_attr "length" "2")
20326 (set_attr "slot" "core")
20327 (set_attr "slots" "core")
20328 (set_attr "stall" "int2")])
20331 (define_insn "cgen_intrinsic_sltu3i"
20332 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20334 (match_operand:SI 1 "general_operand" "r")
20335 (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20337 "CGEN_ENABLE_INSN_P (817)"
20339 [(set_attr "may_trap" "no")
20340 (set_attr "latency" "0")
20341 (set_attr "length" "2")
20342 (set_attr "slot" "core")
20343 (set_attr "slots" "core")
20344 (set_attr "stall" "none")])
20347 (define_insn "cgen_intrinsic_slt3i"
20348 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20350 (match_operand:SI 1 "general_operand" "r")
20351 (match_operand:SI 2 "cgen_h_uint_5a1_immediate" "")
20353 "CGEN_ENABLE_INSN_P (818)"
20355 [(set_attr "may_trap" "no")
20356 (set_attr "latency" "0")
20357 (set_attr "length" "2")
20358 (set_attr "slot" "core")
20359 (set_attr "slots" "core")
20360 (set_attr "stall" "none")])
20363 (define_insn "cgen_intrinsic_sltu3"
20364 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20366 (match_operand:SI 1 "general_operand" "r")
20367 (match_operand:SI 2 "general_operand" "r")
20369 "CGEN_ENABLE_INSN_P (819)"
20371 [(set_attr "may_trap" "no")
20372 (set_attr "latency" "0")
20373 (set_attr "length" "2")
20374 (set_attr "slot" "core")
20375 (set_attr "slots" "core")
20376 (set_attr "stall" "none")])
20379 (define_insn "cgen_intrinsic_slt3"
20380 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20382 (match_operand:SI 1 "general_operand" "r")
20383 (match_operand:SI 2 "general_operand" "r")
20385 "CGEN_ENABLE_INSN_P (820)"
20387 [(set_attr "may_trap" "no")
20388 (set_attr "latency" "0")
20389 (set_attr "length" "2")
20390 (set_attr "slot" "core")
20391 (set_attr "slots" "core")
20392 (set_attr "stall" "none")])
20395 (define_insn "cgen_intrinsic_neg"
20396 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20398 (match_operand:SI 1 "general_operand" "r")
20400 "CGEN_ENABLE_INSN_P (821)"
20402 [(set_attr "may_trap" "no")
20403 (set_attr "latency" "0")
20404 (set_attr "length" "2")
20405 (set_attr "slot" "core")
20406 (set_attr "slots" "core")
20407 (set_attr "stall" "none")])
20410 (define_insn "cgen_intrinsic_sbvck3"
20411 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20413 (match_operand:SI 1 "general_operand" "r")
20414 (match_operand:SI 2 "general_operand" "r")
20416 "CGEN_ENABLE_INSN_P (822)"
20417 "sbvck3\\t$0,%1,%2"
20418 [(set_attr "may_trap" "no")
20419 (set_attr "latency" "0")
20420 (set_attr "length" "2")
20421 (set_attr "slot" "core")
20422 (set_attr "slots" "core")
20423 (set_attr "stall" "advck")])
20426 (define_insn "cgen_intrinsic_sub"
20427 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20429 (match_operand:SI 1 "general_operand" "0")
20430 (match_operand:SI 2 "general_operand" "r")
20432 "CGEN_ENABLE_INSN_P (823)"
20434 [(set_attr "may_trap" "no")
20435 (set_attr "latency" "0")
20436 (set_attr "length" "2")
20437 (set_attr "slot" "core")
20438 (set_attr "slots" "core")
20439 (set_attr "stall" "none")])
20442 (define_insn "cgen_intrinsic_advck3"
20443 [(set (match_operand:SI 0 "nonimmediate_operand" "=z")
20445 (match_operand:SI 1 "general_operand" "r")
20446 (match_operand:SI 2 "general_operand" "r")
20448 "CGEN_ENABLE_INSN_P (824)"
20449 "advck3\\t$0,%1,%2"
20450 [(set_attr "may_trap" "no")
20451 (set_attr "latency" "0")
20452 (set_attr "length" "2")
20453 (set_attr "slot" "core")
20454 (set_attr "slots" "core")
20455 (set_attr "stall" "advck")])
20458 (define_insn "cgen_intrinsic_add3i"
20459 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20461 (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20464 "CGEN_ENABLE_INSN_P (825)"
20466 [(set_attr "may_trap" "no")
20467 (set_attr "latency" "0")
20468 (set_attr "length" "2")
20469 (set_attr "slot" "core")
20470 (set_attr "slots" "core")
20471 (set_attr "stall" "none")])
20474 (define_insn "cgen_intrinsic_add"
20475 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20477 (match_operand:SI 1 "general_operand" "0")
20478 (match_operand:SI 2 "cgen_h_sint_6a1_immediate" "")
20480 "CGEN_ENABLE_INSN_P (826)"
20482 [(set_attr "may_trap" "no")
20483 (set_attr "latency" "0")
20484 (set_attr "length" "2")
20485 (set_attr "slot" "core")
20486 (set_attr "slots" "core")
20487 (set_attr "stall" "none")])
20490 (define_insn "cgen_intrinsic_add3"
20491 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20493 (match_operand:SI 1 "general_operand" "r")
20494 (match_operand:SI 2 "general_operand" "r")
20496 "CGEN_ENABLE_INSN_P (827)"
20498 [(set_attr "may_trap" "no")
20499 (set_attr "latency" "0")
20500 (set_attr "length" "2")
20501 (set_attr "slot" "core")
20502 (set_attr "slots" "core")
20503 (set_attr "stall" "none")])
20506 (define_insn "cgen_intrinsic_movh"
20507 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20509 (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
20511 "CGEN_ENABLE_INSN_P (828)"
20513 [(set_attr "may_trap" "no")
20514 (set_attr "latency" "0")
20515 (set_attr "length" "4")
20516 (set_attr "slot" "core")
20517 (set_attr "slots" "core")
20518 (set_attr "stall" "none")])
20521 (define_insn "cgen_intrinsic_movu16"
20522 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20524 (match_operand:SI 1 "cgen_h_uint_16a1_immediate" "")
20526 "CGEN_ENABLE_INSN_P (829)"
20528 [(set_attr "may_trap" "no")
20529 (set_attr "latency" "0")
20530 (set_attr "length" "4")
20531 (set_attr "slot" "core")
20532 (set_attr "slots" "core")
20533 (set_attr "stall" "none")])
20536 (define_insn "cgen_intrinsic_movu24"
20537 [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20539 (match_operand:SI 1 "cgen_h_uint_24a1_immediate" "")
20541 "CGEN_ENABLE_INSN_P (830)"
20543 [(set_attr "may_trap" "no")
20544 (set_attr "latency" "0")
20545 (set_attr "length" "4")
20546 (set_attr "slot" "core")
20547 (set_attr "slots" "core")
20548 (set_attr "stall" "none")])
20551 (define_insn "cgen_intrinsic_movi8"
20552 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20554 (match_operand:SI 1 "cgen_h_sint_8a1_immediate" "")
20556 "CGEN_ENABLE_INSN_P (831)"
20558 [(set_attr "may_trap" "no")
20559 (set_attr "latency" "0")
20560 (set_attr "length" "2")
20561 (set_attr "slot" "core")
20562 (set_attr "slots" "core")
20563 (set_attr "stall" "none")])
20566 (define_insn "cgen_intrinsic_movi16"
20567 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20569 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20571 "CGEN_ENABLE_INSN_P (832)"
20573 [(set_attr "may_trap" "no")
20574 (set_attr "latency" "0")
20575 (set_attr "length" "4")
20576 (set_attr "slot" "core")
20577 (set_attr "slots" "core")
20578 (set_attr "stall" "none")])
20581 (define_insn "cgen_intrinsic_mov"
20582 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20584 (match_operand:SI 1 "general_operand" "r")
20586 "CGEN_ENABLE_INSN_P (833)"
20588 [(set_attr "may_trap" "no")
20589 (set_attr "latency" "0")
20590 (set_attr "length" "2")
20591 (set_attr "slot" "core")
20592 (set_attr "slots" "core")
20593 (set_attr "stall" "none")])
20596 (define_insn "cgen_intrinsic_ssarb"
20598 (unspec_volatile:SI [
20599 (match_operand:SI 0 "cgen_h_sint_2a1_immediate" "")
20600 (match_operand:SI 1 "general_operand" "r")
20602 "CGEN_ENABLE_INSN_P (834)"
20604 [(set_attr "may_trap" "no")
20605 (set_attr "latency" "0")
20606 (set_attr "length" "2")
20607 (set_attr "slot" "core")
20608 (set_attr "slots" "core")
20609 (set_attr "stall" "ssarb")])
20612 (define_insn "cgen_intrinsic_extuh"
20613 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20615 (match_operand:SI 1 "general_operand" "0")
20617 "CGEN_ENABLE_INSN_P (835)"
20619 [(set_attr "may_trap" "no")
20620 (set_attr "latency" "0")
20621 (set_attr "length" "2")
20622 (set_attr "slot" "core")
20623 (set_attr "slots" "core")
20624 (set_attr "stall" "none")])
20627 (define_insn "cgen_intrinsic_extub"
20628 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20630 (match_operand:SI 1 "general_operand" "0")
20632 "CGEN_ENABLE_INSN_P (836)"
20634 [(set_attr "may_trap" "no")
20635 (set_attr "latency" "0")
20636 (set_attr "length" "2")
20637 (set_attr "slot" "core")
20638 (set_attr "slots" "core")
20639 (set_attr "stall" "none")])
20642 (define_insn "cgen_intrinsic_exth"
20643 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20645 (match_operand:SI 1 "general_operand" "0")
20647 "CGEN_ENABLE_INSN_P (837)"
20649 [(set_attr "may_trap" "no")
20650 (set_attr "latency" "0")
20651 (set_attr "length" "2")
20652 (set_attr "slot" "core")
20653 (set_attr "slots" "core")
20654 (set_attr "stall" "none")])
20657 (define_insn "cgen_intrinsic_extb"
20658 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20660 (match_operand:SI 1 "general_operand" "0")
20662 "CGEN_ENABLE_INSN_P (838)"
20664 [(set_attr "may_trap" "no")
20665 (set_attr "latency" "0")
20666 (set_attr "length" "2")
20667 (set_attr "slot" "core")
20668 (set_attr "slots" "core")
20669 (set_attr "stall" "none")])
20672 (define_insn "cgen_intrinsic_lw24"
20673 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20675 (match_operand:SI 1 "cgen_h_uint_22a4_immediate" "")
20676 (mem:SI (scratch:SI))
20678 "CGEN_ENABLE_INSN_P (839)"
20680 [(set_attr "may_trap" "no")
20681 (set_attr "latency" "2")
20682 (set_attr "length" "4")
20683 (set_attr "slot" "core")
20684 (set_attr "slots" "core")
20685 (set_attr "stall" "load")])
20688 (define_insn "cgen_intrinsic_sw24"
20689 [(set (mem:SI (scratch:SI))
20691 (match_operand:SI 0 "general_operand" "r")
20692 (match_operand:SI 1 "cgen_h_uint_22a4_immediate" "")
20694 "CGEN_ENABLE_INSN_P (840)"
20696 [(set_attr "may_trap" "no")
20697 (set_attr "latency" "0")
20698 (set_attr "length" "4")
20699 (set_attr "slot" "core")
20700 (set_attr "slots" "core")
20701 (set_attr "stall" "store")])
20704 (define_insn "cgen_intrinsic_lhu16"
20705 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20707 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20708 (match_operand:SI 2 "general_operand" "r")
20709 (mem:SI (scratch:SI))
20711 "CGEN_ENABLE_INSN_P (841)"
20713 [(set_attr "may_trap" "no")
20714 (set_attr "latency" "2")
20715 (set_attr "length" "4")
20716 (set_attr "slot" "core")
20717 (set_attr "slots" "core")
20718 (set_attr "stall" "load")])
20721 (define_insn "cgen_intrinsic_lbu16"
20722 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20724 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20725 (match_operand:SI 2 "general_operand" "r")
20726 (mem:SI (scratch:SI))
20728 "CGEN_ENABLE_INSN_P (842)"
20730 [(set_attr "may_trap" "no")
20731 (set_attr "latency" "2")
20732 (set_attr "length" "4")
20733 (set_attr "slot" "core")
20734 (set_attr "slots" "core")
20735 (set_attr "stall" "load")])
20738 (define_insn "cgen_intrinsic_lw16"
20739 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20741 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20742 (match_operand:SI 2 "general_operand" "r")
20743 (mem:SI (scratch:SI))
20745 "CGEN_ENABLE_INSN_P (843)"
20747 [(set_attr "may_trap" "no")
20748 (set_attr "latency" "2")
20749 (set_attr "length" "4")
20750 (set_attr "slot" "core")
20751 (set_attr "slots" "core")
20752 (set_attr "stall" "load")])
20755 (define_insn "cgen_intrinsic_lh16"
20756 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20758 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20759 (match_operand:SI 2 "general_operand" "r")
20760 (mem:SI (scratch:SI))
20762 "CGEN_ENABLE_INSN_P (844)"
20764 [(set_attr "may_trap" "no")
20765 (set_attr "latency" "2")
20766 (set_attr "length" "4")
20767 (set_attr "slot" "core")
20768 (set_attr "slots" "core")
20769 (set_attr "stall" "load")])
20772 (define_insn "cgen_intrinsic_lb16"
20773 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20775 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20776 (match_operand:SI 2 "general_operand" "r")
20777 (mem:SI (scratch:SI))
20779 "CGEN_ENABLE_INSN_P (845)"
20781 [(set_attr "may_trap" "no")
20782 (set_attr "latency" "2")
20783 (set_attr "length" "4")
20784 (set_attr "slot" "core")
20785 (set_attr "slots" "core")
20786 (set_attr "stall" "load")])
20789 (define_insn "cgen_intrinsic_sw16"
20790 [(set (mem:SI (scratch:SI))
20792 (match_operand:SI 0 "general_operand" "r")
20793 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20794 (match_operand:SI 2 "general_operand" "r")
20796 "CGEN_ENABLE_INSN_P (846)"
20798 [(set_attr "may_trap" "no")
20799 (set_attr "latency" "0")
20800 (set_attr "length" "4")
20801 (set_attr "slot" "core")
20802 (set_attr "slots" "core")
20803 (set_attr "stall" "store")])
20806 (define_insn "cgen_intrinsic_sh16"
20807 [(set (mem:SI (scratch:SI))
20809 (match_operand:SI 0 "general_operand" "r")
20810 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20811 (match_operand:SI 2 "general_operand" "r")
20813 "CGEN_ENABLE_INSN_P (847)"
20815 [(set_attr "may_trap" "no")
20816 (set_attr "latency" "0")
20817 (set_attr "length" "4")
20818 (set_attr "slot" "core")
20819 (set_attr "slots" "core")
20820 (set_attr "stall" "store")])
20823 (define_insn "cgen_intrinsic_sb16"
20824 [(set (mem:SI (scratch:SI))
20826 (match_operand:SI 0 "general_operand" "r")
20827 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
20828 (match_operand:SI 2 "general_operand" "r")
20830 "CGEN_ENABLE_INSN_P (848)"
20832 [(set_attr "may_trap" "no")
20833 (set_attr "latency" "0")
20834 (set_attr "length" "4")
20835 (set_attr "slot" "core")
20836 (set_attr "slots" "core")
20837 (set_attr "stall" "store")])
20840 (define_insn "cgen_intrinsic_lhu_tp"
20841 [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20843 (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
20845 (mem:SI (scratch:SI))
20847 "CGEN_ENABLE_INSN_P (849)"
20849 [(set_attr "may_trap" "no")
20850 (set_attr "latency" "2")
20851 (set_attr "length" "2")
20852 (set_attr "slot" "core")
20853 (set_attr "slots" "core")
20854 (set_attr "stall" "load")])
20857 (define_insn "cgen_intrinsic_lbu_tp"
20858 [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20860 (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
20862 (mem:SI (scratch:SI))
20864 "CGEN_ENABLE_INSN_P (850)"
20866 [(set_attr "may_trap" "no")
20867 (set_attr "latency" "2")
20868 (set_attr "length" "2")
20869 (set_attr "slot" "core")
20870 (set_attr "slots" "core")
20871 (set_attr "stall" "load")])
20874 (define_insn "cgen_intrinsic_lw_tp"
20875 [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20877 (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20879 (mem:SI (scratch:SI))
20881 "CGEN_ENABLE_INSN_P (851)"
20883 [(set_attr "may_trap" "no")
20884 (set_attr "latency" "2")
20885 (set_attr "length" "2")
20886 (set_attr "slot" "core")
20887 (set_attr "slots" "core")
20888 (set_attr "stall" "load")])
20891 (define_insn "cgen_intrinsic_lh_tp"
20892 [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20894 (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
20896 (mem:SI (scratch:SI))
20898 "CGEN_ENABLE_INSN_P (852)"
20900 [(set_attr "may_trap" "no")
20901 (set_attr "latency" "2")
20902 (set_attr "length" "2")
20903 (set_attr "slot" "core")
20904 (set_attr "slots" "core")
20905 (set_attr "stall" "load")])
20908 (define_insn "cgen_intrinsic_lb_tp"
20909 [(set (match_operand:SI 0 "nonimmediate_operand" "=t")
20911 (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
20913 (mem:SI (scratch:SI))
20915 "CGEN_ENABLE_INSN_P (853)"
20917 [(set_attr "may_trap" "no")
20918 (set_attr "latency" "2")
20919 (set_attr "length" "2")
20920 (set_attr "slot" "core")
20921 (set_attr "slots" "core")
20922 (set_attr "stall" "load")])
20925 (define_insn "cgen_intrinsic_sw_tp"
20926 [(set (mem:SI (scratch:SI))
20928 (match_operand:SI 0 "general_operand" "t")
20929 (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20932 "CGEN_ENABLE_INSN_P (854)"
20934 [(set_attr "may_trap" "no")
20935 (set_attr "latency" "0")
20936 (set_attr "length" "2")
20937 (set_attr "slot" "core")
20938 (set_attr "slots" "core")
20939 (set_attr "stall" "store")])
20942 (define_insn "cgen_intrinsic_sh_tp"
20943 [(set (mem:SI (scratch:SI))
20945 (match_operand:SI 0 "general_operand" "t")
20946 (match_operand:SI 1 "cgen_h_uint_6a2_immediate" "")
20949 "CGEN_ENABLE_INSN_P (855)"
20951 [(set_attr "may_trap" "no")
20952 (set_attr "latency" "0")
20953 (set_attr "length" "2")
20954 (set_attr "slot" "core")
20955 (set_attr "slots" "core")
20956 (set_attr "stall" "store")])
20959 (define_insn "cgen_intrinsic_sb_tp"
20960 [(set (mem:SI (scratch:SI))
20962 (match_operand:SI 0 "general_operand" "t")
20963 (match_operand:SI 1 "cgen_h_uint_7a1_immediate" "")
20966 "CGEN_ENABLE_INSN_P (856)"
20968 [(set_attr "may_trap" "no")
20969 (set_attr "latency" "0")
20970 (set_attr "length" "2")
20971 (set_attr "slot" "core")
20972 (set_attr "slots" "core")
20973 (set_attr "stall" "store")])
20976 (define_insn "cgen_intrinsic_lw_sp"
20977 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
20979 (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
20981 (mem:SI (scratch:SI))
20983 "CGEN_ENABLE_INSN_P (857)"
20985 [(set_attr "may_trap" "no")
20986 (set_attr "latency" "2")
20987 (set_attr "length" "2")
20988 (set_attr "slot" "core")
20989 (set_attr "slots" "core")
20990 (set_attr "stall" "load")])
20993 (define_insn "cgen_intrinsic_sw_sp"
20994 [(set (mem:SI (scratch:SI))
20996 (match_operand:SI 0 "general_operand" "r")
20997 (match_operand:SI 1 "cgen_h_uint_5a4_immediate" "")
21000 "CGEN_ENABLE_INSN_P (858)"
21002 [(set_attr "may_trap" "no")
21003 (set_attr "latency" "0")
21004 (set_attr "length" "2")
21005 (set_attr "slot" "core")
21006 (set_attr "slots" "core")
21007 (set_attr "stall" "store")])
21010 (define_insn "cgen_intrinsic_lhu"
21011 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21013 (match_operand:SI 1 "general_operand" "r")
21014 (mem:SI (scratch:SI))
21016 "CGEN_ENABLE_INSN_P (859)"
21018 [(set_attr "may_trap" "no")
21019 (set_attr "latency" "2")
21020 (set_attr "length" "2")
21021 (set_attr "slot" "core")
21022 (set_attr "slots" "core")
21023 (set_attr "stall" "load")])
21026 (define_insn "cgen_intrinsic_lbu"
21027 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21029 (match_operand:SI 1 "general_operand" "r")
21030 (mem:SI (scratch:SI))
21032 "CGEN_ENABLE_INSN_P (860)"
21034 [(set_attr "may_trap" "no")
21035 (set_attr "latency" "2")
21036 (set_attr "length" "2")
21037 (set_attr "slot" "core")
21038 (set_attr "slots" "core")
21039 (set_attr "stall" "load")])
21042 (define_insn "cgen_intrinsic_lw"
21043 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21045 (match_operand:SI 1 "general_operand" "r")
21046 (mem:SI (scratch:SI))
21048 "CGEN_ENABLE_INSN_P (861)"
21050 [(set_attr "may_trap" "no")
21051 (set_attr "latency" "2")
21052 (set_attr "length" "2")
21053 (set_attr "slot" "core")
21054 (set_attr "slots" "core")
21055 (set_attr "stall" "load")])
21058 (define_insn "cgen_intrinsic_lh"
21059 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21061 (match_operand:SI 1 "general_operand" "r")
21062 (mem:SI (scratch:SI))
21064 "CGEN_ENABLE_INSN_P (862)"
21066 [(set_attr "may_trap" "no")
21067 (set_attr "latency" "2")
21068 (set_attr "length" "2")
21069 (set_attr "slot" "core")
21070 (set_attr "slots" "core")
21071 (set_attr "stall" "load")])
21074 (define_insn "cgen_intrinsic_lb"
21075 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21077 (match_operand:SI 1 "general_operand" "r")
21078 (mem:SI (scratch:SI))
21080 "CGEN_ENABLE_INSN_P (863)"
21082 [(set_attr "may_trap" "no")
21083 (set_attr "latency" "2")
21084 (set_attr "length" "2")
21085 (set_attr "slot" "core")
21086 (set_attr "slots" "core")
21087 (set_attr "stall" "load")])
21090 (define_insn "cgen_intrinsic_sw"
21091 [(set (mem:SI (scratch:SI))
21093 (match_operand:SI 0 "general_operand" "r")
21094 (match_operand:SI 1 "general_operand" "r")
21096 "CGEN_ENABLE_INSN_P (864)"
21098 [(set_attr "may_trap" "no")
21099 (set_attr "latency" "0")
21100 (set_attr "length" "2")
21101 (set_attr "slot" "core")
21102 (set_attr "slots" "core")
21103 (set_attr "stall" "store")])
21106 (define_insn "cgen_intrinsic_sh"
21107 [(set (mem:SI (scratch:SI))
21109 (match_operand:SI 0 "general_operand" "r")
21110 (match_operand:SI 1 "general_operand" "r")
21112 "CGEN_ENABLE_INSN_P (865)"
21114 [(set_attr "may_trap" "no")
21115 (set_attr "latency" "0")
21116 (set_attr "length" "2")
21117 (set_attr "slot" "core")
21118 (set_attr "slots" "core")
21119 (set_attr "stall" "store")])
21122 (define_insn "cgen_intrinsic_sb"
21123 [(set (mem:SI (scratch:SI))
21125 (match_operand:SI 0 "general_operand" "r")
21126 (match_operand:SI 1 "general_operand" "r")
21128 "CGEN_ENABLE_INSN_P (866)"
21130 [(set_attr "may_trap" "no")
21131 (set_attr "latency" "0")
21132 (set_attr "length" "2")
21133 (set_attr "slot" "core")
21134 (set_attr "slots" "core")
21135 (set_attr "stall" "store")])
21138 (define_insn "cgen_intrinsic_dsp1"
21139 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21140 (unspec_volatile:SI [
21141 (match_operand:SI 1 "general_operand" "0")
21142 (match_operand:SI 2 "cgen_h_uint_20a1_immediate" "")
21144 "CGEN_ENABLE_INSN_P (867)"
21146 [(set_attr "may_trap" "no")
21147 (set_attr "latency" "0")
21148 (set_attr "length" "4")
21149 (set_attr "slot" "core")
21150 (set_attr "slots" "core")
21151 (set_attr "stall" "none")])
21154 (define_insn "cgen_intrinsic_dsp0"
21155 [(unspec_volatile [
21156 (match_operand:SI 0 "cgen_h_uint_24a1_immediate" "")
21158 "CGEN_ENABLE_INSN_P (868)"
21160 [(set_attr "may_trap" "no")
21161 (set_attr "latency" "0")
21162 (set_attr "length" "4")
21163 (set_attr "slot" "core")
21164 (set_attr "slots" "core")
21165 (set_attr "stall" "none")])
21168 (define_insn "cgen_intrinsic_dsp"
21169 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21170 (unspec_volatile:SI [
21171 (match_operand:SI 1 "general_operand" "0")
21172 (match_operand:SI 2 "general_operand" "r")
21173 (match_operand:SI 3 "cgen_h_uint_16a1_immediate" "")
21175 "CGEN_ENABLE_INSN_P (869)"
21177 [(set_attr "may_trap" "no")
21178 (set_attr "latency" "0")
21179 (set_attr "length" "4")
21180 (set_attr "slot" "core")
21181 (set_attr "slots" "core")
21182 (set_attr "stall" "none")])
21185 (define_insn "cgen_intrinsic_uci"
21186 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21187 (unspec_volatile:SI [
21188 (match_operand:SI 1 "general_operand" "0")
21189 (match_operand:SI 2 "general_operand" "r")
21190 (match_operand:SI 3 "cgen_h_uint_16a1_immediate" "")
21192 "CGEN_ENABLE_INSN_P (870)"
21194 [(set_attr "may_trap" "no")
21195 (set_attr "latency" "0")
21196 (set_attr "length" "4")
21197 (set_attr "slot" "core")
21198 (set_attr "slots" "core")
21199 (set_attr "stall" "none")])
21202 (define_insn "cgen_intrinsic_lhucpm1"
21203 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21205 (match_operand:SI 2 "general_operand" "1")
21206 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21209 (mem:SI (scratch:SI))
21211 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21217 (mem:SI (scratch:SI))
21219 "CGEN_ENABLE_INSN_P (871)"
21220 "lhucpm1\\t%0,(%2+),%3"
21221 [(set_attr "may_trap" "no")
21222 (set_attr "latency" "0")
21223 (set_attr "length" "4")
21224 (set_attr "slot" "core")
21225 (set_attr "slots" "core")
21226 (set_attr "stall" "none")])
21229 (define_insn "cgen_intrinsic_lbucpm1"
21230 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21232 (match_operand:SI 2 "general_operand" "1")
21233 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21236 (mem:SI (scratch:SI))
21238 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21244 (mem:SI (scratch:SI))
21246 "CGEN_ENABLE_INSN_P (872)"
21247 "lbucpm1\\t%0,(%2+),%3"
21248 [(set_attr "may_trap" "no")
21249 (set_attr "latency" "0")
21250 (set_attr "length" "4")
21251 (set_attr "slot" "core")
21252 (set_attr "slots" "core")
21253 (set_attr "stall" "none")])
21256 (define_insn "cgen_intrinsic_lhucpm0"
21257 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21259 (match_operand:SI 2 "general_operand" "1")
21260 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21263 (mem:SI (scratch:SI))
21265 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21271 (mem:SI (scratch:SI))
21273 "CGEN_ENABLE_INSN_P (873)"
21274 "lhucpm0\\t%0,(%2+),%3"
21275 [(set_attr "may_trap" "no")
21276 (set_attr "latency" "0")
21277 (set_attr "length" "4")
21278 (set_attr "slot" "core")
21279 (set_attr "slots" "core")
21280 (set_attr "stall" "none")])
21283 (define_insn "cgen_intrinsic_lbucpm0"
21284 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21286 (match_operand:SI 2 "general_operand" "1")
21287 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21290 (mem:SI (scratch:SI))
21292 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21298 (mem:SI (scratch:SI))
21300 "CGEN_ENABLE_INSN_P (874)"
21301 "lbucpm0\\t%0,(%2+),%3"
21302 [(set_attr "may_trap" "no")
21303 (set_attr "latency" "0")
21304 (set_attr "length" "4")
21305 (set_attr "slot" "core")
21306 (set_attr "slots" "core")
21307 (set_attr "stall" "none")])
21310 (define_insn "cgen_intrinsic_lhucpa"
21311 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21313 (match_operand:SI 2 "general_operand" "1")
21314 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21315 (mem:SI (scratch:SI))
21317 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21321 (mem:SI (scratch:SI))
21323 "CGEN_ENABLE_INSN_P (875)"
21324 "lhucpa\\t%0,(%2+),%3"
21325 [(set_attr "may_trap" "no")
21326 (set_attr "latency" "0")
21327 (set_attr "length" "4")
21328 (set_attr "slot" "core")
21329 (set_attr "slots" "core")
21330 (set_attr "stall" "load")])
21333 (define_insn "cgen_intrinsic_lbucpa"
21334 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21336 (match_operand:SI 2 "general_operand" "1")
21337 (match_operand:SI 3 "cgen_h_sint_10a1_immediate" "")
21338 (mem:SI (scratch:SI))
21340 (set (match_operand:SI 1 "nonimmediate_operand" "=r")
21344 (mem:SI (scratch:SI))
21346 "CGEN_ENABLE_INSN_P (876)"
21347 "lbucpa\\t%0,(%2+),%3"
21348 [(set_attr "may_trap" "no")
21349 (set_attr "latency" "0")
21350 (set_attr "length" "4")
21351 (set_attr "slot" "core")
21352 (set_attr "slots" "core")
21353 (set_attr "stall" "load")])
21356 (define_insn "cgen_intrinsic_lhucp"
21357 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21359 (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21360 (match_operand:SI 2 "general_operand" "r")
21361 (mem:SI (scratch:SI))
21363 "CGEN_ENABLE_INSN_P (877)"
21364 "lhucp\\t%0,%1(%2)"
21365 [(set_attr "may_trap" "no")
21366 (set_attr "latency" "0")
21367 (set_attr "length" "4")
21368 (set_attr "slot" "core")
21369 (set_attr "slots" "core")
21370 (set_attr "stall" "store")])
21373 (define_insn "cgen_intrinsic_lhcp"
21374 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21376 (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21377 (match_operand:SI 2 "general_operand" "r")
21378 (mem:SI (scratch:SI))
21380 "CGEN_ENABLE_INSN_P (878)"
21382 [(set_attr "may_trap" "no")
21383 (set_attr "latency" "0")
21384 (set_attr "length" "4")
21385 (set_attr "slot" "core")
21386 (set_attr "slots" "core")
21387 (set_attr "stall" "store")])
21390 (define_insn "cgen_intrinsic_shcp"
21391 [(set (mem:SI (scratch:SI))
21393 (match_operand:SI 0 "general_operand" "em")
21394 (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21395 (match_operand:SI 2 "general_operand" "r")
21397 "CGEN_ENABLE_INSN_P (879)"
21399 [(set_attr "may_trap" "no")
21400 (set_attr "latency" "0")
21401 (set_attr "length" "4")
21402 (set_attr "slot" "core")
21403 (set_attr "slots" "core")
21404 (set_attr "stall" "store")])
21407 (define_insn "cgen_intrinsic_lbucp"
21408 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21410 (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21411 (match_operand:SI 2 "general_operand" "r")
21412 (mem:SI (scratch:SI))
21414 "CGEN_ENABLE_INSN_P (880)"
21415 "lbucp\\t%0,%1(%2)"
21416 [(set_attr "may_trap" "no")
21417 (set_attr "latency" "0")
21418 (set_attr "length" "4")
21419 (set_attr "slot" "core")
21420 (set_attr "slots" "core")
21421 (set_attr "stall" "store")])
21424 (define_insn "cgen_intrinsic_lbcp"
21425 [(set (match_operand:SI 0 "nonimmediate_operand" "=em")
21427 (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21428 (match_operand:SI 2 "general_operand" "r")
21429 (mem:SI (scratch:SI))
21431 "CGEN_ENABLE_INSN_P (881)"
21433 [(set_attr "may_trap" "no")
21434 (set_attr "latency" "0")
21435 (set_attr "length" "4")
21436 (set_attr "slot" "core")
21437 (set_attr "slots" "core")
21438 (set_attr "stall" "store")])
21441 (define_insn "cgen_intrinsic_sbcp"
21442 [(set (mem:SI (scratch:SI))
21444 (match_operand:SI 0 "general_operand" "em")
21445 (match_operand:SI 1 "cgen_h_sint_12a1_immediate" "")
21446 (match_operand:SI 2 "general_operand" "r")
21448 "CGEN_ENABLE_INSN_P (882)"
21450 [(set_attr "may_trap" "no")
21451 (set_attr "latency" "0")
21452 (set_attr "length" "4")
21453 (set_attr "slot" "core")
21454 (set_attr "slots" "core")
21455 (set_attr "stall" "store")])
21458 (define_insn "cgen_intrinsic_casw3"
21459 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21460 (unspec_volatile:SI [
21461 (match_operand:SI 1 "general_operand" "0")
21462 (match_operand:SI 2 "general_operand" "r")
21463 (match_operand:SI 3 "general_operand" "r")
21465 "CGEN_ENABLE_INSN_P (883)"
21466 "casw3\\t%1,%2,(%3)"
21467 [(set_attr "may_trap" "no")
21468 (set_attr "latency" "0")
21469 (set_attr "length" "4")
21470 (set_attr "slot" "core")
21471 (set_attr "slots" "core")
21472 (set_attr "stall" "none")])
21475 (define_insn "cgen_intrinsic_cash3"
21476 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21477 (unspec_volatile:SI [
21478 (match_operand:SI 1 "general_operand" "0")
21479 (match_operand:SI 2 "general_operand" "r")
21480 (match_operand:SI 3 "general_operand" "r")
21482 "CGEN_ENABLE_INSN_P (884)"
21483 "cash3\\t%1,%2,(%3)"
21484 [(set_attr "may_trap" "no")
21485 (set_attr "latency" "0")
21486 (set_attr "length" "4")
21487 (set_attr "slot" "core")
21488 (set_attr "slots" "core")
21489 (set_attr "stall" "none")])
21492 (define_insn "cgen_intrinsic_casb3"
21493 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21494 (unspec_volatile:SI [
21495 (match_operand:SI 1 "general_operand" "0")
21496 (match_operand:SI 2 "general_operand" "r")
21497 (match_operand:SI 3 "general_operand" "r")
21499 "CGEN_ENABLE_INSN_P (885)"
21500 "casb3\\t%1,%2,(%3)"
21501 [(set_attr "may_trap" "no")
21502 (set_attr "latency" "0")
21503 (set_attr "length" "4")
21504 (set_attr "slot" "core")
21505 (set_attr "slots" "core")
21506 (set_attr "stall" "none")])
21509 (define_insn "cgen_intrinsic_prefd"
21510 [(unspec_volatile [
21511 (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
21512 (match_operand:SI 1 "cgen_h_sint_16a1_immediate" "")
21513 (match_operand:SI 2 "general_operand" "r")
21515 "CGEN_ENABLE_INSN_P (886)"
21517 [(set_attr "may_trap" "no")
21518 (set_attr "latency" "0")
21519 (set_attr "length" "4")
21520 (set_attr "slot" "core")
21521 (set_attr "slots" "core")
21522 (set_attr "stall" "none")])
21525 (define_insn "cgen_intrinsic_pref"
21526 [(unspec_volatile [
21527 (match_operand:SI 0 "cgen_h_uint_4a1_immediate" "")
21528 (match_operand:SI 1 "general_operand" "r")
21530 "CGEN_ENABLE_INSN_P (887)"
21532 [(set_attr "may_trap" "no")
21533 (set_attr "latency" "0")
21534 (set_attr "length" "2")
21535 (set_attr "slot" "core")
21536 (set_attr "slots" "core")
21537 (set_attr "stall" "none")])
21540 (define_insn "cgen_intrinsic_ldcb_r"
21541 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
21542 (unspec_volatile:SI [
21543 (match_operand:SI 1 "general_operand" "r")
21545 "CGEN_ENABLE_INSN_P (888)"
21547 [(set_attr "may_trap" "no")
21548 (set_attr "latency" "3")
21549 (set_attr "length" "2")
21550 (set_attr "slot" "core")
21551 (set_attr "slots" "core")
21552 (set_attr "stall" "none")])
21555 (define_insn "cgen_intrinsic_stcb_r"
21556 [(unspec_volatile [
21557 (match_operand:SI 0 "general_operand" "r")
21558 (match_operand:SI 1 "general_operand" "r")
21560 "CGEN_ENABLE_INSN_P (889)"
21562 [(set_attr "may_trap" "no")
21563 (set_attr "latency" "0")
21564 (set_attr "length" "2")
21565 (set_attr "slot" "core")
21566 (set_attr "slots" "core")
21567 (set_attr "stall" "none")])