1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
23 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Maximum size we are allowed to grow the stack in a single operation.
49 If we want more, we must do it in increments of at most this size.
50 If this value is 0, we don't check at all. */
51 const char * mcore_stack_increment_string = 0;
52 int mcore_stack_increment = STACK_UNITS_MAXSTEP;
54 /* For dumping information about frame sizes. */
55 char * mcore_current_function_name = 0;
56 long mcore_current_compilation_timestamp = 0;
58 /* Global variables for machine-dependent things. */
60 /* Saved operands from the last compare to use when we generate an scc
65 /* Provides the class number of the smallest class containing
67 const int regno_reg_class[FIRST_PSEUDO_REGISTER] =
69 GENERAL_REGS, ONLYR1_REGS, LRW_REGS, LRW_REGS,
70 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
71 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
72 LRW_REGS, LRW_REGS, LRW_REGS, GENERAL_REGS,
73 GENERAL_REGS, C_REGS, NO_REGS, NO_REGS,
76 /* Provide reg_class from a letter such as appears in the machine
78 const enum reg_class reg_class_from_letter[] =
80 /* a */ LRW_REGS, /* b */ ONLYR1_REGS, /* c */ C_REGS, /* d */ NO_REGS,
81 /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
82 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ NO_REGS,
83 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
84 /* q */ NO_REGS, /* r */ GENERAL_REGS, /* s */ NO_REGS, /* t */ NO_REGS,
85 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ ALL_REGS,
86 /* y */ NO_REGS, /* z */ NO_REGS
91 int arg_size; /* stdarg spills (bytes) */
92 int reg_size; /* non-volatile reg saves (bytes) */
93 int reg_mask; /* non-volatile reg saves */
94 int local_size; /* locals */
95 int outbound_size; /* arg overflow on calls out */
99 /* Describe the steps we'll use to grow it. */
100 #define MAX_STACK_GROWS 4 /* gives us some spare space */
101 int growth[MAX_STACK_GROWS];
119 static void output_stack_adjust PARAMS ((int, int));
120 static int calc_live_regs PARAMS ((int *));
121 static int const_ok_for_mcore PARAMS ((int));
122 static int try_constant_tricks PARAMS ((long, int *, int *));
123 static const char * output_inline_const PARAMS ((enum machine_mode, rtx *));
124 static void block_move_sequence PARAMS ((rtx, rtx, rtx, rtx, int, int, int));
125 static void layout_mcore_frame PARAMS ((struct mcore_frame *));
126 static cond_type is_cond_candidate PARAMS ((rtx));
127 static rtx emit_new_cond_insn PARAMS ((rtx, int));
128 static rtx conditionalize_block PARAMS ((rtx));
129 static void conditionalize_optimization PARAMS ((rtx));
130 static rtx handle_structs_in_regs PARAMS ((enum machine_mode, tree, int));
131 static void mcore_mark_dllexport PARAMS ((tree));
132 static void mcore_mark_dllimport PARAMS ((tree));
133 static int mcore_dllexport_p PARAMS ((tree));
134 static int mcore_dllimport_p PARAMS ((tree));
135 const struct attribute_spec mcore_attribute_table[];
136 static tree mcore_handle_naked_attribute PARAMS ((tree *, tree, tree, int, bool *));
137 #ifdef OBJECT_FORMAT_ELF
138 static void mcore_asm_named_section PARAMS ((const char *,
141 static void mcore_unique_section PARAMS ((tree, int));
142 static void mcore_encode_section_info PARAMS ((tree, int));
143 static const char *mcore_strip_name_encoding PARAMS ((const char *));
145 /* Initialize the GCC target structure. */
146 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
147 #undef TARGET_MERGE_DECL_ATTRIBUTES
148 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
151 #ifdef OBJECT_FORMAT_ELF
152 #undef TARGET_ASM_UNALIGNED_HI_OP
153 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
154 #undef TARGET_ASM_UNALIGNED_SI_OP
155 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
158 #undef TARGET_ATTRIBUTE_TABLE
159 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
160 #undef TARGET_ASM_UNIQUE_SECTION
161 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
162 #undef TARGET_ENCODE_SECTION_INFO
163 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
164 #undef TARGET_STRIP_NAME_ENCODING
165 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
167 struct gcc_target targetm = TARGET_INITIALIZER;
169 /* Adjust the stack and return the number of bytes taken to do it. */
171 output_stack_adjust (direction, size)
175 /* If extending stack a lot, we do it incrementally. */
176 if (direction < 0 && size > mcore_stack_increment && mcore_stack_increment > 0)
178 rtx tmp = gen_rtx (REG, SImode, 1);
180 emit_insn (gen_movsi (tmp, GEN_INT (mcore_stack_increment)));
183 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
184 memref = gen_rtx (MEM, SImode, stack_pointer_rtx);
185 MEM_VOLATILE_P (memref) = 1;
186 emit_insn (gen_movsi (memref, stack_pointer_rtx));
187 size -= mcore_stack_increment;
189 while (size > mcore_stack_increment);
191 /* SIZE is now the residual for the last adjustment,
192 which doesn't require a probe. */
198 rtx val = GEN_INT (size);
202 rtx nval = gen_rtx (REG, SImode, 1);
203 emit_insn (gen_movsi (nval, val));
208 insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
210 insn = gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
216 /* Work out the registers which need to be saved,
217 both as a mask and a count. */
220 calc_live_regs (count)
224 int live_regs_mask = 0;
228 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
230 if (regs_ever_live[reg] && !call_used_regs[reg])
233 live_regs_mask |= (1 << reg);
237 return live_regs_mask;
240 /* Print the operand address in x to the stream. */
243 mcore_print_operand_address (stream, x)
247 switch (GET_CODE (x))
250 fprintf (stream, "(%s)", reg_names[REGNO (x)]);
255 rtx base = XEXP (x, 0);
256 rtx index = XEXP (x, 1);
258 if (GET_CODE (base) != REG)
260 /* Ensure that BASE is a register (one of them must be). */
266 switch (GET_CODE (index))
269 fprintf (stream, "(%s,%d)", reg_names[REGNO(base)],
283 output_addr_const (stream, x);
288 /* Print operand x (an rtx) in assembler syntax to file stream
289 according to modifier code.
291 'R' print the next register or memory location along, ie the lsw in
293 'O' print a constant without the #
294 'M' print a constant as its negative
295 'P' print log2 of a power of two
296 'Q' print log2 of an inverse of a power of two
297 'U' print register for ldm/stm instruction
298 'X' print byte number for xtrbN instruction. */
301 mcore_print_operand (stream, x, code)
310 fprintf (asm_out_file, "32");
312 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) + 1));
315 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x)));
318 fprintf (asm_out_file, "%d", exact_log2 (~INTVAL (x)));
321 fprintf (asm_out_file, "%d", INTVAL (x));
324 fprintf (asm_out_file, "%d", - INTVAL (x));
327 /* Next location along in memory or register. */
328 switch (GET_CODE (x))
331 fputs (reg_names[REGNO (x) + 1], (stream));
334 mcore_print_operand_address
335 (stream, XEXP (adjust_address (x, SImode, 4), 0));
342 fprintf (asm_out_file, "%s-%s", reg_names[REGNO (x)],
343 reg_names[REGNO (x) + 3]);
346 fprintf (asm_out_file, "0x%x", INTVAL (x));
349 fprintf (asm_out_file, "%d", 3 - INTVAL (x) / 8);
353 switch (GET_CODE (x))
356 fputs (reg_names[REGNO (x)], (stream));
359 output_address (XEXP (x, 0));
362 output_addr_const (stream, x);
369 /* What does a constant cost ? */
372 mcore_const_costs (exp, code)
377 int val = INTVAL (exp);
379 /* Easy constants. */
380 if ( CONST_OK_FOR_I (val)
381 || CONST_OK_FOR_M (val)
382 || CONST_OK_FOR_N (val)
383 || (code == PLUS && CONST_OK_FOR_L (val)))
386 && ( CONST_OK_FOR_M (~val)
387 || CONST_OK_FOR_N (~val)))
389 else if (code == PLUS
390 && ( CONST_OK_FOR_I (-val)
391 || CONST_OK_FOR_M (-val)
392 || CONST_OK_FOR_N (-val)))
398 /* What does an and instruction cost - we do this b/c immediates may
399 have been relaxed. We want to ensure that cse will cse relaxed immeds
400 out. Otherwise we'll get bad code (multiple reloads of the same const). */
408 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
411 val = INTVAL (XEXP (x, 1));
413 /* Do it directly. */
414 if (CONST_OK_FOR_K (val) || CONST_OK_FOR_M (~val))
416 /* Takes one instruction to load. */
417 else if (const_ok_for_mcore (val))
419 /* Takes two instructions to load. */
420 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
423 /* Takes a lrw to load. */
427 /* What does an or cost - see and_cost(). */
435 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
438 val = INTVAL (XEXP (x, 1));
440 /* Do it directly with bclri. */
441 if (CONST_OK_FOR_M (val))
443 /* Takes one instruction to load. */
444 else if (const_ok_for_mcore (val))
446 /* Takes two instructions to load. */
447 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
450 /* Takes a lrw to load. */
454 /* Check to see if a comparison against a constant can be made more efficient
455 by incrementing/decrementing the constant to get one that is more efficient
459 mcore_modify_comparison (code)
462 rtx op1 = arch_compare_op1;
464 if (GET_CODE (op1) == CONST_INT)
466 int val = INTVAL (op1);
471 if (CONST_OK_FOR_J (val + 1))
473 arch_compare_op1 = GEN_INT (val + 1);
486 /* Prepare the operands for a comparison. */
489 mcore_gen_compare_reg (code)
492 rtx op0 = arch_compare_op0;
493 rtx op1 = arch_compare_op1;
494 rtx cc_reg = gen_rtx (REG, CCmode, CC_REG);
496 if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
497 op1 = force_reg (SImode, op1);
499 /* cmpnei: 0-31 (K immediate)
500 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
503 case EQ: /* Use inverted condition, cmpne. */
507 case NE: /* Use normal condition, cmpne. */
508 if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
509 op1 = force_reg (SImode, op1);
512 case LE: /* Use inverted condition, reversed cmplt. */
516 case GT: /* Use normal condition, reversed cmplt. */
517 if (GET_CODE (op1) == CONST_INT)
518 op1 = force_reg (SImode, op1);
521 case GE: /* Use inverted condition, cmplt. */
525 case LT: /* Use normal condition, cmplt. */
526 if (GET_CODE (op1) == CONST_INT &&
527 /* covered by btsti x,31 */
529 ! CONST_OK_FOR_J (INTVAL (op1)))
530 op1 = force_reg (SImode, op1);
533 case GTU: /* Use inverted condition, cmple. */
534 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0)
536 /* Unsigned > 0 is the same as != 0, but we need
537 to invert the condition, so we want to set
538 code = EQ. This cannot be done however, as the
539 mcore does not support such a test. Instead we
540 cope with this case in the "bgtu" pattern itself
541 so we should never reach this point. */
549 case LEU: /* Use normal condition, reversed cmphs. */
550 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
551 op1 = force_reg (SImode, op1);
554 case LTU: /* Use inverted condition, cmphs. */
558 case GEU: /* Use normal condition, cmphs. */
559 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
560 op1 = force_reg (SImode, op1);
567 emit_insn (gen_rtx (SET, VOIDmode, cc_reg, gen_rtx (code, CCmode, op0, op1)));
574 mcore_symbolic_address_p (x)
577 switch (GET_CODE (x))
584 return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
585 || GET_CODE (XEXP (x, 0)) == LABEL_REF)
586 && GET_CODE (XEXP (x, 1)) == CONST_INT);
593 mcore_call_address_operand (x, mode)
595 enum machine_mode mode;
597 return register_operand (x, mode) || CONSTANT_P (x);
600 /* Functions to output assembly code for a function call. */
603 mcore_output_call (operands, index)
607 static char buffer[20];
608 rtx addr = operands [index];
614 if (mcore_current_function_name == 0)
617 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name,
621 sprintf (buffer, "jsr\t%%%d", index);
627 if (mcore_current_function_name == 0)
630 if (GET_CODE (addr) != SYMBOL_REF)
633 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, XSTR (addr, 0), 0);
636 sprintf (buffer, "jbsr\t%%%d", index);
642 /* Can we load a constant with a single instruction ? */
645 const_ok_for_mcore (value)
648 if (value >= 0 && value <= 127)
651 /* Try exact power of two. */
652 if ((value & (value - 1)) == 0)
655 /* Try exact power of two - 1. */
656 if ((value & (value + 1)) == 0)
662 /* Can we load a constant inline with up to 2 instructions ? */
665 mcore_const_ok_for_inline (value)
670 return try_constant_tricks (value, & x, & y) > 0;
673 /* Are we loading the constant using a not ? */
676 mcore_const_trick_uses_not (value)
681 return try_constant_tricks (value, & x, & y) == 2;
684 /* Try tricks to load a constant inline and return the trick number if
685 success (0 is non-inlinable).
688 1: single instruction (do the usual thing)
689 2: single insn followed by a 'not'
690 3: single insn followed by a subi
691 4: single insn followed by an addi
692 5: single insn followed by rsubi
693 6: single insn followed by bseti
694 7: single insn followed by bclri
695 8: single insn followed by rotli
696 9: single insn followed by lsli
697 10: single insn followed by ixh
698 11: single insn followed by ixw. */
701 try_constant_tricks (value, x, y)
707 unsigned bit, shf, rot;
709 if (const_ok_for_mcore (value))
710 return 1; /* Do the usual thing. */
714 if (const_ok_for_mcore (~value))
720 for (i = 1; i <= 32; i++)
722 if (const_ok_for_mcore (value - i))
730 if (const_ok_for_mcore (value + i))
741 for (i = 0; i <= 31; i++)
743 if (const_ok_for_mcore (i - value))
751 if (const_ok_for_mcore (value & ~bit))
759 if (const_ok_for_mcore (value | bit))
773 for (i = 1; i < 31; i++)
777 /* MCore has rotate left. */
781 rot |= c; /* Simulate rotate. */
783 if (const_ok_for_mcore (rot))
792 shf = 0; /* Can't use logical shift, low order bit is one. */
796 if (shf != 0 && const_ok_for_mcore (shf))
805 if ((value % 3) == 0 && const_ok_for_mcore (value / 3))
812 if ((value % 5) == 0 && const_ok_for_mcore (value / 5))
824 /* Check whether reg is dead at first. This is done by searching ahead
825 for either the next use (i.e., reg is live), a death note, or a set of
826 reg. Don't just use dead_or_set_p() since reload does not always mark
827 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
828 can ignore subregs by extracting the actual register. BRC */
831 mcore_is_dead (first, reg)
837 /* For mcore, subregs can't live independently of their parent regs. */
838 if (GET_CODE (reg) == SUBREG)
839 reg = SUBREG_REG (reg);
841 /* Dies immediately. */
842 if (dead_or_set_p (first, reg))
845 /* Look for conclusive evidence of live/death, otherwise we have
846 to assume that it is live. */
847 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
849 if (GET_CODE (insn) == JUMP_INSN)
850 return 0; /* We lose track, assume it is alive. */
852 else if (GET_CODE(insn) == CALL_INSN)
854 /* Call's might use it for target or register parms. */
855 if (reg_referenced_p (reg, PATTERN (insn))
856 || find_reg_fusage (insn, USE, reg))
858 else if (dead_or_set_p (insn, reg))
861 else if (GET_CODE (insn) == INSN)
863 if (reg_referenced_p (reg, PATTERN (insn)))
865 else if (dead_or_set_p (insn, reg))
870 /* No conclusive evidence either way, we can not take the chance
871 that control flow hid the use from us -- "I'm not dead yet". */
876 /* Count the number of ones in mask. */
879 mcore_num_ones (mask)
882 /* A trick to count set bits recently posted on comp.compilers. */
883 mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555);
884 mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333);
885 mask = ((mask >> 4) + mask) & 0x0f0f0f0f;
886 mask = ((mask >> 8) + mask);
888 return (mask + (mask >> 16)) & 0xff;
891 /* Count the number of zeros in mask. */
894 mcore_num_zeros (mask)
897 return 32 - mcore_num_ones (mask);
900 /* Determine byte being masked. */
903 mcore_byte_offset (mask)
906 if (mask == 0x00ffffffL)
908 else if (mask == 0xff00ffffL)
910 else if (mask == 0xffff00ffL)
912 else if (mask == 0xffffff00L)
918 /* Determine halfword being masked. */
921 mcore_halfword_offset (mask)
924 if (mask == 0x0000ffffL)
926 else if (mask == 0xffff0000L)
932 /* Output a series of bseti's corresponding to mask. */
935 mcore_output_bseti (dst, mask)
942 out_operands[0] = dst;
944 for (bit = 0; bit < 32; bit++)
946 if ((mask & 0x1) == 0x1)
948 out_operands[1] = GEN_INT (bit);
950 output_asm_insn ("bseti\t%0,%1", out_operands);
958 /* Output a series of bclri's corresponding to mask. */
961 mcore_output_bclri (dst, mask)
968 out_operands[0] = dst;
970 for (bit = 0; bit < 32; bit++)
972 if ((mask & 0x1) == 0x0)
974 out_operands[1] = GEN_INT (bit);
976 output_asm_insn ("bclri\t%0,%1", out_operands);
985 /* Output a conditional move of two constants that are +/- 1 within each
986 other. See the "movtK" patterns in mcore.md. I'm not sure this is
987 really worth the effort. */
990 mcore_output_cmov (operands, cmp_t, test)
999 out_operands[0] = operands[0];
1001 /* Check to see which constant is loadable. */
1002 if (const_ok_for_mcore (INTVAL (operands[1])))
1004 out_operands[1] = operands[1];
1005 out_operands[2] = operands[2];
1007 else if (const_ok_for_mcore (INTVAL (operands[2])))
1009 out_operands[1] = operands[2];
1010 out_operands[2] = operands[1];
1012 /* Complement test since constants are swapped. */
1013 cmp_t = (cmp_t == 0);
1015 load_value = INTVAL (out_operands[1]);
1016 adjust_value = INTVAL (out_operands[2]);
1018 /* First output the test if folded into the pattern. */
1021 output_asm_insn (test, operands);
1023 /* Load the constant - for now, only support constants that can be
1024 generated with a single instruction. maybe add general inlinable
1025 constants later (this will increase the # of patterns since the
1026 instruction sequence has a different length attribute). */
1027 if (load_value >= 0 && load_value <= 127)
1028 output_asm_insn ("movi\t%0,%1", out_operands);
1029 else if ((load_value & (load_value - 1)) == 0)
1030 output_asm_insn ("bgeni\t%0,%P1", out_operands);
1031 else if ((load_value & (load_value + 1)) == 0)
1032 output_asm_insn ("bmaski\t%0,%N1", out_operands);
1034 /* Output the constant adjustment. */
1035 if (load_value > adjust_value)
1038 output_asm_insn ("decf\t%0", out_operands);
1040 output_asm_insn ("dect\t%0", out_operands);
1045 output_asm_insn ("incf\t%0", out_operands);
1047 output_asm_insn ("inct\t%0", out_operands);
1053 /* Outputs the peephole for moving a constant that gets not'ed followed
1054 by an and (i.e. combine the not and the and into andn). BRC */
1057 mcore_output_andn (insn, operands)
1058 rtx insn ATTRIBUTE_UNUSED;
1062 rtx out_operands[3];
1063 const char * load_op;
1066 if (try_constant_tricks (INTVAL (operands[1]), &x, &y) != 2)
1069 out_operands[0] = operands[0];
1070 out_operands[1] = GEN_INT(x);
1071 out_operands[2] = operands[2];
1073 if (x >= 0 && x <= 127)
1074 load_op = "movi\t%0,%1";
1076 /* Try exact power of two. */
1077 else if ((x & (x - 1)) == 0)
1078 load_op = "bgeni\t%0,%P1";
1080 /* Try exact power of two - 1. */
1081 else if ((x & (x + 1)) == 0)
1082 load_op = "bmaski\t%0,%N1";
1085 load_op = "BADMOVI\t%0,%1";
1087 sprintf (buf, "%s\n\tandn\t%%2,%%0", load_op);
1088 output_asm_insn (buf, out_operands);
1093 /* Output an inline constant. */
1096 output_inline_const (mode, operands)
1097 enum machine_mode mode;
1102 rtx out_operands[3];
1105 const char *dst_fmt;
1108 value = INTVAL (operands[1]);
1110 if ((trick_no = try_constant_tricks (value, &x, &y)) == 0)
1112 /* lrw's are handled separately: Large inlinable constants
1113 never get turned into lrw's. Our caller uses try_constant_tricks
1114 to back off to an lrw rather than calling this routine. */
1121 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1122 out_operands[0] = operands[0];
1123 out_operands[1] = GEN_INT (x);
1126 out_operands[2] = GEN_INT (y);
1128 /* Select dst format based on mode. */
1129 if (mode == DImode && (! TARGET_LITTLE_END))
1134 if (x >= 0 && x <= 127)
1135 sprintf (load_op, "movi\t%s,%%1", dst_fmt);
1137 /* Try exact power of two. */
1138 else if ((x & (x - 1)) == 0)
1139 sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt);
1141 /* Try exact power of two - 1. */
1142 else if ((x & (x + 1)) == 0)
1143 sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt);
1146 sprintf (load_op, "BADMOVI\t%s,%%1", dst_fmt);
1151 strcpy (buf, load_op);
1154 sprintf (buf, "%s\n\tnot\t%s\t// %d 0x%x", load_op, dst_fmt, value, value);
1157 sprintf (buf, "%s\n\taddi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1160 sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1163 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1164 sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1167 sprintf (buf, "%s\n\tbseti\t%s,%%P2\t// %d 0x%x", load_op, dst_fmt, value, value);
1170 sprintf (buf, "%s\n\tbclri\t%s,%%Q2\t// %d 0x%x", load_op, dst_fmt, value, value);
1173 sprintf (buf, "%s\n\trotli\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1176 sprintf (buf, "%s\n\tlsli\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1179 sprintf (buf, "%s\n\tixh\t%s,%s\t// %d 0x%x", load_op, dst_fmt, dst_fmt, value, value);
1182 sprintf (buf, "%s\n\tixw\t%s,%s\t// %d 0x%x", load_op, dst_fmt, dst_fmt, value, value);
1188 output_asm_insn (buf, out_operands);
1193 /* Output a move of a word or less value. */
1196 mcore_output_move (insn, operands, mode)
1197 rtx insn ATTRIBUTE_UNUSED;
1199 enum machine_mode mode ATTRIBUTE_UNUSED;
1201 rtx dst = operands[0];
1202 rtx src = operands[1];
1204 if (GET_CODE (dst) == REG)
1206 if (GET_CODE (src) == REG)
1208 if (REGNO (src) == CC_REG) /* r-c */
1211 return "mov\t%0,%1"; /* r-r*/
1213 else if (GET_CODE (src) == MEM)
1215 if (GET_CODE (XEXP (src, 0)) == LABEL_REF)
1216 return "lrw\t%0,[%1]"; /* a-R */
1218 return "ldw\t%0,%1"; /* r-m */
1220 else if (GET_CODE (src) == CONST_INT)
1224 if (CONST_OK_FOR_I (INTVAL (src))) /* r-I */
1225 return "movi\t%0,%1";
1226 else if (CONST_OK_FOR_M (INTVAL (src))) /* r-M */
1227 return "bgeni\t%0,%P1\t// %1 %x1";
1228 else if (CONST_OK_FOR_N (INTVAL (src))) /* r-N */
1229 return "bmaski\t%0,%N1\t// %1 %x1";
1230 else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */
1231 return output_inline_const (SImode, operands); /* 1-2 insns */
1233 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1236 return "lrw\t%0, %1"; /* Into the literal pool. */
1238 else if (GET_CODE (dst) == MEM) /* m-r */
1239 return "stw\t%1,%0";
1244 /* Outputs a constant inline -- regardless of the cost.
1245 Useful for things where we've gotten into trouble and think we'd
1246 be doing an lrw into r15 (forbidden). This lets us get out of
1247 that pickle even after register allocation. */
1250 mcore_output_inline_const_forced (insn, operands, mode)
1251 rtx insn ATTRIBUTE_UNUSED;
1253 enum machine_mode mode ATTRIBUTE_UNUSED;
1255 unsigned long value = INTVAL (operands[1]);
1256 unsigned long ovalue = value;
1265 if (mcore_const_ok_for_inline (value))
1266 return output_inline_const (SImode, operands);
1268 for (i = 0; (unsigned) i < ARRAY_SIZE (part); i++)
1271 part[i].low = (value & 0x1F);
1272 value -= part[i].low;
1274 if (mcore_const_ok_for_inline (value))
1281 while ((value & 1) == 0)
1287 if (mcore_const_ok_for_inline (value))
1292 /* 5 bits per iteration, a maximum of 5 times == 25 bits and leaves
1293 7 bits left in the constant -- which we know we can cover with
1294 a movi. The final value can't be zero otherwise we'd have stopped
1295 in the previous iteration. */
1296 if (value == 0 || ! mcore_const_ok_for_inline (value))
1299 /* Now, work our way backwards emitting the constant. */
1301 /* Emit the value that remains -- it will be nonzero. */
1302 operands[1] = GEN_INT (value);
1303 output_asm_insn (output_inline_const (SImode, operands), operands);
1307 /* Shift anything we've already loaded. */
1310 operands[2] = GEN_INT (part[i].shift);
1311 output_asm_insn ("lsli %0,%2", operands);
1312 value <<= part[i].shift;
1315 /* Add anything we need into the low 5 bits. */
1316 if (part[i].low != 0)
1318 operands[2] = GEN_INT (part[i].low);
1319 output_asm_insn ("addi %0,%2", operands);
1320 value += part[i].low;
1326 if (value != ovalue) /* sanity */
1329 /* We've output all the instructions. */
1333 /* Return a sequence of instructions to perform DI or DF move.
1334 Since the MCORE cannot move a DI or DF in one instruction, we have
1335 to take care when we see overlapping source and dest registers. */
1338 mcore_output_movedouble (operands, mode)
1340 enum machine_mode mode ATTRIBUTE_UNUSED;
1342 rtx dst = operands[0];
1343 rtx src = operands[1];
1345 if (GET_CODE (dst) == REG)
1347 if (GET_CODE (src) == REG)
1349 int dstreg = REGNO (dst);
1350 int srcreg = REGNO (src);
1352 /* Ensure the second source not overwritten. */
1353 if (srcreg + 1 == dstreg)
1354 return "mov %R0,%R1\n\tmov %0,%1";
1356 return "mov %0,%1\n\tmov %R0,%R1";
1358 else if (GET_CODE (src) == MEM)
1360 rtx memexp = memexp = XEXP (src, 0);
1361 int dstreg = REGNO (dst);
1364 if (GET_CODE (memexp) == LABEL_REF)
1365 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1366 else if (GET_CODE (memexp) == REG)
1367 basereg = REGNO (memexp);
1368 else if (GET_CODE (memexp) == PLUS)
1370 if (GET_CODE (XEXP (memexp, 0)) == REG)
1371 basereg = REGNO (XEXP (memexp, 0));
1372 else if (GET_CODE (XEXP (memexp, 1)) == REG)
1373 basereg = REGNO (XEXP (memexp, 1));
1380 /* ??? length attribute is wrong here. */
1381 if (dstreg == basereg)
1383 /* Just load them in reverse order. */
1384 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1386 /* XXX: alternative: move basereg to basereg+1
1387 and then fall through. */
1390 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1392 else if (GET_CODE (src) == CONST_INT)
1394 if (TARGET_LITTLE_END)
1396 if (CONST_OK_FOR_I (INTVAL (src)))
1397 output_asm_insn ("movi %0,%1", operands);
1398 else if (CONST_OK_FOR_M (INTVAL (src)))
1399 output_asm_insn ("bgeni %0,%P1", operands);
1400 else if (INTVAL (src) == -1)
1401 output_asm_insn ("bmaski %0,32", operands);
1402 else if (CONST_OK_FOR_N (INTVAL (src)))
1403 output_asm_insn ("bmaski %0,%N1", operands);
1407 if (INTVAL (src) < 0)
1408 return "bmaski %R0,32";
1410 return "movi %R0,0";
1414 if (CONST_OK_FOR_I (INTVAL (src)))
1415 output_asm_insn ("movi %R0,%1", operands);
1416 else if (CONST_OK_FOR_M (INTVAL (src)))
1417 output_asm_insn ("bgeni %R0,%P1", operands);
1418 else if (INTVAL (src) == -1)
1419 output_asm_insn ("bmaski %R0,32", operands);
1420 else if (CONST_OK_FOR_N (INTVAL (src)))
1421 output_asm_insn ("bmaski %R0,%N1", operands);
1425 if (INTVAL (src) < 0)
1426 return "bmaski %0,32";
1434 else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
1435 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1440 /* Predicates used by the templates. */
1442 /* Nonzero if OP can be source of a simple move operation. */
1445 mcore_general_movsrc_operand (op, mode)
1447 enum machine_mode mode;
1449 /* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
1450 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
1453 return general_operand (op, mode);
1456 /* Nonzero if OP can be destination of a simple move operation. */
1459 mcore_general_movdst_operand (op, mode)
1461 enum machine_mode mode;
1463 if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
1466 return general_operand (op, mode);
1469 /* Nonzero if OP is a normal arithmetic register. */
1472 mcore_arith_reg_operand (op, mode)
1474 enum machine_mode mode;
1476 if (! register_operand (op, mode))
1479 if (GET_CODE (op) == SUBREG)
1480 op = SUBREG_REG (op);
1482 if (GET_CODE (op) == REG)
1483 return REGNO (op) != CC_REG;
1488 /* Nonzero if OP should be recognized during reload for an ixh/ixw
1489 operand. See the ixh/ixw patterns. */
1492 mcore_reload_operand (op, mode)
1494 enum machine_mode mode;
1496 if (mcore_arith_reg_operand (op, mode))
1499 if (! reload_in_progress)
1502 return GET_CODE (op) == MEM;
1505 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1508 mcore_arith_J_operand (op, mode)
1510 enum machine_mode mode;
1512 if (register_operand (op, mode))
1515 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
1521 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1524 mcore_arith_K_operand (op, mode)
1526 enum machine_mode mode;
1528 if (register_operand (op, mode))
1531 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
1537 /* Nonzero if OP is a valid source operand for a shift or rotate insn. */
1540 mcore_arith_K_operand_not_0 (op, mode)
1542 enum machine_mode mode;
1544 if (register_operand (op, mode))
1547 if ( GET_CODE (op) == CONST_INT
1548 && CONST_OK_FOR_K (INTVAL (op))
1549 && INTVAL (op) != 0)
1556 mcore_arith_K_S_operand (op, mode)
1558 enum machine_mode mode;
1560 if (register_operand (op, mode))
1563 if (GET_CODE (op) == CONST_INT)
1565 if (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_M (~INTVAL (op)))
1573 mcore_arith_S_operand (op)
1576 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op)))
1583 mcore_arith_M_operand (op, mode)
1585 enum machine_mode mode;
1587 if (register_operand (op, mode))
1590 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
1596 /* Nonzero if OP is a valid source operand for loading. */
1599 mcore_arith_imm_operand (op, mode)
1601 enum machine_mode mode;
1603 if (register_operand (op, mode))
1606 if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
1613 mcore_arith_any_imm_operand (op, mode)
1615 enum machine_mode mode;
1617 if (register_operand (op, mode))
1620 if (GET_CODE (op) == CONST_INT)
1626 /* Nonzero if OP is a valid source operand for a cmov with two consts +/- 1. */
1629 mcore_arith_O_operand (op, mode)
1631 enum machine_mode mode;
1633 if (register_operand (op, mode))
1636 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
1642 /* Nonzero if OP is a valid source operand for a btsti. */
1645 mcore_literal_K_operand (op, mode)
1647 enum machine_mode mode ATTRIBUTE_UNUSED;
1649 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
1655 /* Nonzero if OP is a valid source operand for an add/sub insn. */
1658 mcore_addsub_operand (op, mode)
1660 enum machine_mode mode;
1662 if (register_operand (op, mode))
1665 if (GET_CODE (op) == CONST_INT)
1669 /* The following is removed because it precludes large constants from being
1670 returned as valid source operands for and add/sub insn. While large
1671 constants may not directly be used in an add/sub, they may if first loaded
1672 into a register. Thus, this predicate should indicate that they are valid,
1673 and the constraint in mcore.md should control whether an additional load to
1674 register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */
1676 if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op)))
1684 /* Nonzero if OP is a valid source operand for a compare operation. */
1687 mcore_compare_operand (op, mode)
1689 enum machine_mode mode;
1691 if (register_operand (op, mode))
1694 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1700 /* Expand insert bit field. BRC */
1703 mcore_expand_insv (operands)
1706 int width = INTVAL (operands[1]);
1707 int posn = INTVAL (operands[2]);
1709 rtx mreg, sreg, ereg;
1711 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1712 for width==1 must be removed. Look around line 368. This is something
1713 we really want the md part to do. */
1714 if (width == 1 && GET_CODE (operands[3]) == CONST_INT)
1716 /* Do directly with bseti or bclri. */
1717 /* RBE: 2/97 consider only low bit of constant. */
1718 if ((INTVAL(operands[3])&1) == 0)
1720 mask = ~(1 << posn);
1721 emit_insn (gen_rtx (SET, SImode, operands[0],
1722 gen_rtx (AND, SImode, operands[0], GEN_INT (mask))));
1727 emit_insn (gen_rtx (SET, SImode, operands[0],
1728 gen_rtx (IOR, SImode, operands[0], GEN_INT (mask))));
1734 /* Look at some bit-field placements that we aren't interested
1735 in handling ourselves, unless specifically directed to do so. */
1736 if (! TARGET_W_FIELD)
1737 return 0; /* Generally, give up about now. */
1739 if (width == 8 && posn % 8 == 0)
1740 /* Byte sized and aligned; let caller break it up. */
1743 if (width == 16 && posn % 16 == 0)
1744 /* Short sized and aligned; let caller break it up. */
1747 /* The general case - we can do this a little bit better than what the
1748 machine independent part tries. This will get rid of all the subregs
1749 that mess up constant folding in combine when working with relaxed
1752 /* If setting the entire field, do it directly. */
1753 if (GET_CODE (operands[3]) == CONST_INT &&
1754 INTVAL (operands[3]) == ((1 << width) - 1))
1756 mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn));
1757 emit_insn (gen_rtx (SET, SImode, operands[0],
1758 gen_rtx (IOR, SImode, operands[0], mreg)));
1762 /* Generate the clear mask. */
1763 mreg = force_reg (SImode, GEN_INT (~(((1 << width) - 1) << posn)));
1765 /* Clear the field, to overlay it later with the source. */
1766 emit_insn (gen_rtx (SET, SImode, operands[0],
1767 gen_rtx (AND, SImode, operands[0], mreg)));
1769 /* If the source is constant 0, we've nothing to add back. */
1770 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
1773 /* XXX: Should we worry about more games with constant values?
1774 We've covered the high profile: set/clear single-bit and many-bit
1775 fields. How often do we see "arbitrary bit pattern" constants? */
1776 sreg = copy_to_mode_reg (SImode, operands[3]);
1778 /* Extract src as same width as dst (needed for signed values). We
1779 always have to do this since we widen everything to SImode.
1780 We don't have to mask if we're shifting this up against the
1781 MSB of the register (e.g., the shift will push out any hi-order
1783 if (width + posn != (int) GET_MODE_SIZE (SImode))
1785 ereg = force_reg (SImode, GEN_INT ((1 << width) - 1));
1786 emit_insn (gen_rtx (SET, SImode, sreg,
1787 gen_rtx (AND, SImode, sreg, ereg)));
1790 /* Insert source value in dest. */
1792 emit_insn (gen_rtx (SET, SImode, sreg,
1793 gen_rtx (ASHIFT, SImode, sreg, GEN_INT (posn))));
1795 emit_insn (gen_rtx (SET, SImode, operands[0],
1796 gen_rtx (IOR, SImode, operands[0], sreg)));
1801 /* Return 1 if OP is a load multiple operation. It is known to be a
1802 PARALLEL and the first section will be tested. */
1804 mcore_load_multiple_operation (op, mode)
1806 enum machine_mode mode ATTRIBUTE_UNUSED;
1808 int count = XVECLEN (op, 0);
1813 /* Perform a quick check so we don't blow up below. */
1815 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1816 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1817 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1820 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1821 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1823 for (i = 1; i < count; i++)
1825 rtx elt = XVECEXP (op, 0, i);
1827 if (GET_CODE (elt) != SET
1828 || GET_CODE (SET_DEST (elt)) != REG
1829 || GET_MODE (SET_DEST (elt)) != SImode
1830 || REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
1831 || GET_CODE (SET_SRC (elt)) != MEM
1832 || GET_MODE (SET_SRC (elt)) != SImode
1833 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1834 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1835 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1836 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1843 /* Similar, but tests for store multiple. */
1846 mcore_store_multiple_operation (op, mode)
1848 enum machine_mode mode ATTRIBUTE_UNUSED;
1850 int count = XVECLEN (op, 0);
1855 /* Perform a quick check so we don't blow up below. */
1857 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1858 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1859 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1862 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1863 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1865 for (i = 1; i < count; i++)
1867 rtx elt = XVECEXP (op, 0, i);
1869 if (GET_CODE (elt) != SET
1870 || GET_CODE (SET_SRC (elt)) != REG
1871 || GET_MODE (SET_SRC (elt)) != SImode
1872 || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
1873 || GET_CODE (SET_DEST (elt)) != MEM
1874 || GET_MODE (SET_DEST (elt)) != SImode
1875 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1876 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1877 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1878 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1885 /* ??? Block move stuff stolen from m88k. This code has not been
1886 verified for correctness. */
1888 /* Emit code to perform a block move. Choose the best method.
1890 OPERANDS[0] is the destination.
1891 OPERANDS[1] is the source.
1892 OPERANDS[2] is the size.
1893 OPERANDS[3] is the alignment safe to use. */
1895 /* Emit code to perform a block move with an offset sequence of ldw/st
1896 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1897 known constants. DEST and SRC are registers. OFFSET is the known
1898 starting point for the output pattern. */
1900 static const enum machine_mode mode_from_align[] =
1902 VOIDmode, QImode, HImode, VOIDmode, SImode,
1903 VOIDmode, VOIDmode, VOIDmode, DImode
1907 block_move_sequence (dest, dst_mem, src, src_mem, size, align, offset)
1915 enum machine_mode mode[2];
1920 int offset_ld = offset;
1921 int offset_st = offset;
1923 active[0] = active[1] = FALSE;
1925 /* Establish parameters for the first load and for the second load if
1926 it is known to be the same mode as the first. */
1927 amount[0] = amount[1] = align;
1929 mode[0] = mode_from_align[align];
1931 temp[0] = gen_reg_rtx (mode[0]);
1933 if (size >= 2 * align)
1936 temp[1] = gen_reg_rtx (mode[1]);
1948 /* Change modes as the sequence tails off. */
1949 if (size < amount[next])
1951 amount[next] = (size >= 4 ? 4 : (size >= 2 ? 2 : 1));
1952 mode[next] = mode_from_align[amount[next]];
1953 temp[next] = gen_reg_rtx (mode[next]);
1956 size -= amount[next];
1957 srcp = gen_rtx (MEM,
1959 MEM_IN_STRUCT_P (src_mem) ? mode[next] : BLKmode,
1963 gen_rtx (PLUS, Pmode, src,
1964 gen_rtx (CONST_INT, SImode, offset_ld)));
1966 RTX_UNCHANGING_P (srcp) = RTX_UNCHANGING_P (src_mem);
1967 MEM_VOLATILE_P (srcp) = MEM_VOLATILE_P (src_mem);
1968 MEM_IN_STRUCT_P (srcp) = 1;
1969 emit_insn (gen_rtx (SET, VOIDmode, temp[next], srcp));
1970 offset_ld += amount[next];
1971 active[next] = TRUE;
1976 active[phase] = FALSE;
1978 dstp = gen_rtx (MEM,
1980 MEM_IN_STRUCT_P (dst_mem) ? mode[phase] : BLKmode,
1984 gen_rtx (PLUS, Pmode, dest,
1985 gen_rtx (CONST_INT, SImode, offset_st)));
1987 RTX_UNCHANGING_P (dstp) = RTX_UNCHANGING_P (dst_mem);
1988 MEM_VOLATILE_P (dstp) = MEM_VOLATILE_P (dst_mem);
1989 MEM_IN_STRUCT_P (dstp) = 1;
1990 emit_insn (gen_rtx (SET, VOIDmode, dstp, temp[phase]));
1991 offset_st += amount[phase];
1994 while (active[next]);
1998 mcore_expand_block_move (dst_mem, src_mem, operands)
2003 int align = INTVAL (operands[3]);
2006 if (GET_CODE (operands[2]) == CONST_INT)
2008 bytes = INTVAL (operands[2]);
2015 /* RBE: bumped 1 and 2 byte align from 1 and 2 to 4 and 8 bytes before
2016 we give up and go to memcpy. */
2017 if ((align == 4 && (bytes <= 4*4
2018 || ((bytes & 01) == 0 && bytes <= 8*4)
2019 || ((bytes & 03) == 0 && bytes <= 16*4)))
2020 || (align == 2 && bytes <= 4*2)
2021 || (align == 1 && bytes <= 4*1))
2023 block_move_sequence (operands[0], dst_mem, operands[1], src_mem,
2029 /* If we get here, just use the library routine. */
2030 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0, VOIDmode, 3,
2031 operands[0], Pmode, operands[1], Pmode, operands[2],
2036 /* Code to generate prologue and epilogue sequences. */
2037 static int number_of_regs_before_varargs;
2039 /* Set by SETUP_INCOMING_VARARGS to indicate to prolog that this is
2040 for a varargs function. */
2041 static int current_function_anonymous_args;
2043 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
2044 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
2045 #define ADDI_REACH (32) /* Maximum addi operand. */
2048 layout_mcore_frame (infp)
2049 struct mcore_frame * infp;
2058 unsigned int growths;
2061 /* Might have to spill bytes to re-assemble a big argument that
2062 was passed partially in registers and partially on the stack. */
2063 nbytes = current_function_pretend_args_size;
2065 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
2066 if (current_function_anonymous_args)
2067 nbytes += (NPARM_REGS - number_of_regs_before_varargs) * UNITS_PER_WORD;
2069 infp->arg_size = nbytes;
2071 /* How much space to save non-volatile registers we stomp. */
2072 infp->reg_mask = calc_live_regs (& n);
2073 infp->reg_size = n * 4;
2075 /* And the rest of it... locals and space for overflowed outbounds. */
2076 infp->local_size = get_frame_size ();
2077 infp->outbound_size = current_function_outgoing_args_size;
2079 /* Make sure we have a whole number of words for the locals. */
2080 if (infp->local_size % STACK_BYTES)
2081 infp->local_size = (infp->local_size + STACK_BYTES - 1) & ~ (STACK_BYTES -1);
2083 /* Only thing we know we have to pad is the outbound space, since
2084 we've aligned our locals assuming that base of locals is aligned. */
2085 infp->pad_local = 0;
2087 infp->pad_outbound = 0;
2088 if (infp->outbound_size % STACK_BYTES)
2089 infp->pad_outbound = STACK_BYTES - (infp->outbound_size % STACK_BYTES);
2091 /* Now we see how we want to stage the prologue so that it does
2092 the most appropriate stack growth and register saves to either:
2094 (2) reduce instruction space, or
2095 (3) reduce stack space. */
2096 for (i = 0; i < ARRAY_SIZE (infp->growth); i++)
2097 infp->growth[i] = 0;
2099 regarg = infp->reg_size + infp->arg_size;
2100 localregarg = infp->local_size + regarg;
2101 localreg = infp->local_size + infp->reg_size;
2102 outbounds = infp->outbound_size + infp->pad_outbound;
2105 /* XXX: Consider one where we consider localregarg + outbound too! */
2107 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
2108 use stw's with offsets and buy the frame in one shot. */
2109 if (localregarg <= ADDI_REACH
2110 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
2112 /* Make sure we'll be aligned. */
2113 if (localregarg % STACK_BYTES)
2114 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
2116 step = localregarg + infp->pad_reg;
2117 infp->reg_offset = infp->local_size;
2119 if (outbounds + step <= ADDI_REACH && !frame_pointer_needed)
2122 infp->reg_offset += outbounds;
2126 infp->arg_offset = step - 4;
2127 infp->growth[growths++] = step;
2128 infp->reg_growth = growths;
2129 infp->local_growth = growths;
2131 /* If we haven't already folded it in. */
2133 infp->growth[growths++] = outbounds;
2138 /* Frame can't be done with a single subi, but can be done with 2
2139 insns. If the 'stm' is getting <= 2 registers, we use stw's and
2140 shift some of the stack purchase into the first subi, so both are
2141 single instructions. */
2142 if (localregarg <= STORE_REACH
2143 && (infp->local_size > ADDI_REACH)
2144 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
2148 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
2149 if (localregarg % STACK_BYTES)
2150 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
2152 all = localregarg + infp->pad_reg + infp->pad_local;
2153 step = ADDI_REACH; /* As much up front as we can. */
2157 /* XXX: Consider whether step will still be aligned; we believe so. */
2158 infp->arg_offset = step - 4;
2159 infp->growth[growths++] = step;
2160 infp->reg_growth = growths;
2161 infp->reg_offset = step - infp->pad_reg - infp->reg_size;
2164 /* Can we fold in any space required for outbounds? */
2165 if (outbounds + all <= ADDI_REACH && !frame_pointer_needed)
2171 /* Get the rest of the locals in place. */
2173 infp->growth[growths++] = step;
2174 infp->local_growth = growths;
2179 /* Finish off if we need to do so. */
2181 infp->growth[growths++] = outbounds;
2186 /* Registers + args is nicely aligned, so we'll buy that in one shot.
2187 Then we buy the rest of the frame in 1 or 2 steps depending on
2188 whether we need a frame pointer. */
2189 if ((regarg % STACK_BYTES) == 0)
2191 infp->growth[growths++] = regarg;
2192 infp->reg_growth = growths;
2193 infp->arg_offset = regarg - 4;
2194 infp->reg_offset = 0;
2196 if (infp->local_size % STACK_BYTES)
2197 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
2199 step = infp->local_size + infp->pad_local;
2201 if (!frame_pointer_needed)
2207 infp->growth[growths++] = step;
2208 infp->local_growth = growths;
2210 /* If there's any left to be done. */
2212 infp->growth[growths++] = outbounds;
2217 /* XXX: optimizations that we'll want to play with....
2218 -- regarg is not aligned, but it's a small number of registers;
2219 use some of localsize so that regarg is aligned and then
2220 save the registers. */
2222 /* Simple encoding; plods down the stack buying the pieces as it goes.
2223 -- does not optimize space consumption.
2224 -- does not attempt to optimize instruction counts.
2225 -- but it is safe for all alignments. */
2226 if (regarg % STACK_BYTES != 0)
2227 infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES);
2229 infp->growth[growths++] = infp->arg_size + infp->reg_size + infp->pad_reg;
2230 infp->reg_growth = growths;
2231 infp->arg_offset = infp->growth[0] - 4;
2232 infp->reg_offset = 0;
2234 if (frame_pointer_needed)
2236 if (infp->local_size % STACK_BYTES != 0)
2237 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
2239 infp->growth[growths++] = infp->local_size + infp->pad_local;
2240 infp->local_growth = growths;
2242 infp->growth[growths++] = outbounds;
2246 if ((infp->local_size + outbounds) % STACK_BYTES != 0)
2247 infp->pad_local = STACK_BYTES - ((infp->local_size + outbounds) % STACK_BYTES);
2249 infp->growth[growths++] = infp->local_size + infp->pad_local + outbounds;
2250 infp->local_growth = growths;
2253 /* Anything else that we've forgotten?, plus a few consistency checks. */
2255 assert (infp->reg_offset >= 0);
2256 assert (growths <= MAX_STACK_GROWS);
2258 for (i = 0; i < growths; i++)
2260 if (infp->growth[i] % STACK_BYTES)
2262 fprintf (stderr,"stack growth of %d is not %d aligned\n",
2263 infp->growth[i], STACK_BYTES);
2269 /* Define the offset between two registers, one to be eliminated, and
2270 the other its replacement, at the start of a routine. */
2273 mcore_initial_elimination_offset (from, to)
2279 struct mcore_frame fi;
2281 layout_mcore_frame (& fi);
2284 above_frame = fi.local_size + fi.pad_local + fi.reg_size + fi.pad_reg;
2286 below_frame = fi.outbound_size + fi.pad_outbound;
2288 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
2291 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2292 return above_frame + below_frame;
2294 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2302 /* Keep track of some information about varargs for the prolog. */
2305 mcore_setup_incoming_varargs (args_so_far, mode, type, ptr_pretend_size)
2306 CUMULATIVE_ARGS args_so_far;
2307 enum machine_mode mode;
2309 int * ptr_pretend_size ATTRIBUTE_UNUSED;
2311 current_function_anonymous_args = 1;
2313 /* We need to know how many argument registers are used before
2314 the varargs start, so that we can push the remaining argument
2315 registers during the prologue. */
2316 number_of_regs_before_varargs = args_so_far + mcore_num_arg_regs (mode, type);
2318 /* There is a bug somwehere in the arg handling code.
2319 Until I can find it this workaround always pushes the
2320 last named argument onto the stack. */
2321 number_of_regs_before_varargs = args_so_far;
2323 /* The last named argument may be split between argument registers
2324 and the stack. Allow for this here. */
2325 if (number_of_regs_before_varargs > NPARM_REGS)
2326 number_of_regs_before_varargs = NPARM_REGS;
2330 mcore_expand_prolog ()
2332 struct mcore_frame fi;
2333 int space_allocated = 0;
2336 /* Find out what we're doing. */
2337 layout_mcore_frame (&fi);
2339 space_allocated = fi.arg_size + fi.reg_size + fi.local_size +
2340 fi.outbound_size + fi.pad_outbound + fi.pad_local + fi.pad_reg;
2344 /* Emit a symbol for this routine's frame size. */
2347 x = DECL_RTL (current_function_decl);
2349 if (GET_CODE (x) != MEM)
2354 if (GET_CODE (x) != SYMBOL_REF)
2357 if (mcore_current_function_name)
2358 free (mcore_current_function_name);
2360 mcore_current_function_name = xstrdup (XSTR (x, 0));
2362 ASM_OUTPUT_CG_NODE (asm_out_file, mcore_current_function_name, space_allocated);
2364 if (current_function_calls_alloca)
2365 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, "alloca", 1);
2368 We're looking at how the 8byte alignment affects stack layout
2369 and where we had to pad things. This emits information we can
2370 extract which tells us about frame sizes and the like. */
2371 fprintf (asm_out_file,
2372 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
2373 mcore_current_function_name,
2374 fi.arg_size, fi.reg_size, fi.reg_mask,
2375 fi.local_size, fi.outbound_size,
2376 frame_pointer_needed);
2379 if (mcore_naked_function_p ())
2382 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2383 output_stack_adjust (-1, fi.growth[growth++]); /* grows it */
2385 /* If we have a parameter passed partially in regs and partially in memory,
2386 the registers will have been stored to memory already in function.c. So
2387 we only need to do something here for varargs functions. */
2388 if (fi.arg_size != 0 && current_function_pretend_args_size == 0)
2391 int rn = FIRST_PARM_REG + NPARM_REGS - 1;
2392 int remaining = fi.arg_size;
2394 for (offset = fi.arg_offset; remaining >= 4; offset -= 4, rn--, remaining -= 4)
2396 emit_insn (gen_movsi
2397 (gen_rtx (MEM, SImode,
2398 plus_constant (stack_pointer_rtx, offset)),
2399 gen_rtx (REG, SImode, rn)));
2403 /* Do we need another stack adjustment before we do the register saves? */
2404 if (growth < fi.reg_growth)
2405 output_stack_adjust (-1, fi.growth[growth++]); /* grows it */
2407 if (fi.reg_size != 0)
2410 int offs = fi.reg_offset;
2412 for (i = 15; i >= 0; i--)
2414 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2418 while (fi.reg_mask & (1 << first_reg))
2422 emit_insn (gen_store_multiple (gen_rtx (MEM, SImode, stack_pointer_rtx),
2423 gen_rtx (REG, SImode, first_reg),
2424 GEN_INT (16 - first_reg)));
2426 i -= (15 - first_reg);
2427 offs += (16 - first_reg) * 4;
2429 else if (fi.reg_mask & (1 << i))
2431 emit_insn (gen_movsi
2432 (gen_rtx (MEM, SImode,
2433 plus_constant (stack_pointer_rtx, offs)),
2434 gen_rtx (REG, SImode, i)));
2440 /* Figure the locals + outbounds. */
2441 if (frame_pointer_needed)
2443 /* If we haven't already purchased to 'fp'. */
2444 if (growth < fi.local_growth)
2445 output_stack_adjust (-1, fi.growth[growth++]); /* grows it */
2447 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2449 /* ... and then go any remaining distance for outbounds, etc. */
2450 if (fi.growth[growth])
2451 output_stack_adjust (-1, fi.growth[growth++]);
2455 if (growth < fi.local_growth)
2456 output_stack_adjust (-1, fi.growth[growth++]); /* grows it */
2457 if (fi.growth[growth])
2458 output_stack_adjust (-1, fi.growth[growth++]);
2463 mcore_expand_epilog ()
2465 struct mcore_frame fi;
2468 int growth = MAX_STACK_GROWS - 1 ;
2471 /* Find out what we're doing. */
2472 layout_mcore_frame(&fi);
2474 if (mcore_naked_function_p ())
2477 /* If we had a frame pointer, restore the sp from that. */
2478 if (frame_pointer_needed)
2480 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
2481 growth = fi.local_growth - 1;
2485 /* XXX: while loop should accumulate and do a single sell. */
2486 while (growth >= fi.local_growth)
2488 if (fi.growth[growth] != 0)
2489 output_stack_adjust (1, fi.growth[growth]);
2494 /* Make sure we've shrunk stack back to the point where the registers
2495 were laid down. This is typically 0/1 iterations. Then pull the
2496 register save information back off the stack. */
2497 while (growth >= fi.reg_growth)
2498 output_stack_adjust ( 1, fi.growth[growth--]);
2500 offs = fi.reg_offset;
2502 for (i = 15; i >= 0; i--)
2504 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2508 /* Find the starting register. */
2511 while (fi.reg_mask & (1 << first_reg))
2516 emit_insn (gen_load_multiple (gen_rtx (REG, SImode, first_reg),
2517 gen_rtx (MEM, SImode, stack_pointer_rtx),
2518 GEN_INT (16 - first_reg)));
2520 i -= (15 - first_reg);
2521 offs += (16 - first_reg) * 4;
2523 else if (fi.reg_mask & (1 << i))
2525 emit_insn (gen_movsi
2526 (gen_rtx (REG, SImode, i),
2527 gen_rtx (MEM, SImode,
2528 plus_constant (stack_pointer_rtx, offs))));
2533 /* Give back anything else. */
2534 /* XXX: Should accumuate total and then give it back. */
2536 output_stack_adjust ( 1, fi.growth[growth--]);
2539 /* This code is borrowed from the SH port. */
2541 /* The MCORE cannot load a large constant into a register, constants have to
2542 come from a pc relative load. The reference of a pc relative load
2543 instruction must be less than 1k infront of the instruction. This
2544 means that we often have to dump a constant inside a function, and
2545 generate code to branch around it.
2547 It is important to minimize this, since the branches will slow things
2548 down and make things bigger.
2550 Worst case code looks like:
2566 We fix this by performing a scan before scheduling, which notices which
2567 instructions need to have their operands fetched from the constant table
2568 and builds the table.
2572 scan, find an instruction which needs a pcrel move. Look forward, find the
2573 last barrier which is within MAX_COUNT bytes of the requirement.
2574 If there isn't one, make one. Process all the instructions between
2575 the find and the barrier.
2577 In the above example, we can tell that L3 is within 1k of L1, so
2578 the first move can be shrunk from the 2 insn+constant sequence into
2579 just 1 insn, and the constant moved to L3 to make:
2589 Then the second move becomes the target for the shortening process. */
2593 rtx value; /* Value in table. */
2594 rtx label; /* Label of value. */
2597 /* The maximum number of constants that can fit into one pool, since
2598 the pc relative range is 0...1020 bytes and constants are at least 4
2599 bytes long. We subtact 4 from the range to allow for the case where
2600 we need to add a branch/align before the constant pool. */
2602 #define MAX_COUNT 1016
2603 #define MAX_POOL_SIZE (MAX_COUNT/4)
2604 static pool_node pool_vector[MAX_POOL_SIZE];
2605 static int pool_size;
2607 /* Dump out any constants accumulated in the final pass. These
2608 will only be labels. */
2611 mcore_output_jump_label_table ()
2617 fprintf (asm_out_file, "\t.align 2\n");
2619 for (i = 0; i < pool_size; i++)
2621 pool_node * p = pool_vector + i;
2623 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (p->label));
2625 output_asm_insn (".long %0", &p->value);
2634 /* Check whether insn is a candidate for a conditional. */
2637 is_cond_candidate (insn)
2640 /* The only things we conditionalize are those that can be directly
2641 changed into a conditional. Only bother with SImode items. If
2642 we wanted to be a little more aggressive, we could also do other
2643 modes such as DImode with reg-reg move or load 0. */
2644 if (GET_CODE (insn) == INSN)
2646 rtx pat = PATTERN (insn);
2649 if (GET_CODE (pat) != SET)
2652 dst = XEXP (pat, 0);
2654 if ((GET_CODE (dst) != REG &&
2655 GET_CODE (dst) != SUBREG) ||
2656 GET_MODE (dst) != SImode)
2659 src = XEXP (pat, 1);
2661 if ((GET_CODE (src) == REG ||
2662 (GET_CODE (src) == SUBREG &&
2663 GET_CODE (SUBREG_REG (src)) == REG)) &&
2664 GET_MODE (src) == SImode)
2665 return COND_MOV_INSN;
2666 else if (GET_CODE (src) == CONST_INT &&
2668 return COND_CLR_INSN;
2669 else if (GET_CODE (src) == PLUS &&
2670 (GET_CODE (XEXP (src, 0)) == REG ||
2671 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2672 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2673 GET_MODE (XEXP (src, 0)) == SImode &&
2674 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2675 INTVAL (XEXP (src, 1)) == 1)
2676 return COND_INC_INSN;
2677 else if (((GET_CODE (src) == MINUS &&
2678 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2679 INTVAL( XEXP (src, 1)) == 1) ||
2680 (GET_CODE (src) == PLUS &&
2681 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2682 INTVAL (XEXP (src, 1)) == -1)) &&
2683 (GET_CODE (XEXP (src, 0)) == REG ||
2684 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2685 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2686 GET_MODE (XEXP (src, 0)) == SImode)
2687 return COND_DEC_INSN;
2689 /* some insns that we don't bother with:
2690 (set (rx:DI) (ry:DI))
2691 (set (rx:DI) (const_int 0))
2695 else if (GET_CODE (insn) == JUMP_INSN &&
2696 GET_CODE (PATTERN (insn)) == SET &&
2697 GET_CODE (XEXP (PATTERN (insn), 1)) == LABEL_REF)
2698 return COND_BRANCH_INSN;
2703 /* Emit a conditional version of insn and replace the old insn with the
2704 new one. Return the new insn if emitted. */
2707 emit_new_cond_insn (insn, cond)
2715 if ((num = is_cond_candidate (insn)) == COND_NO)
2718 pat = PATTERN (insn);
2720 if (GET_CODE (insn) == INSN)
2722 dst = SET_DEST (pat);
2723 src = SET_SRC (pat);
2727 dst = JUMP_LABEL (insn);
2736 c_insn = gen_movt0 (dst, src, dst);
2738 c_insn = gen_movt0 (dst, dst, src);
2743 c_insn = gen_incscc (dst, dst);
2745 c_insn = gen_incscc_false (dst, dst);
2750 c_insn = gen_decscc (dst, dst);
2752 c_insn = gen_decscc_false (dst, dst);
2755 case COND_BRANCH_INSN:
2757 c_insn = gen_branch_true (dst);
2759 c_insn = gen_branch_false (dst);
2766 /* Only copy the notes if they exist. */
2767 if (rtx_length [GET_CODE (c_insn)] >= 7 && rtx_length [GET_CODE (insn)] >= 7)
2769 /* We really don't need to bother with the notes and links at this
2770 point, but go ahead and save the notes. This will help is_dead()
2771 when applying peepholes (links don't matter since they are not
2772 used any more beyond this point for the mcore). */
2773 REG_NOTES (c_insn) = REG_NOTES (insn);
2776 if (num == COND_BRANCH_INSN)
2778 /* For jumps, we need to be a little bit careful and emit the new jump
2779 before the old one and to update the use count for the target label.
2780 This way, the barrier following the old (uncond) jump will get
2781 deleted, but the label won't. */
2782 c_insn = emit_jump_insn_before (c_insn, insn);
2784 ++ LABEL_NUSES (dst);
2786 JUMP_LABEL (c_insn) = dst;
2789 c_insn = emit_insn_after (c_insn, insn);
2796 /* Attempt to change a basic block into a series of conditional insns. This
2797 works by taking the branch at the end of the 1st block and scanning for the
2798 end of the 2nd block. If all instructions in the 2nd block have cond.
2799 versions and the label at the start of block 3 is the same as the target
2800 from the branch at block 1, then conditionalize all insn in block 2 using
2801 the inverse condition of the branch at block 1. (Note I'm bending the
2802 definition of basic block here.)
2806 bt L2 <-- end of block 1 (delete)
2809 br L3 <-- end of block 2
2811 L2: ... <-- start of block 3 (NUSES==1)
2822 we can delete the L2 label if NUSES==1 and re-apply the optimization
2823 starting at the last instruction of block 2. This may allow an entire
2824 if-then-else statement to be conditionalized. BRC */
2826 conditionalize_block (first)
2831 rtx end_blk_1_br = 0;
2832 rtx end_blk_2_insn = 0;
2833 rtx start_blk_3_lab = 0;
2839 /* Check that the first insn is a candidate conditional jump. This is
2840 the one that we'll eliminate. If not, advance to the next insn to
2842 if (GET_CODE (first) != JUMP_INSN ||
2843 GET_CODE (PATTERN (first)) != SET ||
2844 GET_CODE (XEXP (PATTERN (first), 1)) != IF_THEN_ELSE)
2845 return NEXT_INSN (first);
2847 /* Extract some information we need. */
2848 end_blk_1_br = first;
2849 br_pat = PATTERN (end_blk_1_br);
2851 /* Complement the condition since we use the reverse cond. for the insns. */
2852 cond = (GET_CODE (XEXP (XEXP (br_pat, 1), 0)) == EQ);
2854 /* Determine what kind of branch we have. */
2855 if (GET_CODE (XEXP (XEXP (br_pat, 1), 1)) == LABEL_REF)
2857 /* A normal branch, so extract label out of first arm. */
2858 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 1), 0));
2862 /* An inverse branch, so extract the label out of the 2nd arm
2863 and complement the condition. */
2865 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 2), 0));
2868 /* Scan forward for the start of block 2: it must start with a
2869 label and that label must be the same as the branch target
2870 label from block 1. We don't care about whether block 2 actually
2871 ends with a branch or a label (an uncond. branch is
2872 conditionalizable). */
2873 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
2877 code = GET_CODE (insn);
2879 /* Look for the label at the start of block 3. */
2880 if (code == CODE_LABEL && CODE_LABEL_NUMBER (insn) == br_lab_num)
2883 /* Skip barriers, notes, and conditionalizable insns. If the
2884 insn is not conditionalizable or makes this optimization fail,
2885 just return the next insn so we can start over from that point. */
2886 if (code != BARRIER && code != NOTE && !is_cond_candidate (insn))
2887 return NEXT_INSN (insn);
2889 /* Remember the last real insn before the label (ie end of block 2). */
2890 if (code == JUMP_INSN || code == INSN)
2893 end_blk_2_insn = insn;
2900 /* It is possible for this optimization to slow performance if the blocks
2901 are long. This really depends upon whether the branch is likely taken
2902 or not. If the branch is taken, we slow performance in many cases. But,
2903 if the branch is not taken, we always help performance (for a single
2904 block, but for a double block (i.e. when the optimization is re-applied)
2905 this is not true since the 'right thing' depends on the overall length of
2906 the collapsed block). As a compromise, don't apply this optimization on
2907 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2908 the best threshold depends on the latencies of the instructions (i.e.,
2909 the branch penalty). */
2910 if (optimize > 1 && blk_size > 2)
2913 /* At this point, we've found the start of block 3 and we know that
2914 it is the destination of the branch from block 1. Also, all
2915 instructions in the block 2 are conditionalizable. So, apply the
2916 conditionalization and delete the branch. */
2917 start_blk_3_lab = insn;
2919 for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab;
2920 insn = NEXT_INSN (insn))
2924 if (INSN_DELETED_P (insn))
2927 /* Try to form a conditional variant of the instruction and emit it. */
2928 if ((newinsn = emit_new_cond_insn (insn, cond)))
2930 if (end_blk_2_insn == insn)
2931 end_blk_2_insn = newinsn;
2937 /* Note whether we will delete the label starting blk 3 when the jump
2938 gets deleted. If so, we want to re-apply this optimization at the
2939 last real instruction right before the label. */
2940 if (LABEL_NUSES (start_blk_3_lab) == 1)
2942 start_blk_3_lab = 0;
2945 /* ??? we probably should redistribute the death notes for this insn, esp.
2946 the death of cc, but it doesn't really matter this late in the game.
2947 The peepholes all use is_dead() which will find the correct death
2948 regardless of whether there is a note. */
2949 delete_insn (end_blk_1_br);
2951 if (! start_blk_3_lab)
2952 return end_blk_2_insn;
2954 /* Return the insn right after the label at the start of block 3. */
2955 return NEXT_INSN (start_blk_3_lab);
2958 /* Apply the conditionalization of blocks optimization. This is the
2959 outer loop that traverses through the insns scanning for a branch
2960 that signifies an opportunity to apply the optimization. Note that
2961 this optimization is applied late. If we could apply it earlier,
2962 say before cse 2, it may expose more optimization opportunities.
2963 but, the pay back probably isn't really worth the effort (we'd have
2964 to update all reg/flow/notes/links/etc to make it work - and stick it
2965 in before cse 2). */
2968 conditionalize_optimization (first)
2973 for (insn = first; insn; insn = conditionalize_block (insn))
2977 static int saved_warn_return_type = -1;
2978 static int saved_warn_return_type_count = 0;
2980 /* This function is called from toplev.c before reorg. */
2983 mcore_dependent_reorg (first)
2986 /* Reset this variable. */
2987 current_function_anonymous_args = 0;
2989 /* Restore the warn_return_type if it has been altered. */
2990 if (saved_warn_return_type != -1)
2992 /* Only restore the value if we have reached another function.
2993 The test of warn_return_type occurs in final_function () in
2994 c-decl.c a long time after the code for the function is generated,
2995 so we need a counter to tell us when we have finished parsing that
2996 function and can restore the flag. */
2997 if (--saved_warn_return_type_count == 0)
2999 warn_return_type = saved_warn_return_type;
3000 saved_warn_return_type = -1;
3007 /* Conditionalize blocks where we can. */
3008 conditionalize_optimization (first);
3010 /* Literal pool generation is now pushed off until the assembler. */
3014 /* Return the reg_class to use when reloading the rtx X into the class
3017 /* If the input is (PLUS REG CONSTANT) representing a stack slot address,
3018 then we want to restrict the class to LRW_REGS since that ensures that
3019 will be able to safely load the constant.
3021 If the input is a constant that should be loaded with mvir1, then use
3024 ??? We don't handle the case where we have (PLUS REG CONSTANT) and
3025 the constant should be loaded with mvir1, because that can lead to cases
3026 where an instruction needs two ONLYR1_REGS reloads. */
3028 mcore_reload_class (x, class)
3030 enum reg_class class;
3032 enum reg_class new_class;
3034 if (class == GENERAL_REGS && CONSTANT_P (x)
3035 && (GET_CODE (x) != CONST_INT
3036 || ( ! CONST_OK_FOR_I (INTVAL (x))
3037 && ! CONST_OK_FOR_M (INTVAL (x))
3038 && ! CONST_OK_FOR_N (INTVAL (x)))))
3039 new_class = LRW_REGS;
3046 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
3047 register. Note that the current version doesn't worry about whether
3048 they are the same mode or note (e.g., a QImode in r2 matches an HImode
3049 in r2 matches an SImode in r2. Might think in the future about whether
3050 we want to be able to say something about modes. */
3052 mcore_is_same_reg (x, y)
3056 /* Strip any and all of the subreg wrappers. */
3057 while (GET_CODE (x) == SUBREG)
3060 while (GET_CODE (y) == SUBREG)
3063 if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y))
3070 mcore_override_options ()
3072 if (mcore_stack_increment_string)
3074 mcore_stack_increment = atoi (mcore_stack_increment_string);
3076 if (mcore_stack_increment < 0
3077 || (mcore_stack_increment == 0
3078 && (mcore_stack_increment_string[0] != '0'
3079 || mcore_stack_increment_string[1] != 0)))
3080 error ("invalid option `-mstack-increment=%s'",
3081 mcore_stack_increment_string);
3084 /* Only the m340 supports little endian code. */
3085 if (TARGET_LITTLE_END && ! TARGET_M340)
3086 target_flags |= M340_BIT;
3090 mcore_must_pass_on_stack (mode, type)
3091 enum machine_mode mode ATTRIBUTE_UNUSED;
3097 /* If the argugment can have its address taken, it must
3098 be placed on the stack. */
3099 if (TREE_ADDRESSABLE (type))
3105 /* Compute the number of word sized registers needed to
3106 hold a function argument of mode MODE and type TYPE. */
3108 mcore_num_arg_regs (mode, type)
3109 enum machine_mode mode;
3114 if (MUST_PASS_IN_STACK (mode, type))
3117 if (type && mode == BLKmode)
3118 size = int_size_in_bytes (type);
3120 size = GET_MODE_SIZE (mode);
3122 return ROUND_ADVANCE (size);
3126 handle_structs_in_regs (mode, type, reg)
3127 enum machine_mode mode;
3133 /* The MCore ABI defines that a structure whoes size is not a whole multiple
3134 of bytes is passed packed into registers (or spilled onto the stack if
3135 not enough registers are available) with the last few bytes of the
3136 structure being packed, left-justified, into the last register/stack slot.
3137 GCC handles this correctly if the last word is in a stack slot, but we
3138 have to generate a special, PARALLEL RTX if the last word is in an
3139 argument register. */
3141 && TYPE_MODE (type) == BLKmode
3142 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
3143 && (size = int_size_in_bytes (type)) > UNITS_PER_WORD
3144 && (size % UNITS_PER_WORD != 0)
3145 && (reg + mcore_num_arg_regs (mode, type) <= (FIRST_PARM_REG + NPARM_REGS)))
3147 rtx arg_regs [NPARM_REGS];
3152 for (nregs = 0; size > 0; size -= UNITS_PER_WORD)
3155 gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, reg ++),
3156 GEN_INT (nregs * UNITS_PER_WORD));
3160 /* We assume here that NPARM_REGS == 6. The assert checks this. */
3161 assert (ARRAY_SIZE (arg_regs) == 6);
3162 rtvec = gen_rtvec (nregs, arg_regs[0], arg_regs[1], arg_regs[2],
3163 arg_regs[3], arg_regs[4], arg_regs[5]);
3165 result = gen_rtx_PARALLEL (mode, rtvec);
3169 return gen_rtx_REG (mode, reg);
3173 mcore_function_value (valtype, func)
3175 tree func ATTRIBUTE_UNUSED;
3177 enum machine_mode mode;
3180 mode = TYPE_MODE (valtype);
3182 PROMOTE_MODE (mode, unsigned_p, NULL);
3184 return handle_structs_in_regs (mode, valtype, FIRST_RET_REG);
3187 /* Define where to put the arguments to a function.
3188 Value is zero to push the argument on the stack,
3189 or a hard register in which to store the argument.
3191 MODE is the argument's machine mode.
3192 TYPE is the data type of the argument (as a tree).
3193 This is null for libcalls where that information may
3195 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3196 the preceding args and about the function being called.
3197 NAMED is nonzero if this argument is a named parameter
3198 (otherwise it is an extra parameter matching an ellipsis).
3200 On MCore the first args are normally in registers
3201 and the rest are pushed. Any arg that starts within the first
3202 NPARM_REGS words is at least partially passed in a register unless
3203 its data type forbids. */
3205 mcore_function_arg (cum, mode, type, named)
3206 CUMULATIVE_ARGS cum;
3207 enum machine_mode mode;
3216 if (MUST_PASS_IN_STACK (mode, type))
3219 arg_reg = ROUND_REG (cum, mode);
3221 if (arg_reg < NPARM_REGS)
3222 return handle_structs_in_regs (mode, type, FIRST_PARM_REG + arg_reg);
3227 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
3228 Returns the number of argument registers required to hold *part* of
3229 a parameter of machine mode MODE and type TYPE (which may be NULL if
3230 the type is not known). If the argument fits entirly in the argument
3231 registers, or entirely on the stack, then 0 is returned. CUM is the
3232 number of argument registers already used by earlier parameters to
3235 mcore_function_arg_partial_nregs (cum, mode, type, named)
3236 CUMULATIVE_ARGS cum;
3237 enum machine_mode mode;
3241 int reg = ROUND_REG (cum, mode);
3246 if (MUST_PASS_IN_STACK (mode, type))
3249 /* REG is not the *hardware* register number of the register that holds
3250 the argument, it is the *argument* register number. So for example,
3251 the first argument to a function goes in argument register 0, which
3252 translates (for the MCore) into hardware register 2. The second
3253 argument goes into argument register 1, which translates into hardware
3254 register 3, and so on. NPARM_REGS is the number of argument registers
3255 supported by the target, not the maximum hardware register number of
3257 if (reg >= NPARM_REGS)
3260 /* If the argument fits entirely in registers, return 0. */
3261 if (reg + mcore_num_arg_regs (mode, type) <= NPARM_REGS)
3264 /* The argument overflows the number of available argument registers.
3265 Compute how many argument registers have not yet been assigned to
3266 hold an argument. */
3267 reg = NPARM_REGS - reg;
3269 /* Return partially in registers and partially on the stack. */
3273 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
3275 mcore_dllexport_name_p (symbol)
3276 const char * symbol;
3278 return symbol[0] == '@' && symbol[1] == 'e' && symbol[2] == '.';
3281 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
3283 mcore_dllimport_name_p (symbol)
3284 const char * symbol;
3286 return symbol[0] == '@' && symbol[1] == 'i' && symbol[2] == '.';
3289 /* Mark a DECL as being dllexport'd. */
3291 mcore_mark_dllexport (decl)
3294 const char * oldname;
3299 rtlname = XEXP (DECL_RTL (decl), 0);
3301 if (GET_CODE (rtlname) == SYMBOL_REF)
3302 oldname = XSTR (rtlname, 0);
3303 else if ( GET_CODE (rtlname) == MEM
3304 && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
3305 oldname = XSTR (XEXP (rtlname, 0), 0);
3309 if (mcore_dllexport_name_p (oldname))
3310 return; /* Already done. */
3312 newname = alloca (strlen (oldname) + 4);
3313 sprintf (newname, "@e.%s", oldname);
3315 /* We pass newname through get_identifier to ensure it has a unique
3316 address. RTL processing can sometimes peek inside the symbol ref
3317 and compare the string's addresses to see if two symbols are
3319 /* ??? At least I think that's why we do this. */
3320 idp = get_identifier (newname);
3322 XEXP (DECL_RTL (decl), 0) =
3323 gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (idp));
3326 /* Mark a DECL as being dllimport'd. */
3328 mcore_mark_dllimport (decl)
3331 const char * oldname;
3337 rtlname = XEXP (DECL_RTL (decl), 0);
3339 if (GET_CODE (rtlname) == SYMBOL_REF)
3340 oldname = XSTR (rtlname, 0);
3341 else if ( GET_CODE (rtlname) == MEM
3342 && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
3343 oldname = XSTR (XEXP (rtlname, 0), 0);
3347 if (mcore_dllexport_name_p (oldname))
3348 abort (); /* This shouldn't happen. */
3349 else if (mcore_dllimport_name_p (oldname))
3350 return; /* Already done. */
3352 /* ??? One can well ask why we're making these checks here,
3353 and that would be a good question. */
3355 /* Imported variables can't be initialized. */
3356 if (TREE_CODE (decl) == VAR_DECL
3357 && !DECL_VIRTUAL_P (decl)
3358 && DECL_INITIAL (decl))
3360 error_with_decl (decl, "initialized variable `%s' is marked dllimport");
3364 /* `extern' needn't be specified with dllimport.
3365 Specify `extern' now and hope for the best. Sigh. */
3366 if (TREE_CODE (decl) == VAR_DECL
3367 /* ??? Is this test for vtables needed? */
3368 && !DECL_VIRTUAL_P (decl))
3370 DECL_EXTERNAL (decl) = 1;
3371 TREE_PUBLIC (decl) = 1;
3374 newname = alloca (strlen (oldname) + 11);
3375 sprintf (newname, "@i.__imp_%s", oldname);
3377 /* We pass newname through get_identifier to ensure it has a unique
3378 address. RTL processing can sometimes peek inside the symbol ref
3379 and compare the string's addresses to see if two symbols are
3381 /* ??? At least I think that's why we do this. */
3382 idp = get_identifier (newname);
3384 newrtl = gen_rtx (MEM, Pmode,
3385 gen_rtx (SYMBOL_REF, Pmode,
3386 IDENTIFIER_POINTER (idp)));
3387 XEXP (DECL_RTL (decl), 0) = newrtl;
3391 mcore_dllexport_p (decl)
3394 if ( TREE_CODE (decl) != VAR_DECL
3395 && TREE_CODE (decl) != FUNCTION_DECL)
3398 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)) != 0;
3402 mcore_dllimport_p (decl)
3405 if ( TREE_CODE (decl) != VAR_DECL
3406 && TREE_CODE (decl) != FUNCTION_DECL)
3409 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl)) != 0;
3412 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3413 install some info in the .drective (PE) or .exports (ELF) sections. */
3416 mcore_encode_section_info (decl, first)
3418 int first ATTRIBUTE_UNUSED;
3420 /* This bit is copied from arm.h. */
3422 && TREE_CONSTANT (decl)
3423 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST))
3425 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
3426 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
3427 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
3430 /* Mark the decl so we can tell from the rtl whether the object is
3431 dllexport'd or dllimport'd. */
3432 if (mcore_dllexport_p (decl))
3433 mcore_mark_dllexport (decl);
3434 else if (mcore_dllimport_p (decl))
3435 mcore_mark_dllimport (decl);
3437 /* It might be that DECL has already been marked as dllimport, but
3438 a subsequent definition nullified that. The attribute is gone
3439 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3440 else if ((TREE_CODE (decl) == FUNCTION_DECL
3441 || TREE_CODE (decl) == VAR_DECL)
3442 && DECL_RTL (decl) != NULL_RTX
3443 && GET_CODE (DECL_RTL (decl)) == MEM
3444 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM
3445 && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
3446 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
3448 const char * oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0);
3449 tree idp = get_identifier (oldname + 9);
3450 rtx newrtl = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (idp));
3452 XEXP (DECL_RTL (decl), 0) = newrtl;
3454 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3455 ??? We leave these alone for now. */
3459 /* Undo the effects of the above. */
3462 mcore_strip_name_encoding (str)
3465 return str + (str[0] == '@' ? 3 : 0);
3468 /* MCore specific attribute support.
3469 dllexport - for exporting a function/variable that will live in a dll
3470 dllimport - for importing a function/variable from a dll
3471 naked - do not create a function prologue/epilogue. */
3473 const struct attribute_spec mcore_attribute_table[] =
3475 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3476 { "dllexport", 0, 0, true, false, false, NULL },
3477 { "dllimport", 0, 0, true, false, false, NULL },
3478 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute },
3479 { NULL, 0, 0, false, false, false, NULL }
3482 /* Handle a "naked" attribute; arguments as in
3483 struct attribute_spec.handler. */
3485 mcore_handle_naked_attribute (node, name, args, flags, no_add_attrs)
3488 tree args ATTRIBUTE_UNUSED;
3489 int flags ATTRIBUTE_UNUSED;
3492 if (TREE_CODE (*node) == FUNCTION_DECL)
3494 /* PR14310 - don't complain about lack of return statement
3495 in naked functions. The solution here is a gross hack
3496 but this is the only way to solve the problem without
3497 adding a new feature to GCC. I did try submitting a patch
3498 that would add such a new feature, but it was (rightfully)
3499 rejected on the grounds that it was creeping featurism,
3500 so hence this code. */
3501 if (warn_return_type)
3503 saved_warn_return_type = warn_return_type;
3504 warn_return_type = 0;
3505 saved_warn_return_type_count = 2;
3507 else if (saved_warn_return_type_count)
3508 saved_warn_return_type_count = 2;
3512 warning ("`%s' attribute only applies to functions",
3513 IDENTIFIER_POINTER (name));
3514 *no_add_attrs = true;
3520 /* ??? It looks like this is PE specific? Oh well, this is what the
3521 old code did as well. */
3524 mcore_unique_section (decl, reloc)
3526 int reloc ATTRIBUTE_UNUSED;
3531 const char * prefix;
3533 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3535 /* Strip off any encoding in name. */
3536 name = (* targetm.strip_name_encoding) (name);
3538 /* The object is put in, for example, section .text$foo.
3539 The linker will then ultimately place them in .text
3540 (everything from the $ on is stripped). */
3541 if (TREE_CODE (decl) == FUNCTION_DECL)
3543 /* For compatibility with EPOC, we ignore the fact that the
3544 section might have relocs against it. */
3545 else if (decl_readonly_section (decl, 0))
3550 len = strlen (name) + strlen (prefix);
3551 string = alloca (len + 1);
3553 sprintf (string, "%s%s", prefix, name);
3555 DECL_SECTION_NAME (decl) = build_string (len, string);
3559 mcore_naked_function_p ()
3561 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE;
3564 #ifdef OBJECT_FORMAT_ELF
3566 mcore_asm_named_section (name, flags)
3568 unsigned int flags ATTRIBUTE_UNUSED;
3570 fprintf (asm_out_file, "\t.section %s\n", name);
3572 #endif /* OBJECT_FORMAT_ELF */