1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Maximum size we are allowed to grow the stack in a single operation.
50 If we want more, we must do it in increments of at most this size.
51 If this value is 0, we don't check at all. */
52 const char * mcore_stack_increment_string = 0;
53 int mcore_stack_increment = STACK_UNITS_MAXSTEP;
55 /* For dumping information about frame sizes. */
56 char * mcore_current_function_name = 0;
57 long mcore_current_compilation_timestamp = 0;
59 /* Global variables for machine-dependent things. */
61 /* Saved operands from the last compare to use when we generate an scc
66 /* Provides the class number of the smallest class containing
68 const int regno_reg_class[FIRST_PSEUDO_REGISTER] =
70 GENERAL_REGS, ONLYR1_REGS, LRW_REGS, LRW_REGS,
71 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
72 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
73 LRW_REGS, LRW_REGS, LRW_REGS, GENERAL_REGS,
74 GENERAL_REGS, C_REGS, NO_REGS, NO_REGS,
77 /* Provide reg_class from a letter such as appears in the machine
79 const enum reg_class reg_class_from_letter[] =
81 /* a */ LRW_REGS, /* b */ ONLYR1_REGS, /* c */ C_REGS, /* d */ NO_REGS,
82 /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
83 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ NO_REGS,
84 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
85 /* q */ NO_REGS, /* r */ GENERAL_REGS, /* s */ NO_REGS, /* t */ NO_REGS,
86 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ ALL_REGS,
87 /* y */ NO_REGS, /* z */ NO_REGS
92 int arg_size; /* Stdarg spills (bytes). */
93 int reg_size; /* Non-volatile reg saves (bytes). */
94 int reg_mask; /* Non-volatile reg saves. */
95 int local_size; /* Locals. */
96 int outbound_size; /* Arg overflow on calls out. */
100 /* Describe the steps we'll use to grow it. */
101 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
102 int growth[MAX_STACK_GROWS];
120 static void output_stack_adjust (int, int);
121 static int calc_live_regs (int *);
122 static int const_ok_for_mcore (int);
123 static int try_constant_tricks (long, int *, int *);
124 static const char * output_inline_const (enum machine_mode, rtx *);
125 static void block_move_sequence (rtx, rtx, rtx, rtx, int, int, int);
126 static void layout_mcore_frame (struct mcore_frame *);
127 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
128 static cond_type is_cond_candidate (rtx);
129 static rtx emit_new_cond_insn (rtx, int);
130 static rtx conditionalize_block (rtx);
131 static void conditionalize_optimization (void);
132 static void mcore_reorg (void);
133 static rtx handle_structs_in_regs (enum machine_mode, tree, int);
134 static void mcore_mark_dllexport (tree);
135 static void mcore_mark_dllimport (tree);
136 static int mcore_dllexport_p (tree);
137 static int mcore_dllimport_p (tree);
138 const struct attribute_spec mcore_attribute_table[];
139 static tree mcore_handle_naked_attribute (tree *, tree, tree, int, bool *);
140 #ifdef OBJECT_FORMAT_ELF
141 static void mcore_asm_named_section (const char *,
144 static void mcore_unique_section (tree, int);
145 static void mcore_encode_section_info (tree, rtx, int);
146 static const char *mcore_strip_name_encoding (const char *);
147 static int mcore_const_costs (rtx, RTX_CODE);
148 static int mcore_and_cost (rtx);
149 static int mcore_ior_cost (rtx);
150 static bool mcore_rtx_costs (rtx, int, int, int *);
151 static void mcore_external_libcall (rtx);
152 static bool mcore_return_in_memory (tree, tree);
155 /* Initialize the GCC target structure. */
156 #undef TARGET_ASM_EXTERNAL_LIBCALL
157 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
159 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
160 #undef TARGET_MERGE_DECL_ATTRIBUTES
161 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
164 #ifdef OBJECT_FORMAT_ELF
165 #undef TARGET_ASM_UNALIGNED_HI_OP
166 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
167 #undef TARGET_ASM_UNALIGNED_SI_OP
168 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
171 #undef TARGET_ATTRIBUTE_TABLE
172 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
173 #undef TARGET_ASM_UNIQUE_SECTION
174 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
175 #undef TARGET_ENCODE_SECTION_INFO
176 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
177 #undef TARGET_STRIP_NAME_ENCODING
178 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
179 #undef TARGET_RTX_COSTS
180 #define TARGET_RTX_COSTS mcore_rtx_costs
181 #undef TARGET_ADDRESS_COST
182 #define TARGET_ADDRESS_COST hook_int_rtx_0
183 #undef TARGET_MACHINE_DEPENDENT_REORG
184 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
186 #undef TARGET_PROMOTE_FUNCTION_ARGS
187 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
188 #undef TARGET_PROMOTE_FUNCTION_RETURN
189 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
190 #undef TARGET_PROMOTE_PROTOTYPES
191 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
193 #undef TARGET_RETURN_IN_MEMORY
194 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
196 #undef TARGET_SETUP_INCOMING_VARARGS
197 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
199 struct gcc_target targetm = TARGET_INITIALIZER;
201 /* Adjust the stack and return the number of bytes taken to do it. */
203 output_stack_adjust (int direction, int size)
205 /* If extending stack a lot, we do it incrementally. */
206 if (direction < 0 && size > mcore_stack_increment && mcore_stack_increment > 0)
208 rtx tmp = gen_rtx_REG (SImode, 1);
211 emit_insn (gen_movsi (tmp, GEN_INT (mcore_stack_increment)));
214 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
215 memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
216 MEM_VOLATILE_P (memref) = 1;
217 emit_insn (gen_movsi (memref, stack_pointer_rtx));
218 size -= mcore_stack_increment;
220 while (size > mcore_stack_increment);
222 /* SIZE is now the residual for the last adjustment,
223 which doesn't require a probe. */
229 rtx val = GEN_INT (size);
233 rtx nval = gen_rtx_REG (SImode, 1);
234 emit_insn (gen_movsi (nval, val));
239 insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
241 insn = gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
247 /* Work out the registers which need to be saved,
248 both as a mask and a count. */
251 calc_live_regs (int * count)
254 int live_regs_mask = 0;
258 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
260 if (regs_ever_live[reg] && !call_used_regs[reg])
263 live_regs_mask |= (1 << reg);
267 return live_regs_mask;
270 /* Print the operand address in x to the stream. */
273 mcore_print_operand_address (FILE * stream, rtx x)
275 switch (GET_CODE (x))
278 fprintf (stream, "(%s)", reg_names[REGNO (x)]);
283 rtx base = XEXP (x, 0);
284 rtx index = XEXP (x, 1);
286 if (GET_CODE (base) != REG)
288 /* Ensure that BASE is a register (one of them must be). */
294 switch (GET_CODE (index))
297 fprintf (stream, "(%s," HOST_WIDE_INT_PRINT_DEC ")",
298 reg_names[REGNO(base)], INTVAL (index));
311 output_addr_const (stream, x);
316 /* Print operand x (an rtx) in assembler syntax to file stream
317 according to modifier code.
319 'R' print the next register or memory location along, ie the lsw in
321 'O' print a constant without the #
322 'M' print a constant as its negative
323 'P' print log2 of a power of two
324 'Q' print log2 of an inverse of a power of two
325 'U' print register for ldm/stm instruction
326 'X' print byte number for xtrbN instruction. */
329 mcore_print_operand (FILE * stream, rtx x, int code)
335 fprintf (asm_out_file, "32");
337 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) + 1));
340 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x)));
343 fprintf (asm_out_file, "%d", exact_log2 (~INTVAL (x)));
346 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
349 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, - INTVAL (x));
352 /* Next location along in memory or register. */
353 switch (GET_CODE (x))
356 fputs (reg_names[REGNO (x) + 1], (stream));
359 mcore_print_operand_address
360 (stream, XEXP (adjust_address (x, SImode, 4), 0));
367 fprintf (asm_out_file, "%s-%s", reg_names[REGNO (x)],
368 reg_names[REGNO (x) + 3]);
371 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
374 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, 3 - INTVAL (x) / 8);
378 switch (GET_CODE (x))
381 fputs (reg_names[REGNO (x)], (stream));
384 output_address (XEXP (x, 0));
387 output_addr_const (stream, x);
394 /* What does a constant cost ? */
397 mcore_const_costs (rtx exp, enum rtx_code code)
399 int val = INTVAL (exp);
401 /* Easy constants. */
402 if ( CONST_OK_FOR_I (val)
403 || CONST_OK_FOR_M (val)
404 || CONST_OK_FOR_N (val)
405 || (code == PLUS && CONST_OK_FOR_L (val)))
408 && ( CONST_OK_FOR_M (~val)
409 || CONST_OK_FOR_N (~val)))
411 else if (code == PLUS
412 && ( CONST_OK_FOR_I (-val)
413 || CONST_OK_FOR_M (-val)
414 || CONST_OK_FOR_N (-val)))
420 /* What does an and instruction cost - we do this b/c immediates may
421 have been relaxed. We want to ensure that cse will cse relaxed immeds
422 out. Otherwise we'll get bad code (multiple reloads of the same const). */
425 mcore_and_cost (rtx x)
429 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
432 val = INTVAL (XEXP (x, 1));
434 /* Do it directly. */
435 if (CONST_OK_FOR_K (val) || CONST_OK_FOR_M (~val))
437 /* Takes one instruction to load. */
438 else if (const_ok_for_mcore (val))
440 /* Takes two instructions to load. */
441 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
444 /* Takes a lrw to load. */
448 /* What does an or cost - see and_cost(). */
451 mcore_ior_cost (rtx x)
455 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
458 val = INTVAL (XEXP (x, 1));
460 /* Do it directly with bclri. */
461 if (CONST_OK_FOR_M (val))
463 /* Takes one instruction to load. */
464 else if (const_ok_for_mcore (val))
466 /* Takes two instructions to load. */
467 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
470 /* Takes a lrw to load. */
475 mcore_rtx_costs (rtx x, int code, int outer_code, int * total)
480 *total = mcore_const_costs (x, outer_code);
492 *total = COSTS_N_INSNS (mcore_and_cost (x));
496 *total = COSTS_N_INSNS (mcore_ior_cost (x));
505 *total = COSTS_N_INSNS (100);
513 /* Check to see if a comparison against a constant can be made more efficient
514 by incrementing/decrementing the constant to get one that is more efficient
518 mcore_modify_comparison (enum rtx_code code)
520 rtx op1 = arch_compare_op1;
522 if (GET_CODE (op1) == CONST_INT)
524 int val = INTVAL (op1);
529 if (CONST_OK_FOR_J (val + 1))
531 arch_compare_op1 = GEN_INT (val + 1);
544 /* Prepare the operands for a comparison. */
547 mcore_gen_compare_reg (enum rtx_code code)
549 rtx op0 = arch_compare_op0;
550 rtx op1 = arch_compare_op1;
551 rtx cc_reg = gen_rtx_REG (CCmode, CC_REG);
553 if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
554 op1 = force_reg (SImode, op1);
556 /* cmpnei: 0-31 (K immediate)
557 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
560 case EQ: /* Use inverted condition, cmpne. */
564 case NE: /* Use normal condition, cmpne. */
565 if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
566 op1 = force_reg (SImode, op1);
569 case LE: /* Use inverted condition, reversed cmplt. */
573 case GT: /* Use normal condition, reversed cmplt. */
574 if (GET_CODE (op1) == CONST_INT)
575 op1 = force_reg (SImode, op1);
578 case GE: /* Use inverted condition, cmplt. */
582 case LT: /* Use normal condition, cmplt. */
583 if (GET_CODE (op1) == CONST_INT &&
584 /* covered by btsti x,31. */
586 ! CONST_OK_FOR_J (INTVAL (op1)))
587 op1 = force_reg (SImode, op1);
590 case GTU: /* Use inverted condition, cmple. */
591 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0)
593 /* Unsigned > 0 is the same as != 0, but we need
594 to invert the condition, so we want to set
595 code = EQ. This cannot be done however, as the
596 mcore does not support such a test. Instead we
597 cope with this case in the "bgtu" pattern itself
598 so we should never reach this point. */
606 case LEU: /* Use normal condition, reversed cmphs. */
607 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
608 op1 = force_reg (SImode, op1);
611 case LTU: /* Use inverted condition, cmphs. */
615 case GEU: /* Use normal condition, cmphs. */
616 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
617 op1 = force_reg (SImode, op1);
624 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_fmt_ee (code, CCmode, op0, op1)));
630 mcore_symbolic_address_p (rtx x)
632 switch (GET_CODE (x))
639 return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
640 || GET_CODE (XEXP (x, 0)) == LABEL_REF)
641 && GET_CODE (XEXP (x, 1)) == CONST_INT);
648 mcore_call_address_operand (rtx x, enum machine_mode mode)
650 return register_operand (x, mode) || CONSTANT_P (x);
653 /* Functions to output assembly code for a function call. */
656 mcore_output_call (rtx operands[], int index)
658 static char buffer[20];
659 rtx addr = operands [index];
665 if (mcore_current_function_name == 0)
668 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name,
672 sprintf (buffer, "jsr\t%%%d", index);
678 if (mcore_current_function_name == 0)
681 if (GET_CODE (addr) != SYMBOL_REF)
684 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, XSTR (addr, 0), 0);
687 sprintf (buffer, "jbsr\t%%%d", index);
693 /* Can we load a constant with a single instruction ? */
696 const_ok_for_mcore (int value)
698 if (value >= 0 && value <= 127)
701 /* Try exact power of two. */
702 if ((value & (value - 1)) == 0)
705 /* Try exact power of two - 1. */
706 if ((value & (value + 1)) == 0)
712 /* Can we load a constant inline with up to 2 instructions ? */
715 mcore_const_ok_for_inline (long value)
719 return try_constant_tricks (value, & x, & y) > 0;
722 /* Are we loading the constant using a not ? */
725 mcore_const_trick_uses_not (long value)
729 return try_constant_tricks (value, & x, & y) == 2;
732 /* Try tricks to load a constant inline and return the trick number if
733 success (0 is non-inlinable).
736 1: single instruction (do the usual thing)
737 2: single insn followed by a 'not'
738 3: single insn followed by a subi
739 4: single insn followed by an addi
740 5: single insn followed by rsubi
741 6: single insn followed by bseti
742 7: single insn followed by bclri
743 8: single insn followed by rotli
744 9: single insn followed by lsli
745 10: single insn followed by ixh
746 11: single insn followed by ixw. */
749 try_constant_tricks (long value, int * x, int * y)
752 unsigned bit, shf, rot;
754 if (const_ok_for_mcore (value))
755 return 1; /* Do the usual thing. */
759 if (const_ok_for_mcore (~value))
765 for (i = 1; i <= 32; i++)
767 if (const_ok_for_mcore (value - i))
775 if (const_ok_for_mcore (value + i))
786 for (i = 0; i <= 31; i++)
788 if (const_ok_for_mcore (i - value))
796 if (const_ok_for_mcore (value & ~bit))
804 if (const_ok_for_mcore (value | bit))
818 for (i = 1; i < 31; i++)
822 /* MCore has rotate left. */
826 rot |= c; /* Simulate rotate. */
828 if (const_ok_for_mcore (rot))
837 shf = 0; /* Can't use logical shift, low order bit is one. */
841 if (shf != 0 && const_ok_for_mcore (shf))
850 if ((value % 3) == 0 && const_ok_for_mcore (value / 3))
857 if ((value % 5) == 0 && const_ok_for_mcore (value / 5))
868 /* Check whether reg is dead at first. This is done by searching ahead
869 for either the next use (i.e., reg is live), a death note, or a set of
870 reg. Don't just use dead_or_set_p() since reload does not always mark
871 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
872 can ignore subregs by extracting the actual register. BRC */
875 mcore_is_dead (rtx first, rtx reg)
879 /* For mcore, subregs can't live independently of their parent regs. */
880 if (GET_CODE (reg) == SUBREG)
881 reg = SUBREG_REG (reg);
883 /* Dies immediately. */
884 if (dead_or_set_p (first, reg))
887 /* Look for conclusive evidence of live/death, otherwise we have
888 to assume that it is live. */
889 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
891 if (GET_CODE (insn) == JUMP_INSN)
892 return 0; /* We lose track, assume it is alive. */
894 else if (GET_CODE(insn) == CALL_INSN)
896 /* Call's might use it for target or register parms. */
897 if (reg_referenced_p (reg, PATTERN (insn))
898 || find_reg_fusage (insn, USE, reg))
900 else if (dead_or_set_p (insn, reg))
903 else if (GET_CODE (insn) == INSN)
905 if (reg_referenced_p (reg, PATTERN (insn)))
907 else if (dead_or_set_p (insn, reg))
912 /* No conclusive evidence either way, we can not take the chance
913 that control flow hid the use from us -- "I'm not dead yet". */
917 /* Count the number of ones in mask. */
920 mcore_num_ones (int mask)
922 /* A trick to count set bits recently posted on comp.compilers. */
923 mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555);
924 mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333);
925 mask = ((mask >> 4) + mask) & 0x0f0f0f0f;
926 mask = ((mask >> 8) + mask);
928 return (mask + (mask >> 16)) & 0xff;
931 /* Count the number of zeros in mask. */
934 mcore_num_zeros (int mask)
936 return 32 - mcore_num_ones (mask);
939 /* Determine byte being masked. */
942 mcore_byte_offset (unsigned int mask)
944 if (mask == 0x00ffffffL)
946 else if (mask == 0xff00ffffL)
948 else if (mask == 0xffff00ffL)
950 else if (mask == 0xffffff00L)
956 /* Determine halfword being masked. */
959 mcore_halfword_offset (unsigned int mask)
961 if (mask == 0x0000ffffL)
963 else if (mask == 0xffff0000L)
969 /* Output a series of bseti's corresponding to mask. */
972 mcore_output_bseti (rtx dst, int mask)
977 out_operands[0] = dst;
979 for (bit = 0; bit < 32; bit++)
981 if ((mask & 0x1) == 0x1)
983 out_operands[1] = GEN_INT (bit);
985 output_asm_insn ("bseti\t%0,%1", out_operands);
993 /* Output a series of bclri's corresponding to mask. */
996 mcore_output_bclri (rtx dst, int mask)
1001 out_operands[0] = dst;
1003 for (bit = 0; bit < 32; bit++)
1005 if ((mask & 0x1) == 0x0)
1007 out_operands[1] = GEN_INT (bit);
1009 output_asm_insn ("bclri\t%0,%1", out_operands);
1018 /* Output a conditional move of two constants that are +/- 1 within each
1019 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1020 really worth the effort. */
1023 mcore_output_cmov (rtx operands[], int cmp_t, const char * test)
1027 rtx out_operands[4];
1029 out_operands[0] = operands[0];
1031 /* Check to see which constant is loadable. */
1032 if (const_ok_for_mcore (INTVAL (operands[1])))
1034 out_operands[1] = operands[1];
1035 out_operands[2] = operands[2];
1037 else if (const_ok_for_mcore (INTVAL (operands[2])))
1039 out_operands[1] = operands[2];
1040 out_operands[2] = operands[1];
1042 /* Complement test since constants are swapped. */
1043 cmp_t = (cmp_t == 0);
1045 load_value = INTVAL (out_operands[1]);
1046 adjust_value = INTVAL (out_operands[2]);
1048 /* First output the test if folded into the pattern. */
1051 output_asm_insn (test, operands);
1053 /* Load the constant - for now, only support constants that can be
1054 generated with a single instruction. maybe add general inlinable
1055 constants later (this will increase the # of patterns since the
1056 instruction sequence has a different length attribute). */
1057 if (load_value >= 0 && load_value <= 127)
1058 output_asm_insn ("movi\t%0,%1", out_operands);
1059 else if ((load_value & (load_value - 1)) == 0)
1060 output_asm_insn ("bgeni\t%0,%P1", out_operands);
1061 else if ((load_value & (load_value + 1)) == 0)
1062 output_asm_insn ("bmaski\t%0,%N1", out_operands);
1064 /* Output the constant adjustment. */
1065 if (load_value > adjust_value)
1068 output_asm_insn ("decf\t%0", out_operands);
1070 output_asm_insn ("dect\t%0", out_operands);
1075 output_asm_insn ("incf\t%0", out_operands);
1077 output_asm_insn ("inct\t%0", out_operands);
1083 /* Outputs the peephole for moving a constant that gets not'ed followed
1084 by an and (i.e. combine the not and the and into andn). BRC */
1087 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
1090 rtx out_operands[3];
1091 const char * load_op;
1094 if (try_constant_tricks (INTVAL (operands[1]), &x, &y) != 2)
1097 out_operands[0] = operands[0];
1098 out_operands[1] = GEN_INT(x);
1099 out_operands[2] = operands[2];
1101 if (x >= 0 && x <= 127)
1102 load_op = "movi\t%0,%1";
1104 /* Try exact power of two. */
1105 else if ((x & (x - 1)) == 0)
1106 load_op = "bgeni\t%0,%P1";
1108 /* Try exact power of two - 1. */
1109 else if ((x & (x + 1)) == 0)
1110 load_op = "bmaski\t%0,%N1";
1113 load_op = "BADMOVI\t%0,%1";
1115 sprintf (buf, "%s\n\tandn\t%%2,%%0", load_op);
1116 output_asm_insn (buf, out_operands);
1121 /* Output an inline constant. */
1124 output_inline_const (enum machine_mode mode, rtx operands[])
1128 rtx out_operands[3];
1131 const char *dst_fmt;
1134 value = INTVAL (operands[1]);
1136 if ((trick_no = try_constant_tricks (value, &x, &y)) == 0)
1138 /* lrw's are handled separately: Large inlinable constants
1139 never get turned into lrw's. Our caller uses try_constant_tricks
1140 to back off to an lrw rather than calling this routine. */
1147 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1148 out_operands[0] = operands[0];
1149 out_operands[1] = GEN_INT (x);
1152 out_operands[2] = GEN_INT (y);
1154 /* Select dst format based on mode. */
1155 if (mode == DImode && (! TARGET_LITTLE_END))
1160 if (x >= 0 && x <= 127)
1161 sprintf (load_op, "movi\t%s,%%1", dst_fmt);
1163 /* Try exact power of two. */
1164 else if ((x & (x - 1)) == 0)
1165 sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt);
1167 /* Try exact power of two - 1. */
1168 else if ((x & (x + 1)) == 0)
1169 sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt);
1172 sprintf (load_op, "BADMOVI\t%s,%%1", dst_fmt);
1177 strcpy (buf, load_op);
1180 sprintf (buf, "%s\n\tnot\t%s\t// %d 0x%x", load_op, dst_fmt, value, value);
1183 sprintf (buf, "%s\n\taddi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1186 sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1189 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1190 sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1193 sprintf (buf, "%s\n\tbseti\t%s,%%P2\t// %d 0x%x", load_op, dst_fmt, value, value);
1196 sprintf (buf, "%s\n\tbclri\t%s,%%Q2\t// %d 0x%x", load_op, dst_fmt, value, value);
1199 sprintf (buf, "%s\n\trotli\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1202 sprintf (buf, "%s\n\tlsli\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1205 sprintf (buf, "%s\n\tixh\t%s,%s\t// %d 0x%x", load_op, dst_fmt, dst_fmt, value, value);
1208 sprintf (buf, "%s\n\tixw\t%s,%s\t// %d 0x%x", load_op, dst_fmt, dst_fmt, value, value);
1214 output_asm_insn (buf, out_operands);
1219 /* Output a move of a word or less value. */
1222 mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1223 enum machine_mode mode ATTRIBUTE_UNUSED)
1225 rtx dst = operands[0];
1226 rtx src = operands[1];
1228 if (GET_CODE (dst) == REG)
1230 if (GET_CODE (src) == REG)
1232 if (REGNO (src) == CC_REG) /* r-c */
1235 return "mov\t%0,%1"; /* r-r*/
1237 else if (GET_CODE (src) == MEM)
1239 if (GET_CODE (XEXP (src, 0)) == LABEL_REF)
1240 return "lrw\t%0,[%1]"; /* a-R */
1242 switch (GET_MODE (src)) /* r-m */
1245 return "ldw\t%0,%1";
1247 return "ld.h\t%0,%1";
1249 return "ld.b\t%0,%1";
1254 else if (GET_CODE (src) == CONST_INT)
1258 if (CONST_OK_FOR_I (INTVAL (src))) /* r-I */
1259 return "movi\t%0,%1";
1260 else if (CONST_OK_FOR_M (INTVAL (src))) /* r-M */
1261 return "bgeni\t%0,%P1\t// %1 %x1";
1262 else if (CONST_OK_FOR_N (INTVAL (src))) /* r-N */
1263 return "bmaski\t%0,%N1\t// %1 %x1";
1264 else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */
1265 return output_inline_const (SImode, operands); /* 1-2 insns */
1267 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1270 return "lrw\t%0, %1"; /* Into the literal pool. */
1272 else if (GET_CODE (dst) == MEM) /* m-r */
1273 switch (GET_MODE (dst))
1276 return "stw\t%1,%0";
1278 return "st.h\t%1,%0";
1280 return "st.b\t%1,%0";
1288 /* Return a sequence of instructions to perform DI or DF move.
1289 Since the MCORE cannot move a DI or DF in one instruction, we have
1290 to take care when we see overlapping source and dest registers. */
1293 mcore_output_movedouble (rtx operands[], enum machine_mode mode ATTRIBUTE_UNUSED)
1295 rtx dst = operands[0];
1296 rtx src = operands[1];
1298 if (GET_CODE (dst) == REG)
1300 if (GET_CODE (src) == REG)
1302 int dstreg = REGNO (dst);
1303 int srcreg = REGNO (src);
1305 /* Ensure the second source not overwritten. */
1306 if (srcreg + 1 == dstreg)
1307 return "mov %R0,%R1\n\tmov %0,%1";
1309 return "mov %0,%1\n\tmov %R0,%R1";
1311 else if (GET_CODE (src) == MEM)
1313 rtx memexp = memexp = XEXP (src, 0);
1314 int dstreg = REGNO (dst);
1317 if (GET_CODE (memexp) == LABEL_REF)
1318 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1319 else if (GET_CODE (memexp) == REG)
1320 basereg = REGNO (memexp);
1321 else if (GET_CODE (memexp) == PLUS)
1323 if (GET_CODE (XEXP (memexp, 0)) == REG)
1324 basereg = REGNO (XEXP (memexp, 0));
1325 else if (GET_CODE (XEXP (memexp, 1)) == REG)
1326 basereg = REGNO (XEXP (memexp, 1));
1333 /* ??? length attribute is wrong here. */
1334 if (dstreg == basereg)
1336 /* Just load them in reverse order. */
1337 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1339 /* XXX: alternative: move basereg to basereg+1
1340 and then fall through. */
1343 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1345 else if (GET_CODE (src) == CONST_INT)
1347 if (TARGET_LITTLE_END)
1349 if (CONST_OK_FOR_I (INTVAL (src)))
1350 output_asm_insn ("movi %0,%1", operands);
1351 else if (CONST_OK_FOR_M (INTVAL (src)))
1352 output_asm_insn ("bgeni %0,%P1", operands);
1353 else if (INTVAL (src) == -1)
1354 output_asm_insn ("bmaski %0,32", operands);
1355 else if (CONST_OK_FOR_N (INTVAL (src)))
1356 output_asm_insn ("bmaski %0,%N1", operands);
1360 if (INTVAL (src) < 0)
1361 return "bmaski %R0,32";
1363 return "movi %R0,0";
1367 if (CONST_OK_FOR_I (INTVAL (src)))
1368 output_asm_insn ("movi %R0,%1", operands);
1369 else if (CONST_OK_FOR_M (INTVAL (src)))
1370 output_asm_insn ("bgeni %R0,%P1", operands);
1371 else if (INTVAL (src) == -1)
1372 output_asm_insn ("bmaski %R0,32", operands);
1373 else if (CONST_OK_FOR_N (INTVAL (src)))
1374 output_asm_insn ("bmaski %R0,%N1", operands);
1378 if (INTVAL (src) < 0)
1379 return "bmaski %0,32";
1387 else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
1388 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1393 /* Predicates used by the templates. */
1395 /* Nonzero if OP can be source of a simple move operation. */
1398 mcore_general_movsrc_operand (rtx op, enum machine_mode mode)
1400 /* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
1401 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
1404 return general_operand (op, mode);
1407 /* Nonzero if OP can be destination of a simple move operation. */
1410 mcore_general_movdst_operand (rtx op, enum machine_mode mode)
1412 if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
1415 return general_operand (op, mode);
1418 /* Nonzero if OP is a normal arithmetic register. */
1421 mcore_arith_reg_operand (rtx op, enum machine_mode mode)
1423 if (! register_operand (op, mode))
1426 if (GET_CODE (op) == SUBREG)
1427 op = SUBREG_REG (op);
1429 if (GET_CODE (op) == REG)
1430 return REGNO (op) != CC_REG;
1435 /* Nonzero if OP should be recognized during reload for an ixh/ixw
1436 operand. See the ixh/ixw patterns. */
1439 mcore_reload_operand (rtx op, enum machine_mode mode)
1441 if (mcore_arith_reg_operand (op, mode))
1444 if (! reload_in_progress)
1447 return GET_CODE (op) == MEM;
1450 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1453 mcore_arith_J_operand (rtx op, enum machine_mode mode)
1455 if (register_operand (op, mode))
1458 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
1464 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1467 mcore_arith_K_operand (rtx op, enum machine_mode mode)
1469 if (register_operand (op, mode))
1472 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
1478 /* Nonzero if OP is a valid source operand for a shift or rotate insn. */
1481 mcore_arith_K_operand_not_0 (rtx op, enum machine_mode mode)
1483 if (register_operand (op, mode))
1486 if ( GET_CODE (op) == CONST_INT
1487 && CONST_OK_FOR_K (INTVAL (op))
1488 && INTVAL (op) != 0)
1495 mcore_arith_K_S_operand (rtx op, enum machine_mode mode)
1497 if (register_operand (op, mode))
1500 if (GET_CODE (op) == CONST_INT)
1502 if (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_M (~INTVAL (op)))
1510 mcore_arith_S_operand (rtx op)
1512 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op)))
1519 mcore_arith_M_operand (rtx op, enum machine_mode mode)
1521 if (register_operand (op, mode))
1524 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
1530 /* Nonzero if OP is a valid source operand for loading. */
1533 mcore_arith_imm_operand (rtx op, enum machine_mode mode)
1535 if (register_operand (op, mode))
1538 if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
1545 mcore_arith_any_imm_operand (rtx op, enum machine_mode mode)
1547 if (register_operand (op, mode))
1550 if (GET_CODE (op) == CONST_INT)
1556 /* Nonzero if OP is a valid source operand for a cmov with two consts +/- 1. */
1559 mcore_arith_O_operand (rtx op, enum machine_mode mode)
1561 if (register_operand (op, mode))
1564 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
1570 /* Nonzero if OP is a valid source operand for a btsti. */
1573 mcore_literal_K_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1575 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
1581 /* Nonzero if OP is a valid source operand for an add/sub insn. */
1584 mcore_addsub_operand (rtx op, enum machine_mode mode)
1586 if (register_operand (op, mode))
1589 if (GET_CODE (op) == CONST_INT)
1593 /* The following is removed because it precludes large constants from being
1594 returned as valid source operands for and add/sub insn. While large
1595 constants may not directly be used in an add/sub, they may if first loaded
1596 into a register. Thus, this predicate should indicate that they are valid,
1597 and the constraint in mcore.md should control whether an additional load to
1598 register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */
1600 if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op)))
1608 /* Nonzero if OP is a valid source operand for a compare operation. */
1611 mcore_compare_operand (rtx op, enum machine_mode mode)
1613 if (register_operand (op, mode))
1616 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1622 /* Expand insert bit field. BRC */
1625 mcore_expand_insv (rtx operands[])
1627 int width = INTVAL (operands[1]);
1628 int posn = INTVAL (operands[2]);
1630 rtx mreg, sreg, ereg;
1632 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1633 for width==1 must be removed. Look around line 368. This is something
1634 we really want the md part to do. */
1635 if (width == 1 && GET_CODE (operands[3]) == CONST_INT)
1637 /* Do directly with bseti or bclri. */
1638 /* RBE: 2/97 consider only low bit of constant. */
1639 if ((INTVAL(operands[3])&1) == 0)
1641 mask = ~(1 << posn);
1642 emit_insn (gen_rtx_SET (SImode, operands[0],
1643 gen_rtx_AND (SImode, operands[0], GEN_INT (mask))));
1648 emit_insn (gen_rtx_SET (SImode, operands[0],
1649 gen_rtx_IOR (SImode, operands[0], GEN_INT (mask))));
1655 /* Look at some bit-field placements that we aren't interested
1656 in handling ourselves, unless specifically directed to do so. */
1657 if (! TARGET_W_FIELD)
1658 return 0; /* Generally, give up about now. */
1660 if (width == 8 && posn % 8 == 0)
1661 /* Byte sized and aligned; let caller break it up. */
1664 if (width == 16 && posn % 16 == 0)
1665 /* Short sized and aligned; let caller break it up. */
1668 /* The general case - we can do this a little bit better than what the
1669 machine independent part tries. This will get rid of all the subregs
1670 that mess up constant folding in combine when working with relaxed
1673 /* If setting the entire field, do it directly. */
1674 if (GET_CODE (operands[3]) == CONST_INT &&
1675 INTVAL (operands[3]) == ((1 << width) - 1))
1677 mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn));
1678 emit_insn (gen_rtx_SET (SImode, operands[0],
1679 gen_rtx_IOR (SImode, operands[0], mreg)));
1683 /* Generate the clear mask. */
1684 mreg = force_reg (SImode, GEN_INT (~(((1 << width) - 1) << posn)));
1686 /* Clear the field, to overlay it later with the source. */
1687 emit_insn (gen_rtx_SET (SImode, operands[0],
1688 gen_rtx_AND (SImode, operands[0], mreg)));
1690 /* If the source is constant 0, we've nothing to add back. */
1691 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
1694 /* XXX: Should we worry about more games with constant values?
1695 We've covered the high profile: set/clear single-bit and many-bit
1696 fields. How often do we see "arbitrary bit pattern" constants? */
1697 sreg = copy_to_mode_reg (SImode, operands[3]);
1699 /* Extract src as same width as dst (needed for signed values). We
1700 always have to do this since we widen everything to SImode.
1701 We don't have to mask if we're shifting this up against the
1702 MSB of the register (e.g., the shift will push out any hi-order
1704 if (width + posn != (int) GET_MODE_SIZE (SImode))
1706 ereg = force_reg (SImode, GEN_INT ((1 << width) - 1));
1707 emit_insn (gen_rtx_SET (SImode, sreg,
1708 gen_rtx_AND (SImode, sreg, ereg)));
1711 /* Insert source value in dest. */
1713 emit_insn (gen_rtx_SET (SImode, sreg,
1714 gen_rtx_ASHIFT (SImode, sreg, GEN_INT (posn))));
1716 emit_insn (gen_rtx_SET (SImode, operands[0],
1717 gen_rtx_IOR (SImode, operands[0], sreg)));
1722 /* Return 1 if OP is a load multiple operation. It is known to be a
1723 PARALLEL and the first section will be tested. */
1726 mcore_load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1728 int count = XVECLEN (op, 0);
1733 /* Perform a quick check so we don't blow up below. */
1735 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1736 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1737 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1740 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1741 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1743 for (i = 1; i < count; i++)
1745 rtx elt = XVECEXP (op, 0, i);
1747 if (GET_CODE (elt) != SET
1748 || GET_CODE (SET_DEST (elt)) != REG
1749 || GET_MODE (SET_DEST (elt)) != SImode
1750 || REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
1751 || GET_CODE (SET_SRC (elt)) != MEM
1752 || GET_MODE (SET_SRC (elt)) != SImode
1753 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1754 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1755 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1756 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1763 /* Similar, but tests for store multiple. */
1766 mcore_store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1768 int count = XVECLEN (op, 0);
1773 /* Perform a quick check so we don't blow up below. */
1775 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1776 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1777 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1780 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1781 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1783 for (i = 1; i < count; i++)
1785 rtx elt = XVECEXP (op, 0, i);
1787 if (GET_CODE (elt) != SET
1788 || GET_CODE (SET_SRC (elt)) != REG
1789 || GET_MODE (SET_SRC (elt)) != SImode
1790 || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
1791 || GET_CODE (SET_DEST (elt)) != MEM
1792 || GET_MODE (SET_DEST (elt)) != SImode
1793 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1794 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1795 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1796 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1803 /* ??? Block move stuff stolen from m88k. This code has not been
1804 verified for correctness. */
1806 /* Emit code to perform a block move. Choose the best method.
1808 OPERANDS[0] is the destination.
1809 OPERANDS[1] is the source.
1810 OPERANDS[2] is the size.
1811 OPERANDS[3] is the alignment safe to use. */
1813 /* Emit code to perform a block move with an offset sequence of ldw/st
1814 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1815 known constants. DEST and SRC are registers. OFFSET is the known
1816 starting point for the output pattern. */
1818 static const enum machine_mode mode_from_align[] =
1820 VOIDmode, QImode, HImode, VOIDmode, SImode,
1821 VOIDmode, VOIDmode, VOIDmode, DImode
1825 block_move_sequence (rtx dest, rtx dst_mem, rtx src, rtx src_mem,
1826 int size, int align, int offset)
1829 enum machine_mode mode[2];
1834 int offset_ld = offset;
1835 int offset_st = offset;
1837 active[0] = active[1] = FALSE;
1839 /* Establish parameters for the first load and for the second load if
1840 it is known to be the same mode as the first. */
1841 amount[0] = amount[1] = align;
1843 mode[0] = mode_from_align[align];
1845 temp[0] = gen_reg_rtx (mode[0]);
1847 if (size >= 2 * align)
1850 temp[1] = gen_reg_rtx (mode[1]);
1862 /* Change modes as the sequence tails off. */
1863 if (size < amount[next])
1865 amount[next] = (size >= 4 ? 4 : (size >= 2 ? 2 : 1));
1866 mode[next] = mode_from_align[amount[next]];
1867 temp[next] = gen_reg_rtx (mode[next]);
1870 size -= amount[next];
1871 srcp = gen_rtx_MEM (
1873 MEM_IN_STRUCT_P (src_mem) ? mode[next] : BLKmode,
1877 gen_rtx_PLUS (Pmode, src, GEN_INT (offset_ld)));
1879 RTX_UNCHANGING_P (srcp) = RTX_UNCHANGING_P (src_mem);
1880 MEM_VOLATILE_P (srcp) = MEM_VOLATILE_P (src_mem);
1881 MEM_IN_STRUCT_P (srcp) = 1;
1882 emit_insn (gen_rtx_SET (VOIDmode, temp[next], srcp));
1883 offset_ld += amount[next];
1884 active[next] = TRUE;
1889 active[phase] = FALSE;
1891 dstp = gen_rtx_MEM (
1893 MEM_IN_STRUCT_P (dst_mem) ? mode[phase] : BLKmode,
1897 gen_rtx_PLUS (Pmode, dest, GEN_INT (offset_st)));
1899 RTX_UNCHANGING_P (dstp) = RTX_UNCHANGING_P (dst_mem);
1900 MEM_VOLATILE_P (dstp) = MEM_VOLATILE_P (dst_mem);
1901 MEM_IN_STRUCT_P (dstp) = 1;
1902 emit_insn (gen_rtx_SET (VOIDmode, dstp, temp[phase]));
1903 offset_st += amount[phase];
1906 while (active[next]);
1910 mcore_expand_block_move (rtx dst_mem, rtx src_mem, rtx * operands)
1912 int align = INTVAL (operands[3]);
1915 if (GET_CODE (operands[2]) == CONST_INT)
1917 bytes = INTVAL (operands[2]);
1924 /* RBE: bumped 1 and 2 byte align from 1 and 2 to 4 and 8 bytes before
1925 we give up and go to memcpy. */
1926 if ((align == 4 && (bytes <= 4*4
1927 || ((bytes & 01) == 0 && bytes <= 8*4)
1928 || ((bytes & 03) == 0 && bytes <= 16*4)))
1929 || (align == 2 && bytes <= 4*2)
1930 || (align == 1 && bytes <= 4*1))
1932 block_move_sequence (operands[0], dst_mem, operands[1], src_mem,
1938 /* If we get here, just use the library routine. */
1939 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0, VOIDmode, 3,
1940 operands[0], Pmode, operands[1], Pmode, operands[2],
1945 /* Code to generate prologue and epilogue sequences. */
1946 static int number_of_regs_before_varargs;
1948 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1949 for a varargs function. */
1950 static int current_function_anonymous_args;
1952 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1953 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1954 #define ADDI_REACH (32) /* Maximum addi operand. */
1957 layout_mcore_frame (struct mcore_frame * infp)
1966 unsigned int growths;
1969 /* Might have to spill bytes to re-assemble a big argument that
1970 was passed partially in registers and partially on the stack. */
1971 nbytes = current_function_pretend_args_size;
1973 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1974 if (current_function_anonymous_args)
1975 nbytes += (NPARM_REGS - number_of_regs_before_varargs) * UNITS_PER_WORD;
1977 infp->arg_size = nbytes;
1979 /* How much space to save non-volatile registers we stomp. */
1980 infp->reg_mask = calc_live_regs (& n);
1981 infp->reg_size = n * 4;
1983 /* And the rest of it... locals and space for overflowed outbounds. */
1984 infp->local_size = get_frame_size ();
1985 infp->outbound_size = current_function_outgoing_args_size;
1987 /* Make sure we have a whole number of words for the locals. */
1988 if (infp->local_size % STACK_BYTES)
1989 infp->local_size = (infp->local_size + STACK_BYTES - 1) & ~ (STACK_BYTES -1);
1991 /* Only thing we know we have to pad is the outbound space, since
1992 we've aligned our locals assuming that base of locals is aligned. */
1993 infp->pad_local = 0;
1995 infp->pad_outbound = 0;
1996 if (infp->outbound_size % STACK_BYTES)
1997 infp->pad_outbound = STACK_BYTES - (infp->outbound_size % STACK_BYTES);
1999 /* Now we see how we want to stage the prologue so that it does
2000 the most appropriate stack growth and register saves to either:
2002 (2) reduce instruction space, or
2003 (3) reduce stack space. */
2004 for (i = 0; i < ARRAY_SIZE (infp->growth); i++)
2005 infp->growth[i] = 0;
2007 regarg = infp->reg_size + infp->arg_size;
2008 localregarg = infp->local_size + regarg;
2009 localreg = infp->local_size + infp->reg_size;
2010 outbounds = infp->outbound_size + infp->pad_outbound;
2013 /* XXX: Consider one where we consider localregarg + outbound too! */
2015 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
2016 use stw's with offsets and buy the frame in one shot. */
2017 if (localregarg <= ADDI_REACH
2018 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
2020 /* Make sure we'll be aligned. */
2021 if (localregarg % STACK_BYTES)
2022 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
2024 step = localregarg + infp->pad_reg;
2025 infp->reg_offset = infp->local_size;
2027 if (outbounds + step <= ADDI_REACH && !frame_pointer_needed)
2030 infp->reg_offset += outbounds;
2034 infp->arg_offset = step - 4;
2035 infp->growth[growths++] = step;
2036 infp->reg_growth = growths;
2037 infp->local_growth = growths;
2039 /* If we haven't already folded it in. */
2041 infp->growth[growths++] = outbounds;
2046 /* Frame can't be done with a single subi, but can be done with 2
2047 insns. If the 'stm' is getting <= 2 registers, we use stw's and
2048 shift some of the stack purchase into the first subi, so both are
2049 single instructions. */
2050 if (localregarg <= STORE_REACH
2051 && (infp->local_size > ADDI_REACH)
2052 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
2056 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
2057 if (localregarg % STACK_BYTES)
2058 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
2060 all = localregarg + infp->pad_reg + infp->pad_local;
2061 step = ADDI_REACH; /* As much up front as we can. */
2065 /* XXX: Consider whether step will still be aligned; we believe so. */
2066 infp->arg_offset = step - 4;
2067 infp->growth[growths++] = step;
2068 infp->reg_growth = growths;
2069 infp->reg_offset = step - infp->pad_reg - infp->reg_size;
2072 /* Can we fold in any space required for outbounds? */
2073 if (outbounds + all <= ADDI_REACH && !frame_pointer_needed)
2079 /* Get the rest of the locals in place. */
2081 infp->growth[growths++] = step;
2082 infp->local_growth = growths;
2087 /* Finish off if we need to do so. */
2089 infp->growth[growths++] = outbounds;
2094 /* Registers + args is nicely aligned, so we'll buy that in one shot.
2095 Then we buy the rest of the frame in 1 or 2 steps depending on
2096 whether we need a frame pointer. */
2097 if ((regarg % STACK_BYTES) == 0)
2099 infp->growth[growths++] = regarg;
2100 infp->reg_growth = growths;
2101 infp->arg_offset = regarg - 4;
2102 infp->reg_offset = 0;
2104 if (infp->local_size % STACK_BYTES)
2105 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
2107 step = infp->local_size + infp->pad_local;
2109 if (!frame_pointer_needed)
2115 infp->growth[growths++] = step;
2116 infp->local_growth = growths;
2118 /* If there's any left to be done. */
2120 infp->growth[growths++] = outbounds;
2125 /* XXX: optimizations that we'll want to play with....
2126 -- regarg is not aligned, but it's a small number of registers;
2127 use some of localsize so that regarg is aligned and then
2128 save the registers. */
2130 /* Simple encoding; plods down the stack buying the pieces as it goes.
2131 -- does not optimize space consumption.
2132 -- does not attempt to optimize instruction counts.
2133 -- but it is safe for all alignments. */
2134 if (regarg % STACK_BYTES != 0)
2135 infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES);
2137 infp->growth[growths++] = infp->arg_size + infp->reg_size + infp->pad_reg;
2138 infp->reg_growth = growths;
2139 infp->arg_offset = infp->growth[0] - 4;
2140 infp->reg_offset = 0;
2142 if (frame_pointer_needed)
2144 if (infp->local_size % STACK_BYTES != 0)
2145 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
2147 infp->growth[growths++] = infp->local_size + infp->pad_local;
2148 infp->local_growth = growths;
2150 infp->growth[growths++] = outbounds;
2154 if ((infp->local_size + outbounds) % STACK_BYTES != 0)
2155 infp->pad_local = STACK_BYTES - ((infp->local_size + outbounds) % STACK_BYTES);
2157 infp->growth[growths++] = infp->local_size + infp->pad_local + outbounds;
2158 infp->local_growth = growths;
2161 /* Anything else that we've forgotten?, plus a few consistency checks. */
2163 assert (infp->reg_offset >= 0);
2164 assert (growths <= MAX_STACK_GROWS);
2166 for (i = 0; i < growths; i++)
2168 if (infp->growth[i] % STACK_BYTES)
2170 fprintf (stderr,"stack growth of %d is not %d aligned\n",
2171 infp->growth[i], STACK_BYTES);
2177 /* Define the offset between two registers, one to be eliminated, and
2178 the other its replacement, at the start of a routine. */
2181 mcore_initial_elimination_offset (int from, int to)
2185 struct mcore_frame fi;
2187 layout_mcore_frame (& fi);
2190 above_frame = fi.local_size + fi.pad_local + fi.reg_size + fi.pad_reg;
2192 below_frame = fi.outbound_size + fi.pad_outbound;
2194 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
2197 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2198 return above_frame + below_frame;
2200 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2208 /* Keep track of some information about varargs for the prolog. */
2211 mcore_setup_incoming_varargs (CUMULATIVE_ARGS *args_so_far,
2212 enum machine_mode mode, tree type,
2213 int * ptr_pretend_size ATTRIBUTE_UNUSED,
2214 int second_time ATTRIBUTE_UNUSED)
2216 current_function_anonymous_args = 1;
2218 /* We need to know how many argument registers are used before
2219 the varargs start, so that we can push the remaining argument
2220 registers during the prologue. */
2221 number_of_regs_before_varargs = *args_so_far + mcore_num_arg_regs (mode, type);
2223 /* There is a bug somewhere in the arg handling code.
2224 Until I can find it this workaround always pushes the
2225 last named argument onto the stack. */
2226 number_of_regs_before_varargs = *args_so_far;
2228 /* The last named argument may be split between argument registers
2229 and the stack. Allow for this here. */
2230 if (number_of_regs_before_varargs > NPARM_REGS)
2231 number_of_regs_before_varargs = NPARM_REGS;
2235 mcore_expand_prolog (void)
2237 struct mcore_frame fi;
2238 int space_allocated = 0;
2241 /* Find out what we're doing. */
2242 layout_mcore_frame (&fi);
2244 space_allocated = fi.arg_size + fi.reg_size + fi.local_size +
2245 fi.outbound_size + fi.pad_outbound + fi.pad_local + fi.pad_reg;
2249 /* Emit a symbol for this routine's frame size. */
2252 x = DECL_RTL (current_function_decl);
2254 if (GET_CODE (x) != MEM)
2259 if (GET_CODE (x) != SYMBOL_REF)
2262 if (mcore_current_function_name)
2263 free (mcore_current_function_name);
2265 mcore_current_function_name = xstrdup (XSTR (x, 0));
2267 ASM_OUTPUT_CG_NODE (asm_out_file, mcore_current_function_name, space_allocated);
2269 if (current_function_calls_alloca)
2270 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, "alloca", 1);
2273 We're looking at how the 8byte alignment affects stack layout
2274 and where we had to pad things. This emits information we can
2275 extract which tells us about frame sizes and the like. */
2276 fprintf (asm_out_file,
2277 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
2278 mcore_current_function_name,
2279 fi.arg_size, fi.reg_size, fi.reg_mask,
2280 fi.local_size, fi.outbound_size,
2281 frame_pointer_needed);
2284 if (mcore_naked_function_p ())
2287 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2288 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2290 /* If we have a parameter passed partially in regs and partially in memory,
2291 the registers will have been stored to memory already in function.c. So
2292 we only need to do something here for varargs functions. */
2293 if (fi.arg_size != 0 && current_function_pretend_args_size == 0)
2296 int rn = FIRST_PARM_REG + NPARM_REGS - 1;
2297 int remaining = fi.arg_size;
2299 for (offset = fi.arg_offset; remaining >= 4; offset -= 4, rn--, remaining -= 4)
2301 emit_insn (gen_movsi
2302 (gen_rtx_MEM (SImode,
2303 plus_constant (stack_pointer_rtx, offset)),
2304 gen_rtx_REG (SImode, rn)));
2308 /* Do we need another stack adjustment before we do the register saves? */
2309 if (growth < fi.reg_growth)
2310 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2312 if (fi.reg_size != 0)
2315 int offs = fi.reg_offset;
2317 for (i = 15; i >= 0; i--)
2319 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2323 while (fi.reg_mask & (1 << first_reg))
2327 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode, stack_pointer_rtx),
2328 gen_rtx_REG (SImode, first_reg),
2329 GEN_INT (16 - first_reg)));
2331 i -= (15 - first_reg);
2332 offs += (16 - first_reg) * 4;
2334 else if (fi.reg_mask & (1 << i))
2336 emit_insn (gen_movsi
2337 (gen_rtx_MEM (SImode,
2338 plus_constant (stack_pointer_rtx, offs)),
2339 gen_rtx_REG (SImode, i)));
2345 /* Figure the locals + outbounds. */
2346 if (frame_pointer_needed)
2348 /* If we haven't already purchased to 'fp'. */
2349 if (growth < fi.local_growth)
2350 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2352 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2354 /* ... and then go any remaining distance for outbounds, etc. */
2355 if (fi.growth[growth])
2356 output_stack_adjust (-1, fi.growth[growth++]);
2360 if (growth < fi.local_growth)
2361 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2362 if (fi.growth[growth])
2363 output_stack_adjust (-1, fi.growth[growth++]);
2368 mcore_expand_epilog (void)
2370 struct mcore_frame fi;
2373 int growth = MAX_STACK_GROWS - 1 ;
2376 /* Find out what we're doing. */
2377 layout_mcore_frame(&fi);
2379 if (mcore_naked_function_p ())
2382 /* If we had a frame pointer, restore the sp from that. */
2383 if (frame_pointer_needed)
2385 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
2386 growth = fi.local_growth - 1;
2390 /* XXX: while loop should accumulate and do a single sell. */
2391 while (growth >= fi.local_growth)
2393 if (fi.growth[growth] != 0)
2394 output_stack_adjust (1, fi.growth[growth]);
2399 /* Make sure we've shrunk stack back to the point where the registers
2400 were laid down. This is typically 0/1 iterations. Then pull the
2401 register save information back off the stack. */
2402 while (growth >= fi.reg_growth)
2403 output_stack_adjust ( 1, fi.growth[growth--]);
2405 offs = fi.reg_offset;
2407 for (i = 15; i >= 0; i--)
2409 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2413 /* Find the starting register. */
2416 while (fi.reg_mask & (1 << first_reg))
2421 emit_insn (gen_load_multiple (gen_rtx_REG (SImode, first_reg),
2422 gen_rtx_MEM (SImode, stack_pointer_rtx),
2423 GEN_INT (16 - first_reg)));
2425 i -= (15 - first_reg);
2426 offs += (16 - first_reg) * 4;
2428 else if (fi.reg_mask & (1 << i))
2430 emit_insn (gen_movsi
2431 (gen_rtx_REG (SImode, i),
2432 gen_rtx_MEM (SImode,
2433 plus_constant (stack_pointer_rtx, offs))));
2438 /* Give back anything else. */
2439 /* XXX: Should accumulate total and then give it back. */
2441 output_stack_adjust ( 1, fi.growth[growth--]);
2444 /* This code is borrowed from the SH port. */
2446 /* The MCORE cannot load a large constant into a register, constants have to
2447 come from a pc relative load. The reference of a pc relative load
2448 instruction must be less than 1k infront of the instruction. This
2449 means that we often have to dump a constant inside a function, and
2450 generate code to branch around it.
2452 It is important to minimize this, since the branches will slow things
2453 down and make things bigger.
2455 Worst case code looks like:
2471 We fix this by performing a scan before scheduling, which notices which
2472 instructions need to have their operands fetched from the constant table
2473 and builds the table.
2477 scan, find an instruction which needs a pcrel move. Look forward, find the
2478 last barrier which is within MAX_COUNT bytes of the requirement.
2479 If there isn't one, make one. Process all the instructions between
2480 the find and the barrier.
2482 In the above example, we can tell that L3 is within 1k of L1, so
2483 the first move can be shrunk from the 2 insn+constant sequence into
2484 just 1 insn, and the constant moved to L3 to make:
2494 Then the second move becomes the target for the shortening process. */
2498 rtx value; /* Value in table. */
2499 rtx label; /* Label of value. */
2502 /* The maximum number of constants that can fit into one pool, since
2503 the pc relative range is 0...1020 bytes and constants are at least 4
2504 bytes long. We subtract 4 from the range to allow for the case where
2505 we need to add a branch/align before the constant pool. */
2507 #define MAX_COUNT 1016
2508 #define MAX_POOL_SIZE (MAX_COUNT/4)
2509 static pool_node pool_vector[MAX_POOL_SIZE];
2510 static int pool_size;
2512 /* Dump out any constants accumulated in the final pass. These
2513 will only be labels. */
2516 mcore_output_jump_label_table (void)
2522 fprintf (asm_out_file, "\t.align 2\n");
2524 for (i = 0; i < pool_size; i++)
2526 pool_node * p = pool_vector + i;
2528 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (p->label));
2530 output_asm_insn (".long %0", &p->value);
2539 /* Check whether insn is a candidate for a conditional. */
2542 is_cond_candidate (rtx insn)
2544 /* The only things we conditionalize are those that can be directly
2545 changed into a conditional. Only bother with SImode items. If
2546 we wanted to be a little more aggressive, we could also do other
2547 modes such as DImode with reg-reg move or load 0. */
2548 if (GET_CODE (insn) == INSN)
2550 rtx pat = PATTERN (insn);
2553 if (GET_CODE (pat) != SET)
2556 dst = XEXP (pat, 0);
2558 if ((GET_CODE (dst) != REG &&
2559 GET_CODE (dst) != SUBREG) ||
2560 GET_MODE (dst) != SImode)
2563 src = XEXP (pat, 1);
2565 if ((GET_CODE (src) == REG ||
2566 (GET_CODE (src) == SUBREG &&
2567 GET_CODE (SUBREG_REG (src)) == REG)) &&
2568 GET_MODE (src) == SImode)
2569 return COND_MOV_INSN;
2570 else if (GET_CODE (src) == CONST_INT &&
2572 return COND_CLR_INSN;
2573 else if (GET_CODE (src) == PLUS &&
2574 (GET_CODE (XEXP (src, 0)) == REG ||
2575 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2576 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2577 GET_MODE (XEXP (src, 0)) == SImode &&
2578 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2579 INTVAL (XEXP (src, 1)) == 1)
2580 return COND_INC_INSN;
2581 else if (((GET_CODE (src) == MINUS &&
2582 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2583 INTVAL( XEXP (src, 1)) == 1) ||
2584 (GET_CODE (src) == PLUS &&
2585 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2586 INTVAL (XEXP (src, 1)) == -1)) &&
2587 (GET_CODE (XEXP (src, 0)) == REG ||
2588 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2589 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2590 GET_MODE (XEXP (src, 0)) == SImode)
2591 return COND_DEC_INSN;
2593 /* Some insns that we don't bother with:
2594 (set (rx:DI) (ry:DI))
2595 (set (rx:DI) (const_int 0))
2599 else if (GET_CODE (insn) == JUMP_INSN &&
2600 GET_CODE (PATTERN (insn)) == SET &&
2601 GET_CODE (XEXP (PATTERN (insn), 1)) == LABEL_REF)
2602 return COND_BRANCH_INSN;
2607 /* Emit a conditional version of insn and replace the old insn with the
2608 new one. Return the new insn if emitted. */
2611 emit_new_cond_insn (rtx insn, int cond)
2617 if ((num = is_cond_candidate (insn)) == COND_NO)
2620 pat = PATTERN (insn);
2622 if (GET_CODE (insn) == INSN)
2624 dst = SET_DEST (pat);
2625 src = SET_SRC (pat);
2629 dst = JUMP_LABEL (insn);
2638 c_insn = gen_movt0 (dst, src, dst);
2640 c_insn = gen_movt0 (dst, dst, src);
2645 c_insn = gen_incscc (dst, dst);
2647 c_insn = gen_incscc_false (dst, dst);
2652 c_insn = gen_decscc (dst, dst);
2654 c_insn = gen_decscc_false (dst, dst);
2657 case COND_BRANCH_INSN:
2659 c_insn = gen_branch_true (dst);
2661 c_insn = gen_branch_false (dst);
2668 /* Only copy the notes if they exist. */
2669 if (rtx_length [GET_CODE (c_insn)] >= 7 && rtx_length [GET_CODE (insn)] >= 7)
2671 /* We really don't need to bother with the notes and links at this
2672 point, but go ahead and save the notes. This will help is_dead()
2673 when applying peepholes (links don't matter since they are not
2674 used any more beyond this point for the mcore). */
2675 REG_NOTES (c_insn) = REG_NOTES (insn);
2678 if (num == COND_BRANCH_INSN)
2680 /* For jumps, we need to be a little bit careful and emit the new jump
2681 before the old one and to update the use count for the target label.
2682 This way, the barrier following the old (uncond) jump will get
2683 deleted, but the label won't. */
2684 c_insn = emit_jump_insn_before (c_insn, insn);
2686 ++ LABEL_NUSES (dst);
2688 JUMP_LABEL (c_insn) = dst;
2691 c_insn = emit_insn_after (c_insn, insn);
2698 /* Attempt to change a basic block into a series of conditional insns. This
2699 works by taking the branch at the end of the 1st block and scanning for the
2700 end of the 2nd block. If all instructions in the 2nd block have cond.
2701 versions and the label at the start of block 3 is the same as the target
2702 from the branch at block 1, then conditionalize all insn in block 2 using
2703 the inverse condition of the branch at block 1. (Note I'm bending the
2704 definition of basic block here.)
2708 bt L2 <-- end of block 1 (delete)
2711 br L3 <-- end of block 2
2713 L2: ... <-- start of block 3 (NUSES==1)
2724 we can delete the L2 label if NUSES==1 and re-apply the optimization
2725 starting at the last instruction of block 2. This may allow an entire
2726 if-then-else statement to be conditionalized. BRC */
2728 conditionalize_block (rtx first)
2732 rtx end_blk_1_br = 0;
2733 rtx end_blk_2_insn = 0;
2734 rtx start_blk_3_lab = 0;
2740 /* Check that the first insn is a candidate conditional jump. This is
2741 the one that we'll eliminate. If not, advance to the next insn to
2743 if (GET_CODE (first) != JUMP_INSN ||
2744 GET_CODE (PATTERN (first)) != SET ||
2745 GET_CODE (XEXP (PATTERN (first), 1)) != IF_THEN_ELSE)
2746 return NEXT_INSN (first);
2748 /* Extract some information we need. */
2749 end_blk_1_br = first;
2750 br_pat = PATTERN (end_blk_1_br);
2752 /* Complement the condition since we use the reverse cond. for the insns. */
2753 cond = (GET_CODE (XEXP (XEXP (br_pat, 1), 0)) == EQ);
2755 /* Determine what kind of branch we have. */
2756 if (GET_CODE (XEXP (XEXP (br_pat, 1), 1)) == LABEL_REF)
2758 /* A normal branch, so extract label out of first arm. */
2759 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 1), 0));
2763 /* An inverse branch, so extract the label out of the 2nd arm
2764 and complement the condition. */
2766 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 2), 0));
2769 /* Scan forward for the start of block 2: it must start with a
2770 label and that label must be the same as the branch target
2771 label from block 1. We don't care about whether block 2 actually
2772 ends with a branch or a label (an uncond. branch is
2773 conditionalizable). */
2774 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
2778 code = GET_CODE (insn);
2780 /* Look for the label at the start of block 3. */
2781 if (code == CODE_LABEL && CODE_LABEL_NUMBER (insn) == br_lab_num)
2784 /* Skip barriers, notes, and conditionalizable insns. If the
2785 insn is not conditionalizable or makes this optimization fail,
2786 just return the next insn so we can start over from that point. */
2787 if (code != BARRIER && code != NOTE && !is_cond_candidate (insn))
2788 return NEXT_INSN (insn);
2790 /* Remember the last real insn before the label (ie end of block 2). */
2791 if (code == JUMP_INSN || code == INSN)
2794 end_blk_2_insn = insn;
2801 /* It is possible for this optimization to slow performance if the blocks
2802 are long. This really depends upon whether the branch is likely taken
2803 or not. If the branch is taken, we slow performance in many cases. But,
2804 if the branch is not taken, we always help performance (for a single
2805 block, but for a double block (i.e. when the optimization is re-applied)
2806 this is not true since the 'right thing' depends on the overall length of
2807 the collapsed block). As a compromise, don't apply this optimization on
2808 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2809 the best threshold depends on the latencies of the instructions (i.e.,
2810 the branch penalty). */
2811 if (optimize > 1 && blk_size > 2)
2814 /* At this point, we've found the start of block 3 and we know that
2815 it is the destination of the branch from block 1. Also, all
2816 instructions in the block 2 are conditionalizable. So, apply the
2817 conditionalization and delete the branch. */
2818 start_blk_3_lab = insn;
2820 for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab;
2821 insn = NEXT_INSN (insn))
2825 if (INSN_DELETED_P (insn))
2828 /* Try to form a conditional variant of the instruction and emit it. */
2829 if ((newinsn = emit_new_cond_insn (insn, cond)))
2831 if (end_blk_2_insn == insn)
2832 end_blk_2_insn = newinsn;
2838 /* Note whether we will delete the label starting blk 3 when the jump
2839 gets deleted. If so, we want to re-apply this optimization at the
2840 last real instruction right before the label. */
2841 if (LABEL_NUSES (start_blk_3_lab) == 1)
2843 start_blk_3_lab = 0;
2846 /* ??? we probably should redistribute the death notes for this insn, esp.
2847 the death of cc, but it doesn't really matter this late in the game.
2848 The peepholes all use is_dead() which will find the correct death
2849 regardless of whether there is a note. */
2850 delete_insn (end_blk_1_br);
2852 if (! start_blk_3_lab)
2853 return end_blk_2_insn;
2855 /* Return the insn right after the label at the start of block 3. */
2856 return NEXT_INSN (start_blk_3_lab);
2859 /* Apply the conditionalization of blocks optimization. This is the
2860 outer loop that traverses through the insns scanning for a branch
2861 that signifies an opportunity to apply the optimization. Note that
2862 this optimization is applied late. If we could apply it earlier,
2863 say before cse 2, it may expose more optimization opportunities.
2864 but, the pay back probably isn't really worth the effort (we'd have
2865 to update all reg/flow/notes/links/etc to make it work - and stick it
2866 in before cse 2). */
2869 conditionalize_optimization (void)
2873 for (insn = get_insns (); insn; insn = conditionalize_block (insn))
2877 static int saved_warn_return_type = -1;
2878 static int saved_warn_return_type_count = 0;
2880 /* This is to handle loads from the constant pool. */
2885 /* Reset this variable. */
2886 current_function_anonymous_args = 0;
2888 /* Restore the warn_return_type if it has been altered. */
2889 if (saved_warn_return_type != -1)
2891 /* Only restore the value if we have reached another function.
2892 The test of warn_return_type occurs in final_function () in
2893 c-decl.c a long time after the code for the function is generated,
2894 so we need a counter to tell us when we have finished parsing that
2895 function and can restore the flag. */
2896 if (--saved_warn_return_type_count == 0)
2898 warn_return_type = saved_warn_return_type;
2899 saved_warn_return_type = -1;
2906 /* Conditionalize blocks where we can. */
2907 conditionalize_optimization ();
2909 /* Literal pool generation is now pushed off until the assembler. */
2913 /* Return true if X is something that can be moved directly into r15. */
2916 mcore_r15_operand_p (rtx x)
2918 switch (GET_CODE (x))
2921 return mcore_const_ok_for_inline (INTVAL (x));
2933 /* Implement SECONDARY_RELOAD_CLASS. If CLASS contains r15, and we can't
2934 directly move X into it, use r1-r14 as a temporary. */
2937 mcore_secondary_reload_class (enum reg_class class,
2938 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2940 if (TEST_HARD_REG_BIT (reg_class_contents[class], 15)
2941 && !mcore_r15_operand_p (x))
2946 /* Return the reg_class to use when reloading the rtx X into the class
2947 CLASS. If X is too complex to move directly into r15, prefer to
2948 use LRW_REGS instead. */
2951 mcore_reload_class (rtx x, enum reg_class class)
2953 if (reg_class_subset_p (LRW_REGS, class) && !mcore_r15_operand_p (x))
2959 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2960 register. Note that the current version doesn't worry about whether
2961 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2962 in r2 matches an SImode in r2. Might think in the future about whether
2963 we want to be able to say something about modes. */
2966 mcore_is_same_reg (rtx x, rtx y)
2968 /* Strip any and all of the subreg wrappers. */
2969 while (GET_CODE (x) == SUBREG)
2972 while (GET_CODE (y) == SUBREG)
2975 if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y))
2982 mcore_override_options (void)
2984 if (mcore_stack_increment_string)
2986 mcore_stack_increment = atoi (mcore_stack_increment_string);
2988 if (mcore_stack_increment < 0
2989 || (mcore_stack_increment == 0
2990 && (mcore_stack_increment_string[0] != '0'
2991 || mcore_stack_increment_string[1] != 0)))
2992 error ("invalid option `-mstack-increment=%s'",
2993 mcore_stack_increment_string);
2996 /* Only the m340 supports little endian code. */
2997 if (TARGET_LITTLE_END && ! TARGET_M340)
2998 target_flags |= M340_BIT;
3002 mcore_must_pass_on_stack (enum machine_mode mode ATTRIBUTE_UNUSED, tree type)
3007 /* If the argument can have its address taken, it must
3008 be placed on the stack. */
3009 if (TREE_ADDRESSABLE (type))
3015 /* Compute the number of word sized registers needed to
3016 hold a function argument of mode MODE and type TYPE. */
3019 mcore_num_arg_regs (enum machine_mode mode, tree type)
3023 if (MUST_PASS_IN_STACK (mode, type))
3026 if (type && mode == BLKmode)
3027 size = int_size_in_bytes (type);
3029 size = GET_MODE_SIZE (mode);
3031 return ROUND_ADVANCE (size);
3035 handle_structs_in_regs (enum machine_mode mode, tree type, int reg)
3039 /* The MCore ABI defines that a structure whoes size is not a whole multiple
3040 of bytes is passed packed into registers (or spilled onto the stack if
3041 not enough registers are available) with the last few bytes of the
3042 structure being packed, left-justified, into the last register/stack slot.
3043 GCC handles this correctly if the last word is in a stack slot, but we
3044 have to generate a special, PARALLEL RTX if the last word is in an
3045 argument register. */
3047 && TYPE_MODE (type) == BLKmode
3048 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
3049 && (size = int_size_in_bytes (type)) > UNITS_PER_WORD
3050 && (size % UNITS_PER_WORD != 0)
3051 && (reg + mcore_num_arg_regs (mode, type) <= (FIRST_PARM_REG + NPARM_REGS)))
3053 rtx arg_regs [NPARM_REGS];
3058 for (nregs = 0; size > 0; size -= UNITS_PER_WORD)
3061 gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, reg ++),
3062 GEN_INT (nregs * UNITS_PER_WORD));
3066 /* We assume here that NPARM_REGS == 6. The assert checks this. */
3067 assert (ARRAY_SIZE (arg_regs) == 6);
3068 rtvec = gen_rtvec (nregs, arg_regs[0], arg_regs[1], arg_regs[2],
3069 arg_regs[3], arg_regs[4], arg_regs[5]);
3071 result = gen_rtx_PARALLEL (mode, rtvec);
3075 return gen_rtx_REG (mode, reg);
3079 mcore_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
3081 enum machine_mode mode;
3084 mode = TYPE_MODE (valtype);
3086 PROMOTE_MODE (mode, unsigned_p, NULL);
3088 return handle_structs_in_regs (mode, valtype, FIRST_RET_REG);
3091 /* Define where to put the arguments to a function.
3092 Value is zero to push the argument on the stack,
3093 or a hard register in which to store the argument.
3095 MODE is the argument's machine mode.
3096 TYPE is the data type of the argument (as a tree).
3097 This is null for libcalls where that information may
3099 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3100 the preceding args and about the function being called.
3101 NAMED is nonzero if this argument is a named parameter
3102 (otherwise it is an extra parameter matching an ellipsis).
3104 On MCore the first args are normally in registers
3105 and the rest are pushed. Any arg that starts within the first
3106 NPARM_REGS words is at least partially passed in a register unless
3107 its data type forbids. */
3110 mcore_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode,
3111 tree type, int named)
3118 if (MUST_PASS_IN_STACK (mode, type))
3121 arg_reg = ROUND_REG (cum, mode);
3123 if (arg_reg < NPARM_REGS)
3124 return handle_structs_in_regs (mode, type, FIRST_PARM_REG + arg_reg);
3129 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
3130 Returns the number of argument registers required to hold *part* of
3131 a parameter of machine mode MODE and type TYPE (which may be NULL if
3132 the type is not known). If the argument fits entirely in the argument
3133 registers, or entirely on the stack, then 0 is returned. CUM is the
3134 number of argument registers already used by earlier parameters to
3138 mcore_function_arg_partial_nregs (CUMULATIVE_ARGS cum, enum machine_mode mode,
3139 tree type, int named)
3141 int reg = ROUND_REG (cum, mode);
3146 if (MUST_PASS_IN_STACK (mode, type))
3149 /* REG is not the *hardware* register number of the register that holds
3150 the argument, it is the *argument* register number. So for example,
3151 the first argument to a function goes in argument register 0, which
3152 translates (for the MCore) into hardware register 2. The second
3153 argument goes into argument register 1, which translates into hardware
3154 register 3, and so on. NPARM_REGS is the number of argument registers
3155 supported by the target, not the maximum hardware register number of
3157 if (reg >= NPARM_REGS)
3160 /* If the argument fits entirely in registers, return 0. */
3161 if (reg + mcore_num_arg_regs (mode, type) <= NPARM_REGS)
3164 /* The argument overflows the number of available argument registers.
3165 Compute how many argument registers have not yet been assigned to
3166 hold an argument. */
3167 reg = NPARM_REGS - reg;
3169 /* Return partially in registers and partially on the stack. */
3173 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
3176 mcore_dllexport_name_p (const char * symbol)
3178 return symbol[0] == '@' && symbol[1] == 'e' && symbol[2] == '.';
3181 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
3184 mcore_dllimport_name_p (const char * symbol)
3186 return symbol[0] == '@' && symbol[1] == 'i' && symbol[2] == '.';
3189 /* Mark a DECL as being dllexport'd. */
3192 mcore_mark_dllexport (tree decl)
3194 const char * oldname;
3199 rtlname = XEXP (DECL_RTL (decl), 0);
3201 if (GET_CODE (rtlname) == SYMBOL_REF)
3202 oldname = XSTR (rtlname, 0);
3203 else if ( GET_CODE (rtlname) == MEM
3204 && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
3205 oldname = XSTR (XEXP (rtlname, 0), 0);
3209 if (mcore_dllexport_name_p (oldname))
3210 return; /* Already done. */
3212 newname = alloca (strlen (oldname) + 4);
3213 sprintf (newname, "@e.%s", oldname);
3215 /* We pass newname through get_identifier to ensure it has a unique
3216 address. RTL processing can sometimes peek inside the symbol ref
3217 and compare the string's addresses to see if two symbols are
3219 /* ??? At least I think that's why we do this. */
3220 idp = get_identifier (newname);
3222 XEXP (DECL_RTL (decl), 0) =
3223 gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
3226 /* Mark a DECL as being dllimport'd. */
3229 mcore_mark_dllimport (tree decl)
3231 const char * oldname;
3237 rtlname = XEXP (DECL_RTL (decl), 0);
3239 if (GET_CODE (rtlname) == SYMBOL_REF)
3240 oldname = XSTR (rtlname, 0);
3241 else if ( GET_CODE (rtlname) == MEM
3242 && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
3243 oldname = XSTR (XEXP (rtlname, 0), 0);
3247 if (mcore_dllexport_name_p (oldname))
3248 abort (); /* This shouldn't happen. */
3249 else if (mcore_dllimport_name_p (oldname))
3250 return; /* Already done. */
3252 /* ??? One can well ask why we're making these checks here,
3253 and that would be a good question. */
3255 /* Imported variables can't be initialized. */
3256 if (TREE_CODE (decl) == VAR_DECL
3257 && !DECL_VIRTUAL_P (decl)
3258 && DECL_INITIAL (decl))
3260 error ("%Jinitialized variable '%D' is marked dllimport", decl, decl);
3264 /* `extern' needn't be specified with dllimport.
3265 Specify `extern' now and hope for the best. Sigh. */
3266 if (TREE_CODE (decl) == VAR_DECL
3267 /* ??? Is this test for vtables needed? */
3268 && !DECL_VIRTUAL_P (decl))
3270 DECL_EXTERNAL (decl) = 1;
3271 TREE_PUBLIC (decl) = 1;
3274 newname = alloca (strlen (oldname) + 11);
3275 sprintf (newname, "@i.__imp_%s", oldname);
3277 /* We pass newname through get_identifier to ensure it has a unique
3278 address. RTL processing can sometimes peek inside the symbol ref
3279 and compare the string's addresses to see if two symbols are
3281 /* ??? At least I think that's why we do this. */
3282 idp = get_identifier (newname);
3284 newrtl = gen_rtx_MEM (Pmode,
3285 gen_rtx_SYMBOL_REF (Pmode,
3286 IDENTIFIER_POINTER (idp)));
3287 XEXP (DECL_RTL (decl), 0) = newrtl;
3291 mcore_dllexport_p (tree decl)
3293 if ( TREE_CODE (decl) != VAR_DECL
3294 && TREE_CODE (decl) != FUNCTION_DECL)
3297 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)) != 0;
3301 mcore_dllimport_p (tree decl)
3303 if ( TREE_CODE (decl) != VAR_DECL
3304 && TREE_CODE (decl) != FUNCTION_DECL)
3307 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl)) != 0;
3310 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3311 install some info in the .drective (PE) or .exports (ELF) sections. */
3314 mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIBUTE_UNUSED)
3316 /* Mark the decl so we can tell from the rtl whether the object is
3317 dllexport'd or dllimport'd. */
3318 if (mcore_dllexport_p (decl))
3319 mcore_mark_dllexport (decl);
3320 else if (mcore_dllimport_p (decl))
3321 mcore_mark_dllimport (decl);
3323 /* It might be that DECL has already been marked as dllimport, but
3324 a subsequent definition nullified that. The attribute is gone
3325 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3326 else if ((TREE_CODE (decl) == FUNCTION_DECL
3327 || TREE_CODE (decl) == VAR_DECL)
3328 && DECL_RTL (decl) != NULL_RTX
3329 && GET_CODE (DECL_RTL (decl)) == MEM
3330 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM
3331 && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
3332 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
3334 const char * oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0);
3335 tree idp = get_identifier (oldname + 9);
3336 rtx newrtl = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
3338 XEXP (DECL_RTL (decl), 0) = newrtl;
3340 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3341 ??? We leave these alone for now. */
3345 /* Undo the effects of the above. */
3348 mcore_strip_name_encoding (const char * str)
3350 return str + (str[0] == '@' ? 3 : 0);
3353 /* MCore specific attribute support.
3354 dllexport - for exporting a function/variable that will live in a dll
3355 dllimport - for importing a function/variable from a dll
3356 naked - do not create a function prologue/epilogue. */
3358 const struct attribute_spec mcore_attribute_table[] =
3360 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3361 { "dllexport", 0, 0, true, false, false, NULL },
3362 { "dllimport", 0, 0, true, false, false, NULL },
3363 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute },
3364 { NULL, 0, 0, false, false, false, NULL }
3367 /* Handle a "naked" attribute; arguments as in
3368 struct attribute_spec.handler. */
3371 mcore_handle_naked_attribute (tree * node, tree name, tree args ATTRIBUTE_UNUSED,
3372 int flags ATTRIBUTE_UNUSED, bool * no_add_attrs)
3374 if (TREE_CODE (*node) == FUNCTION_DECL)
3376 /* PR14310 - don't complain about lack of return statement
3377 in naked functions. The solution here is a gross hack
3378 but this is the only way to solve the problem without
3379 adding a new feature to GCC. I did try submitting a patch
3380 that would add such a new feature, but it was (rightfully)
3381 rejected on the grounds that it was creeping featurism,
3382 so hence this code. */
3383 if (warn_return_type)
3385 saved_warn_return_type = warn_return_type;
3386 warn_return_type = 0;
3387 saved_warn_return_type_count = 2;
3389 else if (saved_warn_return_type_count)
3390 saved_warn_return_type_count = 2;
3394 warning ("`%s' attribute only applies to functions",
3395 IDENTIFIER_POINTER (name));
3396 *no_add_attrs = true;
3402 /* ??? It looks like this is PE specific? Oh well, this is what the
3403 old code did as well. */
3406 mcore_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
3411 const char * prefix;
3413 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3415 /* Strip off any encoding in name. */
3416 name = (* targetm.strip_name_encoding) (name);
3418 /* The object is put in, for example, section .text$foo.
3419 The linker will then ultimately place them in .text
3420 (everything from the $ on is stripped). */
3421 if (TREE_CODE (decl) == FUNCTION_DECL)
3423 /* For compatibility with EPOC, we ignore the fact that the
3424 section might have relocs against it. */
3425 else if (decl_readonly_section (decl, 0))
3430 len = strlen (name) + strlen (prefix);
3431 string = alloca (len + 1);
3433 sprintf (string, "%s%s", prefix, name);
3435 DECL_SECTION_NAME (decl) = build_string (len, string);
3439 mcore_naked_function_p (void)
3441 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE;
3444 #ifdef OBJECT_FORMAT_ELF
3446 mcore_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
3448 fprintf (asm_out_file, "\t.section %s\n", name);
3450 #endif /* OBJECT_FORMAT_ELF */
3452 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3455 mcore_external_libcall (rtx fun)
3457 fprintf (asm_out_file, "\t.import\t");
3458 assemble_name (asm_out_file, XSTR (fun, 0));
3459 fprintf (asm_out_file, "\n");
3462 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3465 mcore_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3467 HOST_WIDE_INT size = int_size_in_bytes (type);
3468 return (size == -1 || size > 2 * UNITS_PER_WORD);