gcc/config/m68k/sync.md

   1 ;; GCC machine description for m68k synchronization instructions.
   2 ;; Copyright (C) 2011, 2012
   3 ;; Free Software Foundation, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21
  22 (define_expand "atomic_compare_and_swap<mode>"
  23   [(match_operand:QI 0 "register_operand" "")           ;; bool success output
  24    (match_operand:I 1 "register_operand" "")            ;; oldval output
  25    (match_operand:I 2 "memory_operand" "")              ;; memory
  26    (match_operand:I 3 "register_operand" "")            ;; expected input
  27    (match_operand:I 4 "register_operand" "")            ;; newval input
  28    (match_operand:SI 5 "const_int_operand" "")          ;; is_weak
  29    (match_operand:SI 6 "const_int_operand" "")          ;; success model
  30    (match_operand:SI 7 "const_int_operand" "")]         ;; failure model
  31   "TARGET_CAS"
  32 {
  33   emit_insn (gen_atomic_compare_and_swap<mode>_1
  34              (operands[0], operands[1], operands[2],
  35               operands[3], operands[4]));
  36   emit_insn (gen_negqi2 (operands[0], operands[0]));
  37   DONE;
  38 })
  39
  40 (define_insn "atomic_compare_and_swap<mode>_1"
  41   [(set (match_operand:I 1 "register_operand" "=d")
  42         (unspec_volatile:I
  43           [(match_operand:I 2 "memory_operand" "+m")
  44            (match_operand:I 3 "register_operand" "1")
  45            (match_operand:I 4 "register_operand" "d")]
  46           UNSPECV_CAS_1))
  47    (set (match_dup 2)
  48         (unspec_volatile:I
  49           [(match_dup 2) (match_dup 3) (match_dup 4)]
  50           UNSPECV_CAS_2))
  51    (set (match_operand:QI 0 "register_operand" "=d")
  52         (unspec_volatile:QI
  53           [(match_dup 2) (match_dup 3) (match_dup 4)]
  54           UNSPECV_CAS_2))]
  55   "TARGET_CAS"
  56   ;; Elide the seq if operands[0] is dead.
  57   "cas<sz> %1,%4,%2\;seq %0")
  58
  59 (define_expand "sync_test_and_setqi"
  60   [(match_operand:QI 0 "register_operand" "")
  61    (match_operand:QI 1 "memory_operand" "")
  62    (match_operand:QI 2 "general_operand" "")]
  63   "!TARGET_CAS"
  64 {
  65   if (operands[2] != const1_rtx)
  66     FAIL;
  67   emit_insn (gen_sync_test_and_setqi_1 (operands[0], operands[1]));
  68   emit_insn (gen_negqi2 (operands[0], operands[0]));
  69   DONE;
  70 })
  71
  72 (define_insn "sync_test_and_setqi_1"
  73   [(set (match_operand:QI 0 "register_operand" "=d")
  74         (unspec_volatile:QI
  75           [(match_operand:QI 1 "memory_operand" "+m")]
  76           UNSPECV_TAS_1))
  77    (set (match_dup 1)
  78         (unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))]
  79   "!TARGET_CAS"
  80   "tas %1\;sne %0")