1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_5200 flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
50 ;;- 'x' if one of the Sun FPA registers
51 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
53 ;;- Immediate Floating point operator constraints
54 ;;- 'G' a floating point constant that is *NOT* one of the standard
55 ;; 68881 constant values (to force calling output_move_const_double
56 ;; to get it from rom if it is a 68881 constant).
57 ;;- 'H' one of the standard FPA constant values
59 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
62 ;;- Immediate integer operand constraints:
64 ;;- 'J' -32768 .. 32767
65 ;;- 'K' all integers EXCEPT -128 .. 127
67 ;;- 'M' all integers EXCEPT -256 .. 255
73 ;;- "%." size separator ("." or "") move%.l d0,d1
74 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
75 ;;- "%-" push operand "sp@-" move%.l d0,%-
76 ;;- "%+" pop operand "sp@+" move%.l d0,%+
77 ;;- "%@" top of stack "sp@" move%.l d0,%@
78 ;;- "%!" fpcr register
79 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
80 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
83 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
84 ;; operand 1 is the argument for `sin'.
85 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
86 ;; operand 1 is the argument for `cos'.
88 ;;- Information about 68040 port.
90 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
91 ;;- be emulated in software by the OS. It is faster to avoid these
92 ;;- instructions and issue a library call rather than trapping into
93 ;;- the kernel. The affected instructions are fintrz and fscale. The
94 ;;- TARGET_68040 flag turns the use of the opcodes off.
96 ;;- The '040 also implements a set of new floating-point instructions
97 ;;- which specify the rounding precision in the opcode. This finally
98 ;;- permit the 68k series to be truly IEEE compliant, and solves all
99 ;;- issues of excess precision accumulating in the extended registers.
100 ;;- By default, GCC does not use these instructions, since such code will
101 ;;- not run on an '030. To use these instructions, use the -m68040-only
102 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
103 ;;- you can make these instructions the default.
105 ;;- These new instructions aren't directly in the md. They are brought
106 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
109 ;;- Information about 68060 port.
111 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
112 ;;- be emulated in software by the OS. It is faster to avoid these
113 ;;- instructions and issue a library call rather than trapping into
114 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
115 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
116 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
118 ;;- FPA port explanation:
120 ;;- Usage of the Sun FPA and the 68881 together
122 ;;- The current port of gcc to the sun fpa disallows use of the m68881
123 ;;- instructions completely if code is targeted for the fpa. This is
124 ;;- for the following reasons:
126 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
127 ;;- can, the 68881 otherwise, and data registers only if you are
128 ;;- forced to it) is a bitch with the current constraint scheme,
129 ;;- especially since it would have to work for any combination of
132 ;;- 2) There are no instructions to move between the two types of
133 ;;- registers; the stack must be used as an intermediary.
135 ;;- It could indeed be done; I think the best way would be to have
136 ;;- separate patterns for TARGET_FPA (which implies a 68881),
137 ;;- TARGET_68881, and no floating point co-processor. Use
138 ;;- define_expands for all of the named instruction patterns, and
139 ;;- include code in the FPA instruction to deal with the 68881 with
140 ;;- preferences specifically set to favor the fpa. Some of this has
141 ;;- already been done:
143 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
144 ;;- case and a TARGET_68881 case (the exceptions are the patterns
145 ;;- which would need one define_expand and three define_insn's under
146 ;;- it (with a lot of duplicate code between them) to replace the
147 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
148 ;;- first two patterns in the md.
150 ;;- Some would still have to be done:
152 ;;- 1) Add code to the fpa patterns which correspond to 68881
153 ;;- patterns to deal with the 68881 case (including preferences!).
154 ;;- What you might actually do here is combine the fpa and 68881 code
155 ;;- back together into one pattern for those instructions where it's
156 ;;- absolutely necessary and save yourself some duplicate code. I'm
157 ;;- not completely sure as to whether you could get away with doing
158 ;;- this only for the mov* insns, or if you'd have to do it for all
160 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
161 ;;- moving between fpa regs and 68881 regs.
163 ;;- Since the fpa is more powerful than the 68881 and also has more
164 ;;- registers, and since I think the resultant md would be medium ugly
165 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
166 ;;- to do this change.
168 ;;- Another reason why someone *might* want to do the change is to
169 ;;- control which register classes are accessed in a slightly cleaner
170 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
171 ;;- the internals manual.
173 ;;- Yet another reason why someone might want to do this change is to
174 ;;- allow use of some of the 68881 insns which have no equivalent on
175 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
177 ;;- If this is ever done, don't forget to change sun3.h so that
178 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
180 ;;- Condition code hack
182 ;;- When a floating point compare is done in the fpa, the resulting
183 ;;- condition codes are left in the fpastatus register. The values in
184 ;;- this register must be moved into the 68000 cc register before any
185 ;;- jump is executed. Once this has been done, regular jump
186 ;;- instructions are fine (ie. floating point jumps are not necessary.
187 ;;- They are only done if the cc is in the 68881).
189 ;;- The instructions that move the fpastatus register to the 68000
190 ;;- register clobber a data register (the move cannot be done direct).
191 ;;- These instructions might be bundled either with the compare
192 ;;- instruction, or the branch instruction. If we were using both the
193 ;;- fpa and the 68881 together, we would wish to only mark the
194 ;;- register clobbered if we were doing the compare in the fpa, but I
195 ;;- think that that decision (whether to clobber the register or not)
196 ;;- must be done before register allocation (makes sense) and hence we
197 ;;- can't know if the floating point compare will be done in the fpa
198 ;;- or the fp. So whenever we are asked for code that uses the fpa,
199 ;;- we will mark a data register as clobbered. This is reasonable, as
200 ;;- almost all floating point compare operations done with fpa code
201 ;;- enabled will be done in the fpa. It's even more reasonable since
202 ;;- we decided to make the 68881 and the fpa mutually exclusive.
204 ;;- We place to code to move the fpastatus register inside of a
205 ;;- define_expand so that we can do it conditionally based on whether
206 ;;- we are targeting an fpa or not.
208 ;;- This still leaves us with the question of where we wish to put the
209 ;;- code to move the fpastatus reg. If we put it in the compare
210 ;;- instruction, we can restrict the clobbering of the register to
211 ;;- floating point compares, but we can't take advantage of floating
212 ;;- point subtracts & etc. that alter the fpastatus register. If we
213 ;;- put it in the branch instruction, all branches compiled with fpa
214 ;;- code enabled will clobber a data register, but we will be able to
215 ;;- take advantage of fpa subtracts. This balance favors putting the
216 ;;- code in with the compare instruction.
218 ;;- Note that if some enterprising hacker should decide to switch
219 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
221 ;;- Usage of the top 16 fpa registers
223 ;;- The only locations which we may transfer fpa registers 16-31 from
224 ;;- or to are the fpa registers 0-15. (68000 registers and memory
225 ;;- locations are impossible). This causes problems in gcc, which
226 ;;- assumes that mov?? instructions require no additional registers
227 ;;- (see section 11.7) and since floating point moves *must* be
228 ;;- supported into general registers (see section 12.3 under
229 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
231 ;;- My solution was to reserve fpa0 for moves into or out of these top
232 ;;- 16 registers and to disparage the choice to reload into or out of
233 ;;- these registers as much as I could. That alternative is always
234 ;;- last in the list, so it will not be used unless all else fails. I
235 ;;- will note that according to my current information, sun's compiler
236 ;;- doesn't use these top 16 registers at all.
238 ;;- There is another possible way to do it. I *believe* that if you
239 ;;- make absolutely sure that the code will not be executed in the
240 ;;- reload pass, you can support the mov?? names with define_expands
241 ;;- which require new registers. This may be possible by the
242 ;;- appropriate juggling of constraints. I may come back to this later.
244 ;;- Usage of constant RAM
246 ;;- This has been handled correctly (I believe) but the way I've done
247 ;;- it could use a little explanation. The constant RAM can only be
248 ;;- accessed when the instruction is in "command register" mode.
249 ;;- "command register" mode means that no accessing of memory or the
250 ;;- 68000 registers is being done. This can be expressed easily in
251 ;;- constraints, so generally the mode of the instruction is
252 ;;- determined by a branch off of which_alternative. In outputting
253 ;;- instructions, a 'w' means to output an access to the constant ram
254 ;;- (if the arg is CONST_DOUBLE and is one of the available
255 ;;- constants), and 'x' means to output a register pair (if the arg is
256 ;;- a 68000 register) and a 'y' is the combination of the above two
257 ;;- processes. You use a 'y' in two operand DF instructions where you
258 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
259 ;;- instructions where the arg might be a 68000 register and the
260 ;;- instruction is *not* in "command register" mode, and you use a 'w'
261 ;;- in two situations: 1) The instruction *is* in command register
262 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
263 ;;- instruction is a two operand SF instruction where you know the
264 ;;- other operand is an fpa register.
266 ;;- Optimization issues
268 ;;- I actually think that I've included all of the fpa instructions
269 ;;- that should be included. Note that if someone is interested in
270 ;;- doing serious floating point work on the sun fpa, I would advise
271 ;;- the use of the "asm" instruction in gcc to allow you to use the
272 ;;- sin, cos, and exponential functions on the fpa board.
274 ;;- END FPA Explanation Section.
277 ;;- Some of these insn's are composites of several m68000 op codes.
278 ;;- The assembler (or final @@??) insures that the appropriate one is
282 [(set (match_operand:DF 0 "push_operand" "=m")
283 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
287 if (FP_REG_P (operands[1]))
288 return \"fmove%.d %f1,%0\";
289 if (FPA_REG_P (operands[1]))
290 return \"fpmove%.d %1, %x0\";
291 return output_move_double (operands);
294 (define_insn "pushdi"
295 [(set (match_operand:DI 0 "push_operand" "=m")
296 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
300 return output_move_double (operands);
303 ;; We don't want to allow a constant operand for test insns because
304 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
305 ;; be folded while optimizing anyway.
307 (define_expand "tstdi"
308 [(parallel [(set (cc0)
309 (match_operand:DI 0 "nonimmediate_operand" ""))
310 (clobber (match_scratch:SI 1 ""))
311 (clobber (match_scratch:DI 2 ""))])]
313 "m68k_last_compare_had_fp_operands = 0;")
317 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
318 (clobber (match_scratch:SI 1 "=X,d"))
319 (clobber (match_scratch:DI 2 "=d,X"))]
323 if (which_alternative == 0)
327 xoperands[0] = operands[2];
328 xoperands[1] = operands[0];
329 output_move_double (xoperands);
330 cc_status.flags |= CC_REVERSED;
331 return \"neg%.l %R2\;negx%.l %2\";
333 if (find_reg_note (insn, REG_DEAD, operands[0]))
335 cc_status.flags |= CC_REVERSED;
336 return \"neg%.l %R0\;negx%.l %0\";
340 ** 'sub' clears %1, and also clears the X cc bit
341 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
342 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
344 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
347 (define_expand "tstsi"
349 (match_operand:SI 0 "nonimmediate_operand" ""))]
351 "m68k_last_compare_had_fp_operands = 0;")
355 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
360 /* ISI's assembler fails to handle tstl a0. */
361 if (! ADDRESS_REG_P (operands[0]))
363 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
365 return \"tst%.l %0\";
366 /* If you think that the 68020 does not support tstl a0,
367 reread page B-167 of the 68020 manual more carefully. */
368 /* On an address reg, cmpw may replace cmpl. */
370 return \"cmp%.w %0,%#0\";
372 return \"cmp%.w %#0,%0\";
376 ;; This can't use an address register, because comparisons
377 ;; with address registers as second operand always test the whole word.
378 (define_expand "tsthi"
380 (match_operand:HI 0 "nonimmediate_operand" ""))]
382 "m68k_last_compare_had_fp_operands = 0;")
386 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
390 (define_expand "tstqi"
392 (match_operand:QI 0 "nonimmediate_operand" ""))]
394 "m68k_last_compare_had_fp_operands = 0;")
398 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
402 (define_expand "tstsf"
404 (match_operand:SF 0 "general_operand" ""))]
405 "TARGET_68881 || TARGET_FPA"
408 m68k_last_compare_had_fp_operands = 1;
411 emit_insn (gen_tstsf_fpa (operands[0]));
416 (define_insn "tstsf_fpa"
418 (match_operand:SF 0 "general_operand" "xmdF"))
419 (clobber (match_scratch:SI 1 "=d"))]
421 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
425 (match_operand:SF 0 "general_operand" "fdm"))]
429 cc_status.flags = CC_IN_68881;
430 if (FP_REG_P (operands[0]))
431 return \"ftst%.x %0\";
432 return \"ftst%.s %0\";
435 (define_expand "tstdf"
437 (match_operand:DF 0 "general_operand" ""))]
438 "TARGET_68881 || TARGET_FPA"
441 m68k_last_compare_had_fp_operands = 1;
444 emit_insn (gen_tstsf_fpa (operands[0]));
449 (define_insn "tstdf_fpa"
451 (match_operand:DF 0 "general_operand" "xrmF"))
452 (clobber (match_scratch:SI 1 "=d"))]
454 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
458 (match_operand:DF 0 "general_operand" "fm"))]
462 cc_status.flags = CC_IN_68881;
463 if (FP_REG_P (operands[0]))
464 return \"ftst%.x %0\";
465 return \"ftst%.d %0\";
468 ;; compare instructions.
470 (define_expand "cmpdi"
473 (compare (match_operand:DI 0 "nonimmediate_operand" "")
474 (match_operand:DI 1 "general_operand" "")))
475 (clobber (match_dup 2))])]
477 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
481 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
482 (match_operand:DI 2 "general_operand" "d,0")))
483 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
487 if (rtx_equal_p (operands[0], operands[1]))
488 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
491 cc_status.flags |= CC_REVERSED;
492 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
496 ;; This is the second "hook" for PIC code (in addition to movsi). See
497 ;; comment of movsi for a description of PIC handling.
498 (define_expand "cmpsi"
500 (compare (match_operand:SI 0 "nonimmediate_operand" "")
501 (match_operand:SI 1 "general_operand" "")))]
505 m68k_last_compare_had_fp_operands = 0;
506 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
508 /* The source is an address which requires PIC relocation.
509 Call legitimize_pic_address with the source, mode, and a relocation
510 register (a new pseudo, or the final destination if reload_in_progress
511 is set). Then fall through normally */
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
521 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
540 if (ADDRESS_REG_P (operands[0])
541 && GET_CODE (operands[1]) == CONST_INT
542 && INTVAL (operands[1]) < 0x8000
543 && INTVAL (operands[1]) >= -0x8000)
546 return \"cmp%.w %0,%1\";
548 return \"cmp%.w %1,%0\";
552 return \"cmp%.l %d0,%d1\";
554 return \"cmp%.l %d1,%d0\";
560 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
561 (match_operand:SI 1 "general_operand" "r,mrKs")))]
565 if (REG_P (operands[1])
566 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
567 { cc_status.flags |= CC_REVERSED;
569 return \"cmp%.l %d1,%d0\";
571 return \"cmp%.l %d0,%d1\";
575 return \"cmp%.l %d0,%d1\";
577 return \"cmp%.l %d1,%d0\";
581 (define_expand "cmphi"
583 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
584 (match_operand:HI 1 "general_src_operand" "")))]
586 "m68k_last_compare_had_fp_operands = 0;")
590 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
591 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
595 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
597 return \"cmpm%.w %0,%1\";
599 return \"cmpm%.w %1,%0\";
601 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
602 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
603 { cc_status.flags |= CC_REVERSED;
605 return \"cmp%.w %d1,%d0\";
607 return \"cmp%.w %d0,%d1\";
611 return \"cmp%.w %d0,%d1\";
613 return \"cmp%.w %d1,%d0\";
617 (define_expand "cmpqi"
619 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
620 (match_operand:QI 1 "general_src_operand" "")))]
622 "m68k_last_compare_had_fp_operands = 0;")
626 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
627 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
631 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
633 return \"cmpm%.b %0,%1\";
635 return \"cmpm%.b %1,%0\";
637 if (REG_P (operands[1])
638 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
639 { cc_status.flags |= CC_REVERSED;
641 return \"cmp%.b %d1,%d0\";
643 return \"cmp%.b %d0,%d1\";
647 return \"cmp%.b %d0,%d1\";
649 return \"cmp%.b %d1,%d0\";
653 (define_expand "cmpdf"
655 (compare (match_operand:DF 0 "general_operand" "")
656 (match_operand:DF 1 "general_operand" "")))]
657 "TARGET_68881 || TARGET_FPA"
660 m68k_last_compare_had_fp_operands = 1;
663 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
668 (define_insn "cmpdf_fpa"
670 (compare (match_operand:DF 0 "general_operand" "x,y")
671 (match_operand:DF 1 "general_operand" "xH,rmF")))
672 (clobber (match_scratch:SI 2 "=d,d"))]
674 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
678 (compare (match_operand:DF 0 "general_operand" "f,mG")
679 (match_operand:DF 1 "general_operand" "fmG,f")))]
683 cc_status.flags = CC_IN_68881;
685 if (REG_P (operands[0]))
687 if (REG_P (operands[1]))
688 return \"fcmp%.x %0,%1\";
690 return \"fcmp%.d %0,%f1\";
692 cc_status.flags |= CC_REVERSED;
693 return \"fcmp%.d %1,%f0\";
695 if (REG_P (operands[0]))
697 if (REG_P (operands[1]))
698 return \"fcmp%.x %1,%0\";
700 return \"fcmp%.d %f1,%0\";
702 cc_status.flags |= CC_REVERSED;
703 return \"fcmp%.d %f0,%1\";
707 (define_expand "cmpsf"
709 (compare (match_operand:SF 0 "general_operand" "")
710 (match_operand:SF 1 "general_operand" "")))]
711 "TARGET_68881 || TARGET_FPA"
714 m68k_last_compare_had_fp_operands = 1;
717 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
722 (define_insn "cmpsf_fpa"
724 (compare (match_operand:SF 0 "general_operand" "x,y")
725 (match_operand:SF 1 "general_operand" "xH,rmF")))
726 (clobber (match_scratch:SI 2 "=d,d"))]
728 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
732 (compare (match_operand:SF 0 "general_operand" "f,mdG")
733 (match_operand:SF 1 "general_operand" "fmdG,f")))]
737 cc_status.flags = CC_IN_68881;
739 if (FP_REG_P (operands[0]))
741 if (FP_REG_P (operands[1]))
742 return \"fcmp%.x %0,%1\";
744 return \"fcmp%.s %0,%f1\";
746 cc_status.flags |= CC_REVERSED;
747 return \"fcmp%.s %1,%f0\";
749 if (FP_REG_P (operands[0]))
751 if (FP_REG_P (operands[1]))
752 return \"fcmp%.x %1,%0\";
754 return \"fcmp%.s %f1,%0\";
756 cc_status.flags |= CC_REVERSED;
757 return \"fcmp%.s %f0,%1\";
761 ;; Recognizers for btst instructions.
763 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
764 ;; specified as a constant, so we must disable all patterns that may extract
765 ;; from a MEM at a constant bit position if we can't use this as a constraint.
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "di"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
775 ;; This is the same as the above pattern except for the constraints. The 'i'
779 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
781 (minus:SI (const_int 7)
782 (match_operand:SI 1 "general_operand" "d"))))]
784 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
787 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
789 (minus:SI (const_int 31)
790 (match_operand:SI 1 "general_operand" "di"))))]
792 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
794 ;; The following two patterns are like the previous two
795 ;; except that they use the fact that bit-number operands
796 ;; are automatically masked to 3 or 5 bits.
799 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
801 (minus:SI (const_int 7)
803 (match_operand:SI 1 "register_operand" "d")
806 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
809 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
811 (minus:SI (const_int 31)
813 (match_operand:SI 1 "register_operand" "d")
816 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
818 ;; Nonoffsettable mem refs are ok in this one pattern
819 ;; since we don't try to adjust them.
821 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
823 (match_operand:SI 1 "const_int_operand" "n")))]
824 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
827 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
828 return output_btst (operands, operands[1], operands[0], insn, 7);
832 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
834 (match_operand:SI 1 "const_int_operand" "n")))]
838 if (GET_CODE (operands[0]) == MEM)
840 operands[0] = adj_offsettable_operand (operands[0],
841 INTVAL (operands[1]) / 8);
842 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
843 return output_btst (operands, operands[1], operands[0], insn, 7);
845 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
846 return output_btst (operands, operands[1], operands[0], insn, 31);
849 ;; This is the same as the above pattern except for the constraints.
850 ;; The 'o' has been replaced with 'Q'.
853 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
855 (match_operand:SI 1 "const_int_operand" "n")))]
859 if (GET_CODE (operands[0]) == MEM)
861 operands[0] = adj_offsettable_operand (operands[0],
862 INTVAL (operands[1]) / 8);
863 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
864 return output_btst (operands, operands[1], operands[0], insn, 7);
866 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
867 return output_btst (operands, operands[1], operands[0], insn, 31);
873 ;; A special case in which it is not desirable
874 ;; to reload the constant into a data register.
875 (define_insn "pushexthisi_const"
876 [(set (match_operand:SI 0 "push_operand" "=m")
877 (match_operand:SI 1 "const_int_operand" "J"))]
878 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
881 if (operands[1] == const0_rtx)
882 return \"clr%.l %0\";
887 ;(define_insn "swapsi"
888 ; [(set (match_operand:SI 0 "general_operand" "+r")
889 ; (match_operand:SI 1 "general_operand" "+r"))
890 ; (set (match_dup 1) (match_dup 0))]
894 ;; Special case of fullword move when source is zero.
895 ;; The reason this is special is to avoid loading a zero
896 ;; into a data reg with moveq in order to store it elsewhere.
898 (define_insn "movsi_const0"
899 [(set (match_operand:SI 0 "general_operand" "=g")
901 ;; clr insns on 68000 read before writing.
902 ;; This isn't so on the 68010, but we have no TARGET_68010.
903 "((TARGET_68020 || TARGET_5200)
904 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
907 if (ADDRESS_REG_P (operands[0]))
909 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
910 if (!TARGET_68040 && !TARGET_68060)
911 return \"sub%.l %0,%0\";
916 /* Many SGS assemblers croak on size specifiers for constants. */
919 return \"lea 0.w,%0\";
922 return \"lea 0:w,%0\";
926 /* moveq is faster on the 68000. */
927 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
928 #if defined(MOTOROLA) && !defined(CRDS)
929 return \"moveq%.l %#0,%0\";
931 return \"moveq %#0,%0\";
933 return \"clr%.l %0\";
936 ;; General case of fullword move.
938 ;; This is the main "hook" for PIC code. When generating
939 ;; PIC, movsi is responsible for determining when the source address
940 ;; needs PIC relocation and appropriately calling legitimize_pic_address
941 ;; to perform the actual relocation.
943 ;; In both the PIC and non-PIC cases the patterns generated will
944 ;; matched by the next define_insn.
945 (define_expand "movsi"
946 [(set (match_operand:SI 0 "general_operand" "")
947 (match_operand:SI 1 "general_operand" ""))]
951 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
953 /* The source is an address which requires PIC relocation.
954 Call legitimize_pic_address with the source, mode, and a relocation
955 register (a new pseudo, or the final destination if reload_in_progress
956 is set). Then fall through normally */
957 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
958 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
960 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
962 /* Don't allow writes to memory except via a register;
963 the m68k doesn't consider PC-relative addresses to be writable. */
964 if (symbolic_operand (operands[0], SImode))
965 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
966 else if (GET_CODE (operands[0]) == MEM
967 && symbolic_operand (XEXP (operands[0], 0), SImode))
968 operands[0] = gen_rtx (MEM, SImode,
969 force_reg (SImode, XEXP (operands[0], 0)));
973 ;; General case of fullword move. The register constraints
974 ;; force integer constants in range for a moveq to be reloaded
975 ;; if they are headed for memory.
977 ;; Notes: make sure no alternative allows g vs g.
978 ;; We don't allow f-regs since fixed point cannot go in them.
979 ;; We do allow y and x regs since fixed point is allowed in them.
980 [(set (match_operand:SI 0 "general_operand" "=g,d,a<,y,!*x*r*m")
981 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
986 if (which_alternative == 4)
987 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
988 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
989 return \"fpmove%.l %x1,%x0\";
990 return output_move_simode (operands);
994 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
995 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
997 "* return output_move_simode (operands);")
999 ;; Special case of fullword move, where we need to get a non-GOT PIC
1000 ;; reference into an address register.
1002 [(set (match_operand:SI 0 "general_operand" "=a<")
1003 (match_operand:SI 1 "pcrel_address" ""))]
1007 if (push_operand (operands[0], SImode))
1009 return \"lea %a1,%0\";
1012 (define_expand "movhi"
1013 [(set (match_operand:HI 0 "general_operand" "")
1014 (match_operand:HI 1 "general_operand" ""))]
1019 [(set (match_operand:HI 0 "general_operand" "=g")
1020 (match_operand:HI 1 "general_src_operand" "gS"))]
1022 "* return output_move_himode (operands);")
1025 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
1026 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
1028 "* return output_move_himode (operands);")
1030 (define_expand "movstricthi"
1031 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1032 (match_operand:HI 1 "general_src_operand" ""))]
1037 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1038 (match_operand:HI 1 "general_src_operand" "rmSn"))]
1040 "* return output_move_stricthi (operands);")
1043 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1044 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
1046 "* return output_move_stricthi (operands);")
1048 (define_expand "movqi"
1049 [(set (match_operand:QI 0 "general_operand" "")
1050 (match_operand:QI 1 "general_src_operand" ""))]
1055 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1056 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
1058 "* return output_move_qimode (operands);")
1061 [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
1062 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
1064 "* return output_move_qimode (operands);")
1066 (define_expand "movstrictqi"
1067 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1068 (match_operand:QI 1 "general_src_operand" ""))]
1073 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1074 (match_operand:QI 1 "general_src_operand" "dmSn"))]
1076 "* return output_move_strictqi (operands);")
1079 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1080 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
1082 "* return output_move_strictqi (operands);")
1084 (define_expand "movsf"
1085 [(set (match_operand:SF 0 "general_operand" "")
1086 (match_operand:SF 1 "general_operand" ""))]
1091 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1092 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1093 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1094 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1098 if (which_alternative >= 4)
1099 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1100 if (FPA_REG_P (operands[0]))
1102 if (FPA_REG_P (operands[1]))
1103 return \"fpmove%.s %x1,%x0\";
1104 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1105 return output_move_const_single (operands);
1106 else if (FP_REG_P (operands[1]))
1107 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1108 return \"fpmove%.s %x1,%x0\";
1110 if (FPA_REG_P (operands[1]))
1112 if (FP_REG_P (operands[0]))
1113 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1115 return \"fpmove%.s %x1,%x0\";
1117 if (FP_REG_P (operands[0]))
1119 if (FP_REG_P (operands[1]))
1120 return \"f%$move%.x %1,%0\";
1121 else if (ADDRESS_REG_P (operands[1]))
1122 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1123 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1124 return output_move_const_single (operands);
1125 return \"f%$move%.s %f1,%0\";
1127 if (FP_REG_P (operands[1]))
1129 if (ADDRESS_REG_P (operands[0]))
1130 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1131 return \"fmove%.s %f1,%0\";
1133 if (operands[1] == CONST0_RTX (SFmode)
1134 /* clr insns on 68000 read before writing.
1135 This isn't so on the 68010, but we have no TARGET_68010. */
1136 && ((TARGET_68020 || TARGET_5200)
1137 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1139 if (ADDRESS_REG_P (operands[0]))
1141 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1142 if (!TARGET_68040 && !TARGET_68060)
1143 return \"sub%.l %0,%0\";
1148 /* Many SGS assemblers croak on size specifiers for constants. */
1149 return \"lea 0,%0\";
1151 return \"lea 0.w,%0\";
1154 return \"lea 0:w,%0\";
1158 /* moveq is faster on the 68000. */
1159 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1161 #if defined(MOTOROLA) && !defined(CRDS)
1162 return \"moveq%.l %#0,%0\";
1164 return \"moveq %#0,%0\";
1167 return \"clr%.l %0\";
1169 return \"move%.l %1,%0\";
1173 [(set (match_operand:SF 0 "general_operand" "=r,g")
1174 (match_operand:SF 1 "general_operand" "g,r"))]
1176 "* return \"move%.l %1,%0\";")
1178 (define_expand "movdf"
1179 [(set (match_operand:DF 0 "general_operand" "")
1180 (match_operand:DF 1 "general_operand" ""))]
1185 [(set (match_operand:DF 0 "general_operand"
1186 "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
1187 (match_operand:DF 1 "general_operand"
1188 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
1189 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1190 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1194 if (which_alternative == 7)
1195 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1196 if (FPA_REG_P (operands[0]))
1198 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1199 return output_move_const_double (operands);
1200 if (FP_REG_P (operands[1]))
1201 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1202 return \"fpmove%.d %x1,%x0\";
1204 else if (FPA_REG_P (operands[1]))
1206 if (FP_REG_P(operands[0]))
1207 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1209 return \"fpmove%.d %x1,%x0\";
1211 if (FP_REG_P (operands[0]))
1213 if (FP_REG_P (operands[1]))
1214 return \"f%&move%.x %1,%0\";
1215 if (REG_P (operands[1]))
1218 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1219 output_asm_insn (\"move%.l %1,%-\", xoperands);
1220 output_asm_insn (\"move%.l %1,%-\", operands);
1221 return \"f%&move%.d %+,%0\";
1223 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1224 return output_move_const_double (operands);
1225 return \"f%&move%.d %f1,%0\";
1227 else if (FP_REG_P (operands[1]))
1229 if (REG_P (operands[0]))
1231 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1232 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1233 return \"move%.l %+,%0\";
1236 return \"fmove%.d %f1,%0\";
1238 return output_move_double (operands);
1242 [(set (match_operand:DF 0 "general_operand" "=r,g")
1243 (match_operand:DF 1 "general_operand" "g,r"))]
1245 "* return output_move_double (operands);")
1247 (define_expand "movxf"
1248 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1249 (match_operand:XF 1 "general_operand" ""))]
1253 if (CONSTANT_P (operands[1]))
1255 operands[1] = force_const_mem (XFmode, operands[1]);
1256 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1257 && ! reload_in_progress)
1258 operands[1] = change_address (operands[1], XFmode,
1259 XEXP (operands[1], 0));
1261 if (flag_pic && TARGET_PCREL && ! reload_in_progress)
1263 /* Don't allow writes to memory except via a register;
1264 the m68k doesn't consider PC-relative addresses to be writable. */
1265 if (GET_CODE (operands[0]) == MEM
1266 && symbolic_operand (XEXP (operands[0], 0), SImode))
1267 operands[0] = gen_rtx (MEM, XFmode,
1268 force_reg (SImode, XEXP (operands[0], 0)));
1273 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1274 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1278 if (FP_REG_P (operands[0]))
1280 if (FP_REG_P (operands[1]))
1281 return \"fmove%.x %1,%0\";
1282 if (REG_P (operands[1]))
1285 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1286 output_asm_insn (\"move%.l %1,%-\", xoperands);
1287 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1288 output_asm_insn (\"move%.l %1,%-\", xoperands);
1289 output_asm_insn (\"move%.l %1,%-\", operands);
1290 return \"fmove%.x %+,%0\";
1292 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1293 return \"fmove%.x %1,%0\";
1294 return \"fmove%.x %f1,%0\";
1296 if (FP_REG_P (operands[1]))
1298 if (REG_P (operands[0]))
1300 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1301 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1302 output_asm_insn (\"move%.l %+,%0\", operands);
1303 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1304 return \"move%.l %+,%0\";
1306 /* Must be memory destination. */
1307 return \"fmove%.x %f1,%0\";
1309 return output_move_double (operands);
1314 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1315 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1316 "! TARGET_68881 && ! TARGET_5200"
1319 if (FP_REG_P (operands[0]))
1321 if (FP_REG_P (operands[1]))
1322 return \"fmove%.x %1,%0\";
1323 if (REG_P (operands[1]))
1326 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1327 output_asm_insn (\"move%.l %1,%-\", xoperands);
1328 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1329 output_asm_insn (\"move%.l %1,%-\", xoperands);
1330 output_asm_insn (\"move%.l %1,%-\", operands);
1331 return \"fmove%.x %+,%0\";
1333 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1334 return \"fmove%.x %1,%0\";
1335 return \"fmove%.x %f1,%0\";
1337 if (FP_REG_P (operands[1]))
1339 if (REG_P (operands[0]))
1341 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1342 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1343 output_asm_insn (\"move%.l %+,%0\", operands);
1344 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1345 return \"move%.l %+,%0\";
1348 return \"fmove%.x %f1,%0\";
1350 return output_move_double (operands);
1355 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1356 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1357 "! TARGET_68881 && TARGET_5200"
1358 "* return output_move_double (operands);")
1360 (define_expand "movdi"
1361 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1362 [(set (match_operand:DI 0 "general_operand" "")
1363 (match_operand:DI 1 "general_operand" ""))]
1367 ;; movdi can apply to fp regs in some cases
1369 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1370 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1371 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1372 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1373 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1374 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1375 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1379 if (which_alternative == 8)
1380 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1381 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1382 return \"fpmove%.d %x1,%x0\";
1383 if (FP_REG_P (operands[0]))
1385 if (FP_REG_P (operands[1]))
1386 return \"fmove%.x %1,%0\";
1387 if (REG_P (operands[1]))
1390 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1391 output_asm_insn (\"move%.l %1,%-\", xoperands);
1392 output_asm_insn (\"move%.l %1,%-\", operands);
1393 return \"fmove%.d %+,%0\";
1395 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1396 return output_move_const_double (operands);
1397 return \"fmove%.d %f1,%0\";
1399 else if (FP_REG_P (operands[1]))
1401 if (REG_P (operands[0]))
1403 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1404 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1405 return \"move%.l %+,%0\";
1408 return \"fmove%.d %f1,%0\";
1410 return output_move_double (operands);
1414 [(set (match_operand:DI 0 "general_operand" "=r,g")
1415 (match_operand:DI 1 "general_operand" "g,r"))]
1417 "* return output_move_double (operands);")
1419 ;; Thus goes after the move instructions
1420 ;; because the move instructions are better (require no spilling)
1421 ;; when they can apply. It goes before the add/sub insns
1422 ;; so we will prefer it to them.
1424 (define_insn "pushasi"
1425 [(set (match_operand:SI 0 "push_operand" "=m")
1426 (match_operand:SI 1 "address_operand" "p"))]
1430 ;; truncation instructions
1431 (define_insn "truncsiqi2"
1432 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1434 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1438 if (GET_CODE (operands[0]) == REG)
1440 /* Must clear condition codes, since the move.l bases them on
1441 the entire 32 bits, not just the desired 8 bits. */
1443 return \"move%.l %1,%0\";
1445 if (GET_CODE (operands[1]) == MEM)
1446 operands[1] = adj_offsettable_operand (operands[1], 3);
1447 return \"move%.b %1,%0\";
1450 (define_insn "trunchiqi2"
1451 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1453 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1457 if (GET_CODE (operands[0]) == REG
1458 && (GET_CODE (operands[1]) == MEM
1459 || GET_CODE (operands[1]) == CONST_INT))
1461 /* Must clear condition codes, since the move.w bases them on
1462 the entire 16 bits, not just the desired 8 bits. */
1464 return \"move%.w %1,%0\";
1466 if (GET_CODE (operands[0]) == REG)
1468 /* Must clear condition codes, since the move.l bases them on
1469 the entire 32 bits, not just the desired 8 bits. */
1471 return \"move%.l %1,%0\";
1473 if (GET_CODE (operands[1]) == MEM)
1474 operands[1] = adj_offsettable_operand (operands[1], 1);
1475 return \"move%.b %1,%0\";
1478 (define_insn "truncsihi2"
1479 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1481 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1485 if (GET_CODE (operands[0]) == REG)
1487 /* Must clear condition codes, since the move.l bases them on
1488 the entire 32 bits, not just the desired 8 bits. */
1490 return \"move%.l %1,%0\";
1492 if (GET_CODE (operands[1]) == MEM)
1493 operands[1] = adj_offsettable_operand (operands[1], 2);
1494 return \"move%.w %1,%0\";
1497 ;; zero extension instructions
1499 (define_insn "zero_extendqidi2"
1500 [(set (match_operand:DI 0 "general_operand" "=&d")
1501 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1506 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1507 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1510 (define_insn "zero_extendhidi2"
1511 [(set (match_operand:DI 0 "general_operand" "=&d")
1512 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1517 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1518 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1521 ;; this is the canonical form for (lshiftrt:DI x 32)
1522 (define_insn "zero_extendsidi2"
1523 [(set (match_operand:DI 0 "general_operand" "=rm")
1524 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1529 if (GET_CODE (operands[0]) == REG)
1530 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1531 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1532 return \"move%.l %1,%0\;clr%.l %0\";
1533 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1534 return \"clr%.l %0\;move%.l %1,%0\";
1536 operands[2] = adj_offsettable_operand (operands[0], 4);
1537 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1538 || REGNO (operands[1]) != REGNO (operands[2]))
1539 output_asm_insn (\"move%.l %1,%2\", operands);
1540 if (ADDRESS_REG_P (operands[0]))
1541 return \"sub%.l %0,%0\";
1543 return \"clr%.l %0\";
1546 (define_expand "zero_extendhisi2"
1547 [(set (match_operand:SI 0 "register_operand" "")
1549 (set (strict_low_part (match_dup 2))
1550 (match_operand:HI 1 "general_operand" ""))]
1554 operands[1] = make_safe_from (operands[1], operands[0]);
1555 if (GET_CODE (operands[0]) == SUBREG)
1556 operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
1557 SUBREG_WORD (operands[0]));
1559 operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
1562 (define_expand "zero_extendqihi2"
1563 [(set (match_operand:HI 0 "register_operand" "")
1565 (set (strict_low_part (match_dup 2))
1566 (match_operand:QI 1 "general_operand" ""))]
1570 operands[1] = make_safe_from (operands[1], operands[0]);
1571 if (GET_CODE (operands[0]) == SUBREG)
1572 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1573 SUBREG_WORD (operands[0]));
1575 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1578 (define_expand "zero_extendqisi2"
1579 [(set (match_operand:SI 0 "register_operand" "")
1581 (set (strict_low_part (match_dup 2))
1582 (match_operand:QI 1 "general_operand" ""))]
1586 operands[1] = make_safe_from (operands[1], operands[0]);
1587 if (GET_CODE (operands[0]) == SUBREG)
1588 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1589 SUBREG_WORD (operands[0]));
1591 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1594 ;; Patterns to recognize zero-extend insns produced by the combiner.
1595 ;; We don't allow both operands in memory, because of aliasing problems.
1596 ;; Explicitly disallow two memory operands via the condition since reloading
1597 ;; of this case will result in worse code than the uncombined patterns.
1600 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1601 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1602 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1605 if (DATA_REG_P (operands[0]))
1607 if (GET_CODE (operands[1]) == REG
1608 && REGNO (operands[0]) == REGNO (operands[1]))
1609 return \"and%.l %#0xFFFF,%0\";
1610 if (reg_mentioned_p (operands[0], operands[1]))
1611 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1612 return \"clr%.l %0\;move%.w %1,%0\";
1614 else if (GET_CODE (operands[0]) == MEM
1615 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1616 return \"move%.w %1,%0\;clr%.w %0\";
1617 else if (GET_CODE (operands[0]) == MEM
1618 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1619 return \"clr%.w %0\;move%.w %1,%0\";
1622 output_asm_insn (\"clr%.w %0\", operands);
1623 operands[0] = adj_offsettable_operand (operands[0], 2);
1624 return \"move%.w %1,%0\";
1629 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1630 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1631 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1634 if (DATA_REG_P (operands[0]))
1636 if (GET_CODE (operands[1]) == REG
1637 && REGNO (operands[0]) == REGNO (operands[1]))
1638 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1639 if (reg_mentioned_p (operands[0], operands[1]))
1640 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1641 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1642 return \"clr%.w %0\;move%.b %1,%0\";
1644 else if (GET_CODE (operands[0]) == MEM
1645 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1647 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1648 == STACK_POINTER_REGNUM)
1650 output_asm_insn (\"clr%.w %-\", operands);
1651 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1652 plus_constant (stack_pointer_rtx, 1));
1653 return \"move%.b %1,%0\";
1656 return \"move%.b %1,%0\;clr%.b %0\";
1658 else if (GET_CODE (operands[0]) == MEM
1659 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1660 return \"clr%.b %0\;move%.b %1,%0\";
1663 output_asm_insn (\"clr%.b %0\", operands);
1664 operands[0] = adj_offsettable_operand (operands[0], 1);
1665 return \"move%.b %1,%0\";
1670 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1671 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1672 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1675 if (DATA_REG_P (operands[0]))
1677 if (GET_CODE (operands[1]) == REG
1678 && REGNO (operands[0]) == REGNO (operands[1]))
1679 return \"and%.l %#0xFF,%0\";
1680 if (reg_mentioned_p (operands[0], operands[1]))
1681 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1682 return \"clr%.l %0\;move%.b %1,%0\";
1684 else if (GET_CODE (operands[0]) == MEM
1685 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1687 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1690 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1692 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1695 return \"clrl %0@-\;moveb %1,%0@(3)\";
1698 else if (GET_CODE (operands[0]) == MEM
1699 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1701 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1704 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1706 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1709 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1714 output_asm_insn (\"clr%.l %0\", operands);
1715 operands[0] = adj_offsettable_operand (operands[0], 3);
1716 return \"move%.b %1,%0\";
1720 ;; sign extension instructions
1722 (define_insn "extendqidi2"
1723 [(set (match_operand:DI 0 "general_operand" "=d")
1724 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1729 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1730 if (TARGET_68020 || TARGET_5200)
1731 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1733 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1736 (define_insn "extendhidi2"
1737 [(set (match_operand:DI 0 "general_operand" "=d")
1739 (match_operand:HI 1 "general_src_operand" "rmS")))]
1744 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1745 if (TARGET_68020 || TARGET_5200)
1746 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1748 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1751 (define_insn "extendsidi2"
1752 [(set (match_operand:DI 0 "general_operand" "=d")
1754 (match_operand:SI 1 "general_operand" "rm")))]
1759 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1760 if (TARGET_68020 || TARGET_5200)
1761 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1763 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1766 ;; Special case when one can avoid register clobbering, copy and test
1767 ;; Maybe there is a way to make that the general case, by forcing the
1768 ;; result of the SI tree to be in the lower register of the DI target
1770 (define_insn "extendplussidi"
1771 [(set (match_operand:DI 0 "register_operand" "=d")
1772 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1773 (match_operand:SI 2 "general_operand" "rmn"))))]
1778 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1779 if (GET_CODE (operands[1]) == CONST_INT
1780 && (unsigned) INTVAL (operands[1]) > 8)
1782 rtx tmp = operands[1];
1784 operands[1] = operands[2];
1787 if (GET_CODE (operands[1]) == REG
1788 && REGNO (operands[1]) == REGNO (operands[3]))
1789 output_asm_insn (\"add%.l %2,%3\", operands);
1791 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1792 if (TARGET_68020 || TARGET_5200)
1793 return \"smi %0\;extb%.l %0\";
1795 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1798 (define_insn "extendhisi2"
1799 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1801 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1805 if (ADDRESS_REG_P (operands[0]))
1806 return \"move%.w %1,%0\";
1807 return \"ext%.l %0\";
1810 (define_insn "extendqihi2"
1811 [(set (match_operand:HI 0 "general_operand" "=d")
1812 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1816 (define_insn "extendqisi2"
1817 [(set (match_operand:SI 0 "general_operand" "=d")
1818 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1819 "TARGET_68020 || TARGET_5200"
1822 ;; Conversions between float and double.
1824 (define_expand "extendsfdf2"
1825 [(set (match_operand:DF 0 "general_operand" "")
1827 (match_operand:SF 1 "general_operand" "")))]
1828 "TARGET_68881 || TARGET_FPA"
1832 [(set (match_operand:DF 0 "general_operand" "=x,y")
1834 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1839 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1841 (match_operand:SF 1 "general_operand" "f,dmF")))]
1845 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1847 if (REGNO (operands[0]) == REGNO (operands[1]))
1849 /* Extending float to double in an fp-reg is a no-op.
1850 NOTICE_UPDATE_CC has already assumed that the
1851 cc will be set. So cancel what it did. */
1852 cc_status = cc_prev_status;
1855 return \"f%&move%.x %1,%0\";
1857 if (FP_REG_P (operands[0]))
1858 return \"f%&move%.s %f1,%0\";
1859 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1861 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1862 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1863 return \"move%.l %+,%0\";
1865 return \"fmove%.d %f1,%0\";
1868 ;; This cannot output into an f-reg because there is no way to be
1869 ;; sure of truncating in that case.
1870 ;; But on the Sun FPA, we can be sure.
1871 (define_expand "truncdfsf2"
1872 [(set (match_operand:SF 0 "general_operand" "")
1874 (match_operand:DF 1 "general_operand" "")))]
1875 "TARGET_68881 || TARGET_FPA"
1879 [(set (match_operand:SF 0 "general_operand" "=x,y")
1881 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1885 ;; On the '040 we can truncate in a register accurately and easily.
1887 [(set (match_operand:SF 0 "general_operand" "=f")
1889 (match_operand:DF 1 "general_operand" "fmG")))]
1893 if (FP_REG_P (operands[1]))
1894 return \"f%$move%.x %1,%0\";
1895 return \"f%$move%.d %f1,%0\";
1899 [(set (match_operand:SF 0 "general_operand" "=dm")
1901 (match_operand:DF 1 "general_operand" "f")))]
1905 ;; Conversion between fixed point and floating point.
1906 ;; Note that among the fix-to-float insns
1907 ;; the ones that start with SImode come first.
1908 ;; That is so that an operand that is a CONST_INT
1909 ;; (and therefore lacks a specific machine mode).
1910 ;; will be recognized as SImode (which is always valid)
1911 ;; rather than as QImode or HImode.
1913 (define_expand "floatsisf2"
1914 [(set (match_operand:SF 0 "general_operand" "")
1915 (float:SF (match_operand:SI 1 "general_operand" "")))]
1916 "TARGET_68881 || TARGET_FPA"
1920 [(set (match_operand:SF 0 "general_operand" "=y,x")
1921 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1926 [(set (match_operand:SF 0 "general_operand" "=f")
1927 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1931 (define_expand "floatsidf2"
1932 [(set (match_operand:DF 0 "general_operand" "")
1933 (float:DF (match_operand:SI 1 "general_operand" "")))]
1934 "TARGET_68881 || TARGET_FPA"
1938 [(set (match_operand:DF 0 "general_operand" "=y,x")
1939 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1944 [(set (match_operand:DF 0 "general_operand" "=f")
1945 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1949 (define_insn "floathisf2"
1950 [(set (match_operand:SF 0 "general_operand" "=f")
1951 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1955 (define_insn "floathidf2"
1956 [(set (match_operand:DF 0 "general_operand" "=f")
1957 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1961 (define_insn "floatqisf2"
1962 [(set (match_operand:SF 0 "general_operand" "=f")
1963 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1967 (define_insn "floatqidf2"
1968 [(set (match_operand:DF 0 "general_operand" "=f")
1969 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1973 ;; New routines to convert floating-point values to integers
1974 ;; to be used on the '040. These should be faster than trapping
1975 ;; into the kernel to emulate fintrz. They should also be faster
1976 ;; than calling the subroutines fixsfsi or fixdfsi.
1978 (define_insn "fix_truncdfsi2"
1979 [(set (match_operand:SI 0 "general_operand" "=dm")
1980 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1981 (clobber (match_scratch:SI 2 "=d"))
1982 (clobber (match_scratch:SI 3 "=d"))]
1983 "TARGET_68881 && TARGET_68040"
1987 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1990 (define_insn "fix_truncdfhi2"
1991 [(set (match_operand:HI 0 "general_operand" "=dm")
1992 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1993 (clobber (match_scratch:SI 2 "=d"))
1994 (clobber (match_scratch:SI 3 "=d"))]
1995 "TARGET_68881 && TARGET_68040"
1999 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
2002 (define_insn "fix_truncdfqi2"
2003 [(set (match_operand:QI 0 "general_operand" "=dm")
2004 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2005 (clobber (match_scratch:SI 2 "=d"))
2006 (clobber (match_scratch:SI 3 "=d"))]
2007 "TARGET_68881 && TARGET_68040"
2011 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
2014 ;; Convert a float to a float whose value is an integer.
2015 ;; This is the first stage of converting it to an integer type.
2017 (define_insn "ftruncdf2"
2018 [(set (match_operand:DF 0 "general_operand" "=f")
2019 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
2020 "TARGET_68881 && !TARGET_68040"
2023 if (FP_REG_P (operands[1]))
2024 return \"fintrz%.x %f1,%0\";
2025 return \"fintrz%.d %f1,%0\";
2028 (define_insn "ftruncsf2"
2029 [(set (match_operand:SF 0 "general_operand" "=f")
2030 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
2031 "TARGET_68881 && !TARGET_68040"
2034 if (FP_REG_P (operands[1]))
2035 return \"fintrz%.x %f1,%0\";
2036 return \"fintrz%.s %f1,%0\";
2039 ;; Convert a float whose value is an integer
2040 ;; to an actual integer. Second stage of converting float to integer type.
2041 (define_insn "fixsfqi2"
2042 [(set (match_operand:QI 0 "general_operand" "=dm")
2043 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2047 (define_insn "fixsfhi2"
2048 [(set (match_operand:HI 0 "general_operand" "=dm")
2049 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2053 (define_insn "fixsfsi2"
2054 [(set (match_operand:SI 0 "general_operand" "=dm")
2055 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2059 (define_insn "fixdfqi2"
2060 [(set (match_operand:QI 0 "general_operand" "=dm")
2061 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2065 (define_insn "fixdfhi2"
2066 [(set (match_operand:HI 0 "general_operand" "=dm")
2067 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2071 (define_insn "fixdfsi2"
2072 [(set (match_operand:SI 0 "general_operand" "=dm")
2073 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2077 ;; Convert a float to an integer.
2078 ;; On the Sun FPA, this is done in one step.
2081 [(set (match_operand:SI 0 "general_operand" "=x,y")
2082 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2087 [(set (match_operand:SI 0 "general_operand" "=x,y")
2088 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2094 (define_insn "adddi_lshrdi_63"
2095 [(set (match_operand:DI 0 "general_operand" "=d")
2096 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2099 (clobber (match_scratch:SI 2 "=d"))]
2103 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2104 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2106 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2107 if (GET_CODE (operands[1]) == REG)
2108 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2109 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2110 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2111 operands[4] = operands[1];
2113 operands[4] = adj_offsettable_operand (operands[1], 4);
2114 if (GET_CODE (operands[1]) == MEM
2115 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2116 output_asm_insn (\"move%.l %4,%3\", operands);
2117 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2118 if (TARGET_68020 || TARGET_5200)
2119 output_asm_insn (\"extb%.l %2\", operands);
2121 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2122 if (GET_CODE (operands[1]) != MEM
2123 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2124 output_asm_insn (\"move%.l %4,%3\", operands);
2125 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2128 (define_insn "adddi_sexthishl32"
2129 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2130 (plus:DI (ashift:DI (sign_extend:DI
2131 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2133 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2134 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2139 if (ADDRESS_REG_P (operands[0]))
2140 return \"add%.w %1,%0\";
2141 else if (ADDRESS_REG_P (operands[3]))
2142 return \"move%.w %1,%3\;add%.l %3,%0\";
2144 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2147 (define_insn "adddi_dilshr32"
2148 [(set (match_operand:DI 0 "general_operand" "=d,o")
2149 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2150 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2151 ;; (const_int 32))))]
2152 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
2154 (match_operand:DI 2 "general_operand" "0,0")))]
2159 if (GET_CODE (operands[0]) == REG)
2160 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2162 operands[2] = adj_offsettable_operand (operands[0], 4);
2163 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2166 (define_insn "adddi_dishl32"
2167 [(set (match_operand:DI 0 "general_operand" "=r,o")
2168 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2169 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2170 ;; (const_int 32))))]
2171 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
2173 (match_operand:DI 2 "general_operand" "0,0")))]
2178 if (GET_CODE (operands[1]) == REG)
2179 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2181 operands[1] = adj_offsettable_operand (operands[1], 4);
2182 return \"add%.l %1,%0\";
2185 (define_insn "adddi3"
2186 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2187 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2188 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2189 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2193 if (DATA_REG_P (operands[0]))
2195 if (DATA_REG_P (operands[2]))
2196 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2197 else if (GET_CODE (operands[2]) == MEM
2198 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2199 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2205 if (GET_CODE (operands[2]) == REG)
2207 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2210 else if (CONSTANT_P (operands[2]))
2211 split_double (operands[2], &high, &low);
2214 low = adj_offsettable_operand (operands[2], 4);
2218 operands[1] = low, operands[2] = high;
2219 xoperands[0] = operands[3];
2220 if (GET_CODE (operands[1]) == CONST_INT
2221 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2222 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2224 xoperands[1] = operands[2];
2226 output_asm_insn (output_move_simode (xoperands), xoperands);
2227 if (GET_CODE (operands[1]) == CONST_INT)
2229 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2232 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2234 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2237 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2239 operands[1] = GEN_INT (-INTVAL (operands[1]));
2241 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2243 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2247 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2250 else if (GET_CODE (operands[0]) == MEM)
2252 if (GET_CODE (operands[2]) == MEM
2253 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2254 return \"add%.l %2,%0\;addx%.l %2,%0\";
2256 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2258 operands[1] = gen_rtx_MEM (SImode,
2259 plus_constant (XEXP(operands[0], 0), -8));
2260 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2262 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2264 operands[1] = XEXP(operands[0], 0);
2265 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2269 operands[1] = adj_offsettable_operand (operands[0], 4);
2270 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2277 (define_insn "addsi_lshrsi_31"
2278 [(set (match_operand:SI 0 "general_operand" "=dm")
2279 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2285 operands[2] = operands[0];
2286 operands[3] = gen_label_rtx();
2287 if (GET_CODE (operands[0]) == MEM)
2289 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2290 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2291 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2292 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2294 output_asm_insn (\"move%.l %1,%0\", operands);
2296 output_asm_insn (\"jbpl %l3\", operands);
2298 output_asm_insn (\"jpl %l3\", operands);
2301 output_asm_insn (\"addq%.l %#1,%2\", operands);
2303 output_asm_insn (\"add%.l %#1,%2\", operands);
2305 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2306 CODE_LABEL_NUMBER (operands[3]));
2310 (define_expand "addsi3"
2311 [(set (match_operand:SI 0 "general_operand" "")
2312 (plus:SI (match_operand:SI 1 "general_operand" "")
2313 (match_operand:SI 2 "general_src_operand" "")))]
2317 ;; Note that the middle two alternatives are near-duplicates
2318 ;; in order to handle insns generated by reload.
2319 ;; This is needed since they are not themselves reloaded,
2320 ;; so commutativity won't apply to them.
2321 (define_insn "*addsi3_internal"
2322 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,d,a")
2323 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2324 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2328 "* return output_addsi3 (operands);")
2330 (define_insn "*addsi3_5200"
2331 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2332 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2333 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2335 "* return output_addsi3 (operands);")
2338 [(set (match_operand:SI 0 "general_operand" "=a")
2339 (plus:SI (match_operand:SI 1 "general_operand" "0")
2341 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2345 (define_insn "addhi3"
2346 [(set (match_operand:HI 0 "general_operand" "=m,r")
2347 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2348 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2352 if (GET_CODE (operands[2]) == CONST_INT)
2355 /* If the constant would be a negative number when interpreted as
2356 HImode, make it negative. This is usually, but not always, done
2357 elsewhere in the compiler. First check for constants out of range,
2358 which could confuse us. */
2360 if (INTVAL (operands[2]) >= 32768)
2361 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2363 if (INTVAL (operands[2]) > 0
2364 && INTVAL (operands[2]) <= 8)
2365 return \"addq%.w %2,%0\";
2366 if (INTVAL (operands[2]) < 0
2367 && INTVAL (operands[2]) >= -8)
2369 operands[2] = GEN_INT (- INTVAL (operands[2]));
2370 return \"subq%.w %2,%0\";
2372 /* On the CPU32 it is faster to use two addqw instructions to
2373 add a small integer (8 < N <= 16) to a register.
2374 Likewise for subqw. */
2375 if (TARGET_CPU32 && REG_P (operands[0]))
2377 if (INTVAL (operands[2]) > 8
2378 && INTVAL (operands[2]) <= 16)
2380 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2381 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2383 if (INTVAL (operands[2]) < -8
2384 && INTVAL (operands[2]) >= -16)
2386 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2387 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2391 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2393 return \"lea (%c2,%0),%0\";
2395 return \"lea %0@(%c2),%0\";
2398 return \"add%.w %2,%0\";
2401 ;; These insns must use MATCH_DUP instead of the more expected
2402 ;; use of a matching constraint because the "output" here is also
2403 ;; an input, so you can't use the matching constraint. That also means
2404 ;; that you can't use the "%", so you need patterns with the matched
2405 ;; operand in both positions.
2408 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2409 (plus:HI (match_dup 0)
2410 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2414 if (GET_CODE (operands[1]) == CONST_INT)
2417 /* If the constant would be a negative number when interpreted as
2418 HImode, make it negative. This is usually, but not always, done
2419 elsewhere in the compiler. First check for constants out of range,
2420 which could confuse us. */
2422 if (INTVAL (operands[1]) >= 32768)
2423 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2425 if (INTVAL (operands[1]) > 0
2426 && INTVAL (operands[1]) <= 8)
2427 return \"addq%.w %1,%0\";
2428 if (INTVAL (operands[1]) < 0
2429 && INTVAL (operands[1]) >= -8)
2431 operands[1] = GEN_INT (- INTVAL (operands[1]));
2432 return \"subq%.w %1,%0\";
2434 /* On the CPU32 it is faster to use two addqw instructions to
2435 add a small integer (8 < N <= 16) to a register.
2436 Likewise for subqw. */
2437 if (TARGET_CPU32 && REG_P (operands[0]))
2439 if (INTVAL (operands[1]) > 8
2440 && INTVAL (operands[1]) <= 16)
2442 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2443 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2445 if (INTVAL (operands[1]) < -8
2446 && INTVAL (operands[1]) >= -16)
2448 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2449 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2453 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2455 return \"lea (%c1,%0),%0\";
2457 return \"lea %0@(%c1),%0\";
2460 return \"add%.w %1,%0\";
2464 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2465 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2470 if (GET_CODE (operands[1]) == CONST_INT)
2473 /* If the constant would be a negative number when interpreted as
2474 HImode, make it negative. This is usually, but not always, done
2475 elsewhere in the compiler. First check for constants out of range,
2476 which could confuse us. */
2478 if (INTVAL (operands[1]) >= 32768)
2479 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2481 if (INTVAL (operands[1]) > 0
2482 && INTVAL (operands[1]) <= 8)
2483 return \"addq%.w %1,%0\";
2484 if (INTVAL (operands[1]) < 0
2485 && INTVAL (operands[1]) >= -8)
2487 operands[1] = GEN_INT (- INTVAL (operands[1]));
2488 return \"subq%.w %1,%0\";
2490 /* On the CPU32 it is faster to use two addqw instructions to
2491 add a small integer (8 < N <= 16) to a register.
2492 Likewise for subqw. */
2493 if (TARGET_CPU32 && REG_P (operands[0]))
2495 if (INTVAL (operands[1]) > 8
2496 && INTVAL (operands[1]) <= 16)
2498 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2499 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2501 if (INTVAL (operands[1]) < -8
2502 && INTVAL (operands[1]) >= -16)
2504 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2505 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2509 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2511 return \"lea (%c1,%0),%0\";
2513 return \"lea %0@(%c1),%0\";
2516 return \"add%.w %1,%0\";
2519 (define_insn "addqi3"
2520 [(set (match_operand:QI 0 "general_operand" "=m,d")
2521 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2522 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2527 if (GET_CODE (operands[2]) == CONST_INT)
2529 if (INTVAL (operands[2]) >= 128)
2530 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2532 if (INTVAL (operands[2]) > 0
2533 && INTVAL (operands[2]) <= 8)
2534 return \"addq%.b %2,%0\";
2535 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2537 operands[2] = GEN_INT (- INTVAL (operands[2]));
2538 return \"subq%.b %2,%0\";
2542 return \"add%.b %2,%0\";
2546 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2547 (plus:QI (match_dup 0)
2548 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2553 if (GET_CODE (operands[1]) == CONST_INT)
2555 if (INTVAL (operands[1]) >= 128)
2556 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2558 if (INTVAL (operands[1]) > 0
2559 && INTVAL (operands[1]) <= 8)
2560 return \"addq%.b %1,%0\";
2561 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2563 operands[1] = GEN_INT (- INTVAL (operands[1]));
2564 return \"subq%.b %1,%0\";
2568 return \"add%.b %1,%0\";
2572 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2573 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2579 if (GET_CODE (operands[1]) == CONST_INT)
2581 if (INTVAL (operands[1]) >= 128)
2582 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2584 if (INTVAL (operands[1]) > 0
2585 && INTVAL (operands[1]) <= 8)
2586 return \"addq%.b %1,%0\";
2587 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2589 operands[1] = GEN_INT (- INTVAL (operands[1]));
2590 return \"subq%.b %1,%0\";
2594 return \"add%.b %1,%0\";
2597 (define_expand "adddf3"
2598 [(set (match_operand:DF 0 "general_operand" "")
2599 (plus:DF (match_operand:DF 1 "general_operand" "")
2600 (match_operand:DF 2 "general_operand" "")))]
2601 "TARGET_68881 || TARGET_FPA"
2605 [(set (match_operand:DF 0 "general_operand" "=x,y")
2606 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2607 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2611 if (rtx_equal_p (operands[0], operands[1]))
2612 return \"fpadd%.d %y2,%0\";
2613 if (rtx_equal_p (operands[0], operands[2]))
2614 return \"fpadd%.d %y1,%0\";
2615 if (which_alternative == 0)
2616 return \"fpadd3%.d %w2,%w1,%0\";
2617 return \"fpadd3%.d %x2,%x1,%0\";
2621 [(set (match_operand:DF 0 "general_operand" "=f")
2622 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2623 (match_operand:DF 1 "general_operand" "0")))]
2628 [(set (match_operand:DF 0 "general_operand" "=f")
2629 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2630 (match_operand:DF 1 "general_operand" "0")))]
2635 [(set (match_operand:DF 0 "general_operand" "=f")
2636 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2637 (match_operand:DF 1 "general_operand" "0")))]
2642 [(set (match_operand:DF 0 "general_operand" "=f")
2643 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2644 (match_operand:DF 2 "general_operand" "fmG")))]
2648 if (REG_P (operands[2]))
2649 return \"f%&add%.x %2,%0\";
2650 return \"f%&add%.d %f2,%0\";
2653 (define_expand "addsf3"
2654 [(set (match_operand:SF 0 "general_operand" "")
2655 (plus:SF (match_operand:SF 1 "general_operand" "")
2656 (match_operand:SF 2 "general_operand" "")))]
2657 "TARGET_68881 || TARGET_FPA"
2661 [(set (match_operand:SF 0 "general_operand" "=x,y")
2662 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2663 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2667 if (rtx_equal_p (operands[0], operands[1]))
2668 return \"fpadd%.s %w2,%0\";
2669 if (rtx_equal_p (operands[0], operands[2]))
2670 return \"fpadd%.s %w1,%0\";
2671 if (which_alternative == 0)
2672 return \"fpadd3%.s %w2,%w1,%0\";
2673 return \"fpadd3%.s %2,%1,%0\";
2677 [(set (match_operand:SF 0 "general_operand" "=f")
2678 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2679 (match_operand:SF 1 "general_operand" "0")))]
2684 [(set (match_operand:SF 0 "general_operand" "=f")
2685 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2686 (match_operand:SF 1 "general_operand" "0")))]
2691 [(set (match_operand:SF 0 "general_operand" "=f")
2692 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2693 (match_operand:SF 1 "general_operand" "0")))]
2698 [(set (match_operand:SF 0 "general_operand" "=f")
2699 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2700 (match_operand:SF 2 "general_operand" "fdmF")))]
2704 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2705 return \"f%$add%.x %2,%0\";
2706 return \"f%$add%.s %f2,%0\";
2709 ;; subtract instructions
2711 (define_insn "subdi_sexthishl32"
2712 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2713 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2714 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2716 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2721 if (ADDRESS_REG_P (operands[0]))
2722 return \"sub%.w %2,%0\";
2723 else if (ADDRESS_REG_P (operands[3]))
2724 return \"move%.w %2,%3\;sub%.l %3,%0\";
2726 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2729 (define_insn "subdi_dishl32"
2730 [(set (match_operand:DI 0 "general_operand" "+ro")
2731 (minus:DI (match_dup 0)
2732 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2738 if (GET_CODE (operands[1]) == REG)
2739 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2741 operands[1] = adj_offsettable_operand (operands[1], 4);
2742 return \"sub%.l %1,%0\";
2745 (define_insn "subdi3"
2746 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2747 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2748 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2749 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2753 if (DATA_REG_P (operands[0]))
2755 if (DATA_REG_P (operands[2]))
2756 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2757 else if (GET_CODE (operands[2]) == MEM
2758 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2760 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2767 if (GET_CODE (operands[2]) == REG)
2769 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2772 else if (CONSTANT_P (operands[2]))
2773 split_double (operands[2], &high, &low);
2776 low = adj_offsettable_operand (operands[2], 4);
2780 operands[1] = low, operands[2] = high;
2781 xoperands[0] = operands[3];
2782 if (GET_CODE (operands[1]) == CONST_INT
2783 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2784 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2786 xoperands[1] = operands[2];
2788 output_asm_insn (output_move_simode (xoperands), xoperands);
2789 if (GET_CODE (operands[1]) == CONST_INT)
2791 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2794 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2796 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2799 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2801 operands[1] = GEN_INT (-INTVAL (operands[1]));
2803 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2805 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2809 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2812 else if (GET_CODE (operands[0]) == MEM)
2814 if (GET_CODE (operands[2]) == MEM
2815 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2816 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2818 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2821 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2822 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2824 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2826 operands[1] = XEXP(operands[0], 0);
2827 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2831 operands[1] = adj_offsettable_operand (operands[0], 4);
2832 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2839 (define_insn "subsi3"
2840 [(set (match_operand:SI 0 "general_operand" "=m,d,a")
2841 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2842 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2847 [(set (match_operand:SI 0 "general_operand" "=a")
2848 (minus:SI (match_operand:SI 1 "general_operand" "0")
2850 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2854 (define_insn "subhi3"
2855 [(set (match_operand:HI 0 "general_operand" "=m,r")
2856 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2857 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2862 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2863 (minus:HI (match_dup 0)
2864 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2868 (define_insn "subqi3"
2869 [(set (match_operand:QI 0 "general_operand" "=m,d")
2870 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2871 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2876 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2877 (minus:QI (match_dup 0)
2878 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2882 (define_expand "subdf3"
2883 [(set (match_operand:DF 0 "general_operand" "")
2884 (minus:DF (match_operand:DF 1 "general_operand" "")
2885 (match_operand:DF 2 "general_operand" "")))]
2886 "TARGET_68881 || TARGET_FPA"
2890 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2891 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2892 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2896 if (rtx_equal_p (operands[0], operands[2]))
2897 return \"fprsub%.d %y1,%0\";
2898 if (rtx_equal_p (operands[0], operands[1]))
2899 return \"fpsub%.d %y2,%0\";
2900 if (which_alternative == 0)
2901 return \"fpsub3%.d %w2,%w1,%0\";
2902 return \"fpsub3%.d %x2,%x1,%0\";
2906 [(set (match_operand:DF 0 "general_operand" "=f")
2907 (minus:DF (match_operand:DF 1 "general_operand" "0")
2908 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2913 [(set (match_operand:DF 0 "general_operand" "=f")
2914 (minus:DF (match_operand:DF 1 "general_operand" "0")
2915 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2920 [(set (match_operand:DF 0 "general_operand" "=f")
2921 (minus:DF (match_operand:DF 1 "general_operand" "0")
2922 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2927 [(set (match_operand:DF 0 "general_operand" "=f")
2928 (minus:DF (match_operand:DF 1 "general_operand" "0")
2929 (match_operand:DF 2 "general_operand" "fmG")))]
2933 if (REG_P (operands[2]))
2934 return \"f%&sub%.x %2,%0\";
2935 return \"f%&sub%.d %f2,%0\";
2938 (define_expand "subsf3"
2939 [(set (match_operand:SF 0 "general_operand" "")
2940 (minus:SF (match_operand:SF 1 "general_operand" "")
2941 (match_operand:SF 2 "general_operand" "")))]
2942 "TARGET_68881 || TARGET_FPA"
2946 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2947 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2948 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2952 if (rtx_equal_p (operands[0], operands[2]))
2953 return \"fprsub%.s %w1,%0\";
2954 if (rtx_equal_p (operands[0], operands[1]))
2955 return \"fpsub%.s %w2,%0\";
2956 if (which_alternative == 0)
2957 return \"fpsub3%.s %w2,%w1,%0\";
2958 return \"fpsub3%.s %2,%1,%0\";
2962 [(set (match_operand:SF 0 "general_operand" "=f")
2963 (minus:SF (match_operand:SF 1 "general_operand" "0")
2964 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2969 [(set (match_operand:SF 0 "general_operand" "=f")
2970 (minus:SF (match_operand:SF 1 "general_operand" "0")
2971 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2976 [(set (match_operand:SF 0 "general_operand" "=f")
2977 (minus:SF (match_operand:SF 1 "general_operand" "0")
2978 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2983 [(set (match_operand:SF 0 "general_operand" "=f")
2984 (minus:SF (match_operand:SF 1 "general_operand" "0")
2985 (match_operand:SF 2 "general_operand" "fdmF")))]
2989 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2990 return \"f%$sub%.x %2,%0\";
2991 return \"f%$sub%.s %f2,%0\";
2994 ;; multiply instructions
2996 (define_insn "mulhi3"
2997 [(set (match_operand:HI 0 "general_operand" "=d")
2998 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2999 (match_operand:HI 2 "general_src_operand" "dmSn")))]
3003 #if defined(MOTOROLA) && !defined(CRDS)
3004 return \"muls%.w %2,%0\";
3006 return \"muls %2,%0\";
3010 (define_insn "mulhisi3"
3011 [(set (match_operand:SI 0 "general_operand" "=d")
3012 (mult:SI (sign_extend:SI
3013 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3015 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3019 #if defined(MOTOROLA) && !defined(CRDS)
3020 return \"muls%.w %2,%0\";
3022 return \"muls %2,%0\";
3027 [(set (match_operand:SI 0 "general_operand" "=d")
3028 (mult:SI (sign_extend:SI
3029 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3030 (match_operand:SI 2 "const_int_operand" "n")))]
3031 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
3034 #if defined(MOTOROLA) && !defined(CRDS)
3035 return \"muls%.w %2,%0\";
3037 return \"muls %2,%0\";
3041 (define_expand "mulsi3"
3042 [(set (match_operand:SI 0 "general_operand" "")
3043 (mult:SI (match_operand:SI 1 "general_operand" "")
3044 (match_operand:SI 2 "general_operand" "")))]
3045 "TARGET_68020 || TARGET_5200"
3049 [(set (match_operand:SI 0 "general_operand" "=d")
3050 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3051 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
3057 [(set (match_operand:SI 0 "general_operand" "=d")
3058 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3059 (match_operand:SI 2 "general_operand" "d<Q>")))]
3063 (define_insn "umulhisi3"
3064 [(set (match_operand:SI 0 "general_operand" "=d")
3065 (mult:SI (zero_extend:SI
3066 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3068 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3072 #if defined(MOTOROLA) && !defined(CRDS)
3073 return \"mulu%.w %2,%0\";
3075 return \"mulu %2,%0\";
3080 [(set (match_operand:SI 0 "general_operand" "=d")
3081 (mult:SI (zero_extend:SI
3082 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3083 (match_operand:SI 2 "const_int_operand" "n")))]
3084 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3087 #if defined(MOTOROLA) && !defined(CRDS)
3088 return \"mulu%.w %2,%0\";
3090 return \"mulu %2,%0\";
3094 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3095 ;; proper matching constraint. This is because the matching is between
3096 ;; the high-numbered word of the DImode operand[0] and operand[1].
3097 (define_expand "umulsidi3"
3099 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3100 (mult:SI (match_operand:SI 1 "register_operand" "")
3101 (match_operand:SI 2 "nonimmediate_operand" "")))
3102 (set (subreg:SI (match_dup 0) 0)
3103 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3104 (zero_extend:DI (match_dup 2)))
3105 (const_int 32))))])]
3106 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3110 [(set (match_operand:SI 0 "register_operand" "=d")
3111 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3112 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3113 (set (match_operand:SI 3 "register_operand" "=d")
3114 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3115 (zero_extend:DI (match_dup 2)))
3117 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3120 ; Match immediate case. For 2.4 only match things < 2^31.
3121 ; It's tricky with larger values in these patterns since we need to match
3122 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3125 [(set (match_operand:SI 0 "register_operand" "=d")
3126 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3127 (match_operand:SI 2 "const_int_operand" "n")))
3128 (set (match_operand:SI 3 "register_operand" "=d")
3129 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3132 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3133 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3136 (define_expand "mulsidi3"
3138 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3139 (mult:SI (match_operand:SI 1 "register_operand" "")
3140 (match_operand:SI 2 "nonimmediate_operand" "")))
3141 (set (subreg:SI (match_dup 0) 0)
3142 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3143 (sign_extend:DI (match_dup 2)))
3144 (const_int 32))))])]
3145 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3149 [(set (match_operand:SI 0 "register_operand" "=d")
3150 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3151 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3152 (set (match_operand:SI 3 "register_operand" "=d")
3153 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3154 (sign_extend:DI (match_dup 2)))
3156 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3160 [(set (match_operand:SI 0 "register_operand" "=d")
3161 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3162 (match_operand:SI 2 "const_sint32_operand" "")))
3163 (set (match_operand:SI 3 "register_operand" "=d")
3164 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3167 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3170 (define_expand "umulsi3_highpart"
3172 [(set (match_operand:SI 0 "register_operand" "")
3175 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3176 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3178 (clobber (match_dup 3))])]
3179 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3182 operands[3] = gen_reg_rtx (SImode);
3183 if (GET_CODE (operands[2]) == CONST_INT
3184 || GET_CODE (operands[2]) == CONST_DOUBLE)
3186 if (! const_uint32_operand (operands[2], VOIDmode))
3188 /* We have to adjust the operand order for the matching constraints. */
3189 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3190 operands[1], operands[2]));
3196 [(set (match_operand:SI 0 "register_operand" "=d")
3199 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3200 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3202 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3203 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3206 (define_insn "const_umulsi3_highpart"
3207 [(set (match_operand:SI 0 "register_operand" "=d")
3210 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3211 (match_operand 3 "const_uint32_operand" ""))
3213 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3214 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3217 (define_expand "smulsi3_highpart"
3219 [(set (match_operand:SI 0 "register_operand" "")
3222 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3223 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3225 (clobber (match_dup 3))])]
3226 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3229 operands[3] = gen_reg_rtx (SImode);
3230 if (GET_CODE (operands[2]) == CONST_INT
3231 || GET_CODE (operands[2]) == CONST_DOUBLE)
3233 if (! const_sint32_operand (operands[2], VOIDmode))
3235 /* We have to adjust the operand order for the matching constraints. */
3236 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3237 operands[1], operands[2]));
3243 [(set (match_operand:SI 0 "register_operand" "=d")
3246 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3247 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3249 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3250 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3253 (define_insn "const_smulsi3_highpart"
3254 [(set (match_operand:SI 0 "register_operand" "=d")
3257 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3258 (match_operand 3 "const_sint32_operand" ""))
3260 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3261 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3264 (define_expand "muldf3"
3265 [(set (match_operand:DF 0 "general_operand" "")
3266 (mult:DF (match_operand:DF 1 "general_operand" "")
3267 (match_operand:DF 2 "general_operand" "")))]
3268 "TARGET_68881 || TARGET_FPA"
3272 [(set (match_operand:DF 0 "general_operand" "=x,y")
3273 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3274 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3278 if (rtx_equal_p (operands[1], operands[2]))
3279 return \"fpsqr%.d %y1,%0\";
3280 if (rtx_equal_p (operands[0], operands[1]))
3281 return \"fpmul%.d %y2,%0\";
3282 if (rtx_equal_p (operands[0], operands[2]))
3283 return \"fpmul%.d %y1,%0\";
3284 if (which_alternative == 0)
3285 return \"fpmul3%.d %w2,%w1,%0\";
3286 return \"fpmul3%.d %x2,%x1,%0\";
3290 [(set (match_operand:DF 0 "general_operand" "=f")
3291 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3292 (match_operand:DF 1 "general_operand" "0")))]
3297 [(set (match_operand:DF 0 "general_operand" "=f")
3298 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3299 (match_operand:DF 1 "general_operand" "0")))]
3304 [(set (match_operand:DF 0 "general_operand" "=f")
3305 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3306 (match_operand:DF 1 "general_operand" "0")))]
3311 [(set (match_operand:DF 0 "general_operand" "=f")
3312 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3313 (match_operand:DF 2 "general_operand" "fmG")))]
3317 if (GET_CODE (operands[2]) == CONST_DOUBLE
3318 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3320 int i = floating_exact_log2 (operands[2]);
3321 operands[2] = GEN_INT (i);
3322 return \"fscale%.l %2,%0\";
3324 if (REG_P (operands[2]))
3325 return \"f%&mul%.x %2,%0\";
3326 return \"f%&mul%.d %f2,%0\";
3329 (define_expand "mulsf3"
3330 [(set (match_operand:SF 0 "general_operand" "")
3331 (mult:SF (match_operand:SF 1 "general_operand" "")
3332 (match_operand:SF 2 "general_operand" "")))]
3333 "TARGET_68881 || TARGET_FPA"
3337 [(set (match_operand:SF 0 "general_operand" "=x,y")
3338 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3339 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3343 if (rtx_equal_p (operands[1], operands[2]))
3344 return \"fpsqr%.s %w1,%0\";
3345 if (rtx_equal_p (operands[0], operands[1]))
3346 return \"fpmul%.s %w2,%0\";
3347 if (rtx_equal_p (operands[0], operands[2]))
3348 return \"fpmul%.s %w1,%0\";
3349 if (which_alternative == 0)
3350 return \"fpmul3%.s %w2,%w1,%0\";
3351 return \"fpmul3%.s %2,%1,%0\";
3355 [(set (match_operand:SF 0 "general_operand" "=f")
3356 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3357 (match_operand:SF 1 "general_operand" "0")))]
3361 return (TARGET_68040_ONLY
3362 ? \"fsmul%.l %2,%0\"
3363 : \"fsglmul%.l %2,%0\");
3367 [(set (match_operand:SF 0 "general_operand" "=f")
3368 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3369 (match_operand:SF 1 "general_operand" "0")))]
3373 return (TARGET_68040_ONLY
3374 ? \"fsmul%.w %2,%0\"
3375 : \"fsglmul%.w %2,%0\");
3379 [(set (match_operand:SF 0 "general_operand" "=f")
3380 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3381 (match_operand:SF 1 "general_operand" "0")))]
3385 return (TARGET_68040_ONLY
3386 ? \"fsmul%.b %2,%0\"
3387 : \"fsglmul%.b %2,%0\");
3391 [(set (match_operand:SF 0 "general_operand" "=f")
3392 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3393 (match_operand:SF 2 "general_operand" "fdmF")))]
3397 #ifdef FSGLMUL_USE_S
3398 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3399 return (TARGET_68040_ONLY
3400 ? \"fsmul%.s %2,%0\"
3401 : \"fsglmul%.s %2,%0\");
3403 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3404 return (TARGET_68040_ONLY
3405 ? \"fsmul%.x %2,%0\"
3406 : \"fsglmul%.x %2,%0\");
3408 return (TARGET_68040_ONLY
3409 ? \"fsmul%.s %f2,%0\"
3410 : \"fsglmul%.s %f2,%0\");
3413 ;; divide instructions
3415 (define_expand "divdf3"
3416 [(set (match_operand:DF 0 "general_operand" "")
3417 (div:DF (match_operand:DF 1 "general_operand" "")
3418 (match_operand:DF 2 "general_operand" "")))]
3419 "TARGET_68881 || TARGET_FPA"
3423 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3424 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3425 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3429 if (rtx_equal_p (operands[0], operands[2]))
3430 return \"fprdiv%.d %y1,%0\";
3431 if (rtx_equal_p (operands[0], operands[1]))
3432 return \"fpdiv%.d %y2,%0\";
3433 if (which_alternative == 0)
3434 return \"fpdiv3%.d %w2,%w1,%0\";
3435 return \"fpdiv3%.d %x2,%x1,%x0\";
3439 [(set (match_operand:DF 0 "general_operand" "=f")
3440 (div:DF (match_operand:DF 1 "general_operand" "0")
3441 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3446 [(set (match_operand:DF 0 "general_operand" "=f")
3447 (div:DF (match_operand:DF 1 "general_operand" "0")
3448 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3453 [(set (match_operand:DF 0 "general_operand" "=f")
3454 (div:DF (match_operand:DF 1 "general_operand" "0")
3455 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3460 [(set (match_operand:DF 0 "general_operand" "=f")
3461 (div:DF (match_operand:DF 1 "general_operand" "0")
3462 (match_operand:DF 2 "general_operand" "fmG")))]
3466 if (REG_P (operands[2]))
3467 return \"f%&div%.x %2,%0\";
3468 return \"f%&div%.d %f2,%0\";
3471 (define_expand "divsf3"
3472 [(set (match_operand:SF 0 "general_operand" "")
3473 (div:SF (match_operand:SF 1 "general_operand" "")
3474 (match_operand:SF 2 "general_operand" "")))]
3475 "TARGET_68881 || TARGET_FPA"
3479 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3480 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3481 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3485 if (rtx_equal_p (operands[0], operands[1]))
3486 return \"fpdiv%.s %w2,%0\";
3487 if (rtx_equal_p (operands[0], operands[2]))
3488 return \"fprdiv%.s %w1,%0\";
3489 if (which_alternative == 0)
3490 return \"fpdiv3%.s %w2,%w1,%0\";
3491 return \"fpdiv3%.s %2,%1,%0\";
3495 [(set (match_operand:SF 0 "general_operand" "=f")
3496 (div:SF (match_operand:SF 1 "general_operand" "0")
3497 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3501 return (TARGET_68040_ONLY
3502 ? \"fsdiv%.l %2,%0\"
3503 : \"fsgldiv%.l %2,%0\");
3507 [(set (match_operand:SF 0 "general_operand" "=f")
3508 (div:SF (match_operand:SF 1 "general_operand" "0")
3509 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3513 return (TARGET_68040_ONLY
3514 ? \"fsdiv%.w %2,%0\"
3515 : \"fsgldiv%.w %2,%0\");
3519 [(set (match_operand:SF 0 "general_operand" "=f")
3520 (div:SF (match_operand:SF 1 "general_operand" "0")
3521 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3525 return (TARGET_68040_ONLY
3526 ? \"fsdiv%.b %2,%0\"
3527 : \"fsgldiv%.b %2,%0\");
3531 [(set (match_operand:SF 0 "general_operand" "=f")
3532 (div:SF (match_operand:SF 1 "general_operand" "0")
3533 (match_operand:SF 2 "general_operand" "fdmF")))]
3537 #ifdef FSGLDIV_USE_S
3538 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3539 return (TARGET_68040_ONLY
3540 ? \"fsdiv%.s %2,%0\"
3541 : \"fsgldiv%.s %2,%0\");
3543 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3544 return (TARGET_68040_ONLY
3545 ? \"fsdiv%.x %2,%0\"
3546 : \"fsgldiv%.x %2,%0\");
3548 return (TARGET_68040_ONLY
3549 ? \"fsdiv%.s %f2,%0\"
3550 : \"fsgldiv%.s %f2,%0\");
3553 ;; Remainder instructions.
3555 (define_insn "divmodsi4"
3556 [(set (match_operand:SI 0 "general_operand" "=d")
3557 (div:SI (match_operand:SI 1 "general_operand" "0")
3558 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3559 (set (match_operand:SI 3 "general_operand" "=d")
3560 (mod:SI (match_dup 1) (match_dup 2)))]
3561 "TARGET_68020 && !TARGET_5200"
3564 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3565 return \"divs%.l %2,%0\";
3567 return \"divsl%.l %2,%3:%0\";
3570 (define_insn "udivmodsi4"
3571 [(set (match_operand:SI 0 "general_operand" "=d")
3572 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3573 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3574 (set (match_operand:SI 3 "general_operand" "=d")
3575 (umod:SI (match_dup 1) (match_dup 2)))]
3576 "TARGET_68020 && !TARGET_5200"
3579 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3580 return \"divu%.l %2,%0\";
3582 return \"divul%.l %2,%3:%0\";
3585 (define_insn "divmodhi4"
3586 [(set (match_operand:HI 0 "general_operand" "=d")
3587 (div:HI (match_operand:HI 1 "general_operand" "0")
3588 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3589 (set (match_operand:HI 3 "general_operand" "=d")
3590 (mod:HI (match_dup 1) (match_dup 2)))]
3595 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3597 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3599 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3602 return \"move%.l %0,%3\;swap %3\";
3608 (define_insn "udivmodhi4"
3609 [(set (match_operand:HI 0 "general_operand" "=d")
3610 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3611 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3612 (set (match_operand:HI 3 "general_operand" "=d")
3613 (umod:HI (match_dup 1) (match_dup 2)))]
3618 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3620 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3622 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3625 return \"move%.l %0,%3\;swap %3\";
3631 ;; logical-and instructions
3633 ;; "anddi3" is mainly here to help combine().
3634 (define_insn "anddi3"
3635 [(set (match_operand:DI 0 "general_operand" "=o,d")
3636 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3637 (match_operand:DI 2 "general_operand" "dn,don")))]
3642 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3643 if (CONSTANT_P (operands[2]))
3647 split_double (operands[2], &hi, &lo);
3649 switch (INTVAL (hi))
3652 output_asm_insn (\"clr%.l %0\", operands);
3660 xoperands[0] = operands[0];
3662 output_asm_insn (output_andsi3 (xoperands), xoperands);
3665 if (GET_CODE (operands[0]) == REG)
3666 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3668 operands[0] = adj_offsettable_operand (operands[0], 4);
3669 switch (INTVAL (lo))
3672 output_asm_insn (\"clr%.l %0\", operands);
3680 xoperands[0] = operands[0];
3682 output_asm_insn (output_andsi3 (xoperands), xoperands);
3687 if (GET_CODE (operands[0]) != REG)
3689 operands[1] = adj_offsettable_operand (operands[0], 4);
3690 return \"and%.l %2,%0\;and%.l %R2,%1\";
3692 if (GET_CODE (operands[2]) != REG)
3694 operands[1] = adj_offsettable_operand (operands[2], 4);
3695 return \"and%.l %2,%0\;and%.l %1,%R0\";
3697 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3700 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3701 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3702 ;; can't allocate pseudos into it.
3704 (define_expand "andsi3"
3705 [(set (match_operand:SI 0 "not_sp_operand" "")
3706 (and:SI (match_operand:SI 1 "general_operand" "")
3707 (match_operand:SI 2 "general_src_operand" "")))]
3711 (define_insn "andsi3_internal"
3712 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3713 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3714 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3718 return output_andsi3 (operands);
3721 (define_insn "andsi3_5200"
3722 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3723 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3724 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3728 (define_insn "andhi3"
3729 [(set (match_operand:HI 0 "general_operand" "=m,d")
3730 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3731 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3736 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3737 (and:HI (match_dup 0)
3738 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3743 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3744 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3749 (define_insn "andqi3"
3750 [(set (match_operand:QI 0 "general_operand" "=m,d")
3751 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3752 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3757 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3758 (and:QI (match_dup 0)
3759 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3764 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3765 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3770 ;; inclusive-or instructions
3772 (define_insn "iordi_zext"
3773 [(set (match_operand:DI 0 "general_operand" "=o,d")
3774 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3775 (match_operand:DI 2 "general_operand" "0,0")))]
3782 if (GET_CODE (operands[0]) == REG)
3783 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3785 operands[0] = adj_offsettable_operand (operands[0], 4);
3786 if (GET_MODE (operands[1]) == SImode)
3787 return \"or%.l %1,%0\";
3788 byte_mode = (GET_MODE (operands[1]) == QImode);
3789 if (GET_CODE (operands[0]) == MEM)
3790 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3792 return \"or%.b %1,%0\";
3794 return \"or%.w %1,%0\";
3797 ;; "iordi3" is mainly here to help combine().
3798 (define_insn "iordi3"
3799 [(set (match_operand:DI 0 "general_operand" "=o,d")
3800 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3801 (match_operand:DI 2 "general_operand" "dn,don")))]
3806 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3807 if (CONSTANT_P (operands[2]))
3811 split_double (operands[2], &hi, &lo);
3813 switch (INTVAL (hi))
3818 /* FIXME : a scratch register would be welcome here if operand[0]
3819 is not a register */
3820 output_asm_insn (\"move%.l %#-1,%0\", operands);
3826 xoperands[0] = operands[0];
3828 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3831 if (GET_CODE (operands[0]) == REG)
3832 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3834 operands[0] = adj_offsettable_operand (operands[0], 4);
3835 switch (INTVAL (lo))
3840 /* FIXME : a scratch register would be welcome here if operand[0]
3841 is not a register */
3842 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3848 xoperands[0] = operands[0];
3850 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3855 if (GET_CODE (operands[0]) != REG)
3857 operands[1] = adj_offsettable_operand (operands[0], 4);
3858 return \"or%.l %2,%0\;or%.l %R2,%1\";
3860 if (GET_CODE (operands[2]) != REG)
3862 operands[1] = adj_offsettable_operand (operands[2], 4);
3863 return \"or%.l %2,%0\;or%.l %1,%R0\";
3865 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3868 (define_expand "iorsi3"
3869 [(set (match_operand:SI 0 "general_operand" "")
3870 (ior:SI (match_operand:SI 1 "general_operand" "")
3871 (match_operand:SI 2 "general_src_operand" "")))]
3875 (define_insn "iorsi3_internal"
3876 [(set (match_operand:SI 0 "general_operand" "=m,d")
3877 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3878 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3882 return output_iorsi3 (operands);
3885 (define_insn "iorsi3_5200"
3886 [(set (match_operand:SI 0 "general_operand" "=m,d")
3887 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3888 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3892 (define_insn "iorhi3"
3893 [(set (match_operand:HI 0 "general_operand" "=m,d")
3894 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3895 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3900 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3901 (ior:HI (match_dup 0)
3902 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3907 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3908 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3913 (define_insn "iorqi3"
3914 [(set (match_operand:QI 0 "general_operand" "=m,d")
3915 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3916 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3921 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3922 (ior:QI (match_dup 0)
3923 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3928 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3929 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3934 ;; On all 68k models, this makes faster code in a special case.
3935 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3937 (define_insn "iorsi_zexthi_ashl16"
3938 [(set (match_operand:SI 0 "general_operand" "=&d")
3939 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3940 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3946 if (GET_CODE (operands[2]) != REG)
3947 operands[2] = adj_offsettable_operand (operands[2], 2);
3948 if (GET_CODE (operands[2]) != REG
3949 || REGNO (operands[2]) != REGNO (operands[0]))
3950 output_asm_insn (\"move%.w %2,%0\", operands);
3951 return \"swap %0\;mov%.w %1,%0\";
3954 (define_insn "iorsi_zext"
3955 [(set (match_operand:SI 0 "general_operand" "=o,d")
3956 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3957 (match_operand:SI 2 "general_operand" "0,0")))]
3964 byte_mode = (GET_MODE (operands[1]) == QImode);
3965 if (GET_CODE (operands[0]) == MEM)
3966 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3968 return \"or%.b %1,%0\";
3970 return \"or%.w %1,%0\";
3975 ;; "xordi3" is mainly here to help combine().
3976 (define_insn "xordi3"
3977 [(set (match_operand:DI 0 "general_operand" "=od")
3978 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3979 (match_operand:DI 2 "general_operand" "dn")))]
3984 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3986 if (CONSTANT_P (operands[2]))
3990 split_double (operands[2], &hi, &lo);
3992 switch (INTVAL (hi))
3997 output_asm_insn (\"not%.l %0\", operands);
4000 /* FIXME : a scratch register would be welcome here if
4001 -128 <= INTVAL (hi) < -1 */
4005 xoperands[0] = operands[0];
4007 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4010 if (GET_CODE (operands[0]) == REG)
4011 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4013 operands[0] = adj_offsettable_operand (operands[0], 4);
4014 switch (INTVAL (lo))
4019 output_asm_insn (\"not%.l %0\", operands);
4022 /* FIXME : a scratch register would be welcome here if
4023 -128 <= INTVAL (lo) < -1 */
4025 /* FIXME : this should be merged with xorsi3 */
4029 xoperands[0] = operands[0];
4031 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4036 if (GET_CODE (operands[0]) != REG)
4038 operands[1] = adj_offsettable_operand (operands[0], 4);
4039 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4041 if (GET_CODE (operands[2]) != REG)
4043 operands[1] = adj_offsettable_operand (operands[2], 4);
4044 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4046 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4049 (define_expand "xorsi3"
4050 [(set (match_operand:SI 0 "general_operand" "")
4051 (xor:SI (match_operand:SI 1 "general_operand" "")
4052 (match_operand:SI 2 "general_operand" "")))]
4056 (define_insn "xorsi3_internal"
4057 [(set (match_operand:SI 0 "general_operand" "=do,m")
4058 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4059 (match_operand:SI 2 "general_operand" "di,dKT")))]
4064 return output_xorsi3 (operands);
4067 (define_insn "xorsi3_5200"
4068 [(set (match_operand:SI 0 "general_operand" "=dm,d")
4069 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4070 (match_operand:SI 2 "general_operand" "d,Ks")))]
4074 (define_insn "xorhi3"
4075 [(set (match_operand:HI 0 "general_operand" "=dm")
4076 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4077 (match_operand:HI 2 "general_operand" "dn")))]
4082 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4083 (xor:HI (match_dup 0)
4084 (match_operand:HI 1 "general_operand" "dn")))]
4089 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4090 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4095 (define_insn "xorqi3"
4096 [(set (match_operand:QI 0 "general_operand" "=dm")
4097 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4098 (match_operand:QI 2 "general_operand" "dn")))]
4103 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4104 (xor:QI (match_dup 0)
4105 (match_operand:QI 1 "general_operand" "dn")))]
4110 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4111 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4116 ;; negation instructions
4118 (define_expand "negdi2"
4119 [(set (match_operand:DI 0 "general_operand" "")
4120 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4125 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4127 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4131 (define_insn "negdi2_internal"
4132 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4133 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4137 if (which_alternative == 0)
4138 return \"neg%.l %0\;negx%.l %0\";
4139 if (GET_CODE (operands[0]) == REG)
4140 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4142 operands[1] = adj_offsettable_operand (operands[0], 4);
4143 if (ADDRESS_REG_P (operands[0]))
4144 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4146 return \"neg%.l %1\;negx%.l %0\";
4149 (define_insn "negdi2_5200"
4150 [(set (match_operand:DI 0 "general_operand" "=d")
4151 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4155 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4156 return \"neg%.l %1\;negx%.l %0\";
4159 (define_expand "negsi2"
4160 [(set (match_operand:SI 0 "general_operand" "")
4161 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4166 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4168 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4172 (define_insn "negsi2_internal"
4173 [(set (match_operand:SI 0 "general_operand" "=dm")
4174 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4178 (define_insn "negsi2_5200"
4179 [(set (match_operand:SI 0 "general_operand" "=d")
4180 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4184 (define_insn "neghi2"
4185 [(set (match_operand:HI 0 "general_operand" "=dm")
4186 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4191 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4192 (neg:HI (match_dup 0)))]
4196 (define_insn "negqi2"
4197 [(set (match_operand:QI 0 "general_operand" "=dm")
4198 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4203 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4204 (neg:QI (match_dup 0)))]
4208 ;; If using software floating point, just flip the sign bit.
4210 (define_expand "negsf2"
4211 [(set (match_operand:SF 0 "general_operand" "")
4212 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4216 if (!TARGET_FPA && !TARGET_68881)
4221 target = operand_subword_force (operands[0], 0, SFmode);
4222 result = expand_binop (SImode, xor_optab,
4223 operand_subword_force (operands[1], 0, SFmode),
4224 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4228 if (result != target)
4229 emit_move_insn (result, target);
4231 /* Make a place for REG_EQUAL. */
4232 emit_move_insn (operands[0], operands[0]);
4238 [(set (match_operand:SF 0 "general_operand" "=x,y")
4239 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4244 [(set (match_operand:SF 0 "general_operand" "=f,d")
4245 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4249 if (DATA_REG_P (operands[0]))
4251 operands[1] = GEN_INT (31);
4252 return \"bchg %1,%0\";
4254 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4255 return \"f%$neg%.x %1,%0\";
4256 return \"f%$neg%.s %f1,%0\";
4259 (define_expand "negdf2"
4260 [(set (match_operand:DF 0 "general_operand" "")
4261 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4265 if (!TARGET_FPA && !TARGET_68881)
4272 target = operand_subword (operands[0], 0, 1, DFmode);
4273 result = expand_binop (SImode, xor_optab,
4274 operand_subword_force (operands[1], 0, DFmode),
4275 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4279 if (result != target)
4280 emit_move_insn (result, target);
4282 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4283 operand_subword_force (operands[1], 1, DFmode));
4285 insns = get_insns ();
4288 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4294 [(set (match_operand:DF 0 "general_operand" "=x,y")
4295 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4300 [(set (match_operand:DF 0 "general_operand" "=f,d")
4301 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4305 if (DATA_REG_P (operands[0]))
4307 operands[1] = GEN_INT (31);
4308 return \"bchg %1,%0\";
4310 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4311 return \"f%&neg%.x %1,%0\";
4312 return \"f%&neg%.d %f1,%0\";
4315 ;; Sqrt instruction for the 68881
4317 (define_insn "sqrtsf2"
4318 [(set (match_operand:SF 0 "general_operand" "=f")
4319 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4323 if (FP_REG_P (operands[1]))
4324 return \"f%$sqrt%.x %1,%0\";
4326 return \"f%$sqrt%.s %1,%0\";
4329 (define_insn "sqrtdf2"
4330 [(set (match_operand:DF 0 "general_operand" "=f")
4331 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4335 if (FP_REG_P (operands[1]))
4336 return \"f%&sqrt%.x %1,%0\";
4338 return \"f%&sqrt%.d %1,%0\";
4341 ;; Absolute value instructions
4342 ;; If using software floating point, just zero the sign bit.
4344 (define_expand "abssf2"
4345 [(set (match_operand:SF 0 "general_operand" "")
4346 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4350 if (!TARGET_FPA && !TARGET_68881)
4355 target = operand_subword_force (operands[0], 0, SFmode);
4356 result = expand_binop (SImode, and_optab,
4357 operand_subword_force (operands[1], 0, SFmode),
4358 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4362 if (result != target)
4363 emit_move_insn (result, target);
4365 /* Make a place for REG_EQUAL. */
4366 emit_move_insn (operands[0], operands[0]);
4372 [(set (match_operand:SF 0 "general_operand" "=x,y")
4373 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4378 [(set (match_operand:SF 0 "general_operand" "=f")
4379 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4383 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4384 return \"f%$abs%.x %1,%0\";
4385 return \"f%$abs%.s %f1,%0\";
4388 (define_expand "absdf2"
4389 [(set (match_operand:DF 0 "general_operand" "")
4390 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4394 if (!TARGET_FPA && !TARGET_68881)
4401 target = operand_subword (operands[0], 0, 1, DFmode);
4402 result = expand_binop (SImode, and_optab,
4403 operand_subword_force (operands[1], 0, DFmode),
4404 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4408 if (result != target)
4409 emit_move_insn (result, target);
4411 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4412 operand_subword_force (operands[1], 1, DFmode));
4414 insns = get_insns ();
4417 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4423 [(set (match_operand:DF 0 "general_operand" "=x,y")
4424 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4429 [(set (match_operand:DF 0 "general_operand" "=f")
4430 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4434 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4435 return \"f%&abs%.x %1,%0\";
4436 return \"f%&abs%.d %f1,%0\";
4439 ;; one complement instructions
4441 ;; "one_cmpldi2" is mainly here to help combine().
4442 (define_insn "one_cmpldi2"
4443 [(set (match_operand:DI 0 "general_operand" "=dm")
4444 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4449 if (GET_CODE (operands[0]) == REG)
4450 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4451 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4452 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4453 operands[1] = operands[0];
4455 operands[1] = adj_offsettable_operand (operands[0], 4);
4456 return \"not%.l %1\;not%.l %0\";
4459 (define_expand "one_cmplsi2"
4460 [(set (match_operand:SI 0 "general_operand" "")
4461 (not:SI (match_operand:SI 1 "general_operand" "")))]
4466 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4468 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4472 (define_insn "one_cmplsi2_internal"
4473 [(set (match_operand:SI 0 "general_operand" "=dm")
4474 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4478 (define_insn "one_cmplsi2_5200"
4479 [(set (match_operand:SI 0 "general_operand" "=d")
4480 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4484 (define_insn "one_cmplhi2"
4485 [(set (match_operand:HI 0 "general_operand" "=dm")
4486 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4491 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4492 (not:HI (match_dup 0)))]
4496 (define_insn "one_cmplqi2"
4497 [(set (match_operand:QI 0 "general_operand" "=dm")
4498 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4503 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4504 (not:QI (match_dup 0)))]
4508 ;; arithmetic shift instructions
4509 ;; We don't need the shift memory by 1 bit instruction
4511 (define_insn "ashldi_extsi"
4512 [(set (match_operand:DI 0 "general_operand" "=ro")
4514 (match_operator:DI 2 "extend_operator"
4515 [(match_operand:SI 1 "general_operand" "rm")])
4521 if (GET_CODE (operands[0]) == REG)
4522 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4524 operands[2] = adj_offsettable_operand (operands[0], 4);
4525 if (ADDRESS_REG_P (operands[0]))
4526 return \"move%.l %1,%0\;sub%.l %2,%2\";
4528 return \"move%.l %1,%0\;clr%.l %2\";
4531 (define_insn "ashldi_sexthi"
4532 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4533 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4535 (clobber (match_scratch:SI 2 "=a,X"))]
4540 if (GET_CODE (operands[0]) == MEM)
4542 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4543 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4544 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4545 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4548 operands[3] = adj_offsettable_operand (operands[0], 4);
4549 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4552 else if (DATA_REG_P (operands[0]))
4553 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4555 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4558 (define_insn "ashldi_const32"
4559 [(set (match_operand:DI 0 "general_operand" "=rm")
4560 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4566 if (GET_CODE (operands[1]) == REG)
4567 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4569 operands[3] = adj_offsettable_operand (operands[1], 4);
4570 if (GET_CODE (operands[0]) == REG)
4571 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4572 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4573 return \"clr%.l %0\;move%.l %3,%0\";
4574 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4575 return \"move%.l %3,%0\;clr%.l %0\";
4577 operands[2] = adj_offsettable_operand (operands[0], 4);
4578 if (ADDRESS_REG_P (operands[2]))
4579 return \"move%.l %3,%0\;sub%.l %2,%2\";
4581 return \"move%.l %3,%0\;clr%.l %2\";
4584 ;; The predicate below must be general_operand, because ashldi3 allows that
4585 (define_insn "ashldi_const"
4586 [(set (match_operand:DI 0 "general_operand" "=d")
4587 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4588 (match_operand 2 "const_int_operand" "n")))]
4590 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4591 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4592 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4595 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4596 if (INTVAL (operands[2]) == 1)
4597 return \"add%.l %1,%1\;addx%.l %0,%0\";
4598 else if (INTVAL (operands[2]) == 8)
4599 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4600 else if (INTVAL (operands[2]) == 16)
4601 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4602 else if (INTVAL (operands[2]) == 48)
4603 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4604 else if (INTVAL (operands[2]) == 2)
4605 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4606 else if (INTVAL (operands[2]) == 3)
4607 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4608 else /* 32 < INTVAL (operands[2]) <= 63 */
4610 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4611 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4612 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4613 return \"mov%.l %1,%0\;moveq %#0,%1\";
4617 (define_expand "ashldi3"
4618 [(set (match_operand:DI 0 "general_operand" "")
4619 (ashift:DI (match_operand:DI 1 "general_operand" "")
4620 (match_operand 2 "const_int_operand" "")))]
4624 /* ??? This is a named pattern like this is not allowed to FAIL based
4626 if (GET_CODE (operands[2]) != CONST_INT
4627 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4628 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4629 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4633 ;; On most 68k models, this makes faster code in a special case.
4635 (define_insn "ashlsi_16"
4636 [(set (match_operand:SI 0 "register_operand" "=d")
4637 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4643 return \"swap %0\;clr%.w %0\";
4646 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4647 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4649 ;; On the 68000, this makes faster code in a special case.
4651 (define_insn "ashlsi_17_24"
4652 [(set (match_operand:SI 0 "register_operand" "=d")
4653 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4654 (match_operand:SI 2 "const_int_operand" "n")))]
4655 "(! TARGET_68020 && !TARGET_5200
4656 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4661 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4662 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4665 (define_insn "ashlsi3"
4666 [(set (match_operand:SI 0 "register_operand" "=d")
4667 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4668 (match_operand:SI 2 "general_operand" "dI")))]
4672 if (operands[2] == const1_rtx)
4674 cc_status.flags = CC_NO_OVERFLOW;
4675 return \"add%.l %0,%0\";
4677 return \"lsl%.l %2,%0\";
4680 (define_insn "ashlhi3"
4681 [(set (match_operand:HI 0 "register_operand" "=d")
4682 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4683 (match_operand:HI 2 "general_operand" "dI")))]
4688 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4689 (ashift:HI (match_dup 0)
4690 (match_operand:HI 1 "general_operand" "dI")))]
4694 (define_insn "ashlqi3"
4695 [(set (match_operand:QI 0 "register_operand" "=d")
4696 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4697 (match_operand:QI 2 "general_operand" "dI")))]
4702 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4703 (ashift:QI (match_dup 0)
4704 (match_operand:QI 1 "general_operand" "dI")))]
4708 ;; On most 68k models, this makes faster code in a special case.
4710 (define_insn "ashrsi_16"
4711 [(set (match_operand:SI 0 "register_operand" "=d")
4712 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4715 "swap %0\;ext%.l %0")
4717 ;; On the 68000, this makes faster code in a special case.
4720 [(set (match_operand:SI 0 "register_operand" "=d")
4721 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4722 (match_operand:SI 2 "const_int_operand" "n")))]
4723 "(! TARGET_68020 && !TARGET_5200
4724 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4727 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4728 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4731 (define_insn "subreghi1ashrdi_const32"
4732 [(set (match_operand:HI 0 "general_operand" "=rm")
4733 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4734 (const_int 32)) 1))]
4738 if (GET_CODE (operands[1]) != REG)
4739 operands[1] = adj_offsettable_operand (operands[1], 2);
4740 return \"move%.w %1,%0\";
4743 (define_insn "subregsi1ashrdi_const32"
4744 [(set (match_operand:SI 0 "general_operand" "=rm")
4745 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4746 (const_int 32)) 1))]
4750 return \"move%.l %1,%0\";
4753 (define_insn "ashrdi_const32"
4754 [(set (match_operand:DI 0 "register_operand" "=d")
4755 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4761 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4763 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4765 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4768 (define_insn "ashrdi_const32_mem"
4769 [(set (match_operand:DI 0 "general_operand" "=o,<")
4770 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4772 (clobber (match_scratch:SI 2 "=d,d"))]
4777 if (which_alternative == 1)
4778 operands[3] = operands[0];
4780 operands[3] = adj_offsettable_operand (operands[0], 4);
4782 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4784 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4787 ;; The predicate below must be general_operand, because ashrdi3 allows that
4788 (define_insn "ashrdi_const"
4789 [(set (match_operand:DI 0 "general_operand" "=d")
4790 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4791 (match_operand 2 "const_int_operand" "n")))]
4793 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4794 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4795 || INTVAL (operands[2]) == 31
4796 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4799 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4800 if (INTVAL (operands[2]) == 63)
4801 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4803 if (INTVAL (operands[2]) == 1)
4804 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4805 else if (INTVAL (operands[2]) == 8)
4806 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4807 else if (INTVAL (operands[2]) == 16)
4808 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4809 else if (INTVAL (operands[2]) == 48)
4810 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4811 else if (INTVAL (operands[2]) == 31)
4812 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4813 else if (INTVAL (operands[2]) == 2)
4814 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4815 else if (INTVAL (operands[2]) == 3)
4816 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4817 else /* 32 < INTVAL (operands[2]) <= 63 */
4819 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4820 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4821 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4822 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4823 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4824 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4828 (define_expand "ashrdi3"
4829 [(set (match_operand:DI 0 "general_operand" "")
4830 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4831 (match_operand 2 "const_int_operand" "")))]
4835 /* ??? This is a named pattern like this is not allowed to FAIL based
4837 if (GET_CODE (operands[2]) != CONST_INT
4838 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4839 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4840 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4844 ;; On all 68k models, this makes faster code in a special case.
4846 (define_insn "ashrsi_31"
4847 [(set (match_operand:SI 0 "register_operand" "=d")
4848 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4853 return \"add%.l %0,%0\;subx%.l %0,%0\";
4856 (define_insn "ashrsi3"
4857 [(set (match_operand:SI 0 "register_operand" "=d")
4858 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4859 (match_operand:SI 2 "general_operand" "dI")))]
4863 (define_insn "ashrhi3"
4864 [(set (match_operand:HI 0 "register_operand" "=d")
4865 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4866 (match_operand:HI 2 "general_operand" "dI")))]
4871 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4872 (ashiftrt:HI (match_dup 0)
4873 (match_operand:HI 1 "general_operand" "dI")))]
4877 (define_insn "ashrqi3"
4878 [(set (match_operand:QI 0 "register_operand" "=d")
4879 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4880 (match_operand:QI 2 "general_operand" "dI")))]
4885 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4886 (ashiftrt:QI (match_dup 0)
4887 (match_operand:QI 1 "general_operand" "dI")))]
4891 ;; logical shift instructions
4893 ;; commented out because of reload problems in 950612-1.c
4896 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4897 ;; (const_int 32)) 1))
4898 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4899 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4900 ;; (const_int 32)) 1))]
4904 ;; return \"move%.l %0,%1\";
4909 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4910 ;; (const_int 32)) 0))
4911 ;; (set (match_operand:DI 1 "general_operand" "=do")
4912 ;; (lshiftrt:DI (match_dup 0)
4913 ;; (const_int 32)))]
4917 ;; if (GET_CODE (operands[1]) == REG)
4918 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4920 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4921 ;; return \"move%.l %0,%2\;clr%.l %1\";
4924 (define_insn "subreg1lshrdi_const32"
4925 [(set (match_operand:SI 0 "general_operand" "=rm")
4926 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4927 (const_int 32)) 1))]
4931 return \"move%.l %1,%0\";
4934 (define_insn "lshrdi_const32"
4935 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4936 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4942 if (which_alternative == 1)
4943 return \"move%.l %1,%0\;clr%.l %0\";
4944 if (which_alternative == 2)
4945 return \"clr%.l %0\;move%.l %1,%0\";
4946 if (GET_CODE (operands[0]) == REG)
4947 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4949 operands[2] = adj_offsettable_operand (operands[0], 4);
4950 if (GET_CODE (operands[1]) == REG)
4951 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4953 operands[3] = adj_offsettable_operand (operands[1], 4);
4954 if (ADDRESS_REG_P (operands[0]))
4955 return \"move%.l %1,%2\;sub%.l %0,%0\";
4957 return \"move%.l %1,%2\;clr%.l %0\";
4960 ;; The predicate below must be general_operand, because lshrdi3 allows that
4961 (define_insn "lshrdi_const"
4962 [(set (match_operand:DI 0 "general_operand" "=d")
4963 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4964 (match_operand 2 "const_int_operand" "n")))]
4966 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4967 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4968 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4971 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4972 if (INTVAL (operands[2]) == 63)
4973 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4975 if (INTVAL (operands[2]) == 1)
4976 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4977 else if (INTVAL (operands[2]) == 8)
4978 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4979 else if (INTVAL (operands[2]) == 16)
4980 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4981 else if (INTVAL (operands[2]) == 48)
4982 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4983 else if (INTVAL (operands[2]) == 2)
4984 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4985 else if (INTVAL (operands[2]) == 3)
4986 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4987 else /* 32 < INTVAL (operands[2]) <= 63 */
4989 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4990 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4991 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4992 return \"mov%.l %0,%1\;moveq %#0,%0\";
4996 (define_expand "lshrdi3"
4997 [(set (match_operand:DI 0 "general_operand" "")
4998 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4999 (match_operand 2 "const_int_operand" "")))]
5003 /* ??? This is a named pattern like this is not allowed to FAIL based
5005 if (GET_CODE (operands[2]) != CONST_INT
5006 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5007 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5008 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5012 ;; On all 68k models, this makes faster code in a special case.
5014 (define_insn "lshrsi_31"
5015 [(set (match_operand:SI 0 "register_operand" "=d")
5016 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5021 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
5024 ;; On most 68k models, this makes faster code in a special case.
5026 (define_insn "lshrsi_16"
5027 [(set (match_operand:SI 0 "register_operand" "=d")
5028 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5034 return \"clr%.w %0\;swap %0\";
5037 ;; On the 68000, this makes faster code in a special case.
5039 (define_insn "lshrsi_17_24"
5040 [(set (match_operand:SI 0 "register_operand" "=d")
5041 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5042 (match_operand:SI 2 "const_int_operand" "n")))]
5043 "(! TARGET_68020 && !TARGET_5200
5044 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
5047 /* I think lsr%.w sets the CC properly. */
5048 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5049 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5052 (define_insn "lshrsi3"
5053 [(set (match_operand:SI 0 "register_operand" "=d")
5054 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5055 (match_operand:SI 2 "general_operand" "dI")))]
5059 (define_insn "lshrhi3"
5060 [(set (match_operand:HI 0 "register_operand" "=d")
5061 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5062 (match_operand:HI 2 "general_operand" "dI")))]
5067 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5068 (lshiftrt:HI (match_dup 0)
5069 (match_operand:HI 1 "general_operand" "dI")))]
5073 (define_insn "lshrqi3"
5074 [(set (match_operand:QI 0 "register_operand" "=d")
5075 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5076 (match_operand:QI 2 "general_operand" "dI")))]
5081 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5082 (lshiftrt:QI (match_dup 0)
5083 (match_operand:QI 1 "general_operand" "dI")))]
5087 ;; rotate instructions
5089 (define_insn "rotlsi3"
5090 [(set (match_operand:SI 0 "register_operand" "=d")
5091 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5092 (match_operand:SI 2 "general_operand" "dINO")))]
5096 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5098 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5100 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5101 return \"ror%.l %2,%0\";
5104 return \"rol%.l %2,%0\";
5107 (define_insn "rotlhi3"
5108 [(set (match_operand:HI 0 "register_operand" "=d")
5109 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5110 (match_operand:HI 2 "general_operand" "dIP")))]
5114 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5116 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5117 return \"ror%.w %2,%0\";
5120 return \"rol%.w %2,%0\";
5124 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5125 (rotate:HI (match_dup 0)
5126 (match_operand:HI 1 "general_operand" "dIP")))]
5130 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5132 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5133 return \"ror%.w %2,%0\";
5136 return \"rol%.w %2,%0\";
5139 (define_insn "rotlqi3"
5140 [(set (match_operand:QI 0 "register_operand" "=d")
5141 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5142 (match_operand:QI 2 "general_operand" "dI")))]
5146 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5148 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5149 return \"ror%.b %2,%0\";
5152 return \"rol%.b %2,%0\";
5156 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5157 (rotate:QI (match_dup 0)
5158 (match_operand:QI 1 "general_operand" "dI")))]
5162 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5164 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5165 return \"ror%.b %2,%0\";
5168 return \"rol%.b %2,%0\";
5171 (define_insn "rotrsi3"
5172 [(set (match_operand:SI 0 "register_operand" "=d")
5173 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5174 (match_operand:SI 2 "general_operand" "dI")))]
5178 (define_insn "rotrhi3"
5179 [(set (match_operand:HI 0 "register_operand" "=d")
5180 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5181 (match_operand:HI 2 "general_operand" "dI")))]
5186 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5187 (rotatert:HI (match_dup 0)
5188 (match_operand:HI 1 "general_operand" "dI")))]
5192 (define_insn "rotrqi3"
5193 [(set (match_operand:QI 0 "register_operand" "=d")
5194 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5195 (match_operand:QI 2 "general_operand" "dI")))]
5200 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5201 (rotatert:QI (match_dup 0)
5202 (match_operand:QI 1 "general_operand" "dI")))]
5207 ;; Bit set/clear in memory byte.
5209 ;; set bit, bit number is int
5210 (define_insn "bsetmemqi"
5211 [(set (match_operand:QI 0 "memory_operand" "+m")
5212 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5213 (match_operand:SI 1 "general_operand" "d")) 0)
5219 return \"bset %1,%0\";
5222 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5224 [(set (match_operand:QI 0 "memory_operand" "+m")
5225 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5226 (match_operator:SI 2 "extend_operator"
5227 [(match_operand 1 "general_operand" "d")])) 0)
5233 return \"bset %1,%0\";
5236 ;; clear bit, bit number is int
5237 (define_insn "bclrmemqi"
5238 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5240 (minus:SI (const_int 7)
5241 (match_operand:SI 1 "general_operand" "d")))
5247 return \"bclr %1,%0\";
5250 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5252 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5254 (minus:SI (const_int 7)
5255 (match_operator:SI 2 "extend_operator"
5256 [(match_operand 1 "general_operand" "d")])))
5262 return \"bclr %1,%0\";
5265 ;; Special cases of bit-field insns which we should
5266 ;; recognize in preference to the general case.
5267 ;; These handle aligned 8-bit and 16-bit fields,
5268 ;; which can usually be done with move instructions.
5271 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5272 ; alignment of structure members is specified.
5274 ; The move is allowed to be odd byte aligned, because that's still faster
5275 ; than an odd byte aligned bit field instruction.
5278 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5280 (match_operand:SI 1 "const_int_operand" "n"))
5281 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5282 "TARGET_68020 && TARGET_BITFIELD
5283 && (INTVAL (operands[1]) % 8) == 0
5284 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5288 = adj_offsettable_operand (operands[0], INTVAL (operands[1]) / 8);
5290 return \"move%.l %2,%0\";
5294 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5295 (match_operand:SI 1 "const_int_operand" "n")
5296 (match_operand:SI 2 "const_int_operand" "n"))
5297 (match_operand:SI 3 "register_operand" "d"))]
5298 "TARGET_68020 && TARGET_BITFIELD
5299 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5300 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5301 && (GET_CODE (operands[0]) == REG
5302 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5305 if (REG_P (operands[0]))
5307 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5308 return \"bfins %3,%0{%b2:%b1}\";
5312 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5314 if (GET_CODE (operands[3]) == MEM)
5315 operands[3] = adj_offsettable_operand (operands[3],
5316 (32 - INTVAL (operands[1])) / 8);
5317 if (INTVAL (operands[1]) == 8)
5318 return \"move%.b %3,%0\";
5319 return \"move%.w %3,%0\";
5324 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5325 ; alignment of structure members is specified.
5327 ; The move is allowed to be odd byte aligned, because that's still faster
5328 ; than an odd byte aligned bit field instruction.
5331 [(set (match_operand:SI 0 "general_operand" "=rm")
5332 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5334 (match_operand:SI 2 "const_int_operand" "n")))]
5335 "TARGET_68020 && TARGET_BITFIELD
5336 && (INTVAL (operands[2]) % 8) == 0
5337 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5341 = adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
5343 return \"move%.l %1,%0\";
5347 [(set (match_operand:SI 0 "general_operand" "=&d")
5348 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5349 (match_operand:SI 2 "const_int_operand" "n")
5350 (match_operand:SI 3 "const_int_operand" "n")))]
5351 "TARGET_68020 && TARGET_BITFIELD
5352 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5353 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5354 && (GET_CODE (operands[1]) == REG
5355 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5358 cc_status.flags |= CC_NOT_NEGATIVE;
5359 if (REG_P (operands[1]))
5361 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5362 return \"bfextu %1{%b3:%b2},%0\";
5366 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5368 output_asm_insn (\"clr%.l %0\", operands);
5369 if (GET_CODE (operands[0]) == MEM)
5370 operands[0] = adj_offsettable_operand (operands[0],
5371 (32 - INTVAL (operands[1])) / 8);
5372 if (INTVAL (operands[2]) == 8)
5373 return \"move%.b %1,%0\";
5374 return \"move%.w %1,%0\";
5378 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5379 ; alignment of structure members is specified.
5381 ; The move is allowed to be odd byte aligned, because that's still faster
5382 ; than an odd byte aligned bit field instruction.
5385 [(set (match_operand:SI 0 "general_operand" "=rm")
5386 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5388 (match_operand:SI 2 "const_int_operand" "n")))]
5389 "TARGET_68020 && TARGET_BITFIELD
5390 && (INTVAL (operands[2]) % 8) == 0
5391 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5395 = adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
5397 return \"move%.l %1,%0\";
5401 [(set (match_operand:SI 0 "general_operand" "=d")
5402 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5403 (match_operand:SI 2 "const_int_operand" "n")
5404 (match_operand:SI 3 "const_int_operand" "n")))]
5405 "TARGET_68020 && TARGET_BITFIELD
5406 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5407 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5408 && (GET_CODE (operands[1]) == REG
5409 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5412 if (REG_P (operands[1]))
5414 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5415 return \"bfexts %1{%b3:%b2},%0\";
5419 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5421 if (INTVAL (operands[2]) == 8)
5422 return \"move%.b %1,%0\;extb%.l %0\";
5423 return \"move%.w %1,%0\;ext%.l %0\";
5426 ;; Bit field instructions, general cases.
5427 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5428 ;; so that its address is reloaded.
5430 (define_expand "extv"
5431 [(set (match_operand:SI 0 "general_operand" "")
5432 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5433 (match_operand:SI 2 "general_operand" "")
5434 (match_operand:SI 3 "general_operand" "")))]
5435 "TARGET_68020 && TARGET_BITFIELD"
5439 [(set (match_operand:SI 0 "general_operand" "=d")
5440 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5441 (match_operand:SI 2 "general_operand" "di")
5442 (match_operand:SI 3 "general_operand" "di")))]
5443 "TARGET_68020 && TARGET_BITFIELD"
5444 "bfexts %1{%b3:%b2},%0")
5446 (define_expand "extzv"
5447 [(set (match_operand:SI 0 "general_operand" "")
5448 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5449 (match_operand:SI 2 "general_operand" "")
5450 (match_operand:SI 3 "general_operand" "")))]
5451 "TARGET_68020 && TARGET_BITFIELD"
5455 [(set (match_operand:SI 0 "general_operand" "=d,d")
5456 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5457 (match_operand:SI 2 "general_operand" "di,di")
5458 (match_operand:SI 3 "general_operand" "di,di")))]
5459 "TARGET_68020 && TARGET_BITFIELD"
5462 if (GET_CODE (operands[2]) == CONST_INT)
5464 if (INTVAL (operands[2]) != 32)
5465 cc_status.flags |= CC_NOT_NEGATIVE;
5471 return \"bfextu %1{%b3:%b2},%0\";
5475 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5476 (match_operand:SI 1 "general_operand" "di")
5477 (match_operand:SI 2 "general_operand" "di"))
5478 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5479 (match_operand 3 "const_int_operand" "n")))]
5480 "TARGET_68020 && TARGET_BITFIELD
5481 && (INTVAL (operands[3]) == -1
5482 || (GET_CODE (operands[1]) == CONST_INT
5483 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5487 return \"bfchg %0{%b2:%b1}\";
5491 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5492 (match_operand:SI 1 "general_operand" "di")
5493 (match_operand:SI 2 "general_operand" "di"))
5495 "TARGET_68020 && TARGET_BITFIELD"
5499 return \"bfclr %0{%b2:%b1}\";
5503 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5504 (match_operand:SI 1 "general_operand" "di")
5505 (match_operand:SI 2 "general_operand" "di"))
5507 "TARGET_68020 && TARGET_BITFIELD"
5511 return \"bfset %0{%b2:%b1}\";
5514 (define_expand "insv"
5515 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5516 (match_operand:SI 1 "general_operand" "")
5517 (match_operand:SI 2 "general_operand" ""))
5518 (match_operand:SI 3 "register_operand" ""))]
5519 "TARGET_68020 && TARGET_BITFIELD"
5523 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5524 (match_operand:SI 1 "general_operand" "di")
5525 (match_operand:SI 2 "general_operand" "di"))
5526 (match_operand:SI 3 "register_operand" "d"))]
5527 "TARGET_68020 && TARGET_BITFIELD"
5528 "bfins %3,%0{%b2:%b1}")
5530 ;; Now recognize bit field insns that operate on registers
5531 ;; (or at least were intended to do so).
5534 [(set (match_operand:SI 0 "general_operand" "=d")
5535 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5536 (match_operand:SI 2 "general_operand" "di")
5537 (match_operand:SI 3 "general_operand" "di")))]
5538 "TARGET_68020 && TARGET_BITFIELD"
5539 "bfexts %1{%b3:%b2},%0")
5542 [(set (match_operand:SI 0 "general_operand" "=d")
5543 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5544 (match_operand:SI 2 "general_operand" "di")
5545 (match_operand:SI 3 "general_operand" "di")))]
5546 "TARGET_68020 && TARGET_BITFIELD"
5549 if (GET_CODE (operands[2]) == CONST_INT)
5551 if (INTVAL (operands[2]) != 32)
5552 cc_status.flags |= CC_NOT_NEGATIVE;
5558 return \"bfextu %1{%b3:%b2},%0\";
5562 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5563 (match_operand:SI 1 "general_operand" "di")
5564 (match_operand:SI 2 "general_operand" "di"))
5566 "TARGET_68020 && TARGET_BITFIELD"
5570 return \"bfclr %0{%b2:%b1}\";
5574 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5575 (match_operand:SI 1 "general_operand" "di")
5576 (match_operand:SI 2 "general_operand" "di"))
5578 "TARGET_68020 && TARGET_BITFIELD"
5582 return \"bfset %0{%b2:%b1}\";
5586 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5587 (match_operand:SI 1 "general_operand" "di")
5588 (match_operand:SI 2 "general_operand" "di"))
5589 (match_operand:SI 3 "register_operand" "d"))]
5590 "TARGET_68020 && TARGET_BITFIELD"
5594 /* These special cases are now recognized by a specific pattern. */
5595 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5596 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5597 return \"move%.w %3,%0\";
5598 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5599 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5600 return \"move%.b %3,%0\";
5602 return \"bfins %3,%0{%b2:%b1}\";
5605 ;; Special patterns for optimizing bit-field instructions.
5609 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5610 (match_operand:SI 1 "const_int_operand" "n")
5611 (match_operand:SI 2 "general_operand" "di")))]
5612 "TARGET_68020 && TARGET_BITFIELD"
5615 if (operands[1] == const1_rtx
5616 && GET_CODE (operands[2]) == CONST_INT)
5618 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5619 return output_btst (operands,
5620 GEN_INT (width - INTVAL (operands[2])),
5621 operands[0], insn, 1000);
5622 /* Pass 1000 as SIGNPOS argument so that btst will
5623 not think we are testing the sign bit for an `and'
5624 and assume that nonzero implies a negative result. */
5626 if (INTVAL (operands[1]) != 32)
5627 cc_status.flags = CC_NOT_NEGATIVE;
5628 return \"bftst %0{%b2:%b1}\";
5632 ;;; now handle the register cases
5635 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5636 (match_operand:SI 1 "const_int_operand" "n")
5637 (match_operand:SI 2 "general_operand" "di")))]
5638 "TARGET_68020 && TARGET_BITFIELD"
5641 if (operands[1] == const1_rtx
5642 && GET_CODE (operands[2]) == CONST_INT)
5644 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5645 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5646 operands[0], insn, 1000);
5647 /* Pass 1000 as SIGNPOS argument so that btst will
5648 not think we are testing the sign bit for an `and'
5649 and assume that nonzero implies a negative result. */
5651 if (INTVAL (operands[1]) != 32)
5652 cc_status.flags = CC_NOT_NEGATIVE;
5653 return \"bftst %0{%b2:%b1}\";
5656 (define_insn "scc0_di"
5657 [(set (match_operand:QI 0 "general_operand" "=dm")
5658 (match_operator 1 "valid_dbcc_comparison_p"
5659 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5663 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5666 (define_insn "scc0_di_5200"
5667 [(set (match_operand:QI 0 "general_operand" "=d")
5668 (match_operator 1 "valid_dbcc_comparison_p"
5669 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5673 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5676 (define_insn "scc_di"
5677 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5678 (match_operator 1 "valid_dbcc_comparison_p"
5679 [(match_operand:DI 2 "general_operand" "ro,r")
5680 (match_operand:DI 3 "general_operand" "r,ro")]))]
5684 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5687 (define_insn "scc_di_5200"
5688 [(set (match_operand:QI 0 "general_operand" "=d,d")
5689 (match_operator 1 "valid_dbcc_comparison_p"
5690 [(match_operand:DI 2 "general_operand" "ro,r")
5691 (match_operand:DI 3 "general_operand" "r,ro")]))]
5695 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5698 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5699 ;; memory, but we cannot allow it to be in memory in case the address
5700 ;; needs to be reloaded.
5702 (define_expand "seq"
5703 [(set (match_operand:QI 0 "register_operand" "")
5704 (eq:QI (cc0) (const_int 0)))]
5708 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5710 m68k_last_compare_had_fp_operands = 0;
5716 [(set (match_operand:QI 0 "register_operand" "=d")
5717 (eq:QI (cc0) (const_int 0)))]
5720 cc_status = cc_prev_status;
5721 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5724 (define_expand "sne"
5725 [(set (match_operand:QI 0 "register_operand" "")
5726 (ne:QI (cc0) (const_int 0)))]
5730 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5732 m68k_last_compare_had_fp_operands = 0;
5738 [(set (match_operand:QI 0 "register_operand" "=d")
5739 (ne:QI (cc0) (const_int 0)))]
5742 cc_status = cc_prev_status;
5743 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5746 (define_expand "sgt"
5747 [(set (match_operand:QI 0 "register_operand" "")
5748 (gt:QI (cc0) (const_int 0)))]
5752 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5754 m68k_last_compare_had_fp_operands = 0;
5760 [(set (match_operand:QI 0 "register_operand" "=d")
5761 (gt:QI (cc0) (const_int 0)))]
5764 cc_status = cc_prev_status;
5765 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5768 (define_expand "sgtu"
5769 [(set (match_operand:QI 0 "register_operand" "")
5770 (gtu:QI (cc0) (const_int 0)))]
5775 [(set (match_operand:QI 0 "register_operand" "=d")
5776 (gtu:QI (cc0) (const_int 0)))]
5779 cc_status = cc_prev_status;
5780 return \"shi %0\"; ")
5782 (define_expand "slt"
5783 [(set (match_operand:QI 0 "register_operand" "")
5784 (lt:QI (cc0) (const_int 0)))]
5788 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5790 m68k_last_compare_had_fp_operands = 0;
5796 [(set (match_operand:QI 0 "register_operand" "=d")
5797 (lt:QI (cc0) (const_int 0)))]
5800 cc_status = cc_prev_status;
5801 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5803 (define_expand "sltu"
5804 [(set (match_operand:QI 0 "register_operand" "")
5805 (ltu:QI (cc0) (const_int 0)))]
5810 [(set (match_operand:QI 0 "register_operand" "=d")
5811 (ltu:QI (cc0) (const_int 0)))]
5814 cc_status = cc_prev_status;
5815 return \"scs %0\"; ")
5817 (define_expand "sge"
5818 [(set (match_operand:QI 0 "register_operand" "")
5819 (ge:QI (cc0) (const_int 0)))]
5823 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5825 m68k_last_compare_had_fp_operands = 0;
5831 [(set (match_operand:QI 0 "register_operand" "=d")
5832 (ge:QI (cc0) (const_int 0)))]
5835 cc_status = cc_prev_status;
5836 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5838 (define_expand "sgeu"
5839 [(set (match_operand:QI 0 "register_operand" "")
5840 (geu:QI (cc0) (const_int 0)))]
5845 [(set (match_operand:QI 0 "register_operand" "=d")
5846 (geu:QI (cc0) (const_int 0)))]
5849 cc_status = cc_prev_status;
5850 return \"scc %0\"; ")
5852 (define_expand "sle"
5853 [(set (match_operand:QI 0 "register_operand" "")
5854 (le:QI (cc0) (const_int 0)))]
5858 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5860 m68k_last_compare_had_fp_operands = 0;
5866 [(set (match_operand:QI 0 "register_operand" "=d")
5867 (le:QI (cc0) (const_int 0)))]
5870 cc_status = cc_prev_status;
5871 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5874 (define_expand "sleu"
5875 [(set (match_operand:QI 0 "register_operand" "")
5876 (leu:QI (cc0) (const_int 0)))]
5881 [(set (match_operand:QI 0 "register_operand" "=d")
5882 (leu:QI (cc0) (const_int 0)))]
5885 cc_status = cc_prev_status;
5886 return \"sls %0\"; ")
5888 ;; Basic conditional jump instructions.
5890 (define_insn "beq0_di"
5892 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5894 (label_ref (match_operand 1 "" ","))
5896 (clobber (match_scratch:SI 2 "=d,d"))]
5901 if (which_alternative == 1)
5903 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5905 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5907 if ((cc_prev_status.value1
5908 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5909 || (cc_prev_status.value2
5910 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5912 cc_status = cc_prev_status;
5914 return \"jbeq %l1\";
5919 if (GET_CODE (operands[0]) == REG)
5920 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5922 operands[3] = adj_offsettable_operand (operands[0], 4);
5923 if (! ADDRESS_REG_P (operands[0]))
5925 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5927 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5930 return \"or%.l %0,%2\;jbeq %l1\";
5932 return \"or%.l %0,%2\;jeq %l1\";
5938 return \"or%.l %3,%2\;jbeq %l1\";
5940 return \"or%.l %3,%2\;jeq %l1\";
5945 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5947 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5950 operands[4] = gen_label_rtx();
5951 if (TARGET_68020 || TARGET_5200)
5954 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5956 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5962 #ifdef SGS_CMP_ORDER
5963 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5965 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5968 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5971 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5972 CODE_LABEL_NUMBER (operands[4]));
5976 (define_insn "bne0_di"
5978 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5980 (label_ref (match_operand 1 "" ","))
5982 (clobber (match_scratch:SI 2 "=d,X"))]
5986 if ((cc_prev_status.value1
5987 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5988 || (cc_prev_status.value2
5989 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5991 cc_status = cc_prev_status;
5993 return \"jbne %l1\";
5999 if (GET_CODE (operands[0]) == REG)
6000 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6002 operands[3] = adj_offsettable_operand (operands[0], 4);
6003 if (!ADDRESS_REG_P (operands[0]))
6005 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6007 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6010 return \"or%.l %0,%2\;jbne %l1\";
6012 return \"or%.l %0,%2\;jne %l1\";
6018 return \"or%.l %3,%2\;jbne %l1\";
6020 return \"or%.l %3,%2\;jne %l1\";
6025 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6027 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6030 if (TARGET_68020 || TARGET_5200)
6033 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6035 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6041 #ifdef SGS_CMP_ORDER
6042 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6044 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6047 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6052 (define_insn "bge0_di"
6054 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6056 (label_ref (match_operand 1 "" ""))
6061 if ((cc_prev_status.value1
6062 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6063 || (cc_prev_status.value2
6064 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6066 cc_status = cc_prev_status;
6067 if (cc_status.flags & CC_REVERSED)
6070 return \"jble %l1\";
6078 return \"jbpl %l1\";
6085 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6086 output_asm_insn(\"tst%.l %0\", operands);
6089 /* On an address reg, cmpw may replace cmpl. */
6090 #ifdef SGS_CMP_ORDER
6091 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6093 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6098 return \"jbpl %l1\";
6104 (define_insn "blt0_di"
6106 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6108 (label_ref (match_operand 1 "" ""))
6113 if ((cc_prev_status.value1
6114 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6115 || (cc_prev_status.value2
6116 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6118 cc_status = cc_prev_status;
6119 if (cc_status.flags & CC_REVERSED)
6122 return \"jbgt %l1\";
6130 return \"jbmi %l1\";
6137 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6138 output_asm_insn(\"tst%.l %0\", operands);
6141 /* On an address reg, cmpw may replace cmpl. */
6142 #ifdef SGS_CMP_ORDER
6143 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6145 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6150 return \"jbmi %l1\";
6158 (if_then_else (eq (cc0)
6160 (label_ref (match_operand 0 "" ""))
6166 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6168 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6174 (if_then_else (ne (cc0)
6176 (label_ref (match_operand 0 "" ""))
6182 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6184 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6190 (if_then_else (gt (cc0)
6192 (label_ref (match_operand 0 "" ""))
6197 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6199 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6205 (if_then_else (gtu (cc0)
6207 (label_ref (match_operand 0 "" ""))
6212 return \"jbhi %l0\";
6220 (if_then_else (lt (cc0)
6222 (label_ref (match_operand 0 "" ""))
6227 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6229 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6235 (if_then_else (ltu (cc0)
6237 (label_ref (match_operand 0 "" ""))
6242 return \"jbcs %l0\";
6250 (if_then_else (ge (cc0)
6252 (label_ref (match_operand 0 "" ""))
6257 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6259 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6265 (if_then_else (geu (cc0)
6267 (label_ref (match_operand 0 "" ""))
6272 return \"jbcc %l0\";
6280 (if_then_else (le (cc0)
6282 (label_ref (match_operand 0 "" ""))
6287 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6289 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6295 (if_then_else (leu (cc0)
6297 (label_ref (match_operand 0 "" ""))
6302 return \"jbls %l0\";
6308 ;; Negated conditional jump instructions.
6312 (if_then_else (eq (cc0)
6315 (label_ref (match_operand 0 "" ""))))]
6320 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6322 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6328 (if_then_else (ne (cc0)
6331 (label_ref (match_operand 0 "" ""))))]
6336 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6338 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6344 (if_then_else (gt (cc0)
6347 (label_ref (match_operand 0 "" ""))))]
6351 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6353 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6359 (if_then_else (gtu (cc0)
6362 (label_ref (match_operand 0 "" ""))))]
6366 return \"jbls %l0\";
6374 (if_then_else (lt (cc0)
6377 (label_ref (match_operand 0 "" ""))))]
6381 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6383 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6389 (if_then_else (ltu (cc0)
6392 (label_ref (match_operand 0 "" ""))))]
6396 return \"jbcc %l0\";
6404 (if_then_else (ge (cc0)
6407 (label_ref (match_operand 0 "" ""))))]
6411 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6413 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6419 (if_then_else (geu (cc0)
6422 (label_ref (match_operand 0 "" ""))))]
6426 return \"jbcs %l0\";
6434 (if_then_else (le (cc0)
6437 (label_ref (match_operand 0 "" ""))))]
6441 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6443 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6449 (if_then_else (leu (cc0)
6452 (label_ref (match_operand 0 "" ""))))]
6456 return \"jbhi %l0\";
6462 ;; Unconditional and other jump instructions
6465 (label_ref (match_operand 0 "" "")))]
6469 return \"jbra %l0\";
6475 ;; We support two different ways of handling dispatch tables.
6476 ;; The NeXT uses absolute tables, and other machines use relative.
6477 ;; This define_expand can generate either kind.
6478 (define_expand "tablejump"
6479 [(parallel [(set (pc) (match_operand 0 "" ""))
6480 (use (label_ref (match_operand 1 "" "")))])]
6484 #ifdef CASE_VECTOR_PC_RELATIVE
6485 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6486 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6490 ;; Jump to variable address from dispatch table of absolute addresses.
6492 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6493 (use (label_ref (match_operand 1 "" "")))]
6497 return \"jmp (%0)\";
6503 ;; Jump to variable address from dispatch table of relative addresses.
6507 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6508 (use (label_ref (match_operand 1 "" "")))]
6511 #ifdef ASM_RETURN_CASE_JUMP
6512 ASM_RETURN_CASE_JUMP;
6515 #ifdef ASM_OUTPUT_CASE_LABEL
6517 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6519 return \"jmp 6(%%pc,%0.w)\";
6524 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6526 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6527 #endif /* end !CRDS */
6532 return \"jmp 2(pc,%0.w)\";
6534 return \"jmp 2(%%pc,%0.w)\";
6535 #endif /* end !CRDS */
6542 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6544 return \"extl %0\;jmp pc@(2,%0:l)\";
6550 return \"jmp (2,pc,%0.w)\";
6552 return \"jmp pc@(2,%0:w)\";
6559 ;; Decrement-and-branch insns.
6563 (ne (match_operand:HI 0 "general_operand" "+d*g")
6565 (label_ref (match_operand 1 "" ""))
6568 (plus:HI (match_dup 0)
6574 if (DATA_REG_P (operands[0]))
6575 return \"dbra %0,%l1\";
6576 if (GET_CODE (operands[0]) == MEM)
6580 return \"sub%.w %#1,%0\;jbcc %l1\";
6582 return \"subq%.w %#1,%0\;jbcc %l1\";
6584 #else /* not MOTOROLA */
6585 return \"subqw %#1,%0\;jcc %l1\";
6589 #ifdef SGS_CMP_ORDER
6591 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6593 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6595 #else /* not SGS_CMP_ORDER */
6596 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6598 #else /* not MOTOROLA */
6599 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6606 (ne (match_operand:SI 0 "general_operand" "+d*g")
6608 (label_ref (match_operand 1 "" ""))
6611 (plus:SI (match_dup 0)
6619 if (DATA_REG_P (operands[0]))
6620 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6621 if (GET_CODE (operands[0]) == MEM)
6622 return \"sub%.l %#1,%0\;jbcc %l1\";
6624 if (DATA_REG_P (operands[0]))
6625 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6626 if (GET_CODE (operands[0]) == MEM)
6627 return \"subq%.l %#1,%0\;jbcc %l1\";
6628 #endif /* NO_ADDSUB_Q */
6629 #ifdef SGS_CMP_ORDER
6631 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6633 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6635 #else /* not SGS_CMP_ORDER */
6636 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6637 #endif /* not SGS_CMP_ORDER */
6638 #else /* not MOTOROLA */
6639 if (DATA_REG_P (operands[0]))
6640 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6641 if (GET_CODE (operands[0]) == MEM)
6642 return \"subql %#1,%0\;jcc %l1\";
6643 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6644 #endif /* not MOTOROLA */
6647 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6652 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6655 (label_ref (match_operand 1 "" ""))
6658 (plus:HI (match_dup 0)
6660 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6666 if (DATA_REG_P (operands[0]))
6667 return \"dbra %0,%l1\";
6668 if (GET_CODE (operands[0]) == MEM)
6669 return \"sub%.w %#1,%0\;jbcc %l1\";
6671 if (DATA_REG_P (operands[0]))
6672 return \"dbra %0,%l1\";
6673 if (GET_CODE (operands[0]) == MEM)
6674 return \"subq%.w %#1,%0\;jbcc %l1\";
6676 #ifdef SGS_CMP_ORDER
6678 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6680 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6682 #else /* not SGS_CMP_ORDER */
6683 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6684 #endif /* not SGS_CMP_ORDER */
6685 #else /* not MOTOROLA */
6686 if (DATA_REG_P (operands[0]))
6687 return \"dbra %0,%l1\";
6688 if (GET_CODE (operands[0]) == MEM)
6689 return \"subqw %#1,%0\;jcc %l1\";
6690 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6691 #endif /* not MOTOROLA */
6694 (define_expand "decrement_and_branch_until_zero"
6695 [(parallel [(set (pc)
6697 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6700 (label_ref (match_operand 1 "" ""))
6703 (plus:SI (match_dup 0)
6711 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6714 (label_ref (match_operand 1 "" ""))
6717 (plus:SI (match_dup 0)
6719 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6725 if (DATA_REG_P (operands[0]))
6726 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6727 if (GET_CODE (operands[0]) == MEM)
6728 return \"sub%.l %#1,%0\;jbcc %l1\";
6730 if (DATA_REG_P (operands[0]))
6731 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6732 if (GET_CODE (operands[0]) == MEM)
6733 return \"subq%.l %#1,%0\;jbcc %l1\";
6735 #ifdef SGS_CMP_ORDER
6737 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6739 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6741 #else /* not SGS_CMP_ORDER */
6742 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6743 #endif /* not SGS_CMP_ORDER */
6744 #else /* not MOTOROLA */
6745 if (DATA_REG_P (operands[0]))
6746 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6747 if (GET_CODE (operands[0]) == MEM)
6748 return \"subql %#1,%0\;jcc %l1\";
6749 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6750 #endif /* not MOTOROLA */
6754 ;; For PIC calls, in order to be able to support
6755 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6756 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6758 ;; PIC calls are handled by loading the address of the function into a
6759 ;; register (via movsi), then emitting a register indirect call using
6760 ;; the "jsr" function call syntax.
6762 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6763 ;; operand to the jbsr statement to indicate that this call should
6764 ;; go through the PLT (why? because this is the way that Sun does it).
6766 ;; We have different patterns for PIC calls and non-PIC calls. The
6767 ;; different patterns are only used to choose the right syntax.
6769 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6770 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6771 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6772 ;; section at link time. However, all global objects reference are still
6773 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6774 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6775 ;; We need to have a way to differentiate these two different operands.
6777 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6778 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6779 ;; to be changed to recognize function calls symbol_ref operand as a valid
6780 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6781 ;; avoid the compiler to load this symbol_ref operand into a register.
6782 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6783 ;; since the value is a PC relative offset, not a real address.
6785 ;; All global objects are treated in the similar way as in SUN3. The only
6786 ;; difference is: on m68k svr4, the reference of such global object needs
6787 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6788 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6791 ;; Call subroutine with no return value.
6792 (define_expand "call"
6793 [(call (match_operand:QI 0 "memory_operand" "")
6794 (match_operand:SI 1 "general_operand" ""))]
6795 ;; Operand 1 not really used on the m68000.
6800 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6801 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6804 ;; This is a normal call sequence.
6806 [(call (match_operand:QI 0 "memory_operand" "o")
6807 (match_operand:SI 1 "general_operand" "g"))]
6808 ;; Operand 1 not really used on the m68000.
6812 #if defined (MOTOROLA) && !defined (USE_GAS)
6814 if (GET_CODE (operands[0]) == MEM
6815 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6824 ;; This is a PIC call sequence.
6826 [(call (match_operand:QI 0 "memory_operand" "o")
6827 (match_operand:SI 1 "general_operand" "g"))]
6828 ;; Operand 1 not really used on the m68000.
6832 if (GET_CODE (operands[0]) == MEM
6833 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6835 if (TARGET_PCREL) return \"bsr.l %o0\";
6838 return \"bsr.l %0\";
6841 return \"bsr.l %0@PLTPC\";
6843 return \"bsr %0@PLTPC\";
6848 return \"bsr.l %0\";
6850 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6851 GAS just plain ignores it. FIXME: not anymore, gas doesnt! */
6852 return \"jbsr %0,a1\";
6859 ;; Call subroutine, returning value in operand 0
6860 ;; (which must be a hard register).
6861 ;; See comments before "call" regarding PIC calls.
6862 (define_expand "call_value"
6863 [(set (match_operand 0 "" "")
6864 (call (match_operand:QI 1 "memory_operand" "")
6865 (match_operand:SI 2 "general_operand" "")))]
6866 ;; Operand 2 not really used on the m68000.
6870 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6871 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6874 ;; This is a normal call_value
6876 [(set (match_operand 0 "" "=rf")
6877 (call (match_operand:QI 1 "memory_operand" "o")
6878 (match_operand:SI 2 "general_operand" "g")))]
6879 ;; Operand 2 not really used on the m68000.
6882 #if defined (MOTOROLA) && !defined (USE_GAS)
6884 if (GET_CODE (operands[1]) == MEM
6885 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6894 ;; This is a PIC call_value
6896 [(set (match_operand 0 "" "=rf")
6897 (call (match_operand:QI 1 "memory_operand" "o")
6898 (match_operand:SI 2 "general_operand" "g")))]
6899 ;; Operand 2 not really used on the m68000.
6902 if (GET_CODE (operands[1]) == MEM
6903 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6905 if (TARGET_PCREL) return \"bsr.l %o1\";
6908 return \"bsr.l %1\";
6911 return \"bsr.l %1@PLTPC\";
6913 return \"bsr %1@PLTPC\";
6918 return \"bsr.l %1\";
6920 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6921 GAS just plain ignores it. FIXME: Not anymore, gas doesnt! */
6922 return \"jbsr %1,a1\";
6929 ;; Call subroutine returning any type.
6931 (define_expand "untyped_call"
6932 [(parallel [(call (match_operand 0 "" "")
6934 (match_operand 1 "" "")
6935 (match_operand 2 "" "")])]
6936 "NEEDS_UNTYPED_CALL"
6941 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6943 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6945 rtx set = XVECEXP (operands[2], 0, i);
6946 emit_move_insn (SET_DEST (set), SET_SRC (set));
6949 /* The optimizer does not know that the call sets the function value
6950 registers we stored in the result block. We avoid problems by
6951 claiming that all hard registers are used and clobbered at this
6953 emit_insn (gen_blockage ());
6958 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6959 ;; all of memory. This blocks insns from being moved across this point.
6961 (define_insn "blockage"
6962 [(unspec_volatile [(const_int 0)] 0)]
6971 (define_insn "probe"
6976 operands[0] = plus_constant (stack_pointer_rtx, NEED_PROBE);
6977 return \"tstl %a0\";
6980 ;; Used for frameless functions which save no regs and allocate no locals.
6981 (define_insn "return"
6986 if (current_function_pops_args == 0)
6988 operands[0] = GEN_INT (current_function_pops_args);
6992 (define_insn "indirect_jump"
6993 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6997 ;; This should not be used unless the add/sub insns can't be.
7000 [(set (match_operand:SI 0 "general_operand" "=a")
7001 (match_operand:QI 1 "address_operand" "p"))]
7006 /* Recognize an insn that refers to a table of offsets. Such an insn will
7007 need to refer to a label on the insn. So output one. Use the
7008 label-number of the table of offsets to generate this label. This code,
7009 and similar code above, assumes that there will be at most one reference
7011 if (GET_CODE (operands[1]) == PLUS
7012 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
7013 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
7015 rtx labelref = XEXP (operands[1], 1);
7016 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
7018 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
7019 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7021 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
7022 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7023 #endif /* not SGS */
7024 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
7025 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
7026 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7027 #ifdef SGS_SWITCH_TABLES
7028 /* Set flag saying we need to define the symbol
7029 LD%n (with value L%n-LI%n) at the end of the switch table. */
7030 switch_table_difference_label_flag = 1;
7031 #endif /* SGS_SWITCH_TABLES */
7032 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7034 #endif /* SGS_NO_LI */
7036 return \"lea %a1,%0\";
7039 ;; This is the first machine-dependent peephole optimization.
7040 ;; It is useful when a floating value is returned from a function call
7041 ;; and then is moved into an FP register.
7042 ;; But it is mainly intended to test the support for these optimizations.
7045 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7046 (set (match_operand:DF 0 "register_operand" "=f")
7047 (match_operand:DF 1 "register_operand" "ad"))]
7048 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7052 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7053 output_asm_insn (\"move%.l %1,%@\", xoperands);
7054 output_asm_insn (\"move%.l %1,%-\", operands);
7055 return \"fmove%.d %+,%0\";
7059 ;; Optimize a stack-adjust followed by a push of an argument.
7060 ;; This is said to happen frequently with -msoft-float
7061 ;; when there are consecutive library calls.
7064 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7065 (match_operand:SI 0 "const_int_operand" "n")))
7066 (set (match_operand:SF 1 "push_operand" "=m")
7067 (match_operand:SF 2 "general_operand" "rmfF"))]
7068 "INTVAL (operands[0]) >= 4
7069 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7072 if (INTVAL (operands[0]) > 4)
7075 xoperands[0] = stack_pointer_rtx;
7076 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7078 if (INTVAL (xoperands[1]) <= 8)
7081 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7083 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7085 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7087 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7088 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7092 if (INTVAL (xoperands[1]) <= 0x7FFF)
7095 output_asm_insn (\"add%.w %1,%0\", xoperands);
7098 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7100 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7104 output_asm_insn (\"add%.l %1,%0\", xoperands);
7106 if (FP_REG_P (operands[2]))
7107 return \"fmove%.s %2,%@\";
7108 return \"move%.l %2,%@\";
7111 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7114 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7115 (match_operand:SI 0 "const_int_operand" "n")))
7116 (set (match_operand:SI 1 "push_operand" "=m")
7117 (match_operand:SI 2 "general_operand" "g"))]
7118 "INTVAL (operands[0]) >= 4
7119 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7122 if (INTVAL (operands[0]) > 4)
7125 xoperands[0] = stack_pointer_rtx;
7126 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7128 if (INTVAL (xoperands[1]) <= 8)
7131 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7133 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7135 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7137 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7138 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7142 if (INTVAL (xoperands[1]) <= 0x7FFF)
7145 output_asm_insn (\"add%.w %1,%0\", xoperands);
7149 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7151 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7156 output_asm_insn (\"add%.l %1,%0\", xoperands);
7158 if (operands[2] == const0_rtx)
7159 return \"clr%.l %@\";
7160 return \"move%.l %2,%@\";
7163 ;; Speed up pushing a single byte but leaving four bytes of space.
7166 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7167 (match_operand:QI 1 "general_operand" "dami"))
7168 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7169 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7174 if (GET_CODE (operands[1]) == REG)
7175 return \"move%.l %1,%-\";
7177 xoperands[1] = operands[1];
7179 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7180 xoperands[3] = stack_pointer_rtx;
7182 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7184 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7189 [(set (match_operand:SI 0 "register_operand" "=d")
7191 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7192 (match_operand:HI 1 "general_operand" "rmn"))]
7193 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7196 if (GET_CODE (operands[1]) == CONST_INT)
7198 if (operands[1] == const0_rtx
7199 && (DATA_REG_P (operands[0])
7200 || GET_CODE (operands[0]) == MEM)
7201 /* clr insns on 68000 read before writing.
7202 This isn't so on the 68010, but we have no TARGET_68010. */
7203 && ((TARGET_68020 || TARGET_5200)
7204 || !(GET_CODE (operands[0]) == MEM
7205 && MEM_VOLATILE_P (operands[0]))))
7206 return \"clr%.w %0\";
7208 return \"move%.w %1,%0\";
7216 ;; jCC label ; abnormal loop termination
7217 ;; dbra dN, loop ; normal loop termination
7225 ;; Which moves the jCC condition outside the inner loop for free.
7228 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7229 [(cc0) (const_int 0)])
7230 (label_ref (match_operand 2 "" ""))
7235 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7238 (label_ref (match_operand 1 "" ""))
7241 (plus:HI (match_dup 0)
7243 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7247 output_dbcc_and_branch (operands);
7252 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7253 [(cc0) (const_int 0)])
7254 (label_ref (match_operand 2 "" ""))
7259 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7262 (label_ref (match_operand 1 "" ""))
7265 (plus:SI (match_dup 0)
7267 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7271 output_dbcc_and_branch (operands);
7276 ;; FPA multiply and add.
7278 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7279 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7280 (match_operand:DF 2 "general_operand" "xH,y,y"))
7281 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7284 fpma%.d %1,%w2,%w3,%0
7285 fpma%.d %x1,%x2,%x3,%0
7286 fpma%.d %x1,%x2,%x3,%0")
7289 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7290 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7291 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7292 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7295 fpma%.s %1,%w2,%w3,%0
7297 fpma%.s %1,%2,%3,%0")
7299 ;; FPA Multiply and subtract
7301 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7302 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7303 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7304 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7307 fpms%.d %3,%w2,%w1,%0
7308 fpms%.d %x3,%2,%x1,%0
7309 fpms%.d %x3,%2,%x1,%0")
7312 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7313 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7314 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7315 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7318 fpms%.s %3,%w2,%w1,%0
7320 fpms%.s %3,%2,%1,%0")
7323 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7324 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7325 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7326 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7329 fpmr%.d %2,%w1,%w3,%0
7330 fpmr%.d %x2,%1,%x3,%0
7331 fpmr%.d %x2,%1,%x3,%0")
7334 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7335 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7336 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7337 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7340 fpmr%.s %2,%w1,%w3,%0
7341 fpmr%.s %x2,%1,%x3,%0
7342 fpmr%.s %x2,%1,%x3,%0")
7344 ;; FPA Add and multiply
7346 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7347 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7348 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7349 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7352 fpam%.d %2,%w1,%w3,%0
7353 fpam%.d %x2,%1,%x3,%0
7354 fpam%.d %x2,%1,%x3,%0")
7357 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7358 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7359 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7360 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7363 fpam%.s %2,%w1,%w3,%0
7364 fpam%.s %x2,%1,%x3,%0
7365 fpam%.s %x2,%1,%x3,%0")
7367 ;;FPA Subtract and multiply
7369 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7370 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7371 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7372 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7375 fpsm%.d %2,%w1,%w3,%0
7376 fpsm%.d %x2,%1,%x3,%0
7377 fpsm%.d %x2,%1,%x3,%0")
7380 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7381 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7382 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7383 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7386 fpsm%.d %3,%w2,%w1,%0
7387 fpsm%.d %x3,%2,%x1,%0
7388 fpsm%.d %x3,%2,%x1,%0")
7391 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7392 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7393 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7394 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7397 fpsm%.s %2,%w1,%w3,%0
7398 fpsm%.s %x2,%1,%x3,%0
7399 fpsm%.s %x2,%1,%x3,%0")
7402 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7403 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7404 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7405 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7408 fpsm%.s %3,%w2,%w1,%0
7409 fpsm%.s %x3,%2,%x1,%0
7410 fpsm%.s %x3,%2,%x1,%0")
7412 (define_expand "tstxf"
7414 (match_operand:XF 0 "nonimmediate_operand" ""))]
7416 "m68k_last_compare_had_fp_operands = 1;")
7420 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7424 cc_status.flags = CC_IN_68881;
7425 return \"ftst%.x %0\";
7428 (define_expand "cmpxf"
7430 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7431 (match_operand:XF 1 "nonimmediate_operand" "")))]
7433 "m68k_last_compare_had_fp_operands = 1;")
7437 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7438 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7442 cc_status.flags = CC_IN_68881;
7443 #ifdef SGS_CMP_ORDER
7444 if (REG_P (operands[0]))
7446 if (REG_P (operands[1]))
7447 return \"fcmp%.x %0,%1\";
7449 return \"fcmp%.x %0,%f1\";
7451 cc_status.flags |= CC_REVERSED;
7452 return \"fcmp%.x %1,%f0\";
7454 if (REG_P (operands[0]))
7456 if (REG_P (operands[1]))
7457 return \"fcmp%.x %1,%0\";
7459 return \"fcmp%.x %f1,%0\";
7461 cc_status.flags |= CC_REVERSED;
7462 return \"fcmp%.x %f0,%1\";
7466 (define_insn "extendsfxf2"
7467 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7468 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7472 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7474 if (REGNO (operands[0]) == REGNO (operands[1]))
7476 /* Extending float to double in an fp-reg is a no-op.
7477 NOTICE_UPDATE_CC has already assumed that the
7478 cc will be set. So cancel what it did. */
7479 cc_status = cc_prev_status;
7482 return \"f%$move%.x %1,%0\";
7484 if (FP_REG_P (operands[0]))
7486 if (FP_REG_P (operands[1]))
7487 return \"f%$move%.x %1,%0\";
7488 else if (ADDRESS_REG_P (operands[1]))
7489 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7490 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7491 return output_move_const_single (operands);
7492 return \"f%$move%.s %f1,%0\";
7494 return \"fmove%.x %f1,%0\";
7498 (define_insn "extenddfxf2"
7499 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7501 (match_operand:DF 1 "general_operand" "f,rmE")))]
7505 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7507 if (REGNO (operands[0]) == REGNO (operands[1]))
7509 /* Extending float to double in an fp-reg is a no-op.
7510 NOTICE_UPDATE_CC has already assumed that the
7511 cc will be set. So cancel what it did. */
7512 cc_status = cc_prev_status;
7515 return \"fmove%.x %1,%0\";
7517 if (FP_REG_P (operands[0]))
7519 if (REG_P (operands[1]))
7522 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7523 output_asm_insn (\"move%.l %1,%-\", xoperands);
7524 output_asm_insn (\"move%.l %1,%-\", operands);
7525 return \"f%&move%.d %+,%0\";
7527 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7528 return output_move_const_double (operands);
7529 return \"f%&move%.d %f1,%0\";
7531 return \"fmove%.x %f1,%0\";
7534 (define_insn "truncxfdf2"
7535 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7537 (match_operand:XF 1 "general_operand" "f,f")))]
7541 if (REG_P (operands[0]))
7543 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7544 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7545 return \"move%.l %+,%0\";
7547 return \"fmove%.d %f1,%0\";
7550 (define_insn "truncxfsf2"
7551 [(set (match_operand:SF 0 "general_operand" "=dm")
7553 (match_operand:XF 1 "general_operand" "f")))]
7557 (define_insn "floatsixf2"
7558 [(set (match_operand:XF 0 "general_operand" "=f")
7559 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7563 (define_insn "floathixf2"
7564 [(set (match_operand:XF 0 "general_operand" "=f")
7565 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7569 (define_insn "floatqixf2"
7570 [(set (match_operand:XF 0 "general_operand" "=f")
7571 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7575 (define_insn "ftruncxf2"
7576 [(set (match_operand:XF 0 "general_operand" "=f")
7577 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7581 if (FP_REG_P (operands[1]))
7582 return \"fintrz%.x %f1,%0\";
7583 return \"fintrz%.x %f1,%0\";
7586 (define_insn "fixxfqi2"
7587 [(set (match_operand:QI 0 "general_operand" "=dm")
7588 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7592 (define_insn "fixxfhi2"
7593 [(set (match_operand:HI 0 "general_operand" "=dm")
7594 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7598 (define_insn "fixxfsi2"
7599 [(set (match_operand:SI 0 "general_operand" "=dm")
7600 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7605 [(set (match_operand:XF 0 "general_operand" "=f")
7606 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7607 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7612 [(set (match_operand:XF 0 "general_operand" "=f")
7613 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7614 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7619 [(set (match_operand:XF 0 "general_operand" "=f")
7620 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7621 (match_operand:XF 1 "general_operand" "0")))]
7625 (define_insn "addxf3"
7626 [(set (match_operand:XF 0 "general_operand" "=f")
7627 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7628 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7632 if (REG_P (operands[2]))
7633 return \"fadd%.x %2,%0\";
7634 return \"fadd%.x %f2,%0\";
7638 [(set (match_operand:XF 0 "general_operand" "=f")
7639 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7640 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7645 [(set (match_operand:XF 0 "general_operand" "=f")
7646 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7647 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7652 [(set (match_operand:XF 0 "general_operand" "=f")
7653 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7654 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7658 (define_insn "subxf3"
7659 [(set (match_operand:XF 0 "general_operand" "=f")
7660 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7661 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7665 if (REG_P (operands[2]))
7666 return \"fsub%.x %2,%0\";
7667 return \"fsub%.x %f2,%0\";
7671 [(set (match_operand:XF 0 "general_operand" "=f")
7672 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7673 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7678 [(set (match_operand:XF 0 "general_operand" "=f")
7679 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7680 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7685 [(set (match_operand:XF 0 "general_operand" "=f")
7686 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7687 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7691 (define_insn "mulxf3"
7692 [(set (match_operand:XF 0 "general_operand" "=f")
7693 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7694 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7698 if (REG_P (operands[2]))
7699 return \"fmul%.x %2,%0\";
7700 return \"fmul%.x %f2,%0\";
7704 [(set (match_operand:XF 0 "general_operand" "=f")
7705 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7706 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7711 [(set (match_operand:XF 0 "general_operand" "=f")
7712 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7713 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7718 [(set (match_operand:XF 0 "general_operand" "=f")
7719 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7720 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7724 (define_insn "divxf3"
7725 [(set (match_operand:XF 0 "general_operand" "=f")
7726 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7727 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7731 if (REG_P (operands[2]))
7732 return \"fdiv%.x %2,%0\";
7733 return \"fdiv%.x %f2,%0\";
7736 (define_expand "negxf2"
7737 [(set (match_operand:XF 0 "general_operand" "")
7738 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7742 /* ??? There isn't an FPA define_insn so we could handle it here too.
7743 For now we don't (paranoia). */
7751 target = operand_subword (operands[0], 0, 1, XFmode);
7752 result = expand_binop (SImode, xor_optab,
7753 operand_subword_force (operands[1], 0, XFmode),
7754 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7758 if (result != target)
7759 emit_move_insn (result, target);
7761 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7762 operand_subword_force (operands[1], 1, XFmode));
7763 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7764 operand_subword_force (operands[1], 2, XFmode));
7766 insns = get_insns ();
7769 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7774 (define_insn "negxf2_68881"
7775 [(set (match_operand:XF 0 "general_operand" "=f")
7776 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7780 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7781 return \"fneg%.x %1,%0\";
7782 return \"fneg%.x %f1,%0\";
7785 (define_expand "absxf2"
7786 [(set (match_operand:XF 0 "general_operand" "")
7787 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7791 /* ??? There isn't an FPA define_insn so we could handle it here too.
7792 For now we don't (paranoia). */
7800 target = operand_subword (operands[0], 0, 1, XFmode);
7801 result = expand_binop (SImode, and_optab,
7802 operand_subword_force (operands[1], 0, XFmode),
7803 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7807 if (result != target)
7808 emit_move_insn (result, target);
7810 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7811 operand_subword_force (operands[1], 1, XFmode));
7812 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7813 operand_subword_force (operands[1], 2, XFmode));
7815 insns = get_insns ();
7818 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7823 (define_insn "absxf2_68881"
7824 [(set (match_operand:XF 0 "general_operand" "=f")
7825 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7829 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7830 return \"fabs%.x %1,%0\";
7831 return \"fabs%.x %f1,%0\";
7834 (define_insn "sqrtxf2"
7835 [(set (match_operand:XF 0 "general_operand" "=f")
7836 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7840 (define_insn "sinsf2"
7841 [(set (match_operand:SF 0 "general_operand" "=f")
7842 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7843 "TARGET_68881 && flag_fast_math"
7846 if (FP_REG_P (operands[1]))
7847 return \"fsin%.x %1,%0\";
7849 return \"fsin%.s %1,%0\";
7852 (define_insn "sindf2"
7853 [(set (match_operand:DF 0 "general_operand" "=f")
7854 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7855 "TARGET_68881 && flag_fast_math"
7858 if (FP_REG_P (operands[1]))
7859 return \"fsin%.x %1,%0\";
7861 return \"fsin%.d %1,%0\";
7864 (define_insn "sinxf2"
7865 [(set (match_operand:XF 0 "general_operand" "=f")
7866 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7867 "TARGET_68881 && flag_fast_math"
7870 (define_insn "cossf2"
7871 [(set (match_operand:SF 0 "general_operand" "=f")
7872 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7873 "TARGET_68881 && flag_fast_math"
7876 if (FP_REG_P (operands[1]))
7877 return \"fcos%.x %1,%0\";
7879 return \"fcos%.s %1,%0\";
7882 (define_insn "cosdf2"
7883 [(set (match_operand:DF 0 "general_operand" "=f")
7884 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7885 "TARGET_68881 && flag_fast_math"
7888 if (FP_REG_P (operands[1]))
7889 return \"fcos%.x %1,%0\";
7891 return \"fcos%.d %1,%0\";
7894 (define_insn "cosxf2"
7895 [(set (match_operand:XF 0 "general_operand" "=f")
7896 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7897 "TARGET_68881 && flag_fast_math"
7901 [(trap_if (const_int -1) (const_int 7))]
7905 (define_insn "conditional_trap"
7906 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7907 [(cc0) (const_int 0)])
7908 (match_operand:SI 1 "const_int_operand" "I"))]
7909 "TARGET_68020 && ! flags_in_68881 ()"
7912 switch (GET_CODE (operands[0]))
7914 case EQ: return \"trapeq\";
7915 case NE: return \"trapne\";
7916 case GT: return \"trapgt\";
7917 case GTU: return \"traphi\";
7918 case LT: return \"traplt\";
7919 case LTU: return \"trapcs\";
7920 case GE: return \"trapge\";
7921 case GEU: return \"trapcc\";
7922 case LE: return \"traple\";
7923 case LEU: return \"trapls\";