1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
308 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
309 (clobber (match_scratch:SI 1 "=X,d"))
310 (clobber (match_scratch:DI 2 "=d,X"))]
314 if (which_alternative == 0)
318 xoperands[0] = operands[2];
319 xoperands[1] = operands[0];
320 output_move_double (xoperands);
321 cc_status.flags |= CC_REVERSED;
322 return \"neg%.l %R2\;negx%.l %2\";
324 if (find_reg_note (insn, REG_DEAD, operands[0]))
326 cc_status.flags |= CC_REVERSED;
327 return \"neg%.l %R0\;negx%.l %0\";
331 ** 'sub' clears %1, and also clears the X cc bit
332 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
333 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
335 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
340 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
345 /* ISI's assembler fails to handle tstl a0. */
346 if (! ADDRESS_REG_P (operands[0]))
348 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
350 return \"tst%.l %0\";
351 /* If you think that the 68020 does not support tstl a0,
352 reread page B-167 of the 68020 manual more carefully. */
353 /* On an address reg, cmpw may replace cmpl. */
355 return \"cmp%.w %0,%#0\";
357 return \"cmp%.w %#0,%0\";
361 ;; This can't use an address register, because comparisons
362 ;; with address registers as second operand always test the whole word.
365 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
371 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
375 (define_expand "tstsf"
377 (match_operand:SF 0 "general_operand" ""))]
378 "TARGET_68881 || TARGET_FPA"
383 emit_insn (gen_tstsf_fpa (operands[0]));
388 (define_insn "tstsf_fpa"
390 (match_operand:SF 0 "general_operand" "xmdF"))
391 (clobber (match_scratch:SI 1 "=d"))]
393 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
397 (match_operand:SF 0 "general_operand" "fdm"))]
401 cc_status.flags = CC_IN_68881;
402 if (FP_REG_P (operands[0]))
403 return \"ftst%.x %0\";
404 return \"ftst%.s %0\";
407 (define_expand "tstdf"
409 (match_operand:DF 0 "general_operand" ""))]
410 "TARGET_68881 || TARGET_FPA"
415 emit_insn (gen_tstsf_fpa (operands[0]));
420 (define_insn "tstdf_fpa"
422 (match_operand:DF 0 "general_operand" "xrmF"))
423 (clobber (match_scratch:SI 1 "=d"))]
425 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
429 (match_operand:DF 0 "general_operand" "fm"))]
433 cc_status.flags = CC_IN_68881;
434 if (FP_REG_P (operands[0]))
435 return \"ftst%.x %0\";
436 return \"ftst%.d %0\";
439 ;; compare instructions.
441 (define_expand "cmpdi"
444 (compare (match_operand:DI 0 "nonimmediate_operand" "")
445 (match_operand:DI 1 "general_operand" "")))
446 (clobber (match_dup 2))])]
448 "operands[2] = gen_reg_rtx (DImode);")
452 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
453 (match_operand:DI 2 "general_operand" "d,0")))
454 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
458 if (rtx_equal_p (operands[0], operands[1]))
459 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
462 cc_status.flags |= CC_REVERSED;
463 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
467 ;; This is the second "hook" for PIC code (in addition to movsi). See
468 ;; comment of movsi for a description of PIC handling.
469 (define_expand "cmpsi"
471 (compare (match_operand:SI 0 "nonimmediate_operand" "")
472 (match_operand:SI 1 "general_operand" "")))]
476 if (flag_pic && symbolic_operand (operands[1], SImode))
478 /* The source is an address which requires PIC relocation.
479 Call legitimize_pic_address with the source, mode, and a relocation
480 register (a new pseudo, or the final destination if reload_in_progress
481 is set). Then fall through normally */
482 extern rtx legitimize_pic_address();
483 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
484 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
488 ;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
491 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
492 (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
496 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
498 return \"cmpm%.l %0,%1\";
500 return \"cmpm%.l %1,%0\";
502 if (REG_P (operands[1])
503 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
504 { cc_status.flags |= CC_REVERSED;
506 return \"cmp%.l %d1,%d0\";
508 return \"cmp%.l %d0,%d1\";
512 return \"cmp%.l %d0,%d1\";
514 return \"cmp%.l %d1,%d0\";
520 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
521 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.w %0,%1\";
529 return \"cmpm%.w %1,%0\";
531 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.w %d1,%d0\";
537 return \"cmp%.w %d0,%d1\";
541 return \"cmp%.w %d0,%d1\";
543 return \"cmp%.w %d1,%d0\";
549 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
550 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
554 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
556 return \"cmpm%.b %0,%1\";
558 return \"cmpm%.b %1,%0\";
560 if (REG_P (operands[1])
561 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
562 { cc_status.flags |= CC_REVERSED;
564 return \"cmp%.b %d1,%d0\";
566 return \"cmp%.b %d0,%d1\";
570 return \"cmp%.b %d0,%d1\";
572 return \"cmp%.b %d1,%d0\";
576 (define_expand "cmpdf"
578 (compare (match_operand:DF 0 "general_operand" "")
579 (match_operand:DF 1 "general_operand" "")))]
580 "TARGET_68881 || TARGET_FPA"
585 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
590 (define_insn "cmpdf_fpa"
592 (compare (match_operand:DF 0 "general_operand" "x,y")
593 (match_operand:DF 1 "general_operand" "xH,rmF")))
594 (clobber (match_scratch:SI 2 "=d,d"))]
596 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
600 (compare (match_operand:DF 0 "general_operand" "f,mG")
601 (match_operand:DF 1 "general_operand" "fmG,f")))]
605 cc_status.flags = CC_IN_68881;
607 if (REG_P (operands[0]))
609 if (REG_P (operands[1]))
610 return \"fcmp%.x %0,%1\";
612 return \"fcmp%.d %0,%f1\";
614 cc_status.flags |= CC_REVERSED;
615 return \"fcmp%.d %1,%f0\";
617 if (REG_P (operands[0]))
619 if (REG_P (operands[1]))
620 return \"fcmp%.x %1,%0\";
622 return \"fcmp%.d %f1,%0\";
624 cc_status.flags |= CC_REVERSED;
625 return \"fcmp%.d %f0,%1\";
629 (define_expand "cmpsf"
631 (compare (match_operand:SF 0 "general_operand" "")
632 (match_operand:SF 1 "general_operand" "")))]
633 "TARGET_68881 || TARGET_FPA"
638 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
643 (define_insn "cmpsf_fpa"
645 (compare (match_operand:SF 0 "general_operand" "x,y")
646 (match_operand:SF 1 "general_operand" "xH,rmF")))
647 (clobber (match_scratch:SI 2 "=d,d"))]
649 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
653 (compare (match_operand:SF 0 "general_operand" "f,mdG")
654 (match_operand:SF 1 "general_operand" "fmdG,f")))]
658 cc_status.flags = CC_IN_68881;
660 if (FP_REG_P (operands[0]))
662 if (FP_REG_P (operands[1]))
663 return \"fcmp%.x %0,%1\";
665 return \"fcmp%.s %0,%f1\";
667 cc_status.flags |= CC_REVERSED;
668 return \"fcmp%.s %1,%f0\";
670 if (FP_REG_P (operands[0]))
672 if (FP_REG_P (operands[1]))
673 return \"fcmp%.x %1,%0\";
675 return \"fcmp%.s %f1,%0\";
677 cc_status.flags |= CC_REVERSED;
678 return \"fcmp%.s %f0,%1\";
682 ;; Recognizers for btst instructions.
685 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
687 (minus:SI (const_int 7)
688 (match_operand:SI 1 "general_operand" "di"))))]
690 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
693 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
695 (minus:SI (const_int 31)
696 (match_operand:SI 1 "general_operand" "di"))))]
698 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
700 ;; The following two patterns are like the previous two
701 ;; except that they use the fact that bit-number operands
702 ;; are automatically masked to 3 or 5 bits.
705 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
707 (minus:SI (const_int 7)
709 (match_operand:SI 1 "register_operand" "d")
712 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
715 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
717 (minus:SI (const_int 31)
719 (match_operand:SI 1 "register_operand" "d")
722 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
724 ;; Nonoffsettable mem refs are ok in this one pattern
725 ;; since we don't try to adjust them.
727 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
729 (match_operand:SI 1 "const_int_operand" "n")))]
730 "(unsigned) INTVAL (operands[1]) < 8"
733 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
734 return output_btst (operands, operands[1], operands[0], insn, 7);
738 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
740 (match_operand:SI 1 "const_int_operand" "n")))]
744 if (GET_CODE (operands[0]) == MEM)
746 operands[0] = adj_offsettable_operand (operands[0],
747 INTVAL (operands[1]) / 8);
748 operands[1] = gen_rtx (CONST_INT, VOIDmode,
749 7 - INTVAL (operands[1]) % 8);
750 return output_btst (operands, operands[1], operands[0], insn, 7);
752 operands[1] = gen_rtx (CONST_INT, VOIDmode,
753 31 - INTVAL (operands[1]));
754 return output_btst (operands, operands[1], operands[0], insn, 31);
760 ;; A special case in which it is not desirable
761 ;; to reload the constant into a data register.
762 (define_insn "pushexthisi_const"
763 [(set (match_operand:SI 0 "push_operand" "=m")
764 (match_operand:SI 1 "const_int_operand" "J"))]
765 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
768 if (operands[1] == const0_rtx)
769 return \"clr%.l %0\";
774 ;(define_insn "swapsi"
775 ; [(set (match_operand:SI 0 "general_operand" "+r")
776 ; (match_operand:SI 1 "general_operand" "+r"))
777 ; (set (match_dup 1) (match_dup 0))]
781 ;; Special case of fullword move when source is zero.
782 ;; The reason this is special is to avoid loading a zero
783 ;; into a data reg with moveq in order to store it elsewhere.
785 (define_insn "movsi_const0"
786 [(set (match_operand:SI 0 "general_operand" "=g")
788 ;; clr insns on 68000 read before writing.
789 ;; This isn't so on the 68010, but we have no TARGET_68010.
790 "((TARGET_68020 || TARGET_5200)
791 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
794 if (ADDRESS_REG_P (operands[0]))
796 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
797 if (!TARGET_68040 && !TARGET_68060)
798 return \"sub%.l %0,%0\";
803 /* Many SGS assemblers croak on size specifiers for constants. */
806 return \"lea 0.w,%0\";
809 return \"lea 0:w,%0\";
813 /* moveq is faster on the 68000. */
814 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
815 #if defined(MOTOROLA) && !defined(CRDS)
816 return \"moveq%.l %#0,%0\";
818 return \"moveq %#0,%0\";
820 return \"clr%.l %0\";
823 ;; General case of fullword move.
825 ;; This is the main "hook" for PIC code. When generating
826 ;; PIC, movsi is responsible for determining when the source address
827 ;; needs PIC relocation and appropriately calling legitimize_pic_address
828 ;; to perform the actual relocation.
830 ;; In both the PIC and non-PIC cases the patterns generated will
831 ;; matched by the next define_insn.
832 (define_expand "movsi"
833 [(set (match_operand:SI 0 "general_operand" "")
834 (match_operand:SI 1 "general_operand" ""))]
838 if (flag_pic && symbolic_operand (operands[1], SImode))
840 /* The source is an address which requires PIC relocation.
841 Call legitimize_pic_address with the source, mode, and a relocation
842 register (a new pseudo, or the final destination if reload_in_progress
843 is set). Then fall through normally */
844 extern rtx legitimize_pic_address();
845 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
846 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
850 ;; General case of fullword move. The register constraints
851 ;; force integer constants in range for a moveq to be reloaded
852 ;; if they are headed for memory.
854 ;; Notes: make sure no alternative allows g vs g.
855 ;; We don't allow f-regs since fixed point cannot go in them.
856 ;; We do allow y and x regs since fixed point is allowed in them.
857 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
858 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
862 if (which_alternative == 3)
863 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
864 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
865 return \"fpmove%.l %x1,%x0\";
866 if (GET_CODE (operands[1]) == CONST_INT)
867 return output_move_simode_const (operands);
868 else if ((GET_CODE (operands[1]) == SYMBOL_REF
869 || GET_CODE (operands[1]) == CONST)
870 && push_operand (operands[0], SImode))
872 else if ((GET_CODE (operands[1]) == SYMBOL_REF
873 || GET_CODE (operands[1]) == CONST)
874 && ADDRESS_REG_P (operands[0]))
875 return \"lea %a1,%0\";
876 return \"move%.l %1,%0\";
880 [(set (match_operand:HI 0 "general_operand" "=g")
881 (match_operand:HI 1 "general_operand" "g"))]
885 if (GET_CODE (operands[1]) == CONST_INT)
887 if (operands[1] == const0_rtx
888 && (DATA_REG_P (operands[0])
889 || GET_CODE (operands[0]) == MEM)
890 /* clr insns on 68000 read before writing.
891 This isn't so on the 68010, but we have no TARGET_68010. */
892 && ((TARGET_68020 || TARGET_5200)
893 || !(GET_CODE (operands[0]) == MEM
894 && MEM_VOLATILE_P (operands[0]))))
895 return \"clr%.w %0\";
896 else if (DATA_REG_P (operands[0])
897 && INTVAL (operands[1]) < 128
898 && INTVAL (operands[1]) >= -128)
900 #if defined(MOTOROLA) && !defined(CRDS)
901 return \"moveq%.l %1,%0\";
903 return \"moveq %1,%0\";
906 else if (INTVAL (operands[1]) < 0x8000
907 && INTVAL (operands[1]) >= -0x8000)
908 return \"move%.w %1,%0\";
910 else if (CONSTANT_P (operands[1]))
911 return \"move%.l %1,%0\";
913 /* Recognize the insn before a tablejump, one that refers
914 to a table of offsets. Such an insn will need to refer
915 to a label on the insn. So output one. Use the label-number
916 of the table of offsets to generate this label. This code,
917 and similar code below, assumes that there will be at most one
918 reference to each table. */
919 if (GET_CODE (operands[1]) == MEM
920 && GET_CODE (XEXP (operands[1], 0)) == PLUS
921 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
922 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
924 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
925 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
927 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
928 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
930 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
931 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
933 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
934 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
935 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
936 #ifdef SGS_SWITCH_TABLES
937 /* Set flag saying we need to define the symbol
938 LD%n (with value L%n-LI%n) at the end of the switch table. */
939 switch_table_difference_label_flag = 1;
940 #endif /* SGS_SWITCH_TABLES */
941 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
943 #endif /* SGS_NO_LI */
944 return \"move%.w %1,%0\";
947 (define_insn "movstricthi"
948 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
949 (match_operand:HI 1 "general_operand" "rmn"))]
953 if (GET_CODE (operands[1]) == CONST_INT)
955 if (operands[1] == const0_rtx
956 && (DATA_REG_P (operands[0])
957 || GET_CODE (operands[0]) == MEM)
958 /* clr insns on 68000 read before writing.
959 This isn't so on the 68010, but we have no TARGET_68010. */
960 && ((TARGET_68020 || TARGET_5200)
961 || !(GET_CODE (operands[0]) == MEM
962 && MEM_VOLATILE_P (operands[0]))))
963 return \"clr%.w %0\";
965 return \"move%.w %1,%0\";
969 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
970 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
976 /* This is probably useless, since it loses for pushing a struct
977 of several bytes a byte at a time. */
978 if (GET_CODE (operands[0]) == MEM
979 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
980 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
981 && ! ADDRESS_REG_P (operands[1]))
983 xoperands[1] = operands[1];
985 = gen_rtx (MEM, QImode,
986 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
987 /* Just pushing a byte puts it in the high byte of the halfword. */
988 /* We must put it in the low-order, high-numbered byte. */
989 output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands);
993 /* clr and st insns on 68000 read before writing.
994 This isn't so on the 68010, but we have no TARGET_68010. */
995 if (!ADDRESS_REG_P (operands[0])
997 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
999 if (operands[1] == const0_rtx)
1000 return \"clr%.b %0\";
1001 if (GET_CODE (operands[1]) == CONST_INT
1002 && (INTVAL (operands[1]) & 255) == 255)
1008 if (GET_CODE (operands[1]) == CONST_INT
1009 && DATA_REG_P (operands[0])
1010 && INTVAL (operands[1]) < 128
1011 && INTVAL (operands[1]) >= -128)
1013 #if defined(MOTOROLA) && !defined(CRDS)
1014 return \"moveq%.l %1,%0\";
1016 return \"moveq %1,%0\";
1019 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1020 return \"move%.l %1,%0\";
1021 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1022 return \"move%.w %1,%0\";
1023 return \"move%.b %1,%0\";
1026 (define_insn "movstrictqi"
1027 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1028 (match_operand:QI 1 "general_operand" "dmn"))]
1032 if (operands[1] == const0_rtx
1033 /* clr insns on 68000 read before writing.
1034 This isn't so on the 68010, but we have no TARGET_68010. */
1035 && ((TARGET_68020 || TARGET_5200)
1036 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1037 return \"clr%.b %0\";
1038 return \"move%.b %1,%0\";
1041 (define_insn "movsf"
1042 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1043 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1044 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1045 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1049 if (which_alternative >= 4)
1050 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1051 if (FPA_REG_P (operands[0]))
1053 if (FPA_REG_P (operands[1]))
1054 return \"fpmove%.s %x1,%x0\";
1055 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1056 return output_move_const_single (operands);
1057 else if (FP_REG_P (operands[1]))
1058 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1059 return \"fpmove%.s %x1,%x0\";
1061 if (FPA_REG_P (operands[1]))
1063 if (FP_REG_P (operands[0]))
1064 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1066 return \"fpmove%.s %x1,%x0\";
1068 if (FP_REG_P (operands[0]))
1070 if (FP_REG_P (operands[1]))
1071 return \"f%$move%.x %1,%0\";
1072 else if (ADDRESS_REG_P (operands[1]))
1073 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1074 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1075 return output_move_const_single (operands);
1076 return \"f%$move%.s %f1,%0\";
1078 if (FP_REG_P (operands[1]))
1080 if (ADDRESS_REG_P (operands[0]))
1081 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1082 return \"fmove%.s %f1,%0\";
1084 return \"move%.l %1,%0\";
1087 (define_insn "movdf"
1088 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1089 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1090 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1091 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1095 if (which_alternative == 7)
1096 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1097 if (FPA_REG_P (operands[0]))
1099 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1100 return output_move_const_double (operands);
1101 if (FP_REG_P (operands[1]))
1102 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1103 return \"fpmove%.d %x1,%x0\";
1105 else if (FPA_REG_P (operands[1]))
1107 if (FP_REG_P(operands[0]))
1108 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1110 return \"fpmove%.d %x1,%x0\";
1112 if (FP_REG_P (operands[0]))
1114 if (FP_REG_P (operands[1]))
1115 return \"f%&move%.x %1,%0\";
1116 if (REG_P (operands[1]))
1119 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1120 output_asm_insn (\"move%.l %1,%-\", xoperands);
1121 output_asm_insn (\"move%.l %1,%-\", operands);
1122 return \"f%&move%.d %+,%0\";
1124 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1125 return output_move_const_double (operands);
1126 return \"f%&move%.d %f1,%0\";
1128 else if (FP_REG_P (operands[1]))
1130 if (REG_P (operands[0]))
1132 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1133 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1134 return \"move%.l %+,%0\";
1137 return \"fmove%.d %f1,%0\";
1139 return output_move_double (operands);
1143 (define_expand "movxf"
1144 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1145 (match_operand:XF 1 "general_operand" ""))]
1149 if (CONSTANT_P (operands[1]))
1151 operands[1] = force_const_mem (XFmode, operands[1]);
1152 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1153 && ! reload_in_progress)
1154 operands[1] = change_address (operands[1], XFmode,
1155 XEXP (operands[1], 0));
1160 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1161 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1165 if (FP_REG_P (operands[0]))
1167 if (FP_REG_P (operands[1]))
1168 return \"fmove%.x %1,%0\";
1169 if (REG_P (operands[1]))
1172 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1173 output_asm_insn (\"move%.l %1,%-\", xoperands);
1174 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1175 output_asm_insn (\"move%.l %1,%-\", xoperands);
1176 output_asm_insn (\"move%.l %1,%-\", operands);
1177 return \"fmove%.x %+,%0\";
1179 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1180 return \"fmove%.x %1,%0\";
1181 return \"fmove%.x %f1,%0\";
1183 if (REG_P (operands[0]))
1185 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1186 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1187 output_asm_insn (\"move%.l %+,%0\", operands);
1188 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1189 return \"move%.l %+,%0\";
1191 return \"fmove%.x %f1,%0\";
1196 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1197 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1201 if (FP_REG_P (operands[0]))
1203 if (FP_REG_P (operands[1]))
1204 return \"fmove%.x %1,%0\";
1205 if (REG_P (operands[1]))
1208 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1209 output_asm_insn (\"move%.l %1,%-\", xoperands);
1210 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1211 output_asm_insn (\"move%.l %1,%-\", xoperands);
1212 output_asm_insn (\"move%.l %1,%-\", operands);
1213 return \"fmove%.x %+,%0\";
1215 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1216 return \"fmove%.x %1,%0\";
1217 return \"fmove%.x %f1,%0\";
1219 if (FP_REG_P (operands[1]))
1221 if (REG_P (operands[0]))
1223 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1224 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1225 output_asm_insn (\"move%.l %+,%0\", operands);
1226 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1227 return \"move%.l %+,%0\";
1230 return \"fmove%.x %f1,%0\";
1232 return output_move_double (operands);
1236 ;; movdi can apply to fp regs in some cases
1237 (define_insn "movdi"
1238 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1239 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1240 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1241 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1242 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1243 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1244 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1248 if (which_alternative == 8)
1249 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1250 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1251 return \"fpmove%.d %x1,%x0\";
1252 if (FP_REG_P (operands[0]))
1254 if (FP_REG_P (operands[1]))
1255 return \"fmove%.x %1,%0\";
1256 if (REG_P (operands[1]))
1259 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1260 output_asm_insn (\"move%.l %1,%-\", xoperands);
1261 output_asm_insn (\"move%.l %1,%-\", operands);
1262 return \"fmove%.d %+,%0\";
1264 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1265 return output_move_const_double (operands);
1266 return \"fmove%.d %f1,%0\";
1268 else if (FP_REG_P (operands[1]))
1270 if (REG_P (operands[0]))
1272 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1273 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1274 return \"move%.l %+,%0\";
1277 return \"fmove%.d %f1,%0\";
1279 return output_move_double (operands);
1283 ;; Thus goes after the move instructions
1284 ;; because the move instructions are better (require no spilling)
1285 ;; when they can apply. It goes before the add/sub insns
1286 ;; so we will prefer it to them.
1288 (define_insn "pushasi"
1289 [(set (match_operand:SI 0 "push_operand" "=m")
1290 (match_operand:SI 1 "address_operand" "p"))]
1294 ;; truncation instructions
1295 (define_insn "truncsiqi2"
1296 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1298 (match_operand:SI 1 "general_operand" "doJ,i")))]
1302 if (GET_CODE (operands[0]) == REG)
1304 /* Must clear condition codes, since the move.l bases them on
1305 the entire 32 bits, not just the desired 8 bits. */
1307 return \"move%.l %1,%0\";
1309 if (GET_CODE (operands[1]) == MEM)
1310 operands[1] = adj_offsettable_operand (operands[1], 3);
1311 return \"move%.b %1,%0\";
1314 (define_insn "trunchiqi2"
1315 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1317 (match_operand:HI 1 "general_operand" "doJ,i")))]
1321 if (GET_CODE (operands[0]) == REG
1322 && (GET_CODE (operands[1]) == MEM
1323 || GET_CODE (operands[1]) == CONST_INT))
1325 /* Must clear condition codes, since the move.w bases them on
1326 the entire 16 bits, not just the desired 8 bits. */
1328 return \"move%.w %1,%0\";
1330 if (GET_CODE (operands[0]) == REG)
1332 /* Must clear condition codes, since the move.l bases them on
1333 the entire 32 bits, not just the desired 8 bits. */
1335 return \"move%.l %1,%0\";
1337 if (GET_CODE (operands[1]) == MEM)
1338 operands[1] = adj_offsettable_operand (operands[1], 1);
1339 return \"move%.b %1,%0\";
1342 (define_insn "truncsihi2"
1343 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1345 (match_operand:SI 1 "general_operand" "roJ,i")))]
1349 if (GET_CODE (operands[0]) == REG)
1351 /* Must clear condition codes, since the move.l bases them on
1352 the entire 32 bits, not just the desired 8 bits. */
1354 return \"move%.l %1,%0\";
1356 if (GET_CODE (operands[1]) == MEM)
1357 operands[1] = adj_offsettable_operand (operands[1], 2);
1358 return \"move%.w %1,%0\";
1361 ;; zero extension instructions
1363 ;; this is the canonical form for (lshiftrt:DI x 32)
1364 (define_insn "zero_extendsidi2"
1365 [(set (match_operand:DI 0 "general_operand" "rm")
1366 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1371 if (GET_CODE (operands[0]) == REG)
1372 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1373 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1374 return \"move%.l %1,%0\;clr%.l %0\";
1375 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1376 return \"clr%.l %0\;move%.l %1,%0\";
1378 operands[2] = adj_offsettable_operand (operands[0], 4);
1379 if (ADDRESS_REG_P (operands[0]))
1380 return \"move%.l %1,%2\;sub%.l %0,%0\";
1382 return \"move%.l %1,%2\;clr%.l %0\";
1385 (define_expand "zero_extendhisi2"
1386 [(set (match_operand:SI 0 "register_operand" "")
1388 (set (strict_low_part (match_dup 2))
1389 (match_operand:HI 1 "general_operand" ""))]
1393 operands[1] = make_safe_from (operands[1], operands[0]);
1394 if (GET_CODE (operands[0]) == SUBREG)
1395 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1396 SUBREG_WORD (operands[0]));
1398 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1401 (define_expand "zero_extendqihi2"
1402 [(set (match_operand:HI 0 "register_operand" "")
1404 (set (strict_low_part (match_dup 2))
1405 (match_operand:QI 1 "general_operand" ""))]
1409 operands[1] = make_safe_from (operands[1], operands[0]);
1410 if (GET_CODE (operands[0]) == SUBREG)
1411 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1412 SUBREG_WORD (operands[0]));
1414 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1417 (define_expand "zero_extendqisi2"
1418 [(set (match_operand:SI 0 "register_operand" "")
1420 (set (strict_low_part (match_dup 2))
1421 (match_operand:QI 1 "general_operand" ""))]
1425 operands[1] = make_safe_from (operands[1], operands[0]);
1426 if (GET_CODE (operands[0]) == SUBREG)
1427 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1428 SUBREG_WORD (operands[0]));
1430 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1433 ;; Patterns to recognize zero-extend insns produced by the combiner.
1434 ;; We don't allow both operands in memory, because of aliasing problems.
1435 ;; Explicitly disallow two memory operands via the condition since reloading
1436 ;; of this case will result in worse code than the uncombined patterns.
1439 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1440 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1441 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1444 if (DATA_REG_P (operands[0]))
1446 if (GET_CODE (operands[1]) == REG
1447 && REGNO (operands[0]) == REGNO (operands[1]))
1448 return \"and%.l %#0xFFFF,%0\";
1449 if (reg_mentioned_p (operands[0], operands[1]))
1450 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1451 return \"clr%.l %0\;move%.w %1,%0\";
1453 else if (GET_CODE (operands[0]) == MEM
1454 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1455 return \"move%.w %1,%0\;clr%.w %0\";
1456 else if (GET_CODE (operands[0]) == MEM
1457 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1458 return \"clr%.w %0\;move%.w %1,%0\";
1461 output_asm_insn (\"clr%.w %0\", operands);
1462 operands[0] = adj_offsettable_operand (operands[0], 2);
1463 return \"move%.w %1,%0\";
1468 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1469 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1470 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1473 if (DATA_REG_P (operands[0]))
1475 if (GET_CODE (operands[1]) == REG
1476 && REGNO (operands[0]) == REGNO (operands[1]))
1477 return \"and%.w %#0xFF,%0\";
1478 if (reg_mentioned_p (operands[0], operands[1]))
1479 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1480 return \"clr%.w %0\;move%.b %1,%0\";
1482 else if (GET_CODE (operands[0]) == MEM
1483 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1485 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1486 == STACK_POINTER_REGNUM)
1488 output_asm_insn (\"clr%.w %-\", operands);
1489 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1490 plus_constant (stack_pointer_rtx, 1));
1491 return \"move%.b %1,%0\";
1494 return \"move%.b %1,%0\;clr%.b %0\";
1496 else if (GET_CODE (operands[0]) == MEM
1497 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1498 return \"clr%.b %0\;move%.b %1,%0\";
1501 output_asm_insn (\"clr%.b %0\", operands);
1502 operands[0] = adj_offsettable_operand (operands[0], 1);
1503 return \"move%.b %1,%0\";
1508 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1509 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1510 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1513 if (DATA_REG_P (operands[0]))
1515 if (GET_CODE (operands[1]) == REG
1516 && REGNO (operands[0]) == REGNO (operands[1]))
1517 return \"and%.l %#0xFF,%0\";
1518 if (reg_mentioned_p (operands[0], operands[1]))
1519 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1520 return \"clr%.l %0\;move%.b %1,%0\";
1522 else if (GET_CODE (operands[0]) == MEM
1523 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1525 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1528 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1530 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1533 return \"clrl %0@-\;moveb %1,%0@(3)\";
1536 else if (GET_CODE (operands[0]) == MEM
1537 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1539 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1542 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1544 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1547 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1552 output_asm_insn (\"clr%.l %0\", operands);
1553 operands[0] = adj_offsettable_operand (operands[0], 3);
1554 return \"move%.b %1,%0\";
1558 ;; sign extension instructions
1560 (define_insn "extendqidi2"
1561 [(set (match_operand:DI 0 "general_operand" "=d")
1563 (match_operand:QI 1 "general_operand" "rm")))]
1568 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1569 if (TARGET_68020 || TARGET_5200)
1570 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1572 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1575 (define_insn "extendhidi2"
1576 [(set (match_operand:DI 0 "general_operand" "=d")
1578 (match_operand:HI 1 "general_operand" "rm")))]
1583 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1584 if (TARGET_68020 || TARGET_5200)
1585 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1587 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1590 (define_insn "extendsidi2"
1591 [(set (match_operand:DI 0 "general_operand" "=d")
1593 (match_operand:SI 1 "general_operand" "rm")))]
1598 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1599 if (TARGET_68020 || TARGET_5200)
1600 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1602 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1605 ;; Special case when one can avoid register clobbering, copy and test
1606 ;; Maybe there is a way to make that the general case, by forcing the
1607 ;; result of the SI tree to be in the lower register of the DI target
1609 (define_insn "extendplussidi"
1610 [(set (match_operand:DI 0 "register_operand" "=d")
1611 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1612 (match_operand:SI 2 "general_operand" "rmn"))))]
1617 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1618 if (GET_CODE (operands[1]) == CONST_INT
1619 && (unsigned) INTVAL (operands[1]) > 8)
1621 rtx tmp = operands[1];
1623 operands[1] = operands[2];
1626 if (GET_CODE (operands[1]) == REG
1627 && REGNO (operands[1]) == REGNO (operands[3]))
1628 output_asm_insn (\"add%.l %2,%3\", operands);
1630 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1631 if (TARGET_68020 || TARGET_5200)
1632 return \"smi %0\;extb%.l %0\";
1634 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1637 (define_insn "extendhisi2"
1638 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1640 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1644 if (ADDRESS_REG_P (operands[0]))
1645 return \"move%.w %1,%0\";
1646 return \"ext%.l %0\";
1649 (define_insn "extendqihi2"
1650 [(set (match_operand:HI 0 "general_operand" "=d")
1651 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1655 (define_insn "extendqisi2"
1656 [(set (match_operand:SI 0 "general_operand" "=d")
1657 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1658 "TARGET_68020 || TARGET_5200"
1661 ;; Conversions between float and double.
1663 (define_expand "extendsfdf2"
1664 [(set (match_operand:DF 0 "general_operand" "")
1666 (match_operand:SF 1 "general_operand" "")))]
1667 "TARGET_68881 || TARGET_FPA"
1671 [(set (match_operand:DF 0 "general_operand" "=x,y")
1673 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1678 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1680 (match_operand:SF 1 "general_operand" "f,dmF")))]
1684 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1686 if (REGNO (operands[0]) == REGNO (operands[1]))
1688 /* Extending float to double in an fp-reg is a no-op.
1689 NOTICE_UPDATE_CC has already assumed that the
1690 cc will be set. So cancel what it did. */
1691 cc_status = cc_prev_status;
1694 return \"f%&move%.x %1,%0\";
1696 if (FP_REG_P (operands[0]))
1697 return \"f%&move%.s %f1,%0\";
1698 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1700 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1701 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1702 return \"move%.l %+,%0\";
1704 return \"fmove%.d %f1,%0\";
1707 ;; This cannot output into an f-reg because there is no way to be
1708 ;; sure of truncating in that case.
1709 ;; But on the Sun FPA, we can be sure.
1710 (define_expand "truncdfsf2"
1711 [(set (match_operand:SF 0 "general_operand" "")
1713 (match_operand:DF 1 "general_operand" "")))]
1714 "TARGET_68881 || TARGET_FPA"
1718 [(set (match_operand:SF 0 "general_operand" "=x,y")
1720 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1724 ;; On the '040 we can truncate in a register accurately and easily.
1726 [(set (match_operand:SF 0 "general_operand" "=f")
1728 (match_operand:DF 1 "general_operand" "fmG")))]
1732 if (FP_REG_P (operands[1]))
1733 return \"f%$move%.x %1,%0\";
1734 return \"f%$move%.d %f1,%0\";
1738 [(set (match_operand:SF 0 "general_operand" "=dm")
1740 (match_operand:DF 1 "general_operand" "f")))]
1744 ;; Conversion between fixed point and floating point.
1745 ;; Note that among the fix-to-float insns
1746 ;; the ones that start with SImode come first.
1747 ;; That is so that an operand that is a CONST_INT
1748 ;; (and therefore lacks a specific machine mode).
1749 ;; will be recognized as SImode (which is always valid)
1750 ;; rather than as QImode or HImode.
1752 (define_expand "floatsisf2"
1753 [(set (match_operand:SF 0 "general_operand" "")
1754 (float:SF (match_operand:SI 1 "general_operand" "")))]
1755 "TARGET_68881 || TARGET_FPA"
1759 [(set (match_operand:SF 0 "general_operand" "=y,x")
1760 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1765 [(set (match_operand:SF 0 "general_operand" "=f")
1766 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1770 (define_expand "floatsidf2"
1771 [(set (match_operand:DF 0 "general_operand" "")
1772 (float:DF (match_operand:SI 1 "general_operand" "")))]
1773 "TARGET_68881 || TARGET_FPA"
1777 [(set (match_operand:DF 0 "general_operand" "=y,x")
1778 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1783 [(set (match_operand:DF 0 "general_operand" "=f")
1784 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1788 (define_insn "floathisf2"
1789 [(set (match_operand:SF 0 "general_operand" "=f")
1790 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1794 (define_insn "floathidf2"
1795 [(set (match_operand:DF 0 "general_operand" "=f")
1796 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1800 (define_insn "floatqisf2"
1801 [(set (match_operand:SF 0 "general_operand" "=f")
1802 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1806 (define_insn "floatqidf2"
1807 [(set (match_operand:DF 0 "general_operand" "=f")
1808 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1812 ;; New routines to convert floating-point values to integers
1813 ;; to be used on the '040. These should be faster than trapping
1814 ;; into the kernel to emulate fintrz. They should also be faster
1815 ;; than calling the subroutines fixsfsi or fixdfsi.
1817 (define_insn "fix_truncdfsi2"
1818 [(set (match_operand:SI 0 "general_operand" "=dm")
1819 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1820 (clobber (match_scratch:SI 2 "=d"))
1821 (clobber (match_scratch:SI 3 "=d"))]
1822 "TARGET_68881 && TARGET_68040"
1826 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1829 (define_insn "fix_truncdfhi2"
1830 [(set (match_operand:HI 0 "general_operand" "=dm")
1831 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1832 (clobber (match_scratch:SI 2 "=d"))
1833 (clobber (match_scratch:SI 3 "=d"))]
1834 "TARGET_68881 && TARGET_68040"
1838 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1841 (define_insn "fix_truncdfqi2"
1842 [(set (match_operand:QI 0 "general_operand" "=dm")
1843 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1844 (clobber (match_scratch:SI 2 "=d"))
1845 (clobber (match_scratch:SI 3 "=d"))]
1846 "TARGET_68881 && TARGET_68040"
1850 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1853 ;; Convert a float to a float whose value is an integer.
1854 ;; This is the first stage of converting it to an integer type.
1856 (define_insn "ftruncdf2"
1857 [(set (match_operand:DF 0 "general_operand" "=f")
1858 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1859 "TARGET_68881 && !TARGET_68040"
1862 if (FP_REG_P (operands[1]))
1863 return \"fintrz%.x %f1,%0\";
1864 return \"fintrz%.d %f1,%0\";
1867 (define_insn "ftruncsf2"
1868 [(set (match_operand:SF 0 "general_operand" "=f")
1869 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1870 "TARGET_68881 && !TARGET_68040"
1873 if (FP_REG_P (operands[1]))
1874 return \"fintrz%.x %f1,%0\";
1875 return \"fintrz%.s %f1,%0\";
1878 ;; Convert a float whose value is an integer
1879 ;; to an actual integer. Second stage of converting float to integer type.
1880 (define_insn "fixsfqi2"
1881 [(set (match_operand:QI 0 "general_operand" "=dm")
1882 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1886 (define_insn "fixsfhi2"
1887 [(set (match_operand:HI 0 "general_operand" "=dm")
1888 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1892 (define_insn "fixsfsi2"
1893 [(set (match_operand:SI 0 "general_operand" "=dm")
1894 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1898 (define_insn "fixdfqi2"
1899 [(set (match_operand:QI 0 "general_operand" "=dm")
1900 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1904 (define_insn "fixdfhi2"
1905 [(set (match_operand:HI 0 "general_operand" "=dm")
1906 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1910 (define_insn "fixdfsi2"
1911 [(set (match_operand:SI 0 "general_operand" "=dm")
1912 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1916 ;; Convert a float to an integer.
1917 ;; On the Sun FPA, this is done in one step.
1920 [(set (match_operand:SI 0 "general_operand" "=x,y")
1921 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1926 [(set (match_operand:SI 0 "general_operand" "=x,y")
1927 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1933 (define_insn "adddi_lshrdi_63"
1934 [(set (match_operand:DI 0 "general_operand" "=d")
1935 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1938 (clobber (match_scratch:SI 2 "=d"))]
1942 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1943 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1945 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1946 if (GET_CODE (operands[1]) == REG)
1947 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1948 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1949 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1950 operands[4] = operands[1];
1952 operands[4] = adj_offsettable_operand (operands[1], 4);
1953 if (GET_CODE (operands[1]) == MEM
1954 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1955 output_asm_insn (\"move%.l %4,%3\", operands);
1956 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1957 if (TARGET_68020 || TARGET_5200)
1958 output_asm_insn (\"extb%.l %2\", operands);
1960 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1961 if (GET_CODE (operands[1]) != MEM
1962 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1963 output_asm_insn (\"move%.l %4,%3\", operands);
1964 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1967 (define_insn "adddi_sexthishl32"
1968 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
1969 (plus:DI (ashift:DI (sign_extend:DI
1970 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1972 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1973 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1978 if (ADDRESS_REG_P (operands[0]))
1979 return \"add%.w %1,%0\";
1980 else if (ADDRESS_REG_P (operands[3]))
1981 return \"move%.w %1,%3\;add%.l %3,%0\";
1983 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1986 (define_insn "adddi_dilshr32"
1987 [(set (match_operand:DI 0 "general_operand" "=do")
1988 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1989 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1990 ;; (const_int 32))))]
1991 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1993 (match_operand:DI 2 "general_operand" "0")))]
1998 if (GET_CODE (operands[0]) == REG)
1999 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2001 operands[2] = adj_offsettable_operand (operands[0], 4);
2002 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2005 (define_insn "adddi_dishl32"
2006 [(set (match_operand:DI 0 "general_operand" "=ro")
2007 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2008 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2009 ;; (const_int 32))))]
2010 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2012 (match_operand:DI 2 "general_operand" "0")))]
2017 if (GET_CODE (operands[1]) == REG)
2018 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2020 operands[1] = adj_offsettable_operand (operands[1], 4);
2021 return \"add%.l %1,%0\";
2024 (define_insn "adddi3"
2025 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2026 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2027 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2028 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2032 if (DATA_REG_P (operands[0]))
2034 if (DATA_REG_P (operands[2]))
2035 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2036 else if (GET_CODE (operands[2]) == MEM
2037 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2039 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2043 /* TODO : this should work also for CONST operands[2] */
2044 if (GET_CODE (operands[2]) == REG)
2045 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2047 operands[1] = adj_offsettable_operand (operands[2], 4);
2048 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2051 else if (GET_CODE (operands[0]) == MEM)
2053 if (GET_CODE (operands[2]) == MEM
2054 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2055 return \"add%.l %2,%0\;addx%.l %2,%0\";
2057 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2059 operands[1] = gen_rtx (MEM, SImode,
2060 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2061 gen_rtx (CONST_INT, VOIDmode, -8)));
2062 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2064 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2066 operands[1] = XEXP(operands[0], 0);
2067 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2071 operands[1] = adj_offsettable_operand (operands[0], 4);
2072 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2077 (define_insn "addsi_lshrsi_31"
2078 [(set (match_operand:SI 0 "general_operand" "=dm")
2079 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2085 operands[2] = operands[0];
2086 operands[3] = gen_label_rtx();
2087 if (GET_CODE (operands[0]) == MEM)
2089 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2090 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2091 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2092 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2094 output_asm_insn (\"move%.l %1,%0\", operands);
2096 output_asm_insn (\"jbpl %l3\", operands);
2098 output_asm_insn (\"jpl %l3\", operands);
2101 output_asm_insn (\"addq%.l %#1,%2\", operands);
2103 output_asm_insn (\"add%.l %#1,%2\", operands);
2105 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2106 CODE_LABEL_NUMBER (operands[3]));
2110 ;; Note that the middle two alternatives are near-duplicates
2111 ;; in order to handle insns generated by reload.
2112 ;; This is needed since they are not themselves reloaded,
2113 ;; so commutativity won't apply to them.
2114 (define_insn "addsi3"
2115 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2116 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2117 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2121 if (! operands_match_p (operands[0], operands[1]))
2123 if (!ADDRESS_REG_P (operands[1]))
2125 rtx tmp = operands[1];
2127 operands[1] = operands[2];
2131 /* These insns can result from reloads to access
2132 stack slots over 64k from the frame pointer. */
2133 if (GET_CODE (operands[2]) == CONST_INT
2134 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2135 return \"move%.l %2,%0\;add%.l %1,%0\";
2137 if (GET_CODE (operands[2]) == REG)
2138 return \"lea 0(%1,%2.l),%0\";
2140 return \"lea %c2(%1),%0\";
2143 if (GET_CODE (operands[2]) == REG)
2144 return \"lea (%1,%2.l),%0\";
2146 return \"lea (%c2,%1),%0\";
2147 #else /* not MOTOROLA (MIT syntax) */
2148 if (GET_CODE (operands[2]) == REG)
2149 return \"lea %1@(0,%2:l),%0\";
2151 return \"lea %1@(%c2),%0\";
2152 #endif /* not MOTOROLA */
2153 #endif /* not SGS */
2155 if (GET_CODE (operands[2]) == CONST_INT)
2158 if (INTVAL (operands[2]) > 0
2159 && INTVAL (operands[2]) <= 8)
2160 return \"addq%.l %2,%0\";
2161 if (INTVAL (operands[2]) < 0
2162 && INTVAL (operands[2]) >= -8)
2164 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2165 - INTVAL (operands[2]));
2166 return \"subq%.l %2,%0\";
2168 /* On the CPU32 it is faster to use two addql instructions to
2169 add a small integer (8 < N <= 16) to a register.
2170 Likewise for subql. */
2171 if (TARGET_CPU32 && REG_P (operands[0]))
2173 if (INTVAL (operands[2]) > 8
2174 && INTVAL (operands[2]) <= 16)
2176 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2177 INTVAL (operands[2]) - 8);
2178 return \"addq%.l %#8,%0\;addq%.l %2,%0\";
2180 if (INTVAL (operands[2]) < -8
2181 && INTVAL (operands[2]) >= -16)
2183 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2184 - INTVAL (operands[2]) - 8);
2185 return \"subq%.l %#8,%0\;subq%.l %2,%0\";
2189 if (ADDRESS_REG_P (operands[0])
2190 && INTVAL (operands[2]) >= -0x8000
2191 && INTVAL (operands[2]) < 0x8000)
2194 return \"add%.w %2,%0\";
2197 return \"lea (%c2,%0),%0\";
2199 return \"lea %0@(%c2),%0\";
2203 return \"add%.l %2,%0\";
2207 [(set (match_operand:SI 0 "general_operand" "=a")
2208 (plus:SI (match_operand:SI 1 "general_operand" "0")
2210 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2214 (define_insn "addhi3"
2215 [(set (match_operand:HI 0 "general_operand" "=m,r")
2216 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2217 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2221 if (GET_CODE (operands[2]) == CONST_INT)
2224 /* If the constant would be a negative number when interpreted as
2225 HImode, make it negative. This is usually, but not always, done
2226 elsewhere in the compiler. First check for constants out of range,
2227 which could confuse us. */
2229 if (INTVAL (operands[2]) >= 32768)
2230 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2231 INTVAL (operands[2]) - 65536);
2233 if (INTVAL (operands[2]) > 0
2234 && INTVAL (operands[2]) <= 8)
2235 return \"addq%.w %2,%0\";
2236 if (INTVAL (operands[2]) < 0
2237 && INTVAL (operands[2]) >= -8)
2239 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2240 - INTVAL (operands[2]));
2241 return \"subq%.w %2,%0\";
2243 /* On the CPU32 it is faster to use two addqw instructions to
2244 add a small integer (8 < N <= 16) to a register.
2245 Likewise for subqw. */
2246 if (TARGET_CPU32 && REG_P (operands[0]))
2248 if (INTVAL (operands[2]) > 8
2249 && INTVAL (operands[2]) <= 16)
2251 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2252 INTVAL (operands[2]) - 8);
2253 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2255 if (INTVAL (operands[2]) < -8
2256 && INTVAL (operands[2]) >= -16)
2258 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2259 - INTVAL (operands[2]) - 8);
2260 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2264 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2266 return \"lea (%c2,%0),%0\";
2268 return \"lea %0@(%c2),%0\";
2271 return \"add%.w %2,%0\";
2274 ;; These insns must use MATCH_DUP instead of the more expected
2275 ;; use of a matching constraint because the "output" here is also
2276 ;; an input, so you can't use the matching constraint. That also means
2277 ;; that you can't use the "%", so you need patterns with the matched
2278 ;; operand in both positions.
2281 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2282 (plus:HI (match_dup 0)
2283 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2287 if (GET_CODE (operands[1]) == CONST_INT)
2290 /* If the constant would be a negative number when interpreted as
2291 HImode, make it negative. This is usually, but not always, done
2292 elsewhere in the compiler. First check for constants out of range,
2293 which could confuse us. */
2295 if (INTVAL (operands[1]) >= 32768)
2296 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2297 INTVAL (operands[1]) - 65536);
2299 if (INTVAL (operands[1]) > 0
2300 && INTVAL (operands[1]) <= 8)
2301 return \"addq%.w %1,%0\";
2302 if (INTVAL (operands[1]) < 0
2303 && INTVAL (operands[1]) >= -8)
2305 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2306 - INTVAL (operands[1]));
2307 return \"subq%.w %1,%0\";
2309 /* On the CPU32 it is faster to use two addqw instructions to
2310 add a small integer (8 < N <= 16) to a register.
2311 Likewise for subqw. */
2312 if (TARGET_CPU32 && REG_P (operands[0]))
2314 if (INTVAL (operands[1]) > 8
2315 && INTVAL (operands[1]) <= 16)
2317 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2318 INTVAL (operands[1]) - 8);
2319 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2321 if (INTVAL (operands[1]) < -8
2322 && INTVAL (operands[1]) >= -16)
2324 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2325 - INTVAL (operands[1]) - 8);
2326 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2330 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2332 return \"lea (%c1,%0),%0\";
2334 return \"lea %0@(%c1),%0\";
2337 return \"add%.w %1,%0\";
2341 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2342 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2347 if (GET_CODE (operands[1]) == CONST_INT)
2350 /* If the constant would be a negative number when interpreted as
2351 HImode, make it negative. This is usually, but not always, done
2352 elsewhere in the compiler. First check for constants out of range,
2353 which could confuse us. */
2355 if (INTVAL (operands[1]) >= 32768)
2356 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2357 INTVAL (operands[1]) - 65536);
2359 if (INTVAL (operands[1]) > 0
2360 && INTVAL (operands[1]) <= 8)
2361 return \"addq%.w %1,%0\";
2362 if (INTVAL (operands[1]) < 0
2363 && INTVAL (operands[1]) >= -8)
2365 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2366 - INTVAL (operands[1]));
2367 return \"subq%.w %1,%0\";
2369 /* On the CPU32 it is faster to use two addqw instructions to
2370 add a small integer (8 < N <= 16) to a register.
2371 Likewise for subqw. */
2372 if (TARGET_CPU32 && REG_P (operands[0]))
2374 if (INTVAL (operands[1]) > 8
2375 && INTVAL (operands[1]) <= 16)
2377 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2378 INTVAL (operands[1]) - 8);
2379 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2381 if (INTVAL (operands[1]) < -8
2382 && INTVAL (operands[1]) >= -16)
2384 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2385 - INTVAL (operands[1]) - 8);
2386 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2390 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2392 return \"lea (%c1,%0),%0\";
2394 return \"lea %0@(%c1),%0\";
2397 return \"add%.w %1,%0\";
2400 (define_insn "addqi3"
2401 [(set (match_operand:QI 0 "general_operand" "=m,d")
2402 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2403 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2408 if (GET_CODE (operands[2]) == CONST_INT)
2410 if (INTVAL (operands[2]) >= 128)
2411 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2412 INTVAL (operands[2]) - 256);
2414 if (INTVAL (operands[2]) > 0
2415 && INTVAL (operands[2]) <= 8)
2416 return \"addq%.b %2,%0\";
2417 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2419 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2420 return \"subq%.b %2,%0\";
2424 return \"add%.b %2,%0\";
2428 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2429 (plus:QI (match_dup 0)
2430 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2435 if (GET_CODE (operands[1]) == CONST_INT)
2437 if (INTVAL (operands[1]) >= 128)
2438 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2439 INTVAL (operands[1]) - 256);
2441 if (INTVAL (operands[1]) > 0
2442 && INTVAL (operands[1]) <= 8)
2443 return \"addq%.b %1,%0\";
2444 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2446 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2447 return \"subq%.b %1,%0\";
2451 return \"add%.b %1,%0\";
2455 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2456 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2462 if (GET_CODE (operands[1]) == CONST_INT)
2464 if (INTVAL (operands[1]) >= 128)
2465 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2466 INTVAL (operands[1]) - 256);
2468 if (INTVAL (operands[1]) > 0
2469 && INTVAL (operands[1]) <= 8)
2470 return \"addq%.b %1,%0\";
2471 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2473 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2474 return \"subq%.b %1,%0\";
2478 return \"add%.b %1,%0\";
2481 (define_expand "adddf3"
2482 [(set (match_operand:DF 0 "general_operand" "")
2483 (plus:DF (match_operand:DF 1 "general_operand" "")
2484 (match_operand:DF 2 "general_operand" "")))]
2485 "TARGET_68881 || TARGET_FPA"
2489 [(set (match_operand:DF 0 "general_operand" "=x,y")
2490 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2491 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2495 if (rtx_equal_p (operands[0], operands[1]))
2496 return \"fpadd%.d %y2,%0\";
2497 if (rtx_equal_p (operands[0], operands[2]))
2498 return \"fpadd%.d %y1,%0\";
2499 if (which_alternative == 0)
2500 return \"fpadd3%.d %w2,%w1,%0\";
2501 return \"fpadd3%.d %x2,%x1,%0\";
2505 [(set (match_operand:DF 0 "general_operand" "=f")
2506 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2507 (match_operand:DF 1 "general_operand" "0")))]
2512 [(set (match_operand:DF 0 "general_operand" "=f")
2513 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2514 (match_operand:DF 1 "general_operand" "0")))]
2519 [(set (match_operand:DF 0 "general_operand" "=f")
2520 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2521 (match_operand:DF 1 "general_operand" "0")))]
2526 [(set (match_operand:DF 0 "general_operand" "=f")
2527 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2528 (match_operand:DF 2 "general_operand" "fmG")))]
2532 if (REG_P (operands[2]))
2533 return \"f%&add%.x %2,%0\";
2534 return \"f%&add%.d %f2,%0\";
2537 (define_expand "addsf3"
2538 [(set (match_operand:SF 0 "general_operand" "")
2539 (plus:SF (match_operand:SF 1 "general_operand" "")
2540 (match_operand:SF 2 "general_operand" "")))]
2541 "TARGET_68881 || TARGET_FPA"
2545 [(set (match_operand:SF 0 "general_operand" "=x,y")
2546 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2547 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2551 if (rtx_equal_p (operands[0], operands[1]))
2552 return \"fpadd%.s %w2,%0\";
2553 if (rtx_equal_p (operands[0], operands[2]))
2554 return \"fpadd%.s %w1,%0\";
2555 if (which_alternative == 0)
2556 return \"fpadd3%.s %w2,%w1,%0\";
2557 return \"fpadd3%.s %2,%1,%0\";
2561 [(set (match_operand:SF 0 "general_operand" "=f")
2562 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2563 (match_operand:SF 1 "general_operand" "0")))]
2568 [(set (match_operand:SF 0 "general_operand" "=f")
2569 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2570 (match_operand:SF 1 "general_operand" "0")))]
2575 [(set (match_operand:SF 0 "general_operand" "=f")
2576 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2577 (match_operand:SF 1 "general_operand" "0")))]
2582 [(set (match_operand:SF 0 "general_operand" "=f")
2583 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2584 (match_operand:SF 2 "general_operand" "fdmF")))]
2588 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2589 return \"f%$add%.x %2,%0\";
2590 return \"f%$add%.s %f2,%0\";
2593 ;; subtract instructions
2595 (define_insn "subdi_sexthishl32"
2596 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2597 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2598 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2600 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2605 if (ADDRESS_REG_P (operands[0]))
2606 return \"sub%.w %2,%0\";
2607 else if (ADDRESS_REG_P (operands[3]))
2608 return \"move%.w %2,%3\;sub%.l %3,%0\";
2610 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2613 (define_insn "subdi_dishl32"
2614 [(set (match_operand:DI 0 "general_operand" "+ro")
2615 (minus:DI (match_dup 0)
2616 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2622 if (GET_CODE (operands[1]) == REG)
2623 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2625 operands[1] = adj_offsettable_operand (operands[1], 4);
2626 return \"sub%.l %1,%0\";
2629 (define_insn "subdi3"
2630 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2631 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2632 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2633 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2637 if (DATA_REG_P (operands[0]))
2639 if (DATA_REG_P (operands[2]))
2640 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2641 else if (GET_CODE (operands[2]) == MEM
2642 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2644 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2648 /* TODO : this should work also for CONST operands[2] */
2649 if (GET_CODE (operands[2]) == REG)
2650 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2652 operands[1] = adj_offsettable_operand (operands[2], 4);
2653 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2656 else if (GET_CODE (operands[0]) == MEM)
2658 if (GET_CODE (operands[2]) == MEM
2659 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2660 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2662 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2664 operands[1] = gen_rtx (MEM, SImode,
2665 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2666 gen_rtx (CONST_INT, VOIDmode, -8)));
2667 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2669 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2671 operands[1] = XEXP(operands[0], 0);
2672 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2676 operands[1] = adj_offsettable_operand (operands[0], 4);
2677 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2682 (define_insn "subsi3"
2683 [(set (match_operand:SI 0 "general_operand" "=m,r")
2684 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2685 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2690 [(set (match_operand:SI 0 "general_operand" "=a")
2691 (minus:SI (match_operand:SI 1 "general_operand" "0")
2693 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2697 (define_insn "subhi3"
2698 [(set (match_operand:HI 0 "general_operand" "=m,r")
2699 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2700 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2705 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2706 (minus:HI (match_dup 0)
2707 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2711 (define_insn "subqi3"
2712 [(set (match_operand:QI 0 "general_operand" "=m,d")
2713 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2714 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2719 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2720 (minus:QI (match_dup 0)
2721 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2725 (define_expand "subdf3"
2726 [(set (match_operand:DF 0 "general_operand" "")
2727 (minus:DF (match_operand:DF 1 "general_operand" "")
2728 (match_operand:DF 2 "general_operand" "")))]
2729 "TARGET_68881 || TARGET_FPA"
2733 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2734 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2735 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2739 if (rtx_equal_p (operands[0], operands[2]))
2740 return \"fprsub%.d %y1,%0\";
2741 if (rtx_equal_p (operands[0], operands[1]))
2742 return \"fpsub%.d %y2,%0\";
2743 if (which_alternative == 0)
2744 return \"fpsub3%.d %w2,%w1,%0\";
2745 return \"fpsub3%.d %x2,%x1,%0\";
2749 [(set (match_operand:DF 0 "general_operand" "=f")
2750 (minus:DF (match_operand:DF 1 "general_operand" "0")
2751 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2756 [(set (match_operand:DF 0 "general_operand" "=f")
2757 (minus:DF (match_operand:DF 1 "general_operand" "0")
2758 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2763 [(set (match_operand:DF 0 "general_operand" "=f")
2764 (minus:DF (match_operand:DF 1 "general_operand" "0")
2765 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2770 [(set (match_operand:DF 0 "general_operand" "=f")
2771 (minus:DF (match_operand:DF 1 "general_operand" "0")
2772 (match_operand:DF 2 "general_operand" "fmG")))]
2776 if (REG_P (operands[2]))
2777 return \"f%&sub%.x %2,%0\";
2778 return \"f%&sub%.d %f2,%0\";
2781 (define_expand "subsf3"
2782 [(set (match_operand:SF 0 "general_operand" "")
2783 (minus:SF (match_operand:SF 1 "general_operand" "")
2784 (match_operand:SF 2 "general_operand" "")))]
2785 "TARGET_68881 || TARGET_FPA"
2789 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2790 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2791 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2795 if (rtx_equal_p (operands[0], operands[2]))
2796 return \"fprsub%.s %w1,%0\";
2797 if (rtx_equal_p (operands[0], operands[1]))
2798 return \"fpsub%.s %w2,%0\";
2799 if (which_alternative == 0)
2800 return \"fpsub3%.s %w2,%w1,%0\";
2801 return \"fpsub3%.s %2,%1,%0\";
2805 [(set (match_operand:SF 0 "general_operand" "=f")
2806 (minus:SF (match_operand:SF 1 "general_operand" "0")
2807 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2812 [(set (match_operand:SF 0 "general_operand" "=f")
2813 (minus:SF (match_operand:SF 1 "general_operand" "0")
2814 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2819 [(set (match_operand:SF 0 "general_operand" "=f")
2820 (minus:SF (match_operand:SF 1 "general_operand" "0")
2821 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2826 [(set (match_operand:SF 0 "general_operand" "=f")
2827 (minus:SF (match_operand:SF 1 "general_operand" "0")
2828 (match_operand:SF 2 "general_operand" "fdmF")))]
2832 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2833 return \"f%$sub%.x %2,%0\";
2834 return \"f%$sub%.s %f2,%0\";
2837 ;; multiply instructions
2839 (define_insn "mulhi3"
2840 [(set (match_operand:HI 0 "general_operand" "=d")
2841 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2842 (match_operand:HI 2 "general_operand" "dmn")))]
2846 #if defined(MOTOROLA) && !defined(CRDS)
2847 return \"muls%.w %2,%0\";
2849 return \"muls %2,%0\";
2853 (define_insn "mulhisi3"
2854 [(set (match_operand:SI 0 "general_operand" "=d")
2855 (mult:SI (sign_extend:SI
2856 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2858 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2862 #if defined(MOTOROLA) && !defined(CRDS)
2863 return \"muls%.w %2,%0\";
2865 return \"muls %2,%0\";
2870 [(set (match_operand:SI 0 "general_operand" "=d")
2871 (mult:SI (sign_extend:SI
2872 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2873 (match_operand:SI 2 "const_int_operand" "n")))]
2874 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2877 #if defined(MOTOROLA) && !defined(CRDS)
2878 return \"muls%.w %2,%0\";
2880 return \"muls %2,%0\";
2884 (define_insn "mulsi3"
2885 [(set (match_operand:SI 0 "general_operand" "=d")
2886 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2887 (match_operand:SI 2 "general_operand" "dmsK")))]
2888 "TARGET_68020 || TARGET_5200"
2891 (define_insn "umulhisi3"
2892 [(set (match_operand:SI 0 "general_operand" "=d")
2893 (mult:SI (zero_extend:SI
2894 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2896 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2900 #if defined(MOTOROLA) && !defined(CRDS)
2901 return \"mulu%.w %2,%0\";
2903 return \"mulu %2,%0\";
2908 [(set (match_operand:SI 0 "general_operand" "=d")
2909 (mult:SI (zero_extend:SI
2910 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2911 (match_operand:SI 2 "const_int_operand" "n")))]
2912 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2915 #if defined(MOTOROLA) && !defined(CRDS)
2916 return \"mulu%.w %2,%0\";
2918 return \"mulu %2,%0\";
2922 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2923 ;; proper matching constraint. This is because the matching is between
2924 ;; the high-numbered word of the DImode operand[0] and operand[1].
2925 (define_expand "umulsidi3"
2927 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2928 (mult:SI (match_operand:SI 1 "register_operand" "")
2929 (match_operand:SI 2 "nonimmediate_operand" "")))
2930 (set (subreg:SI (match_dup 0) 0)
2931 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2932 (zero_extend:DI (match_dup 2)))
2933 (const_int 32))))])]
2934 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2938 [(set (match_operand:SI 0 "register_operand" "=d")
2939 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2940 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2941 (set (match_operand:SI 3 "register_operand" "=d")
2942 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2943 (zero_extend:DI (match_dup 2)))
2945 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2948 ; Match immediate case. For 2.4 only match things < 2^31.
2949 ; It's tricky with larger values in these patterns since we need to match
2950 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2953 [(set (match_operand:SI 0 "register_operand" "=d")
2954 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2955 (match_operand:SI 2 "const_int_operand" "n")))
2956 (set (match_operand:SI 3 "register_operand" "=d")
2957 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2960 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2961 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2964 (define_expand "mulsidi3"
2966 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2967 (mult:SI (match_operand:SI 1 "register_operand" "")
2968 (match_operand:SI 2 "nonimmediate_operand" "")))
2969 (set (subreg:SI (match_dup 0) 0)
2970 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2971 (sign_extend:DI (match_dup 2)))
2972 (const_int 32))))])]
2973 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2977 [(set (match_operand:SI 0 "register_operand" "=d")
2978 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2979 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2980 (set (match_operand:SI 3 "register_operand" "=d")
2981 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2982 (sign_extend:DI (match_dup 2)))
2984 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2988 [(set (match_operand:SI 0 "register_operand" "=d")
2989 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2990 (match_operand:SI 2 "const_sint32_operand" "")))
2991 (set (match_operand:SI 3 "register_operand" "=d")
2992 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2995 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2998 (define_expand "umulsi3_highpart"
3000 [(set (match_operand:SI 0 "register_operand" "")
3003 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3004 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3006 (clobber (match_dup 3))])]
3007 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3010 operands[3] = gen_reg_rtx (SImode);
3011 if (GET_CODE (operands[2]) == CONST_INT
3012 || GET_CODE (operands[2]) == CONST_DOUBLE)
3014 if (! const_uint32_operand (operands[2], VOIDmode))
3016 /* We have to adjust the operand order for the matching constraints. */
3017 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3018 operands[1], operands[2]));
3024 [(set (match_operand:SI 0 "register_operand" "=d")
3027 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3028 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3030 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3031 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3034 (define_insn "const_umulsi3_highpart"
3035 [(set (match_operand:SI 0 "register_operand" "=d")
3038 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3039 (match_operand 3 "const_uint32_operand" ""))
3041 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3042 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3045 (define_expand "smulsi3_highpart"
3047 [(set (match_operand:SI 0 "register_operand" "")
3050 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3051 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3053 (clobber (match_dup 3))])]
3054 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3057 operands[3] = gen_reg_rtx (SImode);
3058 if (GET_CODE (operands[2]) == CONST_INT
3059 || GET_CODE (operands[2]) == CONST_DOUBLE)
3061 if (! const_sint32_operand (operands[2], VOIDmode))
3063 /* We have to adjust the operand order for the matching constraints. */
3064 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3065 operands[1], operands[2]));
3071 [(set (match_operand:SI 0 "register_operand" "=d")
3074 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3075 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3077 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3078 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3081 (define_insn "const_smulsi3_highpart"
3082 [(set (match_operand:SI 0 "register_operand" "=d")
3085 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3086 (match_operand 3 "const_sint32_operand" ""))
3088 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3089 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3092 (define_expand "muldf3"
3093 [(set (match_operand:DF 0 "general_operand" "")
3094 (mult:DF (match_operand:DF 1 "general_operand" "")
3095 (match_operand:DF 2 "general_operand" "")))]
3096 "TARGET_68881 || TARGET_FPA"
3100 [(set (match_operand:DF 0 "general_operand" "=x,y")
3101 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3102 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3106 if (rtx_equal_p (operands[1], operands[2]))
3107 return \"fpsqr%.d %y1,%0\";
3108 if (rtx_equal_p (operands[0], operands[1]))
3109 return \"fpmul%.d %y2,%0\";
3110 if (rtx_equal_p (operands[0], operands[2]))
3111 return \"fpmul%.d %y1,%0\";
3112 if (which_alternative == 0)
3113 return \"fpmul3%.d %w2,%w1,%0\";
3114 return \"fpmul3%.d %x2,%x1,%0\";
3118 [(set (match_operand:DF 0 "general_operand" "=f")
3119 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3120 (match_operand:DF 1 "general_operand" "0")))]
3125 [(set (match_operand:DF 0 "general_operand" "=f")
3126 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3127 (match_operand:DF 1 "general_operand" "0")))]
3132 [(set (match_operand:DF 0 "general_operand" "=f")
3133 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3134 (match_operand:DF 1 "general_operand" "0")))]
3139 [(set (match_operand:DF 0 "general_operand" "=f")
3140 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3141 (match_operand:DF 2 "general_operand" "fmG")))]
3145 if (GET_CODE (operands[2]) == CONST_DOUBLE
3146 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3148 int i = floating_exact_log2 (operands[2]);
3149 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3150 return \"fscale%.l %2,%0\";
3152 if (REG_P (operands[2]))
3153 return \"f%&mul%.x %2,%0\";
3154 return \"f%&mul%.d %f2,%0\";
3157 (define_expand "mulsf3"
3158 [(set (match_operand:SF 0 "general_operand" "")
3159 (mult:SF (match_operand:SF 1 "general_operand" "")
3160 (match_operand:SF 2 "general_operand" "")))]
3161 "TARGET_68881 || TARGET_FPA"
3165 [(set (match_operand:SF 0 "general_operand" "=x,y")
3166 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3167 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3171 if (rtx_equal_p (operands[1], operands[2]))
3172 return \"fpsqr%.s %w1,%0\";
3173 if (rtx_equal_p (operands[0], operands[1]))
3174 return \"fpmul%.s %w2,%0\";
3175 if (rtx_equal_p (operands[0], operands[2]))
3176 return \"fpmul%.s %w1,%0\";
3177 if (which_alternative == 0)
3178 return \"fpmul3%.s %w2,%w1,%0\";
3179 return \"fpmul3%.s %2,%1,%0\";
3183 [(set (match_operand:SF 0 "general_operand" "=f")
3184 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3185 (match_operand:SF 1 "general_operand" "0")))]
3189 return (TARGET_68040_ONLY
3190 ? \"fsmul%.l %2,%0\"
3191 : \"fsglmul%.l %2,%0\");
3195 [(set (match_operand:SF 0 "general_operand" "=f")
3196 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3197 (match_operand:SF 1 "general_operand" "0")))]
3201 return (TARGET_68040_ONLY
3202 ? \"fsmul%.w %2,%0\"
3203 : \"fsglmul%.w %2,%0\");
3207 [(set (match_operand:SF 0 "general_operand" "=f")
3208 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3209 (match_operand:SF 1 "general_operand" "0")))]
3213 return (TARGET_68040_ONLY
3214 ? \"fsmul%.b %2,%0\"
3215 : \"fsglmul%.b %2,%0\");
3219 [(set (match_operand:SF 0 "general_operand" "=f")
3220 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3221 (match_operand:SF 2 "general_operand" "fdmF")))]
3225 #ifdef FSGLMUL_USE_S
3226 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3227 return (TARGET_68040_ONLY
3228 ? \"fsmul%.s %2,%0\"
3229 : \"fsglmul%.s %2,%0\");
3231 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3232 return (TARGET_68040_ONLY
3233 ? \"fsmul%.x %2,%0\"
3234 : \"fsglmul%.x %2,%0\");
3236 return (TARGET_68040_ONLY
3237 ? \"fsmul%.s %f2,%0\"
3238 : \"fsglmul%.s %f2,%0\");
3241 ;; divide instructions
3243 (define_expand "divdf3"
3244 [(set (match_operand:DF 0 "general_operand" "")
3245 (div:DF (match_operand:DF 1 "general_operand" "")
3246 (match_operand:DF 2 "general_operand" "")))]
3247 "TARGET_68881 || TARGET_FPA"
3251 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3252 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3253 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3257 if (rtx_equal_p (operands[0], operands[2]))
3258 return \"fprdiv%.d %y1,%0\";
3259 if (rtx_equal_p (operands[0], operands[1]))
3260 return \"fpdiv%.d %y2,%0\";
3261 if (which_alternative == 0)
3262 return \"fpdiv3%.d %w2,%w1,%0\";
3263 return \"fpdiv3%.d %x2,%x1,%x0\";
3267 [(set (match_operand:DF 0 "general_operand" "=f")
3268 (div:DF (match_operand:DF 1 "general_operand" "0")
3269 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3274 [(set (match_operand:DF 0 "general_operand" "=f")
3275 (div:DF (match_operand:DF 1 "general_operand" "0")
3276 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3281 [(set (match_operand:DF 0 "general_operand" "=f")
3282 (div:DF (match_operand:DF 1 "general_operand" "0")
3283 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3288 [(set (match_operand:DF 0 "general_operand" "=f")
3289 (div:DF (match_operand:DF 1 "general_operand" "0")
3290 (match_operand:DF 2 "general_operand" "fmG")))]
3294 if (REG_P (operands[2]))
3295 return \"f%&div%.x %2,%0\";
3296 return \"f%&div%.d %f2,%0\";
3299 (define_expand "divsf3"
3300 [(set (match_operand:SF 0 "general_operand" "")
3301 (div:SF (match_operand:SF 1 "general_operand" "")
3302 (match_operand:SF 2 "general_operand" "")))]
3303 "TARGET_68881 || TARGET_FPA"
3307 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3308 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3309 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3313 if (rtx_equal_p (operands[0], operands[1]))
3314 return \"fpdiv%.s %w2,%0\";
3315 if (rtx_equal_p (operands[0], operands[2]))
3316 return \"fprdiv%.s %w1,%0\";
3317 if (which_alternative == 0)
3318 return \"fpdiv3%.s %w2,%w1,%0\";
3319 return \"fpdiv3%.s %2,%1,%0\";
3323 [(set (match_operand:SF 0 "general_operand" "=f")
3324 (div:SF (match_operand:SF 1 "general_operand" "0")
3325 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3329 return (TARGET_68040_ONLY
3330 ? \"fsdiv%.l %2,%0\"
3331 : \"fsgldiv%.l %2,%0\");
3335 [(set (match_operand:SF 0 "general_operand" "=f")
3336 (div:SF (match_operand:SF 1 "general_operand" "0")
3337 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3341 return (TARGET_68040_ONLY
3342 ? \"fsdiv%.w %2,%0\"
3343 : \"fsgldiv%.w %2,%0\");
3347 [(set (match_operand:SF 0 "general_operand" "=f")
3348 (div:SF (match_operand:SF 1 "general_operand" "0")
3349 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3353 return (TARGET_68040_ONLY
3354 ? \"fsdiv%.b %2,%0\"
3355 : \"fsgldiv%.b %2,%0\");
3359 [(set (match_operand:SF 0 "general_operand" "=f")
3360 (div:SF (match_operand:SF 1 "general_operand" "0")
3361 (match_operand:SF 2 "general_operand" "fdmF")))]
3365 #ifdef FSGLDIV_USE_S
3366 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3367 return (TARGET_68040_ONLY
3368 ? \"fsdiv%.s %2,%0\"
3369 : \"fsgldiv%.s %2,%0\");
3371 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3372 return (TARGET_68040_ONLY
3373 ? \"fsdiv%.x %2,%0\"
3374 : \"fsgldiv%.x %2,%0\");
3376 return (TARGET_68040_ONLY
3377 ? \"fsdiv%.s %f2,%0\"
3378 : \"fsgldiv%.s %f2,%0\");
3381 ;; Remainder instructions.
3383 (define_insn "divmodsi4"
3384 [(set (match_operand:SI 0 "general_operand" "=d")
3385 (div:SI (match_operand:SI 1 "general_operand" "0")
3386 (match_operand:SI 2 "general_operand" "dmsK")))
3387 (set (match_operand:SI 3 "general_operand" "=d")
3388 (mod:SI (match_dup 1) (match_dup 2)))]
3389 "TARGET_68020 && !TARGET_5200"
3392 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3393 return \"divs%.l %2,%0\";
3395 return \"divsl%.l %2,%3:%0\";
3398 (define_insn "udivmodsi4"
3399 [(set (match_operand:SI 0 "general_operand" "=d")
3400 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3401 (match_operand:SI 2 "general_operand" "dmsK")))
3402 (set (match_operand:SI 3 "general_operand" "=d")
3403 (umod:SI (match_dup 1) (match_dup 2)))]
3404 "TARGET_68020 && !TARGET_5200"
3407 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3408 return \"divu%.l %2,%0\";
3410 return \"divul%.l %2,%3:%0\";
3413 (define_insn "divmodhi4"
3414 [(set (match_operand:HI 0 "general_operand" "=d")
3415 (div:HI (match_operand:HI 1 "general_operand" "0")
3416 (match_operand:HI 2 "general_operand" "dmsK")))
3417 (set (match_operand:HI 3 "general_operand" "=d")
3418 (mod:HI (match_dup 1) (match_dup 2)))]
3423 output_asm_insn(\"ext%.l %0\;divs%.w %2,%0\", operands);
3425 output_asm_insn(\"extl %0\;divs %2,%0\", operands);
3427 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3430 return \"move%.l %0,%3\;swap %3\";
3436 (define_insn "udivmodhi4"
3437 [(set (match_operand:HI 0 "general_operand" "=d")
3438 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3439 (match_operand:HI 2 "general_operand" "dmsK")))
3440 (set (match_operand:HI 3 "general_operand" "=d")
3441 (umod:HI (match_dup 1) (match_dup 2)))]
3446 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3448 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3450 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3453 return \"move%.l %0,%3\;swap %3\";
3459 ;; logical-and instructions
3461 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3462 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3463 ;; can't allocate pseudos into it.
3465 (define_expand "andsi3"
3466 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3467 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3468 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3472 (define_insn "andsi3_internal"
3473 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3474 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3475 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3480 if (GET_CODE (operands[2]) == CONST_INT
3481 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3482 && (DATA_REG_P (operands[0])
3483 || offsettable_memref_p (operands[0])))
3485 if (GET_CODE (operands[0]) != REG)
3486 operands[0] = adj_offsettable_operand (operands[0], 2);
3487 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3488 INTVAL (operands[2]) & 0xffff);
3489 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3491 if (operands[2] == const0_rtx)
3492 return \"clr%.w %0\";
3493 return \"and%.w %2,%0\";
3495 if (GET_CODE (operands[2]) == CONST_INT
3496 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3497 && (DATA_REG_P (operands[0])
3498 || offsettable_memref_p (operands[0])))
3500 if (DATA_REG_P (operands[0]))
3502 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3506 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3507 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3509 /* This does not set condition codes in a standard way. */
3511 return \"bclr %1,%0\";
3513 return \"and%.l %2,%0\";
3516 (define_insn "andsi3_5200"
3517 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3518 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3519 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3523 (define_insn "andhi3"
3524 [(set (match_operand:HI 0 "general_operand" "=m,d")
3525 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3526 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3531 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3532 (and:HI (match_dup 0)
3533 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3538 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3539 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3544 (define_insn "andqi3"
3545 [(set (match_operand:QI 0 "general_operand" "=m,d")
3546 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3547 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3552 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3553 (and:QI (match_dup 0)
3554 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3559 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3560 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3565 ;; inclusive-or instructions
3567 (define_expand "iorsi3"
3568 [(set (match_operand:SI 0 "general_operand" "")
3569 (ior:SI (match_operand:SI 1 "general_operand" "")
3570 (match_operand:SI 2 "general_operand" "")))]
3574 (define_insn "iorsi3_internal"
3575 [(set (match_operand:SI 0 "general_operand" "=m,d")
3576 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3577 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3581 register int logval;
3582 if (GET_CODE (operands[2]) == CONST_INT
3583 && INTVAL (operands[2]) >> 16 == 0
3584 && (DATA_REG_P (operands[0])
3585 || offsettable_memref_p (operands[0])))
3587 if (GET_CODE (operands[0]) != REG)
3588 operands[0] = adj_offsettable_operand (operands[0], 2);
3589 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3591 return \"or%.w %2,%0\";
3593 if (GET_CODE (operands[2]) == CONST_INT
3594 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3595 && (DATA_REG_P (operands[0])
3596 || offsettable_memref_p (operands[0])))
3598 if (DATA_REG_P (operands[0]))
3600 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3604 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3605 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3608 return \"bset %1,%0\";
3610 return \"or%.l %2,%0\";
3613 (define_insn "iorsi3_5200"
3614 [(set (match_operand:SI 0 "general_operand" "=m,d")
3615 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3616 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3620 (define_insn "iorhi3"
3621 [(set (match_operand:HI 0 "general_operand" "=m,d")
3622 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3623 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3628 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3629 (ior:HI (match_dup 0)
3630 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3635 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3636 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3641 (define_insn "iorqi3"
3642 [(set (match_operand:QI 0 "general_operand" "=m,d")
3643 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3644 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3649 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3650 (ior:QI (match_dup 0)
3651 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3656 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3657 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3662 ;; On all 68k models, this makes faster code in a special case.
3663 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3665 (define_insn "iorsi_zexthi_ashl16"
3666 [(set (match_operand:SI 0 "general_operand" "=d,d")
3667 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3668 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3674 if (GET_CODE (operands[2]) != REG)
3676 operands[2] = adj_offsettable_operand (operands[2], 2);
3677 output_asm_insn (\"move%.w %2,%0\", operands);
3679 return \"swap %0\;mov%.w %1,%0\";
3683 [(set (match_operand:SI 0 "general_operand" "=o,d")
3684 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3685 (match_operand:SI 2 "general_operand" "0,0")))]
3692 byte_mode = (GET_MODE(operands[1]) == QImode);
3693 if (GET_CODE (operands[0]) == MEM)
3694 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3696 return \"or%.b %1,%0\";
3698 return \"or%.w %1,%0\";
3703 (define_expand "xorsi3"
3704 [(set (match_operand:SI 0 "general_operand" "")
3705 (xor:SI (match_operand:SI 1 "general_operand" "")
3706 (match_operand:SI 2 "general_operand" "")))]
3710 (define_insn "xorsi3_internal"
3711 [(set (match_operand:SI 0 "general_operand" "=do,m")
3712 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3713 (match_operand:SI 2 "general_operand" "di,dKs")))]
3717 if (GET_CODE (operands[2]) == CONST_INT
3718 && INTVAL (operands[2]) >> 16 == 0
3719 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
3721 if (! DATA_REG_P (operands[0]))
3722 operands[0] = adj_offsettable_operand (operands[0], 2);
3723 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3725 return \"eor%.w %2,%0\";
3727 return \"eor%.l %2,%0\";
3730 (define_insn "xorsi3_5200"
3731 [(set (match_operand:SI 0 "general_operand" "=dm")
3732 (xor:SI (match_operand:SI 1 "general_operand" "%0")
3733 (match_operand:SI 2 "general_operand" "dn")))]
3737 (define_insn "xorhi3"
3738 [(set (match_operand:HI 0 "general_operand" "=dm")
3739 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3740 (match_operand:HI 2 "general_operand" "dn")))]
3745 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3746 (xor:HI (match_dup 0)
3747 (match_operand:HI 1 "general_operand" "dn")))]
3752 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3753 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3758 (define_insn "xorqi3"
3759 [(set (match_operand:QI 0 "general_operand" "=dm")
3760 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3761 (match_operand:QI 2 "general_operand" "dn")))]
3766 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3767 (xor:QI (match_dup 0)
3768 (match_operand:QI 1 "general_operand" "dn")))]
3773 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3774 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3779 ;; negation instructions
3781 (define_expand "negdi2"
3782 [(set (match_operand:DI 0 "general_operand" "")
3783 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3788 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3790 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3794 (define_insn "negdi2_internal"
3795 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
3796 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3800 if (which_alternative == 0)
3801 return \"neg%.l %0\;negx%.l %0\";
3802 if (GET_CODE (operands[0]) == REG)
3803 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3805 operands[1] = adj_offsettable_operand (operands[0], 4);
3806 if (ADDRESS_REG_P (operands[0]))
3807 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3809 return \"neg%.l %1\;negx%.l %0\";
3812 (define_insn "negdi2_5200"
3813 [(set (match_operand:DI 0 "general_operand" "=d")
3814 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3818 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3819 return \"neg%.l %1\;negx%.l %0\";
3822 (define_expand "negsi2"
3823 [(set (match_operand:SI 0 "general_operand" "")
3824 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3829 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3831 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3835 (define_insn "negsi2_internal"
3836 [(set (match_operand:SI 0 "general_operand" "=dm")
3837 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3841 (define_insn "negsi2_5200"
3842 [(set (match_operand:SI 0 "general_operand" "=d")
3843 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3847 (define_insn "neghi2"
3848 [(set (match_operand:HI 0 "general_operand" "=dm")
3849 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3854 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3855 (neg:HI (match_dup 0)))]
3859 (define_insn "negqi2"
3860 [(set (match_operand:QI 0 "general_operand" "=dm")
3861 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3866 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3867 (neg:QI (match_dup 0)))]
3871 ;; If using software floating point, just flip the sign bit.
3873 (define_expand "negsf2"
3874 [(set (match_operand:SF 0 "general_operand" "")
3875 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3879 if (!TARGET_FPA && !TARGET_68881)
3884 target = operand_subword_force (operands[0], 0, SFmode);
3885 result = expand_binop (SImode, xor_optab,
3886 operand_subword_force (operands[1], 0, SFmode),
3887 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3891 if (result != target)
3892 emit_move_insn (result, target);
3894 /* Make a place for REG_EQUAL. */
3895 emit_move_insn (operands[0], operands[0]);
3901 [(set (match_operand:SF 0 "general_operand" "=x,y")
3902 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3907 [(set (match_operand:SF 0 "general_operand" "=f,d")
3908 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3912 if (DATA_REG_P (operands[0]))
3914 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3915 return \"bchg %1,%0\";
3917 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3918 return \"f%$neg%.x %1,%0\";
3919 return \"f%$neg%.s %f1,%0\";
3922 (define_expand "negdf2"
3923 [(set (match_operand:DF 0 "general_operand" "")
3924 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3928 if (!TARGET_FPA && !TARGET_68881)
3935 target = operand_subword (operands[0], 0, 1, DFmode);
3936 result = expand_binop (SImode, xor_optab,
3937 operand_subword_force (operands[1], 0, DFmode),
3938 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3942 if (result != target)
3943 emit_move_insn (result, target);
3945 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3946 operand_subword_force (operands[1], 1, DFmode));
3948 insns = get_insns ();
3951 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3957 [(set (match_operand:DF 0 "general_operand" "=x,y")
3958 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3963 [(set (match_operand:DF 0 "general_operand" "=f,d")
3964 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3968 if (DATA_REG_P (operands[0]))
3970 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3971 return \"bchg %1,%0\";
3973 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3974 return \"f%&neg%.x %1,%0\";
3975 return \"f%&neg%.d %f1,%0\";
3978 ;; Sqrt instruction for the 68881
3980 (define_insn "sqrtsf2"
3981 [(set (match_operand:SF 0 "general_operand" "=f")
3982 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3986 if (FP_REG_P (operands[1]))
3987 return \"f%$sqrt%.x %1,%0\";
3989 return \"f%$sqrt%.s %1,%0\";
3992 (define_insn "sqrtdf2"
3993 [(set (match_operand:DF 0 "general_operand" "=f")
3994 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3998 if (FP_REG_P (operands[1]))
3999 return \"f%&sqrt%.x %1,%0\";
4001 return \"f%&sqrt%.d %1,%0\";
4004 ;; Absolute value instructions
4005 ;; If using software floating point, just zero the sign bit.
4007 (define_expand "abssf2"
4008 [(set (match_operand:SF 0 "general_operand" "")
4009 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4013 if (!TARGET_FPA && !TARGET_68881)
4018 target = operand_subword_force (operands[0], 0, SFmode);
4019 result = expand_binop (SImode, and_optab,
4020 operand_subword_force (operands[1], 0, SFmode),
4021 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4025 if (result != target)
4026 emit_move_insn (result, target);
4028 /* Make a place for REG_EQUAL. */
4029 emit_move_insn (operands[0], operands[0]);
4035 [(set (match_operand:SF 0 "general_operand" "=x,y")
4036 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4041 [(set (match_operand:SF 0 "general_operand" "=f")
4042 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4046 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4047 return \"f%$abs%.x %1,%0\";
4048 return \"f%$abs%.s %f1,%0\";
4051 (define_expand "absdf2"
4052 [(set (match_operand:DF 0 "general_operand" "")
4053 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4057 if (!TARGET_FPA && !TARGET_68881)
4064 target = operand_subword (operands[0], 0, 1, DFmode);
4065 result = expand_binop (SImode, and_optab,
4066 operand_subword_force (operands[1], 0, DFmode),
4067 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4071 if (result != target)
4072 emit_move_insn (result, target);
4074 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4075 operand_subword_force (operands[1], 1, DFmode));
4077 insns = get_insns ();
4080 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4086 [(set (match_operand:DF 0 "general_operand" "=x,y")
4087 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4092 [(set (match_operand:DF 0 "general_operand" "=f")
4093 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4097 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4098 return \"f%&abs%.x %1,%0\";
4099 return \"f%&abs%.d %f1,%0\";
4102 ;; one complement instructions
4104 ;; "one_cmpldi2" is only here to help combine().
4105 (define_insn "one_cmpldi2"
4106 [(set (match_operand:DI 0 "general_operand" "=dm")
4107 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4112 if (GET_CODE (operands[0]) == REG)
4113 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4114 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4115 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4116 operands[1] = operands[0];
4118 operands[1] = adj_offsettable_operand (operands[0], 4);
4119 return \"not%.l %1\;not%.l %0\";
4122 (define_expand "one_cmplsi2"
4123 [(set (match_operand:SI 0 "general_operand" "")
4124 (not:SI (match_operand:SI 1 "general_operand" "")))]
4129 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4131 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4135 (define_insn "one_cmplsi2_internal"
4136 [(set (match_operand:SI 0 "general_operand" "=dm")
4137 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4141 (define_insn "one_cmplsi2_5200"
4142 [(set (match_operand:SI 0 "general_operand" "=d")
4143 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4147 (define_insn "one_cmplhi2"
4148 [(set (match_operand:HI 0 "general_operand" "=dm")
4149 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4154 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4155 (not:HI (match_dup 0)))]
4159 (define_insn "one_cmplqi2"
4160 [(set (match_operand:QI 0 "general_operand" "=dm")
4161 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4166 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4167 (not:QI (match_dup 0)))]
4171 ;; arithmetic shift instructions
4172 ;; We don't need the shift memory by 1 bit instruction
4174 (define_insn "ashldi_extsi"
4175 [(set (match_operand:DI 0 "general_operand" "=ro")
4177 (match_operator:DI 2 "extend_operator"
4178 [(match_operand:SI 1 "general_operand" "rm")])
4184 if (GET_CODE (operands[0]) == REG)
4185 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4187 operands[2] = adj_offsettable_operand (operands[0], 4);
4188 if (ADDRESS_REG_P (operands[0]))
4189 return \"move%.l %1,%0\;sub%.l %2,%2\";
4191 return \"move%.l %1,%0\;clr%.l %2\";
4194 (define_insn "ashldi_sexthi"
4195 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4196 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4198 (clobber (match_scratch:SI 2 "=a,X"))]
4203 if (GET_CODE (operands[0]) == MEM)
4205 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4206 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4207 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4208 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4211 operands[3] = adj_offsettable_operand (operands[0], 4);
4212 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4215 else if (DATA_REG_P (operands[0]))
4216 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4218 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4221 (define_insn "ashldi_const32"
4222 [(set (match_operand:DI 0 "general_operand" "=rm")
4223 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4229 if (GET_CODE (operands[1]) == REG)
4230 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4232 operands[3] = adj_offsettable_operand (operands[1], 4);
4233 if (GET_CODE (operands[0]) == REG)
4234 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4235 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4236 return \"clr%.l %0\;move%.l %3,%0\";
4237 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4238 return \"move%.l %3,%0\;clr%.l %0\";
4240 operands[2] = adj_offsettable_operand (operands[0], 4);
4241 if (ADDRESS_REG_P (operands[2]))
4242 return \"move%.l %3,%0\;sub%.l %2,%2\";
4244 return \"move%.l %3,%0\;clr%.l %2\";
4247 ;; The predicate below must be general_operand, because ashldi3 allows that
4248 (define_insn "ashldi_const"
4249 [(set (match_operand:DI 0 "general_operand" "=d")
4250 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4251 (match_operand 2 "const_int_operand" "n")))]
4252 "(INTVAL (operands[2]) == 1
4253 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4254 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4257 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4258 if (INTVAL (operands[2]) == 1)
4259 return \"add%.l %1,%1\;addx%.l %0,%0\";
4260 else if (INTVAL (operands[2]) == 8)
4261 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4262 else if (INTVAL (operands[2]) == 16)
4263 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4264 else if (INTVAL (operands[2]) == 2)
4265 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4266 else/* if (INTVAL (operands[2]) == 3)*/
4267 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4270 (define_expand "ashldi3"
4271 [(set (match_operand:DI 0 "general_operand" "")
4272 (ashift:DI (match_operand:DI 1 "general_operand" "")
4273 (match_operand 2 "const_int_operand" "")))]
4277 if (GET_CODE (operands[2]) != CONST_INT
4278 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4279 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4280 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4284 ;; On most 68k models, this makes faster code in a special case.
4286 (define_insn "ashlsi_16"
4287 [(set (match_operand:SI 0 "register_operand" "=d")
4288 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4294 return \"swap %0\;clr%.w %0\";
4297 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4298 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4300 ;; On the 68000, this makes faster code in a special case.
4302 (define_insn "ashlsi_17_24"
4303 [(set (match_operand:SI 0 "register_operand" "=d")
4304 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4305 (match_operand:SI 2 "const_int_operand" "n")))]
4306 "(! TARGET_68020 && !TARGET_5200
4307 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4312 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4313 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4316 (define_insn "ashlsi3"
4317 [(set (match_operand:SI 0 "register_operand" "=d")
4318 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4319 (match_operand:SI 2 "general_operand" "dI")))]
4323 if (operands[2] == const1_rtx)
4325 cc_status.flags = CC_NO_OVERFLOW;
4326 return \"add%.l %0,%0\";
4328 return \"lsl%.l %2,%0\";
4331 (define_insn "ashlhi3"
4332 [(set (match_operand:HI 0 "register_operand" "=d")
4333 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4334 (match_operand:HI 2 "general_operand" "dI")))]
4339 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4340 (ashift:HI (match_dup 0)
4341 (match_operand:HI 1 "general_operand" "dI")))]
4345 (define_insn "ashlqi3"
4346 [(set (match_operand:QI 0 "register_operand" "=d")
4347 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4348 (match_operand:QI 2 "general_operand" "dI")))]
4353 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4354 (ashift:QI (match_dup 0)
4355 (match_operand:QI 1 "general_operand" "dI")))]
4359 ;; On all 68k models, this makes faster code in a special case.
4361 (define_insn "ashrsi_16"
4362 [(set (match_operand:SI 0 "register_operand" "=d")
4363 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4366 "swap %0\;ext%.l %0")
4368 ;; On the 68000, this makes faster code in a special case.
4371 [(set (match_operand:SI 0 "register_operand" "=d")
4372 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4373 (match_operand:SI 2 "const_int_operand" "n")))]
4374 "(! TARGET_68020 && !TARGET_5200
4375 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4378 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4379 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4382 (define_insn "subreghi1ashrdi_const32"
4383 [(set (match_operand:HI 0 "general_operand" "=rm")
4384 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4385 (const_int 32)) 1))]
4389 if (GET_CODE (operands[1]) != REG)
4390 operands[1] = adj_offsettable_operand (operands[1], 2);
4391 return \"move%.w %1,%0\";
4394 (define_insn "subregsi1ashrdi_const32"
4395 [(set (match_operand:SI 0 "general_operand" "=rm")
4396 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4397 (const_int 32)) 1))]
4401 return \"move%.l %1,%0\";
4404 (define_insn "ashrdi_const32"
4405 [(set (match_operand:DI 0 "register_operand" "=d")
4406 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4412 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4414 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4416 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4419 (define_insn "ashrdi_const32_mem"
4420 [(set (match_operand:DI 0 "general_operand" "=o,<")
4421 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4423 (clobber (match_scratch:SI 2 "=d,d"))]
4428 if (which_alternative == 1)
4429 operands[3] = operands[0];
4431 operands[3] = adj_offsettable_operand (operands[0], 4);
4433 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4435 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4438 ;; The predicate below must be general_operand, because ashrdi3 allows that
4439 (define_insn "ashrdi_const"
4440 [(set (match_operand:DI 0 "general_operand" "=d")
4441 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4442 (match_operand 2 "const_int_operand" "n")))]
4444 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4445 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4446 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4449 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4450 if (INTVAL (operands[2]) == 63)
4451 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4453 if (INTVAL (operands[2]) == 1)
4454 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4455 else if (INTVAL (operands[2]) == 8)
4456 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4457 else if (INTVAL (operands[2]) == 16)
4458 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4459 else if (INTVAL (operands[2]) == 2)
4460 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4461 else/* if (INTVAL (operands[2]) == 3)*/
4462 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4465 (define_expand "ashrdi3"
4466 [(set (match_operand:DI 0 "general_operand" "")
4467 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4468 (match_operand 2 "const_int_operand" "")))]
4472 if (GET_CODE (operands[2]) != CONST_INT
4473 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4474 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4475 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4476 && INTVAL (operands[2]) != 63))
4480 ;; On all 68k models, this makes faster code in a special case.
4482 (define_insn "ashrsi_31"
4483 [(set (match_operand:SI 0 "register_operand" "=d")
4484 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4489 return \"add%.l %0,%0\;subx%.l %0,%0\";
4492 (define_insn "ashrsi3"
4493 [(set (match_operand:SI 0 "register_operand" "=d")
4494 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4495 (match_operand:SI 2 "general_operand" "dI")))]
4499 (define_insn "ashrhi3"
4500 [(set (match_operand:HI 0 "register_operand" "=d")
4501 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4502 (match_operand:HI 2 "general_operand" "dI")))]
4507 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4508 (ashiftrt:HI (match_dup 0)
4509 (match_operand:HI 1 "general_operand" "dI")))]
4513 (define_insn "ashrqi3"
4514 [(set (match_operand:QI 0 "register_operand" "=d")
4515 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4516 (match_operand:QI 2 "general_operand" "dI")))]
4521 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4522 (ashiftrt:QI (match_dup 0)
4523 (match_operand:QI 1 "general_operand" "dI")))]
4527 ;; logical shift instructions
4529 ;; commented out because of reload problems in 950612-1.c
4532 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4533 ;; (const_int 32)) 1))
4534 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4535 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4536 ;; (const_int 32)) 1))]
4540 ;; return \"move%.l %0,%1\";
4545 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4546 ;; (const_int 32)) 0))
4547 ;; (set (match_operand:DI 1 "general_operand" "=do")
4548 ;; (lshiftrt:DI (match_dup 0)
4549 ;; (const_int 32)))]
4553 ;; if (GET_CODE (operands[1]) == REG)
4554 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4556 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4557 ;; return \"move%.l %0,%2\;clr%.l %1\";
4560 (define_insn "subreg1lshrdi_const32"
4561 [(set (match_operand:SI 0 "general_operand" "=rm")
4562 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4563 (const_int 32)) 1))]
4567 return \"move%.l %1,%0\";
4570 (define_insn "lshrdi_const32"
4571 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4572 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4578 if (which_alternative == 1)
4579 return \"move%.l %1,%0\;clr%.l %0\";
4580 if (which_alternative == 2)
4581 return \"clr%.l %0\;move%.l %1,%0\";
4582 if (GET_CODE (operands[0]) == REG)
4583 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4585 operands[2] = adj_offsettable_operand (operands[0], 4);
4586 if (GET_CODE (operands[1]) == REG)
4587 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4589 operands[3] = adj_offsettable_operand (operands[1], 4);
4590 if (ADDRESS_REG_P (operands[0]))
4591 return \"move%.l %1,%2\;sub%.l %0,%0\";
4593 return \"move%.l %1,%2\;clr%.l %0\";
4596 ;; The predicate below must be general_operand, because lshrdi3 allows that
4597 (define_insn "lshrdi_const"
4598 [(set (match_operand:DI 0 "general_operand" "=d")
4599 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4600 (match_operand 2 "const_int_operand" "n")))]
4602 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4603 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4604 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4607 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4608 if (INTVAL (operands[2]) == 63)
4609 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4611 if (INTVAL (operands[2]) == 1)
4612 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4613 else if (INTVAL (operands[2]) == 8)
4614 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4615 else if (INTVAL (operands[2]) == 16)
4616 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4617 else if (INTVAL (operands[2]) == 2)
4618 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4619 else /*if (INTVAL (operands[2]) == 3)*/
4620 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4623 (define_expand "lshrdi3"
4624 [(set (match_operand:DI 0 "general_operand" "")
4625 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4626 (match_operand 2 "const_int_operand" "")))]
4630 if (GET_CODE (operands[2]) != CONST_INT
4631 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4632 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4633 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4634 && INTVAL (operands[2]) != 63))
4638 ;; On all 68k models, this makes faster code in a special case.
4640 (define_insn "lshrsi_31"
4641 [(set (match_operand:SI 0 "register_operand" "=d")
4642 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4647 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4650 ;; On most 68k models, this makes faster code in a special case.
4652 (define_insn "lshrsi_16"
4653 [(set (match_operand:SI 0 "register_operand" "=d")
4654 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4660 return \"clr%.w %0\;swap %0\";
4663 ;; On the 68000, this makes faster code in a special case.
4665 (define_insn "lshrsi_17_24"
4666 [(set (match_operand:SI 0 "register_operand" "=d")
4667 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4668 (match_operand:SI 2 "const_int_operand" "n")))]
4669 "(! TARGET_68020 && !TARGET_5200
4670 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4673 /* I think lsr%.w sets the CC properly. */
4674 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4675 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4678 (define_insn "lshrsi3"
4679 [(set (match_operand:SI 0 "register_operand" "=d")
4680 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4681 (match_operand:SI 2 "general_operand" "dI")))]
4685 (define_insn "lshrhi3"
4686 [(set (match_operand:HI 0 "register_operand" "=d")
4687 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4688 (match_operand:HI 2 "general_operand" "dI")))]
4693 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4694 (lshiftrt:HI (match_dup 0)
4695 (match_operand:HI 1 "general_operand" "dI")))]
4699 (define_insn "lshrqi3"
4700 [(set (match_operand:QI 0 "register_operand" "=d")
4701 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4702 (match_operand:QI 2 "general_operand" "dI")))]
4707 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4708 (lshiftrt:QI (match_dup 0)
4709 (match_operand:QI 1 "general_operand" "dI")))]
4713 ;; rotate instructions
4715 (define_insn "rotlsi3"
4716 [(set (match_operand:SI 0 "register_operand" "=d")
4717 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4718 (match_operand:SI 2 "general_operand" "dINO")))]
4722 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4724 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4726 INTVAL (operands[2]) = 32 - INTVAL (operands[2]);
4727 return \"ror%.l %2,%0\";
4730 return \"rol%.l %2,%0\";
4733 (define_insn "rotlhi3"
4734 [(set (match_operand:HI 0 "register_operand" "=d")
4735 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4736 (match_operand:HI 2 "general_operand" "dIP")))]
4740 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4742 INTVAL (operands[2]) = 16 - INTVAL (operands[2]);
4743 return \"ror%.w %2,%0\";
4746 return \"rol%.w %2,%0\";
4750 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4751 (rotate:HI (match_dup 0)
4752 (match_operand:HI 1 "general_operand" "dIP")))]
4756 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4758 INTVAL (operands[2]) = 16 - INTVAL (operands[2]);
4759 return \"ror%.w %2,%0\";
4762 return \"rol%.w %2,%0\";
4765 (define_insn "rotlqi3"
4766 [(set (match_operand:QI 0 "register_operand" "=d")
4767 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4768 (match_operand:QI 2 "general_operand" "dI")))]
4772 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4774 INTVAL (operands[2]) = 8 - INTVAL (operands[2]);
4775 return \"ror%.b %2,%0\";
4778 return \"rol%.b %2,%0\";
4782 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4783 (rotate:QI (match_dup 0)
4784 (match_operand:QI 1 "general_operand" "dI")))]
4788 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4790 INTVAL (operands[2]) = 8 - INTVAL (operands[2]);
4791 return \"ror%.b %2,%0\";
4794 return \"rol%.b %2,%0\";
4797 (define_insn "rotrsi3"
4798 [(set (match_operand:SI 0 "register_operand" "=d")
4799 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4800 (match_operand:SI 2 "general_operand" "dI")))]
4804 (define_insn "rotrhi3"
4805 [(set (match_operand:HI 0 "register_operand" "=d")
4806 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4807 (match_operand:HI 2 "general_operand" "dI")))]
4812 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4813 (rotatert:HI (match_dup 0)
4814 (match_operand:HI 1 "general_operand" "dI")))]
4818 (define_insn "rotrqi3"
4819 [(set (match_operand:QI 0 "register_operand" "=d")
4820 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4821 (match_operand:QI 2 "general_operand" "dI")))]
4826 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4827 (rotatert:QI (match_dup 0)
4828 (match_operand:QI 1 "general_operand" "dI")))]
4833 ;; Bit set/clear in memory byte.
4835 ;; set bit, bit number is int
4836 (define_insn "bsetmemqi"
4837 [(set (match_operand:QI 0 "memory_operand" "+m")
4838 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4839 (match_operand:SI 1 "general_operand" "d")) 0)
4845 return \"bset %1,%0\";
4848 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4850 [(set (match_operand:QI 0 "memory_operand" "+m")
4851 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4852 (match_operator:SI 2 "extend_operator"
4853 [(match_operand 1 "general_operand" "d")])) 0)
4859 return \"bset %1,%0\";
4862 ;; clear bit, bit number is int
4863 (define_insn "bclrmemqi"
4864 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4866 (minus:SI (const_int 7)
4867 (match_operand:SI 1 "general_operand" "d")))
4873 return \"bclr %1,%0\";
4876 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4878 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4880 (minus:SI (const_int 7)
4881 (match_operator:SI 2 "extend_operator"
4882 [(match_operand 1 "general_operand" "d")])))
4888 return \"bclr %1,%0\";
4891 ;; Special cases of bit-field insns which we should
4892 ;; recognize in preference to the general case.
4893 ;; These handle aligned 8-bit and 16-bit fields,
4894 ;; which can usually be done with move instructions.
4897 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4898 ; alignment of structure members is specified.
4900 ; The move is allowed to be odd byte aligned, because that's still faster
4901 ; than an odd byte aligned bit field instruction.
4904 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4906 (match_operand:SI 2 "const_int_operand" "n"))
4907 (match_operand:SI 3 "general_operand" "rmi"))]
4908 "TARGET_68020 && TARGET_BITFIELD
4909 && (INTVAL (operands[2]) % 8) == 0
4910 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4914 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4916 return \"move%.l %3,%0\";
4920 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4921 (match_operand:SI 1 "const_int_operand" "n")
4922 (match_operand:SI 2 "const_int_operand" "n"))
4923 (match_operand:SI 3 "register_operand" "d"))]
4924 "TARGET_68020 && TARGET_BITFIELD
4925 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4926 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4927 && (GET_CODE (operands[0]) == REG
4928 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4931 if (REG_P (operands[0]))
4933 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4934 return \"bfins %3,%0{%b2:%b1}\";
4938 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4940 if (GET_CODE (operands[3]) == MEM)
4941 operands[3] = adj_offsettable_operand (operands[3],
4942 (32 - INTVAL (operands[1])) / 8);
4943 if (INTVAL (operands[1]) == 8)
4944 return \"move%.b %3,%0\";
4945 return \"move%.w %3,%0\";
4950 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4951 ; alignment of structure members is specified.
4953 ; The move is allowed to be odd byte aligned, because that's still faster
4954 ; than an odd byte aligned bit field instruction.
4957 [(set (match_operand:SI 0 "general_operand" "=rm")
4958 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
4960 (match_operand:SI 3 "const_int_operand" "n")))]
4961 "TARGET_68020 && TARGET_BITFIELD
4962 && (INTVAL (operands[3]) % 8) == 0
4963 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4967 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4969 return \"move%.l %1,%0\";
4973 [(set (match_operand:SI 0 "general_operand" "=&d")
4974 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4975 (match_operand:SI 2 "const_int_operand" "n")
4976 (match_operand:SI 3 "const_int_operand" "n")))]
4977 "TARGET_68020 && TARGET_BITFIELD
4978 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4979 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4980 && (GET_CODE (operands[1]) == REG
4981 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4984 cc_status.flags |= CC_NOT_NEGATIVE;
4985 if (REG_P (operands[1]))
4987 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4988 return \"bfextu %1{%b3:%b2},%0\";
4992 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4994 output_asm_insn (\"clr%.l %0\", operands);
4995 if (GET_CODE (operands[0]) == MEM)
4996 operands[0] = adj_offsettable_operand (operands[0],
4997 (32 - INTVAL (operands[1])) / 8);
4998 if (INTVAL (operands[2]) == 8)
4999 return \"move%.b %1,%0\";
5000 return \"move%.w %1,%0\";
5004 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5005 ; alignment of structure members is specified.
5007 ; The move is allowed to be odd byte aligned, because that's still faster
5008 ; than an odd byte aligned bit field instruction.
5011 [(set (match_operand:SI 0 "general_operand" "=rm")
5012 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5014 (match_operand:SI 3 "const_int_operand" "n")))]
5015 "TARGET_68020 && TARGET_BITFIELD
5016 && (INTVAL (operands[3]) % 8) == 0
5017 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5021 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5023 return \"move%.l %1,%0\";
5027 [(set (match_operand:SI 0 "general_operand" "=d")
5028 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5029 (match_operand:SI 2 "const_int_operand" "n")
5030 (match_operand:SI 3 "const_int_operand" "n")))]
5031 "TARGET_68020 && TARGET_BITFIELD
5032 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5033 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5034 && (GET_CODE (operands[1]) == REG
5035 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5038 if (REG_P (operands[1]))
5040 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5041 return \"bfexts %1{%b3:%b2},%0\";
5045 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5047 if (INTVAL (operands[2]) == 8)
5048 return \"move%.b %1,%0\;extb%.l %0\";
5049 return \"move%.w %1,%0\;ext%.l %0\";
5052 ;; Bit field instructions, general cases.
5053 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5054 ;; so that its address is reloaded.
5056 (define_expand "extv"
5057 [(set (match_operand:SI 0 "general_operand" "")
5058 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5059 (match_operand:SI 2 "general_operand" "")
5060 (match_operand:SI 3 "general_operand" "")))]
5061 "TARGET_68020 && TARGET_BITFIELD"
5065 [(set (match_operand:SI 0 "general_operand" "=d")
5066 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5067 (match_operand:SI 2 "general_operand" "di")
5068 (match_operand:SI 3 "general_operand" "di")))]
5069 "TARGET_68020 && TARGET_BITFIELD"
5070 "bfexts %1{%b3:%b2},%0")
5072 (define_expand "extzv"
5073 [(set (match_operand:SI 0 "general_operand" "")
5074 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5075 (match_operand:SI 2 "general_operand" "")
5076 (match_operand:SI 3 "general_operand" "")))]
5077 "TARGET_68020 && TARGET_BITFIELD"
5081 [(set (match_operand:SI 0 "general_operand" "=d,d")
5082 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5083 (match_operand:SI 2 "general_operand" "di,di")
5084 (match_operand:SI 3 "general_operand" "di,di")))]
5085 "TARGET_68020 && TARGET_BITFIELD"
5088 if (GET_CODE (operands[2]) == CONST_INT)
5090 if (INTVAL (operands[2]) != 32)
5091 cc_status.flags |= CC_NOT_NEGATIVE;
5097 return \"bfextu %1{%b3:%b2},%0\";
5101 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5102 (match_operand:SI 1 "general_operand" "di")
5103 (match_operand:SI 2 "general_operand" "di"))
5104 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5105 (match_operand 3 "const_int_operand" "n")))]
5106 "TARGET_68020 && TARGET_BITFIELD
5107 && (INTVAL (operands[3]) == -1
5108 || (GET_CODE (operands[1]) == CONST_INT
5109 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5113 return \"bfchg %0{%b2:%b1}\";
5117 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5118 (match_operand:SI 1 "general_operand" "di")
5119 (match_operand:SI 2 "general_operand" "di"))
5121 "TARGET_68020 && TARGET_BITFIELD"
5125 return \"bfclr %0{%b2:%b1}\";
5129 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5130 (match_operand:SI 1 "general_operand" "di")
5131 (match_operand:SI 2 "general_operand" "di"))
5133 "TARGET_68020 && TARGET_BITFIELD"
5137 return \"bfset %0{%b2:%b1}\";
5140 (define_expand "insv"
5141 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5142 (match_operand:SI 1 "general_operand" "")
5143 (match_operand:SI 2 "general_operand" ""))
5144 (match_operand:SI 3 "register_operand" ""))]
5145 "TARGET_68020 && TARGET_BITFIELD"
5149 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5150 (match_operand:SI 1 "general_operand" "di")
5151 (match_operand:SI 2 "general_operand" "di"))
5152 (match_operand:SI 3 "register_operand" "d"))]
5153 "TARGET_68020 && TARGET_BITFIELD"
5154 "bfins %3,%0{%b2:%b1}")
5156 ;; Now recognize bit field insns that operate on registers
5157 ;; (or at least were intended to do so).
5160 [(set (match_operand:SI 0 "general_operand" "=d")
5161 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5162 (match_operand:SI 2 "general_operand" "di")
5163 (match_operand:SI 3 "general_operand" "di")))]
5164 "TARGET_68020 && TARGET_BITFIELD"
5165 "bfexts %1{%b3:%b2},%0")
5168 [(set (match_operand:SI 0 "general_operand" "=d")
5169 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5170 (match_operand:SI 2 "general_operand" "di")
5171 (match_operand:SI 3 "general_operand" "di")))]
5172 "TARGET_68020 && TARGET_BITFIELD"
5175 if (GET_CODE (operands[2]) == CONST_INT)
5177 if (INTVAL (operands[2]) != 32)
5178 cc_status.flags |= CC_NOT_NEGATIVE;
5184 return \"bfextu %1{%b3:%b2},%0\";
5188 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5189 (match_operand:SI 1 "general_operand" "di")
5190 (match_operand:SI 2 "general_operand" "di"))
5192 "TARGET_68020 && TARGET_BITFIELD"
5196 return \"bfclr %0{%b2:%b1}\";
5200 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5201 (match_operand:SI 1 "general_operand" "di")
5202 (match_operand:SI 2 "general_operand" "di"))
5204 "TARGET_68020 && TARGET_BITFIELD"
5208 return \"bfset %0{%b2:%b1}\";
5212 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5213 (match_operand:SI 1 "general_operand" "di")
5214 (match_operand:SI 2 "general_operand" "di"))
5215 (match_operand:SI 3 "register_operand" "d"))]
5216 "TARGET_68020 && TARGET_BITFIELD"
5220 /* These special cases are now recognized by a specific pattern. */
5221 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5222 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5223 return \"move%.w %3,%0\";
5224 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5225 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5226 return \"move%.b %3,%0\";
5228 return \"bfins %3,%0{%b2:%b1}\";
5231 ;; Special patterns for optimizing bit-field instructions.
5235 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5236 (match_operand:SI 1 "const_int_operand" "n")
5237 (match_operand:SI 2 "general_operand" "di")))]
5238 "TARGET_68020 && TARGET_BITFIELD"
5241 if (operands[1] == const1_rtx
5242 && GET_CODE (operands[2]) == CONST_INT)
5244 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5245 return output_btst (operands,
5246 gen_rtx (CONST_INT, VOIDmode,
5247 width - INTVAL (operands[2])),
5250 /* Pass 1000 as SIGNPOS argument so that btst will
5251 not think we are testing the sign bit for an `and'
5252 and assume that nonzero implies a negative result. */
5254 if (INTVAL (operands[1]) != 32)
5255 cc_status.flags = CC_NOT_NEGATIVE;
5256 return \"bftst %0{%b2:%b1}\";
5260 ;;; now handle the register cases
5263 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5264 (match_operand:SI 1 "const_int_operand" "n")
5265 (match_operand:SI 2 "general_operand" "di")))]
5266 "TARGET_68020 && TARGET_BITFIELD"
5269 if (operands[1] == const1_rtx
5270 && GET_CODE (operands[2]) == CONST_INT)
5272 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5273 return output_btst (operands,
5274 gen_rtx (CONST_INT, VOIDmode,
5275 width - INTVAL (operands[2])),
5278 /* Pass 1000 as SIGNPOS argument so that btst will
5279 not think we are testing the sign bit for an `and'
5280 and assume that nonzero implies a negative result. */
5282 if (INTVAL (operands[1]) != 32)
5283 cc_status.flags = CC_NOT_NEGATIVE;
5284 return \"bftst %0{%b2:%b1}\";
5287 (define_insn "scc0_di"
5288 [(set (match_operand:QI 0 "general_operand" "=dm")
5289 (match_operator 1 "valid_dbcc_comparison_p"
5290 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5294 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5297 (define_insn "scc_di"
5298 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5299 (match_operator 1 "valid_dbcc_comparison_p"
5300 [(match_operand:DI 2 "general_operand" "ro,r")
5301 (match_operand:DI 3 "general_operand" "r,ro")]))]
5305 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5309 [(set (match_operand:QI 0 "general_operand" "=dm")
5310 (eq:QI (cc0) (const_int 0)))]
5313 cc_status = cc_prev_status;
5314 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5318 [(set (match_operand:QI 0 "general_operand" "=dm")
5319 (ne:QI (cc0) (const_int 0)))]
5322 cc_status = cc_prev_status;
5323 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5327 [(set (match_operand:QI 0 "general_operand" "=dm")
5328 (gt:QI (cc0) (const_int 0)))]
5331 cc_status = cc_prev_status;
5332 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5336 [(set (match_operand:QI 0 "general_operand" "=dm")
5337 (gtu:QI (cc0) (const_int 0)))]
5339 "* cc_status = cc_prev_status;
5340 return \"shi %0\"; ")
5343 [(set (match_operand:QI 0 "general_operand" "=dm")
5344 (lt:QI (cc0) (const_int 0)))]
5346 "* cc_status = cc_prev_status;
5347 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5350 [(set (match_operand:QI 0 "general_operand" "=dm")
5351 (ltu:QI (cc0) (const_int 0)))]
5353 "* cc_status = cc_prev_status;
5354 return \"scs %0\"; ")
5357 [(set (match_operand:QI 0 "general_operand" "=dm")
5358 (ge:QI (cc0) (const_int 0)))]
5360 "* cc_status = cc_prev_status;
5361 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5364 [(set (match_operand:QI 0 "general_operand" "=dm")
5365 (geu:QI (cc0) (const_int 0)))]
5367 "* cc_status = cc_prev_status;
5368 return \"scc %0\"; ")
5371 [(set (match_operand:QI 0 "general_operand" "=dm")
5372 (le:QI (cc0) (const_int 0)))]
5375 cc_status = cc_prev_status;
5376 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5380 [(set (match_operand:QI 0 "general_operand" "=dm")
5381 (leu:QI (cc0) (const_int 0)))]
5383 "* cc_status = cc_prev_status;
5384 return \"sls %0\"; ")
5386 ;; Basic conditional jump instructions.
5388 (define_insn "beq0_di"
5390 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5392 (label_ref (match_operand 1 "" ","))
5394 (clobber (match_scratch:SI 2 "=d,d"))]
5399 if (which_alternative == 1)
5401 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5403 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5405 if ((cc_prev_status.value1
5406 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5407 || (cc_prev_status.value2
5408 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5410 cc_status = cc_prev_status;
5412 return \"jbeq %l1\";
5417 if (GET_CODE (operands[0]) == REG)
5418 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5420 operands[3] = adj_offsettable_operand (operands[0], 4);
5421 if (! ADDRESS_REG_P (operands[0]))
5423 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5425 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5427 operands[4] = gen_label_rtx();
5429 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5431 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5433 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5434 CODE_LABEL_NUMBER (operands[4]));
5438 (define_insn "bne0_di"
5440 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5442 (label_ref (match_operand 1 "" ","))
5444 (clobber (match_scratch:SI 2 "=d,X"))]
5448 if ((cc_prev_status.value1
5449 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5450 || (cc_prev_status.value2
5451 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5453 cc_status = cc_prev_status;
5455 return \"jbne %l1\";
5461 if (GET_CODE (operands[0]) == REG)
5462 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5464 operands[3] = adj_offsettable_operand (operands[0], 4);
5465 if (ADDRESS_REG_P (operands[0]))
5467 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5469 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5473 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5475 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5479 (define_insn "bge0_di"
5481 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5483 (label_ref (match_operand 1 "" ""))
5488 if ((cc_prev_status.value1
5489 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5490 || (cc_prev_status.value2
5491 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5493 cc_status = cc_prev_status;
5494 if (cc_status.flags & CC_REVERSED)
5497 return \"jble %l1\";
5505 return \"jbpl %l1\";
5513 return \"tst%.l %0\;jbpl %l1\";
5515 return \"tst%.l %0\;jpl %l1\";
5519 (define_insn "blt0_di"
5521 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5523 (label_ref (match_operand 1 "" ""))
5528 if ((cc_prev_status.value1
5529 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5530 || (cc_prev_status.value2
5531 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5533 cc_status = cc_prev_status;
5534 if (cc_status.flags & CC_REVERSED)
5537 return \"jbgt %l1\";
5545 return \"jbmi %l1\";
5553 return \"tst%.l %0\;jbmi %l1\";
5555 return \"tst%.l %0\;jmi %l1\";
5561 (if_then_else (eq (cc0)
5563 (label_ref (match_operand 0 "" ""))
5569 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5571 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5577 (if_then_else (ne (cc0)
5579 (label_ref (match_operand 0 "" ""))
5585 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5587 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5593 (if_then_else (gt (cc0)
5595 (label_ref (match_operand 0 "" ""))
5600 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5602 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5608 (if_then_else (gtu (cc0)
5610 (label_ref (match_operand 0 "" ""))
5615 return \"jbhi %l0\";
5623 (if_then_else (lt (cc0)
5625 (label_ref (match_operand 0 "" ""))
5630 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5632 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5638 (if_then_else (ltu (cc0)
5640 (label_ref (match_operand 0 "" ""))
5645 return \"jbcs %l0\";
5653 (if_then_else (ge (cc0)
5655 (label_ref (match_operand 0 "" ""))
5660 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
5662 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
5668 (if_then_else (geu (cc0)
5670 (label_ref (match_operand 0 "" ""))
5675 return \"jbcc %l0\";
5683 (if_then_else (le (cc0)
5685 (label_ref (match_operand 0 "" ""))
5690 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5692 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5698 (if_then_else (leu (cc0)
5700 (label_ref (match_operand 0 "" ""))
5705 return \"jbls %l0\";
5711 ;; Negated conditional jump instructions.
5715 (if_then_else (eq (cc0)
5718 (label_ref (match_operand 0 "" ""))))]
5723 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5725 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5731 (if_then_else (ne (cc0)
5734 (label_ref (match_operand 0 "" ""))))]
5739 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5741 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5747 (if_then_else (gt (cc0)
5750 (label_ref (match_operand 0 "" ""))))]
5754 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
5756 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
5762 (if_then_else (gtu (cc0)
5765 (label_ref (match_operand 0 "" ""))))]
5769 return \"jbls %l0\";
5777 (if_then_else (lt (cc0)
5780 (label_ref (match_operand 0 "" ""))))]
5784 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
5786 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
5792 (if_then_else (ltu (cc0)
5795 (label_ref (match_operand 0 "" ""))))]
5799 return \"jbcc %l0\";
5807 (if_then_else (ge (cc0)
5810 (label_ref (match_operand 0 "" ""))))]
5814 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
5816 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
5822 (if_then_else (geu (cc0)
5825 (label_ref (match_operand 0 "" ""))))]
5829 return \"jbcs %l0\";
5837 (if_then_else (le (cc0)
5840 (label_ref (match_operand 0 "" ""))))]
5844 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
5846 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
5852 (if_then_else (leu (cc0)
5855 (label_ref (match_operand 0 "" ""))))]
5859 return \"jbhi %l0\";
5865 ;; Unconditional and other jump instructions
5868 (label_ref (match_operand 0 "" "")))]
5872 return \"jbra %l0\";
5878 ;; We support two different ways of handling dispatch tables.
5879 ;; The NeXT uses absolute tables, and other machines use relative.
5880 ;; This define_expand can generate either kind.
5881 (define_expand "tablejump"
5882 [(parallel [(set (pc) (match_operand 0 "" ""))
5883 (use (label_ref (match_operand 1 "" "")))])]
5887 #ifdef CASE_VECTOR_PC_RELATIVE
5888 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
5889 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
5893 ;; Jump to variable address from dispatch table of absolute addresses.
5895 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
5896 (use (label_ref (match_operand 1 "" "")))]
5900 return \"jmp (%0)\";
5906 ;; Jump to variable address from dispatch table of relative addresses.
5910 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
5911 (use (label_ref (match_operand 1 "" "")))]
5914 #ifdef ASM_RETURN_CASE_JUMP
5915 ASM_RETURN_CASE_JUMP;
5918 #ifdef ASM_OUTPUT_CASE_LABEL
5919 return \"jmp 6(%%pc,%0.w)\";
5922 return \"jmp 2(pc,%0.w)\";
5924 return \"jmp 2(%%pc,%0.w)\";
5925 #endif /* end !CRDS */
5929 return \"jmp (2,pc,%0.w)\";
5931 return \"jmp pc@(2,%0:w)\";
5937 ;; Decrement-and-branch insns.
5941 (ne (match_operand:HI 0 "general_operand" "+d*g")
5943 (label_ref (match_operand 1 "" ""))
5946 (plus:HI (match_dup 0)
5952 if (DATA_REG_P (operands[0]))
5953 return \"dbra %0,%l1\";
5954 if (GET_CODE (operands[0]) == MEM)
5958 return \"sub%.w %#1,%0\;jbcc %l1\";
5960 return \"subq%.w %#1,%0\;jbcc %l1\";
5962 #else /* not MOTOROLA */
5963 return \"subqw %#1,%0\;jcc %l1\";
5967 #ifdef SGS_CMP_ORDER
5969 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5971 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5973 #else /* not SGS_CMP_ORDER */
5974 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
5976 #else /* not MOTOROLA */
5977 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
5984 (ne (match_operand:SI 0 "general_operand" "+d*g")
5986 (label_ref (match_operand 1 "" ""))
5989 (plus:SI (match_dup 0)
5997 if (DATA_REG_P (operands[0]))
5998 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
5999 if (GET_CODE (operands[0]) == MEM)
6000 return \"sub%.l %#1,%0\;jbcc %l1\";
6002 if (DATA_REG_P (operands[0]))
6003 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6004 if (GET_CODE (operands[0]) == MEM)
6005 return \"subq%.l %#1,%0\;jbcc %l1\";
6006 #endif /* NO_ADDSUB_Q */
6007 #ifdef SGS_CMP_ORDER
6009 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6011 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6013 #else /* not SGS_CMP_ORDER */
6014 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6015 #endif /* not SGS_CMP_ORDER */
6016 #else /* not MOTOROLA */
6017 if (DATA_REG_P (operands[0]))
6018 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6019 if (GET_CODE (operands[0]) == MEM)
6020 return \"subql %#1,%0\;jcc %l1\";
6021 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6022 #endif /* not MOTOROLA */
6025 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6030 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6033 (label_ref (match_operand 1 "" ""))
6036 (plus:HI (match_dup 0)
6038 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6044 if (DATA_REG_P (operands[0]))
6045 return \"dbra %0,%l1\";
6046 if (GET_CODE (operands[0]) == MEM)
6047 return \"sub%.w %#1,%0\;jbcc %l1\";
6049 if (DATA_REG_P (operands[0]))
6050 return \"dbra %0,%l1\";
6051 if (GET_CODE (operands[0]) == MEM)
6052 return \"subq%.w %#1,%0\;jbcc %l1\";
6054 #ifdef SGS_CMP_ORDER
6056 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6058 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6060 #else /* not SGS_CMP_ORDER */
6061 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6062 #endif /* not SGS_CMP_ORDER */
6063 #else /* not MOTOROLA */
6064 if (DATA_REG_P (operands[0]))
6065 return \"dbra %0,%l1\";
6066 if (GET_CODE (operands[0]) == MEM)
6067 return \"subqw %#1,%0\;jcc %l1\";
6068 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6069 #endif /* not MOTOROLA */
6072 (define_expand "decrement_and_branch_until_zero"
6073 [(parallel [(set (pc)
6075 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6078 (label_ref (match_operand 1 "" ""))
6081 (plus:SI (match_dup 0)
6089 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6092 (label_ref (match_operand 1 "" ""))
6095 (plus:SI (match_dup 0)
6097 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6103 if (DATA_REG_P (operands[0]))
6104 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6105 if (GET_CODE (operands[0]) == MEM)
6106 return \"sub%.l %#1,%0\;jbcc %l1\";
6108 if (DATA_REG_P (operands[0]))
6109 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6110 if (GET_CODE (operands[0]) == MEM)
6111 return \"subq%.l %#1,%0\;jbcc %l1\";
6113 #ifdef SGS_CMP_ORDER
6115 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6117 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6119 #else /* not SGS_CMP_ORDER */
6120 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6121 #endif /* not SGS_CMP_ORDER */
6122 #else /* not MOTOROLA */
6123 if (DATA_REG_P (operands[0]))
6124 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6125 if (GET_CODE (operands[0]) == MEM)
6126 return \"subql %#1,%0\;jcc %l1\";
6127 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6128 #endif /* not MOTOROLA */
6132 ;; For PIC calls, in order to be able to support
6133 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6134 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6136 ;; PIC calls are handled by loading the address of the function into a
6137 ;; register (via movsi), then emitting a register indirect call using
6138 ;; the "jsr" function call syntax.
6140 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6141 ;; operand to the jbsr statement to indicate that this call should
6142 ;; go through the PLT (why? because this is the way that Sun does it).
6144 ;; We have different patterns for PIC calls and non-PIC calls. The
6145 ;; different patterns are only used to choose the right syntax.
6147 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6148 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6149 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6150 ;; section at link time. However, all global objects reference are still
6151 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6152 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6153 ;; We need to have a way to differentiate these two different operands.
6155 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6156 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6157 ;; to be changed to recognize function calls symbol_ref operand as a valid
6158 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6159 ;; avoid the compiler to load this symbol_ref operand into a register.
6160 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6161 ;; since the value is a PC relative offset, not a real address.
6163 ;; All global objects are treated in the similar way as in SUN3. The only
6164 ;; difference is: on m68k svr4, the reference of such global object needs
6165 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6166 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6169 ;; Call subroutine with no return value.
6170 (define_expand "call"
6171 [(call (match_operand:QI 0 "memory_operand" "")
6172 (match_operand:SI 1 "general_operand" ""))]
6173 ;; Operand 1 not really used on the m68000.
6178 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6179 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6182 ;; This is a normal call sequence.
6184 [(call (match_operand:QI 0 "memory_operand" "o")
6185 (match_operand:SI 1 "general_operand" "g"))]
6186 ;; Operand 1 not really used on the m68000.
6190 #if defined (MOTOROLA) && !defined (USE_GAS)
6192 if (GET_CODE (operands[0]) == MEM
6193 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6202 ;; This is a PIC call sequence.
6204 [(call (match_operand:QI 0 "memory_operand" "o")
6205 (match_operand:SI 1 "general_operand" "g"))]
6206 ;; Operand 1 not really used on the m68000.
6210 if (GET_CODE (operands[0]) == MEM
6211 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6214 return \"bsr.l %0\";
6217 return \"bsr.l %0@PLTPC\";
6219 return \"bsr %0@PLTPC\";
6223 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6224 GAS just plain ignores it. */
6225 return \"jbsr %0,a1\";
6230 ;; Call subroutine, returning value in operand 0
6231 ;; (which must be a hard register).
6232 ;; See comments before "call" regarding PIC calls.
6233 (define_expand "call_value"
6234 [(set (match_operand 0 "" "")
6235 (call (match_operand:QI 1 "memory_operand" "")
6236 (match_operand:SI 2 "general_operand" "")))]
6237 ;; Operand 2 not really used on the m68000.
6241 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6242 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6245 ;; This is a normal call_value
6247 [(set (match_operand 0 "" "=rf")
6248 (call (match_operand:QI 1 "memory_operand" "o")
6249 (match_operand:SI 2 "general_operand" "g")))]
6250 ;; Operand 2 not really used on the m68000.
6253 #if defined (MOTOROLA) && !defined (USE_GAS)
6255 if (GET_CODE (operands[1]) == MEM
6256 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6265 ;; This is a PIC call_value
6267 [(set (match_operand 0 "" "=rf")
6268 (call (match_operand:QI 1 "memory_operand" "o")
6269 (match_operand:SI 2 "general_operand" "g")))]
6270 ;; Operand 2 not really used on the m68000.
6273 if (GET_CODE (operands[1]) == MEM
6274 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6277 return \"bsr.l %1\";
6280 return \"bsr.l %1@PLTPC\";
6282 return \"bsr %1@PLTPC\";
6286 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6287 GAS just plain ignores it. */
6288 return \"jbsr %1,a1\";
6293 ;; Call subroutine returning any type.
6295 (define_expand "untyped_call"
6296 [(parallel [(call (match_operand 0 "" "")
6298 (match_operand 1 "" "")
6299 (match_operand 2 "" "")])]
6300 "NEEDS_UNTYPED_CALL"
6305 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6307 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6309 rtx set = XVECEXP (operands[2], 0, i);
6310 emit_move_insn (SET_DEST (set), SET_SRC (set));
6313 /* The optimizer does not know that the call sets the function value
6314 registers we stored in the result block. We avoid problems by
6315 claiming that all hard registers are used and clobbered at this
6317 emit_insn (gen_blockage ());
6322 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6323 ;; all of memory. This blocks insns from being moved across this point.
6325 (define_insn "blockage"
6326 [(unspec_volatile [(const_int 0)] 0)]
6335 (define_insn "probe"
6340 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6341 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6342 return \"tstl %a0\";
6345 ;; Used for frameless functions which save no regs and allocate no locals.
6346 (define_insn "return"
6351 if (current_function_pops_args == 0)
6353 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6357 (define_insn "indirect_jump"
6358 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6362 ;; This should not be used unless the add/sub insns can't be.
6365 [(set (match_operand:SI 0 "general_operand" "=a")
6366 (match_operand:QI 1 "address_operand" "p"))]
6371 /* Recognize an insn that refers to a table of offsets. Such an insn will
6372 need to refer to a label on the insn. So output one. Use the
6373 label-number of the table of offsets to generate this label. This code,
6374 and similar code above, assumes that there will be at most one reference
6376 if (GET_CODE (operands[1]) == PLUS
6377 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6378 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6380 rtx labelref = XEXP (operands[1], 1);
6381 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6383 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6384 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6386 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6387 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6388 #endif /* not SGS */
6389 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6390 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6391 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6392 #ifdef SGS_SWITCH_TABLES
6393 /* Set flag saying we need to define the symbol
6394 LD%n (with value L%n-LI%n) at the end of the switch table. */
6395 switch_table_difference_label_flag = 1;
6396 #endif /* SGS_SWITCH_TABLES */
6397 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6399 #endif /* SGS_NO_LI */
6401 return \"lea %a1,%0\";
6404 ;; This is the first machine-dependent peephole optimization.
6405 ;; It is useful when a floating value is returned from a function call
6406 ;; and then is moved into an FP register.
6407 ;; But it is mainly intended to test the support for these optimizations.
6410 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6411 (set (match_operand:DF 0 "register_operand" "=f")
6412 (match_operand:DF 1 "register_operand" "ad"))]
6413 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6417 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6418 output_asm_insn (\"move%.l %1,%@\", xoperands);
6419 output_asm_insn (\"move%.l %1,%-\", operands);
6420 return \"fmove%.d %+,%0\";
6424 ;; Optimize a stack-adjust followed by a push of an argument.
6425 ;; This is said to happen frequently with -msoft-float
6426 ;; when there are consecutive library calls.
6429 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6430 (match_operand:SI 0 "const_int_operand" "n")))
6431 (set (match_operand:SF 1 "push_operand" "=m")
6432 (match_operand:SF 2 "general_operand" "rmfF"))]
6433 "INTVAL (operands[0]) >= 4
6434 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6437 if (INTVAL (operands[0]) > 4)
6440 xoperands[0] = stack_pointer_rtx;
6441 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6443 if (INTVAL (xoperands[1]) <= 8)
6446 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6448 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6450 else if (INTVAL (xoperands[1]) <= 16
6451 && TARGET_68020 && !TARGET_68040 && !TARGET_68060)
6453 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6454 INTVAL (xoperands[1]) - 8);
6455 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6459 if (INTVAL (xoperands[1]) <= 0x7FFF && !TARGET_5200)
6460 output_asm_insn (\"add%.w %1,%0\", xoperands);
6462 output_asm_insn (\"add%.l %1,%0\", xoperands);
6464 if (FP_REG_P (operands[2]))
6465 return \"fmove%.s %2,%@\";
6466 return \"move%.l %2,%@\";
6469 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6472 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6473 (match_operand:SI 0 "const_int_operand" "n")))
6474 (set (match_operand:SI 1 "push_operand" "=m")
6475 (match_operand:SI 2 "general_operand" "g"))]
6476 "INTVAL (operands[0]) >= 4
6477 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6480 if (INTVAL (operands[0]) > 4)
6483 xoperands[0] = stack_pointer_rtx;
6484 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6486 if (INTVAL (xoperands[1]) <= 8)
6489 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6491 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6493 else if (INTVAL (xoperands[1]) <= 16
6494 && TARGET_68020 && !TARGET_68040 && !TARGET_68060)
6496 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6497 INTVAL (xoperands[1]) - 8);
6498 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6502 if (INTVAL (xoperands[1]) <= 0x7FFF && !TARGET_5200)
6503 output_asm_insn (\"add%.w %1,%0\", xoperands);
6505 output_asm_insn (\"add%.l %1,%0\", xoperands);
6507 if (operands[2] == const0_rtx)
6508 return \"clr%.l %@\";
6509 return \"move%.l %2,%@\";
6512 ;; Speed up pushing a single byte but leaving four bytes of space.
6515 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6516 (match_operand:QI 1 "general_operand" "dami"))
6517 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6518 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6523 if (GET_CODE (operands[1]) == REG)
6524 return \"move%.l %1,%-\";
6526 xoperands[1] = operands[1];
6528 = gen_rtx (MEM, QImode,
6529 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
6530 gen_rtx (CONST_INT, VOIDmode, 3)));
6531 xoperands[3] = stack_pointer_rtx;
6533 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6535 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
6540 [(set (match_operand:SI 0 "register_operand" "=d")
6542 (set (strict_low_part (subreg:HI (match_dup 0) 0))
6543 (match_operand:HI 1 "general_operand" "rmn"))]
6544 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6547 if (GET_CODE (operands[1]) == CONST_INT)
6549 if (operands[1] == const0_rtx
6550 && (DATA_REG_P (operands[0])
6551 || GET_CODE (operands[0]) == MEM)
6552 /* clr insns on 68000 read before writing.
6553 This isn't so on the 68010, but we have no TARGET_68010. */
6554 && ((TARGET_68020 || TARGET_5200)
6555 || !(GET_CODE (operands[0]) == MEM
6556 && MEM_VOLATILE_P (operands[0]))))
6557 return \"clr%.w %0\";
6559 return \"move%.w %1,%0\";
6567 ;; jCC label ; abnormal loop termination
6568 ;; dbra dN, loop ; normal loop termination
6576 ;; Which moves the jCC condition outside the inner loop for free.
6579 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6580 [(cc0) (const_int 0)])
6581 (label_ref (match_operand 2 "" ""))
6586 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
6589 (label_ref (match_operand 1 "" ""))
6592 (plus:HI (match_dup 0)
6594 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6598 output_dbcc_and_branch (operands);
6603 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6604 [(cc0) (const_int 0)])
6605 (label_ref (match_operand 2 "" ""))
6610 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
6613 (label_ref (match_operand 1 "" ""))
6616 (plus:SI (match_dup 0)
6618 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6622 output_dbcc_and_branch (operands);
6627 ;; FPA multiply and add.
6629 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6630 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
6631 (match_operand:DF 2 "general_operand" "xH,y,y"))
6632 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
6635 fpma%.d %1,%w2,%w3,%0
6636 fpma%.d %x1,%x2,%x3,%0
6637 fpma%.d %x1,%x2,%x3,%0")
6640 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6641 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
6642 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
6643 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
6646 fpma%.s %1,%w2,%w3,%0
6648 fpma%.s %1,%2,%3,%0")
6650 ;; FPA Multiply and subtract
6652 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6653 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6654 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
6655 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6658 fpms%.d %3,%w2,%w1,%0
6659 fpms%.d %x3,%2,%x1,%0
6660 fpms%.d %x3,%2,%x1,%0")
6663 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6664 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6665 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
6666 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6669 fpms%.s %3,%w2,%w1,%0
6671 fpms%.s %3,%2,%1,%0")
6674 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6675 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6676 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6677 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6680 fpmr%.d %2,%w1,%w3,%0
6681 fpmr%.d %x2,%1,%x3,%0
6682 fpmr%.d %x2,%1,%x3,%0")
6685 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6686 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6687 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6688 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6691 fpmr%.s %2,%w1,%w3,%0
6692 fpmr%.s %x2,%1,%x3,%0
6693 fpmr%.s %x2,%1,%x3,%0")
6695 ;; FPA Add and multiply
6697 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6698 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6699 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6700 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6703 fpam%.d %2,%w1,%w3,%0
6704 fpam%.d %x2,%1,%x3,%0
6705 fpam%.d %x2,%1,%x3,%0")
6708 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6709 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6710 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6711 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6714 fpam%.s %2,%w1,%w3,%0
6715 fpam%.s %x2,%1,%x3,%0
6716 fpam%.s %x2,%1,%x3,%0")
6718 ;;FPA Subtract and multiply
6720 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6721 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
6722 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6723 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6726 fpsm%.d %2,%w1,%w3,%0
6727 fpsm%.d %x2,%1,%x3,%0
6728 fpsm%.d %x2,%1,%x3,%0")
6731 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6732 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6733 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
6734 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6737 fpsm%.d %3,%w2,%w1,%0
6738 fpsm%.d %x3,%2,%x1,%0
6739 fpsm%.d %x3,%2,%x1,%0")
6742 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6743 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
6744 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6745 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6748 fpsm%.s %2,%w1,%w3,%0
6749 fpsm%.s %x2,%1,%x3,%0
6750 fpsm%.s %x2,%1,%x3,%0")
6753 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6754 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6755 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
6756 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6759 fpsm%.s %3,%w2,%w1,%0
6760 fpsm%.s %x3,%2,%x1,%0
6761 fpsm%.s %x3,%2,%x1,%0")
6763 (define_insn "tstxf"
6765 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6769 cc_status.flags = CC_IN_68881;
6770 return \"ftst%.x %0\";
6773 (define_insn "cmpxf"
6775 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
6776 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
6780 cc_status.flags = CC_IN_68881;
6781 #ifdef SGS_CMP_ORDER
6782 if (REG_P (operands[0]))
6784 if (REG_P (operands[1]))
6785 return \"fcmp%.x %0,%1\";
6787 return \"fcmp%.x %0,%f1\";
6789 cc_status.flags |= CC_REVERSED;
6790 return \"fcmp%.x %1,%f0\";
6792 if (REG_P (operands[0]))
6794 if (REG_P (operands[1]))
6795 return \"fcmp%.x %1,%0\";
6797 return \"fcmp%.x %f1,%0\";
6799 cc_status.flags |= CC_REVERSED;
6800 return \"fcmp%.x %f0,%1\";
6804 (define_insn "extendsfxf2"
6805 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6806 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
6810 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6812 if (REGNO (operands[0]) == REGNO (operands[1]))
6814 /* Extending float to double in an fp-reg is a no-op.
6815 NOTICE_UPDATE_CC has already assumed that the
6816 cc will be set. So cancel what it did. */
6817 cc_status = cc_prev_status;
6820 return \"f%$move%.x %1,%0\";
6822 if (FP_REG_P (operands[0]))
6823 return \"f%$move%.s %f1,%0\";
6824 return \"fmove%.x %f1,%0\";
6828 (define_insn "extenddfxf2"
6829 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6831 (match_operand:DF 1 "general_operand" "f,m")))]
6835 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6837 if (REGNO (operands[0]) == REGNO (operands[1]))
6839 /* Extending float to double in an fp-reg is a no-op.
6840 NOTICE_UPDATE_CC has already assumed that the
6841 cc will be set. So cancel what it did. */
6842 cc_status = cc_prev_status;
6845 return \"fmove%.x %1,%0\";
6847 if (FP_REG_P (operands[0]))
6848 return \"f%&move%.d %f1,%0\";
6849 return \"fmove%.x %f1,%0\";
6852 (define_insn "truncxfdf2"
6853 [(set (match_operand:DF 0 "general_operand" "=m,!r")
6855 (match_operand:XF 1 "general_operand" "f,f")))]
6859 if (REG_P (operands[0]))
6861 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
6862 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
6863 return \"move%.l %+,%0\";
6865 return \"fmove%.d %f1,%0\";
6868 (define_insn "truncxfsf2"
6869 [(set (match_operand:SF 0 "general_operand" "=dm")
6871 (match_operand:XF 1 "general_operand" "f")))]
6875 (define_insn "floatsixf2"
6876 [(set (match_operand:XF 0 "general_operand" "=f")
6877 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
6881 (define_insn "floathixf2"
6882 [(set (match_operand:XF 0 "general_operand" "=f")
6883 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
6887 (define_insn "floatqixf2"
6888 [(set (match_operand:XF 0 "general_operand" "=f")
6889 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
6893 (define_insn "ftruncxf2"
6894 [(set (match_operand:XF 0 "general_operand" "=f")
6895 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
6899 if (FP_REG_P (operands[1]))
6900 return \"fintrz%.x %f1,%0\";
6901 return \"fintrz%.x %f1,%0\";
6904 (define_insn "fixxfqi2"
6905 [(set (match_operand:QI 0 "general_operand" "=dm")
6906 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
6910 (define_insn "fixxfhi2"
6911 [(set (match_operand:HI 0 "general_operand" "=dm")
6912 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
6916 (define_insn "fixxfsi2"
6917 [(set (match_operand:SI 0 "general_operand" "=dm")
6918 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
6923 [(set (match_operand:XF 0 "general_operand" "=f")
6924 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
6925 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6930 [(set (match_operand:XF 0 "general_operand" "=f")
6931 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
6932 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6937 [(set (match_operand:XF 0 "general_operand" "=f")
6938 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
6939 (match_operand:XF 1 "general_operand" "0")))]
6943 (define_insn "addxf3"
6944 [(set (match_operand:XF 0 "general_operand" "=f")
6945 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6946 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6950 if (REG_P (operands[2]))
6951 return \"fadd%.x %2,%0\";
6952 return \"fadd%.x %f2,%0\";
6956 [(set (match_operand:XF 0 "general_operand" "=f")
6957 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6958 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
6963 [(set (match_operand:XF 0 "general_operand" "=f")
6964 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6965 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
6970 [(set (match_operand:XF 0 "general_operand" "=f")
6971 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6972 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
6976 (define_insn "subxf3"
6977 [(set (match_operand:XF 0 "general_operand" "=f")
6978 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6979 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6983 if (REG_P (operands[2]))
6984 return \"fsub%.x %2,%0\";
6985 return \"fsub%.x %f2,%0\";
6989 [(set (match_operand:XF 0 "general_operand" "=f")
6990 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
6991 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6996 [(set (match_operand:XF 0 "general_operand" "=f")
6997 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
6998 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7003 [(set (match_operand:XF 0 "general_operand" "=f")
7004 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7005 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7009 (define_insn "mulxf3"
7010 [(set (match_operand:XF 0 "general_operand" "=f")
7011 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7012 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7016 if (REG_P (operands[2]))
7017 return \"fmul%.x %2,%0\";
7018 return \"fmul%.x %f2,%0\";
7022 [(set (match_operand:XF 0 "general_operand" "=f")
7023 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7024 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7029 [(set (match_operand:XF 0 "general_operand" "=f")
7030 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7031 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7036 [(set (match_operand:XF 0 "general_operand" "=f")
7037 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7038 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7042 (define_insn "divxf3"
7043 [(set (match_operand:XF 0 "general_operand" "=f")
7044 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7045 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7049 if (REG_P (operands[2]))
7050 return \"fdiv%.x %2,%0\";
7051 return \"fdiv%.x %f2,%0\";
7054 (define_expand "negxf2"
7055 [(set (match_operand:XF 0 "general_operand" "")
7056 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7060 /* ??? There isn't an FPA define_insn so we could handle it here too.
7061 For now we don't (paranoia). */
7069 target = operand_subword (operands[0], 0, 1, XFmode);
7070 result = expand_binop (SImode, xor_optab,
7071 operand_subword_force (operands[1], 0, XFmode),
7072 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7076 if (result != target)
7077 emit_move_insn (result, target);
7079 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7080 operand_subword_force (operands[1], 1, XFmode));
7081 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7082 operand_subword_force (operands[1], 2, XFmode));
7084 insns = get_insns ();
7087 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7092 (define_insn "negxf2_68881"
7093 [(set (match_operand:XF 0 "general_operand" "=f")
7094 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7098 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7099 return \"fneg%.x %1,%0\";
7100 return \"fneg%.x %f1,%0\";
7103 (define_expand "absxf2"
7104 [(set (match_operand:XF 0 "general_operand" "")
7105 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7109 /* ??? There isn't an FPA define_insn so we could handle it here too.
7110 For now we don't (paranoia). */
7118 target = operand_subword (operands[0], 0, 1, XFmode);
7119 result = expand_binop (SImode, and_optab,
7120 operand_subword_force (operands[1], 0, XFmode),
7121 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7125 if (result != target)
7126 emit_move_insn (result, target);
7128 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7129 operand_subword_force (operands[1], 1, XFmode));
7130 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7131 operand_subword_force (operands[1], 2, XFmode));
7133 insns = get_insns ();
7136 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7141 (define_insn "absxf2_68881"
7142 [(set (match_operand:XF 0 "general_operand" "=f")
7143 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7147 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7148 return \"fabs%.x %1,%0\";
7149 return \"fabs%.x %f1,%0\";
7152 (define_insn "sqrtxf2"
7153 [(set (match_operand:XF 0 "general_operand" "=f")
7154 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7158 (define_insn "sinsf2"
7159 [(set (match_operand:SF 0 "general_operand" "=f")
7160 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7161 "TARGET_68881 && flag_fast_math"
7164 if (FP_REG_P (operands[1]))
7165 return \"fsin%.x %1,%0\";
7167 return \"fsin%.s %1,%0\";
7170 (define_insn "sindf2"
7171 [(set (match_operand:DF 0 "general_operand" "=f")
7172 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7173 "TARGET_68881 && flag_fast_math"
7176 if (FP_REG_P (operands[1]))
7177 return \"fsin%.x %1,%0\";
7179 return \"fsin%.d %1,%0\";
7182 (define_insn "sinxf2"
7183 [(set (match_operand:XF 0 "general_operand" "=f")
7184 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7185 "TARGET_68881 && flag_fast_math"
7188 (define_insn "cossf2"
7189 [(set (match_operand:SF 0 "general_operand" "=f")
7190 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7191 "TARGET_68881 && flag_fast_math"
7194 if (FP_REG_P (operands[1]))
7195 return \"fcos%.x %1,%0\";
7197 return \"fcos%.s %1,%0\";
7200 (define_insn "cosdf2"
7201 [(set (match_operand:DF 0 "general_operand" "=f")
7202 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7203 "TARGET_68881 && flag_fast_math"
7206 if (FP_REG_P (operands[1]))
7207 return \"fcos%.x %1,%0\";
7209 return \"fcos%.d %1,%0\";
7212 (define_insn "cosxf2"
7213 [(set (match_operand:XF 0 "general_operand" "=f")
7214 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7215 "TARGET_68881 && flag_fast_math"