1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
753 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
755 (minus:SI (const_int 7)
756 (match_operand:SI 1 "general_operand" "di"))))]
758 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
761 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
763 (minus:SI (const_int 31)
764 (match_operand:SI 1 "general_operand" "di"))))]
766 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
768 ;; The following two patterns are like the previous two
769 ;; except that they use the fact that bit-number operands
770 ;; are automatically masked to 3 or 5 bits.
773 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
775 (minus:SI (const_int 7)
777 (match_operand:SI 1 "register_operand" "d")
780 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
783 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
785 (minus:SI (const_int 31)
787 (match_operand:SI 1 "register_operand" "d")
790 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
792 ;; Nonoffsettable mem refs are ok in this one pattern
793 ;; since we don't try to adjust them.
795 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
797 (match_operand:SI 1 "const_int_operand" "n")))]
798 "(unsigned) INTVAL (operands[1]) < 8"
801 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
802 return output_btst (operands, operands[1], operands[0], insn, 7);
806 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
808 (match_operand:SI 1 "const_int_operand" "n")))]
812 if (GET_CODE (operands[0]) == MEM)
814 operands[0] = adj_offsettable_operand (operands[0],
815 INTVAL (operands[1]) / 8);
816 operands[1] = gen_rtx (CONST_INT, VOIDmode,
817 7 - INTVAL (operands[1]) % 8);
818 return output_btst (operands, operands[1], operands[0], insn, 7);
820 operands[1] = gen_rtx (CONST_INT, VOIDmode,
821 31 - INTVAL (operands[1]));
822 return output_btst (operands, operands[1], operands[0], insn, 31);
828 ;; A special case in which it is not desirable
829 ;; to reload the constant into a data register.
830 (define_insn "pushexthisi_const"
831 [(set (match_operand:SI 0 "push_operand" "=m")
832 (match_operand:SI 1 "const_int_operand" "J"))]
833 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
836 if (operands[1] == const0_rtx)
837 return \"clr%.l %0\";
842 ;(define_insn "swapsi"
843 ; [(set (match_operand:SI 0 "general_operand" "+r")
844 ; (match_operand:SI 1 "general_operand" "+r"))
845 ; (set (match_dup 1) (match_dup 0))]
849 ;; Special case of fullword move when source is zero.
850 ;; The reason this is special is to avoid loading a zero
851 ;; into a data reg with moveq in order to store it elsewhere.
853 (define_insn "movsi_const0"
854 [(set (match_operand:SI 0 "general_operand" "=g")
856 ;; clr insns on 68000 read before writing.
857 ;; This isn't so on the 68010, but we have no TARGET_68010.
858 "((TARGET_68020 || TARGET_5200)
859 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
862 if (ADDRESS_REG_P (operands[0]))
864 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
865 if (!TARGET_68040 && !TARGET_68060)
866 return \"sub%.l %0,%0\";
871 /* Many SGS assemblers croak on size specifiers for constants. */
874 return \"lea 0.w,%0\";
877 return \"lea 0:w,%0\";
881 /* moveq is faster on the 68000. */
882 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
883 #if defined(MOTOROLA) && !defined(CRDS)
884 return \"moveq%.l %#0,%0\";
886 return \"moveq %#0,%0\";
888 return \"clr%.l %0\";
891 ;; General case of fullword move.
893 ;; This is the main "hook" for PIC code. When generating
894 ;; PIC, movsi is responsible for determining when the source address
895 ;; needs PIC relocation and appropriately calling legitimize_pic_address
896 ;; to perform the actual relocation.
898 ;; In both the PIC and non-PIC cases the patterns generated will
899 ;; matched by the next define_insn.
900 (define_expand "movsi"
901 [(set (match_operand:SI 0 "general_operand" "")
902 (match_operand:SI 1 "general_operand" ""))]
906 if (flag_pic && symbolic_operand (operands[1], SImode))
908 /* The source is an address which requires PIC relocation.
909 Call legitimize_pic_address with the source, mode, and a relocation
910 register (a new pseudo, or the final destination if reload_in_progress
911 is set). Then fall through normally */
912 extern rtx legitimize_pic_address();
913 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
914 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
918 ;; General case of fullword move. The register constraints
919 ;; force integer constants in range for a moveq to be reloaded
920 ;; if they are headed for memory.
922 ;; Notes: make sure no alternative allows g vs g.
923 ;; We don't allow f-regs since fixed point cannot go in them.
924 ;; We do allow y and x regs since fixed point is allowed in them.
925 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
926 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
930 if (which_alternative == 3)
931 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
932 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
933 return \"fpmove%.l %x1,%x0\";
934 return output_move_simode (operands);
938 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
939 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
941 "* return output_move_simode (operands);")
943 (define_expand "movhi"
944 [(set (match_operand:HI 0 "general_operand" "")
945 (match_operand:HI 1 "general_operand" ""))]
950 [(set (match_operand:HI 0 "general_operand" "=g")
951 (match_operand:HI 1 "general_operand" "g"))]
953 "* return output_move_himode (operands);")
956 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
957 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
959 "* return output_move_himode (operands);")
961 (define_expand "movstricthi"
962 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
963 (match_operand:HI 1 "general_operand" ""))]
968 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
969 (match_operand:HI 1 "general_operand" "rmn"))]
971 "* return output_move_stricthi (operands);")
974 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
975 (match_operand:HI 1 "general_operand" "rmn,r"))]
977 "* return output_move_stricthi (operands);")
979 (define_expand "movqi"
980 [(set (match_operand:QI 0 "general_operand" "")
981 (match_operand:QI 1 "general_operand" ""))]
986 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
987 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
989 "* return output_move_qimode (operands);")
992 [(set (match_operand:QI 0 "general_operand" "=d*a<Q>,d*am")
993 (match_operand:QI 1 "general_operand" "d*ami,d*a<Q>"))]
995 "* return output_move_qimode (operands);")
997 (define_expand "movstrictqi"
998 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
999 (match_operand:QI 1 "general_operand" ""))]
1004 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1005 (match_operand:QI 1 "general_operand" "dmn"))]
1007 "* return output_move_strictqi (operands);")
1010 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1011 (match_operand:QI 1 "general_operand" "dmn,d"))]
1013 "* return output_move_strictqi (operands);")
1015 (define_expand "movsf"
1016 [(set (match_operand:SF 0 "general_operand" "")
1017 (match_operand:SF 1 "general_operand" ""))]
1022 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1023 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1024 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1025 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1029 if (which_alternative >= 4)
1030 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1031 if (FPA_REG_P (operands[0]))
1033 if (FPA_REG_P (operands[1]))
1034 return \"fpmove%.s %x1,%x0\";
1035 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1036 return output_move_const_single (operands);
1037 else if (FP_REG_P (operands[1]))
1038 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1039 return \"fpmove%.s %x1,%x0\";
1041 if (FPA_REG_P (operands[1]))
1043 if (FP_REG_P (operands[0]))
1044 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1046 return \"fpmove%.s %x1,%x0\";
1048 if (FP_REG_P (operands[0]))
1050 if (FP_REG_P (operands[1]))
1051 return \"f%$move%.x %1,%0\";
1052 else if (ADDRESS_REG_P (operands[1]))
1053 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1054 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1055 return output_move_const_single (operands);
1056 return \"f%$move%.s %f1,%0\";
1058 if (FP_REG_P (operands[1]))
1060 if (ADDRESS_REG_P (operands[0]))
1061 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1062 return \"fmove%.s %f1,%0\";
1064 return \"move%.l %1,%0\";
1068 [(set (match_operand:SF 0 "general_operand" "=r,g")
1069 (match_operand:SF 1 "general_operand" "g,r"))]
1071 "* return \"move%.l %1,%0\";")
1073 (define_expand "movdf"
1074 [(set (match_operand:DF 0 "general_operand" "")
1075 (match_operand:DF 1 "general_operand" ""))]
1080 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1081 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1082 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1083 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1087 if (which_alternative == 7)
1088 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1089 if (FPA_REG_P (operands[0]))
1091 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1092 return output_move_const_double (operands);
1093 if (FP_REG_P (operands[1]))
1094 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1095 return \"fpmove%.d %x1,%x0\";
1097 else if (FPA_REG_P (operands[1]))
1099 if (FP_REG_P(operands[0]))
1100 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1102 return \"fpmove%.d %x1,%x0\";
1104 if (FP_REG_P (operands[0]))
1106 if (FP_REG_P (operands[1]))
1107 return \"f%&move%.x %1,%0\";
1108 if (REG_P (operands[1]))
1111 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1112 output_asm_insn (\"move%.l %1,%-\", xoperands);
1113 output_asm_insn (\"move%.l %1,%-\", operands);
1114 return \"f%&move%.d %+,%0\";
1116 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1117 return output_move_const_double (operands);
1118 return \"f%&move%.d %f1,%0\";
1120 else if (FP_REG_P (operands[1]))
1122 if (REG_P (operands[0]))
1124 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1125 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1126 return \"move%.l %+,%0\";
1129 return \"fmove%.d %f1,%0\";
1131 return output_move_double (operands);
1135 [(set (match_operand:DF 0 "general_operand" "=r,g")
1136 (match_operand:DF 1 "general_operand" "g,r"))]
1138 "* return output_move_double (operands);")
1140 (define_expand "movxf"
1141 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1142 (match_operand:XF 1 "general_operand" ""))]
1146 if (CONSTANT_P (operands[1]))
1148 operands[1] = force_const_mem (XFmode, operands[1]);
1149 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1150 && ! reload_in_progress)
1151 operands[1] = change_address (operands[1], XFmode,
1152 XEXP (operands[1], 0));
1157 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1158 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1162 if (FP_REG_P (operands[0]))
1164 if (FP_REG_P (operands[1]))
1165 return \"fmove%.x %1,%0\";
1166 if (REG_P (operands[1]))
1169 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1170 output_asm_insn (\"move%.l %1,%-\", xoperands);
1171 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1172 output_asm_insn (\"move%.l %1,%-\", xoperands);
1173 output_asm_insn (\"move%.l %1,%-\", operands);
1174 return \"fmove%.x %+,%0\";
1176 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1177 return \"fmove%.x %1,%0\";
1178 return \"fmove%.x %f1,%0\";
1180 if (REG_P (operands[0]))
1182 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1183 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1184 output_asm_insn (\"move%.l %+,%0\", operands);
1185 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1186 return \"move%.l %+,%0\";
1188 return \"fmove%.x %f1,%0\";
1193 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1194 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1195 "! TARGET_68881 && ! TARGET_5200"
1198 if (FP_REG_P (operands[0]))
1200 if (FP_REG_P (operands[1]))
1201 return \"fmove%.x %1,%0\";
1202 if (REG_P (operands[1]))
1205 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1206 output_asm_insn (\"move%.l %1,%-\", xoperands);
1207 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1208 output_asm_insn (\"move%.l %1,%-\", xoperands);
1209 output_asm_insn (\"move%.l %1,%-\", operands);
1210 return \"fmove%.x %+,%0\";
1212 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1213 return \"fmove%.x %1,%0\";
1214 return \"fmove%.x %f1,%0\";
1216 if (FP_REG_P (operands[1]))
1218 if (REG_P (operands[0]))
1220 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1221 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1222 output_asm_insn (\"move%.l %+,%0\", operands);
1223 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1224 return \"move%.l %+,%0\";
1227 return \"fmove%.x %f1,%0\";
1229 return output_move_double (operands);
1234 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1235 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1236 "! TARGET_68881 && TARGET_5200"
1237 "* return output_move_double (operands);")
1239 (define_expand "movdi"
1240 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1241 [(set (match_operand:DI 0 "general_operand" "")
1242 (match_operand:DI 1 "general_operand" ""))]
1246 ;; movdi can apply to fp regs in some cases
1248 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1249 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1250 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1251 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1252 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1253 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1254 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1258 if (which_alternative == 8)
1259 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1260 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1261 return \"fpmove%.d %x1,%x0\";
1262 if (FP_REG_P (operands[0]))
1264 if (FP_REG_P (operands[1]))
1265 return \"fmove%.x %1,%0\";
1266 if (REG_P (operands[1]))
1269 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1270 output_asm_insn (\"move%.l %1,%-\", xoperands);
1271 output_asm_insn (\"move%.l %1,%-\", operands);
1272 return \"fmove%.d %+,%0\";
1274 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1275 return output_move_const_double (operands);
1276 return \"fmove%.d %f1,%0\";
1278 else if (FP_REG_P (operands[1]))
1280 if (REG_P (operands[0]))
1282 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1283 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1284 return \"move%.l %+,%0\";
1287 return \"fmove%.d %f1,%0\";
1289 return output_move_double (operands);
1293 [(set (match_operand:DI 0 "general_operand" "=r,g")
1294 (match_operand:DI 1 "general_operand" "g,r"))]
1296 "* return output_move_double (operands);")
1298 ;; Thus goes after the move instructions
1299 ;; because the move instructions are better (require no spilling)
1300 ;; when they can apply. It goes before the add/sub insns
1301 ;; so we will prefer it to them.
1303 (define_insn "pushasi"
1304 [(set (match_operand:SI 0 "push_operand" "=m")
1305 (match_operand:SI 1 "address_operand" "p"))]
1309 ;; truncation instructions
1310 (define_insn "truncsiqi2"
1311 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1313 (match_operand:SI 1 "general_operand" "doJ,i")))]
1317 if (GET_CODE (operands[0]) == REG)
1319 /* Must clear condition codes, since the move.l bases them on
1320 the entire 32 bits, not just the desired 8 bits. */
1322 return \"move%.l %1,%0\";
1324 if (GET_CODE (operands[1]) == MEM)
1325 operands[1] = adj_offsettable_operand (operands[1], 3);
1326 return \"move%.b %1,%0\";
1329 (define_insn "trunchiqi2"
1330 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1332 (match_operand:HI 1 "general_operand" "doJ,i")))]
1336 if (GET_CODE (operands[0]) == REG
1337 && (GET_CODE (operands[1]) == MEM
1338 || GET_CODE (operands[1]) == CONST_INT))
1340 /* Must clear condition codes, since the move.w bases them on
1341 the entire 16 bits, not just the desired 8 bits. */
1343 return \"move%.w %1,%0\";
1345 if (GET_CODE (operands[0]) == REG)
1347 /* Must clear condition codes, since the move.l bases them on
1348 the entire 32 bits, not just the desired 8 bits. */
1350 return \"move%.l %1,%0\";
1352 if (GET_CODE (operands[1]) == MEM)
1353 operands[1] = adj_offsettable_operand (operands[1], 1);
1354 return \"move%.b %1,%0\";
1357 (define_insn "truncsihi2"
1358 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1360 (match_operand:SI 1 "general_operand" "roJ,i")))]
1364 if (GET_CODE (operands[0]) == REG)
1366 /* Must clear condition codes, since the move.l bases them on
1367 the entire 32 bits, not just the desired 8 bits. */
1369 return \"move%.l %1,%0\";
1371 if (GET_CODE (operands[1]) == MEM)
1372 operands[1] = adj_offsettable_operand (operands[1], 2);
1373 return \"move%.w %1,%0\";
1376 ;; zero extension instructions
1378 ;; this is the canonical form for (lshiftrt:DI x 32)
1379 (define_insn "zero_extendsidi2"
1380 [(set (match_operand:DI 0 "general_operand" "rm")
1381 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1386 if (GET_CODE (operands[0]) == REG)
1387 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1388 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1389 return \"move%.l %1,%0\;clr%.l %0\";
1390 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1391 return \"clr%.l %0\;move%.l %1,%0\";
1393 operands[2] = adj_offsettable_operand (operands[0], 4);
1394 if (ADDRESS_REG_P (operands[0]))
1395 return \"move%.l %1,%2\;sub%.l %0,%0\";
1397 return \"move%.l %1,%2\;clr%.l %0\";
1400 (define_expand "zero_extendhisi2"
1401 [(set (match_operand:SI 0 "register_operand" "")
1403 (set (strict_low_part (match_dup 2))
1404 (match_operand:HI 1 "general_operand" ""))]
1408 operands[1] = make_safe_from (operands[1], operands[0]);
1409 if (GET_CODE (operands[0]) == SUBREG)
1410 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1411 SUBREG_WORD (operands[0]));
1413 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1416 (define_expand "zero_extendqihi2"
1417 [(set (match_operand:HI 0 "register_operand" "")
1419 (set (strict_low_part (match_dup 2))
1420 (match_operand:QI 1 "general_operand" ""))]
1424 operands[1] = make_safe_from (operands[1], operands[0]);
1425 if (GET_CODE (operands[0]) == SUBREG)
1426 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1427 SUBREG_WORD (operands[0]));
1429 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1432 (define_expand "zero_extendqisi2"
1433 [(set (match_operand:SI 0 "register_operand" "")
1435 (set (strict_low_part (match_dup 2))
1436 (match_operand:QI 1 "general_operand" ""))]
1440 operands[1] = make_safe_from (operands[1], operands[0]);
1441 if (GET_CODE (operands[0]) == SUBREG)
1442 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1443 SUBREG_WORD (operands[0]));
1445 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1448 ;; Patterns to recognize zero-extend insns produced by the combiner.
1449 ;; We don't allow both operands in memory, because of aliasing problems.
1450 ;; Explicitly disallow two memory operands via the condition since reloading
1451 ;; of this case will result in worse code than the uncombined patterns.
1454 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1455 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1456 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1459 if (DATA_REG_P (operands[0]))
1461 if (GET_CODE (operands[1]) == REG
1462 && REGNO (operands[0]) == REGNO (operands[1]))
1463 return \"and%.l %#0xFFFF,%0\";
1464 if (reg_mentioned_p (operands[0], operands[1]))
1465 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1466 return \"clr%.l %0\;move%.w %1,%0\";
1468 else if (GET_CODE (operands[0]) == MEM
1469 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1470 return \"move%.w %1,%0\;clr%.w %0\";
1471 else if (GET_CODE (operands[0]) == MEM
1472 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1473 return \"clr%.w %0\;move%.w %1,%0\";
1476 output_asm_insn (\"clr%.w %0\", operands);
1477 operands[0] = adj_offsettable_operand (operands[0], 2);
1478 return \"move%.w %1,%0\";
1483 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1484 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1485 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1488 if (DATA_REG_P (operands[0]))
1490 if (GET_CODE (operands[1]) == REG
1491 && REGNO (operands[0]) == REGNO (operands[1]))
1492 return \"and%.w %#0xFF,%0\";
1493 if (reg_mentioned_p (operands[0], operands[1]))
1494 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1495 return \"clr%.w %0\;move%.b %1,%0\";
1497 else if (GET_CODE (operands[0]) == MEM
1498 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1500 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1501 == STACK_POINTER_REGNUM)
1503 output_asm_insn (\"clr%.w %-\", operands);
1504 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1505 plus_constant (stack_pointer_rtx, 1));
1506 return \"move%.b %1,%0\";
1509 return \"move%.b %1,%0\;clr%.b %0\";
1511 else if (GET_CODE (operands[0]) == MEM
1512 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1513 return \"clr%.b %0\;move%.b %1,%0\";
1516 output_asm_insn (\"clr%.b %0\", operands);
1517 operands[0] = adj_offsettable_operand (operands[0], 1);
1518 return \"move%.b %1,%0\";
1523 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1524 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1525 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1528 if (DATA_REG_P (operands[0]))
1530 if (GET_CODE (operands[1]) == REG
1531 && REGNO (operands[0]) == REGNO (operands[1]))
1532 return \"and%.l %#0xFF,%0\";
1533 if (reg_mentioned_p (operands[0], operands[1]))
1534 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1535 return \"clr%.l %0\;move%.b %1,%0\";
1537 else if (GET_CODE (operands[0]) == MEM
1538 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1540 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1543 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1545 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1548 return \"clrl %0@-\;moveb %1,%0@(3)\";
1551 else if (GET_CODE (operands[0]) == MEM
1552 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1554 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1557 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1559 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1562 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1567 output_asm_insn (\"clr%.l %0\", operands);
1568 operands[0] = adj_offsettable_operand (operands[0], 3);
1569 return \"move%.b %1,%0\";
1573 ;; sign extension instructions
1575 (define_insn "extendqidi2"
1576 [(set (match_operand:DI 0 "general_operand" "=d")
1578 (match_operand:QI 1 "general_operand" "rm")))]
1583 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1584 if (TARGET_68020 || TARGET_5200)
1585 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1587 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1590 (define_insn "extendhidi2"
1591 [(set (match_operand:DI 0 "general_operand" "=d")
1593 (match_operand:HI 1 "general_operand" "rm")))]
1598 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1599 if (TARGET_68020 || TARGET_5200)
1600 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1602 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1605 (define_insn "extendsidi2"
1606 [(set (match_operand:DI 0 "general_operand" "=d")
1608 (match_operand:SI 1 "general_operand" "rm")))]
1613 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1614 if (TARGET_68020 || TARGET_5200)
1615 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1617 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1620 ;; Special case when one can avoid register clobbering, copy and test
1621 ;; Maybe there is a way to make that the general case, by forcing the
1622 ;; result of the SI tree to be in the lower register of the DI target
1624 (define_insn "extendplussidi"
1625 [(set (match_operand:DI 0 "register_operand" "=d")
1626 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1627 (match_operand:SI 2 "general_operand" "rmn"))))]
1632 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1633 if (GET_CODE (operands[1]) == CONST_INT
1634 && (unsigned) INTVAL (operands[1]) > 8)
1636 rtx tmp = operands[1];
1638 operands[1] = operands[2];
1641 if (GET_CODE (operands[1]) == REG
1642 && REGNO (operands[1]) == REGNO (operands[3]))
1643 output_asm_insn (\"add%.l %2,%3\", operands);
1645 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1646 if (TARGET_68020 || TARGET_5200)
1647 return \"smi %0\;extb%.l %0\";
1649 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1652 (define_insn "extendhisi2"
1653 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1655 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1659 if (ADDRESS_REG_P (operands[0]))
1660 return \"move%.w %1,%0\";
1661 return \"ext%.l %0\";
1664 (define_insn "extendqihi2"
1665 [(set (match_operand:HI 0 "general_operand" "=d")
1666 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1670 (define_insn "extendqisi2"
1671 [(set (match_operand:SI 0 "general_operand" "=d")
1672 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1673 "TARGET_68020 || TARGET_5200"
1676 ;; Conversions between float and double.
1678 (define_expand "extendsfdf2"
1679 [(set (match_operand:DF 0 "general_operand" "")
1681 (match_operand:SF 1 "general_operand" "")))]
1682 "TARGET_68881 || TARGET_FPA"
1686 [(set (match_operand:DF 0 "general_operand" "=x,y")
1688 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1693 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1695 (match_operand:SF 1 "general_operand" "f,dmF")))]
1699 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1701 if (REGNO (operands[0]) == REGNO (operands[1]))
1703 /* Extending float to double in an fp-reg is a no-op.
1704 NOTICE_UPDATE_CC has already assumed that the
1705 cc will be set. So cancel what it did. */
1706 cc_status = cc_prev_status;
1709 return \"f%&move%.x %1,%0\";
1711 if (FP_REG_P (operands[0]))
1712 return \"f%&move%.s %f1,%0\";
1713 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1715 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1716 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1717 return \"move%.l %+,%0\";
1719 return \"fmove%.d %f1,%0\";
1722 ;; This cannot output into an f-reg because there is no way to be
1723 ;; sure of truncating in that case.
1724 ;; But on the Sun FPA, we can be sure.
1725 (define_expand "truncdfsf2"
1726 [(set (match_operand:SF 0 "general_operand" "")
1728 (match_operand:DF 1 "general_operand" "")))]
1729 "TARGET_68881 || TARGET_FPA"
1733 [(set (match_operand:SF 0 "general_operand" "=x,y")
1735 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1739 ;; On the '040 we can truncate in a register accurately and easily.
1741 [(set (match_operand:SF 0 "general_operand" "=f")
1743 (match_operand:DF 1 "general_operand" "fmG")))]
1747 if (FP_REG_P (operands[1]))
1748 return \"f%$move%.x %1,%0\";
1749 return \"f%$move%.d %f1,%0\";
1753 [(set (match_operand:SF 0 "general_operand" "=dm")
1755 (match_operand:DF 1 "general_operand" "f")))]
1759 ;; Conversion between fixed point and floating point.
1760 ;; Note that among the fix-to-float insns
1761 ;; the ones that start with SImode come first.
1762 ;; That is so that an operand that is a CONST_INT
1763 ;; (and therefore lacks a specific machine mode).
1764 ;; will be recognized as SImode (which is always valid)
1765 ;; rather than as QImode or HImode.
1767 (define_expand "floatsisf2"
1768 [(set (match_operand:SF 0 "general_operand" "")
1769 (float:SF (match_operand:SI 1 "general_operand" "")))]
1770 "TARGET_68881 || TARGET_FPA"
1774 [(set (match_operand:SF 0 "general_operand" "=y,x")
1775 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1780 [(set (match_operand:SF 0 "general_operand" "=f")
1781 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1785 (define_expand "floatsidf2"
1786 [(set (match_operand:DF 0 "general_operand" "")
1787 (float:DF (match_operand:SI 1 "general_operand" "")))]
1788 "TARGET_68881 || TARGET_FPA"
1792 [(set (match_operand:DF 0 "general_operand" "=y,x")
1793 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1798 [(set (match_operand:DF 0 "general_operand" "=f")
1799 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1803 (define_insn "floathisf2"
1804 [(set (match_operand:SF 0 "general_operand" "=f")
1805 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1809 (define_insn "floathidf2"
1810 [(set (match_operand:DF 0 "general_operand" "=f")
1811 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1815 (define_insn "floatqisf2"
1816 [(set (match_operand:SF 0 "general_operand" "=f")
1817 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1821 (define_insn "floatqidf2"
1822 [(set (match_operand:DF 0 "general_operand" "=f")
1823 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1827 ;; New routines to convert floating-point values to integers
1828 ;; to be used on the '040. These should be faster than trapping
1829 ;; into the kernel to emulate fintrz. They should also be faster
1830 ;; than calling the subroutines fixsfsi or fixdfsi.
1832 (define_insn "fix_truncdfsi2"
1833 [(set (match_operand:SI 0 "general_operand" "=dm")
1834 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1835 (clobber (match_scratch:SI 2 "=d"))
1836 (clobber (match_scratch:SI 3 "=d"))]
1837 "TARGET_68881 && TARGET_68040"
1841 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1844 (define_insn "fix_truncdfhi2"
1845 [(set (match_operand:HI 0 "general_operand" "=dm")
1846 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1847 (clobber (match_scratch:SI 2 "=d"))
1848 (clobber (match_scratch:SI 3 "=d"))]
1849 "TARGET_68881 && TARGET_68040"
1853 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1856 (define_insn "fix_truncdfqi2"
1857 [(set (match_operand:QI 0 "general_operand" "=dm")
1858 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1859 (clobber (match_scratch:SI 2 "=d"))
1860 (clobber (match_scratch:SI 3 "=d"))]
1861 "TARGET_68881 && TARGET_68040"
1865 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1868 ;; Convert a float to a float whose value is an integer.
1869 ;; This is the first stage of converting it to an integer type.
1871 (define_insn "ftruncdf2"
1872 [(set (match_operand:DF 0 "general_operand" "=f")
1873 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1874 "TARGET_68881 && !TARGET_68040"
1877 if (FP_REG_P (operands[1]))
1878 return \"fintrz%.x %f1,%0\";
1879 return \"fintrz%.d %f1,%0\";
1882 (define_insn "ftruncsf2"
1883 [(set (match_operand:SF 0 "general_operand" "=f")
1884 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1885 "TARGET_68881 && !TARGET_68040"
1888 if (FP_REG_P (operands[1]))
1889 return \"fintrz%.x %f1,%0\";
1890 return \"fintrz%.s %f1,%0\";
1893 ;; Convert a float whose value is an integer
1894 ;; to an actual integer. Second stage of converting float to integer type.
1895 (define_insn "fixsfqi2"
1896 [(set (match_operand:QI 0 "general_operand" "=dm")
1897 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1901 (define_insn "fixsfhi2"
1902 [(set (match_operand:HI 0 "general_operand" "=dm")
1903 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1907 (define_insn "fixsfsi2"
1908 [(set (match_operand:SI 0 "general_operand" "=dm")
1909 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1913 (define_insn "fixdfqi2"
1914 [(set (match_operand:QI 0 "general_operand" "=dm")
1915 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1919 (define_insn "fixdfhi2"
1920 [(set (match_operand:HI 0 "general_operand" "=dm")
1921 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1925 (define_insn "fixdfsi2"
1926 [(set (match_operand:SI 0 "general_operand" "=dm")
1927 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1931 ;; Convert a float to an integer.
1932 ;; On the Sun FPA, this is done in one step.
1935 [(set (match_operand:SI 0 "general_operand" "=x,y")
1936 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1941 [(set (match_operand:SI 0 "general_operand" "=x,y")
1942 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1948 (define_insn "adddi_lshrdi_63"
1949 [(set (match_operand:DI 0 "general_operand" "=d")
1950 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1953 (clobber (match_scratch:SI 2 "=d"))]
1957 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1958 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1960 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1961 if (GET_CODE (operands[1]) == REG)
1962 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1963 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1964 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1965 operands[4] = operands[1];
1967 operands[4] = adj_offsettable_operand (operands[1], 4);
1968 if (GET_CODE (operands[1]) == MEM
1969 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1970 output_asm_insn (\"move%.l %4,%3\", operands);
1971 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1972 if (TARGET_68020 || TARGET_5200)
1973 output_asm_insn (\"extb%.l %2\", operands);
1975 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1976 if (GET_CODE (operands[1]) != MEM
1977 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1978 output_asm_insn (\"move%.l %4,%3\", operands);
1979 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1982 (define_insn "adddi_sexthishl32"
1983 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
1984 (plus:DI (ashift:DI (sign_extend:DI
1985 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1987 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1988 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1993 if (ADDRESS_REG_P (operands[0]))
1994 return \"add%.w %1,%0\";
1995 else if (ADDRESS_REG_P (operands[3]))
1996 return \"move%.w %1,%3\;add%.l %3,%0\";
1998 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2001 (define_insn "adddi_dilshr32"
2002 [(set (match_operand:DI 0 "general_operand" "=do")
2003 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2004 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2005 ;; (const_int 32))))]
2006 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2008 (match_operand:DI 2 "general_operand" "0")))]
2013 if (GET_CODE (operands[0]) == REG)
2014 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2016 operands[2] = adj_offsettable_operand (operands[0], 4);
2017 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2020 (define_insn "adddi_dishl32"
2021 [(set (match_operand:DI 0 "general_operand" "=ro")
2022 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2023 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2024 ;; (const_int 32))))]
2025 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2027 (match_operand:DI 2 "general_operand" "0")))]
2032 if (GET_CODE (operands[1]) == REG)
2033 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2035 operands[1] = adj_offsettable_operand (operands[1], 4);
2036 return \"add%.l %1,%0\";
2039 (define_insn "adddi3"
2040 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2041 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2042 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2043 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2047 if (DATA_REG_P (operands[0]))
2049 if (DATA_REG_P (operands[2]))
2050 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2051 else if (GET_CODE (operands[2]) == MEM
2052 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2054 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2058 if (GET_CODE (operands[2]) == REG)
2059 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2060 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2062 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2063 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2065 else if (GET_CODE (operands[2]) == CONST_INT)
2067 operands[1] = operands[2];
2068 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2071 operands[1] = adj_offsettable_operand (operands[2], 4);
2072 /* TODO : for consts, optimize move and add */
2073 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2076 else if (GET_CODE (operands[0]) == MEM)
2078 if (GET_CODE (operands[2]) == MEM
2079 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2080 return \"add%.l %2,%0\;addx%.l %2,%0\";
2082 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2084 operands[1] = gen_rtx (MEM, SImode,
2085 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2086 gen_rtx (CONST_INT, VOIDmode, -8)));
2087 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2089 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2091 operands[1] = XEXP(operands[0], 0);
2092 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2096 operands[1] = adj_offsettable_operand (operands[0], 4);
2097 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2102 (define_insn "addsi_lshrsi_31"
2103 [(set (match_operand:SI 0 "general_operand" "=dm")
2104 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2110 operands[2] = operands[0];
2111 operands[3] = gen_label_rtx();
2112 if (GET_CODE (operands[0]) == MEM)
2114 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2115 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2116 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2117 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2119 output_asm_insn (\"move%.l %1,%0\", operands);
2121 output_asm_insn (\"jbpl %l3\", operands);
2123 output_asm_insn (\"jpl %l3\", operands);
2126 output_asm_insn (\"addq%.l %#1,%2\", operands);
2128 output_asm_insn (\"add%.l %#1,%2\", operands);
2130 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2131 CODE_LABEL_NUMBER (operands[3]));
2135 (define_expand "addsi3"
2136 [(set (match_operand:SI 0 "general_operand" "")
2137 (plus:SI (match_operand:SI 1 "general_operand" "")
2138 (match_operand:SI 2 "general_operand" "")))]
2142 ;; Note that the middle two alternatives are near-duplicates
2143 ;; in order to handle insns generated by reload.
2144 ;; This is needed since they are not themselves reloaded,
2145 ;; so commutativity won't apply to them.
2146 (define_insn "*addsi3_internal"
2147 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2148 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2149 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2151 "* return output_addsi3 (operands);")
2153 (define_insn "*addsi3_5200"
2154 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2155 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2156 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2158 "* return output_addsi3 (operands);")
2161 [(set (match_operand:SI 0 "general_operand" "=a")
2162 (plus:SI (match_operand:SI 1 "general_operand" "0")
2164 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2168 (define_insn "addhi3"
2169 [(set (match_operand:HI 0 "general_operand" "=m,r")
2170 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2171 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2175 if (GET_CODE (operands[2]) == CONST_INT)
2178 /* If the constant would be a negative number when interpreted as
2179 HImode, make it negative. This is usually, but not always, done
2180 elsewhere in the compiler. First check for constants out of range,
2181 which could confuse us. */
2183 if (INTVAL (operands[2]) >= 32768)
2184 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2185 INTVAL (operands[2]) - 65536);
2187 if (INTVAL (operands[2]) > 0
2188 && INTVAL (operands[2]) <= 8)
2189 return \"addq%.w %2,%0\";
2190 if (INTVAL (operands[2]) < 0
2191 && INTVAL (operands[2]) >= -8)
2193 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2194 - INTVAL (operands[2]));
2195 return \"subq%.w %2,%0\";
2197 /* On the CPU32 it is faster to use two addqw instructions to
2198 add a small integer (8 < N <= 16) to a register.
2199 Likewise for subqw. */
2200 if (TARGET_CPU32 && REG_P (operands[0]))
2202 if (INTVAL (operands[2]) > 8
2203 && INTVAL (operands[2]) <= 16)
2205 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2206 INTVAL (operands[2]) - 8);
2207 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2209 if (INTVAL (operands[2]) < -8
2210 && INTVAL (operands[2]) >= -16)
2212 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2213 - INTVAL (operands[2]) - 8);
2214 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2218 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2220 return \"lea (%c2,%0),%0\";
2222 return \"lea %0@(%c2),%0\";
2225 return \"add%.w %2,%0\";
2228 ;; These insns must use MATCH_DUP instead of the more expected
2229 ;; use of a matching constraint because the "output" here is also
2230 ;; an input, so you can't use the matching constraint. That also means
2231 ;; that you can't use the "%", so you need patterns with the matched
2232 ;; operand in both positions.
2235 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2236 (plus:HI (match_dup 0)
2237 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2241 if (GET_CODE (operands[1]) == CONST_INT)
2244 /* If the constant would be a negative number when interpreted as
2245 HImode, make it negative. This is usually, but not always, done
2246 elsewhere in the compiler. First check for constants out of range,
2247 which could confuse us. */
2249 if (INTVAL (operands[1]) >= 32768)
2250 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2251 INTVAL (operands[1]) - 65536);
2253 if (INTVAL (operands[1]) > 0
2254 && INTVAL (operands[1]) <= 8)
2255 return \"addq%.w %1,%0\";
2256 if (INTVAL (operands[1]) < 0
2257 && INTVAL (operands[1]) >= -8)
2259 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2260 - INTVAL (operands[1]));
2261 return \"subq%.w %1,%0\";
2263 /* On the CPU32 it is faster to use two addqw instructions to
2264 add a small integer (8 < N <= 16) to a register.
2265 Likewise for subqw. */
2266 if (TARGET_CPU32 && REG_P (operands[0]))
2268 if (INTVAL (operands[1]) > 8
2269 && INTVAL (operands[1]) <= 16)
2271 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2272 INTVAL (operands[1]) - 8);
2273 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2275 if (INTVAL (operands[1]) < -8
2276 && INTVAL (operands[1]) >= -16)
2278 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2279 - INTVAL (operands[1]) - 8);
2280 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2284 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2286 return \"lea (%c1,%0),%0\";
2288 return \"lea %0@(%c1),%0\";
2291 return \"add%.w %1,%0\";
2295 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2296 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2301 if (GET_CODE (operands[1]) == CONST_INT)
2304 /* If the constant would be a negative number when interpreted as
2305 HImode, make it negative. This is usually, but not always, done
2306 elsewhere in the compiler. First check for constants out of range,
2307 which could confuse us. */
2309 if (INTVAL (operands[1]) >= 32768)
2310 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2311 INTVAL (operands[1]) - 65536);
2313 if (INTVAL (operands[1]) > 0
2314 && INTVAL (operands[1]) <= 8)
2315 return \"addq%.w %1,%0\";
2316 if (INTVAL (operands[1]) < 0
2317 && INTVAL (operands[1]) >= -8)
2319 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2320 - INTVAL (operands[1]));
2321 return \"subq%.w %1,%0\";
2323 /* On the CPU32 it is faster to use two addqw instructions to
2324 add a small integer (8 < N <= 16) to a register.
2325 Likewise for subqw. */
2326 if (TARGET_CPU32 && REG_P (operands[0]))
2328 if (INTVAL (operands[1]) > 8
2329 && INTVAL (operands[1]) <= 16)
2331 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2332 INTVAL (operands[1]) - 8);
2333 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2335 if (INTVAL (operands[1]) < -8
2336 && INTVAL (operands[1]) >= -16)
2338 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2339 - INTVAL (operands[1]) - 8);
2340 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2344 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2346 return \"lea (%c1,%0),%0\";
2348 return \"lea %0@(%c1),%0\";
2351 return \"add%.w %1,%0\";
2354 (define_insn "addqi3"
2355 [(set (match_operand:QI 0 "general_operand" "=m,d")
2356 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2357 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2362 if (GET_CODE (operands[2]) == CONST_INT)
2364 if (INTVAL (operands[2]) >= 128)
2365 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2366 INTVAL (operands[2]) - 256);
2368 if (INTVAL (operands[2]) > 0
2369 && INTVAL (operands[2]) <= 8)
2370 return \"addq%.b %2,%0\";
2371 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2373 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2374 return \"subq%.b %2,%0\";
2378 return \"add%.b %2,%0\";
2382 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2383 (plus:QI (match_dup 0)
2384 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2389 if (GET_CODE (operands[1]) == CONST_INT)
2391 if (INTVAL (operands[1]) >= 128)
2392 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2393 INTVAL (operands[1]) - 256);
2395 if (INTVAL (operands[1]) > 0
2396 && INTVAL (operands[1]) <= 8)
2397 return \"addq%.b %1,%0\";
2398 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2400 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2401 return \"subq%.b %1,%0\";
2405 return \"add%.b %1,%0\";
2409 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2410 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2416 if (GET_CODE (operands[1]) == CONST_INT)
2418 if (INTVAL (operands[1]) >= 128)
2419 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2420 INTVAL (operands[1]) - 256);
2422 if (INTVAL (operands[1]) > 0
2423 && INTVAL (operands[1]) <= 8)
2424 return \"addq%.b %1,%0\";
2425 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2427 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2428 return \"subq%.b %1,%0\";
2432 return \"add%.b %1,%0\";
2435 (define_expand "adddf3"
2436 [(set (match_operand:DF 0 "general_operand" "")
2437 (plus:DF (match_operand:DF 1 "general_operand" "")
2438 (match_operand:DF 2 "general_operand" "")))]
2439 "TARGET_68881 || TARGET_FPA"
2443 [(set (match_operand:DF 0 "general_operand" "=x,y")
2444 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2445 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2449 if (rtx_equal_p (operands[0], operands[1]))
2450 return \"fpadd%.d %y2,%0\";
2451 if (rtx_equal_p (operands[0], operands[2]))
2452 return \"fpadd%.d %y1,%0\";
2453 if (which_alternative == 0)
2454 return \"fpadd3%.d %w2,%w1,%0\";
2455 return \"fpadd3%.d %x2,%x1,%0\";
2459 [(set (match_operand:DF 0 "general_operand" "=f")
2460 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2461 (match_operand:DF 1 "general_operand" "0")))]
2466 [(set (match_operand:DF 0 "general_operand" "=f")
2467 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2468 (match_operand:DF 1 "general_operand" "0")))]
2473 [(set (match_operand:DF 0 "general_operand" "=f")
2474 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2475 (match_operand:DF 1 "general_operand" "0")))]
2480 [(set (match_operand:DF 0 "general_operand" "=f")
2481 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2482 (match_operand:DF 2 "general_operand" "fmG")))]
2486 if (REG_P (operands[2]))
2487 return \"f%&add%.x %2,%0\";
2488 return \"f%&add%.d %f2,%0\";
2491 (define_expand "addsf3"
2492 [(set (match_operand:SF 0 "general_operand" "")
2493 (plus:SF (match_operand:SF 1 "general_operand" "")
2494 (match_operand:SF 2 "general_operand" "")))]
2495 "TARGET_68881 || TARGET_FPA"
2499 [(set (match_operand:SF 0 "general_operand" "=x,y")
2500 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2501 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2505 if (rtx_equal_p (operands[0], operands[1]))
2506 return \"fpadd%.s %w2,%0\";
2507 if (rtx_equal_p (operands[0], operands[2]))
2508 return \"fpadd%.s %w1,%0\";
2509 if (which_alternative == 0)
2510 return \"fpadd3%.s %w2,%w1,%0\";
2511 return \"fpadd3%.s %2,%1,%0\";
2515 [(set (match_operand:SF 0 "general_operand" "=f")
2516 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2517 (match_operand:SF 1 "general_operand" "0")))]
2522 [(set (match_operand:SF 0 "general_operand" "=f")
2523 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2524 (match_operand:SF 1 "general_operand" "0")))]
2529 [(set (match_operand:SF 0 "general_operand" "=f")
2530 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2531 (match_operand:SF 1 "general_operand" "0")))]
2536 [(set (match_operand:SF 0 "general_operand" "=f")
2537 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2538 (match_operand:SF 2 "general_operand" "fdmF")))]
2542 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2543 return \"f%$add%.x %2,%0\";
2544 return \"f%$add%.s %f2,%0\";
2547 ;; subtract instructions
2549 (define_insn "subdi_sexthishl32"
2550 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2551 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2552 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2554 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2559 if (ADDRESS_REG_P (operands[0]))
2560 return \"sub%.w %2,%0\";
2561 else if (ADDRESS_REG_P (operands[3]))
2562 return \"move%.w %2,%3\;sub%.l %3,%0\";
2564 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2567 (define_insn "subdi_dishl32"
2568 [(set (match_operand:DI 0 "general_operand" "+ro")
2569 (minus:DI (match_dup 0)
2570 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2576 if (GET_CODE (operands[1]) == REG)
2577 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2579 operands[1] = adj_offsettable_operand (operands[1], 4);
2580 return \"sub%.l %1,%0\";
2583 (define_insn "subdi3"
2584 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2585 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2586 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2587 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2591 if (DATA_REG_P (operands[0]))
2593 if (DATA_REG_P (operands[2]))
2594 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2595 else if (GET_CODE (operands[2]) == MEM
2596 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2598 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2602 if (GET_CODE (operands[2]) == REG)
2603 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2604 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2606 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2607 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2609 else if (GET_CODE (operands[2]) == CONST_INT)
2611 operands[1] = operands[2];
2612 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2615 operands[1] = adj_offsettable_operand (operands[2], 4);
2616 /* TODO : for consts, optimize move and sub */
2617 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2620 else if (GET_CODE (operands[0]) == MEM)
2622 if (GET_CODE (operands[2]) == MEM
2623 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2624 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2626 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2628 operands[1] = gen_rtx (MEM, SImode,
2629 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2630 gen_rtx (CONST_INT, VOIDmode, -8)));
2631 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2633 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2635 operands[1] = XEXP(operands[0], 0);
2636 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2640 operands[1] = adj_offsettable_operand (operands[0], 4);
2641 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2646 (define_insn "subsi3"
2647 [(set (match_operand:SI 0 "general_operand" "=m,r")
2648 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2649 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2654 [(set (match_operand:SI 0 "general_operand" "=a")
2655 (minus:SI (match_operand:SI 1 "general_operand" "0")
2657 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2661 (define_insn "subhi3"
2662 [(set (match_operand:HI 0 "general_operand" "=m,r")
2663 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2664 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2669 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2670 (minus:HI (match_dup 0)
2671 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2675 (define_insn "subqi3"
2676 [(set (match_operand:QI 0 "general_operand" "=m,d")
2677 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2678 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2683 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2684 (minus:QI (match_dup 0)
2685 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2689 (define_expand "subdf3"
2690 [(set (match_operand:DF 0 "general_operand" "")
2691 (minus:DF (match_operand:DF 1 "general_operand" "")
2692 (match_operand:DF 2 "general_operand" "")))]
2693 "TARGET_68881 || TARGET_FPA"
2697 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2698 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2699 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2703 if (rtx_equal_p (operands[0], operands[2]))
2704 return \"fprsub%.d %y1,%0\";
2705 if (rtx_equal_p (operands[0], operands[1]))
2706 return \"fpsub%.d %y2,%0\";
2707 if (which_alternative == 0)
2708 return \"fpsub3%.d %w2,%w1,%0\";
2709 return \"fpsub3%.d %x2,%x1,%0\";
2713 [(set (match_operand:DF 0 "general_operand" "=f")
2714 (minus:DF (match_operand:DF 1 "general_operand" "0")
2715 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2720 [(set (match_operand:DF 0 "general_operand" "=f")
2721 (minus:DF (match_operand:DF 1 "general_operand" "0")
2722 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2727 [(set (match_operand:DF 0 "general_operand" "=f")
2728 (minus:DF (match_operand:DF 1 "general_operand" "0")
2729 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2734 [(set (match_operand:DF 0 "general_operand" "=f")
2735 (minus:DF (match_operand:DF 1 "general_operand" "0")
2736 (match_operand:DF 2 "general_operand" "fmG")))]
2740 if (REG_P (operands[2]))
2741 return \"f%&sub%.x %2,%0\";
2742 return \"f%&sub%.d %f2,%0\";
2745 (define_expand "subsf3"
2746 [(set (match_operand:SF 0 "general_operand" "")
2747 (minus:SF (match_operand:SF 1 "general_operand" "")
2748 (match_operand:SF 2 "general_operand" "")))]
2749 "TARGET_68881 || TARGET_FPA"
2753 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2754 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2755 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2759 if (rtx_equal_p (operands[0], operands[2]))
2760 return \"fprsub%.s %w1,%0\";
2761 if (rtx_equal_p (operands[0], operands[1]))
2762 return \"fpsub%.s %w2,%0\";
2763 if (which_alternative == 0)
2764 return \"fpsub3%.s %w2,%w1,%0\";
2765 return \"fpsub3%.s %2,%1,%0\";
2769 [(set (match_operand:SF 0 "general_operand" "=f")
2770 (minus:SF (match_operand:SF 1 "general_operand" "0")
2771 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2776 [(set (match_operand:SF 0 "general_operand" "=f")
2777 (minus:SF (match_operand:SF 1 "general_operand" "0")
2778 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2783 [(set (match_operand:SF 0 "general_operand" "=f")
2784 (minus:SF (match_operand:SF 1 "general_operand" "0")
2785 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2790 [(set (match_operand:SF 0 "general_operand" "=f")
2791 (minus:SF (match_operand:SF 1 "general_operand" "0")
2792 (match_operand:SF 2 "general_operand" "fdmF")))]
2796 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2797 return \"f%$sub%.x %2,%0\";
2798 return \"f%$sub%.s %f2,%0\";
2801 ;; multiply instructions
2803 (define_insn "mulhi3"
2804 [(set (match_operand:HI 0 "general_operand" "=d")
2805 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2806 (match_operand:HI 2 "general_operand" "dmn")))]
2810 #if defined(MOTOROLA) && !defined(CRDS)
2811 return \"muls%.w %2,%0\";
2813 return \"muls %2,%0\";
2817 (define_insn "mulhisi3"
2818 [(set (match_operand:SI 0 "general_operand" "=d")
2819 (mult:SI (sign_extend:SI
2820 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2822 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2826 #if defined(MOTOROLA) && !defined(CRDS)
2827 return \"muls%.w %2,%0\";
2829 return \"muls %2,%0\";
2834 [(set (match_operand:SI 0 "general_operand" "=d")
2835 (mult:SI (sign_extend:SI
2836 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2837 (match_operand:SI 2 "const_int_operand" "n")))]
2838 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2841 #if defined(MOTOROLA) && !defined(CRDS)
2842 return \"muls%.w %2,%0\";
2844 return \"muls %2,%0\";
2848 (define_expand "mulsi3"
2849 [(set (match_operand:SI 0 "general_operand" "")
2850 (mult:SI (match_operand:SI 1 "general_operand" "")
2851 (match_operand:SI 2 "general_operand" "")))]
2852 "TARGET_68020 || TARGET_5200"
2856 [(set (match_operand:SI 0 "general_operand" "=d")
2857 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2858 (match_operand:SI 2 "general_operand" "dmsK")))]
2863 [(set (match_operand:SI 0 "general_operand" "=d")
2864 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2865 (match_operand:SI 2 "general_operand" "d<Q>")))]
2869 (define_insn "umulhisi3"
2870 [(set (match_operand:SI 0 "general_operand" "=d")
2871 (mult:SI (zero_extend:SI
2872 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2874 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2878 #if defined(MOTOROLA) && !defined(CRDS)
2879 return \"mulu%.w %2,%0\";
2881 return \"mulu %2,%0\";
2886 [(set (match_operand:SI 0 "general_operand" "=d")
2887 (mult:SI (zero_extend:SI
2888 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2889 (match_operand:SI 2 "const_int_operand" "n")))]
2890 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2893 #if defined(MOTOROLA) && !defined(CRDS)
2894 return \"mulu%.w %2,%0\";
2896 return \"mulu %2,%0\";
2900 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2901 ;; proper matching constraint. This is because the matching is between
2902 ;; the high-numbered word of the DImode operand[0] and operand[1].
2903 (define_expand "umulsidi3"
2905 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2906 (mult:SI (match_operand:SI 1 "register_operand" "")
2907 (match_operand:SI 2 "nonimmediate_operand" "")))
2908 (set (subreg:SI (match_dup 0) 0)
2909 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2910 (zero_extend:DI (match_dup 2)))
2911 (const_int 32))))])]
2912 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2916 [(set (match_operand:SI 0 "register_operand" "=d")
2917 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2918 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2919 (set (match_operand:SI 3 "register_operand" "=d")
2920 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2921 (zero_extend:DI (match_dup 2)))
2923 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2926 ; Match immediate case. For 2.4 only match things < 2^31.
2927 ; It's tricky with larger values in these patterns since we need to match
2928 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2931 [(set (match_operand:SI 0 "register_operand" "=d")
2932 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2933 (match_operand:SI 2 "const_int_operand" "n")))
2934 (set (match_operand:SI 3 "register_operand" "=d")
2935 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2938 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2939 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2942 (define_expand "mulsidi3"
2944 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2945 (mult:SI (match_operand:SI 1 "register_operand" "")
2946 (match_operand:SI 2 "nonimmediate_operand" "")))
2947 (set (subreg:SI (match_dup 0) 0)
2948 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2949 (sign_extend:DI (match_dup 2)))
2950 (const_int 32))))])]
2951 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2955 [(set (match_operand:SI 0 "register_operand" "=d")
2956 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2957 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2958 (set (match_operand:SI 3 "register_operand" "=d")
2959 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2960 (sign_extend:DI (match_dup 2)))
2962 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2966 [(set (match_operand:SI 0 "register_operand" "=d")
2967 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2968 (match_operand:SI 2 "const_sint32_operand" "")))
2969 (set (match_operand:SI 3 "register_operand" "=d")
2970 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2973 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2976 (define_expand "umulsi3_highpart"
2978 [(set (match_operand:SI 0 "register_operand" "")
2981 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2982 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2984 (clobber (match_dup 3))])]
2985 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2988 operands[3] = gen_reg_rtx (SImode);
2989 if (GET_CODE (operands[2]) == CONST_INT
2990 || GET_CODE (operands[2]) == CONST_DOUBLE)
2992 if (! const_uint32_operand (operands[2], VOIDmode))
2994 /* We have to adjust the operand order for the matching constraints. */
2995 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2996 operands[1], operands[2]));
3002 [(set (match_operand:SI 0 "register_operand" "=d")
3005 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3006 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3008 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3009 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3012 (define_insn "const_umulsi3_highpart"
3013 [(set (match_operand:SI 0 "register_operand" "=d")
3016 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3017 (match_operand 3 "const_uint32_operand" ""))
3019 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3020 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3023 (define_expand "smulsi3_highpart"
3025 [(set (match_operand:SI 0 "register_operand" "")
3028 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3029 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3031 (clobber (match_dup 3))])]
3032 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3035 operands[3] = gen_reg_rtx (SImode);
3036 if (GET_CODE (operands[2]) == CONST_INT
3037 || GET_CODE (operands[2]) == CONST_DOUBLE)
3039 if (! const_sint32_operand (operands[2], VOIDmode))
3041 /* We have to adjust the operand order for the matching constraints. */
3042 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3043 operands[1], operands[2]));
3049 [(set (match_operand:SI 0 "register_operand" "=d")
3052 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3053 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3055 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3056 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3059 (define_insn "const_smulsi3_highpart"
3060 [(set (match_operand:SI 0 "register_operand" "=d")
3063 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3064 (match_operand 3 "const_sint32_operand" ""))
3066 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3067 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3070 (define_expand "muldf3"
3071 [(set (match_operand:DF 0 "general_operand" "")
3072 (mult:DF (match_operand:DF 1 "general_operand" "")
3073 (match_operand:DF 2 "general_operand" "")))]
3074 "TARGET_68881 || TARGET_FPA"
3078 [(set (match_operand:DF 0 "general_operand" "=x,y")
3079 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3080 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3084 if (rtx_equal_p (operands[1], operands[2]))
3085 return \"fpsqr%.d %y1,%0\";
3086 if (rtx_equal_p (operands[0], operands[1]))
3087 return \"fpmul%.d %y2,%0\";
3088 if (rtx_equal_p (operands[0], operands[2]))
3089 return \"fpmul%.d %y1,%0\";
3090 if (which_alternative == 0)
3091 return \"fpmul3%.d %w2,%w1,%0\";
3092 return \"fpmul3%.d %x2,%x1,%0\";
3096 [(set (match_operand:DF 0 "general_operand" "=f")
3097 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3098 (match_operand:DF 1 "general_operand" "0")))]
3103 [(set (match_operand:DF 0 "general_operand" "=f")
3104 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3105 (match_operand:DF 1 "general_operand" "0")))]
3110 [(set (match_operand:DF 0 "general_operand" "=f")
3111 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3112 (match_operand:DF 1 "general_operand" "0")))]
3117 [(set (match_operand:DF 0 "general_operand" "=f")
3118 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3119 (match_operand:DF 2 "general_operand" "fmG")))]
3123 if (GET_CODE (operands[2]) == CONST_DOUBLE
3124 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3126 int i = floating_exact_log2 (operands[2]);
3127 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3128 return \"fscale%.l %2,%0\";
3130 if (REG_P (operands[2]))
3131 return \"f%&mul%.x %2,%0\";
3132 return \"f%&mul%.d %f2,%0\";
3135 (define_expand "mulsf3"
3136 [(set (match_operand:SF 0 "general_operand" "")
3137 (mult:SF (match_operand:SF 1 "general_operand" "")
3138 (match_operand:SF 2 "general_operand" "")))]
3139 "TARGET_68881 || TARGET_FPA"
3143 [(set (match_operand:SF 0 "general_operand" "=x,y")
3144 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3145 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3149 if (rtx_equal_p (operands[1], operands[2]))
3150 return \"fpsqr%.s %w1,%0\";
3151 if (rtx_equal_p (operands[0], operands[1]))
3152 return \"fpmul%.s %w2,%0\";
3153 if (rtx_equal_p (operands[0], operands[2]))
3154 return \"fpmul%.s %w1,%0\";
3155 if (which_alternative == 0)
3156 return \"fpmul3%.s %w2,%w1,%0\";
3157 return \"fpmul3%.s %2,%1,%0\";
3161 [(set (match_operand:SF 0 "general_operand" "=f")
3162 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3163 (match_operand:SF 1 "general_operand" "0")))]
3167 return (TARGET_68040_ONLY
3168 ? \"fsmul%.l %2,%0\"
3169 : \"fsglmul%.l %2,%0\");
3173 [(set (match_operand:SF 0 "general_operand" "=f")
3174 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3175 (match_operand:SF 1 "general_operand" "0")))]
3179 return (TARGET_68040_ONLY
3180 ? \"fsmul%.w %2,%0\"
3181 : \"fsglmul%.w %2,%0\");
3185 [(set (match_operand:SF 0 "general_operand" "=f")
3186 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3187 (match_operand:SF 1 "general_operand" "0")))]
3191 return (TARGET_68040_ONLY
3192 ? \"fsmul%.b %2,%0\"
3193 : \"fsglmul%.b %2,%0\");
3197 [(set (match_operand:SF 0 "general_operand" "=f")
3198 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3199 (match_operand:SF 2 "general_operand" "fdmF")))]
3203 #ifdef FSGLMUL_USE_S
3204 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3205 return (TARGET_68040_ONLY
3206 ? \"fsmul%.s %2,%0\"
3207 : \"fsglmul%.s %2,%0\");
3209 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3210 return (TARGET_68040_ONLY
3211 ? \"fsmul%.x %2,%0\"
3212 : \"fsglmul%.x %2,%0\");
3214 return (TARGET_68040_ONLY
3215 ? \"fsmul%.s %f2,%0\"
3216 : \"fsglmul%.s %f2,%0\");
3219 ;; divide instructions
3221 (define_expand "divdf3"
3222 [(set (match_operand:DF 0 "general_operand" "")
3223 (div:DF (match_operand:DF 1 "general_operand" "")
3224 (match_operand:DF 2 "general_operand" "")))]
3225 "TARGET_68881 || TARGET_FPA"
3229 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3230 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3231 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3235 if (rtx_equal_p (operands[0], operands[2]))
3236 return \"fprdiv%.d %y1,%0\";
3237 if (rtx_equal_p (operands[0], operands[1]))
3238 return \"fpdiv%.d %y2,%0\";
3239 if (which_alternative == 0)
3240 return \"fpdiv3%.d %w2,%w1,%0\";
3241 return \"fpdiv3%.d %x2,%x1,%x0\";
3245 [(set (match_operand:DF 0 "general_operand" "=f")
3246 (div:DF (match_operand:DF 1 "general_operand" "0")
3247 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3252 [(set (match_operand:DF 0 "general_operand" "=f")
3253 (div:DF (match_operand:DF 1 "general_operand" "0")
3254 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3259 [(set (match_operand:DF 0 "general_operand" "=f")
3260 (div:DF (match_operand:DF 1 "general_operand" "0")
3261 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3266 [(set (match_operand:DF 0 "general_operand" "=f")
3267 (div:DF (match_operand:DF 1 "general_operand" "0")
3268 (match_operand:DF 2 "general_operand" "fmG")))]
3272 if (REG_P (operands[2]))
3273 return \"f%&div%.x %2,%0\";
3274 return \"f%&div%.d %f2,%0\";
3277 (define_expand "divsf3"
3278 [(set (match_operand:SF 0 "general_operand" "")
3279 (div:SF (match_operand:SF 1 "general_operand" "")
3280 (match_operand:SF 2 "general_operand" "")))]
3281 "TARGET_68881 || TARGET_FPA"
3285 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3286 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3287 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3291 if (rtx_equal_p (operands[0], operands[1]))
3292 return \"fpdiv%.s %w2,%0\";
3293 if (rtx_equal_p (operands[0], operands[2]))
3294 return \"fprdiv%.s %w1,%0\";
3295 if (which_alternative == 0)
3296 return \"fpdiv3%.s %w2,%w1,%0\";
3297 return \"fpdiv3%.s %2,%1,%0\";
3301 [(set (match_operand:SF 0 "general_operand" "=f")
3302 (div:SF (match_operand:SF 1 "general_operand" "0")
3303 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3307 return (TARGET_68040_ONLY
3308 ? \"fsdiv%.l %2,%0\"
3309 : \"fsgldiv%.l %2,%0\");
3313 [(set (match_operand:SF 0 "general_operand" "=f")
3314 (div:SF (match_operand:SF 1 "general_operand" "0")
3315 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3319 return (TARGET_68040_ONLY
3320 ? \"fsdiv%.w %2,%0\"
3321 : \"fsgldiv%.w %2,%0\");
3325 [(set (match_operand:SF 0 "general_operand" "=f")
3326 (div:SF (match_operand:SF 1 "general_operand" "0")
3327 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3331 return (TARGET_68040_ONLY
3332 ? \"fsdiv%.b %2,%0\"
3333 : \"fsgldiv%.b %2,%0\");
3337 [(set (match_operand:SF 0 "general_operand" "=f")
3338 (div:SF (match_operand:SF 1 "general_operand" "0")
3339 (match_operand:SF 2 "general_operand" "fdmF")))]
3343 #ifdef FSGLDIV_USE_S
3344 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3345 return (TARGET_68040_ONLY
3346 ? \"fsdiv%.s %2,%0\"
3347 : \"fsgldiv%.s %2,%0\");
3349 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3350 return (TARGET_68040_ONLY
3351 ? \"fsdiv%.x %2,%0\"
3352 : \"fsgldiv%.x %2,%0\");
3354 return (TARGET_68040_ONLY
3355 ? \"fsdiv%.s %f2,%0\"
3356 : \"fsgldiv%.s %f2,%0\");
3359 ;; Remainder instructions.
3361 (define_insn "divmodsi4"
3362 [(set (match_operand:SI 0 "general_operand" "=d")
3363 (div:SI (match_operand:SI 1 "general_operand" "0")
3364 (match_operand:SI 2 "general_operand" "dmsK")))
3365 (set (match_operand:SI 3 "general_operand" "=d")
3366 (mod:SI (match_dup 1) (match_dup 2)))]
3367 "TARGET_68020 && !TARGET_5200"
3370 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3371 return \"divs%.l %2,%0\";
3373 return \"divsl%.l %2,%3:%0\";
3376 (define_insn "udivmodsi4"
3377 [(set (match_operand:SI 0 "general_operand" "=d")
3378 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3379 (match_operand:SI 2 "general_operand" "dmsK")))
3380 (set (match_operand:SI 3 "general_operand" "=d")
3381 (umod:SI (match_dup 1) (match_dup 2)))]
3382 "TARGET_68020 && !TARGET_5200"
3385 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3386 return \"divu%.l %2,%0\";
3388 return \"divul%.l %2,%3:%0\";
3391 (define_insn "divmodhi4"
3392 [(set (match_operand:HI 0 "general_operand" "=d")
3393 (div:HI (match_operand:HI 1 "general_operand" "0")
3394 (match_operand:HI 2 "general_operand" "dmsK")))
3395 (set (match_operand:HI 3 "general_operand" "=d")
3396 (mod:HI (match_dup 1) (match_dup 2)))]
3401 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3403 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3405 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3408 return \"move%.l %0,%3\;swap %3\";
3414 (define_insn "udivmodhi4"
3415 [(set (match_operand:HI 0 "general_operand" "=d")
3416 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3417 (match_operand:HI 2 "general_operand" "dmsK")))
3418 (set (match_operand:HI 3 "general_operand" "=d")
3419 (umod:HI (match_dup 1) (match_dup 2)))]
3424 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3426 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3428 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3431 return \"move%.l %0,%3\;swap %3\";
3437 ;; logical-and instructions
3439 ;; "anddi3" is mainly here to help combine().
3440 (define_insn "anddi3"
3441 [(set (match_operand:DI 0 "general_operand" "=o,d")
3442 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3443 (match_operand:DI 2 "general_operand" "dn,don")))]
3448 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3449 if (GET_CODE (operands[2]) == CONST_DOUBLE
3450 || GET_CODE (operands[2]) == CONST_INT)
3454 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3456 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3457 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3462 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3464 switch (INTVAL (hi))
3467 output_asm_insn (\"clr%.l %0\", operands);
3475 xoperands[0] = operands[0];
3477 output_asm_insn (output_andsi3 (xoperands), xoperands);
3480 if (GET_CODE (operands[0]) == REG)
3481 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3483 operands[0] = adj_offsettable_operand (operands[0], 4);
3484 switch (INTVAL (lo))
3487 output_asm_insn (\"clr%.l %0\", operands);
3495 xoperands[0] = operands[0];
3497 output_asm_insn (output_andsi3 (xoperands), xoperands);
3502 if (GET_CODE (operands[0]) != REG)
3504 operands[1] = adj_offsettable_operand (operands[0], 4);
3505 return \"and%.l %2,%0\;and%.l %R2,%1\";
3507 if (GET_CODE (operands[2]) != REG)
3509 operands[1] = adj_offsettable_operand (operands[2], 4);
3510 return \"and%.l %2,%0\;and%.l %1,%R0\";
3512 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3515 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3516 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3517 ;; can't allocate pseudos into it.
3519 (define_expand "andsi3"
3520 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3521 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3522 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3526 (define_insn "andsi3_internal"
3527 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3528 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3529 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3533 return output_andsi3 (operands);
3536 (define_insn "andsi3_5200"
3537 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3538 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3539 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3543 (define_insn "andhi3"
3544 [(set (match_operand:HI 0 "general_operand" "=m,d")
3545 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3546 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3551 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3552 (and:HI (match_dup 0)
3553 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3558 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3559 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3564 (define_insn "andqi3"
3565 [(set (match_operand:QI 0 "general_operand" "=m,d")
3566 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3567 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3572 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3573 (and:QI (match_dup 0)
3574 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3579 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3580 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3585 ;; inclusive-or instructions
3587 ;; "iordi3" is mainly here to help combine().
3588 (define_insn "iordi3"
3589 [(set (match_operand:DI 0 "general_operand" "=o,d")
3590 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3591 (match_operand:DI 2 "general_operand" "dn,don")))]
3596 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3597 if (GET_CODE (operands[2]) == CONST_DOUBLE
3598 || GET_CODE (operands[2]) == CONST_INT)
3602 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3604 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3605 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3610 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3612 switch (INTVAL (hi))
3617 /* FIXME : a scratch register would be welcome here if operand[0]
3618 is not a register */
3619 output_asm_insn (\"move%.l %#-1,%0\", operands);
3625 xoperands[0] = operands[0];
3627 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3630 if (GET_CODE (operands[0]) == REG)
3631 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3633 operands[0] = adj_offsettable_operand (operands[0], 4);
3634 switch (INTVAL (lo))
3639 /* FIXME : a scratch register would be welcome here if operand[0]
3640 is not a register */
3641 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3647 xoperands[0] = operands[0];
3649 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3654 if (GET_CODE (operands[0]) != REG)
3656 operands[1] = adj_offsettable_operand (operands[0], 4);
3657 return \"or%.l %2,%0\;or%.l %R2,%1\";
3659 if (GET_CODE (operands[2]) != REG)
3661 operands[1] = adj_offsettable_operand (operands[2], 4);
3662 return \"or%.l %2,%0\;or%.l %1,%R0\";
3664 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3667 (define_expand "iorsi3"
3668 [(set (match_operand:SI 0 "general_operand" "")
3669 (ior:SI (match_operand:SI 1 "general_operand" "")
3670 (match_operand:SI 2 "general_operand" "")))]
3674 (define_insn "iorsi3_internal"
3675 [(set (match_operand:SI 0 "general_operand" "=m,d")
3676 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3677 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3681 return output_iorsi3 (operands);
3684 (define_insn "iorsi3_5200"
3685 [(set (match_operand:SI 0 "general_operand" "=m,d")
3686 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3687 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3691 (define_insn "iorhi3"
3692 [(set (match_operand:HI 0 "general_operand" "=m,d")
3693 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3694 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3699 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3700 (ior:HI (match_dup 0)
3701 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3706 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3707 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3712 (define_insn "iorqi3"
3713 [(set (match_operand:QI 0 "general_operand" "=m,d")
3714 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3715 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3720 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3721 (ior:QI (match_dup 0)
3722 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3727 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3728 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3733 ;; On all 68k models, this makes faster code in a special case.
3734 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3736 ;; ??? This pattern can not work as written, because it fails if operand 0
3737 ;; and operand 1 are the same register. This can happen for alternative 1.
3738 ;; This will still fail even if an early clobber is added to the output
3739 ;; for alternative 1. This is because reload may satisfy the matching
3740 ;; constraint by forcing the output to use exactly the same register as
3741 ;; operand 2, without noticing that this then causes a conflict with operand 1.
3742 ;; Possible fix: check for operand 0/1 overlap, and emit correct but slower
3743 ;; code. This should be rare if the early clobber is added.
3745 (define_insn "iorsi_zexthi_ashl16"
3746 [(set (match_operand:SI 0 "general_operand" "=&d,d")
3747 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3748 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3754 if (GET_CODE (operands[2]) != REG)
3756 operands[2] = adj_offsettable_operand (operands[2], 2);
3757 output_asm_insn (\"move%.w %2,%0\", operands);
3759 return \"swap %0\;mov%.w %1,%0\";
3763 [(set (match_operand:SI 0 "general_operand" "=o,d")
3764 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3765 (match_operand:SI 2 "general_operand" "0,0")))]
3772 byte_mode = (GET_MODE(operands[1]) == QImode);
3773 if (GET_CODE (operands[0]) == MEM)
3774 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3776 return \"or%.b %1,%0\";
3778 return \"or%.w %1,%0\";
3783 ;; "xordi3" is mainly here to help combine().
3784 (define_insn "xordi3"
3785 [(set (match_operand:DI 0 "general_operand" "=od")
3786 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3787 (match_operand:DI 2 "general_operand" "dn")))]
3792 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3793 if (GET_CODE (operands[2]) == CONST_DOUBLE
3794 || GET_CODE (operands[2]) == CONST_INT)
3798 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3800 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3801 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3806 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3808 switch (INTVAL (hi))
3813 output_asm_insn (\"not%.l %0\", operands);
3816 /* FIXME : a scratch register would be welcome here if
3817 -128 <= INTVAL (hi) < -1 */
3821 xoperands[0] = operands[0];
3823 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3826 if (GET_CODE (operands[0]) == REG)
3827 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3829 operands[0] = adj_offsettable_operand (operands[0], 4);
3830 switch (INTVAL (lo))
3835 output_asm_insn (\"not%.l %0\", operands);
3838 /* FIXME : a scratch register would be welcome here if
3839 -128 <= INTVAL (lo) < -1 */
3841 /* FIXME : this should be merged with xorsi3 */
3845 xoperands[0] = operands[0];
3847 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3852 if (GET_CODE (operands[0]) != REG)
3854 operands[1] = adj_offsettable_operand (operands[0], 4);
3855 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3857 if (GET_CODE (operands[2]) != REG)
3859 operands[1] = adj_offsettable_operand (operands[2], 4);
3860 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3862 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3865 (define_expand "xorsi3"
3866 [(set (match_operand:SI 0 "general_operand" "")
3867 (xor:SI (match_operand:SI 1 "general_operand" "")
3868 (match_operand:SI 2 "general_operand" "")))]
3872 (define_insn "xorsi3_internal"
3873 [(set (match_operand:SI 0 "general_operand" "=do,m")
3874 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3875 (match_operand:SI 2 "general_operand" "di,dKs")))]
3879 return output_xorsi3 (operands);
3882 (define_insn "xorsi3_5200"
3883 [(set (match_operand:SI 0 "general_operand" "=dm,d")
3884 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3885 (match_operand:SI 2 "general_operand" "d,Ks")))]
3889 (define_insn "xorhi3"
3890 [(set (match_operand:HI 0 "general_operand" "=dm")
3891 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3892 (match_operand:HI 2 "general_operand" "dn")))]
3897 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3898 (xor:HI (match_dup 0)
3899 (match_operand:HI 1 "general_operand" "dn")))]
3904 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3905 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3910 (define_insn "xorqi3"
3911 [(set (match_operand:QI 0 "general_operand" "=dm")
3912 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3913 (match_operand:QI 2 "general_operand" "dn")))]
3918 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3919 (xor:QI (match_dup 0)
3920 (match_operand:QI 1 "general_operand" "dn")))]
3925 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3926 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3931 ;; negation instructions
3933 (define_expand "negdi2"
3934 [(set (match_operand:DI 0 "general_operand" "")
3935 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3940 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3942 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3946 (define_insn "negdi2_internal"
3947 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
3948 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3952 if (which_alternative == 0)
3953 return \"neg%.l %0\;negx%.l %0\";
3954 if (GET_CODE (operands[0]) == REG)
3955 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3957 operands[1] = adj_offsettable_operand (operands[0], 4);
3958 if (ADDRESS_REG_P (operands[0]))
3959 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3961 return \"neg%.l %1\;negx%.l %0\";
3964 (define_insn "negdi2_5200"
3965 [(set (match_operand:DI 0 "general_operand" "=d")
3966 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3970 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3971 return \"neg%.l %1\;negx%.l %0\";
3974 (define_expand "negsi2"
3975 [(set (match_operand:SI 0 "general_operand" "")
3976 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3981 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3983 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3987 (define_insn "negsi2_internal"
3988 [(set (match_operand:SI 0 "general_operand" "=dm")
3989 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3993 (define_insn "negsi2_5200"
3994 [(set (match_operand:SI 0 "general_operand" "=d")
3995 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3999 (define_insn "neghi2"
4000 [(set (match_operand:HI 0 "general_operand" "=dm")
4001 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4006 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4007 (neg:HI (match_dup 0)))]
4011 (define_insn "negqi2"
4012 [(set (match_operand:QI 0 "general_operand" "=dm")
4013 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4018 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4019 (neg:QI (match_dup 0)))]
4023 ;; If using software floating point, just flip the sign bit.
4025 (define_expand "negsf2"
4026 [(set (match_operand:SF 0 "general_operand" "")
4027 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4031 if (!TARGET_FPA && !TARGET_68881)
4036 target = operand_subword_force (operands[0], 0, SFmode);
4037 result = expand_binop (SImode, xor_optab,
4038 operand_subword_force (operands[1], 0, SFmode),
4039 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4043 if (result != target)
4044 emit_move_insn (result, target);
4046 /* Make a place for REG_EQUAL. */
4047 emit_move_insn (operands[0], operands[0]);
4053 [(set (match_operand:SF 0 "general_operand" "=x,y")
4054 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4059 [(set (match_operand:SF 0 "general_operand" "=f,d")
4060 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4064 if (DATA_REG_P (operands[0]))
4066 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
4067 return \"bchg %1,%0\";
4069 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4070 return \"f%$neg%.x %1,%0\";
4071 return \"f%$neg%.s %f1,%0\";
4074 (define_expand "negdf2"
4075 [(set (match_operand:DF 0 "general_operand" "")
4076 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4080 if (!TARGET_FPA && !TARGET_68881)
4087 target = operand_subword (operands[0], 0, 1, DFmode);
4088 result = expand_binop (SImode, xor_optab,
4089 operand_subword_force (operands[1], 0, DFmode),
4090 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4094 if (result != target)
4095 emit_move_insn (result, target);
4097 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4098 operand_subword_force (operands[1], 1, DFmode));
4100 insns = get_insns ();
4103 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4109 [(set (match_operand:DF 0 "general_operand" "=x,y")
4110 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4115 [(set (match_operand:DF 0 "general_operand" "=f,d")
4116 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4120 if (DATA_REG_P (operands[0]))
4122 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
4123 return \"bchg %1,%0\";
4125 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4126 return \"f%&neg%.x %1,%0\";
4127 return \"f%&neg%.d %f1,%0\";
4130 ;; Sqrt instruction for the 68881
4132 (define_insn "sqrtsf2"
4133 [(set (match_operand:SF 0 "general_operand" "=f")
4134 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4138 if (FP_REG_P (operands[1]))
4139 return \"f%$sqrt%.x %1,%0\";
4141 return \"f%$sqrt%.s %1,%0\";
4144 (define_insn "sqrtdf2"
4145 [(set (match_operand:DF 0 "general_operand" "=f")
4146 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4150 if (FP_REG_P (operands[1]))
4151 return \"f%&sqrt%.x %1,%0\";
4153 return \"f%&sqrt%.d %1,%0\";
4156 ;; Absolute value instructions
4157 ;; If using software floating point, just zero the sign bit.
4159 (define_expand "abssf2"
4160 [(set (match_operand:SF 0 "general_operand" "")
4161 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4165 if (!TARGET_FPA && !TARGET_68881)
4170 target = operand_subword_force (operands[0], 0, SFmode);
4171 result = expand_binop (SImode, and_optab,
4172 operand_subword_force (operands[1], 0, SFmode),
4173 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4177 if (result != target)
4178 emit_move_insn (result, target);
4180 /* Make a place for REG_EQUAL. */
4181 emit_move_insn (operands[0], operands[0]);
4187 [(set (match_operand:SF 0 "general_operand" "=x,y")
4188 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4193 [(set (match_operand:SF 0 "general_operand" "=f")
4194 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4198 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4199 return \"f%$abs%.x %1,%0\";
4200 return \"f%$abs%.s %f1,%0\";
4203 (define_expand "absdf2"
4204 [(set (match_operand:DF 0 "general_operand" "")
4205 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4209 if (!TARGET_FPA && !TARGET_68881)
4216 target = operand_subword (operands[0], 0, 1, DFmode);
4217 result = expand_binop (SImode, and_optab,
4218 operand_subword_force (operands[1], 0, DFmode),
4219 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4223 if (result != target)
4224 emit_move_insn (result, target);
4226 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4227 operand_subword_force (operands[1], 1, DFmode));
4229 insns = get_insns ();
4232 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4238 [(set (match_operand:DF 0 "general_operand" "=x,y")
4239 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4244 [(set (match_operand:DF 0 "general_operand" "=f")
4245 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4249 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4250 return \"f%&abs%.x %1,%0\";
4251 return \"f%&abs%.d %f1,%0\";
4254 ;; one complement instructions
4256 ;; "one_cmpldi2" is mainly here to help combine().
4257 (define_insn "one_cmpldi2"
4258 [(set (match_operand:DI 0 "general_operand" "=dm")
4259 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4264 if (GET_CODE (operands[0]) == REG)
4265 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4266 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4267 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4268 operands[1] = operands[0];
4270 operands[1] = adj_offsettable_operand (operands[0], 4);
4271 return \"not%.l %1\;not%.l %0\";
4274 (define_expand "one_cmplsi2"
4275 [(set (match_operand:SI 0 "general_operand" "")
4276 (not:SI (match_operand:SI 1 "general_operand" "")))]
4281 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4283 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4287 (define_insn "one_cmplsi2_internal"
4288 [(set (match_operand:SI 0 "general_operand" "=dm")
4289 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4293 (define_insn "one_cmplsi2_5200"
4294 [(set (match_operand:SI 0 "general_operand" "=d")
4295 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4299 (define_insn "one_cmplhi2"
4300 [(set (match_operand:HI 0 "general_operand" "=dm")
4301 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4306 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4307 (not:HI (match_dup 0)))]
4311 (define_insn "one_cmplqi2"
4312 [(set (match_operand:QI 0 "general_operand" "=dm")
4313 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4318 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4319 (not:QI (match_dup 0)))]
4323 ;; arithmetic shift instructions
4324 ;; We don't need the shift memory by 1 bit instruction
4326 (define_insn "ashldi_extsi"
4327 [(set (match_operand:DI 0 "general_operand" "=ro")
4329 (match_operator:DI 2 "extend_operator"
4330 [(match_operand:SI 1 "general_operand" "rm")])
4336 if (GET_CODE (operands[0]) == REG)
4337 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4339 operands[2] = adj_offsettable_operand (operands[0], 4);
4340 if (ADDRESS_REG_P (operands[0]))
4341 return \"move%.l %1,%0\;sub%.l %2,%2\";
4343 return \"move%.l %1,%0\;clr%.l %2\";
4346 (define_insn "ashldi_sexthi"
4347 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4348 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4350 (clobber (match_scratch:SI 2 "=a,X"))]
4355 if (GET_CODE (operands[0]) == MEM)
4357 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4358 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4359 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4360 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4363 operands[3] = adj_offsettable_operand (operands[0], 4);
4364 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4367 else if (DATA_REG_P (operands[0]))
4368 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4370 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4373 (define_insn "ashldi_const32"
4374 [(set (match_operand:DI 0 "general_operand" "=rm")
4375 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4381 if (GET_CODE (operands[1]) == REG)
4382 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4384 operands[3] = adj_offsettable_operand (operands[1], 4);
4385 if (GET_CODE (operands[0]) == REG)
4386 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4387 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4388 return \"clr%.l %0\;move%.l %3,%0\";
4389 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4390 return \"move%.l %3,%0\;clr%.l %0\";
4392 operands[2] = adj_offsettable_operand (operands[0], 4);
4393 if (ADDRESS_REG_P (operands[2]))
4394 return \"move%.l %3,%0\;sub%.l %2,%2\";
4396 return \"move%.l %3,%0\;clr%.l %2\";
4399 ;; The predicate below must be general_operand, because ashldi3 allows that
4400 (define_insn "ashldi_const"
4401 [(set (match_operand:DI 0 "general_operand" "=d")
4402 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4403 (match_operand 2 "const_int_operand" "n")))]
4404 "(INTVAL (operands[2]) == 1
4405 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4406 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4409 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4410 if (INTVAL (operands[2]) == 1)
4411 return \"add%.l %1,%1\;addx%.l %0,%0\";
4412 else if (INTVAL (operands[2]) == 8)
4413 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4414 else if (INTVAL (operands[2]) == 16)
4415 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4416 else if (INTVAL (operands[2]) == 2)
4417 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4418 else/* if (INTVAL (operands[2]) == 3)*/
4419 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4422 (define_expand "ashldi3"
4423 [(set (match_operand:DI 0 "general_operand" "")
4424 (ashift:DI (match_operand:DI 1 "general_operand" "")
4425 (match_operand 2 "const_int_operand" "")))]
4429 if (GET_CODE (operands[2]) != CONST_INT
4430 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4431 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4432 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4436 ;; On most 68k models, this makes faster code in a special case.
4438 (define_insn "ashlsi_16"
4439 [(set (match_operand:SI 0 "register_operand" "=d")
4440 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4446 return \"swap %0\;clr%.w %0\";
4449 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4450 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4452 ;; On the 68000, this makes faster code in a special case.
4454 (define_insn "ashlsi_17_24"
4455 [(set (match_operand:SI 0 "register_operand" "=d")
4456 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4457 (match_operand:SI 2 "const_int_operand" "n")))]
4458 "(! TARGET_68020 && !TARGET_5200
4459 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4464 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4465 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4468 (define_insn "ashlsi3"
4469 [(set (match_operand:SI 0 "register_operand" "=d")
4470 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4471 (match_operand:SI 2 "general_operand" "dI")))]
4475 if (operands[2] == const1_rtx)
4477 cc_status.flags = CC_NO_OVERFLOW;
4478 return \"add%.l %0,%0\";
4480 return \"lsl%.l %2,%0\";
4483 (define_insn "ashlhi3"
4484 [(set (match_operand:HI 0 "register_operand" "=d")
4485 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4486 (match_operand:HI 2 "general_operand" "dI")))]
4491 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4492 (ashift:HI (match_dup 0)
4493 (match_operand:HI 1 "general_operand" "dI")))]
4497 (define_insn "ashlqi3"
4498 [(set (match_operand:QI 0 "register_operand" "=d")
4499 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4500 (match_operand:QI 2 "general_operand" "dI")))]
4505 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4506 (ashift:QI (match_dup 0)
4507 (match_operand:QI 1 "general_operand" "dI")))]
4511 ;; On most 68k models, this makes faster code in a special case.
4513 (define_insn "ashrsi_16"
4514 [(set (match_operand:SI 0 "register_operand" "=d")
4515 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4518 "swap %0\;ext%.l %0")
4520 ;; On the 68000, this makes faster code in a special case.
4523 [(set (match_operand:SI 0 "register_operand" "=d")
4524 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4525 (match_operand:SI 2 "const_int_operand" "n")))]
4526 "(! TARGET_68020 && !TARGET_5200
4527 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4530 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4531 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4534 (define_insn "subreghi1ashrdi_const32"
4535 [(set (match_operand:HI 0 "general_operand" "=rm")
4536 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4537 (const_int 32)) 1))]
4541 if (GET_CODE (operands[1]) != REG)
4542 operands[1] = adj_offsettable_operand (operands[1], 2);
4543 return \"move%.w %1,%0\";
4546 (define_insn "subregsi1ashrdi_const32"
4547 [(set (match_operand:SI 0 "general_operand" "=rm")
4548 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4549 (const_int 32)) 1))]
4553 return \"move%.l %1,%0\";
4556 (define_insn "ashrdi_const32"
4557 [(set (match_operand:DI 0 "register_operand" "=d")
4558 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4564 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4566 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4568 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4571 (define_insn "ashrdi_const32_mem"
4572 [(set (match_operand:DI 0 "general_operand" "=o,<")
4573 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4575 (clobber (match_scratch:SI 2 "=d,d"))]
4580 if (which_alternative == 1)
4581 operands[3] = operands[0];
4583 operands[3] = adj_offsettable_operand (operands[0], 4);
4585 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4587 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4590 ;; The predicate below must be general_operand, because ashrdi3 allows that
4591 (define_insn "ashrdi_const"
4592 [(set (match_operand:DI 0 "general_operand" "=d")
4593 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4594 (match_operand 2 "const_int_operand" "n")))]
4596 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4597 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4598 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31
4599 || INTVAL (operands[2]) == 63))"
4602 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4603 if (INTVAL (operands[2]) == 63)
4604 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4606 if (INTVAL (operands[2]) == 1)
4607 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4608 else if (INTVAL (operands[2]) == 8)
4609 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4610 else if (INTVAL (operands[2]) == 16)
4611 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4612 else if (INTVAL (operands[2]) == 31)
4613 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4614 else if (INTVAL (operands[2]) == 2)
4615 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4616 else/* if (INTVAL (operands[2]) == 3)*/
4617 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4620 (define_expand "ashrdi3"
4621 [(set (match_operand:DI 0 "general_operand" "")
4622 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4623 (match_operand 2 "const_int_operand" "")))]
4627 if (GET_CODE (operands[2]) != CONST_INT
4628 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4629 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4630 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 31
4631 && INTVAL (operands[2]) != 32 && INTVAL (operands[2]) != 63))
4635 ;; On all 68k models, this makes faster code in a special case.
4637 (define_insn "ashrsi_31"
4638 [(set (match_operand:SI 0 "register_operand" "=d")
4639 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4644 return \"add%.l %0,%0\;subx%.l %0,%0\";
4647 (define_insn "ashrsi3"
4648 [(set (match_operand:SI 0 "register_operand" "=d")
4649 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4650 (match_operand:SI 2 "general_operand" "dI")))]
4654 (define_insn "ashrhi3"
4655 [(set (match_operand:HI 0 "register_operand" "=d")
4656 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4657 (match_operand:HI 2 "general_operand" "dI")))]
4662 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4663 (ashiftrt:HI (match_dup 0)
4664 (match_operand:HI 1 "general_operand" "dI")))]
4668 (define_insn "ashrqi3"
4669 [(set (match_operand:QI 0 "register_operand" "=d")
4670 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4671 (match_operand:QI 2 "general_operand" "dI")))]
4676 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4677 (ashiftrt:QI (match_dup 0)
4678 (match_operand:QI 1 "general_operand" "dI")))]
4682 ;; logical shift instructions
4684 ;; commented out because of reload problems in 950612-1.c
4687 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4688 ;; (const_int 32)) 1))
4689 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4690 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4691 ;; (const_int 32)) 1))]
4695 ;; return \"move%.l %0,%1\";
4700 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4701 ;; (const_int 32)) 0))
4702 ;; (set (match_operand:DI 1 "general_operand" "=do")
4703 ;; (lshiftrt:DI (match_dup 0)
4704 ;; (const_int 32)))]
4708 ;; if (GET_CODE (operands[1]) == REG)
4709 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4711 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4712 ;; return \"move%.l %0,%2\;clr%.l %1\";
4715 (define_insn "subreg1lshrdi_const32"
4716 [(set (match_operand:SI 0 "general_operand" "=rm")
4717 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4718 (const_int 32)) 1))]
4722 return \"move%.l %1,%0\";
4725 (define_insn "lshrdi_const32"
4726 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4727 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4733 if (which_alternative == 1)
4734 return \"move%.l %1,%0\;clr%.l %0\";
4735 if (which_alternative == 2)
4736 return \"clr%.l %0\;move%.l %1,%0\";
4737 if (GET_CODE (operands[0]) == REG)
4738 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4740 operands[2] = adj_offsettable_operand (operands[0], 4);
4741 if (GET_CODE (operands[1]) == REG)
4742 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4744 operands[3] = adj_offsettable_operand (operands[1], 4);
4745 if (ADDRESS_REG_P (operands[0]))
4746 return \"move%.l %1,%2\;sub%.l %0,%0\";
4748 return \"move%.l %1,%2\;clr%.l %0\";
4751 ;; The predicate below must be general_operand, because lshrdi3 allows that
4752 (define_insn "lshrdi_const"
4753 [(set (match_operand:DI 0 "general_operand" "=d")
4754 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4755 (match_operand 2 "const_int_operand" "n")))]
4757 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4758 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4759 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4762 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4763 if (INTVAL (operands[2]) == 63)
4764 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4766 if (INTVAL (operands[2]) == 1)
4767 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4768 else if (INTVAL (operands[2]) == 8)
4769 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4770 else if (INTVAL (operands[2]) == 16)
4771 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4772 else if (INTVAL (operands[2]) == 2)
4773 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4774 else /*if (INTVAL (operands[2]) == 3)*/
4775 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4778 (define_expand "lshrdi3"
4779 [(set (match_operand:DI 0 "general_operand" "")
4780 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4781 (match_operand 2 "const_int_operand" "")))]
4785 if (GET_CODE (operands[2]) != CONST_INT
4786 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4787 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4788 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4789 && INTVAL (operands[2]) != 63))
4793 ;; On all 68k models, this makes faster code in a special case.
4795 (define_insn "lshrsi_31"
4796 [(set (match_operand:SI 0 "register_operand" "=d")
4797 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4802 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4805 ;; On most 68k models, this makes faster code in a special case.
4807 (define_insn "lshrsi_16"
4808 [(set (match_operand:SI 0 "register_operand" "=d")
4809 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4815 return \"clr%.w %0\;swap %0\";
4818 ;; On the 68000, this makes faster code in a special case.
4820 (define_insn "lshrsi_17_24"
4821 [(set (match_operand:SI 0 "register_operand" "=d")
4822 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4823 (match_operand:SI 2 "const_int_operand" "n")))]
4824 "(! TARGET_68020 && !TARGET_5200
4825 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4828 /* I think lsr%.w sets the CC properly. */
4829 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4830 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4833 (define_insn "lshrsi3"
4834 [(set (match_operand:SI 0 "register_operand" "=d")
4835 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4836 (match_operand:SI 2 "general_operand" "dI")))]
4840 (define_insn "lshrhi3"
4841 [(set (match_operand:HI 0 "register_operand" "=d")
4842 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4843 (match_operand:HI 2 "general_operand" "dI")))]
4848 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4849 (lshiftrt:HI (match_dup 0)
4850 (match_operand:HI 1 "general_operand" "dI")))]
4854 (define_insn "lshrqi3"
4855 [(set (match_operand:QI 0 "register_operand" "=d")
4856 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4857 (match_operand:QI 2 "general_operand" "dI")))]
4862 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4863 (lshiftrt:QI (match_dup 0)
4864 (match_operand:QI 1 "general_operand" "dI")))]
4868 ;; rotate instructions
4870 (define_insn "rotlsi3"
4871 [(set (match_operand:SI 0 "register_operand" "=d")
4872 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4873 (match_operand:SI 2 "general_operand" "dINO")))]
4877 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4879 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4881 operands[2] = gen_rtx (CONST_INT, VOIDmode, 32 - INTVAL (operands[2]));
4882 return \"ror%.l %2,%0\";
4885 return \"rol%.l %2,%0\";
4888 (define_insn "rotlhi3"
4889 [(set (match_operand:HI 0 "register_operand" "=d")
4890 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4891 (match_operand:HI 2 "general_operand" "dIP")))]
4895 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4897 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
4898 return \"ror%.w %2,%0\";
4901 return \"rol%.w %2,%0\";
4905 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4906 (rotate:HI (match_dup 0)
4907 (match_operand:HI 1 "general_operand" "dIP")))]
4911 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4913 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
4914 return \"ror%.w %2,%0\";
4917 return \"rol%.w %2,%0\";
4920 (define_insn "rotlqi3"
4921 [(set (match_operand:QI 0 "register_operand" "=d")
4922 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4923 (match_operand:QI 2 "general_operand" "dI")))]
4927 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4929 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
4930 return \"ror%.b %2,%0\";
4933 return \"rol%.b %2,%0\";
4937 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4938 (rotate:QI (match_dup 0)
4939 (match_operand:QI 1 "general_operand" "dI")))]
4943 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4945 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
4946 return \"ror%.b %2,%0\";
4949 return \"rol%.b %2,%0\";
4952 (define_insn "rotrsi3"
4953 [(set (match_operand:SI 0 "register_operand" "=d")
4954 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4955 (match_operand:SI 2 "general_operand" "dI")))]
4959 (define_insn "rotrhi3"
4960 [(set (match_operand:HI 0 "register_operand" "=d")
4961 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4962 (match_operand:HI 2 "general_operand" "dI")))]
4967 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4968 (rotatert:HI (match_dup 0)
4969 (match_operand:HI 1 "general_operand" "dI")))]
4973 (define_insn "rotrqi3"
4974 [(set (match_operand:QI 0 "register_operand" "=d")
4975 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4976 (match_operand:QI 2 "general_operand" "dI")))]
4981 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4982 (rotatert:QI (match_dup 0)
4983 (match_operand:QI 1 "general_operand" "dI")))]
4988 ;; Bit set/clear in memory byte.
4990 ;; set bit, bit number is int
4991 (define_insn "bsetmemqi"
4992 [(set (match_operand:QI 0 "memory_operand" "+m")
4993 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4994 (match_operand:SI 1 "general_operand" "d")) 0)
5000 return \"bset %1,%0\";
5003 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5005 [(set (match_operand:QI 0 "memory_operand" "+m")
5006 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5007 (match_operator:SI 2 "extend_operator"
5008 [(match_operand 1 "general_operand" "d")])) 0)
5014 return \"bset %1,%0\";
5017 ;; clear bit, bit number is int
5018 (define_insn "bclrmemqi"
5019 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5021 (minus:SI (const_int 7)
5022 (match_operand:SI 1 "general_operand" "d")))
5028 return \"bclr %1,%0\";
5031 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5033 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5035 (minus:SI (const_int 7)
5036 (match_operator:SI 2 "extend_operator"
5037 [(match_operand 1 "general_operand" "d")])))
5043 return \"bclr %1,%0\";
5046 ;; Special cases of bit-field insns which we should
5047 ;; recognize in preference to the general case.
5048 ;; These handle aligned 8-bit and 16-bit fields,
5049 ;; which can usually be done with move instructions.
5052 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5053 ; alignment of structure members is specified.
5055 ; The move is allowed to be odd byte aligned, because that's still faster
5056 ; than an odd byte aligned bit field instruction.
5059 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5061 (match_operand:SI 2 "const_int_operand" "n"))
5062 (match_operand:SI 3 "general_operand" "rmi"))]
5063 "TARGET_68020 && TARGET_BITFIELD
5064 && (INTVAL (operands[2]) % 8) == 0
5065 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5069 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5071 return \"move%.l %3,%0\";
5075 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5076 (match_operand:SI 1 "const_int_operand" "n")
5077 (match_operand:SI 2 "const_int_operand" "n"))
5078 (match_operand:SI 3 "register_operand" "d"))]
5079 "TARGET_68020 && TARGET_BITFIELD
5080 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5081 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5082 && (GET_CODE (operands[0]) == REG
5083 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5086 if (REG_P (operands[0]))
5088 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5089 return \"bfins %3,%0{%b2:%b1}\";
5093 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5095 if (GET_CODE (operands[3]) == MEM)
5096 operands[3] = adj_offsettable_operand (operands[3],
5097 (32 - INTVAL (operands[1])) / 8);
5098 if (INTVAL (operands[1]) == 8)
5099 return \"move%.b %3,%0\";
5100 return \"move%.w %3,%0\";
5105 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5106 ; alignment of structure members is specified.
5108 ; The move is allowed to be odd byte aligned, because that's still faster
5109 ; than an odd byte aligned bit field instruction.
5112 [(set (match_operand:SI 0 "general_operand" "=rm")
5113 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5115 (match_operand:SI 3 "const_int_operand" "n")))]
5116 "TARGET_68020 && TARGET_BITFIELD
5117 && (INTVAL (operands[3]) % 8) == 0
5118 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5122 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5124 return \"move%.l %1,%0\";
5128 [(set (match_operand:SI 0 "general_operand" "=&d")
5129 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5130 (match_operand:SI 2 "const_int_operand" "n")
5131 (match_operand:SI 3 "const_int_operand" "n")))]
5132 "TARGET_68020 && TARGET_BITFIELD
5133 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5134 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5135 && (GET_CODE (operands[1]) == REG
5136 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5139 cc_status.flags |= CC_NOT_NEGATIVE;
5140 if (REG_P (operands[1]))
5142 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5143 return \"bfextu %1{%b3:%b2},%0\";
5147 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5149 output_asm_insn (\"clr%.l %0\", operands);
5150 if (GET_CODE (operands[0]) == MEM)
5151 operands[0] = adj_offsettable_operand (operands[0],
5152 (32 - INTVAL (operands[1])) / 8);
5153 if (INTVAL (operands[2]) == 8)
5154 return \"move%.b %1,%0\";
5155 return \"move%.w %1,%0\";
5159 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5160 ; alignment of structure members is specified.
5162 ; The move is allowed to be odd byte aligned, because that's still faster
5163 ; than an odd byte aligned bit field instruction.
5166 [(set (match_operand:SI 0 "general_operand" "=rm")
5167 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5169 (match_operand:SI 3 "const_int_operand" "n")))]
5170 "TARGET_68020 && TARGET_BITFIELD
5171 && (INTVAL (operands[3]) % 8) == 0
5172 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5176 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5178 return \"move%.l %1,%0\";
5182 [(set (match_operand:SI 0 "general_operand" "=d")
5183 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5184 (match_operand:SI 2 "const_int_operand" "n")
5185 (match_operand:SI 3 "const_int_operand" "n")))]
5186 "TARGET_68020 && TARGET_BITFIELD
5187 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5188 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5189 && (GET_CODE (operands[1]) == REG
5190 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5193 if (REG_P (operands[1]))
5195 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5196 return \"bfexts %1{%b3:%b2},%0\";
5200 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5202 if (INTVAL (operands[2]) == 8)
5203 return \"move%.b %1,%0\;extb%.l %0\";
5204 return \"move%.w %1,%0\;ext%.l %0\";
5207 ;; Bit field instructions, general cases.
5208 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5209 ;; so that its address is reloaded.
5211 (define_expand "extv"
5212 [(set (match_operand:SI 0 "general_operand" "")
5213 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5214 (match_operand:SI 2 "general_operand" "")
5215 (match_operand:SI 3 "general_operand" "")))]
5216 "TARGET_68020 && TARGET_BITFIELD"
5220 [(set (match_operand:SI 0 "general_operand" "=d")
5221 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5222 (match_operand:SI 2 "general_operand" "di")
5223 (match_operand:SI 3 "general_operand" "di")))]
5224 "TARGET_68020 && TARGET_BITFIELD"
5225 "bfexts %1{%b3:%b2},%0")
5227 (define_expand "extzv"
5228 [(set (match_operand:SI 0 "general_operand" "")
5229 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5230 (match_operand:SI 2 "general_operand" "")
5231 (match_operand:SI 3 "general_operand" "")))]
5232 "TARGET_68020 && TARGET_BITFIELD"
5236 [(set (match_operand:SI 0 "general_operand" "=d,d")
5237 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5238 (match_operand:SI 2 "general_operand" "di,di")
5239 (match_operand:SI 3 "general_operand" "di,di")))]
5240 "TARGET_68020 && TARGET_BITFIELD"
5243 if (GET_CODE (operands[2]) == CONST_INT)
5245 if (INTVAL (operands[2]) != 32)
5246 cc_status.flags |= CC_NOT_NEGATIVE;
5252 return \"bfextu %1{%b3:%b2},%0\";
5256 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5257 (match_operand:SI 1 "general_operand" "di")
5258 (match_operand:SI 2 "general_operand" "di"))
5259 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5260 (match_operand 3 "const_int_operand" "n")))]
5261 "TARGET_68020 && TARGET_BITFIELD
5262 && (INTVAL (operands[3]) == -1
5263 || (GET_CODE (operands[1]) == CONST_INT
5264 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5268 return \"bfchg %0{%b2:%b1}\";
5272 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5273 (match_operand:SI 1 "general_operand" "di")
5274 (match_operand:SI 2 "general_operand" "di"))
5276 "TARGET_68020 && TARGET_BITFIELD"
5280 return \"bfclr %0{%b2:%b1}\";
5284 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5285 (match_operand:SI 1 "general_operand" "di")
5286 (match_operand:SI 2 "general_operand" "di"))
5288 "TARGET_68020 && TARGET_BITFIELD"
5292 return \"bfset %0{%b2:%b1}\";
5295 (define_expand "insv"
5296 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5297 (match_operand:SI 1 "general_operand" "")
5298 (match_operand:SI 2 "general_operand" ""))
5299 (match_operand:SI 3 "register_operand" ""))]
5300 "TARGET_68020 && TARGET_BITFIELD"
5304 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5305 (match_operand:SI 1 "general_operand" "di")
5306 (match_operand:SI 2 "general_operand" "di"))
5307 (match_operand:SI 3 "register_operand" "d"))]
5308 "TARGET_68020 && TARGET_BITFIELD"
5309 "bfins %3,%0{%b2:%b1}")
5311 ;; Now recognize bit field insns that operate on registers
5312 ;; (or at least were intended to do so).
5315 [(set (match_operand:SI 0 "general_operand" "=d")
5316 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5317 (match_operand:SI 2 "general_operand" "di")
5318 (match_operand:SI 3 "general_operand" "di")))]
5319 "TARGET_68020 && TARGET_BITFIELD"
5320 "bfexts %1{%b3:%b2},%0")
5323 [(set (match_operand:SI 0 "general_operand" "=d")
5324 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5325 (match_operand:SI 2 "general_operand" "di")
5326 (match_operand:SI 3 "general_operand" "di")))]
5327 "TARGET_68020 && TARGET_BITFIELD"
5330 if (GET_CODE (operands[2]) == CONST_INT)
5332 if (INTVAL (operands[2]) != 32)
5333 cc_status.flags |= CC_NOT_NEGATIVE;
5339 return \"bfextu %1{%b3:%b2},%0\";
5343 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5344 (match_operand:SI 1 "general_operand" "di")
5345 (match_operand:SI 2 "general_operand" "di"))
5347 "TARGET_68020 && TARGET_BITFIELD"
5351 return \"bfclr %0{%b2:%b1}\";
5355 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5356 (match_operand:SI 1 "general_operand" "di")
5357 (match_operand:SI 2 "general_operand" "di"))
5359 "TARGET_68020 && TARGET_BITFIELD"
5363 return \"bfset %0{%b2:%b1}\";
5367 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5368 (match_operand:SI 1 "general_operand" "di")
5369 (match_operand:SI 2 "general_operand" "di"))
5370 (match_operand:SI 3 "register_operand" "d"))]
5371 "TARGET_68020 && TARGET_BITFIELD"
5375 /* These special cases are now recognized by a specific pattern. */
5376 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5377 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5378 return \"move%.w %3,%0\";
5379 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5380 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5381 return \"move%.b %3,%0\";
5383 return \"bfins %3,%0{%b2:%b1}\";
5386 ;; Special patterns for optimizing bit-field instructions.
5390 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5391 (match_operand:SI 1 "const_int_operand" "n")
5392 (match_operand:SI 2 "general_operand" "di")))]
5393 "TARGET_68020 && TARGET_BITFIELD"
5396 if (operands[1] == const1_rtx
5397 && GET_CODE (operands[2]) == CONST_INT)
5399 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5400 return output_btst (operands,
5401 gen_rtx (CONST_INT, VOIDmode,
5402 width - INTVAL (operands[2])),
5405 /* Pass 1000 as SIGNPOS argument so that btst will
5406 not think we are testing the sign bit for an `and'
5407 and assume that nonzero implies a negative result. */
5409 if (INTVAL (operands[1]) != 32)
5410 cc_status.flags = CC_NOT_NEGATIVE;
5411 return \"bftst %0{%b2:%b1}\";
5415 ;;; now handle the register cases
5418 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5419 (match_operand:SI 1 "const_int_operand" "n")
5420 (match_operand:SI 2 "general_operand" "di")))]
5421 "TARGET_68020 && TARGET_BITFIELD"
5424 if (operands[1] == const1_rtx
5425 && GET_CODE (operands[2]) == CONST_INT)
5427 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5428 return output_btst (operands,
5429 gen_rtx (CONST_INT, VOIDmode,
5430 width - INTVAL (operands[2])),
5433 /* Pass 1000 as SIGNPOS argument so that btst will
5434 not think we are testing the sign bit for an `and'
5435 and assume that nonzero implies a negative result. */
5437 if (INTVAL (operands[1]) != 32)
5438 cc_status.flags = CC_NOT_NEGATIVE;
5439 return \"bftst %0{%b2:%b1}\";
5442 (define_insn "scc0_di"
5443 [(set (match_operand:QI 0 "general_operand" "=dm")
5444 (match_operator 1 "valid_dbcc_comparison_p"
5445 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5449 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5452 (define_insn "scc0_di_5200"
5453 [(set (match_operand:QI 0 "general_operand" "=d")
5454 (match_operator 1 "valid_dbcc_comparison_p"
5455 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5459 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5462 (define_insn "scc_di"
5463 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5464 (match_operator 1 "valid_dbcc_comparison_p"
5465 [(match_operand:DI 2 "general_operand" "ro,r")
5466 (match_operand:DI 3 "general_operand" "r,ro")]))]
5470 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5473 (define_insn "scc_di_5200"
5474 [(set (match_operand:QI 0 "general_operand" "=d,d")
5475 (match_operator 1 "valid_dbcc_comparison_p"
5476 [(match_operand:DI 2 "general_operand" "ro,r")
5477 (match_operand:DI 3 "general_operand" "r,ro")]))]
5481 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5484 (define_expand "seq"
5485 [(set (match_operand:QI 0 "general_operand" "")
5486 (eq:QI (cc0) (const_int 0)))]
5490 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5492 m68k_last_compare_had_fp_operands = 0;
5498 [(set (match_operand:QI 0 "general_operand" "=dm")
5499 (eq:QI (cc0) (const_int 0)))]
5502 cc_status = cc_prev_status;
5503 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5507 [(set (match_operand:QI 0 "general_operand" "=d")
5508 (eq:QI (cc0) (const_int 0)))]
5511 cc_status = cc_prev_status;
5512 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5515 (define_expand "sne"
5516 [(set (match_operand:QI 0 "general_operand" "")
5517 (ne:QI (cc0) (const_int 0)))]
5521 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5523 m68k_last_compare_had_fp_operands = 0;
5529 [(set (match_operand:QI 0 "general_operand" "=dm")
5530 (ne:QI (cc0) (const_int 0)))]
5533 cc_status = cc_prev_status;
5534 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5538 [(set (match_operand:QI 0 "general_operand" "=d")
5539 (ne:QI (cc0) (const_int 0)))]
5542 cc_status = cc_prev_status;
5543 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5546 (define_expand "sgt"
5547 [(set (match_operand:QI 0 "general_operand" "")
5548 (gt:QI (cc0) (const_int 0)))]
5552 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5554 m68k_last_compare_had_fp_operands = 0;
5560 [(set (match_operand:QI 0 "general_operand" "=dm")
5561 (gt:QI (cc0) (const_int 0)))]
5564 cc_status = cc_prev_status;
5565 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5569 [(set (match_operand:QI 0 "general_operand" "=d")
5570 (gt:QI (cc0) (const_int 0)))]
5573 cc_status = cc_prev_status;
5574 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5577 (define_expand "sgtu"
5578 [(set (match_operand:QI 0 "general_operand" "")
5579 (gtu:QI (cc0) (const_int 0)))]
5584 [(set (match_operand:QI 0 "general_operand" "=dm")
5585 (gtu:QI (cc0) (const_int 0)))]
5587 "* cc_status = cc_prev_status;
5588 return \"shi %0\"; ")
5591 [(set (match_operand:QI 0 "general_operand" "=d")
5592 (gtu:QI (cc0) (const_int 0)))]
5594 "* cc_status = cc_prev_status;
5595 return \"shi %0\"; ")
5597 (define_expand "slt"
5598 [(set (match_operand:QI 0 "general_operand" "")
5599 (lt:QI (cc0) (const_int 0)))]
5603 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5605 m68k_last_compare_had_fp_operands = 0;
5611 [(set (match_operand:QI 0 "general_operand" "=dm")
5612 (lt:QI (cc0) (const_int 0)))]
5614 "* cc_status = cc_prev_status;
5615 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5618 [(set (match_operand:QI 0 "general_operand" "=d")
5619 (lt:QI (cc0) (const_int 0)))]
5621 "* cc_status = cc_prev_status;
5622 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5624 (define_expand "sltu"
5625 [(set (match_operand:QI 0 "general_operand" "")
5626 (ltu:QI (cc0) (const_int 0)))]
5631 [(set (match_operand:QI 0 "general_operand" "=dm")
5632 (ltu:QI (cc0) (const_int 0)))]
5634 "* cc_status = cc_prev_status;
5635 return \"scs %0\"; ")
5638 [(set (match_operand:QI 0 "general_operand" "=d")
5639 (ltu:QI (cc0) (const_int 0)))]
5641 "* cc_status = cc_prev_status;
5642 return \"scs %0\"; ")
5644 (define_expand "sge"
5645 [(set (match_operand:QI 0 "general_operand" "")
5646 (ge:QI (cc0) (const_int 0)))]
5650 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5652 m68k_last_compare_had_fp_operands = 0;
5658 [(set (match_operand:QI 0 "general_operand" "=dm")
5659 (ge:QI (cc0) (const_int 0)))]
5661 "* cc_status = cc_prev_status;
5662 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5665 [(set (match_operand:QI 0 "general_operand" "=d")
5666 (ge:QI (cc0) (const_int 0)))]
5668 "* cc_status = cc_prev_status;
5669 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5671 (define_expand "sgeu"
5672 [(set (match_operand:QI 0 "general_operand" "")
5673 (geu:QI (cc0) (const_int 0)))]
5678 [(set (match_operand:QI 0 "general_operand" "=dm")
5679 (geu:QI (cc0) (const_int 0)))]
5681 "* cc_status = cc_prev_status;
5682 return \"scc %0\"; ")
5685 [(set (match_operand:QI 0 "general_operand" "=d")
5686 (geu:QI (cc0) (const_int 0)))]
5688 "* cc_status = cc_prev_status;
5689 return \"scc %0\"; ")
5691 (define_expand "sle"
5692 [(set (match_operand:QI 0 "general_operand" "")
5693 (le:QI (cc0) (const_int 0)))]
5697 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5699 m68k_last_compare_had_fp_operands = 0;
5705 [(set (match_operand:QI 0 "general_operand" "=dm")
5706 (le:QI (cc0) (const_int 0)))]
5709 cc_status = cc_prev_status;
5710 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5714 [(set (match_operand:QI 0 "general_operand" "=d")
5715 (le:QI (cc0) (const_int 0)))]
5718 cc_status = cc_prev_status;
5719 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5722 (define_expand "sleu"
5723 [(set (match_operand:QI 0 "general_operand" "")
5724 (leu:QI (cc0) (const_int 0)))]
5729 [(set (match_operand:QI 0 "general_operand" "=dm")
5730 (leu:QI (cc0) (const_int 0)))]
5732 "* cc_status = cc_prev_status;
5733 return \"sls %0\"; ")
5736 [(set (match_operand:QI 0 "general_operand" "=d")
5737 (leu:QI (cc0) (const_int 0)))]
5739 "* cc_status = cc_prev_status;
5740 return \"sls %0\"; ")
5742 ;; Basic conditional jump instructions.
5744 (define_insn "beq0_di"
5746 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5748 (label_ref (match_operand 1 "" ","))
5750 (clobber (match_scratch:SI 2 "=d,d"))]
5755 if (which_alternative == 1)
5757 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5759 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5761 if ((cc_prev_status.value1
5762 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5763 || (cc_prev_status.value2
5764 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5766 cc_status = cc_prev_status;
5768 return \"jbeq %l1\";
5773 if (GET_CODE (operands[0]) == REG)
5774 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5776 operands[3] = adj_offsettable_operand (operands[0], 4);
5777 if (! ADDRESS_REG_P (operands[0]))
5779 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5781 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5783 operands[4] = gen_label_rtx();
5784 if (TARGET_68020 || TARGET_5200)
5786 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5788 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5792 #ifdef SGS_CMP_ORDER
5793 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5795 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5798 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5800 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5801 CODE_LABEL_NUMBER (operands[4]));
5805 (define_insn "bne0_di"
5807 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5809 (label_ref (match_operand 1 "" ","))
5811 (clobber (match_scratch:SI 2 "=d,X"))]
5815 if ((cc_prev_status.value1
5816 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5817 || (cc_prev_status.value2
5818 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5820 cc_status = cc_prev_status;
5822 return \"jbne %l1\";
5828 if (GET_CODE (operands[0]) == REG)
5829 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5831 operands[3] = adj_offsettable_operand (operands[0], 4);
5832 if (!ADDRESS_REG_P (operands[0]))
5834 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5836 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5838 if (TARGET_68020 || TARGET_5200)
5840 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5842 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5846 #ifdef SGS_CMP_ORDER
5847 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5849 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5852 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5856 (define_insn "bge0_di"
5858 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5860 (label_ref (match_operand 1 "" ""))
5865 if ((cc_prev_status.value1
5866 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5867 || (cc_prev_status.value2
5868 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5870 cc_status = cc_prev_status;
5871 if (cc_status.flags & CC_REVERSED)
5874 return \"jble %l1\";
5882 return \"jbpl %l1\";
5889 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5890 output_asm_insn(\"tst%.l %0\", operands);
5892 /* On an address reg, cmpw may replace cmpl. */
5893 #ifdef SGS_CMP_ORDER
5894 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5896 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5900 return \"jbpl %l1\";
5906 (define_insn "blt0_di"
5908 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5910 (label_ref (match_operand 1 "" ""))
5915 if ((cc_prev_status.value1
5916 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5917 || (cc_prev_status.value2
5918 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5920 cc_status = cc_prev_status;
5921 if (cc_status.flags & CC_REVERSED)
5924 return \"jbgt %l1\";
5932 return \"jbmi %l1\";
5939 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5940 output_asm_insn(\"tst%.l %0\", operands);
5942 /* On an address reg, cmpw may replace cmpl. */
5943 #ifdef SGS_CMP_ORDER
5944 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5946 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5950 return \"jbmi %l1\";
5958 (if_then_else (eq (cc0)
5960 (label_ref (match_operand 0 "" ""))
5966 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5968 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5974 (if_then_else (ne (cc0)
5976 (label_ref (match_operand 0 "" ""))
5982 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5984 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5990 (if_then_else (gt (cc0)
5992 (label_ref (match_operand 0 "" ""))
5997 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5999 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6005 (if_then_else (gtu (cc0)
6007 (label_ref (match_operand 0 "" ""))
6012 return \"jbhi %l0\";
6020 (if_then_else (lt (cc0)
6022 (label_ref (match_operand 0 "" ""))
6027 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6029 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6035 (if_then_else (ltu (cc0)
6037 (label_ref (match_operand 0 "" ""))
6042 return \"jbcs %l0\";
6050 (if_then_else (ge (cc0)
6052 (label_ref (match_operand 0 "" ""))
6057 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6059 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6065 (if_then_else (geu (cc0)
6067 (label_ref (match_operand 0 "" ""))
6072 return \"jbcc %l0\";
6080 (if_then_else (le (cc0)
6082 (label_ref (match_operand 0 "" ""))
6087 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6089 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6095 (if_then_else (leu (cc0)
6097 (label_ref (match_operand 0 "" ""))
6102 return \"jbls %l0\";
6108 ;; Negated conditional jump instructions.
6112 (if_then_else (eq (cc0)
6115 (label_ref (match_operand 0 "" ""))))]
6120 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6122 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6128 (if_then_else (ne (cc0)
6131 (label_ref (match_operand 0 "" ""))))]
6136 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6138 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6144 (if_then_else (gt (cc0)
6147 (label_ref (match_operand 0 "" ""))))]
6151 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6153 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6159 (if_then_else (gtu (cc0)
6162 (label_ref (match_operand 0 "" ""))))]
6166 return \"jbls %l0\";
6174 (if_then_else (lt (cc0)
6177 (label_ref (match_operand 0 "" ""))))]
6181 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6183 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6189 (if_then_else (ltu (cc0)
6192 (label_ref (match_operand 0 "" ""))))]
6196 return \"jbcc %l0\";
6204 (if_then_else (ge (cc0)
6207 (label_ref (match_operand 0 "" ""))))]
6211 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6213 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6219 (if_then_else (geu (cc0)
6222 (label_ref (match_operand 0 "" ""))))]
6226 return \"jbcs %l0\";
6234 (if_then_else (le (cc0)
6237 (label_ref (match_operand 0 "" ""))))]
6241 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6243 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6249 (if_then_else (leu (cc0)
6252 (label_ref (match_operand 0 "" ""))))]
6256 return \"jbhi %l0\";
6262 ;; Unconditional and other jump instructions
6265 (label_ref (match_operand 0 "" "")))]
6269 return \"jbra %l0\";
6275 ;; We support two different ways of handling dispatch tables.
6276 ;; The NeXT uses absolute tables, and other machines use relative.
6277 ;; This define_expand can generate either kind.
6278 (define_expand "tablejump"
6279 [(parallel [(set (pc) (match_operand 0 "" ""))
6280 (use (label_ref (match_operand 1 "" "")))])]
6284 #ifdef CASE_VECTOR_PC_RELATIVE
6285 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
6286 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
6290 ;; Jump to variable address from dispatch table of absolute addresses.
6292 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6293 (use (label_ref (match_operand 1 "" "")))]
6297 return \"jmp (%0)\";
6303 ;; Jump to variable address from dispatch table of relative addresses.
6307 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6308 (use (label_ref (match_operand 1 "" "")))]
6311 #ifdef ASM_RETURN_CASE_JUMP
6312 ASM_RETURN_CASE_JUMP;
6315 #ifdef ASM_OUTPUT_CASE_LABEL
6317 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6319 return \"jmp 6(%%pc,%0.w)\";
6324 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6326 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6327 #endif /* end !CRDS */
6332 return \"jmp 2(pc,%0.w)\";
6334 return \"jmp 2(%%pc,%0.w)\";
6335 #endif /* end !CRDS */
6342 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6344 return \"extl %0\;jmp pc@(2,%0:l)\";
6350 return \"jmp (2,pc,%0.w)\";
6352 return \"jmp pc@(2,%0:w)\";
6359 ;; Decrement-and-branch insns.
6363 (ne (match_operand:HI 0 "general_operand" "+d*g")
6365 (label_ref (match_operand 1 "" ""))
6368 (plus:HI (match_dup 0)
6374 if (DATA_REG_P (operands[0]))
6375 return \"dbra %0,%l1\";
6376 if (GET_CODE (operands[0]) == MEM)
6380 return \"sub%.w %#1,%0\;jbcc %l1\";
6382 return \"subq%.w %#1,%0\;jbcc %l1\";
6384 #else /* not MOTOROLA */
6385 return \"subqw %#1,%0\;jcc %l1\";
6389 #ifdef SGS_CMP_ORDER
6391 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6393 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6395 #else /* not SGS_CMP_ORDER */
6396 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6398 #else /* not MOTOROLA */
6399 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6406 (ne (match_operand:SI 0 "general_operand" "+d*g")
6408 (label_ref (match_operand 1 "" ""))
6411 (plus:SI (match_dup 0)
6419 if (DATA_REG_P (operands[0]))
6420 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6421 if (GET_CODE (operands[0]) == MEM)
6422 return \"sub%.l %#1,%0\;jbcc %l1\";
6424 if (DATA_REG_P (operands[0]))
6425 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6426 if (GET_CODE (operands[0]) == MEM)
6427 return \"subq%.l %#1,%0\;jbcc %l1\";
6428 #endif /* NO_ADDSUB_Q */
6429 #ifdef SGS_CMP_ORDER
6431 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6433 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6435 #else /* not SGS_CMP_ORDER */
6436 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6437 #endif /* not SGS_CMP_ORDER */
6438 #else /* not MOTOROLA */
6439 if (DATA_REG_P (operands[0]))
6440 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6441 if (GET_CODE (operands[0]) == MEM)
6442 return \"subql %#1,%0\;jcc %l1\";
6443 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6444 #endif /* not MOTOROLA */
6447 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6452 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6455 (label_ref (match_operand 1 "" ""))
6458 (plus:HI (match_dup 0)
6460 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6466 if (DATA_REG_P (operands[0]))
6467 return \"dbra %0,%l1\";
6468 if (GET_CODE (operands[0]) == MEM)
6469 return \"sub%.w %#1,%0\;jbcc %l1\";
6471 if (DATA_REG_P (operands[0]))
6472 return \"dbra %0,%l1\";
6473 if (GET_CODE (operands[0]) == MEM)
6474 return \"subq%.w %#1,%0\;jbcc %l1\";
6476 #ifdef SGS_CMP_ORDER
6478 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6480 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6482 #else /* not SGS_CMP_ORDER */
6483 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6484 #endif /* not SGS_CMP_ORDER */
6485 #else /* not MOTOROLA */
6486 if (DATA_REG_P (operands[0]))
6487 return \"dbra %0,%l1\";
6488 if (GET_CODE (operands[0]) == MEM)
6489 return \"subqw %#1,%0\;jcc %l1\";
6490 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6491 #endif /* not MOTOROLA */
6494 (define_expand "decrement_and_branch_until_zero"
6495 [(parallel [(set (pc)
6497 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6500 (label_ref (match_operand 1 "" ""))
6503 (plus:SI (match_dup 0)
6511 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6514 (label_ref (match_operand 1 "" ""))
6517 (plus:SI (match_dup 0)
6519 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6525 if (DATA_REG_P (operands[0]))
6526 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6527 if (GET_CODE (operands[0]) == MEM)
6528 return \"sub%.l %#1,%0\;jbcc %l1\";
6530 if (DATA_REG_P (operands[0]))
6531 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6532 if (GET_CODE (operands[0]) == MEM)
6533 return \"subq%.l %#1,%0\;jbcc %l1\";
6535 #ifdef SGS_CMP_ORDER
6537 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6539 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6541 #else /* not SGS_CMP_ORDER */
6542 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6543 #endif /* not SGS_CMP_ORDER */
6544 #else /* not MOTOROLA */
6545 if (DATA_REG_P (operands[0]))
6546 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6547 if (GET_CODE (operands[0]) == MEM)
6548 return \"subql %#1,%0\;jcc %l1\";
6549 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6550 #endif /* not MOTOROLA */
6554 ;; For PIC calls, in order to be able to support
6555 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6556 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6558 ;; PIC calls are handled by loading the address of the function into a
6559 ;; register (via movsi), then emitting a register indirect call using
6560 ;; the "jsr" function call syntax.
6562 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6563 ;; operand to the jbsr statement to indicate that this call should
6564 ;; go through the PLT (why? because this is the way that Sun does it).
6566 ;; We have different patterns for PIC calls and non-PIC calls. The
6567 ;; different patterns are only used to choose the right syntax.
6569 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6570 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6571 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6572 ;; section at link time. However, all global objects reference are still
6573 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6574 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6575 ;; We need to have a way to differentiate these two different operands.
6577 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6578 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6579 ;; to be changed to recognize function calls symbol_ref operand as a valid
6580 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6581 ;; avoid the compiler to load this symbol_ref operand into a register.
6582 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6583 ;; since the value is a PC relative offset, not a real address.
6585 ;; All global objects are treated in the similar way as in SUN3. The only
6586 ;; difference is: on m68k svr4, the reference of such global object needs
6587 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6588 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6591 ;; Call subroutine with no return value.
6592 (define_expand "call"
6593 [(call (match_operand:QI 0 "memory_operand" "")
6594 (match_operand:SI 1 "general_operand" ""))]
6595 ;; Operand 1 not really used on the m68000.
6600 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6601 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6604 ;; This is a normal call sequence.
6606 [(call (match_operand:QI 0 "memory_operand" "o")
6607 (match_operand:SI 1 "general_operand" "g"))]
6608 ;; Operand 1 not really used on the m68000.
6612 #if defined (MOTOROLA) && !defined (USE_GAS)
6614 if (GET_CODE (operands[0]) == MEM
6615 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6624 ;; This is a PIC call sequence.
6626 [(call (match_operand:QI 0 "memory_operand" "o")
6627 (match_operand:SI 1 "general_operand" "g"))]
6628 ;; Operand 1 not really used on the m68000.
6632 if (GET_CODE (operands[0]) == MEM
6633 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6636 return \"bsr.l %0\";
6639 return \"bsr.l %0@PLTPC\";
6641 return \"bsr %0@PLTPC\";
6645 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6646 GAS just plain ignores it. */
6647 return \"jbsr %0,a1\";
6652 ;; Call subroutine, returning value in operand 0
6653 ;; (which must be a hard register).
6654 ;; See comments before "call" regarding PIC calls.
6655 (define_expand "call_value"
6656 [(set (match_operand 0 "" "")
6657 (call (match_operand:QI 1 "memory_operand" "")
6658 (match_operand:SI 2 "general_operand" "")))]
6659 ;; Operand 2 not really used on the m68000.
6663 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6664 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6667 ;; This is a normal call_value
6669 [(set (match_operand 0 "" "=rf")
6670 (call (match_operand:QI 1 "memory_operand" "o")
6671 (match_operand:SI 2 "general_operand" "g")))]
6672 ;; Operand 2 not really used on the m68000.
6675 #if defined (MOTOROLA) && !defined (USE_GAS)
6677 if (GET_CODE (operands[1]) == MEM
6678 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6687 ;; This is a PIC call_value
6689 [(set (match_operand 0 "" "=rf")
6690 (call (match_operand:QI 1 "memory_operand" "o")
6691 (match_operand:SI 2 "general_operand" "g")))]
6692 ;; Operand 2 not really used on the m68000.
6695 if (GET_CODE (operands[1]) == MEM
6696 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6699 return \"bsr.l %1\";
6702 return \"bsr.l %1@PLTPC\";
6704 return \"bsr %1@PLTPC\";
6708 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6709 GAS just plain ignores it. */
6710 return \"jbsr %1,a1\";
6715 ;; Call subroutine returning any type.
6717 (define_expand "untyped_call"
6718 [(parallel [(call (match_operand 0 "" "")
6720 (match_operand 1 "" "")
6721 (match_operand 2 "" "")])]
6722 "NEEDS_UNTYPED_CALL"
6727 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6729 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6731 rtx set = XVECEXP (operands[2], 0, i);
6732 emit_move_insn (SET_DEST (set), SET_SRC (set));
6735 /* The optimizer does not know that the call sets the function value
6736 registers we stored in the result block. We avoid problems by
6737 claiming that all hard registers are used and clobbered at this
6739 emit_insn (gen_blockage ());
6744 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6745 ;; all of memory. This blocks insns from being moved across this point.
6747 (define_insn "blockage"
6748 [(unspec_volatile [(const_int 0)] 0)]
6757 (define_insn "probe"
6762 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6763 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6764 return \"tstl %a0\";
6767 ;; Used for frameless functions which save no regs and allocate no locals.
6768 (define_insn "return"
6773 if (current_function_pops_args == 0)
6775 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6779 (define_insn "indirect_jump"
6780 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6784 ;; This should not be used unless the add/sub insns can't be.
6787 [(set (match_operand:SI 0 "general_operand" "=a")
6788 (match_operand:QI 1 "address_operand" "p"))]
6793 /* Recognize an insn that refers to a table of offsets. Such an insn will
6794 need to refer to a label on the insn. So output one. Use the
6795 label-number of the table of offsets to generate this label. This code,
6796 and similar code above, assumes that there will be at most one reference
6798 if (GET_CODE (operands[1]) == PLUS
6799 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6800 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6802 rtx labelref = XEXP (operands[1], 1);
6803 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6805 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6806 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6808 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6809 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6810 #endif /* not SGS */
6811 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6812 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6813 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6814 #ifdef SGS_SWITCH_TABLES
6815 /* Set flag saying we need to define the symbol
6816 LD%n (with value L%n-LI%n) at the end of the switch table. */
6817 switch_table_difference_label_flag = 1;
6818 #endif /* SGS_SWITCH_TABLES */
6819 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6821 #endif /* SGS_NO_LI */
6823 return \"lea %a1,%0\";
6826 ;; This is the first machine-dependent peephole optimization.
6827 ;; It is useful when a floating value is returned from a function call
6828 ;; and then is moved into an FP register.
6829 ;; But it is mainly intended to test the support for these optimizations.
6832 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6833 (set (match_operand:DF 0 "register_operand" "=f")
6834 (match_operand:DF 1 "register_operand" "ad"))]
6835 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6839 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6840 output_asm_insn (\"move%.l %1,%@\", xoperands);
6841 output_asm_insn (\"move%.l %1,%-\", operands);
6842 return \"fmove%.d %+,%0\";
6846 ;; Optimize a stack-adjust followed by a push of an argument.
6847 ;; This is said to happen frequently with -msoft-float
6848 ;; when there are consecutive library calls.
6851 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6852 (match_operand:SI 0 "const_int_operand" "n")))
6853 (set (match_operand:SF 1 "push_operand" "=m")
6854 (match_operand:SF 2 "general_operand" "rmfF"))]
6855 "INTVAL (operands[0]) >= 4
6856 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6859 if (INTVAL (operands[0]) > 4)
6862 xoperands[0] = stack_pointer_rtx;
6863 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6865 if (INTVAL (xoperands[1]) <= 8)
6868 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6870 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6872 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6874 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6875 INTVAL (xoperands[1]) - 8);
6876 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6880 if (INTVAL (xoperands[1]) <= 0x7FFF)
6883 output_asm_insn (\"add%.w %1,%0\", xoperands);
6886 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6888 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6892 output_asm_insn (\"add%.l %1,%0\", xoperands);
6894 if (FP_REG_P (operands[2]))
6895 return \"fmove%.s %2,%@\";
6896 return \"move%.l %2,%@\";
6899 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6902 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6903 (match_operand:SI 0 "const_int_operand" "n")))
6904 (set (match_operand:SI 1 "push_operand" "=m")
6905 (match_operand:SI 2 "general_operand" "g"))]
6906 "INTVAL (operands[0]) >= 4
6907 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6910 if (INTVAL (operands[0]) > 4)
6913 xoperands[0] = stack_pointer_rtx;
6914 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6916 if (INTVAL (xoperands[1]) <= 8)
6919 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6921 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6923 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6925 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6926 INTVAL (xoperands[1]) - 8);
6927 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6931 if (INTVAL (xoperands[1]) <= 0x7FFF)
6934 output_asm_insn (\"add%.w %1,%0\", xoperands);
6937 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6939 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6943 output_asm_insn (\"add%.l %1,%0\", xoperands);
6945 if (operands[2] == const0_rtx)
6946 return \"clr%.l %@\";
6947 return \"move%.l %2,%@\";
6950 ;; Speed up pushing a single byte but leaving four bytes of space.
6953 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6954 (match_operand:QI 1 "general_operand" "dami"))
6955 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6956 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6961 if (GET_CODE (operands[1]) == REG)
6962 return \"move%.l %1,%-\";
6964 xoperands[1] = operands[1];
6966 = gen_rtx (MEM, QImode,
6967 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
6968 gen_rtx (CONST_INT, VOIDmode, 3)));
6969 xoperands[3] = stack_pointer_rtx;
6971 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6973 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
6978 [(set (match_operand:SI 0 "register_operand" "=d")
6980 (set (strict_low_part (subreg:HI (match_dup 0) 0))
6981 (match_operand:HI 1 "general_operand" "rmn"))]
6982 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6985 if (GET_CODE (operands[1]) == CONST_INT)
6987 if (operands[1] == const0_rtx
6988 && (DATA_REG_P (operands[0])
6989 || GET_CODE (operands[0]) == MEM)
6990 /* clr insns on 68000 read before writing.
6991 This isn't so on the 68010, but we have no TARGET_68010. */
6992 && ((TARGET_68020 || TARGET_5200)
6993 || !(GET_CODE (operands[0]) == MEM
6994 && MEM_VOLATILE_P (operands[0]))))
6995 return \"clr%.w %0\";
6997 return \"move%.w %1,%0\";
7005 ;; jCC label ; abnormal loop termination
7006 ;; dbra dN, loop ; normal loop termination
7014 ;; Which moves the jCC condition outside the inner loop for free.
7017 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7018 [(cc0) (const_int 0)])
7019 (label_ref (match_operand 2 "" ""))
7024 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7027 (label_ref (match_operand 1 "" ""))
7030 (plus:HI (match_dup 0)
7032 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7036 output_dbcc_and_branch (operands);
7041 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7042 [(cc0) (const_int 0)])
7043 (label_ref (match_operand 2 "" ""))
7048 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7051 (label_ref (match_operand 1 "" ""))
7054 (plus:SI (match_dup 0)
7056 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7060 output_dbcc_and_branch (operands);
7065 ;; FPA multiply and add.
7067 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7068 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7069 (match_operand:DF 2 "general_operand" "xH,y,y"))
7070 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7073 fpma%.d %1,%w2,%w3,%0
7074 fpma%.d %x1,%x2,%x3,%0
7075 fpma%.d %x1,%x2,%x3,%0")
7078 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7079 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7080 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7081 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7084 fpma%.s %1,%w2,%w3,%0
7086 fpma%.s %1,%2,%3,%0")
7088 ;; FPA Multiply and subtract
7090 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7091 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7092 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7093 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7096 fpms%.d %3,%w2,%w1,%0
7097 fpms%.d %x3,%2,%x1,%0
7098 fpms%.d %x3,%2,%x1,%0")
7101 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7102 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7103 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7104 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7107 fpms%.s %3,%w2,%w1,%0
7109 fpms%.s %3,%2,%1,%0")
7112 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7113 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7114 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7115 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7118 fpmr%.d %2,%w1,%w3,%0
7119 fpmr%.d %x2,%1,%x3,%0
7120 fpmr%.d %x2,%1,%x3,%0")
7123 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7124 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7125 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7126 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7129 fpmr%.s %2,%w1,%w3,%0
7130 fpmr%.s %x2,%1,%x3,%0
7131 fpmr%.s %x2,%1,%x3,%0")
7133 ;; FPA Add and multiply
7135 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7136 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7137 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7138 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7141 fpam%.d %2,%w1,%w3,%0
7142 fpam%.d %x2,%1,%x3,%0
7143 fpam%.d %x2,%1,%x3,%0")
7146 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7147 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7148 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7149 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7152 fpam%.s %2,%w1,%w3,%0
7153 fpam%.s %x2,%1,%x3,%0
7154 fpam%.s %x2,%1,%x3,%0")
7156 ;;FPA Subtract and multiply
7158 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7159 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7160 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7161 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7164 fpsm%.d %2,%w1,%w3,%0
7165 fpsm%.d %x2,%1,%x3,%0
7166 fpsm%.d %x2,%1,%x3,%0")
7169 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7170 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7171 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7172 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7175 fpsm%.d %3,%w2,%w1,%0
7176 fpsm%.d %x3,%2,%x1,%0
7177 fpsm%.d %x3,%2,%x1,%0")
7180 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7181 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7182 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7183 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7186 fpsm%.s %2,%w1,%w3,%0
7187 fpsm%.s %x2,%1,%x3,%0
7188 fpsm%.s %x2,%1,%x3,%0")
7191 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7192 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7193 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7194 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7197 fpsm%.s %3,%w2,%w1,%0
7198 fpsm%.s %x3,%2,%x1,%0
7199 fpsm%.s %x3,%2,%x1,%0")
7201 (define_expand "tstxf"
7203 (match_operand:XF 0 "nonimmediate_operand" ""))]
7205 "m68k_last_compare_had_fp_operands = 1;")
7209 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7213 cc_status.flags = CC_IN_68881;
7214 return \"ftst%.x %0\";
7217 (define_expand "cmpxf"
7219 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7220 (match_operand:XF 1 "nonimmediate_operand" "")))]
7222 "m68k_last_compare_had_fp_operands = 1;")
7226 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7227 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7231 cc_status.flags = CC_IN_68881;
7232 #ifdef SGS_CMP_ORDER
7233 if (REG_P (operands[0]))
7235 if (REG_P (operands[1]))
7236 return \"fcmp%.x %0,%1\";
7238 return \"fcmp%.x %0,%f1\";
7240 cc_status.flags |= CC_REVERSED;
7241 return \"fcmp%.x %1,%f0\";
7243 if (REG_P (operands[0]))
7245 if (REG_P (operands[1]))
7246 return \"fcmp%.x %1,%0\";
7248 return \"fcmp%.x %f1,%0\";
7250 cc_status.flags |= CC_REVERSED;
7251 return \"fcmp%.x %f0,%1\";
7255 (define_insn "extendsfxf2"
7256 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7257 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
7261 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7263 if (REGNO (operands[0]) == REGNO (operands[1]))
7265 /* Extending float to double in an fp-reg is a no-op.
7266 NOTICE_UPDATE_CC has already assumed that the
7267 cc will be set. So cancel what it did. */
7268 cc_status = cc_prev_status;
7271 return \"f%$move%.x %1,%0\";
7273 if (FP_REG_P (operands[0]))
7274 return \"f%$move%.s %f1,%0\";
7275 return \"fmove%.x %f1,%0\";
7279 (define_insn "extenddfxf2"
7280 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7282 (match_operand:DF 1 "general_operand" "f,m")))]
7286 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7288 if (REGNO (operands[0]) == REGNO (operands[1]))
7290 /* Extending float to double in an fp-reg is a no-op.
7291 NOTICE_UPDATE_CC has already assumed that the
7292 cc will be set. So cancel what it did. */
7293 cc_status = cc_prev_status;
7296 return \"fmove%.x %1,%0\";
7298 if (FP_REG_P (operands[0]))
7299 return \"f%&move%.d %f1,%0\";
7300 return \"fmove%.x %f1,%0\";
7303 (define_insn "truncxfdf2"
7304 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7306 (match_operand:XF 1 "general_operand" "f,f")))]
7310 if (REG_P (operands[0]))
7312 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7313 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
7314 return \"move%.l %+,%0\";
7316 return \"fmove%.d %f1,%0\";
7319 (define_insn "truncxfsf2"
7320 [(set (match_operand:SF 0 "general_operand" "=dm")
7322 (match_operand:XF 1 "general_operand" "f")))]
7326 (define_insn "floatsixf2"
7327 [(set (match_operand:XF 0 "general_operand" "=f")
7328 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7332 (define_insn "floathixf2"
7333 [(set (match_operand:XF 0 "general_operand" "=f")
7334 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7338 (define_insn "floatqixf2"
7339 [(set (match_operand:XF 0 "general_operand" "=f")
7340 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7344 (define_insn "ftruncxf2"
7345 [(set (match_operand:XF 0 "general_operand" "=f")
7346 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7350 if (FP_REG_P (operands[1]))
7351 return \"fintrz%.x %f1,%0\";
7352 return \"fintrz%.x %f1,%0\";
7355 (define_insn "fixxfqi2"
7356 [(set (match_operand:QI 0 "general_operand" "=dm")
7357 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7361 (define_insn "fixxfhi2"
7362 [(set (match_operand:HI 0 "general_operand" "=dm")
7363 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7367 (define_insn "fixxfsi2"
7368 [(set (match_operand:SI 0 "general_operand" "=dm")
7369 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7374 [(set (match_operand:XF 0 "general_operand" "=f")
7375 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7376 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7381 [(set (match_operand:XF 0 "general_operand" "=f")
7382 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7383 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7388 [(set (match_operand:XF 0 "general_operand" "=f")
7389 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7390 (match_operand:XF 1 "general_operand" "0")))]
7394 (define_insn "addxf3"
7395 [(set (match_operand:XF 0 "general_operand" "=f")
7396 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7397 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7401 if (REG_P (operands[2]))
7402 return \"fadd%.x %2,%0\";
7403 return \"fadd%.x %f2,%0\";
7407 [(set (match_operand:XF 0 "general_operand" "=f")
7408 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7409 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7414 [(set (match_operand:XF 0 "general_operand" "=f")
7415 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7416 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7421 [(set (match_operand:XF 0 "general_operand" "=f")
7422 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7423 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7427 (define_insn "subxf3"
7428 [(set (match_operand:XF 0 "general_operand" "=f")
7429 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7430 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7434 if (REG_P (operands[2]))
7435 return \"fsub%.x %2,%0\";
7436 return \"fsub%.x %f2,%0\";
7440 [(set (match_operand:XF 0 "general_operand" "=f")
7441 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7442 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7447 [(set (match_operand:XF 0 "general_operand" "=f")
7448 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7449 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7454 [(set (match_operand:XF 0 "general_operand" "=f")
7455 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7456 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7460 (define_insn "mulxf3"
7461 [(set (match_operand:XF 0 "general_operand" "=f")
7462 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7463 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7467 if (REG_P (operands[2]))
7468 return \"fmul%.x %2,%0\";
7469 return \"fmul%.x %f2,%0\";
7473 [(set (match_operand:XF 0 "general_operand" "=f")
7474 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7475 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7480 [(set (match_operand:XF 0 "general_operand" "=f")
7481 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7482 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7487 [(set (match_operand:XF 0 "general_operand" "=f")
7488 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7489 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7493 (define_insn "divxf3"
7494 [(set (match_operand:XF 0 "general_operand" "=f")
7495 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7496 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7500 if (REG_P (operands[2]))
7501 return \"fdiv%.x %2,%0\";
7502 return \"fdiv%.x %f2,%0\";
7505 (define_expand "negxf2"
7506 [(set (match_operand:XF 0 "general_operand" "")
7507 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7511 /* ??? There isn't an FPA define_insn so we could handle it here too.
7512 For now we don't (paranoia). */
7520 target = operand_subword (operands[0], 0, 1, XFmode);
7521 result = expand_binop (SImode, xor_optab,
7522 operand_subword_force (operands[1], 0, XFmode),
7523 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7527 if (result != target)
7528 emit_move_insn (result, target);
7530 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7531 operand_subword_force (operands[1], 1, XFmode));
7532 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7533 operand_subword_force (operands[1], 2, XFmode));
7535 insns = get_insns ();
7538 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7543 (define_insn "negxf2_68881"
7544 [(set (match_operand:XF 0 "general_operand" "=f")
7545 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7549 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7550 return \"fneg%.x %1,%0\";
7551 return \"fneg%.x %f1,%0\";
7554 (define_expand "absxf2"
7555 [(set (match_operand:XF 0 "general_operand" "")
7556 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7560 /* ??? There isn't an FPA define_insn so we could handle it here too.
7561 For now we don't (paranoia). */
7569 target = operand_subword (operands[0], 0, 1, XFmode);
7570 result = expand_binop (SImode, and_optab,
7571 operand_subword_force (operands[1], 0, XFmode),
7572 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7576 if (result != target)
7577 emit_move_insn (result, target);
7579 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7580 operand_subword_force (operands[1], 1, XFmode));
7581 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7582 operand_subword_force (operands[1], 2, XFmode));
7584 insns = get_insns ();
7587 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7592 (define_insn "absxf2_68881"
7593 [(set (match_operand:XF 0 "general_operand" "=f")
7594 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7598 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7599 return \"fabs%.x %1,%0\";
7600 return \"fabs%.x %f1,%0\";
7603 (define_insn "sqrtxf2"
7604 [(set (match_operand:XF 0 "general_operand" "=f")
7605 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7609 (define_insn "sinsf2"
7610 [(set (match_operand:SF 0 "general_operand" "=f")
7611 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7612 "TARGET_68881 && flag_fast_math"
7615 if (FP_REG_P (operands[1]))
7616 return \"fsin%.x %1,%0\";
7618 return \"fsin%.s %1,%0\";
7621 (define_insn "sindf2"
7622 [(set (match_operand:DF 0 "general_operand" "=f")
7623 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7624 "TARGET_68881 && flag_fast_math"
7627 if (FP_REG_P (operands[1]))
7628 return \"fsin%.x %1,%0\";
7630 return \"fsin%.d %1,%0\";
7633 (define_insn "sinxf2"
7634 [(set (match_operand:XF 0 "general_operand" "=f")
7635 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7636 "TARGET_68881 && flag_fast_math"
7639 (define_insn "cossf2"
7640 [(set (match_operand:SF 0 "general_operand" "=f")
7641 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7642 "TARGET_68881 && flag_fast_math"
7645 if (FP_REG_P (operands[1]))
7646 return \"fcos%.x %1,%0\";
7648 return \"fcos%.s %1,%0\";
7651 (define_insn "cosdf2"
7652 [(set (match_operand:DF 0 "general_operand" "=f")
7653 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7654 "TARGET_68881 && flag_fast_math"
7657 if (FP_REG_P (operands[1]))
7658 return \"fcos%.x %1,%0\";
7660 return \"fcos%.d %1,%0\";
7663 (define_insn "cosxf2"
7664 [(set (match_operand:XF 0 "general_operand" "=f")
7665 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7666 "TARGET_68881 && flag_fast_math"