1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
753 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
755 (minus:SI (const_int 7)
756 (match_operand:SI 1 "general_operand" "di"))))]
758 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
761 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
763 (minus:SI (const_int 31)
764 (match_operand:SI 1 "general_operand" "di"))))]
766 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
768 ;; The following two patterns are like the previous two
769 ;; except that they use the fact that bit-number operands
770 ;; are automatically masked to 3 or 5 bits.
773 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
775 (minus:SI (const_int 7)
777 (match_operand:SI 1 "register_operand" "d")
780 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
783 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
785 (minus:SI (const_int 31)
787 (match_operand:SI 1 "register_operand" "d")
790 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
792 ;; Nonoffsettable mem refs are ok in this one pattern
793 ;; since we don't try to adjust them.
795 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
797 (match_operand:SI 1 "const_int_operand" "n")))]
798 "(unsigned) INTVAL (operands[1]) < 8"
801 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
802 return output_btst (operands, operands[1], operands[0], insn, 7);
806 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
808 (match_operand:SI 1 "const_int_operand" "n")))]
812 if (GET_CODE (operands[0]) == MEM)
814 operands[0] = adj_offsettable_operand (operands[0],
815 INTVAL (operands[1]) / 8);
816 operands[1] = gen_rtx (CONST_INT, VOIDmode,
817 7 - INTVAL (operands[1]) % 8);
818 return output_btst (operands, operands[1], operands[0], insn, 7);
820 operands[1] = gen_rtx (CONST_INT, VOIDmode,
821 31 - INTVAL (operands[1]));
822 return output_btst (operands, operands[1], operands[0], insn, 31);
828 ;; A special case in which it is not desirable
829 ;; to reload the constant into a data register.
830 (define_insn "pushexthisi_const"
831 [(set (match_operand:SI 0 "push_operand" "=m")
832 (match_operand:SI 1 "const_int_operand" "J"))]
833 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
836 if (operands[1] == const0_rtx)
837 return \"clr%.l %0\";
842 ;(define_insn "swapsi"
843 ; [(set (match_operand:SI 0 "general_operand" "+r")
844 ; (match_operand:SI 1 "general_operand" "+r"))
845 ; (set (match_dup 1) (match_dup 0))]
849 ;; Special case of fullword move when source is zero.
850 ;; The reason this is special is to avoid loading a zero
851 ;; into a data reg with moveq in order to store it elsewhere.
853 (define_insn "movsi_const0"
854 [(set (match_operand:SI 0 "general_operand" "=g")
856 ;; clr insns on 68000 read before writing.
857 ;; This isn't so on the 68010, but we have no TARGET_68010.
858 "((TARGET_68020 || TARGET_5200)
859 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
862 if (ADDRESS_REG_P (operands[0]))
864 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
865 if (!TARGET_68040 && !TARGET_68060)
866 return \"sub%.l %0,%0\";
871 /* Many SGS assemblers croak on size specifiers for constants. */
874 return \"lea 0.w,%0\";
877 return \"lea 0:w,%0\";
881 /* moveq is faster on the 68000. */
882 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
883 #if defined(MOTOROLA) && !defined(CRDS)
884 return \"moveq%.l %#0,%0\";
886 return \"moveq %#0,%0\";
888 return \"clr%.l %0\";
891 ;; General case of fullword move.
893 ;; This is the main "hook" for PIC code. When generating
894 ;; PIC, movsi is responsible for determining when the source address
895 ;; needs PIC relocation and appropriately calling legitimize_pic_address
896 ;; to perform the actual relocation.
898 ;; In both the PIC and non-PIC cases the patterns generated will
899 ;; matched by the next define_insn.
900 (define_expand "movsi"
901 [(set (match_operand:SI 0 "general_operand" "")
902 (match_operand:SI 1 "general_operand" ""))]
906 if (flag_pic && symbolic_operand (operands[1], SImode))
908 /* The source is an address which requires PIC relocation.
909 Call legitimize_pic_address with the source, mode, and a relocation
910 register (a new pseudo, or the final destination if reload_in_progress
911 is set). Then fall through normally */
912 extern rtx legitimize_pic_address();
913 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
914 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
918 ;; General case of fullword move. The register constraints
919 ;; force integer constants in range for a moveq to be reloaded
920 ;; if they are headed for memory.
922 ;; Notes: make sure no alternative allows g vs g.
923 ;; We don't allow f-regs since fixed point cannot go in them.
924 ;; We do allow y and x regs since fixed point is allowed in them.
925 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
926 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
930 if (which_alternative == 3)
931 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
932 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
933 return \"fpmove%.l %x1,%x0\";
934 return output_move_simode (operands);
938 [(set (match_operand:SI 0 "general_operand" "=r<>,g")
939 (match_operand:SI 1 "general_operand" "g,r<>"))]
941 "* return output_move_simode (operands);")
943 (define_expand "movhi"
944 [(set (match_operand:HI 0 "general_operand" "")
945 (match_operand:HI 1 "general_operand" ""))]
950 [(set (match_operand:HI 0 "general_operand" "=g")
951 (match_operand:HI 1 "general_operand" "g"))]
953 "* return output_move_himode (operands);")
956 [(set (match_operand:HI 0 "general_operand" "=r<>,g")
957 (match_operand:HI 1 "general_operand" "g,r<>"))]
959 "* return output_move_himode (operands);")
961 (define_insn "movstricthi"
962 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
963 (match_operand:HI 1 "general_operand" "rmn"))]
967 if (GET_CODE (operands[1]) == CONST_INT)
969 if (operands[1] == const0_rtx
970 && (DATA_REG_P (operands[0])
971 || GET_CODE (operands[0]) == MEM)
972 /* clr insns on 68000 read before writing.
973 This isn't so on the 68010, but we have no TARGET_68010. */
974 && ((TARGET_68020 || TARGET_5200)
975 || !(GET_CODE (operands[0]) == MEM
976 && MEM_VOLATILE_P (operands[0]))))
977 return \"clr%.w %0\";
979 return \"move%.w %1,%0\";
982 (define_expand "movqi"
983 [(set (match_operand:QI 0 "general_operand" "")
984 (match_operand:QI 1 "general_operand" ""))]
989 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
990 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
992 "* return output_move_qimode (operands);")
995 [(set (match_operand:QI 0 "general_operand" "=d<>,dm")
996 (match_operand:QI 1 "general_operand" "dmi,d<>"))]
998 "* return output_move_qimode (operands);")
1000 (define_insn "movstrictqi"
1001 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1002 (match_operand:QI 1 "general_operand" "dmn"))]
1006 if (operands[1] == const0_rtx
1007 /* clr insns on 68000 read before writing.
1008 This isn't so on the 68010, but we have no TARGET_68010. */
1009 && ((TARGET_68020 || TARGET_5200)
1010 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1011 return \"clr%.b %0\";
1012 return \"move%.b %1,%0\";
1015 (define_expand "movsf"
1016 [(set (match_operand:SF 0 "general_operand" "")
1017 (match_operand:SF 1 "general_operand" ""))]
1022 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1023 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1024 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1025 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1029 if (which_alternative >= 4)
1030 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1031 if (FPA_REG_P (operands[0]))
1033 if (FPA_REG_P (operands[1]))
1034 return \"fpmove%.s %x1,%x0\";
1035 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1036 return output_move_const_single (operands);
1037 else if (FP_REG_P (operands[1]))
1038 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1039 return \"fpmove%.s %x1,%x0\";
1041 if (FPA_REG_P (operands[1]))
1043 if (FP_REG_P (operands[0]))
1044 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1046 return \"fpmove%.s %x1,%x0\";
1048 if (FP_REG_P (operands[0]))
1050 if (FP_REG_P (operands[1]))
1051 return \"f%$move%.x %1,%0\";
1052 else if (ADDRESS_REG_P (operands[1]))
1053 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1054 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1055 return output_move_const_single (operands);
1056 return \"f%$move%.s %f1,%0\";
1058 if (FP_REG_P (operands[1]))
1060 if (ADDRESS_REG_P (operands[0]))
1061 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1062 return \"fmove%.s %f1,%0\";
1064 return \"move%.l %1,%0\";
1068 [(set (match_operand:SF 0 "general_operand" "=r,g")
1069 (match_operand:SF 1 "general_operand" "g,r"))]
1071 "* return \"move%.l %1,%0\";")
1073 (define_expand "movdf"
1074 [(set (match_operand:DF 0 "general_operand" "")
1075 (match_operand:DF 1 "general_operand" ""))]
1080 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1081 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1082 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1083 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1087 if (which_alternative == 7)
1088 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1089 if (FPA_REG_P (operands[0]))
1091 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1092 return output_move_const_double (operands);
1093 if (FP_REG_P (operands[1]))
1094 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1095 return \"fpmove%.d %x1,%x0\";
1097 else if (FPA_REG_P (operands[1]))
1099 if (FP_REG_P(operands[0]))
1100 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1102 return \"fpmove%.d %x1,%x0\";
1104 if (FP_REG_P (operands[0]))
1106 if (FP_REG_P (operands[1]))
1107 return \"f%&move%.x %1,%0\";
1108 if (REG_P (operands[1]))
1111 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1112 output_asm_insn (\"move%.l %1,%-\", xoperands);
1113 output_asm_insn (\"move%.l %1,%-\", operands);
1114 return \"f%&move%.d %+,%0\";
1116 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1117 return output_move_const_double (operands);
1118 return \"f%&move%.d %f1,%0\";
1120 else if (FP_REG_P (operands[1]))
1122 if (REG_P (operands[0]))
1124 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1125 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1126 return \"move%.l %+,%0\";
1129 return \"fmove%.d %f1,%0\";
1131 return output_move_double (operands);
1135 [(set (match_operand:DF 0 "general_operand" "=r,g")
1136 (match_operand:DF 1 "general_operand" "g,r"))]
1138 "* return output_move_double (operands);")
1140 (define_expand "movxf"
1141 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1142 (match_operand:XF 1 "general_operand" ""))]
1146 if (CONSTANT_P (operands[1]))
1148 operands[1] = force_const_mem (XFmode, operands[1]);
1149 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1150 && ! reload_in_progress)
1151 operands[1] = change_address (operands[1], XFmode,
1152 XEXP (operands[1], 0));
1157 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1158 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1162 if (FP_REG_P (operands[0]))
1164 if (FP_REG_P (operands[1]))
1165 return \"fmove%.x %1,%0\";
1166 if (REG_P (operands[1]))
1169 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1170 output_asm_insn (\"move%.l %1,%-\", xoperands);
1171 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1172 output_asm_insn (\"move%.l %1,%-\", xoperands);
1173 output_asm_insn (\"move%.l %1,%-\", operands);
1174 return \"fmove%.x %+,%0\";
1176 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1177 return \"fmove%.x %1,%0\";
1178 return \"fmove%.x %f1,%0\";
1180 if (REG_P (operands[0]))
1182 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1183 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1184 output_asm_insn (\"move%.l %+,%0\", operands);
1185 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1186 return \"move%.l %+,%0\";
1188 return \"fmove%.x %f1,%0\";
1193 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1194 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1198 if (FP_REG_P (operands[0]))
1200 if (FP_REG_P (operands[1]))
1201 return \"fmove%.x %1,%0\";
1202 if (REG_P (operands[1]))
1205 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1206 output_asm_insn (\"move%.l %1,%-\", xoperands);
1207 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1208 output_asm_insn (\"move%.l %1,%-\", xoperands);
1209 output_asm_insn (\"move%.l %1,%-\", operands);
1210 return \"fmove%.x %+,%0\";
1212 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1213 return \"fmove%.x %1,%0\";
1214 return \"fmove%.x %f1,%0\";
1216 if (FP_REG_P (operands[1]))
1218 if (REG_P (operands[0]))
1220 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1221 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1222 output_asm_insn (\"move%.l %+,%0\", operands);
1223 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1224 return \"move%.l %+,%0\";
1227 return \"fmove%.x %f1,%0\";
1229 return output_move_double (operands);
1233 (define_expand "movdi"
1234 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1235 [(set (match_operand:DI 0 "general_operand" "")
1236 (match_operand:DI 1 "general_operand" ""))]
1240 ;; movdi can apply to fp regs in some cases
1242 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1243 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1244 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1245 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1246 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1247 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1248 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1252 if (which_alternative == 8)
1253 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1254 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1255 return \"fpmove%.d %x1,%x0\";
1256 if (FP_REG_P (operands[0]))
1258 if (FP_REG_P (operands[1]))
1259 return \"fmove%.x %1,%0\";
1260 if (REG_P (operands[1]))
1263 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1264 output_asm_insn (\"move%.l %1,%-\", xoperands);
1265 output_asm_insn (\"move%.l %1,%-\", operands);
1266 return \"fmove%.d %+,%0\";
1268 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1269 return output_move_const_double (operands);
1270 return \"fmove%.d %f1,%0\";
1272 else if (FP_REG_P (operands[1]))
1274 if (REG_P (operands[0]))
1276 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1277 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1278 return \"move%.l %+,%0\";
1281 return \"fmove%.d %f1,%0\";
1283 return output_move_double (operands);
1287 [(set (match_operand:DI 0 "general_operand" "=r,g")
1288 (match_operand:DI 1 "general_operand" "g,r"))]
1290 "* return output_move_double (operands);")
1292 ;; Thus goes after the move instructions
1293 ;; because the move instructions are better (require no spilling)
1294 ;; when they can apply. It goes before the add/sub insns
1295 ;; so we will prefer it to them.
1297 (define_insn "pushasi"
1298 [(set (match_operand:SI 0 "push_operand" "=m")
1299 (match_operand:SI 1 "address_operand" "p"))]
1303 ;; truncation instructions
1304 (define_insn "truncsiqi2"
1305 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1307 (match_operand:SI 1 "general_operand" "doJ,i")))]
1311 if (GET_CODE (operands[0]) == REG)
1313 /* Must clear condition codes, since the move.l bases them on
1314 the entire 32 bits, not just the desired 8 bits. */
1316 return \"move%.l %1,%0\";
1318 if (GET_CODE (operands[1]) == MEM)
1319 operands[1] = adj_offsettable_operand (operands[1], 3);
1320 return \"move%.b %1,%0\";
1323 (define_insn "trunchiqi2"
1324 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1326 (match_operand:HI 1 "general_operand" "doJ,i")))]
1330 if (GET_CODE (operands[0]) == REG
1331 && (GET_CODE (operands[1]) == MEM
1332 || GET_CODE (operands[1]) == CONST_INT))
1334 /* Must clear condition codes, since the move.w bases them on
1335 the entire 16 bits, not just the desired 8 bits. */
1337 return \"move%.w %1,%0\";
1339 if (GET_CODE (operands[0]) == REG)
1341 /* Must clear condition codes, since the move.l bases them on
1342 the entire 32 bits, not just the desired 8 bits. */
1344 return \"move%.l %1,%0\";
1346 if (GET_CODE (operands[1]) == MEM)
1347 operands[1] = adj_offsettable_operand (operands[1], 1);
1348 return \"move%.b %1,%0\";
1351 (define_insn "truncsihi2"
1352 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1354 (match_operand:SI 1 "general_operand" "roJ,i")))]
1358 if (GET_CODE (operands[0]) == REG)
1360 /* Must clear condition codes, since the move.l bases them on
1361 the entire 32 bits, not just the desired 8 bits. */
1363 return \"move%.l %1,%0\";
1365 if (GET_CODE (operands[1]) == MEM)
1366 operands[1] = adj_offsettable_operand (operands[1], 2);
1367 return \"move%.w %1,%0\";
1370 ;; zero extension instructions
1372 ;; this is the canonical form for (lshiftrt:DI x 32)
1373 (define_insn "zero_extendsidi2"
1374 [(set (match_operand:DI 0 "general_operand" "rm")
1375 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1380 if (GET_CODE (operands[0]) == REG)
1381 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1382 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1383 return \"move%.l %1,%0\;clr%.l %0\";
1384 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1385 return \"clr%.l %0\;move%.l %1,%0\";
1387 operands[2] = adj_offsettable_operand (operands[0], 4);
1388 if (ADDRESS_REG_P (operands[0]))
1389 return \"move%.l %1,%2\;sub%.l %0,%0\";
1391 return \"move%.l %1,%2\;clr%.l %0\";
1394 (define_expand "zero_extendhisi2"
1395 [(set (match_operand:SI 0 "register_operand" "")
1397 (set (strict_low_part (match_dup 2))
1398 (match_operand:HI 1 "general_operand" ""))]
1402 operands[1] = make_safe_from (operands[1], operands[0]);
1403 if (GET_CODE (operands[0]) == SUBREG)
1404 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1405 SUBREG_WORD (operands[0]));
1407 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1410 (define_expand "zero_extendqihi2"
1411 [(set (match_operand:HI 0 "register_operand" "")
1413 (set (strict_low_part (match_dup 2))
1414 (match_operand:QI 1 "general_operand" ""))]
1418 operands[1] = make_safe_from (operands[1], operands[0]);
1419 if (GET_CODE (operands[0]) == SUBREG)
1420 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1421 SUBREG_WORD (operands[0]));
1423 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1426 (define_expand "zero_extendqisi2"
1427 [(set (match_operand:SI 0 "register_operand" "")
1429 (set (strict_low_part (match_dup 2))
1430 (match_operand:QI 1 "general_operand" ""))]
1434 operands[1] = make_safe_from (operands[1], operands[0]);
1435 if (GET_CODE (operands[0]) == SUBREG)
1436 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1437 SUBREG_WORD (operands[0]));
1439 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1442 ;; Patterns to recognize zero-extend insns produced by the combiner.
1443 ;; We don't allow both operands in memory, because of aliasing problems.
1444 ;; Explicitly disallow two memory operands via the condition since reloading
1445 ;; of this case will result in worse code than the uncombined patterns.
1448 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1449 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1450 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1453 if (DATA_REG_P (operands[0]))
1455 if (GET_CODE (operands[1]) == REG
1456 && REGNO (operands[0]) == REGNO (operands[1]))
1457 return \"and%.l %#0xFFFF,%0\";
1458 if (reg_mentioned_p (operands[0], operands[1]))
1459 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1460 return \"clr%.l %0\;move%.w %1,%0\";
1462 else if (GET_CODE (operands[0]) == MEM
1463 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1464 return \"move%.w %1,%0\;clr%.w %0\";
1465 else if (GET_CODE (operands[0]) == MEM
1466 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1467 return \"clr%.w %0\;move%.w %1,%0\";
1470 output_asm_insn (\"clr%.w %0\", operands);
1471 operands[0] = adj_offsettable_operand (operands[0], 2);
1472 return \"move%.w %1,%0\";
1477 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1478 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1479 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1482 if (DATA_REG_P (operands[0]))
1484 if (GET_CODE (operands[1]) == REG
1485 && REGNO (operands[0]) == REGNO (operands[1]))
1486 return \"and%.w %#0xFF,%0\";
1487 if (reg_mentioned_p (operands[0], operands[1]))
1488 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1489 return \"clr%.w %0\;move%.b %1,%0\";
1491 else if (GET_CODE (operands[0]) == MEM
1492 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1494 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1495 == STACK_POINTER_REGNUM)
1497 output_asm_insn (\"clr%.w %-\", operands);
1498 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1499 plus_constant (stack_pointer_rtx, 1));
1500 return \"move%.b %1,%0\";
1503 return \"move%.b %1,%0\;clr%.b %0\";
1505 else if (GET_CODE (operands[0]) == MEM
1506 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1507 return \"clr%.b %0\;move%.b %1,%0\";
1510 output_asm_insn (\"clr%.b %0\", operands);
1511 operands[0] = adj_offsettable_operand (operands[0], 1);
1512 return \"move%.b %1,%0\";
1517 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1518 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1519 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1522 if (DATA_REG_P (operands[0]))
1524 if (GET_CODE (operands[1]) == REG
1525 && REGNO (operands[0]) == REGNO (operands[1]))
1526 return \"and%.l %#0xFF,%0\";
1527 if (reg_mentioned_p (operands[0], operands[1]))
1528 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1529 return \"clr%.l %0\;move%.b %1,%0\";
1531 else if (GET_CODE (operands[0]) == MEM
1532 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1534 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1537 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1539 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1542 return \"clrl %0@-\;moveb %1,%0@(3)\";
1545 else if (GET_CODE (operands[0]) == MEM
1546 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1548 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1551 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1553 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1556 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1561 output_asm_insn (\"clr%.l %0\", operands);
1562 operands[0] = adj_offsettable_operand (operands[0], 3);
1563 return \"move%.b %1,%0\";
1567 ;; sign extension instructions
1569 (define_insn "extendqidi2"
1570 [(set (match_operand:DI 0 "general_operand" "=d")
1572 (match_operand:QI 1 "general_operand" "rm")))]
1577 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1578 if (TARGET_68020 || TARGET_5200)
1579 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1581 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1584 (define_insn "extendhidi2"
1585 [(set (match_operand:DI 0 "general_operand" "=d")
1587 (match_operand:HI 1 "general_operand" "rm")))]
1592 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1593 if (TARGET_68020 || TARGET_5200)
1594 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1596 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1599 (define_insn "extendsidi2"
1600 [(set (match_operand:DI 0 "general_operand" "=d")
1602 (match_operand:SI 1 "general_operand" "rm")))]
1607 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1608 if (TARGET_68020 || TARGET_5200)
1609 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1611 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1614 ;; Special case when one can avoid register clobbering, copy and test
1615 ;; Maybe there is a way to make that the general case, by forcing the
1616 ;; result of the SI tree to be in the lower register of the DI target
1618 (define_insn "extendplussidi"
1619 [(set (match_operand:DI 0 "register_operand" "=d")
1620 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1621 (match_operand:SI 2 "general_operand" "rmn"))))]
1626 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1627 if (GET_CODE (operands[1]) == CONST_INT
1628 && (unsigned) INTVAL (operands[1]) > 8)
1630 rtx tmp = operands[1];
1632 operands[1] = operands[2];
1635 if (GET_CODE (operands[1]) == REG
1636 && REGNO (operands[1]) == REGNO (operands[3]))
1637 output_asm_insn (\"add%.l %2,%3\", operands);
1639 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1640 if (TARGET_68020 || TARGET_5200)
1641 return \"smi %0\;extb%.l %0\";
1643 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1646 (define_insn "extendhisi2"
1647 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1649 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1653 if (ADDRESS_REG_P (operands[0]))
1654 return \"move%.w %1,%0\";
1655 return \"ext%.l %0\";
1658 (define_insn "extendqihi2"
1659 [(set (match_operand:HI 0 "general_operand" "=d")
1660 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1664 (define_insn "extendqisi2"
1665 [(set (match_operand:SI 0 "general_operand" "=d")
1666 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1667 "TARGET_68020 || TARGET_5200"
1670 ;; Conversions between float and double.
1672 (define_expand "extendsfdf2"
1673 [(set (match_operand:DF 0 "general_operand" "")
1675 (match_operand:SF 1 "general_operand" "")))]
1676 "TARGET_68881 || TARGET_FPA"
1680 [(set (match_operand:DF 0 "general_operand" "=x,y")
1682 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1687 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1689 (match_operand:SF 1 "general_operand" "f,dmF")))]
1693 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1695 if (REGNO (operands[0]) == REGNO (operands[1]))
1697 /* Extending float to double in an fp-reg is a no-op.
1698 NOTICE_UPDATE_CC has already assumed that the
1699 cc will be set. So cancel what it did. */
1700 cc_status = cc_prev_status;
1703 return \"f%&move%.x %1,%0\";
1705 if (FP_REG_P (operands[0]))
1706 return \"f%&move%.s %f1,%0\";
1707 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1709 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1710 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1711 return \"move%.l %+,%0\";
1713 return \"fmove%.d %f1,%0\";
1716 ;; This cannot output into an f-reg because there is no way to be
1717 ;; sure of truncating in that case.
1718 ;; But on the Sun FPA, we can be sure.
1719 (define_expand "truncdfsf2"
1720 [(set (match_operand:SF 0 "general_operand" "")
1722 (match_operand:DF 1 "general_operand" "")))]
1723 "TARGET_68881 || TARGET_FPA"
1727 [(set (match_operand:SF 0 "general_operand" "=x,y")
1729 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1733 ;; On the '040 we can truncate in a register accurately and easily.
1735 [(set (match_operand:SF 0 "general_operand" "=f")
1737 (match_operand:DF 1 "general_operand" "fmG")))]
1741 if (FP_REG_P (operands[1]))
1742 return \"f%$move%.x %1,%0\";
1743 return \"f%$move%.d %f1,%0\";
1747 [(set (match_operand:SF 0 "general_operand" "=dm")
1749 (match_operand:DF 1 "general_operand" "f")))]
1753 ;; Conversion between fixed point and floating point.
1754 ;; Note that among the fix-to-float insns
1755 ;; the ones that start with SImode come first.
1756 ;; That is so that an operand that is a CONST_INT
1757 ;; (and therefore lacks a specific machine mode).
1758 ;; will be recognized as SImode (which is always valid)
1759 ;; rather than as QImode or HImode.
1761 (define_expand "floatsisf2"
1762 [(set (match_operand:SF 0 "general_operand" "")
1763 (float:SF (match_operand:SI 1 "general_operand" "")))]
1764 "TARGET_68881 || TARGET_FPA"
1768 [(set (match_operand:SF 0 "general_operand" "=y,x")
1769 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1774 [(set (match_operand:SF 0 "general_operand" "=f")
1775 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1779 (define_expand "floatsidf2"
1780 [(set (match_operand:DF 0 "general_operand" "")
1781 (float:DF (match_operand:SI 1 "general_operand" "")))]
1782 "TARGET_68881 || TARGET_FPA"
1786 [(set (match_operand:DF 0 "general_operand" "=y,x")
1787 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1792 [(set (match_operand:DF 0 "general_operand" "=f")
1793 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1797 (define_insn "floathisf2"
1798 [(set (match_operand:SF 0 "general_operand" "=f")
1799 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1803 (define_insn "floathidf2"
1804 [(set (match_operand:DF 0 "general_operand" "=f")
1805 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1809 (define_insn "floatqisf2"
1810 [(set (match_operand:SF 0 "general_operand" "=f")
1811 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1815 (define_insn "floatqidf2"
1816 [(set (match_operand:DF 0 "general_operand" "=f")
1817 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1821 ;; New routines to convert floating-point values to integers
1822 ;; to be used on the '040. These should be faster than trapping
1823 ;; into the kernel to emulate fintrz. They should also be faster
1824 ;; than calling the subroutines fixsfsi or fixdfsi.
1826 (define_insn "fix_truncdfsi2"
1827 [(set (match_operand:SI 0 "general_operand" "=dm")
1828 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1829 (clobber (match_scratch:SI 2 "=d"))
1830 (clobber (match_scratch:SI 3 "=d"))]
1831 "TARGET_68881 && TARGET_68040"
1835 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1838 (define_insn "fix_truncdfhi2"
1839 [(set (match_operand:HI 0 "general_operand" "=dm")
1840 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1841 (clobber (match_scratch:SI 2 "=d"))
1842 (clobber (match_scratch:SI 3 "=d"))]
1843 "TARGET_68881 && TARGET_68040"
1847 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1850 (define_insn "fix_truncdfqi2"
1851 [(set (match_operand:QI 0 "general_operand" "=dm")
1852 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1853 (clobber (match_scratch:SI 2 "=d"))
1854 (clobber (match_scratch:SI 3 "=d"))]
1855 "TARGET_68881 && TARGET_68040"
1859 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1862 ;; Convert a float to a float whose value is an integer.
1863 ;; This is the first stage of converting it to an integer type.
1865 (define_insn "ftruncdf2"
1866 [(set (match_operand:DF 0 "general_operand" "=f")
1867 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1868 "TARGET_68881 && !TARGET_68040"
1871 if (FP_REG_P (operands[1]))
1872 return \"fintrz%.x %f1,%0\";
1873 return \"fintrz%.d %f1,%0\";
1876 (define_insn "ftruncsf2"
1877 [(set (match_operand:SF 0 "general_operand" "=f")
1878 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1879 "TARGET_68881 && !TARGET_68040"
1882 if (FP_REG_P (operands[1]))
1883 return \"fintrz%.x %f1,%0\";
1884 return \"fintrz%.s %f1,%0\";
1887 ;; Convert a float whose value is an integer
1888 ;; to an actual integer. Second stage of converting float to integer type.
1889 (define_insn "fixsfqi2"
1890 [(set (match_operand:QI 0 "general_operand" "=dm")
1891 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1895 (define_insn "fixsfhi2"
1896 [(set (match_operand:HI 0 "general_operand" "=dm")
1897 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1901 (define_insn "fixsfsi2"
1902 [(set (match_operand:SI 0 "general_operand" "=dm")
1903 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1907 (define_insn "fixdfqi2"
1908 [(set (match_operand:QI 0 "general_operand" "=dm")
1909 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1913 (define_insn "fixdfhi2"
1914 [(set (match_operand:HI 0 "general_operand" "=dm")
1915 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1919 (define_insn "fixdfsi2"
1920 [(set (match_operand:SI 0 "general_operand" "=dm")
1921 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1925 ;; Convert a float to an integer.
1926 ;; On the Sun FPA, this is done in one step.
1929 [(set (match_operand:SI 0 "general_operand" "=x,y")
1930 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1935 [(set (match_operand:SI 0 "general_operand" "=x,y")
1936 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1942 (define_insn "adddi_lshrdi_63"
1943 [(set (match_operand:DI 0 "general_operand" "=d")
1944 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1947 (clobber (match_scratch:SI 2 "=d"))]
1951 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1952 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1954 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1955 if (GET_CODE (operands[1]) == REG)
1956 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1957 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1958 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1959 operands[4] = operands[1];
1961 operands[4] = adj_offsettable_operand (operands[1], 4);
1962 if (GET_CODE (operands[1]) == MEM
1963 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1964 output_asm_insn (\"move%.l %4,%3\", operands);
1965 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1966 if (TARGET_68020 || TARGET_5200)
1967 output_asm_insn (\"extb%.l %2\", operands);
1969 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1970 if (GET_CODE (operands[1]) != MEM
1971 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1972 output_asm_insn (\"move%.l %4,%3\", operands);
1973 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1976 (define_insn "adddi_sexthishl32"
1977 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
1978 (plus:DI (ashift:DI (sign_extend:DI
1979 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1981 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1982 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1987 if (ADDRESS_REG_P (operands[0]))
1988 return \"add%.w %1,%0\";
1989 else if (ADDRESS_REG_P (operands[3]))
1990 return \"move%.w %1,%3\;add%.l %3,%0\";
1992 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1995 (define_insn "adddi_dilshr32"
1996 [(set (match_operand:DI 0 "general_operand" "=do")
1997 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1998 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1999 ;; (const_int 32))))]
2000 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2002 (match_operand:DI 2 "general_operand" "0")))]
2007 if (GET_CODE (operands[0]) == REG)
2008 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2010 operands[2] = adj_offsettable_operand (operands[0], 4);
2011 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2014 (define_insn "adddi_dishl32"
2015 [(set (match_operand:DI 0 "general_operand" "=ro")
2016 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2017 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2018 ;; (const_int 32))))]
2019 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2021 (match_operand:DI 2 "general_operand" "0")))]
2026 if (GET_CODE (operands[1]) == REG)
2027 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2029 operands[1] = adj_offsettable_operand (operands[1], 4);
2030 return \"add%.l %1,%0\";
2033 (define_insn "adddi3"
2034 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2035 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2036 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2037 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2041 if (DATA_REG_P (operands[0]))
2043 if (DATA_REG_P (operands[2]))
2044 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2045 else if (GET_CODE (operands[2]) == MEM
2046 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2048 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2052 /* TODO : this should work also for CONST operands[2] */
2053 if (GET_CODE (operands[2]) == REG)
2054 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2056 operands[1] = adj_offsettable_operand (operands[2], 4);
2057 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2060 else if (GET_CODE (operands[0]) == MEM)
2062 if (GET_CODE (operands[2]) == MEM
2063 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2064 return \"add%.l %2,%0\;addx%.l %2,%0\";
2066 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2068 operands[1] = gen_rtx (MEM, SImode,
2069 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2070 gen_rtx (CONST_INT, VOIDmode, -8)));
2071 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2073 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2075 operands[1] = XEXP(operands[0], 0);
2076 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2080 operands[1] = adj_offsettable_operand (operands[0], 4);
2081 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2086 (define_insn "addsi_lshrsi_31"
2087 [(set (match_operand:SI 0 "general_operand" "=dm")
2088 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2094 operands[2] = operands[0];
2095 operands[3] = gen_label_rtx();
2096 if (GET_CODE (operands[0]) == MEM)
2098 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2099 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2100 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2101 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2103 output_asm_insn (\"move%.l %1,%0\", operands);
2105 output_asm_insn (\"jbpl %l3\", operands);
2107 output_asm_insn (\"jpl %l3\", operands);
2110 output_asm_insn (\"addq%.l %#1,%2\", operands);
2112 output_asm_insn (\"add%.l %#1,%2\", operands);
2114 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2115 CODE_LABEL_NUMBER (operands[3]));
2119 ;; Note that the middle two alternatives are near-duplicates
2120 ;; in order to handle insns generated by reload.
2121 ;; This is needed since they are not themselves reloaded,
2122 ;; so commutativity won't apply to them.
2123 (define_insn "addsi3"
2124 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2125 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2126 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2130 if (! operands_match_p (operands[0], operands[1]))
2132 if (!ADDRESS_REG_P (operands[1]))
2134 rtx tmp = operands[1];
2136 operands[1] = operands[2];
2140 /* These insns can result from reloads to access
2141 stack slots over 64k from the frame pointer. */
2142 if (GET_CODE (operands[2]) == CONST_INT
2143 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2144 return \"move%.l %2,%0\;add%.l %1,%0\";
2146 if (GET_CODE (operands[2]) == REG)
2147 return \"lea 0(%1,%2.l),%0\";
2149 return \"lea %c2(%1),%0\";
2152 if (GET_CODE (operands[2]) == REG)
2153 return \"lea (%1,%2.l),%0\";
2155 return \"lea (%c2,%1),%0\";
2156 #else /* not MOTOROLA (MIT syntax) */
2157 if (GET_CODE (operands[2]) == REG)
2158 return \"lea %1@(0,%2:l),%0\";
2160 return \"lea %1@(%c2),%0\";
2161 #endif /* not MOTOROLA */
2162 #endif /* not SGS */
2164 if (GET_CODE (operands[2]) == CONST_INT)
2167 if (INTVAL (operands[2]) > 0
2168 && INTVAL (operands[2]) <= 8)
2169 return \"addq%.l %2,%0\";
2170 if (INTVAL (operands[2]) < 0
2171 && INTVAL (operands[2]) >= -8)
2173 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2174 - INTVAL (operands[2]));
2175 return \"subq%.l %2,%0\";
2177 /* On the CPU32 it is faster to use two addql instructions to
2178 add a small integer (8 < N <= 16) to a register.
2179 Likewise for subql. */
2180 if (TARGET_CPU32 && REG_P (operands[0]))
2182 if (INTVAL (operands[2]) > 8
2183 && INTVAL (operands[2]) <= 16)
2185 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2186 INTVAL (operands[2]) - 8);
2187 return \"addq%.l %#8,%0\;addq%.l %2,%0\";
2189 if (INTVAL (operands[2]) < -8
2190 && INTVAL (operands[2]) >= -16)
2192 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2193 - INTVAL (operands[2]) - 8);
2194 return \"subq%.l %#8,%0\;subq%.l %2,%0\";
2198 if (ADDRESS_REG_P (operands[0])
2199 && INTVAL (operands[2]) >= -0x8000
2200 && INTVAL (operands[2]) < 0x8000)
2203 return \"add%.w %2,%0\";
2206 return \"lea (%c2,%0),%0\";
2208 return \"lea %0@(%c2),%0\";
2212 return \"add%.l %2,%0\";
2216 [(set (match_operand:SI 0 "general_operand" "=a")
2217 (plus:SI (match_operand:SI 1 "general_operand" "0")
2219 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2223 (define_insn "addhi3"
2224 [(set (match_operand:HI 0 "general_operand" "=m,r")
2225 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2226 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2230 if (GET_CODE (operands[2]) == CONST_INT)
2233 /* If the constant would be a negative number when interpreted as
2234 HImode, make it negative. This is usually, but not always, done
2235 elsewhere in the compiler. First check for constants out of range,
2236 which could confuse us. */
2238 if (INTVAL (operands[2]) >= 32768)
2239 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2240 INTVAL (operands[2]) - 65536);
2242 if (INTVAL (operands[2]) > 0
2243 && INTVAL (operands[2]) <= 8)
2244 return \"addq%.w %2,%0\";
2245 if (INTVAL (operands[2]) < 0
2246 && INTVAL (operands[2]) >= -8)
2248 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2249 - INTVAL (operands[2]));
2250 return \"subq%.w %2,%0\";
2252 /* On the CPU32 it is faster to use two addqw instructions to
2253 add a small integer (8 < N <= 16) to a register.
2254 Likewise for subqw. */
2255 if (TARGET_CPU32 && REG_P (operands[0]))
2257 if (INTVAL (operands[2]) > 8
2258 && INTVAL (operands[2]) <= 16)
2260 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2261 INTVAL (operands[2]) - 8);
2262 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2264 if (INTVAL (operands[2]) < -8
2265 && INTVAL (operands[2]) >= -16)
2267 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2268 - INTVAL (operands[2]) - 8);
2269 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2273 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2275 return \"lea (%c2,%0),%0\";
2277 return \"lea %0@(%c2),%0\";
2280 return \"add%.w %2,%0\";
2283 ;; These insns must use MATCH_DUP instead of the more expected
2284 ;; use of a matching constraint because the "output" here is also
2285 ;; an input, so you can't use the matching constraint. That also means
2286 ;; that you can't use the "%", so you need patterns with the matched
2287 ;; operand in both positions.
2290 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2291 (plus:HI (match_dup 0)
2292 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2296 if (GET_CODE (operands[1]) == CONST_INT)
2299 /* If the constant would be a negative number when interpreted as
2300 HImode, make it negative. This is usually, but not always, done
2301 elsewhere in the compiler. First check for constants out of range,
2302 which could confuse us. */
2304 if (INTVAL (operands[1]) >= 32768)
2305 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2306 INTVAL (operands[1]) - 65536);
2308 if (INTVAL (operands[1]) > 0
2309 && INTVAL (operands[1]) <= 8)
2310 return \"addq%.w %1,%0\";
2311 if (INTVAL (operands[1]) < 0
2312 && INTVAL (operands[1]) >= -8)
2314 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2315 - INTVAL (operands[1]));
2316 return \"subq%.w %1,%0\";
2318 /* On the CPU32 it is faster to use two addqw instructions to
2319 add a small integer (8 < N <= 16) to a register.
2320 Likewise for subqw. */
2321 if (TARGET_CPU32 && REG_P (operands[0]))
2323 if (INTVAL (operands[1]) > 8
2324 && INTVAL (operands[1]) <= 16)
2326 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2327 INTVAL (operands[1]) - 8);
2328 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2330 if (INTVAL (operands[1]) < -8
2331 && INTVAL (operands[1]) >= -16)
2333 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2334 - INTVAL (operands[1]) - 8);
2335 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2339 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2341 return \"lea (%c1,%0),%0\";
2343 return \"lea %0@(%c1),%0\";
2346 return \"add%.w %1,%0\";
2350 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2351 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2356 if (GET_CODE (operands[1]) == CONST_INT)
2359 /* If the constant would be a negative number when interpreted as
2360 HImode, make it negative. This is usually, but not always, done
2361 elsewhere in the compiler. First check for constants out of range,
2362 which could confuse us. */
2364 if (INTVAL (operands[1]) >= 32768)
2365 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2366 INTVAL (operands[1]) - 65536);
2368 if (INTVAL (operands[1]) > 0
2369 && INTVAL (operands[1]) <= 8)
2370 return \"addq%.w %1,%0\";
2371 if (INTVAL (operands[1]) < 0
2372 && INTVAL (operands[1]) >= -8)
2374 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2375 - INTVAL (operands[1]));
2376 return \"subq%.w %1,%0\";
2378 /* On the CPU32 it is faster to use two addqw instructions to
2379 add a small integer (8 < N <= 16) to a register.
2380 Likewise for subqw. */
2381 if (TARGET_CPU32 && REG_P (operands[0]))
2383 if (INTVAL (operands[1]) > 8
2384 && INTVAL (operands[1]) <= 16)
2386 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2387 INTVAL (operands[1]) - 8);
2388 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2390 if (INTVAL (operands[1]) < -8
2391 && INTVAL (operands[1]) >= -16)
2393 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2394 - INTVAL (operands[1]) - 8);
2395 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2399 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2401 return \"lea (%c1,%0),%0\";
2403 return \"lea %0@(%c1),%0\";
2406 return \"add%.w %1,%0\";
2409 (define_insn "addqi3"
2410 [(set (match_operand:QI 0 "general_operand" "=m,d")
2411 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2412 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2417 if (GET_CODE (operands[2]) == CONST_INT)
2419 if (INTVAL (operands[2]) >= 128)
2420 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2421 INTVAL (operands[2]) - 256);
2423 if (INTVAL (operands[2]) > 0
2424 && INTVAL (operands[2]) <= 8)
2425 return \"addq%.b %2,%0\";
2426 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2428 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2429 return \"subq%.b %2,%0\";
2433 return \"add%.b %2,%0\";
2437 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2438 (plus:QI (match_dup 0)
2439 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2444 if (GET_CODE (operands[1]) == CONST_INT)
2446 if (INTVAL (operands[1]) >= 128)
2447 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2448 INTVAL (operands[1]) - 256);
2450 if (INTVAL (operands[1]) > 0
2451 && INTVAL (operands[1]) <= 8)
2452 return \"addq%.b %1,%0\";
2453 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2455 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2456 return \"subq%.b %1,%0\";
2460 return \"add%.b %1,%0\";
2464 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2465 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2471 if (GET_CODE (operands[1]) == CONST_INT)
2473 if (INTVAL (operands[1]) >= 128)
2474 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2475 INTVAL (operands[1]) - 256);
2477 if (INTVAL (operands[1]) > 0
2478 && INTVAL (operands[1]) <= 8)
2479 return \"addq%.b %1,%0\";
2480 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2482 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2483 return \"subq%.b %1,%0\";
2487 return \"add%.b %1,%0\";
2490 (define_expand "adddf3"
2491 [(set (match_operand:DF 0 "general_operand" "")
2492 (plus:DF (match_operand:DF 1 "general_operand" "")
2493 (match_operand:DF 2 "general_operand" "")))]
2494 "TARGET_68881 || TARGET_FPA"
2498 [(set (match_operand:DF 0 "general_operand" "=x,y")
2499 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2500 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2504 if (rtx_equal_p (operands[0], operands[1]))
2505 return \"fpadd%.d %y2,%0\";
2506 if (rtx_equal_p (operands[0], operands[2]))
2507 return \"fpadd%.d %y1,%0\";
2508 if (which_alternative == 0)
2509 return \"fpadd3%.d %w2,%w1,%0\";
2510 return \"fpadd3%.d %x2,%x1,%0\";
2514 [(set (match_operand:DF 0 "general_operand" "=f")
2515 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2516 (match_operand:DF 1 "general_operand" "0")))]
2521 [(set (match_operand:DF 0 "general_operand" "=f")
2522 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2523 (match_operand:DF 1 "general_operand" "0")))]
2528 [(set (match_operand:DF 0 "general_operand" "=f")
2529 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2530 (match_operand:DF 1 "general_operand" "0")))]
2535 [(set (match_operand:DF 0 "general_operand" "=f")
2536 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2537 (match_operand:DF 2 "general_operand" "fmG")))]
2541 if (REG_P (operands[2]))
2542 return \"f%&add%.x %2,%0\";
2543 return \"f%&add%.d %f2,%0\";
2546 (define_expand "addsf3"
2547 [(set (match_operand:SF 0 "general_operand" "")
2548 (plus:SF (match_operand:SF 1 "general_operand" "")
2549 (match_operand:SF 2 "general_operand" "")))]
2550 "TARGET_68881 || TARGET_FPA"
2554 [(set (match_operand:SF 0 "general_operand" "=x,y")
2555 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2556 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2560 if (rtx_equal_p (operands[0], operands[1]))
2561 return \"fpadd%.s %w2,%0\";
2562 if (rtx_equal_p (operands[0], operands[2]))
2563 return \"fpadd%.s %w1,%0\";
2564 if (which_alternative == 0)
2565 return \"fpadd3%.s %w2,%w1,%0\";
2566 return \"fpadd3%.s %2,%1,%0\";
2570 [(set (match_operand:SF 0 "general_operand" "=f")
2571 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2572 (match_operand:SF 1 "general_operand" "0")))]
2577 [(set (match_operand:SF 0 "general_operand" "=f")
2578 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2579 (match_operand:SF 1 "general_operand" "0")))]
2584 [(set (match_operand:SF 0 "general_operand" "=f")
2585 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2586 (match_operand:SF 1 "general_operand" "0")))]
2591 [(set (match_operand:SF 0 "general_operand" "=f")
2592 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2593 (match_operand:SF 2 "general_operand" "fdmF")))]
2597 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2598 return \"f%$add%.x %2,%0\";
2599 return \"f%$add%.s %f2,%0\";
2602 ;; subtract instructions
2604 (define_insn "subdi_sexthishl32"
2605 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2606 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2607 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2609 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2614 if (ADDRESS_REG_P (operands[0]))
2615 return \"sub%.w %2,%0\";
2616 else if (ADDRESS_REG_P (operands[3]))
2617 return \"move%.w %2,%3\;sub%.l %3,%0\";
2619 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2622 (define_insn "subdi_dishl32"
2623 [(set (match_operand:DI 0 "general_operand" "+ro")
2624 (minus:DI (match_dup 0)
2625 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2631 if (GET_CODE (operands[1]) == REG)
2632 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2634 operands[1] = adj_offsettable_operand (operands[1], 4);
2635 return \"sub%.l %1,%0\";
2638 (define_insn "subdi3"
2639 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2640 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2641 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2642 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2646 if (DATA_REG_P (operands[0]))
2648 if (DATA_REG_P (operands[2]))
2649 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2650 else if (GET_CODE (operands[2]) == MEM
2651 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2653 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2657 /* TODO : this should work also for CONST operands[2] */
2658 if (GET_CODE (operands[2]) == REG)
2659 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2661 operands[1] = adj_offsettable_operand (operands[2], 4);
2662 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2665 else if (GET_CODE (operands[0]) == MEM)
2667 if (GET_CODE (operands[2]) == MEM
2668 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2669 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2671 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2673 operands[1] = gen_rtx (MEM, SImode,
2674 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2675 gen_rtx (CONST_INT, VOIDmode, -8)));
2676 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2678 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2680 operands[1] = XEXP(operands[0], 0);
2681 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2685 operands[1] = adj_offsettable_operand (operands[0], 4);
2686 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2691 (define_insn "subsi3"
2692 [(set (match_operand:SI 0 "general_operand" "=m,r")
2693 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2694 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2699 [(set (match_operand:SI 0 "general_operand" "=a")
2700 (minus:SI (match_operand:SI 1 "general_operand" "0")
2702 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2706 (define_insn "subhi3"
2707 [(set (match_operand:HI 0 "general_operand" "=m,r")
2708 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2709 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2714 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2715 (minus:HI (match_dup 0)
2716 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2720 (define_insn "subqi3"
2721 [(set (match_operand:QI 0 "general_operand" "=m,d")
2722 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2723 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2728 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2729 (minus:QI (match_dup 0)
2730 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2734 (define_expand "subdf3"
2735 [(set (match_operand:DF 0 "general_operand" "")
2736 (minus:DF (match_operand:DF 1 "general_operand" "")
2737 (match_operand:DF 2 "general_operand" "")))]
2738 "TARGET_68881 || TARGET_FPA"
2742 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2743 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2744 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2748 if (rtx_equal_p (operands[0], operands[2]))
2749 return \"fprsub%.d %y1,%0\";
2750 if (rtx_equal_p (operands[0], operands[1]))
2751 return \"fpsub%.d %y2,%0\";
2752 if (which_alternative == 0)
2753 return \"fpsub3%.d %w2,%w1,%0\";
2754 return \"fpsub3%.d %x2,%x1,%0\";
2758 [(set (match_operand:DF 0 "general_operand" "=f")
2759 (minus:DF (match_operand:DF 1 "general_operand" "0")
2760 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2765 [(set (match_operand:DF 0 "general_operand" "=f")
2766 (minus:DF (match_operand:DF 1 "general_operand" "0")
2767 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2772 [(set (match_operand:DF 0 "general_operand" "=f")
2773 (minus:DF (match_operand:DF 1 "general_operand" "0")
2774 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2779 [(set (match_operand:DF 0 "general_operand" "=f")
2780 (minus:DF (match_operand:DF 1 "general_operand" "0")
2781 (match_operand:DF 2 "general_operand" "fmG")))]
2785 if (REG_P (operands[2]))
2786 return \"f%&sub%.x %2,%0\";
2787 return \"f%&sub%.d %f2,%0\";
2790 (define_expand "subsf3"
2791 [(set (match_operand:SF 0 "general_operand" "")
2792 (minus:SF (match_operand:SF 1 "general_operand" "")
2793 (match_operand:SF 2 "general_operand" "")))]
2794 "TARGET_68881 || TARGET_FPA"
2798 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2799 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2800 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2804 if (rtx_equal_p (operands[0], operands[2]))
2805 return \"fprsub%.s %w1,%0\";
2806 if (rtx_equal_p (operands[0], operands[1]))
2807 return \"fpsub%.s %w2,%0\";
2808 if (which_alternative == 0)
2809 return \"fpsub3%.s %w2,%w1,%0\";
2810 return \"fpsub3%.s %2,%1,%0\";
2814 [(set (match_operand:SF 0 "general_operand" "=f")
2815 (minus:SF (match_operand:SF 1 "general_operand" "0")
2816 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2821 [(set (match_operand:SF 0 "general_operand" "=f")
2822 (minus:SF (match_operand:SF 1 "general_operand" "0")
2823 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2828 [(set (match_operand:SF 0 "general_operand" "=f")
2829 (minus:SF (match_operand:SF 1 "general_operand" "0")
2830 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2835 [(set (match_operand:SF 0 "general_operand" "=f")
2836 (minus:SF (match_operand:SF 1 "general_operand" "0")
2837 (match_operand:SF 2 "general_operand" "fdmF")))]
2841 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2842 return \"f%$sub%.x %2,%0\";
2843 return \"f%$sub%.s %f2,%0\";
2846 ;; multiply instructions
2848 (define_insn "mulhi3"
2849 [(set (match_operand:HI 0 "general_operand" "=d")
2850 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2851 (match_operand:HI 2 "general_operand" "dmn")))]
2855 #if defined(MOTOROLA) && !defined(CRDS)
2856 return \"muls%.w %2,%0\";
2858 return \"muls %2,%0\";
2862 (define_insn "mulhisi3"
2863 [(set (match_operand:SI 0 "general_operand" "=d")
2864 (mult:SI (sign_extend:SI
2865 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2867 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2871 #if defined(MOTOROLA) && !defined(CRDS)
2872 return \"muls%.w %2,%0\";
2874 return \"muls %2,%0\";
2879 [(set (match_operand:SI 0 "general_operand" "=d")
2880 (mult:SI (sign_extend:SI
2881 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2882 (match_operand:SI 2 "const_int_operand" "n")))]
2883 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2886 #if defined(MOTOROLA) && !defined(CRDS)
2887 return \"muls%.w %2,%0\";
2889 return \"muls %2,%0\";
2893 (define_expand "mulsi3"
2894 [(set (match_operand:SI 0 "general_operand" "")
2895 (mult:SI (match_operand:SI 1 "general_operand" "")
2896 (match_operand:SI 2 "general_operand" "")))]
2897 "TARGET_68020 || TARGET_5200"
2901 [(set (match_operand:SI 0 "general_operand" "=d")
2902 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2903 (match_operand:SI 2 "general_operand" "dmsK")))]
2908 [(set (match_operand:SI 0 "general_operand" "=d")
2909 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2910 (match_operand:SI 2 "general_operand" "d<>")))]
2914 (define_insn "umulhisi3"
2915 [(set (match_operand:SI 0 "general_operand" "=d")
2916 (mult:SI (zero_extend:SI
2917 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2919 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2923 #if defined(MOTOROLA) && !defined(CRDS)
2924 return \"mulu%.w %2,%0\";
2926 return \"mulu %2,%0\";
2931 [(set (match_operand:SI 0 "general_operand" "=d")
2932 (mult:SI (zero_extend:SI
2933 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2934 (match_operand:SI 2 "const_int_operand" "n")))]
2935 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2938 #if defined(MOTOROLA) && !defined(CRDS)
2939 return \"mulu%.w %2,%0\";
2941 return \"mulu %2,%0\";
2945 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2946 ;; proper matching constraint. This is because the matching is between
2947 ;; the high-numbered word of the DImode operand[0] and operand[1].
2948 (define_expand "umulsidi3"
2950 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2951 (mult:SI (match_operand:SI 1 "register_operand" "")
2952 (match_operand:SI 2 "nonimmediate_operand" "")))
2953 (set (subreg:SI (match_dup 0) 0)
2954 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2955 (zero_extend:DI (match_dup 2)))
2956 (const_int 32))))])]
2957 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2961 [(set (match_operand:SI 0 "register_operand" "=d")
2962 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2963 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2964 (set (match_operand:SI 3 "register_operand" "=d")
2965 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2966 (zero_extend:DI (match_dup 2)))
2968 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2971 ; Match immediate case. For 2.4 only match things < 2^31.
2972 ; It's tricky with larger values in these patterns since we need to match
2973 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2976 [(set (match_operand:SI 0 "register_operand" "=d")
2977 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2978 (match_operand:SI 2 "const_int_operand" "n")))
2979 (set (match_operand:SI 3 "register_operand" "=d")
2980 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2983 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2984 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2987 (define_expand "mulsidi3"
2989 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2990 (mult:SI (match_operand:SI 1 "register_operand" "")
2991 (match_operand:SI 2 "nonimmediate_operand" "")))
2992 (set (subreg:SI (match_dup 0) 0)
2993 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2994 (sign_extend:DI (match_dup 2)))
2995 (const_int 32))))])]
2996 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3000 [(set (match_operand:SI 0 "register_operand" "=d")
3001 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3002 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3003 (set (match_operand:SI 3 "register_operand" "=d")
3004 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3005 (sign_extend:DI (match_dup 2)))
3007 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3011 [(set (match_operand:SI 0 "register_operand" "=d")
3012 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3013 (match_operand:SI 2 "const_sint32_operand" "")))
3014 (set (match_operand:SI 3 "register_operand" "=d")
3015 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3018 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3021 (define_expand "umulsi3_highpart"
3023 [(set (match_operand:SI 0 "register_operand" "")
3026 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3027 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3029 (clobber (match_dup 3))])]
3030 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3033 operands[3] = gen_reg_rtx (SImode);
3034 if (GET_CODE (operands[2]) == CONST_INT
3035 || GET_CODE (operands[2]) == CONST_DOUBLE)
3037 if (! const_uint32_operand (operands[2], VOIDmode))
3039 /* We have to adjust the operand order for the matching constraints. */
3040 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3041 operands[1], operands[2]));
3047 [(set (match_operand:SI 0 "register_operand" "=d")
3050 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3051 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3053 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3054 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3057 (define_insn "const_umulsi3_highpart"
3058 [(set (match_operand:SI 0 "register_operand" "=d")
3061 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3062 (match_operand 3 "const_uint32_operand" ""))
3064 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3065 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3068 (define_expand "smulsi3_highpart"
3070 [(set (match_operand:SI 0 "register_operand" "")
3073 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3074 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3076 (clobber (match_dup 3))])]
3077 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3080 operands[3] = gen_reg_rtx (SImode);
3081 if (GET_CODE (operands[2]) == CONST_INT
3082 || GET_CODE (operands[2]) == CONST_DOUBLE)
3084 if (! const_sint32_operand (operands[2], VOIDmode))
3086 /* We have to adjust the operand order for the matching constraints. */
3087 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3088 operands[1], operands[2]));
3094 [(set (match_operand:SI 0 "register_operand" "=d")
3097 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3098 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3100 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3101 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3104 (define_insn "const_smulsi3_highpart"
3105 [(set (match_operand:SI 0 "register_operand" "=d")
3108 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3109 (match_operand 3 "const_sint32_operand" ""))
3111 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3112 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3115 (define_expand "muldf3"
3116 [(set (match_operand:DF 0 "general_operand" "")
3117 (mult:DF (match_operand:DF 1 "general_operand" "")
3118 (match_operand:DF 2 "general_operand" "")))]
3119 "TARGET_68881 || TARGET_FPA"
3123 [(set (match_operand:DF 0 "general_operand" "=x,y")
3124 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3125 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3129 if (rtx_equal_p (operands[1], operands[2]))
3130 return \"fpsqr%.d %y1,%0\";
3131 if (rtx_equal_p (operands[0], operands[1]))
3132 return \"fpmul%.d %y2,%0\";
3133 if (rtx_equal_p (operands[0], operands[2]))
3134 return \"fpmul%.d %y1,%0\";
3135 if (which_alternative == 0)
3136 return \"fpmul3%.d %w2,%w1,%0\";
3137 return \"fpmul3%.d %x2,%x1,%0\";
3141 [(set (match_operand:DF 0 "general_operand" "=f")
3142 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3143 (match_operand:DF 1 "general_operand" "0")))]
3148 [(set (match_operand:DF 0 "general_operand" "=f")
3149 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3150 (match_operand:DF 1 "general_operand" "0")))]
3155 [(set (match_operand:DF 0 "general_operand" "=f")
3156 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3157 (match_operand:DF 1 "general_operand" "0")))]
3162 [(set (match_operand:DF 0 "general_operand" "=f")
3163 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3164 (match_operand:DF 2 "general_operand" "fmG")))]
3168 if (GET_CODE (operands[2]) == CONST_DOUBLE
3169 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3171 int i = floating_exact_log2 (operands[2]);
3172 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3173 return \"fscale%.l %2,%0\";
3175 if (REG_P (operands[2]))
3176 return \"f%&mul%.x %2,%0\";
3177 return \"f%&mul%.d %f2,%0\";
3180 (define_expand "mulsf3"
3181 [(set (match_operand:SF 0 "general_operand" "")
3182 (mult:SF (match_operand:SF 1 "general_operand" "")
3183 (match_operand:SF 2 "general_operand" "")))]
3184 "TARGET_68881 || TARGET_FPA"
3188 [(set (match_operand:SF 0 "general_operand" "=x,y")
3189 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3190 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3194 if (rtx_equal_p (operands[1], operands[2]))
3195 return \"fpsqr%.s %w1,%0\";
3196 if (rtx_equal_p (operands[0], operands[1]))
3197 return \"fpmul%.s %w2,%0\";
3198 if (rtx_equal_p (operands[0], operands[2]))
3199 return \"fpmul%.s %w1,%0\";
3200 if (which_alternative == 0)
3201 return \"fpmul3%.s %w2,%w1,%0\";
3202 return \"fpmul3%.s %2,%1,%0\";
3206 [(set (match_operand:SF 0 "general_operand" "=f")
3207 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3208 (match_operand:SF 1 "general_operand" "0")))]
3212 return (TARGET_68040_ONLY
3213 ? \"fsmul%.l %2,%0\"
3214 : \"fsglmul%.l %2,%0\");
3218 [(set (match_operand:SF 0 "general_operand" "=f")
3219 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3220 (match_operand:SF 1 "general_operand" "0")))]
3224 return (TARGET_68040_ONLY
3225 ? \"fsmul%.w %2,%0\"
3226 : \"fsglmul%.w %2,%0\");
3230 [(set (match_operand:SF 0 "general_operand" "=f")
3231 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3232 (match_operand:SF 1 "general_operand" "0")))]
3236 return (TARGET_68040_ONLY
3237 ? \"fsmul%.b %2,%0\"
3238 : \"fsglmul%.b %2,%0\");
3242 [(set (match_operand:SF 0 "general_operand" "=f")
3243 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3244 (match_operand:SF 2 "general_operand" "fdmF")))]
3248 #ifdef FSGLMUL_USE_S
3249 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3250 return (TARGET_68040_ONLY
3251 ? \"fsmul%.s %2,%0\"
3252 : \"fsglmul%.s %2,%0\");
3254 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3255 return (TARGET_68040_ONLY
3256 ? \"fsmul%.x %2,%0\"
3257 : \"fsglmul%.x %2,%0\");
3259 return (TARGET_68040_ONLY
3260 ? \"fsmul%.s %f2,%0\"
3261 : \"fsglmul%.s %f2,%0\");
3264 ;; divide instructions
3266 (define_expand "divdf3"
3267 [(set (match_operand:DF 0 "general_operand" "")
3268 (div:DF (match_operand:DF 1 "general_operand" "")
3269 (match_operand:DF 2 "general_operand" "")))]
3270 "TARGET_68881 || TARGET_FPA"
3274 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3275 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3276 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3280 if (rtx_equal_p (operands[0], operands[2]))
3281 return \"fprdiv%.d %y1,%0\";
3282 if (rtx_equal_p (operands[0], operands[1]))
3283 return \"fpdiv%.d %y2,%0\";
3284 if (which_alternative == 0)
3285 return \"fpdiv3%.d %w2,%w1,%0\";
3286 return \"fpdiv3%.d %x2,%x1,%x0\";
3290 [(set (match_operand:DF 0 "general_operand" "=f")
3291 (div:DF (match_operand:DF 1 "general_operand" "0")
3292 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3297 [(set (match_operand:DF 0 "general_operand" "=f")
3298 (div:DF (match_operand:DF 1 "general_operand" "0")
3299 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3304 [(set (match_operand:DF 0 "general_operand" "=f")
3305 (div:DF (match_operand:DF 1 "general_operand" "0")
3306 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3311 [(set (match_operand:DF 0 "general_operand" "=f")
3312 (div:DF (match_operand:DF 1 "general_operand" "0")
3313 (match_operand:DF 2 "general_operand" "fmG")))]
3317 if (REG_P (operands[2]))
3318 return \"f%&div%.x %2,%0\";
3319 return \"f%&div%.d %f2,%0\";
3322 (define_expand "divsf3"
3323 [(set (match_operand:SF 0 "general_operand" "")
3324 (div:SF (match_operand:SF 1 "general_operand" "")
3325 (match_operand:SF 2 "general_operand" "")))]
3326 "TARGET_68881 || TARGET_FPA"
3330 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3331 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3332 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3336 if (rtx_equal_p (operands[0], operands[1]))
3337 return \"fpdiv%.s %w2,%0\";
3338 if (rtx_equal_p (operands[0], operands[2]))
3339 return \"fprdiv%.s %w1,%0\";
3340 if (which_alternative == 0)
3341 return \"fpdiv3%.s %w2,%w1,%0\";
3342 return \"fpdiv3%.s %2,%1,%0\";
3346 [(set (match_operand:SF 0 "general_operand" "=f")
3347 (div:SF (match_operand:SF 1 "general_operand" "0")
3348 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3352 return (TARGET_68040_ONLY
3353 ? \"fsdiv%.l %2,%0\"
3354 : \"fsgldiv%.l %2,%0\");
3358 [(set (match_operand:SF 0 "general_operand" "=f")
3359 (div:SF (match_operand:SF 1 "general_operand" "0")
3360 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3364 return (TARGET_68040_ONLY
3365 ? \"fsdiv%.w %2,%0\"
3366 : \"fsgldiv%.w %2,%0\");
3370 [(set (match_operand:SF 0 "general_operand" "=f")
3371 (div:SF (match_operand:SF 1 "general_operand" "0")
3372 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3376 return (TARGET_68040_ONLY
3377 ? \"fsdiv%.b %2,%0\"
3378 : \"fsgldiv%.b %2,%0\");
3382 [(set (match_operand:SF 0 "general_operand" "=f")
3383 (div:SF (match_operand:SF 1 "general_operand" "0")
3384 (match_operand:SF 2 "general_operand" "fdmF")))]
3388 #ifdef FSGLDIV_USE_S
3389 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3390 return (TARGET_68040_ONLY
3391 ? \"fsdiv%.s %2,%0\"
3392 : \"fsgldiv%.s %2,%0\");
3394 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3395 return (TARGET_68040_ONLY
3396 ? \"fsdiv%.x %2,%0\"
3397 : \"fsgldiv%.x %2,%0\");
3399 return (TARGET_68040_ONLY
3400 ? \"fsdiv%.s %f2,%0\"
3401 : \"fsgldiv%.s %f2,%0\");
3404 ;; Remainder instructions.
3406 (define_insn "divmodsi4"
3407 [(set (match_operand:SI 0 "general_operand" "=d")
3408 (div:SI (match_operand:SI 1 "general_operand" "0")
3409 (match_operand:SI 2 "general_operand" "dmsK")))
3410 (set (match_operand:SI 3 "general_operand" "=d")
3411 (mod:SI (match_dup 1) (match_dup 2)))]
3412 "TARGET_68020 && !TARGET_5200"
3415 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3416 return \"divs%.l %2,%0\";
3418 return \"divsl%.l %2,%3:%0\";
3421 (define_insn "udivmodsi4"
3422 [(set (match_operand:SI 0 "general_operand" "=d")
3423 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3424 (match_operand:SI 2 "general_operand" "dmsK")))
3425 (set (match_operand:SI 3 "general_operand" "=d")
3426 (umod:SI (match_dup 1) (match_dup 2)))]
3427 "TARGET_68020 && !TARGET_5200"
3430 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3431 return \"divu%.l %2,%0\";
3433 return \"divul%.l %2,%3:%0\";
3436 (define_insn "divmodhi4"
3437 [(set (match_operand:HI 0 "general_operand" "=d")
3438 (div:HI (match_operand:HI 1 "general_operand" "0")
3439 (match_operand:HI 2 "general_operand" "dmsK")))
3440 (set (match_operand:HI 3 "general_operand" "=d")
3441 (mod:HI (match_dup 1) (match_dup 2)))]
3446 output_asm_insn(\"ext%.l %0\;divs%.w %2,%0\", operands);
3448 output_asm_insn(\"extl %0\;divs %2,%0\", operands);
3450 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3453 return \"move%.l %0,%3\;swap %3\";
3459 (define_insn "udivmodhi4"
3460 [(set (match_operand:HI 0 "general_operand" "=d")
3461 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3462 (match_operand:HI 2 "general_operand" "dmsK")))
3463 (set (match_operand:HI 3 "general_operand" "=d")
3464 (umod:HI (match_dup 1) (match_dup 2)))]
3469 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3471 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3473 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3476 return \"move%.l %0,%3\;swap %3\";
3482 ;; logical-and instructions
3484 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3485 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3486 ;; can't allocate pseudos into it.
3488 (define_expand "andsi3"
3489 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3490 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3491 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3495 (define_insn "andsi3_internal"
3496 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3497 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3498 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3503 if (GET_CODE (operands[2]) == CONST_INT
3504 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3505 && (DATA_REG_P (operands[0])
3506 || offsettable_memref_p (operands[0])))
3508 if (GET_CODE (operands[0]) != REG)
3509 operands[0] = adj_offsettable_operand (operands[0], 2);
3510 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3511 INTVAL (operands[2]) & 0xffff);
3512 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3514 if (operands[2] == const0_rtx)
3515 return \"clr%.w %0\";
3516 return \"and%.w %2,%0\";
3518 if (GET_CODE (operands[2]) == CONST_INT
3519 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3520 && (DATA_REG_P (operands[0])
3521 || offsettable_memref_p (operands[0])))
3523 if (DATA_REG_P (operands[0]))
3525 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3529 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3530 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3532 /* This does not set condition codes in a standard way. */
3534 return \"bclr %1,%0\";
3536 return \"and%.l %2,%0\";
3539 (define_insn "andsi3_5200"
3540 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3541 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3542 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3546 (define_insn "andhi3"
3547 [(set (match_operand:HI 0 "general_operand" "=m,d")
3548 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3549 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3554 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3555 (and:HI (match_dup 0)
3556 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3561 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3562 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3567 (define_insn "andqi3"
3568 [(set (match_operand:QI 0 "general_operand" "=m,d")
3569 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3570 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3575 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3576 (and:QI (match_dup 0)
3577 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3582 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3583 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3588 ;; inclusive-or instructions
3590 (define_expand "iorsi3"
3591 [(set (match_operand:SI 0 "general_operand" "")
3592 (ior:SI (match_operand:SI 1 "general_operand" "")
3593 (match_operand:SI 2 "general_operand" "")))]
3597 (define_insn "iorsi3_internal"
3598 [(set (match_operand:SI 0 "general_operand" "=m,d")
3599 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3600 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3604 register int logval;
3605 if (GET_CODE (operands[2]) == CONST_INT
3606 && INTVAL (operands[2]) >> 16 == 0
3607 && (DATA_REG_P (operands[0])
3608 || offsettable_memref_p (operands[0])))
3610 if (GET_CODE (operands[0]) != REG)
3611 operands[0] = adj_offsettable_operand (operands[0], 2);
3612 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3614 return \"or%.w %2,%0\";
3616 if (GET_CODE (operands[2]) == CONST_INT
3617 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3618 && (DATA_REG_P (operands[0])
3619 || offsettable_memref_p (operands[0])))
3621 if (DATA_REG_P (operands[0]))
3623 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3627 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3628 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3631 return \"bset %1,%0\";
3633 return \"or%.l %2,%0\";
3636 (define_insn "iorsi3_5200"
3637 [(set (match_operand:SI 0 "general_operand" "=m,d")
3638 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3639 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3643 (define_insn "iorhi3"
3644 [(set (match_operand:HI 0 "general_operand" "=m,d")
3645 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3646 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3651 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3652 (ior:HI (match_dup 0)
3653 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3658 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3659 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3664 (define_insn "iorqi3"
3665 [(set (match_operand:QI 0 "general_operand" "=m,d")
3666 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3667 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3672 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3673 (ior:QI (match_dup 0)
3674 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3679 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3680 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3685 ;; On all 68k models, this makes faster code in a special case.
3686 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3688 (define_insn "iorsi_zexthi_ashl16"
3689 [(set (match_operand:SI 0 "general_operand" "=d,d")
3690 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3691 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3697 if (GET_CODE (operands[2]) != REG)
3699 operands[2] = adj_offsettable_operand (operands[2], 2);
3700 output_asm_insn (\"move%.w %2,%0\", operands);
3702 return \"swap %0\;mov%.w %1,%0\";
3706 [(set (match_operand:SI 0 "general_operand" "=o,d")
3707 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3708 (match_operand:SI 2 "general_operand" "0,0")))]
3715 byte_mode = (GET_MODE(operands[1]) == QImode);
3716 if (GET_CODE (operands[0]) == MEM)
3717 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3719 return \"or%.b %1,%0\";
3721 return \"or%.w %1,%0\";
3726 (define_expand "xorsi3"
3727 [(set (match_operand:SI 0 "general_operand" "")
3728 (xor:SI (match_operand:SI 1 "general_operand" "")
3729 (match_operand:SI 2 "general_operand" "")))]
3733 (define_insn "xorsi3_internal"
3734 [(set (match_operand:SI 0 "general_operand" "=do,m")
3735 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3736 (match_operand:SI 2 "general_operand" "di,dKs")))]
3740 if (GET_CODE (operands[2]) == CONST_INT
3741 && INTVAL (operands[2]) >> 16 == 0
3742 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
3744 if (! DATA_REG_P (operands[0]))
3745 operands[0] = adj_offsettable_operand (operands[0], 2);
3746 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3748 return \"eor%.w %2,%0\";
3750 return \"eor%.l %2,%0\";
3753 (define_insn "xorsi3_5200"
3754 [(set (match_operand:SI 0 "general_operand" "=dm,d")
3755 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3756 (match_operand:SI 2 "general_operand" "d,Ks")))]
3760 (define_insn "xorhi3"
3761 [(set (match_operand:HI 0 "general_operand" "=dm")
3762 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3763 (match_operand:HI 2 "general_operand" "dn")))]
3768 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3769 (xor:HI (match_dup 0)
3770 (match_operand:HI 1 "general_operand" "dn")))]
3775 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3776 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3781 (define_insn "xorqi3"
3782 [(set (match_operand:QI 0 "general_operand" "=dm")
3783 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3784 (match_operand:QI 2 "general_operand" "dn")))]
3789 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3790 (xor:QI (match_dup 0)
3791 (match_operand:QI 1 "general_operand" "dn")))]
3796 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3797 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3802 ;; negation instructions
3804 (define_expand "negdi2"
3805 [(set (match_operand:DI 0 "general_operand" "")
3806 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3811 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3813 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3817 (define_insn "negdi2_internal"
3818 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
3819 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3823 if (which_alternative == 0)
3824 return \"neg%.l %0\;negx%.l %0\";
3825 if (GET_CODE (operands[0]) == REG)
3826 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3828 operands[1] = adj_offsettable_operand (operands[0], 4);
3829 if (ADDRESS_REG_P (operands[0]))
3830 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3832 return \"neg%.l %1\;negx%.l %0\";
3835 (define_insn "negdi2_5200"
3836 [(set (match_operand:DI 0 "general_operand" "=d")
3837 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3841 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3842 return \"neg%.l %1\;negx%.l %0\";
3845 (define_expand "negsi2"
3846 [(set (match_operand:SI 0 "general_operand" "")
3847 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3852 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3854 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3858 (define_insn "negsi2_internal"
3859 [(set (match_operand:SI 0 "general_operand" "=dm")
3860 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3864 (define_insn "negsi2_5200"
3865 [(set (match_operand:SI 0 "general_operand" "=d")
3866 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3870 (define_insn "neghi2"
3871 [(set (match_operand:HI 0 "general_operand" "=dm")
3872 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3877 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3878 (neg:HI (match_dup 0)))]
3882 (define_insn "negqi2"
3883 [(set (match_operand:QI 0 "general_operand" "=dm")
3884 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3889 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3890 (neg:QI (match_dup 0)))]
3894 ;; If using software floating point, just flip the sign bit.
3896 (define_expand "negsf2"
3897 [(set (match_operand:SF 0 "general_operand" "")
3898 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3902 if (!TARGET_FPA && !TARGET_68881)
3907 target = operand_subword_force (operands[0], 0, SFmode);
3908 result = expand_binop (SImode, xor_optab,
3909 operand_subword_force (operands[1], 0, SFmode),
3910 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3914 if (result != target)
3915 emit_move_insn (result, target);
3917 /* Make a place for REG_EQUAL. */
3918 emit_move_insn (operands[0], operands[0]);
3924 [(set (match_operand:SF 0 "general_operand" "=x,y")
3925 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3930 [(set (match_operand:SF 0 "general_operand" "=f,d")
3931 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3935 if (DATA_REG_P (operands[0]))
3937 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3938 return \"bchg %1,%0\";
3940 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3941 return \"f%$neg%.x %1,%0\";
3942 return \"f%$neg%.s %f1,%0\";
3945 (define_expand "negdf2"
3946 [(set (match_operand:DF 0 "general_operand" "")
3947 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3951 if (!TARGET_FPA && !TARGET_68881)
3958 target = operand_subword (operands[0], 0, 1, DFmode);
3959 result = expand_binop (SImode, xor_optab,
3960 operand_subword_force (operands[1], 0, DFmode),
3961 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3965 if (result != target)
3966 emit_move_insn (result, target);
3968 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3969 operand_subword_force (operands[1], 1, DFmode));
3971 insns = get_insns ();
3974 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3980 [(set (match_operand:DF 0 "general_operand" "=x,y")
3981 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3986 [(set (match_operand:DF 0 "general_operand" "=f,d")
3987 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3991 if (DATA_REG_P (operands[0]))
3993 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3994 return \"bchg %1,%0\";
3996 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3997 return \"f%&neg%.x %1,%0\";
3998 return \"f%&neg%.d %f1,%0\";
4001 ;; Sqrt instruction for the 68881
4003 (define_insn "sqrtsf2"
4004 [(set (match_operand:SF 0 "general_operand" "=f")
4005 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4009 if (FP_REG_P (operands[1]))
4010 return \"f%$sqrt%.x %1,%0\";
4012 return \"f%$sqrt%.s %1,%0\";
4015 (define_insn "sqrtdf2"
4016 [(set (match_operand:DF 0 "general_operand" "=f")
4017 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4021 if (FP_REG_P (operands[1]))
4022 return \"f%&sqrt%.x %1,%0\";
4024 return \"f%&sqrt%.d %1,%0\";
4027 ;; Absolute value instructions
4028 ;; If using software floating point, just zero the sign bit.
4030 (define_expand "abssf2"
4031 [(set (match_operand:SF 0 "general_operand" "")
4032 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4036 if (!TARGET_FPA && !TARGET_68881)
4041 target = operand_subword_force (operands[0], 0, SFmode);
4042 result = expand_binop (SImode, and_optab,
4043 operand_subword_force (operands[1], 0, SFmode),
4044 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4048 if (result != target)
4049 emit_move_insn (result, target);
4051 /* Make a place for REG_EQUAL. */
4052 emit_move_insn (operands[0], operands[0]);
4058 [(set (match_operand:SF 0 "general_operand" "=x,y")
4059 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4064 [(set (match_operand:SF 0 "general_operand" "=f")
4065 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4069 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4070 return \"f%$abs%.x %1,%0\";
4071 return \"f%$abs%.s %f1,%0\";
4074 (define_expand "absdf2"
4075 [(set (match_operand:DF 0 "general_operand" "")
4076 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4080 if (!TARGET_FPA && !TARGET_68881)
4087 target = operand_subword (operands[0], 0, 1, DFmode);
4088 result = expand_binop (SImode, and_optab,
4089 operand_subword_force (operands[1], 0, DFmode),
4090 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4094 if (result != target)
4095 emit_move_insn (result, target);
4097 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4098 operand_subword_force (operands[1], 1, DFmode));
4100 insns = get_insns ();
4103 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4109 [(set (match_operand:DF 0 "general_operand" "=x,y")
4110 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4115 [(set (match_operand:DF 0 "general_operand" "=f")
4116 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4120 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4121 return \"f%&abs%.x %1,%0\";
4122 return \"f%&abs%.d %f1,%0\";
4125 ;; one complement instructions
4127 ;; "one_cmpldi2" is only here to help combine().
4128 (define_insn "one_cmpldi2"
4129 [(set (match_operand:DI 0 "general_operand" "=dm")
4130 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4135 if (GET_CODE (operands[0]) == REG)
4136 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4137 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4138 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4139 operands[1] = operands[0];
4141 operands[1] = adj_offsettable_operand (operands[0], 4);
4142 return \"not%.l %1\;not%.l %0\";
4145 (define_expand "one_cmplsi2"
4146 [(set (match_operand:SI 0 "general_operand" "")
4147 (not:SI (match_operand:SI 1 "general_operand" "")))]
4152 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4154 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4158 (define_insn "one_cmplsi2_internal"
4159 [(set (match_operand:SI 0 "general_operand" "=dm")
4160 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4164 (define_insn "one_cmplsi2_5200"
4165 [(set (match_operand:SI 0 "general_operand" "=d")
4166 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4170 (define_insn "one_cmplhi2"
4171 [(set (match_operand:HI 0 "general_operand" "=dm")
4172 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4177 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4178 (not:HI (match_dup 0)))]
4182 (define_insn "one_cmplqi2"
4183 [(set (match_operand:QI 0 "general_operand" "=dm")
4184 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4189 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4190 (not:QI (match_dup 0)))]
4194 ;; arithmetic shift instructions
4195 ;; We don't need the shift memory by 1 bit instruction
4197 (define_insn "ashldi_extsi"
4198 [(set (match_operand:DI 0 "general_operand" "=ro")
4200 (match_operator:DI 2 "extend_operator"
4201 [(match_operand:SI 1 "general_operand" "rm")])
4207 if (GET_CODE (operands[0]) == REG)
4208 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4210 operands[2] = adj_offsettable_operand (operands[0], 4);
4211 if (ADDRESS_REG_P (operands[0]))
4212 return \"move%.l %1,%0\;sub%.l %2,%2\";
4214 return \"move%.l %1,%0\;clr%.l %2\";
4217 (define_insn "ashldi_sexthi"
4218 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4219 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4221 (clobber (match_scratch:SI 2 "=a,X"))]
4226 if (GET_CODE (operands[0]) == MEM)
4228 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4229 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4230 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4231 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4234 operands[3] = adj_offsettable_operand (operands[0], 4);
4235 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4238 else if (DATA_REG_P (operands[0]))
4239 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4241 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4244 (define_insn "ashldi_const32"
4245 [(set (match_operand:DI 0 "general_operand" "=rm")
4246 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4252 if (GET_CODE (operands[1]) == REG)
4253 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4255 operands[3] = adj_offsettable_operand (operands[1], 4);
4256 if (GET_CODE (operands[0]) == REG)
4257 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4258 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4259 return \"clr%.l %0\;move%.l %3,%0\";
4260 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4261 return \"move%.l %3,%0\;clr%.l %0\";
4263 operands[2] = adj_offsettable_operand (operands[0], 4);
4264 if (ADDRESS_REG_P (operands[2]))
4265 return \"move%.l %3,%0\;sub%.l %2,%2\";
4267 return \"move%.l %3,%0\;clr%.l %2\";
4270 ;; The predicate below must be general_operand, because ashldi3 allows that
4271 (define_insn "ashldi_const"
4272 [(set (match_operand:DI 0 "general_operand" "=d")
4273 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4274 (match_operand 2 "const_int_operand" "n")))]
4275 "(INTVAL (operands[2]) == 1
4276 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4277 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4280 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4281 if (INTVAL (operands[2]) == 1)
4282 return \"add%.l %1,%1\;addx%.l %0,%0\";
4283 else if (INTVAL (operands[2]) == 8)
4284 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4285 else if (INTVAL (operands[2]) == 16)
4286 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4287 else if (INTVAL (operands[2]) == 2)
4288 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4289 else/* if (INTVAL (operands[2]) == 3)*/
4290 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4293 (define_expand "ashldi3"
4294 [(set (match_operand:DI 0 "general_operand" "")
4295 (ashift:DI (match_operand:DI 1 "general_operand" "")
4296 (match_operand 2 "const_int_operand" "")))]
4300 if (GET_CODE (operands[2]) != CONST_INT
4301 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4302 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4303 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4307 ;; On most 68k models, this makes faster code in a special case.
4309 (define_insn "ashlsi_16"
4310 [(set (match_operand:SI 0 "register_operand" "=d")
4311 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4317 return \"swap %0\;clr%.w %0\";
4320 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4321 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4323 ;; On the 68000, this makes faster code in a special case.
4325 (define_insn "ashlsi_17_24"
4326 [(set (match_operand:SI 0 "register_operand" "=d")
4327 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4328 (match_operand:SI 2 "const_int_operand" "n")))]
4329 "(! TARGET_68020 && !TARGET_5200
4330 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4335 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4336 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4339 (define_insn "ashlsi3"
4340 [(set (match_operand:SI 0 "register_operand" "=d")
4341 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4342 (match_operand:SI 2 "general_operand" "dI")))]
4346 if (operands[2] == const1_rtx)
4348 cc_status.flags = CC_NO_OVERFLOW;
4349 return \"add%.l %0,%0\";
4351 return \"lsl%.l %2,%0\";
4354 (define_insn "ashlhi3"
4355 [(set (match_operand:HI 0 "register_operand" "=d")
4356 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4357 (match_operand:HI 2 "general_operand" "dI")))]
4362 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4363 (ashift:HI (match_dup 0)
4364 (match_operand:HI 1 "general_operand" "dI")))]
4368 (define_insn "ashlqi3"
4369 [(set (match_operand:QI 0 "register_operand" "=d")
4370 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4371 (match_operand:QI 2 "general_operand" "dI")))]
4376 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4377 (ashift:QI (match_dup 0)
4378 (match_operand:QI 1 "general_operand" "dI")))]
4382 ;; On most 68k models, this makes faster code in a special case.
4384 (define_insn "ashrsi_16"
4385 [(set (match_operand:SI 0 "register_operand" "=d")
4386 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4389 "swap %0\;ext%.l %0")
4391 ;; On the 68000, this makes faster code in a special case.
4394 [(set (match_operand:SI 0 "register_operand" "=d")
4395 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4396 (match_operand:SI 2 "const_int_operand" "n")))]
4397 "(! TARGET_68020 && !TARGET_5200
4398 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4401 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4402 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4405 (define_insn "subreghi1ashrdi_const32"
4406 [(set (match_operand:HI 0 "general_operand" "=rm")
4407 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4408 (const_int 32)) 1))]
4412 if (GET_CODE (operands[1]) != REG)
4413 operands[1] = adj_offsettable_operand (operands[1], 2);
4414 return \"move%.w %1,%0\";
4417 (define_insn "subregsi1ashrdi_const32"
4418 [(set (match_operand:SI 0 "general_operand" "=rm")
4419 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4420 (const_int 32)) 1))]
4424 return \"move%.l %1,%0\";
4427 (define_insn "ashrdi_const32"
4428 [(set (match_operand:DI 0 "register_operand" "=d")
4429 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4435 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4437 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4439 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4442 (define_insn "ashrdi_const32_mem"
4443 [(set (match_operand:DI 0 "general_operand" "=o,<")
4444 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4446 (clobber (match_scratch:SI 2 "=d,d"))]
4451 if (which_alternative == 1)
4452 operands[3] = operands[0];
4454 operands[3] = adj_offsettable_operand (operands[0], 4);
4456 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4458 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4461 ;; The predicate below must be general_operand, because ashrdi3 allows that
4462 (define_insn "ashrdi_const"
4463 [(set (match_operand:DI 0 "general_operand" "=d")
4464 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4465 (match_operand 2 "const_int_operand" "n")))]
4467 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4468 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4469 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31
4470 || INTVAL (operands[2]) == 63))"
4473 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4474 if (INTVAL (operands[2]) == 63)
4475 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4477 if (INTVAL (operands[2]) == 1)
4478 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4479 else if (INTVAL (operands[2]) == 8)
4480 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4481 else if (INTVAL (operands[2]) == 16)
4482 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4483 else if (INTVAL (operands[2]) == 31)
4484 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4485 else if (INTVAL (operands[2]) == 2)
4486 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4487 else/* if (INTVAL (operands[2]) == 3)*/
4488 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4491 (define_expand "ashrdi3"
4492 [(set (match_operand:DI 0 "general_operand" "")
4493 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4494 (match_operand 2 "const_int_operand" "")))]
4498 if (GET_CODE (operands[2]) != CONST_INT
4499 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4500 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4501 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 31
4502 && INTVAL (operands[2]) != 32 && INTVAL (operands[2]) != 63))
4506 ;; On all 68k models, this makes faster code in a special case.
4508 (define_insn "ashrsi_31"
4509 [(set (match_operand:SI 0 "register_operand" "=d")
4510 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4515 return \"add%.l %0,%0\;subx%.l %0,%0\";
4518 (define_insn "ashrsi3"
4519 [(set (match_operand:SI 0 "register_operand" "=d")
4520 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4521 (match_operand:SI 2 "general_operand" "dI")))]
4525 (define_insn "ashrhi3"
4526 [(set (match_operand:HI 0 "register_operand" "=d")
4527 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4528 (match_operand:HI 2 "general_operand" "dI")))]
4533 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4534 (ashiftrt:HI (match_dup 0)
4535 (match_operand:HI 1 "general_operand" "dI")))]
4539 (define_insn "ashrqi3"
4540 [(set (match_operand:QI 0 "register_operand" "=d")
4541 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4542 (match_operand:QI 2 "general_operand" "dI")))]
4547 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4548 (ashiftrt:QI (match_dup 0)
4549 (match_operand:QI 1 "general_operand" "dI")))]
4553 ;; logical shift instructions
4555 ;; commented out because of reload problems in 950612-1.c
4558 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4559 ;; (const_int 32)) 1))
4560 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4561 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4562 ;; (const_int 32)) 1))]
4566 ;; return \"move%.l %0,%1\";
4571 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4572 ;; (const_int 32)) 0))
4573 ;; (set (match_operand:DI 1 "general_operand" "=do")
4574 ;; (lshiftrt:DI (match_dup 0)
4575 ;; (const_int 32)))]
4579 ;; if (GET_CODE (operands[1]) == REG)
4580 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4582 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4583 ;; return \"move%.l %0,%2\;clr%.l %1\";
4586 (define_insn "subreg1lshrdi_const32"
4587 [(set (match_operand:SI 0 "general_operand" "=rm")
4588 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4589 (const_int 32)) 1))]
4593 return \"move%.l %1,%0\";
4596 (define_insn "lshrdi_const32"
4597 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4598 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4604 if (which_alternative == 1)
4605 return \"move%.l %1,%0\;clr%.l %0\";
4606 if (which_alternative == 2)
4607 return \"clr%.l %0\;move%.l %1,%0\";
4608 if (GET_CODE (operands[0]) == REG)
4609 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4611 operands[2] = adj_offsettable_operand (operands[0], 4);
4612 if (GET_CODE (operands[1]) == REG)
4613 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4615 operands[3] = adj_offsettable_operand (operands[1], 4);
4616 if (ADDRESS_REG_P (operands[0]))
4617 return \"move%.l %1,%2\;sub%.l %0,%0\";
4619 return \"move%.l %1,%2\;clr%.l %0\";
4622 ;; The predicate below must be general_operand, because lshrdi3 allows that
4623 (define_insn "lshrdi_const"
4624 [(set (match_operand:DI 0 "general_operand" "=d")
4625 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4626 (match_operand 2 "const_int_operand" "n")))]
4628 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4629 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4630 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4633 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4634 if (INTVAL (operands[2]) == 63)
4635 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4637 if (INTVAL (operands[2]) == 1)
4638 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4639 else if (INTVAL (operands[2]) == 8)
4640 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4641 else if (INTVAL (operands[2]) == 16)
4642 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4643 else if (INTVAL (operands[2]) == 2)
4644 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4645 else /*if (INTVAL (operands[2]) == 3)*/
4646 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4649 (define_expand "lshrdi3"
4650 [(set (match_operand:DI 0 "general_operand" "")
4651 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4652 (match_operand 2 "const_int_operand" "")))]
4656 if (GET_CODE (operands[2]) != CONST_INT
4657 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4658 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4659 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4660 && INTVAL (operands[2]) != 63))
4664 ;; On all 68k models, this makes faster code in a special case.
4666 (define_insn "lshrsi_31"
4667 [(set (match_operand:SI 0 "register_operand" "=d")
4668 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4673 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4676 ;; On most 68k models, this makes faster code in a special case.
4678 (define_insn "lshrsi_16"
4679 [(set (match_operand:SI 0 "register_operand" "=d")
4680 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4686 return \"clr%.w %0\;swap %0\";
4689 ;; On the 68000, this makes faster code in a special case.
4691 (define_insn "lshrsi_17_24"
4692 [(set (match_operand:SI 0 "register_operand" "=d")
4693 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4694 (match_operand:SI 2 "const_int_operand" "n")))]
4695 "(! TARGET_68020 && !TARGET_5200
4696 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4699 /* I think lsr%.w sets the CC properly. */
4700 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4701 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4704 (define_insn "lshrsi3"
4705 [(set (match_operand:SI 0 "register_operand" "=d")
4706 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4707 (match_operand:SI 2 "general_operand" "dI")))]
4711 (define_insn "lshrhi3"
4712 [(set (match_operand:HI 0 "register_operand" "=d")
4713 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4714 (match_operand:HI 2 "general_operand" "dI")))]
4719 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4720 (lshiftrt:HI (match_dup 0)
4721 (match_operand:HI 1 "general_operand" "dI")))]
4725 (define_insn "lshrqi3"
4726 [(set (match_operand:QI 0 "register_operand" "=d")
4727 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4728 (match_operand:QI 2 "general_operand" "dI")))]
4733 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4734 (lshiftrt:QI (match_dup 0)
4735 (match_operand:QI 1 "general_operand" "dI")))]
4739 ;; rotate instructions
4741 (define_insn "rotlsi3"
4742 [(set (match_operand:SI 0 "register_operand" "=d")
4743 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4744 (match_operand:SI 2 "general_operand" "dINO")))]
4748 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4750 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4752 INTVAL (operands[2]) = 32 - INTVAL (operands[2]);
4753 return \"ror%.l %2,%0\";
4756 return \"rol%.l %2,%0\";
4759 (define_insn "rotlhi3"
4760 [(set (match_operand:HI 0 "register_operand" "=d")
4761 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4762 (match_operand:HI 2 "general_operand" "dIP")))]
4766 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4768 INTVAL (operands[2]) = 16 - INTVAL (operands[2]);
4769 return \"ror%.w %2,%0\";
4772 return \"rol%.w %2,%0\";
4776 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4777 (rotate:HI (match_dup 0)
4778 (match_operand:HI 1 "general_operand" "dIP")))]
4782 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4784 INTVAL (operands[2]) = 16 - INTVAL (operands[2]);
4785 return \"ror%.w %2,%0\";
4788 return \"rol%.w %2,%0\";
4791 (define_insn "rotlqi3"
4792 [(set (match_operand:QI 0 "register_operand" "=d")
4793 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4794 (match_operand:QI 2 "general_operand" "dI")))]
4798 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4800 INTVAL (operands[2]) = 8 - INTVAL (operands[2]);
4801 return \"ror%.b %2,%0\";
4804 return \"rol%.b %2,%0\";
4808 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4809 (rotate:QI (match_dup 0)
4810 (match_operand:QI 1 "general_operand" "dI")))]
4814 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4816 INTVAL (operands[2]) = 8 - INTVAL (operands[2]);
4817 return \"ror%.b %2,%0\";
4820 return \"rol%.b %2,%0\";
4823 (define_insn "rotrsi3"
4824 [(set (match_operand:SI 0 "register_operand" "=d")
4825 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4826 (match_operand:SI 2 "general_operand" "dI")))]
4830 (define_insn "rotrhi3"
4831 [(set (match_operand:HI 0 "register_operand" "=d")
4832 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4833 (match_operand:HI 2 "general_operand" "dI")))]
4838 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4839 (rotatert:HI (match_dup 0)
4840 (match_operand:HI 1 "general_operand" "dI")))]
4844 (define_insn "rotrqi3"
4845 [(set (match_operand:QI 0 "register_operand" "=d")
4846 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4847 (match_operand:QI 2 "general_operand" "dI")))]
4852 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4853 (rotatert:QI (match_dup 0)
4854 (match_operand:QI 1 "general_operand" "dI")))]
4859 ;; Bit set/clear in memory byte.
4861 ;; set bit, bit number is int
4862 (define_insn "bsetmemqi"
4863 [(set (match_operand:QI 0 "memory_operand" "+m")
4864 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4865 (match_operand:SI 1 "general_operand" "d")) 0)
4871 return \"bset %1,%0\";
4874 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4876 [(set (match_operand:QI 0 "memory_operand" "+m")
4877 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4878 (match_operator:SI 2 "extend_operator"
4879 [(match_operand 1 "general_operand" "d")])) 0)
4885 return \"bset %1,%0\";
4888 ;; clear bit, bit number is int
4889 (define_insn "bclrmemqi"
4890 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4892 (minus:SI (const_int 7)
4893 (match_operand:SI 1 "general_operand" "d")))
4899 return \"bclr %1,%0\";
4902 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4904 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4906 (minus:SI (const_int 7)
4907 (match_operator:SI 2 "extend_operator"
4908 [(match_operand 1 "general_operand" "d")])))
4914 return \"bclr %1,%0\";
4917 ;; Special cases of bit-field insns which we should
4918 ;; recognize in preference to the general case.
4919 ;; These handle aligned 8-bit and 16-bit fields,
4920 ;; which can usually be done with move instructions.
4923 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4924 ; alignment of structure members is specified.
4926 ; The move is allowed to be odd byte aligned, because that's still faster
4927 ; than an odd byte aligned bit field instruction.
4930 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4932 (match_operand:SI 2 "const_int_operand" "n"))
4933 (match_operand:SI 3 "general_operand" "rmi"))]
4934 "TARGET_68020 && TARGET_BITFIELD
4935 && (INTVAL (operands[2]) % 8) == 0
4936 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4940 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4942 return \"move%.l %3,%0\";
4946 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4947 (match_operand:SI 1 "const_int_operand" "n")
4948 (match_operand:SI 2 "const_int_operand" "n"))
4949 (match_operand:SI 3 "register_operand" "d"))]
4950 "TARGET_68020 && TARGET_BITFIELD
4951 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4952 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4953 && (GET_CODE (operands[0]) == REG
4954 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4957 if (REG_P (operands[0]))
4959 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4960 return \"bfins %3,%0{%b2:%b1}\";
4964 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4966 if (GET_CODE (operands[3]) == MEM)
4967 operands[3] = adj_offsettable_operand (operands[3],
4968 (32 - INTVAL (operands[1])) / 8);
4969 if (INTVAL (operands[1]) == 8)
4970 return \"move%.b %3,%0\";
4971 return \"move%.w %3,%0\";
4976 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4977 ; alignment of structure members is specified.
4979 ; The move is allowed to be odd byte aligned, because that's still faster
4980 ; than an odd byte aligned bit field instruction.
4983 [(set (match_operand:SI 0 "general_operand" "=rm")
4984 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
4986 (match_operand:SI 3 "const_int_operand" "n")))]
4987 "TARGET_68020 && TARGET_BITFIELD
4988 && (INTVAL (operands[3]) % 8) == 0
4989 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4993 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4995 return \"move%.l %1,%0\";
4999 [(set (match_operand:SI 0 "general_operand" "=&d")
5000 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5001 (match_operand:SI 2 "const_int_operand" "n")
5002 (match_operand:SI 3 "const_int_operand" "n")))]
5003 "TARGET_68020 && TARGET_BITFIELD
5004 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5005 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5006 && (GET_CODE (operands[1]) == REG
5007 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5010 cc_status.flags |= CC_NOT_NEGATIVE;
5011 if (REG_P (operands[1]))
5013 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5014 return \"bfextu %1{%b3:%b2},%0\";
5018 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5020 output_asm_insn (\"clr%.l %0\", operands);
5021 if (GET_CODE (operands[0]) == MEM)
5022 operands[0] = adj_offsettable_operand (operands[0],
5023 (32 - INTVAL (operands[1])) / 8);
5024 if (INTVAL (operands[2]) == 8)
5025 return \"move%.b %1,%0\";
5026 return \"move%.w %1,%0\";
5030 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5031 ; alignment of structure members is specified.
5033 ; The move is allowed to be odd byte aligned, because that's still faster
5034 ; than an odd byte aligned bit field instruction.
5037 [(set (match_operand:SI 0 "general_operand" "=rm")
5038 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5040 (match_operand:SI 3 "const_int_operand" "n")))]
5041 "TARGET_68020 && TARGET_BITFIELD
5042 && (INTVAL (operands[3]) % 8) == 0
5043 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5047 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5049 return \"move%.l %1,%0\";
5053 [(set (match_operand:SI 0 "general_operand" "=d")
5054 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5055 (match_operand:SI 2 "const_int_operand" "n")
5056 (match_operand:SI 3 "const_int_operand" "n")))]
5057 "TARGET_68020 && TARGET_BITFIELD
5058 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5059 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5060 && (GET_CODE (operands[1]) == REG
5061 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5064 if (REG_P (operands[1]))
5066 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5067 return \"bfexts %1{%b3:%b2},%0\";
5071 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5073 if (INTVAL (operands[2]) == 8)
5074 return \"move%.b %1,%0\;extb%.l %0\";
5075 return \"move%.w %1,%0\;ext%.l %0\";
5078 ;; Bit field instructions, general cases.
5079 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5080 ;; so that its address is reloaded.
5082 (define_expand "extv"
5083 [(set (match_operand:SI 0 "general_operand" "")
5084 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5085 (match_operand:SI 2 "general_operand" "")
5086 (match_operand:SI 3 "general_operand" "")))]
5087 "TARGET_68020 && TARGET_BITFIELD"
5091 [(set (match_operand:SI 0 "general_operand" "=d")
5092 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5093 (match_operand:SI 2 "general_operand" "di")
5094 (match_operand:SI 3 "general_operand" "di")))]
5095 "TARGET_68020 && TARGET_BITFIELD"
5096 "bfexts %1{%b3:%b2},%0")
5098 (define_expand "extzv"
5099 [(set (match_operand:SI 0 "general_operand" "")
5100 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5101 (match_operand:SI 2 "general_operand" "")
5102 (match_operand:SI 3 "general_operand" "")))]
5103 "TARGET_68020 && TARGET_BITFIELD"
5107 [(set (match_operand:SI 0 "general_operand" "=d,d")
5108 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5109 (match_operand:SI 2 "general_operand" "di,di")
5110 (match_operand:SI 3 "general_operand" "di,di")))]
5111 "TARGET_68020 && TARGET_BITFIELD"
5114 if (GET_CODE (operands[2]) == CONST_INT)
5116 if (INTVAL (operands[2]) != 32)
5117 cc_status.flags |= CC_NOT_NEGATIVE;
5123 return \"bfextu %1{%b3:%b2},%0\";
5127 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5128 (match_operand:SI 1 "general_operand" "di")
5129 (match_operand:SI 2 "general_operand" "di"))
5130 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5131 (match_operand 3 "const_int_operand" "n")))]
5132 "TARGET_68020 && TARGET_BITFIELD
5133 && (INTVAL (operands[3]) == -1
5134 || (GET_CODE (operands[1]) == CONST_INT
5135 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5139 return \"bfchg %0{%b2:%b1}\";
5143 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5144 (match_operand:SI 1 "general_operand" "di")
5145 (match_operand:SI 2 "general_operand" "di"))
5147 "TARGET_68020 && TARGET_BITFIELD"
5151 return \"bfclr %0{%b2:%b1}\";
5155 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5156 (match_operand:SI 1 "general_operand" "di")
5157 (match_operand:SI 2 "general_operand" "di"))
5159 "TARGET_68020 && TARGET_BITFIELD"
5163 return \"bfset %0{%b2:%b1}\";
5166 (define_expand "insv"
5167 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5168 (match_operand:SI 1 "general_operand" "")
5169 (match_operand:SI 2 "general_operand" ""))
5170 (match_operand:SI 3 "register_operand" ""))]
5171 "TARGET_68020 && TARGET_BITFIELD"
5175 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5176 (match_operand:SI 1 "general_operand" "di")
5177 (match_operand:SI 2 "general_operand" "di"))
5178 (match_operand:SI 3 "register_operand" "d"))]
5179 "TARGET_68020 && TARGET_BITFIELD"
5180 "bfins %3,%0{%b2:%b1}")
5182 ;; Now recognize bit field insns that operate on registers
5183 ;; (or at least were intended to do so).
5186 [(set (match_operand:SI 0 "general_operand" "=d")
5187 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5188 (match_operand:SI 2 "general_operand" "di")
5189 (match_operand:SI 3 "general_operand" "di")))]
5190 "TARGET_68020 && TARGET_BITFIELD"
5191 "bfexts %1{%b3:%b2},%0")
5194 [(set (match_operand:SI 0 "general_operand" "=d")
5195 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5196 (match_operand:SI 2 "general_operand" "di")
5197 (match_operand:SI 3 "general_operand" "di")))]
5198 "TARGET_68020 && TARGET_BITFIELD"
5201 if (GET_CODE (operands[2]) == CONST_INT)
5203 if (INTVAL (operands[2]) != 32)
5204 cc_status.flags |= CC_NOT_NEGATIVE;
5210 return \"bfextu %1{%b3:%b2},%0\";
5214 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5215 (match_operand:SI 1 "general_operand" "di")
5216 (match_operand:SI 2 "general_operand" "di"))
5218 "TARGET_68020 && TARGET_BITFIELD"
5222 return \"bfclr %0{%b2:%b1}\";
5226 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5227 (match_operand:SI 1 "general_operand" "di")
5228 (match_operand:SI 2 "general_operand" "di"))
5230 "TARGET_68020 && TARGET_BITFIELD"
5234 return \"bfset %0{%b2:%b1}\";
5238 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5239 (match_operand:SI 1 "general_operand" "di")
5240 (match_operand:SI 2 "general_operand" "di"))
5241 (match_operand:SI 3 "register_operand" "d"))]
5242 "TARGET_68020 && TARGET_BITFIELD"
5246 /* These special cases are now recognized by a specific pattern. */
5247 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5248 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5249 return \"move%.w %3,%0\";
5250 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5251 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5252 return \"move%.b %3,%0\";
5254 return \"bfins %3,%0{%b2:%b1}\";
5257 ;; Special patterns for optimizing bit-field instructions.
5261 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5262 (match_operand:SI 1 "const_int_operand" "n")
5263 (match_operand:SI 2 "general_operand" "di")))]
5264 "TARGET_68020 && TARGET_BITFIELD"
5267 if (operands[1] == const1_rtx
5268 && GET_CODE (operands[2]) == CONST_INT)
5270 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5271 return output_btst (operands,
5272 gen_rtx (CONST_INT, VOIDmode,
5273 width - INTVAL (operands[2])),
5276 /* Pass 1000 as SIGNPOS argument so that btst will
5277 not think we are testing the sign bit for an `and'
5278 and assume that nonzero implies a negative result. */
5280 if (INTVAL (operands[1]) != 32)
5281 cc_status.flags = CC_NOT_NEGATIVE;
5282 return \"bftst %0{%b2:%b1}\";
5286 ;;; now handle the register cases
5289 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5290 (match_operand:SI 1 "const_int_operand" "n")
5291 (match_operand:SI 2 "general_operand" "di")))]
5292 "TARGET_68020 && TARGET_BITFIELD"
5295 if (operands[1] == const1_rtx
5296 && GET_CODE (operands[2]) == CONST_INT)
5298 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5299 return output_btst (operands,
5300 gen_rtx (CONST_INT, VOIDmode,
5301 width - INTVAL (operands[2])),
5304 /* Pass 1000 as SIGNPOS argument so that btst will
5305 not think we are testing the sign bit for an `and'
5306 and assume that nonzero implies a negative result. */
5308 if (INTVAL (operands[1]) != 32)
5309 cc_status.flags = CC_NOT_NEGATIVE;
5310 return \"bftst %0{%b2:%b1}\";
5313 (define_insn "scc0_di"
5314 [(set (match_operand:QI 0 "general_operand" "=dm")
5315 (match_operator 1 "valid_dbcc_comparison_p"
5316 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5320 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5323 (define_insn "scc_di"
5324 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5325 (match_operator 1 "valid_dbcc_comparison_p"
5326 [(match_operand:DI 2 "general_operand" "ro,r")
5327 (match_operand:DI 3 "general_operand" "r,ro")]))]
5331 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5334 (define_expand "seq"
5335 [(set (match_operand:QI 0 "general_operand" "")
5336 (eq:QI (cc0) (const_int 0)))]
5340 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5342 m68k_last_compare_had_fp_operands = 0;
5348 [(set (match_operand:QI 0 "general_operand" "=dm")
5349 (eq:QI (cc0) (const_int 0)))]
5352 cc_status = cc_prev_status;
5353 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5356 (define_expand "sne"
5357 [(set (match_operand:QI 0 "general_operand" "")
5358 (ne:QI (cc0) (const_int 0)))]
5362 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5364 m68k_last_compare_had_fp_operands = 0;
5370 [(set (match_operand:QI 0 "general_operand" "=dm")
5371 (ne:QI (cc0) (const_int 0)))]
5374 cc_status = cc_prev_status;
5375 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5378 (define_expand "sgt"
5379 [(set (match_operand:QI 0 "general_operand" "")
5380 (gt:QI (cc0) (const_int 0)))]
5384 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5386 m68k_last_compare_had_fp_operands = 0;
5392 [(set (match_operand:QI 0 "general_operand" "=dm")
5393 (gt:QI (cc0) (const_int 0)))]
5396 cc_status = cc_prev_status;
5397 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5401 [(set (match_operand:QI 0 "general_operand" "=dm")
5402 (gtu:QI (cc0) (const_int 0)))]
5404 "* cc_status = cc_prev_status;
5405 return \"shi %0\"; ")
5407 (define_expand "slt"
5408 [(set (match_operand:QI 0 "general_operand" "")
5409 (lt:QI (cc0) (const_int 0)))]
5413 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5415 m68k_last_compare_had_fp_operands = 0;
5421 [(set (match_operand:QI 0 "general_operand" "=dm")
5422 (lt:QI (cc0) (const_int 0)))]
5424 "* cc_status = cc_prev_status;
5425 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5428 [(set (match_operand:QI 0 "general_operand" "=dm")
5429 (ltu:QI (cc0) (const_int 0)))]
5431 "* cc_status = cc_prev_status;
5432 return \"scs %0\"; ")
5434 (define_expand "sge"
5435 [(set (match_operand:QI 0 "general_operand" "")
5436 (ge:QI (cc0) (const_int 0)))]
5440 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5442 m68k_last_compare_had_fp_operands = 0;
5448 [(set (match_operand:QI 0 "general_operand" "=dm")
5449 (ge:QI (cc0) (const_int 0)))]
5451 "* cc_status = cc_prev_status;
5452 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5455 [(set (match_operand:QI 0 "general_operand" "=dm")
5456 (geu:QI (cc0) (const_int 0)))]
5458 "* cc_status = cc_prev_status;
5459 return \"scc %0\"; ")
5461 (define_expand "sle"
5462 [(set (match_operand:QI 0 "general_operand" "")
5463 (le:QI (cc0) (const_int 0)))]
5467 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5469 m68k_last_compare_had_fp_operands = 0;
5475 [(set (match_operand:QI 0 "general_operand" "=dm")
5476 (le:QI (cc0) (const_int 0)))]
5479 cc_status = cc_prev_status;
5480 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5484 [(set (match_operand:QI 0 "general_operand" "=dm")
5485 (leu:QI (cc0) (const_int 0)))]
5487 "* cc_status = cc_prev_status;
5488 return \"sls %0\"; ")
5490 ;; Basic conditional jump instructions.
5492 (define_insn "beq0_di"
5494 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5496 (label_ref (match_operand 1 "" ","))
5498 (clobber (match_scratch:SI 2 "=d,d"))]
5503 if (which_alternative == 1)
5505 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5507 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5509 if ((cc_prev_status.value1
5510 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5511 || (cc_prev_status.value2
5512 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5514 cc_status = cc_prev_status;
5516 return \"jbeq %l1\";
5521 if (GET_CODE (operands[0]) == REG)
5522 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5524 operands[3] = adj_offsettable_operand (operands[0], 4);
5525 if (! ADDRESS_REG_P (operands[0]))
5527 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5529 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5531 operands[4] = gen_label_rtx();
5532 if (TARGET_68020 || TARGET_5200)
5534 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5536 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5540 #ifdef SGS_CMP_ORDER
5541 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5543 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5546 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5548 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5549 CODE_LABEL_NUMBER (operands[4]));
5553 (define_insn "bne0_di"
5555 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5557 (label_ref (match_operand 1 "" ","))
5559 (clobber (match_scratch:SI 2 "=d,X"))]
5563 if ((cc_prev_status.value1
5564 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5565 || (cc_prev_status.value2
5566 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5568 cc_status = cc_prev_status;
5570 return \"jbne %l1\";
5576 if (GET_CODE (operands[0]) == REG)
5577 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5579 operands[3] = adj_offsettable_operand (operands[0], 4);
5580 if (!ADDRESS_REG_P (operands[0]))
5582 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5584 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5586 if (TARGET_68020 || TARGET_5200)
5588 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5590 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5594 #ifdef SGS_CMP_ORDER
5595 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5597 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5600 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5604 (define_insn "bge0_di"
5606 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5608 (label_ref (match_operand 1 "" ""))
5613 if ((cc_prev_status.value1
5614 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5615 || (cc_prev_status.value2
5616 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5618 cc_status = cc_prev_status;
5619 if (cc_status.flags & CC_REVERSED)
5622 return \"jble %l1\";
5630 return \"jbpl %l1\";
5637 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5638 output_asm_insn(\"tst%.l %0\", operands);
5640 /* On an address reg, cmpw may replace cmpl. */
5641 #ifdef SGS_CMP_ORDER
5642 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5644 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5648 return \"jbpl %l1\";
5654 (define_insn "blt0_di"
5656 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5658 (label_ref (match_operand 1 "" ""))
5663 if ((cc_prev_status.value1
5664 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5665 || (cc_prev_status.value2
5666 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5668 cc_status = cc_prev_status;
5669 if (cc_status.flags & CC_REVERSED)
5672 return \"jbgt %l1\";
5680 return \"jbmi %l1\";
5687 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5688 output_asm_insn(\"tst%.l %0\", operands);
5690 /* On an address reg, cmpw may replace cmpl. */
5691 #ifdef SGS_CMP_ORDER
5692 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5694 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5698 return \"jbmi %l1\";
5706 (if_then_else (eq (cc0)
5708 (label_ref (match_operand 0 "" ""))
5714 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5716 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5722 (if_then_else (ne (cc0)
5724 (label_ref (match_operand 0 "" ""))
5730 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5732 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5738 (if_then_else (gt (cc0)
5740 (label_ref (match_operand 0 "" ""))
5745 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5747 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5753 (if_then_else (gtu (cc0)
5755 (label_ref (match_operand 0 "" ""))
5760 return \"jbhi %l0\";
5768 (if_then_else (lt (cc0)
5770 (label_ref (match_operand 0 "" ""))
5775 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5777 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5783 (if_then_else (ltu (cc0)
5785 (label_ref (match_operand 0 "" ""))
5790 return \"jbcs %l0\";
5798 (if_then_else (ge (cc0)
5800 (label_ref (match_operand 0 "" ""))
5805 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
5807 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
5813 (if_then_else (geu (cc0)
5815 (label_ref (match_operand 0 "" ""))
5820 return \"jbcc %l0\";
5828 (if_then_else (le (cc0)
5830 (label_ref (match_operand 0 "" ""))
5835 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5837 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5843 (if_then_else (leu (cc0)
5845 (label_ref (match_operand 0 "" ""))
5850 return \"jbls %l0\";
5856 ;; Negated conditional jump instructions.
5860 (if_then_else (eq (cc0)
5863 (label_ref (match_operand 0 "" ""))))]
5868 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5870 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5876 (if_then_else (ne (cc0)
5879 (label_ref (match_operand 0 "" ""))))]
5884 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5886 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5892 (if_then_else (gt (cc0)
5895 (label_ref (match_operand 0 "" ""))))]
5899 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
5901 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
5907 (if_then_else (gtu (cc0)
5910 (label_ref (match_operand 0 "" ""))))]
5914 return \"jbls %l0\";
5922 (if_then_else (lt (cc0)
5925 (label_ref (match_operand 0 "" ""))))]
5929 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
5931 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
5937 (if_then_else (ltu (cc0)
5940 (label_ref (match_operand 0 "" ""))))]
5944 return \"jbcc %l0\";
5952 (if_then_else (ge (cc0)
5955 (label_ref (match_operand 0 "" ""))))]
5959 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
5961 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
5967 (if_then_else (geu (cc0)
5970 (label_ref (match_operand 0 "" ""))))]
5974 return \"jbcs %l0\";
5982 (if_then_else (le (cc0)
5985 (label_ref (match_operand 0 "" ""))))]
5989 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
5991 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
5997 (if_then_else (leu (cc0)
6000 (label_ref (match_operand 0 "" ""))))]
6004 return \"jbhi %l0\";
6010 ;; Unconditional and other jump instructions
6013 (label_ref (match_operand 0 "" "")))]
6017 return \"jbra %l0\";
6023 ;; We support two different ways of handling dispatch tables.
6024 ;; The NeXT uses absolute tables, and other machines use relative.
6025 ;; This define_expand can generate either kind.
6026 (define_expand "tablejump"
6027 [(parallel [(set (pc) (match_operand 0 "" ""))
6028 (use (label_ref (match_operand 1 "" "")))])]
6032 #ifdef CASE_VECTOR_PC_RELATIVE
6033 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
6034 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
6038 ;; Jump to variable address from dispatch table of absolute addresses.
6040 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6041 (use (label_ref (match_operand 1 "" "")))]
6045 return \"jmp (%0)\";
6051 ;; Jump to variable address from dispatch table of relative addresses.
6055 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6056 (use (label_ref (match_operand 1 "" "")))]
6059 #ifdef ASM_RETURN_CASE_JUMP
6060 ASM_RETURN_CASE_JUMP;
6063 #ifdef ASM_OUTPUT_CASE_LABEL
6064 return \"jmp 6(%%pc,%0.w)\";
6067 return \"jmp 2(pc,%0.w)\";
6069 return \"jmp 2(%%pc,%0.w)\";
6070 #endif /* end !CRDS */
6074 return \"jmp (2,pc,%0.w)\";
6076 return \"jmp pc@(2,%0:w)\";
6082 ;; Decrement-and-branch insns.
6086 (ne (match_operand:HI 0 "general_operand" "+d*g")
6088 (label_ref (match_operand 1 "" ""))
6091 (plus:HI (match_dup 0)
6097 if (DATA_REG_P (operands[0]))
6098 return \"dbra %0,%l1\";
6099 if (GET_CODE (operands[0]) == MEM)
6103 return \"sub%.w %#1,%0\;jbcc %l1\";
6105 return \"subq%.w %#1,%0\;jbcc %l1\";
6107 #else /* not MOTOROLA */
6108 return \"subqw %#1,%0\;jcc %l1\";
6112 #ifdef SGS_CMP_ORDER
6114 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6116 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6118 #else /* not SGS_CMP_ORDER */
6119 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6121 #else /* not MOTOROLA */
6122 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6129 (ne (match_operand:SI 0 "general_operand" "+d*g")
6131 (label_ref (match_operand 1 "" ""))
6134 (plus:SI (match_dup 0)
6142 if (DATA_REG_P (operands[0]))
6143 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6144 if (GET_CODE (operands[0]) == MEM)
6145 return \"sub%.l %#1,%0\;jbcc %l1\";
6147 if (DATA_REG_P (operands[0]))
6148 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6149 if (GET_CODE (operands[0]) == MEM)
6150 return \"subq%.l %#1,%0\;jbcc %l1\";
6151 #endif /* NO_ADDSUB_Q */
6152 #ifdef SGS_CMP_ORDER
6154 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6156 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6158 #else /* not SGS_CMP_ORDER */
6159 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6160 #endif /* not SGS_CMP_ORDER */
6161 #else /* not MOTOROLA */
6162 if (DATA_REG_P (operands[0]))
6163 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6164 if (GET_CODE (operands[0]) == MEM)
6165 return \"subql %#1,%0\;jcc %l1\";
6166 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6167 #endif /* not MOTOROLA */
6170 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6175 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6178 (label_ref (match_operand 1 "" ""))
6181 (plus:HI (match_dup 0)
6183 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6189 if (DATA_REG_P (operands[0]))
6190 return \"dbra %0,%l1\";
6191 if (GET_CODE (operands[0]) == MEM)
6192 return \"sub%.w %#1,%0\;jbcc %l1\";
6194 if (DATA_REG_P (operands[0]))
6195 return \"dbra %0,%l1\";
6196 if (GET_CODE (operands[0]) == MEM)
6197 return \"subq%.w %#1,%0\;jbcc %l1\";
6199 #ifdef SGS_CMP_ORDER
6201 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6203 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6205 #else /* not SGS_CMP_ORDER */
6206 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6207 #endif /* not SGS_CMP_ORDER */
6208 #else /* not MOTOROLA */
6209 if (DATA_REG_P (operands[0]))
6210 return \"dbra %0,%l1\";
6211 if (GET_CODE (operands[0]) == MEM)
6212 return \"subqw %#1,%0\;jcc %l1\";
6213 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6214 #endif /* not MOTOROLA */
6217 (define_expand "decrement_and_branch_until_zero"
6218 [(parallel [(set (pc)
6220 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6223 (label_ref (match_operand 1 "" ""))
6226 (plus:SI (match_dup 0)
6234 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6237 (label_ref (match_operand 1 "" ""))
6240 (plus:SI (match_dup 0)
6242 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6248 if (DATA_REG_P (operands[0]))
6249 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6250 if (GET_CODE (operands[0]) == MEM)
6251 return \"sub%.l %#1,%0\;jbcc %l1\";
6253 if (DATA_REG_P (operands[0]))
6254 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6255 if (GET_CODE (operands[0]) == MEM)
6256 return \"subq%.l %#1,%0\;jbcc %l1\";
6258 #ifdef SGS_CMP_ORDER
6260 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6262 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6264 #else /* not SGS_CMP_ORDER */
6265 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6266 #endif /* not SGS_CMP_ORDER */
6267 #else /* not MOTOROLA */
6268 if (DATA_REG_P (operands[0]))
6269 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6270 if (GET_CODE (operands[0]) == MEM)
6271 return \"subql %#1,%0\;jcc %l1\";
6272 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6273 #endif /* not MOTOROLA */
6277 ;; For PIC calls, in order to be able to support
6278 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6279 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6281 ;; PIC calls are handled by loading the address of the function into a
6282 ;; register (via movsi), then emitting a register indirect call using
6283 ;; the "jsr" function call syntax.
6285 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6286 ;; operand to the jbsr statement to indicate that this call should
6287 ;; go through the PLT (why? because this is the way that Sun does it).
6289 ;; We have different patterns for PIC calls and non-PIC calls. The
6290 ;; different patterns are only used to choose the right syntax.
6292 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6293 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6294 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6295 ;; section at link time. However, all global objects reference are still
6296 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6297 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6298 ;; We need to have a way to differentiate these two different operands.
6300 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6301 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6302 ;; to be changed to recognize function calls symbol_ref operand as a valid
6303 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6304 ;; avoid the compiler to load this symbol_ref operand into a register.
6305 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6306 ;; since the value is a PC relative offset, not a real address.
6308 ;; All global objects are treated in the similar way as in SUN3. The only
6309 ;; difference is: on m68k svr4, the reference of such global object needs
6310 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6311 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6314 ;; Call subroutine with no return value.
6315 (define_expand "call"
6316 [(call (match_operand:QI 0 "memory_operand" "")
6317 (match_operand:SI 1 "general_operand" ""))]
6318 ;; Operand 1 not really used on the m68000.
6323 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6324 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6327 ;; This is a normal call sequence.
6329 [(call (match_operand:QI 0 "memory_operand" "o")
6330 (match_operand:SI 1 "general_operand" "g"))]
6331 ;; Operand 1 not really used on the m68000.
6335 #if defined (MOTOROLA) && !defined (USE_GAS)
6337 if (GET_CODE (operands[0]) == MEM
6338 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6347 ;; This is a PIC call sequence.
6349 [(call (match_operand:QI 0 "memory_operand" "o")
6350 (match_operand:SI 1 "general_operand" "g"))]
6351 ;; Operand 1 not really used on the m68000.
6355 if (GET_CODE (operands[0]) == MEM
6356 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6359 return \"bsr.l %0\";
6362 return \"bsr.l %0@PLTPC\";
6364 return \"bsr %0@PLTPC\";
6368 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6369 GAS just plain ignores it. */
6370 return \"jbsr %0,a1\";
6375 ;; Call subroutine, returning value in operand 0
6376 ;; (which must be a hard register).
6377 ;; See comments before "call" regarding PIC calls.
6378 (define_expand "call_value"
6379 [(set (match_operand 0 "" "")
6380 (call (match_operand:QI 1 "memory_operand" "")
6381 (match_operand:SI 2 "general_operand" "")))]
6382 ;; Operand 2 not really used on the m68000.
6386 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6387 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6390 ;; This is a normal call_value
6392 [(set (match_operand 0 "" "=rf")
6393 (call (match_operand:QI 1 "memory_operand" "o")
6394 (match_operand:SI 2 "general_operand" "g")))]
6395 ;; Operand 2 not really used on the m68000.
6398 #if defined (MOTOROLA) && !defined (USE_GAS)
6400 if (GET_CODE (operands[1]) == MEM
6401 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6410 ;; This is a PIC call_value
6412 [(set (match_operand 0 "" "=rf")
6413 (call (match_operand:QI 1 "memory_operand" "o")
6414 (match_operand:SI 2 "general_operand" "g")))]
6415 ;; Operand 2 not really used on the m68000.
6418 if (GET_CODE (operands[1]) == MEM
6419 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6422 return \"bsr.l %1\";
6425 return \"bsr.l %1@PLTPC\";
6427 return \"bsr %1@PLTPC\";
6431 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6432 GAS just plain ignores it. */
6433 return \"jbsr %1,a1\";
6438 ;; Call subroutine returning any type.
6440 (define_expand "untyped_call"
6441 [(parallel [(call (match_operand 0 "" "")
6443 (match_operand 1 "" "")
6444 (match_operand 2 "" "")])]
6445 "NEEDS_UNTYPED_CALL"
6450 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6452 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6454 rtx set = XVECEXP (operands[2], 0, i);
6455 emit_move_insn (SET_DEST (set), SET_SRC (set));
6458 /* The optimizer does not know that the call sets the function value
6459 registers we stored in the result block. We avoid problems by
6460 claiming that all hard registers are used and clobbered at this
6462 emit_insn (gen_blockage ());
6467 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6468 ;; all of memory. This blocks insns from being moved across this point.
6470 (define_insn "blockage"
6471 [(unspec_volatile [(const_int 0)] 0)]
6480 (define_insn "probe"
6485 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6486 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6487 return \"tstl %a0\";
6490 ;; Used for frameless functions which save no regs and allocate no locals.
6491 (define_insn "return"
6496 if (current_function_pops_args == 0)
6498 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6502 (define_insn "indirect_jump"
6503 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6507 ;; This should not be used unless the add/sub insns can't be.
6510 [(set (match_operand:SI 0 "general_operand" "=a")
6511 (match_operand:QI 1 "address_operand" "p"))]
6516 /* Recognize an insn that refers to a table of offsets. Such an insn will
6517 need to refer to a label on the insn. So output one. Use the
6518 label-number of the table of offsets to generate this label. This code,
6519 and similar code above, assumes that there will be at most one reference
6521 if (GET_CODE (operands[1]) == PLUS
6522 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6523 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6525 rtx labelref = XEXP (operands[1], 1);
6526 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6528 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6529 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6531 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6532 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6533 #endif /* not SGS */
6534 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6535 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6536 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6537 #ifdef SGS_SWITCH_TABLES
6538 /* Set flag saying we need to define the symbol
6539 LD%n (with value L%n-LI%n) at the end of the switch table. */
6540 switch_table_difference_label_flag = 1;
6541 #endif /* SGS_SWITCH_TABLES */
6542 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6544 #endif /* SGS_NO_LI */
6546 return \"lea %a1,%0\";
6549 ;; This is the first machine-dependent peephole optimization.
6550 ;; It is useful when a floating value is returned from a function call
6551 ;; and then is moved into an FP register.
6552 ;; But it is mainly intended to test the support for these optimizations.
6555 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6556 (set (match_operand:DF 0 "register_operand" "=f")
6557 (match_operand:DF 1 "register_operand" "ad"))]
6558 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6562 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6563 output_asm_insn (\"move%.l %1,%@\", xoperands);
6564 output_asm_insn (\"move%.l %1,%-\", operands);
6565 return \"fmove%.d %+,%0\";
6569 ;; Optimize a stack-adjust followed by a push of an argument.
6570 ;; This is said to happen frequently with -msoft-float
6571 ;; when there are consecutive library calls.
6574 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6575 (match_operand:SI 0 "const_int_operand" "n")))
6576 (set (match_operand:SF 1 "push_operand" "=m")
6577 (match_operand:SF 2 "general_operand" "rmfF"))]
6578 "INTVAL (operands[0]) >= 4
6579 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6582 if (INTVAL (operands[0]) > 4)
6585 xoperands[0] = stack_pointer_rtx;
6586 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6588 if (INTVAL (xoperands[1]) <= 8)
6591 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6593 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6595 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6597 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6598 INTVAL (xoperands[1]) - 8);
6599 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6603 if (INTVAL (xoperands[1]) <= 0x7FFF)
6606 output_asm_insn (\"add%.w %1,%0\", xoperands);
6609 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6611 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6615 output_asm_insn (\"add%.l %1,%0\", xoperands);
6617 if (FP_REG_P (operands[2]))
6618 return \"fmove%.s %2,%@\";
6619 return \"move%.l %2,%@\";
6622 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6625 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6626 (match_operand:SI 0 "const_int_operand" "n")))
6627 (set (match_operand:SI 1 "push_operand" "=m")
6628 (match_operand:SI 2 "general_operand" "g"))]
6629 "INTVAL (operands[0]) >= 4
6630 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6633 if (INTVAL (operands[0]) > 4)
6636 xoperands[0] = stack_pointer_rtx;
6637 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6639 if (INTVAL (xoperands[1]) <= 8)
6642 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6644 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6646 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6648 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6649 INTVAL (xoperands[1]) - 8);
6650 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6654 if (INTVAL (xoperands[1]) <= 0x7FFF)
6657 output_asm_insn (\"add%.w %1,%0\", xoperands);
6660 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6662 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6666 output_asm_insn (\"add%.l %1,%0\", xoperands);
6668 if (operands[2] == const0_rtx)
6669 return \"clr%.l %@\";
6670 return \"move%.l %2,%@\";
6673 ;; Speed up pushing a single byte but leaving four bytes of space.
6676 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6677 (match_operand:QI 1 "general_operand" "dami"))
6678 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6679 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6684 if (GET_CODE (operands[1]) == REG)
6685 return \"move%.l %1,%-\";
6687 xoperands[1] = operands[1];
6689 = gen_rtx (MEM, QImode,
6690 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
6691 gen_rtx (CONST_INT, VOIDmode, 3)));
6692 xoperands[3] = stack_pointer_rtx;
6694 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6696 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
6701 [(set (match_operand:SI 0 "register_operand" "=d")
6703 (set (strict_low_part (subreg:HI (match_dup 0) 0))
6704 (match_operand:HI 1 "general_operand" "rmn"))]
6705 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6708 if (GET_CODE (operands[1]) == CONST_INT)
6710 if (operands[1] == const0_rtx
6711 && (DATA_REG_P (operands[0])
6712 || GET_CODE (operands[0]) == MEM)
6713 /* clr insns on 68000 read before writing.
6714 This isn't so on the 68010, but we have no TARGET_68010. */
6715 && ((TARGET_68020 || TARGET_5200)
6716 || !(GET_CODE (operands[0]) == MEM
6717 && MEM_VOLATILE_P (operands[0]))))
6718 return \"clr%.w %0\";
6720 return \"move%.w %1,%0\";
6728 ;; jCC label ; abnormal loop termination
6729 ;; dbra dN, loop ; normal loop termination
6737 ;; Which moves the jCC condition outside the inner loop for free.
6740 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6741 [(cc0) (const_int 0)])
6742 (label_ref (match_operand 2 "" ""))
6747 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
6750 (label_ref (match_operand 1 "" ""))
6753 (plus:HI (match_dup 0)
6755 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6759 output_dbcc_and_branch (operands);
6764 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6765 [(cc0) (const_int 0)])
6766 (label_ref (match_operand 2 "" ""))
6771 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
6774 (label_ref (match_operand 1 "" ""))
6777 (plus:SI (match_dup 0)
6779 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6783 output_dbcc_and_branch (operands);
6788 ;; FPA multiply and add.
6790 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6791 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
6792 (match_operand:DF 2 "general_operand" "xH,y,y"))
6793 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
6796 fpma%.d %1,%w2,%w3,%0
6797 fpma%.d %x1,%x2,%x3,%0
6798 fpma%.d %x1,%x2,%x3,%0")
6801 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6802 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
6803 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
6804 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
6807 fpma%.s %1,%w2,%w3,%0
6809 fpma%.s %1,%2,%3,%0")
6811 ;; FPA Multiply and subtract
6813 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6814 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6815 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
6816 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6819 fpms%.d %3,%w2,%w1,%0
6820 fpms%.d %x3,%2,%x1,%0
6821 fpms%.d %x3,%2,%x1,%0")
6824 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6825 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6826 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
6827 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6830 fpms%.s %3,%w2,%w1,%0
6832 fpms%.s %3,%2,%1,%0")
6835 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6836 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6837 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6838 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6841 fpmr%.d %2,%w1,%w3,%0
6842 fpmr%.d %x2,%1,%x3,%0
6843 fpmr%.d %x2,%1,%x3,%0")
6846 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6847 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6848 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6849 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6852 fpmr%.s %2,%w1,%w3,%0
6853 fpmr%.s %x2,%1,%x3,%0
6854 fpmr%.s %x2,%1,%x3,%0")
6856 ;; FPA Add and multiply
6858 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6859 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6860 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6861 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6864 fpam%.d %2,%w1,%w3,%0
6865 fpam%.d %x2,%1,%x3,%0
6866 fpam%.d %x2,%1,%x3,%0")
6869 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6870 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6871 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6872 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6875 fpam%.s %2,%w1,%w3,%0
6876 fpam%.s %x2,%1,%x3,%0
6877 fpam%.s %x2,%1,%x3,%0")
6879 ;;FPA Subtract and multiply
6881 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6882 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
6883 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6884 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6887 fpsm%.d %2,%w1,%w3,%0
6888 fpsm%.d %x2,%1,%x3,%0
6889 fpsm%.d %x2,%1,%x3,%0")
6892 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6893 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6894 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
6895 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6898 fpsm%.d %3,%w2,%w1,%0
6899 fpsm%.d %x3,%2,%x1,%0
6900 fpsm%.d %x3,%2,%x1,%0")
6903 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6904 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
6905 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6906 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6909 fpsm%.s %2,%w1,%w3,%0
6910 fpsm%.s %x2,%1,%x3,%0
6911 fpsm%.s %x2,%1,%x3,%0")
6914 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6915 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6916 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
6917 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6920 fpsm%.s %3,%w2,%w1,%0
6921 fpsm%.s %x3,%2,%x1,%0
6922 fpsm%.s %x3,%2,%x1,%0")
6924 (define_expand "tstxf"
6926 (match_operand:XF 0 "nonimmediate_operand" ""))]
6928 "m68k_last_compare_had_fp_operands = 1;")
6932 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6936 cc_status.flags = CC_IN_68881;
6937 return \"ftst%.x %0\";
6940 (define_expand "cmpxf"
6942 (compare (match_operand:XF 0 "nonimmediate_operand" "")
6943 (match_operand:XF 1 "nonimmediate_operand" "")))]
6945 "m68k_last_compare_had_fp_operands = 1;")
6949 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
6950 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
6954 cc_status.flags = CC_IN_68881;
6955 #ifdef SGS_CMP_ORDER
6956 if (REG_P (operands[0]))
6958 if (REG_P (operands[1]))
6959 return \"fcmp%.x %0,%1\";
6961 return \"fcmp%.x %0,%f1\";
6963 cc_status.flags |= CC_REVERSED;
6964 return \"fcmp%.x %1,%f0\";
6966 if (REG_P (operands[0]))
6968 if (REG_P (operands[1]))
6969 return \"fcmp%.x %1,%0\";
6971 return \"fcmp%.x %f1,%0\";
6973 cc_status.flags |= CC_REVERSED;
6974 return \"fcmp%.x %f0,%1\";
6978 (define_insn "extendsfxf2"
6979 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6980 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
6984 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6986 if (REGNO (operands[0]) == REGNO (operands[1]))
6988 /* Extending float to double in an fp-reg is a no-op.
6989 NOTICE_UPDATE_CC has already assumed that the
6990 cc will be set. So cancel what it did. */
6991 cc_status = cc_prev_status;
6994 return \"f%$move%.x %1,%0\";
6996 if (FP_REG_P (operands[0]))
6997 return \"f%$move%.s %f1,%0\";
6998 return \"fmove%.x %f1,%0\";
7002 (define_insn "extenddfxf2"
7003 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7005 (match_operand:DF 1 "general_operand" "f,m")))]
7009 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7011 if (REGNO (operands[0]) == REGNO (operands[1]))
7013 /* Extending float to double in an fp-reg is a no-op.
7014 NOTICE_UPDATE_CC has already assumed that the
7015 cc will be set. So cancel what it did. */
7016 cc_status = cc_prev_status;
7019 return \"fmove%.x %1,%0\";
7021 if (FP_REG_P (operands[0]))
7022 return \"f%&move%.d %f1,%0\";
7023 return \"fmove%.x %f1,%0\";
7026 (define_insn "truncxfdf2"
7027 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7029 (match_operand:XF 1 "general_operand" "f,f")))]
7033 if (REG_P (operands[0]))
7035 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7036 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
7037 return \"move%.l %+,%0\";
7039 return \"fmove%.d %f1,%0\";
7042 (define_insn "truncxfsf2"
7043 [(set (match_operand:SF 0 "general_operand" "=dm")
7045 (match_operand:XF 1 "general_operand" "f")))]
7049 (define_insn "floatsixf2"
7050 [(set (match_operand:XF 0 "general_operand" "=f")
7051 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7055 (define_insn "floathixf2"
7056 [(set (match_operand:XF 0 "general_operand" "=f")
7057 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7061 (define_insn "floatqixf2"
7062 [(set (match_operand:XF 0 "general_operand" "=f")
7063 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7067 (define_insn "ftruncxf2"
7068 [(set (match_operand:XF 0 "general_operand" "=f")
7069 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7073 if (FP_REG_P (operands[1]))
7074 return \"fintrz%.x %f1,%0\";
7075 return \"fintrz%.x %f1,%0\";
7078 (define_insn "fixxfqi2"
7079 [(set (match_operand:QI 0 "general_operand" "=dm")
7080 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7084 (define_insn "fixxfhi2"
7085 [(set (match_operand:HI 0 "general_operand" "=dm")
7086 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7090 (define_insn "fixxfsi2"
7091 [(set (match_operand:SI 0 "general_operand" "=dm")
7092 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7097 [(set (match_operand:XF 0 "general_operand" "=f")
7098 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7099 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7104 [(set (match_operand:XF 0 "general_operand" "=f")
7105 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7106 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7111 [(set (match_operand:XF 0 "general_operand" "=f")
7112 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7113 (match_operand:XF 1 "general_operand" "0")))]
7117 (define_insn "addxf3"
7118 [(set (match_operand:XF 0 "general_operand" "=f")
7119 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7120 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7124 if (REG_P (operands[2]))
7125 return \"fadd%.x %2,%0\";
7126 return \"fadd%.x %f2,%0\";
7130 [(set (match_operand:XF 0 "general_operand" "=f")
7131 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7132 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7137 [(set (match_operand:XF 0 "general_operand" "=f")
7138 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7139 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7144 [(set (match_operand:XF 0 "general_operand" "=f")
7145 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7146 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7150 (define_insn "subxf3"
7151 [(set (match_operand:XF 0 "general_operand" "=f")
7152 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7153 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7157 if (REG_P (operands[2]))
7158 return \"fsub%.x %2,%0\";
7159 return \"fsub%.x %f2,%0\";
7163 [(set (match_operand:XF 0 "general_operand" "=f")
7164 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7165 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7170 [(set (match_operand:XF 0 "general_operand" "=f")
7171 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7172 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7177 [(set (match_operand:XF 0 "general_operand" "=f")
7178 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7179 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7183 (define_insn "mulxf3"
7184 [(set (match_operand:XF 0 "general_operand" "=f")
7185 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7186 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7190 if (REG_P (operands[2]))
7191 return \"fmul%.x %2,%0\";
7192 return \"fmul%.x %f2,%0\";
7196 [(set (match_operand:XF 0 "general_operand" "=f")
7197 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7198 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7203 [(set (match_operand:XF 0 "general_operand" "=f")
7204 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7205 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7210 [(set (match_operand:XF 0 "general_operand" "=f")
7211 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7212 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7216 (define_insn "divxf3"
7217 [(set (match_operand:XF 0 "general_operand" "=f")
7218 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7219 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7223 if (REG_P (operands[2]))
7224 return \"fdiv%.x %2,%0\";
7225 return \"fdiv%.x %f2,%0\";
7228 (define_expand "negxf2"
7229 [(set (match_operand:XF 0 "general_operand" "")
7230 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7234 /* ??? There isn't an FPA define_insn so we could handle it here too.
7235 For now we don't (paranoia). */
7243 target = operand_subword (operands[0], 0, 1, XFmode);
7244 result = expand_binop (SImode, xor_optab,
7245 operand_subword_force (operands[1], 0, XFmode),
7246 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7250 if (result != target)
7251 emit_move_insn (result, target);
7253 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7254 operand_subword_force (operands[1], 1, XFmode));
7255 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7256 operand_subword_force (operands[1], 2, XFmode));
7258 insns = get_insns ();
7261 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7266 (define_insn "negxf2_68881"
7267 [(set (match_operand:XF 0 "general_operand" "=f")
7268 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7272 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7273 return \"fneg%.x %1,%0\";
7274 return \"fneg%.x %f1,%0\";
7277 (define_expand "absxf2"
7278 [(set (match_operand:XF 0 "general_operand" "")
7279 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7283 /* ??? There isn't an FPA define_insn so we could handle it here too.
7284 For now we don't (paranoia). */
7292 target = operand_subword (operands[0], 0, 1, XFmode);
7293 result = expand_binop (SImode, and_optab,
7294 operand_subword_force (operands[1], 0, XFmode),
7295 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7299 if (result != target)
7300 emit_move_insn (result, target);
7302 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7303 operand_subword_force (operands[1], 1, XFmode));
7304 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7305 operand_subword_force (operands[1], 2, XFmode));
7307 insns = get_insns ();
7310 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7315 (define_insn "absxf2_68881"
7316 [(set (match_operand:XF 0 "general_operand" "=f")
7317 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7321 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7322 return \"fabs%.x %1,%0\";
7323 return \"fabs%.x %f1,%0\";
7326 (define_insn "sqrtxf2"
7327 [(set (match_operand:XF 0 "general_operand" "=f")
7328 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7332 (define_insn "sinsf2"
7333 [(set (match_operand:SF 0 "general_operand" "=f")
7334 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7335 "TARGET_68881 && flag_fast_math"
7338 if (FP_REG_P (operands[1]))
7339 return \"fsin%.x %1,%0\";
7341 return \"fsin%.s %1,%0\";
7344 (define_insn "sindf2"
7345 [(set (match_operand:DF 0 "general_operand" "=f")
7346 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7347 "TARGET_68881 && flag_fast_math"
7350 if (FP_REG_P (operands[1]))
7351 return \"fsin%.x %1,%0\";
7353 return \"fsin%.d %1,%0\";
7356 (define_insn "sinxf2"
7357 [(set (match_operand:XF 0 "general_operand" "=f")
7358 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7359 "TARGET_68881 && flag_fast_math"
7362 (define_insn "cossf2"
7363 [(set (match_operand:SF 0 "general_operand" "=f")
7364 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7365 "TARGET_68881 && flag_fast_math"
7368 if (FP_REG_P (operands[1]))
7369 return \"fcos%.x %1,%0\";
7371 return \"fcos%.s %1,%0\";
7374 (define_insn "cosdf2"
7375 [(set (match_operand:DF 0 "general_operand" "=f")
7376 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7377 "TARGET_68881 && flag_fast_math"
7380 if (FP_REG_P (operands[1]))
7381 return \"fcos%.x %1,%0\";
7383 return \"fcos%.d %1,%0\";
7386 (define_insn "cosxf2"
7387 [(set (match_operand:XF 0 "general_operand" "=f")
7388 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7389 "TARGET_68881 && flag_fast_math"