1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
22 ;;- instruction definitions
24 ;;- @@The original PO technology requires these to be ordered by speed,
25 ;;- @@ so that assigner will pick the fastest.
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;;- When naming insn's (operand 0 of define_insn) be careful about using
30 ;;- names from other targets machine descriptions.
32 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
33 ;;- updates for most instructions.
35 ;;- Operand classes for the register allocator:
36 ;;- 'a' one of the address registers can be used.
37 ;;- 'd' one of the data registers can be used.
38 ;;- 'f' one of the m68881 registers can be used
39 ;;- 'r' either a data or an address register can be used.
40 ;;- 'x' if one of the Sun FPA registers
41 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
43 ;;- Immediate Floating point operator constraints
44 ;;- 'G' a floating point constant that is *NOT* one of the standard
45 ;; 68881 constant values (to force calling output_move_const_double
46 ;; to get it from rom if it is a 68881 constant).
47 ;;- 'H' one of the standard FPA constant values
49 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
52 ;;- Immediate integer operand constraints:
54 ;;- 'J' -32768 .. 32767
55 ;;- 'K' all integers EXCEPT -128 .. 127
57 ;;- 'M' all integers EXCEPT -256 .. 255
60 ;;- "%." size separator ("." or "") move%.l d0,d1
61 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
62 ;;- "%-" push operand "sp@-" move%.l d0,%-
63 ;;- "%+" pop operand "sp@+" move%.l d0,%+
64 ;;- "%@" top of stack "sp@" move%.l d0,%@
65 ;;- "%!" fpcr register
66 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
67 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
70 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
71 ;; operand 1 is the argument for `sin'.
72 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
73 ;; operand 1 is the argument for `cos'.
75 ;;- Information about 68040 port.
77 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
78 ;;- be emulated in software by the OS. It is faster to avoid these
79 ;;- instructions and issue a library call rather than trapping into
80 ;;- the kernel. The affected instructions are fintrz and fscale. The
81 ;;- TARGET_68040 flag turns the use of the opcodes off.
83 ;;- The '040 also implements a set of new floating-point instructions
84 ;;- which specify the rounding precision in the opcode. This finally
85 ;;- permit the 68k series to be truly IEEE compliant, and solves all
86 ;;- issues of excess precision accumulating in the extended registers.
87 ;;- By default, GCC does not use these instructions, since such code will
88 ;;- not run on an '030. To use these instructions, use the -m68040-only
89 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
90 ;;- you can make these instructions the default.
92 ;;- These new instructions aren't directly in the md. They are brought
93 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
96 ;;- Information about 68060 port.
98 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
99 ;;- be emulated in software by the OS. It is faster to avoid these
100 ;;- instructions and issue a library call rather than trapping into
101 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
102 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq, fintrz;
103 ;;- and fscale. The TARGET_68060 flag turns the use of the opcodes
107 ;;- FPA port explanation:
109 ;;- Usage of the Sun FPA and the 68881 together
111 ;;- The current port of gcc to the sun fpa disallows use of the m68881
112 ;;- instructions completely if code is targeted for the fpa. This is
113 ;;- for the following reasons:
115 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
116 ;;- can, the 68881 otherwise, and data registers only if you are
117 ;;- forced to it) is a bitch with the current constraint scheme,
118 ;;- especially since it would have to work for any combination of
121 ;;- 2) There are no instructions to move between the two types of
122 ;;- registers; the stack must be used as an intermediary.
124 ;;- It could indeed be done; I think the best way would be to have
125 ;;- separate patterns for TARGET_FPA (which implies a 68881),
126 ;;- TARGET_68881, and no floating point co-processor. Use
127 ;;- define_expands for all of the named instruction patterns, and
128 ;;- include code in the FPA instruction to deal with the 68881 with
129 ;;- preferences specifically set to favor the fpa. Some of this has
130 ;;- already been done:
132 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
133 ;;- case and a TARGET_68881 case (the exceptions are the patterns
134 ;;- which would need one define_expand and three define_insn's under
135 ;;- it (with a lot of duplicate code between them) to replace the
136 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
137 ;;- first two patterns in the md.
139 ;;- Some would still have to be done:
141 ;;- 1) Add code to the fpa patterns which correspond to 68881
142 ;;- patterns to deal with the 68881 case (including preferences!).
143 ;;- What you might actually do here is combine the fpa and 68881 code
144 ;;- back together into one pattern for those instructions where it's
145 ;;- absolutely necessary and save yourself some duplicate code. I'm
146 ;;- not completely sure as to whether you could get away with doing
147 ;;- this only for the mov* insns, or if you'd have to do it for all
149 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
150 ;;- moving between fpa regs and 68881 regs.
152 ;;- Since the fpa is more powerful than the 68881 and also has more
153 ;;- registers, and since I think the resultant md would be medium ugly
154 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
155 ;;- to do this change.
157 ;;- Another reason why someone *might* want to do the change is to
158 ;;- control which register classes are accessed in a slightly cleaner
159 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
160 ;;- the internals manual.
162 ;;- Yet another reason why someone might want to do this change is to
163 ;;- allow use of some of the 68881 insns which have no equivalent on
164 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
166 ;;- If this is ever done, don't forget to change sun3.h so that
167 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
169 ;;- Condition code hack
171 ;;- When a floating point compare is done in the fpa, the resulting
172 ;;- condition codes are left in the fpastatus register. The values in
173 ;;- this register must be moved into the 68000 cc register before any
174 ;;- jump is executed. Once this has been done, regular jump
175 ;;- instructions are fine (ie. floating point jumps are not necessary.
176 ;;- They are only done if the cc is in the 68881).
178 ;;- The instructions that move the fpastatus register to the 68000
179 ;;- register clobber a data register (the move cannot be done direct).
180 ;;- These instructions might be bundled either with the compare
181 ;;- instruction, or the branch instruction. If we were using both the
182 ;;- fpa and the 68881 together, we would wish to only mark the
183 ;;- register clobbered if we were doing the compare in the fpa, but I
184 ;;- think that that decision (whether to clobber the register or not)
185 ;;- must be done before register allocation (makes sense) and hence we
186 ;;- can't know if the floating point compare will be done in the fpa
187 ;;- or the fp. So whenever we are asked for code that uses the fpa,
188 ;;- we will mark a data register as clobbered. This is reasonable, as
189 ;;- almost all floating point compare operations done with fpa code
190 ;;- enabled will be done in the fpa. It's even more reasonable since
191 ;;- we decided to make the 68881 and the fpa mutually exclusive.
193 ;;- We place to code to move the fpastatus register inside of a
194 ;;- define_expand so that we can do it conditionally based on whether
195 ;;- we are targeting an fpa or not.
197 ;;- This still leaves us with the question of where we wish to put the
198 ;;- code to move the fpastatus reg. If we put it in the compare
199 ;;- instruction, we can restrict the clobbering of the register to
200 ;;- floating point compares, but we can't take advantage of floating
201 ;;- point subtracts & etc. that alter the fpastatus register. If we
202 ;;- put it in the branch instruction, all branches compiled with fpa
203 ;;- code enabled will clobber a data register, but we will be able to
204 ;;- take advantage of fpa subtracts. This balance favors putting the
205 ;;- code in with the compare instruction.
207 ;;- Note that if some enterprising hacker should decide to switch
208 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
210 ;;- Usage of the top 16 fpa registers
212 ;;- The only locations which we may transfer fpa registers 16-31 from
213 ;;- or to are the fpa registers 0-15. (68000 registers and memory
214 ;;- locations are impossible). This causes problems in gcc, which
215 ;;- assumes that mov?? instructions require no additional registers
216 ;;- (see section 11.7) and since floating point moves *must* be
217 ;;- supported into general registers (see section 12.3 under
218 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
220 ;;- My solution was to reserve fpa0 for moves into or out of these top
221 ;;- 16 registers and to disparage the choice to reload into or out of
222 ;;- these registers as much as I could. That alternative is always
223 ;;- last in the list, so it will not be used unless all else fails. I
224 ;;- will note that according to my current information, sun's compiler
225 ;;- doesn't use these top 16 registers at all.
227 ;;- There is another possible way to do it. I *believe* that if you
228 ;;- make absolutely sure that the code will not be executed in the
229 ;;- reload pass, you can support the mov?? names with define_expands
230 ;;- which require new registers. This may be possible by the
231 ;;- appropriate juggling of constraints. I may come back to this later.
233 ;;- Usage of constant RAM
235 ;;- This has been handled correctly (I believe) but the way I've done
236 ;;- it could use a little explanation. The constant RAM can only be
237 ;;- accessed when the instruction is in "command register" mode.
238 ;;- "command register" mode means that no accessing of memory or the
239 ;;- 68000 registers is being done. This can be expressed easily in
240 ;;- constraints, so generally the mode of the instruction is
241 ;;- determined by a branch off of which_alternative. In outputting
242 ;;- instructions, a 'w' means to output an access to the constant ram
243 ;;- (if the arg is CONST_DOUBLE and is one of the available
244 ;;- constants), and 'x' means to output a register pair (if the arg is
245 ;;- a 68000 register) and a 'y' is the combination of the above two
246 ;;- processes. You use a 'y' in two operand DF instructions where you
247 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
248 ;;- instructions where the arg might be a 68000 register and the
249 ;;- instruction is *not* in "command register" mode, and you use a 'w'
250 ;;- in two situations: 1) The instruction *is* in command register
251 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
252 ;;- instruction is a two operand SF instruction where you know the
253 ;;- other operand is an fpa register.
255 ;;- Optimization issues
257 ;;- I actually think that I've included all of the fpa instructions
258 ;;- that should be included. Note that if someone is interested in
259 ;;- doing serious floating point work on the sun fpa, I would advise
260 ;;- the use of the "asm" instruction in gcc to allow you to use the
261 ;;- sin, cos, and exponential functions on the fpa board.
263 ;;- END FPA Explanation Section.
266 ;;- Some of these insn's are composites of several m68000 op codes.
267 ;;- The assembler (or final @@??) insures that the appropriate one is
271 [(set (match_operand:DF 0 "push_operand" "=m")
272 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
276 if (FP_REG_P (operands[1]))
277 return \"fmove%.d %f1,%0\";
278 if (FPA_REG_P (operands[1]))
279 return \"fpmove%.d %1, %x0\";
280 return output_move_double (operands);
283 (define_insn "pushdi"
284 [(set (match_operand:DI 0 "push_operand" "=m")
285 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
289 return output_move_double (operands);
292 ;; We don't want to allow a constant operand for test insns because
293 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
294 ;; be folded while optimizing anyway.
296 (define_expand "tstdi"
299 (match_operand:DI 0 "nonimmediate_operand" "d"))
300 (clobber (match_dup 1))])]
302 "operands[1] = gen_reg_rtx (DImode);")
306 (match_operand:DI 1 "nonimmediate_operand" "0"))
307 (clobber (match_operand:DI 0 "register_operand" "=d"))]
311 cc_status.flags |= CC_REVERSED;
312 return \"neg%.l %R0\;negx%.l %0\";
317 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
322 /* ISI's assembler fails to handle tstl a0. */
323 if (! ADDRESS_REG_P (operands[0]))
325 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
327 return \"tst%.l %0\";
328 /* If you think that the 68020 does not support tstl a0,
329 reread page B-167 of the 68020 manual more carefully. */
330 /* On an address reg, cmpw may replace cmpl. */
332 return \"cmp%.w %0,%#0\";
334 return \"cmp%.w %#0,%0\";
338 ;; This can't use an address register, because comparisons
339 ;; with address registers as second operand always test the whole word.
342 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
348 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
352 (define_expand "tstsf"
354 (match_operand:SF 0 "general_operand" ""))]
355 "TARGET_68881 || TARGET_FPA"
360 emit_insn (gen_tstsf_fpa (operands[0]));
365 (define_insn "tstsf_fpa"
367 (match_operand:SF 0 "general_operand" "xmdF"))
368 (clobber (match_scratch:SI 1 "=d"))]
370 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
374 (match_operand:SF 0 "general_operand" "fdm"))]
378 cc_status.flags = CC_IN_68881;
379 if (FP_REG_P (operands[0]))
380 return \"ftst%.x %0\";
381 return \"ftst%.s %0\";
384 (define_expand "tstdf"
386 (match_operand:DF 0 "general_operand" ""))]
387 "TARGET_68881 || TARGET_FPA"
392 emit_insn (gen_tstsf_fpa (operands[0]));
397 (define_insn "tstdf_fpa"
399 (match_operand:DF 0 "general_operand" "xrmF"))
400 (clobber (match_scratch:SI 1 "=d"))]
402 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
406 (match_operand:DF 0 "general_operand" "fm"))]
410 cc_status.flags = CC_IN_68881;
411 if (FP_REG_P (operands[0]))
412 return \"ftst%.x %0\";
413 return \"ftst%.d %0\";
416 ;; compare instructions.
418 (define_expand "cmpdi"
421 (compare (match_operand:DI 0 "nonimmediate_operand" "")
422 (match_operand:DI 1 "general_operand" "")))
423 (clobber (match_dup 2))])]
425 "operands[2] = gen_reg_rtx (DImode);")
429 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
430 (match_operand:DI 2 "general_operand" "d,0")))
431 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
435 if (rtx_equal_p (operands[0], operands[1]))
436 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
439 cc_status.flags |= CC_REVERSED;
440 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
444 ;; This is the second "hook" for PIC code (in addition to movsi). See
445 ;; comment of movsi for a description of PIC handling.
446 (define_expand "cmpsi"
448 (compare (match_operand:SI 0 "nonimmediate_operand" "")
449 (match_operand:SI 1 "general_operand" "")))]
453 if (flag_pic && symbolic_operand (operands[1], SImode))
455 /* The source is an address which requires PIC relocation.
456 Call legitimize_pic_address with the source, mode, and a relocation
457 register (a new pseudo, or the final destination if reload_in_progress
458 is set). Then fall through normally */
459 extern rtx legitimize_pic_address();
460 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
461 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
465 ;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
468 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
469 (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
473 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
475 return \"cmpm%.l %0,%1\";
477 return \"cmpm%.l %1,%0\";
479 if (REG_P (operands[1])
480 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
481 { cc_status.flags |= CC_REVERSED;
483 return \"cmp%.l %d1,%d0\";
485 return \"cmp%.l %d0,%d1\";
489 return \"cmp%.l %d0,%d1\";
491 return \"cmp%.l %d1,%d0\";
497 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
498 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
502 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
504 return \"cmpm%.w %0,%1\";
506 return \"cmpm%.w %1,%0\";
508 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
509 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
510 { cc_status.flags |= CC_REVERSED;
512 return \"cmp%.w %d1,%d0\";
514 return \"cmp%.w %d0,%d1\";
518 return \"cmp%.w %d0,%d1\";
520 return \"cmp%.w %d1,%d0\";
526 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
527 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
531 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
533 return \"cmpm%.b %0,%1\";
535 return \"cmpm%.b %1,%0\";
537 if (REG_P (operands[1])
538 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
539 { cc_status.flags |= CC_REVERSED;
541 return \"cmp%.b %d1,%d0\";
543 return \"cmp%.b %d0,%d1\";
547 return \"cmp%.b %d0,%d1\";
549 return \"cmp%.b %d1,%d0\";
553 (define_expand "cmpdf"
555 (compare (match_operand:DF 0 "general_operand" "")
556 (match_operand:DF 1 "general_operand" "")))]
557 "TARGET_68881 || TARGET_FPA"
562 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
567 (define_insn "cmpdf_fpa"
569 (compare (match_operand:DF 0 "general_operand" "x,y")
570 (match_operand:DF 1 "general_operand" "xH,rmF")))
571 (clobber (match_scratch:SI 2 "=d,d"))]
573 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
577 (compare (match_operand:DF 0 "general_operand" "f,mG")
578 (match_operand:DF 1 "general_operand" "fmG,f")))]
582 cc_status.flags = CC_IN_68881;
584 if (REG_P (operands[0]))
586 if (REG_P (operands[1]))
587 return \"fcmp%.x %0,%1\";
589 return \"fcmp%.d %0,%f1\";
591 cc_status.flags |= CC_REVERSED;
592 return \"fcmp%.d %1,%f0\";
594 if (REG_P (operands[0]))
596 if (REG_P (operands[1]))
597 return \"fcmp%.x %1,%0\";
599 return \"fcmp%.d %f1,%0\";
601 cc_status.flags |= CC_REVERSED;
602 return \"fcmp%.d %f0,%1\";
606 (define_expand "cmpsf"
608 (compare (match_operand:SF 0 "general_operand" "")
609 (match_operand:SF 1 "general_operand" "")))]
610 "TARGET_68881 || TARGET_FPA"
615 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
620 (define_insn "cmpsf_fpa"
622 (compare (match_operand:SF 0 "general_operand" "x,y")
623 (match_operand:SF 1 "general_operand" "xH,rmF")))
624 (clobber (match_scratch:SI 2 "=d,d"))]
626 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
630 (compare (match_operand:SF 0 "general_operand" "f,mdG")
631 (match_operand:SF 1 "general_operand" "fmdG,f")))]
635 cc_status.flags = CC_IN_68881;
637 if (FP_REG_P (operands[0]))
639 if (FP_REG_P (operands[1]))
640 return \"fcmp%.x %0,%1\";
642 return \"fcmp%.s %0,%f1\";
644 cc_status.flags |= CC_REVERSED;
645 return \"fcmp%.s %1,%f0\";
647 if (FP_REG_P (operands[0]))
649 if (FP_REG_P (operands[1]))
650 return \"fcmp%.x %1,%0\";
652 return \"fcmp%.s %f1,%0\";
654 cc_status.flags |= CC_REVERSED;
655 return \"fcmp%.s %f0,%1\";
659 ;; Recognizers for btst instructions.
662 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
664 (minus:SI (const_int 7)
665 (match_operand:SI 1 "general_operand" "di"))))]
667 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
670 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
672 (minus:SI (const_int 31)
673 (match_operand:SI 1 "general_operand" "di"))))]
675 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
677 ;; The following two patterns are like the previous two
678 ;; except that they use the fact that bit-number operands
679 ;; are automatically masked to 3 or 5 bits.
682 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
684 (minus:SI (const_int 7)
686 (match_operand:SI 1 "register_operand" "d")
689 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
692 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
694 (minus:SI (const_int 31)
696 (match_operand:SI 1 "register_operand" "d")
699 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
701 ;; Nonoffsettable mem refs are ok in this one pattern
702 ;; since we don't try to adjust them.
704 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
706 (match_operand:SI 1 "const_int_operand" "n")))]
707 "(unsigned) INTVAL (operands[1]) < 8"
710 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
711 return output_btst (operands, operands[1], operands[0], insn, 7);
715 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
717 (match_operand:SI 1 "const_int_operand" "n")))]
721 if (GET_CODE (operands[0]) == MEM)
723 operands[0] = adj_offsettable_operand (operands[0],
724 INTVAL (operands[1]) / 8);
725 operands[1] = gen_rtx (CONST_INT, VOIDmode,
726 7 - INTVAL (operands[1]) % 8);
727 return output_btst (operands, operands[1], operands[0], insn, 7);
729 operands[1] = gen_rtx (CONST_INT, VOIDmode,
730 31 - INTVAL (operands[1]));
731 return output_btst (operands, operands[1], operands[0], insn, 31);
737 ;; A special case in which it is not desirable
738 ;; to reload the constant into a data register.
739 (define_insn "pushexthisi_const"
740 [(set (match_operand:SI 0 "push_operand" "=m")
741 (match_operand:SI 1 "const_int_operand" "J"))]
742 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
745 if (operands[1] == const0_rtx)
746 return \"clr%.l %0\";
751 ;(define_insn "swapsi"
752 ; [(set (match_operand:SI 0 "general_operand" "+r")
753 ; (match_operand:SI 1 "general_operand" "+r"))
754 ; (set (match_dup 1) (match_dup 0))]
758 ;; Special case of fullword move when source is zero.
759 ;; The reason this is special is to avoid loading a zero
760 ;; into a data reg with moveq in order to store it elsewhere.
762 (define_insn "movsi_const0"
763 [(set (match_operand:SI 0 "general_operand" "=g")
765 ;; clr insns on 68000 read before writing.
766 ;; This isn't so on the 68010, but we have no alternative for it.
768 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
771 if (ADDRESS_REG_P (operands[0]))
772 return \"sub%.l %0,%0\";
773 /* moveq is faster on the 68000. */
774 if (DATA_REG_P (operands[0]) && !TARGET_68020)
775 #if defined(MOTOROLA) && !defined(CRDS)
776 return \"moveq%.l %#0,%0\";
778 return \"moveq %#0,%0\";
780 return \"clr%.l %0\";
783 ;; General case of fullword move.
785 ;; This is the main "hook" for PIC code. When generating
786 ;; PIC, movsi is responsible for determining when the source address
787 ;; needs PIC relocation and appropriately calling legitimize_pic_address
788 ;; to perform the actual relocation.
790 ;; In both the PIC and non-PIC cases the patterns generated will
791 ;; matched by the next define_insn.
792 (define_expand "movsi"
793 [(set (match_operand:SI 0 "general_operand" "")
794 (match_operand:SI 1 "general_operand" ""))]
798 if (flag_pic && symbolic_operand (operands[1], SImode))
800 /* The source is an address which requires PIC relocation.
801 Call legitimize_pic_address with the source, mode, and a relocation
802 register (a new pseudo, or the final destination if reload_in_progress
803 is set). Then fall through normally */
804 extern rtx legitimize_pic_address();
805 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
806 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
810 ;; General case of fullword move. The register constraints
811 ;; force integer constants in range for a moveq to be reloaded
812 ;; if they are headed for memory.
814 ;; Notes: make sure no alternative allows g vs g.
815 ;; We don't allow f-regs since fixed point cannot go in them.
816 ;; We do allow y and x regs since fixed point is allowed in them.
817 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
818 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
822 if (which_alternative == 3)
823 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
824 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
825 return \"fpmove%.l %x1,%x0\";
826 if (GET_CODE (operands[1]) == CONST_INT)
827 return output_move_simode_const (operands);
828 else if ((GET_CODE (operands[1]) == SYMBOL_REF
829 || GET_CODE (operands[1]) == CONST)
830 && push_operand (operands[0], SImode))
832 else if ((GET_CODE (operands[1]) == SYMBOL_REF
833 || GET_CODE (operands[1]) == CONST)
834 && ADDRESS_REG_P (operands[0]))
835 return \"lea %a1,%0\";
836 return \"move%.l %1,%0\";
840 [(set (match_operand:HI 0 "general_operand" "=g")
841 (match_operand:HI 1 "general_operand" "g"))]
845 if (GET_CODE (operands[1]) == CONST_INT)
847 if (operands[1] == const0_rtx
848 && (DATA_REG_P (operands[0])
849 || GET_CODE (operands[0]) == MEM)
850 /* clr insns on 68000 read before writing.
851 This isn't so on the 68010, but we have no alternative for it. */
853 || !(GET_CODE (operands[0]) == MEM
854 && MEM_VOLATILE_P (operands[0]))))
855 return \"clr%.w %0\";
856 else if (DATA_REG_P (operands[0])
857 && INTVAL (operands[1]) < 128
858 && INTVAL (operands[1]) >= -128)
860 #if defined(MOTOROLA) && !defined(CRDS)
861 return \"moveq%.l %1,%0\";
863 return \"moveq %1,%0\";
866 else if (INTVAL (operands[1]) < 0x8000
867 && INTVAL (operands[1]) >= -0x8000)
868 return \"move%.w %1,%0\";
870 else if (CONSTANT_P (operands[1]))
871 return \"move%.l %1,%0\";
873 /* Recognize the insn before a tablejump, one that refers
874 to a table of offsets. Such an insn will need to refer
875 to a label on the insn. So output one. Use the label-number
876 of the table of offsets to generate this label. This code,
877 and similar code below, assumes that there will be at most one
878 reference to each table. */
879 if (GET_CODE (operands[1]) == MEM
880 && GET_CODE (XEXP (operands[1], 0)) == PLUS
881 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
882 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
884 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
885 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
887 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
888 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
890 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
891 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
893 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
894 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
895 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
896 #ifdef SGS_SWITCH_TABLES
897 /* Set flag saying we need to define the symbol
898 LD%n (with value L%n-LI%n) at the end of the switch table. */
899 switch_table_difference_label_flag = 1;
900 #endif /* SGS_SWITCH_TABLES */
901 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
903 #endif /* SGS_NO_LI */
904 return \"move%.w %1,%0\";
907 (define_insn "movstricthi"
908 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
909 (match_operand:HI 1 "general_operand" "rmn"))]
913 if (GET_CODE (operands[1]) == CONST_INT)
915 if (operands[1] == const0_rtx
916 && (DATA_REG_P (operands[0])
917 || GET_CODE (operands[0]) == MEM)
918 /* clr insns on 68000 read before writing.
919 This isn't so on the 68010, but we have no alternative for it. */
921 || !(GET_CODE (operands[0]) == MEM
922 && MEM_VOLATILE_P (operands[0]))))
923 return \"clr%.w %0\";
925 return \"move%.w %1,%0\";
929 [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a")
930 (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))]
936 /* This is probably useless, since it loses for pushing a struct
937 of several bytes a byte at a time. */
938 if (GET_CODE (operands[0]) == MEM
939 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
940 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
941 && ! ADDRESS_REG_P (operands[1]))
943 xoperands[1] = operands[1];
945 = gen_rtx (MEM, QImode,
946 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
947 /* Just pushing a byte puts it in the high byte of the halfword. */
948 /* We must put it in the low-order, high-numbered byte. */
949 output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands);
953 /* Moving a byte into an address register is not possible. */
954 /* Use d0 as an intermediate, but don't clobber its contents. */
955 if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
957 /* ??? For 2.5, don't allow this choice and use secondary reloads
960 See if the address register is used in the address. If it
961 is, we have to generate a more complex sequence than those below. */
963 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
964 operands[1], NULL_RTX))
966 /* See if the stack pointer is used in the address. If it isn't,
967 we can push d0 or d1 (the insn can't use both of them) on
968 the stack, perform our move into d0/d1, copy the byte from d0/1,
970 if (! reg_mentioned_p (stack_pointer_rtx, operands[1]))
972 if (! refers_to_regno_p (0, 1, operands[1], NULL_RTX))
973 return \"move%.l %/d0,%-\;move%.b %1,%/d0\;move%.l %/d0,%0\;move%.l %+,%/d0\";
975 return \"move%.l %/d1,%-\;move%.b %1,%/d1\;move%.l %/d1,%0\;move%.l %+,%/d1\";
979 /* Otherwise, we know that d0 cannot be used in the address
980 (since sp and one address register is). Assume that sp is
981 being used as a base register and replace the address
982 register that is our operand[0] with d0. */
983 rtx reg_map[FIRST_PSEUDO_REGISTER];
986 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
989 reg_map[REGNO (operands[0])] = gen_rtx (REG, Pmode, 0);
990 operands[1] = copy_rtx (operands[1]);
991 replace_regs (operands[1], reg_map, FIRST_PSEUDO_REGISTER, 0);
992 return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\";
996 /* If the address of operand 1 uses d0, choose d1 as intermediate. */
997 if (refers_to_regno_p (0, 1, operands[1], NULL_RTX))
998 return \"exg %/d1,%0\;move%.b %1,%/d1\;exg %/d1,%0\";
999 /* Otherwise d0 is usable.
1000 (An effective address on the 68k can't use two d-regs.) */
1002 return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\";
1005 /* Likewise for moving from an address reg. */
1006 if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM)
1008 /* ??? For 2.5, don't allow this choice and use secondary reloads
1011 See if the address register is used in the address. If it
1012 is, we have to generate a more complex sequence than those below. */
1014 if (refers_to_regno_p (REGNO (operands[1]), REGNO (operands[1]) + 1,
1015 operands[0], NULL_RTX))
1017 /* See if the stack pointer is used in the address. If it isn't,
1018 we can push d0 or d1 (the insn can't use both of them) on
1019 the stack, copy the byte to d0/1, perform our move from d0/d1,
1021 if (! reg_mentioned_p (stack_pointer_rtx, operands[0]))
1023 if (! refers_to_regno_p (0, 1, operands[0], NULL_RTX))
1024 return \"move%.l %/d0,%-\;move%.l %1,%/d0\;move%.b %/d0,%0\;move%.l %+,%/d0\";
1026 return \"move%.l %/d1,%-\;move%.l %1,%/d1\;move%.b %/d1,%0\;move%.l %+,%/d1\";
1030 /* Otherwise, we know that d0 cannot be used in the address
1031 (since sp and one address register is). Assume that sp is
1032 being used as a base register and replace the address
1033 register that is our operand[1] with d0. */
1034 rtx reg_map[FIRST_PSEUDO_REGISTER];
1037 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1040 reg_map[REGNO (operands[1])] = gen_rtx (REG, Pmode, 0);
1041 operands[0] = copy_rtx (operands[0]);
1042 replace_regs (operands[0], reg_map, FIRST_PSEUDO_REGISTER, 0);
1043 return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\";
1047 if (refers_to_regno_p (0, 1, operands[0], NULL_RTX))
1048 return \"exg %/d1,%1\;move%.b %/d1,%0\;exg %/d1,%1\";
1050 return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\";
1053 /* clr and st insns on 68000 read before writing.
1054 This isn't so on the 68010, but we have no alternative for it. */
1056 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
1058 if (operands[1] == const0_rtx)
1059 return \"clr%.b %0\";
1060 if (GET_CODE (operands[1]) == CONST_INT
1061 && INTVAL (operands[1]) == -1)
1067 if (GET_CODE (operands[1]) == CONST_INT
1068 && DATA_REG_P (operands[0])
1069 && INTVAL (operands[1]) < 128
1070 && INTVAL (operands[1]) >= -128)
1072 #if defined(MOTOROLA) && !defined(CRDS)
1073 return \"moveq%.l %1,%0\";
1075 return \"moveq %1,%0\";
1078 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1079 return \"move%.l %1,%0\";
1080 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1081 return \"move%.w %1,%0\";
1082 return \"move%.b %1,%0\";
1085 (define_insn "movstrictqi"
1086 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1087 (match_operand:QI 1 "general_operand" "dmn"))]
1091 if (operands[1] == const0_rtx
1092 /* clr insns on 68000 read before writing.
1093 This isn't so on the 68010, but we have no alternative for it. */
1095 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1096 return \"clr%.b %0\";
1097 return \"move%.b %1,%0\";
1100 (define_insn "movsf"
1101 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1102 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1103 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1104 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1108 if (which_alternative >= 4)
1109 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1110 if (FPA_REG_P (operands[0]))
1112 if (FPA_REG_P (operands[1]))
1113 return \"fpmove%.s %x1,%x0\";
1114 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1115 return output_move_const_single (operands);
1116 else if (FP_REG_P (operands[1]))
1117 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1118 return \"fpmove%.s %x1,%x0\";
1120 if (FPA_REG_P (operands[1]))
1122 if (FP_REG_P (operands[0]))
1123 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1125 return \"fpmove%.s %x1,%x0\";
1127 if (FP_REG_P (operands[0]))
1129 if (FP_REG_P (operands[1]))
1130 return \"f%$move%.x %1,%0\";
1131 else if (ADDRESS_REG_P (operands[1]))
1132 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1133 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1134 return output_move_const_single (operands);
1135 return \"f%$move%.s %f1,%0\";
1137 if (FP_REG_P (operands[1]))
1139 if (ADDRESS_REG_P (operands[0]))
1140 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1141 return \"fmove%.s %f1,%0\";
1143 return \"move%.l %1,%0\";
1146 (define_insn "movdf"
1147 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1148 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1149 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1150 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1154 if (which_alternative == 7)
1155 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1156 if (FPA_REG_P (operands[0]))
1158 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1159 return output_move_const_double (operands);
1160 if (FP_REG_P (operands[1]))
1161 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1162 return \"fpmove%.d %x1,%x0\";
1164 else if (FPA_REG_P (operands[1]))
1166 if (FP_REG_P(operands[0]))
1167 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1169 return \"fpmove%.d %x1,%x0\";
1171 if (FP_REG_P (operands[0]))
1173 if (FP_REG_P (operands[1]))
1174 return \"f%&move%.x %1,%0\";
1175 if (REG_P (operands[1]))
1178 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1179 output_asm_insn (\"move%.l %1,%-\", xoperands);
1180 output_asm_insn (\"move%.l %1,%-\", operands);
1181 return \"f%&move%.d %+,%0\";
1183 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1184 return output_move_const_double (operands);
1185 return \"f%&move%.d %f1,%0\";
1187 else if (FP_REG_P (operands[1]))
1189 if (REG_P (operands[0]))
1191 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1192 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1193 return \"move%.l %+,%0\";
1196 return \"fmove%.d %f1,%0\";
1198 return output_move_double (operands);
1202 (define_expand "movxf"
1203 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1204 (match_operand:XF 1 "general_operand" ""))]
1208 if (CONSTANT_P (operands[1]))
1210 operands[1] = force_const_mem (XFmode, operands[1]);
1211 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1212 && ! reload_in_progress)
1213 operands[1] = change_address (operands[1], XFmode,
1214 XEXP (operands[1], 0));
1219 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1220 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1224 if (FP_REG_P (operands[0]))
1226 if (FP_REG_P (operands[1]))
1227 return \"fmove%.x %1,%0\";
1228 if (REG_P (operands[1]))
1231 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1232 output_asm_insn (\"move%.l %1,%-\", xoperands);
1233 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1234 output_asm_insn (\"move%.l %1,%-\", xoperands);
1235 output_asm_insn (\"move%.l %1,%-\", operands);
1236 return \"fmove%.x %+,%0\";
1238 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1239 return \"fmove%.x %1,%0\";
1240 return \"fmove%.x %f1,%0\";
1242 if (REG_P (operands[0]))
1244 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1245 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1246 output_asm_insn (\"move%.l %+,%0\", operands);
1247 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1248 return \"move%.l %+,%0\";
1250 return \"fmove%.x %f1,%0\";
1255 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1256 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1260 if (FP_REG_P (operands[0]))
1262 if (FP_REG_P (operands[1]))
1263 return \"fmove%.x %1,%0\";
1264 if (REG_P (operands[1]))
1267 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1268 output_asm_insn (\"move%.l %1,%-\", xoperands);
1269 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1270 output_asm_insn (\"move%.l %1,%-\", xoperands);
1271 output_asm_insn (\"move%.l %1,%-\", operands);
1272 return \"fmove%.x %+,%0\";
1274 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1275 return \"fmove%.x %1,%0\";
1276 return \"fmove%.x %f1,%0\";
1278 if (FP_REG_P (operands[1]))
1280 if (REG_P (operands[0]))
1282 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1283 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1284 output_asm_insn (\"move%.l %+,%0\", operands);
1285 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1286 return \"move%.l %+,%0\";
1289 return \"fmove%.x %f1,%0\";
1291 return output_move_double (operands);
1295 ;; movdi can apply to fp regs in some cases
1296 (define_insn "movdi"
1297 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1298 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1299 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1300 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1301 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1302 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1303 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1307 if (which_alternative == 8)
1308 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1309 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1310 return \"fpmove%.d %x1,%x0\";
1311 if (FP_REG_P (operands[0]))
1313 if (FP_REG_P (operands[1]))
1314 return \"fmove%.x %1,%0\";
1315 if (REG_P (operands[1]))
1318 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1319 output_asm_insn (\"move%.l %1,%-\", xoperands);
1320 output_asm_insn (\"move%.l %1,%-\", operands);
1321 return \"fmove%.d %+,%0\";
1323 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1324 return output_move_const_double (operands);
1325 return \"fmove%.d %f1,%0\";
1327 else if (FP_REG_P (operands[1]))
1329 if (REG_P (operands[0]))
1331 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1332 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1333 return \"move%.l %+,%0\";
1336 return \"fmove%.d %f1,%0\";
1338 return output_move_double (operands);
1342 ;; Thus goes after the move instructions
1343 ;; because the move instructions are better (require no spilling)
1344 ;; when they can apply. It goes before the add/sub insns
1345 ;; so we will prefer it to them.
1347 (define_insn "pushasi"
1348 [(set (match_operand:SI 0 "push_operand" "=m")
1349 (match_operand:SI 1 "address_operand" "p"))]
1353 ;; truncation instructions
1354 (define_insn "truncsiqi2"
1355 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1357 (match_operand:SI 1 "general_operand" "doJ,i")))]
1361 if (GET_CODE (operands[0]) == REG)
1363 /* Must clear condition codes, since the move.l bases them on
1364 the entire 32 bits, not just the desired 8 bits. */
1366 return \"move%.l %1,%0\";
1368 if (GET_CODE (operands[1]) == MEM)
1369 operands[1] = adj_offsettable_operand (operands[1], 3);
1370 return \"move%.b %1,%0\";
1373 (define_insn "trunchiqi2"
1374 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1376 (match_operand:HI 1 "general_operand" "doJ,i")))]
1380 if (GET_CODE (operands[0]) == REG
1381 && (GET_CODE (operands[1]) == MEM
1382 || GET_CODE (operands[1]) == CONST_INT))
1384 /* Must clear condition codes, since the move.w bases them on
1385 the entire 16 bits, not just the desired 8 bits. */
1387 return \"move%.w %1,%0\";
1389 if (GET_CODE (operands[0]) == REG)
1391 /* Must clear condition codes, since the move.l bases them on
1392 the entire 32 bits, not just the desired 8 bits. */
1394 return \"move%.l %1,%0\";
1396 if (GET_CODE (operands[1]) == MEM)
1397 operands[1] = adj_offsettable_operand (operands[1], 1);
1398 return \"move%.b %1,%0\";
1401 (define_insn "truncsihi2"
1402 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1404 (match_operand:SI 1 "general_operand" "roJ,i")))]
1408 if (GET_CODE (operands[0]) == REG)
1410 /* Must clear condition codes, since the move.l bases them on
1411 the entire 32 bits, not just the desired 8 bits. */
1413 return \"move%.l %1,%0\";
1415 if (GET_CODE (operands[1]) == MEM)
1416 operands[1] = adj_offsettable_operand (operands[1], 2);
1417 return \"move%.w %1,%0\";
1420 ;; zero extension instructions
1422 ;; this is the canonical form for (lshiftrt:DI x 32)
1423 (define_insn "zero_extendsidi2"
1424 [(set (match_operand:DI 0 "general_operand" "ro,<,>")
1425 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,rm,rm")))]
1430 if (which_alternative == 2)
1431 return \"clr%.l %0\;move%.l %1,%0\";
1432 if (which_alternative == 1)
1433 return \"move%.l %1,%0\;clr%.l %0\";
1434 if (GET_CODE (operands[0]) == REG)
1435 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1437 operands[2] = adj_offsettable_operand (operands[0], 4);
1438 if (ADDRESS_REG_P (operands[0]))
1439 return \"move%.l %1,%2\;sub%.l %0,%0\";
1441 return \"move%.l %1,%2\;clr%.l %0\";
1444 (define_expand "zero_extendhisi2"
1445 [(set (match_operand:SI 0 "register_operand" "")
1447 (set (strict_low_part (match_dup 2))
1448 (match_operand:HI 1 "general_operand" ""))]
1452 operands[1] = make_safe_from (operands[1], operands[0]);
1453 if (GET_CODE (operands[0]) == SUBREG)
1454 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1455 SUBREG_WORD (operands[0]));
1457 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1460 (define_expand "zero_extendqihi2"
1461 [(set (match_operand:HI 0 "register_operand" "")
1463 (set (strict_low_part (match_dup 2))
1464 (match_operand:QI 1 "general_operand" ""))]
1468 operands[1] = make_safe_from (operands[1], operands[0]);
1469 if (GET_CODE (operands[0]) == SUBREG)
1470 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1471 SUBREG_WORD (operands[0]));
1473 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1476 (define_expand "zero_extendqisi2"
1477 [(set (match_operand:SI 0 "register_operand" "")
1479 (set (strict_low_part (match_dup 2))
1480 (match_operand:QI 1 "general_operand" ""))]
1484 operands[1] = make_safe_from (operands[1], operands[0]);
1485 if (GET_CODE (operands[0]) == SUBREG)
1486 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1487 SUBREG_WORD (operands[0]));
1489 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1492 ;; Patterns to recognize zero-extend insns produced by the combiner.
1493 ;; We don't allow both operands in memory, because of aliasing problems.
1494 ;; Explicitly disallow two memory operands via the condition since reloading
1495 ;; of this case will result in worse code than the uncombined patterns.
1498 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1499 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1500 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1503 if (DATA_REG_P (operands[0]))
1505 if (GET_CODE (operands[1]) == REG
1506 && REGNO (operands[0]) == REGNO (operands[1]))
1507 return \"and%.l %#0xFFFF,%0\";
1508 if (reg_mentioned_p (operands[0], operands[1]))
1509 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1510 return \"clr%.l %0\;move%.w %1,%0\";
1512 else if (GET_CODE (operands[0]) == MEM
1513 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1514 return \"move%.w %1,%0\;clr%.w %0\";
1515 else if (GET_CODE (operands[0]) == MEM
1516 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1517 return \"clr%.w %0\;move%.w %1,%0\";
1520 output_asm_insn (\"clr%.w %0\", operands);
1521 operands[0] = adj_offsettable_operand (operands[0], 2);
1522 return \"move%.w %1,%0\";
1527 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1528 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1529 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1532 if (DATA_REG_P (operands[0]))
1534 if (GET_CODE (operands[1]) == REG
1535 && REGNO (operands[0]) == REGNO (operands[1]))
1536 return \"and%.w %#0xFF,%0\";
1537 if (reg_mentioned_p (operands[0], operands[1]))
1538 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1539 return \"clr%.w %0\;move%.b %1,%0\";
1541 else if (GET_CODE (operands[0]) == MEM
1542 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1544 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1545 == STACK_POINTER_REGNUM)
1547 output_asm_insn (\"clr%.w %-\", operands);
1548 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1549 plus_constant (stack_pointer_rtx, 1));
1550 return \"move%.b %1,%0\";
1553 return \"move%.b %1,%0\;clr%.b %0\";
1555 else if (GET_CODE (operands[0]) == MEM
1556 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1557 return \"clr%.b %0\;move%.b %1,%0\";
1560 output_asm_insn (\"clr%.b %0\", operands);
1561 operands[0] = adj_offsettable_operand (operands[0], 1);
1562 return \"move%.b %1,%0\";
1567 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1568 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1569 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1572 if (DATA_REG_P (operands[0]))
1574 if (GET_CODE (operands[1]) == REG
1575 && REGNO (operands[0]) == REGNO (operands[1]))
1576 return \"and%.l %#0xFF,%0\";
1577 if (reg_mentioned_p (operands[0], operands[1]))
1578 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1579 return \"clr%.l %0\;move%.b %1,%0\";
1581 else if (GET_CODE (operands[0]) == MEM
1582 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1584 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1587 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1589 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1592 return \"clrl %0@-\;moveb %1,%0@(3)\";
1595 else if (GET_CODE (operands[0]) == MEM
1596 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1598 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1601 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1603 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1606 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1611 output_asm_insn (\"clr%.l %0\", operands);
1612 operands[0] = adj_offsettable_operand (operands[0], 3);
1613 return \"move%.b %1,%0\";
1617 ;; sign extension instructions
1619 (define_insn "extendqidi2"
1620 [(set (match_operand:DI 0 "general_operand" "=d")
1622 (match_operand:QI 1 "general_operand" "rm")))]
1627 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1629 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1631 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1634 (define_insn "extendhidi2"
1635 [(set (match_operand:DI 0 "general_operand" "=d")
1637 (match_operand:HI 1 "general_operand" "rm")))]
1642 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1644 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1646 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1649 (define_insn "extendsidi2"
1650 [(set (match_operand:DI 0 "general_operand" "=d")
1652 (match_operand:SI 1 "general_operand" "rm")))]
1657 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1659 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1661 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1664 ;; Special case when one can avoid register clobbering, copy and test
1665 ;; Maybe there is a way to make that the general case, by forcing the
1666 ;; result of the SI tree to be in the lower register of the DI target
1668 (define_insn "extendplussidi"
1669 [(set (match_operand:DI 0 "register_operand" "=d")
1670 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1671 (match_operand:SI 2 "general_operand" "rmn"))))]
1676 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1677 if (GET_CODE (operands[1]) == CONST_INT
1678 && (unsigned) INTVAL (operands[1]) > 8)
1680 rtx tmp = operands[1];
1682 operands[1] = operands[2];
1686 return \"move%.l %2,%3\;add%.l %1,%3\;smi %0\;extb%.l %0\";
1688 return \"move%.l %2,%3\;add%.l %1,%3\;smi %0\;ext%.w %0\;ext%.l %0\";
1691 (define_insn "extendhisi2"
1692 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1694 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1698 if (ADDRESS_REG_P (operands[0]))
1699 return \"move%.w %1,%0\";
1700 return \"ext%.l %0\";
1703 (define_insn "extendqihi2"
1704 [(set (match_operand:HI 0 "general_operand" "=d")
1705 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1709 (define_insn "extendqisi2"
1710 [(set (match_operand:SI 0 "general_operand" "=d")
1711 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1715 ;; Conversions between float and double.
1717 (define_expand "extendsfdf2"
1718 [(set (match_operand:DF 0 "general_operand" "")
1720 (match_operand:SF 1 "general_operand" "")))]
1721 "TARGET_68881 || TARGET_FPA"
1725 [(set (match_operand:DF 0 "general_operand" "=x,y")
1727 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1732 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1734 (match_operand:SF 1 "general_operand" "f,dmF")))]
1738 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1740 if (REGNO (operands[0]) == REGNO (operands[1]))
1742 /* Extending float to double in an fp-reg is a no-op.
1743 NOTICE_UPDATE_CC has already assumed that the
1744 cc will be set. So cancel what it did. */
1745 cc_status = cc_prev_status;
1748 return \"f%&move%.x %1,%0\";
1750 if (FP_REG_P (operands[0]))
1751 return \"f%&move%.s %f1,%0\";
1752 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1754 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1755 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1756 return \"move%.l %+,%0\";
1758 return \"fmove%.d %f1,%0\";
1761 ;; This cannot output into an f-reg because there is no way to be
1762 ;; sure of truncating in that case.
1763 ;; But on the Sun FPA, we can be sure.
1764 (define_expand "truncdfsf2"
1765 [(set (match_operand:SF 0 "general_operand" "")
1767 (match_operand:DF 1 "general_operand" "")))]
1768 "TARGET_68881 || TARGET_FPA"
1772 [(set (match_operand:SF 0 "general_operand" "=x,y")
1774 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1778 ;; On the '040 we can truncate in a register accurately and easily.
1780 [(set (match_operand:SF 0 "general_operand" "=f")
1782 (match_operand:DF 1 "general_operand" "fmG")))]
1786 if (FP_REG_P (operands[1]))
1787 return \"f%$move%.x %1,%0\";
1788 return \"f%$move%.d %f1,%0\";
1792 [(set (match_operand:SF 0 "general_operand" "=dm")
1794 (match_operand:DF 1 "general_operand" "f")))]
1798 ;; Conversion between fixed point and floating point.
1799 ;; Note that among the fix-to-float insns
1800 ;; the ones that start with SImode come first.
1801 ;; That is so that an operand that is a CONST_INT
1802 ;; (and therefore lacks a specific machine mode).
1803 ;; will be recognized as SImode (which is always valid)
1804 ;; rather than as QImode or HImode.
1806 (define_expand "floatsisf2"
1807 [(set (match_operand:SF 0 "general_operand" "")
1808 (float:SF (match_operand:SI 1 "general_operand" "")))]
1809 "TARGET_68881 || TARGET_FPA"
1813 [(set (match_operand:SF 0 "general_operand" "=y,x")
1814 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1819 [(set (match_operand:SF 0 "general_operand" "=f")
1820 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1824 (define_expand "floatsidf2"
1825 [(set (match_operand:DF 0 "general_operand" "")
1826 (float:DF (match_operand:SI 1 "general_operand" "")))]
1827 "TARGET_68881 || TARGET_FPA"
1831 [(set (match_operand:DF 0 "general_operand" "=y,x")
1832 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1837 [(set (match_operand:DF 0 "general_operand" "=f")
1838 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1842 (define_insn "floathisf2"
1843 [(set (match_operand:SF 0 "general_operand" "=f")
1844 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1848 (define_insn "floathidf2"
1849 [(set (match_operand:DF 0 "general_operand" "=f")
1850 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1854 (define_insn "floatqisf2"
1855 [(set (match_operand:SF 0 "general_operand" "=f")
1856 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1860 (define_insn "floatqidf2"
1861 [(set (match_operand:DF 0 "general_operand" "=f")
1862 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1866 ;; New routines to convert floating-point values to integers
1867 ;; to be used on the '040. These should be faster than trapping
1868 ;; into the kernel to emulate fintrz. They should also be faster
1869 ;; than calling the subroutines fixsfsi or fixdfsi.
1871 (define_insn "fix_truncdfsi2"
1872 [(set (match_operand:SI 0 "general_operand" "=dm")
1873 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1874 (clobber (match_scratch:SI 2 "=d"))
1875 (clobber (match_scratch:SI 3 "=d"))]
1876 "TARGET_68881 && TARGET_68040"
1880 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1883 (define_insn "fix_truncdfhi2"
1884 [(set (match_operand:HI 0 "general_operand" "=dm")
1885 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1886 (clobber (match_scratch:SI 2 "=d"))
1887 (clobber (match_scratch:SI 3 "=d"))]
1888 "TARGET_68881 && TARGET_68040"
1892 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1895 (define_insn "fix_truncdfqi2"
1896 [(set (match_operand:QI 0 "general_operand" "=dm")
1897 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1898 (clobber (match_scratch:SI 2 "=d"))
1899 (clobber (match_scratch:SI 3 "=d"))]
1900 "TARGET_68881 && TARGET_68040"
1904 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1907 ;; Convert a float to a float whose value is an integer.
1908 ;; This is the first stage of converting it to an integer type.
1910 (define_insn "ftruncdf2"
1911 [(set (match_operand:DF 0 "general_operand" "=f")
1912 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1913 "TARGET_68881 && !TARGET_68040 && !TARGET_68060"
1916 if (FP_REG_P (operands[1]))
1917 return \"fintrz%.x %f1,%0\";
1918 return \"fintrz%.d %f1,%0\";
1921 (define_insn "ftruncsf2"
1922 [(set (match_operand:SF 0 "general_operand" "=f")
1923 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1924 "TARGET_68881 && !TARGET_68040 && !TARGET_68060"
1927 if (FP_REG_P (operands[1]))
1928 return \"fintrz%.x %f1,%0\";
1929 return \"fintrz%.s %f1,%0\";
1932 ;; Convert a float whose value is an integer
1933 ;; to an actual integer. Second stage of converting float to integer type.
1934 (define_insn "fixsfqi2"
1935 [(set (match_operand:QI 0 "general_operand" "=dm")
1936 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1940 (define_insn "fixsfhi2"
1941 [(set (match_operand:HI 0 "general_operand" "=dm")
1942 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1946 (define_insn "fixsfsi2"
1947 [(set (match_operand:SI 0 "general_operand" "=dm")
1948 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1952 (define_insn "fixdfqi2"
1953 [(set (match_operand:QI 0 "general_operand" "=dm")
1954 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1958 (define_insn "fixdfhi2"
1959 [(set (match_operand:HI 0 "general_operand" "=dm")
1960 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1964 (define_insn "fixdfsi2"
1965 [(set (match_operand:SI 0 "general_operand" "=dm")
1966 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1970 ;; Convert a float to an integer.
1971 ;; On the Sun FPA, this is done in one step.
1974 [(set (match_operand:SI 0 "general_operand" "=x,y")
1975 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1980 [(set (match_operand:SI 0 "general_operand" "=x,y")
1981 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1987 (define_insn "adddi_lshrdi_63"
1988 [(set (match_operand:DI 0 "general_operand" "=d")
1989 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1992 (clobber (match_scratch:SI 2 "=d"))]
1996 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1997 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1999 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2000 if (GET_CODE (operands[1]) == REG)
2001 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2002 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2003 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2004 operands[4] = operands[1];
2006 operands[4] = adj_offsettable_operand (operands[1], 4);
2007 if (GET_CODE (operands[1]) == MEM
2008 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2009 output_asm_insn (\"move%.l %4,%3\", operands);
2010 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2012 output_asm_insn (\"extb%.l %2\", operands);
2014 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2015 if (GET_CODE (operands[1]) != MEM
2016 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2017 output_asm_insn (\"move%.l %4,%3\", operands);
2018 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2021 (define_insn "adddi_sexthishl32"
2022 [(set (match_operand:DI 0 "general_operand" "=o,d,a")
2023 (plus:DI (ashift:DI (sign_extend:DI
2024 (match_operand:HI 1 "general_operand" "rm,rm,rm"))
2026 (match_operand:DI 2 "general_operand" "0,0,0")))
2027 (clobber (match_scratch:SI 3 "=&d*a,a*d,X"))]
2032 if (ADDRESS_REG_P (operands[0]))
2033 return \"add%.w %1,%0\";
2034 else if (DATA_REG_P (operands[3]))
2035 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2036 else if (DATA_REG_P (operands[0]))
2037 return \"move%.w %1,%3\;add%.l %3,%0\";
2039 return \"move%.l %0,%3\;add%.w %1,%3\;mov%.l %3,%0\";
2042 (define_insn "adddi_dilshr32"
2043 [(set (match_operand:DI 0 "general_operand" "=do")
2044 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2045 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2046 ;; (const_int 32))))]
2047 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2049 (match_operand:DI 2 "general_operand" "0")))]
2054 if (GET_CODE (operands[0]) == REG)
2055 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2057 operands[2] = adj_offsettable_operand (operands[0], 4);
2058 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2061 (define_insn "adddi_dishl32"
2062 [(set (match_operand:DI 0 "general_operand" "=ro")
2063 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2064 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2065 ;; (const_int 32))))]
2066 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2068 (match_operand:DI 2 "general_operand" "0")))]
2073 if (GET_CODE (operands[1]) == REG)
2074 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2076 operands[1] = adj_offsettable_operand (operands[1], 4);
2077 return \"add%.l %1,%0\";
2080 (define_insn "adddi3"
2081 [(set (match_operand:DI 0 "general_operand" "=d,<,d,o<>")
2082 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
2083 (match_operand:DI 2 "general_operand" "d,<,*ao>,d")))
2084 (clobber (match_scratch:SI 3 "=X,X,&d,&d"))]
2088 if (DATA_REG_P (operands[0]))
2090 if (DATA_REG_P (operands[2]))
2091 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2092 else if (GET_CODE (operands[2]) == MEM
2093 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2095 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2099 /* TODO : this should work also for CONST operands[2] */
2100 if (GET_CODE (operands[2]) == REG)
2101 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2103 operands[1] = adj_offsettable_operand (operands[2], 4);
2104 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2107 else if (GET_CODE (operands[0]) == MEM)
2109 if (GET_CODE (operands[2]) == MEM
2110 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2111 return \"add%.l %2,%0\;addx%.l %2,%0\";
2113 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2115 operands[1] = gen_rtx (MEM, SImode,
2116 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2117 gen_rtx (CONST_INT, VOIDmode, -8)));
2118 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2120 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2122 operands[1] = XEXP(operands[0], 0);
2123 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2127 operands[1] = adj_offsettable_operand (operands[0], 4);
2128 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2133 (define_insn "addsi_lshrsi_31"
2134 [(set (match_operand:SI 0 "general_operand" "=dm")
2135 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2141 operands[2] = operands[0];
2142 operands[3] = gen_label_rtx();
2143 if (GET_CODE (operands[0]) == MEM)
2145 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2146 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2147 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2148 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2150 output_asm_insn (\"move%.l %1,%0\", operands);
2152 output_asm_insn (\"jbpl %l3\", operands);
2154 output_asm_insn (\"jpl %l3\", operands);
2157 output_asm_insn (\"addq%.l %#1,%2\", operands);
2159 output_asm_insn (\"add%.l %#1,%2\", operands);
2161 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2162 CODE_LABEL_NUMBER (operands[3]));
2166 ;; Note that the middle two alternatives are near-duplicates
2167 ;; in order to handle insns generated by reload.
2168 ;; This is needed since they are not themselves reloaded,
2169 ;; so commutativity won't apply to them.
2170 (define_insn "addsi3"
2171 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2172 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2173 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2177 if (! operands_match_p (operands[0], operands[1]))
2179 if (!ADDRESS_REG_P (operands[1]))
2181 rtx tmp = operands[1];
2183 operands[1] = operands[2];
2187 /* These insns can result from reloads to access
2188 stack slots over 64k from the frame pointer. */
2189 if (GET_CODE (operands[2]) == CONST_INT
2190 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2191 return \"move%.l %2,%0\;add%.l %1,%0\";
2193 if (GET_CODE (operands[2]) == REG)
2194 return \"lea 0(%1,%2.l),%0\";
2196 return \"lea %c2(%1),%0\";
2199 if (GET_CODE (operands[2]) == REG)
2200 return \"lea (%1,%2.l),%0\";
2202 return \"lea (%c2,%1),%0\";
2203 #else /* not MOTOROLA (MIT syntax) */
2204 if (GET_CODE (operands[2]) == REG)
2205 return \"lea %1@(0,%2:l),%0\";
2207 return \"lea %1@(%c2),%0\";
2208 #endif /* not MOTOROLA */
2209 #endif /* not SGS */
2211 if (GET_CODE (operands[2]) == CONST_INT)
2214 if (INTVAL (operands[2]) > 0
2215 && INTVAL (operands[2]) <= 8)
2216 return (ADDRESS_REG_P (operands[0])
2218 : \"addq%.l %2,%0\");
2219 if (INTVAL (operands[2]) < 0
2220 && INTVAL (operands[2]) >= -8)
2222 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2223 - INTVAL (operands[2]));
2224 return (ADDRESS_REG_P (operands[0])
2226 : \"subq%.l %2,%0\");
2228 /* On everything except the 68000 it is faster to use two
2229 addqw instructions to add a small integer (8 < N <= 16)
2230 to an address register. Likewise for subqw.*/
2231 if (INTVAL (operands[2]) > 8
2232 && INTVAL (operands[2]) <= 16
2233 && ADDRESS_REG_P (operands[0])
2236 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8);
2237 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2239 if (INTVAL (operands[2]) < -8
2240 && INTVAL (operands[2]) >= -16
2241 && ADDRESS_REG_P (operands[0])
2244 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2245 - INTVAL (operands[2]) - 8);
2246 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2249 if (ADDRESS_REG_P (operands[0])
2250 && INTVAL (operands[2]) >= -0x8000
2251 && INTVAL (operands[2]) < 0x8000)
2252 return \"add%.w %2,%0\";
2254 return \"add%.l %2,%0\";
2258 [(set (match_operand:SI 0 "general_operand" "=a")
2259 (plus:SI (match_operand:SI 1 "general_operand" "0")
2261 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2265 (define_insn "addhi3"
2266 [(set (match_operand:HI 0 "general_operand" "=m,r")
2267 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2268 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2273 if (GET_CODE (operands[2]) == CONST_INT)
2275 /* If the constant would be a negative number when interpreted as
2276 HImode, make it negative. This is usually, but not always, done
2277 elsewhere in the compiler. First check for constants out of range,
2278 which could confuse us. */
2280 if (INTVAL (operands[2]) >= 32768)
2281 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2282 INTVAL (operands[2]) - 65536);
2284 if (INTVAL (operands[2]) > 0
2285 && INTVAL (operands[2]) <= 8)
2286 return \"addq%.w %2,%0\";
2287 if (INTVAL (operands[2]) < 0
2288 && INTVAL (operands[2]) >= -8)
2290 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2291 - INTVAL (operands[2]));
2292 return \"subq%.w %2,%0\";
2294 /* On everything except the 68000 it is faster to use two
2295 addqw instructions to add a small integer (8 < N <= 16)
2296 to an address register. Likewise for subqw. */
2297 if (INTVAL (operands[2]) > 8
2298 && INTVAL (operands[2]) <= 16
2299 && ADDRESS_REG_P (operands[0])
2302 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8);
2303 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2305 if (INTVAL (operands[2]) < -8
2306 && INTVAL (operands[2]) >= -16
2307 && ADDRESS_REG_P (operands[0])
2310 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2311 - INTVAL (operands[2]) - 8);
2312 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2316 return \"add%.w %2,%0\";
2319 ;; These insns must use MATCH_DUP instead of the more expected
2320 ;; use of a matching constraint because the "output" here is also
2321 ;; an input, so you can't use the matching constraint. That also means
2322 ;; that you can't use the "%", so you need patterns with the matched
2323 ;; operand in both positions.
2326 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2327 (plus:HI (match_dup 0)
2328 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2333 if (GET_CODE (operands[1]) == CONST_INT)
2335 /* If the constant would be a negative number when interpreted as
2336 HImode, make it negative. This is usually, but not always, done
2337 elsewhere in the compiler. First check for constants out of range,
2338 which could confuse us. */
2340 if (INTVAL (operands[1]) >= 32768)
2341 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2342 INTVAL (operands[1]) - 65536);
2344 if (INTVAL (operands[1]) > 0
2345 && INTVAL (operands[1]) <= 8)
2346 return \"addq%.w %1,%0\";
2347 if (INTVAL (operands[1]) < 0
2348 && INTVAL (operands[1]) >= -8)
2350 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2351 - INTVAL (operands[1]));
2352 return \"subq%.w %1,%0\";
2354 /* On everything except the 68000 it is faster to use two
2355 addqw instructions to add a small integer (8 < N <= 16)
2356 to an address register. Likewise for subqw. */
2357 if (INTVAL (operands[1]) > 8
2358 && INTVAL (operands[1]) <= 16
2359 && ADDRESS_REG_P (operands[0])
2362 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8);
2363 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2365 if (INTVAL (operands[1]) < -8
2366 && INTVAL (operands[1]) >= -16
2367 && ADDRESS_REG_P (operands[0])
2370 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2371 - INTVAL (operands[1]) - 8);
2372 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2376 return \"add%.w %1,%0\";
2380 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2381 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2387 if (GET_CODE (operands[1]) == CONST_INT)
2389 /* If the constant would be a negative number when interpreted as
2390 HImode, make it negative. This is usually, but not always, done
2391 elsewhere in the compiler. First check for constants out of range,
2392 which could confuse us. */
2394 if (INTVAL (operands[1]) >= 32768)
2395 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2396 INTVAL (operands[1]) - 65536);
2398 if (INTVAL (operands[1]) > 0
2399 && INTVAL (operands[1]) <= 8)
2400 return \"addq%.w %1,%0\";
2401 if (INTVAL (operands[1]) < 0
2402 && INTVAL (operands[1]) >= -8)
2404 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2405 - INTVAL (operands[1]));
2406 return \"subq%.w %1,%0\";
2408 /* On everything except the 68000 it is faster to use two
2409 addqw instructions to add a small integer (8 < N <= 16)
2410 to an address register. Likewise for subqw. */
2411 if (INTVAL (operands[1]) > 8
2412 && INTVAL (operands[1]) <= 16
2413 && ADDRESS_REG_P (operands[0])
2416 operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8);
2417 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2419 if (INTVAL (operands[1]) < -8
2420 && INTVAL (operands[1]) >= -16
2421 && ADDRESS_REG_P (operands[0])
2424 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2425 - INTVAL (operands[1]) - 8);
2426 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2430 return \"add%.w %1,%0\";
2433 (define_insn "addqi3"
2434 [(set (match_operand:QI 0 "general_operand" "=m,d")
2435 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2436 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2441 if (GET_CODE (operands[2]) == CONST_INT)
2443 if (INTVAL (operands[2]) >= 128)
2444 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2445 INTVAL (operands[2]) - 256);
2447 if (INTVAL (operands[2]) > 0
2448 && INTVAL (operands[2]) <= 8)
2449 return \"addq%.b %2,%0\";
2450 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2452 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2453 return \"subq%.b %2,%0\";
2457 return \"add%.b %2,%0\";
2461 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2462 (plus:QI (match_dup 0)
2463 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2468 if (GET_CODE (operands[1]) == CONST_INT)
2470 if (INTVAL (operands[1]) >= 128)
2471 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2472 INTVAL (operands[1]) - 256);
2474 if (INTVAL (operands[1]) > 0
2475 && INTVAL (operands[1]) <= 8)
2476 return \"addq%.b %1,%0\";
2477 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2479 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2480 return \"subq%.b %1,%0\";
2484 return \"add%.b %1,%0\";
2488 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2489 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2495 if (GET_CODE (operands[1]) == CONST_INT)
2497 if (INTVAL (operands[1]) >= 128)
2498 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2499 INTVAL (operands[1]) - 256);
2501 if (INTVAL (operands[1]) > 0
2502 && INTVAL (operands[1]) <= 8)
2503 return \"addq%.b %1,%0\";
2504 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2506 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2507 return \"subq%.b %1,%0\";
2511 return \"add%.b %1,%0\";
2514 (define_expand "adddf3"
2515 [(set (match_operand:DF 0 "general_operand" "")
2516 (plus:DF (match_operand:DF 1 "general_operand" "")
2517 (match_operand:DF 2 "general_operand" "")))]
2518 "TARGET_68881 || TARGET_FPA"
2522 [(set (match_operand:DF 0 "general_operand" "=x,y")
2523 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2524 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2528 if (rtx_equal_p (operands[0], operands[1]))
2529 return \"fpadd%.d %y2,%0\";
2530 if (rtx_equal_p (operands[0], operands[2]))
2531 return \"fpadd%.d %y1,%0\";
2532 if (which_alternative == 0)
2533 return \"fpadd3%.d %w2,%w1,%0\";
2534 return \"fpadd3%.d %x2,%x1,%0\";
2538 [(set (match_operand:DF 0 "general_operand" "=f")
2539 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2540 (match_operand:DF 1 "general_operand" "0")))]
2545 [(set (match_operand:DF 0 "general_operand" "=f")
2546 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2547 (match_operand:DF 1 "general_operand" "0")))]
2552 [(set (match_operand:DF 0 "general_operand" "=f")
2553 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2554 (match_operand:DF 1 "general_operand" "0")))]
2559 [(set (match_operand:DF 0 "general_operand" "=f")
2560 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2561 (match_operand:DF 2 "general_operand" "fmG")))]
2565 if (REG_P (operands[2]))
2566 return \"f%&add%.x %2,%0\";
2567 return \"f%&add%.d %f2,%0\";
2570 (define_expand "addsf3"
2571 [(set (match_operand:SF 0 "general_operand" "")
2572 (plus:SF (match_operand:SF 1 "general_operand" "")
2573 (match_operand:SF 2 "general_operand" "")))]
2574 "TARGET_68881 || TARGET_FPA"
2578 [(set (match_operand:SF 0 "general_operand" "=x,y")
2579 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2580 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2584 if (rtx_equal_p (operands[0], operands[1]))
2585 return \"fpadd%.s %w2,%0\";
2586 if (rtx_equal_p (operands[0], operands[2]))
2587 return \"fpadd%.s %w1,%0\";
2588 if (which_alternative == 0)
2589 return \"fpadd3%.s %w2,%w1,%0\";
2590 return \"fpadd3%.s %2,%1,%0\";
2594 [(set (match_operand:SF 0 "general_operand" "=f")
2595 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2596 (match_operand:SF 1 "general_operand" "0")))]
2601 [(set (match_operand:SF 0 "general_operand" "=f")
2602 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2603 (match_operand:SF 1 "general_operand" "0")))]
2608 [(set (match_operand:SF 0 "general_operand" "=f")
2609 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2610 (match_operand:SF 1 "general_operand" "0")))]
2615 [(set (match_operand:SF 0 "general_operand" "=f")
2616 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2617 (match_operand:SF 2 "general_operand" "fdmF")))]
2621 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2622 return \"f%$add%.x %2,%0\";
2623 return \"f%$add%.s %f2,%0\";
2626 ;; subtract instructions
2628 (define_insn "subdi_sexthishl32"
2629 [(set (match_operand:DI 0 "general_operand" "=o,d,a")
2630 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0")
2631 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm"))
2633 (clobber (match_scratch:SI 3 "=&d*a,a*d,X"))]
2638 if (ADDRESS_REG_P (operands[0]))
2639 return \"sub%.w %2,%0\";
2640 else if (DATA_REG_P (operands[3]))
2641 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2642 else if (DATA_REG_P (operands[0]))
2643 return \"move%.w %2,%3\;sub%.l %3,%0\";
2645 return \"move%.l %0,%3\;sub%.w %2,%3\;mov%.l %3,%0\";
2648 (define_insn "subdi_dishl32"
2649 [(set (match_operand:DI 0 "general_operand" "+ro")
2650 (minus:DI (match_dup 0)
2651 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2657 if (GET_CODE (operands[1]) == REG)
2658 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2660 operands[1] = adj_offsettable_operand (operands[1], 4);
2661 return \"sub%.l %1,%0\";
2664 (define_insn "subdi3"
2665 [(set (match_operand:DI 0 "general_operand" "=d,<,d,o<>")
2666 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2667 (match_operand:DI 2 "general_operand" "d,<,*ao>,d")))
2668 (clobber (match_scratch:SI 3 "=X,X,&d,&d"))]
2672 if (DATA_REG_P (operands[0]))
2674 if (DATA_REG_P (operands[2]))
2675 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2676 else if (GET_CODE (operands[2]) == MEM
2677 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2679 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2683 /* TODO : this should work also for CONST operands[2] */
2684 if (GET_CODE (operands[2]) == REG)
2685 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2687 operands[1] = adj_offsettable_operand (operands[2], 4);
2688 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2691 else if (GET_CODE (operands[0]) == MEM)
2693 if (GET_CODE (operands[2]) == MEM
2694 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2695 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2697 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2699 operands[1] = gen_rtx (MEM, SImode,
2700 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2701 gen_rtx (CONST_INT, VOIDmode, -8)));
2702 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2704 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2706 operands[1] = XEXP(operands[0], 0);
2707 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2711 operands[1] = adj_offsettable_operand (operands[0], 4);
2712 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2717 (define_insn "subsi3"
2718 [(set (match_operand:SI 0 "general_operand" "=m,r")
2719 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2720 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2725 [(set (match_operand:SI 0 "general_operand" "=a")
2726 (minus:SI (match_operand:SI 1 "general_operand" "0")
2728 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2732 (define_insn "subhi3"
2733 [(set (match_operand:HI 0 "general_operand" "=m,r")
2734 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2735 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2740 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2741 (minus:HI (match_dup 0)
2742 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2746 (define_insn "subqi3"
2747 [(set (match_operand:QI 0 "general_operand" "=m,d")
2748 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2749 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2754 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2755 (minus:QI (match_dup 0)
2756 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2760 (define_expand "subdf3"
2761 [(set (match_operand:DF 0 "general_operand" "")
2762 (minus:DF (match_operand:DF 1 "general_operand" "")
2763 (match_operand:DF 2 "general_operand" "")))]
2764 "TARGET_68881 || TARGET_FPA"
2768 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2769 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2770 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2774 if (rtx_equal_p (operands[0], operands[2]))
2775 return \"fprsub%.d %y1,%0\";
2776 if (rtx_equal_p (operands[0], operands[1]))
2777 return \"fpsub%.d %y2,%0\";
2778 if (which_alternative == 0)
2779 return \"fpsub3%.d %w2,%w1,%0\";
2780 return \"fpsub3%.d %x2,%x1,%0\";
2784 [(set (match_operand:DF 0 "general_operand" "=f")
2785 (minus:DF (match_operand:DF 1 "general_operand" "0")
2786 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2791 [(set (match_operand:DF 0 "general_operand" "=f")
2792 (minus:DF (match_operand:DF 1 "general_operand" "0")
2793 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2798 [(set (match_operand:DF 0 "general_operand" "=f")
2799 (minus:DF (match_operand:DF 1 "general_operand" "0")
2800 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2805 [(set (match_operand:DF 0 "general_operand" "=f")
2806 (minus:DF (match_operand:DF 1 "general_operand" "0")
2807 (match_operand:DF 2 "general_operand" "fmG")))]
2811 if (REG_P (operands[2]))
2812 return \"f%&sub%.x %2,%0\";
2813 return \"f%&sub%.d %f2,%0\";
2816 (define_expand "subsf3"
2817 [(set (match_operand:SF 0 "general_operand" "")
2818 (minus:SF (match_operand:SF 1 "general_operand" "")
2819 (match_operand:SF 2 "general_operand" "")))]
2820 "TARGET_68881 || TARGET_FPA"
2824 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2825 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2826 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2830 if (rtx_equal_p (operands[0], operands[2]))
2831 return \"fprsub%.s %w1,%0\";
2832 if (rtx_equal_p (operands[0], operands[1]))
2833 return \"fpsub%.s %w2,%0\";
2834 if (which_alternative == 0)
2835 return \"fpsub3%.s %w2,%w1,%0\";
2836 return \"fpsub3%.s %2,%1,%0\";
2840 [(set (match_operand:SF 0 "general_operand" "=f")
2841 (minus:SF (match_operand:SF 1 "general_operand" "0")
2842 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2847 [(set (match_operand:SF 0 "general_operand" "=f")
2848 (minus:SF (match_operand:SF 1 "general_operand" "0")
2849 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2854 [(set (match_operand:SF 0 "general_operand" "=f")
2855 (minus:SF (match_operand:SF 1 "general_operand" "0")
2856 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2861 [(set (match_operand:SF 0 "general_operand" "=f")
2862 (minus:SF (match_operand:SF 1 "general_operand" "0")
2863 (match_operand:SF 2 "general_operand" "fdmF")))]
2867 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2868 return \"f%$sub%.x %2,%0\";
2869 return \"f%$sub%.s %f2,%0\";
2872 ;; multiply instructions
2874 (define_insn "mulhi3"
2875 [(set (match_operand:HI 0 "general_operand" "=d")
2876 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2877 (match_operand:HI 2 "general_operand" "dmn")))]
2881 #if defined(MOTOROLA) && !defined(CRDS)
2882 return \"muls%.w %2,%0\";
2884 return \"muls %2,%0\";
2888 (define_insn "mulhisi3"
2889 [(set (match_operand:SI 0 "general_operand" "=d")
2890 (mult:SI (sign_extend:SI
2891 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2893 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2897 #if defined(MOTOROLA) && !defined(CRDS)
2898 return \"muls%.w %2,%0\";
2900 return \"muls %2,%0\";
2905 [(set (match_operand:SI 0 "general_operand" "=d")
2906 (mult:SI (sign_extend:SI
2907 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2908 (match_operand:SI 2 "const_int_operand" "n")))]
2909 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2912 #if defined(MOTOROLA) && !defined(CRDS)
2913 return \"muls%.w %2,%0\";
2915 return \"muls %2,%0\";
2919 (define_insn "mulsi3"
2920 [(set (match_operand:SI 0 "general_operand" "=d")
2921 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2922 (match_operand:SI 2 "general_operand" "dmsK")))]
2926 (define_insn "umulhisi3"
2927 [(set (match_operand:SI 0 "general_operand" "=d")
2928 (mult:SI (zero_extend:SI
2929 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2931 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2935 #if defined(MOTOROLA) && !defined(CRDS)
2936 return \"mulu%.w %2,%0\";
2938 return \"mulu %2,%0\";
2943 [(set (match_operand:SI 0 "general_operand" "=d")
2944 (mult:SI (zero_extend:SI
2945 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2946 (match_operand:SI 2 "const_int_operand" "n")))]
2947 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2950 #if defined(MOTOROLA) && !defined(CRDS)
2951 return \"mulu%.w %2,%0\";
2953 return \"mulu %2,%0\";
2957 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2958 ;; proper matching constraint. This is because the matching is between
2959 ;; the high-numbered word of the DImode operand[0] and operand[1].
2960 (define_expand "umulsidi3"
2962 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2963 (mult:SI (match_operand:SI 1 "register_operand" "")
2964 (match_operand:SI 2 "nonimmediate_operand" "")))
2965 (set (subreg:SI (match_dup 0) 0)
2966 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2967 (zero_extend:DI (match_dup 2)))
2968 (const_int 32))))])]
2969 "TARGET_68020 && !TARGET_68060"
2973 [(set (match_operand:SI 0 "register_operand" "=d")
2974 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2975 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2976 (set (match_operand:SI 3 "register_operand" "=d")
2977 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2978 (zero_extend:DI (match_dup 2)))
2980 "TARGET_68020 && !TARGET_68060"
2983 ; Match immediate case. For 2.4 only match things < 2^31.
2984 ; It's tricky with larger values in these patterns since we need to match
2985 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2988 [(set (match_operand:SI 0 "register_operand" "=d")
2989 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2990 (match_operand:SI 2 "const_int_operand" "n")))
2991 (set (match_operand:SI 3 "register_operand" "=d")
2992 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2995 "TARGET_68020 && !TARGET_68060
2996 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2999 (define_expand "mulsidi3"
3001 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3002 (mult:SI (match_operand:SI 1 "register_operand" "")
3003 (match_operand:SI 2 "nonimmediate_operand" "")))
3004 (set (subreg:SI (match_dup 0) 0)
3005 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3006 (sign_extend:DI (match_dup 2)))
3007 (const_int 32))))])]
3008 "TARGET_68020 && !TARGET_68060"
3012 [(set (match_operand:SI 0 "register_operand" "=d")
3013 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3014 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3015 (set (match_operand:SI 3 "register_operand" "=d")
3016 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3017 (sign_extend:DI (match_dup 2)))
3019 "TARGET_68020 && !TARGET_68060"
3023 [(set (match_operand:SI 0 "register_operand" "=d")
3024 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3025 (match_operand:SI 2 "const_int_operand" "n")))
3026 (set (match_operand:SI 3 "register_operand" "=d")
3027 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3030 "TARGET_68020 && !TARGET_68060
3031 /* This test is a noop on 32 bit machines,
3032 but important for a cross-compiler hosted on 64-bit machines. */
3033 && INTVAL (operands[2]) <= 0x7fffffff
3034 && INTVAL (operands[2]) >= -0x80000000"
3037 (define_expand "umulsi3_highpart"
3039 [(set (match_operand:SI 0 "register_operand" "")
3042 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3043 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3045 (clobber (match_dup 3))])]
3046 "TARGET_68020 && !TARGET_68060"
3049 operands[3] = gen_reg_rtx (SImode);
3050 if (GET_CODE (operands[2]) == CONST_INT
3051 || GET_CODE (operands[2]) == CONST_DOUBLE)
3053 if (! const_uint32_operand (operands[2], VOIDmode))
3055 /* We have to adjust the operand order for the matching constraints. */
3056 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3057 operands[1], operands[2]));
3063 [(set (match_operand:SI 0 "register_operand" "=d")
3066 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3067 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3069 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3070 "TARGET_68020 && !TARGET_68060"
3073 (define_insn "const_umulsi3_highpart"
3074 [(set (match_operand:SI 0 "register_operand" "=d")
3077 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3078 (match_operand 3 "const_uint32_operand" ""))
3080 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3081 "TARGET_68020 && !TARGET_68060"
3084 (define_expand "smulsi3_highpart"
3086 [(set (match_operand:SI 0 "register_operand" "")
3089 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3090 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3092 (clobber (match_dup 3))])]
3093 "TARGET_68020 && !TARGET_68060"
3096 operands[3] = gen_reg_rtx (SImode);
3097 if (GET_CODE (operands[2]) == CONST_INT
3098 || GET_CODE (operands[2]) == CONST_DOUBLE)
3100 if (! const_sint32_operand (operands[2], VOIDmode))
3102 /* We have to adjust the operand order for the matching constraints. */
3103 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3104 operands[1], operands[2]));
3110 [(set (match_operand:SI 0 "register_operand" "=d")
3113 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3114 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3116 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3117 "TARGET_68020 && !TARGET_68060"
3120 (define_insn "const_smulsi3_highpart"
3121 [(set (match_operand:SI 0 "register_operand" "=d")
3124 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3125 (match_operand 3 "const_sint32_operand" ""))
3127 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3128 "TARGET_68020 && !TARGET_68060"
3131 (define_expand "muldf3"
3132 [(set (match_operand:DF 0 "general_operand" "")
3133 (mult:DF (match_operand:DF 1 "general_operand" "")
3134 (match_operand:DF 2 "general_operand" "")))]
3135 "TARGET_68881 || TARGET_FPA"
3139 [(set (match_operand:DF 0 "general_operand" "=x,y")
3140 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3141 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3145 if (rtx_equal_p (operands[1], operands[2]))
3146 return \"fpsqr%.d %y1,%0\";
3147 if (rtx_equal_p (operands[0], operands[1]))
3148 return \"fpmul%.d %y2,%0\";
3149 if (rtx_equal_p (operands[0], operands[2]))
3150 return \"fpmul%.d %y1,%0\";
3151 if (which_alternative == 0)
3152 return \"fpmul3%.d %w2,%w1,%0\";
3153 return \"fpmul3%.d %x2,%x1,%0\";
3157 [(set (match_operand:DF 0 "general_operand" "=f")
3158 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3159 (match_operand:DF 1 "general_operand" "0")))]
3164 [(set (match_operand:DF 0 "general_operand" "=f")
3165 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3166 (match_operand:DF 1 "general_operand" "0")))]
3171 [(set (match_operand:DF 0 "general_operand" "=f")
3172 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3173 (match_operand:DF 1 "general_operand" "0")))]
3178 [(set (match_operand:DF 0 "general_operand" "=f")
3179 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3180 (match_operand:DF 2 "general_operand" "fmG")))]
3184 if (GET_CODE (operands[2]) == CONST_DOUBLE
3185 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3187 int i = floating_exact_log2 (operands[2]);
3188 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3189 return \"fscale%.l %2,%0\";
3191 if (REG_P (operands[2]))
3192 return \"f%&mul%.x %2,%0\";
3193 return \"f%&mul%.d %f2,%0\";
3196 (define_expand "mulsf3"
3197 [(set (match_operand:SF 0 "general_operand" "")
3198 (mult:SF (match_operand:SF 1 "general_operand" "")
3199 (match_operand:SF 2 "general_operand" "")))]
3200 "TARGET_68881 || TARGET_FPA"
3204 [(set (match_operand:SF 0 "general_operand" "=x,y")
3205 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3206 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3210 if (rtx_equal_p (operands[1], operands[2]))
3211 return \"fpsqr%.s %w1,%0\";
3212 if (rtx_equal_p (operands[0], operands[1]))
3213 return \"fpmul%.s %w2,%0\";
3214 if (rtx_equal_p (operands[0], operands[2]))
3215 return \"fpmul%.s %w1,%0\";
3216 if (which_alternative == 0)
3217 return \"fpmul3%.s %w2,%w1,%0\";
3218 return \"fpmul3%.s %2,%1,%0\";
3222 [(set (match_operand:SF 0 "general_operand" "=f")
3223 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3224 (match_operand:SF 1 "general_operand" "0")))]
3228 return (TARGET_68040_ONLY
3229 ? \"fsmul%.l %2,%0\"
3230 : \"fsglmul%.l %2,%0\");
3234 [(set (match_operand:SF 0 "general_operand" "=f")
3235 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3236 (match_operand:SF 1 "general_operand" "0")))]
3240 return (TARGET_68040_ONLY
3241 ? \"fsmul%.w %2,%0\"
3242 : \"fsglmul%.w %2,%0\");
3246 [(set (match_operand:SF 0 "general_operand" "=f")
3247 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3248 (match_operand:SF 1 "general_operand" "0")))]
3252 return (TARGET_68040_ONLY
3253 ? \"fsmul%.b %2,%0\"
3254 : \"fsglmul%.b %2,%0\");
3258 [(set (match_operand:SF 0 "general_operand" "=f")
3259 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3260 (match_operand:SF 2 "general_operand" "fdmF")))]
3264 #ifdef FSGLMUL_USE_S
3265 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3266 return (TARGET_68040_ONLY
3267 ? \"fsmul%.s %2,%0\"
3268 : \"fsglmul%.s %2,%0\");
3270 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3271 return (TARGET_68040_ONLY
3272 ? \"fsmul%.x %2,%0\"
3273 : \"fsglmul%.x %2,%0\");
3275 return (TARGET_68040_ONLY
3276 ? \"fsmul%.s %f2,%0\"
3277 : \"fsglmul%.s %f2,%0\");
3280 ;; divide instructions
3282 (define_expand "divdf3"
3283 [(set (match_operand:DF 0 "general_operand" "")
3284 (div:DF (match_operand:DF 1 "general_operand" "")
3285 (match_operand:DF 2 "general_operand" "")))]
3286 "TARGET_68881 || TARGET_FPA"
3290 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3291 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3292 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3296 if (rtx_equal_p (operands[0], operands[2]))
3297 return \"fprdiv%.d %y1,%0\";
3298 if (rtx_equal_p (operands[0], operands[1]))
3299 return \"fpdiv%.d %y2,%0\";
3300 if (which_alternative == 0)
3301 return \"fpdiv3%.d %w2,%w1,%0\";
3302 return \"fpdiv3%.d %x2,%x1,%x0\";
3306 [(set (match_operand:DF 0 "general_operand" "=f")
3307 (div:DF (match_operand:DF 1 "general_operand" "0")
3308 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3313 [(set (match_operand:DF 0 "general_operand" "=f")
3314 (div:DF (match_operand:DF 1 "general_operand" "0")
3315 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3320 [(set (match_operand:DF 0 "general_operand" "=f")
3321 (div:DF (match_operand:DF 1 "general_operand" "0")
3322 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3327 [(set (match_operand:DF 0 "general_operand" "=f")
3328 (div:DF (match_operand:DF 1 "general_operand" "0")
3329 (match_operand:DF 2 "general_operand" "fmG")))]
3333 if (REG_P (operands[2]))
3334 return \"f%&div%.x %2,%0\";
3335 return \"f%&div%.d %f2,%0\";
3338 (define_expand "divsf3"
3339 [(set (match_operand:SF 0 "general_operand" "")
3340 (div:SF (match_operand:SF 1 "general_operand" "")
3341 (match_operand:SF 2 "general_operand" "")))]
3342 "TARGET_68881 || TARGET_FPA"
3346 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3347 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3348 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3352 if (rtx_equal_p (operands[0], operands[1]))
3353 return \"fpdiv%.s %w2,%0\";
3354 if (rtx_equal_p (operands[0], operands[2]))
3355 return \"fprdiv%.s %w1,%0\";
3356 if (which_alternative == 0)
3357 return \"fpdiv3%.s %w2,%w1,%0\";
3358 return \"fpdiv3%.s %2,%1,%0\";
3362 [(set (match_operand:SF 0 "general_operand" "=f")
3363 (div:SF (match_operand:SF 1 "general_operand" "0")
3364 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3368 return (TARGET_68040_ONLY
3369 ? \"fsdiv%.l %2,%0\"
3370 : \"fsgldiv%.l %2,%0\");
3374 [(set (match_operand:SF 0 "general_operand" "=f")
3375 (div:SF (match_operand:SF 1 "general_operand" "0")
3376 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3380 return (TARGET_68040_ONLY
3381 ? \"fsdiv%.w %2,%0\"
3382 : \"fsgldiv%.w %2,%0\");
3386 [(set (match_operand:SF 0 "general_operand" "=f")
3387 (div:SF (match_operand:SF 1 "general_operand" "0")
3388 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3392 return (TARGET_68040_ONLY
3393 ? \"fsdiv%.b %2,%0\"
3394 : \"fsgldiv%.b %2,%0\");
3398 [(set (match_operand:SF 0 "general_operand" "=f")
3399 (div:SF (match_operand:SF 1 "general_operand" "0")
3400 (match_operand:SF 2 "general_operand" "fdmF")))]
3404 #ifdef FSGLDIV_USE_S
3405 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3406 return (TARGET_68040_ONLY
3407 ? \"fsdiv%.s %2,%0\"
3408 : \"fsgldiv%.s %2,%0\");
3410 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3411 return (TARGET_68040_ONLY
3412 ? \"fsdiv%.x %2,%0\"
3413 : \"fsgldiv%.x %2,%0\");
3415 return (TARGET_68040_ONLY
3416 ? \"fsdiv%.s %f2,%0\"
3417 : \"fsgldiv%.s %f2,%0\");
3420 ;; Remainder instructions.
3422 (define_insn "divmodsi4"
3423 [(set (match_operand:SI 0 "general_operand" "=d")
3424 (div:SI (match_operand:SI 1 "general_operand" "0")
3425 (match_operand:SI 2 "general_operand" "dmsK")))
3426 (set (match_operand:SI 3 "general_operand" "=d")
3427 (mod:SI (match_dup 1) (match_dup 2)))]
3431 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3432 return \"divs%.l %2,%0\";
3434 return \"divsl%.l %2,%3:%0\";
3437 (define_insn "udivmodsi4"
3438 [(set (match_operand:SI 0 "general_operand" "=d")
3439 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3440 (match_operand:SI 2 "general_operand" "dmsK")))
3441 (set (match_operand:SI 3 "general_operand" "=d")
3442 (umod:SI (match_dup 1) (match_dup 2)))]
3446 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3447 return \"divu%.l %2,%0\";
3449 return \"divul%.l %2,%3:%0\";
3452 (define_insn "divmodhi4"
3453 [(set (match_operand:HI 0 "general_operand" "=d")
3454 (div:HI (match_operand:HI 1 "general_operand" "0")
3455 (match_operand:HI 2 "general_operand" "dmsK")))
3456 (set (match_operand:HI 3 "general_operand" "=d")
3457 (mod:HI (match_dup 1) (match_dup 2)))]
3462 output_asm_insn(\"ext%.l %0\;divs%.w %2,%0\", operands);
3464 output_asm_insn(\"extl %0\;divs %2,%0\", operands);
3466 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3469 return \"move%.l %0,%3\;swap %3\";
3475 (define_insn "udivmodhi4"
3476 [(set (match_operand:HI 0 "general_operand" "=d")
3477 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3478 (match_operand:HI 2 "general_operand" "dmsK")))
3479 (set (match_operand:HI 3 "general_operand" "=d")
3480 (umod:HI (match_dup 1) (match_dup 2)))]
3485 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3487 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3489 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3492 return \"move%.l %0,%3\;swap %3\";
3498 ;; logical-and instructions
3500 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3501 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3502 ;; can't allocate pseudos into it.
3503 (define_insn "andsi3"
3504 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3505 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3506 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3511 if (GET_CODE (operands[2]) == CONST_INT
3512 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3513 && (DATA_REG_P (operands[0])
3514 || offsettable_memref_p (operands[0])))
3516 if (GET_CODE (operands[0]) != REG)
3517 operands[0] = adj_offsettable_operand (operands[0], 2);
3518 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3519 INTVAL (operands[2]) & 0xffff);
3520 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3522 if (operands[2] == const0_rtx)
3523 return \"clr%.w %0\";
3524 return \"and%.w %2,%0\";
3526 if (GET_CODE (operands[2]) == CONST_INT
3527 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3528 && (DATA_REG_P (operands[0])
3529 || offsettable_memref_p (operands[0])))
3531 if (DATA_REG_P (operands[0]))
3533 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3537 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3538 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3540 /* This does not set condition codes in a standard way. */
3542 return \"bclr %1,%0\";
3544 return \"and%.l %2,%0\";
3547 (define_insn "andhi3"
3548 [(set (match_operand:HI 0 "general_operand" "=m,d")
3549 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3550 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3555 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3556 (and:HI (match_dup 0)
3557 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3562 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3563 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3568 (define_insn "andqi3"
3569 [(set (match_operand:QI 0 "general_operand" "=m,d")
3570 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3571 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3576 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3577 (and:QI (match_dup 0)
3578 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3583 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3584 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3589 ;; inclusive-or instructions
3591 (define_insn "iorsi3"
3592 [(set (match_operand:SI 0 "general_operand" "=m,d")
3593 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3594 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3598 register int logval;
3599 if (GET_CODE (operands[2]) == CONST_INT
3600 && INTVAL (operands[2]) >> 16 == 0
3601 && (DATA_REG_P (operands[0])
3602 || offsettable_memref_p (operands[0])))
3604 if (GET_CODE (operands[0]) != REG)
3605 operands[0] = adj_offsettable_operand (operands[0], 2);
3606 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3608 return \"or%.w %2,%0\";
3610 if (GET_CODE (operands[2]) == CONST_INT
3611 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3612 && (DATA_REG_P (operands[0])
3613 || offsettable_memref_p (operands[0])))
3615 if (DATA_REG_P (operands[0]))
3617 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3621 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3622 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3625 return \"bset %1,%0\";
3627 return \"or%.l %2,%0\";
3630 (define_insn "iorhi3"
3631 [(set (match_operand:HI 0 "general_operand" "=m,d")
3632 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3633 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3638 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3639 (ior:HI (match_dup 0)
3640 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3645 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3646 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3651 (define_insn "iorqi3"
3652 [(set (match_operand:QI 0 "general_operand" "=m,d")
3653 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3654 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3659 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3660 (ior:QI (match_dup 0)
3661 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3666 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3667 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3673 [(set (match_operand:SI 0 "general_operand" "=o,d")
3674 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3675 (match_operand:SI 2 "general_operand" "0,0")))]
3682 byte_mode = (GET_MODE(operands[1]) == QImode);
3683 if (GET_CODE (operands[0]) == MEM)
3684 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3686 return \"or%.b %1,%0\";
3688 return \"or%.w %1,%0\";
3693 (define_insn "xorsi3"
3694 [(set (match_operand:SI 0 "general_operand" "=do,m")
3695 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3696 (match_operand:SI 2 "general_operand" "di,dKs")))]
3700 if (GET_CODE (operands[2]) == CONST_INT
3701 && INTVAL (operands[2]) >> 16 == 0
3702 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
3704 if (! DATA_REG_P (operands[0]))
3705 operands[0] = adj_offsettable_operand (operands[0], 2);
3706 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3708 return \"eor%.w %2,%0\";
3710 return \"eor%.l %2,%0\";
3713 (define_insn "xorhi3"
3714 [(set (match_operand:HI 0 "general_operand" "=dm")
3715 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3716 (match_operand:HI 2 "general_operand" "dn")))]
3721 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3722 (xor:HI (match_dup 0)
3723 (match_operand:HI 1 "general_operand" "dn")))]
3729 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3730 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3735 (define_insn "xorqi3"
3736 [(set (match_operand:QI 0 "general_operand" "=dm")
3737 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3738 (match_operand:QI 2 "general_operand" "dn")))]
3743 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3744 (xor:QI (match_dup 0)
3745 (match_operand:QI 1 "general_operand" "dn")))]
3750 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3751 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3756 ;; negation instructions
3758 (define_insn "negdi2"
3759 [(set (match_operand:DI 0 "general_operand" "=d*ao,<")
3760 (neg:DI (match_operand:DI 1 "general_operand" "0,0")))]
3764 if (which_alternative == 1)
3765 return \"neg%.l %0\;negx%.l %0\";
3766 if (GET_CODE (operands[0]) == REG)
3767 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3769 operands[1] = adj_offsettable_operand (operands[0], 4);
3770 if (ADDRESS_REG_P (operands[0]))
3771 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3773 return \"neg%.l %1\;negx%.l %0\";
3776 (define_insn "negsi2"
3777 [(set (match_operand:SI 0 "general_operand" "=dm")
3778 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3782 (define_insn "neghi2"
3783 [(set (match_operand:HI 0 "general_operand" "=dm")
3784 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3789 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3790 (neg:HI (match_dup 0)))]
3794 (define_insn "negqi2"
3795 [(set (match_operand:QI 0 "general_operand" "=dm")
3796 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3801 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3802 (neg:QI (match_dup 0)))]
3806 ;; If using software floating point, just flip the sign bit.
3808 (define_expand "negsf2"
3809 [(set (match_operand:SF 0 "general_operand" "")
3810 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3814 if (!TARGET_FPA && !TARGET_68881)
3819 target = operand_subword_force (operands[0], 0, SFmode);
3820 result = expand_binop (SImode, xor_optab,
3821 operand_subword_force (operands[1], 0, SFmode),
3822 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3826 if (result != target)
3827 emit_move_insn (result, target);
3829 /* Make a place for REG_EQUAL. */
3830 emit_move_insn (operands[0], operands[0]);
3836 [(set (match_operand:SF 0 "general_operand" "=x,y")
3837 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3842 [(set (match_operand:SF 0 "general_operand" "=f,d")
3843 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3847 if (DATA_REG_P (operands[0]))
3849 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3850 return \"bchg %1,%0\";
3852 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3853 return \"f%$neg%.x %1,%0\";
3854 return \"f%$neg%.s %f1,%0\";
3857 (define_expand "negdf2"
3858 [(set (match_operand:DF 0 "general_operand" "")
3859 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3863 if (!TARGET_FPA && !TARGET_68881)
3870 target = operand_subword (operands[0], 0, 1, DFmode);
3871 result = expand_binop (SImode, xor_optab,
3872 operand_subword_force (operands[1], 0, DFmode),
3873 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3877 if (result != target)
3878 emit_move_insn (result, target);
3880 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3881 operand_subword_force (operands[1], 1, DFmode));
3883 insns = get_insns ();
3886 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3892 [(set (match_operand:DF 0 "general_operand" "=x,y")
3893 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3898 [(set (match_operand:DF 0 "general_operand" "=f,d")
3899 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3903 if (DATA_REG_P (operands[0]))
3905 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3906 return \"bchg %1,%0\";
3908 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3909 return \"f%&neg%.x %1,%0\";
3910 return \"f%&neg%.d %f1,%0\";
3913 ;; Sqrt instruction for the 68881
3915 (define_insn "sqrtsf2"
3916 [(set (match_operand:SF 0 "general_operand" "=f")
3917 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3921 if (FP_REG_P (operands[1]))
3922 return \"f%$sqrt%.x %1,%0\";
3924 return \"f%$sqrt%.s %1,%0\";
3927 (define_insn "sqrtdf2"
3928 [(set (match_operand:DF 0 "general_operand" "=f")
3929 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3933 if (FP_REG_P (operands[1]))
3934 return \"f%&sqrt%.x %1,%0\";
3936 return \"f%&sqrt%.d %1,%0\";
3939 ;; Absolute value instructions
3940 ;; If using software floating point, just zero the sign bit.
3942 (define_expand "abssf2"
3943 [(set (match_operand:SF 0 "general_operand" "")
3944 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3948 if (!TARGET_FPA && !TARGET_68881)
3953 target = operand_subword_force (operands[0], 0, SFmode);
3954 result = expand_binop (SImode, and_optab,
3955 operand_subword_force (operands[1], 0, SFmode),
3956 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
3960 if (result != target)
3961 emit_move_insn (result, target);
3963 /* Make a place for REG_EQUAL. */
3964 emit_move_insn (operands[0], operands[0]);
3970 [(set (match_operand:SF 0 "general_operand" "=x,y")
3971 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3976 [(set (match_operand:SF 0 "general_operand" "=f")
3977 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
3981 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3982 return \"f%$abs%.x %1,%0\";
3983 return \"f%$abs%.s %f1,%0\";
3986 (define_expand "absdf2"
3987 [(set (match_operand:DF 0 "general_operand" "")
3988 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3992 if (!TARGET_FPA && !TARGET_68881)
3999 target = operand_subword (operands[0], 0, 1, DFmode);
4000 result = expand_binop (SImode, and_optab,
4001 operand_subword_force (operands[1], 0, DFmode),
4002 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4006 if (result != target)
4007 emit_move_insn (result, target);
4009 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4010 operand_subword_force (operands[1], 1, DFmode));
4012 insns = get_insns ();
4015 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4021 [(set (match_operand:DF 0 "general_operand" "=x,y")
4022 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4027 [(set (match_operand:DF 0 "general_operand" "=f")
4028 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4032 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4033 return \"f%&abs%.x %1,%0\";
4034 return \"f%&abs%.d %f1,%0\";
4037 ;; one complement instructions
4039 ;; "one_cmpldi2" is only here to help combine().
4040 (define_insn "one_cmpldi2"
4041 [(set (match_operand:DI 0 "general_operand" "=dm")
4042 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4047 if (GET_CODE (operands[0]) == REG)
4048 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4049 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4050 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4051 operands[1] = operands[0];
4053 operands[1] = adj_offsettable_operand (operands[0], 4);
4054 return \"not%.l %1\;not%.l %0\";
4057 (define_insn "one_cmplsi2"
4058 [(set (match_operand:SI 0 "general_operand" "=dm")
4059 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4063 (define_insn "one_cmplhi2"
4064 [(set (match_operand:HI 0 "general_operand" "=dm")
4065 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4070 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4071 (not:HI (match_dup 0)))]
4075 (define_insn "one_cmplqi2"
4076 [(set (match_operand:QI 0 "general_operand" "=dm")
4077 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4082 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4083 (not:QI (match_dup 0)))]
4087 ;; arithmetic shift instructions
4088 ;; We don't need the shift memory by 1 bit instruction
4090 (define_insn "ashldi_extsi"
4091 [(set (match_operand:DI 0 "general_operand" "=ro")
4093 (match_operator:DI 2 "extend_operator"
4094 [(match_operand:SI 1 "general_operand" "rm")])
4100 if (GET_CODE (operands[0]) == REG)
4101 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4103 operands[2] = adj_offsettable_operand (operands[0], 4);
4104 if (ADDRESS_REG_P (operands[0]))
4105 return \"move%.l %1,%0\;sub%.l %2,%2\";
4107 return \"move%.l %1,%0\;clr%.l %2\";
4110 (define_insn "ashldi_sexthi"
4111 [(set (match_operand:DI 0 "register_operand" "=*da")
4112 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm"))
4118 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4119 if (DATA_REG_P (operands[0]))
4120 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %2\";
4122 return \"move%.w %1,%0\;sub%.l %2,%2\";
4125 (define_insn "ashldi_const32"
4126 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4127 (ashift:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4133 if (GET_CODE (operands[1]) == REG)
4134 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4136 operands[3] = adj_offsettable_operand (operands[1], 4);
4137 if (which_alternative == 1)
4138 return \"clr%.l %0\;move%.l %3,%0\";
4139 if (which_alternative == 2)
4140 return \"move%.l %3,%0\;clr%.l %0\";
4141 if (GET_CODE (operands[0]) == REG)
4142 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4144 operands[2] = adj_offsettable_operand (operands[0], 4);
4145 if (ADDRESS_REG_P (operands[2]))
4146 return \"move%.l %3,%0\;sub%.l %2,%2\";
4148 return \"move%.l %3,%0\;clr%.l %2\";
4151 ;; The predicate below must be general_operand, because ashldi3 allows that
4152 (define_insn "ashldi_const"
4153 [(set (match_operand:DI 0 "general_operand" "=d")
4154 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4155 (match_operand 2 "const_int_operand" "n")))]
4156 "(INTVAL (operands[2]) == 1
4157 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4158 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4161 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4162 if (INTVAL (operands[2]) == 1)
4163 return \"add%.l %1,%1\;addx%.l %0,%0\";
4164 else if (INTVAL (operands[2]) == 8)
4165 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4166 else if (INTVAL (operands[2]) == 16)
4167 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4168 else if (INTVAL (operands[2]) == 2)
4169 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4170 else/* if (INTVAL (operands[2]) == 3)*/
4171 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4174 (define_expand "ashldi3"
4175 [(set (match_operand:DI 0 "general_operand" "")
4176 (ashift:DI (match_operand:DI 1 "general_operand" "")
4177 (match_operand 2 "const_int_operand" "")))]
4181 if (GET_CODE (operands[2]) != CONST_INT
4182 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4183 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4184 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4188 ;; On all 68k models, this makes faster code in a special case.
4191 [(set (match_operand:SI 0 "register_operand" "=d")
4192 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4198 return \"swap %0\;clr%.w %0\";
4201 ;; On the 68000, this makes faster code in a special case.
4204 [(set (match_operand:SI 0 "register_operand" "=d")
4205 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4206 (match_operand:SI 2 "const_int_operand" "n")))]
4208 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4213 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4214 return \"asl%.w %2,%0\;swap %0\;clr%.w %0\";
4217 (define_insn "ashlsi3"
4218 [(set (match_operand:SI 0 "register_operand" "=d")
4219 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4220 (match_operand:SI 2 "general_operand" "dI")))]
4224 if (operands[2] == const1_rtx)
4225 return \"add%.l %0,%0\";
4226 return \"asl%.l %2,%0\";
4229 (define_insn "ashlhi3"
4230 [(set (match_operand:HI 0 "register_operand" "=d")
4231 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4232 (match_operand:HI 2 "general_operand" "dI")))]
4237 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4238 (ashift:HI (match_dup 0)
4239 (match_operand:HI 1 "general_operand" "dI")))]
4243 (define_insn "ashlqi3"
4244 [(set (match_operand:QI 0 "register_operand" "=d")
4245 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4246 (match_operand:QI 2 "general_operand" "dI")))]
4251 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4252 (ashift:QI (match_dup 0)
4253 (match_operand:QI 1 "general_operand" "dI")))]
4257 ;; On all 68k models, this makes faster code in a special case.
4260 [(set (match_operand:SI 0 "register_operand" "=d")
4261 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4264 "swap %0\;ext%.l %0")
4266 ;; On the 68000, this makes faster code in a special case.
4269 [(set (match_operand:SI 0 "register_operand" "=d")
4270 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4271 (match_operand:SI 2 "const_int_operand" "n")))]
4273 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4276 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4277 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4280 (define_insn "subreghi1ashrdi_const32"
4281 [(set (match_operand:HI 0 "general_operand" "=rm")
4282 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4283 (const_int 32)) 1))]
4287 if (GET_CODE (operands[1]) != REG)
4288 operands[1] = adj_offsettable_operand (operands[1], 2);
4289 return \"move%.w %1,%0\";
4292 (define_insn "subregsi1ashrdi_const32"
4293 [(set (match_operand:SI 0 "general_operand" "=rm")
4294 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4295 (const_int 32)) 1))]
4299 return \"move%.l %1,%0\";
4302 (define_insn "ashrdi_const32"
4303 [(set (match_operand:DI 0 "register_operand" "=d")
4304 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4310 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4312 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4314 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4317 (define_insn "ashrdi_const32_mem"
4318 [(set (match_operand:DI 0 "general_operand" "=o,<")
4319 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4321 (clobber (match_scratch:SI 2 "=d,d"))]
4326 if (which_alternative == 1)
4327 operands[3] = operands[0];
4329 operands[3] = adj_offsettable_operand (operands[0], 4);
4331 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4333 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4336 ;; The predicate below must be general_operand, because ashrdi3 allows that
4337 (define_insn "ashrdi_const"
4338 [(set (match_operand:DI 0 "general_operand" "=d")
4339 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4340 (match_operand 2 "const_int_operand" "n")))]
4341 "(INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4342 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4343 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63)"
4346 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4347 if (INTVAL (operands[2]) == 63)
4348 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4350 if (INTVAL (operands[2]) == 1)
4351 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4352 else if (INTVAL (operands[2]) == 8)
4353 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4354 else if (INTVAL (operands[2]) == 16)
4355 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4356 else if (INTVAL (operands[2]) == 2)
4357 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4358 else/* if (INTVAL (operands[2]) == 3)*/
4359 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4362 (define_expand "ashrdi3"
4363 [(set (match_operand:DI 0 "general_operand" "")
4364 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4365 (match_operand 2 "const_int_operand" "")))]
4369 if (GET_CODE (operands[2]) != CONST_INT
4370 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4371 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4372 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4373 && INTVAL (operands[2]) != 63))
4377 ;; On all 68k models, this makes faster code in a special case.
4379 (define_insn "ashrsi_31"
4380 [(set (match_operand:SI 0 "register_operand" "=d")
4381 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4386 return \"add%.l %0,%0\;subx%.l %0,%0\";
4389 (define_insn "ashrsi3"
4390 [(set (match_operand:SI 0 "register_operand" "=d")
4391 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4392 (match_operand:SI 2 "general_operand" "dI")))]
4396 (define_insn "ashrhi3"
4397 [(set (match_operand:HI 0 "register_operand" "=d")
4398 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4399 (match_operand:HI 2 "general_operand" "dI")))]
4404 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4405 (ashiftrt:HI (match_dup 0)
4406 (match_operand:HI 1 "general_operand" "dI")))]
4410 (define_insn "ashrqi3"
4411 [(set (match_operand:QI 0 "register_operand" "=d")
4412 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4413 (match_operand:QI 2 "general_operand" "dI")))]
4418 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4419 (ashiftrt:QI (match_dup 0)
4420 (match_operand:QI 1 "general_operand" "dI")))]
4424 ;; logical shift instructions
4426 ;; commented out because of reload problems in 950612-1.c
4429 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4430 ;; (const_int 32)) 1))
4431 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4432 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4433 ;; (const_int 32)) 1))]
4437 ;; return \"move%.l %0,%1\";
4442 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4443 ;; (const_int 32)) 0))
4444 ;; (set (match_operand:DI 1 "general_operand" "=do")
4445 ;; (lshiftrt:DI (match_dup 0)
4446 ;; (const_int 32)))]
4450 ;; if (GET_CODE (operands[1]) == REG)
4451 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4453 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4454 ;; return \"move%.l %0,%2\;clr%.l %1\";
4457 (define_insn "subreg1lshrdi_const32"
4458 [(set (match_operand:SI 0 "general_operand" "=rm")
4459 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4460 (const_int 32)) 1))]
4464 return \"move%.l %1,%0\";
4467 (define_insn "lshrdi_const32"
4468 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4469 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4475 if (which_alternative == 1)
4476 return \"move%.l %1,%0\;clr%.l %0\";
4477 if (which_alternative == 2)
4478 return \"clr%.l %0\;move%.l %1,%0\";
4479 if (GET_CODE (operands[0]) == REG)
4480 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4482 operands[2] = adj_offsettable_operand (operands[0], 4);
4483 if (GET_CODE (operands[1]) == REG)
4484 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4486 operands[3] = adj_offsettable_operand (operands[1], 4);
4487 if (ADDRESS_REG_P (operands[0]))
4488 return \"move%.l %1,%2\;sub%.l %0,%0\";
4490 return \"move%.l %1,%2\;clr%.l %0\";
4493 ;; The predicate below must be general_operand, because lshrdi3 allows that
4494 (define_insn "lshrdi_const"
4495 [(set (match_operand:DI 0 "general_operand" "=d")
4496 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4497 (match_operand 2 "const_int_operand" "n")))]
4498 "(INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4499 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4500 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63)"
4503 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4504 if (INTVAL (operands[2]) == 63)
4505 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4507 if (INTVAL (operands[2]) == 1)
4508 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4509 else if (INTVAL (operands[2]) == 8)
4510 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4511 else if (INTVAL (operands[2]) == 16)
4512 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4513 else if (INTVAL (operands[2]) == 2)
4514 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4515 else /*if (INTVAL (operands[2]) == 3)*/
4516 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4519 (define_expand "lshrdi3"
4520 [(set (match_operand:DI 0 "general_operand" "")
4521 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4522 (match_operand 2 "const_int_operand" "")))]
4526 if (GET_CODE (operands[2]) != CONST_INT
4527 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4528 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4529 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4530 && INTVAL (operands[2]) != 63))
4534 ;; On all 68k models, this makes faster code in a special case.
4536 (define_insn "lshrsi_31"
4537 [(set (match_operand:SI 0 "register_operand" "=d")
4538 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4543 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4546 ;; On all 68k models, this makes faster code in a special case.
4548 (define_insn "lshrsi_16"
4549 [(set (match_operand:SI 0 "register_operand" "=d")
4550 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4556 return \"clr%.w %0\;swap %0\";
4559 ;; On the 68000, this makes faster code in a special case.
4561 (define_insn "lshrsi_17_24"
4562 [(set (match_operand:SI 0 "register_operand" "=d")
4563 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4564 (match_operand:SI 2 "const_int_operand" "n")))]
4566 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4569 /* I think lsr%.w sets the CC properly. */
4570 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4571 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4574 (define_insn "lshrsi3"
4575 [(set (match_operand:SI 0 "register_operand" "=d")
4576 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4577 (match_operand:SI 2 "general_operand" "dI")))]
4581 (define_insn "lshrhi3"
4582 [(set (match_operand:HI 0 "register_operand" "=d")
4583 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4584 (match_operand:HI 2 "general_operand" "dI")))]
4589 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4590 (lshiftrt:HI (match_dup 0)
4591 (match_operand:HI 1 "general_operand" "dI")))]
4595 (define_insn "lshrqi3"
4596 [(set (match_operand:QI 0 "register_operand" "=d")
4597 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4598 (match_operand:QI 2 "general_operand" "dI")))]
4603 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4604 (lshiftrt:QI (match_dup 0)
4605 (match_operand:QI 1 "general_operand" "dI")))]
4609 ;; rotate instructions
4611 (define_insn "rotlsi3"
4612 [(set (match_operand:SI 0 "register_operand" "=d")
4613 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4614 (match_operand:SI 2 "general_operand" "dI")))]
4618 (define_insn "rotlhi3"
4619 [(set (match_operand:HI 0 "register_operand" "=d")
4620 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4621 (match_operand:HI 2 "general_operand" "dI")))]
4627 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4628 (rotate:HI (match_dup 0)
4629 (match_operand:HI 1 "general_operand" "dI")))]
4633 (define_insn "rotlqi3"
4634 [(set (match_operand:QI 0 "register_operand" "=d")
4635 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4636 (match_operand:QI 2 "general_operand" "dI")))]
4641 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4642 (rotate:QI (match_dup 0)
4643 (match_operand:QI 1 "general_operand" "dI")))]
4647 (define_insn "rotrsi3"
4648 [(set (match_operand:SI 0 "register_operand" "=d")
4649 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4650 (match_operand:SI 2 "general_operand" "dI")))]
4654 (define_insn "rotrhi3"
4655 [(set (match_operand:HI 0 "register_operand" "=d")
4656 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4657 (match_operand:HI 2 "general_operand" "dI")))]
4662 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4663 (rotatert:HI (match_dup 0)
4664 (match_operand:HI 1 "general_operand" "dI")))]
4668 (define_insn "rotrqi3"
4669 [(set (match_operand:QI 0 "register_operand" "=d")
4670 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4671 (match_operand:QI 2 "general_operand" "dI")))]
4676 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4677 (rotatert:QI (match_dup 0)
4678 (match_operand:QI 1 "general_operand" "dI")))]
4683 ;; Bit set/clear in memory byte.
4685 ;; set bit, bit number is int
4686 (define_insn "bsetmemqi"
4687 [(set (match_operand:QI 0 "memory_operand" "+m")
4688 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4689 (match_operand:SI 1 "general_operand" "d")) 0)
4695 return \"bset %1,%0\";
4698 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4700 [(set (match_operand:QI 0 "memory_operand" "+m")
4701 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4702 (match_operator:SI 2 "extend_operator"
4703 [(match_operand 1 "general_operand" "d")])) 0)
4709 return \"bset %1,%0\";
4712 ;; clear bit, bit number is int
4713 (define_insn "bclrmemqi"
4714 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4716 (minus:SI (const_int 7)
4717 (match_operand:SI 1 "general_operand" "d")))
4723 return \"bclr %1,%0\";
4726 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4728 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4730 (minus:SI (const_int 7)
4731 (match_operator:SI 2 "extend_operator"
4732 [(match_operand 1 "general_operand" "d")])))
4738 return \"bclr %1,%0\";
4741 ;; Special cases of bit-field insns which we should
4742 ;; recognize in preference to the general case.
4743 ;; These handle aligned 8-bit and 16-bit fields,
4744 ;; which can usually be done with move instructions.
4747 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4748 ; alignment of structure members is specified.
4750 ; The move is allowed to be odd byte aligned, because that's still faster
4751 ; than an odd byte aligned bit field instruction.
4754 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4756 (match_operand:SI 2 "const_int_operand" "n"))
4757 (match_operand:SI 3 "general_operand" "rmi"))]
4758 "TARGET_68020 && TARGET_BITFIELD
4759 && (INTVAL (operands[2]) % 8) == 0
4760 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4764 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4766 return \"move%.l %3,%0\";
4770 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4771 (match_operand:SI 1 "const_int_operand" "n")
4772 (match_operand:SI 2 "const_int_operand" "n"))
4773 (match_operand:SI 3 "register_operand" "d"))]
4774 "TARGET_68020 && TARGET_BITFIELD
4775 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4776 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4777 && (GET_CODE (operands[0]) == REG
4778 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4781 if (REG_P (operands[0]))
4783 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4784 return \"bfins %3,%0{%b2:%b1}\";
4788 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4790 if (GET_CODE (operands[3]) == MEM)
4791 operands[3] = adj_offsettable_operand (operands[3],
4792 (32 - INTVAL (operands[1])) / 8);
4793 if (INTVAL (operands[1]) == 8)
4794 return \"move%.b %3,%0\";
4795 return \"move%.w %3,%0\";
4800 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4801 ; alignment of structure members is specified.
4803 ; The move is allowed to be odd byte aligned, because that's still faster
4804 ; than an odd byte aligned bit field instruction.
4807 [(set (match_operand:SI 0 "general_operand" "=rm")
4808 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
4810 (match_operand:SI 3 "const_int_operand" "n")))]
4811 "TARGET_68020 && TARGET_BITFIELD
4812 && (INTVAL (operands[3]) % 8) == 0
4813 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4817 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4819 return \"move%.l %1,%0\";
4823 [(set (match_operand:SI 0 "general_operand" "=&d")
4824 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4825 (match_operand:SI 2 "const_int_operand" "n")
4826 (match_operand:SI 3 "const_int_operand" "n")))]
4827 "TARGET_68020 && TARGET_BITFIELD
4828 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4829 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4830 && (GET_CODE (operands[1]) == REG
4831 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4834 cc_status.flags |= CC_NOT_NEGATIVE;
4835 if (REG_P (operands[1]))
4837 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4838 return \"bfextu %1{%b3:%b2},%0\";
4842 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4844 output_asm_insn (\"clr%.l %0\", operands);
4845 if (GET_CODE (operands[0]) == MEM)
4846 operands[0] = adj_offsettable_operand (operands[0],
4847 (32 - INTVAL (operands[1])) / 8);
4848 if (INTVAL (operands[2]) == 8)
4849 return \"move%.b %1,%0\";
4850 return \"move%.w %1,%0\";
4854 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4855 ; alignment of structure members is specified.
4857 ; The move is allowed to be odd byte aligned, because that's still faster
4858 ; than an odd byte aligned bit field instruction.
4861 [(set (match_operand:SI 0 "general_operand" "=rm")
4862 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4864 (match_operand:SI 3 "const_int_operand" "n")))]
4865 "TARGET_68020 && TARGET_BITFIELD
4866 && (INTVAL (operands[3]) % 8) == 0
4867 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4871 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4873 return \"move%.l %1,%0\";
4877 [(set (match_operand:SI 0 "general_operand" "=d")
4878 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4879 (match_operand:SI 2 "const_int_operand" "n")
4880 (match_operand:SI 3 "const_int_operand" "n")))]
4881 "TARGET_68020 && TARGET_BITFIELD
4882 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4883 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4884 && (GET_CODE (operands[1]) == REG
4885 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4888 if (REG_P (operands[1]))
4890 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4891 return \"bfexts %1{%b3:%b2},%0\";
4895 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4897 if (INTVAL (operands[2]) == 8)
4898 return \"move%.b %1,%0\;extb%.l %0\";
4899 return \"move%.w %1,%0\;ext%.l %0\";
4902 ;; Bit field instructions, general cases.
4903 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
4904 ;; so that its address is reloaded.
4906 (define_expand "extv"
4907 [(set (match_operand:SI 0 "general_operand" "")
4908 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
4909 (match_operand:SI 2 "general_operand" "")
4910 (match_operand:SI 3 "general_operand" "")))]
4911 "TARGET_68020 && TARGET_BITFIELD"
4915 [(set (match_operand:SI 0 "general_operand" "=d")
4916 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4917 (match_operand:SI 2 "general_operand" "di")
4918 (match_operand:SI 3 "general_operand" "di")))]
4919 "TARGET_68020 && TARGET_BITFIELD"
4920 "bfexts %1{%b3:%b2},%0")
4922 (define_expand "extzv"
4923 [(set (match_operand:SI 0 "general_operand" "")
4924 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
4925 (match_operand:SI 2 "general_operand" "")
4926 (match_operand:SI 3 "general_operand" "")))]
4927 "TARGET_68020 && TARGET_BITFIELD"
4931 [(set (match_operand:SI 0 "general_operand" "=d,d")
4932 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
4933 (match_operand:SI 2 "general_operand" "di,di")
4934 (match_operand:SI 3 "general_operand" "di,di")))]
4935 "TARGET_68020 && TARGET_BITFIELD"
4938 if (GET_CODE (operands[2]) == CONST_INT)
4940 if (INTVAL (operands[2]) != 32)
4941 cc_status.flags |= CC_NOT_NEGATIVE;
4947 return \"bfextu %1{%b3:%b2},%0\";
4951 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4952 (match_operand:SI 1 "general_operand" "di")
4953 (match_operand:SI 2 "general_operand" "di"))
4954 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
4955 (match_operand 3 "const_int_operand" "n")))]
4956 "TARGET_68020 && TARGET_BITFIELD
4957 && (INTVAL (operands[3]) == -1
4958 || (GET_CODE (operands[1]) == CONST_INT
4959 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
4963 return \"bfchg %0{%b2:%b1}\";
4967 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4968 (match_operand:SI 1 "general_operand" "di")
4969 (match_operand:SI 2 "general_operand" "di"))
4971 "TARGET_68020 && TARGET_BITFIELD"
4975 return \"bfclr %0{%b2:%b1}\";
4979 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4980 (match_operand:SI 1 "general_operand" "di")
4981 (match_operand:SI 2 "general_operand" "di"))
4983 "TARGET_68020 && TARGET_BITFIELD"
4987 return \"bfset %0{%b2:%b1}\";
4990 (define_expand "insv"
4991 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
4992 (match_operand:SI 1 "general_operand" "")
4993 (match_operand:SI 2 "general_operand" ""))
4994 (match_operand:SI 3 "register_operand" ""))]
4995 "TARGET_68020 && TARGET_BITFIELD"
4999 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5000 (match_operand:SI 1 "general_operand" "di")
5001 (match_operand:SI 2 "general_operand" "di"))
5002 (match_operand:SI 3 "register_operand" "d"))]
5003 "TARGET_68020 && TARGET_BITFIELD"
5004 "bfins %3,%0{%b2:%b1}")
5006 ;; Now recognize bit field insns that operate on registers
5007 ;; (or at least were intended to do so).
5010 [(set (match_operand:SI 0 "general_operand" "=d")
5011 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5012 (match_operand:SI 2 "general_operand" "di")
5013 (match_operand:SI 3 "general_operand" "di")))]
5014 "TARGET_68020 && TARGET_BITFIELD"
5015 "bfexts %1{%b3:%b2},%0")
5018 [(set (match_operand:SI 0 "general_operand" "=d")
5019 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5020 (match_operand:SI 2 "general_operand" "di")
5021 (match_operand:SI 3 "general_operand" "di")))]
5022 "TARGET_68020 && TARGET_BITFIELD"
5025 if (GET_CODE (operands[2]) == CONST_INT)
5027 if (INTVAL (operands[2]) != 32)
5028 cc_status.flags |= CC_NOT_NEGATIVE;
5034 return \"bfextu %1{%b3:%b2},%0\";
5038 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5039 (match_operand:SI 1 "general_operand" "di")
5040 (match_operand:SI 2 "general_operand" "di"))
5042 "TARGET_68020 && TARGET_BITFIELD"
5046 return \"bfclr %0{%b2:%b1}\";
5050 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5051 (match_operand:SI 1 "general_operand" "di")
5052 (match_operand:SI 2 "general_operand" "di"))
5054 "TARGET_68020 && TARGET_BITFIELD"
5058 return \"bfset %0{%b2:%b1}\";
5062 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5063 (match_operand:SI 1 "general_operand" "di")
5064 (match_operand:SI 2 "general_operand" "di"))
5065 (match_operand:SI 3 "register_operand" "d"))]
5066 "TARGET_68020 && TARGET_BITFIELD"
5070 /* These special cases are now recognized by a specific pattern. */
5071 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5072 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5073 return \"move%.w %3,%0\";
5074 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5075 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5076 return \"move%.b %3,%0\";
5078 return \"bfins %3,%0{%b2:%b1}\";
5081 ;; Special patterns for optimizing bit-field instructions.
5085 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5086 (match_operand:SI 1 "const_int_operand" "n")
5087 (match_operand:SI 2 "general_operand" "di")))]
5088 "TARGET_68020 && TARGET_BITFIELD"
5091 if (operands[1] == const1_rtx
5092 && GET_CODE (operands[2]) == CONST_INT)
5094 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5095 return output_btst (operands,
5096 gen_rtx (CONST_INT, VOIDmode,
5097 width - INTVAL (operands[2])),
5100 /* Pass 1000 as SIGNPOS argument so that btst will
5101 not think we are testing the sign bit for an `and'
5102 and assume that nonzero implies a negative result. */
5104 if (INTVAL (operands[1]) != 32)
5105 cc_status.flags = CC_NOT_NEGATIVE;
5106 return \"bftst %0{%b2:%b1}\";
5110 ;;; now handle the register cases
5113 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5114 (match_operand:SI 1 "const_int_operand" "n")
5115 (match_operand:SI 2 "general_operand" "di")))]
5116 "TARGET_68020 && TARGET_BITFIELD"
5119 if (operands[1] == const1_rtx
5120 && GET_CODE (operands[2]) == CONST_INT)
5122 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5123 return output_btst (operands,
5124 gen_rtx (CONST_INT, VOIDmode,
5125 width - INTVAL (operands[2])),
5128 /* Pass 1000 as SIGNPOS argument so that btst will
5129 not think we are testing the sign bit for an `and'
5130 and assume that nonzero implies a negative result. */
5132 if (INTVAL (operands[1]) != 32)
5133 cc_status.flags = CC_NOT_NEGATIVE;
5134 return \"bftst %0{%b2:%b1}\";
5137 (define_insn "scc0_di"
5138 [(set (match_operand:QI 0 "general_operand" "=dm")
5139 (match_operator 1 "valid_dbcc_comparison_p"
5140 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5144 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5147 (define_insn "scc_di"
5148 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5149 (match_operator 1 "valid_dbcc_comparison_p"
5150 [(match_operand:DI 2 "general_operand" "ro,r")
5151 (match_operand:DI 3 "general_operand" "r,ro")]))]
5155 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5159 [(set (match_operand:QI 0 "general_operand" "=d")
5160 (eq:QI (cc0) (const_int 0)))]
5163 cc_status = cc_prev_status;
5164 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5168 [(set (match_operand:QI 0 "general_operand" "=d")
5169 (ne:QI (cc0) (const_int 0)))]
5172 cc_status = cc_prev_status;
5173 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5177 [(set (match_operand:QI 0 "general_operand" "=d")
5178 (gt:QI (cc0) (const_int 0)))]
5181 cc_status = cc_prev_status;
5182 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5186 [(set (match_operand:QI 0 "general_operand" "=d")
5187 (gtu:QI (cc0) (const_int 0)))]
5189 "* cc_status = cc_prev_status;
5190 return \"shi %0\"; ")
5193 [(set (match_operand:QI 0 "general_operand" "=d")
5194 (lt:QI (cc0) (const_int 0)))]
5196 "* cc_status = cc_prev_status;
5197 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5200 [(set (match_operand:QI 0 "general_operand" "=d")
5201 (ltu:QI (cc0) (const_int 0)))]
5203 "* cc_status = cc_prev_status;
5204 return \"scs %0\"; ")
5207 [(set (match_operand:QI 0 "general_operand" "=d")
5208 (ge:QI (cc0) (const_int 0)))]
5210 "* cc_status = cc_prev_status;
5211 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5214 [(set (match_operand:QI 0 "general_operand" "=d")
5215 (geu:QI (cc0) (const_int 0)))]
5217 "* cc_status = cc_prev_status;
5218 return \"scc %0\"; ")
5221 [(set (match_operand:QI 0 "general_operand" "=d")
5222 (le:QI (cc0) (const_int 0)))]
5225 cc_status = cc_prev_status;
5226 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5230 [(set (match_operand:QI 0 "general_operand" "=d")
5231 (leu:QI (cc0) (const_int 0)))]
5233 "* cc_status = cc_prev_status;
5234 return \"sls %0\"; ")
5236 ;; Basic conditional jump instructions.
5238 (define_insn "beq0_di"
5240 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5242 (label_ref (match_operand 1 "" ","))
5244 (clobber (match_scratch:SI 2 "=d,d"))]
5248 if (which_alternative == 1)
5250 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5252 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5254 if (GET_CODE (operands[0]) == REG)
5255 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5257 operands[3] = adj_offsettable_operand (operands[0], 4);
5258 if (! ADDRESS_REG_P (operands[0]))
5260 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5262 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5264 operands[4] = gen_label_rtx();
5266 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5268 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5270 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5271 CODE_LABEL_NUMBER (operands[4]));
5275 (define_insn "bne0_di"
5277 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5279 (label_ref (match_operand 1 "" ","))
5281 (clobber (match_scratch:SI 2 "=d,"))]
5285 if (GET_CODE (operands[0]) == REG)
5286 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5288 operands[3] = adj_offsettable_operand (operands[0], 4);
5289 if (ADDRESS_REG_P (operands[0]))
5291 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5293 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5297 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5299 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5303 (define_insn "bge0_di"
5305 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5307 (label_ref (match_operand 1 "" ""))
5313 return \"tst%.l %0\;jbge %l1\";
5315 return \"tst%.l %0\;jge %l1\";
5319 (define_insn "blt0_di"
5321 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5323 (label_ref (match_operand 1 "" ""))
5329 return \"tst%.l %0\;jbmi %l1\";
5331 return \"tst%.l %0\;jmi %l1\";
5337 (if_then_else (eq (cc0)
5339 (label_ref (match_operand 0 "" ""))
5345 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5347 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5353 (if_then_else (ne (cc0)
5355 (label_ref (match_operand 0 "" ""))
5361 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5363 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5369 (if_then_else (gt (cc0)
5371 (label_ref (match_operand 0 "" ""))
5376 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5378 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5384 (if_then_else (gtu (cc0)
5386 (label_ref (match_operand 0 "" ""))
5391 return \"jbhi %l0\";
5399 (if_then_else (lt (cc0)
5401 (label_ref (match_operand 0 "" ""))
5406 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5408 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5414 (if_then_else (ltu (cc0)
5416 (label_ref (match_operand 0 "" ""))
5421 return \"jbcs %l0\";
5429 (if_then_else (ge (cc0)
5431 (label_ref (match_operand 0 "" ""))
5436 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
5438 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
5444 (if_then_else (geu (cc0)
5446 (label_ref (match_operand 0 "" ""))
5451 return \"jbcc %l0\";
5459 (if_then_else (le (cc0)
5461 (label_ref (match_operand 0 "" ""))
5466 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5468 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5474 (if_then_else (leu (cc0)
5476 (label_ref (match_operand 0 "" ""))
5481 return \"jbls %l0\";
5487 ;; Negated conditional jump instructions.
5491 (if_then_else (eq (cc0)
5494 (label_ref (match_operand 0 "" ""))))]
5499 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5501 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5507 (if_then_else (ne (cc0)
5510 (label_ref (match_operand 0 "" ""))))]
5515 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5517 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5523 (if_then_else (gt (cc0)
5526 (label_ref (match_operand 0 "" ""))))]
5530 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
5532 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
5538 (if_then_else (gtu (cc0)
5541 (label_ref (match_operand 0 "" ""))))]
5545 return \"jbls %l0\";
5553 (if_then_else (lt (cc0)
5556 (label_ref (match_operand 0 "" ""))))]
5560 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
5562 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
5568 (if_then_else (ltu (cc0)
5571 (label_ref (match_operand 0 "" ""))))]
5575 return \"jbcc %l0\";
5583 (if_then_else (ge (cc0)
5586 (label_ref (match_operand 0 "" ""))))]
5590 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
5592 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
5598 (if_then_else (geu (cc0)
5601 (label_ref (match_operand 0 "" ""))))]
5605 return \"jbcs %l0\";
5613 (if_then_else (le (cc0)
5616 (label_ref (match_operand 0 "" ""))))]
5620 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
5622 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
5628 (if_then_else (leu (cc0)
5631 (label_ref (match_operand 0 "" ""))))]
5635 return \"jbhi %l0\";
5641 ;; Unconditional and other jump instructions
5644 (label_ref (match_operand 0 "" "")))]
5648 return \"jbra %l0\";
5654 ;; We support two different ways of handling dispatch tables.
5655 ;; The NeXT uses absolute tables, and other machines use relative.
5656 ;; This define_expand can generate either kind.
5657 (define_expand "tablejump"
5658 [(parallel [(set (pc) (match_operand 0 "" ""))
5659 (use (label_ref (match_operand 1 "" "")))])]
5663 #ifdef CASE_VECTOR_PC_RELATIVE
5664 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
5665 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
5669 ;; Jump to variable address from dispatch table of absolute addresses.
5671 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
5672 (use (label_ref (match_operand 1 "" "")))]
5676 return \"jmp (%0)\";
5682 ;; Jump to variable address from dispatch table of relative addresses.
5686 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
5687 (use (label_ref (match_operand 1 "" "")))]
5690 #ifdef ASM_RETURN_CASE_JUMP
5691 ASM_RETURN_CASE_JUMP;
5694 #ifdef ASM_OUTPUT_CASE_LABEL
5695 return \"jmp 6(%%pc,%0.w)\";
5698 return \"jmp 2(pc,%0.w)\";
5700 return \"jmp 2(%%pc,%0.w)\";
5701 #endif /* end !CRDS */
5705 return \"jmp (2,pc,%0.w)\";
5707 return \"jmp pc@(2,%0:w)\";
5713 ;; Decrement-and-branch insns.
5717 (ne (match_operand:HI 0 "general_operand" "+d*g")
5719 (label_ref (match_operand 1 "" ""))
5722 (plus:HI (match_dup 0)
5728 if (DATA_REG_P (operands[0]))
5729 return \"dbra %0,%l1\";
5730 if (GET_CODE (operands[0]) == MEM)
5734 return \"sub%.w %#1,%0\;jbcc %l1\";
5736 return \"subq%.w %#1,%0\;jbcc %l1\";
5738 #else /* not MOTOROLA */
5739 return \"subqw %#1,%0\;jcc %l1\";
5743 #ifdef SGS_CMP_ORDER
5745 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5747 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5749 #else /* not SGS_CMP_ORDER */
5750 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
5752 #else /* not MOTOROLA */
5753 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
5760 (ne (match_operand:SI 0 "general_operand" "+d*g")
5762 (label_ref (match_operand 1 "" ""))
5765 (plus:SI (match_dup 0)
5773 if (DATA_REG_P (operands[0]))
5774 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
5775 if (GET_CODE (operands[0]) == MEM)
5776 return \"sub%.l %#1,%0\;jbcc %l1\";
5778 if (DATA_REG_P (operands[0]))
5779 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
5780 if (GET_CODE (operands[0]) == MEM)
5781 return \"subq%.l %#1,%0\;jbcc %l1\";
5782 #endif /* NO_ADDSUB_Q */
5783 #ifdef SGS_CMP_ORDER
5785 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5787 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5789 #else /* not SGS_CMP_ORDER */
5790 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
5791 #endif /* not SGS_CMP_ORDER */
5792 #else /* not MOTOROLA */
5793 if (DATA_REG_P (operands[0]))
5794 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
5795 if (GET_CODE (operands[0]) == MEM)
5796 return \"subql %#1,%0\;jcc %l1\";
5797 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
5798 #endif /* not MOTOROLA */
5801 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
5806 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
5809 (label_ref (match_operand 1 "" ""))
5812 (plus:HI (match_dup 0)
5814 "find_reg_note (insn, REG_NONNEG, 0)"
5820 if (DATA_REG_P (operands[0]))
5821 return \"dbra %0,%l1\";
5822 if (GET_CODE (operands[0]) == MEM)
5823 return \"sub%.w %#1,%0\;jbcc %l1\";
5825 if (DATA_REG_P (operands[0]))
5826 return \"dbra %0,%l1\";
5827 if (GET_CODE (operands[0]) == MEM)
5828 return \"subq%.w %#1,%0\;jbcc %l1\";
5830 #ifdef SGS_CMP_ORDER
5832 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
5834 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
5836 #else /* not SGS_CMP_ORDER */
5837 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
5838 #endif /* not SGS_CMP_ORDER */
5839 #else /* not MOTOROLA */
5840 if (DATA_REG_P (operands[0]))
5841 return \"dbra %0,%l1\";
5842 if (GET_CODE (operands[0]) == MEM)
5843 return \"subqw %#1,%0\;jcc %l1\";
5844 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
5845 #endif /* not MOTOROLA */
5848 (define_expand "decrement_and_branch_until_zero"
5849 [(parallel [(set (pc)
5851 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
5854 (label_ref (match_operand 1 "" ""))
5857 (plus:SI (match_dup 0)
5865 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5868 (label_ref (match_operand 1 "" ""))
5871 (plus:SI (match_dup 0)
5873 "find_reg_note (insn, REG_NONNEG, 0)"
5879 if (DATA_REG_P (operands[0]))
5880 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
5881 if (GET_CODE (operands[0]) == MEM)
5882 return \"sub%.l %#1,%0\;jbcc %l1\";
5884 if (DATA_REG_P (operands[0]))
5885 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
5886 if (GET_CODE (operands[0]) == MEM)
5887 return \"subq%.l %#1,%0\;jbcc %l1\";
5889 #ifdef SGS_CMP_ORDER
5891 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5893 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5895 #else /* not SGS_CMP_ORDER */
5896 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
5897 #endif /* not SGS_CMP_ORDER */
5898 #else /* not MOTOROLA */
5899 if (DATA_REG_P (operands[0]))
5900 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
5901 if (GET_CODE (operands[0]) == MEM)
5902 return \"subql %#1,%0\;jcc %l1\";
5903 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
5904 #endif /* not MOTOROLA */
5908 ;; For PIC calls, in order to be able to support
5909 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
5910 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
5912 ;; PIC calls are handled by loading the address of the function into a
5913 ;; register (via movsi), then emitting a register indirect call using
5914 ;; the "jsr" function call syntax.
5916 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
5917 ;; operand to the jbsr statement to indicate that this call should
5918 ;; go through the PLT (why? because this is the way that Sun does it).
5920 ;; We have different patterns for PIC calls and non-PIC calls. The
5921 ;; different patterns are only used to choose the right syntax.
5923 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
5924 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
5925 ;; that tells the linker editor to create an entry for `FUNC' in PLT
5926 ;; section at link time. However, all global objects reference are still
5927 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
5928 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
5929 ;; We need to have a way to differentiate these two different operands.
5931 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
5932 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
5933 ;; to be changed to recognize function calls symbol_ref operand as a valid
5934 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
5935 ;; avoid the compiler to load this symbol_ref operand into a register.
5936 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
5937 ;; since the value is a PC relative offset, not a real address.
5939 ;; All global objects are treated in the similar way as in SUN3. The only
5940 ;; difference is: on m68k svr4, the reference of such global object needs
5941 ;; to end with a suffix "@GOT" so the assembler and linker know to create
5942 ;; an entry for it in GOT (Global Offset Table) section. This is done in
5945 ;; Call subroutine with no return value.
5946 (define_expand "call"
5947 [(call (match_operand:QI 0 "memory_operand" "")
5948 (match_operand:SI 1 "general_operand" ""))]
5949 ;; Operand 1 not really used on the m68000.
5954 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5955 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
5958 ;; This is a normal call sequence.
5960 [(call (match_operand:QI 0 "memory_operand" "o")
5961 (match_operand:SI 1 "general_operand" "g"))]
5962 ;; Operand 1 not really used on the m68000.
5966 #if defined (MOTOROLA) && !defined (USE_GAS)
5968 if (GET_CODE (operands[0]) == MEM
5969 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5978 ;; This is a PIC call sequence.
5980 [(call (match_operand:QI 0 "memory_operand" "o")
5981 (match_operand:SI 1 "general_operand" "g"))]
5982 ;; Operand 1 not really used on the m68000.
5986 if (GET_CODE (operands[0]) == MEM
5987 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5990 return \"bsr.l %0\";
5993 return \"bsr.l %0@PLTPC\";
5995 return \"bsr %0@PLTPC\";
5999 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6000 GAS just plain ignores it. */
6001 return \"jbsr %0,a1\";
6006 ;; Call subroutine, returning value in operand 0
6007 ;; (which must be a hard register).
6008 ;; See comments before "call" regarding PIC calls.
6009 (define_expand "call_value"
6010 [(set (match_operand 0 "" "")
6011 (call (match_operand:QI 1 "memory_operand" "")
6012 (match_operand:SI 2 "general_operand" "")))]
6013 ;; Operand 2 not really used on the m68000.
6017 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6018 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6021 ;; This is a normal call_value
6023 [(set (match_operand 0 "" "=rf")
6024 (call (match_operand:QI 1 "memory_operand" "o")
6025 (match_operand:SI 2 "general_operand" "g")))]
6026 ;; Operand 2 not really used on the m68000.
6029 #if defined (MOTOROLA) && !defined (USE_GAS)
6031 if (GET_CODE (operands[1]) == MEM
6032 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6041 ;; This is a PIC call_value
6043 [(set (match_operand 0 "" "=rf")
6044 (call (match_operand:QI 1 "memory_operand" "o")
6045 (match_operand:SI 2 "general_operand" "g")))]
6046 ;; Operand 2 not really used on the m68000.
6049 if (GET_CODE (operands[1]) == MEM
6050 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6053 return \"bsr.l %1\";
6056 return \"bsr.l %1@PLTPC\";
6058 return \"bsr %1@PLTPC\";
6062 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6063 GAS just plain ignores it. */
6064 return \"jbsr %1,a1\";
6069 ;; Call subroutine returning any type.
6071 (define_expand "untyped_call"
6072 [(parallel [(call (match_operand 0 "" "")
6074 (match_operand 1 "" "")
6075 (match_operand 2 "" "")])]
6076 "NEEDS_UNTYPED_CALL"
6081 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6083 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6085 rtx set = XVECEXP (operands[2], 0, i);
6086 emit_move_insn (SET_DEST (set), SET_SRC (set));
6089 /* The optimizer does not know that the call sets the function value
6090 registers we stored in the result block. We avoid problems by
6091 claiming that all hard registers are used and clobbered at this
6093 emit_insn (gen_blockage ());
6098 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6099 ;; all of memory. This blocks insns from being moved across this point.
6101 (define_insn "blockage"
6102 [(unspec_volatile [(const_int 0)] 0)]
6111 (define_insn "probe"
6116 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6117 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6118 return \"tstl %a0\";
6121 ;; Used for frameless functions which save no regs and allocate no locals.
6122 (define_insn "return"
6127 if (current_function_pops_args == 0)
6129 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6133 (define_insn "indirect_jump"
6134 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6138 ;; This should not be used unless the add/sub insns can't be.
6141 [(set (match_operand:SI 0 "general_operand" "=a")
6142 (match_operand:QI 1 "address_operand" "p"))]
6147 /* Recognize an insn that refers to a table of offsets. Such an insn will
6148 need to refer to a label on the insn. So output one. Use the
6149 label-number of the table of offsets to generate this label. This code,
6150 and similar code above, assumes that there will be at most one reference
6152 if (GET_CODE (operands[1]) == PLUS
6153 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6154 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6156 rtx labelref = XEXP (operands[1], 1);
6157 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6159 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6160 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6162 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6163 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6164 #endif /* not SGS */
6165 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6166 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6167 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6168 #ifdef SGS_SWITCH_TABLES
6169 /* Set flag saying we need to define the symbol
6170 LD%n (with value L%n-LI%n) at the end of the switch table. */
6171 switch_table_difference_label_flag = 1;
6172 #endif /* SGS_SWITCH_TABLES */
6173 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6175 #endif /* SGS_NO_LI */
6177 return \"lea %a1,%0\";
6180 ;; This is the first machine-dependent peephole optimization.
6181 ;; It is useful when a floating value is returned from a function call
6182 ;; and then is moved into an FP register.
6183 ;; But it is mainly intended to test the support for these optimizations.
6186 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6187 (set (match_operand:DF 0 "register_operand" "=f")
6188 (match_operand:DF 1 "register_operand" "ad"))]
6189 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6193 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6194 output_asm_insn (\"move%.l %1,%@\", xoperands);
6195 output_asm_insn (\"move%.l %1,%-\", operands);
6196 return \"fmove%.d %+,%0\";
6200 ;; Optimize a stack-adjust followed by a push of an argument.
6201 ;; This is said to happen frequently with -msoft-float
6202 ;; when there are consecutive library calls.
6205 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6206 (match_operand:SI 0 "const_int_operand" "n")))
6207 (set (match_operand:SF 1 "push_operand" "=m")
6208 (match_operand:SF 2 "general_operand" "rmfF"))]
6209 "INTVAL (operands[0]) >= 4
6210 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6213 if (INTVAL (operands[0]) > 4)
6216 xoperands[0] = stack_pointer_rtx;
6217 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6219 if (INTVAL (xoperands[1]) <= 8)
6220 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6221 else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020)
6223 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6224 INTVAL (xoperands[1]) - 8);
6225 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6229 if (INTVAL (xoperands[1]) <= 0x7FFF)
6230 output_asm_insn (\"add%.w %1,%0\", xoperands);
6232 output_asm_insn (\"add%.l %1,%0\", xoperands);
6234 if (FP_REG_P (operands[2]))
6235 return \"fmove%.s %2,%@\";
6236 return \"move%.l %2,%@\";
6239 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6242 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6243 (match_operand:SI 0 "const_int_operand" "n")))
6244 (set (match_operand:SI 1 "push_operand" "=m")
6245 (match_operand:SI 2 "general_operand" "g"))]
6246 "INTVAL (operands[0]) >= 4
6247 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6250 if (INTVAL (operands[0]) > 4)
6253 xoperands[0] = stack_pointer_rtx;
6254 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6256 if (INTVAL (xoperands[1]) <= 8)
6257 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6258 else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020)
6260 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6261 INTVAL (xoperands[1]) - 8);
6262 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6266 if (INTVAL (xoperands[1]) <= 0x7FFF)
6267 output_asm_insn (\"add%.w %1,%0\", xoperands);
6269 output_asm_insn (\"add%.l %1,%0\", xoperands);
6271 if (operands[2] == const0_rtx)
6272 return \"clr%.l %@\";
6273 return \"move%.l %2,%@\";
6276 ;; Speed up pushing a single byte but leaving four bytes of space.
6279 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6280 (match_operand:QI 1 "general_operand" "dami"))
6281 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6282 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6287 if (GET_CODE (operands[1]) == REG)
6288 return \"move%.l %1,%-\";
6290 xoperands[1] = operands[1];
6292 = gen_rtx (MEM, QImode,
6293 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
6294 gen_rtx (CONST_INT, VOIDmode, 3)));
6295 xoperands[3] = stack_pointer_rtx;
6296 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6301 [(set (match_operand:SI 0 "register_operand" "=d")
6303 (set (strict_low_part (subreg:HI (match_dup 0) 0))
6304 (match_operand:HI 1 "general_operand" "rmn"))]
6305 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6308 if (GET_CODE (operands[1]) == CONST_INT)
6310 if (operands[1] == const0_rtx
6311 && (DATA_REG_P (operands[0])
6312 || GET_CODE (operands[0]) == MEM)
6313 /* clr insns on 68000 read before writing.
6314 This isn't so on the 68010, but we have no alternative for it. */
6316 || !(GET_CODE (operands[0]) == MEM
6317 && MEM_VOLATILE_P (operands[0]))))
6318 return \"clr%.w %0\";
6320 return \"move%.w %1,%0\";
6328 ;; jCC label ; abnormal loop termination
6329 ;; dbra dN, loop ; normal loop termination
6337 ;; Which moves the jCC condition outside the inner loop for free.
6340 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6341 [(cc0) (const_int 0)])
6342 (label_ref (match_operand 2 "" ""))
6347 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
6350 (label_ref (match_operand 1 "" ""))
6353 (plus:HI (match_dup 0)
6355 "DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6359 output_dbcc_and_branch (operands);
6364 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6365 [(cc0) (const_int 0)])
6366 (label_ref (match_operand 2 "" ""))
6371 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
6374 (label_ref (match_operand 1 "" ""))
6377 (plus:SI (match_dup 0)
6379 "DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6383 output_dbcc_and_branch (operands);
6388 ;; FPA multiply and add.
6390 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6391 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
6392 (match_operand:DF 2 "general_operand" "xH,y,y"))
6393 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
6396 fpma%.d %1,%w2,%w3,%0
6397 fpma%.d %x1,%x2,%x3,%0
6398 fpma%.d %x1,%x2,%x3,%0")
6401 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6402 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
6403 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
6404 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
6407 fpma%.s %1,%w2,%w3,%0
6409 fpma%.s %1,%2,%3,%0")
6411 ;; FPA Multiply and subtract
6413 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6414 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6415 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
6416 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6419 fpms%.d %3,%w2,%w1,%0
6420 fpms%.d %x3,%2,%x1,%0
6421 fpms%.d %x3,%2,%x1,%0")
6424 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6425 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6426 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
6427 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6430 fpms%.s %3,%w2,%w1,%0
6432 fpms%.s %3,%2,%1,%0")
6435 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6436 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6437 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6438 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6441 fpmr%.d %2,%w1,%w3,%0
6442 fpmr%.d %x2,%1,%x3,%0
6443 fpmr%.d %x2,%1,%x3,%0")
6446 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6447 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6448 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6449 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6452 fpmr%.s %2,%w1,%w3,%0
6453 fpmr%.s %x2,%1,%x3,%0
6454 fpmr%.s %x2,%1,%x3,%0")
6456 ;; FPA Add and multiply
6458 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6459 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6460 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6461 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6464 fpam%.d %2,%w1,%w3,%0
6465 fpam%.d %x2,%1,%x3,%0
6466 fpam%.d %x2,%1,%x3,%0")
6469 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6470 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6471 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6472 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6475 fpam%.s %2,%w1,%w3,%0
6476 fpam%.s %x2,%1,%x3,%0
6477 fpam%.s %x2,%1,%x3,%0")
6479 ;;FPA Subtract and multiply
6481 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6482 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
6483 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6484 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6487 fpsm%.d %2,%w1,%w3,%0
6488 fpsm%.d %x2,%1,%x3,%0
6489 fpsm%.d %x2,%1,%x3,%0")
6492 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6493 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6494 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
6495 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6498 fpsm%.d %3,%w2,%w1,%0
6499 fpsm%.d %x3,%2,%x1,%0
6500 fpsm%.d %x3,%2,%x1,%0")
6503 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6504 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
6505 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6506 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6509 fpsm%.s %2,%w1,%w3,%0
6510 fpsm%.s %x2,%1,%x3,%0
6511 fpsm%.s %x2,%1,%x3,%0")
6514 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6515 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6516 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
6517 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6520 fpsm%.s %3,%w2,%w1,%0
6521 fpsm%.s %x3,%2,%x1,%0
6522 fpsm%.s %x3,%2,%x1,%0")
6524 (define_insn "tstxf"
6526 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6530 cc_status.flags = CC_IN_68881;
6531 return \"ftst%.x %0\";
6534 (define_insn "cmpxf"
6536 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
6537 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
6541 cc_status.flags = CC_IN_68881;
6542 #ifdef SGS_CMP_ORDER
6543 if (REG_P (operands[0]))
6545 if (REG_P (operands[1]))
6546 return \"fcmp%.x %0,%1\";
6548 return \"fcmp%.x %0,%f1\";
6550 cc_status.flags |= CC_REVERSED;
6551 return \"fcmp%.x %1,%f0\";
6553 if (REG_P (operands[0]))
6555 if (REG_P (operands[1]))
6556 return \"fcmp%.x %1,%0\";
6558 return \"fcmp%.x %f1,%0\";
6560 cc_status.flags |= CC_REVERSED;
6561 return \"fcmp%.x %f0,%1\";
6565 (define_insn "extendsfxf2"
6566 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6567 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
6571 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6573 if (REGNO (operands[0]) == REGNO (operands[1]))
6575 /* Extending float to double in an fp-reg is a no-op.
6576 NOTICE_UPDATE_CC has already assumed that the
6577 cc will be set. So cancel what it did. */
6578 cc_status = cc_prev_status;
6581 return \"f%$move%.x %1,%0\";
6583 if (FP_REG_P (operands[0]))
6584 return \"f%$move%.s %f1,%0\";
6585 return \"fmove%.x %f1,%0\";
6589 (define_insn "extenddfxf2"
6590 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6592 (match_operand:DF 1 "general_operand" "f,m")))]
6596 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6598 if (REGNO (operands[0]) == REGNO (operands[1]))
6600 /* Extending float to double in an fp-reg is a no-op.
6601 NOTICE_UPDATE_CC has already assumed that the
6602 cc will be set. So cancel what it did. */
6603 cc_status = cc_prev_status;
6606 return \"fmove%.x %1,%0\";
6608 if (FP_REG_P (operands[0]))
6609 return \"f%&move%.d %f1,%0\";
6610 return \"fmove%.x %f1,%0\";
6613 (define_insn "truncxfdf2"
6614 [(set (match_operand:DF 0 "general_operand" "=m,!r")
6616 (match_operand:XF 1 "general_operand" "f,f")))]
6620 if (REG_P (operands[0]))
6622 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
6623 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
6624 return \"move%.l %+,%0\";
6626 return \"fmove%.d %f1,%0\";
6629 (define_insn "truncxfsf2"
6630 [(set (match_operand:SF 0 "general_operand" "=dm")
6632 (match_operand:XF 1 "general_operand" "f")))]
6636 (define_insn "floatsixf2"
6637 [(set (match_operand:XF 0 "general_operand" "=f")
6638 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
6642 (define_insn "floathixf2"
6643 [(set (match_operand:XF 0 "general_operand" "=f")
6644 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
6648 (define_insn "floatqixf2"
6649 [(set (match_operand:XF 0 "general_operand" "=f")
6650 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
6654 (define_insn "ftruncxf2"
6655 [(set (match_operand:XF 0 "general_operand" "=f")
6656 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
6660 if (FP_REG_P (operands[1]))
6661 return \"fintrz%.x %f1,%0\";
6662 return \"fintrz%.x %f1,%0\";
6665 (define_insn "fixxfqi2"
6666 [(set (match_operand:QI 0 "general_operand" "=dm")
6667 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
6671 (define_insn "fixxfhi2"
6672 [(set (match_operand:HI 0 "general_operand" "=dm")
6673 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
6677 (define_insn "fixxfsi2"
6678 [(set (match_operand:SI 0 "general_operand" "=dm")
6679 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
6684 [(set (match_operand:XF 0 "general_operand" "=f")
6685 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
6686 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6691 [(set (match_operand:XF 0 "general_operand" "=f")
6692 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
6693 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6698 [(set (match_operand:XF 0 "general_operand" "=f")
6699 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
6700 (match_operand:XF 1 "general_operand" "0")))]
6704 (define_insn "addxf3"
6705 [(set (match_operand:XF 0 "general_operand" "=f")
6706 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6707 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6711 if (REG_P (operands[2]))
6712 return \"fadd%.x %2,%0\";
6713 return \"fadd%.x %f2,%0\";
6717 [(set (match_operand:XF 0 "general_operand" "=f")
6718 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6719 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
6724 [(set (match_operand:XF 0 "general_operand" "=f")
6725 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6726 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
6731 [(set (match_operand:XF 0 "general_operand" "=f")
6732 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6733 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
6737 (define_insn "subxf3"
6738 [(set (match_operand:XF 0 "general_operand" "=f")
6739 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6740 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6744 if (REG_P (operands[2]))
6745 return \"fsub%.x %2,%0\";
6746 return \"fsub%.x %f2,%0\";
6750 [(set (match_operand:XF 0 "general_operand" "=f")
6751 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
6752 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6757 [(set (match_operand:XF 0 "general_operand" "=f")
6758 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
6759 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6764 [(set (match_operand:XF 0 "general_operand" "=f")
6765 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
6766 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6770 (define_insn "mulxf3"
6771 [(set (match_operand:XF 0 "general_operand" "=f")
6772 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6773 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6777 if (REG_P (operands[2]))
6778 return \"fmul%.x %2,%0\";
6779 return \"fmul%.x %f2,%0\";
6783 [(set (match_operand:XF 0 "general_operand" "=f")
6784 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6785 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
6790 [(set (match_operand:XF 0 "general_operand" "=f")
6791 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6792 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
6797 [(set (match_operand:XF 0 "general_operand" "=f")
6798 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6799 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
6803 (define_insn "divxf3"
6804 [(set (match_operand:XF 0 "general_operand" "=f")
6805 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6806 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6810 if (REG_P (operands[2]))
6811 return \"fdiv%.x %2,%0\";
6812 return \"fdiv%.x %f2,%0\";
6815 (define_expand "negxf2"
6816 [(set (match_operand:XF 0 "general_operand" "")
6817 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
6821 /* ??? There isn't an FPA define_insn so we could handle it here too.
6822 For now we don't (paranoia). */
6830 target = operand_subword (operands[0], 0, 1, XFmode);
6831 result = expand_binop (SImode, xor_optab,
6832 operand_subword_force (operands[1], 0, XFmode),
6833 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
6837 if (result != target)
6838 emit_move_insn (result, target);
6840 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
6841 operand_subword_force (operands[1], 1, XFmode));
6842 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
6843 operand_subword_force (operands[1], 2, XFmode));
6845 insns = get_insns ();
6848 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
6853 (define_insn "negxf2_68881"
6854 [(set (match_operand:XF 0 "general_operand" "=f")
6855 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
6859 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
6860 return \"fneg%.x %1,%0\";
6861 return \"fneg%.x %f1,%0\";
6864 (define_expand "absxf2"
6865 [(set (match_operand:XF 0 "general_operand" "")
6866 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
6870 /* ??? There isn't an FPA define_insn so we could handle it here too.
6871 For now we don't (paranoia). */
6879 target = operand_subword (operands[0], 0, 1, XFmode);
6880 result = expand_binop (SImode, and_optab,
6881 operand_subword_force (operands[1], 0, XFmode),
6882 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
6886 if (result != target)
6887 emit_move_insn (result, target);
6889 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
6890 operand_subword_force (operands[1], 1, XFmode));
6891 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
6892 operand_subword_force (operands[1], 2, XFmode));
6894 insns = get_insns ();
6897 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
6902 (define_insn "absxf2_68881"
6903 [(set (match_operand:XF 0 "general_operand" "=f")
6904 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
6908 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
6909 return \"fabs%.x %1,%0\";
6910 return \"fabs%.x %f1,%0\";
6913 (define_insn "sqrtxf2"
6914 [(set (match_operand:XF 0 "general_operand" "=f")
6915 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
6919 (define_insn "sinsf2"
6920 [(set (match_operand:SF 0 "general_operand" "=f")
6921 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
6922 "TARGET_68881 && flag_fast_math"
6925 if (FP_REG_P (operands[1]))
6926 return \"fsin%.x %1,%0\";
6928 return \"fsin%.s %1,%0\";
6931 (define_insn "sindf2"
6932 [(set (match_operand:DF 0 "general_operand" "=f")
6933 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
6934 "TARGET_68881 && flag_fast_math"
6937 if (FP_REG_P (operands[1]))
6938 return \"fsin%.x %1,%0\";
6940 return \"fsin%.d %1,%0\";
6943 (define_insn "sinxf2"
6944 [(set (match_operand:XF 0 "general_operand" "=f")
6945 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
6946 "TARGET_68881 && flag_fast_math"
6949 (define_insn "cossf2"
6950 [(set (match_operand:SF 0 "general_operand" "=f")
6951 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
6952 "TARGET_68881 && flag_fast_math"
6955 if (FP_REG_P (operands[1]))
6956 return \"fcos%.x %1,%0\";
6958 return \"fcos%.s %1,%0\";
6961 (define_insn "cosdf2"
6962 [(set (match_operand:DF 0 "general_operand" "=f")
6963 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
6964 "TARGET_68881 && flag_fast_math"
6967 if (FP_REG_P (operands[1]))
6968 return \"fcos%.x %1,%0\";
6970 return \"fcos%.d %1,%0\";
6973 (define_insn "cosxf2"
6974 [(set (match_operand:XF 0 "general_operand" "=f")
6975 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
6976 "TARGET_68881 && flag_fast_math"