1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_5200 flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
51 ;;- Immediate Floating point operator constraints
52 ;;- 'G' a floating point constant that is *NOT* one of the standard
53 ;; 68881 constant values (to force calling output_move_const_double
54 ;; to get it from rom if it is a 68881 constant).
56 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
59 ;;- Immediate integer operand constraints:
61 ;;- 'J' -32768 .. 32767
62 ;;- 'K' all integers EXCEPT -128 .. 127
64 ;;- 'M' all integers EXCEPT -256 .. 255
70 ;;- "%." size separator ("." or "") move%.l d0,d1
71 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
72 ;;- "%-" push operand "sp@-" move%.l d0,%-
73 ;;- "%+" pop operand "sp@+" move%.l d0,%+
74 ;;- "%@" top of stack "sp@" move%.l d0,%@
75 ;;- "%!" fpcr register
76 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
77 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;;- Information about 68040 port.
81 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
82 ;;- be emulated in software by the OS. It is faster to avoid these
83 ;;- instructions and issue a library call rather than trapping into
84 ;;- the kernel. The affected instructions are fintrz and fscale. The
85 ;;- TARGET_68040 flag turns the use of the opcodes off.
87 ;;- The '040 also implements a set of new floating-point instructions
88 ;;- which specify the rounding precision in the opcode. This finally
89 ;;- permit the 68k series to be truly IEEE compliant, and solves all
90 ;;- issues of excess precision accumulating in the extended registers.
91 ;;- By default, GCC does not use these instructions, since such code will
92 ;;- not run on an '030. To use these instructions, use the -m68040-only
93 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
94 ;;- you can make these instructions the default.
96 ;;- These new instructions aren't directly in the md. They are brought
97 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
100 ;;- Information about 68060 port.
102 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
103 ;;- be emulated in software by the OS. It is faster to avoid these
104 ;;- instructions and issue a library call rather than trapping into
105 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
106 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
107 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
109 ;;- Some of these insn's are composites of several m68000 op codes.
110 ;;- The assembler (or final @@??) insures that the appropriate one is
120 ;; UNSPEC_VOLATILE usage:
123 [(UNSPECV_BLOCKAGE 0)
127 [(set (match_operand:DF 0 "push_operand" "=m")
128 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
132 if (FP_REG_P (operands[1]))
133 return \"fmove%.d %f1,%0\";
134 return output_move_double (operands);
137 (define_insn "pushdi"
138 [(set (match_operand:DI 0 "push_operand" "=m")
139 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
143 return output_move_double (operands);
146 ;; We don't want to allow a constant operand for test insns because
147 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
148 ;; be folded while optimizing anyway.
150 (define_expand "tstdi"
151 [(parallel [(set (cc0)
152 (match_operand:DI 0 "nonimmediate_operand" ""))
153 (clobber (match_scratch:SI 1 ""))
154 (clobber (match_scratch:DI 2 ""))])]
156 "m68k_last_compare_had_fp_operands = 0;")
160 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
161 (clobber (match_scratch:SI 1 "=X,d"))
162 (clobber (match_scratch:DI 2 "=d,X"))]
166 if (which_alternative == 0)
170 xoperands[0] = operands[2];
171 xoperands[1] = operands[0];
172 output_move_double (xoperands);
173 cc_status.flags |= CC_REVERSED;
174 return \"neg%.l %R2\;negx%.l %2\";
176 if (find_reg_note (insn, REG_DEAD, operands[0]))
178 cc_status.flags |= CC_REVERSED;
179 return \"neg%.l %R0\;negx%.l %0\";
183 ** 'sub' clears %1, and also clears the X cc bit
184 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
185 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
187 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
190 (define_expand "tstsi"
192 (match_operand:SI 0 "nonimmediate_operand" ""))]
194 "m68k_last_compare_had_fp_operands = 0;")
198 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
203 /* ISI's assembler fails to handle tstl a0. */
204 if (! ADDRESS_REG_P (operands[0]))
206 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
208 return \"tst%.l %0\";
209 /* If you think that the 68020 does not support tstl a0,
210 reread page B-167 of the 68020 manual more carefully. */
211 /* On an address reg, cmpw may replace cmpl. */
213 return \"cmp%.w %0,%#0\";
215 return \"cmp%.w %#0,%0\";
219 ;; This can't use an address register, because comparisons
220 ;; with address registers as second operand always test the whole word.
221 (define_expand "tsthi"
223 (match_operand:HI 0 "nonimmediate_operand" ""))]
225 "m68k_last_compare_had_fp_operands = 0;")
229 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
233 (define_expand "tstqi"
235 (match_operand:QI 0 "nonimmediate_operand" ""))]
237 "m68k_last_compare_had_fp_operands = 0;")
241 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
245 (define_expand "tstsf"
247 (match_operand:SF 0 "general_operand" ""))]
251 m68k_last_compare_had_fp_operands = 1;
256 (match_operand:SF 0 "general_operand" "fdm"))]
260 cc_status.flags = CC_IN_68881;
261 if (FP_REG_P (operands[0]))
262 return \"ftst%.x %0\";
263 return \"ftst%.s %0\";
266 (define_expand "tstdf"
268 (match_operand:DF 0 "general_operand" ""))]
272 m68k_last_compare_had_fp_operands = 1;
277 (match_operand:DF 0 "general_operand" "fm"))]
281 cc_status.flags = CC_IN_68881;
282 if (FP_REG_P (operands[0]))
283 return \"ftst%.x %0\";
284 return \"ftst%.d %0\";
287 ;; compare instructions.
289 (define_expand "cmpdi"
292 (compare (match_operand:DI 0 "nonimmediate_operand" "")
293 (match_operand:DI 1 "general_operand" "")))
294 (clobber (match_dup 2))])]
296 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
300 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
301 (match_operand:DI 2 "general_operand" "d,0")))
302 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
306 if (rtx_equal_p (operands[0], operands[1]))
307 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
310 cc_status.flags |= CC_REVERSED;
311 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
315 ;; This is the second "hook" for PIC code (in addition to movsi). See
316 ;; comment of movsi for a description of PIC handling.
317 (define_expand "cmpsi"
319 (compare (match_operand:SI 0 "nonimmediate_operand" "")
320 (match_operand:SI 1 "general_operand" "")))]
324 m68k_last_compare_had_fp_operands = 0;
325 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
327 /* The source is an address which requires PIC relocation.
328 Call legitimize_pic_address with the source, mode, and a relocation
329 register (a new pseudo, or the final destination if reload_in_progress
330 is set). Then fall through normally */
331 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
332 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
336 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
339 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
340 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
344 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
346 return \"cmpm%.l %0,%1\";
348 return \"cmpm%.l %1,%0\";
350 if (REG_P (operands[1])
351 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
352 { cc_status.flags |= CC_REVERSED;
354 return \"cmp%.l %d1,%d0\";
356 return \"cmp%.l %d0,%d1\";
359 if (ADDRESS_REG_P (operands[0])
360 && GET_CODE (operands[1]) == CONST_INT
361 && INTVAL (operands[1]) < 0x8000
362 && INTVAL (operands[1]) >= -0x8000)
365 return \"cmp%.w %0,%1\";
367 return \"cmp%.w %1,%0\";
371 return \"cmp%.l %d0,%d1\";
373 return \"cmp%.l %d1,%d0\";
379 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
380 (match_operand:SI 1 "general_operand" "r,mrKs")))]
384 if (REG_P (operands[1])
385 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
386 { cc_status.flags |= CC_REVERSED;
388 return \"cmp%.l %d1,%d0\";
390 return \"cmp%.l %d0,%d1\";
394 return \"cmp%.l %d0,%d1\";
396 return \"cmp%.l %d1,%d0\";
400 (define_expand "cmphi"
402 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
403 (match_operand:HI 1 "general_src_operand" "")))]
405 "m68k_last_compare_had_fp_operands = 0;")
409 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
410 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
414 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
416 return \"cmpm%.w %0,%1\";
418 return \"cmpm%.w %1,%0\";
420 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
421 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
422 { cc_status.flags |= CC_REVERSED;
424 return \"cmp%.w %d1,%d0\";
426 return \"cmp%.w %d0,%d1\";
430 return \"cmp%.w %d0,%d1\";
432 return \"cmp%.w %d1,%d0\";
436 (define_expand "cmpqi"
438 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
439 (match_operand:QI 1 "general_src_operand" "")))]
441 "m68k_last_compare_had_fp_operands = 0;")
445 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
446 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
450 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
452 return \"cmpm%.b %0,%1\";
454 return \"cmpm%.b %1,%0\";
456 if (REG_P (operands[1])
457 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
458 { cc_status.flags |= CC_REVERSED;
460 return \"cmp%.b %d1,%d0\";
462 return \"cmp%.b %d0,%d1\";
466 return \"cmp%.b %d0,%d1\";
468 return \"cmp%.b %d1,%d0\";
472 (define_expand "cmpdf"
474 (compare (match_operand:DF 0 "general_operand" "")
475 (match_operand:DF 1 "general_operand" "")))]
479 m68k_last_compare_had_fp_operands = 1;
484 (compare (match_operand:DF 0 "general_operand" "f,mG")
485 (match_operand:DF 1 "general_operand" "fmG,f")))]
489 cc_status.flags = CC_IN_68881;
491 if (REG_P (operands[0]))
493 if (REG_P (operands[1]))
494 return \"fcmp%.x %0,%1\";
496 return \"fcmp%.d %0,%f1\";
498 cc_status.flags |= CC_REVERSED;
499 return \"fcmp%.d %1,%f0\";
501 if (REG_P (operands[0]))
503 if (REG_P (operands[1]))
504 return \"fcmp%.x %1,%0\";
506 return \"fcmp%.d %f1,%0\";
508 cc_status.flags |= CC_REVERSED;
509 return \"fcmp%.d %f0,%1\";
513 (define_expand "cmpsf"
515 (compare (match_operand:SF 0 "general_operand" "")
516 (match_operand:SF 1 "general_operand" "")))]
520 m68k_last_compare_had_fp_operands = 1;
525 (compare (match_operand:SF 0 "general_operand" "f,mdG")
526 (match_operand:SF 1 "general_operand" "fmdG,f")))]
530 cc_status.flags = CC_IN_68881;
532 if (FP_REG_P (operands[0]))
534 if (FP_REG_P (operands[1]))
535 return \"fcmp%.x %0,%1\";
537 return \"fcmp%.s %0,%f1\";
539 cc_status.flags |= CC_REVERSED;
540 return \"fcmp%.s %1,%f0\";
542 if (FP_REG_P (operands[0]))
544 if (FP_REG_P (operands[1]))
545 return \"fcmp%.x %1,%0\";
547 return \"fcmp%.s %f1,%0\";
549 cc_status.flags |= CC_REVERSED;
550 return \"fcmp%.s %f0,%1\";
554 ;; Recognizers for btst instructions.
556 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
557 ;; specified as a constant, so we must disable all patterns that may extract
558 ;; from a MEM at a constant bit position if we can't use this as a constraint.
561 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
563 (minus:SI (const_int 7)
564 (match_operand:SI 1 "general_operand" "di"))))]
566 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
568 ;; This is the same as the above pattern except for the constraints. The 'i'
572 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
574 (minus:SI (const_int 7)
575 (match_operand:SI 1 "general_operand" "d"))))]
577 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
580 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
582 (minus:SI (const_int 31)
583 (match_operand:SI 1 "general_operand" "di"))))]
585 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
587 ;; The following two patterns are like the previous two
588 ;; except that they use the fact that bit-number operands
589 ;; are automatically masked to 3 or 5 bits.
592 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
594 (minus:SI (const_int 7)
596 (match_operand:SI 1 "register_operand" "d")
599 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
602 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
604 (minus:SI (const_int 31)
606 (match_operand:SI 1 "register_operand" "d")
609 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
611 ;; Nonoffsettable mem refs are ok in this one pattern
612 ;; since we don't try to adjust them.
614 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
616 (match_operand:SI 1 "const_int_operand" "n")))]
617 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
620 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
621 return output_btst (operands, operands[1], operands[0], insn, 7);
625 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
627 (match_operand:SI 1 "const_int_operand" "n")))]
631 if (GET_CODE (operands[0]) == MEM)
633 operands[0] = adjust_address (operands[0], QImode,
634 INTVAL (operands[1]) / 8);
635 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
636 return output_btst (operands, operands[1], operands[0], insn, 7);
638 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
639 return output_btst (operands, operands[1], operands[0], insn, 31);
642 ;; This is the same as the above pattern except for the constraints.
643 ;; The 'o' has been replaced with 'Q'.
646 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
648 (match_operand:SI 1 "const_int_operand" "n")))]
652 if (GET_CODE (operands[0]) == MEM)
654 operands[0] = adjust_address (operands[0], QImode,
655 INTVAL (operands[1]) / 8);
656 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
657 return output_btst (operands, operands[1], operands[0], insn, 7);
659 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
660 return output_btst (operands, operands[1], operands[0], insn, 31);
666 ;; A special case in which it is not desirable
667 ;; to reload the constant into a data register.
668 (define_insn "pushexthisi_const"
669 [(set (match_operand:SI 0 "push_operand" "=m")
670 (match_operand:SI 1 "const_int_operand" "J"))]
671 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
674 if (operands[1] == const0_rtx)
675 return \"clr%.l %0\";
680 ;(define_insn "swapsi"
681 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
682 ; (match_operand:SI 1 "general_operand" "+r"))
683 ; (set (match_dup 1) (match_dup 0))]
687 ;; Special case of fullword move when source is zero.
688 ;; The reason this is special is to avoid loading a zero
689 ;; into a data reg with moveq in order to store it elsewhere.
691 (define_insn "movsi_const0"
692 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
694 ;; clr insns on 68000 read before writing.
695 ;; This isn't so on the 68010, but we have no TARGET_68010.
696 "((TARGET_68020 || TARGET_5200)
697 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
700 if (ADDRESS_REG_P (operands[0]))
702 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
703 if (!TARGET_68040 && !TARGET_68060)
704 return \"sub%.l %0,%0\";
709 /* Many SGS assemblers croak on size specifiers for constants. */
712 return \"lea 0.w,%0\";
715 return \"lea 0:w,%0\";
719 /* moveq is faster on the 68000. */
720 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
721 #if defined(MOTOROLA)
722 return \"moveq%.l %#0,%0\";
724 return \"moveq %#0,%0\";
726 return \"clr%.l %0\";
729 ;; General case of fullword move.
731 ;; This is the main "hook" for PIC code. When generating
732 ;; PIC, movsi is responsible for determining when the source address
733 ;; needs PIC relocation and appropriately calling legitimize_pic_address
734 ;; to perform the actual relocation.
736 ;; In both the PIC and non-PIC cases the patterns generated will
737 ;; matched by the next define_insn.
738 (define_expand "movsi"
739 [(set (match_operand:SI 0 "nonimmediate_operand" "")
740 (match_operand:SI 1 "general_operand" ""))]
744 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
746 /* The source is an address which requires PIC relocation.
747 Call legitimize_pic_address with the source, mode, and a relocation
748 register (a new pseudo, or the final destination if reload_in_progress
749 is set). Then fall through normally */
750 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
751 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
753 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
755 /* Don't allow writes to memory except via a register;
756 the m68k doesn't consider PC-relative addresses to be writable. */
757 if (symbolic_operand (operands[0], SImode))
758 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
759 else if (GET_CODE (operands[0]) == MEM
760 && symbolic_operand (XEXP (operands[0], 0), SImode))
761 operands[0] = gen_rtx (MEM, SImode,
762 force_reg (SImode, XEXP (operands[0], 0)));
766 ;; General case of fullword move. The register constraints
767 ;; force integer constants in range for a moveq to be reloaded
768 ;; if they are headed for memory.
770 ;; Notes: make sure no alternative allows g vs g.
771 ;; We don't allow f-regs since fixed point cannot go in them.
772 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
773 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
778 return output_move_simode (operands);
782 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
783 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
785 "* return output_move_simode (operands);")
787 ;; Special case of fullword move, where we need to get a non-GOT PIC
788 ;; reference into an address register.
790 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
791 (match_operand:SI 1 "pcrel_address" ""))]
795 if (push_operand (operands[0], SImode))
797 return \"lea %a1,%0\";
800 (define_expand "movhi"
801 [(set (match_operand:HI 0 "nonimmediate_operand" "")
802 (match_operand:HI 1 "general_operand" ""))]
807 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
808 (match_operand:HI 1 "general_src_operand" "gS"))]
810 "* return output_move_himode (operands);")
813 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
814 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
816 "* return output_move_himode (operands);")
818 (define_expand "movstricthi"
819 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
820 (match_operand:HI 1 "general_src_operand" ""))]
825 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
826 (match_operand:HI 1 "general_src_operand" "rmSn"))]
828 "* return output_move_stricthi (operands);")
831 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
832 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
834 "* return output_move_stricthi (operands);")
836 (define_expand "movqi"
837 [(set (match_operand:QI 0 "nonimmediate_operand" "")
838 (match_operand:QI 1 "general_src_operand" ""))]
843 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
844 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
846 "* return output_move_qimode (operands);")
849 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
850 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
852 "* return output_move_qimode (operands);")
854 (define_expand "movstrictqi"
855 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
856 (match_operand:QI 1 "general_src_operand" ""))]
861 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
862 (match_operand:QI 1 "general_src_operand" "dmSn"))]
864 "* return output_move_strictqi (operands);")
867 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
868 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
870 "* return output_move_strictqi (operands);")
872 (define_expand "pushqi1"
873 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
874 (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
875 (match_operand:QI 0 "general_operand" ""))]
879 (define_expand "movsf"
880 [(set (match_operand:SF 0 "nonimmediate_operand" "")
881 (match_operand:SF 1 "general_operand" ""))]
886 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
887 (match_operand:SF 1 "general_operand" "rmfF"))]
891 if (FP_REG_P (operands[0]))
893 if (FP_REG_P (operands[1]))
894 return \"f%$move%.x %1,%0\";
895 else if (ADDRESS_REG_P (operands[1]))
896 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
897 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
898 return output_move_const_single (operands);
899 return \"f%$move%.s %f1,%0\";
901 if (FP_REG_P (operands[1]))
903 if (ADDRESS_REG_P (operands[0]))
904 return \"fmove%.s %1,%-\;move%.l %+,%0\";
905 return \"fmove%.s %f1,%0\";
907 if (operands[1] == CONST0_RTX (SFmode)
908 /* clr insns on 68000 read before writing.
909 This isn't so on the 68010, but we have no TARGET_68010. */
910 && ((TARGET_68020 || TARGET_5200)
911 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
913 if (ADDRESS_REG_P (operands[0]))
915 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
916 if (!TARGET_68040 && !TARGET_68060)
917 return \"sub%.l %0,%0\";
922 /* Many SGS assemblers croak on size specifiers for constants. */
925 return \"lea 0.w,%0\";
928 return \"lea 0:w,%0\";
932 /* moveq is faster on the 68000. */
933 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
935 #if defined(MOTOROLA)
936 return \"moveq%.l %#0,%0\";
938 return \"moveq %#0,%0\";
941 return \"clr%.l %0\";
943 return \"move%.l %1,%0\";
947 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
948 (match_operand:SF 1 "general_operand" "g,r"))]
950 "* return \"move%.l %1,%0\";")
952 (define_expand "movdf"
953 [(set (match_operand:DF 0 "nonimmediate_operand" "")
954 (match_operand:DF 1 "general_operand" ""))]
959 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
960 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
961 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
962 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
966 if (FP_REG_P (operands[0]))
968 if (FP_REG_P (operands[1]))
969 return \"f%&move%.x %1,%0\";
970 if (REG_P (operands[1]))
973 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
974 output_asm_insn (\"move%.l %1,%-\", xoperands);
975 output_asm_insn (\"move%.l %1,%-\", operands);
976 return \"f%&move%.d %+,%0\";
978 if (GET_CODE (operands[1]) == CONST_DOUBLE)
979 return output_move_const_double (operands);
980 return \"f%&move%.d %f1,%0\";
982 else if (FP_REG_P (operands[1]))
984 if (REG_P (operands[0]))
986 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
987 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
988 return \"move%.l %+,%0\";
991 return \"fmove%.d %f1,%0\";
993 return output_move_double (operands);
997 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
998 (match_operand:DF 1 "general_operand" "g,r"))]
1000 "* return output_move_double (operands);")
1002 ;; ??? The XFmode patterns are schizophrenic about whether constants are
1003 ;; allowed. Most but not all have predicates and constraint that disallow
1004 ;; constants. Most but not all have output templates that handle constants.
1005 ;; See also LEGITIMATE_CONSTANT_P.
1007 (define_expand "movxf"
1008 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1009 (match_operand:XF 1 "general_operand" ""))]
1013 /* We can't rewrite operands during reload. */
1014 if (! reload_in_progress)
1016 if (CONSTANT_P (operands[1]))
1018 operands[1] = force_const_mem (XFmode, operands[1]);
1019 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
1020 operands[1] = adjust_address (operands[1], XFmode, 0);
1022 if (flag_pic && TARGET_PCREL)
1024 /* Don't allow writes to memory except via a register; the
1025 m68k doesn't consider PC-relative addresses to be writable. */
1026 if (GET_CODE (operands[0]) == MEM
1027 && symbolic_operand (XEXP (operands[0], 0), SImode))
1028 operands[0] = gen_rtx (MEM, XFmode,
1029 force_reg (SImode, XEXP (operands[0], 0)));
1035 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1036 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1040 if (FP_REG_P (operands[0]))
1042 if (FP_REG_P (operands[1]))
1043 return \"fmove%.x %1,%0\";
1044 if (REG_P (operands[1]))
1047 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1048 output_asm_insn (\"move%.l %1,%-\", xoperands);
1049 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1050 output_asm_insn (\"move%.l %1,%-\", xoperands);
1051 output_asm_insn (\"move%.l %1,%-\", operands);
1052 return \"fmove%.x %+,%0\";
1054 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1055 return \"fmove%.x %1,%0\";
1056 return \"fmove%.x %f1,%0\";
1058 if (FP_REG_P (operands[1]))
1060 if (REG_P (operands[0]))
1062 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1063 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1064 output_asm_insn (\"move%.l %+,%0\", operands);
1065 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1066 return \"move%.l %+,%0\";
1068 /* Must be memory destination. */
1069 return \"fmove%.x %f1,%0\";
1071 return output_move_double (operands);
1076 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1077 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1078 "! TARGET_68881 && ! TARGET_5200"
1081 if (FP_REG_P (operands[0]))
1083 if (FP_REG_P (operands[1]))
1084 return \"fmove%.x %1,%0\";
1085 if (REG_P (operands[1]))
1088 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1089 output_asm_insn (\"move%.l %1,%-\", xoperands);
1090 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1091 output_asm_insn (\"move%.l %1,%-\", xoperands);
1092 output_asm_insn (\"move%.l %1,%-\", operands);
1093 return \"fmove%.x %+,%0\";
1095 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1096 return \"fmove%.x %1,%0\";
1097 return \"fmove%.x %f1,%0\";
1099 if (FP_REG_P (operands[1]))
1101 if (REG_P (operands[0]))
1103 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1104 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1105 output_asm_insn (\"move%.l %+,%0\", operands);
1106 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1107 return \"move%.l %+,%0\";
1110 return \"fmove%.x %f1,%0\";
1112 return output_move_double (operands);
1117 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1118 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1119 "! TARGET_68881 && TARGET_5200"
1120 "* return output_move_double (operands);")
1122 (define_expand "movdi"
1123 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1124 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1125 (match_operand:DI 1 "general_operand" ""))]
1129 ;; movdi can apply to fp regs in some cases
1131 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1132 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1133 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1134 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1135 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1136 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1137 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1141 if (FP_REG_P (operands[0]))
1143 if (FP_REG_P (operands[1]))
1144 return \"fmove%.x %1,%0\";
1145 if (REG_P (operands[1]))
1148 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1149 output_asm_insn (\"move%.l %1,%-\", xoperands);
1150 output_asm_insn (\"move%.l %1,%-\", operands);
1151 return \"fmove%.d %+,%0\";
1153 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1154 return output_move_const_double (operands);
1155 return \"fmove%.d %f1,%0\";
1157 else if (FP_REG_P (operands[1]))
1159 if (REG_P (operands[0]))
1161 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1162 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1163 return \"move%.l %+,%0\";
1166 return \"fmove%.d %f1,%0\";
1168 return output_move_double (operands);
1172 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1173 (match_operand:DI 1 "general_operand" "g,r"))]
1175 "* return output_move_double (operands);")
1177 ;; Thus goes after the move instructions
1178 ;; because the move instructions are better (require no spilling)
1179 ;; when they can apply. It goes before the add/sub insns
1180 ;; so we will prefer it to them.
1182 (define_insn "pushasi"
1183 [(set (match_operand:SI 0 "push_operand" "=m")
1184 (match_operand:SI 1 "address_operand" "p"))]
1188 ;; truncation instructions
1189 (define_insn "truncsiqi2"
1190 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1192 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1196 if (GET_CODE (operands[0]) == REG)
1198 /* Must clear condition codes, since the move.l bases them on
1199 the entire 32 bits, not just the desired 8 bits. */
1201 return \"move%.l %1,%0\";
1203 if (GET_CODE (operands[1]) == MEM)
1204 operands[1] = adjust_address (operands[1], QImode, 3);
1205 return \"move%.b %1,%0\";
1208 (define_insn "trunchiqi2"
1209 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1211 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1215 if (GET_CODE (operands[0]) == REG
1216 && (GET_CODE (operands[1]) == MEM
1217 || GET_CODE (operands[1]) == CONST_INT))
1219 /* Must clear condition codes, since the move.w bases them on
1220 the entire 16 bits, not just the desired 8 bits. */
1222 return \"move%.w %1,%0\";
1224 if (GET_CODE (operands[0]) == REG)
1226 /* Must clear condition codes, since the move.l bases them on
1227 the entire 32 bits, not just the desired 8 bits. */
1229 return \"move%.l %1,%0\";
1231 if (GET_CODE (operands[1]) == MEM)
1232 operands[1] = adjust_address (operands[1], QImode, 1);
1233 return \"move%.b %1,%0\";
1236 (define_insn "truncsihi2"
1237 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1239 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1243 if (GET_CODE (operands[0]) == REG)
1245 /* Must clear condition codes, since the move.l bases them on
1246 the entire 32 bits, not just the desired 8 bits. */
1248 return \"move%.l %1,%0\";
1250 if (GET_CODE (operands[1]) == MEM)
1251 operands[1] = adjust_address (operands[1], QImode, 2);
1252 return \"move%.w %1,%0\";
1255 ;; zero extension instructions
1257 (define_insn "zero_extendqidi2"
1258 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1259 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1264 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1265 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1268 (define_insn "zero_extendhidi2"
1269 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1270 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1275 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1276 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1279 ;; this is the canonical form for (lshiftrt:DI x 32)
1280 (define_expand "zero_extendsidi2"
1281 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1282 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1286 (define_insn "*zero_extendsidi2_cf"
1287 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
1288 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
1293 if (GET_CODE (operands[0]) == REG)
1294 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1295 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1296 return \"move%.l %1,%0\;clr%.l %0\";
1297 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1298 return \"clr%.l %0\;move%.l %1,%0\";
1300 operands[2] = adjust_address (operands[0], SImode, 4);
1301 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1302 || REGNO (operands[1]) != REGNO (operands[2]))
1303 output_asm_insn (\"move%.l %1,%2\", operands);
1304 if (ADDRESS_REG_P (operands[0]))
1305 return \"sub%.l %0,%0\";
1307 return \"clr%.l %0\";
1310 (define_insn "*zero_extendsidi2"
1311 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1312 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1317 if (GET_CODE (operands[0]) == REG)
1318 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1319 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1320 return \"move%.l %1,%0\;clr%.l %0\";
1321 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1322 return \"clr%.l %0\;move%.l %1,%0\";
1324 operands[2] = adjust_address (operands[0], SImode, 4);
1325 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1326 || REGNO (operands[1]) != REGNO (operands[2]))
1327 output_asm_insn (\"move%.l %1,%2\", operands);
1328 if (ADDRESS_REG_P (operands[0]))
1329 return \"sub%.l %0,%0\";
1331 return \"clr%.l %0\";
1334 (define_expand "zero_extendhisi2"
1335 [(set (match_operand:SI 0 "register_operand" "")
1337 (set (strict_low_part (match_dup 2))
1338 (match_operand:HI 1 "general_operand" ""))]
1342 operands[1] = make_safe_from (operands[1], operands[0]);
1343 operands[2] = gen_lowpart_SUBREG (HImode, operands[0]);
1346 (define_expand "zero_extendqihi2"
1347 [(set (match_operand:HI 0 "register_operand" "")
1349 (set (strict_low_part (match_dup 2))
1350 (match_operand:QI 1 "general_operand" ""))]
1354 operands[1] = make_safe_from (operands[1], operands[0]);
1355 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1358 (define_expand "zero_extendqisi2"
1359 [(set (match_operand:SI 0 "register_operand" "")
1361 (set (strict_low_part (match_dup 2))
1362 (match_operand:QI 1 "general_operand" ""))]
1366 operands[1] = make_safe_from (operands[1], operands[0]);
1367 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1370 ;; Patterns to recognize zero-extend insns produced by the combiner.
1371 ;; We don't allow both operands in memory, because of aliasing problems.
1372 ;; Explicitly disallow two memory operands via the condition since reloading
1373 ;; of this case will result in worse code than the uncombined patterns.
1376 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d<")
1377 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1378 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1381 if (DATA_REG_P (operands[0]))
1383 if (GET_CODE (operands[1]) == REG
1384 && REGNO (operands[0]) == REGNO (operands[1]))
1385 return \"and%.l %#0xFFFF,%0\";
1386 if (reg_mentioned_p (operands[0], operands[1]))
1387 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1388 return \"clr%.l %0\;move%.w %1,%0\";
1390 else if (GET_CODE (operands[0]) == MEM
1391 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1392 return \"move%.w %1,%0\;clr%.w %0\";
1393 else if (GET_CODE (operands[0]) == MEM
1394 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1395 return \"clr%.w %0\;move%.w %1,%0\";
1398 output_asm_insn (\"clr%.w %0\", operands);
1399 operands[0] = adjust_address (operands[0], HImode, 2);
1400 return \"move%.w %1,%0\";
1405 [(set (match_operand:HI 0 "nonimmediate_operand" "=do<>,d")
1406 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1407 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1410 if (DATA_REG_P (operands[0]))
1412 if (GET_CODE (operands[1]) == REG
1413 && REGNO (operands[0]) == REGNO (operands[1]))
1414 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1415 if (reg_mentioned_p (operands[0], operands[1]))
1416 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1417 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1418 return \"clr%.w %0\;move%.b %1,%0\";
1420 else if (GET_CODE (operands[0]) == MEM
1421 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1423 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1424 == STACK_POINTER_REGNUM)
1426 output_asm_insn (\"clr%.w %-\", operands);
1427 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1428 plus_constant (stack_pointer_rtx, 1));
1429 return \"move%.b %1,%0\";
1432 return \"move%.b %1,%0\;clr%.b %0\";
1434 else if (GET_CODE (operands[0]) == MEM
1435 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1436 return \"clr%.b %0\;move%.b %1,%0\";
1439 output_asm_insn (\"clr%.b %0\", operands);
1440 operands[0] = adjust_address (operands[0], QImode, 1);
1441 return \"move%.b %1,%0\";
1446 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d")
1447 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1448 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1451 if (DATA_REG_P (operands[0]))
1453 if (GET_CODE (operands[1]) == REG
1454 && REGNO (operands[0]) == REGNO (operands[1]))
1455 return \"and%.l %#0xFF,%0\";
1456 if (reg_mentioned_p (operands[0], operands[1]))
1457 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1458 return \"clr%.l %0\;move%.b %1,%0\";
1460 else if (GET_CODE (operands[0]) == MEM
1461 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1463 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1466 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1468 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1471 return \"clrl %0@-\;moveb %1,%0@(3)\";
1474 else if (GET_CODE (operands[0]) == MEM
1475 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1477 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1480 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1482 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1485 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1490 output_asm_insn (\"clr%.l %0\", operands);
1491 operands[0] = adjust_address (operands[0], QImode, 3);
1492 return \"move%.b %1,%0\";
1496 ;; sign extension instructions
1498 (define_insn "extendqidi2"
1499 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1500 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1505 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1506 if (TARGET_68020 || TARGET_5200)
1507 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1509 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1512 (define_insn "extendhidi2"
1513 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1515 (match_operand:HI 1 "general_src_operand" "rmS")))]
1520 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1521 if (TARGET_68020 || TARGET_5200)
1522 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1524 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1527 (define_insn "extendsidi2"
1528 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1530 (match_operand:SI 1 "general_operand" "rm")))]
1535 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1536 if (TARGET_68020 || TARGET_5200)
1537 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1539 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1542 ;; Special case when one can avoid register clobbering, copy and test
1543 ;; Maybe there is a way to make that the general case, by forcing the
1544 ;; result of the SI tree to be in the lower register of the DI target
1546 (define_insn "extendplussidi"
1547 [(set (match_operand:DI 0 "register_operand" "=d")
1548 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1549 (match_operand:SI 2 "general_operand" "rmn"))))]
1554 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1555 if (GET_CODE (operands[1]) == CONST_INT
1556 && (unsigned) INTVAL (operands[1]) > 8)
1558 rtx tmp = operands[1];
1560 operands[1] = operands[2];
1563 if (GET_CODE (operands[1]) == REG
1564 && REGNO (operands[1]) == REGNO (operands[3]))
1565 output_asm_insn (\"add%.l %2,%3\", operands);
1567 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1568 if (TARGET_68020 || TARGET_5200)
1569 return \"smi %0\;extb%.l %0\";
1571 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1574 (define_insn "extendhisi2"
1575 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1577 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1581 if (ADDRESS_REG_P (operands[0]))
1582 return \"move%.w %1,%0\";
1583 return \"ext%.l %0\";
1586 (define_insn "extendqihi2"
1587 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1588 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1592 (define_insn "extendqisi2"
1593 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1594 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1595 "TARGET_68020 || TARGET_5200"
1598 ;; Conversions between float and double.
1600 (define_expand "extendsfdf2"
1601 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1603 (match_operand:SF 1 "general_operand" "")))]
1608 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1610 (match_operand:SF 1 "general_operand" "f,dmF")))]
1614 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1616 if (REGNO (operands[0]) == REGNO (operands[1]))
1618 /* Extending float to double in an fp-reg is a no-op.
1619 NOTICE_UPDATE_CC has already assumed that the
1620 cc will be set. So cancel what it did. */
1621 cc_status = cc_prev_status;
1624 return \"f%&move%.x %1,%0\";
1626 if (FP_REG_P (operands[0]))
1627 return \"f%&move%.s %f1,%0\";
1628 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1630 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1631 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1632 return \"move%.l %+,%0\";
1634 return \"fmove%.d %f1,%0\";
1637 ;; This cannot output into an f-reg because there is no way to be
1638 ;; sure of truncating in that case.
1639 (define_expand "truncdfsf2"
1640 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1642 (match_operand:DF 1 "general_operand" "")))]
1646 ;; On the '040 we can truncate in a register accurately and easily.
1648 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1650 (match_operand:DF 1 "general_operand" "fmG")))]
1654 if (FP_REG_P (operands[1]))
1655 return \"f%$move%.x %1,%0\";
1656 return \"f%$move%.d %f1,%0\";
1660 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1662 (match_operand:DF 1 "general_operand" "f")))]
1666 ;; Conversion between fixed point and floating point.
1667 ;; Note that among the fix-to-float insns
1668 ;; the ones that start with SImode come first.
1669 ;; That is so that an operand that is a CONST_INT
1670 ;; (and therefore lacks a specific machine mode).
1671 ;; will be recognized as SImode (which is always valid)
1672 ;; rather than as QImode or HImode.
1674 (define_expand "floatsisf2"
1675 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1676 (float:SF (match_operand:SI 1 "general_operand" "")))]
1681 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1682 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1686 (define_expand "floatsidf2"
1687 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1688 (float:DF (match_operand:SI 1 "general_operand" "")))]
1693 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1694 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1698 (define_insn "floathisf2"
1699 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1700 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1704 (define_insn "floathidf2"
1705 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1706 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1710 (define_insn "floatqisf2"
1711 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1712 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1716 (define_insn "floatqidf2"
1717 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1718 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1722 ;; New routines to convert floating-point values to integers
1723 ;; to be used on the '040. These should be faster than trapping
1724 ;; into the kernel to emulate fintrz. They should also be faster
1725 ;; than calling the subroutines fixsfsi or fixdfsi.
1727 (define_insn "fix_truncdfsi2"
1728 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1729 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1730 (clobber (match_scratch:SI 2 "=d"))
1731 (clobber (match_scratch:SI 3 "=d"))]
1732 "TARGET_68881 && TARGET_68040"
1736 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1739 (define_insn "fix_truncdfhi2"
1740 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1741 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1742 (clobber (match_scratch:SI 2 "=d"))
1743 (clobber (match_scratch:SI 3 "=d"))]
1744 "TARGET_68881 && TARGET_68040"
1748 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1751 (define_insn "fix_truncdfqi2"
1752 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1753 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1754 (clobber (match_scratch:SI 2 "=d"))
1755 (clobber (match_scratch:SI 3 "=d"))]
1756 "TARGET_68881 && TARGET_68040"
1760 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1763 ;; Convert a float to a float whose value is an integer.
1764 ;; This is the first stage of converting it to an integer type.
1766 (define_insn "ftruncdf2"
1767 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1768 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1769 "TARGET_68881 && !TARGET_68040"
1772 if (FP_REG_P (operands[1]))
1773 return \"fintrz%.x %f1,%0\";
1774 return \"fintrz%.d %f1,%0\";
1777 (define_insn "ftruncsf2"
1778 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1779 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1780 "TARGET_68881 && !TARGET_68040"
1783 if (FP_REG_P (operands[1]))
1784 return \"fintrz%.x %f1,%0\";
1785 return \"fintrz%.s %f1,%0\";
1788 ;; Convert a float whose value is an integer
1789 ;; to an actual integer. Second stage of converting float to integer type.
1790 (define_insn "fixsfqi2"
1791 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1792 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1796 (define_insn "fixsfhi2"
1797 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1798 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1802 (define_insn "fixsfsi2"
1803 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1804 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1808 (define_insn "fixdfqi2"
1809 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1810 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1814 (define_insn "fixdfhi2"
1815 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1816 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1820 (define_insn "fixdfsi2"
1821 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1822 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1828 (define_insn "adddi_lshrdi_63"
1829 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1830 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1833 (clobber (match_scratch:SI 2 "=d"))]
1837 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1838 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1840 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1841 if (GET_CODE (operands[1]) == REG)
1842 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1843 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1844 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1845 operands[4] = operands[1];
1847 operands[4] = adjust_address (operands[1], SImode, 4);
1848 if (GET_CODE (operands[1]) == MEM
1849 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1850 output_asm_insn (\"move%.l %4,%3\", operands);
1851 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1852 if (TARGET_68020 || TARGET_5200)
1853 output_asm_insn (\"extb%.l %2\", operands);
1855 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1856 if (GET_CODE (operands[1]) != MEM
1857 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1858 output_asm_insn (\"move%.l %4,%3\", operands);
1859 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1862 (define_insn "adddi_sexthishl32"
1863 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
1864 (plus:DI (ashift:DI (sign_extend:DI
1865 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1867 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1868 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1873 if (ADDRESS_REG_P (operands[0]))
1874 return \"add%.w %1,%0\";
1875 else if (ADDRESS_REG_P (operands[3]))
1876 return \"move%.w %1,%3\;add%.l %3,%0\";
1878 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1881 (define_insn "adddi_dilshr32"
1882 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
1883 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1884 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1885 ;; (const_int 32))))]
1886 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
1888 (match_operand:DI 2 "general_operand" "0,0")))]
1893 if (GET_CODE (operands[0]) == REG)
1894 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1896 operands[2] = adjust_address (operands[0], SImode, 4);
1897 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
1900 (define_insn "adddi_dishl32"
1901 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
1902 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1903 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1904 ;; (const_int 32))))]
1905 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
1907 (match_operand:DI 2 "general_operand" "0,0")))]
1912 if (GET_CODE (operands[1]) == REG)
1913 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1915 operands[1] = adjust_address (operands[1], SImode, 4);
1916 return \"add%.l %1,%0\";
1919 (define_insn "adddi3"
1920 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
1921 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
1922 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
1923 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
1927 if (DATA_REG_P (operands[0]))
1929 if (DATA_REG_P (operands[2]))
1930 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
1931 else if (GET_CODE (operands[2]) == MEM
1932 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
1933 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
1939 if (GET_CODE (operands[2]) == REG)
1941 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
1944 else if (CONSTANT_P (operands[2]))
1945 split_double (operands[2], &high, &low);
1948 low = adjust_address (operands[2], SImode, 4);
1952 operands[1] = low, operands[2] = high;
1953 xoperands[0] = operands[3];
1954 if (GET_CODE (operands[1]) == CONST_INT
1955 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1956 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
1958 xoperands[1] = operands[2];
1960 output_asm_insn (output_move_simode (xoperands), xoperands);
1961 if (GET_CODE (operands[1]) == CONST_INT)
1963 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
1966 return \"add%.l %1,%R0\;addx%.l %3,%0\";
1968 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
1971 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1973 operands[1] = GEN_INT (-INTVAL (operands[1]));
1975 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
1977 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
1981 return \"add%.l %1,%R0\;addx%.l %3,%0\";
1984 else if (GET_CODE (operands[0]) == MEM)
1986 if (GET_CODE (operands[2]) == MEM
1987 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
1988 return \"add%.l %2,%0\;addx%.l %2,%0\";
1990 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1992 operands[1] = gen_rtx_MEM (SImode,
1993 plus_constant (XEXP(operands[0], 0), -8));
1994 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
1996 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1998 operands[1] = XEXP(operands[0], 0);
1999 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2003 operands[1] = adjust_address (operands[0], SImode, 4);
2004 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2011 (define_insn "addsi_lshrsi_31"
2012 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2013 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2019 operands[2] = operands[0];
2020 operands[3] = gen_label_rtx();
2021 if (GET_CODE (operands[0]) == MEM)
2023 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2024 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2025 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2026 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2028 output_asm_insn (\"move%.l %1,%0\", operands);
2030 output_asm_insn (\"jbpl %l3\", operands);
2032 output_asm_insn (\"jpl %l3\", operands);
2035 output_asm_insn (\"addq%.l %#1,%2\", operands);
2037 output_asm_insn (\"add%.l %#1,%2\", operands);
2039 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2040 CODE_LABEL_NUMBER (operands[3]));
2044 (define_expand "addsi3"
2045 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2046 (plus:SI (match_operand:SI 1 "general_operand" "")
2047 (match_operand:SI 2 "general_src_operand" "")))]
2051 ;; Note that the middle two alternatives are near-duplicates
2052 ;; in order to handle insns generated by reload.
2053 ;; This is needed since they are not themselves reloaded,
2054 ;; so commutativity won't apply to them.
2055 (define_insn "*addsi3_internal"
2056 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2057 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2058 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2062 "* return output_addsi3 (operands);")
2064 (define_insn "*addsi3_5200"
2065 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
2066 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2067 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2069 "* return output_addsi3 (operands);")
2072 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2073 (plus:SI (match_operand:SI 1 "general_operand" "0")
2075 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2079 (define_insn "addhi3"
2080 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2081 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2082 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2086 if (GET_CODE (operands[2]) == CONST_INT)
2089 /* If the constant would be a negative number when interpreted as
2090 HImode, make it negative. This is usually, but not always, done
2091 elsewhere in the compiler. First check for constants out of range,
2092 which could confuse us. */
2094 if (INTVAL (operands[2]) >= 32768)
2095 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2097 if (INTVAL (operands[2]) > 0
2098 && INTVAL (operands[2]) <= 8)
2099 return \"addq%.w %2,%0\";
2100 if (INTVAL (operands[2]) < 0
2101 && INTVAL (operands[2]) >= -8)
2103 operands[2] = GEN_INT (- INTVAL (operands[2]));
2104 return \"subq%.w %2,%0\";
2106 /* On the CPU32 it is faster to use two addqw instructions to
2107 add a small integer (8 < N <= 16) to a register.
2108 Likewise for subqw. */
2109 if (TARGET_CPU32 && REG_P (operands[0]))
2111 if (INTVAL (operands[2]) > 8
2112 && INTVAL (operands[2]) <= 16)
2114 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2115 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2117 if (INTVAL (operands[2]) < -8
2118 && INTVAL (operands[2]) >= -16)
2120 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2121 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2125 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2127 return \"lea (%c2,%0),%0\";
2129 return \"lea %0@(%c2),%0\";
2132 return \"add%.w %2,%0\";
2135 ;; These insns must use MATCH_DUP instead of the more expected
2136 ;; use of a matching constraint because the "output" here is also
2137 ;; an input, so you can't use the matching constraint. That also means
2138 ;; that you can't use the "%", so you need patterns with the matched
2139 ;; operand in both positions.
2142 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2143 (plus:HI (match_dup 0)
2144 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2148 if (GET_CODE (operands[1]) == CONST_INT)
2151 /* If the constant would be a negative number when interpreted as
2152 HImode, make it negative. This is usually, but not always, done
2153 elsewhere in the compiler. First check for constants out of range,
2154 which could confuse us. */
2156 if (INTVAL (operands[1]) >= 32768)
2157 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2159 if (INTVAL (operands[1]) > 0
2160 && INTVAL (operands[1]) <= 8)
2161 return \"addq%.w %1,%0\";
2162 if (INTVAL (operands[1]) < 0
2163 && INTVAL (operands[1]) >= -8)
2165 operands[1] = GEN_INT (- INTVAL (operands[1]));
2166 return \"subq%.w %1,%0\";
2168 /* On the CPU32 it is faster to use two addqw instructions to
2169 add a small integer (8 < N <= 16) to a register.
2170 Likewise for subqw. */
2171 if (TARGET_CPU32 && REG_P (operands[0]))
2173 if (INTVAL (operands[1]) > 8
2174 && INTVAL (operands[1]) <= 16)
2176 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2177 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2179 if (INTVAL (operands[1]) < -8
2180 && INTVAL (operands[1]) >= -16)
2182 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2183 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2187 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2189 return \"lea (%c1,%0),%0\";
2191 return \"lea %0@(%c1),%0\";
2194 return \"add%.w %1,%0\";
2198 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2199 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2204 if (GET_CODE (operands[1]) == CONST_INT)
2207 /* If the constant would be a negative number when interpreted as
2208 HImode, make it negative. This is usually, but not always, done
2209 elsewhere in the compiler. First check for constants out of range,
2210 which could confuse us. */
2212 if (INTVAL (operands[1]) >= 32768)
2213 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2215 if (INTVAL (operands[1]) > 0
2216 && INTVAL (operands[1]) <= 8)
2217 return \"addq%.w %1,%0\";
2218 if (INTVAL (operands[1]) < 0
2219 && INTVAL (operands[1]) >= -8)
2221 operands[1] = GEN_INT (- INTVAL (operands[1]));
2222 return \"subq%.w %1,%0\";
2224 /* On the CPU32 it is faster to use two addqw instructions to
2225 add a small integer (8 < N <= 16) to a register.
2226 Likewise for subqw. */
2227 if (TARGET_CPU32 && REG_P (operands[0]))
2229 if (INTVAL (operands[1]) > 8
2230 && INTVAL (operands[1]) <= 16)
2232 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2233 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2235 if (INTVAL (operands[1]) < -8
2236 && INTVAL (operands[1]) >= -16)
2238 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2239 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2243 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2245 return \"lea (%c1,%0),%0\";
2247 return \"lea %0@(%c1),%0\";
2250 return \"add%.w %1,%0\";
2253 (define_insn "addqi3"
2254 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2255 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2256 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2261 if (GET_CODE (operands[2]) == CONST_INT)
2263 if (INTVAL (operands[2]) >= 128)
2264 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2266 if (INTVAL (operands[2]) > 0
2267 && INTVAL (operands[2]) <= 8)
2268 return \"addq%.b %2,%0\";
2269 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2271 operands[2] = GEN_INT (- INTVAL (operands[2]));
2272 return \"subq%.b %2,%0\";
2276 return \"add%.b %2,%0\";
2280 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2281 (plus:QI (match_dup 0)
2282 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2287 if (GET_CODE (operands[1]) == CONST_INT)
2289 if (INTVAL (operands[1]) >= 128)
2290 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2292 if (INTVAL (operands[1]) > 0
2293 && INTVAL (operands[1]) <= 8)
2294 return \"addq%.b %1,%0\";
2295 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2297 operands[1] = GEN_INT (- INTVAL (operands[1]));
2298 return \"subq%.b %1,%0\";
2302 return \"add%.b %1,%0\";
2306 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2307 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2313 if (GET_CODE (operands[1]) == CONST_INT)
2315 if (INTVAL (operands[1]) >= 128)
2316 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2318 if (INTVAL (operands[1]) > 0
2319 && INTVAL (operands[1]) <= 8)
2320 return \"addq%.b %1,%0\";
2321 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2323 operands[1] = GEN_INT (- INTVAL (operands[1]));
2324 return \"subq%.b %1,%0\";
2328 return \"add%.b %1,%0\";
2331 (define_expand "adddf3"
2332 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2333 (plus:DF (match_operand:DF 1 "general_operand" "")
2334 (match_operand:DF 2 "general_operand" "")))]
2339 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2340 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2341 (match_operand:DF 1 "general_operand" "0")))]
2346 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2347 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2348 (match_operand:DF 1 "general_operand" "0")))]
2353 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2354 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2355 (match_operand:DF 1 "general_operand" "0")))]
2360 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2361 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2362 (match_operand:DF 2 "general_operand" "fmG")))]
2366 if (REG_P (operands[2]))
2367 return \"f%&add%.x %2,%0\";
2368 return \"f%&add%.d %f2,%0\";
2371 (define_expand "addsf3"
2372 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2373 (plus:SF (match_operand:SF 1 "general_operand" "")
2374 (match_operand:SF 2 "general_operand" "")))]
2379 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2380 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2381 (match_operand:SF 1 "general_operand" "0")))]
2386 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2387 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2388 (match_operand:SF 1 "general_operand" "0")))]
2393 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2394 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2395 (match_operand:SF 1 "general_operand" "0")))]
2400 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2401 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2402 (match_operand:SF 2 "general_operand" "fdmF")))]
2406 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2407 return \"f%$add%.x %2,%0\";
2408 return \"f%$add%.s %f2,%0\";
2411 ;; subtract instructions
2413 (define_insn "subdi_sexthishl32"
2414 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2415 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2416 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2418 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2423 if (ADDRESS_REG_P (operands[0]))
2424 return \"sub%.w %2,%0\";
2425 else if (ADDRESS_REG_P (operands[3]))
2426 return \"move%.w %2,%3\;sub%.l %3,%0\";
2428 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2431 (define_insn "subdi_dishl32"
2432 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2433 (minus:DI (match_dup 0)
2434 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2440 if (GET_CODE (operands[1]) == REG)
2441 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2443 operands[1] = adjust_address (operands[1], SImode, 4);
2444 return \"sub%.l %1,%0\";
2447 (define_insn "subdi3"
2448 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
2449 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2450 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2451 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2455 if (DATA_REG_P (operands[0]))
2457 if (DATA_REG_P (operands[2]))
2458 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2459 else if (GET_CODE (operands[2]) == MEM
2460 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2462 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2469 if (GET_CODE (operands[2]) == REG)
2471 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2474 else if (CONSTANT_P (operands[2]))
2475 split_double (operands[2], &high, &low);
2478 low = adjust_address (operands[2], SImode, 4);
2482 operands[1] = low, operands[2] = high;
2483 xoperands[0] = operands[3];
2484 if (GET_CODE (operands[1]) == CONST_INT
2485 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2486 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2488 xoperands[1] = operands[2];
2490 output_asm_insn (output_move_simode (xoperands), xoperands);
2491 if (GET_CODE (operands[1]) == CONST_INT)
2493 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2496 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2498 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2501 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2503 operands[1] = GEN_INT (-INTVAL (operands[1]));
2505 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2507 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2511 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2514 else if (GET_CODE (operands[0]) == MEM)
2516 if (GET_CODE (operands[2]) == MEM
2517 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2518 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2520 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2523 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2524 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2526 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2528 operands[1] = XEXP(operands[0], 0);
2529 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2533 operands[1] = adjust_address (operands[0], SImode, 4);
2534 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2541 (define_insn "subsi3"
2542 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
2543 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2544 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2549 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2550 (minus:SI (match_operand:SI 1 "general_operand" "0")
2552 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2556 (define_insn "subhi3"
2557 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2558 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2559 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2564 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2565 (minus:HI (match_dup 0)
2566 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2570 (define_insn "subqi3"
2571 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2572 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2573 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2578 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2579 (minus:QI (match_dup 0)
2580 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2584 (define_expand "subdf3"
2585 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2586 (minus:DF (match_operand:DF 1 "general_operand" "")
2587 (match_operand:DF 2 "general_operand" "")))]
2592 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2593 (minus:DF (match_operand:DF 1 "general_operand" "0")
2594 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2599 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2600 (minus:DF (match_operand:DF 1 "general_operand" "0")
2601 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2606 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2607 (minus:DF (match_operand:DF 1 "general_operand" "0")
2608 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2613 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2614 (minus:DF (match_operand:DF 1 "general_operand" "0")
2615 (match_operand:DF 2 "general_operand" "fmG")))]
2619 if (REG_P (operands[2]))
2620 return \"f%&sub%.x %2,%0\";
2621 return \"f%&sub%.d %f2,%0\";
2624 (define_expand "subsf3"
2625 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2626 (minus:SF (match_operand:SF 1 "general_operand" "")
2627 (match_operand:SF 2 "general_operand" "")))]
2632 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2633 (minus:SF (match_operand:SF 1 "general_operand" "0")
2634 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2639 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2640 (minus:SF (match_operand:SF 1 "general_operand" "0")
2641 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2646 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2647 (minus:SF (match_operand:SF 1 "general_operand" "0")
2648 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2653 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2654 (minus:SF (match_operand:SF 1 "general_operand" "0")
2655 (match_operand:SF 2 "general_operand" "fdmF")))]
2659 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2660 return \"f%$sub%.x %2,%0\";
2661 return \"f%$sub%.s %f2,%0\";
2664 ;; multiply instructions
2666 (define_insn "mulhi3"
2667 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2668 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2669 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2673 #if defined(MOTOROLA)
2674 return \"muls%.w %2,%0\";
2676 return \"muls %2,%0\";
2680 (define_insn "mulhisi3"
2681 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2682 (mult:SI (sign_extend:SI
2683 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2685 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2689 #if defined(MOTOROLA)
2690 return \"muls%.w %2,%0\";
2692 return \"muls %2,%0\";
2697 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2698 (mult:SI (sign_extend:SI
2699 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2700 (match_operand:SI 2 "const_int_operand" "n")))]
2701 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2704 #if defined(MOTOROLA)
2705 return \"muls%.w %2,%0\";
2707 return \"muls %2,%0\";
2711 (define_expand "mulsi3"
2712 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2713 (mult:SI (match_operand:SI 1 "general_operand" "")
2714 (match_operand:SI 2 "general_operand" "")))]
2715 "TARGET_68020 || TARGET_5200"
2719 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2720 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2721 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
2727 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2728 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2729 (match_operand:SI 2 "general_operand" "d<Q>")))]
2733 (define_insn "umulhisi3"
2734 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2735 (mult:SI (zero_extend:SI
2736 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2738 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2742 #if defined(MOTOROLA)
2743 return \"mulu%.w %2,%0\";
2745 return \"mulu %2,%0\";
2750 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2751 (mult:SI (zero_extend:SI
2752 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2753 (match_operand:SI 2 "const_int_operand" "n")))]
2754 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2757 #if defined(MOTOROLA)
2758 return \"mulu%.w %2,%0\";
2760 return \"mulu %2,%0\";
2764 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2765 ;; proper matching constraint. This is because the matching is between
2766 ;; the high-numbered word of the DImode operand[0] and operand[1].
2767 (define_expand "umulsidi3"
2769 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2770 (mult:SI (match_operand:SI 1 "register_operand" "")
2771 (match_operand:SI 2 "register_operand" "")))
2772 (set (subreg:SI (match_dup 0) 0)
2773 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2774 (zero_extend:DI (match_dup 2)))
2775 (const_int 32))))])]
2776 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2780 [(set (match_operand:SI 0 "register_operand" "=d")
2781 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2782 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2783 (set (match_operand:SI 3 "register_operand" "=d")
2784 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2785 (zero_extend:DI (match_dup 2)))
2787 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2790 ; Match immediate case. For 2.4 only match things < 2^31.
2791 ; It's tricky with larger values in these patterns since we need to match
2792 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2795 [(set (match_operand:SI 0 "register_operand" "=d")
2796 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2797 (match_operand:SI 2 "const_int_operand" "n")))
2798 (set (match_operand:SI 3 "register_operand" "=d")
2799 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2802 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2803 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2806 (define_expand "mulsidi3"
2808 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2809 (mult:SI (match_operand:SI 1 "register_operand" "")
2810 (match_operand:SI 2 "register_operand" "")))
2811 (set (subreg:SI (match_dup 0) 0)
2812 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2813 (sign_extend:DI (match_dup 2)))
2814 (const_int 32))))])]
2815 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2819 [(set (match_operand:SI 0 "register_operand" "=d")
2820 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2821 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2822 (set (match_operand:SI 3 "register_operand" "=d")
2823 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2824 (sign_extend:DI (match_dup 2)))
2826 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2830 [(set (match_operand:SI 0 "register_operand" "=d")
2831 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2832 (match_operand:SI 2 "const_int_operand" "n")))
2833 (set (match_operand:SI 3 "register_operand" "=d")
2834 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2837 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2840 (define_expand "umulsi3_highpart"
2842 [(set (match_operand:SI 0 "register_operand" "")
2845 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2846 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2848 (clobber (match_dup 3))])]
2849 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2852 operands[3] = gen_reg_rtx (SImode);
2854 if (GET_CODE (operands[2]) == CONST_INT)
2856 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
2859 /* We have to adjust the operand order for the matching constraints. */
2860 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2861 operands[1], operands[2]));
2867 [(set (match_operand:SI 0 "register_operand" "=d")
2870 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2871 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2873 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2874 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2877 (define_insn "const_umulsi3_highpart"
2878 [(set (match_operand:SI 0 "register_operand" "=d")
2881 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2882 (match_operand:DI 3 "const_uint32_operand" "n"))
2884 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2885 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2888 (define_expand "smulsi3_highpart"
2890 [(set (match_operand:SI 0 "register_operand" "")
2893 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2894 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2896 (clobber (match_dup 3))])]
2897 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2900 operands[3] = gen_reg_rtx (SImode);
2901 if (GET_CODE (operands[2]) == CONST_INT)
2903 /* We have to adjust the operand order for the matching constraints. */
2904 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
2905 operands[1], operands[2]));
2911 [(set (match_operand:SI 0 "register_operand" "=d")
2914 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2915 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2917 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2918 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2921 (define_insn "const_smulsi3_highpart"
2922 [(set (match_operand:SI 0 "register_operand" "=d")
2925 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
2926 (match_operand:DI 3 "const_sint32_operand" "n"))
2928 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2929 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2932 (define_expand "muldf3"
2933 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2934 (mult:DF (match_operand:DF 1 "general_operand" "")
2935 (match_operand:DF 2 "general_operand" "")))]
2940 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2941 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2942 (match_operand:DF 1 "general_operand" "0")))]
2947 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2948 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2949 (match_operand:DF 1 "general_operand" "0")))]
2954 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2955 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2956 (match_operand:DF 1 "general_operand" "0")))]
2961 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2962 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2963 (match_operand:DF 2 "general_operand" "fmG")))]
2967 if (GET_CODE (operands[2]) == CONST_DOUBLE
2968 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
2970 int i = floating_exact_log2 (operands[2]);
2971 operands[2] = GEN_INT (i);
2972 return \"fscale%.l %2,%0\";
2974 if (REG_P (operands[2]))
2975 return \"f%&mul%.x %2,%0\";
2976 return \"f%&mul%.d %f2,%0\";
2979 (define_expand "mulsf3"
2980 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2981 (mult:SF (match_operand:SF 1 "general_operand" "")
2982 (match_operand:SF 2 "general_operand" "")))]
2987 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2988 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2989 (match_operand:SF 1 "general_operand" "0")))]
2993 return (TARGET_68040_ONLY
2994 ? \"fsmul%.l %2,%0\"
2995 : \"fsglmul%.l %2,%0\");
2999 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3000 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3001 (match_operand:SF 1 "general_operand" "0")))]
3005 return (TARGET_68040_ONLY
3006 ? \"fsmul%.w %2,%0\"
3007 : \"fsglmul%.w %2,%0\");
3011 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3012 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3013 (match_operand:SF 1 "general_operand" "0")))]
3017 return (TARGET_68040_ONLY
3018 ? \"fsmul%.b %2,%0\"
3019 : \"fsglmul%.b %2,%0\");
3023 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3024 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3025 (match_operand:SF 2 "general_operand" "fdmF")))]
3029 #ifdef FSGLMUL_USE_S
3030 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3031 return (TARGET_68040_ONLY
3032 ? \"fsmul%.s %2,%0\"
3033 : \"fsglmul%.s %2,%0\");
3035 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3036 return (TARGET_68040_ONLY
3037 ? \"fsmul%.x %2,%0\"
3038 : \"fsglmul%.x %2,%0\");
3040 return (TARGET_68040_ONLY
3041 ? \"fsmul%.s %f2,%0\"
3042 : \"fsglmul%.s %f2,%0\");
3045 ;; divide instructions
3047 (define_expand "divdf3"
3048 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3049 (div:DF (match_operand:DF 1 "general_operand" "")
3050 (match_operand:DF 2 "general_operand" "")))]
3055 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3056 (div:DF (match_operand:DF 1 "general_operand" "0")
3057 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3062 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3063 (div:DF (match_operand:DF 1 "general_operand" "0")
3064 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3069 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3070 (div:DF (match_operand:DF 1 "general_operand" "0")
3071 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3076 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3077 (div:DF (match_operand:DF 1 "general_operand" "0")
3078 (match_operand:DF 2 "general_operand" "fmG")))]
3082 if (REG_P (operands[2]))
3083 return \"f%&div%.x %2,%0\";
3084 return \"f%&div%.d %f2,%0\";
3087 (define_expand "divsf3"
3088 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3089 (div:SF (match_operand:SF 1 "general_operand" "")
3090 (match_operand:SF 2 "general_operand" "")))]
3095 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3096 (div:SF (match_operand:SF 1 "general_operand" "0")
3097 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3101 return (TARGET_68040_ONLY
3102 ? \"fsdiv%.l %2,%0\"
3103 : \"fsgldiv%.l %2,%0\");
3107 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3108 (div:SF (match_operand:SF 1 "general_operand" "0")
3109 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3113 return (TARGET_68040_ONLY
3114 ? \"fsdiv%.w %2,%0\"
3115 : \"fsgldiv%.w %2,%0\");
3119 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3120 (div:SF (match_operand:SF 1 "general_operand" "0")
3121 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3125 return (TARGET_68040_ONLY
3126 ? \"fsdiv%.b %2,%0\"
3127 : \"fsgldiv%.b %2,%0\");
3131 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3132 (div:SF (match_operand:SF 1 "general_operand" "0")
3133 (match_operand:SF 2 "general_operand" "fdmF")))]
3137 #ifdef FSGLDIV_USE_S
3138 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3139 return (TARGET_68040_ONLY
3140 ? \"fsdiv%.s %2,%0\"
3141 : \"fsgldiv%.s %2,%0\");
3143 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3144 return (TARGET_68040_ONLY
3145 ? \"fsdiv%.x %2,%0\"
3146 : \"fsgldiv%.x %2,%0\");
3148 return (TARGET_68040_ONLY
3149 ? \"fsdiv%.s %f2,%0\"
3150 : \"fsgldiv%.s %f2,%0\");
3153 ;; Remainder instructions.
3155 (define_insn "divmodsi4"
3156 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3157 (div:SI (match_operand:SI 1 "general_operand" "0")
3158 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3159 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3160 (mod:SI (match_dup 1) (match_dup 2)))]
3161 "TARGET_68020 && !TARGET_5200"
3164 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3165 return \"divs%.l %2,%0\";
3167 return \"divsl%.l %2,%3:%0\";
3170 (define_insn "udivmodsi4"
3171 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3172 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3173 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3174 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3175 (umod:SI (match_dup 1) (match_dup 2)))]
3176 "TARGET_68020 && !TARGET_5200"
3179 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3180 return \"divu%.l %2,%0\";
3182 return \"divul%.l %2,%3:%0\";
3185 (define_insn "divmodhi4"
3186 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3187 (div:HI (match_operand:HI 1 "general_operand" "0")
3188 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3189 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3190 (mod:HI (match_dup 1) (match_dup 2)))]
3195 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3197 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3199 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3202 return \"move%.l %0,%3\;swap %3\";
3208 (define_insn "udivmodhi4"
3209 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3210 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3211 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3212 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3213 (umod:HI (match_dup 1) (match_dup 2)))]
3218 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3220 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3222 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3225 return \"move%.l %0,%3\;swap %3\";
3231 ;; logical-and instructions
3233 ;; "anddi3" is mainly here to help combine().
3234 (define_insn "anddi3"
3235 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3236 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3237 (match_operand:DI 2 "general_operand" "dn,don")))]
3242 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3243 if (CONSTANT_P (operands[2]))
3247 split_double (operands[2], &hi, &lo);
3249 switch (INTVAL (hi))
3252 output_asm_insn (\"clr%.l %0\", operands);
3260 xoperands[0] = operands[0];
3262 output_asm_insn (output_andsi3 (xoperands), xoperands);
3265 if (GET_CODE (operands[0]) == REG)
3266 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3268 operands[0] = adjust_address (operands[0], SImode, 4);
3269 switch (INTVAL (lo))
3272 output_asm_insn (\"clr%.l %0\", operands);
3280 xoperands[0] = operands[0];
3282 output_asm_insn (output_andsi3 (xoperands), xoperands);
3287 if (GET_CODE (operands[0]) != REG)
3289 operands[1] = adjust_address (operands[0], SImode, 4);
3290 return \"and%.l %2,%0\;and%.l %R2,%1\";
3292 if (GET_CODE (operands[2]) != REG)
3294 operands[1] = adjust_address (operands[2], SImode, 4);
3295 return \"and%.l %2,%0\;and%.l %1,%R0\";
3297 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3300 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3301 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3302 ;; can't allocate pseudos into it.
3304 (define_expand "andsi3"
3305 [(set (match_operand:SI 0 "not_sp_operand" "")
3306 (and:SI (match_operand:SI 1 "general_operand" "")
3307 (match_operand:SI 2 "general_src_operand" "")))]
3311 (define_insn "andsi3_internal"
3312 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3313 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3314 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3318 return output_andsi3 (operands);
3321 (define_insn "andsi3_5200"
3322 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3323 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3324 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3328 (define_insn "andhi3"
3329 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3330 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3331 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3336 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3337 (and:HI (match_dup 0)
3338 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3343 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3344 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3349 (define_insn "andqi3"
3350 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3351 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3352 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3357 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3358 (and:QI (match_dup 0)
3359 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3364 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3365 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3370 ;; inclusive-or instructions
3372 (define_insn "iordi_zext"
3373 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3374 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3375 (match_operand:DI 2 "general_operand" "0,0")))]
3382 if (GET_CODE (operands[0]) == REG)
3383 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3385 operands[0] = adjust_address (operands[0], SImode, 4);
3386 if (GET_MODE (operands[1]) == SImode)
3387 return \"or%.l %1,%0\";
3388 byte_mode = (GET_MODE (operands[1]) == QImode);
3389 if (GET_CODE (operands[0]) == MEM)
3390 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3393 return \"or%.b %1,%0\";
3395 return \"or%.w %1,%0\";
3398 ;; "iordi3" is mainly here to help combine().
3399 (define_insn "iordi3"
3400 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3401 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3402 (match_operand:DI 2 "general_operand" "dn,don")))]
3407 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3408 if (CONSTANT_P (operands[2]))
3412 split_double (operands[2], &hi, &lo);
3414 switch (INTVAL (hi))
3419 /* FIXME : a scratch register would be welcome here if operand[0]
3420 is not a register */
3421 output_asm_insn (\"move%.l %#-1,%0\", operands);
3427 xoperands[0] = operands[0];
3429 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3432 if (GET_CODE (operands[0]) == REG)
3433 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3435 operands[0] = adjust_address (operands[0], SImode, 4);
3436 switch (INTVAL (lo))
3441 /* FIXME : a scratch register would be welcome here if operand[0]
3442 is not a register */
3443 output_asm_insn (\"move%.l %#-1,%0\", operands);
3449 xoperands[0] = operands[0];
3451 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3456 if (GET_CODE (operands[0]) != REG)
3458 operands[1] = adjust_address (operands[0], SImode, 4);
3459 return \"or%.l %2,%0\;or%.l %R2,%1\";
3461 if (GET_CODE (operands[2]) != REG)
3463 operands[1] = adjust_address (operands[2], SImode, 4);
3464 return \"or%.l %2,%0\;or%.l %1,%R0\";
3466 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3469 (define_expand "iorsi3"
3470 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3471 (ior:SI (match_operand:SI 1 "general_operand" "")
3472 (match_operand:SI 2 "general_src_operand" "")))]
3476 (define_insn "iorsi3_internal"
3477 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3478 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3479 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3483 return output_iorsi3 (operands);
3486 (define_insn "iorsi3_5200"
3487 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3488 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3489 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3493 (define_insn "iorhi3"
3494 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3495 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3496 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3501 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3502 (ior:HI (match_dup 0)
3503 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3508 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3509 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3514 (define_insn "iorqi3"
3515 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3516 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3517 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3522 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3523 (ior:QI (match_dup 0)
3524 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3529 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3530 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3535 ;; On all 68k models, this makes faster code in a special case.
3536 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3538 (define_insn "iorsi_zexthi_ashl16"
3539 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3540 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3541 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3547 if (GET_CODE (operands[2]) != REG)
3548 operands[2] = adjust_address (operands[2], HImode, 2);
3549 if (GET_CODE (operands[2]) != REG
3550 || REGNO (operands[2]) != REGNO (operands[0]))
3551 output_asm_insn (\"move%.w %2,%0\", operands);
3552 return \"swap %0\;mov%.w %1,%0\";
3555 (define_insn "iorsi_zext"
3556 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3557 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3558 (match_operand:SI 2 "general_operand" "0,0")))]
3565 byte_mode = (GET_MODE (operands[1]) == QImode);
3566 if (GET_CODE (operands[0]) == MEM)
3567 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3570 return \"or%.b %1,%0\";
3572 return \"or%.w %1,%0\";
3577 ;; "xordi3" is mainly here to help combine().
3578 (define_insn "xordi3"
3579 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3580 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3581 (match_operand:DI 2 "general_operand" "dn")))]
3586 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3588 if (CONSTANT_P (operands[2]))
3592 split_double (operands[2], &hi, &lo);
3594 switch (INTVAL (hi))
3599 output_asm_insn (\"not%.l %0\", operands);
3602 /* FIXME : a scratch register would be welcome here if
3603 -128 <= INTVAL (hi) < -1 */
3607 xoperands[0] = operands[0];
3609 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3612 if (GET_CODE (operands[0]) == REG)
3613 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3615 operands[0] = adjust_address (operands[0], SImode, 4);
3616 switch (INTVAL (lo))
3621 output_asm_insn (\"not%.l %0\", operands);
3624 /* FIXME : a scratch register would be welcome here if
3625 -128 <= INTVAL (lo) < -1 */
3627 /* FIXME : this should be merged with xorsi3 */
3631 xoperands[0] = operands[0];
3633 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3638 if (GET_CODE (operands[0]) != REG)
3640 operands[1] = adjust_address (operands[0], SImode, 4);
3641 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3643 if (GET_CODE (operands[2]) != REG)
3645 operands[1] = adjust_address (operands[2], SImode, 4);
3646 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3648 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3651 (define_expand "xorsi3"
3652 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3653 (xor:SI (match_operand:SI 1 "general_operand" "")
3654 (match_operand:SI 2 "general_operand" "")))]
3658 (define_insn "xorsi3_internal"
3659 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3660 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3661 (match_operand:SI 2 "general_operand" "di,dKT")))]
3666 return output_xorsi3 (operands);
3669 (define_insn "xorsi3_5200"
3670 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3671 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3672 (match_operand:SI 2 "general_operand" "d,Ks")))]
3676 (define_insn "xorhi3"
3677 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3678 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3679 (match_operand:HI 2 "general_operand" "dn")))]
3684 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3685 (xor:HI (match_dup 0)
3686 (match_operand:HI 1 "general_operand" "dn")))]
3691 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3692 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3697 (define_insn "xorqi3"
3698 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3699 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3700 (match_operand:QI 2 "general_operand" "dn")))]
3705 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3706 (xor:QI (match_dup 0)
3707 (match_operand:QI 1 "general_operand" "dn")))]
3712 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3713 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3718 ;; negation instructions
3720 (define_expand "negdi2"
3721 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3722 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3727 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3729 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3733 (define_insn "negdi2_internal"
3734 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
3735 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3739 if (which_alternative == 0)
3740 return \"neg%.l %0\;negx%.l %0\";
3741 if (GET_CODE (operands[0]) == REG)
3742 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3744 operands[1] = adjust_address (operands[0], SImode, 4);
3745 if (ADDRESS_REG_P (operands[0]))
3746 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3748 return \"neg%.l %1\;negx%.l %0\";
3751 (define_insn "negdi2_5200"
3752 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3753 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3757 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3758 return \"neg%.l %1\;negx%.l %0\";
3761 (define_expand "negsi2"
3762 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3763 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3768 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3770 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3774 (define_insn "negsi2_internal"
3775 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3776 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3780 (define_insn "negsi2_5200"
3781 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3782 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3786 (define_insn "neghi2"
3787 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3788 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3793 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3794 (neg:HI (match_dup 0)))]
3798 (define_insn "negqi2"
3799 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3800 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3805 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3806 (neg:QI (match_dup 0)))]
3810 ;; If using software floating point, just flip the sign bit.
3812 (define_expand "negsf2"
3813 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3814 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3823 target = operand_subword_force (operands[0], 0, SFmode);
3824 result = expand_binop (SImode, xor_optab,
3825 operand_subword_force (operands[1], 0, SFmode),
3826 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3830 if (result != target)
3831 emit_move_insn (result, target);
3833 /* Make a place for REG_EQUAL. */
3834 emit_move_insn (operands[0], operands[0]);
3840 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
3841 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3845 if (DATA_REG_P (operands[0]))
3847 operands[1] = GEN_INT (31);
3848 return \"bchg %1,%0\";
3850 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3851 return \"f%$neg%.x %1,%0\";
3852 return \"f%$neg%.s %f1,%0\";
3855 (define_expand "negdf2"
3856 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3857 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3868 target = operand_subword (operands[0], 0, 1, DFmode);
3869 result = expand_binop (SImode, xor_optab,
3870 operand_subword_force (operands[1], 0, DFmode),
3871 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3875 if (result != target)
3876 emit_move_insn (result, target);
3878 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3879 operand_subword_force (operands[1], 1, DFmode));
3881 insns = get_insns ();
3884 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3890 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
3891 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3895 if (DATA_REG_P (operands[0]))
3897 operands[1] = GEN_INT (31);
3898 return \"bchg %1,%0\";
3900 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3901 return \"f%&neg%.x %1,%0\";
3902 return \"f%&neg%.d %f1,%0\";
3905 ;; Sqrt instruction for the 68881
3907 (define_insn "sqrtsf2"
3908 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3909 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3913 if (FP_REG_P (operands[1]))
3914 return \"f%$sqrt%.x %1,%0\";
3916 return \"f%$sqrt%.s %1,%0\";
3919 (define_insn "sqrtdf2"
3920 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3921 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3925 if (FP_REG_P (operands[1]))
3926 return \"f%&sqrt%.x %1,%0\";
3928 return \"f%&sqrt%.d %1,%0\";
3931 ;; Absolute value instructions
3932 ;; If using software floating point, just zero the sign bit.
3934 (define_expand "abssf2"
3935 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3936 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3945 target = operand_subword_force (operands[0], 0, SFmode);
3946 result = expand_binop (SImode, and_optab,
3947 operand_subword_force (operands[1], 0, SFmode),
3948 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3952 if (result != target)
3953 emit_move_insn (result, target);
3955 /* Make a place for REG_EQUAL. */
3956 emit_move_insn (operands[0], operands[0]);
3962 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3963 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
3967 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3968 return \"f%$abs%.x %1,%0\";
3969 return \"f%$abs%.s %f1,%0\";
3972 (define_expand "absdf2"
3973 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3974 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3985 target = operand_subword (operands[0], 0, 1, DFmode);
3986 result = expand_binop (SImode, and_optab,
3987 operand_subword_force (operands[1], 0, DFmode),
3988 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3992 if (result != target)
3993 emit_move_insn (result, target);
3995 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3996 operand_subword_force (operands[1], 1, DFmode));
3998 insns = get_insns ();
4001 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4007 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
4008 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4012 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4013 return \"f%&abs%.x %1,%0\";
4014 return \"f%&abs%.d %f1,%0\";
4017 ;; one complement instructions
4019 ;; "one_cmpldi2" is mainly here to help combine().
4020 (define_insn "one_cmpldi2"
4021 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4022 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4027 if (GET_CODE (operands[0]) == REG)
4028 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4029 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4030 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4031 operands[1] = operands[0];
4033 operands[1] = adjust_address (operands[0], SImode, 4);
4034 return \"not%.l %1\;not%.l %0\";
4037 (define_expand "one_cmplsi2"
4038 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4039 (not:SI (match_operand:SI 1 "general_operand" "")))]
4044 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4046 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4050 (define_insn "one_cmplsi2_internal"
4051 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4052 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4056 (define_insn "one_cmplsi2_5200"
4057 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4058 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4062 (define_insn "one_cmplhi2"
4063 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4064 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4069 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4070 (not:HI (match_dup 0)))]
4074 (define_insn "one_cmplqi2"
4075 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4076 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4081 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4082 (not:QI (match_dup 0)))]
4086 ;; arithmetic shift instructions
4087 ;; We don't need the shift memory by 1 bit instruction
4089 (define_insn "ashldi_extsi"
4090 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4092 (match_operator:DI 2 "extend_operator"
4093 [(match_operand:SI 1 "general_operand" "rm")])
4099 if (GET_CODE (operands[0]) == REG)
4100 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4102 operands[2] = adjust_address (operands[0], SImode, 4);
4103 if (ADDRESS_REG_P (operands[0]))
4104 return \"move%.l %1,%0\;sub%.l %2,%2\";
4106 return \"move%.l %1,%0\;clr%.l %2\";
4109 (define_insn "ashldi_sexthi"
4110 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4111 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4113 (clobber (match_scratch:SI 2 "=a,X"))]
4118 if (GET_CODE (operands[0]) == MEM)
4120 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4121 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4122 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4123 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4126 operands[3] = adjust_address (operands[0], SImode, 4);
4127 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4130 else if (DATA_REG_P (operands[0]))
4131 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4133 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4136 (define_insn "ashldi_const32"
4137 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
4138 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4144 if (GET_CODE (operands[1]) == REG)
4145 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4147 operands[3] = adjust_address (operands[1], SImode, 4);
4148 if (GET_CODE (operands[0]) == REG)
4149 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4150 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4151 return \"clr%.l %0\;move%.l %3,%0\";
4152 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4153 return \"move%.l %3,%0\;clr%.l %0\";
4155 operands[2] = adjust_address (operands[0], SImode, 4);
4156 if (ADDRESS_REG_P (operands[2]))
4157 return \"move%.l %3,%0\;sub%.l %2,%2\";
4159 return \"move%.l %3,%0\;clr%.l %2\";
4162 ;; The predicate below must be general_operand, because ashldi3 allows that
4163 (define_insn "ashldi_const"
4164 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4165 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4166 (match_operand 2 "const_int_operand" "n")))]
4168 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4169 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4170 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4173 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4174 if (INTVAL (operands[2]) == 1)
4175 return \"add%.l %1,%1\;addx%.l %0,%0\";
4176 else if (INTVAL (operands[2]) == 8)
4177 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4178 else if (INTVAL (operands[2]) == 16)
4179 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4180 else if (INTVAL (operands[2]) == 48)
4181 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4182 else if (INTVAL (operands[2]) == 2)
4183 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4184 else if (INTVAL (operands[2]) == 3)
4185 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4186 else /* 32 < INTVAL (operands[2]) <= 63 */
4188 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4189 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4190 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4191 return \"mov%.l %1,%0\;moveq %#0,%1\";
4195 (define_expand "ashldi3"
4196 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4197 (ashift:DI (match_operand:DI 1 "general_operand" "")
4198 (match_operand 2 "const_int_operand" "")))]
4202 /* ??? This is a named pattern like this is not allowed to FAIL based
4204 if (GET_CODE (operands[2]) != CONST_INT
4205 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4206 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4207 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4211 ;; On most 68k models, this makes faster code in a special case.
4213 (define_insn "ashlsi_16"
4214 [(set (match_operand:SI 0 "register_operand" "=d")
4215 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4221 return \"swap %0\;clr%.w %0\";
4224 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4225 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4227 ;; On the 68000, this makes faster code in a special case.
4229 (define_insn "ashlsi_17_24"
4230 [(set (match_operand:SI 0 "register_operand" "=d")
4231 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4232 (match_operand:SI 2 "const_int_operand" "n")))]
4233 "(! TARGET_68020 && !TARGET_5200
4234 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4239 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4240 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4243 (define_insn "ashlsi3"
4244 [(set (match_operand:SI 0 "register_operand" "=d")
4245 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4246 (match_operand:SI 2 "general_operand" "dI")))]
4250 if (operands[2] == const1_rtx)
4252 cc_status.flags = CC_NO_OVERFLOW;
4253 return \"add%.l %0,%0\";
4255 return \"lsl%.l %2,%0\";
4258 (define_insn "ashlhi3"
4259 [(set (match_operand:HI 0 "register_operand" "=d")
4260 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4261 (match_operand:HI 2 "general_operand" "dI")))]
4266 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4267 (ashift:HI (match_dup 0)
4268 (match_operand:HI 1 "general_operand" "dI")))]
4272 (define_insn "ashlqi3"
4273 [(set (match_operand:QI 0 "register_operand" "=d")
4274 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4275 (match_operand:QI 2 "general_operand" "dI")))]
4280 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4281 (ashift:QI (match_dup 0)
4282 (match_operand:QI 1 "general_operand" "dI")))]
4286 ;; On most 68k models, this makes faster code in a special case.
4288 (define_insn "ashrsi_16"
4289 [(set (match_operand:SI 0 "register_operand" "=d")
4290 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4293 "swap %0\;ext%.l %0")
4295 ;; On the 68000, this makes faster code in a special case.
4298 [(set (match_operand:SI 0 "register_operand" "=d")
4299 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4300 (match_operand:SI 2 "const_int_operand" "n")))]
4301 "(! TARGET_68020 && !TARGET_5200
4302 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4305 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4306 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4309 (define_insn "subreghi1ashrdi_const32"
4310 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4311 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4312 (const_int 32)) 6))]
4316 if (GET_CODE (operands[1]) != REG)
4317 operands[1] = adjust_address (operands[1], HImode, 2);
4318 return \"move%.w %1,%0\";
4321 (define_insn "subregsi1ashrdi_const32"
4322 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4323 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4324 (const_int 32)) 4))]
4328 return \"move%.l %1,%0\";
4331 (define_insn "ashrdi_const32"
4332 [(set (match_operand:DI 0 "register_operand" "=d")
4333 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4339 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4341 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4343 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4346 (define_insn "ashrdi_const32_mem"
4347 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,<")
4348 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4350 (clobber (match_scratch:SI 2 "=d,d"))]
4355 if (which_alternative == 1)
4356 operands[3] = operands[0];
4358 operands[3] = adjust_address (operands[0], SImode, 4);
4360 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4362 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4365 ;; The predicate below must be general_operand, because ashrdi3 allows that
4366 (define_insn "ashrdi_const"
4367 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4368 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4369 (match_operand 2 "const_int_operand" "n")))]
4371 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4372 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4373 || INTVAL (operands[2]) == 31
4374 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4377 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4378 if (INTVAL (operands[2]) == 63)
4379 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4381 if (INTVAL (operands[2]) == 1)
4382 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4383 else if (INTVAL (operands[2]) == 8)
4384 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4385 else if (INTVAL (operands[2]) == 16)
4386 return \"move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1\";
4387 else if (INTVAL (operands[2]) == 48)
4388 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4389 else if (INTVAL (operands[2]) == 31)
4390 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4391 else if (INTVAL (operands[2]) == 2)
4392 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4393 else if (INTVAL (operands[2]) == 3)
4394 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4395 else /* 32 < INTVAL (operands[2]) <= 63 */
4397 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4398 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4399 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4400 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4401 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4402 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4406 (define_expand "ashrdi3"
4407 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4408 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4409 (match_operand 2 "const_int_operand" "")))]
4413 /* ??? This is a named pattern like this is not allowed to FAIL based
4415 if (GET_CODE (operands[2]) != CONST_INT
4416 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4417 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4418 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4422 ;; On all 68k models, this makes faster code in a special case.
4424 (define_insn "ashrsi_31"
4425 [(set (match_operand:SI 0 "register_operand" "=d")
4426 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4431 return \"add%.l %0,%0\;subx%.l %0,%0\";
4434 (define_insn "ashrsi3"
4435 [(set (match_operand:SI 0 "register_operand" "=d")
4436 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4437 (match_operand:SI 2 "general_operand" "dI")))]
4441 (define_insn "ashrhi3"
4442 [(set (match_operand:HI 0 "register_operand" "=d")
4443 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4444 (match_operand:HI 2 "general_operand" "dI")))]
4449 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4450 (ashiftrt:HI (match_dup 0)
4451 (match_operand:HI 1 "general_operand" "dI")))]
4455 (define_insn "ashrqi3"
4456 [(set (match_operand:QI 0 "register_operand" "=d")
4457 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4458 (match_operand:QI 2 "general_operand" "dI")))]
4463 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4464 (ashiftrt:QI (match_dup 0)
4465 (match_operand:QI 1 "general_operand" "dI")))]
4469 ;; logical shift instructions
4471 ;; commented out because of reload problems in 950612-1.c
4474 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4475 ;; (const_int 32)) 4))
4476 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4477 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4478 ;; (const_int 32)) 4))]
4482 ;; return \"move%.l %0,%1\";
4487 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4488 ;; (const_int 32)) 0))
4489 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4490 ;; (lshiftrt:DI (match_dup 0)
4491 ;; (const_int 32)))]
4495 ;; if (GET_CODE (operands[1]) == REG)
4496 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4498 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4499 ;; return \"move%.l %0,%2\;clr%.l %1\";
4502 (define_insn "subreg1lshrdi_const32"
4503 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4504 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4505 (const_int 32)) 4))]
4509 return \"move%.l %1,%0\";
4512 (define_insn "lshrdi_const32"
4513 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
4514 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4520 if (which_alternative == 1)
4521 return \"move%.l %1,%0\;clr%.l %0\";
4522 if (which_alternative == 2)
4523 return \"clr%.l %0\;move%.l %1,%0\";
4524 if (GET_CODE (operands[0]) == REG)
4525 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4527 operands[2] = adjust_address (operands[0], SImode, 4);
4528 if (GET_CODE (operands[1]) == REG)
4529 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4531 operands[3] = adjust_address (operands[1], SImode, 4);
4532 if (ADDRESS_REG_P (operands[0]))
4533 return \"move%.l %1,%2\;sub%.l %0,%0\";
4535 return \"move%.l %1,%2\;clr%.l %0\";
4538 ;; The predicate below must be general_operand, because lshrdi3 allows that
4539 (define_insn "lshrdi_const"
4540 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4541 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4542 (match_operand 2 "const_int_operand" "n")))]
4544 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4545 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4546 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4549 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4550 if (INTVAL (operands[2]) == 63)
4551 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4553 if (INTVAL (operands[2]) == 1)
4554 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4555 else if (INTVAL (operands[2]) == 8)
4556 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4557 else if (INTVAL (operands[2]) == 16)
4558 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4559 else if (INTVAL (operands[2]) == 48)
4560 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4561 else if (INTVAL (operands[2]) == 2)
4562 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4563 else if (INTVAL (operands[2]) == 3)
4564 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4565 else /* 32 < INTVAL (operands[2]) <= 63 */
4567 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4568 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4569 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4570 return \"mov%.l %0,%1\;moveq %#0,%0\";
4574 (define_expand "lshrdi3"
4575 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4576 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4577 (match_operand 2 "const_int_operand" "")))]
4581 /* ??? This is a named pattern like this is not allowed to FAIL based
4583 if (GET_CODE (operands[2]) != CONST_INT
4584 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4585 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4586 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4590 ;; On all 68k models, this makes faster code in a special case.
4592 (define_insn "lshrsi_31"
4593 [(set (match_operand:SI 0 "register_operand" "=d")
4594 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4599 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4602 ;; On most 68k models, this makes faster code in a special case.
4604 (define_insn "lshrsi_16"
4605 [(set (match_operand:SI 0 "register_operand" "=d")
4606 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4612 return \"clr%.w %0\;swap %0\";
4615 ;; On the 68000, this makes faster code in a special case.
4617 (define_insn "lshrsi_17_24"
4618 [(set (match_operand:SI 0 "register_operand" "=d")
4619 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4620 (match_operand:SI 2 "const_int_operand" "n")))]
4621 "(! TARGET_68020 && !TARGET_5200
4622 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4625 /* I think lsr%.w sets the CC properly. */
4626 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4627 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4630 (define_insn "lshrsi3"
4631 [(set (match_operand:SI 0 "register_operand" "=d")
4632 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4633 (match_operand:SI 2 "general_operand" "dI")))]
4637 (define_insn "lshrhi3"
4638 [(set (match_operand:HI 0 "register_operand" "=d")
4639 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4640 (match_operand:HI 2 "general_operand" "dI")))]
4645 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4646 (lshiftrt:HI (match_dup 0)
4647 (match_operand:HI 1 "general_operand" "dI")))]
4651 (define_insn "lshrqi3"
4652 [(set (match_operand:QI 0 "register_operand" "=d")
4653 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4654 (match_operand:QI 2 "general_operand" "dI")))]
4659 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4660 (lshiftrt:QI (match_dup 0)
4661 (match_operand:QI 1 "general_operand" "dI")))]
4665 ;; rotate instructions
4667 (define_insn "rotlsi3"
4668 [(set (match_operand:SI 0 "register_operand" "=d")
4669 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4670 (match_operand:SI 2 "general_operand" "dINO")))]
4674 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4676 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4678 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4679 return \"ror%.l %2,%0\";
4682 return \"rol%.l %2,%0\";
4685 (define_insn "rotlhi3"
4686 [(set (match_operand:HI 0 "register_operand" "=d")
4687 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4688 (match_operand:HI 2 "general_operand" "dIP")))]
4692 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4694 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4695 return \"ror%.w %2,%0\";
4698 return \"rol%.w %2,%0\";
4702 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4703 (rotate:HI (match_dup 0)
4704 (match_operand:HI 1 "general_operand" "dIP")))]
4708 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4710 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4711 return \"ror%.w %2,%0\";
4714 return \"rol%.w %2,%0\";
4717 (define_insn "rotlqi3"
4718 [(set (match_operand:QI 0 "register_operand" "=d")
4719 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4720 (match_operand:QI 2 "general_operand" "dI")))]
4724 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4726 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4727 return \"ror%.b %2,%0\";
4730 return \"rol%.b %2,%0\";
4734 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4735 (rotate:QI (match_dup 0)
4736 (match_operand:QI 1 "general_operand" "dI")))]
4740 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4742 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4743 return \"ror%.b %2,%0\";
4746 return \"rol%.b %2,%0\";
4749 (define_insn "rotrsi3"
4750 [(set (match_operand:SI 0 "register_operand" "=d")
4751 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4752 (match_operand:SI 2 "general_operand" "dI")))]
4756 (define_insn "rotrhi3"
4757 [(set (match_operand:HI 0 "register_operand" "=d")
4758 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4759 (match_operand:HI 2 "general_operand" "dI")))]
4764 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4765 (rotatert:HI (match_dup 0)
4766 (match_operand:HI 1 "general_operand" "dI")))]
4770 (define_insn "rotrqi3"
4771 [(set (match_operand:QI 0 "register_operand" "=d")
4772 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4773 (match_operand:QI 2 "general_operand" "dI")))]
4778 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4779 (rotatert:QI (match_dup 0)
4780 (match_operand:QI 1 "general_operand" "dI")))]
4785 ;; Bit set/clear in memory byte.
4787 ;; set bit, bit number is int
4788 (define_insn "bsetmemqi"
4789 [(set (match_operand:QI 0 "memory_operand" "+m")
4790 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4791 (match_operand:SI 1 "general_operand" "d")) 3)
4797 return \"bset %1,%0\";
4800 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4802 [(set (match_operand:QI 0 "memory_operand" "+m")
4803 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4804 (match_operator:SI 2 "extend_operator"
4805 [(match_operand 1 "general_operand" "d")])) 3)
4811 return \"bset %1,%0\";
4814 ;; clear bit, bit number is int
4815 (define_insn "bclrmemqi"
4816 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4818 (minus:SI (const_int 7)
4819 (match_operand:SI 1 "general_operand" "d")))
4825 return \"bclr %1,%0\";
4828 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4830 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4832 (minus:SI (const_int 7)
4833 (match_operator:SI 2 "extend_operator"
4834 [(match_operand 1 "general_operand" "d")])))
4840 return \"bclr %1,%0\";
4843 ;; Special cases of bit-field insns which we should
4844 ;; recognize in preference to the general case.
4845 ;; These handle aligned 8-bit and 16-bit fields,
4846 ;; which can usually be done with move instructions.
4849 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4850 ; alignment of structure members is specified.
4852 ; The move is allowed to be odd byte aligned, because that's still faster
4853 ; than an odd byte aligned bit field instruction.
4856 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4858 (match_operand:SI 1 "const_int_operand" "n"))
4859 (match_operand:SI 2 "general_src_operand" "rmSi"))]
4860 "TARGET_68020 && TARGET_BITFIELD
4861 && (INTVAL (operands[1]) % 8) == 0
4862 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4866 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
4868 return \"move%.l %2,%0\";
4872 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4873 (match_operand:SI 1 "const_int_operand" "n")
4874 (match_operand:SI 2 "const_int_operand" "n"))
4875 (match_operand:SI 3 "register_operand" "d"))]
4876 "TARGET_68020 && TARGET_BITFIELD
4877 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4878 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4879 && (GET_CODE (operands[0]) == REG
4880 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4883 if (REG_P (operands[0]))
4885 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4886 return \"bfins %3,%0{%b2:%b1}\";
4889 operands[0] = adjust_address (operands[0],
4890 INTVAL (operands[1]) == 8 ? QImode : HImode,
4891 INTVAL (operands[2]) / 8);
4893 if (GET_CODE (operands[3]) == MEM)
4894 operands[3] = adjust_address (operands[3],
4895 INTVAL (operands[1]) == 8 ? QImode : HImode,
4896 (32 - INTVAL (operands[1])) / 8);
4898 if (INTVAL (operands[1]) == 8)
4899 return \"move%.b %3,%0\";
4900 return \"move%.w %3,%0\";
4905 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4906 ; alignment of structure members is specified.
4908 ; The move is allowed to be odd byte aligned, because that's still faster
4909 ; than an odd byte aligned bit field instruction.
4912 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4913 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4915 (match_operand:SI 2 "const_int_operand" "n")))]
4916 "TARGET_68020 && TARGET_BITFIELD
4917 && (INTVAL (operands[2]) % 8) == 0
4918 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4922 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4924 return \"move%.l %1,%0\";
4928 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
4929 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4930 (match_operand:SI 2 "const_int_operand" "n")
4931 (match_operand:SI 3 "const_int_operand" "n")))]
4932 "TARGET_68020 && TARGET_BITFIELD
4933 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4934 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4935 && (GET_CODE (operands[1]) == REG
4936 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4939 cc_status.flags |= CC_NOT_NEGATIVE;
4940 if (REG_P (operands[1]))
4942 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4943 return \"bfextu %1{%b3:%b2},%0\";
4947 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
4949 output_asm_insn (\"clr%.l %0\", operands);
4950 if (GET_CODE (operands[0]) == MEM)
4951 operands[0] = adjust_address (operands[0],
4952 INTVAL (operands[2]) == 8 ? QImode : HImode,
4953 (32 - INTVAL (operands[1])) / 8);
4955 if (INTVAL (operands[2]) == 8)
4956 return \"move%.b %1,%0\";
4957 return \"move%.w %1,%0\";
4961 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4962 ; alignment of structure members is specified.
4964 ; The move is allowed to be odd byte aligned, because that's still faster
4965 ; than an odd byte aligned bit field instruction.
4968 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4969 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4971 (match_operand:SI 2 "const_int_operand" "n")))]
4972 "TARGET_68020 && TARGET_BITFIELD
4973 && (INTVAL (operands[2]) % 8) == 0
4974 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4978 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4980 return \"move%.l %1,%0\";
4984 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4985 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4986 (match_operand:SI 2 "const_int_operand" "n")
4987 (match_operand:SI 3 "const_int_operand" "n")))]
4988 "TARGET_68020 && TARGET_BITFIELD
4989 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4990 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4991 && (GET_CODE (operands[1]) == REG
4992 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4995 if (REG_P (operands[1]))
4997 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4998 return \"bfexts %1{%b3:%b2},%0\";
5002 = adjust_address (operands[1],
5003 INTVAL (operands[2]) == 8 ? QImode : HImode,
5004 INTVAL (operands[3]) / 8);
5006 if (INTVAL (operands[2]) == 8)
5007 return \"move%.b %1,%0\;extb%.l %0\";
5008 return \"move%.w %1,%0\;ext%.l %0\";
5011 ;; Bit field instructions, general cases.
5012 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5013 ;; so that its address is reloaded.
5015 (define_expand "extv"
5016 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5017 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5018 (match_operand:SI 2 "general_operand" "")
5019 (match_operand:SI 3 "general_operand" "")))]
5020 "TARGET_68020 && TARGET_BITFIELD"
5024 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5025 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5026 (match_operand:SI 2 "general_operand" "di")
5027 (match_operand:SI 3 "general_operand" "di")))]
5028 "TARGET_68020 && TARGET_BITFIELD"
5029 "bfexts %1{%b3:%b2},%0")
5031 (define_expand "extzv"
5032 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5033 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5034 (match_operand:SI 2 "general_operand" "")
5035 (match_operand:SI 3 "general_operand" "")))]
5036 "TARGET_68020 && TARGET_BITFIELD"
5040 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
5041 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5042 (match_operand:SI 2 "general_operand" "di,di")
5043 (match_operand:SI 3 "general_operand" "di,di")))]
5044 "TARGET_68020 && TARGET_BITFIELD"
5047 if (GET_CODE (operands[2]) == CONST_INT)
5049 if (INTVAL (operands[2]) != 32)
5050 cc_status.flags |= CC_NOT_NEGATIVE;
5056 return \"bfextu %1{%b3:%b2},%0\";
5060 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5061 (match_operand:SI 1 "general_operand" "di")
5062 (match_operand:SI 2 "general_operand" "di"))
5063 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5064 (match_operand 3 "const_int_operand" "n")))]
5065 "TARGET_68020 && TARGET_BITFIELD
5066 && (INTVAL (operands[3]) == -1
5067 || (GET_CODE (operands[1]) == CONST_INT
5068 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5072 return \"bfchg %0{%b2:%b1}\";
5076 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5077 (match_operand:SI 1 "general_operand" "di")
5078 (match_operand:SI 2 "general_operand" "di"))
5080 "TARGET_68020 && TARGET_BITFIELD"
5084 return \"bfclr %0{%b2:%b1}\";
5088 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5089 (match_operand:SI 1 "general_operand" "di")
5090 (match_operand:SI 2 "general_operand" "di"))
5092 "TARGET_68020 && TARGET_BITFIELD"
5096 return \"bfset %0{%b2:%b1}\";
5099 (define_expand "insv"
5100 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5101 (match_operand:SI 1 "general_operand" "")
5102 (match_operand:SI 2 "general_operand" ""))
5103 (match_operand:SI 3 "register_operand" ""))]
5104 "TARGET_68020 && TARGET_BITFIELD"
5108 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5109 (match_operand:SI 1 "general_operand" "di")
5110 (match_operand:SI 2 "general_operand" "di"))
5111 (match_operand:SI 3 "register_operand" "d"))]
5112 "TARGET_68020 && TARGET_BITFIELD"
5113 "bfins %3,%0{%b2:%b1}")
5115 ;; Now recognize bit field insns that operate on registers
5116 ;; (or at least were intended to do so).
5119 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5120 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5121 (match_operand:SI 2 "general_operand" "di")
5122 (match_operand:SI 3 "general_operand" "di")))]
5123 "TARGET_68020 && TARGET_BITFIELD"
5124 "bfexts %1{%b3:%b2},%0")
5127 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5128 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5129 (match_operand:SI 2 "general_operand" "di")
5130 (match_operand:SI 3 "general_operand" "di")))]
5131 "TARGET_68020 && TARGET_BITFIELD"
5134 if (GET_CODE (operands[2]) == CONST_INT)
5136 if (INTVAL (operands[2]) != 32)
5137 cc_status.flags |= CC_NOT_NEGATIVE;
5143 return \"bfextu %1{%b3:%b2},%0\";
5147 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5148 (match_operand:SI 1 "general_operand" "di")
5149 (match_operand:SI 2 "general_operand" "di"))
5151 "TARGET_68020 && TARGET_BITFIELD"
5155 return \"bfclr %0{%b2:%b1}\";
5159 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5160 (match_operand:SI 1 "general_operand" "di")
5161 (match_operand:SI 2 "general_operand" "di"))
5163 "TARGET_68020 && TARGET_BITFIELD"
5167 return \"bfset %0{%b2:%b1}\";
5171 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5172 (match_operand:SI 1 "general_operand" "di")
5173 (match_operand:SI 2 "general_operand" "di"))
5174 (match_operand:SI 3 "register_operand" "d"))]
5175 "TARGET_68020 && TARGET_BITFIELD"
5179 /* These special cases are now recognized by a specific pattern. */
5180 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5181 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5182 return \"move%.w %3,%0\";
5183 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5184 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5185 return \"move%.b %3,%0\";
5187 return \"bfins %3,%0{%b2:%b1}\";
5190 ;; Special patterns for optimizing bit-field instructions.
5194 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5195 (match_operand:SI 1 "const_int_operand" "n")
5196 (match_operand:SI 2 "general_operand" "di")))]
5197 "TARGET_68020 && TARGET_BITFIELD"
5200 if (operands[1] == const1_rtx
5201 && GET_CODE (operands[2]) == CONST_INT)
5203 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5204 return output_btst (operands,
5205 GEN_INT (width - INTVAL (operands[2])),
5206 operands[0], insn, 1000);
5207 /* Pass 1000 as SIGNPOS argument so that btst will
5208 not think we are testing the sign bit for an `and'
5209 and assume that nonzero implies a negative result. */
5211 if (INTVAL (operands[1]) != 32)
5212 cc_status.flags = CC_NOT_NEGATIVE;
5213 return \"bftst %0{%b2:%b1}\";
5217 ;;; now handle the register cases
5220 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5221 (match_operand:SI 1 "const_int_operand" "n")
5222 (match_operand:SI 2 "general_operand" "di")))]
5223 "TARGET_68020 && TARGET_BITFIELD"
5226 if (operands[1] == const1_rtx
5227 && GET_CODE (operands[2]) == CONST_INT)
5229 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5230 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5231 operands[0], insn, 1000);
5232 /* Pass 1000 as SIGNPOS argument so that btst will
5233 not think we are testing the sign bit for an `and'
5234 and assume that nonzero implies a negative result. */
5236 if (INTVAL (operands[1]) != 32)
5237 cc_status.flags = CC_NOT_NEGATIVE;
5238 return \"bftst %0{%b2:%b1}\";
5241 (define_insn "scc0_di"
5242 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5243 (match_operator 1 "valid_dbcc_comparison_p"
5244 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5248 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5251 (define_insn "scc0_di_5200"
5252 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5253 (match_operator 1 "valid_dbcc_comparison_p"
5254 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5258 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5261 (define_insn "scc_di"
5262 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5263 (match_operator 1 "valid_dbcc_comparison_p"
5264 [(match_operand:DI 2 "general_operand" "ro,r")
5265 (match_operand:DI 3 "general_operand" "r,ro")]))]
5269 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5272 (define_insn "scc_di_5200"
5273 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5274 (match_operator 1 "valid_dbcc_comparison_p"
5275 [(match_operand:DI 2 "general_operand" "ro,r")
5276 (match_operand:DI 3 "general_operand" "r,ro")]))]
5280 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5283 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5284 ;; memory, but we cannot allow it to be in memory in case the address
5285 ;; needs to be reloaded.
5287 (define_expand "seq"
5288 [(set (match_operand:QI 0 "register_operand" "")
5289 (eq:QI (cc0) (const_int 0)))]
5293 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5295 m68k_last_compare_had_fp_operands = 0;
5301 [(set (match_operand:QI 0 "register_operand" "=d")
5302 (eq:QI (cc0) (const_int 0)))]
5305 cc_status = cc_prev_status;
5306 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5309 (define_expand "sne"
5310 [(set (match_operand:QI 0 "register_operand" "")
5311 (ne:QI (cc0) (const_int 0)))]
5315 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5317 m68k_last_compare_had_fp_operands = 0;
5323 [(set (match_operand:QI 0 "register_operand" "=d")
5324 (ne:QI (cc0) (const_int 0)))]
5327 cc_status = cc_prev_status;
5328 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5331 (define_expand "sgt"
5332 [(set (match_operand:QI 0 "register_operand" "")
5333 (gt:QI (cc0) (const_int 0)))]
5337 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5339 m68k_last_compare_had_fp_operands = 0;
5345 [(set (match_operand:QI 0 "register_operand" "=d")
5346 (gt:QI (cc0) (const_int 0)))]
5349 cc_status = cc_prev_status;
5350 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5353 (define_expand "sgtu"
5354 [(set (match_operand:QI 0 "register_operand" "")
5355 (gtu:QI (cc0) (const_int 0)))]
5360 [(set (match_operand:QI 0 "register_operand" "=d")
5361 (gtu:QI (cc0) (const_int 0)))]
5364 cc_status = cc_prev_status;
5365 return \"shi %0\"; ")
5367 (define_expand "slt"
5368 [(set (match_operand:QI 0 "register_operand" "")
5369 (lt:QI (cc0) (const_int 0)))]
5373 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5375 m68k_last_compare_had_fp_operands = 0;
5381 [(set (match_operand:QI 0 "register_operand" "=d")
5382 (lt:QI (cc0) (const_int 0)))]
5385 cc_status = cc_prev_status;
5386 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5388 (define_expand "sltu"
5389 [(set (match_operand:QI 0 "register_operand" "")
5390 (ltu:QI (cc0) (const_int 0)))]
5395 [(set (match_operand:QI 0 "register_operand" "=d")
5396 (ltu:QI (cc0) (const_int 0)))]
5399 cc_status = cc_prev_status;
5400 return \"scs %0\"; ")
5402 (define_expand "sge"
5403 [(set (match_operand:QI 0 "register_operand" "")
5404 (ge:QI (cc0) (const_int 0)))]
5408 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5410 m68k_last_compare_had_fp_operands = 0;
5416 [(set (match_operand:QI 0 "register_operand" "=d")
5417 (ge:QI (cc0) (const_int 0)))]
5420 cc_status = cc_prev_status;
5421 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5423 (define_expand "sgeu"
5424 [(set (match_operand:QI 0 "register_operand" "")
5425 (geu:QI (cc0) (const_int 0)))]
5430 [(set (match_operand:QI 0 "register_operand" "=d")
5431 (geu:QI (cc0) (const_int 0)))]
5434 cc_status = cc_prev_status;
5435 return \"scc %0\"; ")
5437 (define_expand "sle"
5438 [(set (match_operand:QI 0 "register_operand" "")
5439 (le:QI (cc0) (const_int 0)))]
5443 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5445 m68k_last_compare_had_fp_operands = 0;
5451 [(set (match_operand:QI 0 "register_operand" "=d")
5452 (le:QI (cc0) (const_int 0)))]
5455 cc_status = cc_prev_status;
5456 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5459 (define_expand "sleu"
5460 [(set (match_operand:QI 0 "register_operand" "")
5461 (leu:QI (cc0) (const_int 0)))]
5466 [(set (match_operand:QI 0 "register_operand" "=d")
5467 (leu:QI (cc0) (const_int 0)))]
5470 cc_status = cc_prev_status;
5471 return \"sls %0\"; ")
5473 (define_expand "sordered"
5474 [(set (match_operand:QI 0 "register_operand" "")
5475 (ordered:QI (cc0) (const_int 0)))]
5476 "TARGET_68881 && !TARGET_68060"
5478 if (! m68k_last_compare_had_fp_operands)
5480 m68k_last_compare_had_fp_operands = 0;
5483 (define_insn "*sordered_1"
5484 [(set (match_operand:QI 0 "register_operand" "=d")
5485 (ordered:QI (cc0) (const_int 0)))]
5486 "TARGET_68881 && !TARGET_68060"
5488 cc_status = cc_prev_status;
5492 (define_expand "sunordered"
5493 [(set (match_operand:QI 0 "register_operand" "")
5494 (unordered:QI (cc0) (const_int 0)))]
5495 "TARGET_68881 && !TARGET_68060"
5497 if (! m68k_last_compare_had_fp_operands)
5499 m68k_last_compare_had_fp_operands = 0;
5502 (define_insn "*sunordered_1"
5503 [(set (match_operand:QI 0 "register_operand" "=d")
5504 (unordered:QI (cc0) (const_int 0)))]
5505 "TARGET_68881 && !TARGET_68060"
5507 cc_status = cc_prev_status;
5511 (define_expand "suneq"
5512 [(set (match_operand:QI 0 "register_operand" "")
5513 (uneq:QI (cc0) (const_int 0)))]
5514 "TARGET_68881 && !TARGET_68060"
5516 if (! m68k_last_compare_had_fp_operands)
5518 m68k_last_compare_had_fp_operands = 0;
5521 (define_insn "*suneq_1"
5522 [(set (match_operand:QI 0 "register_operand" "=d")
5523 (uneq:QI (cc0) (const_int 0)))]
5524 "TARGET_68881 && !TARGET_68060"
5526 cc_status = cc_prev_status;
5530 (define_expand "sunge"
5531 [(set (match_operand:QI 0 "register_operand" "")
5532 (unge:QI (cc0) (const_int 0)))]
5533 "TARGET_68881 && !TARGET_68060"
5535 if (! m68k_last_compare_had_fp_operands)
5537 m68k_last_compare_had_fp_operands = 0;
5540 (define_insn "*sunge_1"
5541 [(set (match_operand:QI 0 "register_operand" "=d")
5542 (unge:QI (cc0) (const_int 0)))]
5543 "TARGET_68881 && !TARGET_68060"
5545 cc_status = cc_prev_status;
5549 (define_expand "sungt"
5550 [(set (match_operand:QI 0 "register_operand" "")
5551 (ungt:QI (cc0) (const_int 0)))]
5552 "TARGET_68881 && !TARGET_68060"
5554 if (! m68k_last_compare_had_fp_operands)
5556 m68k_last_compare_had_fp_operands = 0;
5559 (define_insn "*sungt_1"
5560 [(set (match_operand:QI 0 "register_operand" "=d")
5561 (ungt:QI (cc0) (const_int 0)))]
5562 "TARGET_68881 && !TARGET_68060"
5564 cc_status = cc_prev_status;
5568 (define_expand "sunle"
5569 [(set (match_operand:QI 0 "register_operand" "")
5570 (unle:QI (cc0) (const_int 0)))]
5571 "TARGET_68881 && !TARGET_68060"
5573 if (! m68k_last_compare_had_fp_operands)
5575 m68k_last_compare_had_fp_operands = 0;
5578 (define_insn "*sunle_1"
5579 [(set (match_operand:QI 0 "register_operand" "=d")
5580 (unle:QI (cc0) (const_int 0)))]
5581 "TARGET_68881 && !TARGET_68060"
5583 cc_status = cc_prev_status;
5587 (define_expand "sunlt"
5588 [(set (match_operand:QI 0 "register_operand" "")
5589 (unlt:QI (cc0) (const_int 0)))]
5590 "TARGET_68881 && !TARGET_68060"
5592 if (! m68k_last_compare_had_fp_operands)
5594 m68k_last_compare_had_fp_operands = 0;
5597 (define_insn "*sunlt_1"
5598 [(set (match_operand:QI 0 "register_operand" "=d")
5599 (unlt:QI (cc0) (const_int 0)))]
5600 "TARGET_68881 && !TARGET_68060"
5602 cc_status = cc_prev_status;
5606 (define_expand "sltgt"
5607 [(set (match_operand:QI 0 "register_operand" "")
5608 (ltgt:QI (cc0) (const_int 0)))]
5609 "TARGET_68881 && !TARGET_68060"
5611 if (! m68k_last_compare_had_fp_operands)
5613 m68k_last_compare_had_fp_operands = 0;
5616 (define_insn "*sltgt_1"
5617 [(set (match_operand:QI 0 "register_operand" "=d")
5618 (ltgt:QI (cc0) (const_int 0)))]
5619 "TARGET_68881 && !TARGET_68060"
5621 cc_status = cc_prev_status;
5625 (define_insn "*fsogt_1"
5626 [(set (match_operand:QI 0 "register_operand" "=d")
5627 (not:QI (unle:QI (cc0) (const_int 0))))]
5628 "TARGET_68881 && !TARGET_68060"
5630 cc_status = cc_prev_status;
5634 (define_insn "*fsoge_1"
5635 [(set (match_operand:QI 0 "register_operand" "=d")
5636 (not:QI (unlt:QI (cc0) (const_int 0))))]
5637 "TARGET_68881 && !TARGET_68060"
5639 cc_status = cc_prev_status;
5643 (define_insn "*fsolt_1"
5644 [(set (match_operand:QI 0 "register_operand" "=d")
5645 (not:QI (unge:QI (cc0) (const_int 0))))]
5646 "TARGET_68881 && !TARGET_68060"
5648 cc_status = cc_prev_status;
5652 (define_insn "*fsole_1"
5653 [(set (match_operand:QI 0 "register_operand" "=d")
5654 (not:QI (ungt:QI (cc0) (const_int 0))))]
5655 "TARGET_68881 && !TARGET_68060"
5657 cc_status = cc_prev_status;
5661 ;; Basic conditional jump instructions.
5663 (define_insn "beq0_di"
5665 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5667 (label_ref (match_operand 1 "" ","))
5669 (clobber (match_scratch:SI 2 "=d,d"))]
5674 if (which_alternative == 1)
5676 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5678 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5680 if ((cc_prev_status.value1
5681 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5682 || (cc_prev_status.value2
5683 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5685 cc_status = cc_prev_status;
5687 return \"jbeq %l1\";
5692 if (GET_CODE (operands[0]) == REG)
5693 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5695 operands[3] = adjust_address (operands[0], SImode, 4);
5696 if (! ADDRESS_REG_P (operands[0]))
5698 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5700 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5703 return \"or%.l %0,%2\;jbeq %l1\";
5705 return \"or%.l %0,%2\;jeq %l1\";
5711 return \"or%.l %3,%2\;jbeq %l1\";
5713 return \"or%.l %3,%2\;jeq %l1\";
5718 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5720 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5723 operands[4] = gen_label_rtx();
5724 if (TARGET_68020 || TARGET_5200)
5727 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5729 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5735 #ifdef SGS_CMP_ORDER
5736 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5738 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5741 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5744 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5745 CODE_LABEL_NUMBER (operands[4]));
5749 (define_insn "bne0_di"
5751 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5753 (label_ref (match_operand 1 "" ","))
5755 (clobber (match_scratch:SI 2 "=d,X"))]
5759 if ((cc_prev_status.value1
5760 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5761 || (cc_prev_status.value2
5762 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5764 cc_status = cc_prev_status;
5766 return \"jbne %l1\";
5772 if (GET_CODE (operands[0]) == REG)
5773 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5775 operands[3] = adjust_address (operands[0], SImode, 4);
5776 if (!ADDRESS_REG_P (operands[0]))
5778 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5780 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5783 return \"or%.l %0,%2\;jbne %l1\";
5785 return \"or%.l %0,%2\;jne %l1\";
5791 return \"or%.l %3,%2\;jbne %l1\";
5793 return \"or%.l %3,%2\;jne %l1\";
5798 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5800 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5803 if (TARGET_68020 || TARGET_5200)
5806 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5808 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5814 #ifdef SGS_CMP_ORDER
5815 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5817 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5820 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5825 (define_insn "bge0_di"
5827 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5829 (label_ref (match_operand 1 "" ""))
5834 if ((cc_prev_status.value1
5835 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5836 || (cc_prev_status.value2
5837 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5839 cc_status = cc_prev_status;
5840 if (cc_status.flags & CC_REVERSED)
5843 return \"jble %l1\";
5851 return \"jbpl %l1\";
5858 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5859 output_asm_insn(\"tst%.l %0\", operands);
5862 /* On an address reg, cmpw may replace cmpl. */
5863 #ifdef SGS_CMP_ORDER
5864 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5866 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5871 return \"jbpl %l1\";
5877 (define_insn "blt0_di"
5879 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5881 (label_ref (match_operand 1 "" ""))
5886 if ((cc_prev_status.value1
5887 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5888 || (cc_prev_status.value2
5889 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5891 cc_status = cc_prev_status;
5892 if (cc_status.flags & CC_REVERSED)
5895 return \"jbgt %l1\";
5903 return \"jbmi %l1\";
5910 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5911 output_asm_insn(\"tst%.l %0\", operands);
5914 /* On an address reg, cmpw may replace cmpl. */
5915 #ifdef SGS_CMP_ORDER
5916 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5918 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5923 return \"jbmi %l1\";
5931 (if_then_else (eq (cc0)
5933 (label_ref (match_operand 0 "" ""))
5939 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5941 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5947 (if_then_else (ne (cc0)
5949 (label_ref (match_operand 0 "" ""))
5955 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5957 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5963 (if_then_else (gt (cc0)
5965 (label_ref (match_operand 0 "" ""))
5970 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5972 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5978 (if_then_else (gtu (cc0)
5980 (label_ref (match_operand 0 "" ""))
5985 return \"jbhi %l0\";
5993 (if_then_else (lt (cc0)
5995 (label_ref (match_operand 0 "" ""))
6000 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6002 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6008 (if_then_else (ltu (cc0)
6010 (label_ref (match_operand 0 "" ""))
6015 return \"jbcs %l0\";
6023 (if_then_else (ge (cc0)
6025 (label_ref (match_operand 0 "" ""))
6030 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6032 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6038 (if_then_else (geu (cc0)
6040 (label_ref (match_operand 0 "" ""))
6045 return \"jbcc %l0\";
6053 (if_then_else (le (cc0)
6055 (label_ref (match_operand 0 "" ""))
6060 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6062 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6068 (if_then_else (leu (cc0)
6070 (label_ref (match_operand 0 "" ""))
6075 return \"jbls %l0\";
6081 (define_insn "bordered"
6083 (if_then_else (ordered (cc0) (const_int 0))
6084 (label_ref (match_operand 0 "" ""))
6088 if (!(cc_prev_status.flags & CC_IN_68881))
6097 (define_insn "bunordered"
6099 (if_then_else (unordered (cc0) (const_int 0))
6100 (label_ref (match_operand 0 "" ""))
6104 if (!(cc_prev_status.flags & CC_IN_68881))
6113 (define_insn "buneq"
6115 (if_then_else (uneq (cc0) (const_int 0))
6116 (label_ref (match_operand 0 "" ""))
6120 if (!(cc_prev_status.flags & CC_IN_68881))
6129 (define_insn "bunge"
6131 (if_then_else (unge (cc0) (const_int 0))
6132 (label_ref (match_operand 0 "" ""))
6136 if (!(cc_prev_status.flags & CC_IN_68881))
6145 (define_insn "bungt"
6147 (if_then_else (ungt (cc0) (const_int 0))
6148 (label_ref (match_operand 0 "" ""))
6152 if (!(cc_prev_status.flags & CC_IN_68881))
6161 (define_insn "bunle"
6163 (if_then_else (unle (cc0) (const_int 0))
6164 (label_ref (match_operand 0 "" ""))
6168 if (!(cc_prev_status.flags & CC_IN_68881))
6177 (define_insn "bunlt"
6179 (if_then_else (unlt (cc0) (const_int 0))
6180 (label_ref (match_operand 0 "" ""))
6184 if (!(cc_prev_status.flags & CC_IN_68881))
6193 (define_insn "bltgt"
6195 (if_then_else (ltgt (cc0) (const_int 0))
6196 (label_ref (match_operand 0 "" ""))
6200 if (!(cc_prev_status.flags & CC_IN_68881))
6209 ;; Negated conditional jump instructions.
6213 (if_then_else (eq (cc0)
6216 (label_ref (match_operand 0 "" ""))))]
6221 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6223 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6229 (if_then_else (ne (cc0)
6232 (label_ref (match_operand 0 "" ""))))]
6237 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6239 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6245 (if_then_else (gt (cc0)
6248 (label_ref (match_operand 0 "" ""))))]
6252 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6254 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6260 (if_then_else (gtu (cc0)
6263 (label_ref (match_operand 0 "" ""))))]
6267 return \"jbls %l0\";
6275 (if_then_else (lt (cc0)
6278 (label_ref (match_operand 0 "" ""))))]
6282 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6284 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6290 (if_then_else (ltu (cc0)
6293 (label_ref (match_operand 0 "" ""))))]
6297 return \"jbcc %l0\";
6305 (if_then_else (ge (cc0)
6308 (label_ref (match_operand 0 "" ""))))]
6312 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6314 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6320 (if_then_else (geu (cc0)
6323 (label_ref (match_operand 0 "" ""))))]
6327 return \"jbcs %l0\";
6335 (if_then_else (le (cc0)
6338 (label_ref (match_operand 0 "" ""))))]
6342 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6344 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6350 (if_then_else (leu (cc0)
6353 (label_ref (match_operand 0 "" ""))))]
6357 return \"jbhi %l0\";
6363 (define_insn "*bordered_rev"
6365 (if_then_else (ordered (cc0) (const_int 0))
6367 (label_ref (match_operand 0 "" ""))))]
6370 if (!(cc_prev_status.flags & CC_IN_68881))
6379 (define_insn "*bunordered_rev"
6381 (if_then_else (unordered (cc0) (const_int 0))
6383 (label_ref (match_operand 0 "" ""))))]
6386 if (!(cc_prev_status.flags & CC_IN_68881))
6395 (define_insn "*buneq_rev"
6397 (if_then_else (uneq (cc0) (const_int 0))
6399 (label_ref (match_operand 0 "" ""))))]
6402 if (!(cc_prev_status.flags & CC_IN_68881))
6411 (define_insn "*bunge_rev"
6413 (if_then_else (unge (cc0) (const_int 0))
6415 (label_ref (match_operand 0 "" ""))))]
6418 if (!(cc_prev_status.flags & CC_IN_68881))
6427 (define_insn "*bunle_rev"
6429 (if_then_else (unle (cc0) (const_int 0))
6431 (label_ref (match_operand 0 "" ""))))]
6434 if (!(cc_prev_status.flags & CC_IN_68881))
6443 (define_insn "*bunlt_rev"
6445 (if_then_else (unlt (cc0) (const_int 0))
6447 (label_ref (match_operand 0 "" ""))))]
6450 if (!(cc_prev_status.flags & CC_IN_68881))
6459 (define_insn "*bltgt_rev"
6461 (if_then_else (ltgt (cc0) (const_int 0))
6463 (label_ref (match_operand 0 "" ""))))]
6466 if (!(cc_prev_status.flags & CC_IN_68881))
6475 ;; Unconditional and other jump instructions
6478 (label_ref (match_operand 0 "" "")))]
6482 return \"jbra %l0\";
6488 ;; We support two different ways of handling dispatch tables.
6489 ;; The NeXT uses absolute tables, and other machines use relative.
6490 ;; This define_expand can generate either kind.
6491 (define_expand "tablejump"
6492 [(parallel [(set (pc) (match_operand 0 "" ""))
6493 (use (label_ref (match_operand 1 "" "")))])]
6497 #ifdef CASE_VECTOR_PC_RELATIVE
6498 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6499 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6503 ;; Jump to variable address from dispatch table of absolute addresses.
6505 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6506 (use (label_ref (match_operand 1 "" "")))]
6510 return \"jmp (%0)\";
6516 ;; Jump to variable address from dispatch table of relative addresses.
6520 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6521 (use (label_ref (match_operand 1 "" "")))]
6524 #ifdef ASM_RETURN_CASE_JUMP
6525 ASM_RETURN_CASE_JUMP;
6528 #ifdef ASM_OUTPUT_CASE_LABEL
6531 if (ADDRESS_REG_P (operands[0]))
6532 return \"jmp 6(%%pc,%0.l)\";
6534 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6537 return \"jmp 6(%%pc,%0.w)\";
6541 if (ADDRESS_REG_P (operands[0]))
6542 return \"jmp 2(%%pc,%0.l)\";
6544 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6547 return \"jmp 2(%%pc,%0.w)\";
6552 if (ADDRESS_REG_P (operands[0]))
6555 return \"jmp (2,pc,%0.l)\";
6557 return \"jmp pc@(2,%0:l)\";
6563 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6565 return \"extl %0\;jmp pc@(2,%0:l)\";
6572 return \"jmp (2,pc,%0.w)\";
6574 return \"jmp pc@(2,%0:w)\";
6581 ;; Decrement-and-branch insns.
6585 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6587 (label_ref (match_operand 1 "" ""))
6590 (plus:HI (match_dup 0)
6596 if (DATA_REG_P (operands[0]))
6597 return \"dbra %0,%l1\";
6598 if (GET_CODE (operands[0]) == MEM)
6602 return \"sub%.w %#1,%0\;jbcc %l1\";
6604 return \"subq%.w %#1,%0\;jbcc %l1\";
6606 #else /* not MOTOROLA */
6607 return \"subqw %#1,%0\;jcc %l1\";
6611 #ifdef SGS_CMP_ORDER
6613 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6615 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6617 #else /* not SGS_CMP_ORDER */
6618 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6620 #else /* not MOTOROLA */
6621 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6628 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6630 (label_ref (match_operand 1 "" ""))
6633 (plus:SI (match_dup 0)
6641 if (DATA_REG_P (operands[0]))
6642 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6643 if (GET_CODE (operands[0]) == MEM)
6644 return \"sub%.l %#1,%0\;jbcc %l1\";
6646 if (DATA_REG_P (operands[0]))
6647 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6648 if (GET_CODE (operands[0]) == MEM)
6649 return \"subq%.l %#1,%0\;jbcc %l1\";
6650 #endif /* NO_ADDSUB_Q */
6651 #ifdef SGS_CMP_ORDER
6653 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6655 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6657 #else /* not SGS_CMP_ORDER */
6658 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6659 #endif /* not SGS_CMP_ORDER */
6660 #else /* not MOTOROLA */
6661 if (DATA_REG_P (operands[0]))
6662 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6663 if (GET_CODE (operands[0]) == MEM)
6664 return \"subql %#1,%0\;jcc %l1\";
6665 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6666 #endif /* not MOTOROLA */
6669 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6674 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6677 (label_ref (match_operand 1 "" ""))
6680 (plus:HI (match_dup 0)
6682 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6688 if (DATA_REG_P (operands[0]))
6689 return \"dbra %0,%l1\";
6690 if (GET_CODE (operands[0]) == MEM)
6691 return \"sub%.w %#1,%0\;jbcc %l1\";
6693 if (DATA_REG_P (operands[0]))
6694 return \"dbra %0,%l1\";
6695 if (GET_CODE (operands[0]) == MEM)
6696 return \"subq%.w %#1,%0\;jbcc %l1\";
6698 #ifdef SGS_CMP_ORDER
6700 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6702 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6704 #else /* not SGS_CMP_ORDER */
6705 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6706 #endif /* not SGS_CMP_ORDER */
6707 #else /* not MOTOROLA */
6708 if (DATA_REG_P (operands[0]))
6709 return \"dbra %0,%l1\";
6710 if (GET_CODE (operands[0]) == MEM)
6711 return \"subqw %#1,%0\;jcc %l1\";
6712 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6713 #endif /* not MOTOROLA */
6716 (define_expand "decrement_and_branch_until_zero"
6717 [(parallel [(set (pc)
6719 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6722 (label_ref (match_operand 1 "" ""))
6725 (plus:SI (match_dup 0)
6733 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6736 (label_ref (match_operand 1 "" ""))
6739 (plus:SI (match_dup 0)
6741 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6747 if (DATA_REG_P (operands[0]))
6748 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6749 if (GET_CODE (operands[0]) == MEM)
6750 return \"sub%.l %#1,%0\;jbcc %l1\";
6752 if (DATA_REG_P (operands[0]))
6753 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6754 if (GET_CODE (operands[0]) == MEM)
6755 return \"subq%.l %#1,%0\;jbcc %l1\";
6757 #ifdef SGS_CMP_ORDER
6759 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6761 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6763 #else /* not SGS_CMP_ORDER */
6764 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6765 #endif /* not SGS_CMP_ORDER */
6766 #else /* not MOTOROLA */
6767 if (DATA_REG_P (operands[0]))
6768 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6769 if (GET_CODE (operands[0]) == MEM)
6770 return \"subql %#1,%0\;jcc %l1\";
6771 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6772 #endif /* not MOTOROLA */
6776 ;; For PIC calls, in order to be able to support
6777 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6778 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6780 ;; PIC calls are handled by loading the address of the function into a
6781 ;; register (via movsi), then emitting a register indirect call using
6782 ;; the "jsr" function call syntax.
6784 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6785 ;; operand to the jbsr statement to indicate that this call should
6786 ;; go through the PLT (why? because this is the way that Sun does it).
6788 ;; We have different patterns for PIC calls and non-PIC calls. The
6789 ;; different patterns are only used to choose the right syntax.
6791 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6792 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6793 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6794 ;; section at link time. However, all global objects reference are still
6795 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6796 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6797 ;; We need to have a way to differentiate these two different operands.
6799 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6800 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6801 ;; to be changed to recognize function calls symbol_ref operand as a valid
6802 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6803 ;; avoid the compiler to load this symbol_ref operand into a register.
6804 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6805 ;; since the value is a PC relative offset, not a real address.
6807 ;; All global objects are treated in the similar way as in SUN3. The only
6808 ;; difference is: on m68k svr4, the reference of such global object needs
6809 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6810 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6813 ;; Call subroutine with no return value.
6814 (define_expand "call"
6815 [(call (match_operand:QI 0 "memory_operand" "")
6816 (match_operand:SI 1 "general_operand" ""))]
6817 ;; Operand 1 not really used on the m68000.
6822 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6823 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6826 ;; This is a normal call sequence.
6828 [(call (match_operand:QI 0 "memory_operand" "o")
6829 (match_operand:SI 1 "general_operand" "g"))]
6830 ;; Operand 1 not really used on the m68000.
6834 #if defined (MOTOROLA) && !defined (USE_GAS)
6841 ;; This is a PIC call sequence.
6843 [(call (match_operand:QI 0 "memory_operand" "o")
6844 (match_operand:SI 1 "general_operand" "g"))]
6845 ;; Operand 1 not really used on the m68000.
6849 if (GET_CODE (operands[0]) == MEM
6850 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6852 if (TARGET_PCREL) return \"bsr.l %o0\";
6855 return \"bsr.l %0\";
6858 return \"bsr.l %0@PLTPC\";
6860 return \"bsr %0@PLTPC\";
6865 return \"bsr.l %0\";
6867 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6868 GAS just plain ignores it. FIXME: not anymore, gas doesn't! */
6869 return \"jbsr %0,a1\";
6876 ;; Call subroutine, returning value in operand 0
6877 ;; (which must be a hard register).
6878 ;; See comments before "call" regarding PIC calls.
6879 (define_expand "call_value"
6880 [(set (match_operand 0 "" "")
6881 (call (match_operand:QI 1 "memory_operand" "")
6882 (match_operand:SI 2 "general_operand" "")))]
6883 ;; Operand 2 not really used on the m68000.
6887 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6888 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6891 ;; This is a normal call_value
6893 [(set (match_operand 0 "" "=rf")
6894 (call (match_operand:QI 1 "memory_operand" "o")
6895 (match_operand:SI 2 "general_operand" "g")))]
6896 ;; Operand 2 not really used on the m68000.
6899 #if defined (MOTOROLA) && !defined (USE_GAS)
6906 ;; This is a PIC call_value
6908 [(set (match_operand 0 "" "=rf")
6909 (call (match_operand:QI 1 "memory_operand" "o")
6910 (match_operand:SI 2 "general_operand" "g")))]
6911 ;; Operand 2 not really used on the m68000.
6914 if (GET_CODE (operands[1]) == MEM
6915 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6917 if (TARGET_PCREL) return \"bsr.l %o1\";
6920 return \"bsr.l %1\";
6923 return \"bsr.l %1@PLTPC\";
6925 return \"bsr %1@PLTPC\";
6930 return \"bsr.l %1\";
6932 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6933 GAS just plain ignores it. FIXME: Not anymore, gas doesn't! */
6934 return \"jbsr %1,a1\";
6941 ;; Call subroutine returning any type.
6943 (define_expand "untyped_call"
6944 [(parallel [(call (match_operand 0 "" "")
6946 (match_operand 1 "" "")
6947 (match_operand 2 "" "")])]
6948 "NEEDS_UNTYPED_CALL"
6953 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6955 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6957 rtx set = XVECEXP (operands[2], 0, i);
6958 emit_move_insn (SET_DEST (set), SET_SRC (set));
6961 /* The optimizer does not know that the call sets the function value
6962 registers we stored in the result block. We avoid problems by
6963 claiming that all hard registers are used and clobbered at this
6965 emit_insn (gen_blockage ());
6970 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6971 ;; all of memory. This blocks insns from being moved across this point.
6973 (define_insn "blockage"
6974 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6983 ;; Used for frameless functions which save no regs and allocate no locals.
6984 (define_insn "return"
6989 if (current_function_pops_args == 0)
6991 operands[0] = GEN_INT (current_function_pops_args);
6995 (define_insn "indirect_jump"
6996 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7000 ;; This should not be used unless the add/sub insns can't be.
7003 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
7004 (match_operand:QI 1 "address_operand" "p"))]
7009 /* Recognize an insn that refers to a table of offsets. Such an insn will
7010 need to refer to a label on the insn. So output one. Use the
7011 label-number of the table of offsets to generate this label. This code,
7012 and similar code above, assumes that there will be at most one reference
7014 if (GET_CODE (operands[1]) == PLUS
7015 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
7016 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
7018 rtx labelref = XEXP (operands[1], 1);
7019 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
7021 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
7022 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7024 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
7025 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7026 #endif /* not SGS */
7027 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
7028 (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
7029 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7030 #ifdef SGS_SWITCH_TABLES
7031 /* Set flag saying we need to define the symbol
7032 LD%n (with value L%n-LI%n) at the end of the switch table. */
7033 switch_table_difference_label_flag = 1;
7034 #endif /* SGS_SWITCH_TABLES */
7035 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7037 #endif /* SGS_NO_LI */
7039 return \"lea %a1,%0\";
7042 ;; This is the first machine-dependent peephole optimization.
7043 ;; It is useful when a floating value is returned from a function call
7044 ;; and then is moved into an FP register.
7045 ;; But it is mainly intended to test the support for these optimizations.
7048 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7049 (set (match_operand:DF 0 "register_operand" "=f")
7050 (match_operand:DF 1 "register_operand" "ad"))]
7051 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7055 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7056 output_asm_insn (\"move%.l %1,%@\", xoperands);
7057 output_asm_insn (\"move%.l %1,%-\", operands);
7058 return \"fmove%.d %+,%0\";
7062 ;; Optimize a stack-adjust followed by a push of an argument.
7063 ;; This is said to happen frequently with -msoft-float
7064 ;; when there are consecutive library calls.
7067 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7068 (match_operand:SI 0 "const_int_operand" "n")))
7069 (set (match_operand:SF 1 "push_operand" "=m")
7070 (match_operand:SF 2 "general_operand" "rmfF"))]
7071 "INTVAL (operands[0]) >= 4
7072 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7075 if (INTVAL (operands[0]) > 4)
7078 xoperands[0] = stack_pointer_rtx;
7079 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7081 if (INTVAL (xoperands[1]) <= 8)
7084 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7086 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7088 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7090 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7091 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7095 if (INTVAL (xoperands[1]) <= 0x7FFF)
7098 output_asm_insn (\"add%.w %1,%0\", xoperands);
7101 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7103 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7107 output_asm_insn (\"add%.l %1,%0\", xoperands);
7109 if (FP_REG_P (operands[2]))
7110 return \"fmove%.s %2,%@\";
7111 return \"move%.l %2,%@\";
7114 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7117 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7118 (match_operand:SI 0 "const_int_operand" "n")))
7119 (set (match_operand:SI 1 "push_operand" "=m")
7120 (match_operand:SI 2 "general_operand" "g"))]
7121 "INTVAL (operands[0]) >= 4
7122 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7125 if (INTVAL (operands[0]) > 4)
7128 xoperands[0] = stack_pointer_rtx;
7129 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7131 if (INTVAL (xoperands[1]) <= 8)
7134 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7136 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7138 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7140 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7141 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7145 if (INTVAL (xoperands[1]) <= 0x7FFF)
7148 output_asm_insn (\"add%.w %1,%0\", xoperands);
7152 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7154 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7159 output_asm_insn (\"add%.l %1,%0\", xoperands);
7161 if (operands[2] == const0_rtx)
7162 return \"clr%.l %@\";
7163 return \"move%.l %2,%@\";
7166 ;; Speed up pushing a single byte but leaving four bytes of space.
7169 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7170 (match_operand:QI 1 "general_operand" "dami"))
7171 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7172 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7177 if (GET_CODE (operands[1]) == REG)
7178 return \"move%.l %1,%-\";
7180 xoperands[1] = operands[1];
7182 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7183 xoperands[3] = stack_pointer_rtx;
7185 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7187 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7192 [(set (match_operand:SI 0 "register_operand" "=d")
7194 (set (strict_low_part (subreg:HI (match_dup 0) 2))
7195 (match_operand:HI 1 "general_operand" "rmn"))]
7196 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7199 if (GET_CODE (operands[1]) == CONST_INT)
7201 if (operands[1] == const0_rtx
7202 && (DATA_REG_P (operands[0])
7203 || GET_CODE (operands[0]) == MEM)
7204 /* clr insns on 68000 read before writing.
7205 This isn't so on the 68010, but we have no TARGET_68010. */
7206 && ((TARGET_68020 || TARGET_5200)
7207 || !(GET_CODE (operands[0]) == MEM
7208 && MEM_VOLATILE_P (operands[0]))))
7209 return \"clr%.w %0\";
7211 return \"move%.w %1,%0\";
7219 ;; jCC label ; abnormal loop termination
7220 ;; dbra dN, loop ; normal loop termination
7228 ;; Which moves the jCC condition outside the inner loop for free.
7232 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7233 [(cc0) (const_int 0)])
7234 (label_ref (match_operand 2 "" ""))
7239 (ne (match_operand:HI 0 "register_operand" "")
7241 (label_ref (match_operand 1 "" ""))
7244 (plus:HI (match_dup 0)
7246 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7250 output_dbcc_and_branch (operands);
7255 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7256 [(cc0) (const_int 0)])
7257 (label_ref (match_operand 2 "" ""))
7262 (ne (match_operand:SI 0 "register_operand" "")
7264 (label_ref (match_operand 1 "" ""))
7267 (plus:SI (match_dup 0)
7269 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7273 output_dbcc_and_branch (operands);
7278 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7279 [(cc0) (const_int 0)])
7280 (label_ref (match_operand 2 "" ""))
7285 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
7288 (label_ref (match_operand 1 "" ""))
7291 (plus:HI (match_dup 0)
7293 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7297 output_dbcc_and_branch (operands);
7302 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7303 [(cc0) (const_int 0)])
7304 (label_ref (match_operand 2 "" ""))
7309 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
7312 (label_ref (match_operand 1 "" ""))
7315 (plus:SI (match_dup 0)
7317 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7321 output_dbcc_and_branch (operands);
7326 (define_expand "tstxf"
7328 (match_operand:XF 0 "nonimmediate_operand" ""))]
7330 "m68k_last_compare_had_fp_operands = 1;")
7334 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7338 cc_status.flags = CC_IN_68881;
7339 return \"ftst%.x %0\";
7342 (define_expand "cmpxf"
7344 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7345 (match_operand:XF 1 "nonimmediate_operand" "")))]
7347 "m68k_last_compare_had_fp_operands = 1;")
7351 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7352 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7356 cc_status.flags = CC_IN_68881;
7357 #ifdef SGS_CMP_ORDER
7358 if (REG_P (operands[0]))
7360 if (REG_P (operands[1]))
7361 return \"fcmp%.x %0,%1\";
7363 return \"fcmp%.x %0,%f1\";
7365 cc_status.flags |= CC_REVERSED;
7366 return \"fcmp%.x %1,%f0\";
7368 if (REG_P (operands[0]))
7370 if (REG_P (operands[1]))
7371 return \"fcmp%.x %1,%0\";
7373 return \"fcmp%.x %f1,%0\";
7375 cc_status.flags |= CC_REVERSED;
7376 return \"fcmp%.x %f0,%1\";
7380 (define_insn "extendsfxf2"
7381 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7382 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7386 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7388 if (REGNO (operands[0]) == REGNO (operands[1]))
7390 /* Extending float to double in an fp-reg is a no-op.
7391 NOTICE_UPDATE_CC has already assumed that the
7392 cc will be set. So cancel what it did. */
7393 cc_status = cc_prev_status;
7396 return \"f%$move%.x %1,%0\";
7398 if (FP_REG_P (operands[0]))
7400 if (FP_REG_P (operands[1]))
7401 return \"f%$move%.x %1,%0\";
7402 else if (ADDRESS_REG_P (operands[1]))
7403 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7404 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7405 return output_move_const_single (operands);
7406 return \"f%$move%.s %f1,%0\";
7408 return \"fmove%.x %f1,%0\";
7412 (define_insn "extenddfxf2"
7413 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7415 (match_operand:DF 1 "general_operand" "f,rmE")))]
7419 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7421 if (REGNO (operands[0]) == REGNO (operands[1]))
7423 /* Extending float to double in an fp-reg is a no-op.
7424 NOTICE_UPDATE_CC has already assumed that the
7425 cc will be set. So cancel what it did. */
7426 cc_status = cc_prev_status;
7429 return \"fmove%.x %1,%0\";
7431 if (FP_REG_P (operands[0]))
7433 if (REG_P (operands[1]))
7436 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7437 output_asm_insn (\"move%.l %1,%-\", xoperands);
7438 output_asm_insn (\"move%.l %1,%-\", operands);
7439 return \"f%&move%.d %+,%0\";
7441 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7442 return output_move_const_double (operands);
7443 return \"f%&move%.d %f1,%0\";
7445 return \"fmove%.x %f1,%0\";
7448 (define_insn "truncxfdf2"
7449 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
7451 (match_operand:XF 1 "general_operand" "f,f")))]
7455 if (REG_P (operands[0]))
7457 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7458 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7459 return \"move%.l %+,%0\";
7461 return \"fmove%.d %f1,%0\";
7464 (define_insn "truncxfsf2"
7465 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
7467 (match_operand:XF 1 "general_operand" "f")))]
7471 (define_insn "floatsixf2"
7472 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7473 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7477 (define_insn "floathixf2"
7478 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7479 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7483 (define_insn "floatqixf2"
7484 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7485 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7489 (define_insn "ftruncxf2"
7490 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7491 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7495 if (FP_REG_P (operands[1]))
7496 return \"fintrz%.x %f1,%0\";
7497 return \"fintrz%.x %f1,%0\";
7500 (define_insn "fixxfqi2"
7501 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
7502 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7506 (define_insn "fixxfhi2"
7507 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
7508 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7512 (define_insn "fixxfsi2"
7513 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
7514 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7519 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7520 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7521 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7526 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7527 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7528 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7533 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7534 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7535 (match_operand:XF 1 "general_operand" "0")))]
7539 (define_insn "addxf3"
7540 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7541 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7542 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7546 if (REG_P (operands[2]))
7547 return \"fadd%.x %2,%0\";
7548 return \"fadd%.x %f2,%0\";
7552 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7553 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7554 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7559 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7560 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7561 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7566 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7567 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7568 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7572 (define_insn "subxf3"
7573 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7574 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7575 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7579 if (REG_P (operands[2]))
7580 return \"fsub%.x %2,%0\";
7581 return \"fsub%.x %f2,%0\";
7585 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7586 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7587 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7592 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7593 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7594 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7599 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7600 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7601 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7605 (define_insn "mulxf3"
7606 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7607 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7608 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7612 if (REG_P (operands[2]))
7613 return \"fmul%.x %2,%0\";
7614 return \"fmul%.x %f2,%0\";
7618 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7619 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7620 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7625 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7626 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7627 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7632 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7633 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7634 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7638 (define_insn "divxf3"
7639 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7640 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7641 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7645 if (REG_P (operands[2]))
7646 return \"fdiv%.x %2,%0\";
7647 return \"fdiv%.x %f2,%0\";
7650 (define_expand "negxf2"
7651 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7652 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7663 target = operand_subword (operands[0], 0, 1, XFmode);
7664 result = expand_binop (SImode, xor_optab,
7665 operand_subword_force (operands[1], 0, XFmode),
7666 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7670 if (result != target)
7671 emit_move_insn (result, target);
7673 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7674 operand_subword_force (operands[1], 1, XFmode));
7675 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7676 operand_subword_force (operands[1], 2, XFmode));
7678 insns = get_insns ();
7681 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7686 (define_insn "negxf2_68881"
7687 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7688 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7692 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7693 return \"fneg%.x %1,%0\";
7694 return \"fneg%.x %f1,%0\";
7697 (define_expand "absxf2"
7698 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7699 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7710 target = operand_subword (operands[0], 0, 1, XFmode);
7711 result = expand_binop (SImode, and_optab,
7712 operand_subword_force (operands[1], 0, XFmode),
7713 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7717 if (result != target)
7718 emit_move_insn (result, target);
7720 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7721 operand_subword_force (operands[1], 1, XFmode));
7722 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7723 operand_subword_force (operands[1], 2, XFmode));
7725 insns = get_insns ();
7728 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7733 (define_insn "absxf2_68881"
7734 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7735 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7739 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7740 return \"fabs%.x %1,%0\";
7741 return \"fabs%.x %f1,%0\";
7744 (define_insn "sqrtxf2"
7745 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7746 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7750 (define_insn "sinsf2"
7751 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7752 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_SIN))]
7753 "TARGET_68881 && flag_unsafe_math_optimizations"
7756 if (FP_REG_P (operands[1]))
7757 return \"fsin%.x %1,%0\";
7759 return \"fsin%.s %1,%0\";
7762 (define_insn "sindf2"
7763 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7764 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_SIN))]
7765 "TARGET_68881 && flag_unsafe_math_optimizations"
7768 if (FP_REG_P (operands[1]))
7769 return \"fsin%.x %1,%0\";
7771 return \"fsin%.d %1,%0\";
7774 (define_insn "sinxf2"
7775 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7776 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_SIN))]
7777 "TARGET_68881 && flag_unsafe_math_optimizations"
7780 (define_insn "cossf2"
7781 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7782 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_COS))]
7783 "TARGET_68881 && flag_unsafe_math_optimizations"
7786 if (FP_REG_P (operands[1]))
7787 return \"fcos%.x %1,%0\";
7789 return \"fcos%.s %1,%0\";
7792 (define_insn "cosdf2"
7793 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7794 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_COS))]
7795 "TARGET_68881 && flag_unsafe_math_optimizations"
7798 if (FP_REG_P (operands[1]))
7799 return \"fcos%.x %1,%0\";
7801 return \"fcos%.d %1,%0\";
7804 (define_insn "cosxf2"
7805 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7806 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_COS))]
7807 "TARGET_68881 && flag_unsafe_math_optimizations"
7811 [(trap_if (const_int -1) (const_int 7))]
7815 (define_insn "conditional_trap"
7816 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7817 [(cc0) (const_int 0)])
7818 (match_operand:SI 1 "const_int_operand" "I"))]
7819 "TARGET_68020 && ! flags_in_68881 ()"
7822 switch (GET_CODE (operands[0]))
7824 case EQ: return \"trapeq\";
7825 case NE: return \"trapne\";
7826 case GT: return \"trapgt\";
7827 case GTU: return \"traphi\";
7828 case LT: return \"traplt\";
7829 case LTU: return \"trapcs\";
7830 case GE: return \"trapge\";
7831 case GEU: return \"trapcc\";
7832 case LE: return \"traple\";
7833 case LEU: return \"trapls\";