1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- Information about MCF5200 port.
25 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
26 ;;- 68k ISA. Differences include reduced support for byte and word
27 ;;- operands and the removal of BCD, bitfield, rotate, and integer
28 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
29 ;;- removed opcodes and addressing modes off.
33 ;;- instruction definitions
35 ;;- @@The original PO technology requires these to be ordered by speed,
36 ;;- @@ so that assigner will pick the fastest.
38 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
40 ;;- When naming insn's (operand 0 of define_insn) be careful about using
41 ;;- names from other targets machine descriptions.
43 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
44 ;;- updates for most instructions.
46 ;;- Operand classes for the register allocator:
47 ;;- 'a' one of the address registers can be used.
48 ;;- 'd' one of the data registers can be used.
49 ;;- 'f' one of the m68881/fpu registers can be used
50 ;;- 'r' either a data or an address register can be used.
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
57 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
60 ;;- Immediate integer operand constraints:
62 ;;- 'J' -32768 .. 32767
63 ;;- 'K' all integers EXCEPT -128 .. 127
65 ;;- 'M' all integers EXCEPT -256 .. 255
71 ;;- "%." size separator ("." or "") move%.l d0,d1
72 ;;- "%-" push operand "sp@-" move%.l d0,%-
73 ;;- "%+" pop operand "sp@+" move%.l d0,%+
74 ;;- "%@" top of stack "sp@" move%.l d0,%@
75 ;;- "%!" fpcr register
76 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
77 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;;- Information about 68040 port.
81 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
82 ;;- be emulated in software by the OS. It is faster to avoid these
83 ;;- instructions and issue a library call rather than trapping into
84 ;;- the kernel. The affected instructions are fintrz and fscale. The
85 ;;- TUNE_68040 flag turns the use of the opcodes off.
87 ;;- The '040 also implements a set of new floating-point instructions
88 ;;- which specify the rounding precision in the opcode. This finally
89 ;;- permit the 68k series to be truly IEEE compliant, and solves all
90 ;;- issues of excess precision accumulating in the extended registers.
91 ;;- By default, GCC does not use these instructions, since such code will
92 ;;- not run on an '030. To use these instructions, use the -m68040-only
95 ;;- These new instructions aren't directly in the md. They are brought
96 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
99 ;;- Information about 68060 port.
101 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
102 ;;- be emulated in software by the OS. It is faster to avoid these
103 ;;- instructions and issue a library call rather than trapping into
104 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
105 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
106 ;;- fscale. The TUNE_68060 flag turns the use of the opcodes off.
108 ;;- Some of these insn's are composites of several m68000 op codes.
109 ;;- The assembler (or final @@??) insures that the appropriate one is
119 ;; UNSPEC_VOLATILE usage:
122 [(UNSPECV_BLOCKAGE 0)
125 ;; Registers by name.
131 (include "predicates.md")
133 ;; Mode macros for floating point operations.
134 ;; Valid floating point modes
135 (define_mode_macro FP [SF DF (XF "TARGET_68881")])
136 ;; Mnemonic infix to round result
137 (define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
138 ;; Mnemonic infix to round result for mul or div instruction
139 (define_mode_attr round_mul [(SF "sgl") (DF "%&") (XF "")])
140 ;; Suffix specifying source operand format
141 (define_mode_attr prec [(SF "s") (DF "d") (XF "x")])
142 ;; Allowable D registers
143 (define_mode_attr dreg [(SF "d") (DF "") (XF "")])
144 ;; Allowable 68881 constant constraints
145 (define_mode_attr const [(SF "F") (DF "G") (XF "")])
148 [(set (match_operand:DF 0 "push_operand" "=m")
149 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
152 if (FP_REG_P (operands[1]))
153 return "fmove%.d %f1,%0";
154 return output_move_double (operands);
157 (define_insn "pushdi"
158 [(set (match_operand:DI 0 "push_operand" "=m")
159 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
162 return output_move_double (operands);
165 ;; We don't want to allow a constant operand for test insns because
166 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
167 ;; be folded while optimizing anyway.
169 (define_expand "tstdi"
170 [(parallel [(set (cc0)
171 (match_operand:DI 0 "nonimmediate_operand" ""))
172 (clobber (match_scratch:SI 1 ""))
173 (clobber (match_scratch:DI 2 ""))])]
175 "m68k_last_compare_had_fp_operands = 0;")
179 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
180 (clobber (match_scratch:SI 1 "=X,d"))
181 (clobber (match_scratch:DI 2 "=d,X"))]
184 if (which_alternative == 0)
188 xoperands[0] = operands[2];
189 xoperands[1] = operands[0];
190 output_move_double (xoperands);
191 cc_status.flags |= CC_REVERSED;
192 return "neg%.l %R2\;negx%.l %2";
194 if (find_reg_note (insn, REG_DEAD, operands[0]))
196 cc_status.flags |= CC_REVERSED;
197 return "neg%.l %R0\;negx%.l %0";
201 'sub' clears %1, and also clears the X cc bit
202 'tst' sets the Z cc bit according to the low part of the DImode operand
203 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part.
205 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
208 (define_expand "tstsi"
210 (match_operand:SI 0 "nonimmediate_operand" ""))]
212 "m68k_last_compare_had_fp_operands = 0;")
216 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
219 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
221 /* If you think that the 68020 does not support tstl a0,
222 reread page B-167 of the 68020 manual more carefully. */
223 /* On an address reg, cmpw may replace cmpl. */
224 return "cmp%.w #0,%0";
227 ;; This can't use an address register, because comparisons
228 ;; with address registers as second operand always test the whole word.
229 (define_expand "tsthi"
231 (match_operand:HI 0 "nonimmediate_operand" ""))]
233 "m68k_last_compare_had_fp_operands = 0;")
237 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
241 (define_expand "tstqi"
243 (match_operand:QI 0 "nonimmediate_operand" ""))]
245 "m68k_last_compare_had_fp_operands = 0;")
249 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
253 (define_expand "tst<mode>"
255 (match_operand:FP 0 "general_operand" ""))]
258 m68k_last_compare_had_fp_operands = 1;
261 (define_insn "tst<mode>_68881"
263 (match_operand:FP 0 "general_operand" "f<FP:dreg>m"))]
266 cc_status.flags = CC_IN_68881;
267 if (FP_REG_P (operands[0]))
269 return "ftst%.<FP:prec> %0";
272 (define_insn "tst<mode>_cf"
274 (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U"))]
275 "TARGET_COLDFIRE_FPU"
277 cc_status.flags = CC_IN_68881;
278 if (FP_REG_P (operands[0]))
280 return "ftst%.<FP:prec> %0";
284 ;; compare instructions.
286 (define_expand "cmpdi"
289 (compare (match_operand:DI 0 "nonimmediate_operand" "")
290 (match_operand:DI 1 "general_operand" "")))
291 (clobber (match_dup 2))])]
293 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
297 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
298 (match_operand:DI 2 "general_operand" "d,0")))
299 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
302 if (rtx_equal_p (operands[0], operands[1]))
303 return "sub%.l %R2,%R0\;subx%.l %2,%0";
306 cc_status.flags |= CC_REVERSED;
307 return "sub%.l %R1,%R0\;subx%.l %1,%0";
311 ;; This is the second "hook" for PIC code (in addition to movsi). See
312 ;; comment of movsi for a description of PIC handling.
313 (define_expand "cmpsi"
315 (compare (match_operand:SI 0 "nonimmediate_operand" "")
316 (match_operand:SI 1 "general_operand" "")))]
319 m68k_last_compare_had_fp_operands = 0;
320 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
322 /* The source is an address which requires PIC relocation.
323 Call legitimize_pic_address with the source, mode, and a relocation
324 register (a new pseudo, or the final destination if reload_in_progress
325 is set). Then fall through normally */
326 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
327 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
331 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
334 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
335 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
338 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
339 return "cmpm%.l %1,%0";
340 if (REG_P (operands[1])
341 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
343 cc_status.flags |= CC_REVERSED;
344 return "cmp%.l %d0,%d1";
346 if (ADDRESS_REG_P (operands[0])
347 && GET_CODE (operands[1]) == CONST_INT
348 && INTVAL (operands[1]) < 0x8000
349 && INTVAL (operands[1]) >= -0x8000)
350 return "cmp%.w %1,%0";
351 return "cmp%.l %d1,%d0";
356 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
357 (match_operand:SI 1 "general_operand" "r,mrKs")))]
360 if (REG_P (operands[1])
361 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
363 cc_status.flags |= CC_REVERSED;
364 return "cmp%.l %d0,%d1";
366 return "cmp%.l %d1,%d0";
369 (define_expand "cmphi"
371 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
372 (match_operand:HI 1 "general_src_operand" "")))]
374 "m68k_last_compare_had_fp_operands = 0;")
378 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
379 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
382 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
383 return "cmpm%.w %1,%0";
384 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
385 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
387 cc_status.flags |= CC_REVERSED;
388 return "cmp%.w %d0,%d1";
390 return "cmp%.w %d1,%d0";
393 (define_expand "cmpqi"
395 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
396 (match_operand:QI 1 "general_src_operand" "")))]
398 "m68k_last_compare_had_fp_operands = 0;")
402 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
403 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
406 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
407 return "cmpm%.b %1,%0";
408 if (REG_P (operands[1])
409 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
411 cc_status.flags |= CC_REVERSED;
412 return "cmp%.b %d0,%d1";
414 return "cmp%.b %d1,%d0";
417 (define_expand "cmp<mode>"
419 (compare (match_operand:FP 0 "general_operand" "")
420 (match_operand:FP 1 "general_operand" "")))]
423 m68k_last_compare_had_fp_operands = 1;
424 if (TARGET_COLDFIRE && !reload_completed)
425 operands[1] = force_reg (<MODE>mode, operands[1]);
428 (define_insn "cmp<mode>_68881"
430 (compare (match_operand:FP 0 "general_operand" "f,m<FP:const>")
431 (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,f")))]
434 cc_status.flags = CC_IN_68881;
435 if (FP_REG_P (operands[0]))
437 if (FP_REG_P (operands[1]))
438 return "fcmp%.x %1,%0";
440 return "fcmp%.<FP:prec> %f1,%0";
442 cc_status.flags |= CC_REVERSED;
443 return "fcmp%.<FP:prec> %f0,%1";
446 (define_insn "cmp<mode>_cf"
448 (compare (match_operand:FP 0 "general_operand" "f,<FP:dreg><Q>U")
449 (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,f")))]
450 "TARGET_COLDFIRE_FPU"
452 cc_status.flags = CC_IN_68881;
453 if (FP_REG_P (operands[0]))
455 if (FP_REG_P (operands[1]))
456 return "fcmp%.d %1,%0";
458 return "fcmp%.<FP:prec> %f1,%0";
460 cc_status.flags |= CC_REVERSED;
461 return "fcmp%.<FP:prec> %f0,%1";
464 ;; Recognizers for btst instructions.
466 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
467 ;; specified as a constant, so we must disable all patterns that may extract
468 ;; from a MEM at a constant bit position if we can't use this as a constraint.
471 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
473 (minus:SI (const_int 7)
474 (match_operand:SI 1 "general_operand" "di"))))]
477 return output_btst (operands, operands[1], operands[0], insn, 7);
480 ;; This is the same as the above pattern except for the constraints. The 'i'
484 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
486 (minus:SI (const_int 7)
487 (match_operand:SI 1 "general_operand" "d"))))]
490 return output_btst (operands, operands[1], operands[0], insn, 7);
494 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
496 (minus:SI (const_int 31)
497 (match_operand:SI 1 "general_operand" "di"))))]
500 return output_btst (operands, operands[1], operands[0], insn, 31);
503 ;; The following two patterns are like the previous two
504 ;; except that they use the fact that bit-number operands
505 ;; are automatically masked to 3 or 5 bits.
508 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
510 (minus:SI (const_int 7)
512 (match_operand:SI 1 "register_operand" "d")
516 return output_btst (operands, operands[1], operands[0], insn, 7);
520 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
522 (minus:SI (const_int 31)
524 (match_operand:SI 1 "register_operand" "d")
528 return output_btst (operands, operands[1], operands[0], insn, 31);
531 ;; Nonoffsettable mem refs are ok in this one pattern
532 ;; since we don't try to adjust them.
534 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
536 (match_operand:SI 1 "const_int_operand" "n")))]
537 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
539 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
540 return output_btst (operands, operands[1], operands[0], insn, 7);
544 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
546 (match_operand:SI 1 "const_int_operand" "n")))]
549 if (GET_CODE (operands[0]) == MEM)
551 operands[0] = adjust_address (operands[0], QImode,
552 INTVAL (operands[1]) / 8);
553 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
554 return output_btst (operands, operands[1], operands[0], insn, 7);
556 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
557 return output_btst (operands, operands[1], operands[0], insn, 31);
560 ;; This is the same as the above pattern except for the constraints.
561 ;; The 'o' has been replaced with 'Q'.
564 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
566 (match_operand:SI 1 "const_int_operand" "n")))]
569 if (GET_CODE (operands[0]) == MEM)
571 operands[0] = adjust_address (operands[0], QImode,
572 INTVAL (operands[1]) / 8);
573 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
574 return output_btst (operands, operands[1], operands[0], insn, 7);
576 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
577 return output_btst (operands, operands[1], operands[0], insn, 31);
583 ;; A special case in which it is not desirable
584 ;; to reload the constant into a data register.
585 (define_insn "pushexthisi_const"
586 [(set (match_operand:SI 0 "push_operand" "=m")
587 (match_operand:SI 1 "const_int_operand" "J"))]
588 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
590 if (operands[1] == const0_rtx)
592 if (valid_mov3q_const(operands[1]))
593 return "mov3q%.l %1,%-";
598 ;(define_insn "swapsi"
599 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
600 ; (match_operand:SI 1 "general_operand" "+r"))
601 ; (set (match_dup 1) (match_dup 0))]
605 ;; Special case of fullword move when source is zero.
606 ;; The reason this is special is to avoid loading a zero
607 ;; into a data reg with moveq in order to store it elsewhere.
609 (define_insn "movsi_const0"
610 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
612 ;; clr insns on 68000 read before writing.
613 "((TARGET_68010 || TARGET_COLDFIRE)
614 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
616 if (ADDRESS_REG_P (operands[0]))
618 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
620 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
622 return "sub%.l %0,%0";
624 /* moveq is faster on the 68000. */
625 if (DATA_REG_P (operands[0]) && TUNE_68000_10)
626 return "moveq #0,%0";
630 ;; General case of fullword move.
632 ;; This is the main "hook" for PIC code. When generating
633 ;; PIC, movsi is responsible for determining when the source address
634 ;; needs PIC relocation and appropriately calling legitimize_pic_address
635 ;; to perform the actual relocation.
637 ;; In both the PIC and non-PIC cases the patterns generated will
638 ;; matched by the next define_insn.
639 (define_expand "movsi"
640 [(set (match_operand:SI 0 "nonimmediate_operand" "")
641 (match_operand:SI 1 "general_operand" ""))]
644 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
646 /* The source is an address which requires PIC relocation.
647 Call legitimize_pic_address with the source, mode, and a relocation
648 register (a new pseudo, or the final destination if reload_in_progress
649 is set). Then fall through normally */
650 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
651 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
653 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
655 /* Don't allow writes to memory except via a register;
656 the m68k doesn't consider PC-relative addresses to be writable. */
657 if (symbolic_operand (operands[0], SImode))
658 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
659 else if (GET_CODE (operands[0]) == MEM
660 && symbolic_operand (XEXP (operands[0], 0), SImode))
661 operands[0] = gen_rtx_MEM (SImode,
662 force_reg (SImode, XEXP (operands[0], 0)));
666 ;; General case of fullword move. The register constraints
667 ;; force integer constants in range for a moveq to be reloaded
668 ;; if they are headed for memory.
670 ;; Notes: make sure no alternative allows g vs g.
671 ;; We don't allow f-regs since fixed point cannot go in them.
672 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
673 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
677 return output_move_simode (operands);
680 (define_insn "*movsi_cf"
681 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
682 (match_operand:SI 1 "general_operand" "g,r<Q>,U"))]
683 "TARGET_COLDFIRE && !TARGET_ISAB"
684 "* return output_move_simode (operands);")
686 (define_insn "*movsi_cfv4"
687 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
688 (match_operand:SI 1 "general_operand" "Rg,Rr<Q>,U"))]
690 "* return output_move_simode (operands);")
692 ;; Special case of fullword move, where we need to get a non-GOT PIC
693 ;; reference into an address register.
695 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
696 (match_operand:SI 1 "pcrel_address" ""))]
699 if (push_operand (operands[0], SImode))
704 (define_expand "movhi"
705 [(set (match_operand:HI 0 "nonimmediate_operand" "")
706 (match_operand:HI 1 "general_operand" ""))]
711 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
712 (match_operand:HI 1 "general_src_operand" "gS"))]
714 "* return output_move_himode (operands);")
717 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
718 (match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
720 "* return output_move_himode (operands);")
722 (define_expand "movstricthi"
723 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
724 (match_operand:HI 1 "general_src_operand" ""))]
729 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
730 (match_operand:HI 1 "general_src_operand" "rmSn"))]
732 "* return output_move_stricthi (operands);")
735 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
736 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
738 "* return output_move_stricthi (operands);")
740 (define_expand "movqi"
741 [(set (match_operand:QI 0 "nonimmediate_operand" "")
742 (match_operand:QI 1 "general_src_operand" ""))]
747 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
748 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
750 "* return output_move_qimode (operands);")
753 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
754 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
756 "* return output_move_qimode (operands);")
758 (define_expand "movstrictqi"
759 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
760 (match_operand:QI 1 "general_src_operand" ""))]
765 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
766 (match_operand:QI 1 "general_src_operand" "dmSn"))]
768 "* return output_move_strictqi (operands);")
771 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
772 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
774 "* return output_move_strictqi (operands);")
776 (define_expand "pushqi1"
777 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
778 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1)))
779 (match_operand:QI 0 "general_operand" ""))]
783 (define_expand "reload_insf"
784 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
785 (match_operand:SF 1 "general_operand" "mf"))
786 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
787 "TARGET_COLDFIRE_FPU"
789 if (emit_move_sequence (operands, SFmode, operands[2]))
792 /* We don't want the clobber emitted, so handle this ourselves. */
793 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
797 (define_expand "reload_outsf"
798 [(set (match_operand:SF 0 "general_operand" "")
799 (match_operand:SF 1 "register_operand" "f"))
800 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
801 "TARGET_COLDFIRE_FPU"
803 if (emit_move_sequence (operands, SFmode, operands[2]))
806 /* We don't want the clobber emitted, so handle this ourselves. */
807 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
811 (define_expand "movsf"
812 [(set (match_operand:SF 0 "nonimmediate_operand" "")
813 (match_operand:SF 1 "general_operand" ""))]
818 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
819 (match_operand:SF 1 "general_operand" "rmfF"))]
822 if (FP_REG_P (operands[0]))
824 if (FP_REG_P (operands[1]))
825 return "f%$move%.x %1,%0";
826 else if (ADDRESS_REG_P (operands[1]))
827 return "move%.l %1,%-\;f%$move%.s %+,%0";
828 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
829 return output_move_const_single (operands);
830 return "f%$move%.s %f1,%0";
832 if (FP_REG_P (operands[1]))
834 if (ADDRESS_REG_P (operands[0]))
835 return "fmove%.s %1,%-\;move%.l %+,%0";
836 return "fmove%.s %f1,%0";
838 if (operands[1] == CONST0_RTX (SFmode)
839 /* clr insns on 68000 read before writing. */
840 && ((TARGET_68010 || TARGET_COLDFIRE)
841 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
843 if (ADDRESS_REG_P (operands[0]))
845 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
847 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
849 return "sub%.l %0,%0";
851 /* moveq is faster on the 68000. */
852 if (DATA_REG_P (operands[0]) && TUNE_68000_10)
853 return "moveq #0,%0";
856 return "move%.l %1,%0";
859 (define_insn "movsf_cf_soft"
860 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
861 (match_operand:SF 1 "general_operand" "g,r"))]
862 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
864 return "move%.l %1,%0";
867 (define_insn "movsf_cf_hard"
868 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f
870 (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m
872 "TARGET_COLDFIRE_FPU"
874 if (which_alternative == 4 || which_alternative == 5) {
878 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
879 REAL_VALUE_TO_TARGET_SINGLE (r, l);
880 xoperands[0] = operands[0];
881 xoperands[1] = GEN_INT (l);
882 if (which_alternative == 5) {
884 if (ADDRESS_REG_P (xoperands[0]))
885 output_asm_insn ("sub%.l %0,%0", xoperands);
887 output_asm_insn ("clr%.l %0", xoperands);
889 if (GET_CODE (operands[0]) == MEM
890 && symbolic_operand (XEXP (operands[0], 0), SImode))
891 output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands);
893 output_asm_insn ("move%.l %1,%0", xoperands);
897 output_asm_insn ("move%.l %1,%-;fsmove%.s %+,%0", xoperands);
899 output_asm_insn ("clr%.l %-;fsmove%.s %+,%0", xoperands);
902 if (FP_REG_P (operands[0]))
904 if (ADDRESS_REG_P (operands[1]))
905 return "move%.l %1,%-;f%$smove%.s %+,%0";
906 if (FP_REG_P (operands[1]))
907 return "f%$move%.d %1,%0";
908 if (GET_CODE (operands[1]) == CONST_DOUBLE)
909 return output_move_const_single (operands);
910 return "f%$move%.s %f1,%0";
912 if (FP_REG_P (operands[1]))
914 if (ADDRESS_REG_P (operands[0]))
915 return "fmove%.s %1,%-;move%.l %+,%0";
916 return "fmove%.s %f1,%0";
918 if (operands[1] == CONST0_RTX (SFmode))
920 if (ADDRESS_REG_P (operands[0]))
921 return "sub%.l %0,%0";
924 return "move%.l %1,%0";
927 (define_expand "reload_indf"
928 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
929 (match_operand:DF 1 "general_operand" "mf"))
930 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
931 "TARGET_COLDFIRE_FPU"
933 if (emit_move_sequence (operands, DFmode, operands[2]))
936 /* We don't want the clobber emitted, so handle this ourselves. */
937 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
941 (define_expand "reload_outdf"
942 [(set (match_operand:DF 0 "general_operand" "")
943 (match_operand:DF 1 "register_operand" "f"))
944 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
945 "TARGET_COLDFIRE_FPU"
947 if (emit_move_sequence (operands, DFmode, operands[2]))
950 /* We don't want the clobber emitted, so handle this ourselves. */
951 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
955 (define_expand "movdf"
956 [(set (match_operand:DF 0 "nonimmediate_operand" "")
957 (match_operand:DF 1 "general_operand" ""))]
960 if (TARGET_COLDFIRE_FPU)
961 if (emit_move_sequence (operands, DFmode, 0))
966 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
967 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
968 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
969 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
972 if (FP_REG_P (operands[0]))
974 if (FP_REG_P (operands[1]))
975 return "f%&move%.x %1,%0";
976 if (REG_P (operands[1]))
979 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
980 output_asm_insn ("move%.l %1,%-", xoperands);
981 output_asm_insn ("move%.l %1,%-", operands);
982 return "f%&move%.d %+,%0";
984 if (GET_CODE (operands[1]) == CONST_DOUBLE)
985 return output_move_const_double (operands);
986 return "f%&move%.d %f1,%0";
988 else if (FP_REG_P (operands[1]))
990 if (REG_P (operands[0]))
992 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
993 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
994 return "move%.l %+,%0";
997 return "fmove%.d %f1,%0";
999 return output_move_double (operands);
1002 (define_insn "movdf_cf_soft"
1003 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
1004 (match_operand:DF 1 "general_operand" "g,r"))]
1005 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
1007 return output_move_double (operands);
1010 (define_insn "movdf_cf_hard"
1011 [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f")
1012 (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))]
1013 "TARGET_COLDFIRE_FPU"
1019 switch (which_alternative)
1022 return "fmove%.d %1,%0";
1024 return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0";
1026 return "move%.l %R1,%-;move%.l %1,%-;f%&move%.d %+,%0";
1028 return "move%.l %1,%0;move%.l %R1,%R0";
1030 return output_move_double (operands);
1032 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1033 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
1034 xoperands[0] = operands[0];
1035 xoperands[1] = GEN_INT (l[0]);
1036 xoperands[2] = GEN_INT (l[1]);
1037 if (operands[1] == CONST0_RTX (DFmode))
1038 output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0",
1042 output_asm_insn ("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0",
1045 output_asm_insn ("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0",
1051 ;; ??? The XFmode patterns are schizophrenic about whether constants are
1052 ;; allowed. Most but not all have predicates and constraint that disallow
1053 ;; constants. Most but not all have output templates that handle constants.
1054 ;; See also LEGITIMATE_CONSTANT_P.
1056 (define_expand "movxf"
1057 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1058 (match_operand:XF 1 "general_operand" ""))]
1061 /* We can't rewrite operands during reload. */
1062 if (! reload_in_progress)
1064 if (CONSTANT_P (operands[1]))
1066 operands[1] = force_const_mem (XFmode, operands[1]);
1067 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
1068 operands[1] = adjust_address (operands[1], XFmode, 0);
1070 if (flag_pic && TARGET_PCREL)
1072 /* Don't allow writes to memory except via a register; the
1073 m68k doesn't consider PC-relative addresses to be writable. */
1074 if (GET_CODE (operands[0]) == MEM
1075 && symbolic_operand (XEXP (operands[0], 0), SImode))
1076 operands[0] = gen_rtx_MEM (XFmode,
1077 force_reg (SImode, XEXP (operands[0], 0)));
1083 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r,m,!r")
1084 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r,!r,m"))]
1087 if (FP_REG_P (operands[0]))
1089 if (FP_REG_P (operands[1]))
1090 return "fmove%.x %1,%0";
1091 if (REG_P (operands[1]))
1094 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1095 output_asm_insn ("move%.l %1,%-", xoperands);
1096 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1097 output_asm_insn ("move%.l %1,%-", xoperands);
1098 output_asm_insn ("move%.l %1,%-", operands);
1099 return "fmove%.x %+,%0";
1101 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1102 return "fmove%.x %1,%0";
1103 return "fmove%.x %f1,%0";
1105 if (FP_REG_P (operands[1]))
1107 if (REG_P (operands[0]))
1109 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1110 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1111 output_asm_insn ("move%.l %+,%0", operands);
1112 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1113 return "move%.l %+,%0";
1115 /* Must be memory destination. */
1116 return "fmove%.x %f1,%0";
1118 return output_move_double (operands);
1122 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1123 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1124 "! TARGET_68881 && ! TARGET_COLDFIRE"
1126 if (FP_REG_P (operands[0]))
1128 if (FP_REG_P (operands[1]))
1129 return "fmove%.x %1,%0";
1130 if (REG_P (operands[1]))
1133 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1134 output_asm_insn ("move%.l %1,%-", xoperands);
1135 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1136 output_asm_insn ("move%.l %1,%-", xoperands);
1137 output_asm_insn ("move%.l %1,%-", operands);
1138 return "fmove%.x %+,%0";
1140 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1141 return "fmove%.x %1,%0";
1142 return "fmove%.x %f1,%0";
1144 if (FP_REG_P (operands[1]))
1146 if (REG_P (operands[0]))
1148 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1149 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1150 output_asm_insn ("move%.l %+,%0", operands);
1151 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1152 return "move%.l %+,%0";
1155 return "fmove%.x %f1,%0";
1157 return output_move_double (operands);
1161 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1162 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1163 "! TARGET_68881 && TARGET_COLDFIRE"
1164 "* return output_move_double (operands);")
1166 (define_expand "movdi"
1167 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1168 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1169 (match_operand:DI 1 "general_operand" ""))]
1173 ;; movdi can apply to fp regs in some cases
1175 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1176 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1177 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1178 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1179 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1180 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1181 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1184 if (FP_REG_P (operands[0]))
1186 if (FP_REG_P (operands[1]))
1187 return "fmove%.x %1,%0";
1188 if (REG_P (operands[1]))
1191 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1192 output_asm_insn ("move%.l %1,%-", xoperands);
1193 output_asm_insn ("move%.l %1,%-", operands);
1194 return "fmove%.d %+,%0";
1196 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1197 return output_move_const_double (operands);
1198 return "fmove%.d %f1,%0";
1200 else if (FP_REG_P (operands[1]))
1202 if (REG_P (operands[0]))
1204 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1205 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1206 return "move%.l %+,%0";
1209 return "fmove%.d %f1,%0";
1211 return output_move_double (operands);
1215 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1216 (match_operand:DI 1 "general_operand" "g,r"))]
1218 "* return output_move_double (operands);")
1220 ;; Thus goes after the move instructions
1221 ;; because the move instructions are better (require no spilling)
1222 ;; when they can apply. It goes before the add/sub insns
1223 ;; so we will prefer it to them.
1225 (define_insn "pushasi"
1226 [(set (match_operand:SI 0 "push_operand" "=m")
1227 (match_operand:SI 1 "address_operand" "p"))]
1231 ;; truncation instructions
1232 (define_insn "truncsiqi2"
1233 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1235 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1238 if (GET_CODE (operands[0]) == REG)
1240 /* Must clear condition codes, since the move.l bases them on
1241 the entire 32 bits, not just the desired 8 bits. */
1243 return "move%.l %1,%0";
1245 if (GET_CODE (operands[1]) == MEM)
1246 operands[1] = adjust_address (operands[1], QImode, 3);
1247 return "move%.b %1,%0";
1250 (define_insn "trunchiqi2"
1251 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1253 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1256 if (GET_CODE (operands[0]) == REG
1257 && (GET_CODE (operands[1]) == MEM
1258 || GET_CODE (operands[1]) == CONST_INT))
1260 /* Must clear condition codes, since the move.w bases them on
1261 the entire 16 bits, not just the desired 8 bits. */
1263 return "move%.w %1,%0";
1265 if (GET_CODE (operands[0]) == REG)
1267 /* Must clear condition codes, since the move.l bases them on
1268 the entire 32 bits, not just the desired 8 bits. */
1270 return "move%.l %1,%0";
1272 if (GET_CODE (operands[1]) == MEM)
1273 operands[1] = adjust_address (operands[1], QImode, 1);
1274 return "move%.b %1,%0";
1277 (define_insn "truncsihi2"
1278 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1280 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1283 if (GET_CODE (operands[0]) == REG)
1285 /* Must clear condition codes, since the move.l bases them on
1286 the entire 32 bits, not just the desired 8 bits. */
1288 return "move%.l %1,%0";
1290 if (GET_CODE (operands[1]) == MEM)
1291 operands[1] = adjust_address (operands[1], QImode, 2);
1292 return "move%.w %1,%0";
1295 ;; zero extension instructions
1297 ;; two special patterns to match various post_inc/pre_dec patterns
1298 (define_insn_and_split "*zero_extend_inc"
1299 [(set (match_operand 0 "post_inc_operand" "")
1300 (zero_extend (match_operand 1 "register_operand" "")))]
1301 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1302 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1303 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1311 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1314 (define_insn_and_split "*zero_extend_dec"
1315 [(set (match_operand 0 "pre_dec_operand" "")
1316 (zero_extend (match_operand 1 "register_operand" "")))]
1317 "(GET_MODE (operands[0]) != HImode || XEXP (XEXP (operands[0], 0), 0) != stack_pointer_rtx) &&
1318 GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1319 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1320 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1328 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1331 (define_insn_and_split "zero_extendqidi2"
1332 [(set (match_operand:DI 0 "register_operand" "")
1333 (zero_extend:DI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1338 (zero_extend:SI (match_dup 1)))
1342 operands[2] = gen_lowpart (SImode, operands[0]);
1343 operands[3] = gen_highpart (SImode, operands[0]);
1346 (define_insn_and_split "zero_extendhidi2"
1347 [(set (match_operand:DI 0 "register_operand" "")
1348 (zero_extend:DI (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1353 (zero_extend:SI (match_dup 1)))
1357 operands[2] = gen_lowpart (SImode, operands[0]);
1358 operands[3] = gen_highpart (SImode, operands[0]);
1361 (define_expand "zero_extendsidi2"
1362 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1363 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1366 if (GET_CODE (operands[0]) == MEM
1367 && GET_CODE (operands[1]) == MEM)
1368 operands[1] = force_reg (SImode, operands[1]);
1371 (define_insn_and_split "*zero_extendsidi2"
1372 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1373 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1374 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1382 operands[2] = gen_lowpart (SImode, operands[0]);
1383 operands[3] = gen_highpart (SImode, operands[0]);
1386 (define_insn "*zero_extendhisi2_cf"
1387 [(set (match_operand:SI 0 "register_operand" "=d")
1388 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1392 (define_insn "zero_extendhisi2"
1393 [(set (match_operand:SI 0 "register_operand" "=d")
1394 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1398 (define_expand "zero_extendqihi2"
1399 [(set (match_operand:HI 0 "register_operand" "")
1400 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1404 (define_insn "*zero_extendqihi2"
1405 [(set (match_operand:HI 0 "register_operand" "=d")
1406 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1410 (define_insn "*zero_extendqisi2_cfv4"
1411 [(set (match_operand:SI 0 "register_operand" "=d")
1412 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1416 (define_insn "zero_extendqisi2"
1417 [(set (match_operand:SI 0 "register_operand" "=d")
1418 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1422 ;; these two pattern split everything else which isn't matched by
1423 ;; something else above
1425 [(set (match_operand 0 "register_operand" "")
1426 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1429 && reg_mentioned_p (operands[0], operands[1])"
1430 [(set (strict_low_part (match_dup 2))
1433 (match_op_dup 4 [(match_dup 0) (match_dup 3)]))]
1435 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1436 operands[3] = GEN_INT (GET_MODE_MASK (GET_MODE (operands[1])));
1437 operands[4] = gen_rtx_AND (GET_MODE (operands[0]), operands[0], operands[3]);
1441 [(set (match_operand 0 "register_operand" "")
1442 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1443 "!TARGET_ISAB && reload_completed"
1446 (set (strict_low_part (match_dup 2))
1449 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1452 ;; sign extension instructions
1454 (define_insn "extendqidi2"
1455 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1456 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1460 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1462 return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
1463 if (TARGET_68020 || TARGET_COLDFIRE)
1465 if (ADDRESS_REG_P (operands[1]))
1466 return "move%.w %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1468 return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1472 if (ADDRESS_REG_P (operands[1]))
1473 return "move%.w %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1475 return "move%.b %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1479 (define_insn "extendhidi2"
1480 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1482 (match_operand:HI 1 "general_src_operand" "rmS")))]
1486 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1488 return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
1489 if (TARGET_68020 || TARGET_COLDFIRE)
1490 return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
1492 return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0";
1495 (define_insn "extendsidi2"
1496 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1498 (match_operand:SI 1 "general_operand" "rm")))]
1502 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1503 if (TARGET_68020 || TARGET_COLDFIRE)
1504 return "move%.l %1,%2\;smi %0\;extb%.l %0";
1506 return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0";
1509 ;; Special case when one can avoid register clobbering, copy and test
1510 ;; Maybe there is a way to make that the general case, by forcing the
1511 ;; result of the SI tree to be in the lower register of the DI target
1513 (define_insn "extendplussidi"
1514 [(set (match_operand:DI 0 "register_operand" "=d")
1515 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1516 (match_operand:SI 2 "general_operand" "rmn"))))]
1520 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1521 if (GET_CODE (operands[1]) == CONST_INT
1522 && (unsigned) INTVAL (operands[1]) > 8)
1524 rtx tmp = operands[1];
1526 operands[1] = operands[2];
1529 if (GET_CODE (operands[1]) == REG
1530 && REGNO (operands[1]) == REGNO (operands[3]))
1531 output_asm_insn ("add%.l %2,%3", operands);
1533 output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands);
1534 if (TARGET_68020 || TARGET_COLDFIRE)
1535 return "smi %0\;extb%.l %0";
1537 return "smi %0\;ext%.w %0\;ext%.l %0";
1540 (define_expand "extendhisi2"
1541 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1543 (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1547 (define_insn "*cfv4_extendhisi2"
1548 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1550 (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1554 (define_insn "*68k_extendhisi2"
1555 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1557 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1560 if (ADDRESS_REG_P (operands[0]))
1561 return "move%.w %1,%0";
1565 (define_insn "extendqihi2"
1566 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1567 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1571 (define_expand "extendqisi2"
1572 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1573 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1574 "TARGET_68020 || TARGET_COLDFIRE"
1577 (define_insn "*cfv4_extendqisi2"
1578 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1579 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
1583 (define_insn "*68k_extendqisi2"
1584 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1585 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1586 "TARGET_68020 || (TARGET_COLDFIRE && !TARGET_ISAB)"
1589 ;; Conversions between float and double.
1591 (define_expand "extendsfdf2"
1592 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1594 (match_operand:SF 1 "general_operand" "")))]
1599 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1601 (match_operand:SF 1 "general_operand" "f,dmF")))]
1604 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1606 if (REGNO (operands[0]) == REGNO (operands[1]))
1608 /* Extending float to double in an fp-reg is a no-op.
1609 NOTICE_UPDATE_CC has already assumed that the
1610 cc will be set. So cancel what it did. */
1611 cc_status = cc_prev_status;
1614 return "f%&move%.x %1,%0";
1616 if (FP_REG_P (operands[0]))
1617 return "f%&move%.s %f1,%0";
1618 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1620 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1621 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1622 return "move%.l %+,%0";
1624 return "fmove%.d %f1,%0";
1627 (define_insn "extendsfdf2_cf"
1628 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
1630 (match_operand:SF 1 "general_operand" "f,<Q>U")))]
1631 "TARGET_COLDFIRE_FPU"
1633 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1635 if (REGNO (operands[0]) == REGNO (operands[1]))
1637 /* Extending float to double in an fp-reg is a no-op.
1638 NOTICE_UPDATE_CC has already assumed that the
1639 cc will be set. So cancel what it did. */
1640 cc_status = cc_prev_status;
1643 return "f%&move%.d %1,%0";
1645 return "f%&move%.s %f1,%0";
1648 ;; This cannot output into an f-reg because there is no way to be
1649 ;; sure of truncating in that case.
1650 (define_expand "truncdfsf2"
1651 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1653 (match_operand:DF 1 "general_operand" "")))]
1657 ;; On the '040 we can truncate in a register accurately and easily.
1659 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1661 (match_operand:DF 1 "general_operand" "fmG")))]
1662 "TARGET_68881 && TARGET_68040"
1664 if (FP_REG_P (operands[1]))
1665 return "f%$move%.x %1,%0";
1666 return "f%$move%.d %f1,%0";
1669 (define_insn "truncdfsf2_cf"
1670 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U")
1672 (match_operand:DF 1 "general_operand" "<Q>U,f")))]
1673 "TARGET_COLDFIRE_FPU"
1679 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1681 (match_operand:DF 1 "general_operand" "f")))]
1685 ;; Conversion between fixed point and floating point.
1686 ;; Note that among the fix-to-float insns
1687 ;; the ones that start with SImode come first.
1688 ;; That is so that an operand that is a CONST_INT
1689 ;; (and therefore lacks a specific machine mode).
1690 ;; will be recognized as SImode (which is always valid)
1691 ;; rather than as QImode or HImode.
1693 (define_expand "floatsi<mode>2"
1694 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1695 (float:FP (match_operand:SI 1 "general_operand" "")))]
1699 (define_insn "floatsi<mode>2_68881"
1700 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1701 (float:FP (match_operand:SI 1 "general_operand" "dmi")))]
1703 "f<FP:round>move%.l %1,%0")
1705 (define_insn "floatsi<mode>2_cf"
1706 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1707 (float:FP (match_operand:SI 1 "general_operand" "d<Q>U")))]
1708 "TARGET_COLDFIRE_FPU"
1709 "f<FP:prec>move%.l %1,%0")
1712 (define_expand "floathi<mode>2"
1713 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1714 (float:FP (match_operand:HI 1 "general_operand" "")))]
1718 (define_insn "floathi<mode>2_68881"
1719 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1720 (float:FP (match_operand:HI 1 "general_operand" "dmn")))]
1724 (define_insn "floathi<mode>2_cf"
1725 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1726 (float:FP (match_operand:HI 1 "general_operand" "d<Q>U")))]
1727 "TARGET_COLDFIRE_FPU"
1731 (define_expand "floatqi<mode>2"
1732 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1733 (float:FP (match_operand:QI 1 "general_operand" "")))]
1737 (define_insn "floatqi<mode>2_68881"
1738 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1739 (float:FP (match_operand:QI 1 "general_operand" "dmn")))]
1743 (define_insn "floatqi<mode>2_cf"
1744 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1745 (float:FP (match_operand:QI 1 "general_operand" "d<Q>U")))]
1746 "TARGET_COLDFIRE_FPU"
1750 ;; New routines to convert floating-point values to integers
1751 ;; to be used on the '040. These should be faster than trapping
1752 ;; into the kernel to emulate fintrz. They should also be faster
1753 ;; than calling the subroutines fixsfsi or fixdfsi.
1755 (define_insn "fix_truncdfsi2"
1756 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1757 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1758 (clobber (match_scratch:SI 2 "=d"))
1759 (clobber (match_scratch:SI 3 "=d"))]
1760 "TARGET_68881 && TUNE_68040"
1763 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!";
1766 (define_insn "fix_truncdfhi2"
1767 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1768 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1769 (clobber (match_scratch:SI 2 "=d"))
1770 (clobber (match_scratch:SI 3 "=d"))]
1771 "TARGET_68881 && TUNE_68040"
1774 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!";
1777 (define_insn "fix_truncdfqi2"
1778 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1779 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1780 (clobber (match_scratch:SI 2 "=d"))
1781 (clobber (match_scratch:SI 3 "=d"))]
1782 "TARGET_68881 && TUNE_68040"
1785 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!";
1788 ;; Convert a float to a float whose value is an integer.
1789 ;; This is the first stage of converting it to an integer type.
1791 (define_expand "ftrunc<mode>2"
1792 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1793 (fix:FP (match_operand:FP 1 "general_operand" "")))]
1794 "TARGET_HARD_FLOAT && !TUNE_68040"
1797 (define_insn "ftrunc<mode>2_68881"
1798 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1799 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
1800 "TARGET_68881 && !TUNE_68040"
1802 if (FP_REG_P (operands[1]))
1803 return "fintrz%.x %f1,%0";
1804 return "fintrz%.<FP:prec> %f1,%0";
1807 (define_insn "ftrunc<mode>2_cf"
1808 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1809 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
1810 "TARGET_COLDFIRE_FPU"
1812 if (FP_REG_P (operands[1]))
1813 return "fintrz%.d %f1,%0";
1814 return "fintrz%.<FP:prec> %f1,%0";
1817 ;; Convert a float whose value is an integer
1818 ;; to an actual integer. Second stage of converting float to integer type.
1819 (define_expand "fix<mode>qi2"
1820 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1821 (fix:QI (match_operand:FP 1 "general_operand" "")))]
1825 (define_insn "fix<mode>qi2_68881"
1826 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1827 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
1831 (define_insn "fix<mode>qi2_cf"
1832 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
1833 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
1834 "TARGET_COLDFIRE_FPU"
1837 (define_expand "fix<mode>hi2"
1838 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1839 (fix:HI (match_operand:FP 1 "general_operand" "")))]
1843 (define_insn "fix<mode>hi2_68881"
1844 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1845 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
1849 (define_insn "fix<mode>hi2_cf"
1850 [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
1851 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
1852 "TARGET_COLDFIRE_FPU"
1855 (define_expand "fix<mode>si2"
1856 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1857 (fix:SI (match_operand:FP 1 "general_operand" "")))]
1861 (define_insn "fix<mode>si2_68881"
1862 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1863 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
1867 (define_insn "fix<mode>si2_cf"
1868 [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
1869 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
1870 "TARGET_COLDFIRE_FPU"
1876 (define_insn "adddi_lshrdi_63"
1877 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1878 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1881 (clobber (match_scratch:SI 2 "=d"))]
1884 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1885 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1887 "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
1888 if (GET_CODE (operands[1]) == REG)
1889 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1890 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1891 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1892 operands[4] = operands[1];
1894 operands[4] = adjust_address (operands[1], SImode, 4);
1895 if (GET_CODE (operands[1]) == MEM
1896 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1897 output_asm_insn ("move%.l %4,%3", operands);
1898 output_asm_insn ("move%.l %1,%0\;smi %2", operands);
1899 if (TARGET_68020 || TARGET_COLDFIRE)
1900 output_asm_insn ("extb%.l %2", operands);
1902 output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
1903 if (GET_CODE (operands[1]) != MEM
1904 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1905 output_asm_insn ("move%.l %4,%3", operands);
1906 return "sub%.l %2,%3\;subx%.l %2,%0";
1909 (define_insn "adddi_sexthishl32"
1910 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
1911 (plus:DI (ashift:DI (sign_extend:DI
1912 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1914 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1915 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1919 if (ADDRESS_REG_P (operands[0]))
1920 return "add%.w %1,%0";
1921 else if (ADDRESS_REG_P (operands[3]))
1922 return "move%.w %1,%3\;add%.l %3,%0";
1924 return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
1927 (define_insn "adddi_dilshr32"
1928 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
1929 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1930 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1931 ;; (const_int 32))))]
1932 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
1934 (match_operand:DI 2 "general_operand" "0,0")))]
1938 if (GET_CODE (operands[0]) == REG)
1939 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1941 operands[2] = adjust_address (operands[0], SImode, 4);
1942 return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
1945 (define_insn "adddi_dishl32"
1946 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
1947 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1948 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1949 ;; (const_int 32))))]
1950 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
1952 (match_operand:DI 2 "general_operand" "0,0")))]
1956 if (GET_CODE (operands[1]) == REG)
1957 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1959 operands[1] = adjust_address (operands[1], SImode, 4);
1960 return "add%.l %1,%0";
1963 (define_insn "adddi3"
1964 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
1965 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
1966 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
1967 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
1970 if (DATA_REG_P (operands[0]))
1972 if (DATA_REG_P (operands[2]))
1973 return "add%.l %R2,%R0\;addx%.l %2,%0";
1974 else if (GET_CODE (operands[2]) == MEM
1975 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
1976 return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
1982 if (GET_CODE (operands[2]) == REG)
1984 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
1987 else if (CONSTANT_P (operands[2]))
1988 split_double (operands[2], &high, &low);
1991 low = adjust_address (operands[2], SImode, 4);
1995 operands[1] = low, operands[2] = high;
1996 xoperands[0] = operands[3];
1997 if (GET_CODE (operands[1]) == CONST_INT
1998 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1999 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2001 xoperands[1] = operands[2];
2003 output_asm_insn (output_move_simode (xoperands), xoperands);
2004 if (GET_CODE (operands[1]) == CONST_INT)
2006 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2007 return "addq%.l %1,%R0\;addx%.l %3,%0";
2008 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2010 operands[1] = GEN_INT (-INTVAL (operands[1]));
2011 return "subq%.l %1,%R0\;subx%.l %3,%0";
2014 return "add%.l %1,%R0\;addx%.l %3,%0";
2019 gcc_assert (GET_CODE (operands[0]) == MEM);
2020 if (GET_CODE (operands[2]) == MEM
2021 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2022 return "add%.l %2,%0\;addx%.l %2,%0";
2024 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2026 operands[1] = gen_rtx_MEM (SImode,
2027 plus_constant (XEXP(operands[0], 0), -8));
2028 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1";
2030 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2032 operands[1] = XEXP(operands[0], 0);
2033 return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1";
2037 operands[1] = adjust_address (operands[0], SImode, 4);
2038 return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0";
2043 (define_insn "addsi_lshrsi_31"
2044 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2045 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2050 operands[2] = operands[0];
2051 operands[3] = gen_label_rtx();
2052 if (GET_CODE (operands[0]) == MEM)
2054 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2055 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2056 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2057 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2059 output_asm_insn ("move%.l %1,%0", operands);
2060 output_asm_insn (MOTOROLA ? "jbpl %l3" : "jpl %l3", operands);
2061 output_asm_insn ("addq%.l #1,%2", operands);
2062 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2063 CODE_LABEL_NUMBER (operands[3]));
2067 (define_expand "addsi3"
2068 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2069 (plus:SI (match_operand:SI 1 "general_operand" "")
2070 (match_operand:SI 2 "general_src_operand" "")))]
2074 ;; Note that the middle two alternatives are near-duplicates
2075 ;; in order to handle insns generated by reload.
2076 ;; This is needed since they are not themselves reloaded,
2077 ;; so commutativity won't apply to them.
2078 (define_insn "*addsi3_internal"
2079 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2080 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2081 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2085 "* return output_addsi3 (operands);")
2087 (define_insn "*addsi3_5200"
2088 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
2089 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2090 (match_operand:SI 2 "general_src_operand" "dIL,rJK,a,mrIKLi")))]
2092 "* return output_addsi3 (operands);")
2095 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2096 (plus:SI (match_operand:SI 1 "general_operand" "0")
2098 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2102 (define_insn "addhi3"
2103 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2104 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2105 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2108 if (GET_CODE (operands[2]) == CONST_INT)
2110 /* If the constant would be a negative number when interpreted as
2111 HImode, make it negative. This is usually, but not always, done
2112 elsewhere in the compiler. First check for constants out of range,
2113 which could confuse us. */
2115 if (INTVAL (operands[2]) >= 32768)
2116 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2118 if (INTVAL (operands[2]) > 0
2119 && INTVAL (operands[2]) <= 8)
2120 return "addq%.w %2,%0";
2121 if (INTVAL (operands[2]) < 0
2122 && INTVAL (operands[2]) >= -8)
2124 operands[2] = GEN_INT (- INTVAL (operands[2]));
2125 return "subq%.w %2,%0";
2127 /* On the CPU32 it is faster to use two addqw instructions to
2128 add a small integer (8 < N <= 16) to a register.
2129 Likewise for subqw. */
2130 if (TUNE_CPU32 && REG_P (operands[0]))
2132 if (INTVAL (operands[2]) > 8
2133 && INTVAL (operands[2]) <= 16)
2135 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2136 return "addq%.w #8,%0\;addq%.w %2,%0";
2138 if (INTVAL (operands[2]) < -8
2139 && INTVAL (operands[2]) >= -16)
2141 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2142 return "subq%.w #8,%0\;subq%.w %2,%0";
2145 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2146 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2148 return "add%.w %2,%0";
2151 ;; These insns must use MATCH_DUP instead of the more expected
2152 ;; use of a matching constraint because the "output" here is also
2153 ;; an input, so you can't use the matching constraint. That also means
2154 ;; that you can't use the "%", so you need patterns with the matched
2155 ;; operand in both positions.
2158 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2159 (plus:HI (match_dup 0)
2160 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2163 if (GET_CODE (operands[1]) == CONST_INT)
2165 /* If the constant would be a negative number when interpreted as
2166 HImode, make it negative. This is usually, but not always, done
2167 elsewhere in the compiler. First check for constants out of range,
2168 which could confuse us. */
2170 if (INTVAL (operands[1]) >= 32768)
2171 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2173 if (INTVAL (operands[1]) > 0
2174 && INTVAL (operands[1]) <= 8)
2175 return "addq%.w %1,%0";
2176 if (INTVAL (operands[1]) < 0
2177 && INTVAL (operands[1]) >= -8)
2179 operands[1] = GEN_INT (- INTVAL (operands[1]));
2180 return "subq%.w %1,%0";
2182 /* On the CPU32 it is faster to use two addqw instructions to
2183 add a small integer (8 < N <= 16) to a register.
2184 Likewise for subqw. */
2185 if (TUNE_CPU32 && REG_P (operands[0]))
2187 if (INTVAL (operands[1]) > 8
2188 && INTVAL (operands[1]) <= 16)
2190 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2191 return "addq%.w #8,%0\;addq%.w %1,%0";
2193 if (INTVAL (operands[1]) < -8
2194 && INTVAL (operands[1]) >= -16)
2196 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2197 return "subq%.w #8,%0\;subq%.w %1,%0";
2200 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2201 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2203 return "add%.w %1,%0";
2207 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2208 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2212 if (GET_CODE (operands[1]) == CONST_INT)
2214 /* If the constant would be a negative number when interpreted as
2215 HImode, make it negative. This is usually, but not always, done
2216 elsewhere in the compiler. First check for constants out of range,
2217 which could confuse us. */
2219 if (INTVAL (operands[1]) >= 32768)
2220 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2222 if (INTVAL (operands[1]) > 0
2223 && INTVAL (operands[1]) <= 8)
2224 return "addq%.w %1,%0";
2225 if (INTVAL (operands[1]) < 0
2226 && INTVAL (operands[1]) >= -8)
2228 operands[1] = GEN_INT (- INTVAL (operands[1]));
2229 return "subq%.w %1,%0";
2231 /* On the CPU32 it is faster to use two addqw instructions to
2232 add a small integer (8 < N <= 16) to a register.
2233 Likewise for subqw. */
2234 if (TUNE_CPU32 && REG_P (operands[0]))
2236 if (INTVAL (operands[1]) > 8
2237 && INTVAL (operands[1]) <= 16)
2239 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2240 return "addq%.w #8,%0\;addq%.w %1,%0";
2242 if (INTVAL (operands[1]) < -8
2243 && INTVAL (operands[1]) >= -16)
2245 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2246 return "subq%.w #8,%0\;subq%.w %1,%0";
2249 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2250 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2252 return "add%.w %1,%0";
2255 (define_insn "addqi3"
2256 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2257 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2258 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2261 if (GET_CODE (operands[2]) == CONST_INT)
2263 if (INTVAL (operands[2]) >= 128)
2264 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2266 if (INTVAL (operands[2]) > 0
2267 && INTVAL (operands[2]) <= 8)
2268 return "addq%.b %2,%0";
2269 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2271 operands[2] = GEN_INT (- INTVAL (operands[2]));
2272 return "subq%.b %2,%0";
2275 return "add%.b %2,%0";
2279 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2280 (plus:QI (match_dup 0)
2281 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2284 if (GET_CODE (operands[1]) == CONST_INT)
2286 if (INTVAL (operands[1]) >= 128)
2287 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2289 if (INTVAL (operands[1]) > 0
2290 && INTVAL (operands[1]) <= 8)
2291 return "addq%.b %1,%0";
2292 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2294 operands[1] = GEN_INT (- INTVAL (operands[1]));
2295 return "subq%.b %1,%0";
2298 return "add%.b %1,%0";
2302 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2303 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2307 if (GET_CODE (operands[1]) == CONST_INT)
2309 if (INTVAL (operands[1]) >= 128)
2310 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2312 if (INTVAL (operands[1]) > 0
2313 && INTVAL (operands[1]) <= 8)
2314 return "addq%.b %1,%0";
2315 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2317 operands[1] = GEN_INT (- INTVAL (operands[1]));
2318 return "subq%.b %1,%0";
2321 return "add%.b %1,%0";
2324 (define_expand "add<mode>3"
2325 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2326 (plus:FP (match_operand:FP 1 "general_operand" "")
2327 (match_operand:FP 2 "general_operand" "")))]
2331 (define_insn "add<mode>3_floatsi_68881"
2332 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2333 (plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
2334 (match_operand:FP 1 "general_operand" "0")))]
2336 "f<FP:round>add%.l %2,%0")
2338 (define_insn "add<mode>3_floathi_68881"
2339 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2340 (plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
2341 (match_operand:FP 1 "general_operand" "0")))]
2343 "f<FP:round>add%.w %2,%0")
2345 (define_insn "add<mode>3_floatqi_68881"
2346 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2347 (plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
2348 (match_operand:FP 1 "general_operand" "0")))]
2350 "f<FP:round>add%.b %2,%0")
2352 (define_insn "add<mode>3_68881"
2353 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2354 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2355 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2358 if (FP_REG_P (operands[2]))
2359 return "f<FP:round>add%.x %2,%0";
2360 return "f<FP:round>add%.<FP:prec> %f2,%0";
2363 (define_insn "add<mode>3_cf"
2364 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2365 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2366 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2367 "TARGET_COLDFIRE_FPU"
2369 if (FP_REG_P (operands[2]))
2370 return "f<FP:round>add%.d %2,%0";
2371 return "f<FP:round>add%.<FP:prec> %2,%0";
2374 ;; subtract instructions
2376 (define_insn "subdi_sexthishl32"
2377 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2378 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2379 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2381 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2385 if (ADDRESS_REG_P (operands[0]))
2386 return "sub%.w %2,%0";
2387 else if (ADDRESS_REG_P (operands[3]))
2388 return "move%.w %2,%3\;sub%.l %3,%0";
2390 return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0";
2393 (define_insn "subdi_dishl32"
2394 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2395 (minus:DI (match_dup 0)
2396 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2401 if (GET_CODE (operands[1]) == REG)
2402 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2404 operands[1] = adjust_address (operands[1], SImode, 4);
2405 return "sub%.l %1,%0";
2408 (define_insn "subdi3"
2409 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
2410 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2411 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2412 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2415 if (DATA_REG_P (operands[0]))
2417 if (DATA_REG_P (operands[2]))
2418 return "sub%.l %R2,%R0\;subx%.l %2,%0";
2419 else if (GET_CODE (operands[2]) == MEM
2420 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2422 return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
2429 if (GET_CODE (operands[2]) == REG)
2431 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2434 else if (CONSTANT_P (operands[2]))
2435 split_double (operands[2], &high, &low);
2438 low = adjust_address (operands[2], SImode, 4);
2442 operands[1] = low, operands[2] = high;
2443 xoperands[0] = operands[3];
2444 if (GET_CODE (operands[1]) == CONST_INT
2445 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2446 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2448 xoperands[1] = operands[2];
2450 output_asm_insn (output_move_simode (xoperands), xoperands);
2451 if (GET_CODE (operands[1]) == CONST_INT)
2453 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2454 return "subq%.l %1,%R0\;subx%.l %3,%0";
2455 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2457 operands[1] = GEN_INT (-INTVAL (operands[1]));
2458 return "addq%.l %1,%R0\;addx%.l %3,%0";
2461 return "sub%.l %1,%R0\;subx%.l %3,%0";
2466 gcc_assert (GET_CODE (operands[0]) == MEM);
2467 if (GET_CODE (operands[2]) == MEM
2468 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2469 return "sub%.l %2,%0\;subx%.l %2,%0";
2471 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2474 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2475 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1";
2477 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2479 operands[1] = XEXP(operands[0], 0);
2480 return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1";
2484 operands[1] = adjust_address (operands[0], SImode, 4);
2485 return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0";
2490 (define_insn "subsi3"
2491 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
2492 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2493 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2498 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2499 (minus:SI (match_operand:SI 1 "general_operand" "0")
2501 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2505 (define_insn "subhi3"
2506 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2507 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2508 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2513 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2514 (minus:HI (match_dup 0)
2515 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2519 (define_insn "subqi3"
2520 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2521 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2522 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2527 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2528 (minus:QI (match_dup 0)
2529 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2533 (define_expand "sub<mode>3"
2534 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2535 (minus:FP (match_operand:FP 1 "general_operand" "")
2536 (match_operand:FP 2 "general_operand" "")))]
2540 (define_insn "sub<mode>3_floatsi_68881"
2541 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2542 (minus:FP (match_operand:FP 1 "general_operand" "0")
2543 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
2545 "f<FP:round>sub%.l %2,%0")
2547 (define_insn "sub<mode>3_floathi_68881"
2548 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2549 (minus:FP (match_operand:FP 1 "general_operand" "0")
2550 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
2552 "f<FP:round>sub%.w %2,%0")
2554 (define_insn "sub<mode>3_floatqi_68881"
2555 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2556 (minus:FP (match_operand:FP 1 "general_operand" "0")
2557 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
2559 "f<FP:round>sub%.b %2,%0")
2561 (define_insn "sub<mode>3_68881"
2562 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2563 (minus:FP (match_operand:FP 1 "general_operand" "0")
2564 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2567 if (FP_REG_P (operands[2]))
2568 return "f<FP:round>sub%.x %2,%0";
2569 return "f<FP:round>sub%.<FP:prec> %f2,%0";
2572 (define_insn "sub<mode>3_cf"
2573 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2574 (minus:FP (match_operand:FP 1 "general_operand" "0")
2575 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2576 "TARGET_COLDFIRE_FPU"
2578 if (FP_REG_P (operands[2]))
2579 return "f<FP:round>sub%.d %2,%0";
2580 return "f<FP:round>sub%.<FP:prec> %2,%0";
2583 ;; multiply instructions
2585 (define_insn "mulhi3"
2586 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2587 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2588 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2591 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2594 (define_insn "mulhisi3"
2595 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2596 (mult:SI (sign_extend:SI
2597 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2599 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2602 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2606 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2607 (mult:SI (sign_extend:SI
2608 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2609 (match_operand:SI 2 "const_int_operand" "n")))]
2610 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2612 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2615 (define_expand "mulsi3"
2616 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2617 (mult:SI (match_operand:SI 1 "general_operand" "")
2618 (match_operand:SI 2 "general_operand" "")))]
2619 "TARGET_68020 || TARGET_COLDFIRE"
2623 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2624 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2625 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
2631 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2632 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2633 (match_operand:SI 2 "general_operand" "d<Q>")))]
2637 (define_insn "umulhisi3"
2638 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2639 (mult:SI (zero_extend:SI
2640 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2642 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2645 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
2649 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2650 (mult:SI (zero_extend:SI
2651 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2652 (match_operand:SI 2 "const_int_operand" "n")))]
2653 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2655 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
2658 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2659 ;; proper matching constraint. This is because the matching is between
2660 ;; the high-numbered word of the DImode operand[0] and operand[1].
2661 (define_expand "umulsidi3"
2663 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2664 (mult:SI (match_operand:SI 1 "register_operand" "")
2665 (match_operand:SI 2 "register_operand" "")))
2666 (set (subreg:SI (match_dup 0) 0)
2667 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2668 (zero_extend:DI (match_dup 2)))
2669 (const_int 32))))])]
2670 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2674 [(set (match_operand:SI 0 "register_operand" "=d")
2675 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2676 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2677 (set (match_operand:SI 3 "register_operand" "=d")
2678 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2679 (zero_extend:DI (match_dup 2)))
2681 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2684 ; Match immediate case. For 2.4 only match things < 2^31.
2685 ; It's tricky with larger values in these patterns since we need to match
2686 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2689 [(set (match_operand:SI 0 "register_operand" "=d")
2690 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2691 (match_operand:SI 2 "const_int_operand" "n")))
2692 (set (match_operand:SI 3 "register_operand" "=d")
2693 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2696 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE
2697 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2700 (define_expand "mulsidi3"
2702 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2703 (mult:SI (match_operand:SI 1 "register_operand" "")
2704 (match_operand:SI 2 "register_operand" "")))
2705 (set (subreg:SI (match_dup 0) 0)
2706 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2707 (sign_extend:DI (match_dup 2)))
2708 (const_int 32))))])]
2709 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2713 [(set (match_operand:SI 0 "register_operand" "=d")
2714 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2715 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2716 (set (match_operand:SI 3 "register_operand" "=d")
2717 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2718 (sign_extend:DI (match_dup 2)))
2720 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2724 [(set (match_operand:SI 0 "register_operand" "=d")
2725 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2726 (match_operand:SI 2 "const_int_operand" "n")))
2727 (set (match_operand:SI 3 "register_operand" "=d")
2728 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2731 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2734 (define_expand "umulsi3_highpart"
2736 [(set (match_operand:SI 0 "register_operand" "")
2739 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2740 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2742 (clobber (match_dup 3))])]
2743 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2745 operands[3] = gen_reg_rtx (SImode);
2747 if (GET_CODE (operands[2]) == CONST_INT)
2749 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
2752 /* We have to adjust the operand order for the matching constraints. */
2753 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2754 operands[1], operands[2]));
2760 [(set (match_operand:SI 0 "register_operand" "=d")
2763 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2764 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2766 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2767 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2770 (define_insn "const_umulsi3_highpart"
2771 [(set (match_operand:SI 0 "register_operand" "=d")
2774 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2775 (match_operand:DI 3 "const_uint32_operand" "n"))
2777 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2778 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2781 (define_expand "smulsi3_highpart"
2783 [(set (match_operand:SI 0 "register_operand" "")
2786 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2787 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2789 (clobber (match_dup 3))])]
2790 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2792 operands[3] = gen_reg_rtx (SImode);
2793 if (GET_CODE (operands[2]) == CONST_INT)
2795 /* We have to adjust the operand order for the matching constraints. */
2796 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
2797 operands[1], operands[2]));
2803 [(set (match_operand:SI 0 "register_operand" "=d")
2806 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2807 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2809 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2810 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2813 (define_insn "const_smulsi3_highpart"
2814 [(set (match_operand:SI 0 "register_operand" "=d")
2817 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
2818 (match_operand:DI 3 "const_sint32_operand" "n"))
2820 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2821 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2824 (define_expand "mul<mode>3"
2825 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2826 (mult:FP (match_operand:FP 1 "general_operand" "")
2827 (match_operand:FP 2 "general_operand" "")))]
2831 (define_insn "mul<mode>3_floatsi_68881"
2832 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2833 (mult:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
2834 (match_operand:FP 1 "general_operand" "0")))]
2838 ? "f<FP:round>mul%.l %2,%0"
2839 : "f<FP:round_mul>mul%.l %2,%0";
2842 (define_insn "mul<mode>3_floathi_68881"
2843 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2844 (mult:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
2845 (match_operand:FP 1 "general_operand" "0")))]
2849 ? "f<FP:round>mul%.w %2,%0"
2850 : "f<FP:round_mul>mul%.w %2,%0";
2853 (define_insn "mul<mode>3_floatqi_68881"
2854 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2855 (mult:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
2856 (match_operand:FP 1 "general_operand" "0")))]
2860 ? "f<FP:round>mul%.b %2,%0"
2861 : "f<FP:round_mul>mul%.b %2,%0";
2864 (define_insn "muldf_68881"
2865 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2866 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2867 (match_operand:DF 2 "general_operand" "fmG")))]
2870 if (GET_CODE (operands[2]) == CONST_DOUBLE
2871 && floating_exact_log2 (operands[2]) && !TUNE_68040_60)
2873 int i = floating_exact_log2 (operands[2]);
2874 operands[2] = GEN_INT (i);
2875 return "fscale%.l %2,%0";
2877 if (REG_P (operands[2]))
2878 return "f%&mul%.x %2,%0";
2879 return "f%&mul%.d %f2,%0";
2882 (define_insn "mulsf_68881"
2883 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2884 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2885 (match_operand:SF 2 "general_operand" "fdmF")))]
2888 if (FP_REG_P (operands[2]))
2889 return (TARGET_68040
2891 : "fsglmul%.x %2,%0");
2892 return (TARGET_68040
2894 : "fsglmul%.s %f2,%0");
2897 (define_insn "mulxf3_68881"
2898 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
2899 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
2900 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
2903 return "fmul%.x %f2,%0";
2906 (define_insn "fmul<mode>3_cf"
2907 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2908 (mult:FP (match_operand:FP 1 "general_operand" "%0")
2909 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
2910 "TARGET_COLDFIRE_FPU"
2912 if (FP_REG_P (operands[2]))
2913 return "f<FP:prec>mul%.d %2,%0";
2914 return "f<FP:prec>mul%.<FP:prec> %2,%0";
2917 ;; divide instructions
2919 (define_expand "div<mode>3"
2920 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2921 (div:FP (match_operand:FP 1 "general_operand" "")
2922 (match_operand:FP 2 "general_operand" "")))]
2926 (define_insn "div<mode>3_floatsi_68881"
2927 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2928 (div:FP (match_operand:FP 1 "general_operand" "0")
2929 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
2933 ? "f<FP:round>div%.l %2,%0"
2934 : "f<FP:round_mul>div%.l %2,%0";
2937 (define_insn "div<mode>3_floathi_68881"
2938 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2939 (div:FP (match_operand:FP 1 "general_operand" "0")
2940 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
2944 ? "f<FP:round>div%.w %2,%0"
2945 : "f<FP:round_mul>div%.w %2,%0";
2948 (define_insn "div<mode>3_floatqi_68881"
2949 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2950 (div:FP (match_operand:FP 1 "general_operand" "0")
2951 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
2955 ? "f<FP:round>div%.b %2,%0"
2956 : "f<FP:round_mul>div%.b %2,%0";
2959 (define_insn "div<mode>3_68881"
2960 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2961 (div:FP (match_operand:FP 1 "general_operand" "0")
2962 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2965 if (FP_REG_P (operands[2]))
2966 return (TARGET_68040
2967 ? "f<FP:round>div%.x %2,%0"
2968 : "f<FP:round_mul>div%.x %2,%0");
2969 return (TARGET_68040
2970 ? "f<FP:round>div%.<FP:prec> %f2,%0"
2971 : "f<FP:round_mul>div%.<FP:prec> %f2,%0");
2974 (define_insn "div<mode>3_cf"
2975 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2976 (div:FP (match_operand:FP 1 "general_operand" "0")
2977 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
2978 "TARGET_COLDFIRE_FPU"
2980 if (FP_REG_P (operands[2]))
2981 return "f<FP:prec>div%.d %2,%0";
2982 return "f<FP:prec>div%.<FP:prec> %2,%0";
2985 ;; Remainder instructions.
2987 (define_expand "divmodsi4"
2989 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2990 (div:SI (match_operand:SI 1 "general_operand" "")
2991 (match_operand:SI 2 "general_src_operand" "")))
2992 (set (match_operand:SI 3 "nonimmediate_operand" "")
2993 (mod:SI (match_dup 1) (match_dup 2)))])]
2994 "TARGET_68020 || TARGET_CF_HWDIV"
2998 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2999 (div:SI (match_operand:SI 1 "general_operand" "0")
3000 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3001 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3002 (mod:SI (match_dup 1) (match_dup 2)))]
3005 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3006 return "divs%.l %2,%0";
3007 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3008 return "rems%.l %2,%3:%0";
3010 return "rems%.l %2,%3:%0\;divs%.l %2,%0";
3014 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3015 (div:SI (match_operand:SI 1 "general_operand" "0")
3016 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3017 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3018 (mod:SI (match_dup 1) (match_dup 2)))]
3021 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3022 return "divs%.l %2,%0";
3024 return "divsl%.l %2,%3:%0";
3027 (define_expand "udivmodsi4"
3029 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3030 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3031 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3032 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3033 (umod:SI (match_dup 1) (match_dup 2)))])]
3034 "TARGET_68020 || TARGET_CF_HWDIV"
3038 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3039 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3040 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3041 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3042 (umod:SI (match_dup 1) (match_dup 2)))]
3045 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3046 return "divu%.l %2,%0";
3047 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3048 return "remu%.l %2,%3:%0";
3050 return "remu%.l %2,%3:%0\;divu%.l %2,%0";
3054 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3055 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3056 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3057 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3058 (umod:SI (match_dup 1) (match_dup 2)))]
3059 "TARGET_68020 && !TARGET_COLDFIRE"
3061 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3062 return "divu%.l %2,%0";
3064 return "divul%.l %2,%3:%0";
3067 (define_insn "divmodhi4"
3068 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3069 (div:HI (match_operand:HI 1 "general_operand" "0")
3070 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3071 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3072 (mod:HI (match_dup 1) (match_dup 2)))]
3073 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3075 output_asm_insn (MOTOROLA ?
3076 "ext%.l %0\;divs%.w %2,%0" :
3077 "extl %0\;divs %2,%0",
3079 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3082 return "move%.l %0,%3\;swap %3";
3088 (define_insn "udivmodhi4"
3089 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3090 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3091 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3092 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3093 (umod:HI (match_dup 1) (match_dup 2)))]
3094 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3097 output_asm_insn (MOTOROLA ?
3098 "mvz%.w %0,%0\;divu%.w %2,%0" :
3099 "mvz%.w %0,%0\;divu %2,%0",
3102 output_asm_insn (MOTOROLA ?
3103 "and%.l #0xFFFF,%0\;divu%.w %2,%0" :
3104 "and%.l #0xFFFF,%0\;divu %2,%0",
3107 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3110 return "move%.l %0,%3\;swap %3";
3116 ;; logical-and instructions
3118 ;; "anddi3" is mainly here to help combine().
3119 (define_insn "anddi3"
3120 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3121 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3122 (match_operand:DI 2 "general_operand" "dn,don")))]
3126 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3127 if (CONSTANT_P (operands[2]))
3131 split_double (operands[2], &hi, &lo);
3133 switch (INTVAL (hi))
3136 output_asm_insn ("clr%.l %0", operands);
3144 xoperands[0] = operands[0];
3146 output_asm_insn (output_andsi3 (xoperands), xoperands);
3149 if (GET_CODE (operands[0]) == REG)
3150 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3152 operands[0] = adjust_address (operands[0], SImode, 4);
3153 switch (INTVAL (lo))
3156 output_asm_insn ("clr%.l %0", operands);
3164 xoperands[0] = operands[0];
3166 output_asm_insn (output_andsi3 (xoperands), xoperands);
3171 if (GET_CODE (operands[0]) != REG)
3173 operands[1] = adjust_address (operands[0], SImode, 4);
3174 return "and%.l %2,%0\;and%.l %R2,%1";
3176 if (GET_CODE (operands[2]) != REG)
3178 operands[1] = adjust_address (operands[2], SImode, 4);
3179 return "and%.l %2,%0\;and%.l %1,%R0";
3181 return "and%.l %2,%0\;and%.l %R2,%R0";
3184 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3185 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3186 ;; can't allocate pseudos into it.
3188 (define_expand "andsi3"
3189 [(set (match_operand:SI 0 "not_sp_operand" "")
3190 (and:SI (match_operand:SI 1 "general_operand" "")
3191 (match_operand:SI 2 "general_src_operand" "")))]
3195 ;; produced by split operations after reload finished
3196 (define_insn "*andsi3_split"
3197 [(set (match_operand:SI 0 "register_operand" "=d")
3198 (and:SI (match_operand:SI 1 "register_operand" "0")
3199 (match_operand:SI 2 "const_int_operand" "i")))]
3200 "reload_completed && !TARGET_COLDFIRE"
3202 return output_andsi3 (operands);
3205 (define_insn "andsi3_internal"
3206 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3207 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3208 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3211 return output_andsi3 (operands);
3214 (define_insn "andsi3_5200"
3215 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3216 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3217 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3221 && DATA_REG_P (operands[0])
3222 && GET_CODE (operands[2]) == CONST_INT)
3224 if (INTVAL (operands[2]) == 0x000000ff)
3225 return "mvz%.b %0,%0";
3226 else if (INTVAL (operands[2]) == 0x0000ffff)
3227 return "mvz%.w %0,%0";
3229 return output_andsi3 (operands);
3232 (define_insn "andhi3"
3233 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3234 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3235 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3240 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3241 (and:HI (match_dup 0)
3242 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3247 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3248 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3253 (define_insn "andqi3"
3254 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3255 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3256 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3261 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3262 (and:QI (match_dup 0)
3263 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3268 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3269 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3274 ;; inclusive-or instructions
3276 (define_insn "iordi_zext"
3277 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3278 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3279 (match_operand:DI 2 "general_operand" "0,0")))]
3285 if (GET_CODE (operands[0]) == REG)
3286 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3288 operands[0] = adjust_address (operands[0], SImode, 4);
3289 if (GET_MODE (operands[1]) == SImode)
3290 return "or%.l %1,%0";
3291 byte_mode = (GET_MODE (operands[1]) == QImode);
3292 if (GET_CODE (operands[0]) == MEM)
3293 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3296 return "or%.b %1,%0";
3298 return "or%.w %1,%0";
3301 ;; "iordi3" is mainly here to help combine().
3302 (define_insn "iordi3"
3303 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3304 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3305 (match_operand:DI 2 "general_operand" "dn,don")))]
3309 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3310 if (CONSTANT_P (operands[2]))
3314 split_double (operands[2], &hi, &lo);
3316 switch (INTVAL (hi))
3321 /* FIXME : a scratch register would be welcome here if operand[0]
3322 is not a register */
3323 output_asm_insn ("move%.l #-1,%0", operands);
3329 xoperands[0] = operands[0];
3331 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3334 if (GET_CODE (operands[0]) == REG)
3335 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3337 operands[0] = adjust_address (operands[0], SImode, 4);
3338 switch (INTVAL (lo))
3343 /* FIXME : a scratch register would be welcome here if operand[0]
3344 is not a register */
3345 output_asm_insn ("move%.l #-1,%0", operands);
3351 xoperands[0] = operands[0];
3353 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3358 if (GET_CODE (operands[0]) != REG)
3360 operands[1] = adjust_address (operands[0], SImode, 4);
3361 return "or%.l %2,%0\;or%.l %R2,%1";
3363 if (GET_CODE (operands[2]) != REG)
3365 operands[1] = adjust_address (operands[2], SImode, 4);
3366 return "or%.l %2,%0\;or%.l %1,%R0";
3368 return "or%.l %2,%0\;or%.l %R2,%R0";
3371 (define_expand "iorsi3"
3372 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3373 (ior:SI (match_operand:SI 1 "general_operand" "")
3374 (match_operand:SI 2 "general_src_operand" "")))]
3378 (define_insn "iorsi3_internal"
3379 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3380 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3381 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3384 return output_iorsi3 (operands);
3387 (define_insn "iorsi3_5200"
3388 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3389 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3390 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3393 return output_iorsi3 (operands);
3396 (define_insn "iorhi3"
3397 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3398 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3399 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3404 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3405 (ior:HI (match_dup 0)
3406 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3411 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3412 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3417 (define_insn "iorqi3"
3418 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3419 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3420 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3425 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3426 (ior:QI (match_dup 0)
3427 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3432 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3433 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3438 ;; On all 68k models, this makes faster code in a special case.
3439 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3441 (define_insn "iorsi_zexthi_ashl16"
3442 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3443 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3444 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3449 if (GET_CODE (operands[2]) != REG)
3450 operands[2] = adjust_address (operands[2], HImode, 2);
3451 if (GET_CODE (operands[2]) != REG
3452 || REGNO (operands[2]) != REGNO (operands[0]))
3453 output_asm_insn ("move%.w %2,%0", operands);
3454 return "swap %0\;mov%.w %1,%0";
3457 (define_insn "iorsi_zext"
3458 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3459 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3460 (match_operand:SI 2 "general_operand" "0,0")))]
3466 byte_mode = (GET_MODE (operands[1]) == QImode);
3467 if (GET_CODE (operands[0]) == MEM)
3468 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3471 return "or%.b %1,%0";
3473 return "or%.w %1,%0";
3478 ;; "xordi3" is mainly here to help combine().
3479 (define_insn "xordi3"
3480 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3481 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3482 (match_operand:DI 2 "general_operand" "dn")))]
3486 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3488 if (CONSTANT_P (operands[2]))
3492 split_double (operands[2], &hi, &lo);
3494 switch (INTVAL (hi))
3499 output_asm_insn ("not%.l %0", operands);
3502 /* FIXME : a scratch register would be welcome here if
3503 -128 <= INTVAL (hi) < -1 */
3507 xoperands[0] = operands[0];
3509 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3512 if (GET_CODE (operands[0]) == REG)
3513 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3515 operands[0] = adjust_address (operands[0], SImode, 4);
3516 switch (INTVAL (lo))
3521 output_asm_insn ("not%.l %0", operands);
3524 /* FIXME : a scratch register would be welcome here if
3525 -128 <= INTVAL (lo) < -1 */
3527 /* FIXME : this should be merged with xorsi3 */
3531 xoperands[0] = operands[0];
3533 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3538 if (GET_CODE (operands[0]) != REG)
3540 operands[1] = adjust_address (operands[0], SImode, 4);
3541 return "eor%.l %2,%0\;eor%.l %R2,%1";
3543 if (GET_CODE (operands[2]) != REG)
3545 operands[1] = adjust_address (operands[2], SImode, 4);
3546 return "eor%.l %2,%0\;eor%.l %1,%R0";
3548 return "eor%.l %2,%0\;eor%.l %R2,%R0";
3551 (define_expand "xorsi3"
3552 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3553 (xor:SI (match_operand:SI 1 "general_operand" "")
3554 (match_operand:SI 2 "general_operand" "")))]
3558 (define_insn "xorsi3_internal"
3559 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3560 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3561 (match_operand:SI 2 "general_operand" "di,dKT")))]
3565 return output_xorsi3 (operands);
3568 (define_insn "xorsi3_5200"
3569 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3570 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3571 (match_operand:SI 2 "general_operand" "d,Ks")))]
3574 return output_xorsi3 (operands);
3577 (define_insn "xorhi3"
3578 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3579 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3580 (match_operand:HI 2 "general_operand" "dn")))]
3585 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3586 (xor:HI (match_dup 0)
3587 (match_operand:HI 1 "general_operand" "dn")))]
3592 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3593 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3598 (define_insn "xorqi3"
3599 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3600 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3601 (match_operand:QI 2 "general_operand" "dn")))]
3606 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3607 (xor:QI (match_dup 0)
3608 (match_operand:QI 1 "general_operand" "dn")))]
3613 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3614 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3619 ;; negation instructions
3621 (define_expand "negdi2"
3622 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3623 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3626 if (TARGET_COLDFIRE)
3627 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3629 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3633 (define_insn "negdi2_internal"
3634 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
3635 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3638 if (which_alternative == 0)
3639 return "neg%.l %0\;negx%.l %0";
3640 if (GET_CODE (operands[0]) == REG)
3641 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3643 operands[1] = adjust_address (operands[0], SImode, 4);
3644 if (ADDRESS_REG_P (operands[0]))
3645 return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0";
3647 return "neg%.l %1\;negx%.l %0";
3650 (define_insn "negdi2_5200"
3651 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3652 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3655 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3656 return "neg%.l %1\;negx%.l %0";
3659 (define_expand "negsi2"
3660 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3661 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3664 if (TARGET_COLDFIRE)
3665 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3667 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3671 (define_insn "negsi2_internal"
3672 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3673 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3677 (define_insn "negsi2_5200"
3678 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3679 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3683 (define_insn "neghi2"
3684 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3685 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3690 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3691 (neg:HI (match_dup 0)))]
3695 (define_insn "negqi2"
3696 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3697 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3702 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3703 (neg:QI (match_dup 0)))]
3707 ;; If using software floating point, just flip the sign bit.
3709 (define_expand "negsf2"
3710 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3711 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3714 if (!TARGET_HARD_FLOAT)
3719 target = operand_subword_force (operands[0], 0, SFmode);
3720 result = expand_binop (SImode, xor_optab,
3721 operand_subword_force (operands[1], 0, SFmode),
3722 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
3723 gcc_assert (result);
3725 if (result != target)
3726 emit_move_insn (result, target);
3728 /* Make a place for REG_EQUAL. */
3729 emit_move_insn (operands[0], operands[0]);
3734 (define_expand "negdf2"
3735 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3736 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3739 if (!TARGET_HARD_FLOAT)
3746 target = operand_subword (operands[0], 0, 1, DFmode);
3747 result = expand_binop (SImode, xor_optab,
3748 operand_subword_force (operands[1], 0, DFmode),
3749 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
3750 gcc_assert (result);
3752 if (result != target)
3753 emit_move_insn (result, target);
3755 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3756 operand_subword_force (operands[1], 1, DFmode));
3758 insns = get_insns ();
3761 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3766 (define_expand "negxf2"
3767 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3768 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
3778 target = operand_subword (operands[0], 0, 1, XFmode);
3779 result = expand_binop (SImode, xor_optab,
3780 operand_subword_force (operands[1], 0, XFmode),
3781 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
3782 gcc_assert (result);
3784 if (result != target)
3785 emit_move_insn (result, target);
3787 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
3788 operand_subword_force (operands[1], 1, XFmode));
3789 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
3790 operand_subword_force (operands[1], 2, XFmode));
3792 insns = get_insns ();
3795 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3800 (define_insn "neg<mode>2_68881"
3801 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
3802 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
3805 if (DATA_REG_P (operands[0]))
3807 operands[1] = GEN_INT (31);
3808 return "bchg %1,%0";
3810 if (FP_REG_P (operands[1]))
3811 return "f<FP:round>neg%.x %1,%0";
3812 return "f<FP:round>neg%.<FP:prec> %f1,%0";
3815 (define_insn "neg<mode>2_cf"
3816 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
3817 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
3818 "TARGET_COLDFIRE_FPU"
3820 if (DATA_REG_P (operands[0]))
3822 operands[1] = GEN_INT (31);
3823 return "bchg %1,%0";
3825 if (FP_REG_P (operands[1]))
3826 return "f<FP:prec>neg%.d %1,%0";
3827 return "f<FP:prec>neg%.<FP:prec> %1,%0";
3830 ;; Sqrt instruction for the 68881
3832 (define_expand "sqrt<mode>2"
3833 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3834 (sqrt:FP (match_operand:FP 1 "general_operand" "")))]
3838 (define_insn "sqrt<mode>2_68881"
3839 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3840 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
3843 if (FP_REG_P (operands[1]))
3844 return "f<FP:round>sqrt%.x %1,%0";
3845 return "f<FP:round>sqrt%.<FP:prec> %1,%0";
3848 (define_insn "sqrt<mode>2_cf"
3849 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3850 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
3851 "TARGET_COLDFIRE_FPU"
3853 if (FP_REG_P (operands[1]))
3854 return "f<FP:prec>sqrt%.d %1,%0";
3855 return "f<FP:prec>sqrt%.<FP:prec> %1,%0";
3857 ;; Absolute value instructions
3858 ;; If using software floating point, just zero the sign bit.
3860 (define_expand "abssf2"
3861 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3862 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3865 if (!TARGET_HARD_FLOAT)
3870 target = operand_subword_force (operands[0], 0, SFmode);
3871 result = expand_binop (SImode, and_optab,
3872 operand_subword_force (operands[1], 0, SFmode),
3873 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3874 gcc_assert (result);
3876 if (result != target)
3877 emit_move_insn (result, target);
3879 /* Make a place for REG_EQUAL. */
3880 emit_move_insn (operands[0], operands[0]);
3885 (define_expand "absdf2"
3886 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3887 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3890 if (!TARGET_HARD_FLOAT)
3897 target = operand_subword (operands[0], 0, 1, DFmode);
3898 result = expand_binop (SImode, and_optab,
3899 operand_subword_force (operands[1], 0, DFmode),
3900 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3901 gcc_assert (result);
3903 if (result != target)
3904 emit_move_insn (result, target);
3906 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3907 operand_subword_force (operands[1], 1, DFmode));
3909 insns = get_insns ();
3912 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3917 (define_expand "absxf2"
3918 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3919 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
3929 target = operand_subword (operands[0], 0, 1, XFmode);
3930 result = expand_binop (SImode, and_optab,
3931 operand_subword_force (operands[1], 0, XFmode),
3932 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3933 gcc_assert (result);
3935 if (result != target)
3936 emit_move_insn (result, target);
3938 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
3939 operand_subword_force (operands[1], 1, XFmode));
3940 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
3941 operand_subword_force (operands[1], 2, XFmode));
3943 insns = get_insns ();
3946 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3951 (define_insn "abs<mode>2_68881"
3952 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
3953 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
3956 if (DATA_REG_P (operands[0]))
3958 operands[1] = GEN_INT (31);
3959 return "bclr %1,%0";
3961 if (FP_REG_P (operands[1]))
3962 return "f<FP:round>abs%.x %1,%0";
3963 return "f<FP:round>abs%.<FP:prec> %f1,%0";
3966 (define_insn "abs<mode>2_cf"
3967 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
3968 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
3969 "TARGET_COLDFIRE_FPU"
3971 if (DATA_REG_P (operands[0]))
3973 operands[1] = GEN_INT (31);
3974 return "bclr %1,%0";
3976 if (FP_REG_P (operands[1]))
3977 return "f<FP:prec>abs%.d %1,%0";
3978 return "f<FP:prec>abs%.<FP:prec> %1,%0";
3981 ;; one complement instructions
3983 ;; "one_cmpldi2" is mainly here to help combine().
3984 (define_insn "one_cmpldi2"
3985 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
3986 (not:DI (match_operand:DI 1 "general_operand" "0")))]
3990 if (GET_CODE (operands[0]) == REG)
3991 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3992 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
3993 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3994 operands[1] = operands[0];
3996 operands[1] = adjust_address (operands[0], SImode, 4);
3997 return "not%.l %1\;not%.l %0";
4000 (define_expand "one_cmplsi2"
4001 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4002 (not:SI (match_operand:SI 1 "general_operand" "")))]
4005 if (TARGET_COLDFIRE)
4006 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4008 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4012 (define_insn "one_cmplsi2_internal"
4013 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4014 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4018 (define_insn "one_cmplsi2_5200"
4019 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4020 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4024 (define_insn "one_cmplhi2"
4025 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4026 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4031 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4032 (not:HI (match_dup 0)))]
4036 (define_insn "one_cmplqi2"
4037 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4038 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4043 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4044 (not:QI (match_dup 0)))]
4048 ;; arithmetic shift instructions
4049 ;; We don't need the shift memory by 1 bit instruction
4051 (define_insn "ashldi_extsi"
4052 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4054 (match_operator:DI 2 "extend_operator"
4055 [(match_operand:SI 1 "general_operand" "rm")])
4060 if (GET_CODE (operands[0]) == REG)
4061 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4063 operands[2] = adjust_address (operands[0], SImode, 4);
4064 if (ADDRESS_REG_P (operands[0]))
4065 return "move%.l %1,%0\;sub%.l %2,%2";
4067 return "move%.l %1,%0\;clr%.l %2";
4070 (define_insn "ashldi_sexthi"
4071 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4072 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4074 (clobber (match_scratch:SI 2 "=a,X"))]
4078 if (GET_CODE (operands[0]) == MEM)
4080 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4081 return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
4082 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4083 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0";
4086 operands[3] = adjust_address (operands[0], SImode, 4);
4087 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3";
4090 else if (DATA_REG_P (operands[0]))
4091 return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0";
4093 return "move%.w %1,%0\;sub%.l %R0,%R0";
4096 (define_insn "ashldi_const32"
4097 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
4098 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4103 if (GET_CODE (operands[1]) == REG)
4104 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4106 operands[3] = adjust_address (operands[1], SImode, 4);
4107 if (GET_CODE (operands[0]) == REG)
4108 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4109 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4110 return "clr%.l %0\;move%.l %3,%0";
4111 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4112 return "move%.l %3,%0\;clr%.l %0";
4114 operands[2] = adjust_address (operands[0], SImode, 4);
4115 if (ADDRESS_REG_P (operands[2]))
4116 return "move%.l %3,%0\;sub%.l %2,%2";
4118 return "move%.l %3,%0\;clr%.l %2";
4121 ;; The predicate below must be general_operand, because ashldi3 allows that
4122 (define_insn "ashldi_const"
4123 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4124 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4125 (match_operand 2 "const_int_operand" "n")))]
4127 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4128 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4129 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4131 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4132 if (INTVAL (operands[2]) == 1)
4133 return "add%.l %1,%1\;addx%.l %0,%0";
4134 else if (INTVAL (operands[2]) == 8)
4135 return "rol%.l #8,%1\;rol%.l #8,%0\;move%.b %1,%0\;clr%.b %1";
4136 else if (INTVAL (operands[2]) == 16)
4137 return "swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1";
4138 else if (INTVAL (operands[2]) == 48)
4139 return "mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0";
4140 else if (INTVAL (operands[2]) == 2)
4141 return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
4142 else if (INTVAL (operands[2]) == 3)
4143 return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
4144 else /* 32 < INTVAL (operands[2]) <= 63 */
4146 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4147 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asl%.l %2,%1" :
4148 "moveq %2,%0\;asl%.l %0,%1", operands);
4149 return "mov%.l %1,%0\;moveq #0,%1";
4153 (define_expand "ashldi3"
4154 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4155 (ashift:DI (match_operand:DI 1 "general_operand" "")
4156 (match_operand 2 "const_int_operand" "")))]
4160 /* ??? This is a named pattern like this is not allowed to FAIL based
4162 if (GET_CODE (operands[2]) != CONST_INT
4163 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4164 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4165 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4169 ;; On most 68k models, this makes faster code in a special case.
4171 (define_insn "ashlsi_16"
4172 [(set (match_operand:SI 0 "register_operand" "=d")
4173 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4178 return "swap %0\;clr%.w %0";
4181 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4182 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4184 ;; On the 68000, this makes faster code in a special case.
4186 (define_insn "ashlsi_17_24"
4187 [(set (match_operand:SI 0 "register_operand" "=d")
4188 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4189 (match_operand:SI 2 "const_int_operand" "n")))]
4191 && INTVAL (operands[2]) > 16
4192 && INTVAL (operands[2]) <= 24"
4196 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4197 return "lsl%.w %2,%0\;swap %0\;clr%.w %0";
4200 (define_insn "ashlsi3"
4201 [(set (match_operand:SI 0 "register_operand" "=d")
4202 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4203 (match_operand:SI 2 "general_operand" "dI")))]
4206 if (operands[2] == const1_rtx)
4208 cc_status.flags = CC_NO_OVERFLOW;
4209 return "add%.l %0,%0";
4211 return "lsl%.l %2,%0";
4214 (define_insn "ashlhi3"
4215 [(set (match_operand:HI 0 "register_operand" "=d")
4216 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4217 (match_operand:HI 2 "general_operand" "dI")))]
4222 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4223 (ashift:HI (match_dup 0)
4224 (match_operand:HI 1 "general_operand" "dI")))]
4228 (define_insn "ashlqi3"
4229 [(set (match_operand:QI 0 "register_operand" "=d")
4230 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4231 (match_operand:QI 2 "general_operand" "dI")))]
4236 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4237 (ashift:QI (match_dup 0)
4238 (match_operand:QI 1 "general_operand" "dI")))]
4242 ;; On most 68k models, this makes faster code in a special case.
4244 (define_insn "ashrsi_16"
4245 [(set (match_operand:SI 0 "register_operand" "=d")
4246 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4249 "swap %0\;ext%.l %0")
4251 ;; On the 68000, this makes faster code in a special case.
4254 [(set (match_operand:SI 0 "register_operand" "=d")
4255 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4256 (match_operand:SI 2 "const_int_operand" "n")))]
4258 && INTVAL (operands[2]) > 16
4259 && INTVAL (operands[2]) <= 24"
4261 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4262 return "swap %0\;asr%.w %2,%0\;ext%.l %0";
4265 (define_insn "subreghi1ashrdi_const32"
4266 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4267 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4268 (const_int 32)) 6))]
4271 if (GET_CODE (operands[1]) != REG)
4272 operands[1] = adjust_address (operands[1], HImode, 2);
4273 return "move%.w %1,%0";
4276 (define_insn "subregsi1ashrdi_const32"
4277 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4278 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4279 (const_int 32)) 4))]
4282 return "move%.l %1,%0";
4285 (define_insn "ashrdi_const32"
4286 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,<")
4287 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4289 (clobber (match_scratch:SI 2 "=X,d,d"))]
4293 if (which_alternative == 0)
4295 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4297 return "move%.l %1,%2\;smi %0\;extb%.l %0";
4299 return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0";
4303 if (which_alternative == 2)
4304 operands[3] = operands[0];
4305 else if (which_alternative == 1)
4306 operands[3] = adjust_address (operands[0], SImode, 4);
4308 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
4310 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
4314 ;; The predicate below must be general_operand, because ashrdi3 allows that
4315 (define_insn "ashrdi_const"
4316 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4317 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4318 (match_operand 2 "const_int_operand" "n")))
4319 (clobber (match_scratch:SI 3 "=X"))]
4321 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4322 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4323 || INTVAL (operands[2]) == 31
4324 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4326 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4327 if (INTVAL (operands[2]) == 63)
4328 return "add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1";
4330 if (INTVAL (operands[2]) == 1)
4331 return "asr%.l #1,%0\;roxr%.l #1,%1";
4332 else if (INTVAL (operands[2]) == 8)
4333 return "move%.b %0,%1\;asr%.l #8,%0\;ror%.l #8,%1";
4334 else if (INTVAL (operands[2]) == 16)
4335 return "move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1";
4336 else if (INTVAL (operands[2]) == 48)
4337 return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
4338 else if (INTVAL (operands[2]) == 31)
4339 return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0";
4340 else if (INTVAL (operands[2]) == 2)
4341 return "asr%.l #1,%0\;roxr%.l #1,%1\;asr%.l #1,%0\;roxr%.l #1,%1";
4342 else if (INTVAL (operands[2]) == 3)
4343 return "asr%.l #1,%0\;roxr%.l #1,%1\;asr%.l #1,%0\;roxr%.l #1,%1\;asr%.l #1,%0\;roxr%.l #1,%1";
4344 else /* 32 < INTVAL (operands[2]) <= 63 */
4346 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4347 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" :
4348 "moveq %2,%1\;asr%.l %1,%0", operands);
4349 output_asm_insn ("mov%.l %0,%1\;smi %0", operands);
4350 return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" :
4351 TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0";
4355 (define_expand "ashrdi3"
4356 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4357 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4358 (match_operand 2 "const_int_operand" "")))
4359 (clobber (match_scratch:SI 3 ""))])]
4363 /* ??? This is a named pattern like this is not allowed to FAIL based
4365 if (GET_CODE (operands[2]) != CONST_INT
4366 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4367 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4368 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4370 operands[3] = gen_rtx_SCRATCH (SImode);
4373 ;; On all 68k models, this makes faster code in a special case.
4375 (define_insn "ashrsi_31"
4376 [(set (match_operand:SI 0 "register_operand" "=d")
4377 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4381 return "add%.l %0,%0\;subx%.l %0,%0";
4384 (define_insn "ashrsi3"
4385 [(set (match_operand:SI 0 "register_operand" "=d")
4386 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4387 (match_operand:SI 2 "general_operand" "dI")))]
4391 (define_insn "ashrhi3"
4392 [(set (match_operand:HI 0 "register_operand" "=d")
4393 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4394 (match_operand:HI 2 "general_operand" "dI")))]
4399 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4400 (ashiftrt:HI (match_dup 0)
4401 (match_operand:HI 1 "general_operand" "dI")))]
4405 (define_insn "ashrqi3"
4406 [(set (match_operand:QI 0 "register_operand" "=d")
4407 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4408 (match_operand:QI 2 "general_operand" "dI")))]
4413 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4414 (ashiftrt:QI (match_dup 0)
4415 (match_operand:QI 1 "general_operand" "dI")))]
4419 ;; logical shift instructions
4421 ;; commented out because of reload problems in 950612-1.c
4424 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4425 ;; (const_int 32)) 4))
4426 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4427 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4428 ;; (const_int 32)) 4))]
4431 ;; return "move%.l %0,%1";
4436 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4437 ;; (const_int 32)) 0))
4438 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4439 ;; (lshiftrt:DI (match_dup 0)
4440 ;; (const_int 32)))]
4443 ;; if (GET_CODE (operands[1]) == REG)
4444 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4446 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4447 ;; return "move%.l %0,%2\;clr%.l %1";
4450 (define_insn "subreg1lshrdi_const32"
4451 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4452 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4453 (const_int 32)) 4))]
4456 return "move%.l %1,%0";
4459 (define_insn "lshrdi_const32"
4460 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
4461 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4466 if (which_alternative == 1)
4467 return "move%.l %1,%0\;clr%.l %0";
4468 if (which_alternative == 2)
4469 return "clr%.l %0\;move%.l %1,%0";
4470 if (GET_CODE (operands[0]) == REG)
4471 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4473 operands[2] = adjust_address (operands[0], SImode, 4);
4474 if (GET_CODE (operands[1]) == REG)
4475 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4477 operands[3] = adjust_address (operands[1], SImode, 4);
4478 if (ADDRESS_REG_P (operands[0]))
4479 return "move%.l %1,%2\;sub%.l %0,%0";
4481 return "move%.l %1,%2\;clr%.l %0";
4484 ;; The predicate below must be general_operand, because lshrdi3 allows that
4485 (define_insn "lshrdi_const"
4486 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4487 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4488 (match_operand 2 "const_int_operand" "n")))]
4490 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4491 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4492 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4494 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4495 if (INTVAL (operands[2]) == 63)
4496 return "add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1";
4498 if (INTVAL (operands[2]) == 1)
4499 return "lsr%.l #1,%0\;roxr%.l #1,%1";
4500 else if (INTVAL (operands[2]) == 8)
4501 return "move%.b %0,%1\;lsr%.l #8,%0\;ror%.l #8,%1";
4502 else if (INTVAL (operands[2]) == 16)
4503 return "move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0";
4504 else if (INTVAL (operands[2]) == 48)
4505 return "move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1";
4506 else if (INTVAL (operands[2]) == 2)
4507 return "lsr%.l #1,%0\;roxr%.l #1,%1\;lsr%.l #1,%0\;roxr%.l #1,%1";
4508 else if (INTVAL (operands[2]) == 3)
4509 return "lsr%.l #1,%0\;roxr%.l #1,%1\;lsr%.l #1,%0\;roxr%.l #1,%1\;lsr%.l #1,%0\;roxr%.l #1,%1";
4510 else /* 32 < INTVAL (operands[2]) <= 63 */
4512 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4513 output_asm_insn (INTVAL (operands[2]) <= 8 ? "lsr%.l %2,%0" :
4514 "moveq %2,%1\;lsr%.l %1,%0", operands);
4515 return "mov%.l %0,%1\;moveq #0,%0";
4519 (define_expand "lshrdi3"
4520 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4521 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4522 (match_operand 2 "const_int_operand" "")))]
4525 /* ??? This is a named pattern like this is not allowed to FAIL based
4527 if (GET_CODE (operands[2]) != CONST_INT
4528 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4529 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4530 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4534 ;; On all 68k models, this makes faster code in a special case.
4536 (define_insn "lshrsi_31"
4537 [(set (match_operand:SI 0 "register_operand" "=d")
4538 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4542 return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0";
4545 ;; On most 68k models, this makes faster code in a special case.
4547 (define_insn "lshrsi_16"
4548 [(set (match_operand:SI 0 "register_operand" "=d")
4549 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4554 return "clr%.w %0\;swap %0";
4557 ;; On the 68000, this makes faster code in a special case.
4559 (define_insn "lshrsi_17_24"
4560 [(set (match_operand:SI 0 "register_operand" "=d")
4561 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4562 (match_operand:SI 2 "const_int_operand" "n")))]
4564 && INTVAL (operands[2]) > 16
4565 && INTVAL (operands[2]) <= 24"
4567 /* I think lsr%.w sets the CC properly. */
4568 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4569 return "clr%.w %0\;swap %0\;lsr%.w %2,%0";
4572 (define_insn "lshrsi3"
4573 [(set (match_operand:SI 0 "register_operand" "=d")
4574 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4575 (match_operand:SI 2 "general_operand" "dI")))]
4579 (define_insn "lshrhi3"
4580 [(set (match_operand:HI 0 "register_operand" "=d")
4581 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4582 (match_operand:HI 2 "general_operand" "dI")))]
4587 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4588 (lshiftrt:HI (match_dup 0)
4589 (match_operand:HI 1 "general_operand" "dI")))]
4593 (define_insn "lshrqi3"
4594 [(set (match_operand:QI 0 "register_operand" "=d")
4595 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4596 (match_operand:QI 2 "general_operand" "dI")))]
4601 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4602 (lshiftrt:QI (match_dup 0)
4603 (match_operand:QI 1 "general_operand" "dI")))]
4607 ;; rotate instructions
4609 (define_insn "rotlsi3"
4610 [(set (match_operand:SI 0 "register_operand" "=d")
4611 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4612 (match_operand:SI 2 "general_operand" "dINO")))]
4615 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4617 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4619 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4620 return "ror%.l %2,%0";
4623 return "rol%.l %2,%0";
4626 (define_insn "rotlhi3"
4627 [(set (match_operand:HI 0 "register_operand" "=d")
4628 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4629 (match_operand:HI 2 "general_operand" "dIP")))]
4632 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4634 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4635 return "ror%.w %2,%0";
4638 return "rol%.w %2,%0";
4642 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4643 (rotate:HI (match_dup 0)
4644 (match_operand:HI 1 "general_operand" "dIP")))]
4647 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4649 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4650 return "ror%.w %2,%0";
4653 return "rol%.w %2,%0";
4656 (define_insn "rotlqi3"
4657 [(set (match_operand:QI 0 "register_operand" "=d")
4658 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4659 (match_operand:QI 2 "general_operand" "dI")))]
4662 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4664 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4665 return "ror%.b %2,%0";
4668 return "rol%.b %2,%0";
4672 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4673 (rotate:QI (match_dup 0)
4674 (match_operand:QI 1 "general_operand" "dI")))]
4677 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4679 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4680 return "ror%.b %2,%0";
4683 return "rol%.b %2,%0";
4686 (define_insn "rotrsi3"
4687 [(set (match_operand:SI 0 "register_operand" "=d")
4688 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4689 (match_operand:SI 2 "general_operand" "dI")))]
4693 (define_insn "rotrhi3"
4694 [(set (match_operand:HI 0 "register_operand" "=d")
4695 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4696 (match_operand:HI 2 "general_operand" "dI")))]
4701 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4702 (rotatert:HI (match_dup 0)
4703 (match_operand:HI 1 "general_operand" "dI")))]
4707 (define_insn "rotrqi3"
4708 [(set (match_operand:QI 0 "register_operand" "=d")
4709 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4710 (match_operand:QI 2 "general_operand" "dI")))]
4715 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4716 (rotatert:QI (match_dup 0)
4717 (match_operand:QI 1 "general_operand" "dI")))]
4722 ;; Bit set/clear in memory byte.
4724 ;; set bit, bit number is int
4725 (define_insn "bsetmemqi"
4726 [(set (match_operand:QI 0 "memory_operand" "+m")
4727 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4728 (match_operand:SI 1 "general_operand" "d")) 3)
4733 return "bset %1,%0";
4736 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4738 [(set (match_operand:QI 0 "memory_operand" "+m")
4739 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4740 (match_operator:SI 2 "extend_operator"
4741 [(match_operand 1 "general_operand" "d")])) 3)
4746 return "bset %1,%0";
4749 ;; clear bit, bit number is int
4750 (define_insn "bclrmemqi"
4751 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4753 (minus:SI (const_int 7)
4754 (match_operand:SI 1 "general_operand" "d")))
4759 return "bclr %1,%0";
4762 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4764 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4766 (minus:SI (const_int 7)
4767 (match_operator:SI 2 "extend_operator"
4768 [(match_operand 1 "general_operand" "d")])))
4773 return "bclr %1,%0";
4776 ;; Special cases of bit-field insns which we should
4777 ;; recognize in preference to the general case.
4778 ;; These handle aligned 8-bit and 16-bit fields,
4779 ;; which can usually be done with move instructions.
4782 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4783 ; alignment of structure members is specified.
4785 ; The move is allowed to be odd byte aligned, because that's still faster
4786 ; than an odd byte aligned bit-field instruction.
4789 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4791 (match_operand:SI 1 "const_int_operand" "n"))
4792 (match_operand:SI 2 "general_src_operand" "rmSi"))]
4793 "TARGET_68020 && TARGET_BITFIELD
4794 && (INTVAL (operands[1]) % 8) == 0
4795 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4798 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
4800 return "move%.l %2,%0";
4804 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4805 (match_operand:SI 1 "const_int_operand" "n")
4806 (match_operand:SI 2 "const_int_operand" "n"))
4807 (match_operand:SI 3 "register_operand" "d"))]
4808 "TARGET_68020 && TARGET_BITFIELD
4809 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4810 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4811 && (GET_CODE (operands[0]) == REG
4812 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4814 if (REG_P (operands[0]))
4816 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4817 return "bfins %3,%0{%b2:%b1}";
4820 operands[0] = adjust_address (operands[0],
4821 INTVAL (operands[1]) == 8 ? QImode : HImode,
4822 INTVAL (operands[2]) / 8);
4824 if (GET_CODE (operands[3]) == MEM)
4825 operands[3] = adjust_address (operands[3],
4826 INTVAL (operands[1]) == 8 ? QImode : HImode,
4827 (32 - INTVAL (operands[1])) / 8);
4829 if (INTVAL (operands[1]) == 8)
4830 return "move%.b %3,%0";
4831 return "move%.w %3,%0";
4836 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4837 ; alignment of structure members is specified.
4839 ; The move is allowed to be odd byte aligned, because that's still faster
4840 ; than an odd byte aligned bit-field instruction.
4843 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4844 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4846 (match_operand:SI 2 "const_int_operand" "n")))]
4847 "TARGET_68020 && TARGET_BITFIELD
4848 && (INTVAL (operands[2]) % 8) == 0
4849 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4852 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4854 return "move%.l %1,%0";
4858 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
4859 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4860 (match_operand:SI 2 "const_int_operand" "n")
4861 (match_operand:SI 3 "const_int_operand" "n")))]
4862 "TARGET_68020 && TARGET_BITFIELD
4863 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4864 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4865 && (GET_CODE (operands[1]) == REG
4866 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4868 cc_status.flags |= CC_NOT_NEGATIVE;
4869 if (REG_P (operands[1]))
4871 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4872 return "bfextu %1{%b3:%b2},%0";
4876 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
4878 output_asm_insn ("clr%.l %0", operands);
4879 if (GET_CODE (operands[0]) == MEM)
4880 operands[0] = adjust_address (operands[0],
4881 INTVAL (operands[2]) == 8 ? QImode : HImode,
4882 (32 - INTVAL (operands[1])) / 8);
4884 if (INTVAL (operands[2]) == 8)
4885 return "move%.b %1,%0";
4886 return "move%.w %1,%0";
4890 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4891 ; alignment of structure members is specified.
4893 ; The move is allowed to be odd byte aligned, because that's still faster
4894 ; than an odd byte aligned bit-field instruction.
4897 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4898 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4900 (match_operand:SI 2 "const_int_operand" "n")))]
4901 "TARGET_68020 && TARGET_BITFIELD
4902 && (INTVAL (operands[2]) % 8) == 0
4903 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4906 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4908 return "move%.l %1,%0";
4912 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4913 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4914 (match_operand:SI 2 "const_int_operand" "n")
4915 (match_operand:SI 3 "const_int_operand" "n")))]
4916 "TARGET_68020 && TARGET_BITFIELD
4917 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4918 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4919 && (GET_CODE (operands[1]) == REG
4920 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4922 if (REG_P (operands[1]))
4924 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4925 return "bfexts %1{%b3:%b2},%0";
4929 = adjust_address (operands[1],
4930 INTVAL (operands[2]) == 8 ? QImode : HImode,
4931 INTVAL (operands[3]) / 8);
4933 if (INTVAL (operands[2]) == 8)
4934 return "move%.b %1,%0\;extb%.l %0";
4935 return "move%.w %1,%0\;ext%.l %0";
4938 ;; Bit-field instructions, general cases.
4939 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
4940 ;; so that its address is reloaded.
4942 (define_expand "extv"
4943 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4944 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
4945 (match_operand:SI 2 "general_operand" "")
4946 (match_operand:SI 3 "general_operand" "")))]
4947 "TARGET_68020 && TARGET_BITFIELD"
4951 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4952 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4953 (match_operand:SI 2 "general_operand" "dn")
4954 (match_operand:SI 3 "general_operand" "dn")))]
4955 "TARGET_68020 && TARGET_BITFIELD"
4956 "bfexts %1{%b3:%b2},%0")
4958 (define_expand "extzv"
4959 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4960 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
4961 (match_operand:SI 2 "general_operand" "")
4962 (match_operand:SI 3 "general_operand" "")))]
4963 "TARGET_68020 && TARGET_BITFIELD"
4967 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
4968 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
4969 (match_operand:SI 2 "general_operand" "dn,dn")
4970 (match_operand:SI 3 "general_operand" "dn,dn")))]
4971 "TARGET_68020 && TARGET_BITFIELD"
4973 if (GET_CODE (operands[2]) == CONST_INT)
4975 if (INTVAL (operands[2]) != 32)
4976 cc_status.flags |= CC_NOT_NEGATIVE;
4982 return "bfextu %1{%b3:%b2},%0";
4986 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4987 (match_operand:SI 1 "general_operand" "dn")
4988 (match_operand:SI 2 "general_operand" "dn"))
4989 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
4990 (match_operand 3 "const_int_operand" "n")))]
4991 "TARGET_68020 && TARGET_BITFIELD
4992 && (INTVAL (operands[3]) == -1
4993 || (GET_CODE (operands[1]) == CONST_INT
4994 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
4997 return "bfchg %0{%b2:%b1}";
5001 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5002 (match_operand:SI 1 "general_operand" "dn")
5003 (match_operand:SI 2 "general_operand" "dn"))
5005 "TARGET_68020 && TARGET_BITFIELD"
5008 return "bfclr %0{%b2:%b1}";
5012 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5013 (match_operand:SI 1 "general_operand" "dn")
5014 (match_operand:SI 2 "general_operand" "dn"))
5016 "TARGET_68020 && TARGET_BITFIELD"
5019 return "bfset %0{%b2:%b1}";
5022 (define_expand "insv"
5023 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5024 (match_operand:SI 1 "general_operand" "")
5025 (match_operand:SI 2 "general_operand" ""))
5026 (match_operand:SI 3 "register_operand" ""))]
5027 "TARGET_68020 && TARGET_BITFIELD"
5031 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5032 (match_operand:SI 1 "general_operand" "dn")
5033 (match_operand:SI 2 "general_operand" "dn"))
5034 (match_operand:SI 3 "register_operand" "d"))]
5035 "TARGET_68020 && TARGET_BITFIELD"
5036 "bfins %3,%0{%b2:%b1}")
5038 ;; Now recognize bit-field insns that operate on registers
5039 ;; (or at least were intended to do so).
5042 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5043 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5044 (match_operand:SI 2 "general_operand" "dn")
5045 (match_operand:SI 3 "general_operand" "dn")))]
5046 "TARGET_68020 && TARGET_BITFIELD"
5047 "bfexts %1{%b3:%b2},%0")
5050 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5051 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5052 (match_operand:SI 2 "general_operand" "dn")
5053 (match_operand:SI 3 "general_operand" "dn")))]
5054 "TARGET_68020 && TARGET_BITFIELD"
5056 if (GET_CODE (operands[2]) == CONST_INT)
5058 if (INTVAL (operands[2]) != 32)
5059 cc_status.flags |= CC_NOT_NEGATIVE;
5065 return "bfextu %1{%b3:%b2},%0";
5069 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5070 (match_operand:SI 1 "general_operand" "dn")
5071 (match_operand:SI 2 "general_operand" "dn"))
5073 "TARGET_68020 && TARGET_BITFIELD"
5076 return "bfclr %0{%b2:%b1}";
5080 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5081 (match_operand:SI 1 "general_operand" "dn")
5082 (match_operand:SI 2 "general_operand" "dn"))
5084 "TARGET_68020 && TARGET_BITFIELD"
5087 return "bfset %0{%b2:%b1}";
5091 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5092 (match_operand:SI 1 "general_operand" "dn")
5093 (match_operand:SI 2 "general_operand" "dn"))
5094 (match_operand:SI 3 "register_operand" "d"))]
5095 "TARGET_68020 && TARGET_BITFIELD"
5098 /* These special cases are now recognized by a specific pattern. */
5099 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5100 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5101 return "move%.w %3,%0";
5102 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5103 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5104 return "move%.b %3,%0";
5106 return "bfins %3,%0{%b2:%b1}";
5109 ;; Special patterns for optimizing bit-field instructions.
5113 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5114 (match_operand:SI 1 "const_int_operand" "n")
5115 (match_operand:SI 2 "general_operand" "dn")))]
5116 "TARGET_68020 && TARGET_BITFIELD"
5118 if (operands[1] == const1_rtx
5119 && GET_CODE (operands[2]) == CONST_INT)
5121 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5122 return output_btst (operands,
5123 GEN_INT (width - INTVAL (operands[2])),
5124 operands[0], insn, 1000);
5125 /* Pass 1000 as SIGNPOS argument so that btst will
5126 not think we are testing the sign bit for an `and'
5127 and assume that nonzero implies a negative result. */
5129 if (INTVAL (operands[1]) != 32)
5130 cc_status.flags = CC_NOT_NEGATIVE;
5131 return "bftst %0{%b2:%b1}";
5135 ;;; now handle the register cases
5138 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5139 (match_operand:SI 1 "const_int_operand" "n")
5140 (match_operand:SI 2 "general_operand" "dn")))]
5141 "TARGET_68020 && TARGET_BITFIELD"
5143 if (operands[1] == const1_rtx
5144 && GET_CODE (operands[2]) == CONST_INT)
5146 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5147 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5148 operands[0], insn, 1000);
5149 /* Pass 1000 as SIGNPOS argument so that btst will
5150 not think we are testing the sign bit for an `and'
5151 and assume that nonzero implies a negative result. */
5153 if (INTVAL (operands[1]) != 32)
5154 cc_status.flags = CC_NOT_NEGATIVE;
5155 return "bftst %0{%b2:%b1}";
5158 (define_insn "scc0_di"
5159 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5160 (match_operator 1 "valid_dbcc_comparison_p"
5161 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5164 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5167 (define_insn "scc0_di_5200"
5168 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5169 (match_operator 1 "valid_dbcc_comparison_p"
5170 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5173 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5176 (define_insn "scc_di"
5177 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5178 (match_operator 1 "valid_dbcc_comparison_p"
5179 [(match_operand:DI 2 "general_operand" "ro,r")
5180 (match_operand:DI 3 "general_operand" "r,ro")]))]
5183 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5186 (define_insn "scc_di_5200"
5187 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5188 (match_operator 1 "valid_dbcc_comparison_p"
5189 [(match_operand:DI 2 "general_operand" "ro,r")
5190 (match_operand:DI 3 "general_operand" "r,ro")]))]
5193 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5196 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5197 ;; memory, but we cannot allow it to be in memory in case the address
5198 ;; needs to be reloaded.
5200 (define_expand "seq"
5201 [(set (match_operand:QI 0 "register_operand" "")
5202 (eq:QI (cc0) (const_int 0)))]
5205 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5206 && m68k_last_compare_had_fp_operands)
5208 m68k_last_compare_had_fp_operands = 0;
5214 [(set (match_operand:QI 0 "register_operand" "=d")
5215 (eq:QI (cc0) (const_int 0)))]
5218 cc_status = cc_prev_status;
5219 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
5222 (define_expand "sne"
5223 [(set (match_operand:QI 0 "register_operand" "")
5224 (ne:QI (cc0) (const_int 0)))]
5227 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5228 && m68k_last_compare_had_fp_operands)
5230 m68k_last_compare_had_fp_operands = 0;
5236 [(set (match_operand:QI 0 "register_operand" "=d")
5237 (ne:QI (cc0) (const_int 0)))]
5240 cc_status = cc_prev_status;
5241 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
5244 (define_expand "sgt"
5245 [(set (match_operand:QI 0 "register_operand" "")
5246 (gt:QI (cc0) (const_int 0)))]
5249 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5250 && m68k_last_compare_had_fp_operands)
5252 m68k_last_compare_had_fp_operands = 0;
5258 [(set (match_operand:QI 0 "register_operand" "=d")
5259 (gt:QI (cc0) (const_int 0)))]
5262 cc_status = cc_prev_status;
5263 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
5266 (define_expand "sgtu"
5267 [(set (match_operand:QI 0 "register_operand" "")
5268 (gtu:QI (cc0) (const_int 0)))]
5273 [(set (match_operand:QI 0 "register_operand" "=d")
5274 (gtu:QI (cc0) (const_int 0)))]
5277 cc_status = cc_prev_status;
5281 (define_expand "slt"
5282 [(set (match_operand:QI 0 "register_operand" "")
5283 (lt:QI (cc0) (const_int 0)))]
5286 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5287 && m68k_last_compare_had_fp_operands)
5289 m68k_last_compare_had_fp_operands = 0;
5295 [(set (match_operand:QI 0 "register_operand" "=d")
5296 (lt:QI (cc0) (const_int 0)))]
5299 cc_status = cc_prev_status;
5300 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
5303 (define_expand "sltu"
5304 [(set (match_operand:QI 0 "register_operand" "")
5305 (ltu:QI (cc0) (const_int 0)))]
5310 [(set (match_operand:QI 0 "register_operand" "=d")
5311 (ltu:QI (cc0) (const_int 0)))]
5314 cc_status = cc_prev_status;
5318 (define_expand "sge"
5319 [(set (match_operand:QI 0 "register_operand" "")
5320 (ge:QI (cc0) (const_int 0)))]
5323 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5324 && m68k_last_compare_had_fp_operands)
5326 m68k_last_compare_had_fp_operands = 0;
5332 [(set (match_operand:QI 0 "register_operand" "=d")
5333 (ge:QI (cc0) (const_int 0)))]
5336 cc_status = cc_prev_status;
5337 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
5340 (define_expand "sgeu"
5341 [(set (match_operand:QI 0 "register_operand" "")
5342 (geu:QI (cc0) (const_int 0)))]
5347 [(set (match_operand:QI 0 "register_operand" "=d")
5348 (geu:QI (cc0) (const_int 0)))]
5351 cc_status = cc_prev_status;
5355 (define_expand "sle"
5356 [(set (match_operand:QI 0 "register_operand" "")
5357 (le:QI (cc0) (const_int 0)))]
5360 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5361 && m68k_last_compare_had_fp_operands)
5363 m68k_last_compare_had_fp_operands = 0;
5369 [(set (match_operand:QI 0 "register_operand" "=d")
5370 (le:QI (cc0) (const_int 0)))]
5373 cc_status = cc_prev_status;
5374 OUTPUT_JUMP ("sle %0", "fsle %0", 0);
5377 (define_expand "sleu"
5378 [(set (match_operand:QI 0 "register_operand" "")
5379 (leu:QI (cc0) (const_int 0)))]
5384 [(set (match_operand:QI 0 "register_operand" "=d")
5385 (leu:QI (cc0) (const_int 0)))]
5388 cc_status = cc_prev_status;
5392 (define_expand "sordered"
5393 [(set (match_operand:QI 0 "register_operand" "")
5394 (ordered:QI (cc0) (const_int 0)))]
5395 "TARGET_68881 && !TUNE_68060"
5397 gcc_assert (m68k_last_compare_had_fp_operands);
5398 m68k_last_compare_had_fp_operands = 0;
5401 (define_insn "*sordered_1"
5402 [(set (match_operand:QI 0 "register_operand" "=d")
5403 (ordered:QI (cc0) (const_int 0)))]
5404 "TARGET_68881 && !TUNE_68060"
5406 cc_status = cc_prev_status;
5410 (define_expand "sunordered"
5411 [(set (match_operand:QI 0 "register_operand" "")
5412 (unordered:QI (cc0) (const_int 0)))]
5413 "TARGET_68881 && !TUNE_68060"
5415 gcc_assert (m68k_last_compare_had_fp_operands);
5416 m68k_last_compare_had_fp_operands = 0;
5419 (define_insn "*sunordered_1"
5420 [(set (match_operand:QI 0 "register_operand" "=d")
5421 (unordered:QI (cc0) (const_int 0)))]
5422 "TARGET_68881 && !TUNE_68060"
5424 cc_status = cc_prev_status;
5428 (define_expand "suneq"
5429 [(set (match_operand:QI 0 "register_operand" "")
5430 (uneq:QI (cc0) (const_int 0)))]
5431 "TARGET_68881 && !TUNE_68060"
5433 gcc_assert (m68k_last_compare_had_fp_operands);
5434 m68k_last_compare_had_fp_operands = 0;
5437 (define_insn "*suneq_1"
5438 [(set (match_operand:QI 0 "register_operand" "=d")
5439 (uneq:QI (cc0) (const_int 0)))]
5440 "TARGET_68881 && !TUNE_68060"
5442 cc_status = cc_prev_status;
5446 (define_expand "sunge"
5447 [(set (match_operand:QI 0 "register_operand" "")
5448 (unge:QI (cc0) (const_int 0)))]
5449 "TARGET_68881 && !TUNE_68060"
5451 gcc_assert (m68k_last_compare_had_fp_operands);
5452 m68k_last_compare_had_fp_operands = 0;
5455 (define_insn "*sunge_1"
5456 [(set (match_operand:QI 0 "register_operand" "=d")
5457 (unge:QI (cc0) (const_int 0)))]
5458 "TARGET_68881 && !TUNE_68060"
5460 cc_status = cc_prev_status;
5464 (define_expand "sungt"
5465 [(set (match_operand:QI 0 "register_operand" "")
5466 (ungt:QI (cc0) (const_int 0)))]
5467 "TARGET_68881 && !TUNE_68060"
5469 gcc_assert (m68k_last_compare_had_fp_operands);
5470 m68k_last_compare_had_fp_operands = 0;
5473 (define_insn "*sungt_1"
5474 [(set (match_operand:QI 0 "register_operand" "=d")
5475 (ungt:QI (cc0) (const_int 0)))]
5476 "TARGET_68881 && !TUNE_68060"
5478 cc_status = cc_prev_status;
5482 (define_expand "sunle"
5483 [(set (match_operand:QI 0 "register_operand" "")
5484 (unle:QI (cc0) (const_int 0)))]
5485 "TARGET_68881 && !TUNE_68060"
5487 gcc_assert (m68k_last_compare_had_fp_operands);
5488 m68k_last_compare_had_fp_operands = 0;
5491 (define_insn "*sunle_1"
5492 [(set (match_operand:QI 0 "register_operand" "=d")
5493 (unle:QI (cc0) (const_int 0)))]
5494 "TARGET_68881 && !TUNE_68060"
5496 cc_status = cc_prev_status;
5500 (define_expand "sunlt"
5501 [(set (match_operand:QI 0 "register_operand" "")
5502 (unlt:QI (cc0) (const_int 0)))]
5503 "TARGET_68881 && !TUNE_68060"
5505 gcc_assert (m68k_last_compare_had_fp_operands);
5506 m68k_last_compare_had_fp_operands = 0;
5509 (define_insn "*sunlt_1"
5510 [(set (match_operand:QI 0 "register_operand" "=d")
5511 (unlt:QI (cc0) (const_int 0)))]
5512 "TARGET_68881 && !TUNE_68060"
5514 cc_status = cc_prev_status;
5518 (define_expand "sltgt"
5519 [(set (match_operand:QI 0 "register_operand" "")
5520 (ltgt:QI (cc0) (const_int 0)))]
5521 "TARGET_68881 && !TUNE_68060"
5523 gcc_assert (m68k_last_compare_had_fp_operands);
5524 m68k_last_compare_had_fp_operands = 0;
5527 (define_insn "*sltgt_1"
5528 [(set (match_operand:QI 0 "register_operand" "=d")
5529 (ltgt:QI (cc0) (const_int 0)))]
5530 "TARGET_68881 && !TUNE_68060"
5532 cc_status = cc_prev_status;
5536 (define_insn "*fsogt_1"
5537 [(set (match_operand:QI 0 "register_operand" "=d")
5538 (not:QI (unle:QI (cc0) (const_int 0))))]
5539 "TARGET_68881 && !TUNE_68060"
5541 cc_status = cc_prev_status;
5545 (define_insn "*fsoge_1"
5546 [(set (match_operand:QI 0 "register_operand" "=d")
5547 (not:QI (unlt:QI (cc0) (const_int 0))))]
5548 "TARGET_68881 && !TUNE_68060"
5550 cc_status = cc_prev_status;
5554 (define_insn "*fsolt_1"
5555 [(set (match_operand:QI 0 "register_operand" "=d")
5556 (not:QI (unge:QI (cc0) (const_int 0))))]
5557 "TARGET_68881 && !TUNE_68060"
5559 cc_status = cc_prev_status;
5563 (define_insn "*fsole_1"
5564 [(set (match_operand:QI 0 "register_operand" "=d")
5565 (not:QI (ungt:QI (cc0) (const_int 0))))]
5566 "TARGET_68881 && !TUNE_68060"
5568 cc_status = cc_prev_status;
5572 ;; Basic conditional jump instructions.
5574 (define_insn "beq0_di"
5576 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5578 (label_ref (match_operand 1 "" ","))
5580 (clobber (match_scratch:SI 2 "=d,d"))]
5584 if (which_alternative == 1)
5587 return "move%.l %0,%2\;or%.l %0,%2\;jbeq %l1";
5589 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
5591 if ((cc_prev_status.value1
5592 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5593 || (cc_prev_status.value2
5594 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5596 cc_status = cc_prev_status;
5597 return MOTOROLA ? "jbeq %l1" : "jeq %l1";
5599 if (GET_CODE (operands[0]) == REG)
5600 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5602 operands[3] = adjust_address (operands[0], SImode, 4);
5603 if (! ADDRESS_REG_P (operands[0]))
5605 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5607 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5610 return "or%.l %0,%2\;jbeq %l1";
5612 return "or%.l %0,%2\;jeq %l1";
5617 return "or%.l %3,%2\;jbeq %l1";
5619 return "or%.l %3,%2\;jeq %l1";
5623 return "move%.l %0,%2\;or%.l %3,%2\;jbeq %l1";
5625 return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
5627 operands[4] = gen_label_rtx();
5628 if (TARGET_68020 || TARGET_COLDFIRE)
5631 output_asm_insn ("tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1", operands);
5633 output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
5638 output_asm_insn ("cmp%.w #0,%0\;jbne %l4\;cmp%.w #0,%3\;jbeq %l1", operands);
5640 output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands);
5642 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5643 CODE_LABEL_NUMBER (operands[4]));
5647 (define_insn "bne0_di"
5649 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5651 (label_ref (match_operand 1 "" ","))
5653 (clobber (match_scratch:SI 2 "=d,X"))]
5656 if ((cc_prev_status.value1
5657 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5658 || (cc_prev_status.value2
5659 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5661 cc_status = cc_prev_status;
5662 return MOTOROLA ? "jbne %l1" : "jne %l1";
5665 if (GET_CODE (operands[0]) == REG)
5666 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5668 operands[3] = adjust_address (operands[0], SImode, 4);
5669 if (!ADDRESS_REG_P (operands[0]))
5671 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5673 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5676 return "or%.l %0,%2\;jbne %l1";
5678 return "or%.l %0,%2\;jne %l1";
5683 return "or%.l %3,%2\;jbne %l1";
5685 return "or%.l %3,%2\;jne %l1";
5689 return "move%.l %0,%2\;or%.l %3,%2\;jbne %l1";
5691 return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
5693 if (TARGET_68020 || TARGET_COLDFIRE)
5696 return "tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1";
5698 return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
5703 return "cmp%.w #0,%0\;jbne %l1\;cmp%.w #0,%3\;jbne %l1";
5705 return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1";
5709 (define_insn "bge0_di"
5711 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5713 (label_ref (match_operand 1 "" ""))
5717 if ((cc_prev_status.value1
5718 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5719 || (cc_prev_status.value2
5720 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5722 cc_status = cc_prev_status;
5723 if (cc_status.flags & CC_REVERSED)
5725 return MOTOROLA ? "jble %l1" : "jle %l1";
5729 return MOTOROLA ? "jbpl %l1" : "jpl %l1";
5733 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5734 output_asm_insn("tst%.l %0", operands);
5737 /* On an address reg, cmpw may replace cmpl. */
5738 output_asm_insn("cmp%.w #0,%0", operands);
5740 return MOTOROLA ? "jbpl %l1" : "jpl %l1";
5743 (define_insn "blt0_di"
5745 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5747 (label_ref (match_operand 1 "" ""))
5751 if ((cc_prev_status.value1
5752 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5753 || (cc_prev_status.value2
5754 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5756 cc_status = cc_prev_status;
5757 if (cc_status.flags & CC_REVERSED)
5759 return MOTOROLA ? "jbgt %l1" : "jgt %l1";
5763 return MOTOROLA ? "jbmi %l1" : "jmi %l1";
5767 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5768 output_asm_insn("tst%.l %0", operands);
5771 /* On an address reg, cmpw may replace cmpl. */
5772 output_asm_insn("cmp%.w #0,%0", operands);
5775 return MOTOROLA ? "jbmi %l1" : "jmi %l1";
5780 (if_then_else (eq (cc0)
5782 (label_ref (match_operand 0 "" ""))
5787 OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
5789 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
5794 (if_then_else (ne (cc0)
5796 (label_ref (match_operand 0 "" ""))
5801 OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
5803 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
5808 (if_then_else (gt (cc0)
5810 (label_ref (match_operand 0 "" ""))
5815 OUTPUT_JUMP ("jbgt %l0", "fbgt %l0", 0);
5817 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
5822 (if_then_else (gtu (cc0)
5824 (label_ref (match_operand 0 "" ""))
5828 return MOTOROLA ? "jbhi %l0" : "jhi %l0";
5833 (if_then_else (lt (cc0)
5835 (label_ref (match_operand 0 "" ""))
5840 OUTPUT_JUMP ("jblt %l0", "fblt %l0", "jbmi %l0");
5842 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
5847 (if_then_else (ltu (cc0)
5849 (label_ref (match_operand 0 "" ""))
5853 return MOTOROLA ? "jbcs %l0" : "jcs %l0";
5858 (if_then_else (ge (cc0)
5860 (label_ref (match_operand 0 "" ""))
5865 OUTPUT_JUMP ("jbge %l0", "fbge %l0", "jbpl %l0");
5867 OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
5872 (if_then_else (geu (cc0)
5874 (label_ref (match_operand 0 "" ""))
5878 return MOTOROLA ? "jbcc %l0" : "jcc %l0";
5883 (if_then_else (le (cc0)
5885 (label_ref (match_operand 0 "" ""))
5890 OUTPUT_JUMP ("jble %l0", "fble %l0", 0);
5892 OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
5897 (if_then_else (leu (cc0)
5899 (label_ref (match_operand 0 "" ""))
5903 return MOTOROLA ? "jbls %l0" : "jls %l0";
5906 (define_insn "bordered"
5908 (if_then_else (ordered (cc0) (const_int 0))
5909 (label_ref (match_operand 0 "" ""))
5913 gcc_assert (cc_prev_status.flags & CC_IN_68881);
5914 return MOTOROLA ? "fbor %l0" : "fjor %l0";
5917 (define_insn "bunordered"
5919 (if_then_else (unordered (cc0) (const_int 0))
5920 (label_ref (match_operand 0 "" ""))
5924 gcc_assert (cc_prev_status.flags & CC_IN_68881);
5925 return MOTOROLA ? "fbun %l0" : "fjun %l0";
5928 (define_insn "buneq"
5930 (if_then_else (uneq (cc0) (const_int 0))
5931 (label_ref (match_operand 0 "" ""))
5935 gcc_assert (cc_prev_status.flags & CC_IN_68881);
5936 return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
5939 (define_insn "bunge"
5941 (if_then_else (unge (cc0) (const_int 0))
5942 (label_ref (match_operand 0 "" ""))
5946 gcc_assert (cc_prev_status.flags & CC_IN_68881);
5947 return MOTOROLA ? "fbuge %l0" : "fjuge %l0";
5950 (define_insn "bungt"
5952 (if_then_else (ungt (cc0) (const_int 0))
5953 (label_ref (match_operand 0 "" ""))
5957 gcc_assert (cc_prev_status.flags & CC_IN_68881);
5958 return MOTOROLA ? "fbugt %l0" : "fjugt %l0";
5961 (define_insn "bunle"
5963 (if_then_else (unle (cc0) (const_int 0))
5964 (label_ref (match_operand 0 "" ""))
5968 gcc_assert (cc_prev_status.flags & CC_IN_68881);
5969 return MOTOROLA ? "fbule %l0" : "fjule %l0";
5972 (define_insn "bunlt"
5974 (if_then_else (unlt (cc0) (const_int 0))
5975 (label_ref (match_operand 0 "" ""))
5979 gcc_assert (cc_prev_status.flags & CC_IN_68881);
5980 return MOTOROLA ? "fbult %l0" : "fjult %l0";
5983 (define_insn "bltgt"
5985 (if_then_else (ltgt (cc0) (const_int 0))
5986 (label_ref (match_operand 0 "" ""))
5990 gcc_assert (cc_prev_status.flags & CC_IN_68881);
5991 return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
5994 ;; Negated conditional jump instructions.
5998 (if_then_else (eq (cc0)
6001 (label_ref (match_operand 0 "" ""))))]
6005 OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
6007 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6012 (if_then_else (ne (cc0)
6015 (label_ref (match_operand 0 "" ""))))]
6019 OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
6021 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6026 (if_then_else (gt (cc0)
6029 (label_ref (match_operand 0 "" ""))))]
6033 OUTPUT_JUMP ("jble %l0", "fbngt %l0", 0);
6035 OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
6040 (if_then_else (gtu (cc0)
6043 (label_ref (match_operand 0 "" ""))))]
6046 return MOTOROLA ? "jbls %l0" : "jls %l0";
6051 (if_then_else (lt (cc0)
6054 (label_ref (match_operand 0 "" ""))))]
6058 OUTPUT_JUMP ("jbge %l0", "fbnlt %l0", "jbpl %l0");
6060 OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
6065 (if_then_else (ltu (cc0)
6068 (label_ref (match_operand 0 "" ""))))]
6071 return MOTOROLA ? "jbcc %l0" : "jcc %l0";
6076 (if_then_else (ge (cc0)
6079 (label_ref (match_operand 0 "" ""))))]
6083 OUTPUT_JUMP ("jblt %l0", "fbnge %l0", "jbmi %l0");
6085 OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
6090 (if_then_else (geu (cc0)
6093 (label_ref (match_operand 0 "" ""))))]
6096 return MOTOROLA ? "jbcs %l0" : "jcs %l0";
6101 (if_then_else (le (cc0)
6104 (label_ref (match_operand 0 "" ""))))]
6108 OUTPUT_JUMP ("jbgt %l0", "fbnle %l0", 0);
6110 OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
6115 (if_then_else (leu (cc0)
6118 (label_ref (match_operand 0 "" ""))))]
6121 return MOTOROLA ? "jbhi %l0" : "jhi %l0";
6124 (define_insn "*bordered_rev"
6126 (if_then_else (ordered (cc0) (const_int 0))
6128 (label_ref (match_operand 0 "" ""))))]
6131 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6132 return MOTOROLA ? "fbun %l0" : "fjun %l0";
6135 (define_insn "*bunordered_rev"
6137 (if_then_else (unordered (cc0) (const_int 0))
6139 (label_ref (match_operand 0 "" ""))))]
6142 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6143 return MOTOROLA ? "fbor %l0" : "fjor %l0";
6146 (define_insn "*buneq_rev"
6148 (if_then_else (uneq (cc0) (const_int 0))
6150 (label_ref (match_operand 0 "" ""))))]
6153 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6154 return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
6157 (define_insn "*bunge_rev"
6159 (if_then_else (unge (cc0) (const_int 0))
6161 (label_ref (match_operand 0 "" ""))))]
6164 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6165 return MOTOROLA ? "fbolt %l0" : "fjolt %l0";
6168 (define_insn "*bungt_rev"
6170 (if_then_else (ungt (cc0) (const_int 0))
6172 (label_ref (match_operand 0 "" ""))))]
6175 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6176 return MOTOROLA ? "fbole %l0" : "fjole %l0";
6179 (define_insn "*bunle_rev"
6181 (if_then_else (unle (cc0) (const_int 0))
6183 (label_ref (match_operand 0 "" ""))))]
6186 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6187 return MOTOROLA ? "fbogt %l0" : "fjogt %l0";
6190 (define_insn "*bunlt_rev"
6192 (if_then_else (unlt (cc0) (const_int 0))
6194 (label_ref (match_operand 0 "" ""))))]
6197 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6198 return MOTOROLA ? "fboge %l0" : "fjoge %l0";
6201 (define_insn "*bltgt_rev"
6203 (if_then_else (ltgt (cc0) (const_int 0))
6205 (label_ref (match_operand 0 "" ""))))]
6208 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6209 return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
6212 ;; Unconditional and other jump instructions
6215 (label_ref (match_operand 0 "" "")))]
6218 return MOTOROLA ? "jbra %l0" : "jra %l0";
6221 (define_expand "tablejump"
6222 [(parallel [(set (pc) (match_operand 0 "" ""))
6223 (use (label_ref (match_operand 1 "" "")))])]
6226 #ifdef CASE_VECTOR_PC_RELATIVE
6227 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6228 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6232 ;; Jump to variable address from dispatch table of absolute addresses.
6234 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6235 (use (label_ref (match_operand 1 "" "")))]
6238 return MOTOROLA ? "jmp (%0)" : "jmp %0@";
6241 ;; Jump to variable address from dispatch table of relative addresses.
6245 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6246 (use (label_ref (match_operand 1 "" "")))]
6249 #ifdef ASM_RETURN_CASE_JUMP
6250 ASM_RETURN_CASE_JUMP;
6252 if (TARGET_COLDFIRE)
6254 if (ADDRESS_REG_P (operands[0]))
6255 return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
6257 return "ext%.l %0\;jmp (2,pc,%0.l)";
6259 return "extl %0\;jmp pc@(2,%0:l)";
6262 return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
6266 ;; Decrement-and-branch insns.
6270 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6272 (label_ref (match_operand 1 "" ""))
6275 (plus:HI (match_dup 0)
6280 if (DATA_REG_P (operands[0]))
6281 return "dbra %0,%l1";
6282 if (GET_CODE (operands[0]) == MEM)
6284 "subq%.w #1,%0\;jbcc %l1" :
6285 "subqw #1,%0\;jcc %l1";
6287 "subq%.w #1,%0\;cmp%.w #-1,%0\;jbne %l1" :
6288 "subqw #1,%0\;cmpw #-1,%0\;jne %l1";
6294 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6296 (label_ref (match_operand 1 "" ""))
6299 (plus:SI (match_dup 0)
6304 if (DATA_REG_P (operands[0]))
6306 "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jbcc %l1" :
6307 "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
6308 if (GET_CODE (operands[0]) == MEM)
6310 "subq%.l #1,%0\;jbcc %l1" :
6311 "subq%.l #1,%0\;jcc %l1";
6313 "subq.l #1,%0\;cmp.l #-1,%0\;jbne %l1" :
6314 "subql #1,%0\;cmpl #-1,%0\;jne %l1";
6317 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6322 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6325 (label_ref (match_operand 1 "" ""))
6328 (plus:HI (match_dup 0)
6330 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6333 if (DATA_REG_P (operands[0]))
6334 return "dbra %0,%l1";
6335 if (GET_CODE (operands[0]) == MEM)
6337 "subq%.w #1,%0\;jbcc %l1" :
6338 "subq%.w #1,%0\;jcc %l1";
6340 "subq.w #1,%0\;cmp.w #-1,%0\;jbne %l1" :
6341 "subqw #1,%0\;cmpw #-1,%0\;jne %l1";
6344 (define_expand "decrement_and_branch_until_zero"
6345 [(parallel [(set (pc)
6347 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6350 (label_ref (match_operand 1 "" ""))
6353 (plus:SI (match_dup 0)
6361 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6364 (label_ref (match_operand 1 "" ""))
6367 (plus:SI (match_dup 0)
6369 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6372 if (DATA_REG_P (operands[0]))
6374 "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jbcc %l1" :
6375 "dbra %0,%l1\;clr%.w %0\;subql #1,%0\;jcc %l1";
6376 if (GET_CODE (operands[0]) == MEM)
6378 "subq%.l #1,%0\;jbcc %l1" :
6379 "subql #1,%0\;jcc %l1";
6381 "subq.l #1,%0\;cmp.l #-1,%0\;jbne %l1" :
6382 "subql #1,%0\;cmpl #-1,%0\;jne %l1";
6386 ;; For PIC calls, in order to be able to support
6387 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6388 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6390 ;; PIC calls are handled by loading the address of the function into a
6391 ;; register (via movsi), then emitting a register indirect call using
6392 ;; the "jsr" function call syntax.
6394 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6395 ;; operand to the jbsr statement to indicate that this call should
6396 ;; go through the PLT (why? because this is the way that Sun does it).
6398 ;; We have different patterns for PIC calls and non-PIC calls. The
6399 ;; different patterns are only used to choose the right syntax.
6401 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6402 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6403 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6404 ;; section at link time. However, all global objects reference are still
6405 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6406 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6407 ;; We need to have a way to differentiate these two different operands.
6409 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6410 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6411 ;; to be changed to recognize function calls symbol_ref operand as a valid
6412 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6413 ;; avoid the compiler to load this symbol_ref operand into a register.
6414 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6415 ;; since the value is a PC relative offset, not a real address.
6417 ;; All global objects are treated in the similar way as in SUN3. The only
6418 ;; difference is: on m68k svr4, the reference of such global object needs
6419 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6420 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6423 ;; Call subroutine with no return value.
6424 (define_expand "call"
6425 [(call (match_operand:QI 0 "memory_operand" "")
6426 (match_operand:SI 1 "general_operand" ""))]
6427 ;; Operand 1 not really used on the m68000.
6431 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6432 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6435 ;; This is a normal call sequence.
6437 [(call (match_operand:QI 0 "memory_operand" "o")
6438 (match_operand:SI 1 "general_operand" "g"))]
6439 ;; Operand 1 not really used on the m68000.
6443 #if MOTOROLA && !defined (USE_GAS)
6450 ;; This is a PIC call sequence.
6452 [(call (match_operand:QI 0 "memory_operand" "o")
6453 (match_operand:SI 1 "general_operand" "g"))]
6454 ;; Operand 1 not really used on the m68000.
6458 m68k_output_pic_call(operands[0]);
6462 ;; Call subroutine, returning value in operand 0
6463 ;; (which must be a hard register).
6464 ;; See comments before "call" regarding PIC calls.
6465 (define_expand "call_value"
6466 [(set (match_operand 0 "" "")
6467 (call (match_operand:QI 1 "memory_operand" "")
6468 (match_operand:SI 2 "general_operand" "")))]
6469 ;; Operand 2 not really used on the m68000.
6472 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6473 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6476 ;; This is a normal call_value
6478 [(set (match_operand 0 "" "=rf")
6479 (call (match_operand:QI 1 "memory_operand" "o")
6480 (match_operand:SI 2 "general_operand" "g")))]
6481 ;; Operand 2 not really used on the m68000.
6484 #if MOTOROLA && !defined (USE_GAS)
6491 ;; This is a PIC call_value
6493 [(set (match_operand 0 "" "=rf")
6494 (call (match_operand:QI 1 "memory_operand" "o")
6495 (match_operand:SI 2 "general_operand" "g")))]
6496 ;; Operand 2 not really used on the m68000.
6499 m68k_output_pic_call(operands[1]);
6503 ;; Call subroutine returning any type.
6505 (define_expand "untyped_call"
6506 [(parallel [(call (match_operand 0 "" "")
6508 (match_operand 1 "" "")
6509 (match_operand 2 "" "")])]
6510 "NEEDS_UNTYPED_CALL"
6514 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6516 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6518 rtx set = XVECEXP (operands[2], 0, i);
6519 emit_move_insn (SET_DEST (set), SET_SRC (set));
6522 /* The optimizer does not know that the call sets the function value
6523 registers we stored in the result block. We avoid problems by
6524 claiming that all hard registers are used and clobbered at this
6526 emit_insn (gen_blockage ());
6531 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6532 ;; all of memory. This blocks insns from being moved across this point.
6534 (define_insn "blockage"
6535 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6544 ;; Used for frameless functions which save no regs and allocate no locals.
6545 (define_insn "return"
6549 if (current_function_pops_args == 0)
6551 operands[0] = GEN_INT (current_function_pops_args);
6555 (define_insn "indirect_jump"
6556 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6560 ;; This should not be used unless the add/sub insns can't be.
6563 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
6564 (match_operand:QI 1 "address_operand" "p"))]
6567 /* Recognize an insn that refers to a table of offsets. Such an insn will
6568 need to refer to a label on the insn. So output one. Use the
6569 label-number of the table of offsets to generate this label. This code,
6570 and similar code above, assumes that there will be at most one reference
6572 if (GET_CODE (operands[1]) == PLUS
6573 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6574 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6576 rtx labelref = XEXP (operands[1], 1);
6578 asm_fprintf (asm_out_file, "\\t.set %LLI%d,.+2\\n",
6579 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6581 (*targetm.asm_out.internal_label) (asm_out_file, "LI",
6582 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6584 return "lea %a1,%0";
6587 ;; This is the first machine-dependent peephole optimization.
6588 ;; It is useful when a floating value is returned from a function call
6589 ;; and then is moved into an FP register.
6590 ;; But it is mainly intended to test the support for these optimizations.
6593 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
6594 (set (match_operand:DF 0 "register_operand" "=f")
6595 (match_operand:DF 1 "register_operand" "ad"))]
6596 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6599 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6600 output_asm_insn ("move%.l %1,%@", xoperands);
6601 output_asm_insn ("move%.l %1,%-", operands);
6602 return "fmove%.d %+,%0";
6605 ;; Optimize a stack-adjust followed by a push of an argument.
6606 ;; This is said to happen frequently with -msoft-float
6607 ;; when there are consecutive library calls.
6610 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
6611 (match_operand:SI 0 "const_int_operand" "n")))
6612 (set (match_operand:SF 1 "push_operand" "=m")
6613 (match_operand:SF 2 "general_operand" "rmfF"))]
6614 "INTVAL (operands[0]) >= 4
6615 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6617 if (INTVAL (operands[0]) > 4)
6620 xoperands[0] = stack_pointer_rtx;
6621 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
6622 if (INTVAL (xoperands[1]) <= 8)
6624 if (!TARGET_COLDFIRE)
6625 output_asm_insn ("addq%.w %1,%0", xoperands);
6627 output_asm_insn ("addq%.l %1,%0", xoperands);
6629 else if (TUNE_CPU32 && INTVAL (xoperands[1]) <= 16)
6631 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
6632 output_asm_insn ("addq%.w #8,%0\;addq%.w %1,%0", xoperands);
6634 else if (INTVAL (xoperands[1]) <= 0x7FFF)
6637 output_asm_insn ("add%.w %1,%0", xoperands);
6639 output_asm_insn ("lea (%c1,%0),%0", xoperands);
6641 output_asm_insn ("lea %0@(%c1),%0", xoperands);
6644 output_asm_insn ("add%.l %1,%0", xoperands);
6646 if (FP_REG_P (operands[2]))
6647 return "fmove%.s %2,%@";
6648 return "move%.l %2,%@";
6651 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6654 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
6655 (match_operand:SI 0 "const_int_operand" "n")))
6656 (set (match_operand:SI 1 "push_operand" "=m")
6657 (match_operand:SI 2 "general_operand" "g"))]
6658 "INTVAL (operands[0]) >= 4
6659 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6661 if (INTVAL (operands[0]) > 4)
6664 xoperands[0] = stack_pointer_rtx;
6665 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
6666 if (INTVAL (xoperands[1]) <= 8)
6668 if (!TARGET_COLDFIRE)
6669 output_asm_insn ("addq%.w %1,%0", xoperands);
6671 output_asm_insn ("addq%.l %1,%0", xoperands);
6673 else if (TUNE_CPU32 && INTVAL (xoperands[1]) <= 16)
6675 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
6676 output_asm_insn ("addq%.w #8,%0\;addq%.w %1,%0", xoperands);
6678 else if (INTVAL (xoperands[1]) <= 0x7FFF)
6681 output_asm_insn ("add%.w %1,%0", xoperands);
6683 output_asm_insn ("lea (%c1,%0),%0", xoperands);
6685 output_asm_insn ("lea %0@(%c1),%0", xoperands);
6688 output_asm_insn ("add%.l %1,%0", xoperands);
6690 if (operands[2] == const0_rtx)
6692 return "move%.l %2,%@";
6695 ;; Speed up pushing a single byte but leaving four bytes of space.
6698 [(set (mem:QI (pre_dec:SI (reg:SI SP_REG)))
6699 (match_operand:QI 1 "general_operand" "dami"))
6700 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (const_int 2)))]
6701 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6705 if (GET_CODE (operands[1]) == REG)
6706 return "move%.l %1,%-";
6708 xoperands[1] = operands[1];
6710 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
6711 xoperands[3] = stack_pointer_rtx;
6712 if (!TARGET_COLDFIRE)
6713 output_asm_insn ("subq%.w #4,%3\;move%.b %1,%2", xoperands);
6715 output_asm_insn ("subq%.l #4,%3\;move%.b %1,%2", xoperands);
6720 [(set (match_operand:SI 0 "register_operand" "=d")
6722 (set (strict_low_part (subreg:HI (match_dup 0) 2))
6723 (match_operand:HI 1 "general_operand" "rmn"))]
6724 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6726 if (GET_CODE (operands[1]) == CONST_INT)
6728 if (operands[1] == const0_rtx
6729 && (DATA_REG_P (operands[0])
6730 || GET_CODE (operands[0]) == MEM)
6731 /* clr insns on 68000 read before writing. */
6732 && ((TARGET_68010 || TARGET_COLDFIRE)
6733 || !(GET_CODE (operands[0]) == MEM
6734 && MEM_VOLATILE_P (operands[0]))))
6737 return "move%.w %1,%0";
6745 ;; jCC label ; abnormal loop termination
6746 ;; dbra dN, loop ; normal loop termination
6754 ;; Which moves the jCC condition outside the inner loop for free.
6758 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6759 [(cc0) (const_int 0)])
6760 (label_ref (match_operand 2 "" ""))
6765 (ne (match_operand:HI 0 "register_operand" "")
6767 (label_ref (match_operand 1 "" ""))
6770 (plus:HI (match_dup 0)
6772 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6775 output_dbcc_and_branch (operands);
6780 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6781 [(cc0) (const_int 0)])
6782 (label_ref (match_operand 2 "" ""))
6787 (ne (match_operand:SI 0 "register_operand" "")
6789 (label_ref (match_operand 1 "" ""))
6792 (plus:SI (match_dup 0)
6794 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6797 output_dbcc_and_branch (operands);
6802 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6803 [(cc0) (const_int 0)])
6804 (label_ref (match_operand 2 "" ""))
6809 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
6812 (label_ref (match_operand 1 "" ""))
6815 (plus:HI (match_dup 0)
6817 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6820 output_dbcc_and_branch (operands);
6825 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6826 [(cc0) (const_int 0)])
6827 (label_ref (match_operand 2 "" ""))
6832 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
6835 (label_ref (match_operand 1 "" ""))
6838 (plus:SI (match_dup 0)
6840 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6843 output_dbcc_and_branch (operands);
6848 (define_insn "extendsfxf2"
6849 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
6850 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
6853 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6855 if (REGNO (operands[0]) == REGNO (operands[1]))
6857 /* Extending float to double in an fp-reg is a no-op.
6858 NOTICE_UPDATE_CC has already assumed that the
6859 cc will be set. So cancel what it did. */
6860 cc_status = cc_prev_status;
6863 return "f%$move%.x %1,%0";
6865 if (FP_REG_P (operands[0]))
6867 if (FP_REG_P (operands[1]))
6868 return "f%$move%.x %1,%0";
6869 else if (ADDRESS_REG_P (operands[1]))
6870 return "move%.l %1,%-\;f%$move%.s %+,%0";
6871 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
6872 return output_move_const_single (operands);
6873 return "f%$move%.s %f1,%0";
6875 return "fmove%.x %f1,%0";
6879 (define_insn "extenddfxf2"
6880 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
6882 (match_operand:DF 1 "general_operand" "f,rmE")))]
6885 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6887 if (REGNO (operands[0]) == REGNO (operands[1]))
6889 /* Extending float to double in an fp-reg is a no-op.
6890 NOTICE_UPDATE_CC has already assumed that the
6891 cc will be set. So cancel what it did. */
6892 cc_status = cc_prev_status;
6895 return "fmove%.x %1,%0";
6897 if (FP_REG_P (operands[0]))
6899 if (REG_P (operands[1]))
6902 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6903 output_asm_insn ("move%.l %1,%-", xoperands);
6904 output_asm_insn ("move%.l %1,%-", operands);
6905 return "f%&move%.d %+,%0";
6907 if (GET_CODE (operands[1]) == CONST_DOUBLE)
6908 return output_move_const_double (operands);
6909 return "f%&move%.d %f1,%0";
6911 return "fmove%.x %f1,%0";
6914 (define_insn "truncxfdf2"
6915 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
6917 (match_operand:XF 1 "general_operand" "f,f")))]
6920 if (REG_P (operands[0]))
6922 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
6923 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6924 return "move%.l %+,%0";
6926 return "fmove%.d %f1,%0";
6929 (define_insn "truncxfsf2"
6930 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
6932 (match_operand:XF 1 "general_operand" "f")))]
6936 (define_insn "sin<mode>2"
6937 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
6939 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_SIN))]
6940 "TARGET_68881 && flag_unsafe_math_optimizations"
6942 if (FP_REG_P (operands[1]))
6943 return "fsin%.x %1,%0";
6945 return "fsin%.<FP:prec> %1,%0";
6948 (define_insn "cos<mode>2"
6949 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
6951 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_COS))]
6952 "TARGET_68881 && flag_unsafe_math_optimizations"
6954 if (FP_REG_P (operands[1]))
6955 return "fcos%.x %1,%0";
6957 return "fcos%.<FP:prec> %1,%0";
6961 [(trap_if (const_int -1) (const_int 7))]
6965 (define_insn "conditional_trap"
6966 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
6967 [(cc0) (const_int 0)])
6968 (match_operand:SI 1 "const_int_operand" "I"))]
6969 "TARGET_68020 && ! flags_in_68881 ()"
6971 switch (GET_CODE (operands[0]))
6973 case EQ: return "trapeq";
6974 case NE: return "trapne";
6975 case GT: return "trapgt";
6976 case GTU: return "traphi";
6977 case LT: return "traplt";
6978 case LTU: return "trapcs";
6979 case GE: return "trapge";
6980 case GEU: return "trapcc";
6981 case LE: return "traple";
6982 case LEU: return "trapls";
6983 default: gcc_unreachable ();